998 files changed, 36308 insertions, 14056 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index db3c5414223e..87b63fde06d7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -165,12 +165,9 @@ config TRACE_IRQFLAGS_SUPPORT
        bool
        default y
-config RWSEM_GENERIC_SPINLOCK
-        bool
-        default y
 config RWSEM_XCHGADD_ALGORITHM
        bool
+        default y
 config ARCH_HAS_ILOG2_U32
        bool
@@ -314,6 +311,7 @@ config ARCH_MULTIPLATFORM
        select CLKSRC_OF
        select COMMON_CLK
        select GENERIC_CLOCKEVENTS
+        select MIGHT_HAVE_PCI
        select MULTI_IRQ_HANDLER
        select SPARSE_IRQ
        select USE_OF
@@ -376,7 +374,6 @@ config ARCH_AT91
        select ARCH_REQUIRE_GPIOLIB
        select CLKDEV_LOOKUP
        select IRQ_DOMAIN
-        select NEED_MACH_GPIO_H
        select NEED_MACH_IO_H if PCCARD
        select PINCTRL
        select PINCTRL_AT91 if USE_OF
@@ -480,6 +477,7 @@ config ARCH_IOP13XX
        select PCI
        select PLAT_IOP
        select VMSPLIT_1G
+        select SPARSE_IRQ
        help
          Support for Intel's IOP13XX (XScale) family of processors.
@@ -755,7 +753,7 @@ config ARCH_S3C64XX
        select ATAGS
        select CLKDEV_LOOKUP
        select CLKSRC_SAMSUNG_PWM
-        select COMMON_CLK
+        select COMMON_CLK_SAMSUNG
        select CPU_V6K
        select GENERIC_CLOCKEVENTS
        select GPIO_SAMSUNG
@@ -829,25 +827,6 @@ config ARCH_S5PV210
        help
          Samsung S5PV210/S5PC110 series based systems
-config ARCH_EXYNOS
-        bool "Samsung EXYNOS"
-        select ARCH_HAS_CPUFREQ
-        select ARCH_HAS_HOLES_MEMORYMODEL
-        select ARCH_REQUIRE_GPIOLIB
-        select ARCH_SPARSEMEM_ENABLE
-        select ARM_GIC
-        select COMMON_CLK
-        select CPU_V7
-        select GENERIC_CLOCKEVENTS
-        select HAVE_S3C2410_I2C if I2C
-        select HAVE_S3C2410_WATCHDOG if WATCHDOG
-        select HAVE_S3C_RTC if RTC_CLASS
-        select NEED_MACH_MEMORY_H
-        select SPARSE_IRQ
-        select USE_OF
-        help
-          Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
 config ARCH_DAVINCI
        bool "TI DaVinci"
        select ARCH_HAS_HOLES_MEMORYMODEL
@@ -951,6 +930,8 @@ source "arch/arm/mach-mvebu/Kconfig"
 source "arch/arm/mach-at91/Kconfig"
+source "arch/arm/mach-axxia/Kconfig"
 source "arch/arm/mach-bcm/Kconfig"
 source "arch/arm/mach-berlin/Kconfig"
@@ -1105,11 +1086,6 @@ source "arch/arm/firmware/Kconfig"
 source arch/arm/mm/Kconfig
-config ARM_NR_BANKS
-        int
-        default 16 if ARCH_EP93XX
-        default 8
 config IWMMXT
        bool "Enable iWMMXt support"
        depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
@@ -1230,19 +1206,6 @@ config ARM_ERRATA_742231
          register of the Cortex-A9 which reduces the linefill issuing
          capabilities of the processor.
-config PL310_ERRATA_588369
-        bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
-        depends on CACHE_L2X0
-        help
-           The PL310 L2 cache controller implements three types of Clean &
-           Invalidate maintenance operations: by Physical Address
-           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
-           They are architecturally defined to behave as the execution of a
-           clean operation followed immediately by an invalidate operation,
-           both performing to the same memory location. This functionality
-           is not correctly implemented in PL310 as clean lines are not
-           invalidated as a result of these operations.
 config ARM_ERRATA_643719
        bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
        depends on CPU_V7 && SMP
@@ -1265,17 +1228,6 @@ config ARM_ERRATA_720789
          tables. The workaround changes the TLB flushing routines to invalidate
          entries regardless of the ASID.
-config PL310_ERRATA_727915
-        bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
-        depends on CACHE_L2X0
-        help
-          PL310 implements the Clean & Invalidate by Way L2 cache maintenance
-          operation (offset 0x7FC). This operation runs in background so that
-          PL310 can handle normal accesses while it is in progress. Under very
-          rare circumstances, due to this erratum, write data can be lost when
-          PL310 treats a cacheable write transaction during a Clean &
-          Invalidate by Way operation.
 config ARM_ERRATA_743622
        bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
        depends on CPU_V7
@@ -1301,21 +1253,6 @@ config ARM_ERRATA_751472
          operation is received by a CPU before the ICIALLUIS has completed,
          potentially leading to corrupted entries in the cache or TLB.
-config PL310_ERRATA_753970
-        bool "PL310 errata: cache sync operation may be faulty"
-        depends on CACHE_PL310
-        help
-          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
-          Under some condition the effect of cache sync operation on
-          the store buffer still remains when the operation completes.
-          This means that the store buffer is always asked to drain and
-          this prevents it from merging any further writes. The workaround
-          is to replace the normal offset of cache sync operation (0x730)
-          by another offset targeting an unmapped PL310 register 0x740.
-          This has the same effect as the cache sync operation: store buffer
-          drain and waiting for all buffers empty.
 config ARM_ERRATA_754322
        bool "ARM errata: possible faulty MMU translations following an ASID switch"
        depends on CPU_V7
@@ -1364,18 +1301,6 @@ config ARM_ERRATA_764369
          relevant cache maintenance functions and sets a specific bit
          in the diagnostic control register of the SCU.
-config PL310_ERRATA_769419
-        bool "PL310 errata: no automatic Store Buffer drain"
-        depends on CACHE_L2X0
-        help
-          On revisions of the PL310 prior to r3p2, the Store Buffer does
-          not automatically drain. This can cause normal, non-cacheable
-          writes to be retained when the memory system is idle, leading
-          to suboptimal I/O performance for drivers using coherent DMA.
-          This option adds a write barrier to the cpu_idle loop so that,
-          on systems with an outer cache, the store buffer is drained
-          explicitly.
 config ARM_ERRATA_775420
       bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
       depends on CPU_V7
@@ -1646,9 +1571,9 @@ config ARCH_NR_GPIO
        int
        default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
        default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
+        default 416 if ARCH_SUNXI
        default 392 if ARCH_U8500
        default 352 if ARCH_VT8500
-        default 288 if ARCH_SUNXI
        default 264 if MACH_H4700
        default 0
        help
@@ -2295,6 +2220,11 @@ config ARCH_SUSPEND_POSSIBLE
 config ARM_CPU_SUSPEND
        def_bool PM_SLEEP
+config ARCH_HIBERNATION_POSSIBLE
+        bool
+        depends on MMU
+        default y if ARCH_SUSPEND_POSSIBLE
 endmenu
 source "net/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index eab8ecbe69c1..8f90595069a1 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -317,6 +317,13 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on i.MX6SL.
+        config DEBUG_IMX6SX_UART
+                bool "i.MX6SX Debug UART"
+                depends on SOC_IMX6SX
+                help
+                  Say Y here if you want kernel low-level debugging support
+                  on i.MX6SX.
        config DEBUG_KEYSTONE_UART0
                bool "Kernel low-level debugging on KEYSTONE2 using UART0"
                depends on ARCH_KEYSTONE
@@ -349,56 +356,40 @@ choice
                  Say Y here if you want kernel low-level debugging support
                  on MMP UART3.
-        config DEBUG_MSM_UART1
+        config DEBUG_MSM_UART
-                bool "Kernel low-level debugging messages via MSM UART1"
+                bool "Kernel low-level debugging messages via MSM UART"
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                depends on ARCH_MSM
-                select DEBUG_MSM_UART
                help
                  Say Y here if you want the debug print routines to direct
-                  their output to the first serial port on MSM devices.
+                  their output to the serial port on MSM devices.
-        config DEBUG_MSM_UART2
+                  ARCH                DEBUG_UART_PHYS   DEBUG_UART_BASE   #
-                bool "Kernel low-level debugging messages via MSM UART2"
+                  MSM7X00A, QSD8X50   0xa9a00000        0xe1000000        UART1
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  MSM7X00A, QSD8X50   0xa9b00000        0xe1000000        UART2
-                select DEBUG_MSM_UART
+                  MSM7X00A, QSD8X50   0xa9c00000        0xe1000000        UART3
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the second serial port on MSM devices.
-        config DEBUG_MSM_UART3
+                  MSM7X30             0xaca00000        0xe1000000        UART1
-                bool "Kernel low-level debugging messages via MSM UART3"
+                  MSM7X30             0xacb00000        0xe1000000        UART2
-                depends on ARCH_MSM7X00A || ARCH_MSM7X30 || ARCH_QSD8X50
+                  MSM7X30             0xacc00000        0xe1000000        UART3
-                select DEBUG_MSM_UART
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the third serial port on MSM devices.
-        config DEBUG_MSM8660_UART
+                  Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
-                bool "Kernel low-level debugging messages via MSM 8660 UART"
+                  options based on your needs.
-                depends on ARCH_MSM8X60
-                select MSM_HAS_DEBUG_UART_HS
-                select DEBUG_MSM_UART
-                help
-                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8660 devices.
-        config DEBUG_MSM8960_UART
+        config DEBUG_QCOM_UARTDM
-                bool "Kernel low-level debugging messages via MSM 8960 UART"
+                bool "Kernel low-level debugging messages via QCOM UARTDM"
-                depends on ARCH_MSM8960
+                depends on ARCH_QCOM
-                select MSM_HAS_DEBUG_UART_HS
-                select DEBUG_MSM_UART
                help
                  Say Y here if you want the debug print routines to direct
-                  their output to the serial port on MSM 8960 devices.
+                  their output to the serial port on Qualcomm devices.
-        config DEBUG_MSM8974_UART
+                  ARCH      DEBUG_UART_PHYS   DEBUG_UART_BASE
-                bool "Kernel low-level debugging messages via MSM 8974 UART"
+                  APQ8084   0xf995e000        0xfa75e000
-                depends on ARCH_MSM8974
+                  MSM8X60   0x19c40000        0xf0040000
-                select MSM_HAS_DEBUG_UART_HS
+                  MSM8960   0x16440000        0xf0040000
-                select DEBUG_MSM_UART
+                  MSM8974   0xf991e000        0xfa71e000
-                help
-                  Say Y here if you want the debug print routines to direct
+                  Please adjust DEBUG_UART_PHYS and DEBUG_UART_BASE configuration
-                  their output to the serial port on MSM 8974 devices.
+                  options based on your needs.
        config DEBUG_MVEBU_UART
                bool "Kernel low-level debugging messages via MVEBU UART (old bootloaders)"
@@ -625,6 +616,7 @@ choice
        config DEBUG_S3C_UART0
                depends on PLAT_SAMSUNG
                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                bool "Use S3C UART 0 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -637,6 +629,7 @@ choice
        config DEBUG_S3C_UART1
                depends on PLAT_SAMSUNG
                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                bool "Use S3C UART 1 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -649,6 +642,7 @@ choice
        config DEBUG_S3C_UART2
                depends on PLAT_SAMSUNG
                select DEBUG_EXYNOS_UART if ARCH_EXYNOS
+                select DEBUG_S3C24XX_UART if ARCH_S3C24XX
                bool "Use S3C UART 2 for low-level debug"
                help
                  Say Y here if you want the debug print routines to direct
@@ -670,6 +664,33 @@ choice
                  The uncompressor code port configuration is now handled
                  by CONFIG_S3C_LOWLEVEL_UART_PORT.
+        config DEBUG_S3C2410_UART0
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 0 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 0. The port must have been initialised
+                  by the boot-loader before use.
+        config DEBUG_S3C2410_UART1
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 1 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 1. The port must have been initialised
+                  by the boot-loader before use.
+        config DEBUG_S3C2410_UART2
+                depends on ARCH_S3C24XX
+                select DEBUG_S3C2410_UART
+                bool "Use S3C2410/S3C2412 UART 2 for low-level debug"
+                help
+                  Say Y here if you want the debug print routines to direct
+                  their output to UART 2. The port must have been initialised
+                  by the boot-loader before use.
        config DEBUG_SOCFPGA_UART
                depends on ARCH_SOCFPGA
                bool "Use SOCFPGA UART for low-level debug"
@@ -921,6 +942,13 @@ endchoice
 config DEBUG_EXYNOS_UART
        bool
+config DEBUG_S3C2410_UART
+        bool
+        select DEBUG_S3C24XX_UART
+config DEBUG_S3C24XX_UART
+        bool
 config DEBUG_OMAP2PLUS_UART
        bool
        depends on ARCH_OMAP2PLUS
@@ -935,13 +963,23 @@ config DEBUG_IMX_UART_PORT
                                                DEBUG_IMX51_UART || \
                                                DEBUG_IMX53_UART || \
                                                DEBUG_IMX6Q_UART || \
-                                                DEBUG_IMX6SL_UART
+                                                DEBUG_IMX6SL_UART || \
+                                                DEBUG_IMX6SX_UART
        default 1
        depends on ARCH_MXC
        help
          Choose UART port on which kernel low-level debug messages
          should be output.
+config DEBUG_VF_UART_PORT
+        int "Vybrid Debug UART Port Selection" if DEBUG_VF_UART
+        default 1
+        range 0 3
+        depends on SOC_VF610
+        help
+          Choose UART port on which kernel low-level debug messages
+          should be output.
 config DEBUG_TEGRA_UART
        bool
        depends on ARCH_TEGRA
@@ -950,10 +988,6 @@ config DEBUG_STI_UART
        bool
        depends on ARCH_STI
-config DEBUG_MSM_UART
-        bool
-        depends on ARCH_MSM || ARCH_QCOM
 config DEBUG_LL_INCLUDE
        string
        default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250
@@ -970,9 +1004,11 @@ config DEBUG_LL_INCLUDE
                                 DEBUG_IMX51_UART || \
                                 DEBUG_IMX53_UART ||\
                                 DEBUG_IMX6Q_UART || \
-                                 DEBUG_IMX6SL_UART
+                                 DEBUG_IMX6SL_UART || \
-        default "debug/msm.S" if DEBUG_MSM_UART
+                                 DEBUG_IMX6SX_UART
+        default "debug/msm.S" if DEBUG_MSM_UART || DEBUG_QCOM_UARTDM
        default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
+        default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART
        default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
        default "debug/sti.S" if DEBUG_STI_UART
        default "debug/tegra.S" if DEBUG_TEGRA_UART
@@ -1029,12 +1065,19 @@ config DEBUG_UART_PHYS
        default 0x40090000 if ARCH_LPC32XX
        default 0x40100000 if DEBUG_PXA_UART1
        default 0x42000000 if ARCH_GEMINI
+        default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
+                                DEBUG_S3C2410_UART0)
+        default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
+                                DEBUG_S3C2410_UART1)
+        default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
+                                DEBUG_S3C2410_UART2)
        default 0x7c0003f8 if FOOTBRIDGE
        default 0x80070000 if DEBUG_IMX23_UART
        default 0x80074000 if DEBUG_IMX28_UART
        default 0x80230000 if DEBUG_PICOXCELL_UART
        default 0x808c0000 if ARCH_EP93XX
        default 0x90020000 if DEBUG_NSPIRE_CLASSIC_UART || DEBUG_NSPIRE_CX_UART
+        default 0xa9a00000 if DEBUG_MSM_UART
        default 0xb0090000 if DEBUG_VEXPRESS_UART0_CRX
        default 0xc0013000 if DEBUG_U300_UART
        default 0xc8000000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN
@@ -1050,6 +1093,7 @@ config DEBUG_UART_PHYS
                                ARCH_ORION5X
        default 0xf7fc9000 if DEBUG_BERLIN_UART
        default 0xf8b00000 if DEBUG_HI3716_UART
+        default 0xf991e000 if DEBUG_QCOM_UARTDM
        default 0xfcb00000 if DEBUG_HI3620_UART
        default 0xfe800000 if ARCH_IOP32X
        default 0xffc02000 if DEBUG_SOCFPGA_UART
@@ -1058,11 +1102,13 @@ config DEBUG_UART_PHYS
        default 0xfffff700 if ARCH_IOP33X
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
                DEBUG_LL_UART_EFM32 || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || \
+                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
 config DEBUG_UART_VIRT
        hex "Virtual base address of debug UART"
        default 0xe0010fe0 if ARCH_RPC
+        default 0xe1000000 if DEBUG_MSM_UART
        default 0xf0000be0 if ARCH_EBSA110
        default 0xf0009000 if DEBUG_CNS3XXX
        default 0xf01fb000 if DEBUG_NOMADIK_UART
@@ -1075,9 +1121,16 @@ config DEBUG_UART_VIRT
        default 0xf2100000 if DEBUG_PXA_UART1
        default 0xf4090000 if ARCH_LPC32XX
        default 0xf4200000 if ARCH_GEMINI
+        default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \
+                                DEBUG_S3C2410_UART0)
+        default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \
+                                DEBUG_S3C2410_UART1)
+        default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \
+                                DEBUG_S3C2410_UART2)
        default 0xf7fc9000 if DEBUG_BERLIN_UART
        default 0xf8009000 if DEBUG_VEXPRESS_UART0_CA9
        default 0xf8090000 if DEBUG_VEXPRESS_UART0_RS1
+        default 0xfa71e000 if DEBUG_QCOM_UARTDM
        default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
        default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
        default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
@@ -1116,7 +1169,8 @@ config DEBUG_UART_VIRT
        default 0xff003000 if DEBUG_U300_UART
        default DEBUG_UART_PHYS if !MMU
        depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \
-                DEBUG_UART_8250 || DEBUG_UART_PL01X
+                DEBUG_UART_8250 || DEBUG_UART_PL01X || \
+                DEBUG_MSM_UART || DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART
 config DEBUG_UART_8250_SHIFT
        int "Register offset shift for the 8250 debug UART"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 41c1931f0155..6721fab13734 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -138,10 +138,12 @@ endif
 textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000
 textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
+textofs-$(CONFIG_ARCH_AXXIA) := 0x00308000
 # Machine directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AT91)             += at91
+machine-$(CONFIG_ARCH_AXXIA)            += axxia
 machine-$(CONFIG_ARCH_BCM)              += bcm
 machine-$(CONFIG_ARCH_BERLIN)           += berlin
 machine-$(CONFIG_ARCH_CLPS711X)         += clps711x
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
index d1153c8a765a..9448aa0c6686 100644
--- a/arch/arm/boot/compressed/atags_to_fdt.c
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -7,6 +7,8 @@
 #define do_extend_cmdline 0
 #endif
+#define NR_BANKS 16
 static int node_offset(void *fdt, const char *node_path)
 {
        int offset = fdt_path_offset(fdt, node_path);
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 066b03480b63..3a8b32df6b31 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -60,11 +60,6 @@
                add     \rb, \rb, #0x00010000   @ Ser1
 #endif
                .endm
-#elif defined(CONFIG_ARCH_S3C24XX)
-                .macro loadsp, rb, tmp
-                mov     \rb, #0x50000000
-                add     \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
-                .endm
 #else
                .macro  loadsp, rb, tmp
                addruart \rb, \tmp
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 377b7c364033..5986ff63b901 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -50,13 +50,15 @@ dtb-$(CONFIG_ARCH_AT91)	+= sama5d35ek.dtb
 dtb-$(CONFIG_ARCH_AT91) += sama5d36ek.dtb
 dtb-$(CONFIG_ARCH_ATLAS6) += atlas6-evb.dtb
+dtb-$(CONFIG_ARCH_AXXIA) += axm5516-amarillo.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
 dtb-$(CONFIG_ARCH_BCM_5301X) += bcm4708-netgear-r6250.dtb
 dtb-$(CONFIG_ARCH_BCM_MOBILE) += bcm28155-ap.dtb \
        bcm21664-garnet.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += \
        berlin2-sony-nsz-gs7.dtb        \
-        berlin2cd-google-chromecast.dtb
+        berlin2cd-google-chromecast.dtb \
+        berlin2q-marvell-dmp.dtb
 dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
        da850-evm.dtb
 dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
@@ -72,10 +74,14 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
        exynos5250-arndale.dtb \
        exynos5250-smdk5250.dtb \
        exynos5250-snow.dtb \
+        exynos5260-xyref5260.dtb \
+        exynos5410-smdk5410.dtb \
        exynos5420-arndale-octa.dtb \
+        exynos5420-peach-pit.dtb \
        exynos5420-smdk5420.dtb \
        exynos5440-sd5v1.dtb \
-        exynos5440-ssdk5440.dtb
+        exynos5440-ssdk5440.dtb \
+        exynos5800-peach-pi.dtb
 dtb-$(CONFIG_ARCH_HI3xxx) += hi3620-hi4511.dtb
 dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
        ecx-2000.dtb
@@ -127,6 +133,9 @@ kirkwood := \
        kirkwood-nsa310a.dtb \
        kirkwood-openblocks_a6.dtb \
        kirkwood-openblocks_a7.dtb \
+        kirkwood-openrd-base.dtb \
+        kirkwood-openrd-client.dtb \
+        kirkwood-openrd-ultimate.dtb \
        kirkwood-rd88f6192.dtb \
        kirkwood-rd88f6281-a0.dtb \
        kirkwood-rd88f6281-a1.dtb \
@@ -157,10 +166,12 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx27-phytec-phycard-s-rdk.dtb \
        imx31-bug.dtb \
        imx35-eukrea-mbimxsd35-baseboard.dtb \
+        imx35-pdk.dtb \
        imx50-evk.dtb \
        imx51-apf51.dtb \
        imx51-apf51dev.dtb \
        imx51-babbage.dtb \
+        imx51-digi-connectcore-jsk.dtb \
        imx51-eukrea-mbimxsd51-baseboard.dtb \
        imx53-ard.dtb \
        imx53-m53evk.dtb \
@@ -179,6 +190,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6dl-gw54xx.dtb \
        imx6dl-hummingboard.dtb \
        imx6dl-nitrogen6x.dtb \
+        imx6dl-phytec-pbab01.dtb \
+        imx6dl-riotboard.dtb \
        imx6dl-sabreauto.dtb \
        imx6dl-sabrelite.dtb \
        imx6dl-sabresd.dtb \
@@ -203,6 +216,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
        imx6q-udoo.dtb \
        imx6q-wandboard.dtb \
        imx6sl-evk.dtb \
+        vf610-colibri.dtb \
        vf610-cosmic.dtb \
        vf610-twr.dtb
 dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@@ -230,76 +244,84 @@ dtb-$(CONFIG_ARCH_NOMADIK) += ste-nomadik-s8815.dtb
 dtb-$(CONFIG_ARCH_NSPIRE) += nspire-cx.dtb \
        nspire-tp.dtb \
        nspire-clp.dtb
-dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
+dtb-$(CONFIG_ARCH_OMAP2) += omap2420-h4.dtb \
-        omap2430-sdp.dtb \
        omap2420-n800.dtb \
        omap2420-n810.dtb \
        omap2420-n810-wimax.dtb \
+        omap2430-sdp.dtb
+dtb-$(CONFIG_ARCH_OMAP3) += am3517-craneboard.dtb \
+        am3517-evm.dtb \
+        am3517_mt_ventoux.dtb \
        omap3430-sdp.dtb \
        omap3-beagle.dtb \
+        omap3-beagle-xm.dtb \
+        omap3-beagle-xm-ab.dtb \
        omap3-cm-t3517.dtb \
-        omap3-sbc-t3517.dtb \
        omap3-cm-t3530.dtb \
-        omap3-sbc-t3530.dtb \
        omap3-cm-t3730.dtb \
-        omap3-sbc-t3730.dtb \
        omap3-devkit8000.dtb \
-        omap3-beagle-xm.dtb \
-        omap3-beagle-xm-ab.dtb \
        omap3-evm.dtb \
        omap3-evm-37xx.dtb \
+        omap3-gta04.dtb \
+        omap3-igep0020.dtb \
+        omap3-igep0030.dtb \
        omap3-ldp.dtb \
+        omap3-lilly-dbb056.dtb \
        omap3-n900.dtb \
        omap3-n9.dtb \
        omap3-n950.dtb \
        omap3-overo-alto35.dtb \
-        omap3-overo-storm-alto35.dtb \
        omap3-overo-chestnut43.dtb \
-        omap3-overo-storm-chestnut43.dtb \
        omap3-overo-gallop43.dtb \
-        omap3-overo-storm-gallop43.dtb \
        omap3-overo-palo43.dtb \
+        omap3-overo-storm-alto35.dtb \
+        omap3-overo-storm-chestnut43.dtb \
+        omap3-overo-storm-gallop43.dtb \
        omap3-overo-storm-palo43.dtb \
-        omap3-overo-summit.dtb \
        omap3-overo-storm-summit.dtb \
-        omap3-overo-tobi.dtb \
        omap3-overo-storm-tobi.dtb \
-        omap3-gta04.dtb \
+        omap3-overo-summit.dtb \
-        omap3-igep0020.dtb \
+        omap3-overo-tobi.dtb \
-        omap3-igep0030.dtb \
+        omap3-sbc-t3517.dtb \
-        omap3-lilly-dbb056.dtb \
+        omap3-sbc-t3530.dtb \
-        omap3-zoom3.dtb \
+        omap3-sbc-t3730.dtb \
-        omap4-duovero-parlor.dtb \
+        omap3-zoom3.dtb
+dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
+        am335x-bone.dtb \
+        am335x-boneblack.dtb \
+        am335x-evm.dtb \
+        am335x-evmsk.dtb \
+        am335x-nano.dtb
+dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
        omap4-panda.dtb \
        omap4-panda-a4.dtb \
        omap4-panda-es.dtb \
-        omap4-var-som.dtb \
        omap4-sdp.dtb \
        omap4-sdp-es23plus.dtb \
-        omap5-uevm.dtb \
+        omap4-var-dvk-om44.dtb \
-        am335x-evm.dtb \
+        omap4-var-stk-om44.dtb
-        am335x-evmsk.dtb \
+dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
-        am335x-bone.dtb \
+        am437x-gp-evm.dtb
-        am335x-boneblack.dtb \
+dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
-        am335x-nano.dtb \
+        omap5-sbc-t54.dtb \
-        am335x-base0033.dtb \
+        omap5-uevm.dtb
-        am3517-craneboard.dtb \
+dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
-        am3517-evm.dtb \
+        dra72-evm.dtb
-        am3517_mt_ventoux.dtb \
+dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-d2-network.dtb \
-        am43x-epos-evm.dtb \
+        orion5x-lacie-ethernet-disk-mini-v2.dtb \
-        am437x-gp-evm.dtb \
+        orion5x-maxtor-shared-storage-2.dtb \
-        dra7-evm.dtb
+        orion5x-rd88f5182-nas.dtb
-dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
 dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
-dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
+dtb-$(CONFIG_ARCH_QCOM) += \
-        qcom-msm8960-cdp.dtb \
+        qcom-apq8064-ifc6410.dtb \
-        qcom-apq8074-dragonboard.dtb
+        qcom-apq8074-dragonboard.dtb \
+        qcom-apq8084-mtp.dtb \
+        qcom-msm8660-surf.dtb \
+        qcom-msm8960-cdp.dtb
 dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
 dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
        s3c6410-smdk6410.dtb
-dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
+dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += r7s72100-genmai.dtb \
-        r7s72100-genmai.dtb \
-        r7s72100-genmai-reference.dtb \
        r8a7740-armadillo800eva.dtb \
        r8a7778-bockw.dtb \
        r8a7778-bockw-reference.dtb \
@@ -314,12 +336,14 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += emev2-kzm9d.dtb \
        r8a73a4-ape6evm-reference.dtb \
        sh7372-mackerel.dtb
 dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d.dtb \
-        r7s72100-genmai-reference.dtb \
+        r7s72100-genmai.dtb \
+        r8a7791-henninger.dtb \
        r8a7791-koelsch.dtb \
        r8a7790-lager.dtb
 dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_arria5_socdk.dtb \
        socfpga_cyclone5_socdk.dtb \
        socfpga_cyclone5_sockit.dtb \
+        socfpga_cyclone5_socrates.dtb \
        socfpga_vt.dtb
 dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
        spear1340-evb.dtb
@@ -328,24 +352,33 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
        spear320-evb.dtb \
        spear320-hmi.dtb
 dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
-dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
+dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
-        stih416-b2000.dtb \
+        stih415-b2000.dtb \
        stih415-b2020.dtb \
-        stih416-b2020.dtb
+        stih416-b2000.dtb \
-dtb-$(CONFIG_ARCH_SUNXI) += \
+        stih416-b2020.dtb \
+        stih416-b2020-revE.dtb
+dtb-$(CONFIG_MACH_SUN4I) += \
        sun4i-a10-a1000.dtb \
        sun4i-a10-cubieboard.dtb \
        sun4i-a10-mini-xplus.dtb \
        sun4i-a10-hackberry.dtb \
        sun4i-a10-inet97fv2.dtb \
        sun4i-a10-olinuxino-lime.dtb \
-        sun4i-a10-pcduino.dtb \
+        sun4i-a10-pcduino.dtb
+dtb-$(CONFIG_MACH_SUN5I) += \
        sun5i-a10s-olinuxino-micro.dtb \
+        sun5i-a10s-r7-tv-dongle.dtb \
        sun5i-a13-olinuxino.dtb \
-        sun5i-a13-olinuxino-micro.dtb \
+        sun5i-a13-olinuxino-micro.dtb
+dtb-$(CONFIG_MACH_SUN6I) += \
+        sun6i-a31-app4-evb1.dtb \
        sun6i-a31-colombus.dtb \
+        sun6i-a31-m9.dtb
+dtb-$(CONFIG_MACH_SUN7I) += \
        sun7i-a20-cubieboard2.dtb \
        sun7i-a20-cubietruck.dtb \
+        sun7i-a20-i12-tvbox.dtb \
        sun7i-a20-olinuxino-micro.dtb
 dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra20-iris-512.dtb \
@@ -360,7 +393,11 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
        tegra30-beaver.dtb \
        tegra30-cardhu-a02.dtb \
        tegra30-cardhu-a04.dtb \
+        tegra30-colibri-eval-v3.dtb \
        tegra114-dalmore.dtb \
+        tegra114-roth.dtb \
+        tegra114-tn7.dtb \
+        tegra124-jetson-tk1.dtb \
        tegra124-venice2.dtb
 dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
 dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2e7d932887b5..bde1777b62be 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -182,31 +182,31 @@
 &usb {
        status = "okay";
+};
-        control@44e10620 {
+&usb_ctrl_mod {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401300 {
+&usb0_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401b00 {
+&usb1_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401000 {
+&usb0 {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401800 {
+&usb1 {
-                status = "okay";
+        status = "okay";
-                dr_mode = "host";
+        dr_mode = "host";
-        };
+};
-        dma-controller@47402000  {
+&cppi41dma  {
-                status = "okay";
+        status = "okay";
-        };
 };
 &i2c0 {
@@ -280,13 +280,14 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
 };
 &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
 };
 &mmc1 {
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 6b71ad95a5cf..305975d3f531 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -26,7 +26,6 @@
        pinctrl-0 = <&emmc_pins>;
        bus-width = <8>;
        status = "okay";
-        ti,vcc-aux-disable-is-sleep;
 };
 &am33xx_pinmux {
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index 6028217ace0f..ecb267767cf5 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -268,34 +268,34 @@
        lcd_pins_s0: lcd_pins_s0 {
                pinctrl-single,pins = <
-                        0x20 0x01       /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
+                        0x20 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad8.lcd_data23 */
-                        0x24 0x01       /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
+                        0x24 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad9.lcd_data22 */
-                        0x28 0x01       /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
+                        0x28 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad10.lcd_data21 */
-                        0x2c 0x01       /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
+                        0x2c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad11.lcd_data20 */
-                        0x30 0x01       /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
+                        0x30 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad12.lcd_data19 */
-                        0x34 0x01       /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
+                        0x34 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad13.lcd_data18 */
-                        0x38 0x01       /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
+                        0x38 (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad14.lcd_data17 */
-                        0x3c 0x01       /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
+                        0x3c (PIN_OUTPUT | MUX_MODE1)           /* gpmc_ad15.lcd_data16 */
-                        0xa0 0x00       /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
+                        0xa0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data0.lcd_data0 */
-                        0xa4 0x00       /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
+                        0xa4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data1.lcd_data1 */
-                        0xa8 0x00       /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
+                        0xa8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data2.lcd_data2 */
-                        0xac 0x00       /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
+                        0xac (PIN_OUTPUT | MUX_MODE0)           /* lcd_data3.lcd_data3 */
-                        0xb0 0x00       /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
+                        0xb0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data4.lcd_data4 */
-                        0xb4 0x00       /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
+                        0xb4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data5.lcd_data5 */
-                        0xb8 0x00       /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
+                        0xb8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data6.lcd_data6 */
-                        0xbc 0x00       /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
+                        0xbc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data7.lcd_data7 */
-                        0xc0 0x00       /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
+                        0xc0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data8.lcd_data8 */
-                        0xc4 0x00       /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
+                        0xc4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data9.lcd_data9 */
-                        0xc8 0x00       /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
+                        0xc8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data10.lcd_data10 */
-                        0xcc 0x00       /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
+                        0xcc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data11.lcd_data11 */
-                        0xd0 0x00       /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
+                        0xd0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data12.lcd_data12 */
-                        0xd4 0x00       /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
+                        0xd4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data13.lcd_data13 */
-                        0xd8 0x00       /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
+                        0xd8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_data14.lcd_data14 */
-                        0xdc 0x00       /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
+                        0xdc (PIN_OUTPUT | MUX_MODE0)           /* lcd_data15.lcd_data15 */
-                        0xe0 0x00       /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
+                        0xe0 (PIN_OUTPUT | MUX_MODE0)           /* lcd_vsync.lcd_vsync */
-                        0xe4 0x00       /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
+                        0xe4 (PIN_OUTPUT | MUX_MODE0)           /* lcd_hsync.lcd_hsync */
-                        0xe8 0x00       /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
+                        0xe8 (PIN_OUTPUT | MUX_MODE0)           /* lcd_pclk.lcd_pclk */
-                        0xec 0x00       /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
+                        0xec (PIN_OUTPUT | MUX_MODE0)           /* lcd_ac_bias_en.lcd_ac_bias_en */
                >;
        };
@@ -330,31 +330,31 @@
 &usb {
        status = "okay";
+};
-        control@44e10620 {
+&usb_ctrl_mod {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401300 {
+&usb0_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401b00 {
+&usb1_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401000 {
+&usb0 {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401800 {
+&usb1 {
-                status = "okay";
+        status = "okay";
-                dr_mode = "host";
+        dr_mode = "host";
-        };
+};
-        dma-controller@47402000  {
+&cppi41dma  {
-                status = "okay";
+        status = "okay";
-        };
 };
 &i2c1 {
@@ -614,12 +614,14 @@
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
 };
 &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
 };
 &cpsw_emac0 {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index ab238850a7b2..ab9a34ce524c 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -57,6 +57,17 @@
                enable-active-high;
        };
+        vtt_fixed: fixedregulator@3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vtt";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+        };
        leds {
                pinctrl-names = "default";
                pinctrl-0 = <&user_leds_s0>;
@@ -363,31 +374,31 @@
 &usb {
        status = "okay";
+};
-        control@44e10620 {
+&usb_ctrl_mod {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401300 {
+&usb0_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401b00 {
+&usb1_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401000 {
+&usb0 {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401800 {
+&usb1 {
-                status = "okay";
+        status = "okay";
-                dr_mode = "host";
+        dr_mode = "host";
-        };
+};
-        dma-controller@47402000  {
+&cppi41dma  {
-                status = "okay";
+        status = "okay";
-        };
 };
 &epwmss2 {
@@ -484,12 +495,14 @@
        pinctrl-0 = <&cpsw_default>;
        pinctrl-1 = <&cpsw_sleep>;
        dual_emac = <1>;
+        status = "okay";
 };
 &davinci_mdio {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&davinci_mdio_default>;
        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
 };
 &cpsw_emac0 {
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
index 9f22c189f636..8a0a72dc7dd7 100644
--- a/arch/arm/boot/dts/am335x-igep0033.dtsi
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -95,6 +95,14 @@
        };
 };
+&mac {
+        status = "okay";
+};
+&davinci_mdio {
+        status = "okay";
+};
 &cpsw_emac0 {
        phy_id = <&davinci_mdio>, <0>;
 };
@@ -200,31 +208,31 @@
 &usb {
        status = "okay";
+};
-        control@44e10620 {
+&usb_ctrl_mod {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401300 {
+&usb0_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb-phy@47401b00 {
+&usb1_phy {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401000 {
+&usb0 {
-                status = "okay";
+        status = "okay";
-        };
+};
-        usb@47401800 {
+&usb1 {
-                status = "okay";
+        status = "okay";
-                dr_mode = "host";
+        dr_mode = "host";
-        };
+};
-        dma-controller@47402000  {
+&cppi41dma  {
-                status = "okay";
+        status = "okay";
-        };
 };
 #include "tps65910.dtsi"
diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts
index 9907b494b99c..a3466455b171 100644
--- a/arch/arm/boot/dts/am335x-nano.dts
+++ b/arch/arm/boot/dts/am335x-nano.dts
@@ -344,6 +344,11 @@
 &mac {
        dual_emac = <1>;
+        status = "okay";
+};
+&davinci_mdio {
+        status = "okay";
 };
 &cpsw_emac0 {
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 9ccfe508dea2..712edce7d6fb 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -96,47 +96,29 @@
                clock-div = <1>;
        };
-        ehrpwm0_gate_tbclk: ehrpwm0_gate_tbclk {
+        ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
                #clock-cells = <0>;
-                compatible = "ti,composite-no-wait-gate-clock";
+                compatible = "ti,gate-clock";
                clocks = <&dpll_per_m2_ck>;
                ti,bit-shift = <0>;
                reg = <0x0664>;
        };
-        ehrpwm0_tbclk: ehrpwm0_tbclk {
+        ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
-                #clock-cells = <0>;
-                compatible = "ti,composite-clock";
-                clocks = <&ehrpwm0_gate_tbclk>;
-        };
-        ehrpwm1_gate_tbclk: ehrpwm1_gate_tbclk {
                #clock-cells = <0>;
-                compatible = "ti,composite-no-wait-gate-clock";
+                compatible = "ti,gate-clock";
                clocks = <&dpll_per_m2_ck>;
                ti,bit-shift = <1>;
                reg = <0x0664>;
        };
-        ehrpwm1_tbclk: ehrpwm1_tbclk {
+        ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
-                #clock-cells = <0>;
-                compatible = "ti,composite-clock";
-                clocks = <&ehrpwm1_gate_tbclk>;
-        };
-        ehrpwm2_gate_tbclk: ehrpwm2_gate_tbclk {
                #clock-cells = <0>;
-                compatible = "ti,composite-no-wait-gate-clock";
+                compatible = "ti,gate-clock";
                clocks = <&dpll_per_m2_ck>;
                ti,bit-shift = <2>;
                reg = <0x0664>;
        };
-        ehrpwm2_tbclk: ehrpwm2_tbclk {
-                #clock-cells = <0>;
-                compatible = "ti,composite-clock";
-                clocks = <&ehrpwm2_gate_tbclk>;
-        };
 };
 &prcm_clocks {
        clk_32768_ck: clk_32768_ck {
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index 07f283c20eb1..9f53e824b037 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -144,12 +144,9 @@
                        compatible = "ti,edma3";
                        ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
                        reg =   <0x49000000 0x10000>,
-                                <0x44e10f90 0x10>;
+                                <0x44e10f90 0x40>;
                        interrupts = <12 13 14>;
                        #dma-cells = <1>;
-                        dma-channels = <64>;
-                        ti,edma-regions = <4>;
-                        ti,edma-slots = <256>;
                };
                gpio0: gpio@44e07000 {
@@ -688,6 +685,7 @@
                         */
                        interrupts = <40 41 42 43>;
                        ranges;
+                        status = "disabled";
                        davinci_mdio: mdio@4a101000 {
                                compatible = "ti,davinci_mdio";
@@ -696,6 +694,7 @@
                                ti,hwmods = "davinci_mdio";
                                bus_freq = <1000000>;
                                reg = <0x4a101000 0x100>;
+                                status = "disabled";
                        };
                        cpsw_emac0: slave@4a100200 {
@@ -802,7 +801,7 @@
                              <0x46000000 0x400000>;
                        reg-names = "mpu", "dat";
                        interrupts = <80>, <81>;
-                        interrupts-names = "tx", "rx";
+                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 8>,
                                <&edma 9>;
@@ -816,7 +815,7 @@
                              <0x46400000 0x400000>;
                        reg-names = "mpu", "dat";
                        interrupts = <82>, <83>;
-                        interrupts-names = "tx", "rx";
+                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 10>,
                                <&edma 11>;
diff --git a/arch/arm/boot/dts/am3517.dtsi b/arch/arm/boot/dts/am3517.dtsi
index 788391f91684..5a452fdd7c5d 100644
--- a/arch/arm/boot/dts/am3517.dtsi
+++ b/arch/arm/boot/dts/am3517.dtsi
@@ -62,5 +62,21 @@
        };
 };
+&iva {
+        status = "disabled";
+};
+&mailbox {
+        status = "disabled";
+};
+&mmu_isp {
+        status = "disabled";
+};
+&smartreflex_mpu_iva {
+        status = "disabled";
+};
 /include/ "am35xx-clocks.dtsi"
 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 36d523a26831..794c73e5c4e4 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -67,11 +67,15 @@
        };
        ocp {
-                compatible = "simple-bus";
+                compatible = "ti,am4372-l3-noc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
                ti,hwmods = "l3_main";
+                reg = <0x44000000 0x400000
+                       0x44800000 0x400000>;
+                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                prcm: prcm@44df0000 {
                        compatible = "ti,am4-prcm";
@@ -108,9 +112,6 @@
                                        <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
                                        <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                        #dma-cells = <1>;
-                        dma-channels = <64>;
-                        ti,edma-regions = <4>;
-                        ti,edma-slots = <256>;
                };
                uart0: serial@44e09000 {
@@ -521,6 +522,12 @@
                                /* Filled in by U-Boot */
                                mac-address = [ 00 00 00 00 00 00 ];
                        };
+                        phy_sel: cpsw-phy-sel@44e10650 {
+                                compatible = "ti,am43xx-cpsw-phy-sel";
+                                reg= <0x44e10650 0x4>;
+                                reg-names = "gmii-sel";
+                        };
                };
                epwmss0: epwmss@48300000 {
@@ -691,7 +698,7 @@
                              <0x46000000 0x400000>;
                        reg-names = "mpu", "dat";
                        interrupts = <80>, <81>;
-                        interrupts-names = "tx", "rx";
+                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 8>,
                               <&edma 9>;
@@ -705,7 +712,7 @@
                              <0x46400000 0x400000>;
                        reg-names = "mpu", "dat";
                        interrupts = <82>, <83>;
-                        interrupts-names = "tx", "rx";
+                        interrupt-names = "tx", "rx";
                        status = "disabled";
                        dmas = <&edma 10>,
                               <&edma 11>;
@@ -735,6 +742,121 @@
                        #size-cells = <1>;
                        status = "disabled";
                };
+                am43xx_control_usb2phy1: control-phy@44e10620 {
+                        compatible = "ti,control-phy-usb2-am437";
+                        reg = <0x44e10620 0x4>;
+                        reg-names = "power";
+                };
+                am43xx_control_usb2phy2: control-phy@0x44e10628 {
+                        compatible = "ti,control-phy-usb2-am437";
+                        reg = <0x44e10628 0x4>;
+                        reg-names = "power";
+                };
+                ocp2scp0: ocp2scp@483a8000 {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        ti,hwmods = "ocp2scp0";
+                        usb2_phy1: phy@483a8000 {
+                                compatible = "ti,am437x-usb2";
+                                reg = <0x483a8000 0x8000>;
+                                ctrl-module = <&am43xx_control_usb2phy1>;
+                                clocks = <&usb_phy0_always_on_clk32k>,
+                                         <&usb_otg_ss0_refclk960m>;
+                                clock-names = "wkupclk", "refclk";
+                                #phy-cells = <0>;
+                                status = "disabled";
+                        };
+                };
+                ocp2scp1: ocp2scp@483e8000 {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        ti,hwmods = "ocp2scp1";
+                        usb2_phy2: phy@483e8000 {
+                                compatible = "ti,am437x-usb2";
+                                reg = <0x483e8000 0x8000>;
+                                ctrl-module = <&am43xx_control_usb2phy2>;
+                                clocks = <&usb_phy1_always_on_clk32k>,
+                                         <&usb_otg_ss1_refclk960m>;
+                                clock-names = "wkupclk", "refclk";
+                                #phy-cells = <0>;
+                                status = "disabled";
+                        };
+                };
+                dwc3_1: omap_dwc3@48380000 {
+                        compatible = "ti,am437x-dwc3";
+                        ti,hwmods = "usb_otg_ss0";
+                        reg = <0x48380000 0x10000>;
+                        interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <1>;
+                        ranges;
+                        usb1: usb@48390000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x48390000 0x17000>;
+                                interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+                                phys = <&usb2_phy1>;
+                                phy-names = "usb2-phy";
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                                status = "disabled";
+                        };
+                };
+                dwc3_2: omap_dwc3@483c0000 {
+                        compatible = "ti,am437x-dwc3";
+                        ti,hwmods = "usb_otg_ss1";
+                        reg = <0x483c0000 0x10000>;
+                        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <1>;
+                        ranges;
+                        usb2: usb@483d0000 {
+                                compatible = "synopsys,dwc3";
+                                reg = <0x483d0000 0x17000>;
+                                interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+                                phys = <&usb2_phy2>;
+                                phy-names = "usb2-phy";
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                                status = "disabled";
+                        };
+                };
+                qspi: qspi@47900000 {
+                        compatible = "ti,am4372-qspi";
+                        reg = <0x47900000 0x100>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "qspi";
+                        interrupts = <0 138 0x4>;
+                        num-cs = <4>;
+                        status = "disabled";
+                };
+                hdq: hdq@48347000 {
+                        compatible = "ti,am43xx-hdq";
+                        reg = <0x48347000 0x1000>;
+                        interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&func_12m_clk>;
+                        clock-names = "fck";
+                        ti,hwmods = "hdq1w";
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index df8798e8bd25..c25d15837ce9 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -27,6 +27,17 @@
                enable-active-high;
        };
+        vtt_fixed: fixedregulator-vtt {
+                compatible = "regulator-fixed";
+                regulator-name = "vtt_fixed";
+                regulator-min-microvolt = <1500000>;
+                regulator-max-microvolt = <1500000>;
+                regulator-always-on;
+                regulator-boot-on;
+                enable-active-high;
+                gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+        };
        backlight {
                compatible = "pwm-backlight";
                pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
@@ -81,6 +92,85 @@
                        0x164 MUX_MODE0       /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
                >;
        };
+        pixcir_ts_pins: pixcir_ts_pins {
+                pinctrl-single,pins = <
+                        0x264 (PIN_INPUT_PULLUP | MUX_MODE7)  /* spi2_d0.gpio3_22 */
+                >;
+        };
+        cpsw_default: cpsw_default {
+                pinctrl-single,pins = <
+                        /* Slave 1 */
+                        0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxdv.rgmii1_rxctl */
+                        0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
+                        0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
+                        0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
+                        0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
+                        0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
+                        0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxclk.rmii1_rclk */
+                        0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd3 */
+                        0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd2 */
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd1.rgmii1_rxd1 */
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)  /* mii1_rxd0.rgmii1_rxd0 */
+                >;
+        };
+        cpsw_sleep: cpsw_sleep {
+                pinctrl-single,pins = <
+                        /* Slave 1 reset value */
+                        0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+        davinci_mdio_default: davinci_mdio_default {
+                pinctrl-single,pins = <
+                        /* MDIO */
+                        0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)    /* mdio_data.mdio_data */
+                        0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)                   /* mdio_clk.mdio_clk */
+                >;
+        };
+        davinci_mdio_sleep: davinci_mdio_sleep {
+                pinctrl-single,pins = <
+                        /* MDIO reset value */
+                        0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                        0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+                >;
+        };
+        nand_flash_x8: nand_flash_x8 {
+                pinctrl-single,pins = <
+                        0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* spi2_cs0.gpio/eMMCorNANDsel */
+                        0x0  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad0.gpmc_ad0 */
+                        0x4  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad1.gpmc_ad1 */
+                        0x8  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad2.gpmc_ad2 */
+                        0xc  (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad3.gpmc_ad3 */
+                        0x10 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad4.gpmc_ad4 */
+                        0x14 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad5.gpmc_ad5 */
+                        0x18 (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad6.gpmc_ad6 */
+                        0x1c (PIN_INPUT  | MUX_MODE0)   /* gpmc_ad7.gpmc_ad7 */
+                        0x70 (PIN_INPUT_PULLUP | MUX_MODE0)     /* gpmc_wait0.gpmc_wait0 */
+                        0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7)    /* gpmc_wpn.gpmc_wpn */
+                        0x7c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_csn0.gpmc_csn0  */
+                        0x90 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_advn_ale.gpmc_advn_ale */
+                        0x94 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_oen_ren.gpmc_oen_ren */
+                        0x98 (PIN_OUTPUT | MUX_MODE0)           /* gpmc_wen.gpmc_wen */
+                        0x9c (PIN_OUTPUT | MUX_MODE0)           /* gpmc_be0n_cle.gpmc_be0n_cle */
+                >;
+        };
 };
 &i2c0 {
@@ -93,6 +183,20 @@
        status = "okay";
        pinctrl-names = "default";
        pinctrl-0 = <&i2c1_pins>;
+        pixcir_ts@5c {
+                compatible = "pixcir,pixcir_tangoc";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pixcir_ts_pins>;
+                reg = <0x5c>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <22 0>;
+                attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
+                x-size = <1024>;
+                y-size = <600>;
+        };
 };
 &epwmss0 {
@@ -117,6 +221,11 @@
        status = "okay";
 };
+&gpio5 {
+        status = "okay";
+        ti,no-reset-on-init;
+};
 &mmc1 {
        status = "okay";
        vmmc-supply = <&vmmcsd_fixed>;
@@ -125,3 +234,128 @@
        pinctrl-0 = <&mmc1_pins>;
        cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
 };
+&usb2_phy1 {
+        status = "okay";
+};
+&usb1 {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+&usb2_phy2 {
+        status = "okay";
+};
+&usb2 {
+        dr_mode = "host";
+        status = "okay";
+};
+&mac {
+        slaves = <1>;
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&cpsw_default>;
+        pinctrl-1 = <&cpsw_sleep>;
+        status = "okay";
+};
+&davinci_mdio {
+        pinctrl-names = "default", "sleep";
+        pinctrl-0 = <&davinci_mdio_default>;
+        pinctrl-1 = <&davinci_mdio_sleep>;
+        status = "okay";
+};
+&cpsw_emac0 {
+        phy_id = <&davinci_mdio>, <0>;
+        phy-mode = "rgmii";
+};
+&elm {
+        status = "okay";
+};
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_flash_x8>;
+        ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+        nand@0,0 {
+                reg = <0 0 4>;          /* device IO registers */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <8>;
+                gpmc,device-width = <1>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <40>;
+                gpmc,cs-wr-off-ns = <40>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <25>;
+                gpmc,adv-wr-off-ns = <25>;
+                gpmc,we-on-ns = <0>;
+                gpmc,we-off-ns = <20>;
+                gpmc,oe-on-ns = <3>;
+                gpmc,oe-off-ns = <30>;
+                gpmc,access-ns = <30>;
+                gpmc,rd-cycle-ns = <40>;
+                gpmc,wr-cycle-ns = <40>;
+                gpmc,wait-pin = <0>;
+                gpmc,wait-on-read;
+                gpmc,wait-on-write;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x00040000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00040000 0x00040000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x000c0000 0x00040000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00100000 0x00080000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x00180000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x00280000 0x00040000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env.backup1";
+                        reg = <0x002c0000 0x00040000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00300000 0x00700000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00a00000 0x1f600000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 167dbc8494de..ad362c50e32e 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -138,6 +138,29 @@
                                0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
                        >;
                };
+                qspi1_default: qspi1_default {
+                        pinctrl-single,pins = <
+                                0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
+                                0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
+                                0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
+                                0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
+                                0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
+                                0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
+                        >;
+                };
+                pixcir_ts_pins: pixcir_ts_pins {
+                        pinctrl-single,pins = <
+                                0x44 (PIN_INPUT_PULLUP | MUX_MODE7)     /* gpmc_a1.gpio1_17 */
+                        >;
+                };
+                hdq_pins: pinmux_hdq_pins {
+                        pinctrl-single,pins = <
+                                0x234 (PIN_INPUT_PULLUP | MUX_MODE1)    /* cam1_wen.hdq_gpio */
+                        >;
+                };
        };
        matrix_keypad: matrix_keypad@0 {
@@ -226,7 +249,9 @@
        };
        pixcir_ts@5c {
-                compatible = "pixcir,pixcir_ts";
+                compatible = "pixcir,pixcir_tangoc";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pixcir_ts_pins>;
                reg = <0x5c>;
                interrupt-parent = <&gpio1>;
                interrupts = <17 0>;
@@ -234,7 +259,7 @@
                attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
                x-size = <1024>;
-                y-size = <768>;
+                y-size = <600>;
        };
 };
@@ -341,7 +366,7 @@
                };
                partition@9 {
                        label = "NAND.file-system";
-                        reg = <0x00800000 0x1F600000>;
+                        reg = <0x00a00000 0x1f600000>;
                };
        };
 };
@@ -367,3 +392,79 @@
        pinctrl-0 = <&spi1_pins>;
        status = "okay";
 };
+&usb2_phy1 {
+        status = "okay";
+};
+&usb1 {
+        dr_mode = "peripheral";
+        status = "okay";
+};
+&usb2_phy2 {
+        status = "okay";
+};
+&usb2 {
+        dr_mode = "host";
+        status = "okay";
+};
+&qspi {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&qspi1_default>;
+        spi-max-frequency = <48000000>;
+        m25p80@0 {
+                compatible = "mx66l51235l";
+                spi-max-frequency = <48000000>;
+                reg = <0>;
+                spi-cpol;
+                spi-cpha;
+                spi-tx-bus-width = <1>;
+                spi-rx-bus-width = <4>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* MTD partition table.
+                 * The ROM checks the first 512KiB
+                 * for a valid file to boot(XIP).
+                 */
+                partition@0 {
+                        label = "QSPI.U_BOOT";
+                        reg = <0x00000000 0x000080000>;
+                };
+                partition@1 {
+                        label = "QSPI.U_BOOT.backup";
+                        reg = <0x00080000 0x00080000>;
+                };
+                partition@2 {
+                        label = "QSPI.U-BOOT-SPL_OS";
+                        reg = <0x00100000 0x00010000>;
+                };
+                partition@3 {
+                        label = "QSPI.U_BOOT_ENV";
+                        reg = <0x00110000 0x00010000>;
+                };
+                partition@4 {
+                        label = "QSPI.U-BOOT-ENV.backup";
+                        reg = <0x00120000 0x00010000>;
+                };
+                partition@5 {
+                        label = "QSPI.KERNEL";
+                        reg = <0x00130000 0x0800000>;
+                };
+                partition@6 {
+                        label = "QSPI.FILESYSTEM";
+                        reg = <0x00930000 0x36D0000>;
+                };
+        };
+};
+&hdq {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdq_pins>;
+};
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 142009cc9332..c7dc9dab93a4 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -11,6 +11,22 @@
        sys_clkin_ck: sys_clkin_ck {
                #clock-cells = <0>;
                compatible = "ti,mux-clock";
+                clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
+                ti,bit-shift = <31>;
+                reg = <0x0040>;
+        };
+        crystal_freq_sel_ck: crystal_freq_sel_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
+                ti,bit-shift = <29>;
+                reg = <0x0040>;
+        };
+        sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
                clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
                ti,bit-shift = <22>;
                reg = <0x0040>;
@@ -87,6 +103,54 @@
                clock-mult = <1>;
                clock-div = <1>;
        };
+        ehrpwm0_tbclk: ehrpwm0_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0664>;
+        };
+        ehrpwm1_tbclk: ehrpwm1_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0664>;
+        };
+        ehrpwm2_tbclk: ehrpwm2_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0664>;
+        };
+        ehrpwm3_tbclk: ehrpwm3_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0664>;
+        };
+        ehrpwm4_tbclk: ehrpwm4_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0664>;
+        };
+        ehrpwm5_tbclk: ehrpwm5_tbclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_m2_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0664>;
+        };
 };
 &prcm_clocks {
        clk_32768_ck: clk_32768_ck {
@@ -229,6 +293,7 @@
                reg = <0x2e30>;
                ti,index-starts-at-one;
                ti,invert-autoidle-bit;
+                ti,set-rate-parent;
        };
        dpll_per_ck: dpll_per_ck {
@@ -511,6 +576,7 @@
                compatible = "ti,mux-clock";
                clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
                reg = <0x4244>;
+                ti,set-rate-parent;
        };
        dpll_extdev_ck: dpll_extdev_ck {
@@ -609,10 +675,13 @@
        dpll_per_clkdcoldo: dpll_per_clkdcoldo {
                #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,fixed-factor-clock";
                clocks = <&dpll_per_ck>;
-                clock-mult = <1>;
+                ti,clock-mult = <1>;
-                clock-div = <1>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <8>;
+                reg = <0x2e14>;
+                ti,invert-autoidle-bit;
        };
        dll_aging_clk_div: dll_aging_clk_div {
@@ -653,4 +722,36 @@
                clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
                reg = <0x4260>;
        };
+        usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&usbphy_32khz_clkmux>;
+                ti,bit-shift = <8>;
+                reg = <0x2a40>;
+        };
+        usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&usbphy_32khz_clkmux>;
+                ti,bit-shift = <8>;
+                reg = <0x2a48>;
+        };
+        usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x8a60>;
+        };
+        usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_per_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x8a68>;
+        };
 };
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index 82f238a9063f..416f4e5a69c1 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -35,7 +35,6 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
                        sata@a0000 {
@@ -67,6 +66,7 @@
                        i2c@11000 {
                                pinctrl-0 = <&i2c0_pins>;
                                pinctrl-names = "default";
+                                clock-frequency = <100000>;
                                status = "okay";
                                audio_codec: audio-codec@4a {
                                        compatible = "cirrus,cs42l51";
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 2354fe023ee0..097df7d8f0f6 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -47,7 +47,6 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
                        timer@20300 {
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
index 651aeb5ef439..d6d572e5af32 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn102.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -50,7 +50,6 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn104.dts b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
index 4e27587667bf..c5fe8b5dcdc7 100644
--- a/arch/arm/boot/dts/armada-370-netgear-rn104.dts
+++ b/arch/arm/boot/dts/armada-370-netgear-rn104.dts
@@ -50,7 +50,6 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index 3e2c857d6000..4169f4096ea3 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -51,7 +51,6 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
                        sata@a0000 {
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index bb77970c0b12..23227e0027ec 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -157,6 +157,7 @@
                                reg-shift = <2>;
                                interrupts = <41>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
                        serial@12100 {
@@ -165,6 +166,7 @@
                                reg-shift = <2>;
                                interrupts = <42>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -203,6 +205,11 @@
                                reg = <0x20300 0x34>, <0x20704 0x4>;
                        };
+                        pmsu@22000 {
+                                compatible = "marvell,armada-370-pmsu";
+                                reg = <0x22000 0x1000>;
+                        };
                        usb@50000 {
                                compatible = "marvell,orion-ehci";
                                reg = <0x50000 0x500>;
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index af1f11e9e5a0..21b588b6f6bd 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -220,6 +220,11 @@
                                clocks = <&coreclk 2>;
                        };
+                        cpurst@20800 {
+                                compatible = "marvell,armada-370-cpu-reset";
+                                reg = <0x20800 0x8>;
+                        };
                        audio_controller: audio-controller@30000 {
                                compatible = "marvell,armada370-audio";
                                reg = <0x30000 0x4000>;
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 9378d3136b41..772fec2d26ce 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -68,7 +68,6 @@
                        };
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
@@ -79,6 +78,11 @@
                                };
                        };
+                        sata@a0000 {
+                                status = "okay";
+                                nr-ports = <2>;
+                        };
                        nand: nand@d0000 {
                                pinctrl-0 = <&nand_pins>;
                                pinctrl-names = "default";
@@ -102,6 +106,14 @@
                                };
                        };
+                        usb@54000 {
+                                status = "okay";
+                        };
+                        usb3@58000 {
+                                status = "okay";
+                        };
                        mvsdio@d4000 {
                                pinctrl-0 = <&sdio_pins &sdio_st_pins>;
                                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index 3877693fb2d8..fb92551a1e71 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -39,6 +39,8 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-375-smp";
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
@@ -128,6 +130,11 @@
                                cache-level = <2>;
                        };
+                        scu@c000 {
+                                compatible = "arm,cortex-a9-scu";
+                                reg = <0xc000 0x58>;
+                        };
                        timer@c600 {
                                compatible = "arm,cortex-a9-twd-timer";
                                reg = <0xc600 0x20>;
@@ -194,6 +201,7 @@
                                reg-shift = <2>;
                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -203,6 +211,7 @@
                                reg-shift = <2>;
                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -320,6 +329,46 @@
                                clocks = <&coreclk 0>;
                        };
+                        watchdog@20300 {
+                                compatible = "marvell,armada-375-wdt";
+                                reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
+                                clocks = <&coreclk 0>;
+                        };
+                        cpurst@20800 {
+                                compatible = "marvell,armada-370-cpu-reset";
+                                reg = <0x20800 0x10>;
+                        };
+                        coherency-fabric@21010 {
+                                compatible = "marvell,armada-375-coherency-fabric";
+                                reg = <0x21010 0x1c>;
+                        };
+                        usb@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x50000 0x500>;
+                                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 18>;
+                                status = "disabled";
+                        };
+                        usb@54000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x54000 0x500>;
+                                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 26>;
+                                status = "disabled";
+                        };
+                        usb3@58000 {
+                                compatible = "marvell,armada-375-xhci";
+                                reg = <0x58000 0x20000>,<0x5b880 0x80>;
+                                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 16>;
+                                status = "disabled";
+                        };
                        xor@60800 {
                                compatible = "marvell,orion-xor";
                                reg = <0x60800 0x100
@@ -391,6 +440,12 @@
                                status = "disabled";
                        };
+                        thermal@e8078 {
+                                compatible = "marvell,armada375-thermal";
+                                reg = <0xe8078 0x4>, <0xe807c 0x8>;
+                                status = "okay";
+                        };
                        coreclk: mvebu-sar@e8204 {
                                compatible = "marvell,armada-375-core-clock";
                                reg = <0xe8204 0x04>;
diff --git a/arch/arm/boot/dts/armada-380.dtsi b/arch/arm/boot/dts/armada-380.dtsi
index 068031f0f263..e69bc6759c39 100644
--- a/arch/arm/boot/dts/armada-380.dtsi
+++ b/arch/arm/boot/dts/armada-380.dtsi
@@ -21,6 +21,8 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-380-smp";
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
@@ -99,7 +101,7 @@
                        pcie@3,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                reg = <0x1000 0 0 0 0>;
+                                reg = <0x1800 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
                                #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-385-db.dts b/arch/arm/boot/dts/armada-385-db.dts
index 6828d77696a6..ff9637dd8d0f 100644
--- a/arch/arm/boot/dts/armada-385-db.dts
+++ b/arch/arm/boot/dts/armada-385-db.dts
@@ -55,7 +55,6 @@
                        };
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
@@ -65,6 +64,10 @@
                                phy-mode = "rgmii-id";
                        };
+                        usb@50000 {
+                                status = "ok";
+                        };
                        ethernet@70000 {
                                status = "okay";
                                phy = <&phy0>;
@@ -81,6 +84,14 @@
                                };
                        };
+                        sata@a8000 {
+                                status = "okay";
+                        };
+                        sata@e0000 {
+                                status = "okay";
+                        };
                        flash@d0000 {
                                status = "okay";
                                num-cs = <1>;
@@ -101,6 +112,22 @@
                                        reg = <0x1000000 0x3f000000>;
                                };
                        };
+                        sdhci@d8000 {
+                                clock-frequency = <200000000>;
+                                broken-cd;
+                                wp-inverted;
+                                bus-width = <8>;
+                                status = "okay";
+                        };
+                        usb3@f0000 {
+                                status = "okay";
+                        };
+                        usb3@f8000 {
+                                status = "okay";
+                        };
                };
                pcie-controller {
diff --git a/arch/arm/boot/dts/armada-385-rd.dts b/arch/arm/boot/dts/armada-385-rd.dts
index 45250c88814b..40893255a3f0 100644
--- a/arch/arm/boot/dts/armada-385-rd.dts
+++ b/arch/arm/boot/dts/armada-385-rd.dts
@@ -51,7 +51,6 @@
                        };
                        serial@12000 {
-                                clock-frequency = <200000000>;
                                status = "okay";
                        };
@@ -77,6 +76,10 @@
                                        reg = <1>;
                                };
                        };
+                        usb3@f0000 {
+                                status = "okay";
+                        };
                };
                pcie-controller {
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index e2919f02e1d4..f011009bf4cf 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -21,6 +21,8 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-380-smp";
                cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a9";
@@ -110,7 +112,7 @@
                        pcie@3,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-                                reg = <0x1000 0 0 0 0>;
+                                reg = <0x1800 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
                                #interrupt-cells = <1>;
@@ -131,7 +133,7 @@
                        pcie@4,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-                                reg = <0x1000 0 0 0 0>;
+                                reg = <0x2000 0 0 0 0>;
                                #address-cells = <3>;
                                #size-cells = <2>;
                                #interrupt-cells = <1>;
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index ca8813bb99ba..3de364e81b52 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -108,6 +108,11 @@
                                cache-level = <2>;
                        };
+                        scu@c000 {
+                                compatible = "arm,cortex-a9-scu";
+                                reg = <0xc000 0x58>;
+                        };
                        timer@c600 {
                                compatible = "arm,cortex-a9-twd-timer";
                                reg = <0xc600 0x20>;
@@ -174,6 +179,7 @@
                                reg-shift = <2>;
                                interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -183,6 +189,7 @@
                                reg-shift = <2>;
                                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -267,6 +274,28 @@
                                clock-names = "nbclk", "fixed";
                        };
+                        watchdog@20300 {
+                                compatible = "marvell,armada-380-wdt";
+                                reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
+                                clocks = <&coreclk 2>, <&refclk>;
+                                clock-names = "nbclk", "fixed";
+                        };
+                        cpurst@20800 {
+                                compatible = "marvell,armada-370-cpu-reset";
+                                reg = <0x20800 0x10>;
+                        };
+                        coherency-fabric@21010 {
+                                compatible = "marvell,armada-380-coherency-fabric";
+                                reg = <0x21010 0x1c>;
+                        };
+                        pmsu@22000 {
+                                compatible = "marvell,armada-380-pmsu";
+                                reg = <0x22000 0x1000>;
+                        };
                        eth1: ethernet@30000 {
                                compatible = "marvell,armada-370-neta";
                                reg = <0x30000 0x4000>;
@@ -283,6 +312,14 @@
                                status = "disabled";
                        };
+                        usb@50000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0x58000 0x500>;
+                                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 18>;
+                                status = "disabled";
+                        };
                        xor@60800 {
                                compatible = "marvell,orion-xor";
                                reg = <0x60800 0x100
@@ -339,6 +376,22 @@
                                clocks = <&gateclk 4>;
                        };
+                        sata@a8000 {
+                                compatible = "marvell,armada-380-ahci";
+                                reg = <0xa8000 0x2000>;
+                                interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 15>;
+                                status = "disabled";
+                        };
+                        sata@e0000 {
+                                compatible = "marvell,armada-380-ahci";
+                                reg = <0xe0000 0x2000>;
+                                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 30>;
+                                status = "disabled";
+                        };
                        coredivclk: clock@e4250 {
                                compatible = "marvell,armada-380-corediv-clock";
                                reg = <0xe4250 0xc>;
@@ -347,6 +400,12 @@
                                clock-output-names = "nand";
                        };
+                        thermal@e8078 {
+                                compatible = "marvell,armada380-thermal";
+                                reg = <0xe4078 0x4>, <0xe4074 0x4>;
+                                status = "okay";
+                        };
                        flash@d0000 {
                                compatible = "marvell,armada370-nand";
                                reg = <0xd0000 0x54>;
@@ -356,6 +415,31 @@
                                clocks = <&coredivclk 0>;
                                status = "disabled";
                        };
+                        sdhci@d8000 {
+                                compatible = "marvell,armada-380-sdhci";
+                                reg = <0xd8000 0x1000>, <0xdc000 0x100>;
+                                interrupts = <0 25 0x4>;
+                                clocks = <&gateclk 17>;
+                                mrvl,clk-delay-cycles = <0x1F>;
+                                status = "disabled";
+                        };
+                        usb3@f0000 {
+                                compatible = "marvell,armada-380-xhci";
+                                reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
+                                interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 9>;
+                                status = "disabled";
+                        };
+                        usb3@f8000 {
+                                compatible = "marvell,armada-380-xhci";
+                                reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
+                                interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&gateclk 10>;
+                                status = "disabled";
+                        };
                };
        };
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
index d83d7d69ac01..a55a97a70505 100644
--- a/arch/arm/boot/dts/armada-xp-axpwifiap.dts
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -95,12 +95,10 @@
                        };
                        serial@12000 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12100 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index 448373c4b0e5..42ddb2864365 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -49,7 +49,7 @@
                        /* Device Bus parameters are required */
                        /* Read parameters */
-                        devbus,bus-width    = <8>;
+                        devbus,bus-width    = <16>;
                        devbus,turn-off-ps  = <60000>;
                        devbus,badr-skew-ps = <0>;
                        devbus,acc-first-ps = <124000>;
@@ -106,19 +106,15 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12100 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12200 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12300 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index 61bda687f782..0478c55ca656 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -59,7 +59,7 @@
                        /* Device Bus parameters are required */
                        /* Read parameters */
-                        devbus,bus-width    = <8>;
+                        devbus,bus-width    = <16>;
                        devbus,turn-off-ps  = <60000>;
                        devbus,badr-skew-ps = <0>;
                        devbus,acc-first-ps = <124000>;
@@ -104,19 +104,15 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12100 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12200 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12300 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
@@ -146,22 +142,22 @@
                        ethernet@70000 {
                                status = "okay";
                                phy = <&phy0>;
-                                phy-mode = "rgmii-id";
+                                phy-mode = "qsgmii";
                        };
                        ethernet@74000 {
                                status = "okay";
                                phy = <&phy1>;
-                                phy-mode = "rgmii-id";
+                                phy-mode = "qsgmii";
                        };
                        ethernet@30000 {
                                status = "okay";
                                phy = <&phy2>;
-                                phy-mode = "rgmii-id";
+                                phy-mode = "qsgmii";
                        };
                        ethernet@34000 {
                                status = "okay";
                                phy = <&phy3>;
-                                phy-mode = "rgmii-id";
+                                phy-mode = "qsgmii";
                        };
                        /* Front-side USB slot */
diff --git a/arch/arm/boot/dts/armada-xp-matrix.dts b/arch/arm/boot/dts/armada-xp-matrix.dts
index c2242745b9b8..25674fe81f70 100644
--- a/arch/arm/boot/dts/armada-xp-matrix.dts
+++ b/arch/arm/boot/dts/armada-xp-matrix.dts
@@ -37,19 +37,15 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12100 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12200 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12300 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 98335fb34b7a..1257ff1ed278 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -27,6 +27,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-xp-smp";
                cpu@0 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 9480cf891f8c..3396b25b39e1 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -29,6 +29,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-xp-smp";
                cpu@0 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 31ba6d8fbadf..6da84bf40aaf 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -30,6 +30,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "marvell,armada-xp-smp";
                cpu@0 {
                        device_type = "cpu";
diff --git a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
index ff049ee862eb..0cf999abc4ed 100644
--- a/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
+++ b/arch/arm/boot/dts/armada-xp-netgear-rn2120.dts
@@ -138,7 +138,6 @@
                        };
                        serial@12000 {
-                                clocks = <&coreclk 0>;
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 985948ce67b3..e5c6a0492ca0 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -39,7 +39,7 @@
                        /* Device Bus parameters are required */
                        /* Read parameters */
-                        devbus,bus-width    = <8>;
+                        devbus,bus-width    = <16>;
                        devbus,turn-off-ps  = <60000>;
                        devbus,badr-skew-ps = <0>;
                        devbus,acc-first-ps = <124000>;
@@ -72,11 +72,9 @@
                internal-regs {
                        serial@12000 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        serial@12100 {
-                                clock-frequency = <250000000>;
                                status = "okay";
                        };
                        pinctrl {
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index abb9f9dcc525..5902e8359c91 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -58,6 +58,7 @@
                                reg-shift = <2>;
                                interrupts = <43>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
                        serial@12300 {
@@ -66,6 +67,7 @@
                                reg-shift = <2>;
                                interrupts = <44>;
                                reg-io-width = <1>;
+                                clocks = <&coreclk 0>;
                                status = "disabled";
                        };
@@ -117,9 +119,9 @@
                                clock-names = "nbclk", "fixed";
                        };
-                        armada-370-xp-pmsu@22000 {
+                        cpurst@20800 {
-                                compatible = "marvell,armada-370-xp-pmsu";
+                                compatible = "marvell,armada-370-cpu-reset";
-                                reg = <0x22100 0x400>, <0x20800 0x20>;
+                                reg = <0x20800 0x20>;
                        };
                        eth2: ethernet@30000 {
diff --git a/arch/arm/boot/dts/at91-cosino_mega2560.dts b/arch/arm/boot/dts/at91-cosino_mega2560.dts
index a542d5837a17..27ebb0f722fd 100644
--- a/arch/arm/boot/dts/at91-cosino_mega2560.dts
+++ b/arch/arm/boot/dts/at91-cosino_mega2560.dts
@@ -32,11 +32,6 @@
                                status = "okay";
                        };
-                        tsadcc: tsadcc@f804c000 {
-                                status = "okay";
-                        };
                        rtc@fffffeb0 {
                                status = "okay";
                        };
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index ce1375595e5f..5b8e40400bec 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -21,6 +21,14 @@
                reg = <0x20000000 0x10000000>;
        };
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+        main_xtal {
+                clock-frequency = <12000000>;
+        };
        ahb {
                apb {
                        mmc0: mmc@f0000000 {
@@ -34,7 +42,7 @@
                        };
                        spi0: spi@f0004000 {
-                                cs-gpios = <&pioD 13 0>;
+                                cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
                                status = "okay";
                        };
@@ -43,11 +51,54 @@
                        };
                        i2c0: i2c@f0014000 {
+                                pinctrl-0 = <&pinctrl_i2c0_pu>;
                                status = "okay";
                        };
                        i2c1: i2c@f0018000 {
                                status = "okay";
+                                pmic: act8865@5b {
+                                        compatible = "active-semi,act8865";
+                                        reg = <0x5b>;
+                                        status = "okay";
+                                        regulators {
+                                                vcc_1v8_reg: DCDC_REG1 {
+                                                        regulator-name = "VCC_1V8";
+                                                        regulator-min-microvolt = <1800000>;
+                                                        regulator-max-microvolt = <1800000>;
+                                                        regulator-always-on;
+                                                };
+                                                vcc_1v2_reg: DCDC_REG2 {
+                                                        regulator-name = "VCC_1V2";
+                                                        regulator-min-microvolt = <1200000>;
+                                                        regulator-max-microvolt = <1200000>;
+                                                        regulator-always-on;
+                                                };
+                                                vcc_3v3_reg: DCDC_REG3 {
+                                                        regulator-name = "VCC_3V3";
+                                                        regulator-min-microvolt = <3300000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                                vddfuse_reg: LDO_REG1 {
+                                                        regulator-name = "FUSE_2V5";
+                                                        regulator-min-microvolt = <2500000>;
+                                                        regulator-max-microvolt = <2500000>;
+                                                };
+                                                vddana_reg: LDO_REG2 {
+                                                        regulator-name = "VDDANA";
+                                                        regulator-min-microvolt = <3300000>;
+                                                        regulator-max-microvolt = <3300000>;
+                                                        regulator-always-on;
+                                                };
+                                        };
+                                };
                        };
                        macb0: ethernet@f0028000 {
@@ -55,6 +106,12 @@
                                status = "okay";
                        };
+                        pwm0: pwm@f002c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_pwm0_pwmh0_0 &pinctrl_pwm0_pwmh1_0>;
+                                status = "okay";
+                        };
                        usart0: serial@f001c000 {
                                status = "okay";
                        };
@@ -79,7 +136,7 @@
                        };
                        spi1: spi@f8008000 {
-                                cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioD 16 0>;
+                                cs-gpios = <&pioC 25 0>;
                                status = "okay";
                        };
@@ -102,6 +159,7 @@
                        i2c2: i2c@f801c000 {
                                dmas = <0>, <0>;        /* Do not use DMA for i2c2 */
+                                pinctrl-0 = <&pinctrl_i2c2_pu>;
                                status = "okay";
                        };
@@ -116,6 +174,18 @@
                        pinctrl@fffff200 {
                                board {
+                                        pinctrl_i2c0_pu: i2c0_pu {
+                                                atmel,pins =
+                                                        <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
+                                        };
+                                        pinctrl_i2c2_pu: i2c2_pu {
+                                                atmel,pins =
+                                                        <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
+                                                        <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
+                                        };
                                        pinctrl_mmc0_cd: mmc0_cd {
                                                atmel,pins =
                                                        <AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 366fc2cbcd64..c0e0eae16a27 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -641,7 +641,7 @@
                                trigger@3 {
                                        reg = <3>;
                                        trigger-name = "external";
-                                        trigger-value = <0x13>;
+                                        trigger-value = <0xd>;
                                        trigger-external;
                                };
                        };
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index e21dda0e8986..b309c1c6e848 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -10,7 +10,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 / {
        model = "Atmel AT91SAM9261 family SoC";
@@ -29,6 +29,7 @@
                i2c0 = &i2c0;
                ssc0 = &ssc0;
                ssc1 = &ssc1;
+                ssc2 = &ssc2;
        };
        cpus {
@@ -45,6 +46,18 @@
                reg = <0x20000000 0x08000000>;
        };
+        main_xtal: main_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        slow_xtal: slow_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
        ahb {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -182,6 +195,8 @@
                                interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
                                status = "disabled";
                        };
@@ -191,6 +206,19 @@
                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
+                                clocks = <&ssc1_clk>;
+                                clock-names = "pclk";
+                                status = "disabled";
+                        };
+                        ssc2: ssc@fffc4000 {
+                                compatible = "atmel,at91rm9200-ssc";
+                                reg = <0xfffc4000 0x4000>;
+                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
+                                clocks = <&ssc2_clk>;
+                                clock-names = "pclk";
                                status = "disabled";
                        };
@@ -385,6 +413,22 @@
                                        };
                                };
+                                ssc2 {
+                                        pinctrl_ssc2_tx: ssc2_tx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_ssc2_rx: ssc2_rx-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 29 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
@@ -524,17 +568,24 @@
                                #size-cells = <0>;
                                #interrupt-cells = <1>;
-                                clk32k: slck {
+                                slow_rc_osc: slow_rc_osc {
                                        compatible = "fixed-clock";
                                        #clock-cells = <0>;
                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                clk32k: slck {
+                                        compatible = "atmel,at91sam9260-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc &slow_xtal>;
                                };
                                main: mainck {
                                        compatible = "atmel,at91rm9200-clk-main";
                                        #clock-cells = <0>;
                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
-                                        clocks = <&clk32k>;
+                                        clocks = <&main_xtal>;
                                };
                                plla: pllack {
@@ -545,7 +596,8 @@
                                        reg = <0>;
                                        atmel,clk-input-range = <1000000 32000000>;
                                        #atmel,pll-clk-output-range-cells = <4>;
-                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                        atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+                                                                <190000000 240000000 2 1>;
                                };
                                pllb: pllbck {
@@ -554,9 +606,9 @@
                                        interrupts-extended = <&pmc AT91_PMC_LOCKB>;
                                        clocks = <&main>;
                                        reg = <1>;
-                                        atmel,clk-input-range = <1000000 32000000>;
+                                        atmel,clk-input-range = <1000000 5000000>;
                                        #atmel,pll-clk-output-range-cells = <4>;
-                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                        atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
                                };
                                mck: masterck {
@@ -565,16 +617,48 @@
                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
                                        clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
                                        atmel,clk-output-range = <0 94000000>;
-                                        atmel,clk-divisors = <1 2 4 3>;
+                                        atmel,clk-divisors = <1 2 4 0>;
                                };
                                usb: usbck {
                                        compatible = "atmel,at91rm9200-clk-usb";
                                        #clock-cells = <0>;
-                                        atmel,clk-divisors = <1 2 4 3>;
+                                        atmel,clk-divisors = <1 2 4 0>;
                                        clocks = <&pllb>;
                                };
+                                prog: progck {
+                                        compatible = "atmel,at91rm9200-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+                                        prog2: prog2 {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                interrupts = <AT91_PMC_PCKRDY(2)>;
+                                        };
+                                        prog3: prog3 {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                                interrupts = <AT91_PMC_PCKRDY(3)>;
+                                        };
+                                };
                                systemck {
                                        compatible = "atmel,at91rm9200-clk-system";
                                        #address-cells = <1>;
@@ -592,6 +676,30 @@
                                                clocks = <&usb>;
                                        };
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+                                        pck2: pck2 {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                                clocks = <&prog2>;
+                                        };
+                                        pck3: pck3 {
+                                                #clock-cells = <0>;
+                                                reg = <11>;
+                                                clocks = <&prog3>;
+                                        };
                                        hclk0: hclk0 {
                                                #clock-cells = <0>;
                                                reg = <16>;
@@ -666,6 +774,21 @@
                                                reg = <13>;
                                        };
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                        };
+                                        ssc1_clk: ssc1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                        };
+                                        ssc2_clk: ssc2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                        };
                                        tc0_clk: tc0_clk {
                                                #clock-cells = <0>;
                                                reg = <17>;
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index 2ce527e70c7a..c6683ea8b743 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -20,6 +20,10 @@
                reg = <0x20000000 0x4000000>;
        };
+        main_xtal {
+                clock-frequency = <18432000>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 9cdaecff13b3..ace6bf197b70 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -136,6 +136,36 @@
                                      >;
                                /* shared pinctrl settings */
+                                adc0 {
+                                        pinctrl_adc0_adtrg: adc0_adtrg {
+                                                atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0 {
+                                                atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1 {
+                                                atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2 {
+                                                atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3 {
+                                                atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4 {
+                                                atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad5: adc0_ad5 {
+                                                atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad6: adc0_ad6 {
+                                                atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad7: adc0_ad7 {
+                                                atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
@@ -634,10 +664,9 @@
                        adc0: adc@fffb0000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "atmel,at91sam9260-adc";
+                                compatible = "atmel,at91sam9g45-adc";
                                reg = <0xfffb0000 0x100>;
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
-                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xff>;
                                atmel,adc-vref = <3300>;
                                atmel,adc-startup-time = <40>;
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 7ff665a8c708..9f5b0a674995 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -8,6 +8,7 @@
 */
 /dts-v1/;
 #include "at91sam9g45.dtsi"
+#include <dt-bindings/pwm/pwm.h>
 / {
        model = "Atmel AT91SAM9M10G45-EK";
@@ -130,6 +131,21 @@
                                status = "okay";
                        };
+                        adc0: adc@fffb0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_ad6
+                                        &pinctrl_adc0_ad7>;
+                                atmel,adc-ts-wires = <4>;
+                                status = "okay";
+                        };
                        pwm0: pwm@fffb8000 {
                                status = "okay";
@@ -216,14 +232,14 @@
                d6 {
                        label = "d6";
-                        pwms = <&pwm0 3 5000 0>;
+                        pwms = <&pwm0 3 5000 PWM_POLARITY_INVERTED>;
                        max-brightness = <255>;
                        linux,default-trigger = "nand-disk";
                };
                d7 {
                        label = "d7";
-                        pwms = <&pwm0 1 5000 0>;
+                        pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
                        max-brightness = <255>;
                        linux,default-trigger = "mmc0";
                };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 9f04808fc697..d1b82e6635d5 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
 / {
        model = "Atmel AT91SAM9N12 SoC";
@@ -49,6 +50,18 @@
                reg = <0x20000000 0x10000000>;
        };
+        slow_xtal: slow_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        main_xtal: main_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
        ahb {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -75,8 +88,280 @@
                        };
                        pmc: pmc@fffffc00 {
-                                compatible = "atmel,at91rm9200-pmc";
+                                compatible = "atmel,at91sam9n12-pmc";
-                                reg = <0xfffffc00 0x100>;
+                                reg = <0xfffffc00 0x200>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+                                main_rc_osc: main_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-main-rc-osc";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
+                                        clock-frequency = <12000000>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                main_osc: main_osc {
+                                        compatible = "atmel,at91rm9200-clk-main-osc";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                        clocks = <&main_xtal>;
+                                };
+                                main: mainck {
+                                        compatible = "atmel,at91sam9x5-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
+                                        clocks = <&main_rc_osc>, <&main_osc>;
+                                };
+                                plla: pllack {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <2000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
+                                                                      <695000000 750000000 1 0>,
+                                                                      <645000000 700000000 2 0>,
+                                                                      <595000000 650000000 3 0>,
+                                                                      <545000000 600000000 0 1>,
+                                                                      <495000000 555000000 1 1>,
+                                                                      <445000000 500000000 1 2>,
+                                                                      <400000000 450000000 1 3>;
+                                };
+                                plladiv: plladivck {
+                                        compatible = "atmel,at91sam9x5-clk-plldiv";
+                                        #clock-cells = <0>;
+                                        clocks = <&plla>;
+                                };
+                                pllb: pllbck {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+                                        clocks = <&main>;
+                                        reg = <1>;
+                                        atmel,clk-input-range = <2000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <3>;
+                                        atmel,pll-clk-output-ranges = <30000000 100000000 0>;
+                                };
+                                mck: masterck {
+                                        compatible = "atmel,at91sam9x5-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>;
+                                        atmel,clk-output-range = <0 133333333>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                        atmel,master-clk-have-div3-pres;
+                                };
+                                usb: usbck {
+                                        compatible = "atmel,at91sam9n12-clk-usb";
+                                        #clock-cells = <0>;
+                                        clocks = <&pllb>;
+                                };
+                                prog: progck {
+                                        compatible = "atmel,at91sam9x5-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&pllb>, <&mck>;
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+                                };
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        ddrck: ddrck {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                clocks = <&mck>;
+                                        };
+                                        lcdck: lcdck {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                                clocks = <&mck>;
+                                        };
+                                        uhpck: uhpck {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                                clocks = <&usb>;
+                                        };
+                                        udpck: udpck {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                                clocks = <&usb>;
+                                        };
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+                                };
+                                periphck {
+                                        compatible = "atmel,at91sam9x5-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+                                        pioAB_clk: pioAB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                        };
+                                        pioCD_clk: pioCD_clk {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                        };
+                                        fuse_clk: fuse_clk {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                        };
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <5>;
+                                        };
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+                                        usart3_clk: usart3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+                                        twi0_clk: twi0_clk {
+                                                reg = <9>;
+                                                #clock-cells = <0>;
+                                        };
+                                        twi1_clk: twi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                        };
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                        };
+                                        spi1_clk: spi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                        };
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                        };
+                                        uart1_clk: uart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                        };
+                                        tcb_clk: tcb_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                        };
+                                        pwm_clk: pwm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <18>;
+                                        };
+                                        adc_clk: adc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                        };
+                                        dma0_clk: dma0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <20>;
+                                        };
+                                        uhphs_clk: uhphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <22>;
+                                        };
+                                        udphs_clk: udphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <23>;
+                                        };
+                                        lcdc_clk: lcdc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <25>;
+                                        };
+                                        sha_clk: sha_clk {
+                                                #clock-cells = <0>;
+                                                reg = <27>;
+                                        };
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <28>;
+                                        };
+                                        aes_clk: aes_clk {
+                                                #clock-cells = <0>;
+                                                reg = <29>;
+                                        };
+                                        trng_clk: trng_clk {
+                                                #clock-cells = <0>;
+                                                reg = <30>;
+                                        };
+                                };
                        };
                        rstc@fffffe00 {
@@ -88,6 +373,7 @@
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                clocks = <&mck>;
                        };
                        shdwc@fffffe10 {
@@ -95,12 +381,38 @@
                                reg = <0xfffffe10 0x10>;
                        };
+                        sckc@fffffe50 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfffffe50 0x4>;
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_xtal>;
+                                };
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                clk32k: slck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc>, <&slow_osc>;
+                                };
+                        };
                        mmc0: mmc@f0008000 {
                                compatible = "atmel,hsmci";
                                reg = <0xf0008000 0x600>;
                                interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
                                dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -110,12 +422,16 @@
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb_clk>;
+                                clock-names = "t0_clk";
                        };
                        tcb1: timer@f800c000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf800c000 0x100>;
                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb_clk>;
+                                clock-names = "t0_clk";
                        };
                        dma: dma-controller@ffffec00 {
@@ -123,6 +439,8 @@
                                reg = <0xffffec00 0x200>;
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
+                                clocks = <&dma0_clk>;
+                                clock-names = "dma_clk";
                        };
                        pinctrl@fffff400 {
@@ -392,6 +710,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioAB_clk>;
                                };
                                pioB: gpio@fffff600 {
@@ -402,6 +721,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioAB_clk>;
                                };
                                pioC: gpio@fffff800 {
@@ -412,6 +732,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioCD_clk>;
                                };
                                pioD: gpio@fffffa00 {
@@ -422,6 +743,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioCD_clk>;
                                };
                        };
@@ -431,6 +753,8 @@
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&mck>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -443,6 +767,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
                                status = "disabled";
                        };
@@ -452,6 +778,8 @@
                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
+                                clocks = <&usart0_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -461,6 +789,8 @@
                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
+                                clocks = <&usart1_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -470,6 +800,8 @@
                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -479,6 +811,8 @@
                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
+                                clocks = <&usart3_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -493,6 +827,7 @@
                                #size-cells = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c0>;
+                                clocks = <&twi0_clk>;
                                status = "disabled";
                        };
@@ -507,6 +842,7 @@
                                #size-cells = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c1>;
+                                clocks = <&twi1_clk>;
                                status = "disabled";
                        };
@@ -521,6 +857,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
                                status = "disabled";
                        };
@@ -535,6 +873,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
+                                clocks = <&spi1_clk>;
+                                clock-names = "spi_clk";
                                status = "disabled";
                        };
@@ -554,6 +894,7 @@
                                reg = <0xf8034000 0x300>;
                                interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>;
                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
                                status = "disabled";
                        };
                };
@@ -584,6 +925,9 @@
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00500000 0x00100000>;
                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+                                 <&uhpck>;
+                        clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                        status = "disabled";
                };
        };
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 924a6a6ffd0f..64bbe46e4f90 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -21,6 +21,14 @@
                reg = <0x20000000 0x8000000>;
        };
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+        main_xtal {
+                clock-frequency = <16000000>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 63e1784d272c..1da183155eee 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -8,9 +8,10 @@
 #include "skeleton.dtsi"
 #include <dt-bindings/pinctrl/at91.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
 / {
        model = "Atmel AT91SAM9RL family SoC";
@@ -32,6 +33,7 @@
                i2c1 = &i2c1;
                ssc0 = &ssc0;
                ssc1 = &ssc1;
+                pwm0 = &pwm0;
        };
        cpus {
@@ -48,12 +50,43 @@
                reg = <0x20000000 0x04000000>;
        };
+        slow_xtal: slow_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        main_xtal: main_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        clocks {
+                adc_op_clk: adc_op_clk{
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <1000000>;
+                };
+        };
        ahb {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
+                fb0: fb@00500000 {
+                        compatible = "atmel,at91sam9rl-lcdc";
+                        reg = <0x00500000 0x1000>;
+                        interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_fb>;
+                        clocks = <&lcd_clk>, <&lcd_clk>;
+                        clock-names = "hclk", "lcdc_clk";
+                        status = "disabled";
+                };
                nand0: nand@40000000 {
                        compatible = "atmel,at91rm9200-nand";
                        #address-cells = <1>;
@@ -187,6 +220,16 @@
                                status = "disabled";
                        };
+                        pwm0: pwm@fffc8000 {
+                                compatible = "atmel,at91sam9rl-pwm";
+                                reg = <0xfffc8000 0x300>;
+                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
+                                #pwm-cells = <3>;
+                                clocks = <&pwm_clk>;
+                                clock-names = "pwm_clk";
+                                status = "disabled";
+                        };
                        spi0: spi@fffcc000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
@@ -200,6 +243,111 @@
                                status = "disabled";
                        };
+                        adc0: adc@fffd0000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-adc";
+                                reg = <0xfffd0000 0x100>;
+                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&adc_clk>, <&adc_op_clk>;
+                                clock-names = "adc_clk", "adc_op_clk";
+                                atmel,adc-use-external-triggers;
+                                atmel,adc-channels-used = <0x3f>;
+                                atmel,adc-vref = <3300>;
+                                atmel,adc-startup-time = <40>;
+                                atmel,adc-res = <8 10>;
+                                atmel,adc-res-names = "lowres", "highres";
+                                atmel,adc-use-res = "highres";
+                                trigger@0 {
+                                        reg = <0>;
+                                        trigger-name = "timer-counter-0";
+                                        trigger-value = <0x1>;
+                                };
+                                trigger@1 {
+                                        reg = <1>;
+                                        trigger-name = "timer-counter-1";
+                                        trigger-value = <0x3>;
+                                };
+                                trigger@2 {
+                                        reg = <2>;
+                                        trigger-name = "timer-counter-2";
+                                        trigger-value = <0x5>;
+                                };
+                                trigger@3 {
+                                        reg = <3>;
+                                        trigger-name = "external";
+                                        trigger-value = <0x13>;
+                                        trigger-external;
+                                };
+                        };
+                        usb0: gadget@fffd4000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                compatible = "atmel,at91sam9rl-udc";
+                                reg = <0x00600000 0x100000>,
+                                      <0xfffd4000 0x4000>;
+                                interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                                clocks = <&udphs_clk>, <&utmi>;
+                                clock-names = "pclk", "hclk";
+                                status = "disabled";
+                                ep0 {
+                                        reg = <0>;
+                                        atmel,fifo-size = <64>;
+                                        atmel,nb-banks = <1>;
+                                };
+                                ep1 {
+                                        reg = <1>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep2 {
+                                        reg = <2>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <2>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep3 {
+                                        reg = <3>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep4 {
+                                        reg = <4>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                };
+                                ep5 {
+                                        reg = <5>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                                ep6 {
+                                        reg = <6>;
+                                        atmel,fifo-size = <1024>;
+                                        atmel,nb-banks = <3>;
+                                        atmel,can-dma;
+                                        atmel,can-isoc;
+                                };
+                        };
                        ramc0: ramc@ffffea00 {
                                compatible = "atmel,at91sam9260-sdramc";
                                reg = <0xffffea00 0x200>;
@@ -238,6 +386,44 @@
                                        <0x003fffff 0x0001ff3c>;  /* pioD */
                                /* shared pinctrl settings */
+                                adc0 {
+                                        pinctrl_adc0_ts: adc0_ts-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad0: adc0_ad0-0 {
+                                                atmel,pins = <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad1: adc0_ad1-0 {
+                                                atmel,pins = <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad2: adc0_ad2-0 {
+                                                atmel,pins = <AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad3: adc0_ad3-0 {
+                                                atmel,pins = <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad4: adc0_ad4-0 {
+                                                atmel,pins = <AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_ad5: adc0_ad5-0 {
+                                                atmel,pins = <AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_adc0_adtrg: adc0_adtrg-0 {
+                                                atmel,pins = <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                dbgu {
                                        pinctrl_dbgu: dbgu-0 {
                                                atmel,pins =
@@ -246,6 +432,33 @@
                                        };
                                };
+                                fb {
+                                        pinctrl_fb: fb-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOC 1 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 15 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 16 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 18 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                i2c_gpio0 {
                                        pinctrl_i2c_gpio0: i2c_gpio0-0 {
                                                atmel,pins =
@@ -307,6 +520,61 @@
                                        };
                                };
+                                pwm0 {
+                                        pinctrl_pwm0_pwm0_0: pwm0_pwm0-0 {
+                                                atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm0_1: pwm0_pwm0-1 {
+                                                atmel,pins = <AT91_PIOC 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm0_2: pwm0_pwm0-2 {
+                                                atmel,pins = <AT91_PIOD 14 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm1_0: pwm0_pwm1-0 {
+                                                atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm1_1: pwm0_pwm1-1 {
+                                                atmel,pins = <AT91_PIOC 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm1_2: pwm0_pwm1-2 {
+                                                atmel,pins = <AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm2_0: pwm0_pwm2-0 {
+                                                atmel,pins = <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm2_1: pwm0_pwm2-1 {
+                                                atmel,pins = <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm2_2: pwm0_pwm2-2 {
+                                                atmel,pins = <AT91_PIOD 16 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm3_0: pwm0_pwm3-0 {
+                                                atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
+                                        };
+                                        pinctrl_pwm0_pwm3_1: pwm0_pwm3-1 {
+                                                atmel,pins = <AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
+                                spi0 {
+                                        pinctrl_spi0: spi0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
+                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
+                                        };
+                                };
                                ssc0 {
                                        pinctrl_ssc0_tx: ssc0_tx-0 {
                                                atmel,pins =
@@ -339,15 +607,6 @@
                                        };
                                };
-                                spi0 {
-                                        pinctrl_spi0: spi0-0 {
-                                                atmel,pins =
-                                                        <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_NONE>,
-                                                        <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE>,
-                                                        <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
-                                        };
-                                };
                                tcb0 {
                                        pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
                                                atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
@@ -548,17 +807,11 @@
                                #size-cells = <0>;
                                #interrupt-cells = <1>;
-                                clk32k: slck {
-                                        compatible = "fixed-clock";
-                                        #clock-cells = <0>;
-                                        clock-frequency = <32768>;
-                                };
                                main: mainck {
                                        compatible = "atmel,at91rm9200-clk-main";
                                        #clock-cells = <0>;
                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
-                                        clocks = <&clk32k>;
+                                        clocks = <&main_xtal>;
                                };
                                plla: pllack {
@@ -568,8 +821,9 @@
                                        clocks = <&main>;
                                        reg = <0>;
                                        atmel,clk-input-range = <1000000 32000000>;
-                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        #atmel,pll-clk-output-range-cells = <3>;
-                                        atmel,pll-clk-output-ranges = <80000000 200000000 190000000 240000000>;
+                                        atmel,pll-clk-output-ranges = <80000000 200000000 0>,
+                                                                <190000000 240000000 2>;
                                };
                                utmi: utmick {
@@ -586,7 +840,7 @@
                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
                                        clocks = <&clk32k>, <&main>, <&plla>, <&utmi>;
                                        atmel,clk-output-range = <0 94000000>;
-                                        atmel,clk-divisors = <1 2 4 3>;
+                                        atmel,clk-divisors = <1 2 4 0>;
                                };
                                prog: progck {
@@ -769,6 +1023,32 @@
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                status = "disabled";
                        };
+                        sckc@fffffd50 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfffffd50 0x4>;
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        atmel,startup-time-usec = <1200000>;
+                                        clocks = <&slow_xtal>;
+                                };
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        atmel,startup-time-usec = <75>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                clk32k: slck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc &slow_osc>;
+                                };
+                        };
                };
        };
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index cddb37825fad..d4a010e40fe3 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -20,6 +20,15 @@
                reg = <0x20000000 0x4000000>;
        };
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+        main_xtal {
+                clock-frequency = <12000000>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -32,6 +41,37 @@
        };
        ahb {
+                fb0: fb@00500000 {
+                        display = <&display0>;
+                        status = "okay";
+                        display0: display {
+                                bits-per-pixel = <16>;
+                                atmel,lcdcon-backlight;
+                                atmel,dmacon = <0x1>;
+                                atmel,lcdcon2 = <0x80008002>;
+                                atmel,guard-time = <1>;
+                                atmel,lcd-wiring-mode = "RGB";
+                                display-timings {
+                                        native-mode = <&timing0>;
+                                        timing0: timing0 {
+                                                clock-frequency = <4965000>;
+                                                hactive = <240>;
+                                                vactive = <320>;
+                                                hback-porch = <1>;
+                                                hfront-porch = <33>;
+                                                vback-porch = <1>;
+                                                vfront-porch = <0>;
+                                                hsync-len = <5>;
+                                                vsync-len = <1>;
+                                                hsync-active = <1>;
+                                                vsync-active = <1>;
+                                        };
+                                };
+                        };
+                };
                nand0: nand@40000000 {
                        nand-bus-width = <8>;
                        nand-ecc-mode = "soft";
@@ -92,6 +132,43 @@
                                status = "okay";
                        };
+                        adc0: adc@fffd0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <
+                                        &pinctrl_adc0_ad0
+                                        &pinctrl_adc0_ad1
+                                        &pinctrl_adc0_ad2
+                                        &pinctrl_adc0_ad3
+                                        &pinctrl_adc0_ad4
+                                        &pinctrl_adc0_ad5
+                                        &pinctrl_adc0_adtrg>;
+                                atmel,adc-ts-wires = <4>;
+                                status = "okay";
+                        };
+                        usb0: gadget@fffd4000 {
+                                atmel,vbus-gpio = <&pioA 8 GPIO_ACTIVE_HIGH>;
+                                status = "okay";
+                        };
+                        spi0: spi@fffcc000 {
+                                status = "okay";
+                                cs-gpios = <&pioA 28 0>, <0>, <0>, <0>;
+                                mtd_dataflash@0 {
+                                        compatible = "atmel,at45", "atmel,dataflash";
+                                        spi-max-frequency = <15000000>;
+                                        reg = <0>;
+                                };
+                        };
+                        pwm0: pwm@fffc8000 {
+                                status = "okay";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_pwm0_pwm1_2>,
+                                        <&pinctrl_pwm0_pwm2_2>;
+                        };
                        dbgu: serial@fffff200 {
                                status = "okay";
                        };
@@ -117,18 +194,24 @@
                };
        };
-        leds {
+        pwmleds {
-                compatible = "gpio-leds";
+                compatible = "pwm-leds";
                ds1 {
                        label = "ds1";
-                        gpios = <&pioD 15 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 1 5000 PWM_POLARITY_INVERTED>;
+                        max-brightness = <255>;
                };
                ds2 {
                        label = "ds2";
-                        gpios = <&pioD 16 GPIO_ACTIVE_LOW>;
+                        pwms = <&pwm0 2 5000 PWM_POLARITY_INVERTED>;
+                        max-brightness = <255>;
                };
+        };
+        leds {
+                compatible = "gpio-leds";
                ds3 {
                        label = "ds3";
@@ -154,4 +237,12 @@
                        gpio-key,wakeup;
                };
        };
+        i2c@0 {
+                status = "okay";
+        };
+        i2c@1 {
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index fc13c9240da8..1a57298636a5 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/at91.h>
 / {
        model = "Atmel AT91SAM9x5 family SoC";
@@ -51,6 +52,24 @@
                reg = <0x20000000 0x10000000>;
        };
+        slow_xtal: slow_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        main_xtal: main_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        adc_op_clk: adc_op_clk{
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <5000000>;
+        };
        ahb {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -77,8 +96,272 @@
                        };
                        pmc: pmc@fffffc00 {
-                                compatible = "atmel,at91rm9200-pmc";
+                                compatible = "atmel,at91sam9x5-pmc";
                                reg = <0xfffffc00 0x100>;
+                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                interrupt-controller;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                #interrupt-cells = <1>;
+                                main_rc_osc: main_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-main-rc-osc";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCRCS>;
+                                        clock-frequency = <12000000>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                main_osc: main_osc {
+                                        compatible = "atmel,at91rm9200-clk-main-osc";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+                                        clocks = <&main_xtal>;
+                                };
+                                main: mainck {
+                                        compatible = "atmel,at91sam9x5-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MOSCSELS>;
+                                        clocks = <&main_rc_osc>, <&main_osc>;
+                                };
+                                plla: pllack {
+                                        compatible = "atmel,at91rm9200-clk-pll";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+                                        clocks = <&main>;
+                                        reg = <0>;
+                                        atmel,clk-input-range = <2000000 32000000>;
+                                        #atmel,pll-clk-output-range-cells = <4>;
+                                        atmel,pll-clk-output-ranges = <745000000 800000000 0 0
+                                                                       695000000 750000000 1 0
+                                                                       645000000 700000000 2 0
+                                                                       595000000 650000000 3 0
+                                                                       545000000 600000000 0 1
+                                                                       495000000 555000000 1 1
+                                                                       445000000 500000000 1 2
+                                                                       400000000 450000000 1 3>;
+                                };
+                                plladiv: plladivck {
+                                        compatible = "atmel,at91sam9x5-clk-plldiv";
+                                        #clock-cells = <0>;
+                                        clocks = <&plla>;
+                                };
+                                utmi: utmick {
+                                        compatible = "atmel,at91sam9x5-clk-utmi";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_LOCKU>;
+                                        clocks = <&main>;
+                                };
+                                mck: masterck {
+                                        compatible = "atmel,at91sam9x5-clk-master";
+                                        #clock-cells = <0>;
+                                        interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
+                                        atmel,clk-output-range = <0 133333333>;
+                                        atmel,clk-divisors = <1 2 4 3>;
+                                        atmel,master-clk-have-div3-pres;
+                                };
+                                usb: usbck {
+                                        compatible = "atmel,at91sam9x5-clk-usb";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+                                prog: progck {
+                                        compatible = "atmel,at91sam9x5-clk-programmable";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
+                                        prog0: prog0 {
+                                                #clock-cells = <0>;
+                                                reg = <0>;
+                                                interrupts = <AT91_PMC_PCKRDY(0)>;
+                                        };
+                                        prog1: prog1 {
+                                                #clock-cells = <0>;
+                                                reg = <1>;
+                                                interrupts = <AT91_PMC_PCKRDY(1)>;
+                                        };
+                                };
+                                smd: smdclk {
+                                        compatible = "atmel,at91sam9x5-clk-smd";
+                                        #clock-cells = <0>;
+                                        clocks = <&plladiv>, <&utmi>;
+                                };
+                                systemck {
+                                        compatible = "atmel,at91rm9200-clk-system";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        ddrck: ddrck {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                                clocks = <&mck>;
+                                        };
+                                        smdck: smdck {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                                clocks = <&smd>;
+                                        };
+                                        uhpck: uhpck {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                                clocks = <&usb>;
+                                        };
+                                        udpck: udpck {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                                clocks = <&usb>;
+                                        };
+                                        pck0: pck0 {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                                clocks = <&prog0>;
+                                        };
+                                        pck1: pck1 {
+                                                #clock-cells = <0>;
+                                                reg = <9>;
+                                                clocks = <&prog1>;
+                                        };
+                                };
+                                periphck {
+                                        compatible = "atmel,at91sam9x5-clk-peripheral";
+                                        #address-cells = <1>;
+                                        #size-cells = <0>;
+                                        clocks = <&mck>;
+                                        pioAB_clk: pioAB_clk {
+                                                #clock-cells = <0>;
+                                                reg = <2>;
+                                        };
+                                        pioCD_clk: pioCD_clk {
+                                                #clock-cells = <0>;
+                                                reg = <3>;
+                                        };
+                                        smd_clk: smd_clk {
+                                                #clock-cells = <0>;
+                                                reg = <4>;
+                                        };
+                                        usart0_clk: usart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <5>;
+                                        };
+                                        usart1_clk: usart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <6>;
+                                        };
+                                        usart2_clk: usart2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <7>;
+                                        };
+                                        twi0_clk: twi0_clk {
+                                                reg = <9>;
+                                                #clock-cells = <0>;
+                                        };
+                                        twi1_clk: twi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <10>;
+                                        };
+                                        twi2_clk: twi2_clk {
+                                                #clock-cells = <0>;
+                                                reg = <11>;
+                                        };
+                                        mci0_clk: mci0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <12>;
+                                        };
+                                        spi0_clk: spi0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <13>;
+                                        };
+                                        spi1_clk: spi1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <14>;
+                                        };
+                                        uart0_clk: uart0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <15>;
+                                        };
+                                        uart1_clk: uart1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <16>;
+                                        };
+                                        tcb0_clk: tcb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <17>;
+                                        };
+                                        pwm_clk: pwm_clk {
+                                                #clock-cells = <0>;
+                                                reg = <18>;
+                                        };
+                                        adc_clk: adc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <19>;
+                                        };
+                                        dma0_clk: dma0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <20>;
+                                        };
+                                        dma1_clk: dma1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <21>;
+                                        };
+                                        uhphs_clk: uhphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <22>;
+                                        };
+                                        udphs_clk: udphs_clk {
+                                                #clock-cells = <0>;
+                                                reg = <23>;
+                                        };
+                                        mci1_clk: mci1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <26>;
+                                        };
+                                        ssc0_clk: ssc0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <28>;
+                                        };
+                                };
                        };
                        rstc@fffffe00 {
@@ -95,18 +378,47 @@
                                compatible = "atmel,at91sam9260-pit";
                                reg = <0xfffffe30 0xf>;
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
+                                clocks = <&mck>;
+                        };
+                        sckc@fffffe50 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfffffe50 0x4>;
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_xtal>;
+                                };
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                };
+                                clk32k: slck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc>, <&slow_osc>;
+                                };
                        };
                        tcb0: timer@f8008000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf8008000 0x100>;
                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb0_clk>;
+                                clock-names = "t0_clk";
                        };
                        tcb1: timer@f800c000 {
                                compatible = "atmel,at91sam9x5-tcb";
                                reg = <0xf800c000 0x100>;
                                interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&tcb0_clk>;
+                                clock-names = "t0_clk";
                        };
                        dma0: dma-controller@ffffec00 {
@@ -114,6 +426,8 @@
                                reg = <0xffffec00 0x200>;
                                interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
+                                clocks = <&dma0_clk>;
+                                clock-names = "dma_clk";
                        };
                        dma1: dma-controller@ffffee00 {
@@ -121,6 +435,8 @@
                                reg = <0xffffee00 0x200>;
                                interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
                                #dma-cells = <2>;
+                                clocks = <&dma1_clk>;
+                                clock-names = "dma_clk";
                        };
                        pinctrl@fffff400 {
@@ -453,6 +769,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioAB_clk>;
                                };
                                pioB: gpio@fffff600 {
@@ -464,6 +781,7 @@
                                        #gpio-lines = <19>;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioAB_clk>;
                                };
                                pioC: gpio@fffff800 {
@@ -474,6 +792,7 @@
                                        gpio-controller;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioCD_clk>;
                                };
                                pioD: gpio@fffffa00 {
@@ -485,6 +804,7 @@
                                        #gpio-lines = <22>;
                                        interrupt-controller;
                                        #interrupt-cells = <2>;
+                                        clocks = <&pioCD_clk>;
                                };
                        };
@@ -497,6 +817,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
+                                clocks = <&ssc0_clk>;
+                                clock-names = "pclk";
                                status = "disabled";
                        };
@@ -507,6 +829,8 @@
                                dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                pinctrl-names = "default";
+                                clocks = <&mci0_clk>;
+                                clock-names = "mci_clk";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -519,6 +843,8 @@
                                dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(0)>;
                                dma-names = "rxtx";
                                pinctrl-names = "default";
+                                clocks = <&mci1_clk>;
+                                clock-names = "mci_clk";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                status = "disabled";
@@ -530,6 +856,8 @@
                                interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_dbgu>;
+                                clocks = <&mck>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -539,6 +867,8 @@
                                interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart0>;
+                                clocks = <&usart0_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -548,6 +878,8 @@
                                interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart1>;
+                                clocks = <&usart1_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -557,6 +889,8 @@
                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart2>;
+                                clocks = <&usart2_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -571,6 +905,7 @@
                                #size-cells = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c0>;
+                                clocks = <&twi0_clk>;
                                status = "disabled";
                        };
@@ -585,6 +920,7 @@
                                #size-cells = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c1>;
+                                clocks = <&twi1_clk>;
                                status = "disabled";
                        };
@@ -599,6 +935,7 @@
                                #size-cells = <0>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_i2c2>;
+                                clocks = <&twi2_clk>;
                                status = "disabled";
                        };
@@ -608,6 +945,8 @@
                                interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_uart0>;
+                                clocks = <&uart0_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -617,6 +956,8 @@
                                interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_uart1>;
+                                clocks = <&uart1_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
@@ -626,6 +967,9 @@
                                compatible = "atmel,at91sam9260-adc";
                                reg = <0xf804c000 0x100>;
                                interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
+                                clocks = <&adc_clk>,
+                                         <&adc_op_clk>;
+                                clock-names = "adc_clk", "adc_op_clk";
                                atmel,adc-use-external-triggers;
                                atmel,adc-channels-used = <0xffff>;
                                atmel,adc-vref = <3300>;
@@ -673,6 +1017,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi0>;
+                                clocks = <&spi0_clk>;
+                                clock-names = "spi_clk";
                                status = "disabled";
                        };
@@ -687,6 +1033,8 @@
                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_spi1>;
+                                clocks = <&spi1_clk>;
+                                clock-names = "spi_clk";
                                status = "disabled";
                        };
@@ -805,6 +1153,9 @@
                        compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                        reg = <0x00600000 0x100000>;
                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>,
+                                 <&uhpck>;
+                        clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
                        status = "disabled";
                };
@@ -812,6 +1163,8 @@
                        compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                        reg = <0x00700000 0x100000>;
                        interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
+                        clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
+                        clock-names = "usb_clk", "ehci_clk", "uhpck";
                        status = "disabled";
                };
        };
diff --git a/arch/arm/boot/dts/at91sam9x5_can.dtsi b/arch/arm/boot/dts/at91sam9x5_can.dtsi
new file mode 100644
index 000000000000..f44ab7702a12
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_can.dtsi
@@ -0,0 +1,31 @@
+/*
+ * at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
+ * Ethernet interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+        ahb {
+                apb {
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        can0_clk: can0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <29>;
+                                        };
+                                        can1_clk: can1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <30>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_isi.dtsi b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
new file mode 100644
index 000000000000..98bc877a68ef
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_isi.dtsi
@@ -0,0 +1,26 @@
+/*
+ * at91sam9x5_isi.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
+ * Image Sensor Interface.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+        ahb {
+                apb {
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        isi_clk: isi_clk {
+                                                #clock-cells = <0>;
+                                                reg = <25>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_lcd.dtsi b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
new file mode 100644
index 000000000000..485302e8233d
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9x5_lcd.dtsi
@@ -0,0 +1,26 @@
+/*
+ * at91sam9x5_lcd.dtsi - Device Tree Include file for AT91SAM9x5 SoC with an
+ * LCD controller.
+ *
+ * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
+ *
+ * Licensed under GPLv2.
+ */
+#include <dt-bindings/pinctrl/at91.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+/ {
+        ahb {
+                apb {
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        lcdc_clk: lcdc_clk {
+                                                #clock-cells = <0>;
+                                                reg = <25>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
index 55731ffba764..57e89d1d0325 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb0.dtsi
@@ -43,12 +43,23 @@
                                };
                        };
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        macb0_clk: macb0_clk {
+                                                #clock-cells = <0>;
+                                                reg = <24>;
+                                        };
+                                };
+                        };
                        macb0: ethernet@f802c000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf802c000 0x100>;
                                interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb0_rmii>;
+                                clocks = <&macb0_clk>, <&macb0_clk>;
+                                clock-names = "hclk", "pclk";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
index 77425a627a94..663676c02861 100644
--- a/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_macb1.dtsi
@@ -31,12 +31,23 @@
                                };
                        };
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        macb1_clk: macb1_clk {
+                                                #clock-cells = <0>;
+                                                reg = <27>;
+                                        };
+                                };
+                        };
                        macb1: ethernet@f8030000 {
                                compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                reg = <0xf8030000 0x100>;
                                interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_macb1_rmii>;
+                                clocks = <&macb1_clk>, <&macb1_clk>;
+                                clock-names = "hclk", "pclk";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
index 6801106fa1f8..140217a54384 100644
--- a/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5_usart3.dtsi
@@ -42,12 +42,23 @@
                                };
                        };
+                        pmc: pmc@fffffc00 {
+                                periphck {
+                                        usart3_clk: usart3_clk {
+                                                #clock-cells = <0>;
+                                                reg = <8>;
+                                        };
+                                };
+                        };
                        usart3: serial@f8028000 {
                                compatible = "atmel,at91sam9260-usart";
                                reg = <0xf8028000 0x200>;
                                interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_usart3>;
+                                clocks = <&usart3_clk>;
+                                clock-names = "usart";
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 4a5ee5cc115a..8413e21192eb 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -23,6 +23,14 @@
                };
        };
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+        main_xtal {
+                clock-frequency = <12000000>;
+        };
        ahb {
                apb {
                        pinctrl@fffff400 {
diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi
index 9d72674049d6..bb22842a0826 100644
--- a/arch/arm/boot/dts/atlas6.dtsi
+++ b/arch/arm/boot/dts/atlas6.dtsi
@@ -39,6 +39,11 @@
                };
        };
+        arm-pmu {
+                compatible = "arm,cortex-a9-pmu";
+                interrupts = <29>;
+        };
        axi {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -167,6 +172,7 @@
                                compatible = "sirf,prima2-dspif";
                                reg = <0xa8000000 0x10000>;
                                interrupts = <9>;
+                                resets = <&rstc 1>;
                        };
                        gps@a8010000 {
@@ -174,6 +180,7 @@
                                reg = <0xa8010000 0x10000>;
                                interrupts = <7>;
                                clocks = <&clks 9>;
+                                resets = <&rstc 2>;
                        };
                        dsp@a9000000 {
@@ -181,6 +188,7 @@
                                reg = <0xa9000000 0x1000000>;
                                interrupts = <8>;
                                clocks = <&clks 8>;
+                                resets = <&rstc 0>;
                        };
                };
@@ -195,6 +203,7 @@
                                compatible = "sirf,prima2-tick";
                                reg = <0xb0020000 0x1000>;
                                interrupts = <0>;
+                                clocks = <&clks 11>;
                        };
                        nand@b0030000 {
@@ -297,9 +306,9 @@
                                reg = <0xb00d0000 0x10000>;
                                interrupts = <15>;
                                sirf,spi-num-chipselects = <1>;
-                                cs-gpios = <&gpio 0 0>;
+                                dmas = <&dmac1 9>,
-                                sirf,spi-dma-rx-channel = <25>;
+                                     <&dmac1 4>;
-                                sirf,spi-dma-tx-channel = <20>;
+                                dma-names = "rx", "tx";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 19>;
@@ -312,8 +321,9 @@
                                reg = <0xb0170000 0x10000>;
                                interrupts = <16>;
                                sirf,spi-num-chipselects = <1>;
-                                sirf,spi-dma-rx-channel = <12>;
+                                dmas = <&dmac0 12>,
-                                sirf,spi-dma-tx-channel = <13>;
+                                     <&dmac0 13>;
+                                dma-names = "rx", "tx";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 20>;
@@ -554,6 +564,18 @@
                                                sirf,function = "usp0_uart_nostreamctrl";
                                        };
                                };
+                                usp0_only_utfs_pins_a: usp0@2 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_utfs_grp";
+                                                sirf,function = "usp0_only_utfs";
+                                        };
+                                };
+                                usp0_only_urfs_pins_a: usp0@3 {
+                                        usp0 {
+                                                sirf,pins = "usp0_only_urfs_grp";
+                                                sirf,function = "usp0_only_urfs";
+                                        };
+                                };
                                usp1_pins_a: usp1@0 {
                                        usp1 {
                                                sirf,pins = "usp1grp";
diff --git a/arch/arm/boot/dts/axm5516-amarillo.dts b/arch/arm/boot/dts/axm5516-amarillo.dts
new file mode 100644
index 000000000000..a9d60471d9ff
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-amarillo.dts
@@ -0,0 +1,51 @@
+/*
+ * arch/arm/boot/dts/axm5516-amarillo.dts
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+/memreserve/ 0x00000000 0x00400000;
+#include "axm55xx.dtsi"
+#include "axm5516-cpus.dtsi"
+/ {
+        model = "Amarillo AXM5516";
+        compatible = "lsi,axm5516-amarillo", "lsi,axm5516";
+        memory {
+                device_type = "memory";
+                reg = <0 0x00000000 0x02 0x00000000>;
+        };
+};
+&serial0 {
+        status = "okay";
+};
+&serial1 {
+        status = "okay";
+};
+&serial2 {
+        status = "okay";
+};
+&serial3 {
+        status = "okay";
+};
+&gpio0 {
+        status = "okay";
+};
+&gpio1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/axm5516-cpus.dtsi b/arch/arm/boot/dts/axm5516-cpus.dtsi
new file mode 100644
index 000000000000..b85f360cb125
--- /dev/null
+++ b/arch/arm/boot/dts/axm5516-cpus.dtsi
@@ -0,0 +1,204 @@
+/*
+ * arch/arm/boot/dts/axm5516-cpus.dtsi
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/ {
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu-map {
+                        cluster0 {
+                                core0 {
+                                        cpu = <&CPU0>;
+                                };
+                                core1 {
+                                        cpu = <&CPU1>;
+                                };
+                                core2 {
+                                        cpu = <&CPU2>;
+                                };
+                                core3 {
+                                        cpu = <&CPU3>;
+                                };
+                        };
+                        cluster1 {
+                                core0 {
+                                        cpu = <&CPU4>;
+                                };
+                                core1 {
+                                        cpu = <&CPU5>;
+                                };
+                                core2 {
+                                        cpu = <&CPU6>;
+                                };
+                                core3 {
+                                        cpu = <&CPU7>;
+                                };
+                        };
+                        cluster2 {
+                                core0 {
+                                        cpu = <&CPU8>;
+                                };
+                                core1 {
+                                        cpu = <&CPU9>;
+                                };
+                                core2 {
+                                        cpu = <&CPU10>;
+                                };
+                                core3 {
+                                        cpu = <&CPU11>;
+                                };
+                        };
+                        cluster3 {
+                                core0 {
+                                        cpu = <&CPU12>;
+                                };
+                                core1 {
+                                        cpu = <&CPU13>;
+                                };
+                                core2 {
+                                        cpu = <&CPU14>;
+                                };
+                                core3 {
+                                        cpu = <&CPU15>;
+                                };
+                        };
+                };
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x00>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x01>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x02>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x03>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU4: cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x100>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU5: cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x101>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU6: cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x102>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU7: cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x103>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU8: cpu@200 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x200>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU9: cpu@201 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x201>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU10: cpu@202 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x202>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU11: cpu@203 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x203>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU12: cpu@300 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x300>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU13: cpu@301 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x301>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU14: cpu@302 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x302>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+                CPU15: cpu@303 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x303>;
+                        clock-frequency= <1400000000>;
+                        cpu-release-addr = <0>; // Fixed by the boot loader
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi
new file mode 100644
index 000000000000..ea288f0a1d39
--- /dev/null
+++ b/arch/arm/boot/dts/axm55xx.dtsi
@@ -0,0 +1,204 @@
+/*
+ * arch/arm/boot/dts/axm55xx.dtsi
+ *
+ * Copyright (C) 2013 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/lsi,axm5516-clks.h>
+#include "skeleton64.dtsi"
+/ {
+        interrupt-parent = <&gic>;
+        aliases {
+                serial0   = &serial0;
+                serial1   = &serial1;
+                serial2   = &serial2;
+                serial3   = &serial3;
+                timer     = &timer0;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+                clk_ref0: clk_ref0 {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <125000000>;
+                };
+                clk_ref1: clk_ref1 {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <125000000>;
+                };
+                clk_ref2: clk_ref2 {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <125000000>;
+                };
+                clks: clock-controller@2010020000 {
+                        compatible = "lsi,axm5516-clks";
+                        #clock-cells = <1>;
+                        reg = <0x20 0x10020000 0 0x20000>;
+                };
+        };
+        gic: interrupt-controller@2001001000 {
+                compatible = "arm,cortex-a15-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0x20 0x01001000 0 0x1000>,
+                      <0x20 0x01002000 0 0x1000>,
+                      <0x20 0x01004000 0 0x2000>,
+                      <0x20 0x01006000 0 0x2000>;
+                interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
+                                IRQ_TYPE_LEVEL_HIGH)>;
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts =
+                        <GIC_PPI 13
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 14
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 11
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                        <GIC_PPI 10
+                                (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+        };
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+        };
+        soc {
+                compatible = "simple-bus";
+                device_type = "soc";
+                #address-cells = <2>;
+                #size-cells = <2>;
+                interrupt-parent = <&gic>;
+                ranges;
+                syscon: syscon@2010030000 {
+                        compatible = "lsi,axxia-syscon", "syscon";
+                        reg = <0x20 0x10030000 0 0x2000>;
+                };
+                reset: reset@2010031000 {
+                        compatible = "lsi,axm55xx-reset";
+                        syscon = <&syscon>;
+                };
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <2>;
+                        #size-cells = <2>;
+                        ranges;
+                        serial0: uart@2010080000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x20 0x10080000 0 0x1000>;
+                                interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                        serial1: uart@2010081000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x20 0x10081000 0 0x1000>;
+                                interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                        serial2: uart@2010082000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x20 0x10082000 0 0x1000>;
+                                interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                        serial3: uart@2010083000 {
+                                compatible = "arm,pl011", "arm,primecell";
+                                reg = <0x20 0x10083000 0 0x1000>;
+                                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                        timer0: timer@2010091000 {
+                                compatible = "arm,sp804", "arm,primecell";
+                                reg = <0x20 0x10091000 0 0x1000>;
+                                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "okay";
+                        };
+                        gpio0: gpio@2010092000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0x20 0x10092000 0x00 0x1000>;
+                                interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+                                             <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                        gpio1: gpio@2010093000 {
+                                #gpio-cells = <2>;
+                                compatible = "arm,pl061", "arm,primecell";
+                                gpio-controller;
+                                reg = <0x20 0x10093000 0x00 0x1000>;
+                                interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks AXXIA_CLK_PER>;
+                                clock-names = "apb_pclk";
+                                status = "disabled";
+                        };
+                };
+        };
+};
+/*
+  Local Variables:
+  mode: C
+  End:
+*/
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 64d069bcc409..6b05ae6d476f 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -193,6 +193,14 @@
                status = "disabled";
        };
+        pwm: pwm@3e01a000 {
+                compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
+                reg = <0x3e01a000 0xcc>;
+                clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
+                #pwm-cells = <3>;
+                status = "disabled";
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 08a44d41b672..8b366822bb43 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -14,6 +14,8 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include "dt-bindings/clock/bcm21664.h"
 #include "skeleton.dtsi"
 / {
@@ -43,7 +45,7 @@
                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e000000 0x118>;
-                clocks = <&uartb_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
                interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -53,7 +55,7 @@
                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e001000 0x118>;
-                clocks = <&uartb2_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
                interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -63,7 +65,7 @@
                compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
                status = "disabled";
                reg = <0x3e002000 0x118>;
-                clocks = <&uartb3_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
                reg-shift = <2>;
                reg-io-width = <4>;
@@ -85,7 +87,7 @@
                compatible = "brcm,kona-timer";
                reg = <0x35006000 0x1c>;
                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&hub_timer_clk>;
+                clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
        };
        gpio: gpio@35003000 {
@@ -106,7 +108,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f180000 0x801c>;
                interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio1_clk>;
+                clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
                status = "disabled";
        };
@@ -114,7 +116,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f190000 0x801c>;
                interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio2_clk>;
+                clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
                status = "disabled";
        };
@@ -122,7 +124,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f1a0000 0x801c>;
                interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio3_clk>;
+                clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
                status = "disabled";
        };
@@ -130,7 +132,7 @@
                compatible = "brcm,kona-sdhci";
                reg = <0x3f1b0000 0x801c>;
                interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
-                clocks = <&sdio4_clk>;
+                clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
                status = "disabled";
        };
@@ -140,7 +142,7 @@
                interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc1_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
                status = "disabled";
        };
@@ -150,7 +152,7 @@
                interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc2_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
                status = "disabled";
        };
@@ -160,7 +162,7 @@
                interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc3_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
                status = "disabled";
        };
@@ -170,105 +172,149 @@
                interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
                #address-cells = <1>;
                #size-cells = <0>;
-                clocks = <&bsc4_clk>;
+                clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
                status = "disabled";
        };
        clocks {
-                bsc1_clk: bsc1 {
+                #address-cells = <1>;
-                        compatible = "fixed-clock";
+                #size-cells = <1>;
-                        clock-frequency = <13000000>;
+                ranges;
-                        #clock-cells = <0>;
-                };
-                bsc2_clk: bsc2 {
+                /*
-                        compatible = "fixed-clock";
+                 * Fixed clocks are defined before CCUs whose
-                        clock-frequency = <13000000>;
+                 * clocks may depend on them.
+                 */
+                ref_32k_clk: ref_32k {
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
                };
-                bsc3_clk: bsc3 {
+                bbl_32k_clk: bbl_32k {
-                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <32768>;
                };
-                bsc4_clk: bsc4 {
+                ref_13m_clk: ref_13m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <13000000>;
-                        #clock-cells = <0>;
                };
-                pmu_bsc_clk: pmu_bsc {
+                var_13m_clk: var_13m {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <13000000>;
-                        #clock-cells = <0>;
                };
-                hub_timer_clk: hub_timer {
+                dft_19_5m_clk: dft_19_5m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <32768>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <19500000>;
                };
-                pwm_clk: pwm {
+                ref_crystal_clk: ref_crystal {
+                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <26000000>;
-                        #clock-cells = <0>;
                };
-                sdio1_clk: sdio1 {
+                ref_52m_clk: ref_52m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
                };
-                sdio2_clk: sdio2 {
+                var_52m_clk: var_52m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
                };
-                sdio3_clk: sdio3 {
+                usb_otg_ahb_clk: usb_otg_ahb {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <52000000>;
                };
-                sdio4_clk: sdio4 {
+                ref_96m_clk: ref_96m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <48000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
                };
-                tmon_1m_clk: tmon_1m {
+                var_96m_clk: var_96m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <1000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <96000000>;
                };
-                uartb_clk: uartb {
+                ref_104m_clk: ref_104m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <104000000>;
                };
-                uartb2_clk: uartb2 {
+                var_104m_clk: var_104m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <104000000>;
                };
-                uartb3_clk: uartb3 {
+                ref_156m_clk: ref_156m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <13000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <156000000>;
                };
-                usb_otg_ahb_clk: usb_otg_ahb {
+                var_156m_clk: var_156m {
-                        compatible = "fixed-clock";
-                        clock-frequency = <52000000>;
                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <156000000>;
+                };
+                root_ccu: root_ccu {
+                        compatible = BCM21664_DT_ROOT_CCU_COMPAT;
+                        reg = <0x35001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "frac_1m";
+                };
+                aon_ccu: aon_ccu {
+                        compatible = BCM21664_DT_AON_CCU_COMPAT;
+                        reg = <0x35002000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "hub_timer";
+                };
+                master_ccu: master_ccu {
+                        compatible = BCM21664_DT_MASTER_CCU_COMPAT;
+                        reg = <0x3f001000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "sdio1",
+                                             "sdio2",
+                                             "sdio3",
+                                             "sdio4",
+                                             "sdio1_sleep",
+                                             "sdio2_sleep",
+                                             "sdio3_sleep",
+                                             "sdio4_sleep";
+                };
+                slave_ccu: slave_ccu {
+                        compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
+                        reg = <0x3e011000 0x0f00>;
+                        #clock-cells = <1>;
+                        clock-output-names = "uartb",
+                                             "uartb2",
+                                             "uartb3",
+                                             "bsc1",
+                                             "bsc2",
+                                             "bsc3",
+                                             "bsc4";
                };
        };
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
index af3da55eef49..9ce91dd60cb6 100644
--- a/arch/arm/boot/dts/bcm28155-ap.dts
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -69,6 +69,10 @@
                status = "okay";
        };
+        pwm: pwm@3e01a000 {
+                status = "okay";
+        };
        usbotg: usb@3f120000 {
                vusb_d-supply = <&usbldo_reg>;
                vusb_a-supply = <&iosr1_reg>;
diff --git a/arch/arm/boot/dts/bcm59056.dtsi b/arch/arm/boot/dts/bcm59056.dtsi
index dfadaaa89b05..066adfb10bd5 100644
--- a/arch/arm/boot/dts/bcm59056.dtsi
+++ b/arch/arm/boot/dts/bcm59056.dtsi
@@ -70,5 +70,26 @@
                vsr_reg: vsr {
                };
+                gpldo1_reg: gpldo1 {
+                };
+                gpldo2_reg: gpldo2 {
+                };
+                gpldo3_reg: gpldo3 {
+                };
+                gpldo4_reg: gpldo4 {
+                };
+                gpldo5_reg: gpldo5 {
+                };
+                gpldo6_reg: gpldo6 {
+                };
+                vbus_reg: vbus {
+                };
        };
 };
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 56a1af2f1052..2477dac4d643 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -12,6 +12,7 @@
 */
 #include "skeleton.dtsi"
+#include <dt-bindings/clock/berlin2.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
@@ -37,24 +38,10 @@
                };
        };
-        clocks {
+        refclk: oscillator {
-                smclk: sysmgr-clock {
+                compatible = "fixed-clock";
-                        compatible = "fixed-clock";
+                #clock-cells = <0>;
-                        #clock-cells = <0>;
+                clock-frequency = <25000000>;
-                        clock-frequency = <25000000>;
-                };
-                cfgclk: cfg-clock {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <100000000>;
-                };
-                sysclk: system-clock {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <400000000>;
-                };
        };
        soc {
@@ -72,6 +59,11 @@
                        cache-level = <2>;
                };
+                scu: snoop-control-unit@ad0000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0xad0000 0x58>;
+                };
                gic: interrupt-controller@ad1000 {
                        compatible = "arm,cortex-a9-gic";
                        reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
@@ -83,7 +75,7 @@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&sysclk>;
+                        clocks = <&chip CLKID_TWD>;
                };
                apb@e80000 {
@@ -94,11 +86,83 @@
                        ranges = <0 0xe80000 0x10000>;
                        interrupt-parent = <&aic>;
+                        gpio0: gpio@0400 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0400 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porta: gpio-port@0 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <0>;
+                                };
+                        };
+                        gpio1: gpio@0800 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0800 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portb: gpio-port@1 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <1>;
+                                };
+                        };
+                        gpio2: gpio@0c00 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0c00 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portc: gpio-port@2 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <2>;
+                                };
+                        };
+                        gpio3: gpio@1000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x1000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portd: gpio-port@3 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <3>;
+                                };
+                        };
                        timer0: timer@2c00 {
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c00 0x14>;
                                interrupts = <8>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "okay";
                        };
@@ -107,7 +171,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c14 0x14>;
                                interrupts = <9>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "okay";
                        };
@@ -116,7 +180,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c28 0x14>;
                                interrupts = <10>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -125,7 +189,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c3c 0x14>;
                                interrupts = <11>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -134,7 +198,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c50 0x14>;
                                interrupts = <12>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -143,7 +207,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c64 0x14>;
                                interrupts = <13>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -152,7 +216,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c78 0x14>;
                                interrupts = <14>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -161,7 +225,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c8c 0x14>;
                                interrupts = <15>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -176,6 +240,14 @@
                        };
                };
+                chip: chip-control@ea0000 {
+                        compatible = "marvell,berlin2-chip-ctrl";
+                        #clock-cells = <1>;
+                        reg = <0xea0000 0x400>;
+                        clocks = <&refclk>;
+                        clock-names = "refclk";
+                };
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
@@ -184,13 +256,48 @@
                        ranges = <0 0xfc0000 0x10000>;
                        interrupt-parent = <&sic>;
+                        sm_gpio1: gpio@5000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x5000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portf: gpio-port@5 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                };
+                        };
+                        sm_gpio0: gpio@c000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0xc000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porte: gpio-port@4 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <11>;
+                                };
+                        };
                        uart0: serial@9000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x9000 0x100>;
                                reg-shift = <2>;
                                reg-io-width = <1>;
                                interrupts = <8>;
-                                clocks = <&smclk>;
+                                clocks = <&refclk>;
+                                pinctrl-0 = <&uart0_pmux>;
+                                pinctrl-names = "default";
                                status = "disabled";
                        };
@@ -200,7 +307,9 @@
                                reg-shift = <2>;
                                reg-io-width = <1>;
                                interrupts = <9>;
-                                clocks = <&smclk>;
+                                clocks = <&refclk>;
+                                pinctrl-0 = <&uart1_pmux>;
+                                pinctrl-names = "default";
                                status = "disabled";
                        };
@@ -210,10 +319,32 @@
                                reg-shift = <2>;
                                reg-io-width = <1>;
                                interrupts = <10>;
-                                clocks = <&smclk>;
+                                clocks = <&refclk>;
+                                pinctrl-0 = <&uart2_pmux>;
+                                pinctrl-names = "default";
                                status = "disabled";
                        };
+                        sysctrl: system-controller@d000 {
+                                compatible = "marvell,berlin2-system-ctrl";
+                                reg = <0xd000 0x100>;
+                                uart0_pmux: uart0-pmux {
+                                        groups = "GSM4";
+                                        function = "uart0";
+                                };
+                                uart1_pmux: uart1-pmux {
+                                        groups = "GSM5";
+                                        function = "uart1";
+                                };
+                                uart2_pmux: uart2-pmux {
+                                        groups = "GSM3";
+                                        function = "uart2";
+                                };
+                        };
                        sic: interrupt-controller@e000 {
                                compatible = "snps,dw-apb-ictl";
                                reg = <0xe000 0x400>;
diff --git a/arch/arm/boot/dts/berlin2cd.dtsi b/arch/arm/boot/dts/berlin2cd.dtsi
index 094968c27533..cc1df65da504 100644
--- a/arch/arm/boot/dts/berlin2cd.dtsi
+++ b/arch/arm/boot/dts/berlin2cd.dtsi
@@ -12,6 +12,7 @@
 */
 #include "skeleton.dtsi"
+#include <dt-bindings/clock/berlin2.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 / {
@@ -30,24 +31,10 @@
                };
        };
-        clocks {
+        refclk: oscillator {
-                smclk: sysmgr-clock {
+                compatible = "fixed-clock";
-                        compatible = "fixed-clock";
+                #clock-cells = <0>;
-                        #clock-cells = <0>;
+                clock-frequency = <25000000>;
-                        clock-frequency = <25000000>;
-                };
-                cfgclk: cfg-clock {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <75000000>;
-                };
-                sysclk: system-clock {
-                        compatible = "fixed-clock";
-                        #clock-cells = <0>;
-                        clock-frequency = <300000000>;
-                };
        };
        soc {
@@ -76,7 +63,7 @@
                        compatible = "arm,cortex-a9-twd-timer";
                        reg = <0xad0600 0x20>;
                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&sysclk>;
+                        clocks = <&chip CLKID_TWD>;
                };
                apb@e80000 {
@@ -87,11 +74,83 @@
                        ranges = <0 0xe80000 0x10000>;
                        interrupt-parent = <&aic>;
+                        gpio0: gpio@0400 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0400 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porta: gpio-port@0 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <0>;
+                                };
+                        };
+                        gpio1: gpio@0800 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0800 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portb: gpio-port@1 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <1>;
+                                };
+                        };
+                        gpio2: gpio@0c00 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0c00 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portc: gpio-port@2 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <2>;
+                                };
+                        };
+                        gpio3: gpio@1000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x1000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portd: gpio-port@3 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <3>;
+                                };
+                        };
                        timer0: timer@2c00 {
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c00 0x14>;
                                interrupts = <8>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "okay";
                        };
@@ -100,7 +159,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c14 0x14>;
                                interrupts = <9>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "okay";
                        };
@@ -109,7 +168,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c28 0x14>;
                                interrupts = <10>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -118,7 +177,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c3c 0x14>;
                                interrupts = <11>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -127,7 +186,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c50 0x14>;
                                interrupts = <12>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -136,7 +195,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c64 0x14>;
                                interrupts = <13>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -145,7 +204,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c78 0x14>;
                                interrupts = <14>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -154,7 +213,7 @@
                                compatible = "snps,dw-apb-timer";
                                reg = <0x2c8c 0x14>;
                                interrupts = <15>;
-                                clocks = <&cfgclk>;
+                                clocks = <&chip CLKID_CFG>;
                                clock-names = "timer";
                                status = "disabled";
                        };
@@ -169,6 +228,19 @@
                        };
                };
+                chip: chip-control@ea0000 {
+                        compatible = "marvell,berlin2cd-chip-ctrl";
+                        #clock-cells = <1>;
+                        reg = <0xea0000 0x400>;
+                        clocks = <&refclk>;
+                        clock-names = "refclk";
+                        uart0_pmux: uart0-pmux {
+                                groups = "G6";
+                                function = "uart0";
+                        };
+                };
                apb@fc0000 {
                        compatible = "simple-bus";
                        #address-cells = <1>;
@@ -177,13 +249,45 @@
                        ranges = <0 0xfc0000 0x10000>;
                        interrupt-parent = <&sic>;
+                        sm_gpio1: gpio@5000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x5000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portf: gpio-port@5 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                };
+                        };
+                        sm_gpio0: gpio@c000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0xc000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porte: gpio-port@4 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <8>;
+                                        reg = <0>;
+                                };
+                        };
                        uart0: serial@9000 {
                                compatible = "snps,dw-apb-uart";
                                reg = <0x9000 0x100>;
                                reg-shift = <2>;
                                reg-io-width = <1>;
                                interrupts = <8>;
-                                clocks = <&smclk>;
+                                clocks = <&refclk>;
+                                pinctrl-0 = <&uart0_pmux>;
+                                pinctrl-names = "default";
                                status = "disabled";
                        };
@@ -193,10 +297,15 @@
                                reg-shift = <2>;
                                reg-io-width = <1>;
                                interrupts = <9>;
-                                clocks = <&smclk>;
+                                clocks = <&refclk>;
                                status = "disabled";
                        };
+                        sysctrl: system-controller@d000 {
+                                compatible = "marvell,berlin2cd-system-ctrl";
+                                reg = <0xd000 0x100>;
+                        };
                        sic: interrupt-controller@e000 {
                                compatible = "snps,dw-apb-ictl";
                                reg = <0xe000 0x400>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
new file mode 100644
index 000000000000..995150f93795
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include "berlin2q.dtsi"
+/ {
+        model = "Marvell BG2-Q DMP";
+        compatible = "marvell,berlin2q-dmp", "marvell,berlin2q", "marvell,berlin";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x80000000>;
+        };
+        choosen {
+                bootargs = "console=ttyS0,115200 earlyprintk";
+        };
+};
+&sdhci1 {
+        broken-cd;
+        sdhci,wp-inverted;
+        status = "okay";
+};
+&sdhci2 {
+        non-removable;
+        status = "okay";
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
new file mode 100644
index 000000000000..635a16a64cb4
--- /dev/null
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -0,0 +1,363 @@
+/*
+ * Copyright (C) 2014 Antoine Ténart <antoine.tenart@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <dt-bindings/clock/berlin2q.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include "skeleton.dtsi"
+/ {
+        model = "Marvell Armada 1500 pro (BG2-Q) SoC";
+        compatible = "marvell,berlin2q", "marvell,berlin";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <0>;
+                };
+                cpu@1 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <1>;
+                };
+                cpu@2 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <2>;
+                };
+                cpu@3 {
+                        compatible = "arm,cortex-a9";
+                        device_type = "cpu";
+                        next-level-cache = <&l2>;
+                        reg = <3>;
+                };
+        };
+        refclk: oscillator {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <25000000>;
+        };
+        soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0xf7000000 0x1000000>;
+                interrupt-parent = <&gic>;
+                sdhci0: sdhci@ab0000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0000 0x200>;
+                        clocks = <&chip CLKID_SDIO1XIN>;
+                        interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                sdhci1: sdhci@ab0800 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab0800 0x200>;
+                        clocks = <&chip CLKID_SDIO1XIN>;
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        status = "disabled";
+                };
+                sdhci2: sdhci@ab1000 {
+                        compatible = "mrvl,pxav3-mmc";
+                        reg = <0xab1000 0x200>;
+                        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&chip CLKID_SDIO1XIN>;
+                        status = "disabled";
+                };
+                l2: l2-cache-controller@ac0000 {
+                        compatible = "arm,pl310-cache";
+                        reg = <0xac0000 0x1000>;
+                        cache-level = <2>;
+                };
+                scu: snoop-control-unit@ad0000 {
+                        compatible = "arm,cortex-a9-scu";
+                        reg = <0xad0000 0x58>;
+                };
+                local-timer@ad0600 {
+                        compatible = "arm,cortex-a9-twd-timer";
+                        reg = <0xad0600 0x20>;
+                        clocks = <&chip CLKID_TWD>;
+                        interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>;
+                };
+                gic: interrupt-controller@ad1000 {
+                        compatible = "arm,cortex-a9-gic";
+                        reg = <0xad1000 0x1000>, <0xad0100 0x100>;
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                };
+                apb@e80000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0xe80000 0x10000>;
+                        interrupt-parent = <&aic>;
+                        gpio0: gpio@0400 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0400 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porta: gpio-port@0 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <0>;
+                                };
+                        };
+                        gpio1: gpio@0800 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0800 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portb: gpio-port@1 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <1>;
+                                };
+                        };
+                        gpio2: gpio@0c00 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x0c00 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portc: gpio-port@2 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <2>;
+                                };
+                        };
+                        gpio3: gpio@1000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x1000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portd: gpio-port@3 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                        interrupt-controller;
+                                        #interrupt-cells = <2>;
+                                        interrupts = <3>;
+                                };
+                        };
+                        timer0: timer@2c00 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c00 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                interrupts = <8>;
+                        };
+                        timer1: timer@2c14 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c14 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer2: timer@2c28 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c28 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer3: timer@2c3c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c3c 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer4: timer@2c50 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c50 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer5: timer@2c64 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c64 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer6: timer@2c78 {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c78 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        timer7: timer@2c8c {
+                                compatible = "snps,dw-apb-timer";
+                                reg = <0x2c8c 0x14>;
+                                clocks = <&chip CLKID_CFG>;
+                                clock-names = "timer";
+                                status = "disabled";
+                        };
+                        aic: interrupt-controller@3800 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0x3800 0x30>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                        gpio4: gpio@5000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0x5000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                porte: gpio-port@4 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                };
+                        };
+                        gpio5: gpio@c000 {
+                                compatible = "snps,dw-apb-gpio";
+                                reg = <0xc000 0x400>;
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                portf: gpio-port@5 {
+                                        compatible = "snps,dw-apb-gpio-port";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        snps,nr-gpios = <32>;
+                                        reg = <0>;
+                                };
+                        };
+                };
+                chip: chip-control@ea0000 {
+                        compatible = "marvell,berlin2q-chip-ctrl";
+                        #clock-cells = <1>;
+                        reg = <0xea0000 0x400>, <0xdd0170 0x10>;
+                        clocks = <&refclk>;
+                        clock-names = "refclk";
+                };
+                apb@fc0000 {
+                        compatible = "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0xfc0000 0x10000>;
+                        interrupt-parent = <&sic>;
+                        uart0: uart@9000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0x9000 0x100>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <8>;
+                                clocks = <&refclk>;
+                                reg-shift = <2>;
+                                pinctrl-0 = <&uart0_pmux>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+                        uart1: uart@a000 {
+                                compatible = "snps,dw-apb-uart";
+                                reg = <0xa000 0x100>;
+                                interrupt-parent = <&sic>;
+                                interrupts = <9>;
+                                clocks = <&refclk>;
+                                reg-shift = <2>;
+                                pinctrl-0 = <&uart1_pmux>;
+                                pinctrl-names = "default";
+                                status = "disabled";
+                        };
+                        sysctrl: pin-controller@d000 {
+                                compatible = "marvell,berlin2q-system-ctrl";
+                                reg = <0xd000 0x100>;
+                                uart0_pmux: uart0-pmux {
+                                        groups = "GSM12";
+                                        function = "uart0";
+                                };
+                                uart1_pmux: uart1-pmux {
+                                        groups = "GSM14";
+                                        function = "uart1";
+                                };
+                        };
+                        sic: interrupt-controller@e000 {
+                                compatible = "snps,dw-apb-ictl";
+                                reg = <0xe000 0x30>;
+                                interrupt-controller;
+                                #interrupt-cells = <1>;
+                                interrupt-parent = <&gic>;
+                                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 5babba0a3a75..4adc28039c30 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -7,11 +7,11 @@
 */
 /dts-v1/;
-#include "dra7.dtsi"
+#include "dra74x.dtsi"
 / {
-        model = "TI DRA7";
+        model = "TI DRA742";
-        compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
+        compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
        memory {
                device_type = "memory";
@@ -93,6 +93,64 @@
                        0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
                >;
        };
+        qspi1_pins: pinmux_qspi1_pins {
+                pinctrl-single,pins = <
+                        0x4c (PIN_INPUT | MUX_MODE1)  /* gpmc_a3.qspi1_cs2 */
+                        0x50 (PIN_INPUT | MUX_MODE1)  /* gpmc_a4.qspi1_cs3 */
+                        0x74 (PIN_INPUT | MUX_MODE1)  /* gpmc_a13.qspi1_rtclk */
+                        0x78 (PIN_INPUT | MUX_MODE1)  /* gpmc_a14.qspi1_d3 */
+                        0x7c (PIN_INPUT | MUX_MODE1)  /* gpmc_a15.qspi1_d2 */
+                        0x80 (PIN_INPUT | MUX_MODE1) /* gpmc_a16.qspi1_d1 */
+                        0x84 (PIN_INPUT | MUX_MODE1)  /* gpmc_a17.qspi1_d0 */
+                        0x88 (PIN_INPUT | MUX_MODE1)  /* qpmc_a18.qspi1_sclk */
+                        0xb8 (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs2.qspi1_cs0 */
+                        0xbc (PIN_INPUT_PULLUP | MUX_MODE1)  /* gpmc_cs3.qspi1_cs1 */
+                >;
+        };
+        usb1_pins: pinmux_usb1_pins {
+                pinctrl-single,pins = <
+                        0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
+                >;
+        };
+        usb2_pins: pinmux_usb2_pins {
+                pinctrl-single,pins = <
+                        0x284 (PIN_INPUT_SLEW | MUX_MODE0) /* usb2_drvvbus */
+                >;
+        };
+        nand_flash_x16: nand_flash_x16 {
+                /* On DRA7 EVM, GPMC_WPN and NAND_BOOTn comes from DIP switch
+                 * So NAND flash requires following switch settings:
+                 * SW5.9 (GPMC_WPN) = LOW
+                 * SW5.1 (NAND_BOOTn) = HIGH */
+                pinctrl-single,pins = <
+                        0x0     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad0     */
+                        0x4     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad1     */
+                        0x8     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad2     */
+                        0xc     (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad3     */
+                        0x10    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad4     */
+                        0x14    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad5     */
+                        0x18    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad6     */
+                        0x1c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad7     */
+                        0x20    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad8     */
+                        0x24    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad9     */
+                        0x28    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad10    */
+                        0x2c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad11    */
+                        0x30    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad12    */
+                        0x34    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad13    */
+                        0x38    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad14    */
+                        0x3c    (PIN_INPUT  | MUX_MODE0)        /* gpmc_ad15    */
+                        0xd8    (PIN_INPUT_PULLUP  | MUX_MODE0) /* gpmc_wait0   */
+                        0xcc    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_wen     */
+                        0xb4    (PIN_OUTPUT_PULLUP | MUX_MODE0) /* gpmc_csn0    */
+                        0xc4    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_advn_ale */
+                        0xc8    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_oen_ren  */
+                        0xd0    (PIN_OUTPUT | MUX_MODE0)        /* gpmc_be0n_cle */
+                >;
+        };
 };
 &i2c1 {
@@ -273,3 +331,167 @@
 &cpu0 {
        cpu0-supply = <&smps123_reg>;
 };
+&qspi {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&qspi1_pins>;
+        spi-max-frequency = <48000000>;
+        m25p80@0 {
+                compatible = "s25fl256s1";
+                spi-max-frequency = <48000000>;
+                reg = <0>;
+                spi-tx-bus-width = <1>;
+                spi-rx-bus-width = <4>;
+                spi-cpol;
+                spi-cpha;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* MTD partition table.
+                 * The ROM checks the first four physical blocks
+                 * for a valid file to boot and the flash here is
+                 * 64KiB block size.
+                 */
+                partition@0 {
+                        label = "QSPI.SPL";
+                        reg = <0x00000000 0x000010000>;
+                };
+                partition@1 {
+                        label = "QSPI.SPL.backup1";
+                        reg = <0x00010000 0x00010000>;
+                };
+                partition@2 {
+                        label = "QSPI.SPL.backup2";
+                        reg = <0x00020000 0x00010000>;
+                };
+                partition@3 {
+                        label = "QSPI.SPL.backup3";
+                        reg = <0x00030000 0x00010000>;
+                };
+                partition@4 {
+                        label = "QSPI.u-boot";
+                        reg = <0x00040000 0x00100000>;
+                };
+                partition@5 {
+                        label = "QSPI.u-boot-spl-os";
+                        reg = <0x00140000 0x00010000>;
+                };
+                partition@6 {
+                        label = "QSPI.u-boot-env";
+                        reg = <0x00150000 0x00010000>;
+                };
+                partition@7 {
+                        label = "QSPI.u-boot-env.backup1";
+                        reg = <0x00160000 0x0010000>;
+                };
+                partition@8 {
+                        label = "QSPI.kernel";
+                        reg = <0x00170000 0x0800000>;
+                };
+                partition@9 {
+                        label = "QSPI.file-system";
+                        reg = <0x00970000 0x01690000>;
+                };
+        };
+};
+&usb1 {
+        dr_mode = "peripheral";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb1_pins>;
+};
+&usb2 {
+        dr_mode = "host";
+        pinctrl-names = "default";
+        pinctrl-0 = <&usb2_pins>;
+};
+&elm {
+        status = "okay";
+};
+&gpmc {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&nand_flash_x16>;
+        ranges = <0 0 0 0x01000000>;    /* minimum GPMC partition = 16MB */
+        nand@0,0 {
+                reg = <0 0 4>;          /* device IO registers */
+                ti,nand-ecc-opt = "bch8";
+                ti,elm-id = <&elm>;
+                nand-bus-width = <16>;
+                gpmc,device-width = <2>;
+                gpmc,sync-clk-ps = <0>;
+                gpmc,cs-on-ns = <0>;
+                gpmc,cs-rd-off-ns = <40>;
+                gpmc,cs-wr-off-ns = <40>;
+                gpmc,adv-on-ns = <0>;
+                gpmc,adv-rd-off-ns = <30>;
+                gpmc,adv-wr-off-ns = <30>;
+                gpmc,we-on-ns = <5>;
+                gpmc,we-off-ns = <25>;
+                gpmc,oe-on-ns = <2>;
+                gpmc,oe-off-ns = <20>;
+                gpmc,access-ns = <20>;
+                gpmc,wr-access-ns = <40>;
+                gpmc,rd-cycle-ns = <40>;
+                gpmc,wr-cycle-ns = <40>;
+                gpmc,wait-pin = <0>;
+                gpmc,wait-on-read;
+                gpmc,wait-on-write;
+                gpmc,bus-turnaround-ns = <0>;
+                gpmc,cycle2cycle-delay-ns = <0>;
+                gpmc,clk-activation-ns = <0>;
+                gpmc,wait-monitoring-ns = <0>;
+                gpmc,wr-data-mux-bus-ns = <0>;
+                /* MTD partition table */
+                /* All SPL-* partitions are sized to minimal length
+                 * which can be independently programmable. For
+                 * NAND flash this is equal to size of erase-block */
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "NAND.SPL";
+                        reg = <0x00000000 0x000020000>;
+                };
+                partition@1 {
+                        label = "NAND.SPL.backup1";
+                        reg = <0x00020000 0x00020000>;
+                };
+                partition@2 {
+                        label = "NAND.SPL.backup2";
+                        reg = <0x00040000 0x00020000>;
+                };
+                partition@3 {
+                        label = "NAND.SPL.backup3";
+                        reg = <0x00060000 0x00020000>;
+                };
+                partition@4 {
+                        label = "NAND.u-boot-spl-os";
+                        reg = <0x00080000 0x00040000>;
+                };
+                partition@5 {
+                        label = "NAND.u-boot";
+                        reg = <0x000c0000 0x00100000>;
+                };
+                partition@6 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001c0000 0x00020000>;
+                };
+                partition@7 {
+                        label = "NAND.u-boot-env";
+                        reg = <0x001e0000 0x00020000>;
+                };
+                partition@8 {
+                        label = "NAND.kernel";
+                        reg = <0x00200000 0x00800000>;
+                };
+                partition@9 {
+                        label = "NAND.file-system";
+                        reg = <0x00a00000 0x0f600000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 149b55099935..c29945e07c5a 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -33,33 +33,6 @@
                serial5 = &uart6;
        };
-        cpus {
-                #address-cells = <1>;
-                #size-cells = <0>;
-                cpu0: cpu@0 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <0>;
-                        operating-points = <
-                                /* kHz    uV */
-                                1000000 1060000
-                                1176000 1160000
-                                >;
-                        clocks = <&dpll_mpu_ck>;
-                        clock-names = "cpu";
-                        clock-latency = <300000>; /* From omap-cpufreq driver */
-                };
-                cpu@1 {
-                        device_type = "cpu";
-                        compatible = "arm,cortex-a15";
-                        reg = <1>;
-                };
-        };
        timer {
                compatible = "arm,armv7-timer";
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -99,13 +72,13 @@
         * hierarchy.
         */
        ocp {
-                compatible = "ti,omap4-l3-noc", "simple-bus";
+                compatible = "ti,dra7-l3-noc", "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
                ti,hwmods = "l3_main_1", "l3_main_2";
-                reg = <0x44000000 0x2000>,
+                reg = <0x44000000 0x1000000>,
-                      <0x44800000 0x3000>;
+                      <0x45000000 0x1000>;
                interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
@@ -789,6 +762,228 @@
                        dma-names = "tx0", "rx0";
                        status = "disabled";
                };
+                qspi: qspi@4b300000 {
+                        compatible = "ti,dra7xxx-qspi";
+                        reg = <0x4b300000 0x100>;
+                        reg-names = "qspi_base";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "qspi";
+                        clocks = <&qspi_gfclk_div>;
+                        clock-names = "fck";
+                        num-cs = <4>;
+                        interrupts = <0 343 0x4>;
+                        status = "disabled";
+                };
+                omap_control_sata: control-phy@4a002374 {
+                        compatible = "ti,control-phy-pipe3";
+                        reg = <0x4a002374 0x4>;
+                        reg-names = "power";
+                        clocks = <&sys_clkin1>;
+                        clock-names = "sysclk";
+                };
+                /* OCP2SCP3 */
+                ocp2scp@4a090000 {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        reg = <0x4a090000 0x20>;
+                        ti,hwmods = "ocp2scp3";
+                        sata_phy: phy@4A096000 {
+                                compatible = "ti,phy-pipe3-sata";
+                                reg = <0x4A096000 0x80>, /* phy_rx */
+                                      <0x4A096400 0x64>, /* phy_tx */
+                                      <0x4A096800 0x40>; /* pll_ctrl */
+                                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+                                ctrl-module = <&omap_control_sata>;
+                                clocks = <&sys_clkin1>;
+                                clock-names = "sysclk";
+                                #phy-cells = <0>;
+                        };
+                };
+                sata: sata@4a141100 {
+                        compatible = "snps,dwc-ahci";
+                        reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&sata_phy>;
+                        phy-names = "sata-phy";
+                        clocks = <&sata_ref_clk>;
+                        ti,hwmods = "sata";
+                };
+                omap_control_usb2phy1: control-phy@4a002300 {
+                        compatible = "ti,control-phy-usb2";
+                        reg = <0x4a002300 0x4>;
+                        reg-names = "power";
+                };
+                omap_control_usb3phy1: control-phy@4a002370 {
+                        compatible = "ti,control-phy-pipe3";
+                        reg = <0x4a002370 0x4>;
+                        reg-names = "power";
+                };
+                omap_control_usb2phy2: control-phy@0x4a002e74 {
+                        compatible = "ti,control-phy-usb2-dra7";
+                        reg = <0x4a002e74 0x4>;
+                        reg-names = "power";
+                };
+                /* OCP2SCP1 */
+                ocp2scp@4a080000 {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        reg = <0x4a080000 0x20>;
+                        ti,hwmods = "ocp2scp1";
+                        usb2_phy1: phy@4a084000 {
+                                compatible = "ti,omap-usb2";
+                                reg = <0x4a084000 0x400>;
+                                ctrl-module = <&omap_control_usb2phy1>;
+                                clocks = <&usb_phy1_always_on_clk32k>,
+                                         <&usb_otg_ss1_refclk960m>;
+                                clock-names =   "wkupclk",
+                                                "refclk";
+                                #phy-cells = <0>;
+                        };
+                        usb2_phy2: phy@4a085000 {
+                                compatible = "ti,omap-usb2";
+                                reg = <0x4a085000 0x400>;
+                                ctrl-module = <&omap_control_usb2phy2>;
+                                clocks = <&usb_phy2_always_on_clk32k>,
+                                         <&usb_otg_ss2_refclk960m>;
+                                clock-names =   "wkupclk",
+                                                "refclk";
+                                #phy-cells = <0>;
+                        };
+                        usb3_phy1: phy@4a084400 {
+                                compatible = "ti,omap-usb3";
+                                reg = <0x4a084400 0x80>,
+                                      <0x4a084800 0x64>,
+                                      <0x4a084c00 0x40>;
+                                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+                                ctrl-module = <&omap_control_usb3phy1>;
+                                clocks = <&usb_phy3_always_on_clk32k>,
+                                         <&sys_clkin1>,
+                                         <&usb_otg_ss1_refclk960m>;
+                                clock-names =   "wkupclk",
+                                                "sysclk",
+                                                "refclk";
+                                #phy-cells = <0>;
+                        };
+                };
+                omap_dwc3_1@48880000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss1";
+                        reg = <0x48880000 0x10000>;
+                        interrupts = <0 77 4>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        usb1: usb@48890000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x48890000 0x17000>;
+                                interrupts = <0 76 4>;
+                                phys = <&usb2_phy1>, <&usb3_phy1>;
+                                phy-names = "usb2-phy", "usb3-phy";
+                                tx-fifo-resize;
+                                maximum-speed = "super-speed";
+                                dr_mode = "otg";
+                        };
+                };
+                omap_dwc3_2@488c0000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss2";
+                        reg = <0x488c0000 0x10000>;
+                        interrupts = <0 92 4>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        usb2: usb@488d0000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x488d0000 0x17000>;
+                                interrupts = <0 78 4>;
+                                phys = <&usb2_phy2>;
+                                phy-names = "usb2-phy";
+                                tx-fifo-resize;
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                        };
+                };
+                /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
+                omap_dwc3_3@48900000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss3";
+                        reg = <0x48900000 0x10000>;
+                /*      interrupts = <0 TBD 4>; */
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        status = "disabled";
+                        usb3: usb@48910000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x48910000 0x17000>;
+                /*              interrupts = <0 93 4>; */
+                                tx-fifo-resize;
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                        };
+                };
+                omap_dwc3_4@48940000 {
+                        compatible = "ti,dwc3";
+                        ti,hwmods = "usb_otg_ss4";
+                        reg = <0x48940000 0x10000>;
+                /*      interrupts = <0 TBD 4>; */
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        utmi-mode = <2>;
+                        ranges;
+                        status = "disabled";
+                        usb4: usb@48950000 {
+                                compatible = "snps,dwc3";
+                                reg = <0x48950000 0x17000>;
+                /*              interrupts = <0 TBD 4>; */
+                                tx-fifo-resize;
+                                maximum-speed = "high-speed";
+                                dr_mode = "otg";
+                        };
+                };
+                elm: elm@48078000 {
+                        compatible = "ti,am3352-elm";
+                        reg = <0x48078000 0xfc0>;      /* device IO registers */
+                        interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "elm";
+                        status = "disabled";
+                };
+                gpmc: gpmc@50000000 {
+                        compatible = "ti,am3352-gpmc";
+                        ti,hwmods = "gpmc";
+                        reg = <0x50000000 0x37c>;      /* device IO registers */
+                        interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                        gpmc,num-cs = <8>;
+                        gpmc,num-waitpins = <2>;
+                        #address-cells = <2>;
+                        #size-cells = <1>;
+                        status = "disabled";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
new file mode 100644
index 000000000000..514702348818
--- /dev/null
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "dra72x.dtsi"
+/ {
+        model = "TI DRA722";
+        compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1024 MB */
+        };
+};
+&uart1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
new file mode 100644
index 000000000000..f1ec22f6ebf4
--- /dev/null
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+#include "dra7.dtsi"
+/ {
+        compatible = "ti,dra722", "ti,dra72", "ti,dra7";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
new file mode 100644
index 000000000000..a4e8bb9f95c0
--- /dev/null
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * Based on "omap4.dtsi"
+ */
+#include "dra7.dtsi"
+/ {
+        compatible = "ti,dra742", "ti,dra74", "ti,dra7";
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                        operating-points = <
+                                /* kHz    uV */
+                                1000000 1060000
+                                1176000 1160000
+                                >;
+                        clocks = <&dpll_mpu_ck>;
+                        clock-names = "cpu";
+                        clock-latency = <300000>; /* From omap-cpufreq driver */
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 264b9caa9eef..b03cfe49d22b 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1386,6 +1386,14 @@
                ti,dividers = <1>, <8>;
        };
+        l3init_960m_gfclk: l3init_960m_gfclk {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&dpll_usb_clkdcoldo>;
+                ti,bit-shift = <8>;
+                reg = <0x06c0>;
+        };
        dss_32khz_clk: dss_32khz_clk {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
@@ -1533,7 +1541,7 @@
        usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
-                clocks = <&dpll_usb_clkdcoldo>;
+                clocks = <&l3init_960m_gfclk>;
                ti,bit-shift = <8>;
                reg = <0x13f0>;
        };
@@ -1541,7 +1549,7 @@
        usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m {
                #clock-cells = <0>;
                compatible = "ti,gate-clock";
-                clocks = <&dpll_usb_clkdcoldo>;
+                clocks = <&l3init_960m_gfclk>;
                ti,bit-shift = <8>;
                reg = <0x1340>;
        };
diff --git a/arch/arm/boot/dts/exynos3250-pinctrl.dtsi b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
new file mode 100644
index 000000000000..47b92c150f4e
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250-pinctrl.dtsi
@@ -0,0 +1,475 @@
+/*
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoCs pin-mux and pin-config optiosn are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb: gpb {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <0x2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_data: uart1-data {
+                samsung,pins = "gpa0-4", "gpa0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c2_bus: i2c2-bus {
+                samsung,pins = "gpa0-6", "gpa0-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c3_bus: i2c3-bus {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpb-0", "gpb-2", "gpb-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb-0", "gpb-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpb-4", "gpb-6", "gpb-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb-2", "gpb-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        i2s2_bus: i2s2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pcm2_bus: pcm2-bus {
+                samsung,pins = "gpc1-0", "gpc1-1", "gpc1-2", "gpc1-3",
+                                "gpc1-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpc1-3", "gpc1-4";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        pwm0_out: pwm0-out {
+                samsung,pins = "gpd0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pwm1_out: pwm1-out {
+                samsung,pins = "gpd0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpd0-2", "gpd0-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        pwm2_out: pwm2-out {
+                samsung,pins = "gpd0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        pwm3_out: pwm3-out {
+                samsung,pins = "gpd0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c0_bus: i2c0-bus {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        mipi0_clk: mipi0-clk {
+                samsung,pins = "gpd1-0", "gpd1-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        i2c1_bus: i2c1-bus {
+                samsung,pins = "gpd1-2", "gpd1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_1 {
+        gpe0: gpe0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpe1: gpe1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpe2: gpe2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+        };
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk1: gpk1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk2: gpk2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpl0: gpl0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm0: gpm0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm1: gpm1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm2: gpm2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm3: gpm3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpm4: gpm4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 32 0>, <0 33 0>, <0 34 0>, <0 35 0>,
+                                <0 36 0>, <0 37 0>, <0 38 0>, <0 39 0>;
+                #interrupt-cells = <2>;
+        };
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                interrupt-parent = <&gic>;
+                interrupts = <0 40 0>, <0 41 0>, <0 42 0>, <0 43 0>,
+                                <0 44 0>, <0 45 0>, <0 46 0>, <0 47 0>;
+                #interrupt-cells = <2>;
+        };
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpk0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpk0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_cd: sd0-cd {
+                samsung,pins = "gpk0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_rdqs: sd0-rdqs {
+                samsung,pins = "gpk0-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpk0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpk0-4", "gpk0-5", "gpk0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpl0-0", "gpl0-1", "gpl0-2", "gpl0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpk1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpk1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_cd: sd1-cd {
+                samsung,pins = "gpk1-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpk1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpk1-4", "gpk1-5", "gpk1-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <3>;
+        };
+        cam_port_b_io: cam-port-b-io {
+                samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
+                                "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
+                                "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        cam_port_b_clk_active: cam-port-b-clk-active {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <3>;
+        };
+        cam_port_b_clk_idle: cam-port-b-clk-idle {
+                samsung,pins = "gpm2-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_i2c0: fimc-is-i2c0 {
+                samsung,pins = "gpm4-0", "gpm4-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_i2c1: fimc-is-i2c1 {
+                samsung,pins = "gpm4-2", "gpm4-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        fimc_is_uart: fimc-is-uart {
+                samsung,pins = "gpm3-5", "gpm3-7";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
new file mode 100644
index 000000000000..3e678fa335bf
--- /dev/null
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -0,0 +1,444 @@
+/*
+ * Samsung's Exynos3250 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos3250 SoC device nodes are listed in this file. Exynos3250
+ * based board files can include this file and provide values for board specfic
+ * bindings.
+ *
+ * Note: This file does not include device nodes for all the controllers in
+ * Exynos3250 SoC. As device tree coverage for Exynos3250 increases, additional
+ * nodes can be added to this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos3250.h>
+/ {
+        compatible = "samsung,exynos3250";
+        interrupt-parent = <&gic>;
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                mshc0 = &mshc_0;
+                mshc1 = &mshc_1;
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                i2c0 = &i2c_0;
+                i2c1 = &i2c_1;
+                i2c2 = &i2c_2;
+                i2c3 = &i2c_3;
+                i2c4 = &i2c_4;
+                i2c5 = &i2c_5;
+                i2c6 = &i2c_6;
+                i2c7 = &i2c_7;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0>;
+                        clock-frequency = <1000000000>;
+                };
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <1>;
+                        clock-frequency = <1000000000>;
+                };
+        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                fixed-rate-clocks {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        xusbxti: clock@0 {
+                                compatible = "fixed-clock";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0>;
+                                clock-frequency = <0>;
+                                #clock-cells = <0>;
+                                clock-output-names = "xusbxti";
+                        };
+                        xxti: clock@1 {
+                                compatible = "fixed-clock";
+                                reg = <1>;
+                                clock-frequency = <0>;
+                                #clock-cells = <0>;
+                                clock-output-names = "xxti";
+                        };
+                        xtcxo: clock@2 {
+                                compatible = "fixed-clock";
+                                reg = <2>;
+                                clock-frequency = <0>;
+                                #clock-cells = <0>;
+                                clock-output-names = "xtcxo";
+                        };
+                };
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x40000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x40000>;
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
+                        smp-sysram@3f000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x3f000 0x1000>;
+                        };
+                };
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
+                sys_reg: syscon@10010000 {
+                        compatible = "samsung,exynos3-sysreg", "syscon";
+                        reg = <0x10010000 0x400>;
+                };
+                pmu_system_controller: system-controller@10020000 {
+                        compatible = "samsung,exynos3250-pmu", "syscon";
+                        reg = <0x10020000 0x4000>;
+                };
+                pd_cam: cam-power-domain@10023C00 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C00 0x20>;
+                };
+                pd_mfc: mfc-power-domain@10023C40 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C40 0x20>;
+                };
+                pd_g3d: g3d-power-domain@10023C60 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C60 0x20>;
+                };
+                pd_lcd0: lcd0-power-domain@10023C80 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023C80 0x20>;
+                };
+                pd_isp: isp-power-domain@10023CA0 {
+                        compatible = "samsung,exynos4210-pd";
+                        reg = <0x10023CA0 0x20>;
+                };
+                cmu: clock-controller@10030000 {
+                        compatible = "samsung,exynos3250-cmu";
+                        reg = <0x10030000 0x20000>;
+                        #clock-cells = <1>;
+                };
+                rtc: rtc@10070000 {
+                        compatible = "samsung,s3c6410-rtc";
+                        reg = <0x10070000 0x100>;
+                        interrupts = <0 73 0>, <0 74 0>;
+                        status = "disabled";
+                };
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a15-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg = <0x10481000 0x1000>,
+                              <0x10482000 0x1000>,
+                              <0x10484000 0x2000>,
+                              <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
+                mct@10050000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x10050000 0x800>;
+                        interrupts = <0 218 0>, <0 219 0>, <0 220 0>, <0 221 0>,
+                                     <0 223 0>, <0 226 0>, <0 227 0>, <0 228 0>;
+                        clocks = <&cmu CLK_FIN_PLL>, <&cmu CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+                };
+                pinctrl_1: pinctrl@11000000 {
+                        compatible = "samsung,exynos3250-pinctrl";
+                        reg = <0x11000000 0x1000>;
+                        interrupts = <0 225 0>;
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 48 0>;
+                        };
+                };
+                pinctrl_0: pinctrl@11400000 {
+                        compatible = "samsung,exynos3250-pinctrl";
+                        reg = <0x11400000 0x1000>;
+                        interrupts = <0 240 0>;
+                };
+                mshc_0: mshc@12510000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12510000 0x1000>;
+                        interrupts = <0 142 0>;
+                        clocks = <&cmu CLK_SDMMC0>, <&cmu CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                mshc_1: mshc@12520000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12520000 0x1000>;
+                        interrupts = <0 143 0>;
+                        clocks = <&cmu CLK_SDMMC1>, <&cmu CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        status = "disabled";
+                };
+                amba {
+                        compatible = "arm,amba-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        interrupt-parent = <&gic>;
+                        ranges;
+                        pdma0: pdma@12680000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12680000 0x1000>;
+                                interrupts = <0 138 0>;
+                                clocks = <&cmu CLK_PDMA0>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                        pdma1: pdma@12690000 {
+                                compatible = "arm,pl330", "arm,primecell";
+                                reg = <0x12690000 0x1000>;
+                                interrupts = <0 139 0>;
+                                clocks = <&cmu CLK_PDMA1>;
+                                clock-names = "apb_pclk";
+                                #dma-cells = <1>;
+                                #dma-channels = <8>;
+                                #dma-requests = <32>;
+                        };
+                };
+                adc: adc@126C0000 {
+                        compatible = "samsung,exynos-adc-v3";
+                        reg = <0x126C0000 0x100>, <0x10020718 0x4>;
+                        interrupts = <0 137 0>;
+                        clock-names = "adc", "sclk_tsadc";
+                        clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>;
+                        #io-channel-cells = <1>;
+                        io-channel-ranges;
+                        status = "disabled";
+                };
+                serial_0: serial@13800000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13800000 0x100>;
+                        interrupts = <0 109 0>;
+                        clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                serial_1: serial@13810000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x13810000 0x100>;
+                        interrupts = <0 110 0>;
+                        clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                i2c_0: i2c@13860000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13860000 0x100>;
+                        interrupts = <0 113 0>;
+                        clocks = <&cmu CLK_I2C0>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c0_bus>;
+                        status = "disabled";
+                };
+                i2c_1: i2c@13870000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13870000 0x100>;
+                        interrupts = <0 114 0>;
+                        clocks = <&cmu CLK_I2C1>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c1_bus>;
+                        status = "disabled";
+                };
+                i2c_2: i2c@13880000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13880000 0x100>;
+                        interrupts = <0 115 0>;
+                        clocks = <&cmu CLK_I2C2>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c2_bus>;
+                        status = "disabled";
+                };
+                i2c_3: i2c@13890000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x13890000 0x100>;
+                        interrupts = <0 116 0>;
+                        clocks = <&cmu CLK_I2C3>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c3_bus>;
+                        status = "disabled";
+                };
+                i2c_4: i2c@138A0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138A0000 0x100>;
+                        interrupts = <0 117 0>;
+                        clocks = <&cmu CLK_I2C4>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c4_bus>;
+                        status = "disabled";
+                };
+                i2c_5: i2c@138B0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138B0000 0x100>;
+                        interrupts = <0 118 0>;
+                        clocks = <&cmu CLK_I2C5>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c5_bus>;
+                        status = "disabled";
+                };
+                i2c_6: i2c@138C0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138C0000 0x100>;
+                        interrupts = <0 119 0>;
+                        clocks = <&cmu CLK_I2C6>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c6_bus>;
+                        status = "disabled";
+                };
+                i2c_7: i2c@138D0000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "samsung,s3c2440-i2c";
+                        reg = <0x138D0000 0x100>;
+                        interrupts = <0 120 0>;
+                        clocks = <&cmu CLK_I2C7>;
+                        clock-names = "i2c";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&i2c7_bus>;
+                        status = "disabled";
+                };
+                spi_0: spi@13920000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13920000 0x100>;
+                        interrupts = <0 121 0>;
+                        dmas = <&pdma0 7>, <&pdma0 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI0>, <&cmu CLK_SCLK_SPI0>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi0_bus>;
+                        status = "disabled";
+                };
+                spi_1: spi@13930000 {
+                        compatible = "samsung,exynos4210-spi";
+                        reg = <0x13930000 0x100>;
+                        interrupts = <0 122 0>;
+                        dmas = <&pdma1 7>, <&pdma1 6>;
+                        dma-names = "tx", "rx";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&cmu CLK_SPI1>, <&cmu CLK_SCLK_SPI1>;
+                        clock-names = "spi", "spi_busclk0";
+                        samsung,spi-src-clk = <0>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&spi1_bus>;
+                        status = "disabled";
+                };
+                pwm: pwm@139D0000 {
+                        compatible = "samsung,exynos4210-pwm";
+                        reg = <0x139D0000 0x1000>;
+                        interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+                                     <0 107 0>, <0 108 0>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
+                pmu {
+                        compatible = "arm,cortex-a7-pmu";
+                        interrupts = <0 18 0>, <0 19 0>;
+                };
+        };
+};
+#include "exynos3250-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 2f8bcd068d17..b8ece4be41ca 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -20,6 +20,7 @@
 */
 #include <dt-bindings/clock/exynos4.h>
+#include <dt-bindings/clock/exynos-audss-clk.h>
 #include "skeleton.dtsi"
 / {
@@ -45,6 +46,23 @@
                fimc3 = &fimc_3;
        };
+        clock_audss: clock-controller@03810000 {
+                compatible = "samsung,exynos4210-audss-clock";
+                reg = <0x03810000 0x0C>;
+                #clock-cells = <1>;
+        };
+        i2s0: i2s@03830000 {
+                compatible = "samsung,s5pv210-i2s";
+                reg = <0x03830000 0x100>;
+                clocks = <&clock_audss EXYNOS_I2S_BUS>;
+                clock-names = "iis";
+                dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
+                dma-names = "tx", "rx", "tx-sec";
+                samsung,idma-addr = <0x03000000>;
+                status = "disabled";
+        };
        chipid@10000000 {
                compatible = "samsung,exynos4210-chipid";
                reg = <0x10000000 0x100>;
@@ -110,6 +128,11 @@
                reg = <0x10010000 0x400>;
        };
+        pmu_system_controller: system-controller@10020000 {
+                compatible = "samsung,exynos4210-pmu", "syscon";
+                reg = <0x10020000 0x4000>;
+        };
        dsi_0: dsi@11C80000 {
                compatible = "samsung,exynos4210-mipi-dsi";
                reg = <0x11C80000 0x10000>;
@@ -117,7 +140,7 @@
                samsung,power-domain = <&pd_lcd0>;
                phys = <&mipi_phy 1>;
                phy-names = "dsim";
-                clocks = <&clock 286>, <&clock 143>;
+                clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
                clock-names = "bus_clk", "pll_clk";
                status = "disabled";
                #address-cells = <1>;
@@ -129,12 +152,10 @@
                status = "disabled";
                #address-cells = <1>;
                #size-cells = <1>;
+                #clock-cells = <1>;
+                clock-output-names = "cam_a_clkout", "cam_b_clkout";
                ranges;
-                clock_cam: clock-controller {
-                         #clock-cells = <1>;
-                };
                fimc_0: fimc@11800000 {
                        compatible = "samsung,exynos4210-fimc";
                        reg = <0x11800000 0x1000>;
@@ -273,6 +294,27 @@
                status = "disabled";
        };
+        exynos_usbphy: exynos-usbphy@125B0000 {
+                compatible = "samsung,exynos4210-usb2-phy";
+                reg = <0x125B0000 0x100>;
+                samsung,pmureg-phandle = <&pmu_system_controller>;
+                clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
+                clock-names = "phy", "ref";
+                #phy-cells = <1>;
+                status = "disabled";
+        };
+        hsotg@12480000 {
+                compatible = "samsung,s3c6400-hsotg";
+                reg = <0x12480000 0x20000>;
+                interrupts = <0 71 0>;
+                clocks = <&clock CLK_USB_DEVICE>;
+                clock-names = "otg";
+                phys = <&exynos_usbphy 0>;
+                phy-names = "usb2-phy";
+                status = "disabled";
+        };
        ehci@12580000 {
                compatible = "samsung,exynos4210-ehci";
                reg = <0x12580000 0x100>;
@@ -291,6 +333,26 @@
                status = "disabled";
        };
+        i2s1: i2s@13960000 {
+                compatible = "samsung,s5pv210-i2s";
+                reg = <0x13960000 0x100>;
+                clocks = <&clock CLK_I2S1>;
+                clock-names = "iis";
+                dmas = <&pdma1 12>, <&pdma1 11>;
+                dma-names = "tx", "rx";
+                status = "disabled";
+        };
+        i2s2: i2s@13970000 {
+                compatible = "samsung,s5pv210-i2s";
+                reg = <0x13970000 0x100>;
+                clocks = <&clock CLK_I2S2>;
+                clock-names = "iis";
+                dmas = <&pdma0 14>, <&pdma0 13>;
+                dma-names = "tx", "rx";
+                status = "disabled";
+        };
        mfc: codec@13400000 {
                compatible = "samsung,mfc-v5";
                reg = <0x13400000 0x10000>;
@@ -371,6 +433,8 @@
                interrupts = <0 60 0>;
                clocks = <&clock CLK_I2C2>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c2_bus>;
                status = "disabled";
        };
@@ -382,6 +446,8 @@
                interrupts = <0 61 0>;
                clocks = <&clock CLK_I2C3>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c3_bus>;
                status = "disabled";
        };
@@ -393,6 +459,8 @@
                interrupts = <0 62 0>;
                clocks = <&clock CLK_I2C4>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c4_bus>;
                status = "disabled";
        };
@@ -404,6 +472,8 @@
                interrupts = <0 63 0>;
                clocks = <&clock CLK_I2C5>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c5_bus>;
                status = "disabled";
        };
@@ -415,6 +485,8 @@
                interrupts = <0 64 0>;
                clocks = <&clock CLK_I2C6>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c6_bus>;
                status = "disabled";
        };
@@ -426,6 +498,8 @@
                interrupts = <0 65 0>;
                clocks = <&clock CLK_I2C7>;
                clock-names = "i2c";
+                pinctrl-names = "default";
+                pinctrl-0 = <&i2c7_bus>;
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index 72fb11f7ea21..f767c425d0b5 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -16,6 +16,7 @@
 /dts-v1/;
 #include "exynos4210.dtsi"
+#include <dt-bindings/input/input.h>
 / {
        model = "Insignal Origen evaluation board based on Exynos4210";
@@ -48,6 +49,14 @@
                };
        };
+        watchdog@10060000 {
+                status = "okay";
+        };
+        rtc@10070000 {
+                status = "okay";
+        };
        tmu@100C0000 {
                status = "okay";
        };
@@ -251,35 +260,35 @@
                up {
                        label = "Up";
                        gpios = <&gpx2 0 1>;
-                        linux,code = <103>;
+                        linux,code = <KEY_UP>;
                        gpio-key,wakeup;
                };
                down {
                        label = "Down";
                        gpios = <&gpx2 1 1>;
-                        linux,code = <108>;
+                        linux,code = <KEY_DOWN>;
                        gpio-key,wakeup;
                };
                back {
                        label = "Back";
                        gpios = <&gpx1 7 1>;
-                        linux,code = <158>;
+                        linux,code = <KEY_BACK>;
                        gpio-key,wakeup;
                };
                home {
                        label = "Home";
                        gpios = <&gpx1 6 1>;
-                        linux,code = <102>;
+                        linux,code = <KEY_HOME>;
                        gpio-key,wakeup;
                };
                menu {
                        label = "Menu";
                        gpios = <&gpx1 5 1>;
-                        linux,code = <139>;
+                        linux,code = <KEY_MENU>;
                        gpio-key,wakeup;
                };
        };
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 63aa2bb24a4b..f516da9e8b3a 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -88,6 +88,12 @@
                };
        };
+        hsotg@12480000 {
+                vusb_d-supply = <&vusb_reg>;
+                vusb_a-supply = <&vusbdac_reg>;
+                status = "okay";
+        };
        sdhci_emmc: sdhci@12510000 {
                bus-width = <8>;
                non-removable;
@@ -97,6 +103,10 @@
                status = "okay";
        };
+        exynos-usbphy@125B0000 {
+                status = "okay";
+        };
        serial@13800000 {
                status = "okay";
        };
diff --git a/arch/arm/boot/dts/exynos4210-universal_c210.dts b/arch/arm/boot/dts/exynos4210-universal_c210.dts
index 63e34b24b04f..d50eb3aa708e 100644
--- a/arch/arm/boot/dts/exynos4210-universal_c210.dts
+++ b/arch/arm/boot/dts/exynos4210-universal_c210.dts
@@ -28,6 +28,21 @@
                bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rw rootwait earlyprintk panic=5 maxcpus=1";
        };
+        sysram@02020000 {
+                smp-sysram@0 {
+                        status = "disabled";
+                };
+                smp-sysram@5000 {
+                        compatible = "samsung,exynos4210-sysram";
+                        reg = <0x5000 0x1000>;
+                };
+                smp-sysram@1f000 {
+                        status = "disabled";
+                };
+        };
        mct@10050000 {
                compatible = "none";
        };
@@ -53,6 +68,12 @@
                enable-active-high;
        };
+        hsotg@12480000 {
+                vusb_d-supply = <&ldo3_reg>;
+                vusb_a-supply = <&ldo8_reg>;
+                status = "okay";
+        };
        sdhci_emmc: sdhci@12510000 {
                bus-width = <8>;
                non-removable;
@@ -62,6 +83,34 @@
                status = "okay";
        };
+        sdhci_sd: sdhci@12530000 {
+                bus-width = <4>;
+                pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>;
+                pinctrl-names = "default";
+                vmmc-supply = <&ldo5_reg>;
+                cd-gpios = <&gpx3 4 0>;
+                cd-inverted;
+                status = "okay";
+        };
+        ehci@12580000 {
+                status = "okay";
+                port@0 {
+                        status = "okay";
+                };
+        };
+        ohci@12590000 {
+                status = "okay";
+                port@0 {
+                        status = "okay";
+                };
+        };
+        exynos-usbphy@125B0000 {
+                status = "okay";
+        };
        serial@13800000 {
                status = "okay";
        };
@@ -201,6 +250,7 @@
                                        regulator-name = "VUSB+MIPI_1.1V";
                                        regulator-min-microvolt = <1100000>;
                                        regulator-max-microvolt = <1100000>;
+                                        regulator-always-on;
                                };
                                ldo4_reg: LDO4 {
@@ -231,6 +281,7 @@
                                        regulator-name = "VUSB+VDAC_3.3V";
                                        regulator-min-microvolt = <3300000>;
                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
                                };
                                ldo9_reg: LDO9 {
@@ -413,6 +464,29 @@
                compatible = "samsung,s5p6440-pwm";
                status = "okay";
        };
+        camera {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <>;
+                fimc_0: fimc@11800000 {
+                        status = "okay";
+                };
+                fimc_1: fimc@11810000 {
+                        status = "okay";
+                };
+                fimc_2: fimc@11820000 {
+                        status = "okay";
+                };
+                fimc_3: fimc@11830000 {
+                        status = "okay";
+                };
+        };
 };
 &mdma1 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index cacf6140dd2f..ee3001f38821 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -31,6 +31,24 @@
                pinctrl2 = &pinctrl_2;
        };
+        sysram@02020000 {
+                compatible = "mmio-sram";
+                reg = <0x02020000 0x20000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x02020000 0x20000>;
+                smp-sysram@0 {
+                        compatible = "samsung,exynos4210-sysram";
+                        reg = <0x0 0x1000>;
+                };
+                smp-sysram@1f000 {
+                        compatible = "samsung,exynos4210-sysram-ns";
+                        reg = <0x1f000 0x1000>;
+                };
+        };
        pd_lcd1: lcd1-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index e2c0dcab4d81..e925c9fbfb07 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 #include "exynos4412.dtsi"
+#include <dt-bindings/input/input.h>
 / {
        model = "Insignal Origen evaluation board based on Exynos4412";
@@ -48,6 +49,14 @@
                };
        };
+        watchdog@10060000 {
+                status = "okay";
+        };
+        rtc@10070000 {
+                status = "okay";
+        };
        pinctrl@11000000 {
                keypad_rows: keypad-rows {
                        samsung,pins = "gpx2-0", "gpx2-1", "gpx2-2";
@@ -76,37 +85,37 @@
                key_home {
                        keypad,row = <0>;
                        keypad,column = <0>;
-                        linux,code = <102>;
+                        linux,code = <KEY_HOME>;
                };
                key_down {
                        keypad,row = <0>;
                        keypad,column = <1>;
-                        linux,code = <108>;
+                        linux,code = <KEY_DOWN>;
                };
                key_up {
                        keypad,row = <1>;
                        keypad,column = <0>;
-                        linux,code = <103>;
+                        linux,code = <KEY_UP>;
                };
                key_menu {
                        keypad,row = <1>;
                        keypad,column = <1>;
-                        linux,code = <139>;
+                        linux,code = <KEY_MENU>;
                };
                key_back {
                        keypad,row = <2>;
                        keypad,column = <0>;
-                        linux,code = <158>;
+                        linux,code = <KEY_BACK>;
                };
                key_enter {
                        keypad,row = <2>;
                        keypad,column = <1>;
-                        linux,code = <28>;
+                        linux,code = <KEY_ENTER>;
                };
        };
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
index 9583563dd0ef..77878447b312 100644
--- a/arch/arm/boot/dts/exynos4412-trats2.dts
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -20,7 +20,8 @@
        compatible = "samsung,trats2", "samsung,exynos4412", "samsung,exynos4";
        aliases {
-                i2c8 = &i2c_ak8975;
+                i2c9 = &i2c_ak8975;
+                i2c10 = &i2c_cm36651;
        };
        memory {
@@ -80,39 +81,67 @@
                        enable-active-high;
                };
-                /* More to come */
+                cam_af_reg: voltage-regulator-3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "CAM_AF";
+                        regulator-min-microvolt = <2800000>;
+                        regulator-max-microvolt = <2800000>;
+                        gpio = <&gpm0 4 0>;
+                        enable-active-high;
+                };
+                cam_isp_core_reg: voltage-regulator-4 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "CAM_ISP_CORE_1.2V_EN";
+                        regulator-min-microvolt = <1200000>;
+                        regulator-max-microvolt = <1200000>;
+                        gpio = <&gpm0 3 0>;
+                        enable-active-high;
+                        regulator-always-on;
+                };
+                ps_als_reg: voltage-regulator-5 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "LED_A_3.0V";
+                        regulator-min-microvolt = <3000000>;
+                        regulator-max-microvolt = <3000000>;
+                        gpio = <&gpj0 5 0>;
+                        enable-active-high;
+                };
        };
        gpio-keys {
                compatible = "gpio-keys";
                key-down {
-                        interrupt-parent = <&gpj1>;
+                        gpios = <&gpx3 3 1>;
-                        interrupts = <2 0>;
-                        gpios = <&gpj1 2 1>;
                        linux,code = <114>;
                        label = "volume down";
                        debounce-interval = <10>;
                };
                key-up {
-                        interrupt-parent = <&gpj1>;
+                        gpios = <&gpx2 2 1>;
-                        interrupts = <1 0>;
-                        gpios = <&gpj1 1 1>;
                        linux,code = <115>;
                        label = "volume up";
                        debounce-interval = <10>;
                };
                key-power {
-                        interrupt-parent = <&gpx2>;
-                        interrupts = <7 0>;
                        gpios = <&gpx2 7 1>;
                        linux,code = <116>;
                        label = "power";
                        debounce-interval = <10>;
                        gpio-key,wakeup;
                };
+                key-ok {
+                        gpios = <&gpx0 1 1>;
+                        linux,code = <139>;
+                        label = "ok";
+                        debounce-inteval = <10>;
+                        gpio-key,wakeup;
+                };
        };
        adc: adc@126C0000 {
@@ -140,6 +169,38 @@
                };
        };
+        i2c_0: i2c@13860000 {
+                samsung,i2c-sda-delay = <100>;
+                samsung,i2c-slave-addr = <0x10>;
+                samsung,i2c-max-bus-freq = <400000>;
+                pinctrl-0 = <&i2c0_bus>;
+                pinctrl-names = "default";
+                status = "okay";
+                s5c73m3@3c {
+                        compatible = "samsung,s5c73m3";
+                        reg = <0x3c>;
+                        standby-gpios = <&gpm0 1 1>;   /* ISP_STANDBY */
+                        xshutdown-gpios = <&gpf1 3 1>; /* ISP_RESET */
+                        vdd-int-supply = <&buck9_reg>;
+                        vddio-cis-supply = <&ldo9_reg>;
+                        vdda-supply = <&ldo17_reg>;
+                        vddio-host-supply = <&ldo18_reg>;
+                        vdd-af-supply = <&cam_af_reg>;
+                        vdd-reg-supply = <&cam_io_reg>;
+                        clock-frequency = <24000000>;
+                        /* CAM_A_CLKOUT */
+                        clocks = <&camera 0>;
+                        clock-names = "cis_extclk";
+                        port {
+                                s5c73m3_ep: endpoint {
+                                        remote-endpoint = <&csis0_ep>;
+                                        data-lanes = <1 2 3 4>;
+                                };
+                        };
+                };
+        };
        i2c@138D0000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-slave-addr = <0x10>;
@@ -503,12 +564,28 @@
                status = "okay";
                ak8975@0c {
-                        compatible = "ak,ak8975";
+                        compatible = "asahi-kasei,ak8975";
                        reg = <0x0c>;
                        gpios = <&gpj0 7 0>;
                };
        };
+        i2c_cm36651: i2c-gpio-2 {
+                compatible = "i2c-gpio";
+                gpios = <&gpf0 0 1>, <&gpf0 1 1>;
+                i2c-gpio,delay-us = <2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cm36651@18 {
+                        compatible = "capella,cm36651";
+                        reg = <0x18>;
+                        interrupt-parent = <&gpx0>;
+                        interrupts = <2 2>;
+                        vled-supply = <&ps_als_reg>;
+                };
+        };
        spi_1: spi@13930000 {
                pinctrl-names = "default";
                pinctrl-0 = <&spi1_bus>;
@@ -586,8 +663,8 @@
                status = "okay";
        };
-        camera {
+        camera: camera {
-                pinctrl-0 = <&cam_port_b_clk_active>;
+                pinctrl-0 = <&cam_port_a_clk_active &cam_port_b_clk_active>;
                pinctrl-names = "default";
                status = "okay";
@@ -607,6 +684,23 @@
                        status = "okay";
                };
+                csis_0: csis@11880000 {
+                        status = "okay";
+                        vddcore-supply = <&ldo8_reg>;
+                        vddio-supply = <&ldo10_reg>;
+                        clock-frequency = <176000000>;
+                        /* Camera C (3) MIPI CSI-2 (CSIS0) */
+                        port@3 {
+                                reg = <3>;
+                                csis0_ep: endpoint {
+                                        remote-endpoint = <&s5c73m3_ep>;
+                                        data-lanes = <1 2 3 4>;
+                                        samsung,csis-hs-settle = <12>;
+                                };
+                        };
+                };
                csis_1: csis@11890000 {
                        vddcore-supply = <&ldo8_reg>;
                        vddio-supply = <&ldo10_reg>;
@@ -647,10 +741,11 @@
                                        reg = <0x10>;
                                        svdda-supply = <&cam_io_reg>;
                                        svddio-supply = <&ldo19_reg>;
+                                        afvdd-supply = <&ldo19_reg>;
                                        clock-frequency = <24000000>;
                                        /* CAM_B_CLKOUT */
-                                        clocks = <&clock_cam 1>;
+                                        clocks = <&camera 1>;
-                                        clock-names = "mclk";
+                                        clock-names = "extclk";
                                        samsung,camclk-out = <1>;
                                        gpios = <&gpm1 6 0>;
@@ -665,6 +760,16 @@
                };
        };
+        exynos-usbphy@125B0000 {
+                status = "okay";
+        };
+        hsotg@12480000 {
+                vusb_d-supply = <&ldo15_reg>;
+                vusb_a-supply = <&ldo12_reg>;
+                status = "okay";
+        };
        thermistor-ap@0 {
                compatible = "ntc,ncp15wb473";
                pullup-uv = <1800000>;   /* VCC_1.8V_AP */
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 15d3c0ac2f5f..c42a3e196cd5 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -29,4 +29,8 @@
        gic: interrupt-controller@10490000 {
                cpu-offset = <0x4000>;
        };
+        pmu_system_controller: system-controller@10020000 {
+                compatible = "samsung,exynos4412-pmu", "syscon";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c4a9306f8529..c5a943df1cd7 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -37,6 +37,24 @@
                interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
        };
+        sysram@02020000 {
+                compatible = "mmio-sram";
+                reg = <0x02020000 0x40000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x02020000 0x40000>;
+                smp-sysram@0 {
+                        compatible = "samsung,exynos4210-sysram";
+                        reg = <0x0 0x1000>;
+                };
+                smp-sysram@2f000 {
+                        compatible = "samsung,exynos4210-sysram-ns";
+                        reg = <0x2f000 0x1000>;
+                };
+        };
        pd_isp: isp-power-domain@10023CA0 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10023CA0 0x20>;
@@ -119,6 +137,10 @@
                interrupts = <0 72 0>;
        };
+        pmu_system_controller: system-controller@10020000 {
+                compatible = "samsung,exynos4212-pmu", "syscon";
+        };
        g2d@10800000 {
                compatible = "samsung,exynos4212-g2d";
                reg = <0x10800000 0x1000>;
@@ -243,4 +265,9 @@
                clock-names = "biu", "ciu";
                status = "disabled";
        };
+        exynos-usbphy@125B0000 {
+                compatible = "samsung,exynos4x12-usb2-phy";
+                samsung,sysreg-phandle = <&sys_reg>;
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 090f9830b129..d0de1f50d15b 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -12,6 +12,7 @@
 /dts-v1/;
 #include "exynos5250.dtsi"
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
 / {
        model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -107,6 +108,7 @@
                                        regulator-name = "VDD_IOPERI_1.8V";
                                        regulator-min-microvolt = <1800000>;
                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
                                        op_mode = <1>;
                                };
@@ -444,42 +446,42 @@
                menu {
                        label = "SW-TACT2";
                        gpios = <&gpx1 4 1>;
-                        linux,code = <139>;
+                        linux,code = <KEY_MENU>;
                        gpio-key,wakeup;
                };
                home {
                        label = "SW-TACT3";
                        gpios = <&gpx1 5 1>;
-                        linux,code = <102>;
+                        linux,code = <KEY_HOME>;
                        gpio-key,wakeup;
                };
                up {
                        label = "SW-TACT4";
                        gpios = <&gpx1 6 1>;
-                        linux,code = <103>;
+                        linux,code = <KEY_UP>;
                        gpio-key,wakeup;
                };
                down {
                        label = "SW-TACT5";
                        gpios = <&gpx1 7 1>;
-                        linux,code = <108>;
+                        linux,code = <KEY_DOWN>;
                        gpio-key,wakeup;
                };
                back {
                        label = "SW-TACT6";
                        gpios = <&gpx2 0 1>;
-                        linux,code = <158>;
+                        linux,code = <KEY_BACK>;
                        gpio-key,wakeup;
                };
                wakeup {
                        label = "SW-TACT7";
                        gpios = <&gpx2 1 1>;
-                        linux,code = <143>;
+                        linux,code = <KEY_WAKEUP>;
                        gpio-key,wakeup;
                };
        };
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 2c1560d52f1a..89ac90f59e2e 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -240,7 +240,7 @@
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <378000>;
-                hdmiphy@38 {
+                hdmiphy: hdmiphy@38 {
                        compatible = "samsung,exynos4212-hdmiphy";
                        reg = <0x38>;
                };
@@ -304,6 +304,10 @@
        hdmi {
                hpd-gpio = <&gpx3 7 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&hdmi_hpd_irq>;
+                phy = <&hdmiphy>;
+                ddc = <&i2c_2>;
        };
        gpio-keys {
diff --git a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
index 9a49e6804ae1..886cfca044ac 100644
--- a/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5250-pinctrl.dtsi
@@ -351,6 +351,34 @@
                        samsung,pin-drv = <0>;
                };
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpb2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpb2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpb2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpb2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
                i2c7_bus: i2c7-bus {
                        samsung,pins = "gpb2-2", "gpb2-3";
                        samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 1ce1088a00fb..079fdf9e3f18 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -25,6 +25,13 @@
        };
        pinctrl@11400000 {
+                ec_irq: ec-irq {
+                        samsung,pins = "gpx1-6";
+                        samsung,pin-function = <0>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
                sd3_clk: sd3-clk {
                        samsung,pin-drv = <0>;
                };
@@ -37,6 +44,50 @@
                sd3_bus4: sd3-bus-width4 {
                        samsung,pin-drv = <0>;
                };
+                max98095_en: max98095-en {
+                        samsung,pins = "gpx1-7";
+                        samsung,pin-function = <0>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                tps65090_irq: tps65090-irq {
+                        samsung,pins = "gpx2-6";
+                        samsung,pin-function = <0>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                usb3_vbus_en: usb3-vbus-en {
+                        samsung,pins = "gpx2-7";
+                        samsung,pin-function = <1>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                hdmi_hpd_irq: hdmi-hpd-irq {
+                        samsung,pins = "gpx3-7";
+                        samsung,pin-function = <0>;
+                        samsung,pin-pud = <1>;
+                        samsung,pin-drv = <0>;
+                };
+        };
+        pinctrl@13400000 {
+                arb_their_claim: arb-their-claim {
+                        samsung,pins = "gpe0-4";
+                        samsung,pin-function = <0>;
+                        samsung,pin-pud = <3>;
+                        samsung,pin-drv = <0>;
+                };
+                arb_our_claim: arb-our-claim {
+                        samsung,pins = "gpf0-3";
+                        samsung,pin-function = <1>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
        };
        gpio-keys {
@@ -52,6 +103,12 @@
                };
        };
+        vbat: vbat-fixed-regulator {
+                compatible = "regulator-fixed";
+                regulator-name = "vbat-supply";
+                regulator-boot-on;
+        };
        i2c-arbitrator {
                compatible = "i2c-arb-gpio-challenge";
                #address-cells = <1>;
@@ -65,6 +122,9 @@
                wait-retry-us = <3000>;
                wait-free-us = <50000>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&arb_our_claim &arb_their_claim>;
                /* Use ID 104 as a hint that we're on physical bus 4 */
                i2c_104: i2c@0 {
                        reg = <0>;
@@ -82,6 +142,8 @@
                                reg = <0x1e>;
                                interrupts = <6 0>;
                                interrupt-parent = <&gpx1>;
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&ec_irq>;
                                wakeup-source;
                                keyboard-controller {
@@ -173,6 +235,83 @@
                                                        0x070c0069>;    /* LEFT */
                                };
                        };
+                        power-regulator {
+                                compatible = "ti,tps65090";
+                                reg = <0x48>;
+                                /*
+                                 * Config irq to disable internal pulls
+                                 * even though we run in polling mode.
+                                 */
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&tps65090_irq>;
+                                vsys1-supply = <&vbat>;
+                                vsys2-supply = <&vbat>;
+                                vsys3-supply = <&vbat>;
+                                infet1-supply = <&vbat>;
+                                infet2-supply = <&vbat>;
+                                infet3-supply = <&vbat>;
+                                infet4-supply = <&vbat>;
+                                infet5-supply = <&vbat>;
+                                infet6-supply = <&vbat>;
+                                infet7-supply = <&vbat>;
+                                vsys-l1-supply = <&vbat>;
+                                vsys-l2-supply = <&vbat>;
+                                regulators {
+                                        dcdc1 {
+                                                ti,enable-ext-control;
+                                        };
+                                        dcdc2 {
+                                                ti,enable-ext-control;
+                                        };
+                                        dcdc3 {
+                                                ti,enable-ext-control;
+                                        };
+                                        fet1 {
+                                                regulator-name = "vcd_led";
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        tps65090_fet2: fet2 {
+                                                regulator-name = "video_mid";
+                                                regulator-always-on;
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        fet3 {
+                                                regulator-name = "wwan_r";
+                                                regulator-always-on;
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        fet4 {
+                                                regulator-name = "sdcard";
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        fet5 {
+                                                regulator-name = "camout";
+                                                regulator-always-on;
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        fet6 {
+                                                regulator-name = "lcd_vdd";
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        tps65090_fet7: fet7 {
+                                                regulator-name = "video_mid_1a";
+                                                regulator-always-on;
+                                                ti,overcurrent-wait = <3>;
+                                        };
+                                        ldo1 {
+                                        };
+                                        ldo2 {
+                                        };
+                                };
+                                charger {
+                                        compatible = "ti,tps65090-charger";
+                                };
+                        };
                };
        };
@@ -196,6 +335,41 @@
                };
        };
+        i2c@12CD0000 {
+                max98095: codec@11 {
+                        compatible = "maxim,max98095";
+                        reg = <0x11>;
+                        pinctrl-0 = <&max98095_en>;
+                        pinctrl-names = "default";
+                };
+        };
+        i2s0: i2s@03830000 {
+                status = "okay";
+        };
+        sound {
+                compatible = "google,snow-audio-max98095";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&max98095>;
+        };
+        usb3_vbus_reg: regulator-usb3 {
+                compatible = "regulator-fixed";
+                regulator-name = "P5.0V_USB3CON";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpx2 7 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb3_vbus_en>;
+                enable-active-high;
+        };
+        phy@12100000 {
+                vbus-supply = <&usb3_vbus_reg>;
+        };
        usb@12110000 {
                samsung,vbus-gpio = <&gpx1 1 0>;
        };
@@ -206,4 +380,54 @@
                        clock-frequency = <24000000>;
                };
        };
+        hdmi {
+                hdmi-en-supply = <&tps65090_fet7>;
+                vdd-supply = <&ldo8_reg>;
+                vdd_osc-supply = <&ldo10_reg>;
+                vdd_pll-supply = <&ldo8_reg>;
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 1000000 0>;
+                brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+                default-brightness-level = <7>;
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+        };
+        fimd@14400000 {
+                status = "okay";
+                samsung,invert-vclk;
+        };
+        dp-controller@145B0000 {
+                status = "okay";
+                pinctrl-names = "default";
+                pinctrl-0 = <&dp_hpd>;
+                samsung,color-space = <0>;
+                samsung,dynamic-range = <0>;
+                samsung,ycbcr-coeff = <0>;
+                samsung,color-depth = <1>;
+                samsung,link-rate = <0x0a>;
+                samsung,lane-count = <2>;
+                samsung,hpd-gpio = <&gpx0 7 0>;
+                display-timings {
+                        native-mode = <&timing1>;
+                        timing1: timing@1 {
+                                clock-frequency = <70589280>;
+                                hactive = <1366>;
+                                vactive = <768>;
+                                hfront-porch = <40>;
+                                hback-porch = <40>;
+                                hsync-len = <32>;
+                                vback-porch = <10>;
+                                vfront-porch = <12>;
+                                vsync-len = <6>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 37423314a028..834fb5a5306f 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -72,6 +72,24 @@
                };
        };
+        sysram@02020000 {
+                compatible = "mmio-sram";
+                reg = <0x02020000 0x30000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x02020000 0x30000>;
+                smp-sysram@0 {
+                        compatible = "samsung,exynos4210-sysram";
+                        reg = <0x0 0x1000>;
+                };
+                smp-sysram@2f000 {
+                        compatible = "samsung,exynos4210-sysram-ns";
+                        reg = <0x2f000 0x1000>;
+                };
+        };
        pd_gsc: gsc-power-domain@10044000 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10044000 0x20>;
@@ -175,6 +193,11 @@
                reg = <0x10040000 0x5000>;
        };
+        sysreg_system_controller: syscon@10050000 {
+                compatible = "samsung,exynos5-sysreg", "syscon";
+                reg = <0x10050000 0x5000>;
+        };
        watchdog@101D0000 {
                compatible = "samsung,exynos5250-wdt";
                reg = <0x101D0000 0x100>;
@@ -250,7 +273,7 @@
        sata_phy: sata-phy@12170000 {
                compatible = "samsung,exynos5250-sata-phy";
                reg = <0x12170000 0x1ff>;
-                clocks = <&clock 287>;
+                clocks = <&clock CLK_SATA_PHYCTRL>;
                clock-names = "sata_phyctrl";
                #phy-cells = <0>;
                samsung,syscon-phandle = <&pmu_system_controller>;
@@ -533,22 +556,18 @@
                        compatible = "synopsys,dwc3";
                        reg = <0x12000000 0x10000>;
                        interrupts = <0 72 0>;
-                        usb-phy = <&usb2_phy &usb3_phy>;
+                        phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>;
+                        phy-names = "usb2-phy", "usb3-phy";
                };
        };
-        usb3_phy: usbphy@12100000 {
+        usbdrd_phy: phy@12100000 {
-                compatible = "samsung,exynos5250-usb3phy";
+                compatible = "samsung,exynos5250-usbdrd-phy";
                reg = <0x12100000 0x100>;
-                clocks = <&clock CLK_FIN_PLL>, <&clock CLK_USB3>;
+                clocks = <&clock CLK_USB3>, <&clock CLK_FIN_PLL>;
-                clock-names = "ext_xtal", "usbdrd30";
+                clock-names = "phy", "ref";
-                #address-cells = <1>;
+                samsung,pmu-syscon = <&pmu_system_controller>;
-                #size-cells = <1>;
+                #phy-cells = <1>;
-                ranges;
-                usbphy-sys {
-                        reg = <0x10040704 0x8>;
-                };
        };
        usb@12110000 {
@@ -558,6 +577,12 @@
                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        phys = <&usb2_phy_gen 1>;
+                };
        };
        usb@12120000 {
@@ -567,6 +592,12 @@
                clocks = <&clock CLK_USB2>;
                clock-names = "usbhost";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        phys = <&usb2_phy_gen 1>;
+                };
        };
        usb2_phy: usbphy@12130000 {
@@ -584,6 +615,16 @@
                };
        };
+        usb2_phy_gen: phy@12130000 {
+                compatible = "samsung,exynos5250-usb2-phy";
+                reg = <0x12130000 0x100>;
+                clocks = <&clock CLK_USB2>, <&clock CLK_FIN_PLL>;
+                clock-names = "phy", "ref";
+                #phy-cells = <1>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
+                samsung,pmureg-phandle = <&pmu_system_controller>;
+        };
        pwm: pwm@12dd0000 {
                compatible = "samsung,exynos4210-pwm";
                reg = <0x12dd0000 0x100>;
@@ -690,6 +731,7 @@
                         <&clock CLK_MOUT_HDMI>;
                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
                                "sclk_hdmiphy", "mout_hdmi";
+                samsung,syscon-phandle = <&pmu_system_controller>;
        };
        mixer {
@@ -733,7 +775,7 @@
                compatible = "samsung,exynos4210-secss";
                reg = <0x10830000 0x10000>;
                interrupts = <0 112 0>;
-                clocks = <&clock 348>;
+                clocks = <&clock CLK_SSS>;
                clock-names = "secss";
        };
 };
diff --git a/arch/arm/boot/dts/exynos5260-pinctrl.dtsi b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
new file mode 100644
index 000000000000..f6ee55ea0708
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-pinctrl.dtsi
@@ -0,0 +1,574 @@
+/*
+ * Samsung's Exynos5260 SoC pin-mux and pin-config device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * Samsung's Exynos5260 SoC pin-mux and pin-config options are listed as device
+ * tree nodes are listed in this file.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define PIN_PULL_NONE   0
+#define PIN_PULL_DOWN   1
+#define PIN_PULL_UP     3
+&pinctrl_0 {
+        gpa0: gpa0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpa1: gpa1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpa2: gpa2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb0: gpb0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb1: gpb1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb2: gpb2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb3: gpb3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb4: gpb4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpb5: gpb5 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd0: gpd0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd1: gpd1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpd2: gpd2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpe0: gpe0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpe1: gpe1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpf0: gpf0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpf1: gpf1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpk0: gpk0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx0: gpx0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx1: gpx1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx2: gpx2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpx3: gpx3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        uart0_data: uart0-data {
+                samsung,pins = "gpa0-0", "gpa0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        uart0_fctl: uart0-fctl {
+                samsung,pins = "gpa0-2", "gpa0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_data: uart1-data {
+                samsung,pins = "gpa1-0", "gpa1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        uart1_fctl: uart1-fctl {
+                samsung,pins = "gpa1-2", "gpa1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        uart2_data: uart2-data {
+                samsung,pins = "gpa1-4", "gpa1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        spi0_bus: spi0-bus {
+                samsung,pins = "gpa2-0", "gpa2-2", "gpa2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        spi1_bus: spi1-bus {
+                samsung,pins = "gpa2-4", "gpa2-6", "gpa2-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        usb3_vbus0_en: usb3-vbus0-en {
+                samsung,pins = "gpa2-4";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        i2s1_bus: i2s1-bus {
+                samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                "gpb0-4";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        pcm1_bus: pcm1-bus {
+                samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2", "gpb0-3",
+                                "gpb0-4";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        spdif1_bus: spdif1-bus {
+                samsung,pins = "gpb0-0", "gpb0-1", "gpb0-2";
+                samsung,pin-function = <4>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        spi2_bus: spi2-bus {
+                samsung,pins = "gpb1-0", "gpb1-2", "gpb1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c0_hs_bus: i2c0-hs-bus {
+                samsung,pins = "gpb3-0", "gpb3-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c1_hs_bus: i2c1-hs-bus {
+                samsung,pins = "gpb3-2", "gpb3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c2_hs_bus: i2c2-hs-bus {
+                samsung,pins = "gpb3-4", "gpb3-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c3_hs_bus: i2c3-hs-bus {
+                samsung,pins = "gpb3-6", "gpb3-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c4_bus: i2c4-bus {
+                samsung,pins = "gpb4-0", "gpb4-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c5_bus: i2c5-bus {
+                samsung,pins = "gpb4-2", "gpb4-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c6_bus: i2c6-bus {
+                samsung,pins = "gpb4-4", "gpb4-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c7_bus: i2c7-bus {
+                samsung,pins = "gpb4-6", "gpb4-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c8_bus: i2c8-bus {
+                samsung,pins = "gpb5-0", "gpb5-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c9_bus: i2c9-bus {
+                samsung,pins = "gpb5-2", "gpb5-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c10_bus: i2c10-bus {
+                samsung,pins = "gpb5-4", "gpb5-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        i2c11_bus: i2c11-bus {
+                samsung,pins = "gpb5-6", "gpb5-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        cam_gpio_a: cam-gpio-a {
+                samsung,pins = "gpe0-0", "gpe0-1", "gpe0-2", "gpe0-3",
+                        "gpe0-4", "gpe0-5", "gpe0-6", "gpe0-7",
+                        "gpe1-0", "gpe1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        cam_gpio_b: cam-gpio-b {
+                samsung,pins = "gpf0-0", "gpf0-1", "gpf0-2", "gpf0-3",
+                        "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                samsung,pin-function = <3>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        cam_i2c1_bus: cam-i2c1-bus {
+                samsung,pins = "gpf0-2", "gpf0-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        cam_i2c0_bus: cam-i2c0-bus {
+                samsung,pins = "gpf0-0", "gpf0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <0>;
+        };
+        cam_spi0_bus: cam-spi0-bus {
+                samsung,pins = "gpf1-0", "gpf1-1", "gpf1-2", "gpf1-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+        cam_spi1_bus: cam-spi1-bus {
+                samsung,pins = "gpf1-4", "gpf1-5", "gpf1-6", "gpf1-7";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_1 {
+        gpc0: gpc0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc1: gpc1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc2: gpc2 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc3: gpc3 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpc4: gpc4 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        sd0_clk: sd0-clk {
+                samsung,pins = "gpc0-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_cmd: sd0-cmd {
+                samsung,pins = "gpc0-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus1: sd0-bus-width1 {
+                samsung,pins = "gpc0-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus4: sd0-bus-width4 {
+                samsung,pins = "gpc0-3", "gpc0-4", "gpc0-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_bus8: sd0-bus-width8 {
+                samsung,pins = "gpc3-0", "gpc3-1", "gpc3-2", "gpc3-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd0_rdqs: sd0-rdqs {
+                samsung,pins = "gpc0-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_clk: sd1-clk {
+                samsung,pins = "gpc1-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_cmd: sd1-cmd {
+                samsung,pins = "gpc1-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus1: sd1-bus-width1 {
+                samsung,pins = "gpc1-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus4: sd1-bus-width4 {
+                samsung,pins = "gpc1-3", "gpc1-4", "gpc1-5";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd1_bus8: sd1-bus-width8 {
+                samsung,pins = "gpc4-0", "gpc4-1", "gpc4-2", "gpc4-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_clk: sd2-clk {
+                samsung,pins = "gpc2-0";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_cmd: sd2-cmd {
+                samsung,pins = "gpc2-1";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_NONE>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_cd: sd2-cd {
+                samsung,pins = "gpc2-2";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_bus1: sd2-bus-width1 {
+                samsung,pins = "gpc2-3";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+        sd2_bus4: sd2-bus-width4 {
+                samsung,pins = "gpc2-4", "gpc2-5", "gpc2-6";
+                samsung,pin-function = <2>;
+                samsung,pin-pud = <PIN_PULL_UP>;
+                samsung,pin-drv = <3>;
+        };
+};
+&pinctrl_2 {
+        gpz0: gpz0 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+        gpz1: gpz1 {
+                gpio-controller;
+                #gpio-cells = <2>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts
new file mode 100644
index 000000000000..8c84ab27c19b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts
@@ -0,0 +1,103 @@
+/*
+ * SAMSUNG XYREF5260 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+#include "exynos5260.dtsi"
+/ {
+        model = "SAMSUNG XYREF5260 board based on EXYNOS5260";
+        compatible = "samsung,xyref5260", "samsung,exynos5260", "samsung,exynos5";
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+        fin_pll: xxti {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "fin_pll";
+                #clock-cells = <0>;
+        };
+        xrtcxti: xrtcxti {
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+                clock-output-names = "xrtcxti";
+                #clock-cells = <0>;
+        };
+};
+&pinctrl_0 {
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+&uart0 {
+        status = "okay";
+};
+&uart1 {
+        status = "okay";
+};
+&uart2 {
+        status = "okay";
+};
+&uart3 {
+        status = "okay";
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        bypass-smu;
+        supports-highspeed;
+        supports-hs200-mode; /* 200 Mhz */
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_rdqs &sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+                disable-wp;
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
new file mode 100644
index 000000000000..5398a60207ca
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -0,0 +1,304 @@
+/*
+ * SAMSUNG EXYNOS5260 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos5260-clk.h>
+/ {
+        compatible = "samsung,exynos5260", "samsung,exynos5";
+        interrupt-parent = <&gic>;
+        aliases {
+                pinctrl0 = &pinctrl_0;
+                pinctrl1 = &pinctrl_1;
+                pinctrl2 = &pinctrl_2;
+        };
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                        cci-control-port = <&cci_control1>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                        cci-control-port = <&cci_control1>;
+                };
+                cpu@100 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                        cci-control-port = <&cci_control0>;
+                };
+                cpu@101 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                        cci-control-port = <&cci_control0>;
+                };
+                cpu@102 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x102>;
+                        cci-control-port = <&cci_control0>;
+                };
+                cpu@103 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x103>;
+                        cci-control-port = <&cci_control0>;
+                };
+        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                clock_top: clock-controller@10010000 {
+                        compatible = "samsung,exynos5260-clock-top";
+                        reg = <0x10010000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_peri: clock-controller@10200000 {
+                        compatible = "samsung,exynos5260-clock-peri";
+                        reg = <0x10200000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_egl: clock-controller@10600000 {
+                        compatible = "samsung,exynos5260-clock-egl";
+                        reg = <0x10600000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_kfc: clock-controller@10700000 {
+                        compatible = "samsung,exynos5260-clock-kfc";
+                        reg = <0x10700000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_g2d: clock-controller@10A00000 {
+                        compatible = "samsung,exynos5260-clock-g2d";
+                        reg = <0x10A00000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_mif: clock-controller@10CE0000 {
+                        compatible = "samsung,exynos5260-clock-mif";
+                        reg = <0x10CE0000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_mfc: clock-controller@11090000 {
+                        compatible = "samsung,exynos5260-clock-mfc";
+                        reg = <0x11090000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_g3d: clock-controller@11830000 {
+                        compatible = "samsung,exynos5260-clock-g3d";
+                        reg = <0x11830000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_fsys: clock-controller@122E0000 {
+                        compatible = "samsung,exynos5260-clock-fsys";
+                        reg = <0x122E0000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_aud: clock-controller@128C0000 {
+                        compatible = "samsung,exynos5260-clock-aud";
+                        reg = <0x128C0000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_isp: clock-controller@133C0000 {
+                        compatible = "samsung,exynos5260-clock-isp";
+                        reg = <0x133C0000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_gscl: clock-controller@13F00000 {
+                        compatible = "samsung,exynos5260-clock-gscl";
+                        reg = <0x13F00000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                clock_disp: clock-controller@14550000 {
+                        compatible = "samsung,exynos5260-clock-disp";
+                        reg = <0x14550000 0x10000>;
+                        #clock-cells = <1>;
+                };
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        #address-cells = <0>;
+                        #size-cells = <0>;
+                        interrupt-controller;
+                        reg = <0x10481000 0x1000>,
+                                <0x10482000 0x1000>,
+                                <0x10484000 0x2000>,
+                                <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
+                chipid: chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
+                mct: mct@100B0000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x100B0000 0x1000>;
+                        clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+                        interrupts = <0 104 0>, <0 105 0>, <0 106 0>,
+                                        <0 107 0>, <0 122 0>, <0 123 0>,
+                                        <0 124 0>, <0 125 0>, <0 126 0>,
+                                        <0 127 0>, <0 128 0>, <0 129 0>;
+                };
+                cci: cci@10F00000 {
+                        compatible = "arm,cci-400";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x10F00000 0x1000>;
+                        ranges = <0x0 0x10F00000 0x6000>;
+                        cci_control0: slave-if@4000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x4000 0x1000>;
+                        };
+                        cci_control1: slave-if@5000 {
+                                compatible = "arm,cci-400-ctrl-if";
+                                interface-type = "ace";
+                                reg = <0x5000 0x1000>;
+                        };
+                };
+                pinctrl_0: pinctrl@11600000 {
+                        compatible = "samsung,exynos5260-pinctrl";
+                        reg = <0x11600000 0x1000>;
+                        interrupts = <0 79 0>;
+                        wakeup-interrupt-controller {
+                                compatible = "samsung,exynos4210-wakeup-eint";
+                                interrupt-parent = <&gic>;
+                                interrupts = <0 32 0>;
+                        };
+                };
+                pinctrl_1: pinctrl@12290000 {
+                        compatible = "samsung,exynos5260-pinctrl";
+                        reg = <0x12290000 0x1000>;
+                        interrupts = <0 157 0>;
+                };
+                pinctrl_2: pinctrl@128B0000 {
+                        compatible = "samsung,exynos5260-pinctrl";
+                        reg = <0x128B0000 0x1000>;
+                        interrupts = <0 243 0>;
+                };
+                uart0: serial@12C00000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C00000 0x100>;
+                        interrupts = <0 146 0>;
+                        clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                uart1: serial@12C10000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C10000 0x100>;
+                        interrupts = <0 147 0>;
+                        clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                uart2: serial@12C20000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C20000 0x100>;
+                        interrupts = <0 148 0>;
+                        clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                uart3: serial@12860000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12860000 0x100>;
+                        interrupts = <0 145 0>;
+                        clocks = <&clock_aud AUD_CLK_AUD_UART>, <&clock_aud AUD_SCLK_AUD_UART>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                mmc_0: mmc@12140000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12140000 0x2000>;
+                        interrupts = <0 156 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock_fsys FSYS_CLK_MMC0>, <&clock_top TOP_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <64>;
+                        status = "disabled";
+                };
+                mmc_1: mmc@12150000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12150000 0x2000>;
+                        interrupts = <0 158 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock_fsys FSYS_CLK_MMC1>, <&clock_top TOP_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <64>;
+                        status = "disabled";
+                };
+                mmc_2: mmc@12160000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12160000 0x2000>;
+                        interrupts = <0 159 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock_fsys FSYS_CLK_MMC2>, <&clock_top TOP_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <64>;
+                        status = "disabled";
+                };
+        };
+};
+#include "exynos5260-pinctrl.dtsi"
diff --git a/arch/arm/boot/dts/exynos5410-smdk5410.dts b/arch/arm/boot/dts/exynos5410-smdk5410.dts
new file mode 100644
index 000000000000..7275bbd6fc4b
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410-smdk5410.dts
@@ -0,0 +1,82 @@
+/*
+ * SAMSUNG SMDK5410 board device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/dts-v1/;
+#include "exynos5410.dtsi"
+/ {
+        model = "Samsung SMDK5410 board based on EXYNOS5410";
+        compatible = "samsung,smdk5410", "samsung,exynos5410", "samsung,exynos5";
+        memory {
+                reg = <0x40000000 0x80000000>;
+        };
+        chosen {
+                bootargs = "console=ttySAC2,115200";
+        };
+        fin_pll: xxti {
+                compatible = "fixed-clock";
+                clock-frequency = <24000000>;
+                clock-output-names = "fin_pll";
+                #clock-cells = <0>;
+        };
+        firmware@02037000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x02037000 0x1000>;
+        };
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        broken-cd;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        card-detect-delay = <200>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+                disable-wp;
+        };
+};
+&uart0 {
+                status = "okay";
+};
+&uart1 {
+                status = "okay";
+};
+&uart2 {
+                status = "okay";
+};
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
new file mode 100644
index 000000000000..3839c26f467f
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -0,0 +1,206 @@
+/*
+ * SAMSUNG EXYNOS5410 SoC device tree source
+ *
+ * Copyright (c) 2013 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
+ * EXYNOS5410 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/exynos5410.h>
+/ {
+        compatible = "samsung,exynos5410", "samsung,exynos5";
+        interrupt-parent = <&gic>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                CPU0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x0>;
+                };
+                CPU1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x1>;
+                };
+                CPU2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x2>;
+                };
+                CPU3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0x3>;
+                };
+        };
+        soc: soc {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                combiner: interrupt-controller@10440000 {
+                        compatible = "samsung,exynos4210-combiner";
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        samsung,combiner-nr = <32>;
+                        reg = <0x10440000 0x1000>;
+                        interrupts =    <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                                        <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                                        <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                                        <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
+                                        <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
+                                        <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
+                                        <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
+                                        <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
+                };
+                gic: interrupt-controller@10481000 {
+                        compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                        #interrupt-cells = <3>;
+                        interrupt-controller;
+                        reg =   <0x10481000 0x1000>,
+                                <0x10482000 0x1000>,
+                                <0x10484000 0x2000>,
+                                <0x10486000 0x2000>;
+                        interrupts = <1 9 0xf04>;
+                };
+                chipid@10000000 {
+                        compatible = "samsung,exynos4210-chipid";
+                        reg = <0x10000000 0x100>;
+                };
+                mct: mct@101C0000 {
+                        compatible = "samsung,exynos4210-mct";
+                        reg = <0x101C0000 0xB00>;
+                        interrupt-parent = <&interrupt_map>;
+                        interrupts = <0>, <1>, <2>, <3>,
+                                <4>, <5>, <6>, <7>,
+                                <8>, <9>, <10>, <11>;
+                        clocks = <&fin_pll>, <&clock CLK_MCT>;
+                        clock-names = "fin_pll", "mct";
+                        interrupt_map: interrupt-map {
+                                #interrupt-cells = <1>;
+                                #address-cells = <0>;
+                                #size-cells = <0>;
+                                interrupt-map = <0 &combiner 23 3>,
+                                                <1 &combiner 23 4>,
+                                                <2 &combiner 25 2>,
+                                                <3 &combiner 25 3>,
+                                                <4 &gic 0 120 0>,
+                                                <5 &gic 0 121 0>,
+                                                <6 &gic 0 122 0>,
+                                                <7 &gic 0 123 0>,
+                                                <8 &gic 0 128 0>,
+                                                <9 &gic 0 129 0>,
+                                                <10 &gic 0 130 0>,
+                                                <11 &gic 0 131 0>;
+                        };
+                };
+                sysram@02020000 {
+                        compatible = "mmio-sram";
+                        reg = <0x02020000 0x54000>;
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges = <0 0x02020000 0x54000>;
+                        smp-sysram@0 {
+                                compatible = "samsung,exynos4210-sysram";
+                                reg = <0x0 0x1000>;
+                        };
+                        smp-sysram@53000 {
+                                compatible = "samsung,exynos4210-sysram-ns";
+                                reg = <0x53000 0x1000>;
+                        };
+                };
+                clock: clock-controller@10010000 {
+                        compatible = "samsung,exynos5410-clock";
+                        reg = <0x10010000 0x30000>;
+                        #clock-cells = <1>;
+                };
+                mmc_0: mmc@12200000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12200000 0x1000>;
+                        interrupts = <0 75 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
+                mmc_1: mmc@12210000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12210000 0x1000>;
+                        interrupts = <0 76 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
+                mmc_2: mmc@12220000 {
+                        compatible = "samsung,exynos5250-dw-mshc";
+                        reg = <0x12220000 0x1000>;
+                        interrupts = <0 77 0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
+                        clock-names = "biu", "ciu";
+                        fifo-depth = <0x80>;
+                        status = "disabled";
+                };
+                uart0: serial@12C00000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C00000 0x100>;
+                        interrupts = <0 51 0>;
+                        clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                uart1: serial@12C10000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C10000 0x100>;
+                        interrupts = <0 52 0>;
+                        clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+                uart2: serial@12C20000 {
+                        compatible = "samsung,exynos4210-uart";
+                        reg = <0x12C20000 0x100>;
+                        interrupts = <0 53 0>;
+                        clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
+                        clock-names = "uart", "clk_uart_baud0";
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-arndale-octa.dts b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
index 80a3bf4c5986..434fd9d3e09d 100644
--- a/arch/arm/boot/dts/exynos5420-arndale-octa.dts
+++ b/arch/arm/boot/dts/exynos5420-arndale-octa.dts
@@ -26,6 +26,11 @@
                bootargs = "console=ttySAC3,115200";
        };
+        firmware@02073000 {
+                compatible = "samsung,secure-firmware";
+                reg = <0x02073000 0x1000>;
+        };
        fixed-rate-clocks {
                oscclk {
                        compatible = "samsung,exynos5420-oscclk";
@@ -37,6 +42,11 @@
                status = "okay";
        };
+        codec@11000000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+        };
        mmc@12200000 {
                status = "okay";
                broken-cd;
@@ -364,16 +374,4 @@
                        gpio-key,wakeup;
                };
        };
-        amba {
-                mdma1: mdma@11C10000 {
-                        /*
-                         * MDMA1 can support both secure and non-secure
-                         * AXI transactions. When this is enabled in the kernel
-                         * for boards that run in secure mode, we are getting
-                         * imprecise external aborts causing the kernel to oops.
-                         */
-                        status = "disabled";
-                };
-        };
 };
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
new file mode 100644
index 000000000000..1c5b8f9f4a36
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -0,0 +1,287 @@
+/*
+ * Google Peach Pit Rev 6+ board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "exynos5420.dtsi"
+/ {
+        model = "Google Peach Pit Rev 6+";
+        compatible = "google,pit-rev16",
+                "google,pit-rev15", "google,pit-rev14",
+                "google,pit-rev13", "google,pit-rev12",
+                "google,pit-rev11", "google,pit-rev10",
+                "google,pit-rev9", "google,pit-rev8",
+                "google,pit-rev7", "google,pit-rev6",
+                "google,pit", "google,peach","samsung,exynos5420",
+                "samsung,exynos5";
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&power_key_irq>;
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 1000000 0>;
+                brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+                default-brightness-level = <7>;
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+        };
+        sound {
+                compatible = "google,snow-audio-max98090";
+                samsung,i2s-controller = <&i2s0>;
+                samsung,audio-codec = <&max98090>;
+        };
+        usb300_vbus_reg: regulator-usb300 {
+                compatible = "regulator-fixed";
+                regulator-name = "P5.0V_USB3CON0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gph0 0 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb300_vbus_en>;
+                enable-active-high;
+        };
+        usb301_vbus_reg: regulator-usb301 {
+                compatible = "regulator-fixed";
+                regulator-name = "P5.0V_USB3CON1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gph0 1 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb301_vbus_en>;
+                enable-active-high;
+        };
+};
+&pinctrl_0 {
+        max98090_irq: max98090-irq {
+                samsung,pins = "gpx0-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        tpm_irq: tpm-irq {
+                samsung,pins = "gpx1-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        power_key_irq: power-key-irq {
+                samsung,pins = "gpx1-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+        dp_hpd_gpio: dp_hpd_gpio {
+                samsung,pins = "gpx2-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_3 {
+        usb300_vbus_en: usb300-vbus-en {
+                samsung,pins = "gph0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        usb301_vbus_en: usb301-vbus-en {
+                samsung,pins = "gph0-1";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+&rtc {
+        status = "okay";
+};
+&uart_3 {
+        status = "okay";
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        caps2-mmc-hs200-1_8v;
+        supports-highspeed;
+        non-removable;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+        };
+};
+&hsi2c_7 {
+        status = "okay";
+        max98090: codec@10 {
+                compatible = "maxim,max98090";
+                reg = <0x10>;
+                interrupts = <2 0>;
+                interrupt-parent = <&gpx0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&max98090_irq>;
+        };
+};
+&hsi2c_9 {
+        status = "okay";
+        clock-frequency = <400000>;
+        tpm@20 {
+                compatible = "infineon,slb9645tt";
+                reg = <0x20>;
+                /* Unused irq; but still need to configure the pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tpm_irq>;
+        };
+};
+&i2c_2  {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x50>;
+};
+&hdmi {
+        status = "okay";
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        ddc = <&i2c_2>;
+};
+&usbdrd_phy0 {
+        vbus-supply = <&usb300_vbus_reg>;
+};
+&usbdrd_phy1 {
+        vbus-supply = <&usb301_vbus_reg>;
+};
+/*
+ * Use longest HW watchdog in SoC (32 seconds) since the hardware
+ * watchdog provides no debugging information (compared to soft/hard
+ * lockup detectors) and so should be last resort.
+ */
+&watchdog {
+        timeout-sec = <32>;
+};
+&i2s0 {
+        status = "okay";
+};
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+&dp {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd_gpio>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x06>;
+        samsung,lane-count = <2>;
+        samsung,hpd-gpio = <&gpx2 6 0>;
+        display-timings {
+                native-mode = <&timing1>;
+                timing1: timing@1 {
+                        clock-frequency = <70589280>;
+                        hactive = <1366>;
+                        vactive = <768>;
+                        hfront-porch = <40>;
+                        hback-porch = <40>;
+                        hsync-len = <32>;
+                        vback-porch = <10>;
+                        vfront-porch = <12>;
+                        vsync-len = <6>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index e62c8eb57438..ba686e40eac7 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -624,6 +624,34 @@
                        samsung,pin-drv = <0>;
                };
+                pwm0_out: pwm0-out {
+                        samsung,pins = "gpb2-0";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm1_out: pwm1-out {
+                        samsung,pins = "gpb2-1";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm2_out: pwm2-out {
+                        samsung,pins = "gpb2-2";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                pwm3_out: pwm3-out {
+                        samsung,pins = "gpb2-3";
+                        samsung,pin-function = <2>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
                i2c7_hs_bus: i2c7-hs-bus {
                        samsung,pins = "gpb2-2", "gpb2-3";
                        samsung,pin-function = <3>;
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 69104850eb5e..6052aa9c5659 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -68,6 +68,11 @@
                status = "okay";
        };
+        codec@11000000 {
+                samsung,mfc-r = <0x43000000 0x800000>;
+                samsung,mfc-l = <0x51000000 0x800000>;
+        };
        mmc@12200000 {
                status = "okay";
                broken-cd;
@@ -140,6 +145,22 @@
                };
        };
+        pinctrl@14000000 {
+                usb300_vbus_en: usb300-vbus-en {
+                        samsung,pins = "gpg0-5";
+                        samsung,pin-function = <1>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+                usb301_vbus_en: usb301-vbus-en {
+                        samsung,pins = "gpg1-4";
+                        samsung,pin-function = <1>;
+                        samsung,pin-pud = <0>;
+                        samsung,pin-drv = <0>;
+                };
+        };
        hdmi@14530000 {
                status = "okay";
                hpd-gpio = <&gpx3 7 0>;
@@ -147,6 +168,36 @@
                pinctrl-0 = <&hdmi_hpd_irq>;
        };
+        usb300_vbus_reg: regulator-usb300 {
+                compatible = "regulator-fixed";
+                regulator-name = "VBUS0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpg0 5 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb300_vbus_en>;
+                enable-active-high;
+        };
+        usb301_vbus_reg: regulator-usb301 {
+                compatible = "regulator-fixed";
+                regulator-name = "VBUS1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gpg1 4 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb301_vbus_en>;
+                enable-active-high;
+        };
+        phy@12100000 {
+                vbus-supply = <&usb300_vbus_reg>;
+        };
+        phy@12500000 {
+                vbus-supply = <&usb301_vbus_reg>;
+        };
        i2c_2: i2c@12C80000 {
                samsung,i2c-sda-delay = <100>;
                samsung,i2c-max-bus-freq = <66000>;
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index c3a9a66c5767..e38532271ef9 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -47,6 +47,8 @@
                spi0 = &spi_0;
                spi1 = &spi_1;
                spi2 = &spi_2;
+                usbdrdphy0 = &usbdrd_phy0;
+                usbdrdphy1 = &usbdrd_phy1;
        };
        cpus {
@@ -58,6 +60,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <0x0>;
                        clock-frequency = <1800000000>;
+                        cci-control-port = <&cci_control1>;
                };
                cpu1: cpu@1 {
@@ -65,6 +68,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <0x1>;
                        clock-frequency = <1800000000>;
+                        cci-control-port = <&cci_control1>;
                };
                cpu2: cpu@2 {
@@ -72,6 +76,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <0x2>;
                        clock-frequency = <1800000000>;
+                        cci-control-port = <&cci_control1>;
                };
                cpu3: cpu@3 {
@@ -79,6 +84,7 @@
                        compatible = "arm,cortex-a15";
                        reg = <0x3>;
                        clock-frequency = <1800000000>;
+                        cci-control-port = <&cci_control1>;
                };
                cpu4: cpu@100 {
@@ -86,6 +92,7 @@
                        compatible = "arm,cortex-a7";
                        reg = <0x100>;
                        clock-frequency = <1000000000>;
+                        cci-control-port = <&cci_control0>;
                };
                cpu5: cpu@101 {
@@ -93,6 +100,7 @@
                        compatible = "arm,cortex-a7";
                        reg = <0x101>;
                        clock-frequency = <1000000000>;
+                        cci-control-port = <&cci_control0>;
                };
                cpu6: cpu@102 {
@@ -100,6 +108,7 @@
                        compatible = "arm,cortex-a7";
                        reg = <0x102>;
                        clock-frequency = <1000000000>;
+                        cci-control-port = <&cci_control0>;
                };
                cpu7: cpu@103 {
@@ -107,6 +116,44 @@
                        compatible = "arm,cortex-a7";
                        reg = <0x103>;
                        clock-frequency = <1000000000>;
+                        cci-control-port = <&cci_control0>;
+                };
+        };
+        cci@10d20000 {
+                compatible = "arm,cci-400";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                reg = <0x10d20000 0x1000>;
+                ranges = <0x0 0x10d20000 0x6000>;
+                cci_control0: slave-if@4000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x4000 0x1000>;
+                };
+                cci_control1: slave-if@5000 {
+                        compatible = "arm,cci-400-ctrl-if";
+                        interface-type = "ace";
+                        reg = <0x5000 0x1000>;
+                };
+        };
+        sysram@02020000 {
+                compatible = "mmio-sram";
+                reg = <0x02020000 0x54000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges = <0 0x02020000 0x54000>;
+                smp-sysram@0 {
+                        compatible = "samsung,exynos4210-sysram";
+                        reg = <0x0 0x1000>;
+                };
+                smp-sysram@53000 {
+                        compatible = "samsung,exynos4210-sysram-ns";
+                        reg = <0x53000 0x1000>;
                };
        };
@@ -125,12 +172,13 @@
                clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
        };
-        codec@11000000 {
+        mfc: codec@11000000 {
                compatible = "samsung,mfc-v7";
                reg = <0x11000000 0x10000>;
                interrupts = <0 96 0>;
                clocks = <&clock CLK_MFC>;
                clock-names = "mfc";
+                samsung,power-domain = <&mfc_pd>;
        };
        mmc_0: mmc@12200000 {
@@ -169,7 +217,7 @@
                status = "disabled";
        };
-        mct@101C0000 {
+        mct: mct@101C0000 {
                compatible = "samsung,exynos4210-mct";
                reg = <0x101C0000 0x800>;
                interrupt-controller;
@@ -219,16 +267,6 @@
                reg = <0x100440C0 0x20>;
        };
-        mau_pd: power-domain@100440E0 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x100440E0 0x20>;
-        };
-        g2d_pd: power-domain@10044100 {
-                compatible = "samsung,exynos4210-pd";
-                reg = <0x10044100 0x20>;
-        };
        msc_pd: power-domain@10044120 {
                compatible = "samsung,exynos4210-pd";
                reg = <0x10044120 0x20>;
@@ -270,7 +308,7 @@
                interrupts = <0 47 0>;
        };
-        rtc@101E0000 {
+        rtc: rtc@101E0000 {
                clocks = <&clock CLK_RTC>;
                clock-names = "rtc";
                status = "disabled";
@@ -336,6 +374,13 @@
                        #dma-cells = <1>;
                        #dma-channels = <8>;
                        #dma-requests = <1>;
+                        /*
+                         * MDMA1 can support both secure and non-secure
+                         * AXI transactions. When this is enabled in the kernel
+                         * for boards that run in secure mode, we are getting
+                         * imprecise external aborts causing the kernel to oops.
+                         */
+                        status = "disabled";
                };
        };
@@ -385,7 +430,7 @@
        spi_0: spi@12d20000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d20000 0x100>;
-                interrupts = <0 66 0>;
+                interrupts = <0 68 0>;
                dmas = <&pdma0 5
                        &pdma0 4>;
                dma-names = "tx", "rx";
@@ -401,7 +446,7 @@
        spi_1: spi@12d30000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d30000 0x100>;
-                interrupts = <0 67 0>;
+                interrupts = <0 69 0>;
                dmas = <&pdma1 5
                        &pdma1 4>;
                dma-names = "tx", "rx";
@@ -417,7 +462,7 @@
        spi_2: spi@12d40000 {
                compatible = "samsung,exynos4210-spi";
                reg = <0x12d40000 0x100>;
-                interrupts = <0 68 0>;
+                interrupts = <0 70 0>;
                dmas = <&pdma0 7
                        &pdma0 6>;
                dma-names = "tx", "rx";
@@ -430,22 +475,22 @@
                status = "disabled";
        };
-        serial@12C00000 {
+        uart_0: serial@12C00000 {
                clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
                clock-names = "uart", "clk_uart_baud0";
        };
-        serial@12C10000 {
+        uart_1: serial@12C10000 {
                clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
                clock-names = "uart", "clk_uart_baud0";
        };
-        serial@12C20000 {
+        uart_2: serial@12C20000 {
                clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
                clock-names = "uart", "clk_uart_baud0";
        };
-        serial@12C30000 {
+        uart_3: serial@12C30000 {
                clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
                clock-names = "uart", "clk_uart_baud0";
        };
@@ -465,14 +510,14 @@
                #phy-cells = <0>;
        };
-        dp-controller@145B0000 {
+        dp: dp-controller@145B0000 {
                clocks = <&clock CLK_DP1>;
                clock-names = "dp";
                phys = <&dp_phy>;
                phy-names = "dp";
        };
-        fimd@14400000 {
+        fimd: fimd@14400000 {
                samsung,power-domain = <&disp_pd>;
                clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
                clock-names = "sclk_fimd", "fimd";
@@ -549,7 +594,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c4_hs_bus>;
-                clocks = <&clock CLK_I2C4>;
+                clocks = <&clock CLK_USI0>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -562,7 +607,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c5_hs_bus>;
-                clocks = <&clock CLK_I2C5>;
+                clocks = <&clock CLK_USI1>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -575,7 +620,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c6_hs_bus>;
-                clocks = <&clock CLK_I2C6>;
+                clocks = <&clock CLK_USI2>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -588,7 +633,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c7_hs_bus>;
-                clocks = <&clock CLK_I2C7>;
+                clocks = <&clock CLK_USI3>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -601,7 +646,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c8_hs_bus>;
-                clocks = <&clock CLK_I2C8>;
+                clocks = <&clock CLK_USI4>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -614,7 +659,7 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c9_hs_bus>;
-                clocks = <&clock CLK_I2C9>;
+                clocks = <&clock CLK_USI5>;
                clock-names = "hsi2c";
                status = "disabled";
        };
@@ -627,13 +672,13 @@
                #size-cells = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&i2c10_hs_bus>;
-                clocks = <&clock CLK_I2C10>;
+                clocks = <&clock CLK_USI6>;
                clock-names = "hsi2c";
                status = "disabled";
        };
-        hdmi@14530000 {
+        hdmi: hdmi@14530000 {
-                compatible = "samsung,exynos4212-hdmi";
+                compatible = "samsung,exynos5420-hdmi";
                reg = <0x14530000 0x70000>;
                interrupts = <0 95 0>;
                clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
@@ -641,10 +686,16 @@
                         <&clock CLK_MOUT_HDMI>;
                clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
                        "sclk_hdmiphy", "mout_hdmi";
+                phy = <&hdmiphy>;
+                samsung,syscon-phandle = <&pmu_system_controller>;
                status = "disabled";
        };
-        mixer@14450000 {
+        hdmiphy: hdmiphy@145D0000 {
+                reg = <0x145D0000 0x20>;
+        };
+        mixer: mixer@14450000 {
                compatible = "samsung,exynos5420-mixer";
                reg = <0x14450000 0x10000>;
                interrupts = <0 94 0>;
@@ -675,6 +726,11 @@
                reg = <0x10040000 0x5000>;
        };
+        sysreg_system_controller: syscon@10050000 {
+                compatible = "samsung,exynos5-sysreg", "syscon";
+                reg = <0x10050000 0x5000>;
+        };
        tmu_cpu0: tmu@10060000 {
                compatible = "samsung,exynos5420-tmu";
                reg = <0x10060000 0x100>;
@@ -715,7 +771,7 @@
                clock-names = "tmu_apbif", "tmu_triminfo_apbif";
        };
-        watchdog@101D0000 {
+        watchdog: watchdog@101D0000 {
                compatible = "samsung,exynos5420-wdt";
                reg = <0x101D0000 0x100>;
                interrupts = <0 42 0>;
@@ -724,12 +780,103 @@
                samsung,syscon-phandle = <&pmu_system_controller>;
        };
-        sss@10830000 {
+        sss: sss@10830000 {
                compatible = "samsung,exynos4210-secss";
                reg = <0x10830000 0x10000>;
                interrupts = <0 112 0>;
-                clocks = <&clock 471>;
+                clocks = <&clock CLK_SSS>;
                clock-names = "secss";
-                samsung,power-domain = <&g2d_pd>;
+        };
+        usbdrd3_0: usb@12000000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock CLK_USBD300>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                dwc3 {
+                        compatible = "snps,dwc3";
+                        reg = <0x12000000 0x10000>;
+                        interrupts = <0 72 0>;
+                        phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>;
+                        phy-names = "usb2-phy", "usb3-phy";
+                };
+        };
+        usbdrd_phy0: phy@12100000 {
+                compatible = "samsung,exynos5420-usbdrd-phy";
+                reg = <0x12100000 0x100>;
+                clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
+                clock-names = "phy", "ref";
+                samsung,pmu-syscon = <&pmu_system_controller>;
+                #phy-cells = <1>;
+        };
+        usbdrd3_1: usb@12400000 {
+                compatible = "samsung,exynos5250-dwusb3";
+                clocks = <&clock CLK_USBD301>;
+                clock-names = "usbdrd30";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                dwc3 {
+                        compatible = "snps,dwc3";
+                        reg = <0x12400000 0x10000>;
+                        interrupts = <0 73 0>;
+                        phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>;
+                        phy-names = "usb2-phy", "usb3-phy";
+                };
+        };
+        usbdrd_phy1: phy@12500000 {
+                compatible = "samsung,exynos5420-usbdrd-phy";
+                reg = <0x12500000 0x100>;
+                clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBPHY301>;
+                clock-names = "phy", "ref";
+                samsung,pmu-syscon = <&pmu_system_controller>;
+                #phy-cells = <1>;
+        };
+        usbhost2: usb@12110000 {
+                compatible = "samsung,exynos4210-ehci";
+                reg = <0x12110000 0x100>;
+                interrupts = <0 71 0>;
+                clocks = <&clock CLK_USBH20>;
+                clock-names = "usbhost";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        phys = <&usb2_phy 1>;
+                };
+        };
+        usbhost1: usb@12120000 {
+                compatible = "samsung,exynos4210-ohci";
+                reg = <0x12120000 0x100>;
+                interrupts = <0 71 0>;
+                clocks = <&clock CLK_USBH20>;
+                clock-names = "usbhost";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                port@0 {
+                        reg = <0>;
+                        phys = <&usb2_phy 1>;
+                };
+        };
+        usb2_phy: phy@12130000 {
+                compatible = "samsung,exynos5250-usb2-phy";
+                reg = <0x12130000 0x100>;
+                clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
+                clock-names = "phy", "ref";
+                #phy-cells = <1>;
+                samsung,sysreg-phandle = <&sysreg_system_controller>;
+                samsung,pmureg-phandle = <&pmu_system_controller>;
        };
 };
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 84f77c2fe4d4..ae3a17c791f6 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -176,7 +176,7 @@
                clock-names = "i2c";
        };
-        watchdog {
+        watchdog@110000 {
                compatible = "samsung,s3c2410-wdt";
                reg = <0x110000 0x1000>;
                interrupts = <0 1 0>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
new file mode 100644
index 000000000000..f3af2079a063
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -0,0 +1,253 @@
+/*
+ * Google Peach Pi Rev 10+ board device tree source
+ *
+ * Copyright (c) 2014 Google, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include "exynos5800.dtsi"
+/ {
+        model = "Google Peach Pi Rev 10+";
+        compatible = "google,pi-rev16",
+                "google,pi-rev15", "google,pi-rev14",
+                "google,pi-rev13", "google,pi-rev12",
+                "google,pi-rev11", "google,pi-rev10",
+                "google,pi", "google,peach", "samsung,exynos5800",
+                "samsung,exynos5";
+        memory {
+                reg = <0x20000000 0x80000000>;
+        };
+        fixed-rate-clocks {
+                oscclk {
+                        compatible = "samsung,exynos5420-oscclk";
+                        clock-frequency = <24000000>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&power_key_irq>;
+                power {
+                        label = "Power";
+                        gpios = <&gpx1 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 1000000 0>;
+                brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+                default-brightness-level = <7>;
+                pinctrl-0 = <&pwm0_out>;
+                pinctrl-names = "default";
+        };
+        usb300_vbus_reg: regulator-usb300 {
+                compatible = "regulator-fixed";
+                regulator-name = "P5.0V_USB3CON0";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gph0 0 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb300_vbus_en>;
+                enable-active-high;
+        };
+        usb301_vbus_reg: regulator-usb301 {
+                compatible = "regulator-fixed";
+                regulator-name = "P5.0V_USB3CON1";
+                regulator-min-microvolt = <5000000>;
+                regulator-max-microvolt = <5000000>;
+                gpio = <&gph0 1 0>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb301_vbus_en>;
+                enable-active-high;
+        };
+};
+&pinctrl_0 {
+        tpm_irq: tpm-irq {
+                samsung,pins = "gpx1-0";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        power_key_irq: power-key-irq {
+                samsung,pins = "gpx1-2";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        dp_hpd_gpio: dp_hpd_gpio {
+                samsung,pins = "gpx2-6";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <3>;
+                samsung,pin-drv = <0>;
+        };
+        hdmi_hpd_irq: hdmi-hpd-irq {
+                samsung,pins = "gpx3-7";
+                samsung,pin-function = <0>;
+                samsung,pin-pud = <1>;
+                samsung,pin-drv = <0>;
+        };
+};
+&pinctrl_3 {
+        usb300_vbus_en: usb300-vbus-en {
+                samsung,pins = "gph0-0";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+        usb301_vbus_en: usb301-vbus-en {
+                samsung,pins = "gph0-1";
+                samsung,pin-function = <1>;
+                samsung,pin-pud = <0>;
+                samsung,pin-drv = <0>;
+        };
+};
+&rtc {
+        status = "okay";
+};
+&uart_3 {
+        status = "okay";
+};
+&mmc_0 {
+        status = "okay";
+        num-slots = <1>;
+        broken-cd;
+        caps2-mmc-hs200-1_8v;
+        supports-highspeed;
+        non-removable;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <0 4>;
+        samsung,dw-mshc-ddr-timing = <0 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <8>;
+        };
+};
+&mmc_2 {
+        status = "okay";
+        num-slots = <1>;
+        supports-highspeed;
+        card-detect-delay = <200>;
+        clock-frequency = <400000000>;
+        samsung,dw-mshc-ciu-div = <3>;
+        samsung,dw-mshc-sdr-timing = <2 3>;
+        samsung,dw-mshc-ddr-timing = <1 2>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
+        slot@0 {
+                reg = <0>;
+                bus-width = <4>;
+        };
+};
+&dp {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dp_hpd_gpio>;
+        samsung,color-space = <0>;
+        samsung,dynamic-range = <0>;
+        samsung,ycbcr-coeff = <0>;
+        samsung,color-depth = <1>;
+        samsung,link-rate = <0x0a>;
+        samsung,lane-count = <2>;
+        samsung,hpd-gpio = <&gpx2 6 0>;
+        display-timings {
+                native-mode = <&timing1>;
+                timing1: timing@1 {
+                        clock-frequency = <150660000>;
+                        hactive = <1920>;
+                        vactive = <1080>;
+                        hfront-porch = <60>;
+                        hback-porch = <172>;
+                        hsync-len = <80>;
+                        vback-porch = <25>;
+                        vfront-porch = <10>;
+                        vsync-len = <10>;
+                };
+        };
+};
+&fimd {
+        status = "okay";
+        samsung,invert-vclk;
+};
+&hsi2c_9 {
+        status = "okay";
+        clock-frequency = <400000>;
+        tpm@20 {
+                compatible = "infineon,slb9645tt";
+                reg = <0x20>;
+                /* Unused irq; but still need to configure the pins */
+                pinctrl-names = "default";
+                pinctrl-0 = <&tpm_irq>;
+        };
+};
+&i2c_2 {
+        status = "okay";
+        samsung,i2c-sda-delay = <100>;
+        samsung,i2c-max-bus-freq = <66000>;
+        samsung,i2c-slave-addr = <0x50>;
+};
+&hdmi {
+        status = "okay";
+        hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&hdmi_hpd_irq>;
+        ddc = <&i2c_2>;
+};
+&usbdrd_phy0 {
+        vbus-supply = <&usb300_vbus_reg>;
+};
+&usbdrd_phy1 {
+        vbus-supply = <&usb301_vbus_reg>;
+};
+/*
+ * Use longest HW watchdog in SoC (32 seconds) since the hardware
+ * watchdog provides no debugging information (compared to soft/hard
+ * lockup detectors) and so should be last resort.
+ */
+&watchdog {
+        timeout-sec = <32>;
+};
diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
new file mode 100644
index 000000000000..c0bb3563cac1
--- /dev/null
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -0,0 +1,28 @@
+/*
+ * SAMSUNG EXYNOS5800 SoC device tree source
+ *
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * SAMSUNG EXYNOS5800 SoC device nodes are listed in this file.
+ * EXYNOS5800 based board files can include this file and provide
+ * values for board specfic bindings.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "exynos5420.dtsi"
+/ {
+        compatible = "samsung,exynos5800", "samsung,exynos5";
+};
+&clock {
+        compatible = "samsung,exynos5800-clock";
+};
+&mfc {
+        compatible = "samsung,mfc-v8";
+};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 62fb3da50bdb..ad12da38fc92 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -172,3 +172,16 @@
        fsl,uart-has-rtscts;
        status = "okay";
 };
+&usbhost1 {
+        phy_type = "serial";
+        dr_mode = "host";
+        status = "okay";
+};
+&usbotg {
+        phy_type = "utmi";
+        dr_mode = "otg";
+        external-vbus-divider;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index f8db366c46ff..9b31faa96377 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -16,21 +16,98 @@
        model = "Ka-Ro TX25";
        compatible = "karo,imx25-tx25", "fsl,imx25";
+        chosen {
+                stdout-path = &uart1;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_fec_phy: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "fec-phy";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio4 9 0>;
+                        enable-active-high;
+                };
+        };
        memory {
                reg = <0x80000000 0x02000000 0x90000000 0x02000000>;
        };
 };
+&iomuxc {
+        pinctrl_uart1: uart1grp {
+                fsl,pins = <
+                        MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
+                        MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
+                        MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
+                        MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
+                >;
+        };
+        pinctrl_fec: fecgrp {
+                fsl,pins = <
+                        MX25_PAD_D11__GPIO_4_9          0x80000000 /* FEC PHY power on pin */
+                        MX25_PAD_D13__GPIO_4_7          0x80000000 /* FEC reset */
+                        MX25_PAD_FEC_MDC__FEC_MDC       0x80000000
+                        MX25_PAD_FEC_MDIO__FEC_MDIO     0x80000000
+                        MX25_PAD_FEC_TDATA0__FEC_TDATA0 0x80000000
+                        MX25_PAD_FEC_TDATA1__FEC_TDATA1 0x80000000
+                        MX25_PAD_FEC_TX_EN__FEC_TX_EN   0x80000000
+                        MX25_PAD_FEC_RDATA0__FEC_RDATA0 0x80000000
+                        MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x80000000
+                        MX25_PAD_FEC_RX_DV__FEC_RX_DV   0x80000000
+                        MX25_PAD_FEC_TX_CLK__FEC_TX_CLK 0x80000000
+                >;
+        };
+        pinctrl_nfc: nfcgrp {
+                fsl,pins = <
+                        MX25_PAD_NF_CE0__NF_CE0         0x80000000
+                        MX25_PAD_NFWE_B__NFWE_B         0x80000000
+                        MX25_PAD_NFRE_B__NFRE_B         0x80000000
+                        MX25_PAD_NFALE__NFALE           0x80000000
+                        MX25_PAD_NFCLE__NFCLE           0x80000000
+                        MX25_PAD_NFWP_B__NFWP_B         0x80000000
+                        MX25_PAD_NFRB__NFRB             0x80000000
+                        MX25_PAD_D7__D7                 0x80000000
+                        MX25_PAD_D6__D6                 0x80000000
+                        MX25_PAD_D5__D5                 0x80000000
+                        MX25_PAD_D4__D4                 0x80000000
+                        MX25_PAD_D3__D3                 0x80000000
+                        MX25_PAD_D2__D2                 0x80000000
+                        MX25_PAD_D1__D1                 0x80000000
+                        MX25_PAD_D0__D0                 0x80000000
+                >;
+        };
+};
 &uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 &fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-reset-gpios = <&gpio3 7 0>;
        phy-mode = "rmii";
+        phy-supply = <&reg_fec_phy>;
        status = "okay";
 };
 &nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nfc>;
        nand-on-flash-bbt;
+        nand-ecc-mode = "hw";
+        nand-bus-width = <8>;
        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index f607ce520eda..c608942b8a3b 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -10,6 +10,7 @@
 */
 /dts-v1/;
+#include <dt-bindings/input/input.h>
 #include "imx25.dtsi"
 / {
@@ -19,18 +20,232 @@
        memory {
                reg = <0x80000000 0x4000000>;
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_fec_3v3: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "fec-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 3 0>;
+                        enable-active-high;
+                };
+                reg_2p5v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                };
+                reg_3p3v: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+                reg_can_3v3: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "can-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio4 6 0>;
+                };
+        };
+        sound {
+                compatible = "fsl,imx25-pdk-sgtl5000",
+                             "fsl,imx-audio-sgtl5000";
+                model = "imx25-pdk-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                mux-int-port = <1>;
+                mux-ext-port = <4>;
+        };
 };
-&uart1 {
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&can1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_can1>;
+        xceiver-supply = <&reg_can_3v3>;
+        status = "okay";
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        cd-gpios = <&gpio2 1 0>;
+        wp-gpios = <&gpio2 0 0>;
        status = "okay";
 };
 &fec {
        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-supply = <&reg_fec_3v3>;
+        phy-reset-gpios = <&gpio4 8 0>;
        status = "okay";
 };
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 129>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+};
+&iomuxc {
+        imx25-pdk {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX25_PAD_RW__AUD4_TXFS                  0xe0
+                                MX25_PAD_OE__AUD4_TXC                   0xe0
+                                MX25_PAD_EB0__AUD4_TXD                  0xe0
+                                MX25_PAD_EB1__AUD4_RXD                  0xe0
+                        >;
+                };
+                pinctrl_can1: can1grp {
+                        fsl,pins = <
+                                MX25_PAD_GPIO_A__CAN1_TX                0x0
+                                MX25_PAD_GPIO_B__CAN1_RX                0x0
+                                MX25_PAD_D14__GPIO_4_6                  0x80000000
+                        >;
+                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX25_PAD_SD1_CMD__SD1_CMD               0x80000000
+                                MX25_PAD_SD1_CLK__SD1_CLK               0x80000000
+                                MX25_PAD_SD1_DATA0__SD1_DATA0           0x80000000
+                                MX25_PAD_SD1_DATA1__SD1_DATA1           0x80000000
+                                MX25_PAD_SD1_DATA2__SD1_DATA2           0x80000000
+                                MX25_PAD_SD1_DATA3__SD1_DATA3           0x80000000
+                                MX25_PAD_A14__GPIO_2_0                  0x80000000
+                                MX25_PAD_A15__GPIO_2_1                  0x80000000
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
+                                MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
+                                MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
+                                MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
+                                MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
+                                MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
+                                MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
+                                MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
+                                MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
+                                MX25_PAD_A17__GPIO_2_3                  0x80000000
+                                MX25_PAD_D12__GPIO_4_8                  0x80000000
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
+                                MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
+                        >;
+                };
+                pinctrl_kpp: kppgrp {
+                        fsl,pins = <
+                                MX25_PAD_KPP_ROW0__KPP_ROW0     0x80000000
+                                MX25_PAD_KPP_ROW1__KPP_ROW1     0x80000000
+                                MX25_PAD_KPP_ROW2__KPP_ROW2     0x80000000
+                                MX25_PAD_KPP_ROW3__KPP_ROW3     0x80000000
+                                MX25_PAD_KPP_COL0__KPP_COL0     0x80000000
+                                MX25_PAD_KPP_COL1__KPP_COL1     0x80000000
+                                MX25_PAD_KPP_COL2__KPP_COL2     0x80000000
+                                MX25_PAD_KPP_COL3__KPP_COL3     0x80000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX25_PAD_UART1_RTS__UART1_RTS           0xe0
+                                MX25_PAD_UART1_CTS__UART1_CTS           0xe0
+                                MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
+                                MX25_PAD_UART1_RXD__UART1_RXD           0xc0
+                        >;
+                };
+        };
+};
 &nfc {
        nand-on-flash-bbt;
        status = "okay";
 };
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp>;
+        linux,keymap = <
+                        MATRIX_KEY(0x0, 0x0, KEY_UP)
+                        MATRIX_KEY(0x0, 0x1, KEY_DOWN)
+                        MATRIX_KEY(0x0, 0x2, KEY_VOLUMEDOWN)
+                        MATRIX_KEY(0x0, 0x3, KEY_HOME)
+                        MATRIX_KEY(0x1, 0x0, KEY_RIGHT)
+                        MATRIX_KEY(0x1, 0x1, KEY_LEFT)
+                        MATRIX_KEY(0x1, 0x2, KEY_ENTER)
+                        MATRIX_KEY(0x1, 0x3, KEY_VOLUMEUP)
+                        MATRIX_KEY(0x2, 0x0, KEY_F6)
+                        MATRIX_KEY(0x2, 0x1, KEY_F8)
+                        MATRIX_KEY(0x2, 0x2, KEY_F9)
+                        MATRIX_KEY(0x2, 0x3, KEY_F10)
+                        MATRIX_KEY(0x3, 0x0, KEY_F1)
+                        MATRIX_KEY(0x3, 0x1, KEY_F2)
+                        MATRIX_KEY(0x3, 0x2, KEY_F3)
+                        MATRIX_KEY(0x3, 0x2, KEY_POWER)
+        >;
+        status = "okay";
+};
+&ssi1 {
+        codec-handle = <&codec>;
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
+&usbhost1 {
+        phy_type = "serial";
+        dr_mode = "host";
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index ea323f09dc78..bb74d9582b7e 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -14,6 +14,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -21,6 +22,8 @@
                i2c0 = &i2c1;
                i2c1 = &i2c2;
                i2c2 = &i2c3;
+                mmc0 = &esdhc1;
+                mmc1 = &esdhc2;
                serial0 = &uart1;
                serial1 = &uart2;
                serial2 = &uart3;
@@ -165,9 +168,10 @@
                                status = "disabled";
                        };
-                        kpp@43fa8000 {
+                        kpp: kpp@43fa8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
+                                compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
                                reg = <0x43fa8000 0x4000>;
                                clocks = <&clks 102>;
                                clock-names = "";
@@ -482,23 +486,13 @@
                                clocks = <&clks 99>;
                        };
-                        usbphy1: usbphy@1 {
-                                compatible = "nop-usbphy";
-                                status = "disabled";
-                        };
-                        usbphy2: usbphy@2 {
-                                compatible = "nop-usbphy";
-                                status = "disabled";
-                        };
                        usbotg: usb@53ff4000 {
                                compatible = "fsl,imx25-usb", "fsl,imx27-usb";
                                reg = <0x53ff4000 0x0200>;
                                interrupts = <37>;
-                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+                                clocks = <&clks 70>;
-                                clock-names = "ipg", "ahb", "per";
                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
@@ -506,9 +500,9 @@
                                compatible = "fsl,imx25-usb", "fsl,imx27-usb";
                                reg = <0x53ff4400 0x0200>;
                                interrupts = <35>;
-                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
+                                clocks = <&clks 70>;
-                                clock-names = "ipg", "ahb", "per";
                                fsl,usbmisc = <&usbmisc 1>;
+                                fsl,usbphy = <&usbphy1>;
                                status = "disabled";
                        };
@@ -518,7 +512,6 @@
                                clocks = <&clks 9>, <&clks 70>, <&clks 8>;
                                clock-names = "ipg", "ahb", "per";
                                reg = <0x53ff4600 0x00f>;
-                                status = "disabled";
                        };
                        dryice@53ffc000 {
@@ -530,6 +523,11 @@
                        };
                };
+                iram: sram@78000000 {
+                        compatible = "mmio-sram";
+                        reg = <0x78000000 0x20000>;
+                };
                emi@80000000 {
                        compatible = "fsl,emi-bus", "simple-bus";
                        #address-cells = <1>;
@@ -550,4 +548,20 @@
                        };
                };
        };
+        usbphy {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usbphy0: usb-phy@0 {
+                        reg = <0>;
+                        compatible = "usb-nop-xceiv";
+                };
+                usbphy1: usb-phy@1 {
+                        reg = <1>;
+                        compatible = "usb-nop-xceiv";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 5ce89aa275df..4c317716b510 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -17,15 +17,181 @@
        compatible = "fsl,imx27-pdk", "fsl,imx27";
        memory {
-                reg = <0x0 0x0>;
+                reg = <0xa0000000 0x08000000>;
        };
+        usbphy {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usbphy0: usbphy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        clocks = <&clks 0>;
+                        clock-names = "main_clk";
+                };
+        };
+};
+&cspi2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cspi2>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+        pmic: mc13783@0 {
+                compatible = "fsl,mc13783";
+                reg = <0>;
+                spi-cs-high;
+                spi-max-frequency = <1000000>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
+                regulators {
+                        vgen_reg: vgen {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        vmmc1_reg: vmmc1 {
+                                regulator-min-microvolt = <1600000>;
+                                regulator-max-microvolt = <3000000>;
+                        };
+                        gpo1_reg: gpo1 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                        gpo3_reg: gpo3 {
+                                regulator-always-on;
+                                regulator-boot-on;
+                        };
+                };
+        };
+};
+&fec {
+        phy-mode = "mii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        status = "okay";
+};
+&kpp {
+        linux,keymap = <
+                MATRIX_KEY(0, 0, KEY_UP)
+                MATRIX_KEY(0, 1, KEY_DOWN)
+                MATRIX_KEY(1, 0, KEY_RIGHT)
+                MATRIX_KEY(1, 1, KEY_LEFT)
+                MATRIX_KEY(1, 2, KEY_ENTER)
+                MATRIX_KEY(2, 0, KEY_F6)
+                MATRIX_KEY(2, 1, KEY_F8)
+                MATRIX_KEY(2, 2, KEY_F9)
+                MATRIX_KEY(2, 3, KEY_F10)
+        >;
+        status = "okay";
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nand>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
 };
 &uart1 {
        fsl,uart-has-rtscts;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
-&fec {
+&usbotg {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        dr_mode = "otg";
+        fsl,usbphy = <&usbphy0>;
+        phy_type = "ulpi";
        status = "okay";
 };
+&iomuxc {
+        imx27-pdk {
+                pinctrl_cspi2: cspi2grp {
+                        fsl,pins = <
+                                MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
+                                MX27_PAD_CSPI2_MOSI__CSPI2_MOSI 0x0
+                                MX27_PAD_CSPI2_SCLK__CSPI2_SCLK 0x0
+                                MX27_PAD_CSPI2_SS0__GPIO4_21    0x0 /* SPI2 CS0 */
+                                MX27_PAD_TOUT__GPIO3_14         0x0 /* PMIC IRQ */
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX27_PAD_SD3_CMD__FEC_TXD0 0x0
+                                MX27_PAD_SD3_CLK__FEC_TXD1 0x0
+                                MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
+                                MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
+                                MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
+                                MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
+                                MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
+                                MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
+                                MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
+                                MX27_PAD_ATA_DATA7__FEC_MDC 0x0
+                                MX27_PAD_ATA_DATA8__FEC_CRS 0x0
+                                MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
+                                MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
+                                MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
+                                MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
+                                MX27_PAD_ATA_DATA13__FEC_COL 0x0
+                                MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
+                                MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
+                        >;
+                };
+                pinctrl_nand: nandgrp {
+                        fsl,pins = <
+                                MX27_PAD_NFRB__NFRB     0x0
+                                MX27_PAD_NFCLE__NFCLE   0x0
+                                MX27_PAD_NFWP_B__NFWP_B 0x0
+                                MX27_PAD_NFCE_B__NFCE_B 0x0
+                                MX27_PAD_NFALE__NFALE   0x0
+                                MX27_PAD_NFRE_B__NFRE_B 0x0
+                                MX27_PAD_NFWE_B__NFWE_B 0x0
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX27_PAD_UART1_TXD__UART1_TXD 0x0
+                                MX27_PAD_UART1_RXD__UART1_RXD 0x0
+                                MX27_PAD_UART1_CTS__UART1_CTS 0x0
+                                MX27_PAD_UART1_RTS__UART1_RTS 0x0
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
+                                MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
+                                MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
+                                MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
+                                MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
+                                MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
+                                MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
+                                MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
+                                MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
+                                MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
+                                MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
+                                MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 3c3964a99637..7c869fe3c30b 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -15,6 +15,10 @@
        model = "Phytec pca100 rapid development kit";
        compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
+        chosen {
+                stdout-path = &uart1;
+        };
        display: display {
                model = "Primeview-PD050VL1";
                native-mode = <&timing0>;
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index df3b2e731835..fe02bc7a24fd 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -12,14 +12,79 @@
 / {
        model = "Phytec pcm970";
        compatible = "phytec,imx27-pcm970", "phytec,imx27-pcm038", "fsl,imx27";
+        chosen {
+                stdout-path = &uart1;
+        };
+        display0: LQ035Q7 {
+                model = "Sharp-LQ035Q7";
+                native-mode = <&timing0>;
+                bits-per-pixel = <16>;
+                fsl,pcr = <0xf00080c0>;
+                display-timings {
+                        timing0: 240x320 {
+                                clock-frequency = <5500000>;
+                                hactive = <240>;
+                                vactive = <320>;
+                                hback-porch = <5>;
+                                hsync-len = <7>;
+                                hfront-porch = <16>;
+                                vback-porch = <7>;
+                                vsync-len = <1>;
+                                vfront-porch = <9>;
+                                pixelclk-active = <1>;
+                                hsync-active = <1>;
+                                vsync-active = <1>;
+                                de-active = <0>;
+                        };
+                };
+        };
+        regulators {
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_csien>;
+                        reg = <2>;
+                        regulator-name = "CSI_EN";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 24 GPIO_ACTIVE_LOW>;
+                        regulator-always-on;
+                };
+        };
+        usbphy {
+                usbphy2: usbphy@2 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <2>;
+                        vcc-supply = <&reg_5v0>;
+                        clocks = <&clks 0>;
+                        clock-names = "main_clk";
+                };
+        };
 };
 &cspi1 {
+        pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
        fsl,spi-num-chipselects = <2>;
        cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
                   <&gpio4 27 GPIO_ACTIVE_LOW>;
 };
+&fb {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_imxfb1>;
+        display = <&display0>;
+        lcd-supply = <&reg_5v0>;
+        fsl,dmacr = <0x00020010>;
+        fsl,lscr1 = <0x00120300>;
+        fsl,lpccr = <0x00a903ff>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <400000>;
        pinctrl-names = "default";
@@ -36,6 +101,50 @@
 &iomuxc {
        imx27_phycore_rdk {
+                pinctrl_csien: csiengrp {
+                        fsl,pins = <
+                                MX27_PAD_USB_OC_B__GPIO2_24 0x0
+                        >;
+                };
+                pinctrl_cspi1cs1: cspi1cs1grp {
+                        fsl,pins = <
+                                MX27_PAD_CSPI1_SS1__GPIO4_27 0x0
+                        >;
+                };
+                pinctrl_imxfb1: imxfbgrp {
+                        fsl,pins = <
+                                MX27_PAD_LD0__LD0 0x0
+                                MX27_PAD_LD1__LD1 0x0
+                                MX27_PAD_LD2__LD2 0x0
+                                MX27_PAD_LD3__LD3 0x0
+                                MX27_PAD_LD4__LD4 0x0
+                                MX27_PAD_LD5__LD5 0x0
+                                MX27_PAD_LD6__LD6 0x0
+                                MX27_PAD_LD7__LD7 0x0
+                                MX27_PAD_LD8__LD8 0x0
+                                MX27_PAD_LD9__LD9 0x0
+                                MX27_PAD_LD10__LD10 0x0
+                                MX27_PAD_LD11__LD11 0x0
+                                MX27_PAD_LD12__LD12 0x0
+                                MX27_PAD_LD13__LD13 0x0
+                                MX27_PAD_LD14__LD14 0x0
+                                MX27_PAD_LD15__LD15 0x0
+                                MX27_PAD_LD16__LD16 0x0
+                                MX27_PAD_LD17__LD17 0x0
+                                MX27_PAD_CLS__CLS 0x0
+                                MX27_PAD_CONTRAST__CONTRAST 0x0
+                                MX27_PAD_LSCLK__LSCLK 0x0
+                                MX27_PAD_OE_ACD__OE_ACD 0x0
+                                MX27_PAD_PS__PS 0x0
+                                MX27_PAD_REV__REV 0x0
+                                MX27_PAD_SPL_SPR__SPL_SPR 0x0
+                                MX27_PAD_HSYNC__HSYNC 0x0
+                                MX27_PAD_VSYNC__VSYNC 0x0
+                        >;
+                };
                pinctrl_i2c1: i2c1grp {
                        /* Add pullup to DATA line */
                        fsl,pins = <
@@ -193,19 +302,16 @@
        dr_mode = "host";
        phy_type = "ulpi";
        vbus-supply = <&reg_5v0>;
+        fsl,usbphy = <&usbphy2>;
        disable-over-current;
        status = "okay";
 };
-&usbphy2 {
-        vcc-supply = <&reg_5v0>;
-};
 &weim {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_weim>;
-        can@d4000000 {
+        can@4,0 {
                compatible = "nxp,sja1000";
                reg = <4 0x00000000 0x00000100>;
                interrupt-parent = <&gpio5>;
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index cefaa6994623..31e9f7049f73 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -41,6 +41,20 @@
                        regulator-max-microvolt = <5000000>;
                };
        };
+        usbphy {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usbphy0: usbphy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        vcc-supply = <&sw3_reg>;
+                        clocks = <&clks 0>;
+                        clock-names = "main_clk";
+                };
+        };
 };
 &audmux {
@@ -66,9 +80,9 @@
        status = "okay";
        pmic: mc13783@0 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                compatible = "fsl,mc13783";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
                reg = <0>;
                spi-cs-high;
                spi-max-frequency = <20000000>;
@@ -166,7 +180,7 @@
 &fec {
        phy-mode = "mii";
-        phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_HIGH>;
+        phy-reset-gpios = <&gpio3 30 GPIO_ACTIVE_LOW>;
        phy-supply = <&reg_3v3>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_fec1>;
@@ -204,7 +218,6 @@
                                MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
                                MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
                                MX27_PAD_CSPI1_SS0__GPIO4_28    0x0 /* SPI1 CS0 */
-                                MX27_PAD_USB_PWR__GPIO2_23      0x0 /* PMIC IRQ */
                        >;
                };
@@ -251,6 +264,21 @@
                        >;
                };
+                pinctrl_pmic: pmicgrp {
+                        fsl,pins = <
+                                MX27_PAD_USB_PWR__GPIO2_23      0x0 /* PMIC IRQ */
+                        >;
+                };
+                pinctrl_ssi1: ssi1grp {
+                        fsl,pins = <
+                                MX27_PAD_SSI1_FS__SSI1_FS 0x0
+                                MX27_PAD_SSI1_RXDAT__SSI1_RXDAT 0x0
+                                MX27_PAD_SSI1_TXDAT__SSI1_TXDAT 0x0
+                                MX27_PAD_SSI1_CLK__SSI1_CLK 0x0
+                        >;
+                };
                pinctrl_usbotg: usbotggrp {
                        fsl,pins = <
                                MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
@@ -279,23 +307,28 @@
        status = "okay";
 };
+&ssi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ssi1>;
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
 &usbotg {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usbotg>;
        dr_mode = "otg";
        phy_type = "ulpi";
+        fsl,usbphy = <&usbphy0>;
        vbus-supply = <&sw3_reg>;
+        disable-over-current;
        status = "okay";
 };
-&usbphy0 {
-        vcc-supply = <&sw3_reg>;
-};
 &weim {
        status = "okay";
-        nor: nor@c0000000 {
+        nor: nor@0,0 {
                compatible = "cfi-flash";
                reg = <0 0x00000000 0x02000000>;
                bank-width = <2>;
@@ -305,7 +338,7 @@
                #size-cells = <1>;
        };
-        sram: sram@c8000000 {
+        sram: sram@1,0 {
                compatible = "mtd-ram";
                reg = <1 0x00000000 0x00800000>;
                bank-width = <2>;
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 137e010eab35..a75555c39533 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -11,11 +11,13 @@
 #include "skeleton.dtsi"
 #include "imx27-pinfunc.h"
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -71,26 +73,6 @@
                };
        };
-        usbphy {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                usbphy0: usbphy@0 {
-                        compatible = "usb-nop-xceiv";
-                        reg = <0>;
-                        clocks = <&clks 75>;
-                        clock-names = "main_clk";
-                };
-                usbphy2: usbphy@2 {
-                        compatible = "usb-nop-xceiv";
-                        reg = <2>;
-                        clocks = <&clks 75>;
-                        clock-names = "main_clk";
-                };
-        };
        soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -464,9 +446,8 @@
                                compatible = "fsl,imx27-usb";
                                reg = <0x10024000 0x200>;
                                interrupts = <56>;
-                                clocks = <&clks 15>;
+                                clocks = <&clks 75>;
                                fsl,usbmisc = <&usbmisc 0>;
-                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
@@ -474,7 +455,7 @@
                                compatible = "fsl,imx27-usb";
                                reg = <0x10024200 0x200>;
                                interrupts = <54>;
-                                clocks = <&clks 15>;
+                                clocks = <&clks 75>;
                                fsl,usbmisc = <&usbmisc 1>;
                                status = "disabled";
                        };
@@ -483,9 +464,8 @@
                                compatible = "fsl,imx27-usb";
                                reg = <0x10024400 0x200>;
                                interrupts = <55>;
-                                clocks = <&clks 15>;
+                                clocks = <&clks 75>;
                                fsl,usbmisc = <&usbmisc 2>;
-                                fsl,usbphy = <&usbphy2>;
                                status = "disabled";
                        };
diff --git a/arch/arm/boot/dts/imx28-duckbill.dts b/arch/arm/boot/dts/imx28-duckbill.dts
index 5f326c1c1850..ce1a7effba37 100644
--- a/arch/arm/boot/dts/imx28-duckbill.dts
+++ b/arch/arm/boot/dts/imx28-duckbill.dts
@@ -25,9 +25,9 @@
                        ssp0: ssp@80010000 {
                                compatible = "fsl,imx28-mmc";
                                pinctrl-names = "default";
-                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                pinctrl-0 = <&mmc0_4bit_pins_a
                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
-                                bus-width = <8>;
+                                bus-width = <4>;
                                vmmc-supply = <&reg_3p3v>;
                                status = "okay";
                        };
@@ -39,7 +39,7 @@
                                hog_pins_a: hog@0 {
                                        reg = <0>;
                                        fsl,pinmux-ids = <
-                                                MX28_PAD_ENET0_RX_CLK__GPIO_4_13 /* PHY Reset */
+                                                MX28_PAD_SSP0_DATA7__GPIO_2_7 /* PHY Reset */
                                        >;
                                        fsl,drive-strength = <MXS_DRIVE_4mA>;
                                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
@@ -82,7 +82,7 @@
                        pinctrl-names = "default";
                        pinctrl-0 = <&mac0_pins_a>;
                        phy-supply = <&reg_3p3v>;
-                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
                        phy-reset-duration = <100>;
                        status = "okay";
                };
@@ -110,12 +110,12 @@
                status {
                        label = "duckbill:green:status";
-                        gpios = <&gpio3 5 0>;
+                        gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
                };
                failure {
                        label = "duckbill:red:status";
-                        gpios = <&gpio3 4 0>;
+                        gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 90a579532b8b..a95cc5358ff4 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -9,6 +9,7 @@
 * http://www.gnu.org/copyleft/gpl.html
 */
+#include <dt-bindings/gpio/gpio.h>
 #include "skeleton.dtsi"
 #include "imx28-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
index 906ae937b013..9c2b715ab8bf 100644
--- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -37,6 +37,17 @@
                compatible = "nxp,pcf8563";
                reg = <0x51>;
        };
+        tsc2007: tsc2007@48 {
+                compatible = "ti,tsc2007";
+                gpios = <&gpio3 2 0>;
+                interrupt-parent = <&gpio3>;
+                interrupts = <0x2 0x8>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tsc2007_1>;
+                reg = <0x48>;
+                ti,x-plate-ohms = <180>;
+        };
 };
 &iomuxc {
@@ -70,6 +81,10 @@
                                MX35_PAD_I2C1_DAT__I2C1_SDA             0x80000000
                        >;
                };
+                pinctrl_tsc2007_1: tsc2007grp-1 {
+                        fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index 1bdec21f4533..f04ae91eea89 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -46,6 +46,14 @@
                        linux,default-trigger = "heartbeat";
                };
        };
+        sound {
+                compatible = "eukrea,asoc-tlv320";
+                eukrea,model = "imx35-eukrea-tlv320aic23";
+                ssi-controller = <&ssi1>;
+                fsl,mux-int-port = <1>;
+                fsl,mux-ext-port = <4>;
+        };
 };
 &audmux {
@@ -124,6 +132,7 @@
 };
 &ssi1 {
+        codec-handle = <&tlv320aic23>;
        fsl,mode = "i2s-slave";
        status = "okay";
 };
@@ -141,3 +150,16 @@
        fsl,uart-has-rtscts;
        status = "okay";
 };
+&usbhost1 {
+        phy_type = "serial";
+        dr_mode = "host";
+        status = "okay";
+};
+&usbotg {
+        phy_type = "utmi";
+        dr_mode = "otg";
+        external-vbus-divider;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
new file mode 100644
index 000000000000..8d715523708f
--- /dev/null
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx35.dtsi"
+/ {
+        model = "Freescale i.MX35 Product Development Kit";
+        compatible = "fsl,imx35-pdk", "fsl,imx35";
+        memory {
+                reg = <0x80000000 0x8000000>,
+                      <0x90000000 0x8000000>;
+        };
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        status = "okay";
+};
+&iomuxc {
+        imx35-pdk {
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,pins = <
+                                MX35_PAD_SD1_CMD__ESDHC1_CMD            0x80000000
+                                MX35_PAD_SD1_CLK__ESDHC1_CLK            0x80000000
+                                MX35_PAD_SD1_DATA0__ESDHC1_DAT0         0x80000000
+                                MX35_PAD_SD1_DATA1__ESDHC1_DAT1         0x80000000
+                                MX35_PAD_SD1_DATA2__ESDHC1_DAT2         0x80000000
+                                MX35_PAD_SD1_DATA3__ESDHC1_DAT3         0x80000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX35_PAD_TXD1__UART1_TXD_MUX            0x1c5
+                                MX35_PAD_RXD1__UART1_RXD_MUX            0x1c5
+                                MX35_PAD_CTS1__UART1_CTS                0x1c5
+                                MX35_PAD_RTS1__UART1_RTS                0x1c5
+                        >;
+                };
+        };
+};
+&nfc {
+        nand-bus-width = <16>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 88b218f8f810..4759abb49436 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -13,6 +13,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -295,9 +296,9 @@
                                compatible = "fsl,imx35-usb", "fsl,imx27-usb";
                                reg = <0x53ff4000 0x0200>;
                                interrupts = <37>;
-                                clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+                                clocks = <&clks 73>;
-                                clock-names = "ipg", "ahb", "per";
                                fsl,usbmisc = <&usbmisc 0>;
+                                fsl,usbphy = <&usbphy0>;
                                status = "disabled";
                        };
@@ -305,9 +306,9 @@
                                compatible = "fsl,imx35-usb", "fsl,imx27-usb";
                                reg = <0x53ff4400 0x0200>;
                                interrupts = <35>;
-                                clocks = <&clks 9>, <&clks 73>, <&clks 28>;
+                                clocks = <&clks 73>;
-                                clock-names = "ipg", "ahb", "per";
                                fsl,usbmisc = <&usbmisc 1>;
+                                fsl,usbphy = <&usbphy1>;
                                status = "disabled";
                        };
@@ -356,4 +357,20 @@
                        };
                };
        };
+        usbphy {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                usbphy0: usb-phy@0 {
+                        reg = <0>;
+                        compatible = "usb-nop-xceiv";
+                };
+                usbphy1: usb-phy@1 {
+                        reg = <1>;
+                        compatible = "usb-nop-xceiv";
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 9c89d1ca97c2..6a201cf54366 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -17,6 +17,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 9e9deb244b76..6bc3243a80d3 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -17,10 +17,28 @@
        model = "Freescale i.MX51 Babbage Board";
        compatible = "fsl,imx51-babbage", "fsl,imx51";
+        chosen {
+                stdout-path = &uart1;
+        };
        memory {
                reg = <0x90000000 0x20000000>;
        };
+        clocks {
+                ckih1 {
+                        clock-frequency = <22579200>;
+                };
+                clk_26M: codec_clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <26000000>;
+                        gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
+                };
+        };
        display0: display@di0 {
                compatible = "fsl,imx-parallel-display";
                interface-pix-fmt = "rgb24";
@@ -82,11 +100,13 @@
        gpio-keys {
                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_keys>;
                power {
                        label = "Power Button";
                        gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
                        gpio-key,wakeup;
                };
        };
@@ -102,6 +122,36 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usbh1_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbh1reg>;
+                        reg = <0>;
+                        regulator-name = "usbh1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+                reg_usbotg_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_usbotgreg>;
+                        reg = <1>;
+                        regulator-name = "usbotg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                };
+        };
        sound {
                compatible = "fsl,imx51-babbage-sgtl5000",
                             "fsl,imx-audio-sgtl5000";
@@ -116,41 +166,23 @@
                mux-ext-port = <3>;
        };
-        clocks {
+        usbphy {
-                ckih1 {
+                #address-cells = <1>;
-                        clock-frequency = <22579200>;
+                #size-cells = <0>;
-                };
+                compatible = "simple-bus";
-                clk_26M: codec_clock {
+                usbh1phy: usbh1phy@0 {
-                        compatible = "fixed-clock";
+                        compatible = "usb-nop-xceiv";
-                        reg=<0>;
+                        reg = <0>;
-                        #clock-cells = <0>;
+                        clocks = <&clks IMX5_CLK_DUMMY>;
-                        clock-frequency = <26000000>;
+                        clock-names = "main_clk";
-                        gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
                };
        };
 };
-&esdhc1 {
+&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc1>;
-        fsl,cd-controller;
-        fsl,wp-controller;
-        status = "okay";
-};
-&esdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_esdhc2>;
-        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
-        wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
-        status = "okay";
-};
-&uart3 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart3>;
+        pinctrl-0 = <&pinctrl_audmux>;
-        fsl,uart-has-rtscts;
        status = "okay";
 };
@@ -163,9 +195,9 @@
        status = "okay";
        pmic: mc13892@0 {
-                #address-cells = <1>;
-                #size-cells = <0>;
                compatible = "fsl,mc13892";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_pmic>;
                spi-max-frequency = <6000000>;
                spi-cs-high;
                reg = <0>;
@@ -280,6 +312,53 @@
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        fsl,cd-controller;
+        fsl,wp-controller;
+        status = "okay";
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2>;
+        cd-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+        wp-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-mode = "mii";
+        phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
+        phy-reset-duration = <1>;
+        status = "okay";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+        sgtl5000: codec@0a {
+                compatible = "fsl,sgtl5000";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_clkcodec>;
+                reg = <0x0a>;
+                clocks = <&clk_26M>;
+                VDDA-supply = <&vdig_reg>;
+                VDDIO-supply = <&vvideo_reg>;
+        };
+};
 &ipu_di0_disp0 {
        remote-endpoint = <&display0_in>;
 };
@@ -288,29 +367,74 @@
        remote-endpoint = <&display1_in>;
 };
+&kpp {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_kpp>;
+        linux,keymap = <
+                MATRIX_KEY(0, 0, KEY_UP)
+                MATRIX_KEY(0, 1, KEY_DOWN)
+                MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
+                MATRIX_KEY(0, 3, KEY_HOME)
+                MATRIX_KEY(1, 0, KEY_RIGHT)
+                MATRIX_KEY(1, 1, KEY_LEFT)
+                MATRIX_KEY(1, 2, KEY_ENTER)
+                MATRIX_KEY(1, 3, KEY_VOLUMEUP)
+                MATRIX_KEY(2, 0, KEY_F6)
+                MATRIX_KEY(2, 1, KEY_F8)
+                MATRIX_KEY(2, 2, KEY_F9)
+                MATRIX_KEY(2, 3, KEY_F10)
+                MATRIX_KEY(3, 0, KEY_F1)
+                MATRIX_KEY(3, 1, KEY_F2)
+                MATRIX_KEY(3, 2, KEY_F3)
+                MATRIX_KEY(3, 3, KEY_POWER)
+        >;
+        status = "okay";
+};
 &ssi2 {
        fsl,mode = "i2s-slave";
        status = "okay";
 };
-&iomuxc {
+&uart1 {
        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
+        pinctrl-0 = <&pinctrl_uart1>;
+        fsl,uart-has-rtscts;
+        status = "okay";
+};
-        imx51-babbage {
+&uart2 {
-                pinctrl_hog: hoggrp {
+        pinctrl-names = "default";
-                        fsl,pins = <
+        pinctrl-0 = <&pinctrl_uart2>;
-                                MX51_PAD_GPIO1_0__SD1_CD     0x20d5
+        status = "okay";
-                                MX51_PAD_GPIO1_1__SD1_WP     0x20d5
+};
-                                MX51_PAD_GPIO1_5__GPIO1_5    0x100
-                                MX51_PAD_GPIO1_6__GPIO1_6    0x100
+&uart3 {
-                                MX51_PAD_EIM_A27__GPIO2_21   0x5
+        pinctrl-names = "default";
-                                MX51_PAD_CSPI1_SS0__GPIO4_24 0x85
+        pinctrl-0 = <&pinctrl_uart3>;
-                                MX51_PAD_CSPI1_SS1__GPIO4_25 0x85
+        fsl,uart-has-rtscts;
-                                MX51_PAD_CSPI1_RDY__GPIO4_26 0x80000000
+        status = "okay";
-                        >;
+};
-                };
+&usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        vbus-supply = <&reg_usbh1_vbus>;
+        fsl,usbphy = <&usbh1phy>;
+        phy_type = "ulpi";
+        status = "okay";
+};
+&usbotg {
+        dr_mode = "otg";
+        disable-over-current;
+        phy_type = "utmi_wide";
+        vbus-supply = <&reg_usbotg_vbus>;
+        status = "okay";
+};
+&iomuxc {
+        imx51-babbage {
                pinctrl_audmux: audmuxgrp {
                        fsl,pins = <
                                MX51_PAD_AUD3_BB_TXD__AUD3_TXD          0x80000000
@@ -320,11 +444,19 @@
                        >;
                };
+                pinctrl_clkcodec: clkcodecgrp {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_RDY__GPIO4_26            0x80000000
+                        >;
+                };
                pinctrl_ecspi1: ecspi1grp {
                        fsl,pins = <
                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                                MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
+                                MX51_PAD_CSPI1_SS1__GPIO4_25            0x85 /* CS1 */
                        >;
                };
@@ -336,6 +468,8 @@
                                MX51_PAD_SD1_DATA1__SD1_DATA1           0x20d5
                                MX51_PAD_SD1_DATA2__SD1_DATA2           0x20d5
                                MX51_PAD_SD1_DATA3__SD1_DATA3           0x20d5
+                                MX51_PAD_GPIO1_0__SD1_CD                0x20d5
+                                MX51_PAD_GPIO1_1__SD1_WP                0x20d5
                        >;
                };
@@ -347,29 +481,38 @@
                                MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
                                MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
                                MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
+                                MX51_PAD_GPIO1_5__GPIO1_5               0x100 /* WP */
+                                MX51_PAD_GPIO1_6__GPIO1_6               0x100 /* CD */
                        >;
                };
                pinctrl_fec: fecgrp {
                        fsl,pins = <
-                                MX51_PAD_EIM_EB2__FEC_MDIO              0x80000000
+                                MX51_PAD_EIM_EB2__FEC_MDIO              0x000001f5
-                                MX51_PAD_EIM_EB3__FEC_RDATA1            0x80000000
+                                MX51_PAD_EIM_EB3__FEC_RDATA1            0x00000085
-                                MX51_PAD_EIM_CS2__FEC_RDATA2            0x80000000
+                                MX51_PAD_EIM_CS2__FEC_RDATA2            0x00000085
-                                MX51_PAD_EIM_CS3__FEC_RDATA3            0x80000000
+                                MX51_PAD_EIM_CS3__FEC_RDATA3            0x00000085
-                                MX51_PAD_EIM_CS4__FEC_RX_ER             0x80000000
+                                MX51_PAD_EIM_CS4__FEC_RX_ER             0x00000180
-                                MX51_PAD_EIM_CS5__FEC_CRS               0x80000000
+                                MX51_PAD_EIM_CS5__FEC_CRS               0x00000180
-                                MX51_PAD_NANDF_RB2__FEC_COL             0x80000000
+                                MX51_PAD_NANDF_RB2__FEC_COL             0x00000180
-                                MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x80000000
+                                MX51_PAD_NANDF_RB3__FEC_RX_CLK          0x00000180
-                                MX51_PAD_NANDF_D9__FEC_RDATA0           0x80000000
+                                MX51_PAD_NANDF_D9__FEC_RDATA0           0x00002180
-                                MX51_PAD_NANDF_D8__FEC_TDATA0           0x80000000
+                                MX51_PAD_NANDF_D8__FEC_TDATA0           0x00002004
-                                MX51_PAD_NANDF_CS2__FEC_TX_ER           0x80000000
+                                MX51_PAD_NANDF_CS2__FEC_TX_ER           0x00002004
-                                MX51_PAD_NANDF_CS3__FEC_MDC             0x80000000
+                                MX51_PAD_NANDF_CS3__FEC_MDC             0x00002004
-                                MX51_PAD_NANDF_CS4__FEC_TDATA1          0x80000000
+                                MX51_PAD_NANDF_CS4__FEC_TDATA1          0x00002004
-                                MX51_PAD_NANDF_CS5__FEC_TDATA2          0x80000000
+                                MX51_PAD_NANDF_CS5__FEC_TDATA2          0x00002004
-                                MX51_PAD_NANDF_CS6__FEC_TDATA3          0x80000000
+                                MX51_PAD_NANDF_CS6__FEC_TDATA3          0x00002004
-                                MX51_PAD_NANDF_CS7__FEC_TX_EN           0x80000000
+                                MX51_PAD_NANDF_CS7__FEC_TX_EN           0x00002004
-                                MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x80000000
+                                MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK      0x00002180
-                                MX51_PAD_EIM_A20__GPIO2_14 0x85 /* Reset */
+                                MX51_PAD_NANDF_D11__FEC_RX_DV           0x000020a4
+                                MX51_PAD_EIM_A20__GPIO2_14              0x00000085 /* Phy Reset */
+                        >;
+                };
+                pinctrl_gpio_keys: gpiokeysgrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_A27__GPIO2_21              0x5
                        >;
                };
@@ -379,6 +522,13 @@
                        >;
                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_D19__I2C1_SCL              0x400001ed
+                                MX51_PAD_EIM_D16__I2C1_SDA              0x400001ed
+                        >;
+                };
                pinctrl_i2c2: i2c2grp {
                        fsl,pins = <
                                MX51_PAD_KEY_COL4__I2C2_SCL             0x400001ed
@@ -455,6 +605,12 @@
                        >;
                };
+                pinctrl_pmic: pmicgrp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_8__GPIO1_8               0xe5 /* IRQ */
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
@@ -479,71 +635,33 @@
                                MX51_PAD_EIM_D24__UART3_CTS             0x1c5
                        >;
                };
-        };
-};
-&uart1 {
+                pinctrl_usbh1: usbh1grp {
-        pinctrl-names = "default";
+                        fsl,pins = <
-        pinctrl-0 = <&pinctrl_uart1>;
+                                MX51_PAD_USBH1_CLK__USBH1_CLK           0x80000000
-        fsl,uart-has-rtscts;
+                                MX51_PAD_USBH1_DIR__USBH1_DIR           0x80000000
-        status = "okay";
+                                MX51_PAD_USBH1_NXT__USBH1_NXT           0x80000000
-};
+                                MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x80000000
+                                MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x80000000
-&uart2 {
+                                MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x80000000
-        pinctrl-names = "default";
+                                MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x80000000
-        pinctrl-0 = <&pinctrl_uart2>;
+                                MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x80000000
-        status = "okay";
+                                MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x80000000
-};
+                                MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x80000000
+                                MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x80000000
+                        >;
+                };
-&i2c2 {
+                pinctrl_usbh1reg: usbh1reggrp {
-        pinctrl-names = "default";
+                        fsl,pins = <
-        pinctrl-0 = <&pinctrl_i2c2>;
+                                MX51_PAD_EIM_D21__GPIO2_5               0x85
-        status = "okay";
+                        >;
+                };
-        sgtl5000: codec@0a {
+                pinctrl_usbotgreg: usbotgreggrp {
-                compatible = "fsl,sgtl5000";
+                        fsl,pins = <
-                reg = <0x0a>;
+                                MX51_PAD_GPIO1_7__GPIO1_7               0x85
-                clocks = <&clk_26M>;
+                        >;
-                VDDA-supply = <&vdig_reg>;
+                };
-                VDDIO-supply = <&vvideo_reg>;
        };
 };
-&audmux {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_audmux>;
-        status = "okay";
-};
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_fec>;
-        phy-mode = "mii";
-        phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
-        phy-reset-duration = <1>;
-        status = "okay";
-};
-&kpp {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_kpp>;
-        linux,keymap = <
-                MATRIX_KEY(0, 0, KEY_UP)
-                MATRIX_KEY(0, 1, KEY_DOWN)
-                MATRIX_KEY(0, 2, KEY_VOLUMEDOWN)
-                MATRIX_KEY(0, 3, KEY_HOME)
-                MATRIX_KEY(1, 0, KEY_RIGHT)
-                MATRIX_KEY(1, 1, KEY_LEFT)
-                MATRIX_KEY(1, 2, KEY_ENTER)
-                MATRIX_KEY(1, 3, KEY_VOLUMEUP)
-                MATRIX_KEY(2, 0, KEY_F6)
-                MATRIX_KEY(2, 1, KEY_F8)
-                MATRIX_KEY(2, 2, KEY_F9)
-                MATRIX_KEY(2, 3, KEY_F10)
-                MATRIX_KEY(3, 0, KEY_F1)
-                MATRIX_KEY(3, 1, KEY_F2)
-                MATRIX_KEY(3, 2, KEY_F3)
-                MATRIX_KEY(3, 3, KEY_POWER)
-                >;
-        status = "okay";
-};
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
new file mode 100644
index 000000000000..1db517d3d497
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx51-digi-connectcore-som.dtsi"
+/ {
+        model = "Digi ConnectCore CC(W)-MX51 JSK";
+        compatible = "digi,connectcore-ccxmx51-jsk",
+                     "digi,connectcore-ccxmx51-som", "fsl,imx51";
+        chosen {
+                linux,stdout-path = &uart1;
+        };
+};
+&owire {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_owire>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&usbotg {
+        dr_mode = "otg";
+        status = "okay";
+};
+&usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        dr_mode = "host";
+        phy_type = "ulpi";
+        disable-over-current;
+        status = "okay";
+};
+&iomuxc {
+        imx51-digi-connectcore-jsk {
+                pinctrl_owire: owiregrp {
+                        fsl,pins = <
+                                MX51_PAD_OWIRE_LINE__OWIRE_LINE         0x40000000
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX51_PAD_UART1_RXD__UART1_RXD           0x1c5
+                                MX51_PAD_UART1_TXD__UART1_TXD           0x1c5
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX51_PAD_UART2_RXD__UART2_RXD           0x1c5
+                                MX51_PAD_UART2_TXD__UART2_TXD           0x1c5
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX51_PAD_UART3_RXD__UART3_RXD           0x1c5
+                                MX51_PAD_UART3_TXD__UART3_TXD           0x1c5
+                        >;
+                };
+                pinctrl_usbh1: usbh1grp {
+                        fsl,pins = <
+                                MX51_PAD_USBH1_DATA0__USBH1_DATA0       0x1e5
+                                MX51_PAD_USBH1_DATA1__USBH1_DATA1       0x1e5
+                                MX51_PAD_USBH1_DATA2__USBH1_DATA2       0x1e5
+                                MX51_PAD_USBH1_DATA3__USBH1_DATA3       0x1e5
+                                MX51_PAD_USBH1_DATA4__USBH1_DATA4       0x1e5
+                                MX51_PAD_USBH1_DATA5__USBH1_DATA5       0x1e5
+                                MX51_PAD_USBH1_DATA6__USBH1_DATA6       0x1e5
+                                MX51_PAD_USBH1_DATA7__USBH1_DATA7       0x1e5
+                                MX51_PAD_USBH1_CLK__USBH1_CLK           0x1e5
+                                MX51_PAD_USBH1_DIR__USBH1_DIR           0x1e5
+                                MX51_PAD_USBH1_NXT__USBH1_NXT           0x1e5
+                                MX51_PAD_USBH1_STP__USBH1_STP           0x1e5
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
new file mode 100644
index 000000000000..321662f53e33
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -0,0 +1,377 @@
+/*
+ * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx51.dtsi"
+/ {
+        model = "Digi ConnectCore CC(W)-MX51";
+        compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
+        memory {
+                reg = <0x90000000 0x08000000>;
+        };
+};
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+        pmic: mc13892@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_mc13892>;
+                compatible = "fsl,mc13892";
+                spi-max-frequency = <16000000>;
+                spi-cs-high;
+                reg = <0>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
+                fsl,mc13xxx-uses-rtc;
+                regulators {
+                        sw1_reg: sw1 {
+                                regulator-min-microvolt = <1000000>;
+                                regulator-max-microvolt = <1100000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw2_reg: sw2 {
+                                regulator-min-microvolt = <1225000>;
+                                regulator-max-microvolt = <1225000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        sw3_reg: sw3 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        swbst_reg: swbst { };
+                        viohi_reg: viohi {
+                                regulator-always-on;
+                        };
+                        vpll_reg: vpll {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        vdig_reg: vdig {
+                                regulator-min-microvolt = <1250000>;
+                                regulator-max-microvolt = <1250000>;
+                                regulator-always-on;
+                        };
+                        vsd_reg: vsd {
+                                regulator-min-microvolt = <3150000>;
+                                regulator-max-microvolt = <3150000>;
+                                regulator-always-on;
+                        };
+                        vusb2_reg: vusb2 {
+                                regulator-min-microvolt = <2600000>;
+                                regulator-max-microvolt = <2600000>;
+                                regulator-always-on;
+                        };
+                        vvideo_reg: vvideo {
+                                regulator-min-microvolt = <2775000>;
+                                regulator-max-microvolt = <2775000>;
+                                regulator-always-on;
+                        };
+                        vaudio_reg: vaudio {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                        vcam_reg: vcam {
+                                regulator-min-microvolt = <2750000>;
+                                regulator-max-microvolt = <2750000>;
+                                regulator-always-on;
+                        };
+                        vgen1_reg: vgen1 {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+                        vgen2_reg: vgen2 {
+                                regulator-min-microvolt = <3150000>;
+                                regulator-max-microvolt = <3150000>;
+                                regulator-always-on;
+                        };
+                        vgen3_reg: vgen3 {
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <1800000>;
+                                regulator-always-on;
+                        };
+                        vusb_reg: vusb {
+                                regulator-always-on;
+                        };
+                        gpo1_reg: gpo1 { };
+                        gpo2_reg: gpo2 { };
+                        gpo3_reg: gpo3 { };
+                        gpo4_reg: gpo4 { };
+                        pwgt2spi_reg: pwgt2spi {
+                                regulator-always-on;
+                        };
+                        vcoincell_reg: vcoincell {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&esdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc2>;
+        cap-sdio-irq;
+        enable-sdio-wakeup;
+        keep-power-in-suspend;
+        max-frequency = <50000000>;
+        no-1-8-v;
+        non-removable;
+        vmmc-supply = <&gpo4_reg>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec>;
+        phy-mode = "mii";
+        phy-supply = <&gpo3_reg>;
+        /* Pins shared with LCD2, keep status disabled */
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <400000>;
+        status = "okay";
+        mma7455l@1d {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_mma7455l>;
+                compatible = "fsl,mma7455l";
+                reg = <0x1d>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
+        };
+};
+&nfc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_nfc>;
+        nand-bus-width = <8>;
+        nand-ecc-mode = "hw";
+        nand-on-flash-bbt;
+        status = "okay";
+};
+&usbotg {
+        phy_type = "utmi_wide";
+        disable-over-current;
+        /* Device role is not known, keep status disabled */
+};
+&weim {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_weim>;
+        status = "okay";
+        lan9221: lan9221@5,0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_lan9221>;
+                compatible = "smsc,lan9221", "smsc,lan9115";
+                reg = <5 0x00000000 0x1000>;
+                fsl,weim-cs-timing = <
+                        0x00420081 0x00000000
+                        0x32260000 0x00000000
+                        0x72080f00 0x00000000
+                >;
+                clocks = <&clks IMX5_CLK_DUMMY>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
+                phy-mode = "mii";
+                reg-io-width = <2>;
+                smsc,irq-push-pull;
+                vdd33a-supply = <&gpo2_reg>;
+                vddvario-supply = <&gpo2_reg>;
+        };
+};
+&iomuxc {
+        imx51-digi-connectcore-som {
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                                MX51_PAD_CSPI1_SS0__GPIO4_24            0x85 /* CS0 */
+                        >;
+                };
+                pinctrl_esdhc2: esdhc2grp {
+                        fsl,pins = <
+                                MX51_PAD_SD2_CMD__SD2_CMD               0x400020d5
+                                MX51_PAD_SD2_CLK__SD2_CLK               0x20d5
+                                MX51_PAD_SD2_DATA0__SD2_DATA0           0x20d5
+                                MX51_PAD_SD2_DATA1__SD2_DATA1           0x20d5
+                                MX51_PAD_SD2_DATA2__SD2_DATA2           0x20d5
+                                MX51_PAD_SD2_DATA3__SD2_DATA3           0x20d5
+                        >;
+                };
+                pinctrl_fec: fecgrp {
+                        fsl,pins = <
+                                MX51_PAD_DI_GP3__FEC_TX_ER              0x80000000
+                                MX51_PAD_DI2_PIN4__FEC_CRS              0x80000000
+                                MX51_PAD_DI2_PIN2__FEC_MDC              0x80000000
+                                MX51_PAD_DI2_PIN3__FEC_MDIO             0x80000000
+                                MX51_PAD_DI2_DISP_CLK__FEC_RDATA1       0x80000000
+                                MX51_PAD_DI_GP4__FEC_RDATA2             0x80000000
+                                MX51_PAD_DISP2_DAT0__FEC_RDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT1__FEC_RX_ER          0x80000000
+                                MX51_PAD_DISP2_DAT6__FEC_TDATA1         0x80000000
+                                MX51_PAD_DISP2_DAT7__FEC_TDATA2         0x80000000
+                                MX51_PAD_DISP2_DAT8__FEC_TDATA3         0x80000000
+                                MX51_PAD_DISP2_DAT9__FEC_TX_EN          0x80000000
+                                MX51_PAD_DISP2_DAT10__FEC_COL           0x80000000
+                                MX51_PAD_DISP2_DAT11__FEC_RX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT12__FEC_RX_DV         0x80000000
+                                MX51_PAD_DISP2_DAT13__FEC_TX_CLK        0x80000000
+                                MX51_PAD_DISP2_DAT14__FEC_RDATA0        0x80000000
+                                MX51_PAD_DISP2_DAT15__FEC_TDATA0        0x80000000
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_2__I2C2_SCL              0x400001ed
+                                MX51_PAD_GPIO1_3__I2C2_SDA              0x400001ed
+                        >;
+                };
+                pinctrl_nfc: nfcgrp {
+                        fsl,pins = <
+                                MX51_PAD_NANDF_D0__NANDF_D0             0x80000000
+                                MX51_PAD_NANDF_D1__NANDF_D1             0x80000000
+                                MX51_PAD_NANDF_D2__NANDF_D2             0x80000000
+                                MX51_PAD_NANDF_D3__NANDF_D3             0x80000000
+                                MX51_PAD_NANDF_D4__NANDF_D4             0x80000000
+                                MX51_PAD_NANDF_D5__NANDF_D5             0x80000000
+                                MX51_PAD_NANDF_D6__NANDF_D6             0x80000000
+                                MX51_PAD_NANDF_D7__NANDF_D7             0x80000000
+                                MX51_PAD_NANDF_ALE__NANDF_ALE           0x80000000
+                                MX51_PAD_NANDF_CLE__NANDF_CLE           0x80000000
+                                MX51_PAD_NANDF_RE_B__NANDF_RE_B         0x80000000
+                                MX51_PAD_NANDF_WE_B__NANDF_WE_B         0x80000000
+                                MX51_PAD_NANDF_WP_B__NANDF_WP_B         0x80000000
+                                MX51_PAD_NANDF_CS0__NANDF_CS0           0x80000000
+                                MX51_PAD_NANDF_RB0__NANDF_RB0           0x80000000
+                        >;
+                };
+                pinctrl_lan9221: lan9221grp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_9__GPIO1_9               0xe5 /* IRQ */
+                        >;
+                };
+                pinctrl_mc13892: mc13892grp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_5__GPIO1_5               0xe5 /* IRQ */
+                        >;
+                };
+                pinctrl_mma7455l: mma7455lgrp {
+                        fsl,pins = <
+                                MX51_PAD_GPIO1_7__GPIO1_7               0xe5 /* IRQ1 */
+                                MX51_PAD_GPIO1_6__GPIO1_6               0xe5 /* IRQ2 */
+                        >;
+                };
+                pinctrl_weim: weimgrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_DA0__EIM_DA0               0x80000000
+                                MX51_PAD_EIM_DA1__EIM_DA1               0x80000000
+                                MX51_PAD_EIM_DA2__EIM_DA2               0x80000000
+                                MX51_PAD_EIM_DA3__EIM_DA3               0x80000000
+                                MX51_PAD_EIM_DA4__EIM_DA4               0x80000000
+                                MX51_PAD_EIM_DA5__EIM_DA5               0x80000000
+                                MX51_PAD_EIM_DA6__EIM_DA6               0x80000000
+                                MX51_PAD_EIM_DA7__EIM_DA7               0x80000000
+                                MX51_PAD_EIM_DA8__EIM_DA8               0x80000000
+                                MX51_PAD_EIM_DA9__EIM_DA9               0x80000000
+                                MX51_PAD_EIM_DA10__EIM_DA10             0x80000000
+                                MX51_PAD_EIM_DA11__EIM_DA11             0x80000000
+                                MX51_PAD_EIM_DA12__EIM_DA12             0x80000000
+                                MX51_PAD_EIM_DA13__EIM_DA13             0x80000000
+                                MX51_PAD_EIM_DA14__EIM_DA14             0x80000000
+                                MX51_PAD_EIM_DA15__EIM_DA15             0x80000000
+                                MX51_PAD_EIM_A16__EIM_A16               0x80000000
+                                MX51_PAD_EIM_A17__EIM_A17               0x80000000
+                                MX51_PAD_EIM_A18__EIM_A18               0x80000000
+                                MX51_PAD_EIM_A19__EIM_A19               0x80000000
+                                MX51_PAD_EIM_A20__EIM_A20               0x80000000
+                                MX51_PAD_EIM_A21__EIM_A21               0x80000000
+                                MX51_PAD_EIM_A22__EIM_A22               0x80000000
+                                MX51_PAD_EIM_A23__EIM_A23               0x80000000
+                                MX51_PAD_EIM_A24__EIM_A24               0x80000000
+                                MX51_PAD_EIM_A25__EIM_A25               0x80000000
+                                MX51_PAD_EIM_A26__EIM_A26               0x80000000
+                                MX51_PAD_EIM_A27__EIM_A27               0x80000000
+                                MX51_PAD_EIM_D16__EIM_D16               0x80000000
+                                MX51_PAD_EIM_D17__EIM_D17               0x80000000
+                                MX51_PAD_EIM_D18__EIM_D18               0x80000000
+                                MX51_PAD_EIM_D19__EIM_D19               0x80000000
+                                MX51_PAD_EIM_D20__EIM_D20               0x80000000
+                                MX51_PAD_EIM_D21__EIM_D21               0x80000000
+                                MX51_PAD_EIM_D22__EIM_D22               0x80000000
+                                MX51_PAD_EIM_D23__EIM_D23               0x80000000
+                                MX51_PAD_EIM_D24__EIM_D24               0x80000000
+                                MX51_PAD_EIM_D25__EIM_D25               0x80000000
+                                MX51_PAD_EIM_D26__EIM_D26               0x80000000
+                                MX51_PAD_EIM_D27__EIM_D27               0x80000000
+                                MX51_PAD_EIM_D28__EIM_D28               0x80000000
+                                MX51_PAD_EIM_D29__EIM_D29               0x80000000
+                                MX51_PAD_EIM_D30__EIM_D30               0x80000000
+                                MX51_PAD_EIM_D31__EIM_D31               0x80000000
+                                MX51_PAD_EIM_OE__EIM_OE                 0x80000000
+                                MX51_PAD_EIM_DTACK__EIM_DTACK           0x80000000
+                                MX51_PAD_EIM_LBA__EIM_LBA               0x80000000
+                                MX51_PAD_EIM_CS5__EIM_CS5               0x80000000 /* CS5 */
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index 9b3acf6e4282..63164266af83 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -42,6 +42,17 @@
                compatible = "nxp,pcf8563";
                reg = <0x51>;
        };
+        tsc2007: tsc2007@49 {
+                compatible = "ti,tsc2007";
+                gpios = <&gpio4 0 1>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <0x0 0x8>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_tsc2007_1>;
+                reg = <0x49>;
+                ti,x-plate-ohms = <180>;
+        };
 };
 &iomuxc {
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 5cec4f322096..75e66c9c6144 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -24,6 +24,14 @@
        model = "Eukrea CPUIMX51";
        compatible = "eukrea,mbimxsd51","eukrea,cpuimx51", "fsl,imx51";
+        clocks {
+                clk24M: can_clock {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <24000000>;
+                };
+        };
        gpio_keys {
                compatible = "gpio-keys";
                pinctrl-names = "default";
@@ -50,6 +58,23 @@
                };
        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_can: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "CAN_RST";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
+                        startup-delay-us = <20000>;
+                        enable-active-high;
+                };
+        };
        sound {
                compatible = "eukrea,asoc-tlv320";
                eukrea,model = "imx51-eukrea-tlv320aic23";
@@ -57,6 +82,20 @@
                fsl,mux-int-port = <2>;
                fsl,mux-ext-port = <3>;
        };
+        usbphy {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "simple-bus";
+                usbh1phy: usbh1phy@0 {
+                        compatible = "usb-nop-xceiv";
+                        reg = <0>;
+                        clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
+                        clock-names = "main_clk";
+                        clock-frequency = <19200000>;
+                };
+        };
 };
 &audmux {
@@ -72,6 +111,26 @@
        status = "okay";
 };
+&ecspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi1>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
+        status = "okay";
+        can0: can@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_can>;
+                compatible = "microchip,mcp2515";
+                reg = <0>;
+                clocks = <&clk24M>;
+                spi-max-frequency = <10000000>;
+                interrupt-parent = <&gpio1>;
+                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                vdd-supply = <&reg_can>;
+        };
+};
 &i2c1 {
        tlv320aic23: codec@1a {
                compatible = "ti,tlv320aic23";
@@ -90,6 +149,23 @@
                        >;
                };
+                pinctrl_can: cangrp {
+                        fsl,pins = <
+                                MX51_PAD_CSI2_PIXCLK__GPIO4_15          0x80000000      /* nReset */
+                                MX51_PAD_GPIO1_1__GPIO1_1               0x80000000      /* IRQ */
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX51_PAD_CSPI1_MISO__ECSPI1_MISO        0x185
+                                MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI        0x185
+                                MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK        0x185
+                                MX51_PAD_CSPI1_SS0__GPIO4_24            0x80000000      /* CS0 */
+                        >;
+                };
                pinctrl_esdhc1: esdhc1grp {
                        fsl,pins = <
                                MX51_PAD_SD1_CMD__SD1_CMD               0x400020d5
@@ -151,6 +227,29 @@
                                MX51_PAD_CSI1_D9__GPIO3_13 0x1f5
                        >;
                };
+                pinctrl_usbh1: usbh1grp {
+                        fsl,pins = <
+                                MX51_PAD_USBH1_CLK__USBH1_CLK     0x1e5
+                                MX51_PAD_USBH1_DIR__USBH1_DIR     0x1e5
+                                MX51_PAD_USBH1_NXT__USBH1_NXT     0x1e5
+                                MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
+                                MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
+                                MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
+                                MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
+                                MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
+                                MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
+                                MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
+                                MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
+                                MX51_PAD_USBH1_STP__USBH1_STP     0x1e5
+                        >;
+                };
+                pinctrl_usbh1_vbus: usbh1-vbusgrp {
+                        fsl,pins = <
+                                MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
+                        >;
+                };
        };
 };
@@ -173,3 +272,24 @@
        fsl,uart-has-rtscts;
        status = "okay";
 };
+&usbh1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        fsl,usbphy = <&usbh1phy>;
+        dr_mode = "host";
+        phy_type = "ulpi";
+        status = "okay";
+};
+&usbotg {
+        dr_mode = "otg";
+        phy_type = "utmi_wide";
+        status = "okay";
+};
+&usbphy0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1_vbus>;
+        reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 150bb4e2f744..bebbf3ba0d5e 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -19,6 +19,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -537,6 +538,8 @@
                        };
                        nfc: nand@83fdb000 {
+                                #address-cells = <1>;
+                                #size-cells = <1>;
                                compatible = "fsl,imx51-nand";
                                reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
                                interrupts = <8>;
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 7c8c12969892..3e3f17aa93a1 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -17,6 +17,10 @@
        model = "TQ MBa53 starter kit";
        compatible = "tq,mba53", "tq,tqma53", "fsl,imx53";
+        chosen {
+                stdout-path = &uart2;
+        };
        backlight {
                compatible = "pwm-backlight";
                pwms = <&pwm2 0 50000>;
@@ -244,7 +248,7 @@
 &tve {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_vga_sync_1>;
-        i2c-ddc-bus = <&i2c3>;
+        ddc-i2c-bus = <&i2c3>;
        fsl,tve-mode = "vga";
        fsl,hsync-pin = <4>;
        fsl,vsync-pin = <6>;
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index ede04fa4161f..fd8c60dde7de 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -13,6 +13,10 @@
 #include "imx53.dtsi"
 / {
+        chosen {
+                stdout-path = &uart1;
+        };
        memory {
                reg = <0x70000000 0x20000000>,
                      <0xb0000000 0x20000000>;
@@ -272,6 +276,14 @@
                        >;
                };
+                pinctrl_vga_sync: vgasync-grp {
+                        fsl,pins = <
+                                /* VGA_HSYNC, VSYNC with max drive strength */
+                                MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
+                                MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX53_PAD_CSI0_DAT10__UART1_TXD_MUX      0x1e4
@@ -281,6 +293,15 @@
        };
 };
+&tve {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_vga_sync>;
+        fsl,tve-mode = "vga";
+        fsl,hsync-pin = <4>;
+        fsl,vsync-pin = <6>;
+        status = "okay";
+};
 &uart1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_uart1>;
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 9c2bff2252d0..6456a0084388 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -18,6 +18,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
@@ -115,7 +116,7 @@
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,imx53-ipu";
-                        reg = <0x18000000 0x080000000>;
+                        reg = <0x18000000 0x08000000>;
                        interrupts = <11 10>;
                        clocks = <&clks IMX5_CLK_IPU_GATE>,
                                 <&clks IMX5_CLK_IPU_DI0_GATE>,
@@ -726,8 +727,8 @@
                                clocks = <&clks IMX5_CLK_VPU_GATE>,
                                         <&clks IMX5_CLK_VPU_GATE>;
                                clock-names = "per", "ahb";
+                                resets = <&src 1>;
                                iram = <&ocram>;
-                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/imx6dl-hummingboard.dts b/arch/arm/boot/dts/imx6dl-hummingboard.dts
index 5bfae54fb780..5373a5f2782b 100644
--- a/arch/arm/boot/dts/imx6dl-hummingboard.dts
+++ b/arch/arm/boot/dts/imx6dl-hummingboard.dts
@@ -11,6 +11,10 @@
        model = "SolidRun HummingBoard DL/Solo";
        compatible = "solidrun,hummingboard", "fsl,imx6dl";
+        chosen {
+                stdout-path = &uart1;
+        };
        ir_recv: ir-receiver {
                compatible = "gpio-ir-receiver";
                gpios = <&gpio1 2 1>;
@@ -67,6 +71,13 @@
        status = "okay";
 };
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
 &i2c1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
@@ -82,6 +93,13 @@
         */
 };
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hummingboard_i2c2>;
+        status = "okay";
+};
 &iomuxc {
        hummingboard {
                pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
@@ -97,6 +115,12 @@
                        >;
                };
+                pinctrl_hummingboard_hdmi: hummingboard-hdmi {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                        >;
+                };
                pinctrl_hummingboard_i2c1: hummingboard-i2c1 {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
@@ -104,6 +128,13 @@
                        >;
                };
+                pinctrl_hummingboard_i2c2: hummingboard-i2c2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                        >;
+                };
                pinctrl_hummingboard_spdif: hummingboard-spdif {
                        fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
                };
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts
new file mode 100644
index 000000000000..08e97801494e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-phytec-pbab01.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+#include "imx6dl-phytec-pfla02.dtsi"
+#include "imx6qdl-phytec-pbab01.dtsi"
+/ {
+        model = "Phytec phyFLEX-i.MX6 DualLite/Solo Carrier-Board";
+        compatible = "phytec,imx6dl-pbab01", "phytec,imx6dl-pfla02", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..964bc2ad3c5d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-phytec-pfla02.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include "imx6dl.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
+/ {
+        model = "Phytec phyFLEX-i.MX6 DualLite/Solo";
+        compatible = "phytec,imx6dl-pfla02", "fsl,imx6dl";
+        memory {
+                reg = <0x10000000 0x20000000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
new file mode 100644
index 000000000000..909fafc0b650
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -0,0 +1,539 @@
+/*
+ * Copyright 2014 Iain Paton <ipaton0@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+/dts-v1/;
+#include "imx6dl.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "RIoTboard i.MX6S";
+        compatible = "riot,imx6s-riotboard", "fsl,imx6dl";
+        memory {
+                reg = <0x10000000 0x40000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_2p5v: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "2P5V";
+                        regulator-min-microvolt = <2500000>;
+                        regulator-max-microvolt = <2500000>;
+                };
+                reg_3p3v: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                };
+                reg_usb_otg_vbus: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_led>;
+                led0: user1 {
+                        label = "user1";
+                        gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
+                };
+                led1: user2 {
+                        label = "user2";
+                        gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
+                        default-state = "off";
+                };
+        };
+        sound {
+                compatible = "fsl,imx-audio-sgtl5000";
+                model = "imx6-riotboard-sgtl5000";
+                ssi-controller = <&ssi1>;
+                audio-codec = <&codec>;
+                audio-routing =
+                        "MIC_IN", "Mic Jack",
+                        "Mic Jack", "Mic Bias",
+                        "Headphone Jack", "HP_OUT";
+                        mux-int-port = <1>;
+                        mux-ext-port = <3>;
+        };
+};
+&audmux {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_audmux>;
+        status = "okay";
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 31 0>;
+        interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
+                              <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
+        status = "okay";
+};
+&hdmi {
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        codec: sgtl5000@0a {
+                compatible = "fsl,sgtl5000";
+                reg = <0x0a>;
+                clocks = <&clks 201>;
+                VDDA-supply = <&reg_2p5v>;
+                VDDIO-supply = <&reg_3p3v>;
+        };
+        pmic: pf0100@08 {
+                compatible = "fsl,pfuze100";
+                reg = <0x08>;
+                interrupt-parent = <&gpio5>;
+                interrupts = <16 8>;
+                regulators {
+                        reg_vddcore: sw1ab {                            /* VDDARM_IN */
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-always-on;
+                        };
+                        reg_vddsoc: sw1c {                              /* VDDSOC_IN */
+                                regulator-min-microvolt = <300000>;
+                                regulator-max-microvolt = <1875000>;
+                                regulator-always-on;
+                        };
+                        reg_gen_3v3: sw2 {                              /* VDDHIGH_IN */
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        reg_ddr_1v5a: sw3a {                            /* NVCC_DRAM, NVCC_RGMII */
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-always-on;
+                        };
+                        reg_ddr_1v5b: sw3b {                            /* NVCC_DRAM, NVCC_RGMII */
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-always-on;
+                        };
+                        reg_ddr_vtt: sw4 {                              /* MIPI conn */
+                                regulator-min-microvolt = <400000>;
+                                regulator-max-microvolt = <1975000>;
+                                regulator-always-on;
+                        };
+                        reg_5v_600mA: swbst {                           /* not used */
+                                regulator-min-microvolt = <5000000>;
+                                regulator-max-microvolt = <5150000>;
+                        };
+                        reg_snvs_3v: vsnvs {                            /* VDD_SNVS_IN */
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                        vref_reg: vrefddr {                             /* VREF_DDR */
+                                regulator-boot-on;
+                                regulator-always-on;
+                        };
+                        reg_vgen1_1v5: vgen1 {                          /* not used */
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                        };
+                        reg_vgen2_1v2_eth: vgen2 {                      /* pcie ? */
+                                regulator-min-microvolt = <800000>;
+                                regulator-max-microvolt = <1550000>;
+                                regulator-always-on;
+                        };
+                        reg_vgen3_2v8: vgen3 {                          /* not used */
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        reg_vgen4_1v8: vgen4 {                          /* NVCC_SD3 */
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        reg_vgen5_2v5_sgtl: vgen5 {                     /* Pwr LED & 5V0_delayed enable */
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        reg_vgen6_3v3: vgen6 {                          /* #V#_DELAYED enable, MIPI */
+                                regulator-min-microvolt = <1800000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
+&i2c4 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c4>;
+        clocks = <&clks 116>;
+        status = "okay";
+};
+&pwm1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm1>;
+        status = "okay";
+};
+&pwm2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm2>;
+        status = "okay";
+};
+&pwm3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm3>;
+        status = "okay";
+};
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
+&ssi1 {
+        fsl,mode = "i2s-slave";
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "okay";
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "okay";
+};
+&uart5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart5>;
+        status = "okay";
+};
+&usbh1 {
+        dr_mode = "host";
+        disable-over-current;
+        status = "okay";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        dr_mode = "otg";
+        status = "okay";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3>;
+        cd-gpios = <&gpio7 0 0>;
+        wp-gpios = <&gpio7 1 0>;
+        vmmc-supply = <&reg_3p3v>;
+        status = "okay";
+};
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        vmmc-supply = <&reg_3p3v>;
+        non-removable;
+        status = "okay";
+};
+&iomuxc {
+        pinctrl-names = "default";
+        imx6-riotboard {
+                pinctrl_audmux: audmuxgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT7__AUD3_RXD          0x8000000
+                                MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x8000000
+                                MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x8000000
+                                MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x8000000
+                                MX6QDL_PAD_GPIO_0__CCM_CLKO1            0x130b0         /* CAM_MCLK */
+                        >;
+                };
+                pinctrl_ecspi1: ecspi1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
+                                MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
+                                MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
+                                MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17      0x000b1         /* CS0 */
+                        >;
+                };
+                pinctrl_ecspi2: ecspi2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09      0x000b1         /* CS1 */
+                                MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI     0x100b1
+                                MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO     0x100b1
+                                MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12      0x000b1         /* CS0 */
+                                MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK     0x100b1
+                        >;
+                };
+                pinctrl_ecspi3: ecspi3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
+                                MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
+                                MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
+                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24       0x000b1         /* CS0 */
+                                MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25       0x000b1         /* CS1 */
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x80000000
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x0a0b1         /* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0         /* AR8035 pin strapping: IO voltage: pull up */
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x130b0         /* AR8035 pin strapping: PHYADDR#0: pull down */
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x130b0         /* AR8035 pin strapping: PHYADDR#1: pull down */
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0         /* AR8035 pin strapping: MODE#1: pull up */
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0         /* AR8035 pin strapping: MODE#3: pull up */
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x130b0         /* AR8035 pin strapping: MODE#0: pull down */
+                                MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0xc0000000      /* GPIO16 -> AR8035 25MHz */
+                                MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x130b0         /* RGMII_nRST */
+                                MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28       0x80000000      /* AR8035 interrupt */
+                                MX6QDL_PAD_GPIO_6__ENET_IRQ             0x000b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
+                                MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c3: i2c3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_5__I2C3_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_i2c4: i2c4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_7__I2C4_SCL             0x4001b8b1
+                                MX6QDL_PAD_GPIO_8__I2C4_SDA             0x4001b8b1
+                        >;
+                };
+                pinctrl_led: ledgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_A25__GPIO5_IO02          0x80000000      /* user led0 */
+                                MX6QDL_PAD_EIM_D28__GPIO3_IO28          0x80000000      /* user led1 */
+                        >;
+                };
+                pinctrl_pwm1: pwm1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT8__PWM1_OUT         0x1b0b1
+                        >;
+                };
+                pinctrl_pwm2: pwm2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT9__PWM2_OUT         0x1b0b1
+                        >;
+                };
+                pinctrl_pwm3: pwm3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
+                        >;
+                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
+                                MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D27__UART2_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_uart5: uart5grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID       0x17059
+                                MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x80000000      /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
+                                MX6QDL_PAD_EIM_D21__USB_OTG_OC          0x80000000
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                                MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x80000000      /* SD2 CD */
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x80000000      /* SD2 WP */
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                                MX6QDL_PAD_SD3_DAT5__GPIO7_IO00         0x80000000      /* SD3 CD */
+                                MX6QDL_PAD_SD3_DAT4__GPIO7_IO01         0x80000000      /* SD3 WP */
+                        >;
+                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_NANDF_ALE__GPIO6_IO08        0x80000000      /* SD4 RST (eMMC) */
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 5c5f574330f9..0a9c49d69d41 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -84,9 +84,10 @@
                        i2c4: i2c@021f8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                                compatible = "fsl,imx1-i2c";
+                                compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
                                reg = <0x021f8000 0x4000>;
                                interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
+                                clocks = <&clks 116>;
                                status = "disabled";
                        };
                };
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index e4ae38fd0269..e0302636aff5 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -18,6 +18,10 @@
        model = "Data Modul eDM-QMX6 Board";
        compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
+        chosen {
+                stdout-path = &uart2;
+        };
        aliases {
                gpio7 = &stmpe_gpio1;
                gpio8 = &stmpe_gpio2;
@@ -91,6 +95,20 @@
        };
 };
+&ecspi5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi5>;
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio1 12 0>;
+        status = "okay";
+        flash: m25p80@0 {
+                compatible = "m25p80";
+                spi-max-frequency = <40000000>;
+                reg = <0>;
+        };
+};
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
@@ -105,7 +123,8 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c2
                     &pinctrl_stmpe1
-                     &pinctrl_stmpe2>;
+                     &pinctrl_stmpe2
+                     &pinctrl_pfuze>;
        status = "okay";
        pmic: pfuze100@08 {
@@ -216,6 +235,8 @@
                reg = <0x40>;
                interrupts = <30 0>;
                interrupt-parent = <&gpio3>;
+                vcc-supply = <&sw2_reg>;
+                vio-supply = <&sw2_reg>;
                stmpe_gpio1: stmpe_gpio {
                        #gpio-cells = <2>;
@@ -228,6 +249,8 @@
                reg = <0x44>;
                interrupts = <2 0>;
                interrupt-parent = <&gpio5>;
+                vcc-supply = <&sw2_reg>;
+                vio-supply = <&sw2_reg>;
                stmpe_gpio2: stmpe_gpio {
                        #gpio-cells = <2>;
@@ -263,6 +286,15 @@
                        >;
                };
+                pinctrl_ecspi5: ecspi5rp-1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO        0x80000000
+                                MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI         0x80000000
+                                MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK         0x80000000
+                                MX6QDL_PAD_SD2_DAT3__GPIO1_IO12         0x80000000
+                        >;
+                };
                pinctrl_enet: enetgrp {
                        fsl,pins = <
                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
@@ -291,6 +323,12 @@
                        >;
                };
+                pinctrl_pfuze: pfuze100grp1 {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D20__GPIO3_IO20          0x80000000
+                        >;
+                };
                pinctrl_stmpe1: stmpe1grp {
                        fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
                };
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index 4a9b4dc9afc0..703539cf36d3 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -14,7 +14,7 @@
        compatible = "zealz,imx6q-gk802", "fsl,imx6q";
        chosen {
-                linux,stdout-path = &uart4;
+                stdout-path = &uart4;
        };
        memory {
@@ -48,6 +48,11 @@
        };
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 /* Internal I2C */
 &i2c2 {
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index e51bb3f0fd56..3689eaa58826 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -157,6 +157,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
index 5607c331fca8..c139ac0ebe15 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
+++ b/arch/arm/boot/dts/imx6q-phytec-pbab01.dts
@@ -11,40 +11,17 @@
 /dts-v1/;
 #include "imx6q-phytec-pfla02.dtsi"
+#include "imx6qdl-phytec-pbab01.dtsi"
 / {
        model = "Phytec phyFLEX-i.MX6 Quad Carrier-Board";
        compatible = "phytec,imx6q-pbab01", "phytec,imx6q-pfla02", "fsl,imx6q";
-};
-&fec {
-        status = "okay";
-};
-&gpmi {
+        chosen {
-        status = "okay";
+                stdout-path = &uart4;
+        };
 };
 &sata {
-        status = "okay";
+        status = "okay";
-};
-&uart4 {
-        status = "okay";
-};
-&usbh1 {
-        status = "okay";
-};
-&usbotg {
-        status = "okay";
-};
-&usdhc2 {
-        status = "okay";
-};
-&usdhc3 {
-        status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index 324f1550976b..cd20d0a948de 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -10,316 +10,13 @@
 */
 #include "imx6q.dtsi"
+#include "imx6qdl-phytec-pfla02.dtsi"
 / {
-        model = "Phytec phyFLEX-i.MX6 Ouad";
+        model = "Phytec phyFLEX-i.MX6 Quad";
        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
        memory {
                reg = <0x10000000 0x80000000>;
        };
-        regulators {
-                compatible = "simple-bus";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                reg_usb_otg_vbus: regulator@0 {
-                        compatible = "regulator-fixed";
-                        reg = <0>;
-                        regulator-name = "usb_otg_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio4 15 0>;
-                };
-                reg_usb_h1_vbus: regulator@1 {
-                        compatible = "regulator-fixed";
-                        reg = <1>;
-                        regulator-name = "usb_h1_vbus";
-                        regulator-min-microvolt = <5000000>;
-                        regulator-max-microvolt = <5000000>;
-                        gpio = <&gpio1 0 0>;
-                };
-        };
-};
-&ecspi3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_ecspi3>;
-        status = "okay";
-        fsl,spi-num-chipselects = <1>;
-        cs-gpios = <&gpio4 24 0>;
-        flash@0 {
-                compatible = "m25p80";
-                spi-max-frequency = <20000000>;
-                reg = <0>;
-        };
-};
-&i2c1 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_i2c1>;
-        status = "okay";
-        eeprom@50 {
-                compatible = "atmel,24c32";
-                reg = <0x50>;
-        };
-        pmic@58 {
-                compatible = "dialog,da9063";
-                reg = <0x58>;
-                interrupt-parent = <&gpio4>;
-                interrupts = <17 0x8>; /* active-low GPIO4_17 */
-                regulators {
-                        vddcore_reg: bcore1 {
-                                regulator-min-microvolt = <730000>;
-                                regulator-max-microvolt = <1380000>;
-                                regulator-always-on;
-                        };
-                        vddsoc_reg: bcore2 {
-                                regulator-min-microvolt = <730000>;
-                                regulator-max-microvolt = <1380000>;
-                                regulator-always-on;
-                        };
-                        vdd_ddr3_reg: bpro {
-                                regulator-min-microvolt = <1500000>;
-                                regulator-max-microvolt = <1500000>;
-                                regulator-always-on;
-                        };
-                        vdd_3v3_reg: bperi {
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                        };
-                        vdd_buckmem_reg: bmem {
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                        };
-                        vdd_eth_reg: bio {
-                                regulator-min-microvolt = <1200000>;
-                                regulator-max-microvolt = <1200000>;
-                                regulator-always-on;
-                        };
-                        vdd_eth_io_reg: ldo4 {
-                                regulator-min-microvolt = <2500000>;
-                                regulator-max-microvolt = <2500000>;
-                                regulator-always-on;
-                        };
-                        vdd_mx6_snvs_reg: ldo5 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                        };
-                        vdd_3v3_pmic_io_reg: ldo6 {
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                                regulator-always-on;
-                        };
-                        vdd_sd0_reg: ldo9 {
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-                        vdd_sd1_reg: ldo10 {
-                                regulator-min-microvolt = <3300000>;
-                                regulator-max-microvolt = <3300000>;
-                        };
-                        vdd_mx6_high_reg: ldo11 {
-                                regulator-min-microvolt = <3000000>;
-                                regulator-max-microvolt = <3000000>;
-                                regulator-always-on;
-                        };
-                };
-        };
-};
-&iomuxc {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_hog>;
-        imx6q-phytec-pfla02 {
-                pinctrl_hog: hoggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
-                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
-                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
-                        >;
-                };
-                pinctrl_ecspi3: ecspi3grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
-                                MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
-                                MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
-                        >;
-                };
-                pinctrl_enet: enetgrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
-                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
-                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
-                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
-                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
-                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
-                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
-                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
-                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
-                                MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
-                        >;
-                };
-                pinctrl_gpmi_nand: gpminandgrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
-                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
-                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
-                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
-                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
-                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
-                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
-                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
-                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
-                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
-                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
-                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
-                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
-                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
-                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
-                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
-                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
-                        >;
-                };
-                pinctrl_i2c1: i2c1grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
-                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
-                        >;
-                };
-                pinctrl_uart4: uart4grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
-                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
-                        >;
-                };
-                pinctrl_usbh1: usbh1grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
-                        >;
-                };
-                pinctrl_usbotg: usbotggrp {
-                        fsl,pins = <
-                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
-                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
-                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
-                        >;
-                };
-                pinctrl_usdhc2: usdhc2grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
-                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
-                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
-                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
-                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
-                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
-                        >;
-                };
-                pinctrl_usdhc3: usdhc3grp {
-                        fsl,pins = <
-                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
-                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
-                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
-                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
-                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
-                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
-                        >;
-                };
-                pinctrl_usdhc3_cdwp: usdhc3cdwp {
-                        fsl,pins = <
-                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
-                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
-                        >;
-                };
-        };
-};
-&fec {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_enet>;
-        phy-mode = "rgmii";
-        phy-reset-gpios = <&gpio3 23 0>;
-        status = "disabled";
-};
-&gpmi {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_gpmi_nand>;
-        nand-on-flash-bbt;
-        status = "disabled";
-};
-&uart4 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_uart4>;
-        status = "disabled";
-};
-&usbh1 {
-        vbus-supply = <&reg_usb_h1_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbh1>;
-        status = "disabled";
-};
-&usbotg {
-        vbus-supply = <&reg_usb_otg_vbus>;
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usbotg>;
-        disable-over-current;
-        status = "disabled";
-};
-&usdhc2 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc2>;
-        cd-gpios = <&gpio1 4 0>;
-        wp-gpios = <&gpio1 2 0>;
-        status = "disabled";
-};
-&usdhc3 {
-        pinctrl-names = "default";
-        pinctrl-0 = <&pinctrl_usdhc3
-                     &pinctrl_usdhc3_cdwp>;
-        cd-gpios = <&gpio1 27 0>;
-        wp-gpios = <&gpio1 29 0>;
-        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index ed397d149ab6..6c561060bf5c 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -16,6 +16,10 @@
        model = "Udoo i.MX6 Quad Board";
        compatible = "udoo,imx6q-udoo", "fsl,imx6q";
+        chosen {
+                stdout-path = &uart2;
+        };
        memory {
                reg = <0x10000000 0x40000000>;
        };
@@ -28,6 +32,18 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        status = "okay";
+};
 &iomuxc {
        imx6q-udoo {
                pinctrl_enet: enetgrp {
@@ -51,6 +67,13 @@
                        >;
                };
+                pinctrl_i2c2: i2c2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
+                        >;
+                };
                pinctrl_uart2: uart2grp {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D26__UART2_TX_DATA       0x1b0b1
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index c2a24888a276..25da82a03110 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -55,6 +55,20 @@
        };
 };
+&hdmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_hdmi>;
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
+&i2c2 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_cubox_i_i2c2>;
+        status = "okay";
+};
 &i2c3 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_cubox_i_i2c3>;
@@ -69,6 +83,19 @@
 &iomuxc {
        cubox_i {
+                pinctrl_cubox_i_hdmi: cubox-i-hdmi {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
+                        >;
+                };
+                pinctrl_cubox_i_i2c2: cubox-i-i2c2 {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
+                                MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
+                        >;
+                };
                pinctrl_cubox_i_i2c3: cubox-i-i2c3 {
                        fsl,pins = <
                                MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index 25cf035dd36e..2c253d6d20bd 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -22,7 +22,7 @@
        };
        chosen {
-                linux,stdout-path = &uart1;
+                stdout-path = &uart1;
        };
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 98a422153ce7..31665adcbf39 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -101,6 +101,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 035d3a85c318..367af3ec9435 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -27,6 +27,13 @@
                bootargs = "console=ttymxc1,115200";
        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
        leds {
                compatible = "gpio-leds";
@@ -148,6 +155,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -394,6 +406,12 @@
                        >;
                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
@@ -436,6 +454,27 @@
 &ldb {
        status = "okay";
+        lvds-channel@0 {
+                fsl,data-mapping = "spwg";
+                fsl,data-width = <18>;
+                status = "okay";
+                display-timings {
+                        native-mode = <&timing0>;
+                        timing0: hsd100pxn1 {
+                                clock-frequency = <65000000>;
+                                hactive = <1024>;
+                                vactive = <768>;
+                                hback-porch = <220>;
+                                hfront-porch = <40>;
+                                vback-porch = <21>;
+                                vfront-porch = <7>;
+                                hsync-len = <60>;
+                                vsync-len = <10>;
+                        };
+                };
+        };
 };
 &pcie {
@@ -443,6 +482,12 @@
        status = "okay";
 };
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
 &ssi1 {
        fsl,mode = "i2s-slave";
        status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index c8e5ae06deaf..c91b5a6c769b 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -30,6 +30,13 @@
                bootargs = "console=ttymxc1,115200";
        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
        leds {
                compatible = "gpio-leds";
@@ -157,6 +164,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -434,6 +446,12 @@
                        >;
                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
@@ -508,6 +526,12 @@
        };
 };
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
 &ssi1 {
        fsl,mode = "i2s-slave";
        status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 2795dfc8c926..698d3063b295 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -30,6 +30,13 @@
                bootargs = "console=ttymxc1,115200";
        };
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm4 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <7>;
+        };
        leds {
                compatible = "gpio-leds";
@@ -147,6 +154,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c3>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -456,6 +468,12 @@
                        >;
                };
+                pinctrl_pwm4: pwm4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
+                        >;
+                };
                pinctrl_uart1: uart1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
@@ -530,6 +548,12 @@
        };
 };
+&pwm4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm4>;
+        status = "okay";
+};
 &ssi1 {
        fsl,mode = "i2s-slave";
        status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 99be301b5232..4c4b17596c8b 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -14,6 +14,10 @@
 #include <dt-bindings/input/input.h>
 / {
+        chosen {
+                stdout-path = &uart2;
+        };
        memory {
                reg = <0x10000000 0x40000000>;
        };
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
new file mode 100644
index 000000000000..584721264121
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -0,0 +1,102 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/ {
+        chosen {
+                linux,stdout-path = &uart4;
+        };
+};
+&fec {
+        status = "okay";
+};
+&gpmi {
+        status = "okay";
+};
+&hdmi {
+        status = "okay";
+};
+&i2c2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c2>;
+        clock-frequency = <100000>;
+        status = "okay";
+        tlv320@18 {
+                compatible = "ti,tlv320aic3x";
+                reg = <0x18>;
+        };
+        stmpe@41 {
+                compatible = "st,stmpe811";
+                reg = <0x41>;
+        };
+        rtc@51 {
+                compatible = "nxp,rtc8564";
+                reg = <0x51>;
+        };
+        adc@64 {
+                compatible = "maxim,max1037";
+                reg = <0x64>;
+        };
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c3>;
+        clock-frequency = <100000>;
+        status = "okay";
+};
+&uart3 {
+        status = "okay";
+};
+&uart4 {
+        status = "okay";
+};
+&usbh1 {
+        status = "okay";
+};
+&usbotg {
+        status = "okay";
+};
+&usdhc2 {
+        status = "okay";
+};
+&usdhc3 {
+        status = "okay";
+};
+&iomuxc {
+        pinctrl_i2c2: i2c2grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
+                >;
+        };
+        pinctrl_i2c3: i2c3grp {
+                fsl,pins = <
+                        MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
+                        MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
new file mode 100644
index 000000000000..faa3494a69d4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "Phytec phyFLEX-i.MX6 Ouad";
+        compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
+        memory {
+                reg = <0x10000000 0x80000000>;
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg_usb_otg_vbus: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio4 15 0>;
+                };
+                reg_usb_h1_vbus: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "usb_h1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio1 0 0>;
+                };
+        };
+        gpio_leds: leds {
+                compatible = "gpio-leds";
+                green {
+                        label = "phyflex:green";
+                        gpios = <&gpio1 30 0>;
+                };
+                red {
+                        label = "phyflex:red";
+                        gpios = <&gpio2 31 0>;
+                };
+        };
+};
+&ecspi3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_ecspi3>;
+        status = "okay";
+        fsl,spi-num-chipselects = <1>;
+        cs-gpios = <&gpio4 24 0>;
+        flash@0 {
+                compatible = "m25p80";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+        eeprom@50 {
+                compatible = "atmel,24c32";
+                reg = <0x50>;
+        };
+        pmic@58 {
+                compatible = "dialog,da9063";
+                reg = <0x58>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <17 0x8>; /* active-low GPIO4_17 */
+                regulators {
+                        vddcore_reg: bcore1 {
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+                        vddsoc_reg: bcore2 {
+                                regulator-min-microvolt = <730000>;
+                                regulator-max-microvolt = <1380000>;
+                                regulator-always-on;
+                        };
+                        vdd_ddr3_reg: bpro {
+                                regulator-min-microvolt = <1500000>;
+                                regulator-max-microvolt = <1500000>;
+                                regulator-always-on;
+                        };
+                        vdd_3v3_reg: bperi {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vdd_buckmem_reg: bmem {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vdd_eth_reg: bio {
+                                regulator-min-microvolt = <1200000>;
+                                regulator-max-microvolt = <1200000>;
+                                regulator-always-on;
+                        };
+                        vdd_eth_io_reg: ldo4 {
+                                regulator-min-microvolt = <2500000>;
+                                regulator-max-microvolt = <2500000>;
+                                regulator-always-on;
+                        };
+                        vdd_mx6_snvs_reg: ldo5 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                        vdd_3v3_pmic_io_reg: ldo6 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                                regulator-always-on;
+                        };
+                        vdd_sd0_reg: ldo9 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vdd_sd1_reg: ldo10 {
+                                regulator-min-microvolt = <3300000>;
+                                regulator-max-microvolt = <3300000>;
+                        };
+                        vdd_mx6_high_reg: ldo11 {
+                                regulator-min-microvolt = <3000000>;
+                                regulator-max-microvolt = <3000000>;
+                                regulator-always-on;
+                        };
+                };
+        };
+};
+&iomuxc {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_hog>;
+        imx6q-phytec-pfla02 {
+                pinctrl_hog: hoggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
+                                MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
+                                MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000 /* PMIC interrupt */
+                                MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
+                                MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
+                        >;
+                };
+                pinctrl_ecspi3: ecspi3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
+                                MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
+                                MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
+                        >;
+                };
+                pinctrl_enet: enetgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
+                                MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
+                                MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
+                                MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
+                                MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
+                                MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
+                                MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
+                        >;
+                };
+                pinctrl_gpmi_nand: gpminandgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
+                                MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
+                                MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
+                                MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
+                                MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
+                                MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
+                                MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
+                                MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
+                                MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
+                                MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
+                                MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
+                                MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
+                                MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
+                                MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
+                                MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
+                                MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
+                                MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
+                        >;
+                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
+                pinctrl_uart3: uart3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
+                                MX6QDL_PAD_EIM_D30__UART3_RTS_B         0x1b0b1
+                                MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
+                        >;
+                };
+                pinctrl_uart4: uart4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
+                                MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
+                        >;
+                };
+                pinctrl_usbh1: usbh1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
+                        >;
+                };
+                pinctrl_usbotg: usbotggrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
+                                MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
+                                MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
+                        >;
+                };
+                pinctrl_usdhc2: usdhc2grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
+                                MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
+                                MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
+                                MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
+                                MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
+                                MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc3: usdhc3grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
+                                MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
+                                MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
+                                MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
+                                MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
+                                MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
+                        >;
+                };
+                pinctrl_usdhc3_cdwp: usdhc3cdwp {
+                        fsl,pins = <
+                                MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
+                                MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
+                        >;
+                };
+        };
+};
+&fec {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_enet>;
+        phy-mode = "rgmii";
+        phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
+        status = "disabled";
+};
+&gpmi {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_gpmi_nand>;
+        nand-on-flash-bbt;
+        status = "disabled";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart3>;
+        status = "disabled";
+};
+&uart4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart4>;
+        status = "disabled";
+};
+&usbh1 {
+        vbus-supply = <&reg_usb_h1_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbh1>;
+        status = "disabled";
+};
+&usbotg {
+        vbus-supply = <&reg_usb_otg_vbus>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usbotg>;
+        disable-over-current;
+        status = "disabled";
+};
+&usdhc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc2>;
+        cd-gpios = <&gpio1 4 0>;
+        wp-gpios = <&gpio1 2 0>;
+        status = "disabled";
+};
+&usdhc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc3
+                     &pinctrl_usdhc3_cdwp>;
+        cd-gpios = <&gpio1 27 0>;
+        wp-gpios = <&gpio1 29 0>;
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 3bec128c7971..6df6127bf835 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -13,6 +13,10 @@
 #include <dt-bindings/input/input.h>
 / {
+        chosen {
+                stdout-path = &uart2;
+        };
        memory {
                reg = <0x10000000 0x40000000>;
        };
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 0d816d3be4b6..40ea36534643 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -14,6 +14,10 @@
 #include <dt-bindings/input/input.h>
 / {
+        chosen {
+                stdout-path = &uart1;
+        };
        memory {
                reg = <0x10000000 0x40000000>;
        };
@@ -105,6 +109,17 @@
                default-brightness-level = <7>;
                status = "okay";
        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_gpio_leds>;
+                red {
+                        gpios = <&gpio1 2 0>;
+                        default-state = "on";
+                };
+        };
 };
 &audmux {
@@ -137,6 +152,11 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c2>;
+        status = "okay";
+};
 &i2c1 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -373,6 +393,12 @@
                        >;
                };
+                pinctrl_pcie: pciegrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_17__GPIO7_IO12  0x80000000
+                        >;
+                };
                pinctrl_pwm1: pwm1grp {
                        fsl,pins = <
                                MX6QDL_PAD_SD1_DAT3__PWM1_OUT           0x1b0b1
@@ -421,6 +447,29 @@
                                MX6QDL_PAD_SD3_DAT7__SD3_DATA7          0x17059
                        >;
                };
+                pinctrl_usdhc4: usdhc4grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
+                                MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
+                                MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
+                                MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
+                                MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
+                                MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
+                                MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
+                                MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
+                                MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
+                                MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
+                        >;
+                };
+        };
+        gpio_leds {
+                pinctrl_gpio_leds: gpioledsgrp {
+                        fsl,pins = <
+                                MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
+                        >;
+                };
        };
 };
@@ -449,6 +498,13 @@
        };
 };
+&pcie {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pcie>;
+        reset-gpio = <&gpio7 12 0>;
+        status = "okay";
+};
 &pwm1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_pwm1>;
@@ -496,3 +552,12 @@
        wp-gpios = <&gpio2 1 0>;
        status = "okay";
 };
+&usdhc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_usdhc4>;
+        bus-width = <8>;
+        non-removable;
+        no-1-8-v;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index bdfdf89d405f..5c6f10c43f65 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -62,6 +62,18 @@
        status = "okay";
 };
+&hdmi {
+        ddc-i2c-bus = <&i2c1>;
+        status = "okay";
+};
+&i2c1 {
+        clock-frequency = <100000>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_i2c1>;
+        status = "okay";
+};
 &i2c2 {
        clock-frequency = <100000>;
        pinctrl-names = "default";
@@ -127,6 +139,13 @@
                        >;
                };
+                pinctrl_i2c1: i2c1grp {
+                        fsl,pins = <
+                                MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
+                                MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
+                        >;
+                };
                pinctrl_i2c2: i2c2grp {
                        fsl,pins = <
                                MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index eca0971d4db1..ce0599134a69 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -16,6 +16,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                can0 = &can1;
                can1 = &can2;
                gpio0 = &gpio1;
@@ -140,15 +141,16 @@
                                  0x81000000 0 0          0x01f80000 0 0x00010000 /* downstream I/O */
                                  0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
                        num-lanes = <1>;
-                        interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupt-names = "msi";
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0x7>;
                        interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
                                        <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>;
+                        clocks = <&clks 144>, <&clks 206>, <&clks 189>;
-                        clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi";
+                        clock-names = "pcie", "pcie_bus", "pcie_phy";
                        status = "disabled";
                };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index d26b099260a3..2d4e5285f3f3 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -14,6 +14,7 @@
 / {
        aliases {
+                ethernet0 = &fec;
                gpio0 = &gpio1;
                gpio1 = &gpio2;
                gpio2 = &gpio3;
diff --git a/arch/arm/boot/dts/k2e-evm.dts b/arch/arm/boot/dts/k2e-evm.dts
index 74b3b63e94cf..c568f067604d 100644
--- a/arch/arm/boot/dts/k2e-evm.dts
+++ b/arch/arm/boot/dts/k2e-evm.dts
@@ -58,3 +58,84 @@
 &usb1 {
        status = "okay";
 };
+&i2c0 {
+        dtt@50 {
+                compatible = "at,24c1024";
+                reg = <0x50>;
+        };
+};
+&aemif {
+        cs0 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                clock-ranges;
+                ranges;
+                ti,cs-chipselect = <0>;
+                /* all timings in nanoseconds */
+                ti,cs-min-turnaround-ns = <12>;
+                ti,cs-read-hold-ns = <6>;
+                ti,cs-read-strobe-ns = <23>;
+                ti,cs-read-setup-ns = <9>;
+                ti,cs-write-hold-ns = <8>;
+                ti,cs-write-strobe-ns = <23>;
+                ti,cs-write-setup-ns = <8>;
+                nand@0,0 {
+                        compatible = "ti,keystone-nand","ti,davinci-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0 0 0x4000000
+                               1 0 0x0000100>;
+                        ti,davinci-chipselect = <0>;
+                        ti,davinci-mask-ale = <0x2000>;
+                        ti,davinci-mask-cle = <0x4000>;
+                        ti,davinci-mask-chipsel = <0>;
+                        nand-ecc-mode = "hw";
+                        ti,davinci-ecc-bits = <4>;
+                        nand-on-flash-bbt;
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "params";
+                                reg = <0x100000 0x80000>;
+                                read-only;
+                        };
+                        partition@180000 {
+                                label = "ubifs";
+                                reg = <0x180000 0x1FE80000>;
+                        };
+                };
+        };
+};
+&spi0 {
+        nor_flash: n25q128a11@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "Micron,n25q128a11";
+                spi-max-frequency = <54000000>;
+                m25p,fast-read;
+                reg = <0>;
+                partition@0 {
+                        label = "u-boot-spl";
+                        reg = <0x0 0x80000>;
+                        read-only;
+                };
+                partition@1 {
+                        label = "misc";
+                        reg = <0x80000 0xf80000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index c93d06f9f2a8..1f90cbf27fd7 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -138,3 +138,32 @@
                };
        };
 };
+&i2c0 {
+        dtt@50 {
+                compatible = "at,24c1024";
+                reg = <0x50>;
+        };
+};
+&spi0 {
+        nor_flash: n25q128a11@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "Micron,n25q128a11";
+                spi-max-frequency = <54000000>;
+                m25p,fast-read;
+                reg = <0>;
+                partition@0 {
+                        label = "u-boot-spl";
+                        reg = <0x0 0x80000>;
+                        read-only;
+                };
+                partition@1 {
+                        label = "misc";
+                        reg = <0x80000 0xf80000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/k2l-evm.dts b/arch/arm/boot/dts/k2l-evm.dts
index 50a70132ac9e..fec43128a2e0 100644
--- a/arch/arm/boot/dts/k2l-evm.dts
+++ b/arch/arm/boot/dts/k2l-evm.dts
@@ -35,3 +35,84 @@
 &usb {
        status = "okay";
 };
+&i2c0 {
+        dtt@50 {
+                compatible = "at,24c1024";
+                reg = <0x50>;
+        };
+};
+&aemif {
+        cs0 {
+                #address-cells = <2>;
+                #size-cells = <1>;
+                clock-ranges;
+                ranges;
+                ti,cs-chipselect = <0>;
+                /* all timings in nanoseconds */
+                ti,cs-min-turnaround-ns = <12>;
+                ti,cs-read-hold-ns = <6>;
+                ti,cs-read-strobe-ns = <23>;
+                ti,cs-read-setup-ns = <9>;
+                ti,cs-write-hold-ns = <8>;
+                ti,cs-write-strobe-ns = <23>;
+                ti,cs-write-setup-ns = <8>;
+                nand@0,0 {
+                        compatible = "ti,keystone-nand","ti,davinci-nand";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0 0 0x4000000
+                               1 0 0x0000100>;
+                        ti,davinci-chipselect = <0>;
+                        ti,davinci-mask-ale = <0x2000>;
+                        ti,davinci-mask-cle = <0x4000>;
+                        ti,davinci-mask-chipsel = <0>;
+                        nand-ecc-mode = "hw";
+                        ti,davinci-ecc-bits = <4>;
+                        nand-on-flash-bbt;
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0 0x100000>;
+                                read-only;
+                        };
+                        partition@100000 {
+                                label = "params";
+                                reg = <0x100000 0x80000>;
+                                read-only;
+                        };
+                        partition@180000 {
+                                label = "ubifs";
+                                reg = <0x180000 0x7FE80000>;
+                        };
+                };
+        };
+};
+&spi0 {
+        nor_flash: n25q128a11@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "Micron,n25q128a11";
+                spi-max-frequency = <54000000>;
+                m25p,fast-read;
+                reg = <0>;
+                partition@0 {
+                        label = "u-boot-spl";
+                        reg = <0x0 0x80000>;
+                        read-only;
+                };
+                partition@1 {
+                        label = "misc";
+                        reg = <0x80000 0xf80000>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 90823eb90c1b..d9f99e7deb83 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -28,8 +28,6 @@
        gic: interrupt-controller {
                compatible = "arm,cortex-a15-gic";
                #interrupt-cells = <3>;
-                #size-cells = <0>;
-                #address-cells = <1>;
                interrupt-controller;
                reg = <0x0 0x02561000 0x0 0x1000>,
                      <0x0 0x02562000 0x0 0x2000>,
@@ -66,6 +64,7 @@
                compatible = "ti,keystone","simple-bus";
                interrupt-parent = <&gic>;
                ranges = <0x0 0x0 0x0 0xc0000000>;
+                dma-ranges = <0x80000000 0x8 0x00000000 0x80000000>;
                rstctrl: reset-controller {
                        compatible = "ti,keystone-reset";
@@ -102,11 +101,6 @@
                        interrupts = <GIC_SPI 283 IRQ_TYPE_EDGE_RISING>;
                        #address-cells = <1>;
                        #size-cells = <0>;
-                        dtt@50 {
-                                compatible = "at,24c1024";
-                                reg = <0x50>;
-                        };
                };
                i2c1: i2c@2530400 {
@@ -115,6 +109,8 @@
                        clock-frequency = <100000>;
                        clocks = <&clki2c>;
                        interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c2: i2c@2530800 {
@@ -123,6 +119,8 @@
                        clock-frequency = <100000>;
                        clocks = <&clki2c>;
                        interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                spi0: spi@21000400 {
@@ -132,6 +130,8 @@
                        ti,davinci-spi-intr-line = <0>;
                        interrupts = <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>;
                        clocks = <&clkspi>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                spi1: spi@21000600 {
@@ -141,6 +141,8 @@
                        ti,davinci-spi-intr-line = <0>;
                        interrupts = <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>;
                        clocks = <&clkspi>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                spi2: spi@21000800 {
@@ -150,6 +152,8 @@
                        ti,davinci-spi-intr-line = <0>;
                        interrupts = <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>;
                        clocks = <&clkspi>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                usb_phy: usb_phy@2620738 {
@@ -169,6 +173,8 @@
                        clock-names = "usb";
                        interrupts = <GIC_SPI 393 IRQ_TYPE_EDGE_RISING>;
                        ranges;
+                        dma-coherent;
+                        dma-ranges;
                        status = "disabled";
                        dwc3@2690000 {
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
index 3916937d6818..dd81508b919b 100644
--- a/arch/arm/boot/dts/kirkwood-6192.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -1,6 +1,6 @@
 / {
        mbus {
-                pcie-controller {
+                pciec: pcie-controller {
                        compatible = "marvell,kirkwood-pcie";
                        status = "disabled";
                        device_type = "pci";
@@ -15,7 +15,7 @@
                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
-                        pcie@1,0 {
+                        pcie0: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
@@ -35,16 +35,9 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        compatible = "marvell,88f6192-pinctrl";
-                        reg = <0x10000 0x20>;
-                        pmx_nand: pmx-nand {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                               "mpp4", "mpp5", "mpp18",
-                                               "mpp19";
-                                marvell,function = "nand";
-                        };
                        pmx_sata0: pmx-sata0 {
                                marvell,pins = "mpp5", "mpp21", "mpp23";
                                marvell,function = "sata0";
@@ -53,22 +46,6 @@
                                marvell,pins = "mpp4", "mpp20", "mpp22";
                                marvell,function = "sata1";
                        };
-                        pmx_spi: pmx-spi {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
-                                marvell,function = "spi";
-                        };
-                        pmx_twsi0: pmx-twsi0 {
-                                marvell,pins = "mpp8", "mpp9";
-                                marvell,function = "twsi0";
-                        };
-                        pmx_uart0: pmx-uart0 {
-                                marvell,pins = "mpp10", "mpp11";
-                                marvell,function = "uart0";
-                        };
-                        pmx_uart1: pmx-uart1 {
-                                marvell,pins = "mpp13", "mpp14";
-                                marvell,function = "uart1";
-                        };
                        pmx_sdio: pmx-sdio {
                                marvell,pins = "mpp12", "mpp13", "mpp14",
                                               "mpp15", "mpp16", "mpp17";
@@ -76,14 +53,14 @@
                        };
                };
-                rtc@10300 {
+                rtc: rtc@10300 {
                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                        reg = <0x10300 0x20>;
                        interrupts = <53>;
                        clocks = <&gate_clk 7>;
                };
-                sata@80000 {
+                sata: sata@80000 {
                        compatible = "marvell,orion-sata";
                        reg = <0x80000 0x5000>;
                        interrupts = <21>;
@@ -92,7 +69,7 @@
                        status = "disabled";
                };
-                mvsdio@90000 {
+                sdio: mvsdio@90000 {
                        compatible = "marvell,orion-sdio";
                        reg = <0x90000 0x200>;
                        interrupts = <28>;
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 416d96e1302f..7dc7d6782e83 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -1,6 +1,6 @@
 / {
        mbus {
-                pcie-controller {
+                pciec: pcie-controller {
                        compatible = "marvell,kirkwood-pcie";
                        status = "disabled";
                        device_type = "pci";
@@ -15,7 +15,7 @@
                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
-                        pcie@1,0 {
+                        pcie0: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
@@ -35,16 +35,9 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        compatible = "marvell,88f6281-pinctrl";
-                        reg = <0x10000 0x20>;
-                        pmx_nand: pmx-nand {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                               "mpp4", "mpp5", "mpp18",
-                                               "mpp19";
-                                marvell,function = "nand";
-                        };
                        pmx_sata0: pmx-sata0 {
                                marvell,pins = "mpp5", "mpp21", "mpp23";
                                marvell,function = "sata0";
@@ -53,22 +46,6 @@
                                marvell,pins = "mpp4", "mpp20", "mpp22";
                                marvell,function = "sata1";
                        };
-                        pmx_spi: pmx-spi {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
-                                marvell,function = "spi";
-                        };
-                        pmx_twsi0: pmx-twsi0 {
-                                marvell,pins = "mpp8", "mpp9";
-                                marvell,function = "twsi0";
-                        };
-                        pmx_uart0: pmx-uart0 {
-                                marvell,pins = "mpp10", "mpp11";
-                                marvell,function = "uart0";
-                        };
-                        pmx_uart1: pmx-uart1 {
-                                marvell,pins = "mpp13", "mpp14";
-                                marvell,function = "uart1";
-                        };
                        pmx_sdio: pmx-sdio {
                                marvell,pins = "mpp12", "mpp13", "mpp14",
                                               "mpp15", "mpp16", "mpp17";
@@ -76,14 +53,14 @@
                        };
                };
-                rtc@10300 {
+                rtc: rtc@10300 {
                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                        reg = <0x10300 0x20>;
                        interrupts = <53>;
                        clocks = <&gate_clk 7>;
                };
-                sata@80000 {
+                sata: sata@80000 {
                        compatible = "marvell,orion-sata";
                        reg = <0x80000 0x5000>;
                        interrupts = <21>;
@@ -94,7 +71,7 @@
                        status = "disabled";
                };
-                mvsdio@90000 {
+                sdio: mvsdio@90000 {
                        compatible = "marvell,orion-sdio";
                        reg = <0x90000 0x200>;
                        interrupts = <28>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index 2902e0d7971d..4680eec990f0 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,6 +1,6 @@
 / {
        mbus {
-                pcie-controller {
+                pciec: pcie-controller {
                        compatible = "marvell,kirkwood-pcie";
                        status = "disabled";
                        device_type = "pci";
@@ -19,7 +19,7 @@
                                0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */
                                0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;
-                        pcie@1,0 {
+                        pcie0: pcie@1,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
                                reg = <0x0800 0 0 0 0>;
@@ -36,7 +36,7 @@
                                status = "disabled";
                        };
-                        pcie@2,0 {
+                        pcie1: pcie@2,0 {
                                device_type = "pci";
                                assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
                                reg = <0x1000 0 0 0 0>;
@@ -56,15 +56,8 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        compatible = "marvell,88f6282-pinctrl";
-                        reg = <0x10000 0x20>;
-                        pmx_nand: pmx-nand {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                                        "mpp4", "mpp5", "mpp18", "mpp19";
-                                marvell,function = "nand";
-                        };
                        pmx_sata0: pmx-sata0 {
                                marvell,pins = "mpp5", "mpp21", "mpp23";
@@ -74,29 +67,16 @@
                                marvell,pins = "mpp4", "mpp20", "mpp22";
                                marvell,function = "sata1";
                        };
-                        pmx_spi: pmx-spi {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
-                                marvell,function = "spi";
-                        };
-                        pmx_twsi0: pmx-twsi0 {
-                                marvell,pins = "mpp8", "mpp9";
-                                marvell,function = "twsi0";
-                        };
+                        /*
+                         * Default I2C1 pinctrl setting on mpp36/mpp37,
+                         * overwrite marvell,pins on board level if required.
+                         */
                        pmx_twsi1: pmx-twsi1 {
                                marvell,pins = "mpp36", "mpp37";
                                marvell,function = "twsi1";
                        };
-                        pmx_uart0: pmx-uart0 {
-                                marvell,pins = "mpp10", "mpp11";
-                                marvell,function = "uart0";
-                        };
-                        pmx_uart1: pmx-uart1 {
-                                marvell,pins = "mpp13", "mpp14";
-                                marvell,function = "uart1";
-                        };
                        pmx_sdio: pmx-sdio {
                                marvell,pins = "mpp12", "mpp13", "mpp14",
                                               "mpp15", "mpp16", "mpp17";
@@ -104,20 +84,20 @@
                        };
                };
-                thermal@10078 {
+                thermal: thermal@10078 {
                        compatible = "marvell,kirkwood-thermal";
                        reg = <0x10078 0x4>;
                        status = "okay";
                };
-                rtc@10300 {
+                rtc: rtc@10300 {
                        compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
                        reg = <0x10300 0x20>;
                        interrupts = <53>;
                        clocks = <&gate_clk 7>;
                };
-                i2c@11100 {
+                i2c1: i2c@11100 {
                        compatible = "marvell,mv64xxx-i2c";
                        reg = <0x11100 0x20>;
                        #address-cells = <1>;
@@ -125,10 +105,12 @@
                        interrupts = <32>;
                        clock-frequency = <100000>;
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_twsi1>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
-                sata@80000 {
+                sata: sata@80000 {
                        compatible = "marvell,orion-sata";
                        reg = <0x80000 0x5000>;
                        interrupts = <21>;
@@ -139,7 +121,7 @@
                        status = "disabled";
                };
-                mvsdio@90000 {
+                sdio: mvsdio@90000 {
                        compatible = "marvell,orion-sdio";
                        reg = <0x90000 0x200>;
                        interrupts = <28>;
diff --git a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
index 3271e4c8ea07..9e1f741d74ff 100644
--- a/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
+++ b/arch/arm/boot/dts/kirkwood-98dx4122.dtsi
@@ -1,31 +1,51 @@
 / {
+        mbus {
+                pciec: pcie-controller {
+                        compatible = "marvell,kirkwood-pcie";
+                        status = "disabled";
+                        device_type = "pci";
+                        #address-cells = <3>;
+                        #size-cells = <2>;
+                        bus-range = <0x00 0xff>;
+                        ranges =
+                               <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
+                                0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
+                                0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;
+                        pcie0: pcie@1,0 {
+                                device_type = "pci";
+                                assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
+                                reg = <0x0800 0 0 0 0>;
+                                #address-cells = <3>;
+                                #size-cells = <2>;
+                                #interrupt-cells = <1>;
+                                ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
+                                          0x81000000 0 0 0x81000000 0x1 0 1 0>;
+                                interrupt-map-mask = <0 0 0 0>;
+                                interrupt-map = <0 0 0 0 &intc 9>;
+                                marvell,pcie-port = <0>;
+                                marvell,pcie-lane = <0>;
+                                clocks = <&gate_clk 2>;
+                                status = "disabled";
+                        };
+                };
+        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        compatible = "marvell,98dx4122-pinctrl";
-                        reg = <0x10000 0x20>;
-                        pmx_nand: pmx-nand {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
-                                               "mpp4", "mpp5", "mpp18",
-                                               "mpp19";
-                                marvell,function = "nand";
-                        };
-                        pmx_spi: pmx-spi {
-                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
-                                marvell,function = "spi";
-                        };
-                        pmx_twsi0: pmx-twsi0 {
-                                marvell,pins = "mpp8", "mpp9";
-                                marvell,function = "twsi0";
-                        };
-                        pmx_uart0: pmx-uart0 {
-                                marvell,pins = "mpp10", "mpp11";
-                                marvell,function = "uart0";
-                        };
-                        pmx_uart1: pmx-uart1 {
-                                marvell,pins = "mpp13", "mpp14";
-                                marvell,function = "uart1";
-                        };
                };
        };
 };
+&sata_phy0 {
+        status = "disabled";
+};
+&sata_phy1 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/kirkwood-b3.dts b/arch/arm/boot/dts/kirkwood-b3.dts
index 6becedebaa4e..c9247f8672ae 100644
--- a/arch/arm/boot/dts/kirkwood-b3.dts
+++ b/arch/arm/boot/dts/kirkwood-b3.dts
@@ -30,6 +30,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        mbus {
@@ -44,7 +45,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_button_power: pmx-button-power {
                                marvell,pins = "mpp39";
                                marvell,function = "gpio";
@@ -69,8 +70,6 @@
                spi@10600 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        m25p16@0 {
                                #address-cells = <1>;
@@ -113,8 +112,6 @@
                         * UART0_TX = Testpoint 66
                         * See the Excito Wiki for more details.
                         */
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 3b62aeeaa3a2..ab6ab4933e6b 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
                                marvell,pins = "mpp15";
                                marvell,function = "sata0";
@@ -25,9 +26,6 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
-                        clock-frequency = <166666667>;
                        status = "okay";
                };
@@ -39,8 +37,6 @@
                };
                spi@10600 {
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index 02d1225ef99f..812df691ae3d 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -22,10 +22,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl@10000 {
+                pin-controller@10000 {
                        pmx_sdio_gpios: pmx-sdio-gpios {
                                marvell,pins = "mpp37", "mpp38";
                                marvell,function = "gpio";
@@ -33,10 +34,7 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
+                        status = "okay";
-                        pinctrl-names = "default";
-                        clock-frequency = <200000000>;
-                        status = "ok";
                };
                sata@80000 {
@@ -59,8 +57,6 @@
 };
 &nand {
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        chip-delay = <25>;
        status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index bf7fe8ab88f4..d85ef0a91b50 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -13,6 +13,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        gpio-leds {
@@ -51,8 +52,6 @@
                };
                serial@12100 {
-                        pinctrl-0 = <&pmx_uart1>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
        };
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index cb9978c652f2..5e586ed04c58 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -13,6 +13,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        gpio-leds {
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index d5aa9564a287..113dcf056dcf 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -50,7 +50,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_power_back_on &pmx_present_sata0
                                     &pmx_present_sata1 &pmx_fan_tacho
@@ -183,8 +183,6 @@
 };
 &nand {
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        status = "okay";
        chip-delay = <35>;
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index f31312ebd0d6..849736349511 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp29";
                                marvell,function = "gpio";
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 28b3ee369778..6467c7924195 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_led_bluetooth: pmx-led-bluetooth {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
@@ -37,8 +38,6 @@
                spi@10600 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        m25p40@0 {
                                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ds109.dts b/arch/arm/boot/dts/kirkwood-ds109.dts
index 772092c94ca3..d4bcc1c7f6b3 100644
--- a/arch/arm/boot/dts/kirkwood-ds109.dts
+++ b/arch/arm/boot/dts/kirkwood-ds109.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds110jv10.dts b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
index aabafbe0da4c..95bf83b91b4a 100644
--- a/arch/arm/boot/dts/kirkwood-ds110jv10.dts
+++ b/arch/arm/boot/dts/kirkwood-ds110jv10.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds111.dts b/arch/arm/boot/dts/kirkwood-ds111.dts
index 16ec7fbab573..61f47fbe44d0 100644
--- a/arch/arm/boot/dts/kirkwood-ds111.dts
+++ b/arch/arm/boot/dts/kirkwood-ds111.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-1 {
diff --git a/arch/arm/boot/dts/kirkwood-ds112.dts b/arch/arm/boot/dts/kirkwood-ds112.dts
index cff1b2388765..bf4143c6cb8f 100644
--- a/arch/arm/boot/dts/kirkwood-ds112.dts
+++ b/arch/arm/boot/dts/kirkwood-ds112.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-1 {
diff --git a/arch/arm/boot/dts/kirkwood-ds209.dts b/arch/arm/boot/dts/kirkwood-ds209.dts
index 330411993d38..6d25093a9ac4 100644
--- a/arch/arm/boot/dts/kirkwood-ds209.dts
+++ b/arch/arm/boot/dts/kirkwood-ds209.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds210.dts b/arch/arm/boot/dts/kirkwood-ds210.dts
index 6052eaa37d4f..2f1933efcac1 100644
--- a/arch/arm/boot/dts/kirkwood-ds210.dts
+++ b/arch/arm/boot/dts/kirkwood-ds210.dts
@@ -26,6 +26,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds212.dts b/arch/arm/boot/dts/kirkwood-ds212.dts
index 7f76cd30e84e..99afd462f956 100644
--- a/arch/arm/boot/dts/kirkwood-ds212.dts
+++ b/arch/arm/boot/dts/kirkwood-ds212.dts
@@ -27,6 +27,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-1 {
diff --git a/arch/arm/boot/dts/kirkwood-ds212j.dts b/arch/arm/boot/dts/kirkwood-ds212j.dts
index 1f83a00f1f74..f5c4213fc67c 100644
--- a/arch/arm/boot/dts/kirkwood-ds212j.dts
+++ b/arch/arm/boot/dts/kirkwood-ds212j.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds409.dts b/arch/arm/boot/dts/kirkwood-ds409.dts
index 0a573add44a2..e80a962ebba0 100644
--- a/arch/arm/boot/dts/kirkwood-ds409.dts
+++ b/arch/arm/boot/dts/kirkwood-ds409.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-15-18 {
diff --git a/arch/arm/boot/dts/kirkwood-ds409slim.dts b/arch/arm/boot/dts/kirkwood-ds409slim.dts
index 1848a6245fd3..cae5af4b88b5 100644
--- a/arch/arm/boot/dts/kirkwood-ds409slim.dts
+++ b/arch/arm/boot/dts/kirkwood-ds409slim.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-32-35 {
diff --git a/arch/arm/boot/dts/kirkwood-ds411.dts b/arch/arm/boot/dts/kirkwood-ds411.dts
index a1737b4311c6..623cd4a37d71 100644
--- a/arch/arm/boot/dts/kirkwood-ds411.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-1 {
diff --git a/arch/arm/boot/dts/kirkwood-ds411j.dts b/arch/arm/boot/dts/kirkwood-ds411j.dts
index 0cde914eceae..3348e330f074 100644
--- a/arch/arm/boot/dts/kirkwood-ds411j.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411j.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-15-18 {
diff --git a/arch/arm/boot/dts/kirkwood-ds411slim.dts b/arch/arm/boot/dts/kirkwood-ds411slim.dts
index aef0cadc2c78..a0a1fad8b4de 100644
--- a/arch/arm/boot/dts/kirkwood-ds411slim.dts
+++ b/arch/arm/boot/dts/kirkwood-ds411slim.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-1 {
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index eb9329420107..aa60a0b049a7 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp29";
                                marvell,function = "gpio";
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 2d51fce74a5a..c5a1fc75c7a3 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_led_health_r: pmx-led-health-r {
                                marvell,pins = "mpp46";
                                marvell,function = "gpio";
@@ -36,7 +37,6 @@
                        };
                };
                serial@12000 {
-                        clock-frequency = <200000000>;
                        status = "ok";
                };
@@ -101,13 +101,19 @@
        status = "okay";
        ethphy0: ethernet-phy@0 {
-                compatible = "marvell,88e1121";
+                /* Marvell 88E1121R */
+                compatible = "ethernet-phy-id0141.0cb0",
+                             "ethernet-phy-ieee802.3-c22";
                reg = <0>;
+                phy-connection-type = "rgmii-id";
        };
        ethphy1: ethernet-phy@1 {
-                compatible = "marvell,88e1121";
+                /* Marvell 88E1121R */
+                compatible = "ethernet-phy-id0141.0cb0",
+                             "ethernet-phy-ieee802.3-c22";
                reg = <1>;
+                phy-connection-type = "rgmii-id";
        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index a1add3f215e3..bfa5edde179c 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_led_os_red: pmx-led-os-red {
                                marvell,pins = "mpp22";
                                marvell,function = "gpio";
@@ -104,8 +105,6 @@
 &nand {
        status = "okay";
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        partition@0 {
                label = "u-boot";
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 8d8c80e3656d..38e31d15a62d 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -14,6 +14,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
                linux,initrd-start = <0x4500040>;
                linux,initrd-end   = <0x4800000>;
        };
@@ -29,7 +30,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_button_reset: pmx-button-reset {
                                marvell,pins = "mpp12";
                                marvell,function = "gpio";
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 59e7a5adeedb..05291f3990d0 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = < &pmx_led_sata_brt_ctrl_1
                                      &pmx_led_sata_brt_ctrl_2
                                      &pmx_led_backup_brt_ctrl_1
diff --git a/arch/arm/boot/dts/kirkwood-km_common.dtsi b/arch/arm/boot/dts/kirkwood-km_common.dtsi
new file mode 100644
index 000000000000..8367c772c764
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_common.dtsi
@@ -0,0 +1,48 @@
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pin-controller@10000 {
+                        pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
+                        pinctrl-names = "default";
+                        pmx_i2c_gpio_sda: pmx-gpio-sda {
+                                marvell,pins = "mpp8";
+                                marvell,function = "gpio";
+                        };
+                        pmx_i2c_gpio_scl: pmx-gpio-scl {
+                                marvell,pins = "mpp9";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+        };
+        i2c@0 {
+                compatible = "i2c-gpio";
+                gpios = < &gpio0 8 GPIO_ACTIVE_HIGH             /* sda */
+                          &gpio0 9 GPIO_ACTIVE_HIGH>;           /* scl */
+                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
+        };
+};
+&nand {
+        status = "okay";
+        chip-delay = <25>;
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_fixedeth.dts b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts
new file mode 100644
index 000000000000..9895f2b10f8a
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_fixedeth.dts
@@ -0,0 +1,23 @@
+/dts-v1/;
+#include "kirkwood.dtsi"
+#include "kirkwood-98dx4122.dtsi"
+#include "kirkwood-km_common.dtsi"
+/ {
+        model = "Keymile Kirkwood Fixed Eth";
+        compatible = "keymile,km_fixedeth", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                speed = <1000>;  /* <SPEED_1000> */
+                duplex = <1>; /* <DUPLEX_FULL> */
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 04a1e44541b3..235bf382fff9 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -2,6 +2,7 @@
 #include "kirkwood.dtsi"
 #include "kirkwood-98dx4122.dtsi"
+#include "kirkwood-km_common.dtsi"
 / {
        model = "Keymile Kirkwood Reference Design";
@@ -11,44 +12,6 @@
                device_type = "memory";
                reg = <0x00000000 0x08000000>;
        };
-        chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk";
-        };
-        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
-                        pinctrl-0 = < &pmx_i2c_gpio_sda &pmx_i2c_gpio_scl >;
-                        pinctrl-names = "default";
-                        pmx_i2c_gpio_sda: pmx-gpio-sda {
-                                marvell,pins = "mpp8";
-                                marvell,function = "gpio";
-                        };
-                        pmx_i2c_gpio_scl: pmx-gpio-scl {
-                                marvell,pins = "mpp9";
-                                marvell,function = "gpio";
-                        };
-                };
-                serial@12000 {
-                        status = "ok";
-                };
-        };
-        i2c@0 {
-                compatible = "i2c-gpio";
-                gpios = < &gpio0 8 GPIO_ACTIVE_HIGH             /* sda */
-                          &gpio0 9 GPIO_ACTIVE_HIGH>;           /* scl */
-                i2c-gpio,delay-us = <2>;        /* ~100 kHz */
-        };
-};
-&nand {
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
-        status = "ok";
-        chip-delay = <25>;
 };
 &mdio {
diff --git a/arch/arm/boot/dts/kirkwood-laplug.dts b/arch/arm/boot/dts/kirkwood-laplug.dts
index 6761ffa2c4ab..24425660e973 100644
--- a/arch/arm/boot/dts/kirkwood-laplug.dts
+++ b/arch/arm/boot/dts/kirkwood-laplug.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        mbus {
@@ -37,14 +38,10 @@
        ocp@f1000000 {
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
                i2c@11000 {
-                        pinctrl-0 = <&pmx_twsi0>;
-                        pinctrl-names = "default";
                        status = "okay";
                        eeprom@50 {
@@ -54,7 +51,7 @@
                        };
                };
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp14";
                                marvell,function = "gpio";
@@ -139,7 +136,6 @@
 &nand {
        /* Total size : 512MB */
        status = "okay";
-        pinctrl-0 = <&pmx_nand>;
        partition@0 {
                label = "u-boot";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 1656653d339b..53484474df1f 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -4,10 +4,11 @@
 / {
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_power_hdd: pmx-power-hdd {
                                marvell,pins = "mpp10";
                                marvell,function = "gpo";
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 73722c067501..f3a991837515 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -12,9 +12,10 @@
                reg = <0x00000000 0x20000000>;
        };
-        chosen {
+        chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
-        };
+                stdout-path = &uart0;
+        };
        mbus {
                pcie-controller {
@@ -27,7 +28,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_led_health: pmx-led-health {
                                marvell,pins = "mpp7";
                                marvell,function = "gpo";
@@ -89,11 +90,9 @@
                };
-                serial@12000 {
+                serial@12000 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
+                };
-                        pinctrl-names = "default";
-                };
                rtc@10300 {
                        status = "disabled";
@@ -163,8 +162,6 @@
 };
 &nand {
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        status = "okay";
        partition@0 {
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
index 32c6fb4a1162..8f76d28759a3 100644
--- a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -28,10 +28,21 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
        ocp@f1000000 {
-                pinctrl@10000 {
+                pin-controller@10000 {
                        pmx_usb_led: pmx-usb-led {
                                marvell,pins = "mpp12";
                                marvell,function = "gpo";
@@ -49,8 +60,6 @@
                };
                spi@10600 {
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
@@ -64,22 +73,11 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
-                        clock-frequency = <200000000>;
-                        status = "ok";
-                };
-                ehci@50000 {
                        status = "okay";
                };
-                pcie-controller {
+                ehci@50000 {
                        status = "okay";
-                        pcie@1,0 {
-                                status = "okay";
-                        };
                };
        };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index 4838478019cc..fd733c63bc27 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        mbus {
@@ -38,7 +39,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_button_power: pmx-button-power {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
@@ -112,8 +113,6 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
index 7c8a0d9d8d1f..b514d643fb6c 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_nv+_v2.dts
@@ -25,6 +25,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        mbus {
@@ -40,7 +41,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_button_power: pmx-button-power {
                                marvell,pins = "mpp47";
                                marvell,function = "gpio";
@@ -119,8 +120,6 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index e6e5ec4fe6b9..fe6c0246db1a 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -4,10 +4,11 @@
 / {
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_ns2_sata0: pmx-ns2-sata0 {
                                marvell,pins = "mpp21";
                                marvell,function = "sata0";
@@ -19,14 +20,10 @@
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
                spi@10600 {
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
@@ -45,8 +42,6 @@
                };
                i2c@11000 {
-                        pinctrl-0 = <&pmx_twsi0>;
-                        pinctrl-names = "default";
                        status = "okay";
                        eeprom@50 {
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 0a07af9d8e58..6139df0f376c 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-#include "kirkwood-nsa310-common.dtsi"
+#include "kirkwood-nsa3x0-common.dtsi"
 / {
        compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
@@ -12,6 +12,7 @@
        chosen {
                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
        };
        mbus {
@@ -25,7 +26,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_unknown>;
                        pinctrl-names = "default";
@@ -59,26 +60,6 @@
                                marvell,function = "gpio";
                        };
-                        pmx_btn_reset: pmx-btn-reset {
-                                marvell,pins = "mpp36";
-                                marvell,function = "gpio";
-                        };
-                        pmx_btn_copy: pmx-btn-copy {
-                                marvell,pins = "mpp37";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_copy_green: pmx-led-copy-green {
-                                marvell,pins = "mpp39";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_copy_red: pmx-led-copy-red {
-                                marvell,pins = "mpp40";
-                                marvell,function = "gpio";
-                        };
                        pmx_led_hdd_green: pmx-led-hdd-green {
                                marvell,pins = "mpp41";
                                marvell,function = "gpio";
@@ -94,10 +75,6 @@
                                marvell,function = "gpio";
                        };
-                        pmx_btn_power: pmx-btn-power {
-                                marvell,pins = "mpp46";
-                                marvell,function = "gpio";
-                        };
                };
                i2c@11000 {
@@ -110,30 +87,6 @@
                };
        };
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
-                pinctrl-names = "default";
-                button@1 {
-                        label = "Power Button";
-                        linux,code = <KEY_POWER>;
-                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-                };
-                button@2 {
-                        label = "Copy Button";
-                        linux,code = <KEY_COPY>;
-                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
-                };
-                button@3 {
-                        label = "Reset Button";
-                        linux,code = <KEY_RESTART>;
-                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-                };
-        };
        gpio-leds {
                compatible = "gpio-leds";
                pinctrl-0 = <&pmx_led_esata_green &pmx_led_esata_red
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
index 27ca6a79c48a..3d2b3d494c19 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310a.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -1,6 +1,6 @@
 /dts-v1/;
-#include "kirkwood-nsa310-common.dtsi"
+#include "kirkwood-nsa3x0-common.dtsi"
 /*
 * There are at least two different NSA310 designs. This variant does
@@ -17,10 +17,11 @@
        chosen {
                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-names = "default";
                        pmx_led_esata_green: pmx-led-esata-green {
@@ -38,11 +39,6 @@
                                marvell,function = "gpio";
                        };
-                        pmx_usb_power_off: pmx-usb-power-off {
-                                marvell,pins = "mpp21";
-                                marvell,function = "gpio";
-                        };
                        pmx_led_sys_green: pmx-led-sys-green {
                                marvell,pins = "mpp28";
                                marvell,function = "gpio";
@@ -53,26 +49,6 @@
                                marvell,function = "gpio";
                        };
-                        pmx_btn_reset: pmx-btn-reset {
-                                marvell,pins = "mpp36";
-                                marvell,function = "gpio";
-                        };
-                        pmx_btn_copy: pmx-btn-copy {
-                                marvell,pins = "mpp37";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_copy_green: pmx-led-copy-green {
-                                marvell,pins = "mpp39";
-                                marvell,function = "gpio";
-                        };
-                        pmx_led_copy_red: pmx-led-copy-red {
-                                marvell,pins = "mpp40";
-                                marvell,function = "gpio";
-                        };
                        pmx_led_hdd_green: pmx-led-hdd-green {
                                marvell,pins = "mpp41";
                                marvell,function = "gpio";
@@ -83,11 +59,6 @@
                                marvell,function = "gpio";
                        };
-                        pmx_btn_power: pmx-btn-power {
-                                marvell,pins = "mpp46";
-                                marvell,function = "gpio";
-                        };
                };
                i2c@11000 {
@@ -100,28 +71,6 @@
                };
        };
-        gpio_keys {
-                compatible = "gpio-keys";
-                #address-cells = <1>;
-                #size-cells = <0>;
-                button@1 {
-                        label = "Power Button";
-                        linux,code = <KEY_POWER>;
-                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-                };
-                button@2 {
-                        label = "Copy Button";
-                        linux,code = <KEY_COPY>;
-                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
-                };
-                button@3 {
-                        label = "Reset Button";
-                        linux,code = <KEY_RESTART>;
-                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
-                };
-        };
        gpio-leds {
                compatible = "gpio-leds";
diff --git a/arch/arm/boot/dts/kirkwood-nsa320.dts b/arch/arm/boot/dts/kirkwood-nsa320.dts
new file mode 100644
index 000000000000..24f686d1044d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa320.dts
@@ -0,0 +1,215 @@
+/* Device tree file for the Zyxel NSA 320 NAS box.
+ *
+ * Copyright (c) 2014, Adam Baker <linux@baker-net.org.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * Based upon the board setup file created by Peter Schildmann */
+/dts-v1/;
+#include "kirkwood-nsa3x0-common.dtsi"
+/ {
+        model = "Zyxel NSA320";
+        compatible = "zyxel,nsa320", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200";
+                stdout-path = &uart0;
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pin-controller@10000 {
+                        pinctrl-names = "default";
+                        /* SATA Activity and Present pins are not connected */
+                        pmx_sata0: pmx-sata0 {
+                                marvell,pins ;
+                                marvell,function = "sata0";
+                        };
+                        pmx_sata1: pmx-sata1 {
+                                marvell,pins ;
+                                marvell,function = "sata1";
+                        };
+                        pmx_led_hdd2_green: pmx-led-hdd2-green {
+                                marvell,pins = "mpp12";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_hdd2_red: pmx-led-hdd2-red {
+                                marvell,pins = "mpp13";
+                                marvell,function = "gpio";
+                        };
+                        pmx_mcu_data: pmx-mcu-data {
+                                marvell,pins = "mpp14";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_usb_green: pmx-led-usb-green {
+                                marvell,pins = "mpp15";
+                                marvell,function = "gpio";
+                        };
+                        pmx_mcu_clk: pmx-mcu-clk {
+                                marvell,pins = "mpp16";
+                                marvell,function = "gpio";
+                        };
+                        pmx_mcu_act: pmx-mcu-act {
+                                marvell,pins = "mpp17";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_green: pmx-led-sys-green {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_sys_orange: pmx-led-sys-orange {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_hdd1_green: pmx-led-hdd1-green {
+                                marvell,pins = "mpp41";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_hdd1_red: pmx-led-hdd1-red {
+                                marvell,pins = "mpp42";
+                                marvell,function = "gpio";
+                        };
+                        pmx_htp: pmx-htp {
+                                marvell,pins = "mpp43";
+                                marvell,function = "gpio";
+                        };
+                        /* Buzzer needs to be switched at around 1kHz so is
+                           not compatible with the gpio-beeper driver. */
+                        pmx_buzzer: pmx-buzzer {
+                                marvell,pins = "mpp44";
+                                marvell,function = "gpio";
+                        };
+                        pmx_vid_b1: pmx-vid-b1 {
+                                marvell,pins = "mpp45";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_resume_data: pmx-power-resume-data {
+                                marvell,pins = "mpp47";
+                                marvell,function = "gpio";
+                        };
+                        pmx_power_resume_clk: pmx-power-resume-clk {
+                                marvell,pins = "mpp49";
+                                marvell,function = "gpio";
+                        };
+                };
+                i2c@11000 {
+                        status = "okay";
+                        pcf8563: pcf8563@51 {
+                                compatible = "nxp,pcf8563";
+                                reg = <0x51>;
+                        };
+                };
+        };
+        regulators {
+                usb0_power: regulator@1 {
+                        enable-active-high;
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_led_hdd2_green &pmx_led_hdd2_red
+                             &pmx_led_usb_green
+                             &pmx_led_sys_green &pmx_led_sys_orange
+                             &pmx_led_copy_green &pmx_led_copy_red
+                             &pmx_led_hdd1_green &pmx_led_hdd1_red>;
+                pinctrl-names = "default";
+                green-sys {
+                        label = "nsa320:green:sys";
+                        gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
+                };
+                orange-sys {
+                        label = "nsa320:orange:sys";
+                        gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
+                };
+                green-hdd1 {
+                        label = "nsa320:green:hdd1";
+                        gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+                };
+                red-hdd1 {
+                        label = "nsa320:red:hdd1";
+                        gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+                };
+                green-hdd2 {
+                        label = "nsa320:green:hdd2";
+                        gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+                red-hdd2 {
+                        label = "nsa320:red:hdd2";
+                        gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+                };
+                green-usb {
+                        label = "nsa320:green:usb";
+                        gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+                };
+                green-copy {
+                        label = "nsa320:green:copy";
+                        gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
+                };
+                red-copy {
+                        label = "nsa320:red:copy";
+                        gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        /* The following pins are currently not assigned to a driver,
+           some of them should be configured as inputs.
+        pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act
+                     &pmx_htp &pmx_vid_b1
+                     &pmx_power_resume_data &pmx_power_resume_clk>; */
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi
index aa78c2d11fe7..2075a2e828f1 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-nsa3x0-common.dtsi
@@ -4,18 +4,53 @@
 / {
        model = "ZyXEL NSA310";
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
-                        pmx_usb_power_off: pmx-usb-power-off {
+                        pmx_usb_power: pmx-usb-power {
                                marvell,pins = "mpp21";
                                marvell,function = "gpio";
                        };
                        pmx_pwr_off: pmx-pwr-off {
                                marvell,pins = "mpp48";
                                marvell,function = "gpio";
                        };
+                        pmx_btn_reset: pmx-btn-reset {
+                                marvell,pins = "mpp36";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_copy: pmx-btn-copy {
+                                marvell,pins = "mpp37";
+                                marvell,function = "gpio";
+                        };
+                        pmx_btn_power: pmx-btn-power {
+                                marvell,pins = "mpp46";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_copy_green: pmx-led-copy-green {
+                                marvell,pins = "mpp39";
+                                marvell,function = "gpio";
+                        };
+                        pmx_led_copy_red: pmx-led-copy-red {
+                                marvell,pins = "mpp40";
+                                marvell,function = "gpio";
+                        };
                };
                serial@12000 {
@@ -26,14 +61,6 @@
                        status = "okay";
                        nr-ports = <2>;
                };
-                pcie-controller {
-                        status = "okay";
-                        pcie@1,0 {
-                                status = "okay";
-                        };
-                };
        };
        gpio_poweroff {
@@ -43,17 +70,42 @@
                gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>;
+                pinctrl-names = "default";
+                button@1 {
+                        label = "Power Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+                };
+                button@2 {
+                        label = "Copy Button";
+                        linux,code = <KEY_COPY>;
+                        gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
+                };
+                button@3 {
+                        label = "Reset Button";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+                };
+        };
        regulators {
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <0>;
-                pinctrl-0 = <&pmx_usb_power_off>;
+                pinctrl-0 = <&pmx_usb_power>;
                pinctrl-names = "default";
-                usb0_power_off: regulator@1 {
+                usb0_power: regulator@1 {
                        compatible = "regulator-fixed";
                        reg = <1>;
-                        regulator-name = "USB Power Off";
+                        regulator-name = "USB Power";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
                        regulator-always-on;
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 0650beafc1de..fb9dc227255d 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -14,19 +14,16 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
                serial@12000 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                };
                serial@12100 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart1>;
-                        pinctrl-names = "default";
                };
                sata@80000 {
@@ -36,8 +33,6 @@
                i2c@11100 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_twsi1>;
-                        pinctrl-names = "default";
                        s35390a: s35390a@30 {
                                compatible = "sii,s35390a";
@@ -45,7 +40,7 @@
                        };
                };
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
                        pinctrl-names = "default";
@@ -133,8 +128,6 @@
 &nand {
        chip-delay = <25>;
        status = "okay";
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        partition@0 {
                label = "uboot";
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
index 38520a287514..d5e3bc518968 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a7.dts
@@ -26,19 +26,16 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
                serial@12000 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                };
                serial@12100 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart1>;
-                        pinctrl-names = "default";
                };
                sata@80000 {
@@ -48,8 +45,6 @@
                i2c@11100 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_twsi1>;
-                        pinctrl-names = "default";
                        s24c02: s24c02@50 {
                                compatible = "atmel,24c02";
@@ -57,7 +52,7 @@
                        };
                };
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
                        pinctrl-names = "default";
@@ -109,13 +104,6 @@
                                marvell,pins = "mpp41", "mpp42", "mpp43";
                                marvell,function = "gpio";
                        };
-                        pmx_ge1: pmx-ge1 {
-                                marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
-                                               "mpp24", "mpp25", "mpp26", "mpp27",
-                                               "mpp30", "mpp31", "mpp32", "mpp33";
-                                marvell,function = "ge1";
-                        };
                };
        };
@@ -158,8 +146,6 @@
 &nand {
        chip-delay = <25>;
        status = "okay";
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        partition@0 {
                label = "uboot";
@@ -213,8 +199,6 @@
 &eth1 {
        status = "okay";
-        pinctrl-0 = <&pmx_ge1>;
-        pinctrl-names = "default";
        ethernet1-port@0 {
                phy-handle = <&ethphy1>;
        };
diff --git a/arch/arm/boot/dts/kirkwood-openrd-base.dts b/arch/arm/boot/dts/kirkwood-openrd-base.dts
new file mode 100644
index 000000000000..8af58999606d
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openrd-base.dts
@@ -0,0 +1,42 @@
+/*
+ * Marvell OpenRD Base Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * base variant of the Marvell Kirkwood Development Board.
+ */
+/dts-v1/;
+#include "kirkwood-openrd.dtsi"
+/ {
+        model = "OpenRD Base";
+        compatible = "marvell,openrd-base", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                serial@12100 {
+                        status = "okay";
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@8 {
+                reg = <8>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-openrd-client.dts b/arch/arm/boot/dts/kirkwood-openrd-client.dts
new file mode 100644
index 000000000000..887b9c1fee43
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openrd-client.dts
@@ -0,0 +1,73 @@
+/*
+ * Marvell OpenRD Client Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * client variant of the Marvell Kirkwood Development Board.
+ */
+/dts-v1/;
+#include "kirkwood-openrd.dtsi"
+/ {
+        model = "OpenRD Client";
+        compatible = "marvell,openrd-client", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        cs42l51: cs42l51@4a {
+                                compatible = "cirrus,cs42l51";
+                                reg = <0x4a>;
+                        };
+                };
+        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,mclk-fs = <256>;
+                simple-audio-card,cpu {
+                        sound-dai = <&audio0>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&cs42l51>;
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@8 {
+                reg = <8>;
+        };
+        ethphy1: ethernet-phy@24 {
+                reg = <24>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+&eth1 {
+        status = "okay";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts
new file mode 100644
index 000000000000..9f12f8b53e24
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openrd-ultimate.dts
@@ -0,0 +1,58 @@
+/*
+ * Marvell OpenRD Ultimate Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are specific to OpenRD
+ * ultimate variant of the Marvell Kirkwood Development Board.
+ */
+/dts-v1/;
+#include "kirkwood-openrd.dtsi"
+/ {
+        model = "OpenRD Ultimate";
+        compatible = "marvell,openrd-ultimate", "marvell,openrd", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+                        clock-frequency = <400000>;
+                        cs42l51: cs42l51@4a {
+                                compatible = "cirrus,cs42l51";
+                                reg = <0x4a>;
+                        };
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+        ethphy1: ethernet-phy@1 {
+                reg = <1>;
+        };
+};
+&eth0 {
+        status = "okay";
+        ethernet0-port@0 {
+                phy-handle = <&ethphy0>;
+        };
+};
+&eth1 {
+        status = "okay";
+        ethernet1-port@0 {
+                phy-handle = <&ethphy1>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-openrd.dtsi b/arch/arm/boot/dts/kirkwood-openrd.dtsi
new file mode 100644
index 000000000000..d3330dadf7ed
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-openrd.dtsi
@@ -0,0 +1,90 @@
+/*
+ * Marvell OpenRD (Base|Client|Ultimate) Board Description
+ *
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This file contains the definitions that are common between the three
+ * variants of the Marvell Kirkwood Development Board.
+ */
+#include "kirkwood.dtsi"
+#include "kirkwood-6281.dtsi"
+/ {
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x20000000>;
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
+        };
+        mbus {
+                pcie-controller {
+                        status = "okay";
+                        pcie@1,0 {
+                                status = "okay";
+                        };
+                };
+        };
+        ocp@f1000000 {
+                pinctrl: pin-controller@10000 {
+                        pinctrl-0 = <&pmx_select28 &pmx_sdio_cd &pmx_select34>;
+                        pinctrl-names = "default";
+                        pmx_select28: pmx-select-uart-sd {
+                                marvell,pins = "mpp28";
+                                marvell,function = "gpio";
+                        };
+                        pmx_sdio_cd: pmx-sdio-cd {
+                                marvell,pins = "mpp29";
+                                marvell,function = "gpio";
+                        };
+                        pmx_select34: pmx-select-rs232-rs484 {
+                                marvell,pins = "mpp34";
+                                marvell,function = "gpio";
+                        };
+                };
+                serial@12000 {
+                        status = "okay";
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+                mvsdio@90000 {
+                        status = "okay";
+                        cd-gpios = <&gpio0 29 9>;
+                };
+        };
+};
+&nand {
+        status = "okay";
+        pinctrl-0 = <&pmx_nand>;
+        pinctrl-names = "default";
+        partition@0 {
+                label = "u-boot";
+                reg = <0x0000000 0x100000>;
+        };
+        partition@100000 {
+                label = "uImage";
+                reg = <0x0100000 0x400000>;
+        };
+        partition@600000 {
+                label = "root";
+                reg = <0x0600000 0x1FA00000>;
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6192.dts b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
index e9dd85049297..35a29dee8dd8 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6192.dts
+++ b/arch/arm/boot/dts/kirkwood-rd88f6192.dts
@@ -26,6 +26,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        mbus {
@@ -39,7 +40,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_usb_power>;
                        pinctrl-names = "default";
@@ -56,8 +57,6 @@
                spi@10600 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        m25p128@0 {
                                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
index d6368c39102e..26cf0e0ccefd 100644
--- a/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-rd88f6281.dtsi
@@ -22,6 +22,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        mbus {
@@ -35,7 +36,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_sdio_cd>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/kirkwood-rs212.dts b/arch/arm/boot/dts/kirkwood-rs212.dts
index 93ec3d00c6ab..3b19f1fd4cac 100644
--- a/arch/arm/boot/dts/kirkwood-rs212.dts
+++ b/arch/arm/boot/dts/kirkwood-rs212.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-3 {
diff --git a/arch/arm/boot/dts/kirkwood-rs409.dts b/arch/arm/boot/dts/kirkwood-rs409.dts
index 311df4e5aa28..921ca49e85a4 100644
--- a/arch/arm/boot/dts/kirkwood-rs409.dts
+++ b/arch/arm/boot/dts/kirkwood-rs409.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-150-15-18 {
diff --git a/arch/arm/boot/dts/kirkwood-rs411.dts b/arch/arm/boot/dts/kirkwood-rs411.dts
index f90da850bb31..02852b0c809f 100644
--- a/arch/arm/boot/dts/kirkwood-rs411.dts
+++ b/arch/arm/boot/dts/kirkwood-rs411.dts
@@ -24,6 +24,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        gpio-fan-100-15-35-3 {
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index 1ff848d570a9..7196c7f3e109 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -17,10 +17,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_usb_power_enable: pmx-usb-power-enable {
                                marvell,pins = "mpp29";
@@ -44,8 +45,6 @@
                        };
                };
                serial@12000 {
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                        status = "okay";
                };
        };
@@ -72,8 +71,6 @@
 };
 &nand {
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        status = "okay";
        partition@0 {
diff --git a/arch/arm/boot/dts/kirkwood-synology.dtsi b/arch/arm/boot/dts/kirkwood-synology.dtsi
index 4227c974729d..811e0971fc58 100644
--- a/arch/arm/boot/dts/kirkwood-synology.dtsi
+++ b/arch/arm/boot/dts/kirkwood-synology.dtsi
@@ -25,7 +25,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pmx_alarmled_12: pmx-alarmled-12 {
                                marvell,pins = "mpp12";
                                marvell,function = "gpio";
@@ -213,8 +213,6 @@
                spi@10600 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        m25p80@0 {
                                #address-cells = <1>;
@@ -259,8 +257,6 @@
                i2c@11000 {
                        status = "okay";
                        clock-frequency = <400000>;
-                        pinctrl-0 = <&pmx_twsi0>;
-                        pinctrl-names = "default";
                        rs5c372: rs5c372@32 {
                                status = "disabled";
@@ -277,14 +273,10 @@
                serial@12000 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                };
                serial@12100 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_uart1>;
-                        pinctrl-names = "default";
                };
                poweroff@12100 {
diff --git a/arch/arm/boot/dts/kirkwood-t5325.dts b/arch/arm/boot/dts/kirkwood-t5325.dts
index 7d1c7677a18f..610ec0f95858 100644
--- a/arch/arm/boot/dts/kirkwood-t5325.dts
+++ b/arch/arm/boot/dts/kirkwood-t5325.dts
@@ -27,6 +27,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        mbus {
@@ -40,7 +41,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_i2s &pmx_sysrst>;
                        pinctrl-names = "default";
@@ -64,10 +65,6 @@
                                marvell,function = "gpio";
                        };
-                        /*
-                         * Redefined from kirkwood-6281.dtsi, because
-                         * we don't use SPI CS on MPP0, but on MPP7.
-                         */
                        pmx_spi: pmx-spi {
                                marvell,pins = "mpp1", "mpp2", "mpp3", "mpp7";
                                marvell,function = "spi";
@@ -86,8 +83,6 @@
                };
                spi@10600 {
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        status = "okay";
                        flash@0 {
@@ -131,6 +126,9 @@
                        alc5621: alc5621@1a {
                                compatible = "realtek,alc5621";
                                reg = <0x1a>;
+                                #sound-dai-cells = <0>;
+                                add-ctrl = <0x3700>;
+                                jack-det-ctrl = <0x4810>;
                        };
                };
@@ -189,6 +187,31 @@
                gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
        };
+        sound {
+                compatible = "simple-audio-card";
+                simple-audio-card,format = "i2s";
+                simple-audio-card,routing =
+                        "Headphone Jack", "HPL",
+                        "Headphone Jack", "HPR",
+                        "Speaker", "SPKOUT",
+                        "Speaker", "SPKOUTN",
+                        "MIC1", "Mic Jack",
+                        "MIC2", "Mic Jack";
+                simple-audio-card,widgets =
+                        "Headphone", "Headphone Jack",
+                        "Speaker", "Speaker",
+                        "Microphone", "Mic Jack";
+                simple-audio-card,mclk-fs = <256>;
+                simple-audio-card,cpu {
+                        sound-dai = <&audio>;
+                };
+                simple-audio-card,codec {
+                        sound-dai = <&alc5621>;
+                };
+        };
 };
 &mdio {
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index 5fc817c2cb87..f5c8c0dd41dc 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -14,10 +14,11 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                stdout-path = &uart0;
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        /*
                         * Switch positions
                         *
@@ -85,9 +86,7 @@
                };
                serial@12000 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                };
                sata@80000 {
@@ -96,9 +95,7 @@
                };
                i2c@11000 {
-                        status = "ok";
+                        status = "okay";
-                        pinctrl-0 = <&pmx_twsi0>;
-                        pinctrl-names = "default";
                };
                mvsdio@90000 {
@@ -175,8 +172,6 @@
 &nand {
        status = "okay";
-        pinctrl-0 = <&pmx_nand>;
-        pinctrl-names = "default";
        partition@0 {
                label = "u-boot";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index c17ae45e19be..9767d73f3857 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -6,7 +6,7 @@
 / {
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 0713d072758a..bfc1a32d4e42 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -16,7 +16,7 @@
        };
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-0 = <&pmx_ram_size &pmx_board_id>;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 911f3a8cee23..df7f15276575 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -9,6 +9,7 @@
        chosen {
                bootargs = "console=ttyS0,115200n8";
+                stdout-path = &uart0;
        };
        mbus {
@@ -25,8 +26,6 @@
                i2c@11000 {
                        status = "okay";
                        clock-frequency = <400000>;
-                        pinctrl-0 = <&pmx_twsi0>;
-                        pinctrl-names = "default";
                        s35390a: s35390a@30 {
                                compatible = "s35390a";
@@ -34,16 +33,10 @@
                        };
                };
                serial@12000 {
-                        clock-frequency = <200000000>;
                        status = "okay";
-                        pinctrl-0 = <&pmx_uart0>;
-                        pinctrl-names = "default";
                };
                serial@12100 {
-                        clock-frequency = <200000000>;
                        status = "okay";
-                        pinctrl-0 = <&pmx_uart1>;
-                        pinctrl-names = "default";
                };
                poweroff@12100 {
                        compatible = "qnap,power-off";
@@ -52,8 +45,6 @@
                };
                spi@10600 {
                        status = "okay";
-                        pinctrl-0 = <&pmx_spi>;
-                        pinctrl-names = "default";
                        m25p128@0 {
                                #address-cells = <1>;
diff --git a/arch/arm/boot/dts/kirkwood-ts419.dtsi b/arch/arm/boot/dts/kirkwood-ts419.dtsi
index 1a9c624c7a92..30ab93bfb1e4 100644
--- a/arch/arm/boot/dts/kirkwood-ts419.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts419.dtsi
@@ -14,7 +14,7 @@
        compatible = "qnap,ts419", "marvell,kirkwood";
        ocp@f1000000 {
-                pinctrl: pinctrl@10000 {
+                pinctrl: pin-controller@10000 {
                        pinctrl-names = "default";
                        pmx_USB_copy_button: pmx-USB-copy-button {
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 90384587c278..afc640cd80c5 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -40,7 +40,7 @@
                pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
                pcie-io-aperture  = <0xf2000000 0x100000>;   /*   1 MiB    I/O space */
-                crypto@0301 {
+                cesa: crypto@0301 {
                        compatible = "marvell,orion-crypto";
                        reg = <MBUS_ID(0xf0, 0x01) 0x30000 0x10000>,
                              <MBUS_ID(0x03, 0x01) 0 0x800>;
@@ -61,6 +61,8 @@
                        chip-delay = <25>;
                        /* set partition map and/or chip-delay in board dts */
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_nand>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
        };
@@ -71,13 +73,59 @@
                #address-cells = <1>;
                #size-cells = <1>;
+                pinctrl: pin-controller@10000 {
+                        /* set compatible property in SoC file */
+                        reg = <0x10000 0x20>;
+                        pmx_ge1: pmx-ge1 {
+                                marvell,pins = "mpp20", "mpp21", "mpp22", "mpp23",
+                                               "mpp24", "mpp25", "mpp26", "mpp27",
+                                               "mpp30", "mpp31", "mpp32", "mpp33";
+                                marvell,function = "ge1";
+                        };
+                        pmx_nand: pmx-nand {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
+                                               "mpp4", "mpp5", "mpp18", "mpp19";
+                                marvell,function = "nand";
+                        };
+                        /*
+                         * Default SPI0 pinctrl setting with CSn on mpp0,
+                         * overwrite marvell,pins on board level if required.
+                         */
+                        pmx_spi: pmx-spi {
+                                marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
+                                marvell,function = "spi";
+                        };
+                        pmx_twsi0: pmx-twsi0 {
+                                marvell,pins = "mpp8", "mpp9";
+                                marvell,function = "twsi0";
+                        };
+                        /*
+                         * Default UART pinctrl setting without RTS/CTS,
+                         * overwrite marvell,pins on board level if required.
+                         */
+                        pmx_uart0: pmx-uart0 {
+                                marvell,pins = "mpp10", "mpp11";
+                                marvell,function = "uart0";
+                        };
+                        pmx_uart1: pmx-uart1 {
+                                marvell,pins = "mpp13", "mpp14";
+                                marvell,function = "uart1";
+                        };
+                };
                core_clk: core-clocks@10030 {
                        compatible = "marvell,kirkwood-core-clock";
                        reg = <0x10030 0x4>;
                        #clock-cells = <1>;
                };
-                spi@10600 {
+                spi0: spi@10600 {
                        compatible = "marvell,orion-spi";
                        #address-cells = <1>;
                        #size-cells = <0>;
@@ -85,6 +133,8 @@
                        interrupts = <23>;
                        reg = <0x10600 0x28>;
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_spi>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
@@ -120,24 +170,30 @@
                        interrupts = <29>;
                        clock-frequency = <100000>;
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_twsi0>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
-                serial@12000 {
+                uart0: serial@12000 {
                        compatible = "ns16550a";
                        reg = <0x12000 0x100>;
                        reg-shift = <2>;
                        interrupts = <33>;
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_uart0>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
-                serial@12100 {
+                uart1: serial@12100 {
                        compatible = "ns16550a";
                        reg = <0x12100 0x100>;
                        reg-shift = <2>;
                        interrupts = <34>;
                        clocks = <&gate_clk 7>;
+                        pinctrl-0 = <&pmx_uart1>;
+                        pinctrl-names = "default";
                        status = "disabled";
                };
@@ -146,7 +202,7 @@
                        reg = <0x20000 0x80>, <0x1500 0x20>;
                };
-                system-controller@20000 {
+                sysc: system-controller@20000 {
                        compatible = "marvell,orion-system-controller";
                        reg = <0x20000 0x120>;
                };
@@ -196,7 +252,7 @@
                        status = "okay";
                };
-                ehci@50000 {
+                usb0: ehci@50000 {
                        compatible = "marvell,orion-ehci";
                        reg = <0x50000 0x1000>;
                        interrupts = <19>;
@@ -204,7 +260,7 @@
                        status = "okay";
                };
-                xor@60800 {
+                dma0: xor@60800 {
                        compatible = "marvell,orion-xor";
                        reg = <0x60800 0x100
                               0x60A00 0x100>;
@@ -224,7 +280,7 @@
                        };
                };
-                xor@60900 {
+                dma1: xor@60900 {
                        compatible = "marvell,orion-xor";
                        reg = <0x60900 0x100
                               0x60B00 0x100>;
@@ -282,6 +338,8 @@
                        reg = <0x76000 0x4000>;
                        clocks = <&gate_clk 19>;
                        marvell,tx-checksum-limit = <1600>;
+                        pinctrl-0 = <&pmx_ge1>;
+                        pinctrl-names = "default";
                        status = "disabled";
                        ethernet1-port@0 {
@@ -314,6 +372,7 @@
                audio0: audio-controller@a0000 {
                        compatible = "marvell,kirkwood-audio";
+                        #sound-dai-cells = <0>;
                        reg = <0xa0000 0x2210>;
                        interrupts = <24>;
                        clocks = <&gate_clk 9>;
diff --git a/arch/arm/boot/dts/marco.dtsi b/arch/arm/boot/dts/marco.dtsi
index 0c9647d28765..fb354225740a 100644
--- a/arch/arm/boot/dts/marco.dtsi
+++ b/arch/arm/boot/dts/marco.dtsi
@@ -36,7 +36,7 @@
                ranges = <0x40000000 0x40000000 0xa0000000>;
                l2-cache-controller@c0030000 {
-                        compatible = "sirf,marco-pl310-cache", "arm,pl310-cache";
+                        compatible = "arm,pl310-cache";
                        reg = <0xc0030000 0x1000>;
                        interrupts = <0 59 0>;
                        arm,tag-latency = <1 1 1>;
diff --git a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
index f577b7df9a29..521c587acaee 100644
--- a/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
+++ b/arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
@@ -24,11 +24,10 @@
                compatible = "smsc,lan9221", "smsc,lan9115";
                bank-width = <2>;
                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <0>;
+                gpmc,cs-on-ns = <1>;
-                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-rd-off-ns = <180>;
-                gpmc,cs-wr-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <180>;
-                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <18>;
-                gpmc,adv-rd-off-ns = <48>;
                gpmc,adv-wr-off-ns = <48>;
                gpmc,oe-on-ns = <54>;
                gpmc,oe-off-ns = <168>;
@@ -36,12 +35,10 @@
                gpmc,we-off-ns = <168>;
                gpmc,rd-cycle-ns = <186>;
                gpmc,wr-cycle-ns = <186>;
-                gpmc,access-ns = <114>;
+                gpmc,access-ns = <144>;
-                gpmc,page-burst-access-ns = <6>;
+                gpmc,page-burst-access-ns = <24>;
-                gpmc,bus-turnaround-ns = <12>;
+                gpmc,bus-turnaround-ns = <90>;
-                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,cycle2cycle-delay-ns = <90>;
-                gpmc,wr-data-mux-bus-ns = <90>;
-                gpmc,wr-access-ns = <186>;
                gpmc,cycle2cycle-samecsen;
                gpmc,cycle2cycle-diffcsen;
                vddvario-supply = <&vddvario>;
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 22f35ea142c1..8f8c07da4ac1 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -71,13 +71,6 @@
                        interrupts = <58>;
                };
-                mailbox: mailbox@48094000 {
-                        compatible = "ti,omap2-mailbox";
-                        ti,hwmods = "mailbox";
-                        reg = <0x48094000 0x200>;
-                        interrupts = <26>;
-                };
                intc: interrupt-controller@1 {
                        compatible = "ti,omap2-intc";
                        interrupt-controller;
diff --git a/arch/arm/boot/dts/omap2420-clocks.dtsi b/arch/arm/boot/dts/omap2420-clocks.dtsi
new file mode 100644
index 000000000000..ce8c742d7e92
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-clocks.dtsi
@@ -0,0 +1,270 @@
+/*
+ * Device Tree Source for OMAP2420 clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&prcm_clocks {
+        sys_clkout2_src_gate: sys_clkout2_src_gate {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <15>;
+                reg = <0x0070>;
+        };
+        sys_clkout2_src_mux: sys_clkout2_src_mux {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0070>;
+        };
+        sys_clkout2_src: sys_clkout2_src {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
+        };
+        sys_clkout2: sys_clkout2 {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkout2_src>;
+                ti,bit-shift = <11>;
+                ti,max-div = <64>;
+                reg = <0x0070>;
+                ti,index-power-of-two;
+        };
+        dsp_gate_ick: dsp_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&dsp_fck>;
+                ti,bit-shift = <1>;
+                reg = <0x0810>;
+        };
+        dsp_div_ick: dsp_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dsp_fck>;
+                ti,bit-shift = <5>;
+                ti,max-div = <3>;
+                reg = <0x0840>;
+                ti,index-starts-at-one;
+        };
+        dsp_ick: dsp_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
+        };
+        iva1_gate_ifck: iva1_gate_ifck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0800>;
+        };
+        iva1_div_ifck: iva1_div_ifck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0840>;
+                ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
+        };
+        iva1_ifck: iva1_ifck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
+        };
+        iva1_ifck_div: iva1_ifck_div {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&iva1_ifck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+        iva1_mpu_int_ifck: iva1_mpu_int_ifck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&iva1_ifck_div>;
+                ti,bit-shift = <8>;
+                reg = <0x0800>;
+        };
+        wdt3_ick: wdt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <28>;
+                reg = <0x0210>;
+        };
+        wdt3_fck: wdt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <28>;
+                reg = <0x0200>;
+        };
+        mmc_ick: mmc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <26>;
+                reg = <0x0210>;
+        };
+        mmc_fck: mmc_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <26>;
+                reg = <0x0200>;
+        };
+        eac_ick: eac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0210>;
+        };
+        eac_fck: eac_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <24>;
+                reg = <0x0200>;
+        };
+        i2c1_fck: i2c1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_12m_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0200>;
+        };
+        i2c2_fck: i2c2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_12m_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0200>;
+        };
+        vlynq_ick: vlynq_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0210>;
+        };
+        vlynq_gate_fck: vlynq_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0200>;
+        };
+        core_d18_ck: core_d18_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <18>;
+        };
+        vlynq_mux_fck: vlynq_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
+                ti,bit-shift = <15>;
+                reg = <0x0240>;
+        };
+        vlynq_fck: vlynq_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
+        };
+};
+&prcm_clockdomains {
+        gfx_clkdm: gfx_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gfx_ick>;
+        };
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
+        };
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
+                         <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
+                         <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
+        };
+        iva1_clkdm: iva1_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&iva1_mpu_int_ifck>;
+        };
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_ick>, <&dss_54m_fck>;
+        };
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
+                         <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
+                         <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
+                         <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
+                         <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
+                         <&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
+                         <&uart3_ick>, <&uart3_fck>, <&cam_ick>,
+                         <&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
+                         <&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
+                         <&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
+                         <&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
+                         <&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
+                         <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
+                         <&pka_ick>;
+        };
+};
+&func_96m_ck {
+        compatible = "fixed-factor-clock";
+        clocks = <&apll96_ck>;
+        clock-mult = <1>;
+        clock-div = <1>;
+};
+&dsp_div_fck {
+        ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
+};
+&ssi_ssr_sst_div_fck {
+        ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
+};
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 85b1fb014c43..e83b0468080c 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -14,6 +14,32 @@
        compatible = "ti,omap2420", "ti,omap2";
        ocp {
+                prcm: prcm@48008000 {
+                        compatible = "ti,omap2-prcm";
+                        reg = <0x48008000 0x1000>;
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+                scrm: scrm@48000000 {
+                        compatible = "ti,omap2-scrm";
+                        reg = <0x48000000 0x1000>;
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
                counter32k: counter@48004000 {
                        compatible = "ti,omap-counter32k";
                        reg = <0x48004000 0x20>;
@@ -125,6 +151,14 @@
                        dma-names = "tx", "rx";
                };
+                mailbox: mailbox@48094000 {
+                        compatible = "ti,omap2-mailbox";
+                        reg = <0x48094000 0x200>;
+                        interrupts = <26>, <34>;
+                        interrupt-names = "dsp", "iva";
+                        ti,hwmods = "mailbox";
+                };
                timer1: timer@48028000 {
                        compatible = "ti,omap2420-timer";
                        reg = <0x48028000 0x400>;
diff --git a/arch/arm/boot/dts/omap2430-clocks.dtsi b/arch/arm/boot/dts/omap2430-clocks.dtsi
new file mode 100644
index 000000000000..805f75df1cf2
--- /dev/null
+++ b/arch/arm/boot/dts/omap2430-clocks.dtsi
@@ -0,0 +1,344 @@
+/*
+ * Device Tree Source for OMAP2430 clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        mcbsp3_mux_fck: mcbsp3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&mcbsp_clks>;
+                reg = <0x02e8>;
+        };
+        mcbsp3_fck: mcbsp3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp3_gate_fck>, <&mcbsp3_mux_fck>;
+        };
+        mcbsp4_mux_fck: mcbsp4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x02e8>;
+        };
+        mcbsp4_fck: mcbsp4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp4_gate_fck>, <&mcbsp4_mux_fck>;
+        };
+        mcbsp5_mux_fck: mcbsp5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x02e8>;
+        };
+        mcbsp5_fck: mcbsp5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp5_gate_fck>, <&mcbsp5_mux_fck>;
+        };
+};
+&prcm_clocks {
+        iva2_1_gate_ick: iva2_1_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&dsp_fck>;
+                ti,bit-shift = <0>;
+                reg = <0x0800>;
+        };
+        iva2_1_div_ick: iva2_1_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&dsp_fck>;
+                ti,bit-shift = <5>;
+                ti,max-div = <3>;
+                reg = <0x0840>;
+                ti,index-starts-at-one;
+        };
+        iva2_1_ick: iva2_1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&iva2_1_gate_ick>, <&iva2_1_div_ick>;
+        };
+        mdm_gate_ick: mdm_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0c10>;
+        };
+        mdm_div_ick: mdm_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_ck>;
+                reg = <0x0c40>;
+                ti,dividers = <0>, <1>, <0>, <0>, <4>, <0>, <6>, <0>, <0>, <9>;
+        };
+        mdm_ick: mdm_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mdm_gate_ick>, <&mdm_div_ick>;
+        };
+        mdm_osc_ck: mdm_osc_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&osc_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0c00>;
+        };
+        mcbsp3_ick: mcbsp3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0214>;
+        };
+        mcbsp3_gate_fck: mcbsp3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <3>;
+                reg = <0x0204>;
+        };
+        mcbsp4_ick: mcbsp4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0214>;
+        };
+        mcbsp4_gate_fck: mcbsp4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <4>;
+                reg = <0x0204>;
+        };
+        mcbsp5_ick: mcbsp5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0214>;
+        };
+        mcbsp5_gate_fck: mcbsp5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <5>;
+                reg = <0x0204>;
+        };
+        mcspi3_ick: mcspi3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0214>;
+        };
+        mcspi3_fck: mcspi3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0204>;
+        };
+        icr_ick: icr_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0410>;
+        };
+        i2chs1_fck: i2chs1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,omap2430-interface-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0204>;
+        };
+        i2chs2_fck: i2chs2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,omap2430-interface-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0204>;
+        };
+        usbhs_ick: usbhs_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0214>;
+        };
+        mmchs1_ick: mmchs1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0214>;
+        };
+        mmchs1_fck: mmchs1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0204>;
+        };
+        mmchs2_ick: mmchs2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0214>;
+        };
+        mmchs2_fck: mmchs2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0204>;
+        };
+        gpio5_ick: gpio5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0214>;
+        };
+        gpio5_fck: gpio5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0204>;
+        };
+        mdm_intc_ick: mdm_intc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0214>;
+        };
+        mmchsdb1_fck: mmchsdb1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <16>;
+                reg = <0x0204>;
+        };
+        mmchsdb2_fck: mmchsdb2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <17>;
+                reg = <0x0204>;
+        };
+};
+&prcm_clockdomains {
+        gfx_clkdm: gfx_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&gfx_ick>;
+        };
+        core_l3_clkdm: core_l3_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&cam_fck>, <&usb_fck>, <&usbhs_ick>;
+        };
+        wkup_clkdm: wkup_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
+                         <&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
+                         <&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>,
+                         <&icr_ick>;
+        };
+        dss_clkdm: dss_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&dss_ick>, <&dss_54m_fck>;
+        };
+        core_l4_clkdm: core_l4_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
+                         <&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
+                         <&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
+                         <&mcbsp1_ick>, <&mcbsp2_ick>, <&mcbsp3_ick>,
+                         <&mcbsp4_ick>, <&mcbsp5_ick>, <&mcspi1_ick>,
+                         <&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
+                         <&mcspi3_ick>, <&mcspi3_fck>, <&uart1_ick>,
+                         <&uart1_fck>, <&uart2_ick>, <&uart2_fck>, <&uart3_ick>,
+                         <&uart3_fck>, <&cam_ick>, <&mailboxes_ick>,
+                         <&wdt4_ick>, <&wdt4_fck>, <&mspro_ick>, <&mspro_fck>,
+                         <&fac_ick>, <&fac_fck>, <&hdq_ick>, <&hdq_fck>,
+                         <&i2c1_ick>, <&i2chs1_fck>, <&i2c2_ick>, <&i2chs2_fck>,
+                         <&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
+                         <&pka_ick>, <&mmchs1_ick>, <&mmchs1_fck>,
+                         <&mmchs2_ick>, <&mmchs2_fck>, <&gpio5_ick>,
+                         <&gpio5_fck>, <&mdm_intc_ick>, <&mmchsdb1_fck>,
+                         <&mmchsdb2_fck>;
+        };
+        mdm_clkdm: mdm_clkdm {
+                compatible = "ti,clockdomain";
+                clocks = <&mdm_osc_ck>;
+        };
+};
+&func_96m_ck {
+        compatible = "ti,mux-clock";
+        clocks = <&apll96_ck>, <&alt_ck>;
+        ti,bit-shift = <4>;
+        reg = <0x0540>;
+};
+&dsp_div_fck {
+        ti,max-div = <4>;
+        ti,index-starts-at-one;
+};
+&ssi_ssr_sst_div_fck {
+        ti,max-div = <5>;
+        ti,index-starts-at-one;
+};
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index d09697dab55e..c4e8013801ee 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -14,6 +14,32 @@
        compatible = "ti,omap2430", "ti,omap2";
        ocp {
+                prcm: prcm@49006000 {
+                        compatible = "ti,omap2-prcm";
+                        reg = <0x49006000 0x1000>;
+                        prcm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                        prcm_clockdomains: clockdomains {
+                        };
+                };
+                scrm: scrm@49002000 {
+                        compatible = "ti,omap2-scrm";
+                        reg = <0x49002000 0x1000>;
+                        scrm_clocks: clocks {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                        };
+                        scrm_clockdomains: clockdomains {
+                        };
+                };
                counter32k: counter@49020000 {
                        compatible = "ti,omap-counter32k";
                        reg = <0x49020000 0x20>;
@@ -216,6 +242,13 @@
                        dma-names = "tx", "rx";
                };
+                mailbox: mailbox@48094000 {
+                        compatible = "ti,omap2-mailbox";
+                        reg = <0x48094000 0x200>;
+                        interrupts = <26>;
+                        ti,hwmods = "mailbox";
+                };
                timer1: timer@49018000 {
                        compatible = "ti,omap2420-timer";
                        reg = <0x49018000 0x400>;
diff --git a/arch/arm/boot/dts/omap24xx-clocks.dtsi b/arch/arm/boot/dts/omap24xx-clocks.dtsi
new file mode 100644
index 000000000000..a1365ca926eb
--- /dev/null
+++ b/arch/arm/boot/dts/omap24xx-clocks.dtsi
@@ -0,0 +1,1244 @@
+/*
+ * Device Tree Source for OMAP24xx clock data
+ *
+ * Copyright (C) 2014 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+&scrm_clocks {
+        mcbsp1_mux_fck: mcbsp1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&mcbsp_clks>;
+                ti,bit-shift = <2>;
+                reg = <0x0274>;
+        };
+        mcbsp1_fck: mcbsp1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
+        };
+        mcbsp2_mux_fck: mcbsp2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_96m_ck>, <&mcbsp_clks>;
+                ti,bit-shift = <6>;
+                reg = <0x0274>;
+        };
+        mcbsp2_fck: mcbsp2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
+        };
+};
+&prcm_clocks {
+        func_32k_ck: func_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+        secure_32k_ck: secure_32k_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <32768>;
+        };
+        virt_12m_ck: virt_12m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <12000000>;
+        };
+        virt_13m_ck: virt_13m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <13000000>;
+        };
+        virt_19200000_ck: virt_19200000_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <19200000>;
+        };
+        virt_26m_ck: virt_26m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <26000000>;
+        };
+        aplls_clkin_ck: aplls_clkin_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x0540>;
+        };
+        aplls_clkin_x2_ck: aplls_clkin_x2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&aplls_clkin_ck>;
+                clock-mult = <2>;
+                clock-div = <1>;
+        };
+        osc_ck: osc_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0060>;
+                ti,index-starts-at-one;
+        };
+        sys_ck: sys_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&osc_ck>;
+                ti,bit-shift = <6>;
+                ti,max-div = <3>;
+                reg = <0x0060>;
+                ti,index-starts-at-one;
+        };
+        alt_ck: alt_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <54000000>;
+        };
+        mcbsp_clks: mcbsp_clks {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0x0>;
+        };
+        dpll_ck: dpll_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap2-dpll-core-clock";
+                clocks = <&sys_ck>, <&sys_ck>;
+                reg = <0x0500>, <0x0540>;
+        };
+        apll96_ck: apll96_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap2-apll-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <2>;
+                ti,idlest-shift = <8>;
+                ti,clock-frequency = <96000000>;
+                reg = <0x0500>, <0x0530>, <0x0520>;
+        };
+        apll54_ck: apll54_ck {
+                #clock-cells = <0>;
+                compatible = "ti,omap2-apll-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <6>;
+                ti,idlest-shift = <9>;
+                ti,clock-frequency = <54000000>;
+                reg = <0x0500>, <0x0530>, <0x0520>;
+        };
+        func_54m_ck: func_54m_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&apll54_ck>, <&alt_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0540>;
+        };
+        core_ck: core_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&dpll_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+        func_96m_ck: func_96m_ck {
+                #clock-cells = <0>;
+        };
+        apll96_d2_ck: apll96_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&apll96_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+        func_48m_ck: func_48m_ck {
+                #clock-cells = <0>;
+                compatible = "ti,mux-clock";
+                clocks = <&apll96_d2_ck>, <&alt_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0540>;
+        };
+        func_12m_ck: func_12m_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&func_48m_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+        sys_clkout_src_gate: sys_clkout_src_gate {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0070>;
+        };
+        sys_clkout_src_mux: sys_clkout_src_mux {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
+                reg = <0x0070>;
+        };
+        sys_clkout_src: sys_clkout_src {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
+        };
+        sys_clkout: sys_clkout {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&sys_clkout_src>;
+                ti,bit-shift = <3>;
+                ti,max-div = <64>;
+                reg = <0x0070>;
+                ti,index-power-of-two;
+        };
+        emul_ck: emul_ck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_54m_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0078>;
+        };
+        mpu_ck: mpu_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,max-div = <31>;
+                reg = <0x0140>;
+                ti,index-starts-at-one;
+        };
+        dsp_gate_fck: dsp_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0800>;
+        };
+        dsp_div_fck: dsp_div_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_ck>;
+                reg = <0x0840>;
+        };
+        dsp_fck: dsp_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
+        };
+        core_l3_ck: core_l3_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_ck>;
+                ti,max-div = <31>;
+                reg = <0x0240>;
+                ti,index-starts-at-one;
+        };
+        gfx_3d_gate_fck: gfx_3d_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0300>;
+        };
+        gfx_3d_div_fck: gfx_3d_div_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_l3_ck>;
+                ti,max-div = <4>;
+                reg = <0x0340>;
+                ti,index-starts-at-one;
+        };
+        gfx_3d_fck: gfx_3d_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
+        };
+        gfx_2d_gate_fck: gfx_2d_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0300>;
+        };
+        gfx_2d_div_fck: gfx_2d_div_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_l3_ck>;
+                ti,max-div = <4>;
+                reg = <0x0340>;
+                ti,index-starts-at-one;
+        };
+        gfx_2d_fck: gfx_2d_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
+        };
+        gfx_ick: gfx_ick {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0310>;
+        };
+        l4_ck: l4_ck {
+                #clock-cells = <0>;
+                compatible = "ti,divider-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <5>;
+                ti,max-div = <3>;
+                reg = <0x0240>;
+                ti,index-starts-at-one;
+        };
+        dss_ick: dss_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0210>;
+        };
+        dss1_gate_fck: dss1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0200>;
+        };
+        core_d2_ck: core_d2_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <2>;
+        };
+        core_d3_ck: core_d3_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <3>;
+        };
+        core_d4_ck: core_d4_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <4>;
+        };
+        core_d5_ck: core_d5_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <5>;
+        };
+        core_d6_ck: core_d6_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <6>;
+        };
+        dummy_ck: dummy_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-clock";
+                clock-frequency = <0>;
+        };
+        core_d8_ck: core_d8_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <8>;
+        };
+        core_d9_ck: core_d9_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <9>;
+        };
+        core_d12_ck: core_d12_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <12>;
+        };
+        core_d16_ck: core_d16_ck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_ck>;
+                clock-mult = <1>;
+                clock-div = <16>;
+        };
+        dss1_mux_fck: dss1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0240>;
+        };
+        dss1_fck: dss1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
+        };
+        dss2_gate_fck: dss2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-no-wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0200>;
+        };
+        dss2_mux_fck: dss2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&sys_ck>, <&func_48m_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x0240>;
+        };
+        dss2_fck: dss2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
+        };
+        dss_54m_fck: dss_54m_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_54m_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0200>;
+        };
+        ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0204>;
+        };
+        ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0240>;
+        };
+        ssi_ssr_sst_fck: ssi_ssr_sst_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
+        };
+        usb_l4_gate_ick: usb_l4_gate_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-interface-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0214>;
+        };
+        usb_l4_div_ick: usb_l4_div_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-divider-clock";
+                clocks = <&core_l3_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x0240>;
+                ti,dividers = <0>, <1>, <2>, <0>, <4>;
+        };
+        usb_l4_ick: usb_l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
+        };
+        ssi_l4_ick: ssi_l4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0214>;
+        };
+        gpt1_ick: gpt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0410>;
+        };
+        gpt1_gate_fck: gpt1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0400>;
+        };
+        gpt1_mux_fck: gpt1_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                reg = <0x0440>;
+        };
+        gpt1_fck: gpt1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
+        };
+        gpt2_ick: gpt2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0210>;
+        };
+        gpt2_gate_fck: gpt2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0200>;
+        };
+        gpt2_mux_fck: gpt2_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0244>;
+        };
+        gpt2_fck: gpt2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
+        };
+        gpt3_ick: gpt3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0210>;
+        };
+        gpt3_gate_fck: gpt3_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0200>;
+        };
+        gpt3_mux_fck: gpt3_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0244>;
+        };
+        gpt3_fck: gpt3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
+        };
+        gpt4_ick: gpt4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0210>;
+        };
+        gpt4_gate_fck: gpt4_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0200>;
+        };
+        gpt4_mux_fck: gpt4_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <6>;
+                reg = <0x0244>;
+        };
+        gpt4_fck: gpt4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
+        };
+        gpt5_ick: gpt5_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0210>;
+        };
+        gpt5_gate_fck: gpt5_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <7>;
+                reg = <0x0200>;
+        };
+        gpt5_mux_fck: gpt5_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0244>;
+        };
+        gpt5_fck: gpt5_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
+        };
+        gpt6_ick: gpt6_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0210>;
+        };
+        gpt6_gate_fck: gpt6_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <8>;
+                reg = <0x0200>;
+        };
+        gpt6_mux_fck: gpt6_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0244>;
+        };
+        gpt6_fck: gpt6_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
+        };
+        gpt7_ick: gpt7_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0210>;
+        };
+        gpt7_gate_fck: gpt7_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <9>;
+                reg = <0x0200>;
+        };
+        gpt7_mux_fck: gpt7_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0244>;
+        };
+        gpt7_fck: gpt7_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
+        };
+        gpt8_ick: gpt8_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0210>;
+        };
+        gpt8_gate_fck: gpt8_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <10>;
+                reg = <0x0200>;
+        };
+        gpt8_mux_fck: gpt8_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x0244>;
+        };
+        gpt8_fck: gpt8_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
+        };
+        gpt9_ick: gpt9_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0210>;
+        };
+        gpt9_gate_fck: gpt9_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <11>;
+                reg = <0x0200>;
+        };
+        gpt9_mux_fck: gpt9_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <16>;
+                reg = <0x0244>;
+        };
+        gpt9_fck: gpt9_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
+        };
+        gpt10_ick: gpt10_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0210>;
+        };
+        gpt10_gate_fck: gpt10_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <12>;
+                reg = <0x0200>;
+        };
+        gpt10_mux_fck: gpt10_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0244>;
+        };
+        gpt10_fck: gpt10_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
+        };
+        gpt11_ick: gpt11_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x0210>;
+        };
+        gpt11_gate_fck: gpt11_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <13>;
+                reg = <0x0200>;
+        };
+        gpt11_mux_fck: gpt11_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0244>;
+        };
+        gpt11_fck: gpt11_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
+        };
+        gpt12_ick: gpt12_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x0210>;
+        };
+        gpt12_gate_fck: gpt12_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <14>;
+                reg = <0x0200>;
+        };
+        gpt12_mux_fck: gpt12_mux_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-mux-clock";
+                clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0244>;
+        };
+        gpt12_fck: gpt12_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-clock";
+                clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
+        };
+        mcbsp1_ick: mcbsp1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <15>;
+                reg = <0x0210>;
+        };
+        mcbsp1_gate_fck: mcbsp1_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <15>;
+                reg = <0x0200>;
+        };
+        mcbsp2_ick: mcbsp2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <16>;
+                reg = <0x0210>;
+        };
+        mcbsp2_gate_fck: mcbsp2_gate_fck {
+                #clock-cells = <0>;
+                compatible = "ti,composite-gate-clock";
+                clocks = <&mcbsp_clks>;
+                ti,bit-shift = <16>;
+                reg = <0x0200>;
+        };
+        mcspi1_ick: mcspi1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <17>;
+                reg = <0x0210>;
+        };
+        mcspi1_fck: mcspi1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <17>;
+                reg = <0x0200>;
+        };
+        mcspi2_ick: mcspi2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0210>;
+        };
+        mcspi2_fck: mcspi2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <18>;
+                reg = <0x0200>;
+        };
+        uart1_ick: uart1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <21>;
+                reg = <0x0210>;
+        };
+        uart1_fck: uart1_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <21>;
+                reg = <0x0200>;
+        };
+        uart2_ick: uart2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0210>;
+        };
+        uart2_fck: uart2_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <22>;
+                reg = <0x0200>;
+        };
+        uart3_ick: uart3_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0214>;
+        };
+        uart3_fck: uart3_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0204>;
+        };
+        gpios_ick: gpios_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0410>;
+        };
+        gpios_fck: gpios_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x0400>;
+        };
+        mpu_wdt_ick: mpu_wdt_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0410>;
+        };
+        mpu_wdt_fck: mpu_wdt_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x0400>;
+        };
+        sync_32k_ick: sync_32k_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x0410>;
+        };
+        wdt1_ick: wdt1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x0410>;
+        };
+        omapctrl_ick: omapctrl_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&sys_ck>;
+                ti,bit-shift = <5>;
+                reg = <0x0410>;
+        };
+        cam_fck: cam_fck {
+                #clock-cells = <0>;
+                compatible = "ti,gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <31>;
+                reg = <0x0200>;
+        };
+        cam_ick: cam_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-no-wait-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <31>;
+                reg = <0x0210>;
+        };
+        mailboxes_ick: mailboxes_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <30>;
+                reg = <0x0210>;
+        };
+        wdt4_ick: wdt4_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <29>;
+                reg = <0x0210>;
+        };
+        wdt4_fck: wdt4_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_32k_ck>;
+                ti,bit-shift = <29>;
+                reg = <0x0200>;
+        };
+        mspro_ick: mspro_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <27>;
+                reg = <0x0210>;
+        };
+        mspro_fck: mspro_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_96m_ck>;
+                ti,bit-shift = <27>;
+                reg = <0x0200>;
+        };
+        fac_ick: fac_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x0210>;
+        };
+        fac_fck: fac_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_12m_ck>;
+                ti,bit-shift = <25>;
+                reg = <0x0200>;
+        };
+        hdq_ick: hdq_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x0210>;
+        };
+        hdq_fck: hdq_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_12m_ck>;
+                ti,bit-shift = <23>;
+                reg = <0x0200>;
+        };
+        i2c1_ick: i2c1_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <19>;
+                reg = <0x0210>;
+        };
+        i2c2_ick: i2c2_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <20>;
+                reg = <0x0210>;
+        };
+        gpmc_fck: gpmc_fck {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&core_l3_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <1>;
+                reg = <0x0238>;
+                ti,clock-mult = <1>;
+        };
+        sdma_fck: sdma_fck {
+                #clock-cells = <0>;
+                compatible = "fixed-factor-clock";
+                clocks = <&core_l3_ck>;
+                clock-mult = <1>;
+                clock-div = <1>;
+        };
+        sdma_ick: sdma_ick {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&core_l3_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <0>;
+                reg = <0x0238>;
+                ti,clock-mult = <1>;
+        };
+        sdrc_ick: sdrc_ick {
+                #clock-cells = <0>;
+                compatible = "ti,fixed-factor-clock";
+                clocks = <&core_l3_ck>;
+                ti,clock-div = <1>;
+                ti,autoidle-shift = <2>;
+                reg = <0x0238>;
+                ti,clock-mult = <1>;
+        };
+        des_ick: des_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x021c>;
+        };
+        sha_ick: sha_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <1>;
+                reg = <0x021c>;
+        };
+        rng_ick: rng_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <2>;
+                reg = <0x021c>;
+        };
+        aes_ick: aes_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <3>;
+                reg = <0x021c>;
+        };
+        pka_ick: pka_ick {
+                #clock-cells = <0>;
+                compatible = "ti,omap3-interface-clock";
+                clocks = <&l4_ck>;
+                ti,bit-shift = <4>;
+                reg = <0x021c>;
+        };
+        usb_fck: usb_fck {
+                #clock-cells = <0>;
+                compatible = "ti,wait-gate-clock";
+                clocks = <&func_48m_ck>;
+                ti,bit-shift = <0>;
+                reg = <0x0204>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
index d00055809e31..25ba08331d88 100644
--- a/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
+++ b/arch/arm/boot/dts/omap3-cm-t3x30.dtsi
@@ -10,18 +10,6 @@
                        cpu0-supply = <&vcc>;
                };
        };
-        vddvario: regulator-vddvario {
-                compatible = "regulator-fixed";
-                regulator-name = "vddvario";
-                regulator-always-on;
-        };
-        vdd33a: regulator-vdd33a {
-                compatible = "regulator-fixed";
-                regulator-name = "vdd33a";
-                regulator-always-on;
-        };
 };
 &omap3_pmx_core {
@@ -35,58 +23,34 @@
        hsusb0_pins: pinmux_hsusb0_pins {
                pinctrl-single,pins = <
-                        OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_clk.hsusb0_clk */
+                        OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_clk.hsusb0_clk */
-                        OMAP3_CORE1_IOPAD(0x21a2, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_stp.hsusb0_stp */
+                        OMAP3_CORE1_IOPAD(0x21a4, PIN_OUTPUT | MUX_MODE0)               /* hsusb0_stp.hsusb0_stp */
-                        OMAP3_CORE1_IOPAD(0x21a4, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_dir.hsusb0_dir */
+                        OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_dir.hsusb0_dir */
-                        OMAP3_CORE1_IOPAD(0x21a6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_nxt.hsusb0_nxt */
+                        OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_nxt.hsusb0_nxt */
-                        OMAP3_CORE1_IOPAD(0x21a8, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data0.hsusb2_data0 */
+                        OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data0.hsusb2_data0 */
-                        OMAP3_CORE1_IOPAD(0x21aa, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data1.hsusb0_data1 */
+                        OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data1.hsusb0_data1 */
-                        OMAP3_CORE1_IOPAD(0x21ac, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data2.hsusb0_data2 */
+                        OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data2.hsusb0_data2 */
-                        OMAP3_CORE1_IOPAD(0x21ae, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data3 */
+                        OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data3 */
-                        OMAP3_CORE1_IOPAD(0x21b0, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data4 */
+                        OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data4 */
-                        OMAP3_CORE1_IOPAD(0x21b2, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data5 */
+                        OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data5 */
-                        OMAP3_CORE1_IOPAD(0x21b4, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data6 */
+                        OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data6 */
-                        OMAP3_CORE1_IOPAD(0x21b6, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data7 */
+                        OMAP3_CORE1_IOPAD(0x21b8, PIN_INPUT_PULLDOWN | MUX_MODE0)       /* hsusb0_data7.hsusb0_data7 */
                >;
        };
 };
+#include "omap-gpmc-smsc911x.dtsi"
 &gpmc {
        ranges = <5 0 0x2c000000 0x01000000>;
-        smsc1: ethernet@5,0 {
+        smsc1: ethernet@gpmc {
                compatible = "smsc,lan9221", "smsc,lan9115";
                pinctrl-names = "default";
                pinctrl-0 = <&smsc1_pins>;
                interrupt-parent = <&gpio6>;
                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
                reg = <5 0 0xff>;
-                bank-width = <2>;
-                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <0>;
-                gpmc,cs-rd-off-ns = <186>;
-                gpmc,cs-wr-off-ns = <186>;
-                gpmc,adv-on-ns = <12>;
-                gpmc,adv-rd-off-ns = <48>;
-                gpmc,adv-wr-off-ns = <48>;
-                gpmc,oe-on-ns = <54>;
-                gpmc,oe-off-ns = <168>;
-                gpmc,we-on-ns = <54>;
-                gpmc,we-off-ns = <168>;
-                gpmc,rd-cycle-ns = <186>;
-                gpmc,wr-cycle-ns = <186>;
-                gpmc,access-ns = <114>;
-                gpmc,page-burst-access-ns = <6>;
-                gpmc,bus-turnaround-ns = <12>;
-                gpmc,cycle2cycle-delay-ns = <18>;
-                gpmc,wr-data-mux-bus-ns = <90>;
-                gpmc,wr-access-ns = <186>;
-                gpmc,cycle2cycle-samecsen;
-                gpmc,cycle2cycle-diffcsen;
-                vddvario-supply = <&vddvario>;
-                vdd33a-supply = <&vdd33a>;
-                reg-io-width = <4>;
-                smsc,save-mac-address;
        };
 };
diff --git a/arch/arm/boot/dts/omap3-evm-37xx.dts b/arch/arm/boot/dts/omap3-evm-37xx.dts
index 4df68ad3736a..9cba94bed7ad 100644
--- a/arch/arm/boot/dts/omap3-evm-37xx.dts
+++ b/arch/arm/boot/dts/omap3-evm-37xx.dts
@@ -89,7 +89,16 @@
        status = "disabled";
 };
+&uart1 {
+        interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>;
+};
+&uart2 {
+        interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
+};
 &uart3 {
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
 };
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index b97736d98a64..e2d163bf0619 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -107,7 +107,7 @@
                >;
        };
-        smsc911x_pins: pinmux_smsc911x_pins {
+        smsc9221_pins: pinmux_smsc9221_pins {
                pinctrl-single,pins = <
                        0x1a2 (PIN_INPUT | MUX_MODE4)           /* mcspi1_cs2.gpio_176 */
                >;
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index 7abd64f6ae21..b22caaaf774b 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -10,7 +10,7 @@
 */
 #include "omap3-igep.dtsi"
-#include "omap-gpmc-smsc911x.dtsi"
+#include "omap-gpmc-smsc9221.dtsi"
 / {
        model = "IGEPv2 (TI OMAP AM/DM37x)";
@@ -248,7 +248,7 @@
        ethernet@gpmc {
                pinctrl-names = "default";
-                pinctrl-0 = <&smsc911x_pins>;
+                pinctrl-0 = <&smsc9221_pins>;
                reg = <5 0 0xff>;
                interrupt-parent = <&gpio6>;
                interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm/boot/dts/omap3-ldp.dts b/arch/arm/boot/dts/omap3-ldp.dts
index 0abe986a4ecc..476ff158ddb3 100644
--- a/arch/arm/boot/dts/omap3-ldp.dts
+++ b/arch/arm/boot/dts/omap3-ldp.dts
@@ -234,6 +234,10 @@
        };
 };
+&uart3 {
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
+};
 &usb_otg_hs {
        pinctrl-names = "default";
        pinctrl-0 = <&musb_pins>;
diff --git a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
index cc1dce6978f5..d97308896f0c 100644
--- a/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
+++ b/arch/arm/boot/dts/omap3-lilly-a83x.dtsi
@@ -176,9 +176,6 @@
 &omap3_pmx_core2 {
        pinctrl-names = "default";
-        pinctrl-0 = <
-                        &hsusb1_2_pins
-        >;
        hsusb1_2_pins: pinmux_hsusb1_2_pins {
                pinctrl-single,pins = <
@@ -357,6 +354,10 @@
        power = <50>;
 };
+&mcbsp2 {
+        status = "okay";
+};
 &gpmc {
        ranges = <0 0 0x30000000 0x1000000>,
                <7 0 0x15000000 0x01000000>;
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 1a57b61f5e24..059a8ff1e6ac 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -10,6 +10,7 @@
 /dts-v1/;
 #include "omap34xx-hs.dtsi"
+#include <dt-bindings/input/input.h>
 / {
        model = "Nokia N900";
@@ -21,6 +22,17 @@
                };
        };
+        leds {
+                compatible = "gpio-leds";
+                heartbeat {
+                        label = "debug::sleep";
+                        gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;  /* gpio162 */
+                        linux,default-trigger = "default-on";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&debug_leds>;
+                };
+        };
        memory {
                device_type = "memory";
                reg = <0x80000000 0x10000000>; /* 256 MB */
@@ -90,6 +102,19 @@
                        };
                };
        };
+        sound: n900-audio {
+                compatible = "nokia,n900-audio";
+                nokia,cpu-dai = <&mcbsp2>;
+                nokia,audio-codec = <&tlv320aic3x>, <&tlv320aic3x_aux>;
+                nokia,headphone-amplifier = <&tpa6130a2>;
+                tvout-selection-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; /* 40 */
+                jack-detection-gpios = <&gpio6 17 GPIO_ACTIVE_HIGH>; /* 177 */
+                eci-switch-gpios = <&gpio6 22 GPIO_ACTIVE_HIGH>; /* 182 */
+                speaker-amplifier-gpios = <&twl_gpio 7 GPIO_ACTIVE_HIGH>;
+        };
 };
 &omap3_pmx_core {
@@ -130,6 +155,21 @@
                >;
        };
+        debug_leds: pinmux_debug_led_pins {
+                pinctrl-single,pins = <
+                        OMAP3_CORE1_IOPAD(0x2198, PIN_OUTPUT | MUX_MODE4)       /* mcbsp1_clkx.gpio_162 */
+                >;
+        };
+        mcspi4_pins: pinmux_mcspi4_pins {
+                pinctrl-single,pins = <
+                        0x15c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_clk */
+                        0x162 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mcspi4_somi */
+                        0x160 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_simo */
+                        0x166 (PIN_OUTPUT | MUX_MODE1) /* mcspi4_cs0 */
+                >;
+        };
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
                        0x114 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc1_clk */
@@ -173,6 +213,37 @@
                        0x0da (PIN_OUTPUT | MUX_MODE1)   /* dss_data23.sdi_clkn */
                >;
        };
+        wl1251_pins: pinmux_wl1251 {
+                pinctrl-single,pins = <
+                        0x0ce (PIN_OUTPUT | MUX_MODE4)          /* gpio 87 => wl1251 enable */
+                        0x05a (PIN_INPUT | MUX_MODE4)           /* gpio 42 => wl1251 irq */
+                >;
+        };
+        ssi_pins: pinmux_ssi {
+                pinctrl-single,pins = <
+                        0x150 (PIN_INPUT_PULLUP | MUX_MODE1)    /* ssi1_rdy_tx */
+                        0x14e (PIN_OUTPUT | MUX_MODE1)          /* ssi1_flag_tx */
+                        0x152 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* ssi1_wake_tx (cawake) */
+                        0x14c (PIN_OUTPUT | MUX_MODE1)          /* ssi1_dat_tx */
+                        0x154 (PIN_INPUT | MUX_MODE1)           /* ssi1_dat_rx */
+                        0x156 (PIN_INPUT | MUX_MODE1)           /* ssi1_flag_rx */
+                        0x158 (PIN_OUTPUT | MUX_MODE1)          /* ssi1_rdy_rx */
+                        0x15a (PIN_OUTPUT | MUX_MODE1)          /* ssi1_wake */
+                >;
+        };
+        modem_pins: pinmux_modem {
+                pinctrl-single,pins = <
+                        0x0ac (PIN_OUTPUT | MUX_MODE4)          /* gpio 70 => cmt_apeslpx */
+                        0x0b0 (PIN_INPUT | WAKEUP_EN | MUX_MODE4) /* gpio 72 => ape_rst_rq */
+                        0x0b2 (PIN_OUTPUT | MUX_MODE4)          /* gpio 73 => cmt_rst_rq */
+                        0x0b4 (PIN_OUTPUT | MUX_MODE4)          /* gpio 74 => cmt_en */
+                        0x0b6 (PIN_OUTPUT | MUX_MODE4)          /* gpio 75 => cmt_rst */
+                        0x15e (PIN_OUTPUT | MUX_MODE4)          /* gpio 157 => cmt_bsi */
+                >;
+        };
 };
 &i2c1 {
@@ -283,57 +354,57 @@
 };
 &twl_keypad {
-        linux,keymap = < 0x00000010 /* KEY_Q */
+        linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_Q)
-                         0x00010018 /* KEY_O */
+                         MATRIX_KEY(0x00, 0x01, KEY_O)
-                         0x00020019 /* KEY_P */
+                         MATRIX_KEY(0x00, 0x02, KEY_P)
-                         0x00030033 /* KEY_COMMA */
+                         MATRIX_KEY(0x00, 0x03, KEY_COMMA)
-                         0x0004000e /* KEY_BACKSPACE */
+                         MATRIX_KEY(0x00, 0x04, KEY_BACKSPACE)
-                         0x0006001e /* KEY_A */
+                         MATRIX_KEY(0x00, 0x06, KEY_A)
-                         0x0007001f /* KEY_S */
+                         MATRIX_KEY(0x00, 0x07, KEY_S)
-                         0x01000011 /* KEY_W */
+                         MATRIX_KEY(0x01, 0x00, KEY_W)
-                         0x01010020 /* KEY_D */
+                         MATRIX_KEY(0x01, 0x01, KEY_D)
-                         0x01020021 /* KEY_F */
+                         MATRIX_KEY(0x01, 0x02, KEY_F)
-                         0x01030022 /* KEY_G */
+                         MATRIX_KEY(0x01, 0x03, KEY_G)
-                         0x01040023 /* KEY_H */
+                         MATRIX_KEY(0x01, 0x04, KEY_H)
-                         0x01050024 /* KEY_J */
+                         MATRIX_KEY(0x01, 0x05, KEY_J)
-                         0x01060025 /* KEY_K */
+                         MATRIX_KEY(0x01, 0x06, KEY_K)
-                         0x01070026 /* KEY_L */
+                         MATRIX_KEY(0x01, 0x07, KEY_L)
-                         0x02000012 /* KEY_E */
+                         MATRIX_KEY(0x02, 0x00, KEY_E)
-                         0x02010034 /* KEY_DOT */
+                         MATRIX_KEY(0x02, 0x01, KEY_DOT)
-                         0x02020067 /* KEY_UP */
+                         MATRIX_KEY(0x02, 0x02, KEY_UP)
-                         0x0203001c /* KEY_ENTER */
+                         MATRIX_KEY(0x02, 0x03, KEY_ENTER)
-                         0x0205002c /* KEY_Z */
+                         MATRIX_KEY(0x02, 0x05, KEY_Z)
-                         0x0206002d /* KEY_X */
+                         MATRIX_KEY(0x02, 0x06, KEY_X)
-                         0x0207002e /* KEY_C */
+                         MATRIX_KEY(0x02, 0x07, KEY_C)
-                         0x02080043 /* KEY_F9 */
+                         MATRIX_KEY(0x02, 0x08, KEY_F9)
-                         0x03000013 /* KEY_R */
+                         MATRIX_KEY(0x03, 0x00, KEY_R)
-                         0x0301002f /* KEY_V */
+                         MATRIX_KEY(0x03, 0x01, KEY_V)
-                         0x03020030 /* KEY_B */
+                         MATRIX_KEY(0x03, 0x02, KEY_B)
-                         0x03030031 /* KEY_N */
+                         MATRIX_KEY(0x03, 0x03, KEY_N)
-                         0x03040032 /* KEY_M */
+                         MATRIX_KEY(0x03, 0x04, KEY_M)
-                         0x03050039 /* KEY_SPACE */
+                         MATRIX_KEY(0x03, 0x05, KEY_SPACE)
-                         0x03060039 /* KEY_SPACE */
+                         MATRIX_KEY(0x03, 0x06, KEY_SPACE)
-                         0x03070069 /* KEY_LEFT */
+                         MATRIX_KEY(0x03, 0x07, KEY_LEFT)
-                         0x04000014 /* KEY_T */
+                         MATRIX_KEY(0x04, 0x00, KEY_T)
-                         0x0401006c /* KEY_DOWN */
+                         MATRIX_KEY(0x04, 0x01, KEY_DOWN)
-                         0x0402006a /* KEY_RIGHT */
+                         MATRIX_KEY(0x04, 0x02, KEY_RIGHT)
-                         0x0404001d /* KEY_LEFTCTRL */
+                         MATRIX_KEY(0x04, 0x04, KEY_LEFTCTRL)
-                         0x04050064 /* KEY_RIGHTALT */
+                         MATRIX_KEY(0x04, 0x05, KEY_RIGHTALT)
-                         0x0406002a /* KEY_LEFTSHIFT */
+                         MATRIX_KEY(0x04, 0x06, KEY_LEFTSHIFT)
-                         0x04080044 /* KEY_F10 */
+                         MATRIX_KEY(0x04, 0x08, KEY_F10)
-                         0x05000015 /* KEY_Y */
+                         MATRIX_KEY(0x05, 0x00, KEY_Y)
-                         0x05080057 /* KEY_F11 */
+                         MATRIX_KEY(0x05, 0x08, KEY_F11)
-                         0x06000016 /* KEY_U */
+                         MATRIX_KEY(0x06, 0x00, KEY_U)
-                         0x07000017 /* KEY_I */
+                         MATRIX_KEY(0x07, 0x00, KEY_I)
-                         0x07010041 /* KEY_F7 */
+                         MATRIX_KEY(0x07, 0x01, KEY_F7)
-                         0x07020042 /* KEY_F8 */
+                         MATRIX_KEY(0x07, 0x02, KEY_F8)
                         >;
 };
@@ -604,6 +675,30 @@
        };
 };
+&mcspi4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi4_pins>;
+        wl1251@0 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&wl1251_pins>;
+                vio-supply = <&vio>;
+                compatible = "ti,wl1251";
+                reg = <0>;
+                spi-max-frequency = <48000000>;
+                spi-cpol;
+                spi-cpha;
+                ti,power-gpio = <&gpio3 23 GPIO_ACTIVE_HIGH>; /* 87 */
+                interrupt-parent = <&gpio2>;
+                interrupts = <10 IRQ_TYPE_NONE>; /* gpio line 42 */
+        };
+};
 &usb_otg_hs {
        interface-type = <0>;
        usb-phy = <&usb2_phy>;
@@ -618,11 +713,13 @@
 };
 &uart2 {
+        interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart2_pins>;
 };
 &uart3 {
+        interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
 };
@@ -662,3 +759,48 @@
                };
        };
 };
+&mcbsp2 {
+        status = "ok";
+};
+&ssi_port1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&ssi_pins>;
+        ti,ssi-cawake-gpio = <&gpio5 23 GPIO_ACTIVE_HIGH>; /* 151 */
+        modem: hsi-client {
+                compatible = "nokia,n900-modem";
+                pinctrl-names = "default";
+                pinctrl-0 = <&modem_pins>;
+                hsi-channel-ids = <0>, <1>, <2>, <3>;
+                hsi-channel-names = "mcsaab-control",
+                                    "speech-control",
+                                    "speech-data",
+                                    "mcsaab-data";
+                hsi-speed-kbps = <55000>;
+                hsi-mode = "frame";
+                hsi-flow = "synchronized";
+                hsi-arb-mode = "round-robin";
+                interrupts-extended = <&gpio3 8 IRQ_TYPE_EDGE_FALLING>; /* 72 */
+                gpios = <&gpio3  6 GPIO_ACTIVE_HIGH>, /* 70 */
+                        <&gpio3  9 GPIO_ACTIVE_HIGH>, /* 73 */
+                        <&gpio3 10 GPIO_ACTIVE_HIGH>, /* 74 */
+                        <&gpio3 11 GPIO_ACTIVE_HIGH>, /* 75 */
+                        <&gpio5 29 GPIO_ACTIVE_HIGH>; /* 157 */
+                gpio-names = "cmt_apeslpx",
+                             "cmt_rst_rq",
+                             "cmt_en",
+                             "cmt_rst",
+                             "cmt_bsi";
+        };
+};
+&ssi_port2 {
+        status = "disabled";
+};
diff --git a/arch/arm/boot/dts/omap3-n950-n9.dtsi b/arch/arm/boot/dts/omap3-n950-n9.dtsi
index 5c26c184f2c1..70addcba37c5 100644
--- a/arch/arm/boot/dts/omap3-n950-n9.dtsi
+++ b/arch/arm/boot/dts/omap3-n950-n9.dtsi
@@ -67,6 +67,20 @@
        ti,pulldowns    = <0x008106>; /* BIT(1) | BIT(2) | BIT(8) | BIT(15) */
 };
+/* CSI-2 receiver */
+&vaux2 {
+        regulator-name = "vaux2";
+        regulator-min-microvolt = <1800000>;
+        regulator-max-microvolt = <1800000>;
+};
+/* Cameras */
+&vaux3 {
+        regulator-name = "vaux3";
+        regulator-min-microvolt = <2800000>;
+        regulator-max-microvolt = <2800000>;
+};
 &i2c2 {
        clock-frequency = <400000>;
 };
diff --git a/arch/arm/boot/dts/omap3-sb-t35.dtsi b/arch/arm/boot/dts/omap3-sb-t35.dtsi
index 7909c51b05a5..d59e3de1441e 100644
--- a/arch/arm/boot/dts/omap3-sb-t35.dtsi
+++ b/arch/arm/boot/dts/omap3-sb-t35.dtsi
@@ -2,20 +2,6 @@
 * Common support for CompuLab SB-T35 used on SBC-T3530, SBC-T3517 and SBC-T3730
 */
-/ {
-        vddvario_sb_t35: regulator-vddvario-sb-t35 {
-                compatible = "regulator-fixed";
-                regulator-name = "vddvario";
-                regulator-always-on;
-        };
-        vdd33a_sb_t35: regulator-vdd33a-sb-t35 {
-                compatible = "regulator-fixed";
-                regulator-name = "vdd33a";
-                regulator-always-on;
-        };
-};
 &omap3_pmx_core {
        smsc2_pins: pinmux_smsc2_pins {
                pinctrl-single,pins = <
@@ -37,11 +23,10 @@
                reg = <4 0 0xff>;
                bank-width = <2>;
                gpmc,mux-add-data;
-                gpmc,cs-on-ns = <0>;
+                gpmc,cs-on-ns = <1>;
-                gpmc,cs-rd-off-ns = <186>;
+                gpmc,cs-rd-off-ns = <180>;
-                gpmc,cs-wr-off-ns = <186>;
+                gpmc,cs-wr-off-ns = <180>;
-                gpmc,adv-on-ns = <12>;
+                gpmc,adv-rd-off-ns = <18>;
-                gpmc,adv-rd-off-ns = <48>;
                gpmc,adv-wr-off-ns = <48>;
                gpmc,oe-on-ns = <54>;
                gpmc,oe-off-ns = <168>;
@@ -49,16 +34,14 @@
                gpmc,we-off-ns = <168>;
                gpmc,rd-cycle-ns = <186>;
                gpmc,wr-cycle-ns = <186>;
-                gpmc,access-ns = <114>;
+                gpmc,access-ns = <144>;
-                gpmc,page-burst-access-ns = <6>;
+                gpmc,page-burst-access-ns = <24>;
-                gpmc,bus-turnaround-ns = <12>;
+                gpmc,bus-turnaround-ns = <90>;
-                gpmc,cycle2cycle-delay-ns = <18>;
+                gpmc,cycle2cycle-delay-ns = <90>;
-                gpmc,wr-data-mux-bus-ns = <90>;
-                gpmc,wr-access-ns = <186>;
                gpmc,cycle2cycle-samecsen;
                gpmc,cycle2cycle-diffcsen;
-                vddvario-supply = <&vddvario_sb_t35>;
+                vddvario-supply = <&vddvario>;
-                vdd33a-supply = <&vdd33a_sb_t35>;
+                vdd33a-supply = <&vdd33a>;
                reg-io-width = <4>;
                smsc,save-mac-address;
        };
diff --git a/arch/arm/boot/dts/omap3-sbc-t3517.dts b/arch/arm/boot/dts/omap3-sbc-t3517.dts
index 024c9c6c682d..42189b65d393 100644
--- a/arch/arm/boot/dts/omap3-sbc-t3517.dts
+++ b/arch/arm/boot/dts/omap3-sbc-t3517.dts
@@ -8,6 +8,19 @@
 / {
        model = "CompuLab SBC-T3517 with CM-T3517";
        compatible = "compulab,omap3-sbc-t3517", "compulab,omap3-cm-t3517", "ti,am3517", "ti,omap3";
+        /* Only one GPMC smsc9220 on SBC-T3517, CM-T3517 uses am35x Ethernet */
+        vddvario: regulator-vddvario-sb-t35 {
+                compatible = "regulator-fixed";
+                regulator-name = "vddvario";
+                regulator-always-on;
+        };
+        vdd33a: regulator-vdd33a-sb-t35 {
+                compatible = "regulator-fixed";
+                regulator-name = "vdd33a";
+                regulator-always-on;
+        };
 };
 &omap3_pmx_core {
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index acb9019dc437..b2891a9a6975 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -61,7 +61,7 @@
                        ti,hwmods = "mpu";
                };
-                iva {
+                iva: iva {
                        compatible = "ti,iva2.2";
                        ti,hwmods = "iva";
@@ -267,7 +267,7 @@
                uart1: serial@4806a000 {
                        compatible = "ti,omap3-uart";
                        reg = <0x4806a000 0x2000>;
-                        interrupts = <72>;
+                        interrupts-extended = <&intc 72>;
                        dmas = <&sdma 49 &sdma 50>;
                        dma-names = "tx", "rx";
                        ti,hwmods = "uart1";
@@ -277,7 +277,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap3-uart";
                        reg = <0x4806c000 0x400>;
-                        interrupts = <73>;
+                        interrupts-extended = <&intc 73>;
                        dmas = <&sdma 51 &sdma 52>;
                        dma-names = "tx", "rx";
                        ti,hwmods = "uart2";
@@ -287,7 +287,7 @@
                uart3: serial@49020000 {
                        compatible = "ti,omap3-uart";
                        reg = <0x49020000 0x400>;
-                        interrupts = <74>;
+                        interrupts-extended = <&intc 74>;
                        dmas = <&sdma 53 &sdma 54>;
                        dma-names = "tx", "rx";
                        ti,hwmods = "uart3";
@@ -757,6 +757,51 @@
                                clock-names = "fck";
                        };
                };
+                ssi: ssi-controller@48058000 {
+                        compatible = "ti,omap3-ssi";
+                        ti,hwmods = "ssi";
+                        status = "disabled";
+                        reg = <0x48058000 0x1000>,
+                              <0x48059000 0x1000>;
+                        reg-names = "sys",
+                                    "gdd";
+                        interrupts = <71>;
+                        interrupt-names = "gdd_mpu";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        ssi_port1: ssi-port@4805a000 {
+                                compatible = "ti,omap3-ssi-port";
+                                reg = <0x4805a000 0x800>,
+                                      <0x4805a800 0x800>;
+                                reg-names = "tx",
+                                            "rx";
+                                interrupt-parent = <&intc>;
+                                interrupts = <67>,
+                                             <68>;
+                        };
+                        ssi_port2: ssi-port@4805b000 {
+                                compatible = "ti,omap3-ssi-port";
+                                reg = <0x4805b000 0x800>,
+                                      <0x4805b800 0x800>;
+                                reg-names = "tx",
+                                            "rx";
+                                interrupt-parent = <&intc>;
+                                interrupts = <69>,
+                                             <70>;
+                        };
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap34xx.dtsi b/arch/arm/boot/dts/omap34xx.dtsi
index 2e92360da1f3..3819c1e91591 100644
--- a/arch/arm/boot/dts/omap34xx.dtsi
+++ b/arch/arm/boot/dts/omap34xx.dtsi
@@ -40,6 +40,17 @@
        };
 };
+&ssi {
+        status = "ok";
+        clocks = <&ssi_ssr_fck>,
+                 <&ssi_sst_fck>,
+                 <&ssi_ick>;
+        clock-names = "ssi_ssr_fck",
+                      "ssi_sst_fck",
+                      "ssi_ick";
+};
 /include/ "omap34xx-omap36xx-clocks.dtsi"
 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap36xx-clocks.dtsi
index 6b5280d04a0e..200ae3a5cbbb 100644
--- a/arch/arm/boot/dts/omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-clocks.dtsi
@@ -83,7 +83,7 @@
 };
 &dpll4_m5x2_mul_ck {
-        clock-mult = <1>;
+        ti,clock-mult = <1>;
 };
 &dpll4_m6x2_mul_ck {
diff --git a/arch/arm/boot/dts/omap36xx.dtsi b/arch/arm/boot/dts/omap36xx.dtsi
index 22cf4647087e..541704a59a5a 100644
--- a/arch/arm/boot/dts/omap36xx.dtsi
+++ b/arch/arm/boot/dts/omap36xx.dtsi
@@ -78,6 +78,17 @@
        clock-names = "fck", "tv_dac_clk";
 };
+&ssi {
+        status = "ok";
+        clocks = <&ssi_ssr_fck>,
+                 <&ssi_sst_fck>,
+                 <&ssi_ick>;
+        clock-names = "ssi_ssr_fck",
+                      "ssi_sst_fck",
+                      "ssi_ick";
+};
 /include/ "omap34xx-omap36xx-clocks.dtsi"
 /include/ "omap36xx-omap3430es2plus-clocks.dtsi"
 /include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 12be2b35dae9..e47ff69dcf70 100644
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -453,10 +453,11 @@
        dpll4_m5x2_mul_ck: dpll4_m5x2_mul_ck {
                #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,fixed-factor-clock";
                clocks = <&dpll4_m5_ck>;
-                clock-mult = <2>;
+                ti,clock-mult = <2>;
-                clock-div = <1>;
+                ti,clock-div = <1>;
+                ti,set-rate-parent;
        };
        dpll4_m5x2_ck: dpll4_m5x2_ck {
diff --git a/arch/arm/boot/dts/omap4-duovero-parlor.dts b/arch/arm/boot/dts/omap4-duovero-parlor.dts
index 96f51d870812..cd53a64d8f2e 100644
--- a/arch/arm/boot/dts/omap4-duovero-parlor.dts
+++ b/arch/arm/boot/dts/omap4-duovero-parlor.dts
@@ -46,35 +46,35 @@
        led_pins: pinmux_led_pins {
                pinctrl-single,pins = <
-                        0xd6 (PIN_OUTPUT | MUX_MODE3)           /* abe_dmic_din3.gpio_122 */
+                        OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3)              /* abe_dmic_din3.gpio_122 */
                >;
        };
        button_pins: pinmux_button_pins {
                pinctrl-single,pins = <
-                        0xd4 (PIN_INPUT_PULLUP | MUX_MODE3)     /* abe_dmic_din2.gpio_121 */
+                        OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3)        /* abe_dmic_din2.gpio_121 */
                >;
        };
        i2c2_pins: pinmux_i2c2_pins {
                pinctrl-single,pins = <
-                        0xe6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_scl */
+                        OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c2_scl */
-                        0xe8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c2_sda */
+                        OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c2_sda */
                >;
        };
        i2c3_pins: pinmux_i2c3_pins {
                pinctrl-single,pins = <
-                        0xea (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_scl */
+                        OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c3_scl */
-                        0xec (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c3_sda */
+                        OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c3_sda */
                >;
        };
        smsc_pins: pinmux_smsc_pins {
                pinctrl-single,pins = <
-                        0x28 (PIN_INPUT | MUX_MODE3)            /* gpmc_a20.gpio_44: IRQ */
+                        OMAP4_IOPAD(0x068, PIN_INPUT | MUX_MODE3)               /* gpmc_a20.gpio_44: IRQ */
-                        0x2a (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a21.gpio_45: nReset */
+                        OMAP4_IOPAD(0x06a, PIN_INPUT_PULLUP | MUX_MODE3)        /* gpmc_a21.gpio_45: nReset */
-                        0x30 (PIN_INPUT_PULLUP | MUX_MODE3)     /* gpmc_a24.gpio_48: amdix enabled */
+                        OMAP4_IOPAD(0x070, PIN_INPUT_PULLUP | MUX_MODE3)        /* gpmc_a24.gpio_48: amdix enabled */
                >;
        };
 };
diff --git a/arch/arm/boot/dts/omap4-duovero.dtsi b/arch/arm/boot/dts/omap4-duovero.dtsi
index a514791154eb..e860ccd9d09c 100644
--- a/arch/arm/boot/dts/omap4-duovero.dtsi
+++ b/arch/arm/boot/dts/omap4-duovero.dtsi
@@ -67,100 +67,98 @@
        pinctrl-names = "default";
        pinctrl-0 = <
                        &twl6040_pins
-                        &mcpdm_pins
-                        &mcbsp1_pins
                        &hsusbb1_pins
        >;
        twl6040_pins: pinmux_twl6040_pins {
                pinctrl-single,pins = <
-                        0x126 (PIN_OUTPUT | MUX_MODE3)          /* usbb2_ulpitll_nxt.gpio_160 */
+                        OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE3)              /* usbb2_ulpitll_nxt.gpio_160 */
-                        0x160 (PIN_INPUT | MUX_MODE0)           /* sys_nirq2.sys_nirq2 */
+                        OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0)               /* sys_nirq2.sys_nirq2 */
                >;
        };
        mcpdm_pins: pinmux_mcpdm_pins {
                pinctrl-single,pins = <
-                        0xc6 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
-                        0xc8 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
-                        0xca (PIN_INPUT_PULLUP   | MUX_MODE0)   /* abe_pdm_frame.abe_pdm_frame */
+                        OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP   | MUX_MODE0)      /* abe_pdm_frame.abe_pdm_frame */
-                        0xcc (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
-                        0xce (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_clks.abe_clks */
+                        OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
                >;
        };
        mcbsp1_pins: pinmux_mcbsp1_pins {
                pinctrl-single,pins = <
-                        0xbe (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
+                        OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0)               /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
-                        0xc0 (PIN_INPUT_PULLDOWN | MUX_MODE0)   /* abe_mcbsp1_dr.abe_mcbsp1_dr */
+                        OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_mcbsp1_dr.abe_mcbsp1_dr */
-                        0xc2 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)  /* abe_mcbsp1_dx.abe_mcbsp1_dx */
+                        OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0)     /* abe_mcbsp1_dx.abe_mcbsp1_dx */
-                        0xc4 (PIN_INPUT | MUX_MODE0)            /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
+                        OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0)               /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
                >;
        };
        hsusbb1_pins: pinmux_hsusbb1_pins {
                pinctrl-single,pins = <
-                        0x82 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
-                        0x84 (PIN_OUTPUT | MUX_MODE4)           /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4)              /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
-                        0x86 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
-                        0x88 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
-                        0x8a (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
-                        0x8c (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
-                        0x8e (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
-                        0x90 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
-                        0x92 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
-                        0x94 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
-                        0x96 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
-                        0x98 (PIN_INPUT_PULLDOWN | MUX_MODE4)   /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
+                        OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
                >;
        };
        hsusb1phy_pins: pinmux_hsusb1phy_pins {
                pinctrl-single,pins = <
-                        0x4c (PIN_OUTPUT | MUX_MODE3)           /* gpmc_wait1.gpio_62 */
+                        OMAP4_IOPAD(0x08c, PIN_OUTPUT | MUX_MODE3)              /* gpmc_wait1.gpio_62 */
                >;
        };
        w2cbw0015_pins: pinmux_w2cbw0015_pins {
                pinctrl-single,pins = <
-                        0x26 (PIN_OUTPUT | MUX_MODE3)           /* gpmc_a19.gpio_43 */
+                        OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3)              /* gpmc_a19.gpio_43 */
-                        0x3a (PIN_INPUT | MUX_MODE3)            /* gpmc_ncs3.gpio_53 */
+                        OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3)               /* gpmc_ncs3.gpio_53 */
                >;
        };
        i2c1_pins: pinmux_i2c1_pins {
                pinctrl-single,pins = <
-                        0xe2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_scl */
+                        OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c1_scl */
-                        0xe4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c1_sda */
+                        OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c1_sda */
                >;
        };
        i2c4_pins: pinmux_i2c4_pins {
                pinctrl-single,pins = <
-                        0xee (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_scl */
+                        OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c4_scl */
-                        0xf0 (PIN_INPUT_PULLUP | MUX_MODE0)     /* i2c4_sda */
+                        OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c4_sda */
                >;
        };
        mmc1_pins: pinmux_mmc1_pins {
                pinctrl-single,pins = <
-                        0xa2 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_clk */
+                        OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_clk */
-                        0xa4 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmcc1_cmd */
+                        OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmcc1_cmd */
-                        0xa6 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmcc1_dat0 */
+                        OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmcc1_dat0 */
-                        0xa8 (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat1 */
+                        OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat1 */
-                        0xaa (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat2 */
+                        OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat2 */
-                        0xac (PIN_INPUT_PULLUP | MUX_MODE0)     /* sdmmc1_dat3 */
+                        OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat3 */
                >;
        };
        mmc5_pins: pinmux_mmc5_pins {
                pinctrl-single,pins = <
-                        0x108 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_clk */
+                        OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_clk */
-                        0x10a (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmcc5_cmd */
+                        OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmcc5_cmd */
-                        0x10c (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmcc5_dat0 */
+                        OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmcc5_dat0 */
-                        0x10e (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat1 */
+                        OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat1 */
-                        0x110 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat2 */
+                        OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat2 */
-                        0x112 (PIN_INPUT_PULLUP | MUX_MODE0)    /* sdmmc5_dat3 */
+                        OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat3 */
                >;
        };
 };
@@ -202,6 +200,18 @@
        clock-frequency = <400000>;
 };
+&mcbsp1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcbsp1_pins>;
+        status = "okay";
+};
+&mcpdm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcpdm_pins>;
+        status = "okay";
+};
 &mmc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&mmc1_pins>;
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index d2c45bfaaa2c..8cfa3c8a72b0 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -481,6 +481,21 @@
        usb-supply = <&vusb>;
 };
+&uart2 {
+        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART2_RX>;
+};
+&uart3 {
+        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART3_RX>;
+};
+&uart4 {
+        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART4_RX>;
+};
 &usb_otg_hs {
        interface-type = <1>;
        mode = <3>;
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 48983c8d56c2..3e1da43068f6 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -570,16 +570,22 @@
 };
 &uart2 {
+        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART2_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart2_pins>;
 };
 &uart3 {
+        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART3_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart3_pins>;
 };
 &uart4 {
+        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
+                               &omap4_pmx_core OMAP4_UART4_RX>;
        pinctrl-names = "default";
        pinctrl-0 = <&uart4_pins>;
 };
diff --git a/arch/arm/boot/dts/omap4-var-dvk-om44.dts b/arch/arm/boot/dts/omap4-var-dvk-om44.dts
new file mode 100644
index 000000000000..458d79fa378b
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var-dvk-om44.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "omap4-var-som-om44.dtsi"
+#include "omap4-var-som-om44-wlan.dtsi"
+#include "omap4-var-om44customboard.dtsi"
+/ {
+        model = "Variscite VAR-DVK-OM44";
+        compatible = "variscite,var-dvk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
+        aliases {
+                display0 = &lcd0;
+                display1 = &hdmi0;
+        };
+        lcd0: display {
+                compatible = "innolux,at070tn83", "panel-dpi";
+                label = "lcd";
+                panel-timing {
+                        clock-frequency = <33333333>;
+                        hback-porch = <40>;
+                        hactive = <800>;
+                        hfront-porch = <40>;
+                        hsync-len = <48>;
+                        vback-porch = <29>;
+                        vactive = <480>;
+                        vfront-porch = <13>;
+                        vsync-len = <3>;
+                };
+                port {
+                        lcd_in: endpoint {
+                                remote-endpoint = <&dpi_out>;
+                        };
+                };
+        };
+        backlight {
+                compatible = "gpio-backlight";
+                pinctrl-names = "default";
+                pinctrl-0 = <&backlight_pins>;
+                gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* gpio 122 */
+        };
+};
+&dss {
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_dpi_pins>;
+        port {
+                dpi_out: endpoint {
+                        remote-endpoint = <&lcd_in>;
+                        data-lines = <24>;
+                };
+        };
+};
+&dsi2 {
+        status = "okay";
+        vdd-supply = <&vcxio>;
+};
diff --git a/arch/arm/boot/dts/omap4-var-om44customboard.dtsi b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
new file mode 100644
index 000000000000..f2d2fdb75628
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var-om44customboard.dtsi
@@ -0,0 +1,235 @@
+/*
+ * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/input/input.h>
+/ {
+        aliases {
+                display0 = &hdmi0;
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_led_pins>;
+                led0 {
+                        label = "var:green:led0";
+                        gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; /* gpio 173 */
+                        linux,default-trigger = "heartbeat";
+                };
+                led1 {
+                        label = "var:green:led1";
+                        gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; /* gpio 172 */
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gpio_key_pins>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                user-key@184 {
+                        label = "user";
+                        gpios = <&gpio6 24 GPIO_ACTIVE_HIGH>; /* gpio 184 */
+                        linux,code = <BTN_EXTRA>;
+                        gpio-key,wakeup;
+                };
+        };
+        hdmi0: connector@0 {
+                compatible = "hdmi-connector";
+                pinctrl-names = "default";
+                pinctrl-0 = <&hdmi_hpd_pins>;
+                label = "hdmi";
+                type = "a";
+                hpd-gpios = <&gpio2 31 GPIO_ACTIVE_HIGH>; /* gpio_63 */
+                port {
+                        hdmi_connector_in: endpoint {
+                                remote-endpoint = <&hdmi_out>;
+                        };
+                };
+        };
+};
+&omap4_pmx_core {
+        uart1_pins: pinmux_uart1_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x13c, PIN_INPUT_PULLUP | MUX_MODE1)        /* mcspi1_cs2.uart1_cts */
+                        OMAP4_IOPAD(0x13e, PIN_OUTPUT | MUX_MODE1)              /* mcspi1_cs3.uart1_rts */
+                        OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE1)        /* i2c2_scl.uart1_rx */
+                        OMAP4_IOPAD(0x128, PIN_OUTPUT | MUX_MODE1)              /* i2c2_sda.uart1_tx */
+                >;
+        };
+        mcspi1_pins: pinmux_mcspi1_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0)               /*  mcspi1_clk.mcspi1_clk */
+                        OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0)               /*  mcspi1_somi.mcspi1_somi */
+                        OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0)               /*  mcspi1_simo.mcspi1_simo */
+                        OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0)               /*  mcspi1_cs0.mcspi1_cs0 */
+                >;
+        };
+        mcasp_pins: pinmux_mcsasp_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x0f8, PIN_OUTPUT | MUX_MODE2)              /*  mcbsp2_dr.abe_mcasp_axr */
+                >;
+        };
+        dss_dpi_pins: pinmux_dss_dpi_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data23 */
+                        OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data22 */
+                        OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data21 */
+                        OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data20 */
+                        OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data19 */
+                        OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data18 */
+                        OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data15 */
+                        OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data14 */
+                        OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data13 */
+                        OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data12 */
+                        OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data11 */
+                        OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data10 */
+                        OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data9 */
+                        OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data16 */
+                        OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data17 */
+                        OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5)              /* dispc2_hsync */
+                        OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5)              /* dispc2_pclk */
+                        OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5)              /* dispc2_vsync */
+                        OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5)              /* dispc2_de */
+                        OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data8 */
+                        OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data7 */
+                        OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data6 */
+                        OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data5 */
+                        OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data4 */
+                        OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data3 */
+                        OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data2 */
+                        OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data1 */
+                        OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5)              /* dispc2_data0 */
+                >;
+        };
+        dss_hdmi_pins: pinmux_dss_hdmi_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x09a, PIN_INPUT_PULLUP | MUX_MODE0)        /* hdmi_cec.hdmi_cec */
+                        OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0)        /* hdmi_scl.hdmi_scl */
+                        OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0)        /* hdmi_sda.hdmi_sda */
+                >;
+        };
+        i2c4_pins: pinmux_i2c4_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c4_scl */
+                        OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c4_sda */
+                >;
+        };
+        mmc5_pins: pinmux_mmc5_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE3)               /* abe_mcbsp2_clkx.gpio_110 */
+                        OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_clk.sdmmc5_clk */
+                        OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_cmd.sdmmc5_cmd */
+                        OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat0.sdmmc5_dat0 */
+                        OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat1.sdmmc5_dat1 */
+                        OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat2.sdmmc5_dat2 */
+                        OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc5_dat3.sdmmc5_dat3 */
+                >;
+        };
+        gpio_led_pins: pinmux_gpio_led_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x17e, PIN_OUTPUT | MUX_MODE3)              /* kpd_col4.gpio_172 */
+                        OMAP4_IOPAD(0x180, PIN_OUTPUT | MUX_MODE3)              /* kpd_col5.gpio_173 */
+                >;
+        };
+        gpio_key_pins: pinmux_gpio_key_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x1a2, PIN_INPUT | MUX_MODE3)               /* sys_boot0.gpio_184 */
+                >;
+        };
+        ks8851_irq_pins: pinmux_ks8851_irq_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x17c, PIN_INPUT_PULLUP | MUX_MODE3)        /* kpd_col3.gpio_171 */
+                >;
+        };
+        hdmi_hpd_pins: pinmux_hdmi_hpd_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3)      /* hdmi_hpd.gpio_63 */
+                >;
+        };
+        backlight_pins: pinmux_backlight_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x116, PIN_OUTPUT | MUX_MODE3)              /* abe_dmic_din3.gpio_122 */
+                >;
+        };
+};
+&i2c4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c4_pins>;
+        clock-frequency = <400000>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart1_pins>;
+        status = "okay";
+};
+&mcspi1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcspi1_pins>;
+        status = "okay";
+        eth@0 {
+                compatible = "ks8851";
+                pinctrl-names = "default";
+                pinctrl-0 = <&ks8851_irq_pins>;
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio 171 */
+        };
+};
+&mmc5 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc5_pins>;
+        vmmc-supply = <&vbat>;
+        bus-width = <4>;
+        cd-gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>; /* gpio 110 */
+        status = "okay";
+};
+&dss {
+        status = "okay";
+};
+&hdmi {
+        status = "okay";
+        pinctrl-names = "default";
+        pinctrl-0 = <&dss_hdmi_pins>;
+        vdda-supply = <&vdac>;
+        port {
+                hdmi_out: endpoint {
+                        remote-endpoint = <&hdmi_connector_in>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
new file mode 100644
index 000000000000..cc66af419236
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var-som-om44-wlan.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        /* regulator for wl12xx on sdio4 */
+        wl12xx_vmmc: wl12xx_vmmc {
+                pinctrl-names = "default";
+                pinctrl-0 = <&wl12xx_ctrl_pins>;
+                compatible = "regulator-fixed";
+                regulator-name = "vwl1271";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <1800000>;
+                gpio = <&gpio2 11 0>;   /* gpio 43 */
+                startup-delay-us = <70000>;
+                enable-active-high;
+        };
+};
+&omap4_pmx_core {
+        uart2_pins: pinmux_uart2_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0)        /* uart2_cts.uart2_cts */
+                        OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0)              /* uart2_rts.uart2_rts */
+                        OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0)        /* uart2_rx.uart2_rx */
+                        OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0)              /* uart2_tx.uart2_tx */
+                >;
+        };
+        wl12xx_ctrl_pins: pinmux_wl12xx_ctrl_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x062, PIN_INPUT_PULLUP | MUX_MODE3)        /* gpmc_a17.gpio_41 (WLAN_IRQ) */
+                        OMAP4_IOPAD(0x064, PIN_OUTPUT | MUX_MODE3)              /* gpmc_a18.gpio_42 (BT_EN) */
+                        OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3)              /* gpmc_a19.gpio_43 (WLAN_EN) */
+                >;
+        };
+        mmc4_pins: pinmux_mmc4_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x154, PIN_INPUT_PULLUP | MUX_MODE1)        /* mcspi4_clk.sdmmc4_clk */
+                        OMAP4_IOPAD(0x156, PIN_INPUT_PULLUP | MUX_MODE1)        /* mcspi4_simo.sdmmc4_cmd */
+                        OMAP4_IOPAD(0x158, PIN_INPUT_PULLUP | MUX_MODE1)        /* mcspi4_somi.sdmmc4_dat0 */
+                        OMAP4_IOPAD(0x15e, PIN_INPUT_PULLUP | MUX_MODE1)        /* uart4_tx.sdmmc4_dat1 */
+                        OMAP4_IOPAD(0x15c, PIN_INPUT_PULLUP | MUX_MODE1)        /* uart4_rx.sdmmc4_dat2 */
+                        OMAP4_IOPAD(0x15a, PIN_INPUT_PULLUP | MUX_MODE1)        /* mcspi4_cs0.sdmmc4_dat3 */
+                >;
+        };
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart2_pins>;
+        status = "okay";
+};
+&mmc4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc4_pins>;
+        vmmc-supply = <&wl12xx_vmmc>;
+        non-removable;
+        bus-width = <4>;
+        cap-power-off-card;
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/omap4-var-som-om44.dtsi b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
new file mode 100644
index 000000000000..062701e1a898
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var-som-om44.dtsi
@@ -0,0 +1,343 @@
+/*
+ * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
+ * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include "omap4460.dtsi"
+/ {
+        model = "Variscite VAR-SOM-OM44";
+        compatible = "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+        sound: sound@0 {
+                compatible = "ti,abe-twl6040";
+                ti,model = "VAR-SOM-OM44";
+                ti,mclk-freq = <38400000>;
+                ti,mcpdm = <&mcpdm>;
+                ti,twl6040 = <&twl6040>;
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "AFML", "Line In",
+                        "AFMR", "Line In";
+        };
+        /* HS USB Host PHY on PORT 1 */
+        hsusb1_phy: hsusb1_phy {
+                compatible = "usb-nop-xceiv";
+                pinctrl-names = "default";
+                pinctrl-0 = <
+                        &hsusbb1_phy_clk_pins
+                        &hsusbb1_phy_rst_pins
+                >;
+                reset-gpios = <&gpio6 17 GPIO_ACTIVE_LOW>; /* gpio 177 */
+                vcc-supply = <&vbat>;
+                clocks = <&auxclk3_ck>;
+                clock-names = "main_clk";
+                clock-frequency = <19200000>;
+        };
+        vbat: fixedregulator-vbat {
+                compatible = "regulator-fixed";
+                regulator-name = "VBAT";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+                regulator-boot-on;
+        };
+};
+&omap4_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &hsusbb1_pins
+        >;
+        twl6040_pins: pinmux_twl6040_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x19c, PIN_OUTPUT | MUX_MODE3)              /* fref_clk2_out.gpio_182 */
+                        OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0)               /* sys_nirq2.sys_nirq2 */
+                >;
+        };
+        mcpdm_pins: pinmux_mcpdm_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_ul_data.abe_pdm_ul_data */
+                        OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_dl_data.abe_pdm_dl_data */
+                        OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)        /* abe_pdm_frame.abe_pdm_frame */
+                        OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_pdm_lb_clk.abe_pdm_lb_clk */
+                        OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)      /* abe_clks.abe_clks */
+                >;
+        };
+        tsc2004_pins: pinmux_tsc2004_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x090, PIN_INPUT | MUX_MODE3)               /* gpmc_ncs4.gpio_101 (irq) */
+                        OMAP4_IOPAD(0x092, PIN_OUTPUT | MUX_MODE3)              /* gpmc_ncs5.gpio_102 (rst) */
+                >;
+        };
+        uart3_pins: pinmux_uart3_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0)        /* uart3_cts_rctx.uart3_cts_rctx */
+                        OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0)              /* uart3_rts_sd.uart3_rts_sd */
+                        OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0)               /* uart3_rx_irrx.uart3_rx_irrx */
+                        OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0)              /* uart3_tx_irtx.uart3_tx_irtx */
+                >;
+        };
+        hsusbb1_pins: pinmux_hsusbb1_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
+                        OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4)              /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
+                        OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
+                        OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
+                        OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
+                        OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
+                        OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
+                        OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
+                        OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
+                        OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
+                        OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
+                        OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4)      /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
+                >;
+        };
+        hsusbb1_phy_rst_pins: pinmux_hsusbb1_phy_rst_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x18c, PIN_OUTPUT | MUX_MODE3)              /* kpd_row2.gpio_177 */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c1_scl */
+                        OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c1_sda */
+                >;
+        };
+        i2c3_pins: pinmux_i2c3_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c3_scl */
+                        OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0)        /* i2c3_sda */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x0e2, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_clk.sdmmc1_clk */
+                        OMAP4_IOPAD(0x0e4, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_cmd.sdmmc1_cmd */
+                        OMAP4_IOPAD(0x0e6, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat0.sdmmc1_dat0 */
+                        OMAP4_IOPAD(0x0e8, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat1.sdmmc1_dat1 */
+                        OMAP4_IOPAD(0x0ea, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat2.sdmmc1_dat2 */
+                        OMAP4_IOPAD(0x0ec, PIN_INPUT_PULLUP | MUX_MODE0)        /* sdmmc1_dat3.sdmmc1_dat3 */
+                >;
+        };
+};
+&omap4_pmx_wkup {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &hsusbb1_hub_rst_pins
+                &lan7500_rst_pins
+        >;
+        hsusbb1_phy_clk_pins: pinmux_hsusbb1_phy_clk_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x058, PIN_OUTPUT | MUX_MODE0)      /* fref_clk3_out */
+                >;
+        };
+        hsusbb1_hub_rst_pins: pinmux_hsusbb1_hub_rst_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x042, PIN_OUTPUT | MUX_MODE3)      /* gpio_wk1 */
+                >;
+        };
+        lan7500_rst_pins: pinmux_lan7500_rst_pins {
+                pinctrl-single,pins = <
+                        OMAP4_IOPAD(0x040, PIN_OUTPUT | MUX_MODE3)      /* gpio_wk0 */
+                >;
+        };
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        status = "okay";
+        clock-frequency = <400000>;
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&twl6040_pins>;
+                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio6 22 0>; /* gpio 182 */
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+        };
+};
+#include "twl6030.dtsi"
+#include "twl6030_omap4.dtsi"
+&vusim {
+        regulator-min-microvolt = <3000000>;
+        regulator-max-microvolt = <3000000>;
+        regulator-always-on;
+};
+&i2c2 {
+        status = "disabled";
+};
+&i2c3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c3_pins>;
+        status = "okay";
+        clock-frequency = <400000>;
+        touchscreen: tsc2004@48 {
+                compatible = "ti,tsc2004";
+                reg = <0x48>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&tsc2004_pins>;
+                interrupt-parent = <&gpio4>;
+                interrupts = <5 IRQ_TYPE_LEVEL_LOW>; /* gpio 101 */
+                status = "disabled";
+        };
+        tmp105@49 {
+                compatible = "ti,tmp105";
+                reg = <0x49>;
+        };
+        eeprom@50 {
+                compatible = "microchip,24c32";
+                reg = <0x50>;
+        };
+};
+&i2c4 {
+        status = "disabled";
+};
+&mcpdm {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mcpdm_pins>;
+        status = "okay";
+};
+&gpmc {
+        status = "disabled";
+};
+&mcspi1 {
+        status = "disabled";
+};
+&mcspi2 {
+        status = "disabled";
+};
+&mcspi3 {
+        status = "disabled";
+};
+&mcspi4 {
+        status = "disabled";
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&vmmc>;
+        bus-width = <4>;
+        ti,non-removable;
+        status = "okay";
+};
+&mmc2 {
+        status = "disabled";
+};
+&mmc3 {
+        status = "disabled";
+};
+&mmc4 {
+        status = "disabled";
+};
+&mmc5 {
+        status = "disabled";
+};
+&uart1 {
+        status = "disabled";
+};
+&uart2 {
+        status = "disabled";
+};
+&uart3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&uart3_pins>;
+        status = "okay";
+};
+&uart4 {
+        status = "disabled";
+};
+&keypad {
+        status = "disabled";
+};
+&twl_usb_comparator {
+        usb-supply = <&vusb>;
+};
+&usb_otg_hs {
+        interface-type = <1>;
+        mode = <3>;
+        power = <50>;
+};
+&usbhshost {
+        port1-mode = "ehci-phy";
+};
+&usbhsehci {
+        phys = <&hsusb1_phy>;
+};
diff --git a/arch/arm/boot/dts/omap4-var-som.dts b/arch/arm/boot/dts/omap4-var-som.dts
deleted file mode 100644
index b41269e871dd..000000000000
--- a/arch/arm/boot/dts/omap4-var-som.dts
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-/dts-v1/;
-#include "omap443x.dtsi"
-/ {
-        model = "Variscite OMAP4 SOM";
-        compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
-        memory {
-                device_type = "memory";
-                reg = <0x80000000 0x40000000>; /* 1 GB */
-        };
-        vdd_eth: fixedregulator@0 {
-                compatible = "regulator-fixed";
-                regulator-name = "VDD_ETH";
-                regulator-min-microvolt = <3300000>;
-                regulator-max-microvolt = <3300000>;
-                enable-active-high;
-                regulator-boot-on;
-        };
-};
-&i2c1 {
-        clock-frequency = <400000>;
-        twl: twl@48 {
-                reg = <0x48>;
-                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
-                interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
-                interrupt-parent = <&gic>;
-        };
-};
-#include "twl6030.dtsi"
-&i2c2 {
-        clock-frequency = <400000>;
-};
-&i2c3 {
-        clock-frequency = <400000>;
-        /*
-         * Temperature Sensor
-         * http://www.ti.com/lit/ds/symlink/tmp105.pdf
-         */
-        tmp105@49 {
-                compatible = "ti,tmp105";
-                reg = <0x49>;
-        };
-};
-&i2c4 {
-        clock-frequency = <400000>;
-};
-&mcspi1 {
-        eth@0 {
-                compatible = "ks8851";
-                spi-max-frequency = <24000000>;
-                reg = <0>;
-                interrupt-parent = <&gpio6>;
-                interrupts = <11 IRQ_TYPE_LEVEL_LOW>; /* gpio line 171 */
-                vdd-supply = <&vdd_eth>;
-        };
-};
-&mmc1 {
-        vmmc-supply = <&vmmc>;
-        ti,bus-width = <8>;
-        ti,non-removable;
-};
-&mmc2 {
-        status = "disabled";
-};
-&mmc3 {
-        status = "disabled";
-};
-&mmc4 {
-        status = "disabled";
-};
-&mmc5 {
-        ti,bus-width = <4>;
-};
diff --git a/arch/arm/boot/dts/omap4-var-stk-om44.dts b/arch/arm/boot/dts/omap4-var-stk-om44.dts
new file mode 100644
index 000000000000..56b64e618608
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var-stk-om44.dts
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2014 Joachim Eastwood <manabian@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "omap4-var-som-om44.dtsi"
+#include "omap4-var-som-om44-wlan.dtsi"
+#include "omap4-var-om44customboard.dtsi"
+/ {
+        model = "Variscite VAR-STK-OM44";
+        compatible = "variscite,var-stk-om44", "variscite,var-som-om44", "ti,omap4460", "ti,omap4";
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 649b5cd38b40..43a587e097d4 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -67,6 +67,7 @@
        local-timer@48240600 {
                compatible = "arm,cortex-a9-twd-timer";
+                clocks = <&mpu_periphclk>;
                reg = <0x48240600 0x20>;
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
        };
@@ -311,7 +312,7 @@
                uart2: serial@4806c000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806c000 0x100>;
-                        interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart2";
                        clock-frequency = <48000000>;
                };
@@ -319,7 +320,7 @@
                uart3: serial@48020000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x48020000 0x100>;
-                        interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart3";
                        clock-frequency = <48000000>;
                };
@@ -327,7 +328,7 @@
                uart4: serial@4806e000 {
                        compatible = "ti,omap4-uart";
                        reg = <0x4806e000 0x100>;
-                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+                        interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        ti,hwmods = "uart4";
                        clock-frequency = <48000000>;
                };
@@ -642,6 +643,8 @@
                                compatible = "ti,omap-usb2";
                                reg = <0x4a0ad080 0x58>;
                                ctrl-module = <&omap_control_usb2phy>;
+                                clocks = <&usb_phy_cm_clk32k>;
+                                clock-names = "wkupclk";
                                #phy-cells = <0>;
                        };
                };
diff --git a/arch/arm/boot/dts/omap5-cm-t54.dts b/arch/arm/boot/dts/omap5-cm-t54.dts
new file mode 100644
index 000000000000..b8698ca68647
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-cm-t54.dts
@@ -0,0 +1,413 @@
+/*
+ * Support for CompuLab CM-T54
+ */
+/dts-v1/;
+#include "omap5.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        model = "CompuLab CM-T54";
+        compatible = "compulab,omap5-cm-t54", "ti,omap5";
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x7F000000>; /* 2048 MB */
+        };
+        vmmcsd_fixed: fixed-regulator-mmcsd {
+                compatible = "regulator-fixed";
+                regulator-name = "vmmcsd_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
+        vwlan_pdn_fixed: fixed-regulator-vwlan-pdn {
+                compatible = "regulator-fixed";
+                regulator-name = "vwlan_pdn_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&ldo2_reg>;
+                gpio = <&gpio4 13 GPIO_ACTIVE_HIGH>;   /* gpio4_109 */
+                startup-delay-us = <1000>;
+                enable-active-high;
+        };
+        vwlan_fixed: fixed-regulator-vwlan {
+                compatible = "regulator-fixed";
+                regulator-name = "vwlan_fixed";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                vin-supply = <&vwlan_pdn_fixed>;
+                gpio = <&gpio4 14 GPIO_ACTIVE_HIGH>;   /* gpio4_110 */
+                startup-delay-us = <1000>;
+                enable-active-high;
+        };
+        /* HS USB Host PHY on PORT 2 */
+        hsusb2_phy: hsusb2_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; /* gpio3_76 HUB_RESET */
+        };
+        /* HS USB Host PHY on PORT 3 */
+        hsusb3_phy: hsusb3_phy {
+                compatible = "usb-nop-xceiv";
+                reset-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 ETH_RESET */
+        };
+        leds {
+                compatible = "gpio-leds";
+                led@1 {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 ACT_LED */
+                        linux,default-trigger = "heartbeat";
+                        default-state = "off";
+                };
+        };
+};
+&omap5_pmx_core {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                        &led_gpio_pins
+                        &usbhost_pins
+        >;
+        led_gpio_pins: pinmux_led_gpio_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x00b0, PIN_OUTPUT | MUX_MODE6) /* hsi2_caflag.gpio3_80 */
+                >;
+        };
+        i2c1_pins: pinmux_i2c1_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x01f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_scl */
+                        OMAP5_IOPAD(0x01f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_pmic_sda */
+                >;
+        };
+        mmc1_pins: pinmux_mmc1_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x01e2, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_clk */
+                        OMAP5_IOPAD(0x01e4, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_cmd */
+                        OMAP5_IOPAD(0x01e6, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data2 */
+                        OMAP5_IOPAD(0x01e8, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data3 */
+                        OMAP5_IOPAD(0x01ea, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data0 */
+                        OMAP5_IOPAD(0x01ec, PIN_INPUT_PULLUP | MUX_MODE0) /* sdcard_data1 */
+                >;
+        };
+        mmc2_pins: pinmux_mmc2_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x0040, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_clk */
+                        OMAP5_IOPAD(0x0042, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_cmd */
+                        OMAP5_IOPAD(0x0044, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data0 */
+                        OMAP5_IOPAD(0x0046, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data1 */
+                        OMAP5_IOPAD(0x0048, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data2 */
+                        OMAP5_IOPAD(0x004a, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data3 */
+                        OMAP5_IOPAD(0x004c, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data4 */
+                        OMAP5_IOPAD(0x004e, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data5 */
+                        OMAP5_IOPAD(0x0050, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data6 */
+                        OMAP5_IOPAD(0x0052, PIN_INPUT_PULLUP | MUX_MODE0) /* emmc_data7 */
+                >;
+        };
+        mmc3_pins: pinmux_mmc3_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
+                        OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
+                        OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
+                        OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
+                        OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
+                        OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
+                >;
+        };
+        wlan_gpios_pins: pinmux_wlan_gpios_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x019c, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_109 */
+                        OMAP5_IOPAD(0x019e, PIN_OUTPUT_PULLDOWN | MUX_MODE6) /* gpio4_110 */
+                >;
+        };
+        usbhost_pins: pinmux_usbhost_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x00c4, PIN_INPUT | MUX_MODE0)  /* usbb2_hsic_strobe */
+                        OMAP5_IOPAD(0x00c6, PIN_INPUT | MUX_MODE0)  /* usbb2_hsic_data */
+                        OMAP5_IOPAD(0x01dc, PIN_INPUT | MUX_MODE0)  /* usbb3_hsic_strobe */
+                        OMAP5_IOPAD(0x01de, PIN_INPUT | MUX_MODE0)  /* usbb3_hsic_data */
+                        OMAP5_IOPAD(0x00a8, PIN_OUTPUT | MUX_MODE6) /* hsi2_caready.gpio3_76 */
+                        OMAP5_IOPAD(0x00b6, PIN_OUTPUT | MUX_MODE6) /* hsi2_acdata.gpio3_83 */
+                >;
+        };
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc1_pins>;
+        vmmc-supply = <&ldo9_reg>;
+        bus-width = <4>;
+};
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins>;
+        vmmc-supply = <&vmmcsd_fixed>;
+        bus-width = <8>;
+        ti,non-removable;
+};
+&mmc3 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &mmc3_pins
+                &wlan_gpios_pins
+        >;
+        vmmc-supply = <&vwlan_fixed>;
+        bus-width = <4>;
+        ti,non-removable;
+};
+&mmc4 {
+        status = "disabled";
+};
+&mmc5 {
+        status = "disabled";
+};
+&i2c1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c1_pins>;
+        clock-frequency = <400000>;
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
+        palmas: palmas@48 {
+                compatible = "ti,palmas";
+                interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* IRQ_SYS_1N */
+                interrupt-parent = <&gic>;
+                reg = <0x48>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                ti,system-power-controller;
+                extcon_usb3: palmas_usb {
+                        compatible = "ti,palmas-usb-vid";
+                        ti,enable-vbus-detection;
+                        ti,enable-id-detection;
+                        ti,wakeup;
+                };
+                rtc {
+                        compatible = "ti,palmas-rtc";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <8 IRQ_TYPE_NONE>;
+                };
+                palmas_pmic {
+                        compatible = "ti,palmas-pmic";
+                        interrupt-parent = <&palmas>;
+                        interrupts = <14 IRQ_TYPE_NONE>;
+                        interrupt-name = "short-irq";
+                        ti,ldo6-vibrator;
+                        regulators {
+                                smps123_reg: smps123 {
+                                        /* VDD_OPP_MPU */
+                                        regulator-name = "smps123";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps45_reg: smps45 {
+                                        /* VDD_OPP_MM */
+                                        regulator-name = "smps45";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps6_reg: smps6 {
+                                        /* VDD_DDR3 - over VDD_SMPS6 */
+                                        regulator-name = "smps6";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps7_reg: smps7 {
+                                        /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
+                                        regulator-name = "smps7";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps8_reg: smps8 {
+                                        /* VDD_OPP_CORE */
+                                        regulator-name = "smps8";
+                                        regulator-min-microvolt = < 600000>;
+                                        regulator-max-microvolt = <1310000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps9_reg: smps9 {
+                                        /* VDDA_2v1_AUD over VDD_2v1 */
+                                        regulator-name = "smps9";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        ti,smps-range = <0x80>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps10_out2_reg: smps10_out2 {
+                                        /* VBUS_5V_OTG */
+                                        regulator-name = "smps10_out2";
+                                        regulator-min-microvolt = <5000000>;
+                                        regulator-max-microvolt = <5000000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                smps10_out1_reg: smps10_out1 {
+                                        /* VBUS_5V_OTG */
+                                        regulator-name = "smps10_out1";
+                                        regulator-min-microvolt = <5000000>;
+                                        regulator-max-microvolt = <5000000>;
+                                };
+                                ldo1_reg: ldo1 {
+                                        /* VDDAPHY_CAM: vdda_csiport */
+                                        regulator-name = "ldo1";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo2_reg: ldo2 {
+                                        /* VDD_3V3_WLAN */
+                                        regulator-name = "ldo2";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        startup-delay-us = <1000>;
+                                };
+                                ldo3_reg: ldo3 {
+                                        /* VCC_1V5_AUD */
+                                        regulator-name = "ldo3";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo4_reg: ldo4 {
+                                        /* VDDAPHY_DISP: vdda_dsiport/hdmi */
+                                        regulator-name = "ldo4";
+                                        regulator-min-microvolt = <1500000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo5_reg: ldo5 {
+                                        /* VDDA_1V8_PHY: usb/sata/hdmi.. */
+                                        regulator-name = "ldo5";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo6_reg: ldo6 {
+                                        /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
+                                        regulator-name = "ldo6";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldo7_reg: ldo7 {
+                                        /* VDD_VPP: vpp1 */
+                                        regulator-name = "ldo7";
+                                        regulator-min-microvolt = <2000000>;
+                                        regulator-max-microvolt = <2000000>;
+                                        /* Only for efuse reprograming! */
+                                        status = "disabled";
+                                };
+                                ldo8_reg: ldo8 {
+                                        /* VDD_3v0: Does not go anywhere */
+                                        regulator-name = "ldo8";
+                                        regulator-min-microvolt = <3000000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-boot-on;
+                                        /* Unused */
+                                        status = "disabled";
+                                };
+                                ldo9_reg: ldo9 {
+                                        /* VCC_DV_SDIO: vdds_sdcard */
+                                        regulator-name = "ldo9";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3000000>;
+                                        regulator-boot-on;
+                                };
+                                ldoln_reg: ldoln {
+                                        /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
+                                        regulator-name = "ldoln";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                ldousb_reg: ldousb {
+                                        /* VDDA_3V_USB: VDDA_USBHS33 */
+                                        regulator-name = "ldousb";
+                                        regulator-min-microvolt = <3250000>;
+                                        regulator-max-microvolt = <3250000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                regen3_reg: regen3 {
+                                        /* REGEN3 controls LDO9 supply to card */
+                                        regulator-name = "regen3";
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                        };
+                };
+        };
+};
+&usbhshost {
+        port2-mode = "ehci-hsic";
+        port3-mode = "ehci-hsic";
+};
+&usbhsehci {
+        phys = <0 &hsusb2_phy &hsusb3_phy>;
+};
+&cpu0 {
+        cpu0-supply = <&smps123_reg>;
+};
diff --git a/arch/arm/boot/dts/omap5-sbc-t54.dts b/arch/arm/boot/dts/omap5-sbc-t54.dts
new file mode 100644
index 000000000000..aa98fea3f2b3
--- /dev/null
+++ b/arch/arm/boot/dts/omap5-sbc-t54.dts
@@ -0,0 +1,51 @@
+/*
+ * Suppport for CompuLab SBC-T54 with CM-T54
+ */
+#include "omap5-cm-t54.dts"
+/ {
+        model = "CompuLab SBC-T54 with CM-T54";
+        compatible = "compulab,omap5-sbc-t54", "compulab,omap5-cm-t54", "ti,omap5";
+};
+&omap5_pmx_core {
+        i2c4_pins: pinmux_i2c4_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x00f8, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
+                        OMAP5_IOPAD(0x00fa, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
+                >;
+        };
+        mmc1_aux_pins: pinmux_mmc1_aux_pins {
+                pinctrl-single,pins = <
+                        OMAP5_IOPAD(0x0174, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_228 */
+                        OMAP5_IOPAD(0x0176, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio8_229 */
+                >;
+        };
+};
+&mmc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <
+                &mmc1_pins
+                &mmc1_aux_pins
+        >;
+        cd-inverted;
+        wp-inverted;
+        cd-gpios = <&gpio8 4 GPIO_ACTIVE_LOW>; /* gpio8_228 */
+        wp-gpios = <&gpio8 5 GPIO_ACTIVE_LOW>; /* gpio8_229 */
+};
+&i2c4 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&i2c4_pins>;
+        clock-frequency = <400000>;
+        at24@50 {
+                compatible = "at24,24c02";
+                pagesize = <16>;
+                reg = <0x50>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index f8c9855ce587..e58be57984ab 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -82,6 +82,12 @@
                             <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
        };
+        pmu {
+                compatible = "arm,cortex-a15-pmu";
+                interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+                             <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+        };
        gic: interrupt-controller@48211000 {
                compatible = "arm,cortex-a15-gic";
                interrupt-controller;
@@ -630,6 +636,13 @@
                        status = "disabled";
                };
+                mailbox: mailbox@4a0f4000 {
+                        compatible = "ti,omap4-mailbox";
+                        reg = <0x4a0f4000 0x200>;
+                        interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+                        ti,hwmods = "mailbox";
+                };
                timer1: timer@4ae18000 {
                        compatible = "ti,omap5430-timer";
                        reg = <0x4ae18000 0x80>;
@@ -803,6 +816,8 @@
                                compatible = "ti,omap-usb2";
                                reg = <0x4a084000 0x7c>;
                                ctrl-module = <&omap_control_usb2phy>;
+                                clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+                                clock-names = "wkupclk", "refclk";
                                #phy-cells = <0>;
                        };
@@ -869,6 +884,46 @@
                        #thermal-sensor-cells = <1>;
                };
+                omap_control_sata: control-phy@4a002374 {
+                        compatible = "ti,control-phy-pipe3";
+                        reg = <0x4a002374 0x4>;
+                        reg-names = "power";
+                        clocks = <&sys_clkin>;
+                        clock-names = "sysclk";
+                };
+                /* OCP2SCP3 */
+                ocp2scp@4a090000 {
+                        compatible = "ti,omap-ocp2scp";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x4a090000 0x20>;
+                        ranges;
+                        ti,hwmods = "ocp2scp3";
+                        sata_phy: phy@4a096000 {
+                                compatible = "ti,phy-pipe3-sata";
+                                reg = <0x4A096000 0x80>, /* phy_rx */
+                                      <0x4A096400 0x64>, /* phy_tx */
+                                      <0x4A096800 0x40>; /* pll_ctrl */
+                                reg-names = "phy_rx", "phy_tx", "pll_ctrl";
+                                ctrl-module = <&omap_control_sata>;
+                                clocks = <&sys_clkin>;
+                                clock-names = "sysclk";
+                                #phy-cells = <0>;
+                        };
+                };
+                sata: sata@4a141100 {
+                        compatible = "snps,dwc-ahci";
+                        reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
+                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+                        phys = <&sata_phy>;
+                        phy-names = "sata-phy";
+                        clocks = <&sata_ref_clk>;
+                        ti,hwmods = "sata";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 465505cada59..e67a23b5d788 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -120,10 +120,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_x2_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x01f0>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        abe_24m_fclk: abe_24m_fclk {
@@ -145,10 +143,11 @@
        abe_iclk: abe_iclk {
                #clock-cells = <0>;
-                compatible = "fixed-factor-clock";
+                compatible = "ti,divider-clock";
-                clocks = <&abe_clk>;
+                clocks = <&aess_fclk>;
-                clock-mult = <1>;
+                ti,bit-shift = <24>;
-                clock-div = <2>;
+                reg = <0x0528>;
+                ti,dividers = <2>, <1>;
        };
        abe_lp_clk_div: abe_lp_clk_div {
@@ -164,10 +163,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_abe_x2_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x01f4>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_ck: dpll_core_ck {
@@ -188,10 +185,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0150>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        c2c_fclk: c2c_fclk {
@@ -215,10 +210,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0138>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h12x2_ck: dpll_core_h12x2_ck {
@@ -226,10 +219,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x013c>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h13x2_ck: dpll_core_h13x2_ck {
@@ -237,10 +228,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0140>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h14x2_ck: dpll_core_h14x2_ck {
@@ -248,10 +237,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0144>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h22x2_ck: dpll_core_h22x2_ck {
@@ -259,10 +246,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0154>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h23x2_ck: dpll_core_h23x2_ck {
@@ -270,10 +255,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0158>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_h24x2_ck: dpll_core_h24x2_ck {
@@ -281,10 +264,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x015c>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_m2_ck: dpll_core_m2_ck {
@@ -292,10 +273,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0130>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_core_m3x2_ck: dpll_core_m3x2_ck {
@@ -303,10 +282,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_core_x2_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0134>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
@@ -335,10 +312,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_iva_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x01b8>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
@@ -346,10 +321,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_iva_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x01bc>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
@@ -372,10 +345,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_mpu_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0170>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        per_dpll_hs_clk_div: per_dpll_hs_clk_div {
@@ -642,10 +613,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0158>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_per_h12x2_ck: dpll_per_h12x2_ck {
@@ -653,10 +622,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x015c>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_per_h14x2_ck: dpll_per_h14x2_ck {
@@ -664,10 +631,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
                ti,max-div = <63>;
-                ti,autoidle-shift = <8>;
                reg = <0x0164>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_per_m2_ck: dpll_per_m2_ck {
@@ -675,10 +640,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0150>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_per_m2x2_ck: dpll_per_m2x2_ck {
@@ -686,10 +649,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0150>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_per_m3x2_ck: dpll_per_m3x2_ck {
@@ -697,10 +658,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_per_x2_ck>;
                ti,max-div = <31>;
-                ti,autoidle-shift = <8>;
                reg = <0x0154>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_unipro1_ck: dpll_unipro1_ck {
@@ -723,10 +682,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_unipro1_ck>;
                ti,max-div = <127>;
-                ti,autoidle-shift = <8>;
                reg = <0x0210>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_unipro2_ck: dpll_unipro2_ck {
@@ -749,10 +706,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_unipro2_ck>;
                ti,max-div = <127>;
-                ti,autoidle-shift = <8>;
                reg = <0x01d0>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        dpll_usb_ck: dpll_usb_ck {
@@ -775,10 +730,8 @@
                compatible = "ti,divider-clock";
                clocks = <&dpll_usb_ck>;
                ti,max-div = <127>;
-                ti,autoidle-shift = <8>;
                reg = <0x0190>;
                ti,index-starts-at-one;
-                ti,invert-autoidle-bit;
        };
        func_128m_clk: func_128m_clk {
@@ -851,6 +804,7 @@
                clocks = <&dpll_per_h12x2_ck>;
                ti,bit-shift = <8>;
                reg = <0x1420>;
+                ti,set-rate-parent;
        };
        dss_sys_clk: dss_sys_clk {
diff --git a/arch/arm/boot/dts/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
new file mode 100644
index 000000000000..c701e8d16bbb
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-lacie-d2-network.dts
@@ -0,0 +1,236 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "orion5x-mv88f5182.dtsi"
+/ {
+        model = "LaCie d2 Network";
+        compatible = "lacie,d2-network", "marvell,orion5x-88f5182", "marvell,orion5x";
+        memory {
+                reg = <0x00000000 0x4000000>; /* 64 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                linux,stdout-path = &uart0;
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+                         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+                         <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_buttons>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                front_button {
+                        label = "Front Push Button";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+                };
+                power_rocker_sw_on {
+                        label = "Power rocker switch (on|auto)";
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <1>; /* D2NET_SWITCH_POWER_ON */
+                        gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+                };
+                power_rocker_sw_off {
+                        label = "Power rocker switch (auto|off)";
+                        linux,input-type = <5>; /* EV_SW */
+                        linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */
+                        gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                pinctrl-0 = <&pmx_sata0_power &pmx_sata1_power>;
+                pinctrl-names = "default";
+                sata0_power: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "SATA0 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+                };
+                sata1_power: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "SATA1 Power";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        enable-active-high;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&devbus_bootcs {
+        status = "okay";
+        devbus,keep-config;
+        /*
+         * Currently the MTD code does not recognize the MX29LV400CBCT
+         * as a bottom-type device. This could cause risks of
+         * accidentally erasing critical flash sectors. We thus define
+         * a single, write-protected partition covering the whole
+         * flash.  TODO: once the flash part TOP/BOTTOM detection
+         * issue is sorted out in the MTD code, break this into at
+         * least three partitions: 'u-boot code', 'u-boot environment'
+         * and 'whatever is left'.
+         */
+        flash@0 {
+                compatible = "cfi-flash";
+                reg = <0 0x80000>;
+                bank-width = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "Full512Kb";
+                        reg = <0 0x80000>;
+                        read-only;
+                };
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy: ethernet-phy {
+                reg = <8>;
+        };
+};
+&ehci0 {
+        status = "okay";
+};
+&eth {
+        status = "okay";
+        ethernet-port@0 {
+                phy-handle = <&ethphy>;
+        };
+};
+&i2c {
+        status = "okay";
+        clock-frequency = <100000>;
+        #address-cells = <1>;
+        rtc@32 {
+                compatible = "ricoh,rs5c372b";
+                reg = <0x32>;
+        };
+        fan@3e {
+                compatible = "gmt,g762";
+                reg = <0x3e>;
+                /* Not enough HW info */
+                status = "disabled";
+        };
+        eeprom@50 {
+                compatible = "atmel,24c08";
+                reg = <0x50>;
+        };
+};
+&pinctrl {
+        pinctrl-0 = <&pmx_leds &pmx_board_id &pmx_fan_fail>;
+        pinctrl-names = "default";
+        pmx_board_id: pmx-board-id {
+                marvell,pins = "mpp0", "mpp1", "mpp2";
+                marvell,function = "gpio";
+        };
+        pmx_buttons: pmx-buttons {
+                marvell,pins = "mpp8", "mpp9", "mpp18";
+                marvell,function = "gpio";
+        };
+        pmx_fan_fail: pmx-fan-fail {
+                marvell,pins = "mpp5";
+                marvell,function = "gpio";
+        };
+        /*
+         * MPP6: Red front LED
+         * MPP16: Blue front LED blink control
+         */
+        pmx_leds: pmx-leds {
+                marvell,pins = "mpp6", "mpp16";
+                marvell,function = "gpio";
+        };
+        pmx_sata0_led_active: pmx-sata0-led-active {
+                marvell,pins = "mpp14";
+                marvell,function = "sata0";
+        };
+        pmx_sata0_power: pmx-sata0-power {
+                marvell,pins = "mpp3";
+                marvell,function = "gpio";
+        };
+        pmx_sata1_led_active: pmx-sata1-led-active {
+                marvell,pins = "mpp15";
+                marvell,function = "sata1";
+        };
+        pmx_sata1_power: pmx-sata1-power {
+                marvell,pins = "mpp12";
+                marvell,function = "gpio";
+        };
+        /*
+         * Non MPP GPIOs:
+         *  GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
+         *  GPIO 23: Blue front LED off
+         *  GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
+         */
+};
+&sata {
+        pinctrl-0 = <&pmx_sata0_led_active
+                     &pmx_sata1_led_active>;
+        pinctrl-names = "default";
+        status = "okay";
+        nr-ports = <2>;
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 5ed6c1376901..89ff404a528c 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -6,8 +6,19 @@
 * warranty of any kind, whether express or implied.
 */
+/*
+ * TODO: add Orion USB device port init when kernel.org support is added.
+ * TODO: add flash write support: see below.
+ * TODO: add power-off support.
+ * TODO: add I2C EEPROM support.
+ */
 /dts-v1/;
-/include/ "orion5x.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "orion5x-mv88f5182.dtsi"
 / {
        model = "LaCie Ethernet Disk mini V2";
@@ -19,49 +30,84 @@
        chosen {
                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                linux,stdout-path = &uart0;
        };
-        ocp@f1000000 {
+        soc {
-                serial@12000 {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
-                        clock-frequency = <166666667>;
+                         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
-                        status = "okay";
+                         <MBUS_ID(0x01, 0x0f) 0 0xfff80000 0x80000>;
-                };
-                sata@80000 {
-                        status = "okay";
-                        nr-ports = <2>;
-                };
        };
-        gpio_keys {
+        gpio-keys {
                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_power_button>;
+                pinctrl-names = "default";
                #address-cells = <1>;
                #size-cells = <0>;
                button@1 {
                        label = "Power-on Switch";
-                        linux,code = <116>; /* KEY_POWER */
+                        linux,code = <KEY_POWER>;
-                        gpios = <&gpio0 18 0>;
+                        gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
                };
        };
-        gpio_leds {
+        gpio-leds {
                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_power_led>;
+                pinctrl-names = "default";
                led@1 {
                        label = "power:blue";
-                        gpios = <&gpio0 16 1>;
+                        gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
                };
        };
 };
-&mdio {
+&devbus_bootcs {
        status = "okay";
-        ethphy: ethernet-phy {
+        /* Read parameters */
-                reg = <8>;
+        devbus,bus-width    = <8>;
+        devbus,turn-off-ps  = <90000>;
+        devbus,badr-skew-ps = <0>;
+        devbus,acc-first-ps = <186000>;
+        devbus,acc-next-ps  = <186000>;
+        /* Write parameters */
+        devbus,wr-high-ps  = <90000>;
+        devbus,wr-low-ps   = <90000>;
+        devbus,ale-wr-ps   = <90000>;
+        /*
+         * Currently the MTD code does not recognize the MX29LV400CBCT
+         * as a bottom-type device. This could cause risks of
+         * accidentally erasing critical flash sectors. We thus define
+         * a single, write-protected partition covering the whole
+         * flash.  TODO: once the flash part TOP/BOTTOM detection
+         * issue is sorted out in the MTD code, break this into at
+         * least three partitions: 'u-boot code', 'u-boot environment'
+         * and 'whatever is left'.
+         */
+        flash@0 {
+                compatible = "cfi-flash";
+                reg = <0 0x80000>;
+                bank-width = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                partition@0 {
+                        label = "Full512Kb";
+                        reg = <0 0x80000>;
+                        read-only;
+                };
        };
 };
+&ehci0 {
+        status = "okay";
+};
 &eth {
        status = "okay";
@@ -69,3 +115,60 @@
                phy-handle = <&ethphy>;
        };
 };
+&i2c {
+        status = "okay";
+        clock-frequency = <100000>;
+        #address-cells = <1>;
+        rtc@32 {
+                compatible = "ricoh,rs5c372a";
+                reg = <0x32>;
+                interrupt-parent = <&gpio0>;
+                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy: ethernet-phy {
+                reg = <8>;
+        };
+};
+&pinctrl {
+        pinctrl-0 = <&pmx_rtc &pmx_power_led_ctrl>;
+        pinctrl-names = "default";
+        pmx_power_button: pmx-power-button {
+                marvell,pins = "mpp18";
+                marvell,function = "gpio";
+        };
+        pmx_power_led: pmx-power-led {
+                marvell,pins = "mpp16";
+                marvell,function = "gpio";
+        };
+        pmx_power_led_ctrl: pmx-power-led-ctrl {
+                marvell,pins = "mpp17";
+                marvell,function = "gpio";
+        };
+        pmx_rtc: pmx-rtc {
+                marvell,pins = "mpp3";
+                marvell,function = "gpio";
+        };
+};
+&sata {
+        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+        pinctrl-names = "default";
+        status = "okay";
+        nr-ports = <2>;
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
new file mode 100644
index 000000000000..ff3484904294
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-maxtor-shared-storage-2.dts
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Copyright (C) Sylver Bruneau <sylver.bruneau@googlemail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "orion5x-mv88f5182.dtsi"
+/ {
+        model = "Maxtor Shared Storage II";
+        compatible = "maxtor,shared-storage-2", "marvell,orion5x-88f5182", "marvell,orion5x";
+        memory {
+                reg = <0x00000000 0x4000000>; /* 64 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                linux,stdout-path = &uart0;
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+                         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+                         <MBUS_ID(0x01, 0x0f) 0 0xff800000 0x40000>;
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                pinctrl-0 = <&pmx_buttons>;
+                pinctrl-names = "default";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                power {
+                        label = "Power";
+                        linux,code = <KEY_POWER>;
+                        gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
+                };
+                reset {
+                        label = "Reset";
+                        linux,code = <KEY_RESTART>;
+                        gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
+                };
+        };
+};
+&devbus_bootcs {
+        status = "okay";
+        devbus,keep-config;
+        /*
+         * Currently the MTD code does not recognize the MX29LV400CBCT
+         * as a bottom-type device. This could cause risks of
+         * accidentally erasing critical flash sectors. We thus define
+         * a single, write-protected partition covering the whole
+         * flash.  TODO: once the flash part TOP/BOTTOM detection
+         * issue is sorted out in the MTD code, break this into at
+         * least three partitions: 'u-boot code', 'u-boot environment'
+         * and 'whatever is left'.
+         */
+        flash@0 {
+                compatible = "cfi-flash";
+                reg = <0 0x40000>;
+                bank-width = <1>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy: ethernet-phy {
+                reg = <8>;
+        };
+};
+&ehci0 {
+        status = "okay";
+};
+&eth {
+        status = "okay";
+        ethernet-port@0 {
+                phy-handle = <&ethphy>;
+        };
+};
+&i2c {
+        status = "okay";
+        clock-frequency = <100000>;
+        #address-cells = <1>;
+        rtc@68 {
+                compatible = "st,m41t81";
+                reg = <0x68>;
+                pinctrl-0 = <&pmx_rtc>;
+                pinctrl-names = "default";
+                interrupt-parent = <&gpio0>;
+                interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+        };
+};
+&pinctrl {
+        pinctrl-0 = <&pmx_leds &pmx_misc>;
+        pinctrl-names = "default";
+        pmx_buttons: pmx-buttons {
+                marvell,pins = "mpp11", "mpp12";
+                marvell,function = "gpio";
+        };
+        /*
+         * MPP0: Power LED
+         * MPP1: Error LED
+         */
+        pmx_leds: pmx-leds {
+                marvell,pins = "mpp0", "mpp1";
+                marvell,function = "gpio";
+        };
+        /*
+         * MPP4: HDD ind. (Single/Dual)
+         * MPP5: HD0 5V control
+         * MPP6: HD0 12V control
+         * MPP7: HD1 5V control
+         * MPP8: HD1 12V control
+         */
+        pmx_misc: pmx-misc {
+                marvell,pins = "mpp4", "mpp5", "mpp6", "mpp7", "mpp8", "mpp10";
+                marvell,function = "gpio";
+        };
+        pmx_rtc: pmx-rtc {
+                marvell,pins = "mpp3";
+                marvell,function = "gpio";
+        };
+        pmx_sata0_led_active: pmx-sata0-led-active {
+                marvell,pins = "mpp14";
+                marvell,function = "sata0";
+        };
+        pmx_sata1_led_active: pmx-sata1-led-active {
+                marvell,pins = "mpp15";
+                marvell,function = "sata1";
+        };
+        /*
+         * Non MPP GPIOs:
+         *  GPIO 22: USB port 1 fuse (0 = Fail, 1 = Ok)
+         *  GPIO 23: Blue front LED off
+         *  GPIO 24: Inhibit board power off (0 = Disabled, 1 = Enabled)
+         */
+};
+&sata {
+        pinctrl-0 = <&pmx_sata0_led_active
+                     &pmx_sata1_led_active>;
+        pinctrl-names = "default";
+        status = "okay";
+        nr-ports = <2>;
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/orion5x-mv88f5182.dtsi b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
new file mode 100644
index 000000000000..d1ed71c60209
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-mv88f5182.dtsi
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include "orion5x.dtsi"
+/ {
+        compatible = "marvell,orion5x-88f5182", "marvell,orion5x";
+        soc {
+                compatible = "marvell,orion5x-88f5182-mbus", "simple-bus";
+                internal-regs {
+                        pinctrl: pinctrl@10000 {
+                                compatible = "marvell,88f5182-pinctrl";
+                                reg = <0x10000 0x8>, <0x10050 0x4>;
+                                pmx_sata0: pmx-sata0 {
+                                        marvell,pins = "mpp12", "mpp14";
+                                        marvell,function = "sata0";
+                                };
+                                pmx_sata1: pmx-sata1 {
+                                        marvell,pins = "mpp13", "mpp15";
+                                        marvell,function = "sata1";
+                                };
+                        };
+                        core_clk: core-clocks@10030 {
+                                compatible = "marvell,mv88f5182-core-clock";
+                                reg = <0x10010 0x4>;
+                                #clock-cells = <1>;
+                        };
+                        mbusc: mbus-controller@20000 {
+                                compatible = "marvell,mbus-controller";
+                                reg = <0x20000 0x100>, <0x1500 0x20>;
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
new file mode 100644
index 000000000000..6fb052507b36
--- /dev/null
+++ b/arch/arm/boot/dts/orion5x-rd88f5182-nas.dts
@@ -0,0 +1,177 @@
+/*
+ * Copyright (C) 2014 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include "orion5x-mv88f5182.dtsi"
+/ {
+        model = "Marvell Reference Design 88F5182 NAS";
+        compatible = "marvell,rd-88f5182-nas", "marvell,orion5x-88f5182", "marvell,orion5x";
+        memory {
+                reg = <0x00000000 0x4000000>; /* 64 MB */
+        };
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+                linux,stdout-path = &uart0;
+        };
+        soc {
+                ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>,
+                         <MBUS_ID(0x09, 0x00) 0 0xf2200000 0x800>,
+                         <MBUS_ID(0x01, 0x0f) 0 0xf4000000 0x80000>,
+                         <MBUS_ID(0x01, 0x1d) 0 0xfc000000 0x1000000>;
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+                pinctrl-0 = <&pmx_debug_led>;
+                pinctrl-names = "default";
+                led@0 {
+                        label = "rd88f5182:cpu";
+                        linux,default-trigger = "heartbeat";
+                        gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
+                };
+        };
+};
+&devbus_bootcs {
+        status = "okay";
+        /* Read parameters */
+        devbus,bus-width    = <8>;
+        devbus,turn-off-ps  = <90000>;
+        devbus,badr-skew-ps = <0>;
+        devbus,acc-first-ps = <186000>;
+        devbus,acc-next-ps  = <186000>;
+        /* Write parameters */
+        devbus,wr-high-ps  = <90000>;
+        devbus,wr-low-ps   = <90000>;
+        devbus,ale-wr-ps   = <90000>;
+        flash@0 {
+                compatible = "cfi-flash";
+                reg = <0 0x80000>;
+                bank-width = <1>;
+        };
+};
+&devbus_cs1 {
+        status = "okay";
+        /* Read parameters */
+        devbus,bus-width    = <8>;
+        devbus,turn-off-ps  = <90000>;
+        devbus,badr-skew-ps = <0>;
+        devbus,acc-first-ps = <186000>;
+        devbus,acc-next-ps  = <186000>;
+        /* Write parameters */
+        devbus,wr-high-ps  = <90000>;
+        devbus,wr-low-ps   = <90000>;
+        devbus,ale-wr-ps   = <90000>;
+        flash@0 {
+                compatible = "cfi-flash";
+                reg = <0 0x1000000>;
+                bank-width = <1>;
+        };
+};
+&ehci0 {
+        status = "okay";
+};
+&ehci1 {
+        status = "okay";
+};
+&eth {
+        status = "okay";
+        ethernet-port@0 {
+                phy-handle = <&ethphy>;
+        };
+};
+&i2c {
+        status = "okay";
+        clock-frequency = <100000>;
+        #address-cells = <1>;
+        rtc@68 {
+                pinctrl-0 = <&pmx_rtc>;
+                pinctrl-names = "default";
+                compatible = "dallas,ds1338";
+                reg = <0x68>;
+        };
+};
+&mdio {
+        status = "okay";
+        ethphy: ethernet-phy {
+                reg = <8>;
+        };
+};
+&pinctrl {
+        pinctrl-0 = <&pmx_reset_switch &pmx_misc_gpios
+                &pmx_pci_gpios>;
+        pinctrl-names = "default";
+        /*
+         * MPP[20] PCI Clock to MV88F5182
+         * MPP[21] PCI Clock to mini PCI CON11
+         * MPP[22] USB 0 over current indication
+         * MPP[23] USB 1 over current indication
+         * MPP[24] USB 1 over current enable
+         * MPP[25] USB 0 over current enable
+         */
+        pmx_debug_led: pmx-debug_led {
+                marvell,pins = "mpp0";
+                marvell,function = "gpio";
+        };
+        pmx_reset_switch: pmx-reset-switch {
+                marvell,pins = "mpp1";
+                marvell,function = "gpio";
+        };
+        pmx_rtc: pmx-rtc {
+                marvell,pins = "mpp3";
+                marvell,function = "gpio";
+        };
+        pmx_misc_gpios: pmx-misc-gpios {
+                marvell,pins = "mpp4", "mpp5";
+                marvell,function = "gpio";
+        };
+        pmx_pci_gpios: pmx-pci-gpios {
+                marvell,pins = "mpp6", "mpp7";
+                marvell,function = "gpio";
+        };
+};
+&sata {
+        pinctrl-0 = <&pmx_sata0 &pmx_sata1>;
+        pinctrl-names = "default";
+        status = "okay";
+        nr-ports = <2>;
+};
+&uart0 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 174d89241f70..75cd01bd6024 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -6,7 +6,9 @@
 * warranty of any kind, whether express or implied.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
 / {
        model = "Marvell Orion5x SoC";
@@ -17,149 +19,214 @@
                gpio0 = &gpio0;
        };
-        intc: interrupt-controller {
+        soc {
-                compatible = "marvell,orion-intc";
+                #address-cells = <2>;
-                interrupt-controller;
-                #interrupt-cells = <1>;
-                reg = <0xf1020200 0x08>;
-        };
-        ocp@f1000000 {
-                compatible = "simple-bus";
-                ranges = <0x00000000 0xf1000000 0x4000000
-                          0xf2200000 0xf2200000 0x0000800>;
-                #address-cells = <1>;
                #size-cells = <1>;
+                controller = <&mbusc>;
-                gpio0: gpio@10100 {
+                devbus_bootcs: devbus-bootcs {
-                        compatible = "marvell,orion-gpio";
+                        compatible = "marvell,orion-devbus";
-                        #gpio-cells = <2>;
+                        reg = <MBUS_ID(0xf0, 0x01) 0x1046C 0x4>;
-                        gpio-controller;
+                        ranges = <0 MBUS_ID(0x01, 0x0f) 0 0xffffffff>;
-                        reg = <0x10100 0x40>;
-                        ngpios = <32>;
-                        interrupt-controller;
-                        #interrupt-cells = <2>;
-                        interrupts = <6>, <7>, <8>, <9>;
-                };
-                spi@10600 {
-                        compatible = "marvell,orion-spi";
                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
-                        cell-index = <0>;
+                        clocks = <&core_clk 0>;
-                        reg = <0x10600 0x28>;
                        status = "disabled";
                };
-                i2c@11000 {
+                devbus_cs0: devbus-cs0 {
-                        compatible = "marvell,mv64xxx-i2c";
+                        compatible = "marvell,orion-devbus";
-                        reg = <0x11000 0x20>;
+                        reg = <MBUS_ID(0xf0, 0x01) 0x1045C 0x4>;
+                        ranges = <0 MBUS_ID(0x01, 0x1e) 0 0xffffffff>;
                        #address-cells = <1>;
-                        #size-cells = <0>;
+                        #size-cells = <1>;
-                        interrupts = <5>;
+                        clocks = <&core_clk 0>;
-                        clock-frequency = <100000>;
                        status = "disabled";
                };
-                serial@12000 {
+                devbus_cs1: devbus-cs1 {
-                        compatible = "ns16550a";
+                        compatible = "marvell,orion-devbus";
-                        reg = <0x12000 0x100>;
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10460 0x4>;
-                        reg-shift = <2>;
+                        ranges = <0 MBUS_ID(0x01, 0x1d) 0 0xffffffff>;
-                        interrupts = <3>;
+                        #address-cells = <1>;
-                        /* set clock-frequency in board dts */
+                        #size-cells = <1>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
-                serial@12100 {
+                devbus_cs2: devbus-cs2 {
-                        compatible = "ns16550a";
+                        compatible = "marvell,orion-devbus";
-                        reg = <0x12100 0x100>;
+                        reg = <MBUS_ID(0xf0, 0x01) 0x10464 0x4>;
-                        reg-shift = <2>;
+                        ranges = <0 MBUS_ID(0x01, 0x1b) 0 0xffffffff>;
-                        interrupts = <4>;
+                        #address-cells = <1>;
-                        /* set clock-frequency in board dts */
+                        #size-cells = <1>;
+                        clocks = <&core_clk 0>;
                        status = "disabled";
                };
-                wdt@20300 {
+                internal-regs {
-                        compatible = "marvell,orion-wdt";
+                        compatible = "simple-bus";
-                        reg = <0x20300 0x28>;
+                        #address-cells = <1>;
-                        status = "okay";
+                        #size-cells = <1>;
-                };
+                        ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
+                        gpio0: gpio@10100 {
+                                compatible = "marvell,orion-gpio";
+                                #gpio-cells = <2>;
+                                gpio-controller;
+                                reg = <0x10100 0x40>;
+                                ngpios = <32>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <6>, <7>, <8>, <9>;
+                        };
-                ehci@50000 {
+                        spi: spi@10600 {
-                        compatible = "marvell,orion-ehci";
+                                compatible = "marvell,orion-spi";
-                        reg = <0x50000 0x1000>;
+                                #address-cells = <1>;
-                        interrupts = <17>;
+                                #size-cells = <0>;
-                        status = "disabled";
+                                cell-index = <0>;
-                };
+                                reg = <0x10600 0x28>;
+                                status = "disabled";
+                        };
-                xor@60900 {
+                        i2c: i2c@11000 {
-                        compatible = "marvell,orion-xor";
+                                compatible = "marvell,mv64xxx-i2c";
-                        reg = <0x60900 0x100
+                                reg = <0x11000 0x20>;
-                               0x60b00 0x100>;
+                                #address-cells = <1>;
-                        status = "okay";
+                                #size-cells = <0>;
+                                interrupts = <5>;
+                                clocks = <&core_clk 0>;
+                                status = "disabled";
+                        };
-                        xor00 {
+                        uart0: serial@12000 {
-                              interrupts = <30>;
+                                compatible = "ns16550a";
-                              dmacap,memcpy;
+                                reg = <0x12000 0x100>;
-                              dmacap,xor;
+                                reg-shift = <2>;
+                                interrupts = <3>;
+                                clocks = <&core_clk 0>;
+                                status = "disabled";
                        };
-                        xor01 {
-                              interrupts = <31>;
+                        uart1: serial@12100 {
-                              dmacap,memcpy;
+                                compatible = "ns16550a";
-                              dmacap,xor;
+                                reg = <0x12100 0x100>;
-                              dmacap,memset;
+                                reg-shift = <2>;
+                                interrupts = <4>;
+                                clocks = <&core_clk 0>;
+                                status = "disabled";
                        };
-                };
-                eth: ethernet-controller@72000 {
+                        bridge_intc: bridge-interrupt-ctrl@20110 {
-                        compatible = "marvell,orion-eth";
+                                compatible = "marvell,orion-bridge-intc";
-                        #address-cells = <1>;
+                                interrupt-controller;
-                        #size-cells = <0>;
+                                #interrupt-cells = <1>;
-                        reg = <0x72000 0x4000>;
+                                reg = <0x20110 0x8>;
-                        marvell,tx-checksum-limit = <1600>;
+                                interrupts = <0>;
-                        status = "disabled";
+                                marvell,#interrupts = <4>;
+                        };
-                        ethernet-port@0 {
+                        intc: interrupt-controller@20200 {
-                                compatible = "marvell,orion-eth-port";
+                                compatible = "marvell,orion-intc";
-                                reg = <0>;
+                                interrupt-controller;
-                                /* overwrite MAC address in bootloader */
+                                #interrupt-cells = <1>;
-                                local-mac-address = [00 00 00 00 00 00];
+                                reg = <0x20200 0x08>;
-                                /* set phy-handle property in board file */
                        };
-                };
-                mdio: mdio-bus@72004 {
+                        timer: timer@20300 {
-                        compatible = "marvell,orion-mdio";
+                                compatible = "marvell,orion-timer";
-                        #address-cells = <1>;
+                                reg = <0x20300 0x20>;
-                        #size-cells = <0>;
+                                interrupt-parent = <&bridge_intc>;
-                        reg = <0x72004 0x84>;
+                                interrupts = <1>, <2>;
-                        interrupts = <22>;
+                                clocks = <&core_clk 0>;
-                        status = "disabled";
+                        };
-                        /* add phy nodes in board file */
+                        wdt: wdt@20300 {
-                };
+                                compatible = "marvell,orion-wdt";
+                                reg = <0x20300 0x28>;
+                                interrupt-parent = <&bridge_intc>;
+                                interrupts = <3>;
+                                status = "okay";
+                        };
-                sata@80000 {
+                        ehci0: ehci@50000 {
-                        compatible = "marvell,orion-sata";
+                                compatible = "marvell,orion-ehci";
-                        reg = <0x80000 0x5000>;
+                                reg = <0x50000 0x1000>;
-                        interrupts = <29>;
+                                interrupts = <17>;
-                        status = "disabled";
+                                status = "disabled";
+                        };
+                        xor: dma-controller@60900 {
+                                compatible = "marvell,orion-xor";
+                                reg = <0x60900 0x100
+                                       0x60b00 0x100>;
+                                status = "okay";
+                                xor00 {
+                                      interrupts = <30>;
+                                      dmacap,memcpy;
+                                      dmacap,xor;
+                                };
+                                xor01 {
+                                      interrupts = <31>;
+                                      dmacap,memcpy;
+                                      dmacap,xor;
+                                      dmacap,memset;
+                                };
+                        };
+                        eth: ethernet-controller@72000 {
+                                compatible = "marvell,orion-eth";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72000 0x4000>;
+                                marvell,tx-checksum-limit = <1600>;
+                                status = "disabled";
+                                ethport: ethernet-port@0 {
+                                        compatible = "marvell,orion-eth-port";
+                                        reg = <0>;
+                                        interrupts = <21>;
+                                        /* overwrite MAC address in bootloader */
+                                        local-mac-address = [00 00 00 00 00 00];
+                                        /* set phy-handle property in board file */
+                                };
+                        };
+                        mdio: mdio-bus@72004 {
+                                compatible = "marvell,orion-mdio";
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                reg = <0x72004 0x84>;
+                                interrupts = <22>;
+                                status = "disabled";
+                                /* add phy nodes in board file */
+                        };
+                        sata: sata@80000 {
+                                compatible = "marvell,orion-sata";
+                                reg = <0x80000 0x5000>;
+                                interrupts = <29>;
+                                status = "disabled";
+                        };
+                        ehci1: ehci@a0000 {
+                                compatible = "marvell,orion-ehci";
+                                reg = <0xa0000 0x1000>;
+                                interrupts = <12>;
+                                status = "disabled";
+                        };
                };
-                crypto@90000 {
+                cesa: crypto@90000 {
                        compatible = "marvell,orion-crypto";
-                        reg = <0x90000 0x10000>,
+                        reg = <MBUS_ID(0xf0, 0x01) 0x90000 0x10000>,
-                              <0xf2200000 0x800>;
+                              <MBUS_ID(0x09, 0x00) 0x0 0x800>;
                        reg-names = "regs", "sram";
                        interrupts = <28>;
                        status = "okay";
                };
-                ehci@a0000 {
-                        compatible = "marvell,orion-ehci";
-                        reg = <0xa0000 0x1000>;
-                        interrupts = <12>;
-                        status = "disabled";
-                };
        };
 };
diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi
index 1e82571d6823..963b7e54ab15 100644
--- a/arch/arm/boot/dts/prima2.dtsi
+++ b/arch/arm/boot/dts/prima2.dtsi
@@ -48,7 +48,7 @@
                ranges = <0x40000000 0x40000000 0x80000000>;
                l2-cache-controller@80040000 {
-                        compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
+                        compatible = "arm,pl310-cache";
                        reg = <0x80040000 0x1000>;
                        interrupts = <59>;
                        arm,tag-latency = <1 1 1>;
@@ -201,6 +201,7 @@
                                compatible = "sirf,prima2-tick";
                                reg = <0xb0020000 0x1000>;
                                interrupts = <0>;
+                                clocks = <&clks 11>;
                        };
                        nand@b0030000 {
@@ -313,8 +314,9 @@
                                reg = <0xb00d0000 0x10000>;
                                interrupts = <15>;
                                sirf,spi-num-chipselects = <1>;
-                                sirf,spi-dma-rx-channel = <25>;
+                                dmas = <&dmac1 9>,
-                                sirf,spi-dma-tx-channel = <20>;
+                                     <&dmac1 4>;
+                                dma-names = "rx", "tx";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 19>;
@@ -327,8 +329,9 @@
                                reg = <0xb0170000 0x10000>;
                                interrupts = <16>;
                                sirf,spi-num-chipselects = <1>;
-                                sirf,spi-dma-rx-channel = <12>;
+                                dmas = <&dmac0 12>,
-                                sirf,spi-dma-tx-channel = <13>;
+                                     <&dmac0 13>;
+                                dma-names = "rx", "tx";
                                #address-cells = <1>;
                                #size-cells = <0>;
                                clocks = <&clks 20>;
diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
new file mode 100644
index 000000000000..7c2441d526bc
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts
@@ -0,0 +1,16 @@
+#include "qcom-apq8064-v2.0.dtsi"
+/ {
+        model = "Qualcomm APQ8064/IFC6410";
+        compatible = "qcom,apq8064-ifc6410", "qcom,apq8064";
+        soc {
+                gsbi@16600000 {
+                        status = "ok";
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+                        serial@16640000 {
+                                status = "ok";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
new file mode 100644
index 000000000000..935c3945fc5e
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064-v2.0.dtsi
@@ -0,0 +1 @@
+#include "qcom-apq8064.dtsi"
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
new file mode 100644
index 000000000000..92bf793622c3
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -0,0 +1,170 @@
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
+/ {
+        model = "Qualcomm APQ8064";
+        compatible = "qcom,apq8064";
+        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <0>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc0>;
+                        qcom,saw = <&saw0>;
+                };
+                cpu@1 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <1>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc1>;
+                        qcom,saw = <&saw1>;
+                };
+                cpu@2 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <2>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc2>;
+                        qcom,saw = <&saw2>;
+                };
+                cpu@3 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
+                        device_type = "cpu";
+                        reg = <3>;
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc3>;
+                        qcom,saw = <&saw3>;
+                };
+                L2: l2-cache {
+                        compatible = "cache";
+                        cache-level = <2>;
+                };
+        };
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 10 0x304>;
+        };
+        soc: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+                intc: interrupt-controller@2000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x02000000 0x1000>,
+                              <0x02002000 0x1000>;
+                };
+                timer@200a000 {
+                        compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                        interrupts = <1 1 0x301>,
+                                     <1 2 0x301>,
+                                     <1 3 0x301>;
+                        reg = <0x0200a000 0x100>;
+                        clock-frequency = <27000000>,
+                                          <32768>;
+                        cpu-offset = <0x80000>;
+                };
+                acc0: clock-controller@2088000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+                };
+                acc1: clock-controller@2098000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+                };
+                acc2: clock-controller@20a8000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
+                };
+                acc3: clock-controller@20b8000 {
+                        compatible = "qcom,kpss-acc-v1";
+                        reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
+                };
+                saw0: regulator@2089000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+                saw1: regulator@2099000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+                saw2: regulator@20a9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+                saw3: regulator@20b9000 {
+                        compatible = "qcom,saw2";
+                        reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
+                        regulator;
+                };
+                gsbi7: gsbi@16600000 {
+                        status = "disabled";
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x16600000 0x100>;
+                        clocks = <&gcc GSBI7_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        serial@16640000 {
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                                reg = <0x16640000 0x1000>,
+                                      <0x16600000 0x1000>;
+                                interrupts = <0 158 0x0>;
+                                clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+                };
+                qcom,ssbi@500000 {
+                        compatible = "qcom,ssbi";
+                        reg = <0x00500000 0x1000>;
+                        qcom,controller-type = "pmic-arbiter";
+                };
+                gcc: clock-controller@900000 {
+                        compatible = "qcom,gcc-apq8064";
+                        reg = <0x00900000 0x4000>;
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
index 13ac3e222495..b4dfb01fe6fb 100644
--- a/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
+++ b/arch/arm/boot/dts/qcom-apq8074-dragonboard.dts
@@ -3,4 +3,43 @@
 / {
        model = "Qualcomm APQ8074 Dragonboard";
        compatible = "qcom,apq8074-dragonboard", "qcom,apq8074";
+        soc {
+                serial@f991e000 {
+                        status = "ok";
+                };
+                sdhci@f9824900 {
+                        bus-width = <8>;
+                        non-removable;
+                        status = "ok";
+                };
+                sdhci@f98a4900 {
+                        cd-gpios = <&msmgpio 62 0x1>;
+                        bus-width = <4>;
+                };
+                pinctrl@fd510000 {
+                        spi8_default: spi8_default {
+                                mosi {
+                                        pins = "gpio45";
+                                        function = "blsp_spi8";
+                                };
+                                miso {
+                                        pins = "gpio46";
+                                        function = "blsp_spi8";
+                                };
+                                cs {
+                                        pins = "gpio47";
+                                        function = "blsp_spi8";
+                                };
+                                clk {
+                                        pins = "gpio48";
+                                        function = "blsp_spi8";
+                                };
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-apq8084-mtp.dts b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
new file mode 100644
index 000000000000..9dae3878b71d
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084-mtp.dts
@@ -0,0 +1,6 @@
+#include "qcom-apq8084.dtsi"
+/ {
+        model = "Qualcomm APQ 8084-MTP";
+        compatible = "qcom,apq8084-mtp", "qcom,apq8084";
+};
diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi
new file mode 100644
index 000000000000..e3e009a5912b
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-apq8084.dtsi
@@ -0,0 +1,179 @@
+/dts-v1/;
+#include "skeleton.dtsi"
+/ {
+        model = "Qualcomm APQ 8084";
+        compatible = "qcom,apq8084";
+        interrupt-parent = <&intc>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "qcom,krait";
+                        reg = <0>;
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "qcom,krait";
+                        reg = <1>;
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc1>;
+                };
+                cpu@2 {
+                        device_type = "cpu";
+                        compatible = "qcom,krait";
+                        reg = <2>;
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc2>;
+                };
+                cpu@3 {
+                        device_type = "cpu";
+                        compatible = "qcom,krait";
+                        reg = <3>;
+                        enable-method = "qcom,kpss-acc-v2";
+                        next-level-cache = <&L2>;
+                        qcom,acc = <&acc3>;
+                };
+                L2: l2-cache {
+                        compatible = "qcom,arch-cache";
+                        cache-level = <2>;
+                        qcom,saw = <&saw_l2>;
+                };
+        };
+        cpu-pmu {
+                compatible = "qcom,krait-pmu";
+                interrupts = <1 7 0xf04>;
+        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 2 0xf08>,
+                             <1 3 0xf08>,
+                             <1 4 0xf08>,
+                             <1 1 0xf08>;
+                clock-frequency = <19200000>;
+        };
+        soc: soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                compatible = "simple-bus";
+                intc: interrupt-controller@f9000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0xf9000000 0x1000>,
+                              <0xf9002000 0x1000>;
+                };
+                timer@f9020000 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
+                        compatible = "arm,armv7-timer-mem";
+                        reg = <0xf9020000 0x1000>;
+                        clock-frequency = <19200000>;
+                        frame@f9021000 {
+                                frame-number = <0>;
+                                interrupts = <0 8 0x4>,
+                                             <0 7 0x4>;
+                                reg = <0xf9021000 0x1000>,
+                                      <0xf9022000 0x1000>;
+                        };
+                        frame@f9023000 {
+                                frame-number = <1>;
+                                interrupts = <0 9 0x4>;
+                                reg = <0xf9023000 0x1000>;
+                                status = "disabled";
+                        };
+                        frame@f9024000 {
+                                frame-number = <2>;
+                                interrupts = <0 10 0x4>;
+                                reg = <0xf9024000 0x1000>;
+                                status = "disabled";
+                        };
+                        frame@f9025000 {
+                                frame-number = <3>;
+                                interrupts = <0 11 0x4>;
+                                reg = <0xf9025000 0x1000>;
+                                status = "disabled";
+                        };
+                        frame@f9026000 {
+                                frame-number = <4>;
+                                interrupts = <0 12 0x4>;
+                                reg = <0xf9026000 0x1000>;
+                                status = "disabled";
+                        };
+                        frame@f9027000 {
+                                frame-number = <5>;
+                                interrupts = <0 13 0x4>;
+                                reg = <0xf9027000 0x1000>;
+                                status = "disabled";
+                        };
+                        frame@f9028000 {
+                                frame-number = <6>;
+                                interrupts = <0 14 0x4>;
+                                reg = <0xf9028000 0x1000>;
+                                status = "disabled";
+                        };
+                };
+                saw_l2: regulator@f9012000 {
+                        compatible = "qcom,saw2";
+                        reg = <0xf9012000 0x1000>;
+                        regulator;
+                };
+                acc0: clock-controller@f9088000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf9088000 0x1000>,
+                              <0xf9008000 0x1000>;
+                };
+                acc1: clock-controller@f9098000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf9098000 0x1000>,
+                              <0xf9008000 0x1000>;
+                };
+                acc2: clock-controller@f90a8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf90a8000 0x1000>,
+                              <0xf9008000 0x1000>;
+                };
+                acc3: clock-controller@f90b8000 {
+                        compatible = "qcom,kpss-acc-v2";
+                        reg = <0xf90b8000 0x1000>,
+                              <0xf9008000 0x1000>;
+                };
+                restart@fc4ab000 {
+                        compatible = "qcom,pshold";
+                        reg = <0xfc4ab000 0x4>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
index 169bad90dac9..45180adfadf1 100644
--- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
+++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
@@ -3,4 +3,14 @@
 / {
        model = "Qualcomm MSM8660 SURF";
        compatible = "qcom,msm8660-surf", "qcom,msm8660";
+        soc {
+                gsbi@19c00000 {
+                        status = "ok";
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+                        serial@19c40000 {
+                                status = "ok";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index c52a9e964a44..53837aaa2f72 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -3,6 +3,7 @@
 /include/ "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 / {
        model = "Qualcomm MSM8660";
@@ -12,16 +13,18 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "qcom,scorpion";
-                enable-method = "qcom,gcc-msm8660";
                cpu@0 {
+                        compatible = "qcom,scorpion";
+                        enable-method = "qcom,gcc-msm8660";
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
                };
                cpu@1 {
+                        compatible = "qcom,scorpion";
+                        enable-method = "qcom,gcc-msm8660";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
@@ -33,55 +36,73 @@
                };
        };
-        intc: interrupt-controller@2080000 {
+        soc: soc {
-                compatible = "qcom,msm-8660-qgic";
+                #address-cells = <1>;
-                interrupt-controller;
+                #size-cells = <1>;
-                #interrupt-cells = <3>;
+                ranges;
-                reg = < 0x02080000 0x1000 >,
+                compatible = "simple-bus";
-                      < 0x02081000 0x1000 >;
-        };
-        timer@2000000 {
+                intc: interrupt-controller@2080000 {
-                compatible = "qcom,scss-timer", "qcom,msm-timer";
+                        compatible = "qcom,msm-8660-qgic";
-                interrupts = <1 0 0x301>,
+                        interrupt-controller;
-                             <1 1 0x301>,
+                        #interrupt-cells = <3>;
-                             <1 2 0x301>;
+                        reg = < 0x02080000 0x1000 >,
-                reg = <0x02000000 0x100>;
+                              < 0x02081000 0x1000 >;
-                clock-frequency = <27000000>,
+                };
-                                  <32768>;
-                cpu-offset = <0x40000>;
-        };
-        msmgpio: gpio@800000 {
+                timer@2000000 {
-                compatible = "qcom,msm-gpio";
+                        compatible = "qcom,scss-timer", "qcom,msm-timer";
-                reg = <0x00800000 0x4000>;
+                        interrupts = <1 0 0x301>,
-                gpio-controller;
+                                     <1 1 0x301>,
-                #gpio-cells = <2>;
+                                     <1 2 0x301>;
-                ngpio = <173>;
+                        reg = <0x02000000 0x100>;
-                interrupts = <0 16 0x4>;
+                        clock-frequency = <27000000>,
-                interrupt-controller;
+                                          <32768>;
-                #interrupt-cells = <2>;
+                        cpu-offset = <0x40000>;
-        };
+                };
-        gcc: clock-controller@900000 {
+                msmgpio: gpio@800000 {
-                compatible = "qcom,gcc-msm8660";
+                        compatible = "qcom,msm-gpio";
-                #clock-cells = <1>;
+                        reg = <0x00800000 0x4000>;
-                #reset-cells = <1>;
+                        gpio-controller;
-                reg = <0x900000 0x4000>;
+                        #gpio-cells = <2>;
-        };
+                        ngpio = <173>;
+                        interrupts = <0 16 0x4>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                };
-        serial@19c40000 {
+                gcc: clock-controller@900000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                        compatible = "qcom,gcc-msm8660";
-                reg = <0x19c40000 0x1000>,
+                        #clock-cells = <1>;
-                      <0x19c00000 0x1000>;
+                        #reset-cells = <1>;
-                interrupts = <0 195 0x0>;
+                        reg = <0x900000 0x4000>;
-                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                };
-                clock-names = "core", "iface";
-        };
+                gsbi12: gsbi@19c00000 {
+                        compatible = "qcom,gsbi-v1.0.0";
+                        reg = <0x19c00000 0x100>;
+                        clocks = <&gcc GSBI12_H_CLK>;
+                        clock-names = "iface";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        ranges;
-        qcom,ssbi@500000 {
+                        serial@19c40000 {
-                compatible = "qcom,ssbi";
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
-                reg = <0x500000 0x1000>;
+                                reg = <0x19c40000 0x1000>,
-                qcom,controller-type = "pmic-arbiter";
+                                      <0x19c00000 0x1000>;
+                                interrupts = <0 195 0x0>;
+                                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+                };
+                qcom,ssbi@500000 {
+                        compatible = "qcom,ssbi";
+                        reg = <0x500000 0x1000>;
+                        qcom,controller-type = "pmic-arbiter";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960-cdp.dts b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
index a58fb88315f6..8f75cc4c8340 100644
--- a/arch/arm/boot/dts/qcom-msm8960-cdp.dts
+++ b/arch/arm/boot/dts/qcom-msm8960-cdp.dts
@@ -3,4 +3,14 @@
 / {
        model = "Qualcomm MSM8960 CDP";
        compatible = "qcom,msm8960-cdp", "qcom,msm8960";
+        soc {
+                gsbi@16400000 {
+                        status = "ok";
+                        qcom,mode = <GSBI_PROT_I2C_UART>;
+                        serial@16440000 {
+                                status = "ok";
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi
index 997b7b94e117..5303e53e34dc 100644
--- a/arch/arm/boot/dts/qcom-msm8960.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8960.dtsi
@@ -3,6 +3,7 @@
 /include/ "skeleton.dtsi"
 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+#include <dt-bindings/soc/qcom,gsbi.h>
 / {
        model = "Qualcomm MSM8960";
@@ -13,10 +14,10 @@
                #address-cells = <1>;
                #size-cells = <0>;
                interrupts = <1 14 0x304>;
-                compatible = "qcom,krait";
-                enable-method = "qcom,kpss-acc-v1";
                cpu@0 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
@@ -25,6 +26,8 @@
                };
                cpu@1 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v1";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
@@ -35,7 +38,6 @@
                L2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
-                        interrupts = <0 2 0x4>;
                };
        };
@@ -45,91 +47,109 @@
                qcom,no-pc-write;
        };
-        intc: interrupt-controller@2000000 {
+        soc: soc {
-                compatible = "qcom,msm-qgic2";
+                #address-cells = <1>;
-                interrupt-controller;
+                #size-cells = <1>;
-                #interrupt-cells = <3>;
+                ranges;
-                reg = < 0x02000000 0x1000 >,
+                compatible = "simple-bus";
-                      < 0x02002000 0x1000 >;
-        };
+                intc: interrupt-controller@2000000 {
+                        compatible = "qcom,msm-qgic2";
+                        interrupt-controller;
+                        #interrupt-cells = <3>;
+                        reg = <0x02000000 0x1000>,
+                              <0x02002000 0x1000>;
+                };
-        timer@200a000 {
+                timer@200a000 {
-                compatible = "qcom,kpss-timer", "qcom,msm-timer";
+                        compatible = "qcom,kpss-timer", "qcom,msm-timer";
-                interrupts = <1 1 0x301>,
+                        interrupts = <1 1 0x301>,
-                             <1 2 0x301>,
+                                     <1 2 0x301>,
-                             <1 3 0x301>;
+                                     <1 3 0x301>;
-                reg = <0x0200a000 0x100>;
+                        reg = <0x0200a000 0x100>;
-                clock-frequency = <27000000>,
+                        clock-frequency = <27000000>,
-                                  <32768>;
+                                          <32768>;
-                cpu-offset = <0x80000>;
+                        cpu-offset = <0x80000>;
-        };
+                };
-        msmgpio: gpio@800000 {
+                msmgpio: gpio@800000 {
-                compatible = "qcom,msm-gpio";
+                        compatible = "qcom,msm-gpio";
-                gpio-controller;
+                        gpio-controller;
-                #gpio-cells = <2>;
+                        #gpio-cells = <2>;
-                ngpio = <150>;
+                        ngpio = <150>;
-                interrupts = <0 16 0x4>;
+                        interrupts = <0 16 0x4>;
-                interrupt-controller;
+                        interrupt-controller;
-                #interrupt-cells = <2>;
+                        #interrupt-cells = <2>;
-                reg = <0x800000 0x4000>;
+                        reg = <0x800000 0x4000>;
-        };
+                };
-        gcc: clock-controller@900000 {
+                gcc: clock-controller@900000 {
-                compatible = "qcom,gcc-msm8960";
+                        compatible = "qcom,gcc-msm8960";
-                #clock-cells = <1>;
+                        #clock-cells = <1>;
-                #reset-cells = <1>;
+                        #reset-cells = <1>;
-                reg = <0x900000 0x4000>;
+                        reg = <0x900000 0x4000>;
-        };
+                };
-        clock-controller@4000000 {
+                clock-controller@4000000 {
-                compatible = "qcom,mmcc-msm8960";
+                        compatible = "qcom,mmcc-msm8960";
-                reg = <0x4000000 0x1000>;
+                        reg = <0x4000000 0x1000>;
-                #clock-cells = <1>;
+                        #clock-cells = <1>;
-                #reset-cells = <1>;
+                        #reset-cells = <1>;
-        };
+                };
-        acc0: clock-controller@2088000 {
+                acc0: clock-controller@2088000 {
-                compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v1";
-                reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+                        reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
-        };
+                };
-        acc1: clock-controller@2098000 {
+                acc1: clock-controller@2098000 {
-                compatible = "qcom,kpss-acc-v1";
+                        compatible = "qcom,kpss-acc-v1";
-                reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
+                        reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
-        };
+                };
-        saw0: regulator@2089000 {
+                saw0: regulator@2089000 {
-                compatible = "qcom,saw2";
+                        compatible = "qcom,saw2";
-                reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
+                        reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
-                regulator;
+                        regulator;
-        };
+                };
-        saw1: regulator@2099000 {
+                saw1: regulator@2099000 {
-                compatible = "qcom,saw2";
+                        compatible = "qcom,saw2";
-                reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
+                        reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
-                regulator;
+                        regulator;
-        };
+                };
-        serial@16440000 {
+                gsbi5: gsbi@16400000 {
-                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                        compatible = "qcom,gsbi-v1.0.0";
-                reg = <0x16440000 0x1000>,
+                        reg = <0x16400000 0x100>;
-                      <0x16400000 0x1000>;
+                        clocks = <&gcc GSBI5_H_CLK>;
-                interrupts = <0 154 0x0>;
+                        clock-names = "iface";
-                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                        #address-cells = <1>;
-                clock-names = "core", "iface";
+                        #size-cells = <1>;
-        };
+                        ranges;
+                        serial@16440000 {
+                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+                                reg = <0x16440000 0x1000>,
+                                      <0x16400000 0x1000>;
+                                interrupts = <0 154 0x0>;
+                                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
+                                clock-names = "core", "iface";
+                                status = "disabled";
+                        };
+                };
-        qcom,ssbi@500000 {
+                qcom,ssbi@500000 {
-                compatible = "qcom,ssbi";
+                        compatible = "qcom,ssbi";
-                reg = <0x500000 0x1000>;
+                        reg = <0x500000 0x1000>;
-                qcom,controller-type = "pmic-arbiter";
+                        qcom,controller-type = "pmic-arbiter";
-        };
+                };
-        rng@1a500000 {
+                rng@1a500000 {
-                compatible = "qcom,prng";
+                        compatible = "qcom,prng";
-                reg = <0x1a500000 0x200>;
+                        reg = <0x1a500000 0x200>;
-                clocks = <&gcc PRNG_CLK>;
+                        clocks = <&gcc PRNG_CLK>;
-                clock-names = "core";
+                        clock-names = "core";
+                };
        };
 };
diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi
index f68723918b3f..69dca2aca25a 100644
--- a/arch/arm/boot/dts/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8974.dtsi
@@ -13,10 +13,10 @@
                #address-cells = <1>;
                #size-cells = <0>;
                interrupts = <1 9 0xf04>;
-                compatible = "qcom,krait";
-                enable-method = "qcom,kpss-acc-v2";
                cpu@0 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v2";
                        device_type = "cpu";
                        reg = <0>;
                        next-level-cache = <&L2>;
@@ -24,6 +24,8 @@
                };
                cpu@1 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v2";
                        device_type = "cpu";
                        reg = <1>;
                        next-level-cache = <&L2>;
@@ -31,6 +33,8 @@
                };
                cpu@2 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v2";
                        device_type = "cpu";
                        reg = <2>;
                        next-level-cache = <&L2>;
@@ -38,6 +42,8 @@
                };
                cpu@3 {
+                        compatible = "qcom,krait";
+                        enable-method = "qcom,kpss-acc-v2";
                        device_type = "cpu";
                        reg = <3>;
                        next-level-cache = <&L2>;
@@ -47,7 +53,6 @@
                L2: l2-cache {
                        compatible = "cache";
                        cache-level = <2>;
-                        interrupts = <0 2 0x4>;
                        qcom,saw = <&saw_l2>;
                };
        };
@@ -57,6 +62,15 @@
                interrupts = <1 7 0xf04>;
        };
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 2 0xf08>,
+                             <1 3 0xf08>,
+                             <1 4 0xf08>,
+                             <1 1 0xf08>;
+                clock-frequency = <19200000>;
+        };
        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -71,15 +85,6 @@
                              <0xf9002000 0x1000>;
                };
-                timer {
-                        compatible = "arm,armv7-timer";
-                        interrupts = <1 2 0xf08>,
-                                     <1 3 0xf08>,
-                                     <1 4 0xf08>,
-                                     <1 1 0xf08>;
-                        clock-frequency = <19200000>;
-                };
                timer@f9020000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
@@ -190,6 +195,29 @@
                        interrupts = <0 108 0x0>;
                        clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+                sdhci@f9824900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 123 0>, <0 138 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
+                };
+                sdhci@f98a4900 {
+                        compatible = "qcom,sdhci-msm-v4";
+                        reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
+                        reg-names = "hc_mem", "core_mem";
+                        interrupts = <0 125 0>, <0 221 0>;
+                        interrupt-names = "hc_irq", "pwr_irq";
+                        clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
+                        clock-names = "core", "iface";
+                        status = "disabled";
                };
                rng@f9bff000 {
@@ -198,5 +226,15 @@
                        clocks = <&gcc GCC_PRNG_AHB_CLK>;
                        clock-names = "core";
                };
+                msmgpio: pinctrl@fd510000 {
+                        compatible = "qcom,msm8974-pinctrl";
+                        reg = <0xfd510000 0x4000>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <0 208 0>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/r7s72100-genmai-reference.dts b/arch/arm/boot/dts/r7s72100-genmai-reference.dts
deleted file mode 100644
index e664611a47c8..000000000000
--- a/arch/arm/boot/dts/r7s72100-genmai-reference.dts
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Device Tree Source for the Genmai board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2.  This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-/dts-v1/;
-#include "r7s72100.dtsi"
-/ {
-        model = "Genmai";
-        compatible = "renesas,genmai-reference", "renesas,r7s72100";
-        chosen {
-                bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
-        };
-        memory {
-                device_type = "memory";
-                reg = <0x08000000 0x08000000>;
-        };
-        lbsc {
-                #address-cells = <1>;
-                #size-cells = <1>;
-        };
-};
-&i2c2 {
-        status = "okay";
-        clock-frequency = <400000>;
-        eeprom@50 {
-                compatible = "renesas,24c128";
-                reg = <0x50>;
-                pagesize = <64>;
-        };
-};
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index b1deaf7e2e06..56849b55e1c2 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -1,7 +1,8 @@
 /*
 * Device Tree Source for the Genmai board
 *
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-14 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
@@ -15,6 +16,10 @@
        model = "Genmai";
        compatible = "renesas,genmai", "renesas,r7s72100";
+        aliases {
+                serial2 = &scif2;
+        };
        chosen {
                bootargs = "console=ttySC2,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
        };
@@ -29,3 +34,26 @@
                #size-cells = <1>;
        };
 };
+&extal_clk {
+        clock-frequency = <13330000>;
+};
+&usb_x1_clk {
+        clock-frequency = <48000000>;
+};
+&i2c2 {
+        status = "okay";
+        clock-frequency = <400000>;
+        eeprom@50 {
+                compatible = "renesas,24c128";
+                reg = <0x50>;
+                pagesize = <64>;
+        };
+};
+&scif2 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi
index ee700717a34b..f50fbc8f3bd9 100644
--- a/arch/arm/boot/dts/r7s72100.dtsi
+++ b/arch/arm/boot/dts/r7s72100.dtsi
@@ -1,13 +1,15 @@
 /*
 * Device Tree Source for the r7s72100 SoC
 *
- * Copyright (C) 2013 Renesas Solutions Corp.
+ * Copyright (C) 2013-14 Renesas Solutions Corp.
+ * Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */
+#include <dt-bindings/clock/r7s72100-clock.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 / {
@@ -28,6 +30,112 @@
                spi4 = &spi4;
        };
+        clocks {
+                ranges;
+                #address-cells = <1>;
+                #size-cells = <1>;
+                /* External clocks */
+                extal_clk: extal_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        /* If clk present, value must be set by board */
+                        clock-frequency = <0>;
+                        clock-output-names = "extal";
+                };
+                usb_x1_clk: usb_x1_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        /* If clk present, value must be set by board */
+                        clock-frequency = <0>;
+                        clock-output-names = "usb_x1";
+                };
+                /* Special CPG clocks */
+                cpg_clocks: cpg_clocks@fcfe0000 {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-cpg-clocks",
+                                     "renesas,rz-cpg-clocks";
+                        reg = <0xfcfe0000 0x18>;
+                        clocks = <&extal_clk>, <&usb_x1_clk>;
+                        clock-output-names = "pll", "i", "g";
+                };
+                /* Fixed factor clocks */
+                b_clk: b_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+                        clock-mult = <1>;
+                        clock-div = <3>;
+                        clock-output-names = "b";
+                };
+                p1_clk: p1_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+                        clock-mult = <1>;
+                        clock-div = <6>;
+                        clock-output-names = "p1";
+                };
+                p0_clk: p0_clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&cpg_clocks R7S72100_CLK_PLL>;
+                        clock-mult = <1>;
+                        clock-div = <12>;
+                        clock-output-names = "p0";
+                };
+                /* MSTP clocks */
+                mstp3_clks: mstp3_clks@fcfe0420 {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xfcfe0420 4>;
+                        clocks = <&p0_clk>;
+                        clock-indices = <R7S72100_CLK_MTU2>;
+                        clock-output-names = "mtu2";
+                };
+                mstp4_clks: mstp4_clks@fcfe0424 {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xfcfe0424 4>;
+                        clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+                                 <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
+                        clock-indices = <
+                                R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
+                                R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
+                        >;
+                        clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
+                };
+                mstp9_clks: mstp9_clks@fcfe0438 {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xfcfe0438 4>;
+                        clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
+                        clock-indices = <
+                                R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
+                        >;
+                        clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
+                };
+                mstp10_clks: mstp10_clks@fcfe043c {
+                        #clock-cells = <1>;
+                        compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
+                        reg = <0xfcfe043c 4>;
+                        clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
+                                 <&p1_clk>;
+                        clock-indices = <
+                                R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
+                                R7S72100_CLK_SPI4
+                        >;
+                        clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
+                };
+        };
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -61,6 +169,7 @@
                             <0 162 IRQ_TYPE_LEVEL_HIGH>,
                             <0 163 IRQ_TYPE_LEVEL_HIGH>,
                             <0 164 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
                clock-frequency = <100000>;
                status = "disabled";
        };
@@ -78,6 +187,7 @@
                             <0 170 IRQ_TYPE_LEVEL_HIGH>,
                             <0 171 IRQ_TYPE_LEVEL_HIGH>,
                             <0 172 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
                clock-frequency = <100000>;
                status = "disabled";
        };
@@ -95,6 +205,7 @@
                             <0 178 IRQ_TYPE_LEVEL_HIGH>,
                             <0 179 IRQ_TYPE_LEVEL_HIGH>,
                             <0 180 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
                clock-frequency = <100000>;
                status = "disabled";
        };
@@ -112,10 +223,107 @@
                             <0 186 IRQ_TYPE_LEVEL_HIGH>,
                             <0 187 IRQ_TYPE_LEVEL_HIGH>,
                             <0 188 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
                clock-frequency = <100000>;
                status = "disabled";
        };
+        scif0: serial@e8007000 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8007000 64>;
+                interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 191 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 192 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 189 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif1: serial@e8007800 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8007800 64>;
+                interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 195 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 196 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 193 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif2: serial@e8008000 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8008000 64>;
+                interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 199 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 200 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 197 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif3: serial@e8008800 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8008800 64>;
+                interrupts = <0 202 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 203 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 204 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 201 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif4: serial@e8009000 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8009000 64>;
+                interrupts = <0 206 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 207 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 208 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 205 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif5: serial@e8009800 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe8009800 64>;
+                interrupts = <0 210 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 211 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 212 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 209 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif6: serial@e800a000 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe800a000 64>;
+                interrupts = <0 214 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 215 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 216 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 213 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
+        scif7: serial@e800a800 {
+                compatible = "renesas,scif-r7s72100", "renesas,scif";
+                reg = <0xe800a800 64>;
+                interrupts = <0 218 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 219 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 220 IRQ_TYPE_LEVEL_HIGH>,
+                             <0 217 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
+                clock-names = "sci_ick";
+                status = "disabled";
+        };
        spi0: spi@e800c800 {
                compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
                reg = <0xe800c800 0x24>;
@@ -123,6 +331,7 @@
                             <0 239 IRQ_TYPE_LEVEL_HIGH>,
                             <0 240 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
+                clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -136,6 +345,7 @@
                             <0 242 IRQ_TYPE_LEVEL_HIGH>,
                             <0 243 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
+                clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -149,6 +359,7 @@
                             <0 245 IRQ_TYPE_LEVEL_HIGH>,
                             <0 246 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
+                clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -162,6 +373,7 @@
                             <0 248 IRQ_TYPE_LEVEL_HIGH>,
                             <0 249 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
+                clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
@@ -175,6 +387,7 @@
                             <0 251 IRQ_TYPE_LEVEL_HIGH>,
                             <0 252 IRQ_TYPE_LEVEL_HIGH>;
                interrupt-names = "error", "rx", "tx";
+                clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
                num-cs = <1>;
                #address-cells = <1>;
                #size-cells = <0>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 62d0211bd192..82c5ac825386 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -55,7 +55,6 @@
                #interrupt-cells = <2>;
                interrupt-controller;
                reg = <0 0xe61c0000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
@@ -95,7 +94,6 @@
                #interrupt-cells = <2>;
                interrupt-controller;
                reg = <0 0xe61c0200 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
                             <0 34 IRQ_TYPE_LEVEL_HIGH>,
@@ -136,7 +134,6 @@
                dma0: dma-controller@e6700020 {
                        compatible = "renesas,shdma-r8a73a4";
                        reg = <0 0xe6700020 0 0x89e0>;
-                        interrupt-parent = <&gic>;
                        interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
                                        0 200 IRQ_TYPE_LEVEL_HIGH
                                        0 201 IRQ_TYPE_LEVEL_HIGH
@@ -171,7 +168,6 @@
                compatible = "renesas,rcar-thermal";
                reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
                         <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
-                interrupt-parent = <&gic>;
                interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
        };
@@ -180,7 +176,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6500000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -190,7 +185,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6510000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -200,7 +194,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6520000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -210,7 +203,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6530000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -220,7 +212,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6540000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -230,7 +221,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe60b0000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -240,7 +230,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6550000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -250,7 +239,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6560000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -260,7 +248,6 @@
                #size-cells = <0>;
                compatible = "renesas,rmobile-iic";
                reg = <0 0xe6570000 0 0x428>;
-                interrupt-parent = <&gic>;
                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -268,7 +255,6 @@
        mmcif0: mmc@ee200000 {
                compatible = "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;
-                interrupt-parent = <&gic>;
                interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
                reg-io-width = <4>;
                status = "disabled";
@@ -277,7 +263,6 @@
        mmcif1: mmc@ee220000 {
                compatible = "renesas,sh-mmcif";
                reg = <0 0xee220000 0 0x80>;
-                interrupt-parent = <&gic>;
                interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
                reg-io-width = <4>;
                status = "disabled";
@@ -309,7 +294,6 @@
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee100000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                status = "disabled";
@@ -318,7 +302,6 @@
        sdhi1: sd@ee120000 {
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee120000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                status = "disabled";
@@ -327,7 +310,6 @@
        sdhi2: sd@ee140000 {
                compatible = "renesas,sdhi-r8a73a4";
                reg = <0 0xee140000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                status = "disabled";
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 95a849bf921f..486007d7ffe4 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -11,6 +11,7 @@
 /dts-v1/;
 #include "r8a7740.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pwm/pwm.h>
@@ -77,26 +78,26 @@
                power-key {
                        gpios = <&pfc 99 GPIO_ACTIVE_LOW>;
-                        linux,code = <116>;
+                        linux,code = <KEY_POWER>;
                        label = "SW3";
                        gpio-key,wakeup;
                };
                back-key {
                        gpios = <&pfc 100 GPIO_ACTIVE_LOW>;
-                        linux,code = <158>;
+                        linux,code = <KEY_BACK>;
                        label = "SW4";
                };
                menu-key {
                        gpios = <&pfc 97 GPIO_ACTIVE_LOW>;
-                        linux,code = <139>;
+                        linux,code = <KEY_MENU>;
                        label = "SW5";
                };
                home-key {
                        gpios = <&pfc 98 GPIO_ACTIVE_LOW>;
-                        linux,code = <102>;
+                        linux,code = <KEY_HOME>;
                        label = "SW6";
                };
        };
@@ -117,6 +118,16 @@
                };
        };
+        i2c2: i2c@2 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "i2c-gpio";
+                gpios = <&pfc 208 GPIO_ACTIVE_HIGH /* sda */
+                         &pfc 91 GPIO_ACTIVE_HIGH /* scl */
+                        >;
+                i2c-gpio,delay-us = <5>;
+        };
        backlight {
                compatible = "pwm-backlight";
                pwms = <&tpu 2 33333 PWM_POLARITY_INVERTED>;
@@ -147,6 +158,18 @@
        };
 };
+&ether {
+        pinctrl-0 = <&ether_pins>;
+        pinctrl-names = "default";
+        phy-handle = <&phy0>;
+        status = "ok";
+        phy0: ethernet-phy@0 {
+                reg = <0>;
+        };
+};
 &i2c0 {
        status = "okay";
        touchscreen@55 {
@@ -166,10 +189,23 @@
        };
 };
+&i2c2 {
+        status = "okay";
+        rtc@30 {
+                compatible = "sii,s35390a";
+                reg = <0x30>;
+        };
+};
 &pfc {
        pinctrl-0 = <&scifa1_pins>;
        pinctrl-names = "default";
+        ether_pins: ether {
+                renesas,groups = "gether_mii", "gether_int";
+                renesas,function = "gether";
+        };
        scifa1_pins: serial1 {
                renesas,groups = "scifa1_data";
                renesas,function = "scifa1";
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 2551e9438d35..55d29f4d2ed6 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -14,6 +14,7 @@
 / {
        compatible = "renesas,r8a7740";
+        interrupt-parent = <&gic>;
        cpus {
                #address-cells = <1>;
@@ -22,6 +23,7 @@
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0x0>;
+                        clock-frequency = <800000000>;
                };
        };
@@ -48,7 +50,6 @@
                        <0xe6900020 1>,
                        <0xe6900040 1>,
                        <0xe6900060 1>;
-                interrupt-parent = <&gic>;
                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
@@ -69,7 +70,6 @@
                        <0xe6900024 1>,
                        <0xe6900044 1>,
                        <0xe6900064 1>;
-                interrupt-parent = <&gic>;
                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
@@ -90,7 +90,6 @@
                        <0xe6900028 1>,
                        <0xe6900048 1>,
                        <0xe6900068 1>;
-                interrupt-parent = <&gic>;
                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
@@ -111,7 +110,6 @@
                        <0xe690002c 1>,
                        <0xe690004c 1>,
                        <0xe690006c 1>;
-                interrupt-parent = <&gic>;
                interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
                              0 149 IRQ_TYPE_LEVEL_HIGH
@@ -122,12 +120,23 @@
                              0 149 IRQ_TYPE_LEVEL_HIGH>;
        };
+        ether: ethernet@e9a00000 {
+                compatible = "renesas,gether-r8a7740";
+                reg = <0xe9a00000 0x800>,
+                      <0xe9a01800 0x800>;
+                interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
+                /* clocks = <&mstp3_clks R8A7740_CLK_GETHER>; */
+                phy-mode = "mii";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
        i2c0: i2c@fff20000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
                reg = <0xfff20000 0x425>;
-                interrupt-parent = <&gic>;
                interrupts = <0 201 IRQ_TYPE_LEVEL_HIGH
                              0 202 IRQ_TYPE_LEVEL_HIGH
                              0 203 IRQ_TYPE_LEVEL_HIGH
@@ -138,9 +147,8 @@
        i2c1: i2c@e6c20000 {
                #address-cells = <1>;
                #size-cells = <0>;
-                compatible = "renesas,rmobile-iic";
+                compatible = "renesas,iic-r8a7740", "renesas,rmobile-iic";
                reg = <0xe6c20000 0x425>;
-                interrupt-parent = <&gic>;
                interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH
                              0 71 IRQ_TYPE_LEVEL_HIGH
                              0 72 IRQ_TYPE_LEVEL_HIGH
@@ -173,9 +181,8 @@
        };
        mmcif0: mmc@e6bd0000 {
-                compatible = "renesas,sh-mmcif";
+                compatible = "renesas,mmcif-r8a7740", "renesas,sh-mmcif";
                reg = <0xe6bd0000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH
                              0 57 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
@@ -184,7 +191,6 @@
        sdhi0: sd@e6850000 {
                compatible = "renesas,sdhi-r8a7740";
                reg = <0xe6850000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH
                              0 118 IRQ_TYPE_LEVEL_HIGH
                              0 119 IRQ_TYPE_LEVEL_HIGH>;
@@ -196,7 +202,6 @@
        sdhi1: sd@e6860000 {
                compatible = "renesas,sdhi-r8a7740";
                reg = <0xe6860000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH
                              0 122 IRQ_TYPE_LEVEL_HIGH
                              0 123 IRQ_TYPE_LEVEL_HIGH>;
@@ -208,7 +213,6 @@
        sdhi2: sd@e6870000 {
                compatible = "renesas,sdhi-r8a7740";
                reg = <0xe6870000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH
                              0 126 IRQ_TYPE_LEVEL_HIGH
                              0 127 IRQ_TYPE_LEVEL_HIGH>;
@@ -219,9 +223,8 @@
        sh_fsi2: sound@fe1f0000 {
                #sound-dai-cells = <1>;
-                compatible = "renesas,sh_fsi2";
+                compatible = "renesas,fsi2-r8a7740", "renesas,sh_fsi2";
                reg = <0xfe1f0000 0x400>;
-                interrupt-parent = <&gic>;
                interrupts = <0 9 0x4>;
                status = "disabled";
        };
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index 06cda19dac6a..f76f6ec01e19 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -109,4 +109,18 @@
        pinctrl-0 = <&hspi0_pins>;
        pinctrl-names = "default";
        status = "okay";
+        flash: flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl008k";
+                reg = <0>;
+                spi-max-frequency = <104000000>;
+                m25p,fast-read;
+                partition@0 {
+                        label = "data(spi)";
+                        reg = <0x00000000 0x00100000>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 85c5b3b99f5e..3af0a2187493 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -20,6 +20,7 @@
 / {
        compatible = "renesas,r8a7778";
+        interrupt-parent = <&gic>;
        cpus {
                cpu@0 {
@@ -52,7 +53,6 @@
                        <0xfe780024 4>,
                        <0xfe780044 4>,
                        <0xfe780064 4>;
-                interrupt-parent = <&gic>;
                interrupts =   <0 27 IRQ_TYPE_LEVEL_HIGH
                                0 28 IRQ_TYPE_LEVEL_HIGH
                                0 29 IRQ_TYPE_LEVEL_HIGH
@@ -63,7 +63,6 @@
        gpio0: gpio@ffc40000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc40000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -75,7 +74,6 @@
        gpio1: gpio@ffc41000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc41000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -87,7 +85,6 @@
        gpio2: gpio@ffc42000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc42000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -99,7 +96,6 @@
        gpio3: gpio@ffc43000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc43000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -111,7 +107,6 @@
        gpio4: gpio@ffc44000 {
                compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
                reg = <0xffc44000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -130,7 +125,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc70000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -140,7 +134,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc71000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -150,7 +143,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc72000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -160,7 +152,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7778";
                reg = <0xffc73000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -168,7 +159,6 @@
        mmcif: mmc@ffe4e000 {
                compatible = "renesas,sh-mmcif";
                reg = <0xffe4e000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -176,7 +166,6 @@
        sdhi0: sd@ffe4c000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4c000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -186,7 +175,6 @@
        sdhi1: sd@ffe4d000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4d000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -196,7 +184,6 @@
        sdhi2: sd@ffe4f000 {
                compatible = "renesas,sdhi-r8a7778";
                reg = <0xffe4f000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -204,26 +191,29 @@
        };
        hspi0: spi@fffc7000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc7000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
        hspi1: spi@fffc8000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc8000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
        hspi2: spi@fffc6000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7778", "renesas,hspi";
                reg = <0xfffc6000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 76f5eef7d1cc..b27c6373ff4d 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -45,6 +45,7 @@
                phy-mode = "mii";
                interrupt-parent = <&irqpin0>;
                interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+                smsc,irq-push-pull;
                reg-io-width = <4>;
                vddvario-supply = <&fixedregulator3v3>;
                vdd33a-supply = <&fixedregulator3v3>;
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index d0561d4c7c46..b517c8e6b420 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -15,6 +15,7 @@
 / {
        compatible = "renesas,r8a7779";
+        interrupt-parent = <&gic>;
        cpus {
                #address-cells = <1>;
@@ -59,7 +60,6 @@
        gpio0: gpio@ffc40000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc40000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -71,7 +71,6 @@
        gpio1: gpio@ffc41000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc41000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -83,7 +82,6 @@
        gpio2: gpio@ffc42000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc42000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -95,7 +93,6 @@
        gpio3: gpio@ffc43000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc43000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -107,7 +104,6 @@
        gpio4: gpio@ffc44000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc44000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -119,7 +115,6 @@
        gpio5: gpio@ffc45000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc45000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -131,7 +126,6 @@
        gpio6: gpio@ffc46000 {
                compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
                reg = <0xffc46000 0x2c>;
-                interrupt-parent = <&gic>;
                interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
                #gpio-cells = <2>;
                gpio-controller;
@@ -150,7 +144,6 @@
                        <0xfe780024 4>,
                        <0xfe780044 4>,
                        <0xfe780064 4>;
-                interrupt-parent = <&gic>;
                interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
                              0 28 IRQ_TYPE_LEVEL_HIGH
                              0 29 IRQ_TYPE_LEVEL_HIGH
@@ -163,7 +156,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7779";
                reg = <0xffc70000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -173,7 +165,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7779";
                reg = <0xffc71000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -183,7 +174,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7779";
                reg = <0xffc72000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -193,7 +183,6 @@
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7779";
                reg = <0xffc73000 0x1000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
                status = "disabled";
        };
@@ -211,14 +200,12 @@
        sata: sata@fc600000 {
                compatible = "renesas,rcar-sata";
                reg = <0xfc600000 0x2000>;
-                interrupt-parent = <&gic>;
                interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
        };
        sdhi0: sd@ffe4c000 {
                compatible = "renesas,sdhi-r8a7779";
                reg = <0xffe4c000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -228,7 +215,6 @@
        sdhi1: sd@ffe4d000 {
                compatible = "renesas,sdhi-r8a7779";
                reg = <0xffe4d000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -238,7 +224,6 @@
        sdhi2: sd@ffe4e000 {
                compatible = "renesas,sdhi-r8a7779";
                reg = <0xffe4e000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -248,7 +233,6 @@
        sdhi3: sd@ffe4f000 {
                compatible = "renesas,sdhi-r8a7779";
                reg = <0xffe4f000 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
                cap-sd-highspeed;
                cap-sdio-irq;
@@ -256,26 +240,29 @@
        };
        hspi0: spi@fffc7000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7779", "renesas,hspi";
                reg = <0xfffc7000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
        hspi1: spi@fffc8000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7779", "renesas,hspi";
                reg = <0xfffc8000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
        hspi2: spi@fffc6000 {
-                compatible = "renesas,hspi";
+                compatible = "renesas,hspi-r8a7779", "renesas,hspi";
                reg = <0xfffc6000 0x18>;
-                interrupt-controller = <&gic>;
                interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
+                #address-cells = <1>;
+                #size-cells = <0>;
                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index d01048ab3e77..dd2fe46073f2 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -12,11 +12,17 @@
 /dts-v1/;
 #include "r8a7790.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 / {
        model = "Lager";
        compatible = "renesas,lager", "renesas,r8a7790";
+        aliases {
+                serial6 = &scif0;
+                serial7 = &scif1;
+        };
        chosen {
                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
        };
@@ -36,6 +42,39 @@
                #size-cells = <1>;
        };
+        gpio_keys {
+                compatible = "gpio-keys";
+                button@1 {
+                        linux,code = <KEY_1>;
+                        label = "SW2-1";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                        gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                };
+                button@2 {
+                        linux,code = <KEY_2>;
+                        label = "SW2-2";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                        gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
+                };
+                button@3 {
+                        linux,code = <KEY_3>;
+                        label = "SW2-3";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                        gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
+                };
+                button@4 {
+                        linux,code = <KEY_4>;
+                        label = "SW2-4";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                        gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+                };
+        };
        leds {
                compatible = "gpio-leds";
                led6 {
@@ -112,7 +151,7 @@
 };
 &pfc {
-        pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
+        pinctrl-0 = <&du_pins>;
        pinctrl-names = "default";
        du_pins: du {
@@ -155,10 +194,16 @@
                renesas,function = "mmc1";
        };
-        qspi_pins: spi {
+        qspi_pins: spi0 {
                renesas,groups = "qspi_ctrl", "qspi_data4";
                renesas,function = "qspi";
        };
+        msiof1_pins: spi2 {
+                renesas,groups = "msiof1_clk", "msiof1_sync", "msiof1_rx",
+                                 "msiof1_tx";
+                renesas,function = "msiof1";
+        };
 };
 &ether {
@@ -173,6 +218,7 @@
                reg = <1>;
                interrupt-parent = <&irqc0>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
        };
 };
@@ -190,7 +236,7 @@
        status = "okay";
 };
-&spi {
+&qspi {
        pinctrl-0 = <&qspi_pins>;
        pinctrl-names = "default";
@@ -202,6 +248,8 @@
                compatible = "spansion,s25fl512s";
                reg = <0>;
                spi-max-frequency = <30000000>;
+                spi-tx-bus-width = <4>;
+                spi-rx-bus-width = <4>;
                m25p,fast-read;
                partition@0 {
@@ -221,6 +269,35 @@
        };
 };
+&scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+&scif1 {
+        pinctrl-0 = <&scif1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+&msiof1 {
+        pinctrl-0 = <&msiof1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        pmic: pmic@0 {
+                compatible = "renesas,r2a11302ft";
+                reg = <0>;
+                spi-max-frequency = <6000000>;
+                spi-cpol;
+                spi-cpha;
+        };
+};
 &sdhi0 {
        pinctrl-0 = <&sdhi0_pins>;
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 618e5b537eaf..7ff29601f962 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -24,6 +24,15 @@
                i2c1 = &i2c1;
                i2c2 = &i2c2;
                i2c3 = &i2c3;
+                i2c4 = &iic0;
+                i2c5 = &iic1;
+                i2c6 = &iic2;
+                i2c7 = &iic3;
+                spi0 = &qspi;
+                spi1 = &msiof0;
+                spi2 = &msiof1;
+                spi3 = &msiof2;
+                spi4 = &msiof3;
        };
        cpus {
@@ -108,6 +117,7 @@
                gpio-ranges = <&pfc 0 0 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
        };
        gpio1: gpio@e6051000 {
@@ -119,6 +129,7 @@
                gpio-ranges = <&pfc 0 32 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
        };
        gpio2: gpio@e6052000 {
@@ -130,6 +141,7 @@
                gpio-ranges = <&pfc 0 64 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
        };
        gpio3: gpio@e6053000 {
@@ -141,6 +153,7 @@
                gpio-ranges = <&pfc 0 96 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
        };
        gpio4: gpio@e6054000 {
@@ -152,6 +165,7 @@
                gpio-ranges = <&pfc 0 128 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
        };
        gpio5: gpio@e6055000 {
@@ -163,6 +177,7 @@
                gpio-ranges = <&pfc 0 160 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
        };
        thermal@e61f0000 {
@@ -231,6 +246,46 @@
                status = "disabled";
        };
+        iic0: i2c@e6500000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+                reg = <0 0xe6500000 0 0x425>;
+                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
+                status = "disabled";
+        };
+        iic1: i2c@e6510000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+                reg = <0 0xe6510000 0 0x425>;
+                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
+                status = "disabled";
+        };
+        iic2: i2c@e6520000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+                reg = <0 0xe6520000 0 0x425>;
+                interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
+                status = "disabled";
+        };
+        iic3: i2c@e60b0000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
+                reg = <0 0xe60b0000 0 0x425>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
+                status = "disabled";
+        };
        mmcif0: mmcif@ee200000 {
                compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
                reg = <0 0xee200000 0 0x80>;
@@ -673,7 +728,7 @@
                        renesas,clock-indices = <
                                R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
-                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
+                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                        >;
                        clock-output-names =
                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
@@ -697,18 +752,19 @@
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
+                        clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
-                                 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
+                                 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
-                                 <&mmc0_clk>, <&rclk_clk>;
+                                 <&hp_clk>, <&hp_clk>, <&rclk_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
+                                R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
-                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
+                                R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
-                                R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
+                                R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1
                        >;
                        clock-output-names =
-                                "tpu0", "mmcif1", "sdhi3", "sdhi2",
+                                "iic2", "tpu0", "mmcif1", "sdhi3",
-                                "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                                "sdhi2", "sdhi1", "sdhi0", "mmcif0",
+                                "iic0", "iic1", "cmt1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -752,20 +808,25 @@
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
+                        clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
-                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
+                                 <&cp_clk>, <&cp_clk>, <&cp_clk>,
+                                 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
+                                 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
+                                R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
-                                R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
+                                R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
-                                R8A7790_CLK_I2C0
+                                R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
+                                R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
                        >;
                        clock-output-names =
-                                "rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
+                                "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
+                                "rcan1", "rcan0", "qspi_mod", "iic3",
+                                "i2c3", "i2c2", "i2c1", "i2c0";
                };
        };
-        spi: spi@e6b10000 {
+        qspi: spi@e6b10000 {
                compatible = "renesas,qspi-r8a7790", "renesas,qspi";
                reg = <0 0xe6b10000 0 0x2c>;
                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
@@ -775,4 +836,44 @@
                #size-cells = <0>;
                status = "disabled";
        };
+        msiof0: spi@e6e20000 {
+                compatible = "renesas,msiof-r8a7790";
+                reg = <0 0xe6e20000 0 0x0064>;
+                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        msiof1: spi@e6e10000 {
+                compatible = "renesas,msiof-r8a7790";
+                reg = <0 0xe6e10000 0 0x0064>;
+                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        msiof2: spi@e6e00000 {
+                compatible = "renesas,msiof-r8a7790";
+                reg = <0 0xe6e00000 0 0x0064>;
+                interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        msiof3: spi@e6c90000 {
+                compatible = "renesas,msiof-r8a7790";
+                reg = <0 0xe6c90000 0 0x0064>;
+                interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
new file mode 100644
index 000000000000..cc6d992e8db2
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -0,0 +1,219 @@
+/*
+ * Device Tree Source for the Henninger board
+ *
+ * Copyright (C) 2014 Renesas Solutions Corp.
+ * Copyright (C) 2014 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+/dts-v1/;
+#include "r8a7791.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+        model = "Henninger";
+        compatible = "renesas,henninger", "renesas,r8a7791";
+        aliases {
+                serial0 = &scif0;
+        };
+        chosen {
+                bootargs = "console=ttySC0,38400 ignore_loglevel rw root=/dev/nfs ip=dhcp";
+        };
+        memory@40000000 {
+                device_type = "memory";
+                reg = <0 0x40000000 0 0x40000000>;
+        };
+        memory@200000000 {
+                device_type = "memory";
+                reg = <2 0x00000000 0 0x40000000>;
+        };
+        vcc_sdhi0: regulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI0 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+        vccq_sdhi0: regulator@1 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI0 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+        vcc_sdhi2: regulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "SDHI2 Vcc";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                regulator-always-on;
+        };
+        vccq_sdhi2: regulator@3 {
+                compatible = "regulator-gpio";
+                regulator-name = "SDHI2 VccQ";
+                regulator-min-microvolt = <1800000>;
+                regulator-max-microvolt = <3300000>;
+                gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+                gpios-states = <1>;
+                states = <3300000 1
+                          1800000 0>;
+        };
+};
+&extal_clk {
+        clock-frequency = <20000000>;
+};
+&pfc {
+        scif0_pins: serial0 {
+                renesas,groups = "scif0_data_d";
+                renesas,function = "scif0";
+        };
+        ether_pins: ether {
+                renesas,groups = "eth_link", "eth_mdio", "eth_rmii";
+                renesas,function = "eth";
+        };
+        phy1_pins: phy1 {
+                renesas,groups = "intc_irq0";
+                renesas,function = "intc";
+        };
+        sdhi0_pins: sd0 {
+                renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
+                renesas,function = "sdhi0";
+        };
+        sdhi2_pins: sd2 {
+                renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
+                renesas,function = "sdhi2";
+        };
+        qspi_pins: spi0 {
+                renesas,groups = "qspi_ctrl", "qspi_data4";
+                renesas,function = "qspi";
+        };
+        msiof0_pins: spi1 {
+                renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+                                 "msiof0_tx";
+                renesas,function = "msiof0";
+        };
+};
+&scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+&ether {
+        pinctrl-0 = <&ether_pins &phy1_pins>;
+        pinctrl-names = "default";
+        phy-handle = <&phy1>;
+        renesas,ether-link-active-low;
+        status = "ok";
+        phy1: ethernet-phy@1 {
+                reg = <1>;
+                interrupt-parent = <&irqc0>;
+                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
+        };
+};
+&sata0 {
+       status = "okay";
+};
+&sdhi0 {
+        pinctrl-0 = <&sdhi0_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi0>;
+        vqmmc-supply = <&vccq_sdhi0>;
+        cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
+        wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
+        status = "okay";
+};
+&sdhi2 {
+        pinctrl-0 = <&sdhi2_pins>;
+        pinctrl-names = "default";
+        vmmc-supply = <&vcc_sdhi2>;
+        vqmmc-supply = <&vccq_sdhi2>;
+        cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
+        status = "okay";
+};
+&qspi {
+        pinctrl-0 = <&qspi_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        flash@0 {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "spansion,s25fl512s";
+                reg = <0>;
+                spi-max-frequency = <30000000>;
+                spi-tx-bus-width = <4>;
+                spi-rx-bus-width = <4>;
+                m25p,fast-read;
+                partition@0 {
+                        label = "loader_prg";
+                        reg = <0x00000000 0x00040000>;
+                        read-only;
+                };
+                partition@40000 {
+                        label = "user_prg";
+                        reg = <0x00040000 0x00400000>;
+                        read-only;
+                };
+                partition@440000 {
+                        label = "flash_fs";
+                        reg = <0x00440000 0x03bc0000>;
+                };
+        };
+};
+&msiof0 {
+        pinctrl-0 = <&msiof0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        pmic@0 {
+                compatible = "renesas,r2a11302ft";
+                reg = <0>;
+                spi-max-frequency = <6000000>;
+                spi-cpol;
+                spi-cpha;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index de1b6977c69a..05d44f9b202f 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -13,11 +13,17 @@
 /dts-v1/;
 #include "r8a7791.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 / {
        model = "Koelsch";
        compatible = "renesas,koelsch", "renesas,r8a7791";
+        aliases {
+                serial6 = &scif0;
+                serial7 = &scif1;
+        };
        chosen {
                bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
        };
@@ -40,51 +46,79 @@
        gpio-keys {
                compatible = "gpio-keys";
+                key-1 {
+                        gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_1>;
+                        label = "SW2-1";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-2 {
+                        gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_2>;
+                        label = "SW2-2";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-3 {
+                        gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_3>;
+                        label = "SW2-3";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
+                key-4 {
+                        gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_4>;
+                        label = "SW2-4";
+                        gpio-key,wakeup;
+                        debounce-interval = <20>;
+                };
                key-a {
                        gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
-                        linux,code = <30>;
+                        linux,code = <KEY_A>;
                        label = "SW30";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-b {
                        gpios = <&gpio7 1 GPIO_ACTIVE_LOW>;
-                        linux,code = <48>;
+                        linux,code = <KEY_B>;
                        label = "SW31";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-c {
                        gpios = <&gpio7 2 GPIO_ACTIVE_LOW>;
-                        linux,code = <46>;
+                        linux,code = <KEY_C>;
                        label = "SW32";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-d {
                        gpios = <&gpio7 3 GPIO_ACTIVE_LOW>;
-                        linux,code = <32>;
+                        linux,code = <KEY_D>;
                        label = "SW33";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-e {
                        gpios = <&gpio7 4 GPIO_ACTIVE_LOW>;
-                        linux,code = <18>;
+                        linux,code = <KEY_E>;
                        label = "SW34";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-f {
                        gpios = <&gpio7 5 GPIO_ACTIVE_LOW>;
-                        linux,code = <33>;
+                        linux,code = <KEY_F>;
                        label = "SW35";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
                };
                key-g {
                        gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
-                        linux,code = <34>;
+                        linux,code = <KEY_G>;
                        label = "SW36";
                        gpio-key,wakeup;
                        debounce-interval = <20>;
@@ -195,11 +229,16 @@
        };
 };
+&i2c6 {
+        status = "okay";
+        clock-frequency = <100000>;
+};
 &pfc {
-        pinctrl-0 = <&du_pins &scif0_pins &scif1_pins>;
+        pinctrl-0 = <&du_pins>;
        pinctrl-names = "default";
-        i2c2_pins: i2c {
+        i2c2_pins: i2c2 {
                renesas,groups = "i2c2";
                renesas,function = "i2c2";
        };
@@ -244,10 +283,16 @@
                renesas,function = "sdhi2";
        };
-        qspi_pins: spi {
+        qspi_pins: spi0 {
                renesas,groups = "qspi_ctrl", "qspi_data4";
                renesas,function = "qspi";
        };
+        msiof0_pins: spi1 {
+                renesas,groups = "msiof0_clk", "msiof0_sync", "msiof0_rx",
+                                 "msiof0_tx";
+                renesas,function = "msiof0";
+        };
 };
 &ether {
@@ -262,6 +307,7 @@
                reg = <1>;
                interrupt-parent = <&irqc0>;
                interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+                micrel,led-mode = <1>;
        };
 };
@@ -269,6 +315,20 @@
        status = "okay";
 };
+&scif0 {
+        pinctrl-0 = <&scif0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
+&scif1 {
+        pinctrl-0 = <&scif1_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+};
 &sdhi0 {
        pinctrl-0 = <&sdhi0_pins>;
        pinctrl-names = "default";
@@ -301,7 +361,7 @@
        status = "okay";
 };
-&spi {
+&qspi {
        pinctrl-0 = <&qspi_pins>;
        pinctrl-names = "default";
@@ -313,6 +373,8 @@
                compatible = "spansion,s25fl512s";
                reg = <0>;
                spi-max-frequency = <30000000>;
+                spi-tx-bus-width = <4>;
+                spi-rx-bus-width = <4>;
                m25p,fast-read;
                partition@0 {
@@ -331,3 +393,18 @@
                };
        };
 };
+&msiof0 {
+        pinctrl-0 = <&msiof0_pins>;
+        pinctrl-names = "default";
+        status = "okay";
+        pmic: pmic@0 {
+                compatible = "renesas,r2a11302ft";
+                reg = <0>;
+                spi-max-frequency = <6000000>;
+                spi-cpol;
+                spi-cpha;
+        };
+};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 46181708e59c..8d7ffaeff6e0 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -27,6 +27,13 @@
                i2c3 = &i2c3;
                i2c4 = &i2c4;
                i2c5 = &i2c5;
+                i2c6 = &i2c6;
+                i2c7 = &i2c7;
+                i2c8 = &i2c8;
+                spi0 = &qspi;
+                spi1 = &msiof0;
+                spi2 = &msiof1;
+                spi3 = &msiof2;
        };
        cpus {
@@ -37,14 +44,14 @@
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <0>;
-                        clock-frequency = <1300000000>;
+                        clock-frequency = <1500000000>;
                };
                cpu1: cpu@1 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a15";
                        reg = <1>;
-                        clock-frequency = <1300000000>;
+                        clock-frequency = <1500000000>;
                };
        };
@@ -69,6 +76,7 @@
                gpio-ranges = <&pfc 0 0 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
        };
        gpio1: gpio@e6051000 {
@@ -80,6 +88,7 @@
                gpio-ranges = <&pfc 0 32 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
        };
        gpio2: gpio@e6052000 {
@@ -91,6 +100,7 @@
                gpio-ranges = <&pfc 0 64 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
        };
        gpio3: gpio@e6053000 {
@@ -102,6 +112,7 @@
                gpio-ranges = <&pfc 0 96 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
        };
        gpio4: gpio@e6054000 {
@@ -113,6 +124,7 @@
                gpio-ranges = <&pfc 0 128 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
        };
        gpio5: gpio@e6055000 {
@@ -124,6 +136,7 @@
                gpio-ranges = <&pfc 0 160 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
        };
        gpio6: gpio@e6055400 {
@@ -135,6 +148,7 @@
                gpio-ranges = <&pfc 0 192 32>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
        };
        gpio7: gpio@e6055800 {
@@ -146,6 +160,7 @@
                gpio-ranges = <&pfc 0 224 26>;
                #interrupt-cells = <2>;
                interrupt-controller;
+                clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
        };
        thermal@e61f0000 {
@@ -180,6 +195,7 @@
                             <0 17 IRQ_TYPE_LEVEL_HIGH>;
        };
+        /* The memory map in the User's Manual maps the cores to bus numbers */
        i2c0: i2c@e6508000 {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -231,6 +247,7 @@
        };
        i2c5: i2c@e6528000 {
+                /* doesn't need pinmux */
                #address-cells = <1>;
                #size-cells = <0>;
                compatible = "renesas,i2c-r8a7791";
@@ -240,6 +257,37 @@
                status = "disabled";
        };
+        i2c6: i2c@e60b0000 {
+                /* doesn't need pinmux */
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
+                reg = <0 0xe60b0000 0 0x425>;
+                interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
+                status = "disabled";
+        };
+        i2c7: i2c@e6500000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
+                reg = <0 0xe6500000 0 0x425>;
+                interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
+                status = "disabled";
+        };
+        i2c8: i2c@e6510000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
+                reg = <0 0xe6510000 0 0x425>;
+                interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
+                status = "disabled";
+        };
        pfc: pfc@e6060000 {
                compatible = "renesas,pfc-r8a7791";
                reg = <0 0xe6060000 0 0x250>;
@@ -249,7 +297,6 @@
        sdhi0: sd@ee100000 {
                compatible = "renesas,sdhi-r8a7791";
                reg = <0 0xee100000 0 0x200>;
-                interrupt-parent = <&gic>;
                interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
                status = "disabled";
@@ -258,7 +305,6 @@
        sdhi1: sd@ee140000 {
                compatible = "renesas,sdhi-r8a7791";
                reg = <0 0xee140000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
                status = "disabled";
@@ -267,7 +313,6 @@
        sdhi2: sd@ee160000 {
                compatible = "renesas,sdhi-r8a7791";
                reg = <0 0xee160000 0 0x100>;
-                interrupt-parent = <&gic>;
                interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
                status = "disabled";
@@ -688,7 +733,7 @@
                        renesas,clock-indices = <
                                R8A7791_CLK_TMU1 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2
                                R8A7791_CLK_CMT0 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1
-                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_SY
+                                R8A7791_CLK_VSP1_DU0 R8A7791_CLK_VSP1_S
                        >;
                        clock-output-names =
                                "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
@@ -712,15 +757,16 @@
                mstp3_clks: mstp3_clks@e615013c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
-                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>,
+                        clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
-                                <&cpg_clocks R8A7791_CLK_SD0>, <&mmc0_clk>, <&rclk_clk>;
+                                 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1
+                                R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
-                                R8A7791_CLK_SDHI0 R8A7791_CLK_MMCIF0 R8A7791_CLK_CMT1
+                                R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1
                        >;
                        clock-output-names =
-                                "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", "cmt1";
+                                "tpu0", "sdhi2", "sdhi1", "sdhi0",
+                                "mmcif0", "i2c7", "i2c8", "cmt1";
                };
                mstp5_clks: mstp5_clks@e6150144 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -733,19 +779,19 @@
                mstp7_clks: mstp7_clks@e615014c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
-                        clocks = <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
+                        clocks = <&mp_clk>,  <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
                                 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
                                 <&zx_clk>, <&zx_clk>, <&zx_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
+                                R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
                                R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
                                R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
                                R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
                                R8A7791_CLK_LVDS0
                        >;
                        clock-output-names =
-                                "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
+                                "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
                                "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
                };
                mstp8_clks: mstp8_clks@e6150990 {
@@ -764,18 +810,23 @@
                mstp9_clks: mstp9_clks@e6150994 {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
-                        clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>,
+                        clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-                                 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
+                                 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
-                                 <&p_clk>;
+                                 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
+                                 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
+                                 <&hp_clk>, <&hp_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                                R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD
+                                R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
-                                R8A7791_CLK_I2C5 R8A7791_CLK_I2C4 R8A7791_CLK_I2C3
+                                R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
-                                R8A7791_CLK_I2C2 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
+                                R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
+                                R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
+                                R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
                        >;
                        clock-output-names =
-                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c4", "i2c3",
+                                "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
-                                "i2c2", "i2c1", "i2c0";
+                                "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
+                                "i2c1", "i2c0";
                };
                mstp11_clks: mstp11_clks@e615099c {
                        compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -789,7 +840,7 @@
                };
        };
-        spi: spi@e6b10000 {
+        qspi: spi@e6b10000 {
                compatible = "renesas,qspi-r8a7791", "renesas,qspi";
                reg = <0 0xe6b10000 0 0x2c>;
                interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
@@ -799,4 +850,34 @@
                #size-cells = <0>;
                status = "disabled";
        };
+        msiof0: spi@e6e20000 {
+                compatible = "renesas,msiof-r8a7791";
+                reg = <0 0xe6e20000 0 0x0064>;
+                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        msiof1: spi@e6e10000 {
+                compatible = "renesas,msiof-r8a7791";
+                reg = <0 0xe6e10000 0 0x0064>;
+                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
+        msiof2: spi@e6e00000 {
+                compatible = "renesas,msiof-r8a7791";
+                reg = <0 0xe6e00000 0 0x0064>;
+                interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
+                #address-cells = <1>;
+                #size-cells = <0>;
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index 035df4053c21..afb327322a4a 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -18,6 +18,7 @@
 / {
        model = "bq Curie 2";
+        compatible = "mundoreader,bq-curie2", "rockchip,rk3066a";
        memory {
                reg = <0x60000000 0x40000000>;
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4d4dfbb59f4b..4387cfd420ba 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -24,6 +24,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "rockchip,rk3066-smp";
                cpu@0 {
                        device_type = "cpu";
@@ -79,7 +80,7 @@
                pinctrl@20008000 {
                        compatible = "rockchip,rk3066a-pinctrl";
-                        reg = <0x20008000 0x150>;
+                        rockchip,grf = <&grf>;
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index 3ba1968a70ab..a5eee55079cb 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -17,6 +17,7 @@
 / {
        model = "Radxa Rock";
+        compatible = "radxa,rock", "rockchip,rk3188";
        memory {
                reg = <0x60000000 0x80000000>;
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index ed9a70af3e3f..238c996d4a7f 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -24,6 +24,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
+                enable-method = "rockchip,rk3066-smp";
                cpu@0 {
                        device_type = "cpu";
@@ -75,17 +76,16 @@
                pinctrl@20008000 {
                        compatible = "rockchip,rk3188-pinctrl";
-                        reg = <0x20008000 0xa0>,
+                        rockchip,grf = <&grf>;
-                              <0x20008164 0x1a0>;
+                        rockchip,pmu = <&pmu>;
-                        reg-names = "base", "pull";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
                        gpio0: gpio0@0x2000a000 {
                                compatible = "rockchip,rk3188-gpio-bank0";
-                                reg = <0x2000a000 0x100>,
+                                reg = <0x2000a000 0x100>;
-                                      <0x20004064 0x8>;
                                interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&clk_gates8 9>;
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 26e5a968d49d..2adf1cc9e85d 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -31,11 +31,16 @@
                        reg = <0x1013c000 0x100>;
                };
-                pmu@20004000 {
+                pmu: pmu@20004000 {
-                        compatible = "rockchip,rk3066-pmu";
+                        compatible = "rockchip,rk3066-pmu", "syscon";
                        reg = <0x20004000 0x100>;
                };
+                grf: grf@20008000 {
+                        compatible = "syscon";
+                        reg = <0x20008000 0x200>;
+                };
                gic: interrupt-controller@1013d000 {
                        compatible = "arm,cortex-a9-gic";
                        interrupt-controller;
diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts
index 59594cf15998..ea92fd69529a 100644
--- a/arch/arm/boot/dts/s3c2416-smdk2416.dts
+++ b/arch/arm/boot/dts/s3c2416-smdk2416.dts
@@ -19,6 +19,19 @@
                reg =  <0x30000000 0x4000000>;
        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                xti: xti {
+                        compatible = "fixed-clock";
+                        clock-frequency = <12000000>;
+                        clock-output-names = "xti";
+                        #clock-cells = <0>;
+                };
+        };
        serial@50000000 {
                status = "okay";
                pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi
index e6555bdd81b8..955e4a4f8c31 100644
--- a/arch/arm/boot/dts/s3c2416.dtsi
+++ b/arch/arm/boot/dts/s3c2416.dtsi
@@ -8,6 +8,7 @@
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/s3c2443.h>
 #include "s3c24xx.dtsi"
 #include "s3c2416-pinctrl.dtsi"
@@ -28,26 +29,53 @@
                compatible = "samsung,s3c2416-irq";
        };
+        clocks: clock-controller@0x4c000000 {
+                compatible = "samsung,s3c2416-clock";
+                reg = <0x4c000000 0x40>;
+                #clock-cells = <1>;
+        };
        pinctrl@56000000 {
                compatible = "samsung,s3c2416-pinctrl";
        };
+        timer@51000000 {
+                clocks = <&clocks PCLK_PWM>;
+                clock-names = "timers";
+        };
        serial@50000000 {
                compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
+                                <&clocks SCLK_UART>;
        };
        serial@50004000 {
                compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
+                                <&clocks SCLK_UART>;
        };
        serial@50008000 {
                compatible = "samsung,s3c2440-uart";
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
+                                <&clocks SCLK_UART>;
        };
        serial@5000C000 {
                compatible = "samsung,s3c2440-uart";
                reg = <0x5000C000 0x4000>;
                interrupts = <1 18 24 4>, <1 18 25 4>;
+                clock-names = "uart", "clk_uart_baud2",
+                                "clk_uart_baud3";
+                clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
+                                <&clocks SCLK_UART>;
                status = "disabled";
        };
@@ -55,6 +83,10 @@
                compatible = "samsung,s3c6410-sdhci";
                reg = <0x4AC00000 0x100>;
                interrupts = <0 0 21 3>;
+                clock-names = "hsmmc", "mmc_busclk.0",
+                                "mmc_busclk.2";
+                clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
+                                <&clocks MUX_HSMMC0>;
                status = "disabled";
        };
@@ -62,18 +94,28 @@
                compatible = "samsung,s3c6410-sdhci";
                reg = <0x4A800000 0x100>;
                interrupts = <0 0 20 3>;
+                clock-names = "hsmmc", "mmc_busclk.0",
+                                "mmc_busclk.2";
+                clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
+                                <&clocks MUX_HSMMC1>;
                status = "disabled";
        };
        watchdog@53000000 {
                interrupts = <1 9 27 3>;
+                clocks = <&clocks PCLK_WDT>;
+                clock-names = "watchdog";
        };
        rtc@57000000 {
                compatible = "samsung,s3c2416-rtc";
+                clocks = <&clocks PCLK_RTC>;
+                clock-names = "rtc";
        };
        i2c@54000000 {
                compatible = "samsung,s3c2440-i2c";
+                clocks = <&clocks PCLK_I2C0>;
+                clock-names = "i2c";
        };
 };
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index eabcfdbb403a..e0b15a6e8897 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -13,7 +13,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 / {
        model = "Atmel SAMA5D3 family SoC";
@@ -58,6 +58,18 @@
                reg = <0x20000000 0x8000000>;
        };
+        slow_xtal: slow_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
+        main_xtal: main_xtal {
+                compatible = "fixed-clock";
+                #clock-cells = <0>;
+                clock-frequency = <0>;
+        };
        clocks {
                adc_op_clk: adc_op_clk{
                        compatible = "fixed-clock";
@@ -113,6 +125,9 @@
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf0008000 0x4000>;
                                interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
+                                dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
+                                       <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
                                clocks = <&ssc0_clk>;
@@ -231,6 +246,9 @@
                                compatible = "atmel,at91sam9g45-ssc";
                                reg = <0xf800c000 0x4000>;
                                interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
+                                dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
+                                       <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
+                                dma-names = "tx", "rx";
                                pinctrl-names = "default";
                                pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
                                clocks = <&ssc1_clk>;
@@ -577,6 +595,84 @@
                                        };
                                };
+                                pwm0 {
+                                        pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
+                                        };
+                                        pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GTX0 */
+                                        };
+                                        pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
+                                        };
+                                        pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GTX1 */
+                                        };
+                                        pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
+                                        };
+                                        pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GRX0 */
+                                        };
+                                        pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
+                                        };
+                                        pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
+                                        };
+                                        pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GRX1 */
+                                        };
+                                        pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
+                                                atmel,pins =
+                                                        <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
+                                        };
+                                        pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GTXCK */
+                                        };
+                                        pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* conflicts with MCI0_DA4 and TIOA0 */
+                                        };
+                                        pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;  /* conflicts with GTXEN */
+                                        };
+                                        pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* conflicts with MCI0_DA5 and TIOB0 */
+                                        };
+                                        pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
+                                        };
+                                        pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* conflicts with MCI0_DA6 and TCLK0 */
+                                        };
+                                        pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
+                                                atmel,pins =
+                                                        <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
+                                        };
+                                        pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
+                                                atmel,pins =
+                                                        <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* conflicts with MCI0_DA7 */
+                                        };
+                                };
                                spi0 {
                                        pinctrl_spi0: spi0-0 {
                                                atmel,pins =
@@ -749,18 +845,29 @@
                                #size-cells = <0>;
                                #interrupt-cells = <1>;
-                                clk32k: slck {
+                                main_rc_osc: main_rc_osc {
-                                        compatible = "fixed-clock";
+                                        compatible = "atmel,at91sam9x5-clk-main-rc-osc";
                                        #clock-cells = <0>;
-                                        clock-frequency = <32768>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCRCS>;
+                                        clock-frequency = <12000000>;
+                                        clock-accuracy = <50000000>;
                                };
-                                main: mainck {
+                                main_osc: main_osc {
-                                        compatible = "atmel,at91rm9200-clk-main";
+                                        compatible = "atmel,at91rm9200-clk-main-osc";
                                        #clock-cells = <0>;
                                        interrupt-parent = <&pmc>;
                                        interrupts = <AT91_PMC_MOSCS>;
-                                        clocks = <&clk32k>;
+                                        clocks = <&main_xtal>;
+                                };
+                                main: mainck {
+                                        compatible = "atmel,at91sam9x5-clk-main";
+                                        #clock-cells = <0>;
+                                        interrupt-parent = <&pmc>;
+                                        interrupts = <AT91_PMC_MOSCSELS>;
+                                        clocks = <&main_rc_osc &main_osc>;
                                };
                                plla: pllack {
@@ -1089,6 +1196,32 @@
                                status = "disabled";
                        };
+                        sckc@fffffe50 {
+                                compatible = "atmel,at91sam9x5-sckc";
+                                reg = <0xfffffe50 0x4>;
+                                slow_rc_osc: slow_rc_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
+                                        #clock-cells = <0>;
+                                        clock-frequency = <32768>;
+                                        clock-accuracy = <50000000>;
+                                        atmel,startup-time-usec = <75>;
+                                };
+                                slow_osc: slow_osc {
+                                        compatible = "atmel,at91sam9x5-clk-slow-osc";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_xtal>;
+                                        atmel,startup-time-usec = <1200000>;
+                                };
+                                clk32k: slowck {
+                                        compatible = "atmel,at91sam9x5-clk-slow";
+                                        #clock-cells = <0>;
+                                        clocks = <&slow_rc_osc &slow_osc>;
+                                };
+                        };
                        rtc@fffffeb0 {
                                compatible = "atmel,at91rm9200-rtc";
                                reg = <0xfffffeb0 0x30>;
diff --git a/arch/arm/boot/dts/sama5d3_mci2.dtsi b/arch/arm/boot/dts/sama5d3_mci2.dtsi
index b029fe7ef17a..1b02208ea6ff 100644
--- a/arch/arm/boot/dts/sama5d3_mci2.dtsi
+++ b/arch/arm/boot/dts/sama5d3_mci2.dtsi
@@ -9,7 +9,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 / {
        ahb {
diff --git a/arch/arm/boot/dts/sama5d3_tcb1.dtsi b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
index 382b04431f66..02848453ca0c 100644
--- a/arch/arm/boot/dts/sama5d3_tcb1.dtsi
+++ b/arch/arm/boot/dts/sama5d3_tcb1.dtsi
@@ -9,7 +9,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 / {
        aliases {
diff --git a/arch/arm/boot/dts/sama5d3_uart.dtsi b/arch/arm/boot/dts/sama5d3_uart.dtsi
index a9fa75e41652..7a8d4c6115f7 100644
--- a/arch/arm/boot/dts/sama5d3_uart.dtsi
+++ b/arch/arm/boot/dts/sama5d3_uart.dtsi
@@ -9,7 +9,7 @@
 #include <dt-bindings/pinctrl/at91.h>
 #include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/clk/at91.h>
+#include <dt-bindings/clock/at91.h>
 / {
        aliases {
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index f55ed072c8e6..b0b1331c1974 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,6 +18,14 @@
                reg = <0x20000000 0x20000000>;
        };
+        slow_xtal {
+                clock-frequency = <32768>;
+        };
+        main_xtal {
+                clock-frequency = <12000000>;
+        };
        ahb {
                apb {
                        spi0: spi@f0004000 {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index dba739b6ef36..306eef0f97ef 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -32,6 +32,10 @@
                                };
                        };
+                        ssc0: ssc@f0008000 {
+                                atmel,clk-from-rk-pin;
+                        };
                        /*
                         * i2c0 conflicts with ISI:
                         * disable it to allow the use of ISI
@@ -156,7 +160,7 @@
        };
        sound {
-                compatible = "atmel,sama5d3ek-wm8904";
+                compatible = "atmel,asoc-wm8904";
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_pck0_as_audio_mck>;
@@ -166,9 +170,12 @@
                        "Headphone Jack", "HPOUTR",
                        "IN2L", "Line In Jack",
                        "IN2R", "Line In Jack",
+                        "MICBIAS", "IN1L",
                        "IN1L", "Mic";
                atmel,ssc-controller = <&ssc0>;
                atmel,audio-codec = <&wm8904>;
+                status = "disabled";
        };
 };
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index eb8886b535e4..a99171c8a782 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -14,6 +14,7 @@
 /dts-v1/;
 #include "sh73a0.dtsi"
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 / {
@@ -112,43 +113,43 @@
                back-key {
                        gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
-                        linux,code = <158>;
+                        linux,code = <KEY_BACK>;
                        label = "SW3";
                };
                right-key {
                        gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
-                        linux,code = <106>;
+                        linux,code = <KEY_RIGHT>;
                        label = "SW2-R";
                };
                left-key {
                        gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
-                        linux,code = <105>;
+                        linux,code = <KEY_LEFT>;
                        label = "SW2-L";
                };
                enter-key {
                        gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
-                        linux,code = <28>;
+                        linux,code = <KEY_ENTER>;
                        label = "SW2-P";
                };
                up-key {
                        gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
-                        linux,code = <103>;
+                        linux,code = <KEY_UP>;
                        label = "SW2-U";
                };
                down-key {
                        gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
-                        linux,code = <108>;
+                        linux,code = <KEY_DOWN>;
                        label = "SW2-D";
                };
                home-key {
                        gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
-                        linux,code = <102>;
+                        linux,code = <KEY_HOME>;
                        label = "SW1";
                };
        };
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 56fc214e6d2c..4676f25e87a7 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -15,7 +15,8 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-/include/ "skeleton.dtsi"
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr.h>
 / {
        #address-cells = <1>;
@@ -75,7 +76,14 @@
                        pdma: pdma@ffe01000 {
                                compatible = "arm,pl330", "arm,primecell";
                                reg = <0xffe01000 0x1000>;
-                                interrupts = <0 180 4>;
+                                interrupts = <0 104 4>,
+                                             <0 105 4>,
+                                             <0 106 4>,
+                                             <0 107 4>,
+                                             <0 108 4>,
+                                             <0 109 4>,
+                                             <0 110 4>,
+                                             <0 111 4>;
                                #dma-cells = <1>;
                                #dma-channels = <8>;
                                #dma-requests = <32>;
@@ -84,6 +92,22 @@
                        };
                };
+                can0: can@ffc00000 {
+                        compatible = "bosch,d_can";
+                        reg = <0xffc00000 0x1000>;
+                        interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
+                        clocks = <&can0_clk>;
+                        status = "disabled";
+                };
+                can1: can@ffc01000 {
+                        compatible = "bosch,d_can";
+                        reg = <0xffc01000 0x1000>;
+                        interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
+                        clocks = <&can1_clk>;
+                        status = "disabled";
+                };
                clkmgr@ffd04000 {
                                compatible = "altr,clk-mgr";
                                reg = <0xffd04000 0x1000>;
@@ -124,7 +148,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                        fixed-divider = <2>;
+                                                        div-reg = <0xe0 0 9>;
                                                        reg = <0x48>;
                                                };
@@ -132,7 +156,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                        fixed-divider = <4>;
+                                                        div-reg = <0xe4 0 9>;
                                                        reg = <0x4C>;
                                                };
@@ -140,7 +164,7 @@
                                                        #clock-cells = <0>;
                                                        compatible = "altr,socfpga-perip-clk";
                                                        clocks = <&main_pll>;
-                                                        fixed-divider = <4>;
+                                                        div-reg = <0xe8 0 9>;
                                                        reg = <0x50>;
                                                };
@@ -460,6 +484,8 @@
                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
                        clocks = <&emac0_clk>;
                        clock-names = "stmmaceth";
+                        resets = <&rst EMAC0_RESET>;
+                        reset-names = "stmmaceth";
                        status = "disabled";
                };
@@ -472,9 +498,111 @@
                        mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
                        clocks = <&emac1_clk>;
                        clock-names = "stmmaceth";
+                        resets = <&rst EMAC1_RESET>;
+                        reset-names = "stmmaceth";
+                        status = "disabled";
+                };
+                i2c0: i2c@ffc04000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc04000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        interrupts = <0 158 0x4>;
+                        status = "disabled";
+                };
+                i2c1: i2c@ffc05000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc05000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        interrupts = <0 159 0x4>;
                        status = "disabled";
                };
+                i2c2: i2c@ffc06000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc06000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        interrupts = <0 160 0x4>;
+                        status = "disabled";
+                };
+                i2c3: i2c@ffc07000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,designware-i2c";
+                        reg = <0xffc07000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        interrupts = <0 161 0x4>;
+                        status = "disabled";
+                };
+                gpio@ff708000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xff708000 0x1000>;
+                        clocks = <&per_base_clk>;
+                        status = "disabled";
+                        gpio0: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 164 4>;
+                        };
+                };
+                gpio@ff709000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xff709000 0x1000>;
+                        clocks = <&per_base_clk>;
+                        status = "disabled";
+                        gpio1: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <29>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 165 4>;
+                        };
+                };
+                gpio@ff70a000 {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        compatible = "snps,dw-apb-gpio";
+                        reg = <0xff70a000 0x1000>;
+                        clocks = <&per_base_clk>;
+                        status = "disabled";
+                        gpio2: gpio-controller@0 {
+                                compatible = "snps,dw-apb-gpio-port";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                                snps,nr-gpios = <27>;
+                                reg = <0>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                interrupts = <0 166 4>;
+                        };
+                };
                L2: l2-cache@fffef000 {
                        compatible = "arm,pl310-cache";
                        reg = <0xfffef000 0x1000>;
@@ -508,24 +636,32 @@
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 167 4>;
                        reg = <0xffc08000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        clock-names = "timer";
                };
                timer1: timer1@ffc09000 {
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 168 4>;
                        reg = <0xffc09000 0x1000>;
+                        clocks = <&l4_sp_clk>;
+                        clock-names = "timer";
                };
                timer2: timer2@ffd00000 {
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 169 4>;
                        reg = <0xffd00000 0x1000>;
+                        clocks = <&osc1>;
+                        clock-names = "timer";
                };
                timer3: timer3@ffd01000 {
                        compatible = "snps,dw-apb-timer";
                        interrupts = <0 170 4>;
                        reg = <0xffd01000 0x1000>;
+                        clocks = <&osc1>;
+                        clock-names = "timer";
                };
                uart0: serial0@ffc02000 {
@@ -534,6 +670,7 @@
                        interrupts = <0 162 4>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                        clocks = <&l4_sp_clk>;
                };
                uart1: serial1@ffc03000 {
@@ -542,13 +679,58 @@
                        interrupts = <0 163 4>;
                        reg-shift = <2>;
                        reg-io-width = <4>;
+                        clocks = <&l4_sp_clk>;
                };
-                rstmgr@ffd05000 {
+                rst: rstmgr@ffd05000 {
                        compatible = "altr,rst-mgr";
                        reg = <0xffd05000 0x1000>;
                };
+                usbphy0: usbphy@0 {
+                        #phy-cells = <0>;
+                        compatible = "usb-nop-xceiv";
+                        status = "okay";
+                };
+                usb0: usb@ffb00000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb00000 0xffff>;
+                        interrupts = <0 125 4>;
+                        clocks = <&usb_mp_clk>;
+                        clock-names = "otg";
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+                usb1: usb@ffb40000 {
+                        compatible = "snps,dwc2";
+                        reg = <0xffb40000 0xffff>;
+                        interrupts = <0 128 4>;
+                        clocks = <&usb_mp_clk>;
+                        clock-names = "otg";
+                        phys = <&usbphy0>;
+                        phy-names = "usb2-phy";
+                        status = "disabled";
+                };
+                watchdog0: watchdog@ffd02000 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd02000 0x1000>;
+                        interrupts = <0 171 4>;
+                        clocks = <&osc1>;
+                        status = "disabled";
+                };
+                watchdog1: watchdog@ffd03000 {
+                        compatible = "snps,dw-wdt";
+                        reg = <0xffd03000 0x1000>;
+                        interrupts = <0 172 4>;
+                        clocks = <&osc1>;
+                        status = "disabled";
+                };
                sysmgr: sysmgr@ffd08000 {
                        compatible = "altr,sys-mgr", "syscon";
                        reg = <0xffd08000 0x4000>;
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 6c87b7070ca7..12d1c2ccaf5b 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi
@@ -15,7 +15,7 @@
 */
 /dts-v1/;
-/include/ "socfpga.dtsi"
+#include "socfpga.dtsi"
 / {
        soc {
@@ -38,32 +38,8 @@
                        };
                };
-                serial0@ffc02000 {
-                        clock-frequency = <100000000>;
-                };
-                serial1@ffc03000 {
-                        clock-frequency = <100000000>;
-                };
                sysmgr@ffd08000 {
                        cpu1-start-addr = <0xffd080c4>;
                };
-                timer0@ffc08000 {
-                        clock-frequency = <100000000>;
-                };
-                timer1@ffc09000 {
-                        clock-frequency = <100000000>;
-                };
-                timer2@ffd00000 {
-                        clock-frequency = <25000000>;
-                };
-                timer3@ffd01000 {
-                        clock-frequency = <25000000>;
-                };
        };
 };
diff --git a/arch/arm/boot/dts/socfpga_arria5_socdk.dts b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
index a87ee1c07661..d532d171e391 100644
--- a/arch/arm/boot/dts/socfpga_arria5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_arria5_socdk.dts
@@ -15,7 +15,7 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-/include/ "socfpga_arria5.dtsi"
+#include "socfpga_arria5.dtsi"
 / {
        model = "Altera SOCFPGA Arria V SoC Development Kit";
@@ -59,3 +59,22 @@
        rxdv-skew-ps = <0>;
        rxc-skew-ps = <2000>;
 };
+&i2c0 {
+        status = "okay";
+        eeprom@51 {
+                compatible = "atmel,24c32";
+                reg = <0x51>;
+                pagesize = <32>;
+        };
+        rtc@68 {
+                compatible = "dallas,ds1339";
+                reg = <0x68>;
+        };
+};
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index ca41b0ebf461..bf511828729f 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
@@ -16,7 +16,7 @@
 */
 /dts-v1/;
-/include/ "socfpga.dtsi"
+#include "socfpga.dtsi"
 / {
        soc {
@@ -45,30 +45,6 @@
                        status = "okay";
                };
-                timer0@ffc08000 {
-                        clock-frequency = <100000000>;
-                };
-                timer1@ffc09000 {
-                        clock-frequency = <100000000>;
-                };
-                timer2@ffd00000 {
-                        clock-frequency = <25000000>;
-                };
-                timer3@ffd01000 {
-                        clock-frequency = <25000000>;
-                };
-                serial0@ffc02000 {
-                        clock-frequency = <100000000>;
-                };
-                serial1@ffc03000 {
-                        clock-frequency = <100000000>;
-                };
                sysmgr@ffd08000 {
                        cpu1-start-addr = <0xffd080c4>;
                };
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
index ae16d975196d..45de1514af0a 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socdk.dts
@@ -15,7 +15,7 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-/include/ "socfpga_cyclone5.dtsi"
+#include "socfpga_cyclone5.dtsi"
 / {
        model = "Altera SOCFPGA Cyclone V SoC Development Kit";
@@ -52,3 +52,22 @@
        rxdv-skew-ps = <0>;
        rxc-skew-ps = <2000>;
 };
+&i2c0 {
+        status = "okay";
+        eeprom@51 {
+                compatible = "atmel,24c32";
+                reg = <0x51>;
+                pagesize = <32>;
+        };
+        rtc@68 {
+                compatible = "dallas,ds1339";
+                reg = <0x68>;
+        };
+};
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
index b79e2a2bf175..d26f155f5fd9 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
+++ b/arch/arm/boot/dts/socfpga_cyclone5_sockit.dts
@@ -15,7 +15,7 @@
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */
-/include/ "socfpga_cyclone5.dtsi"
+#include "socfpga_cyclone5.dtsi"
 / {
        model = "Terasic SoCkit";
@@ -52,3 +52,7 @@
        rxdv-skew-ps = <0>;
        rxc-skew-ps = <2000>;
 };
+&usb1 {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
new file mode 100644
index 000000000000..a1814b457450
--- /dev/null
+++ b/arch/arm/boot/dts/socfpga_cyclone5_socrates.dts
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include "socfpga_cyclone5.dtsi"
+/ {
+        model = "EBV SOCrates";
+        compatible = "ebv,socrates", "altr,socfpga-cyclone5", "altr,socfpga";
+        chosen {
+                bootargs = "console=ttyS0,115200";
+        };
+        memory {
+                name = "memory";
+                device_type = "memory";
+                reg = <0x0 0x40000000>; /* 1GB */
+        };
+};
+&gmac1 {
+        status = "okay";
+};
+&i2c0 {
+        status = "okay";
+        rtc: rtc@68 {
+                compatible = "stm,m41t82";
+                reg = <0x68>;
+        };
+};
+&mmc {
+        status = "okay";
+};
diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts
index 87d6f759a9c1..09792b411110 100644
--- a/arch/arm/boot/dts/socfpga_vt.dts
+++ b/arch/arm/boot/dts/socfpga_vt.dts
@@ -16,7 +16,7 @@
 */
 /dts-v1/;
-/include/ "socfpga.dtsi"
+#include "socfpga.dtsi"
 / {
        model = "Altera SOCFPGA VT";
diff --git a/arch/arm/boot/dts/ste-ccu8540.dts b/arch/arm/boot/dts/ste-ccu8540.dts
index 7f3baf51a3a9..32dd55e5f4e6 100644
--- a/arch/arm/boot/dts/ste-ccu8540.dts
+++ b/arch/arm/boot/dts/ste-ccu8540.dts
@@ -18,6 +18,7 @@
        compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
        memory@0 {
+                device_type = "memory";
                reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
        };
diff --git a/arch/arm/boot/dts/ste-ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts
index 229508750890..651c56d400a4 100644
--- a/arch/arm/boot/dts/ste-ccu9540.dts
+++ b/arch/arm/boot/dts/ste-ccu9540.dts
@@ -38,8 +38,8 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <4>;
-                        mmc-cap-sd-highspeed;
+                        cap-sd-highspeed;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
                        cd-gpios  = <&gpio7 6 0x4>; // 230
@@ -63,7 +63,7 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
                        status = "okay";
diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 6cb9b68e2188..bf8f0eddc2c0 100644
--- a/arch/arm/boot/dts/ste-href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -116,8 +116,15 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <4>;
-                        mmc-cap-sd-highspeed;
+                        cap-sd-highspeed;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
+                        sd-uhs-sdr12;
+                        sd-uhs-sdr25;
+                        full-pwr-cycle;
+                        st,sig-dir-dat0;
+                        st,sig-dir-dat2;
+                        st,sig-dir-cmd;
+                        st,sig-pin-fbclk;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
                        vqmmc-supply = <&vmmci>;
                        pinctrl-names = "default", "sleep";
@@ -132,6 +139,7 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <4>;
+                        non-removable;
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdi1_default_mode>;
                        pinctrl-1 = <&sdi1_sleep_mode>;
@@ -144,7 +152,9 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
+                        non-removable;
+                        vmmc-supply = <&db8500_vsmps2_reg>;
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdi2_default_mode>;
                        pinctrl-1 = <&sdi2_sleep_mode>;
@@ -157,7 +167,8 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
+                        non-removable;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdi4_default_mode>;
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index 5acc0449676a..d316c955bd5f 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -840,8 +840,8 @@
                        interrupts = <22>;
                        max-frequency = <48000000>;
                        bus-width = <4>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
-                        mmc-cap-sd-highspeed;
+                        cap-sd-highspeed;
                        cd-gpios = <&gpio3 15 0x1>;
                        cd-inverted;
                        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index a2f632d0be2a..474ef83229cd 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -156,7 +156,7 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <4>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux3_reg>;
                        vqmmc-supply = <&vmmci>;
                        pinctrl-names = "default", "sleep";
@@ -195,7 +195,7 @@
                        arm,primecell-periphid = <0x10480180>;
                        max-frequency = <100000000>;
                        bus-width = <8>;
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
                        vmmc-supply = <&ab8500_ldo_aux2_reg>;
                        pinctrl-names = "default", "sleep";
                        pinctrl-0 = <&sdi4_default_mode>;
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 6fe688e9e4da..82a661677e97 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -442,8 +442,8 @@
                        clock-names = "apb_pclk", "mclk";
                        max-frequency = <24000000>;
                        bus-width = <4>; // SD-card slot
-                        mmc-cap-mmc-highspeed;
+                        cap-mmc-highspeed;
-                        mmc-cap-sd-highspeed;
+                        cap-sd-highspeed;
                        cd-gpios = <&gpio 12 0x4>;
                        cd-inverted;
                        vmmc-supply = <&ab3100_ldo_g_reg>;
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
new file mode 100644
index 000000000000..fe69f92e5f82
--- /dev/null
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih407.dtsi"
+/ {
+        model = "STiH407 B2120";
+        compatible = "st,stih407-b2120", "st,stih407";
+        chosen {
+                bootargs = "console=ttyAS0,115200";
+                linux,stdout-path = &sbc_serial0;
+        };
+        memory {
+                device_type = "memory";
+                reg = <0x40000000 0x80000000>;
+        };
+        aliases {
+                ttyAS0 = &sbc_serial0;
+        };
+        soc {
+                sbc_serial0: serial@9530000 {
+                        status = "okay";
+                };
+                leds {
+                        compatible = "gpio-leds";
+                        red {
+                                #gpio-cells = <2>;
+                                label = "Front Panel LED";
+                                gpios = <&pio4 1 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        green {
+                                #gpio-cells = <2>;
+                                gpios = <&pio1 3 0>;
+                                default-state = "off";
+                        };
+                };
+                i2c@9842000 {
+                        status = "okay";
+                };
+                i2c@9843000 {
+                        status = "okay";
+                };
+                i2c@9844000 {
+                        status = "okay";
+                };
+                i2c@9845000 {
+                        status = "okay";
+                };
+                i2c@9540000 {
+                        status = "okay";
+                };
+                /* SSC11 to HDMI */
+                i2c@9541000 {
+                        status = "okay";
+                        /* HDMI V1.3a supports Standard mode only */
+                        clock-frequency = <100000>;
+                        st,i2c-min-scl-pulse-width-us = <0>;
+                        st,i2c-min-sda-pulse-width-us = <5>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi b/arch/arm/boot/dts/stih407-clock.dtsi
new file mode 100644
index 000000000000..800f46f009f3
--- /dev/null
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+        clocks {
+                /*
+                 * Fixed 30MHz oscillator inputs to SoC
+                 */
+                clk_sysin: clk-sysin {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <30000000>;
+                };
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: arm-periph-clk {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <600000000>;
+                };
+                /*
+                 * Bootloader initialized system infrastructure clock for
+                 * serial devices.
+                 */
+                clk_ext2f_a9: clockgen-c0@13 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-clock";
+                        clock-frequency = <200000000>;
+                        clock-output-names = "clk-s-icn-reg-0";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
new file mode 100644
index 000000000000..402844cb3152
--- /dev/null
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -0,0 +1,615 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+/ {
+        aliases {
+                /* 0-5: PIO_SBC */
+                gpio0 = &pio0;
+                gpio1 = &pio1;
+                gpio2 = &pio2;
+                gpio3 = &pio3;
+                gpio4 = &pio4;
+                gpio5 = &pio5;
+                /* 10-19: PIO_FRONT0 */
+                gpio6 = &pio10;
+                gpio7 = &pio11;
+                gpio8 = &pio12;
+                gpio9 = &pio13;
+                gpio10 = &pio14;
+                gpio11 = &pio15;
+                gpio12 = &pio16;
+                gpio13 = &pio17;
+                gpio14 = &pio18;
+                gpio15 = &pio19;
+                /* 20: PIO_FRONT1 */
+                gpio16 = &pio20;
+                /* 30-35: PIO_REAR */
+                gpio17 = &pio30;
+                gpio18 = &pio31;
+                gpio19 = &pio32;
+                gpio20 = &pio33;
+                gpio21 = &pio34;
+                gpio22 = &pio35;
+                /* 40-42: PIO_FLASH */
+                gpio23 = &pio40;
+                gpio24 = &pio41;
+                gpio25 = &pio42;
+        };
+        soc {
+                pin-controller-sbc {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stih407-sbc-pinctrl";
+                        st,syscfg = <&syscfg_sbc>;
+                        reg = <0x0961f080 0x4>;
+                        reg-names = "irqmux";
+                        interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
+                        interrupts-names = "irqmux";
+                        ranges = <0 0x09610000 0x6000>;
+                        pio0: gpio@09610000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x100>;
+                                st,bank-name = "PIO0";
+                        };
+                        pio1: gpio@09611000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x100>;
+                                st,bank-name = "PIO1";
+                        };
+                        pio2: gpio@09612000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x100>;
+                                st,bank-name = "PIO2";
+                        };
+                        pio3: gpio@09613000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x3000 0x100>;
+                                st,bank-name = "PIO3";
+                        };
+                        pio4: gpio@09614000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x4000 0x100>;
+                                st,bank-name = "PIO4";
+                        };
+                        pio5: gpio@09615000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x5000 0x100>;
+                                st,bank-name = "PIO5";
+                        };
+                        rc {
+                                pinctrl_ir: ir0 {
+                                        st,pins {
+                                                ir = <&pio4 0 ALT2 IN>;
+                                        };
+                                };
+                        };
+                        /* SBC_ASC0 - UART10 */
+                        sbc_serial0 {
+                                pinctrl_sbc_serial0: sbc_serial0-0 {
+                                        st,pins {
+                                                tx = <&pio3 4 ALT1 OUT>;
+                                                rx = <&pio3 5 ALT1 IN>;
+                                        };
+                                };
+                        };
+                        /* SBC_ASC1 - UART11 */
+                        sbc_serial1 {
+                                pinctrl_sbc_serial1: sbc_serial1-0 {
+                                        st,pins {
+                                                tx = <&pio2 6 ALT3 OUT>;
+                                                rx = <&pio2 7 ALT3 IN>;
+                                        };
+                                };
+                        };
+                        i2c10 {
+                                pinctrl_i2c10_default: i2c10-default {
+                                        st,pins {
+                                                sda = <&pio4 6 ALT1 BIDIR>;
+                                                scl = <&pio4 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        i2c11 {
+                                pinctrl_i2c11_default: i2c11-default {
+                                        st,pins {
+                                                sda = <&pio5 1 ALT1 BIDIR>;
+                                                scl = <&pio5 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        keyscan {
+                                pinctrl_keyscan: keyscan {
+                                        st,pins {
+                                                keyin0 = <&pio4 0 ALT6 IN>;
+                                                keyin1 = <&pio4 5 ALT4 IN>;
+                                                keyin2 = <&pio0 4 ALT2 IN>;
+                                                keyin3 = <&pio2 6 ALT2 IN>;
+                                                keyout0 = <&pio4 6 ALT4 OUT>;
+                                                keyout1 = <&pio1 7 ALT2 OUT>;
+                                                keyout2 = <&pio0 6 ALT2 OUT>;
+                                                keyout3 = <&pio2 7 ALT2 OUT>;
+                                        };
+                                };
+                        };
+                        gmac1 {
+                                /*
+                                 * Almost all the boards based on STiH407 SoC have an embedded
+                                 * switch where the mdio/mdc have been used for managing the SMI
+                                 * iface via I2C. For this reason these lines can be allocated
+                                 * by using dedicated configuration (in case of there will be a
+                                 * standard PHY transceiver on-board).
+                                 */
+                                pinctrl_rgmii1: rgmii1-0 {
+                                        st,pins {
+                                                txd0 = <&pio0 0 ALT1 OUT DE_IO 0 CLK_A>;
+                                                txd1 = <&pio0 1 ALT1 OUT DE_IO 0 CLK_A>;
+                                                txd2 = <&pio0 2 ALT1 OUT DE_IO 0 CLK_A>;
+                                                txd3 = <&pio0 3 ALT1 OUT DE_IO 0 CLK_A>;
+                                                txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
+                                                rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>;
+                                                rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>;
+                                                rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>;
+                                                rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>;
+                                                rxdv = <&pio2 0 ALT1 IN DE_IO 0 CLK_A>;
+                                                rxclk = <&pio2 2 ALT1 IN NICLK 500 CLK_A>;
+                                                clk125 = <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
+                                                phyclk = <&pio2 3 ALT4 OUT NICLK 1750 CLK_B>;
+                                        };
+                                };
+                                pinctrl_rgmii1_mdio: rgmii1-mdio {
+                                        st,pins {
+                                                mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
+                                                mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                                mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+                                        };
+                                };
+                                pinctrl_mii1: mii1 {
+                                        st,pins {
+                                                txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
+                                                txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
+                                                col = <&pio0 7 ALT1 IN BYPASS 1000>;
+                                                mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
+                                                mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
+                                                crs = <&pio1 2 ALT1 IN BYPASS 1000>;
+                                                mdint = <&pio1 3 ALT1 IN BYPASS 0>;
+                                                rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
+                                                rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
+                                                phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
+                                        };
+                                };
+                        };
+                        pwm1 {
+                                pinctrl_pwm1_chan0_default: pwm1-0-default {
+                                        st,pins {
+                                                pwm-out = <&pio3 0 ALT1 OUT>;
+                                        };
+                                };
+                                pinctrl_pwm1_chan1_default: pwm1-1-default {
+                                        st,pins {
+                                                pwm-out = <&pio4 4 ALT1 OUT>;
+                                        };
+                                };
+                                pinctrl_pwm1_chan2_default: pwm1-2-default {
+                                        st,pins {
+                                                pwm-out = <&pio4 6 ALT3 OUT>;
+                                        };
+                                };
+                                pinctrl_pwm1_chan3_default: pwm1-3-default {
+                                        st,pins {
+                                                pwm-out = <&pio4 7 ALT3 OUT>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-front0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stih407-front-pinctrl";
+                        st,syscfg = <&syscfg_front>;
+                        reg = <0x0920f080 0x4>;
+                        reg-names = "irqmux";
+                        interrupts = <GIC_SPI 189 IRQ_TYPE_NONE>;
+                        interrupts-names = "irqmux";
+                        ranges = <0 0x09200000 0x10000>;
+                        pio10: pio@09200000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x100>;
+                                st,bank-name = "PIO10";
+                        };
+                        pio11: pio@09201000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x100>;
+                                st,bank-name = "PIO11";
+                        };
+                        pio12: pio@09202000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x100>;
+                                st,bank-name = "PIO12";
+                        };
+                        pio13: pio@09203000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x3000 0x100>;
+                                st,bank-name = "PIO13";
+                        };
+                        pio14: pio@09204000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x4000 0x100>;
+                                st,bank-name = "PIO14";
+                        };
+                        pio15: pio@09205000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x5000 0x100>;
+                                st,bank-name = "PIO15";
+                        };
+                        pio16: pio@09206000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x6000 0x100>;
+                                st,bank-name = "PIO16";
+                        };
+                        pio17: pio@09207000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x7000 0x100>;
+                                st,bank-name = "PIO17";
+                        };
+                        pio18: pio@09208000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x8000 0x100>;
+                                st,bank-name = "PIO18";
+                        };
+                        pio19: pio@09209000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x9000 0x100>;
+                                st,bank-name = "PIO19";
+                        };
+                        /* Comms */
+                        serial0 {
+                                pinctrl_serial0: serial0-0 {
+                                        st,pins {
+                                                tx = <&pio17 0 ALT1 OUT>;
+                                                rx = <&pio17 1 ALT1 IN>;
+                                        };
+                                };
+                        };
+                        serial1 {
+                                pinctrl_serial1: serial1-0 {
+                                        st,pins {
+                                                tx = <&pio16 0 ALT1 OUT>;
+                                                rx = <&pio16 1 ALT1 IN>;
+                                        };
+                                };
+                        };
+                        serial2 {
+                                pinctrl_serial2: serial2-0 {
+                                        st,pins {
+                                                tx = <&pio15 0 ALT1 OUT>;
+                                                rx = <&pio15 1 ALT1 IN>;
+                                        };
+                                };
+                        };
+                        mmc1 {
+                                pinctrl_sd1: sd1-0 {
+                                        st,pins {
+                                                sd_clk = <&pio19 3 ALT5 BIDIR NICLK 0 CLK_B>;
+                                                sd_cmd = <&pio19 2 ALT5 BIDIR_PU BYPASS 0>;
+                                                sd_dat0 = <&pio19 4 ALT5 BIDIR_PU BYPASS 0>;
+                                                sd_dat1 = <&pio19 5 ALT5 BIDIR_PU BYPASS 0>;
+                                                sd_dat2 = <&pio19 6 ALT5 BIDIR_PU BYPASS 0>;
+                                                sd_dat3 = <&pio19 7 ALT5 BIDIR_PU BYPASS 0>;
+                                                sd_led = <&pio16 6 ALT6 OUT>;
+                                                sd_pwren = <&pio16 7 ALT6 OUT>;
+                                                sd_cd = <&pio19 0 ALT6 IN>;
+                                                sd_wp = <&pio19 1 ALT6 IN>;
+                                        };
+                                };
+                        };
+                        i2c0 {
+                                pinctrl_i2c0_default: i2c0-default {
+                                        st,pins {
+                                                sda = <&pio10 6 ALT2 BIDIR>;
+                                                scl = <&pio10 5 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
+                        i2c1 {
+                                pinctrl_i2c1_default: i2c1-default {
+                                        st,pins {
+                                                sda = <&pio11 1 ALT2 BIDIR>;
+                                                scl = <&pio11 0 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
+                        i2c2 {
+                                pinctrl_i2c2_default: i2c2-default {
+                                        st,pins {
+                                                sda = <&pio15 6 ALT2 BIDIR>;
+                                                scl = <&pio15 5 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
+                        i2c3 {
+                                pinctrl_i2c3_default: i2c3-default {
+                                        st,pins {
+                                                sda = <&pio18 6 ALT1 BIDIR>;
+                                                scl = <&pio18 5 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        spi0 {
+                                pinctrl_spi0_default: spi0-default {
+                                        st,pins {
+                                                mtsr = <&pio12 6 ALT2 BIDIR>;
+                                                mrst = <&pio12 7 ALT2 BIDIR>;
+                                                scl = <&pio12 5 ALT2 BIDIR>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-front1 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stih407-front-pinctrl";
+                        st,syscfg = <&syscfg_front>;
+                        reg = <0x0921f080 0x4>;
+                        reg-names = "irqmux";
+                        interrupts = <GIC_SPI 190 IRQ_TYPE_NONE>;
+                        interrupts-names = "irqmux";
+                        ranges = <0 0x09210000 0x10000>;
+                        pio20: pio@09210000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x100>;
+                                st,bank-name = "PIO20";
+                        };
+                };
+                pin-controller-rear {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stih407-rear-pinctrl";
+                        st,syscfg = <&syscfg_rear>;
+                        reg = <0x0922f080 0x4>;
+                        reg-names = "irqmux";
+                        interrupts = <GIC_SPI 191 IRQ_TYPE_NONE>;
+                        interrupts-names = "irqmux";
+                        ranges = <0 0x09220000 0x6000>;
+                        pio30: gpio@09220000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x0 0x100>;
+                                st,bank-name = "PIO30";
+                        };
+                        pio31: gpio@09221000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x100>;
+                                st,bank-name = "PIO31";
+                        };
+                        pio32: gpio@09222000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x100>;
+                                st,bank-name = "PIO32";
+                        };
+                        pio33: gpio@09223000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x3000 0x100>;
+                                st,bank-name = "PIO33";
+                        };
+                        pio34: gpio@09224000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x4000 0x100>;
+                                st,bank-name = "PIO34";
+                        };
+                        pio35: gpio@09225000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x5000 0x100>;
+                                st,bank-name = "PIO35";
+                        };
+                        i2c4 {
+                                pinctrl_i2c4_default: i2c4-default {
+                                        st,pins {
+                                                sda = <&pio30 1 ALT1 BIDIR>;
+                                                scl = <&pio30 0 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        i2c5 {
+                                pinctrl_i2c5_default: i2c5-default {
+                                        st,pins {
+                                                sda = <&pio34 4 ALT1 BIDIR>;
+                                                scl = <&pio34 3 ALT1 BIDIR>;
+                                        };
+                                };
+                        };
+                        usb3 {
+                                pinctrl_usb3: usb3-2 {
+                                        st,pins {
+                                                usb-oc-detect = <&pio35 4 ALT1 IN>;
+                                                usb-pwr-enable = <&pio35 5 ALT1 OUT>;
+                                                usb-vbus-valid = <&pio35 6 ALT1 IN>;
+                                        };
+                                };
+                        };
+                        pwm0 {
+                                pinctrl_pwm0_chan0_default: pwm0-0-default {
+                                        st,pins {
+                                                pwm-out = <&pio31 1 ALT1 OUT>;
+                                        };
+                                };
+                        };
+                };
+                pin-controller-flash {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "st,stih407-flash-pinctrl";
+                        st,syscfg = <&syscfg_flash>;
+                        reg = <0x0923f080 0x4>;
+                        reg-names = "irqmux";
+                        interrupts = <GIC_SPI 192 IRQ_TYPE_NONE>;
+                        interrupts-names = "irqmux";
+                        ranges = <0 0x09230000 0x3000>;
+                        pio40: gpio@09230000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0 0x100>;
+                                st,bank-name = "PIO40";
+                        };
+                        pio41: gpio@09231000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x1000 0x100>;
+                                st,bank-name = "PIO41";
+                        };
+                        pio42: gpio@09232000 {
+                                gpio-controller;
+                                #gpio-cells = <1>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+                                reg = <0x2000 0x100>;
+                                st,bank-name = "PIO42";
+                        };
+                        mmc0 {
+                                pinctrl_mmc0: mmc0-0 {
+                                        st,pins {
+                                                emmc_clk = <&pio40 6 ALT1 BIDIR>;
+                                                emmc_cmd = <&pio40 7 ALT1 BIDIR_PU>;
+                                                emmc_d0 = <&pio41 0 ALT1 BIDIR_PU>;
+                                                emmc_d1 = <&pio41 1 ALT1 BIDIR_PU>;
+                                                emmc_d2 = <&pio41 2 ALT1 BIDIR_PU>;
+                                                emmc_d3 = <&pio41 3 ALT1 BIDIR_PU>;
+                                                emmc_d4 = <&pio41 4 ALT1 BIDIR_PU>;
+                                                emmc_d5 = <&pio41 5 ALT1 BIDIR_PU>;
+                                                emmc_d6 = <&pio41 6 ALT1 BIDIR_PU>;
+                                                emmc_d7 = <&pio41 7 ALT1 BIDIR_PU>;
+                                        };
+                                };
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
new file mode 100644
index 000000000000..4f9024f19866
--- /dev/null
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -0,0 +1,263 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih407-clock.dtsi"
+#include "stih407-pinctrl.dtsi"
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <0>;
+                };
+                cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a9";
+                        reg = <1>;
+                };
+        };
+        intc: interrupt-controller@08761000 {
+                compatible = "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                interrupt-controller;
+                reg = <0x08761000 0x1000>, <0x08760100 0x100>;
+        };
+        scu@08760000 {
+                compatible = "arm,cortex-a9-scu";
+                reg = <0x08760000 0x1000>;
+        };
+        timer@08760200 {
+                interrupt-parent = <&intc>;
+                compatible = "arm,cortex-a9-global-timer";
+                reg = <0x08760200 0x100>;
+                interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&arm_periph_clk>;
+        };
+        l2: cache-controller {
+                compatible = "arm,pl310-cache";
+                reg = <0x08762000 0x1000>;
+                arm,data-latency = <3 3 3>;
+                arm,tag-latency = <2 2 2>;
+                cache-unified;
+                cache-level = <2>;
+        };
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                interrupt-parent = <&intc>;
+                ranges;
+                compatible = "simple-bus";
+                syscfg_sbc: sbc-syscfg@9620000 {
+                        compatible = "st,stih407-sbc-syscfg", "syscon";
+                        reg = <0x9620000 0x1000>;
+                };
+                syscfg_front: front-syscfg@9280000 {
+                        compatible = "st,stih407-front-syscfg", "syscon";
+                        reg = <0x9280000 0x1000>;
+                };
+                syscfg_rear: rear-syscfg@9290000 {
+                        compatible = "st,stih407-rear-syscfg", "syscon";
+                        reg = <0x9290000 0x1000>;
+                };
+                syscfg_flash: flash-syscfg@92a0000 {
+                        compatible = "st,stih407-flash-syscfg", "syscon";
+                        reg = <0x92a0000 0x1000>;
+                };
+                syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
+                        compatible = "st,stih407-sbc-reg-syscfg", "syscon";
+                        reg = <0x9600000 0x1000>;
+                };
+                syscfg_core: core-syscfg@92b0000 {
+                        compatible = "st,stih407-core-syscfg", "syscon";
+                        reg = <0x92b0000 0x1000>;
+                };
+                syscfg_lpm: lpm-syscfg@94b5100 {
+                        compatible = "st,stih407-lpm-syscfg", "syscon";
+                        reg = <0x94b5100 0x1000>;
+                };
+                serial@9830000 {
+                        compatible = "st,asc";
+                        reg = <0x9830000 0x2c>;
+                        interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_serial0>;
+                        clocks = <&clk_ext2f_a9>;
+                        status = "disabled";
+                };
+                serial@9831000 {
+                        compatible = "st,asc";
+                        reg = <0x9831000 0x2c>;
+                        interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_serial1>;
+                        clocks = <&clk_ext2f_a9>;
+                        status = "disabled";
+                };
+                serial@9832000 {
+                        compatible = "st,asc";
+                        reg = <0x9832000 0x2c>;
+                        interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_serial2>;
+                        clocks = <&clk_ext2f_a9>;
+                        status = "disabled";
+                };
+                /* SBC_ASC0 - UART10 */
+                sbc_serial0: serial@9530000 {
+                        compatible = "st,asc";
+                        reg = <0x9530000 0x2c>;
+                        interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_sbc_serial0>;
+                        clocks = <&clk_sysin>;
+                        status = "disabled";
+                };
+                serial@9531000 {
+                        compatible = "st,asc";
+                        reg = <0x9531000 0x2c>;
+                        interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_sbc_serial1>;
+                        clocks = <&clk_sysin>;
+                        status = "disabled";
+                };
+                i2c@9840000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+                        reg = <0x9840000 0x110>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c0_default>;
+                        status = "disabled";
+                };
+                i2c@9841000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9841000 0x110>;
+                        interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c1_default>;
+                        status = "disabled";
+                };
+                i2c@9842000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9842000 0x110>;
+                        interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c2_default>;
+                        status = "disabled";
+                };
+                i2c@9843000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9843000 0x110>;
+                        interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c3_default>;
+                        status = "disabled";
+                };
+                i2c@9844000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9844000 0x110>;
+                        interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c4_default>;
+                        status = "disabled";
+                };
+                i2c@9845000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9845000 0x110>;
+                        interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_ext2f_a9>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c5_default>;
+                        status = "disabled";
+                };
+                /* SSCs on SBC */
+                i2c@9540000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9540000 0x110>;
+                        interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_sysin>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c10_default>;
+                        status = "disabled";
+                };
+                i2c@9541000 {
+                        compatible = "st,comms-ssc4-i2c";
+                        reg = <0x9541000 0x110>;
+                        interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&clk_sysin>;
+                        clock-names = "ssc";
+                        clock-frequency = <400000>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_i2c11_default>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih415-b2000.dts b/arch/arm/boot/dts/stih415-b2000.dts
index d4af53160435..bdfbd3765db2 100644
--- a/arch/arm/boot/dts/stih415-b2000.dts
+++ b/arch/arm/boot/dts/stih415-b2000.dts
@@ -11,5 +11,5 @@
 #include "stih41x-b2000.dtsi"
 / {
        model = "STiH415 B2000 Board";
-        compatible = "st,stih415", "st,stih415-b2000";
+        compatible = "st,stih415-b2000", "st,stih415";
 };
diff --git a/arch/arm/boot/dts/stih415-b2020.dts b/arch/arm/boot/dts/stih415-b2020.dts
index 442b019e9a3a..71903a87bd31 100644
--- a/arch/arm/boot/dts/stih415-b2020.dts
+++ b/arch/arm/boot/dts/stih415-b2020.dts
@@ -11,5 +11,5 @@
 #include "stih41x-b2020.dtsi"
 / {
        model = "STiH415 B2020 Board";
-        compatible = "st,stih415", "st,stih415-b2020";
+        compatible = "st,stih415-b2020", "st,stih415";
 };
diff --git a/arch/arm/boot/dts/stih415-clock.dtsi b/arch/arm/boot/dts/stih415-clock.dtsi
index d047dbc28d61..3ee34514bc4b 100644
--- a/arch/arm/boot/dts/stih415-clock.dtsi
+++ b/arch/arm/boot/dts/stih415-clock.dtsi
@@ -5,48 +5,529 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/stih415-clks.h>
 / {
        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
                /*
                 * Fixed 30MHz oscillator input to SoC
                 */
-                CLK_SYSIN: CLK_SYSIN {
+                clk_sysin: clk-sysin {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <30000000>;
                };
                /*
-                 * ARM Peripheral clock for timers
+                 * ClockGenAs on SASG1
                 */
-                arm_periph_clk: arm_periph_clk {
+                clockgen-a@fee62000 {
-                        #clock-cells = <0>;
+                        reg = <0xfee62000 0xb48>;
-                        compatible = "fixed-clock";
-                        clock-frequency = <500000000>;
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-plls-c65";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-pll0-hs",
+                                                     "clk-s-a0-pll0-ls",
+                                                     "clk-s-a0-pll1";
+                        };
+                        clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c65",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-osc-prediv";
+                        };
+                        clk_s_a0_hs: clk-s-a0-hs {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-hs",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a0_osc_prediv>,
+                                         <&clk_s_a0_pll 0>, /* PLL0 HS */
+                                         <&clk_s_a0_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-fdma-0",
+                                                     "clk-s-fdma-1",
+                                                     ""; /* clk-s-jit-sense */
+                                                     /* Fourth output unused */
+                        };
+                        clk_s_a0_ls: clk-s-a0-ls {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-ls",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a0_osc_prediv>,
+                                         <&clk_s_a0_pll 1>, /* PLL0 LS */
+                                         <&clk_s_a0_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-icn-reg-0",
+                                                     "clk-s-icn-if-0",
+                                                     "clk-s-icn-reg-lp-0",
+                                                     "clk-s-emiss",
+                                                     "clk-s-eth1-phy",
+                                                     "clk-s-mii-ref-out";
+                                                 /* Remaining outputs unused */
+                        };
+                };
+                clockgen-a@fee81000 {
+                        reg = <0xfee81000 0xb48>;
+                        clk_s_a1_pll: clk-s-a1-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-plls-c65";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a1-pll0-hs",
+                                                     "clk-s-a1-pll0-ls",
+                                                     "clk-s-a1-pll1";
+                        };
+                        clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c65",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a1-osc-prediv";
+                        };
+                        clk_s_a1_hs: clk-s-a1-hs {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-hs",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a1_osc_prediv>,
+                                         <&clk_s_a1_pll 0>, /* PLL0 HS */
+                                         <&clk_s_a1_pll 2>; /* PLL1 */
+                                clock-output-names = "", /* Reserved */
+                                                     "", /* Reserved */
+                                                     "clk-s-stac-phy",
+                                                     "clk-s-vtac-tx-phy";
+                        };
+                        clk_s_a1_ls: clk-s-a1-ls {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-ls",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a1_osc_prediv>,
+                                         <&clk_s_a1_pll 1>, /* PLL0 LS */
+                                         <&clk_s_a1_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-icn-if-2",
+                                                     "clk-s-card-mmc",
+                                                     "clk-s-icn-if-1",
+                                                     "clk-s-gmac0-phy",
+                                                     "clk-s-nand-ctrl",
+                                                     "", /* Reserved */
+                                                     "clk-s-mii0-ref-out",
+                                                     ""; /* clk-s-stac-sys */
+                                                 /* Remaining outputs unused */
+                        };
                };
                /*
-                 * Bootloader initialized system infrastructure clock for
+                 * ClockGenAs on MPE41
-                 * serial devices.
                 */
-                CLKS_ICN_REG_0: CLKS_ICN_REG_0 {
+                clockgen-a@fde12000 {
+                        reg = <0xfde12000 0xb50>;
+                        clk_m_a0_pll0: clk-m-a0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-pll0-phi0",
+                                                     "clk-m-a0-pll0-phi1",
+                                                     "clk-m-a0-pll0-phi2",
+                                                     "clk-m-a0-pll0-phi3";
+                        };
+                        clk_m_a0_pll1: clk-m-a0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-pll1-phi0",
+                                                     "clk-m-a0-pll1-phi1",
+                                                     "clk-m-a0-pll1-phi2",
+                                                     "clk-m-a0-pll1-phi3";
+                        };
+                        clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-osc-prediv";
+                        };
+                        clk_m_a0_div0: clk-m-a0-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "clk-m-apb-pm", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "clk-m-pp-dmu-0",
+                                                     "clk-m-pp-dmu-1",
+                                                     "clk-m-icm-disp",
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a0_div1: clk-m-a0-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "clk-m-a9-ext2f",
+                                                     "clk-m-st40rt",
+                                                     "clk-m-st231-dmu-0",
+                                                     "clk-m-st231-dmu-1",
+                                                     "clk-m-st231-aud",
+                                                     "clk-m-st231-gp-0";
+                        };
+                        clk_m_a0_div2: clk-m-a0-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "clk-m-st231-gp-1",
+                                                     "clk-m-icn-cpu",
+                                                     "clk-m-icn-stac",
+                                                     "clk-m-icn-dmu-0",
+                                                     "clk-m-icn-dmu-1",
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a0_div3: clk-m-a0-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "clk-m-icn-eram",
+                                                     "clk-m-a9-trace";
+                        };
+                };
+                clockgen-a@fd6db000 {
+                        reg = <0xfd6db000 0xb50>;
+                        clk_m_a1_pll0: clk-m-a1-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-pll0-phi0",
+                                                     "clk-m-a1-pll0-phi1",
+                                                     "clk-m-a1-pll0-phi2",
+                                                     "clk-m-a1-pll0-phi3";
+                        };
+                        clk_m_a1_pll1: clk-m-a1-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-pll1-phi0",
+                                                     "clk-m-a1-pll1-phi1",
+                                                     "clk-m-a1-pll1-phi2",
+                                                     "clk-m-a1-pll1-phi3";
+                        };
+                        clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-osc-prediv";
+                        };
+                        clk_m_a1_div0: clk-m-a1-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "clk-m-fdma-12",
+                                                     "clk-m-fdma-10",
+                                                     "clk-m-fdma-11",
+                                                     "clk-m-hva-lmi",
+                                                     "clk-m-proc-sc",
+                                                     "clk-m-tp",
+                                                     "clk-m-icn-gpu",
+                                                     "clk-m-icn-vdp-0";
+                        };
+                        clk_m_a1_div1: clk-m-a1-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "clk-m-icn-vdp-1",
+                                                     "clk-m-icn-vdp-2",
+                                                     "clk-m-icn-vdp-3",
+                                                     "clk-m-prv-t1-bus",
+                                                     "clk-m-icn-vdp-4",
+                                                     "clk-m-icn-reg-10",
+                                                     "", /* Unused */
+                                                     ""; /* clk-m-icn-st231 */
+                        };
+                        clk_m_a1_div2: clk-m-a1-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "clk-m-fvdp-proc-alt",
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a1_div3: clk-m-a1-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     ""; /* Unused */
+                        };
+                };
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "fixed-factor-clock";
-                        clock-frequency = <100000000>;
+                        clocks = <&clk_m_a0_div1 2>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
                };
-                CLKS_GMAC0_PHY: clockgenA1@7 {
+                clockgen-a@fd345000 {
+                        reg = <0xfd345000 0xb50>;
+                        clk_m_a2_pll0: clk-m-a2-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-pll0-phi0",
+                                                     "clk-m-a2-pll0-phi1",
+                                                     "clk-m-a2-pll0-phi2",
+                                                     "clk-m-a2-pll0-phi3";
+                        };
+                        clk_m_a2_pll1: clk-m-a2-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-pll1-phi0",
+                                                     "clk-m-a2-pll1-phi1",
+                                                     "clk-m-a2-pll1-phi2",
+                                                     "clk-m-a2-pll1-phi3";
+                        };
+                        clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-osc-prediv";
+                        };
+                        clk_m_a2_div0: clk-m-a2-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "clk-m-vtac-main-phy",
+                                                     "clk-m-vtac-aux-phy",
+                                                     "clk-m-stac-phy",
+                                                     "clk-m-stac-sys",
+                                                     "", /* clk-m-mpestac-pg */
+                                                     "", /* clk-m-mpestac-wc */
+                                                     "", /* clk-m-mpevtacaux-pg*/
+                                                     ""; /* clk-m-mpevtacmain-pg*/
+                        };
+                        clk_m_a2_div1: clk-m-a2-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "", /* clk-m-mpevtacrx0-wc */
+                                                     "", /* clk-m-mpevtacrx1-wc */
+                                                     "clk-m-compo-main",
+                                                     "clk-m-compo-aux",
+                                                     "clk-m-bdisp-0",
+                                                     "clk-m-bdisp-1",
+                                                     "clk-m-icn-bdisp-0",
+                                                     "clk-m-icn-bdisp-1";
+                        };
+                        clk_m_a2_div2: clk-m-a2-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "", /* clk-m-icn-hqvdp0 */
+                                                     "", /* clk-m-icn-hqvdp1 */
+                                                     "clk-m-icn-compo",
+                                                     "", /* clk-m-icn-vdpaux */
+                                                     "clk-m-icn-ts",
+                                                     "clk-m-icn-reg-lp-10",
+                                                     "clk-m-dcephy-impctrl",
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a2_div3: clk-m-a2-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = ""; /* Unused */
+                                                /* Remaining outputs unused */
+                        };
+                };
+                /*
+                 * A9 PLL
+                 */
+                clockgen-a9@fdde00d8 {
+                        reg = <0xfdde00d8 0x70>;
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih415-plls-c32-a9", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+                /*
+                 * ARM CPU related clocks
+                 */
+                clk_m_a9: clk-m-a9@fdde00d8 {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "st,stih415-clkgen-a9-mux", "st,clkgen-mux";
-                        clock-frequency = <25000000>;
+                        reg = <0xfdde00d8 0x4>;
-                        clock-output-names = "CLKS_GMAC0_PHY";
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_m_a0_div1 2>,
+                                 <&clk_m_a9_ext2f_div2>;
                };
-                CLKS_ETH1_PHY: clockgenA0@7 {
+                /*
+                 * ARM Peripheral clock for timers
+                 */
+                arm_periph_clk: clk-m-a9-periphs {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "fixed-factor-clock";
-                        clock-frequency = <25000000>;
+                        clocks = <&clk_m_a9>;
-                        clock-output-names = "CLKS_ETH1_PHY";
+                        clock-div = <2>;
+                        clock-mult = <1>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/stih415-pinctrl.dtsi b/arch/arm/boot/dts/stih415-pinctrl.dtsi
index f09fb10a3791..8509a037ae21 100644
--- a/arch/arm/boot/dts/stih415-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih415-pinctrl.dtsi
@@ -49,7 +49,7 @@
                        reg             = <0xfe61f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe610000 0x5000>;
                        PIO0: gpio@fe610000 {
@@ -102,6 +102,22 @@
                                };
                        };
+                        keyscan {
+                                pinctrl_keyscan: keyscan {
+                                        st,pins {
+                                                keyin0 = <&PIO0 2 ALT2 IN>;
+                                                keyin1 = <&PIO0 3 ALT2 IN>;
+                                                keyin2 = <&PIO0 4 ALT2 IN>;
+                                                keyin3 = <&PIO2 6 ALT2 IN>;
+                                                keyout0 = <&PIO1 6 ALT2 OUT>;
+                                                keyout1 = <&PIO1 7 ALT2 OUT>;
+                                                keyout2 = <&PIO0 6 ALT2 OUT>;
+                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                        };
+                                };
+                        };
                        sbc_i2c0 {
                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                        st,pins {
@@ -187,7 +203,7 @@
                        reg             = <0xfee0f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfee00000 0x8000>;
                        PIO5: gpio@fee00000 {
@@ -282,7 +298,7 @@
                        reg             = <0xfe82f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe820000 0x8000>;
                        PIO13: gpio@fe820000 {
@@ -423,7 +439,7 @@
                        reg             = <0xfd6bf080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
                        PIO100: gpio@fd6b0000 {
@@ -460,7 +476,7 @@
                        reg             = <0xfd33f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd330000 0x5000>;
                        PIO103: gpio@fd330000 {
diff --git a/arch/arm/boot/dts/stih415.dtsi b/arch/arm/boot/dts/stih415.dtsi
index d89064c20c8a..d6f254f302fe 100644
--- a/arch/arm/boot/dts/stih415.dtsi
+++ b/arch/arm/boot/dts/stih415.dtsi
@@ -82,7 +82,7 @@
                        interrupts      = <0 197 0>;
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_serial2>;
-                        clocks          = <&CLKS_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                };
                /* SBC comms block ASCs in SASG1 */
@@ -91,7 +91,7 @@
                        status          = "disabled";
                        reg             = <0xfe531000 0x2c>;
                        interrupts      = <0 210 0>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_sbc_serial1>;
                };
@@ -100,7 +100,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfed40000 0x110>;
                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLKS_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -113,7 +113,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfed41000 0x110>;
                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLKS_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -126,7 +126,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfe540000 0x110>;
                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -139,7 +139,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfe541000 0x110>;
                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -170,7 +170,7 @@
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii0>;
                        clock-names     = "stmmaceth";
-                        clocks          = <&CLKS_GMAC0_PHY>;
+                        clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
                };
                ethernet1: dwmac@fef08000 {
@@ -193,18 +193,30 @@
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii1>;
                        clock-names     = "stmmaceth";
-                        clocks          = <&CLKS_ETH1_PHY>;
+                        clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
                };
                rc: rc@fe518000 {
                        compatible      = "st,comms-irb";
                        reg             = <0xfe518000 0x234>;
                        interrupts      =  <0 203 0>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        rx-mode         = "infrared";
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_ir>;
                        resets          = <&softreset STIH415_IRB_SOFTRESET>;
                };
+                keyscan: keyscan@fe4b0000 {
+                        compatible = "st,sti-keyscan";
+                        status = "disabled";
+                        reg = <0xfe4b0000 0x2000>;
+                        interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
+                        clocks = <&clk_sysin>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_keyscan>;
+                        resets  = <&powerdown STIH415_KEYSCAN_POWERDOWN>,
+                                  <&softreset STIH415_KEYSCAN_SOFTRESET>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-b2000.dts b/arch/arm/boot/dts/stih416-b2000.dts
index a5eb6eee10bf..488e80a5d69d 100644
--- a/arch/arm/boot/dts/stih416-b2000.dts
+++ b/arch/arm/boot/dts/stih416-b2000.dts
@@ -9,8 +9,7 @@
 /dts-v1/;
 #include "stih416.dtsi"
 #include "stih41x-b2000.dtsi"
 / {
-        compatible = "st,stih416", "st,stih416-b2000";
        model = "STiH416 B2000";
+        compatible = "st,stih416-b2000", "st,stih416";
 };
diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts b/arch/arm/boot/dts/stih416-b2020-revE.dts
new file mode 100644
index 000000000000..ba0fa2caaf18
--- /dev/null
+++ b/arch/arm/boot/dts/stih416-b2020-revE.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Lee Jones <lee.jones@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih416.dtsi"
+#include "stih41x-b2020.dtsi"
+/ {
+        model = "STiH416 B2020 REV-E";
+        compatible = "st,stih416-b2020", "st,stih416";
+        soc {
+                leds {
+                        compatible = "gpio-leds";
+                        red {
+                                #gpio-cells             = <1>;
+                                label                   = "Front Panel LED";
+                                gpios                   = <&PIO4 1>;
+                                linux,default-trigger   = "heartbeat";
+                        };
+                        green {
+                                gpios                   = <&PIO1 3>;
+                                default-state           = "off";
+                        };
+                };
+                ethernet1: dwmac@fef08000 {
+                        snps,reset-gpio = <&PIO0 7>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 276f28da573a..4e2df66b99ea 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -11,6 +11,5 @@
 #include "stih41x-b2020.dtsi"
 / {
        model = "STiH416 B2020";
-        compatible = "st,stih416", "st,stih416-b2020";
+        compatible = "st,stih416-b2020", "st,stih416";
 };
diff --git a/arch/arm/boot/dts/stih416-clock.dtsi b/arch/arm/boot/dts/stih416-clock.dtsi
index a6942c75cbbb..5b4fb838cddb 100644
--- a/arch/arm/boot/dts/stih416-clock.dtsi
+++ b/arch/arm/boot/dts/stih416-clock.dtsi
@@ -6,50 +6,751 @@
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
+#include <dt-bindings/clock/stih416-clks.h>
 / {
        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
                /*
                 * Fixed 30MHz oscillator inputs to SoC
                 */
-                CLK_SYSIN: CLK_SYSIN {
+                clk_sysin: clk-sysin {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
                        clock-frequency = <30000000>;
-                        clock-output-names = "CLK_SYSIN";
+                };
+                /*
+                 * ClockGenAs on SASG2
+                 */
+                clockgen-a@fee62000 {
+                        reg = <0xfee62000 0xb48>;
+                        clk_s_a0_pll: clk-s-a0-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-plls-c65";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-pll0-hs",
+                                                     "clk-s-a0-pll0-ls",
+                                                     "clk-s-a0-pll1";
+                        };
+                        clk_s_a0_osc_prediv: clk-s-a0-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c65",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a0-osc-prediv";
+                        };
+                        clk_s_a0_hs: clk-s-a0-hs {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-hs",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a0_osc_prediv>,
+                                         <&clk_s_a0_pll 0>, /* PLL0 HS */
+                                         <&clk_s_a0_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-fdma-0",
+                                                     "clk-s-fdma-1",
+                                                     ""; /* clk-s-jit-sense */
+                                                     /* Fourth output unused */
+                        };
+                        clk_s_a0_ls: clk-s-a0-ls {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-ls",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a0_osc_prediv>,
+                                         <&clk_s_a0_pll 1>, /* PLL0 LS */
+                                         <&clk_s_a0_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-icn-reg-0",
+                                                     "clk-s-icn-if-0",
+                                                     "clk-s-icn-reg-lp-0",
+                                                     "clk-s-emiss",
+                                                     "clk-s-eth1-phy",
+                                                     "clk-s-mii-ref-out";
+                                                     /* Remaining outputs unused */
+                        };
+                };
+                clockgen-a@fee81000 {
+                        reg = <0xfee81000 0xb48>;
+                        clk_s_a1_pll: clk-s-a1-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-plls-c65";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a1-pll0-hs",
+                                                     "clk-s-a1-pll0-ls",
+                                                     "clk-s-a1-pll1";
+                        };
+                        clk_s_a1_osc_prediv: clk-s-a1-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c65",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-s-a1-osc-prediv";
+                        };
+                        clk_s_a1_hs: clk-s-a1-hs {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-hs",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a1_osc_prediv>,
+                                         <&clk_s_a1_pll 0>, /* PLL0 HS */
+                                         <&clk_s_a1_pll 2>; /* PLL1 */
+                                clock-output-names = "", /* Reserved */
+                                                     "", /* Reserved */
+                                                     "clk-s-stac-phy",
+                                                     "clk-s-vtac-tx-phy";
+                        };
+                        clk_s_a1_ls: clk-s-a1-ls {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c65-ls",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_s_a1_osc_prediv>,
+                                         <&clk_s_a1_pll 1>, /* PLL0 LS */
+                                         <&clk_s_a1_pll 2>; /* PLL1 */
+                                clock-output-names = "clk-s-icn-if-2",
+                                                     "clk-s-card-mmc-0",
+                                                     "clk-s-icn-if-1",
+                                                     "clk-s-gmac0-phy",
+                                                     "clk-s-nand-ctrl",
+                                                     "", /* Reserved */
+                                                     "clk-s-mii0-ref-out",
+                                                     "clk-s-stac-sys",
+                                                     "clk-s-card-mmc-1";
+                                                     /* Remaining outputs unused */
+                        };
+                };
+                /*
+                 * ClockGenAs on MPE42
+                 */
+                clockgen-a@fde12000 {
+                        reg = <0xfde12000 0xb50>;
+                        clk_m_a0_pll0: clk-m-a0-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-pll0-phi0",
+                                                     "clk-m-a0-pll0-phi1",
+                                                     "clk-m-a0-pll0-phi2",
+                                                     "clk-m-a0-pll0-phi3";
+                        };
+                        clk_m_a0_pll1: clk-m-a0-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-pll1-phi0",
+                                                     "clk-m-a0-pll1-phi1",
+                                                     "clk-m-a0-pll1-phi2",
+                                                     "clk-m-a0-pll1-phi3";
+                        };
+                        clk_m_a0_osc_prediv: clk-m-a0-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a0-osc-prediv";
+                        };
+                        clk_m_a0_div0: clk-m-a0-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a0_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "clk-m-fdma-12",
+                                                     "", /* Unused */
+                                                     "clk-m-pp-dmu-0",
+                                                     "clk-m-pp-dmu-1",
+                                                     "clk-m-icm-lmi",
+                                                     "clk-m-vid-dmu-0";
+                        };
+                        clk_m_a0_div1: clk-m-a0-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a0_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "clk-m-vid-dmu-1",
+                                                     "", /* Unused */
+                                                     "clk-m-a9-ext2f",
+                                                     "clk-m-st40rt",
+                                                     "clk-m-st231-dmu-0",
+                                                     "clk-m-st231-dmu-1",
+                                                     "clk-m-st231-aud",
+                                                     "clk-m-st231-gp-0";
+                        };
+                        clk_m_a0_div2: clk-m-a0-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a0_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "clk-m-st231-gp-1",
+                                                     "clk-m-icn-cpu",
+                                                     "clk-m-icn-stac",
+                                                     "clk-m-tx-icn-dmu-0",
+                                                     "clk-m-tx-icn-dmu-1",
+                                                     "clk-m-tx-icn-ts",
+                                                     "clk-m-icn-vdp-0",
+                                                     "clk-m-icn-vdp-1";
+                        };
+                        clk_m_a0_div3: clk-m-a0-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a0_osc_prediv>,
+                                         <&clk_m_a0_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a0_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "clk-m-icn-vp8",
+                                                     "", /* Unused */
+                                                     "clk-m-icn-reg-11",
+                                                     "clk-m-a9-trace";
+                        };
+                };
+                clockgen-a@fd6db000 {
+                        reg = <0xfd6db000 0xb50>;
+                        clk_m_a1_pll0: clk-m-a1-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-pll0-phi0",
+                                                     "clk-m-a1-pll0-phi1",
+                                                     "clk-m-a1-pll0-phi2",
+                                                     "clk-m-a1-pll0-phi3";
+                        };
+                        clk_m_a1_pll1: clk-m-a1-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-pll1-phi0",
+                                                     "clk-m-a1-pll1-phi1",
+                                                     "clk-m-a1-pll1-phi2",
+                                                     "clk-m-a1-pll1-phi3";
+                        };
+                        clk_m_a1_osc_prediv: clk-m-a1-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a1-osc-prediv";
+                        };
+                        clk_m_a1_div0: clk-m-a1-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a1_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "", /* Unused */
+                                                     "clk-m-fdma-10",
+                                                     "clk-m-fdma-11",
+                                                     "clk-m-hva-alt",
+                                                     "clk-m-proc-sc",
+                                                     "clk-m-tp",
+                                                     "clk-m-rx-icn-dmu-0",
+                                                     "clk-m-rx-icn-dmu-1";
+                        };
+                        clk_m_a1_div1: clk-m-a1-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a1_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "clk-m-rx-icn-ts",
+                                                     "clk-m-rx-icn-vdp-0",
+                                                     "", /* Unused */
+                                                     "clk-m-prv-t1-bus",
+                                                     "clk-m-icn-reg-12",
+                                                     "clk-m-icn-reg-10",
+                                                     "", /* Unused */
+                                                     "clk-m-icn-st231";
+                        };
+                        clk_m_a1_div2: clk-m-a1-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a1_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "clk-m-fvdp-proc-alt",
+                                                     "clk-m-icn-reg-13",
+                                                     "clk-m-tx-icn-gpu",
+                                                     "clk-m-rx-icn-gpu",
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* clk-m-apb-pm-12 */
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a1_div3: clk-m-a1-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a1_osc_prediv>,
+                                         <&clk_m_a1_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a1_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     "", /* Unused */
+                                                     ""; /* clk-m-gpu-alt */
+                        };
+                };
+                clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2 {
+                        #clock-cells = <0>;
+                        compatible = "fixed-factor-clock";
+                        clocks = <&clk_m_a0_div1 2>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
+                };
+                clockgen-a@fd345000 {
+                        reg = <0xfd345000 0xb50>;
+                        clk_m_a2_pll0: clk-m-a2-pll0 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-0", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-pll0-phi0",
+                                                     "clk-m-a2-pll0-phi1",
+                                                     "clk-m-a2-pll0-phi2",
+                                                     "clk-m-a2-pll0-phi3";
+                        };
+                        clk_m_a2_pll1: clk-m-a2-pll1 {
+                                #clock-cells = <1>;
+                                compatible = "st,plls-c32-a1x-1", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-pll1-phi0",
+                                                     "clk-m-a2-pll1-phi1",
+                                                     "clk-m-a2-pll1-phi2",
+                                                     "clk-m-a2-pll1-phi3";
+                        };
+                        clk_m_a2_osc_prediv: clk-m-a2-osc-prediv {
+                                #clock-cells = <0>;
+                                compatible = "st,clkgena-prediv-c32",
+                                             "st,clkgena-prediv";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clk-m-a2-osc-prediv";
+                        };
+                        clk_m_a2_div0: clk-m-a2-div0 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf0",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 0>, /* PLL0 PHI0 */
+                                         <&clk_m_a2_pll1 0>; /* PLL1 PHI0 */
+                                clock-output-names = "clk-m-vtac-main-phy",
+                                                     "clk-m-vtac-aux-phy",
+                                                     "clk-m-stac-phy",
+                                                     "clk-m-stac-sys",
+                                                     "", /* clk-m-mpestac-pg */
+                                                     "", /* clk-m-mpestac-wc */
+                                                     "", /* clk-m-mpevtacaux-pg*/
+                                                     ""; /* clk-m-mpevtacmain-pg*/
+                        };
+                        clk_m_a2_div1: clk-m-a2-div1 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf1",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 1>, /* PLL0 PHI1 */
+                                         <&clk_m_a2_pll1 1>; /* PLL1 PHI1 */
+                                clock-output-names = "", /* clk-m-mpevtacrx0-wc */
+                                                     "", /* clk-m-mpevtacrx1-wc */
+                                                     "clk-m-compo-main",
+                                                     "clk-m-compo-aux",
+                                                     "clk-m-bdisp-0",
+                                                     "clk-m-bdisp-1",
+                                                     "clk-m-icn-bdisp",
+                                                     "clk-m-icn-compo";
+                        };
+                        clk_m_a2_div2: clk-m-a2-div2 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf2",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 2>, /* PLL0 PHI2 */
+                                         <&clk_m_a2_pll1 2>; /* PLL1 PHI2 */
+                                clock-output-names = "clk-m-icn-vdp-2",
+                                                     "", /* Unused */
+                                                     "clk-m-icn-reg-14",
+                                                     "clk-m-mdtp",
+                                                     "clk-m-jpegdec",
+                                                     "", /* Unused */
+                                                     "clk-m-dcephy-impctrl",
+                                                     ""; /* Unused */
+                        };
+                        clk_m_a2_div3: clk-m-a2-div3 {
+                                #clock-cells = <1>;
+                                compatible = "st,clkgena-divmux-c32-odf3",
+                                             "st,clkgena-divmux";
+                                clocks = <&clk_m_a2_osc_prediv>,
+                                         <&clk_m_a2_pll0 3>, /* PLL0 PHI3 */
+                                         <&clk_m_a2_pll1 3>; /* PLL1 PHI3 */
+                                clock-output-names = "", /* Unused */
+                                                     ""; /* clk-m-apb-pm-11 */
+                                                     /* Remaining outputs unused */
+                        };
+                };
+                /*
+                 * A9 PLL
+                 */
+                clockgen-a9@fdde08b0 {
+                        reg = <0xfdde08b0 0x70>;
+                        clockgen_a9_pll: clockgen-a9-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih416-plls-c32-a9", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-a9-pll-odf";
+                        };
+                };
+                /*
+                 * ARM CPU related clocks
+                 */
+                clk_m_a9: clk-m-a9@fdde08ac {
+                        #clock-cells = <0>;
+                        compatible = "st,stih416-clkgen-a9-mux", "st,clkgen-mux";
+                        reg = <0xfdde08ac 0x4>;
+                        clocks = <&clockgen_a9_pll 0>,
+                                 <&clockgen_a9_pll 0>,
+                                 <&clk_m_a0_div1 2>,
+                                 <&clk_m_a9_ext2f_div2>;
                };
                /*
                 * ARM Peripheral clock for timers
                 */
-                arm_periph_clk: arm_periph_clk {
+                arm_periph_clk: clk-m-a9-periphs {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "fixed-factor-clock";
-                        clock-frequency = <600000000>;
+                        clocks = <&clk_m_a9>;
+                        clock-div = <2>;
+                        clock-mult = <1>;
                };
                /*
-                 * Bootloader initialized system infrastructure clock for
+                 * Frequency synthesizers on the SASG2
-                 * serial devices.
                 */
-                CLK_S_ICN_REG_0: clockgenA0@4 {
+                clockgen_b0: clockgen-b0@fee108b4 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs216", "st,quadfs";
+                        reg = <0xfee108b4 0x44>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-usb48",
+                                             "clk-s-dss",
+                                             "clk-s-stfe-frc-2",
+                                             "clk-s-thsens-scard";
+                };
+                clockgen_b1: clockgen-b1@fe8308c4 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs216", "st,quadfs";
+                        reg = <0xfe8308c4 0x44>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-pcm-0",
+                                             "clk-s-pcm-1",
+                                             "clk-s-pcm-2",
+                                             "clk-s-pcm-3";
+                };
+                clockgen_c: clockgen-c@fe8307d0 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs432", "st,quadfs";
+                        reg = <0xfe8307d0 0x44>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-c-fs0-ch0",
+                                             "clk-s-c-vcc-sd",
+                                             "clk-s-c-fs0-ch2";
+                };
+                clk_s_vcc_hd: clk-s-vcc-hd@fe8308b8 {
                        #clock-cells = <0>;
-                        compatible = "fixed-clock";
+                        compatible = "st,stih416-clkgenc-vcc-hd", "st,clkgen-mux";
-                        clock-frequency = <100000000>;
+                        reg = <0xfe8308b8 0x4>; /* SYSCFG2558 */
-                        clock-output-names = "CLK_S_ICN_REG_0";
+                        clocks = <&clk_sysin>,
+                                 <&clockgen_c 0>;
                };
-                CLK_S_GMAC0_PHY: clockgenA1@7 {
+                /*
+                 * Add a dummy clock for the HDMI PHY for the VCC input mux
+                 */
+                clk_s_tmds_fromphy: clk-s-tmds-fromphy {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <25000000>;
+                        clock-frequency = <0>;
-                        clock-output-names = "CLK_S_GMAC0_PHY";
+                };
+                clockgen_c_vcc: clockgen-c-vcc@fe8308ac {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-clkgenc", "st,clkgen-vcc";
+                        reg = <0xfe8308ac 0xc>; /* SYSCFG2555,2556,2557 */
+                        clocks = <&clk_s_vcc_hd>,
+                                 <&clockgen_c 1>,
+                                 <&clk_s_tmds_fromphy>,
+                                 <&clockgen_c 2>;
+                        clock-output-names  = "clk-s-pix-hdmi",
+                                              "clk-s-pix-dvo",
+                                              "clk-s-out-dvo",
+                                              "clk-s-pix-hd",
+                                              "clk-s-hddac",
+                                              "clk-s-denc",
+                                              "clk-s-sddac",
+                                              "clk-s-pix-main",
+                                              "clk-s-pix-aux",
+                                              "clk-s-stfe-frc-0",
+                                              "clk-s-ref-mcru",
+                                              "clk-s-slave-mcru",
+                                              "clk-s-tmds-hdmi",
+                                              "clk-s-hdmi-reject-pll",
+                                              "clk-s-thsens";
                };
-                CLK_S_ETH1_PHY: clockgenA0@7 {
+                clockgen_d: clockgen-d@fee107e0 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs216", "st,quadfs";
+                        reg = <0xfee107e0 0x44>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-s-ccsc",
+                                             "clk-s-stfe-frc-1",
+                                             "clk-s-tsout-1",
+                                             "clk-s-mchi";
+                };
+                /*
+                 * Frequency synthesizers on the MPE42
+                 */
+                clockgen_e: clockgen-e@fd3208bc {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs660-E", "st,quadfs";
+                        reg = <0xfd3208bc 0xb0>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-m-pix-mdtp-0",
+                                             "clk-m-pix-mdtp-1",
+                                             "clk-m-pix-mdtp-2",
+                                             "clk-m-mpelpc";
+                };
+                clockgen_f: clockgen-f@fd320878 {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-quadfs660-F", "st,quadfs";
+                        reg = <0xfd320878 0xf0>;
+                        clocks = <&clk_sysin>;
+                        clock-output-names = "clk-m-main-vidfs",
+                                             "clk-m-hva-fs",
+                                             "clk-m-fvdp-vcpu",
+                                             "clk-m-fvdp-proc-fs";
+                };
+                clk_m_fvdp_proc: clk-m-fvdp-proc@fd320910 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih416-clkgenf-vcc-fvdp", "st,clkgen-mux";
+                        reg = <0xfd320910 0x4>; /* SYSCFG8580 */
+                        clocks = <&clk_m_a1_div2 0>,
+                                 <&clockgen_f 3>;
+                };
+                clk_m_hva: clk-m-hva@fd690868 {
+                        #clock-cells = <0>;
+                        compatible = "st,stih416-clkgenf-vcc-hva", "st,clkgen-mux";
+                        reg = <0xfd690868 0x4>; /* SYSCFG9538 */
+                        clocks = <&clockgen_f 1>,
+                                 <&clk_m_a1_div0 3>;
+                };
+                clk_m_f_vcc_hd: clk-m-f-vcc-hd@fd32086c {
+                        #clock-cells = <0>;
+                        compatible = "st,stih416-clkgenf-vcc-hd", "st,clkgen-mux";
+                        reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
+                        clocks = <&clockgen_c_vcc 7>,
+                                 <&clockgen_f 0>;
+                };
+                clk_m_f_vcc_sd: clk-m-f-vcc-sd@fd32086c {
+                        #clock-cells = <0>;
+                        compatible = "st,stih416-clkgenf-vcc-sd", "st,clkgen-mux";
+                        reg = <0xfd32086c 0x4>; /* SYSCFG8539 */
+                        clocks = <&clockgen_c_vcc 8>,
+                                 <&clockgen_f 1>;
+                };
+                /*
+                 * Add a dummy clock for the HDMIRx external signal clock
+                 */
+                clk_m_pix_hdmirx_sas: clk-m-pix-hdmirx-sas {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                        clock-frequency = <25000000>;
+                        clock-frequency = <0>;
-                        clock-output-names = "CLK_S_ETH1_PHY";
+                };
+                clockgen_f_vcc: clockgen-f-vcc@fd32086c {
+                        #clock-cells = <1>;
+                        compatible = "st,stih416-clkgenf", "st,clkgen-vcc";
+                        reg = <0xfd32086c 0xc>; /* SYSCFG8539,8540,8541 */
+                        clocks = <&clk_m_f_vcc_hd>,
+                                 <&clk_m_f_vcc_sd>,
+                                 <&clockgen_f 0>,
+                                 <&clk_m_pix_hdmirx_sas>;
+                        clock-output-names  = "clk-m-pix-main-pipe",
+                                              "clk-m-pix-aux-pipe",
+                                              "clk-m-pix-main-cru",
+                                              "clk-m-pix-aux-cru",
+                                              "clk-m-xfer-be-compo",
+                                              "clk-m-xfer-pip-compo",
+                                              "clk-m-xfer-aux-compo",
+                                              "clk-m-vsens",
+                                              "clk-m-pix-hdmirx-0",
+                                              "clk-m-pix-hdmirx-1";
+                };
+                /*
+                 * DDR PLL
+                 */
+                clockgen-ddr@0xfdde07d8 {
+                        reg = <0xfdde07d8 0x110>;
+                        clockgen_ddr_pll: clockgen-ddr-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih416-plls-c32-ddr", "st,clkgen-plls-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-ddr0",
+                                                     "clockgen-ddr1";
+                        };
+                };
+                /*
+                 * GPU PLL
+                 */
+                clockgen-gpu@fd68ff00 {
+                        reg = <0xfd68ff00 0x910>;
+                        clockgen_gpu_pll: clockgen-gpu-pll {
+                                #clock-cells = <1>;
+                                compatible = "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32";
+                                clocks = <&clk_sysin>;
+                                clock-output-names = "clockgen-gpu-pll";
+                        };
                };
        };
 };
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index aeea304086eb..ee6c119e261e 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -53,7 +53,7 @@
                        reg             = <0xfe61f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe610000 0x6000>;
                        PIO0: gpio@fe610000 {
@@ -122,6 +122,22 @@
                                };
                        };
+                        keyscan {
+                                pinctrl_keyscan: keyscan {
+                                        st,pins {
+                                                keyin0 = <&PIO0 2 ALT2 IN>;
+                                                keyin1 = <&PIO0 3 ALT2 IN>;
+                                                keyin2 = <&PIO0 4 ALT2 IN>;
+                                                keyin3 = <&PIO2 6 ALT2 IN>;
+                                                keyout0 = <&PIO1 6 ALT2 OUT>;
+                                                keyout1 = <&PIO1 7 ALT2 OUT>;
+                                                keyout2 = <&PIO0 6 ALT2 OUT>;
+                                                keyout3 = <&PIO2 7 ALT2 OUT>;
+                                        };
+                                };
+                        };
                        sbc_i2c0 {
                                pinctrl_sbc_i2c0_default: sbc_i2c0-default {
                                        st,pins {
@@ -201,7 +217,7 @@
                        reg             = <0xfee0f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfee00000 0x10000>;
                        PIO5: gpio@fee00000 {
@@ -333,7 +349,7 @@
                        reg             = <0xfe82f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfe820000 0x6000>;
                        PIO13: gpio@fe820000 {
@@ -461,7 +477,7 @@
                        reg             = <0xfd6bf080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges          = <0 0xfd6b0000 0x3000>;
                        PIO100: gpio@fd6b0000 {
@@ -498,7 +514,7 @@
                        reg             = <0xfd33f080 0x4>;
                        reg-names       = "irqmux";
                        interrupts      = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
-                        interrupts-names = "irqmux";
+                        interrupt-names = "irqmux";
                        ranges                  = <0 0xfd330000 0x5000>;
                        PIO103: gpio@fd330000 {
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 78746d20382e..06473c5d9ea9 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -89,7 +89,7 @@
                        status          = "disabled";
                        reg             = <0xfed32000 0x2c>;
                        interrupts      = <0 197 0>;
-                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_serial2 &pinctrl_serial2_oe>;
                };
@@ -102,14 +102,14 @@
                        interrupts      = <0 210 0>;
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_sbc_serial1>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                };
                i2c@fed40000 {
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfed40000 0x110>;
                        interrupts      = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -122,7 +122,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfed41000 0x110>;
                        interrupts      = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_S_ICN_REG_0>;
+                        clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -135,7 +135,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfe540000 0x110>;
                        interrupts      = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -148,7 +148,7 @@
                        compatible      = "st,comms-ssc4-i2c";
                        reg             = <0xfe541000 0x110>;
                        interrupts      = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        clock-names     = "ssc";
                        clock-frequency = <400000>;
                        pinctrl-names   = "default";
@@ -176,7 +176,7 @@
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii0>;
                        clock-names     = "stmmaceth";
-                        clocks          = <&CLK_S_GMAC0_PHY>;
+                        clocks          = <&clk_s_a1_ls CLK_GMAC0_PHY>;
                };
                ethernet1: dwmac@fef08000 {
@@ -198,7 +198,7 @@
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_mii1>;
                        clock-names     = "stmmaceth";
-                        clocks          = <&CLK_S_ETH1_PHY>;
+                        clocks          = <&clk_s_a0_ls CLK_ETH1_PHY>;
                };
                rc: rc@fe518000 {
@@ -206,7 +206,7 @@
                        reg             = <0xfe518000 0x234>;
                        interrupts      =  <0 203 0>;
                        rx-mode         = "infrared";
-                        clocks          = <&CLK_SYSIN>;
+                        clocks          = <&clk_sysin>;
                        pinctrl-names   = "default";
                        pinctrl-0       = <&pinctrl_ir>;
                        resets          = <&softreset STIH416_IRB_SOFTRESET>;
@@ -224,5 +224,17 @@
                        status = "disabled";
                };
+                keyscan: keyscan@fe4b0000 {
+                        compatible = "st,sti-keyscan";
+                        status = "disabled";
+                        reg = <0xfe4b0000 0x2000>;
+                        interrupts = <GIC_SPI 212 IRQ_TYPE_NONE>;
+                        clocks = <&clk_sysin>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_keyscan>;
+                        resets  = <&powerdown STIH416_KEYSCAN_POWERDOWN>,
+                                  <&softreset STIH416_KEYSCAN_SOFTRESET>;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2000.dtsi b/arch/arm/boot/dts/stih41x-b2000.dtsi
index bf65c49095af..b3dd6ca5c2ae 100644
--- a/arch/arm/boot/dts/stih41x-b2000.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2000.dtsi
@@ -6,6 +6,7 @@
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
+#include <dt-bindings/input/input.h>
 / {
        memory{
@@ -14,7 +15,7 @@
        };
        chosen {
-                bootargs = "console=ttyAS0,115200";
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
                linux,stdout-path = &serial2;
        };
@@ -68,5 +69,27 @@
                        snps,reset-active-low;
                        snps,reset-delays-us    = <0 10000 10000>;
                };
+                keyscan: keyscan@fe4b0000 {
+                        keypad,num-rows = <4>;
+                        keypad,num-columns = <4>;
+                        st,debounce-us = <5000>;
+                        linux,keymap = < MATRIX_KEY(0x00, 0x00, KEY_F13)
+                                         MATRIX_KEY(0x00, 0x01, KEY_F9)
+                                         MATRIX_KEY(0x00, 0x02, KEY_F5)
+                                         MATRIX_KEY(0x00, 0x03, KEY_F1)
+                                         MATRIX_KEY(0x01, 0x00, KEY_F14)
+                                         MATRIX_KEY(0x01, 0x01, KEY_F10)
+                                         MATRIX_KEY(0x01, 0x02, KEY_F6)
+                                         MATRIX_KEY(0x01, 0x03, KEY_F2)
+                                         MATRIX_KEY(0x02, 0x00, KEY_F15)
+                                         MATRIX_KEY(0x02, 0x01, KEY_F11)
+                                         MATRIX_KEY(0x02, 0x02, KEY_F7)
+                                         MATRIX_KEY(0x02, 0x03, KEY_F3)
+                                         MATRIX_KEY(0x03, 0x00, KEY_F16)
+                                         MATRIX_KEY(0x03, 0x01, KEY_F12)
+                                         MATRIX_KEY(0x03, 0x02, KEY_F8)
+                                         MATRIX_KEY(0x03, 0x03, KEY_F4) >;
+                };
        };
 };
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 838513f9ddc0..d8a84295c328 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -14,7 +14,7 @@
        };
        chosen {
-                bootargs = "console=ttyAS0,115200";
+                bootargs = "console=ttyAS0,115200 clk_ignore_unused";
                linux,stdout-path = &sbc_serial1;
        };
diff --git a/arch/arm/boot/dts/stih41x.dtsi b/arch/arm/boot/dts/stih41x.dtsi
index f5b9898d9c6e..5cb0e63376b5 100644
--- a/arch/arm/boot/dts/stih41x.dtsi
+++ b/arch/arm/boot/dts/stih41x.dtsi
@@ -1,3 +1,10 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
 / {
        #address-cells = <1>;
        #size-cells = <1>;
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index fa746aea5e66..0b97c071dd56 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -36,6 +36,16 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 4684cbe6843b..c200eacc66e8 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -34,6 +34,16 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index d7c17e46ce23..547fadcb984b 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -36,6 +36,16 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index fe9272ee55c3..f13723e18b86 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -24,6 +24,16 @@
        };
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index dd84a9e313b3..c01cea50cf0c 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -20,6 +20,16 @@
        compatible = "pineriver,mini-xplus", "allwinner,sun4i-a10";
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index 66cf0c7cf5b7..d46a7dbecef5 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -33,6 +33,16 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index 255b47e7019c..fb03bccb78d2 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -34,6 +34,16 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 9174724571e2..d96e179490ce 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -377,6 +377,42 @@
                        #size-cells = <0>;
                };
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun4i-a10-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <32>;
+                        status = "disabled";
+                };
+                mmc1: mmc@01c10000 {
+                        compatible = "allwinner,sun4i-a10-mmc";
+                        reg = <0x01c10000 0x1000>;
+                        clocks = <&ahb_gates 9>, <&mmc1_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun4i-a10-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <34>;
+                        status = "disabled";
+                };
+                mmc3: mmc@01c12000 {
+                        compatible = "allwinner,sun4i-a10-mmc";
+                        reg = <0x01c12000 0x1000>;
+                        clocks = <&ahb_gates 11>, <&mmc3_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <35>;
+                        status = "disabled";
+                };
                usbphy: phy@01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun4i-a10-usb-phy";
@@ -477,6 +513,20 @@
                        #size-cells = <0>;
                        #gpio-cells = <3>;
+                        pwm0_pins_a: pwm0@0 {
+                                allwinner,pins = "PB2";
+                                allwinner,function = "pwm";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        pwm1_pins_a: pwm1@0 {
+                                allwinner,pins = "PI3";
+                                allwinner,function = "pwm";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        uart0_pins_a: uart0@0 {
                                allwinner,pins = "PB22", "PB23";
                                allwinner,function = "uart0";
@@ -529,6 +579,20 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
+                        mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH1";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
                };
                timer@01c20c00 {
@@ -549,6 +613,14 @@
                        interrupts = <24>;
                };
+                pwm: pwm@01c20e00 {
+                        compatible = "allwinner,sun4i-a10-pwm";
+                        reg = <0x01c20e00 0xc>;
+                        clocks = <&osc24M>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
                sid: eeprom@01c23800 {
                        compatible = "allwinner,sun4i-a10-sid";
                        reg = <0x01c23800 0x10>;
@@ -641,30 +713,36 @@
                };
                i2c0: i2c@01c2ac00 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <7>;
                        clocks = <&apb1_gates 0>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c1: i2c@01c2b000 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <8>;
                        clocks = <&apb1_gates 1>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c2: i2c@01c2b400 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <9>;
                        clocks = <&apb1_gates 2>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 23611b71d3aa..ea9519da5764 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -35,6 +35,26 @@
                        };
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino_micro>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 1 0>; /* PG1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc1: mmc@01c10000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc1_pins_a>, <&mmc1_cd_pin_olinuxino_micro>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 13 0>; /* PG13 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        status = "okay";
@@ -49,6 +69,20 @@
                };
                pinctrl@01c20800 {
+                        mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
+                                allwinner,pins = "PG1";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                        mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
+                                allwinner,pins = "PG13";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PE3";
                                allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
new file mode 100644
index 000000000000..43a93762d4f2
--- /dev/null
+++ b/arch/arm/boot/dts/sun5i-a10s-r7-tv-dongle.dts
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun5i-a10s.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "R7 A10s hdmi tv-stick";
+        compatible = "allwinner,r7-tv-dongle", "allwinner,sun5i-a10s";
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_r7>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 1 0>; /* PG1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc1: mmc@01c10000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc1_pins_a>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        mmc0_cd_pin_r7: mmc0_cd_pin@0 {
+                                allwinner,pins = "PG1";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                        led_pins_r7: led_pins@0 {
+                                allwinner,pins = "PB2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <1>;
+                                allwinner,pull = <0>;
+                        };
+                        usb1_vbus_pin_r7: usb1_vbus_pin@0 {
+                                allwinner,pins = "PG13";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_r7>;
+                green {
+                        label = "r7-tv-dongle:green:usr";
+                        gpios = <&pio 1 2 0>;
+                        default-state = "on";
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_r7>;
+                gpio = <&pio 6 13 0>;
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 79989ed5658d..b64f705d9008 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -338,6 +338,33 @@
                        #size-cells = <0>;
                };
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <32>;
+                        status = "disabled";
+                };
+                mmc1: mmc@01c10000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c10000 0x1000>;
+                        clocks = <&ahb_gates 9>, <&mmc1_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <33>;
+                        status = "disabled";
+                };
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <34>;
+                        status = "disabled";
+                };
                usbphy: phy@01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun5i-a13-usb-phy";
@@ -451,6 +478,20 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
+                        mmc1_pins_a: mmc1@0 {
+                                allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
+                                allwinner,function = "mmc1";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -519,7 +560,7 @@
                i2c0: i2c@01c2ac00 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <7>;
                        clocks = <&apb1_gates 0>;
@@ -530,7 +571,7 @@
                i2c1: i2c@01c2b000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <8>;
                        clocks = <&apb1_gates 1>;
@@ -541,7 +582,7 @@
                i2c2: i2c@01c2b400 {
                        #address-cells = <1>;
                        #size-cells = <0>;
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <9>;
                        clocks = <&apb1_gates 2>;
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index 11169d5b5b86..fa44b026483b 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -21,6 +21,16 @@
        compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxinom>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 0 0>; /* PG0 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        status = "okay";
@@ -35,6 +45,13 @@
                };
                pinctrl@01c20800 {
+                        mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
+                                allwinner,pins = "PG0";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
                        led_pins_olinuxinom: led_pins@0 {
                                allwinner,pins = "PG9";
                                allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 7a9187bbeb28..429994e1943e 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -20,6 +20,16 @@
        compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_olinuxino>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 6 0 0>; /* PG0 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        status = "okay";
@@ -34,6 +44,13 @@
                };
                pinctrl@01c20800 {
+                        mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
+                                allwinner,pins = "PG0";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PG9";
                                allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index f01c315bdc4b..3b2a94c40f6e 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -320,6 +320,24 @@
                        #size-cells = <0>;
                };
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <32>;
+                        status = "disabled";
+                };
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <34>;
+                        status = "disabled";
+                };
                usbphy: phy@01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun5i-a13-usb-phy";
@@ -415,6 +433,13 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -461,30 +486,36 @@
                };
                i2c0: i2c@01c2ac00 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <7>;
                        clocks = <&apb1_gates 0>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c1: i2c@01c2b000 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <8>;
                        clocks = <&apb1_gates 1>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c2: i2c@01c2b400 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <9>;
                        clocks = <&apb1_gates 2>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                timer@01c60000 {
diff --git a/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
new file mode 100644
index 000000000000..2bbf8867362b
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-app4-evb1.dts
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Boris Brezillon
+ *
+ * Boris Brezillon <boris.brezillon@free-electrons.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun6i-a31.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "Allwinner A31 APP4 EVB1 Evaluation Board";
+        compatible = "allwinner,app4-evb1", "allwinner,sun6i-a31";
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc@01c00000 {
+                pio: pinctrl@01c20800 {
+                        usb1_vbus_pin_a: usb1_vbus_pin@0 {
+                                allwinner,pins = "PH27";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                usbphy: phy@01c19400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c1a000 {
+                        status = "okay";
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                pinctrl-0 = <&usb1_vbus_pin_a>;
+                gpio = <&pio 7 27 0>;
+                status = "okay";
+        };
+};
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 3898a7bce831..546cf6eff5c7 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -13,6 +13,7 @@
 /dts-v1/;
 /include/ "sun6i-a31.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
 / {
        model = "WITS A31 Colombus Evaluation Board";
@@ -23,6 +24,45 @@
        };
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_colombus>;
+                        vmmc-supply = <&reg_vcc3v0>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 0 8 0>; /* PA8 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                usbphy: phy@01c19400 {
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci1: usb@01c1b000 {
+                        status = "okay";
+                };
+                pio: pinctrl@01c20800 {
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pull = <1>;
+                        };
+                        mmc0_cd_pin_colombus: mmc0_cd_pin@0 {
+                                allwinner,pins = "PA8";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                        usb2_vbus_pin_colombus: usb2_vbus_pin@0 {
+                                allwinner,pins = "PH24";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;
@@ -47,4 +87,11 @@
                        status = "okay";
                };
        };
+        reg_usb2_vbus: usb2-vbus {
+                pinctrl-names = "default";
+                pinctrl-0 = <&usb2_vbus_pin_colombus>;
+                gpio = <&pio 7 24 0>;
+                status = "okay";
+        };
 };
diff --git a/arch/arm/boot/dts/sun6i-a31-m9.dts b/arch/arm/boot/dts/sun6i-a31-m9.dts
new file mode 100644
index 000000000000..bc6115da5ae1
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-m9.dts
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun6i-a31.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "Mele M9 / A1000G Quad top set box";
+        compatible = "mele,m9", "allwinner,sun6i-a31";
+        chosen {
+                bootargs = "earlyprintk console=ttyS0,115200";
+        };
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_m9>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 22 0>; /* PH22 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                pio: pinctrl@01c20800 {
+                        mmc0_cd_pin_m9: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH22";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index d45efa74827c..a9dfa12eb735 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -27,6 +27,7 @@
        cpus {
+                enable-method = "allwinner,sun6i-a31";
                #address-cells = <1>;
                #size-cells = <0>;
@@ -59,6 +60,14 @@
                reg = <0x40000000 0x80000000>;
        };
+        pmu {
+                compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+                interrupts = <0 120 4>,
+                             <0 121 4>,
+                             <0 122 4>,
+                             <0 123 4>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -198,6 +207,38 @@
                                        "apb2_uart4", "apb2_uart5";
                };
+                mmc0_clk: clk@01c20088 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c20088 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc0";
+                };
+                mmc1_clk: clk@01c2008c {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c2008c 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc1";
+                };
+                mmc2_clk: clk@01c20090 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c20090 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc2";
+                };
+                mmc3_clk: clk@01c20094 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun4i-a10-mod0-clk";
+                        reg = <0x01c20094 0x4>;
+                        clocks = <&osc24M>, <&pll6>;
+                        clock-output-names = "mmc3";
+                };
                spi0_clk: clk@01c200a0 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -229,6 +270,17 @@
                        clocks = <&osc24M>, <&pll6>;
                        clock-output-names = "spi3";
                };
+                usb_clk: clk@01c200cc {
+                        #clock-cells = <1>;
+                        #reset-cells = <1>;
+                        compatible = "allwinner,sun6i-a31-usb-clk";
+                        reg = <0x01c200cc 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
+                                             "usb_ohci0", "usb_ohci1",
+                                             "usb_ohci2";
+                };
        };
        soc@01c00000 {
@@ -237,12 +289,134 @@
                #size-cells = <1>;
                ranges;
-                nmi_intc: interrupt-controller@01f00c0c {
+                dma: dma-controller@01c02000 {
-                        compatible = "allwinner,sun6i-a31-sc-nmi";
+                        compatible = "allwinner,sun6i-a31-dma";
-                        interrupt-controller;
+                        reg = <0x01c02000 0x1000>;
-                        #interrupt-cells = <2>;
+                        interrupts = <0 50 4>;
-                        reg = <0x01f00c0c 0x38>;
+                        clocks = <&ahb1_gates 6>;
-                        interrupts = <0 32 4>;
+                        resets = <&ahb1_rst 6>;
+                        #dma-cells = <1>;
+                };
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb1_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 8>;
+                        reset-names = "ahb";
+                        interrupts = <0 60 4>;
+                        status = "disabled";
+                };
+                mmc1: mmc@01c10000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c10000 0x1000>;
+                        clocks = <&ahb1_gates 9>, <&mmc1_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 9>;
+                        reset-names = "ahb";
+                        interrupts = <0 61 4>;
+                        status = "disabled";
+                };
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb1_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 10>;
+                        reset-names = "ahb";
+                        interrupts = <0 62 4>;
+                        status = "disabled";
+                };
+                mmc3: mmc@01c12000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c12000 0x1000>;
+                        clocks = <&ahb1_gates 11>, <&mmc3_clk>;
+                        clock-names = "ahb", "mmc";
+                        resets = <&ahb1_rst 11>;
+                        reset-names = "ahb";
+                        interrupts = <0 63 4>;
+                        status = "disabled";
+                };
+                usbphy: phy@01c19400 {
+                        compatible = "allwinner,sun6i-a31-usb-phy";
+                        reg = <0x01c19400 0x10>,
+                              <0x01c1a800 0x4>,
+                              <0x01c1b800 0x4>;
+                        reg-names = "phy_ctrl",
+                                    "pmu1",
+                                    "pmu2";
+                        clocks = <&usb_clk 8>,
+                                 <&usb_clk 9>,
+                                 <&usb_clk 10>;
+                        clock-names = "usb0_phy",
+                                      "usb1_phy",
+                                      "usb2_phy";
+                        resets = <&usb_clk 0>,
+                                 <&usb_clk 1>,
+                                 <&usb_clk 2>;
+                        reset-names = "usb0_reset",
+                                      "usb1_reset",
+                                      "usb2_reset";
+                        status = "disabled";
+                        #phy-cells = <1>;
+                };
+                ehci0: usb@01c1a000 {
+                        compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+                        reg = <0x01c1a000 0x100>;
+                        interrupts = <0 72 4>;
+                        clocks = <&ahb1_gates 26>;
+                        resets = <&ahb1_rst 26>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci0: usb@01c1a400 {
+                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+                        reg = <0x01c1a400 0x100>;
+                        interrupts = <0 73 4>;
+                        clocks = <&ahb1_gates 29>, <&usb_clk 16>;
+                        resets = <&ahb1_rst 29>;
+                        phys = <&usbphy 1>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ehci1: usb@01c1b000 {
+                        compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
+                        reg = <0x01c1b000 0x100>;
+                        interrupts = <0 74 4>;
+                        clocks = <&ahb1_gates 27>;
+                        resets = <&ahb1_rst 27>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci1: usb@01c1b400 {
+                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+                        reg = <0x01c1b400 0x100>;
+                        interrupts = <0 75 4>;
+                        clocks = <&ahb1_gates 30>, <&usb_clk 17>;
+                        resets = <&ahb1_rst 30>;
+                        phys = <&usbphy 2>;
+                        phy-names = "usb";
+                        status = "disabled";
+                };
+                ohci2: usb@01c1c400 {
+                        compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
+                        reg = <0x01c1c400 0x100>;
+                        interrupts = <0 77 4>;
+                        clocks = <&ahb1_gates 31>, <&usb_clk 18>;
+                        resets = <&ahb1_rst 31>;
+                        status = "disabled";
                };
                pio: pinctrl@01c20800 {
@@ -286,6 +460,13 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
                };
                ahb1_rst: reset@01c202c0 {
@@ -330,6 +511,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 16>;
                        resets = <&apb2_rst 16>;
+                        dmas = <&dma 6>, <&dma 6>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -341,6 +524,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 17>;
                        resets = <&apb2_rst 17>;
+                        dmas = <&dma 7>, <&dma 7>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -352,6 +537,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 18>;
                        resets = <&apb2_rst 18>;
+                        dmas = <&dma 8>, <&dma 8>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -363,6 +550,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 19>;
                        resets = <&apb2_rst 19>;
+                        dmas = <&dma 9>, <&dma 9>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -374,6 +563,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 20>;
                        resets = <&apb2_rst 20>;
+                        dmas = <&dma 10>, <&dma 10>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -385,6 +576,8 @@
                        reg-io-width = <4>;
                        clocks = <&apb2_gates 21>;
                        resets = <&apb2_rst 21>;
+                        dmas = <&dma 22>, <&dma 22>;
+                        dma-names = "rx", "tx";
                        status = "disabled";
                };
@@ -428,12 +621,25 @@
                        status = "disabled";
                };
+                timer@01c60000 {
+                        compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
+                        reg = <0x01c60000 0x1000>;
+                        interrupts = <0 51 4>,
+                                     <0 52 4>,
+                                     <0 53 4>,
+                                     <0 54 4>;
+                        clocks = <&ahb1_gates 19>;
+                        resets = <&ahb1_rst 19>;
+                };
                spi0: spi@01c68000 {
                        compatible = "allwinner,sun6i-a31-spi";
                        reg = <0x01c68000 0x1000>;
                        interrupts = <0 65 4>;
                        clocks = <&ahb1_gates 20>, <&spi0_clk>;
                        clock-names = "ahb", "mod";
+                        dmas = <&dma 23>, <&dma 23>;
+                        dma-names = "rx", "tx";
                        resets = <&ahb1_rst 20>;
                        status = "disabled";
                };
@@ -444,6 +650,8 @@
                        interrupts = <0 66 4>;
                        clocks = <&ahb1_gates 21>, <&spi1_clk>;
                        clock-names = "ahb", "mod";
+                        dmas = <&dma 24>, <&dma 24>;
+                        dma-names = "rx", "tx";
                        resets = <&ahb1_rst 21>;
                        status = "disabled";
                };
@@ -454,6 +662,8 @@
                        interrupts = <0 67 4>;
                        clocks = <&ahb1_gates 22>, <&spi2_clk>;
                        clock-names = "ahb", "mod";
+                        dmas = <&dma 25>, <&dma 25>;
+                        dma-names = "rx", "tx";
                        resets = <&ahb1_rst 22>;
                        status = "disabled";
                };
@@ -464,6 +674,8 @@
                        interrupts = <0 68 4>;
                        clocks = <&ahb1_gates 23>, <&spi3_clk>;
                        clock-names = "ahb", "mod";
+                        dmas = <&dma 26>, <&dma 26>;
+                        dma-names = "rx", "tx";
                        resets = <&ahb1_rst 23>;
                        status = "disabled";
                };
@@ -479,14 +691,74 @@
                        interrupts = <1 9 0xf04>;
                };
+                nmi_intc: interrupt-controller@01f00c0c {
+                        compatible = "allwinner,sun6i-a31-sc-nmi";
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        reg = <0x01f00c0c 0x38>;
+                        interrupts = <0 32 4>;
+                };
+                prcm@01f01400 {
+                        compatible = "allwinner,sun6i-a31-prcm";
+                        reg = <0x01f01400 0x200>;
+                        ar100: ar100_clk {
+                                compatible = "allwinner,sun6i-a31-ar100-clk";
+                                #clock-cells = <0>;
+                                clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
+                                clock-output-names = "ar100";
+                        };
+                        ahb0: ahb0_clk {
+                                compatible = "fixed-factor-clock";
+                                #clock-cells = <0>;
+                                clock-div = <1>;
+                                clock-mult = <1>;
+                                clocks = <&ar100>;
+                                clock-output-names = "ahb0";
+                        };
+                        apb0: apb0_clk {
+                                compatible = "allwinner,sun6i-a31-apb0-clk";
+                                #clock-cells = <0>;
+                                clocks = <&ahb0>;
+                                clock-output-names = "apb0";
+                        };
+                        apb0_gates: apb0_gates_clk {
+                                compatible = "allwinner,sun6i-a31-apb0-gates-clk";
+                                #clock-cells = <1>;
+                                clocks = <&apb0>;
+                                clock-output-names = "apb0_pio", "apb0_ir",
+                                                "apb0_timer", "apb0_p2wi",
+                                                "apb0_uart", "apb0_1wire",
+                                                "apb0_i2c";
+                        };
+                        apb0_rst: apb0_rst {
+                                compatible = "allwinner,sun6i-a31-clock-reset";
+                                #reset-cells = <1>;
+                        };
+                };
                cpucfg@01f01c00 {
                        compatible = "allwinner,sun6i-a31-cpuconfig";
                        reg = <0x01f01c00 0x300>;
                };
-                prcm@01f01c00 {
+                r_pio: pinctrl@01f02c00 {
-                        compatible = "allwinner,sun6i-a31-prcm";
+                        compatible = "allwinner,sun6i-a31-r-pinctrl";
-                        reg = <0x01f01400 0x200>;
+                        reg = <0x01f02c00 0x400>;
+                        interrupts = <0 45 4>,
+                                     <0 46 4>;
+                        clocks = <&apb0_gates 0>;
+                        resets = <&apb0_rst 0>;
+                        gpio-controller;
+                        interrupt-controller;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        #gpio-cells = <3>;
                };
        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 68de89ffbdfa..a5ad945197e8 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -20,6 +20,16 @@
        compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index cb25d3c8da58..b87fea901489 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -20,6 +20,25 @@
        compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc3: mmc@01c12000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc3_pins_a>;
+                        vmmc-supply = <&reg_vmmc3>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
@@ -48,6 +67,18 @@
                };
                pinctrl@01c20800 {
+                        mmc3_pins_a: mmc3@0 {
+                                /* AP6210 requires pull-up */
+                                allwinner,pull = <1>;
+                        };
+                        vmmc3_pin_cubietruck: vmmc3_pin@0 {
+                                allwinner,pins = "PH9";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        ahci_pwr_pin_cubietruck: ahci_pwr_pin@1 {
                                allwinner,pins = "PH12";
                                allwinner,function = "gpio_out";
@@ -63,6 +94,12 @@
                        };
                };
+                pwm: pwm@01c20e00 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pwm0_pins_a>, <&pwm1_pins_a>;
+                        status = "okay";
+                };
                uart0: serial@01c28000 {
                        pinctrl-names = "default";
                        pinctrl-0 = <&uart0_pins_a>;
@@ -139,4 +176,15 @@
        reg_usb2_vbus: usb2-vbus {
                status = "okay";
        };
+        reg_vmmc3: vmmc3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&vmmc3_pin_cubietruck>;
+                regulator-name = "vmmc3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pio 7 9 0>;
+        };
 };
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
new file mode 100644
index 000000000000..b77308e90199
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/dts-v1/;
+/include/ "sun7i-a20.dtsi"
+/include/ "sunxi-common-regulators.dtsi"
+/ {
+        model = "I12 / Q5 / QT840A A20 tvbox";
+        compatible = "allwinner,i12-tvbox", "allwinner,sun7i-a20";
+        soc@01c00000 {
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc3: mmc@01c12000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc3_pins_a>;
+                        vmmc-supply = <&reg_vmmc3>;
+                        bus-width = <4>;
+                        non-removable;
+                        status = "okay";
+                };
+                usbphy: phy@01c13400 {
+                        usb1_vbus-supply = <&reg_usb1_vbus>;
+                        usb2_vbus-supply = <&reg_usb2_vbus>;
+                        status = "okay";
+                };
+                ehci0: usb@01c14000 {
+                        status = "okay";
+                };
+                ohci0: usb@01c14400 {
+                        status = "okay";
+                };
+                ehci1: usb@01c1c000 {
+                        status = "okay";
+                };
+                ohci1: usb@01c1c400 {
+                        status = "okay";
+                };
+                pinctrl@01c20800 {
+                        mmc3_pins_a: mmc3@0 {
+                                /* AP6210 / AP6330 requires pull-up */
+                                allwinner,pull = <1>;
+                        };
+                        vmmc3_pin_i12_tvbox: vmmc3_pin@0 {
+                                allwinner,pins = "PH2";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        vmmc3_io_pin_i12_tvbox: vmmc3_io_pin@0 {
+                                allwinner,pins = "PH12";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        gmac_power_pin_i12_tvbox: gmac_power_pin@0 {
+                                allwinner,pins = "PH21";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        led_pins_i12_tvbox: led_pins@0 {
+                                allwinner,pins = "PH9", "PH20";
+                                allwinner,function = "gpio_out";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                };
+                uart0: serial@01c28000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&uart0_pins_a>;
+                        status = "okay";
+                };
+                gmac: ethernet@01c50000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&gmac_pins_mii_a>;
+                        phy = <&phy1>;
+                        phy-mode = "mii";
+                        phy-supply = <&reg_gmac_3v3>;
+                        status = "okay";
+                        phy1: ethernet-phy@1 {
+                                reg = <1>;
+                        };
+                };
+        };
+        leds {
+                compatible = "gpio-leds";
+                pinctrl-names = "default";
+                pinctrl-0 = <&led_pins_i12_tvbox>;
+                red {
+                        label = "i12_tvbox:red:usr";
+                        gpios = <&pio 7 9 1>;
+                };
+                blue {
+                        label = "i12_tvbox:blue:usr";
+                        gpios = <&pio 7 20 0>;
+                };
+        };
+        reg_usb1_vbus: usb1-vbus {
+                status = "okay";
+        };
+        reg_usb2_vbus: usb2-vbus {
+                status = "okay";
+        };
+        reg_vmmc3: vmmc3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&vmmc3_pin_i12_tvbox>;
+                regulator-name = "vmmc3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                gpio = <&pio 7 2 0>;
+        };
+        reg_vmmc3_io: vmmc3-io {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&vmmc3_io_pin_i12_tvbox>;
+                regulator-name = "vmmc3-io";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                /* This controls VCC-PI, must be always on! */
+                regulator-always-on;
+                enable-active-high;
+                gpio = <&pio 7 12 0>;
+        };
+        reg_gmac_3v3: gmac-3v3 {
+                compatible = "regulator-fixed";
+                pinctrl-names = "default";
+                pinctrl-0 = <&gmac_power_pin_i12_tvbox>;
+                regulator-name = "gmac-3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                startup-delay-us = <50000>;
+                enable-active-high;
+                gpio = <&pio 7 21 0>;
+        };
+};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index eeadf76362fa..b759630bc9a9 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -31,6 +31,26 @@
                        status = "okay";
                };
+                mmc0: mmc@01c0f000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 1 0>; /* PH1 */
+                        cd-inverted;
+                        status = "okay";
+                };
+                mmc3: mmc@01c12000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mmc3_pins_a>, <&mmc3_cd_pin_olinuxinom>;
+                        vmmc-supply = <&reg_vcc3v3>;
+                        bus-width = <4>;
+                        cd-gpios = <&pio 7 11 0>; /* PH11 */
+                        cd-inverted;
+                        status = "okay";
+                };
                usbphy: phy@01c13400 {
                        usb1_vbus-supply = <&reg_usb1_vbus>;
                        usb2_vbus-supply = <&reg_usb2_vbus>;
@@ -65,6 +85,13 @@
                };
                pinctrl@01c20800 {
+                        mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
+                                allwinner,pins = "PH11";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
                        led_pins_olinuxino: led_pins@0 {
                                allwinner,pins = "PH2";
                                allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 32efc105df83..01e94664232a 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -57,6 +57,12 @@
                             <1 10 0xf08>;
        };
+        pmu {
+                compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
+                interrupts = <0 120 4>,
+                             <0 121 4>;
+        };
        clocks {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -87,7 +93,7 @@
                pll4: clk@01c20018 {
                        #clock-cells = <0>;
-                        compatible = "allwinner,sun4i-a10-pll1-clk";
+                        compatible = "allwinner,sun7i-a20-pll4-clk";
                        reg = <0x01c20018 0x4>;
                        clocks = <&osc24M>;
                        clock-output-names = "pll4";
@@ -109,6 +115,14 @@
                        clock-output-names = "pll6_sata", "pll6_other", "pll6";
                };
+                pll8: clk@01c20040 {
+                        #clock-cells = <0>;
+                        compatible = "allwinner,sun7i-a20-pll4-clk";
+                        reg = <0x01c20040 0x4>;
+                        clocks = <&osc24M>;
+                        clock-output-names = "pll8";
+                };
                cpu: cpu@01c20054 {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun4i-a10-cpu-clk";
@@ -447,6 +461,42 @@
                        #size-cells = <0>;
                };
+                mmc0: mmc@01c0f000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c0f000 0x1000>;
+                        clocks = <&ahb_gates 8>, <&mmc0_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <0 32 4>;
+                        status = "disabled";
+                };
+                mmc1: mmc@01c10000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c10000 0x1000>;
+                        clocks = <&ahb_gates 9>, <&mmc1_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <0 33 4>;
+                        status = "disabled";
+                };
+                mmc2: mmc@01c11000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c11000 0x1000>;
+                        clocks = <&ahb_gates 10>, <&mmc2_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <0 34 4>;
+                        status = "disabled";
+                };
+                mmc3: mmc@01c12000 {
+                        compatible = "allwinner,sun5i-a13-mmc";
+                        reg = <0x01c12000 0x1000>;
+                        clocks = <&ahb_gates 11>, <&mmc3_clk>;
+                        clock-names = "ahb", "mmc";
+                        interrupts = <0 35 4>;
+                        status = "disabled";
+                };
                usbphy: phy@01c13400 {
                        #phy-cells = <1>;
                        compatible = "allwinner,sun7i-a20-usb-phy";
@@ -540,6 +590,20 @@
                        #size-cells = <0>;
                        #gpio-cells = <3>;
+                        pwm0_pins_a: pwm0@0 {
+                                allwinner,pins = "PB2";
+                                allwinner,function = "pwm";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
+                        pwm1_pins_a: pwm1@0 {
+                                allwinner,pins = "PI3";
+                                allwinner,function = "pwm";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <0>;
+                        };
                        uart0_pins_a: uart0@0 {
                                allwinner,pins = "PB22", "PB23";
                                allwinner,function = "uart0";
@@ -653,6 +717,27 @@
                                allwinner,drive = <0>;
                                allwinner,pull = <0>;
                        };
+                        mmc0_pins_a: mmc0@0 {
+                                allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+                                allwinner,function = "mmc0";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
+                        mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+                                allwinner,pins = "PH1";
+                                allwinner,function = "gpio_in";
+                                allwinner,drive = <0>;
+                                allwinner,pull = <1>;
+                        };
+                        mmc3_pins_a: mmc3@0 {
+                                allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+                                allwinner,function = "mmc3";
+                                allwinner,drive = <2>;
+                                allwinner,pull = <0>;
+                        };
                };
                timer@01c20c00 {
@@ -678,6 +763,14 @@
                        interrupts = <0 24 4>;
                };
+                pwm: pwm@01c20e00 {
+                        compatible = "allwinner,sun7i-a20-pwm";
+                        reg = <0x01c20e00 0xc>;
+                        clocks = <&osc24M>;
+                        #pwm-cells = <3>;
+                        status = "disabled";
+                };
                sid: eeprom@01c23800 {
                        compatible = "allwinner,sun7i-a20-sid";
                        reg = <0x01c23800 0x200>;
@@ -770,48 +863,58 @@
                };
                i2c0: i2c@01c2ac00 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2ac00 0x400>;
                        interrupts = <0 7 4>;
                        clocks = <&apb1_gates 0>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c1: i2c@01c2b000 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b000 0x400>;
                        interrupts = <0 8 4>;
                        clocks = <&apb1_gates 1>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c2: i2c@01c2b400 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b400 0x400>;
                        interrupts = <0 9 4>;
                        clocks = <&apb1_gates 2>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                i2c3: i2c@01c2b800 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
                        reg = <0x01c2b800 0x400>;
                        interrupts = <0 88 4>;
                        clocks = <&apb1_gates 3>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
-                i2c4: i2c@01c2bc00 {
+                i2c4: i2c@01c2c000 {
-                        compatible = "allwinner,sun4i-i2c";
+                        compatible = "allwinner,sun7i-a20-i2c", "allwinner,sun4i-a10-i2c";
-                        reg = <0x01c2bc00 0x400>;
+                        reg = <0x01c2c000 0x400>;
                        interrupts = <0 89 4>;
                        clocks = <&apb1_gates 15>;
                        clock-frequency = <100000>;
                        status = "disabled";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
                };
                gmac: ethernet@01c50000 {
diff --git a/arch/arm/boot/dts/sunxi-common-regulators.dtsi b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
index 18eeac0670b9..3d021efd1a38 100644
--- a/arch/arm/boot/dts/sunxi-common-regulators.dtsi
+++ b/arch/arm/boot/dts/sunxi-common-regulators.dtsi
@@ -72,4 +72,18 @@
                gpio = <&pio 7 3 0>;
                status = "disabled";
        };
+        reg_vcc3v0: vcc3v0 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v0";
+                regulator-min-microvolt = <3000000>;
+                regulator-max-microvolt = <3000000>;
+        };
+        reg_vcc3v3: vcc3v3 {
+                compatible = "regulator-fixed";
+                regulator-name = "vcc3v3";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+        };
 };
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index a288a12823ed..5c21d216515a 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -25,6 +25,7 @@
                hdmi@54280000 {
                        status = "okay";
+                        hdmi-supply = <&vdd_5v0_hdmi>;
                        vdd-supply = <&vdd_hdmi_reg>;
                        pll-supply = <&palmas_smps3_reg>;
@@ -36,6 +37,8 @@
                dsi@54300000 {
                        status = "okay";
+                        avdd-dsi-csi-supply = <&avdd_1v2_reg>;
                        panel@0 {
                                compatible = "panasonic,vvx10f004b00",
                                             "simple-panel";
@@ -982,12 +985,10 @@
                                                regulator-max-microvolt = <2800000>;
                                        };
-                                        ldo3 {
+                                        avdd_1v2_reg: ldo3 {
                                                regulator-name = "avdd-dsi-csi";
                                                regulator-min-microvolt = <1200000>;
                                                regulator-max-microvolt = <1200000>;
-                                                regulator-always-on;
-                                                regulator-boot-on;
                                        };
                                        ldo4 {
@@ -1105,6 +1106,7 @@
        sdhci@78000400 {
                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
                bus-width = <4>;
                status = "okay";
        };
@@ -1231,8 +1233,6 @@
                        regulator-name = "vdd_hdmi_5v0";
                        regulator-min-microvolt = <5000000>;
                        regulator-max-microvolt = <5000000>;
-                        enable-active-high;
-                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&tps65090_dcdc1_reg>;
                };
@@ -1245,6 +1245,17 @@
                        enable-active-high;
                        gpio = <&palmas_gpio 6 0>;
                };
+                vdd_5v0_hdmi: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "VDD_5V0_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&tps65090_dcdc1_reg>;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
new file mode 100644
index 000000000000..0b0e8e07d965
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -0,0 +1,1113 @@
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "tegra114.dtsi"
+/ {
+        model = "NVIDIA SHIELD";
+        compatible = "nvidia,roth", "nvidia,tegra114";
+        chosen {
+                /* SHIELD's bootloader's arguments need to be overridden */
+                bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:1";
+                /* SHIELD's bootloader will place initrd at this address */
+                linux,initrd-start = <0x82000000>;
+                linux,initrd-end = <0x82800000>;
+        };
+        firmware {
+                trusted-foundations {
+                        compatible = "tlm,trusted-foundations";
+                        tlm,version-major = <2>;
+                        tlm,version-minor = <8>;
+                };
+        };
+        memory {
+                /* memory >= 0x79600000 is reserved for firmware usage */
+                reg = <0x80000000 0x79600000>;
+        };
+        pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        clk1_out_pw4 {
+                                nvidia,pins = "clk1_out_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2",
+                                                "dap1_fs_pn0",
+                                                "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5",
+                                                "dap2_fs_pa2",
+                                                "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5",
+                                                "dap4_dout_pp6",
+                                                "dap4_fs_pp4",
+                                                "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0",
+                                                "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0",
+                                                "ulpi_data0_po1",
+                                                "ulpi_data1_po2",
+                                                "ulpi_data2_po3",
+                                                "ulpi_data3_po4",
+                                                "ulpi_data4_po5",
+                                                "ulpi_data5_po6",
+                                                "ulpi_data6_po7",
+                                                "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1",
+                                                "ulpi_nxt_py2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1",
+                                                "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0",
+                                                "pbb0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5",
+                                                "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_a16_pj7 {
+                                nvidia,pins = "gmi_a16_pj7",
+                                                "gmi_a19_pk7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_a17_pb0 {
+                                nvidia,pins = "gmi_a17_pb0",
+                                                "gmi_a18_pb1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad5_pg5 {
+                                nvidia,pins = "gmi_ad5_pg5",
+                                                "gmi_wr_n_pi0";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad6_pg6 {
+                                nvidia,pins = "gmi_ad6_pg6",
+                                                "gmi_ad7_pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad12_ph4 {
+                                nvidia,pins = "gmi_ad12_ph4";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_cs6_n_pi13 {
+                                nvidia,pins = "gmi_cs6_n_pi3";
+                                nvidia,function = "nand";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad9_ph1 {
+                                nvidia,pins = "gmi_ad9_ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_cs1_n_pj2 {
+                                nvidia,pins = "gmi_cs1_n_pj2",
+                                                "gmi_oe_n_pi1";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_rst_n_pi4 {
+                                nvidia,pins = "gmi_rst_n_pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_iordy_pi5 {
+                                nvidia,pins = "gmi_iordy_pi5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "extperiph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1",
+                                                "sdmmc1_dat0_py7",
+                                                "sdmmc1_dat1_py6",
+                                                "sdmmc1_dat2_py5",
+                                                "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7",
+                                                "sdmmc3_dat0_pb7",
+                                                "sdmmc3_dat1_pb6",
+                                                "sdmmc3_dat2_pb5",
+                                                "sdmmc3_dat3_pb4",
+                                                "sdmmc3_cd_n_pv2",
+                                                "sdmmc3_clk_lb_out_pee4",
+                                                "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7",
+                                                "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,function = "blink";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0",
+                                                "kb_col1_pq1",
+                                                "kb_col2_pq2",
+                                                "kb_row0_pr0",
+                                                "kb_row1_pr1",
+                                                "kb_row2_pr2",
+                                                "kb_row8_ps0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6",
+                                                "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        sys_clk_req_pz5 {
+                                nvidia,pins = "sys_clk_req_pz5";
+                                nvidia,function = "sysclk";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "cpu";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4",
+                                                "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1",
+                                                "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0",
+                                                "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "owr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4",
+                                                "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_ENABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,lock = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_adv_n_pk0 {
+                                nvidia,pins = "gmi_adv_n_pk0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_cs0_n_pj0 {
+                                nvidia,pins = "gmi_cs0_n_pj0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4",
+                                                "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x3_aud_px3 {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_w2_aud_pw2 {
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0",
+                                                "dap3_din_pp1",
+                                                "dap3_dout_pp2",
+                                                "dap3_sclk_pp3";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3",
+                                                "pbb5",
+                                                "pbb6",
+                                                "pbb7";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1",
+                                                "pcc2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad0_pg0 {
+                                nvidia,pins = "gmi_ad0_pg0",
+                                                "gmi_ad1_pg1";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad10_ph2 {
+                                nvidia,pins = "gmi_ad10_ph2",
+                                                "gmi_ad12_ph4",
+                                                "gmi_ad15_ph7",
+                                                "gmi_cs3_n_pk4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad11_ph3 {
+                                nvidia,pins = "gmi_ad11_ph3",
+                                                "gmi_ad13_ph5",
+                                                "gmi_ad8_ph0",
+                                                "gmi_clk_pk1",
+                                                "gmi_cs2_n_pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gmi_ad14_ph6 {
+                                nvidia,pins = "gmi_ad14_ph6",
+                                                "gmi_cs0_n_pj0",
+                                                "gmi_cs4_n_pk2",
+                                                "gmi_cs7_n_pi6",
+                                                "gmi_dqs_p_pj3",
+                                                "gmi_wp_n_pc7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gmi_ad2_pg2 {
+                                nvidia,pins = "gmi_ad2_pg2",
+                                                "gmi_ad3_pg3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "pwm2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6",
+                                                "kb_col7_pq7";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3",
+                                                "kb_row4_pr4",
+                                                "kb_row6_pr6";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        drive_sdio1 {
+                                nvidia,pins = "drive_sdio1";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <36>;
+                                nvidia,pull-up-strength = <20>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOW>;
+                        };
+                        drive_sdio3 {
+                                nvidia,pins = "drive_sdio3";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <36>;
+                                nvidia,pull-up-strength = <20>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                        };
+                        drive_gma {
+                                nvidia,pins = "drive_gma";
+                                nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+                                nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+                                nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
+                                nvidia,pull-down-strength = <2>;
+                                nvidia,pull-up-strength = <2>;
+                                nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+                                nvidia,drive-type = <1>;
+                        };
+                };
+        };
+        /* Usable on reworked devices only */
+        serial@70006300 {
+                status = "okay";
+        };
+        pwm@7000a000 {
+                status = "okay";
+        };
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+                regulator@43 {
+                        compatible = "ti,tps51632";
+                        reg = <0x43>;
+                        regulator-name = "vdd-cpu";
+                        regulator-min-microvolt = <500000>;
+                        regulator-max-microvolt = <1520000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+                palmas: pmic@58 {
+                        compatible = "ti,palmas";
+                        reg = <0x58>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        ti,system-power-controller;
+                        palmas_gpio: gpio {
+                                compatible = "ti,palmas-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                        };
+                        pmic {
+                                compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
+                                regulators {
+                                        smps12 {
+                                                regulator-name = "vdd-ddr";
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1500000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_1v8: smps3 {
+                                                regulator-name = "vdd-1v8";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps457 {
+                                                regulator-name = "vdd-soc";
+                                                regulator-min-microvolt = <900000>;
+                                                regulator-max-microvolt = <1400000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps8 {
+                                                regulator-name = "avdd-pll-1v05";
+                                                regulator-min-microvolt = <1050000>;
+                                                regulator-max-microvolt = <1050000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps9 {
+                                                regulator-name = "vdd-2v85-emmc";
+                                                regulator-min-microvolt = <2800000>;
+                                                regulator-max-microvolt = <2800000>;
+                                                regulator-always-on;
+                                        };
+                                        smps10_out1 {
+                                                regulator-name = "vdd-fan";
+                                                regulator-min-microvolt = <5000000>;
+                                                regulator-max-microvolt = <5000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps10_out2 {
+                                                regulator-name = "vdd-5v0-sys";
+                                                regulator-min-microvolt = <5000000>;
+                                                regulator-max-microvolt = <5000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo2 {
+                                                regulator-name = "vdd-2v8-display";
+                                                regulator-min-microvolt = <2800000>;
+                                                regulator-max-microvolt = <2800000>;
+                                                regulator-boot-on;
+                                        };
+                                        ldo3 {
+                                                regulator-name = "avdd-1v2";
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1200000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo4 {
+                                                regulator-name = "vpp-fuse";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                        };
+                                        ldo5 {
+                                                regulator-name = "avdd-hdmi-pll";
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1200000>;
+                                        };
+                                        ldo6 {
+                                                regulator-name = "vdd-sensor-2v8";
+                                                regulator-min-microvolt = <2850000>;
+                                                regulator-max-microvolt = <2850000>;
+                                        };
+                                        ldo8 {
+                                                regulator-name = "vdd-rtc";
+                                                regulator-min-microvolt = <1100000>;
+                                                regulator-max-microvolt = <1100000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                                ti,enable-ldo8-tracking;
+                                        };
+                                        vddio_sdmmc3: ldo9 {
+                                                regulator-name = "vddio-sdmmc3";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldousb {
+                                                regulator-name = "avdd-usb-hdmi";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_3v3_sys: regen1 {
+                                                regulator-name = "rail-3v3";
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        regen2 {
+                                                regulator-name = "rail-5v0";
+                                                regulator-max-microvolt = <5000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                };
+                        };
+                        rtc {
+                                compatible = "ti,palmas-rtc";
+                                interrupt-parent = <&palmas>;
+                                interrupts = <8 0>;
+                        };
+                };
+        };
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+        };
+        /* SD card */
+        sdhci@78000400 {
+                status = "okay";
+                bus-width = <4>;
+                vmmc-supply = <&vddio_sdmmc3>;
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                power-gpios = <&gpio TEGRA_GPIO(H, 0) GPIO_ACTIVE_HIGH>;
+        };
+        /* eMMC */
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+                vmmc-supply = <&vdd_1v8>;
+                non-removable;
+        };
+        /* External USB port (must be powered) */
+        usb@7d000000 {
+                status = "okay";
+        };
+        usb-phy@7d000000 {
+                status = "okay";
+                nvidia,xcvr-setup = <7>;
+                nvidia,xcvr-lsfslew = <2>;
+                nvidia,xcvr-lsrslew = <2>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                /* Should be changed to "otg" once we have vbus_supply */
+                /* As of now, USB devices need to be powered externally */
+                dr_mode = "host";
+        };
+        /* SHIELD controller */
+        usb@7d008000 {
+                status = "okay";
+        };
+        usb-phy@7d008000 {
+                status = "okay";
+                nvidia,xcvr-setup = <7>;
+                nvidia,xcvr-lsfslew = <2>;
+                nvidia,xcvr-lsrslew = <2>;
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 1 40000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                power-supply = <&lcd_bl_en>;
+                enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                back {
+                        label = "Back";
+                        gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_BACK>;
+                };
+                home {
+                        label = "Home";
+                        gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_HOME>;
+                };
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                lcd_bl_en: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "lcd_bl_en";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-boot-on;
+                };
+                regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "vdd_lcd_1v8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        vin-supply = <&vdd_1v8>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
+                        regulator-boot-on;
+                };
+                regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "vdd_1v8_ts";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 3) GPIO_ACTIVE_LOW>;
+                        regulator-boot-on;
+                };
+                regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "vdd_3v3_ts";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(H, 5) GPIO_ACTIVE_HIGH>;
+                        regulator-boot-on;
+                };
+                regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "vdd_1v8_com";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        vin-supply = <&vdd_1v8>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(X, 1) GPIO_ACTIVE_HIGH>;
+                        regulator-boot-on;
+                };
+                regulator@5 {
+                        compatible = "regulator-fixed";
+                        reg = <5>;
+                        regulator-name = "vdd_3v3_com";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        vin-supply = <&vdd_3v3_sys>;
+                        enable-active-high;
+                        gpio = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra114-tn7.dts b/arch/arm/boot/dts/tegra114-tn7.dts
new file mode 100644
index 000000000000..963662145635
--- /dev/null
+++ b/arch/arm/boot/dts/tegra114-tn7.dts
@@ -0,0 +1,348 @@
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "tegra114.dtsi"
+/ {
+        model = "Tegra Note 7";
+        compatible = "nvidia,tn7", "nvidia,tegra114";
+        chosen {
+                /* TN7's bootloader's arguments need to be overridden */
+                bootargs = "console=ttyS0,115200n8 console=tty1 gpt fbcon=rotate:2";
+                /* TN7's bootloader will place initrd at this address */
+                linux,initrd-start = <0x82000000>;
+                linux,initrd-end = <0x82800000>;
+        };
+        firmware {
+                trusted-foundations {
+                        compatible = "tlm,trusted-foundations";
+                        tlm,version-major = <2>;
+                        tlm,version-minor = <8>;
+                };
+        };
+        memory {
+                /* memory >= 0x37e00000 is reserved for firmware usage */
+                reg = <0x80000000 0x37e00000>;
+        };
+        host1x@50000000 {
+                dsi@54300000 {
+                        status = "okay";
+                        vdd-supply = <&vdd_1v2_ap>;
+                        panel@0 {
+                                compatible = "lg,ld070wx3-sl01";
+                                reg = <0>;
+                                power-supply = <&vdd_lcd>;
+                                backlight = <&backlight>;
+                        };
+                };
+        };
+        serial@70006300 {
+                status = "okay";
+        };
+        pwm@7000a000 {
+                status = "okay";
+        };
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+                palmas: pmic@58 {
+                        compatible = "ti,palmas";
+                        reg = <0x58>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        ti,system-power-controller;
+                        palmas_gpio: gpio {
+                                compatible = "ti,palmas-gpio";
+                                gpio-controller;
+                                #gpio-cells = <2>;
+                        };
+                        pmic {
+                                compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
+                                ldoln-in-supply = <&vdd_smps10_out2>;
+                                regulators {
+                                        smps123 {
+                                                regulator-name = "vd-cpu";
+                                                regulator-min-microvolt = <1000000>;
+                                                regulator-max-microvolt = <1000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps45 {
+                                                regulator-name = "vd-soc";
+                                                regulator-min-microvolt = <1100000>;
+                                                regulator-max-microvolt = <1100000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps6 {
+                                                regulator-name = "va-lcd-hv";
+                                                regulator-min-microvolt = <3000000>;
+                                                regulator-max-microvolt = <3000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        smps7 {
+                                                regulator-name = "vd-ddr";
+                                                regulator-min-microvolt = <1350000>;
+                                                regulator-max-microvolt = <1350000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_1v8: smps8 {
+                                                regulator-name = "vs-pmu-1v8";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_2v9_sys: smps9 {
+                                                regulator-name = "vs-sys-2v9";
+                                                regulator-min-microvolt = <2900000>;
+                                                regulator-max-microvolt = <2900000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_smps10_out1: smps10_out1 {
+                                                regulator-name = "vd-smps10-out1";
+                                                regulator-min-microvolt = <5000000>;
+                                                regulator-max-microvolt = <5000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_smps10_out2: smps10_out2 {
+                                                regulator-name = "vd-smps10-out2";
+                                                regulator-min-microvolt = <5000000>;
+                                                regulator-max-microvolt = <5000000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo1 {
+                                                regulator-name = "va-pllx";
+                                                regulator-min-microvolt = <1050000>;
+                                                regulator-max-microvolt = <1050000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        vdd_1v2_ap: ldo2 {
+                                                regulator-name = "va-ap-1v2";
+                                                regulator-min-microvolt = <1200000>;
+                                                regulator-max-microvolt = <1200000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo3 {
+                                                regulator-name = "vd-fuse";
+                                                regulator-min-microvolt = <1800000>;
+                                                regulator-max-microvolt = <1800000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo4 {
+                                                regulator-name = "vd-ts-hv";
+                                                regulator-min-microvolt = <3200000>;
+                                                regulator-max-microvolt = <3200000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo5 {
+                                                regulator-name = "va-cam2-hv";
+                                                regulator-min-microvolt = <2700000>;
+                                                regulator-max-microvolt = <2700000>;
+                                        };
+                                        ldo6 {
+                                                regulator-name = "va-sns-hv";
+                                                regulator-min-microvolt = <2850000>;
+                                                regulator-max-microvolt = <2850000>;
+                                        };
+                                        ldo7 {
+                                                regulator-name = "va-cam1-hv";
+                                                regulator-min-microvolt = <2700000>;
+                                                regulator-max-microvolt = <2700000>;
+                                        };
+                                        ldo8 {
+                                                regulator-name = "va-ap-rtc";
+                                                regulator-min-microvolt = <1100000>;
+                                                regulator-max-microvolt = <1100000>;
+                                                ti,enable-ldo8-tracking;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldo9 {
+                                                regulator-name = "vi-sdcard";
+                                                regulator-min-microvolt = <2900000>;
+                                                regulator-max-microvolt = <2900000>;
+                                        };
+                                        ldousb {
+                                                regulator-name = "avdd-usb";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                                regulator-always-on;
+                                                regulator-boot-on;
+                                        };
+                                        ldoln {
+                                                regulator-name = "va-hdmi";
+                                                regulator-min-microvolt = <3300000>;
+                                                regulator-max-microvolt = <3300000>;
+                                        };
+                                };
+                        };
+                        rtc {
+                                compatible = "ti,palmas-rtc";
+                                interrupt-parent = <&palmas>;
+                                interrupts = <8 0>;
+                        };
+                };
+        };
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+        };
+        /* eMMC */
+        sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+                vmmc-supply = <&vdd_1v8>;
+                non-removable;
+        };
+        usb@7d000000 {
+                status = "okay";
+        };
+        usb-phy@7d000000 {
+                status = "okay";
+                nvidia,xcvr-setup = <7>;
+                nvidia,xcvr-lsfslew = <2>;
+                nvidia,xcvr-lsrslew = <2>;
+                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+                /* Should be changed to "otg" once we have vbus_supply */
+                /* As of now, USB devices need to be powered externally */
+                dr_mode = "host";
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 1 40000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+                power-supply = <&lcd_bl_en>;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk32k_in: clock {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        gpio-key,wakeup;
+                };
+                volume_down {
+                        label = "Volume Down";
+                        gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEDOWN>;
+                };
+                volume_up {
+                        label = "Volume Up";
+                        gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_VOLUMEUP>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                /* FIXME: output of BQ24192 */
+                vs_sys: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "VS_SYS";
+                        regulator-min-microvolt = <4200000>;
+                        regulator-max-microvolt = <4200000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+                lcd_bl_en: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "VDD_LCD_BL";
+                        regulator-min-microvolt = <16500000>;
+                        regulator-max-microvolt = <16500000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vs_sys>;
+                        regulator-boot-on;
+                };
+                vdd_lcd: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "VD_LCD_1V8";
+                        regulator-min-microvolt = <1800000>;
+                        regulator-max-microvolt = <1800000>;
+                        gpio = <&palmas_gpio 4 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_1v8>;
+                        regulator-boot-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
new file mode 100644
index 000000000000..e31fb61a81d3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -0,0 +1,1827 @@
+/dts-v1/;
+#include <dt-bindings/input/input.h>
+#include "tegra124.dtsi"
+/ {
+        model = "NVIDIA Tegra124 Jetson TK1";
+        compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
+        aliases {
+                rtc0 = "/i2c@0,7000d000/pmic@40";
+                rtc1 = "/rtc@0,7000e000";
+        };
+        memory {
+                reg = <0x0 0x80000000 0x0 0x80000000>;
+        };
+        host1x@0,50000000 {
+                hdmi@0,54280000 {
+                        status = "okay";
+                        hdmi-supply = <&vdd_5v0_hdmi>;
+                        pll-supply = <&vdd_hdmi_pll>;
+                        vdd-supply = <&vdd_3v3_hdmi>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
+        };
+        pinmux: pinmux@0,70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        clk_32k_out_pa0 {
+                                nvidia,pins = "clk_32k_out_pa0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_cts_n_pa1 {
+                                nvidia,pins = "uart3_cts_n_pa1";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_fs_pa2 {
+                                nvidia,pins = "dap2_fs_pa2";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_sclk_pa3 {
+                                nvidia,pins = "dap2_sclk_pa3";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_din_pa4 {
+                                nvidia,pins = "dap2_din_pa4";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap2_dout_pa5 {
+                                nvidia,pins = "dap2_dout_pa5";
+                                nvidia,function = "i2s1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_pa6 {
+                                nvidia,pins = "sdmmc3_clk_pa6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_cmd_pa7 {
+                                nvidia,pins = "sdmmc3_cmd_pa7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb0 {
+                                nvidia,pins = "pb0";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pb1 {
+                                nvidia,pins = "pb1";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins = "sdmmc3_dat3_pb4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat2_pb5 {
+                                nvidia,pins = "sdmmc3_dat2_pb5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat1_pb6 {
+                                nvidia,pins = "sdmmc3_dat1_pb6";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_dat0_pb7 {
+                                nvidia,pins = "sdmmc3_dat0_pb7";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart3_rts_n_pc0 {
+                                nvidia,pins = "uart3_rts_n_pc0";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_txd_pc2 {
+                                nvidia,pins = "uart2_txd_pc2";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart2_rxd_pc3 {
+                                nvidia,pins = "uart2_rxd_pc3";
+                                nvidia,function = "irda";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_scl_pc4 {
+                                nvidia,pins = "gen1_i2c_scl_pc4";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen1_i2c_sda_pc5 {
+                                nvidia,pins = "gen1_i2c_sda_pc5";
+                                nvidia,function = "i2c1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pc7 {
+                                nvidia,pins = "pc7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg0 {
+                                nvidia,pins = "pg0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg1 {
+                                nvidia,pins = "pg1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg2 {
+                                nvidia,pins = "pg2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg3 {
+                                nvidia,pins = "pg3";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pg4 {
+                                nvidia,pins = "pg4";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg5 {
+                                nvidia,pins = "pg5";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg6 {
+                                nvidia,pins = "pg6";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pg7 {
+                                nvidia,pins = "pg7";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph0 {
+                                nvidia,pins = "ph0";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph1 {
+                                nvidia,pins = "ph1";
+                                nvidia,function = "pwm1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph2 {
+                                nvidia,pins = "ph2";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph3 {
+                                nvidia,pins = "ph3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph4 {
+                                nvidia,pins = "ph4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph5 {
+                                nvidia,pins = "ph5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ph6 {
+                                nvidia,pins = "ph6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ph7 {
+                                nvidia,pins = "ph7";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi0 {
+                                nvidia,pins = "pi0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi1 {
+                                nvidia,pins = "pi1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi2 {
+                                nvidia,pins = "pi2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi3 {
+                                nvidia,pins = "pi3";
+                                nvidia,function = "spi4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi4 {
+                                nvidia,pins = "pi4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pi5 {
+                                nvidia,pins = "pi5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi6 {
+                                nvidia,pins = "pi6";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pi7 {
+                                nvidia,pins = "pi7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj0 {
+                                nvidia,pins = "pj0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pj2 {
+                                nvidia,pins = "pj2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_cts_n_pj5 {
+                                nvidia,pins = "uart2_cts_n_pj5";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        uart2_rts_n_pj6 {
+                                nvidia,pins = "uart2_rts_n_pj6";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pj7 {
+                                nvidia,pins = "pj7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk0 {
+                                nvidia,pins = "pk0";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk1 {
+                                nvidia,pins = "pk1";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk2 {
+                                nvidia,pins = "pk2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk3 {
+                                nvidia,pins = "pk3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pk4 {
+                                nvidia,pins = "pk4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_out_pk5 {
+                                nvidia,pins = "spdif_out_pk5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        spdif_in_pk6 {
+                                nvidia,pins = "spdif_in_pk6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pk7 {
+                                nvidia,pins = "pk7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_fs_pn0 {
+                                nvidia,pins = "dap1_fs_pn0";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_din_pn1 {
+                                nvidia,pins = "dap1_din_pn1";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap1_dout_pn2 {
+                                nvidia,pins = "dap1_dout_pn2";
+                                nvidia,function = "sata";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap1_sclk_pn3 {
+                                nvidia,pins = "dap1_sclk_pn3";
+                                nvidia,function = "i2s0";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en0_pn4 {
+                                nvidia,pins = "usb_vbus_en0_pn4";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en1_pn5 {
+                                nvidia,pins = "usb_vbus_en1_pn5";
+                                nvidia,function = "usb";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        hdmi_int_pn7 {
+                                nvidia,pins = "hdmi_int_pn7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data7_po0 {
+                                nvidia,pins = "ulpi_data7_po0";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data0_po1 {
+                                nvidia,pins = "ulpi_data0_po1";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data1_po2 {
+                                nvidia,pins = "ulpi_data1_po2";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data2_po3 {
+                                nvidia,pins = "ulpi_data2_po3";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data3_po4 {
+                                nvidia,pins = "ulpi_data3_po4";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data4_po5 {
+                                nvidia,pins = "ulpi_data4_po5";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_data5_po6 {
+                                nvidia,pins = "ulpi_data5_po6";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_data6_po7 {
+                                nvidia,pins = "ulpi_data6_po7";
+                                nvidia,function = "ulpi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap3_fs_pp0 {
+                                nvidia,pins = "dap3_fs_pp0";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_din_pp1 {
+                                nvidia,pins = "dap3_din_pp1";
+                                nvidia,function = "i2s2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_dout_pp2 {
+                                nvidia,pins = "dap3_dout_pp2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap3_sclk_pp3 {
+                                nvidia,pins = "dap3_sclk_pp3";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap4_fs_pp4 {
+                                nvidia,pins = "dap4_fs_pp4";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_din_pp5 {
+                                nvidia,pins = "dap4_din_pp5";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_dout_pp6 {
+                                nvidia,pins = "dap4_dout_pp6";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap4_sclk_pp7 {
+                                nvidia,pins = "dap4_sclk_pp7";
+                                nvidia,function = "i2s3";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col0_pq0 {
+                                nvidia,pins = "kb_col0_pq0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col1_pq1 {
+                                nvidia,pins = "kb_col1_pq1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col2_pq2 {
+                                nvidia,pins = "kb_col2_pq2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col3_pq3 {
+                                nvidia,pins = "kb_col3_pq3";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_col4_pq4 {
+                                nvidia,pins = "kb_col4_pq4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col5_pq5 {
+                                nvidia,pins = "kb_col5_pq5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col6_pq6 {
+                                nvidia,pins = "kb_col6_pq6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_col7_pq7 {
+                                nvidia,pins = "kb_col7_pq7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row0_pr0 {
+                                nvidia,pins = "kb_row0_pr0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row1_pr1 {
+                                nvidia,pins = "kb_row1_pr1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row2_pr2 {
+                                nvidia,pins = "kb_row2_pr2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row3_pr3 {
+                                nvidia,pins = "kb_row3_pr3";
+                                nvidia,function = "sys";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row4_pr4 {
+                                nvidia,pins = "kb_row4_pr4";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row5_pr5 {
+                                nvidia,pins = "kb_row5_pr5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row6_pr6 {
+                                nvidia,pins = "kb_row6_pr6";
+                                nvidia,function = "displaya_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row7_pr7 {
+                                nvidia,pins = "kb_row7_pr7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row9_ps1 {
+                                nvidia,pins = "kb_row9_ps1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins = "kb_row11_ps3";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row12_ps4 {
+                                nvidia,pins = "kb_row12_ps4";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row13_ps5 {
+                                nvidia,pins = "kb_row13_ps5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row14_ps6 {
+                                nvidia,pins = "kb_row14_ps6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row15_ps7 {
+                                nvidia,pins = "kb_row15_ps7";
+                                nvidia,function = "soc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        kb_row16_pt0 {
+                                nvidia,pins = "kb_row16_pt0";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row17_pt1 {
+                                nvidia,pins = "kb_row17_pt1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gen2_i2c_scl_pt5 {
+                                nvidia,pins = "gen2_i2c_scl_pt5";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        gen2_i2c_sda_pt6 {
+                                nvidia,pins = "gen2_i2c_sda_pt6";
+                                nvidia,function = "i2c2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_cmd_pt7 {
+                                nvidia,pins = "sdmmc4_cmd_pt7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu0 {
+                                nvidia,pins = "pu0";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu1 {
+                                nvidia,pins = "pu1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu2 {
+                                nvidia,pins = "pu2";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu3 {
+                                nvidia,pins = "pu3";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu4 {
+                                nvidia,pins = "pu4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pu5 {
+                                nvidia,pins = "pu5";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pu6 {
+                                nvidia,pins = "pu6";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv0 {
+                                nvidia,pins = "pv0";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pv1 {
+                                nvidia,pins = "pv1";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_cd_n_pv2 {
+                                nvidia,pins = "sdmmc3_cd_n_pv2";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_wp_n_pv3 {
+                                nvidia,pins = "sdmmc1_wp_n_pv3";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_scl_pv4 {
+                                nvidia,pins = "ddc_scl_pv4";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        ddc_sda_pv5 {
+                                nvidia,pins = "ddc_sda_pv5";
+                                nvidia,function = "i2c4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_w2_aud_pw2 {
+                                nvidia,pins = "gpio_w2_aud_pw2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_w3_aud_pw3 {
+                                nvidia,pins = "gpio_w3_aud_pw3";
+                                nvidia,function = "spi6";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dap_mclk1_pw4 {
+                                nvidia,pins = "dap_mclk1_pw4";
+                                nvidia,function = "extperiph1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk2_out_pw5 {
+                                nvidia,pins = "clk2_out_pw5";
+                                nvidia,function = "extperiph2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_txd_pw6 {
+                                nvidia,pins = "uart3_txd_pw6";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        uart3_rxd_pw7 {
+                                nvidia,pins = "uart3_rxd_pw7";
+                                nvidia,function = "uartc";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dvfs_pwm_px0 {
+                                nvidia,pins = "dvfs_pwm_px0";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x1_aud_px1 {
+                                nvidia,pins = "gpio_x1_aud_px1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dvfs_clk_px2 {
+                                nvidia,pins = "dvfs_clk_px2";
+                                nvidia,function = "cldvfs";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x3_aud_px3 {
+                                nvidia,pins = "gpio_x3_aud_px3";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x4_aud_px4 {
+                                nvidia,pins = "gpio_x4_aud_px4";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        gpio_x5_aud_px5 {
+                                nvidia,pins = "gpio_x5_aud_px5";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x6_aud_px6 {
+                                nvidia,pins = "gpio_x6_aud_px6";
+                                nvidia,function = "gmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        gpio_x7_aud_px7 {
+                                nvidia,pins = "gpio_x7_aud_px7";
+                                nvidia,function = "rsvd1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_clk_py0 {
+                                nvidia,pins = "ulpi_clk_py0";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_dir_py1 {
+                                nvidia,pins = "ulpi_dir_py1";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        ulpi_nxt_py2 {
+                                nvidia,pins = "ulpi_nxt_py2";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        ulpi_stp_py3 {
+                                nvidia,pins = "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc1_dat3_py4 {
+                                nvidia,pins = "sdmmc1_dat3_py4";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat2_py5 {
+                                nvidia,pins = "sdmmc1_dat2_py5";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat1_py6 {
+                                nvidia,pins = "sdmmc1_dat1_py6";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_dat0_py7 {
+                                nvidia,pins = "sdmmc1_dat0_py7";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_clk_pz0 {
+                                nvidia,pins = "sdmmc1_clk_pz0";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc1_cmd_pz1 {
+                                nvidia,pins = "sdmmc1_cmd_pz1";
+                                nvidia,function = "sdmmc1";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_scl_pz6 {
+                                nvidia,pins = "pwr_i2c_scl_pz6";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pwr_i2c_sda_pz7 {
+                                nvidia,pins = "pwr_i2c_sda_pz7";
+                                nvidia,function = "i2cpwr";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins = "sdmmc4_dat0_paa0";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat1_paa1 {
+                                nvidia,pins = "sdmmc4_dat1_paa1";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat2_paa2 {
+                                nvidia,pins = "sdmmc4_dat2_paa2";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat3_paa3 {
+                                nvidia,pins = "sdmmc4_dat3_paa3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat4_paa4 {
+                                nvidia,pins = "sdmmc4_dat4_paa4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat5_paa5 {
+                                nvidia,pins = "sdmmc4_dat5_paa5";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat6_paa6 {
+                                nvidia,pins = "sdmmc4_dat6_paa6";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_dat7_paa7 {
+                                nvidia,pins = "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb0 {
+                                nvidia,pins = "pbb0";
+                                nvidia,function = "vimclk2_alt";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_i2c_scl_pbb1 {
+                                nvidia,pins = "cam_i2c_scl_pbb1";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        cam_i2c_sda_pbb2 {
+                                nvidia,pins = "cam_i2c_sda_pbb2";
+                                nvidia,function = "i2c3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        pbb3 {
+                                nvidia,pins = "pbb3";
+                                nvidia,function = "vgp3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb4 {
+                                nvidia,pins = "pbb4";
+                                nvidia,function = "vgp4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb5 {
+                                nvidia,pins = "pbb5";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb6 {
+                                nvidia,pins = "pbb6";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pbb7 {
+                                nvidia,pins = "pbb7";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cam_mclk_pcc0 {
+                                nvidia,pins = "cam_mclk_pcc0";
+                                nvidia,function = "vi_alt3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pcc1 {
+                                nvidia,pins = "pcc1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        pcc2 {
+                                nvidia,pins = "pcc2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins = "sdmmc4_clk_pcc4";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        clk2_req_pcc5 {
+                                nvidia,pins = "clk2_req_pcc5";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_out_pee0 {
+                                nvidia,pins = "clk3_out_pee0";
+                                nvidia,function = "extperiph3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk3_req_pee1 {
+                                nvidia,pins = "clk3_req_pee1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        dap_mclk1_req_pee2 {
+                                nvidia,pins = "dap_mclk1_req_pee2";
+                                nvidia,function = "sata";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        hdmi_cec_pee3 {
+                                nvidia,pins = "hdmi_cec_pee3";
+                                nvidia,function = "cec";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_out_pee4 {
+                                nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        sdmmc3_clk_lb_in_pee5 {
+                                nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+                                nvidia,function = "sdmmc3";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        dp_hpd_pff0 {
+                                nvidia,pins = "dp_hpd_pff0";
+                                nvidia,function = "dp";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        usb_vbus_en2_pff1 {
+                                nvidia,pins = "usb_vbus_en2_pff1";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        pff2 {
+                                nvidia,pins = "pff2";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+                        };
+                        core_pwr_req {
+                                nvidia,pins = "core_pwr_req";
+                                nvidia,function = "pwron";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        cpu_pwr_req {
+                                nvidia,pins = "cpu_pwr_req";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        pwr_int_n {
+                                nvidia,pins = "pwr_int_n";
+                                nvidia,function = "pmi";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        reset_out_n {
+                                nvidia,pins = "reset_out_n";
+                                nvidia,function = "reset_out_n";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                        owr {
+                                nvidia,pins = "owr";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+                        };
+                        clk_32k_in {
+                                nvidia,pins = "clk_32k_in";
+                                nvidia,function = "rsvd2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        jtag_rtck {
+                                nvidia,pins = "jtag_rtck";
+                                nvidia,function = "rtck";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+        /* DB9 serial port */
+        serial@0,70006300 {
+                status = "okay";
+        };
+        /* Expansion GEN1_I2C_*, mini-PCIe I2C, on-board components */
+        i2c@0,7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                rt5639: audio-codec@1c {
+                        compatible = "realtek,rt5639";
+                        reg = <0x1c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>;
+                        realtek,ldo1-en-gpios =
+                                <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_HIGH>;
+                };
+                temperature-sensor@4c {
+                        compatible = "ti,tmp451";
+                        reg = <0x4c>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
+                };
+                eeprom@56 {
+                        compatible = "atmel,24c02";
+                        reg = <0x56>;
+                        pagesize = <8>;
+                };
+        };
+        /* Expansion GEN2_I2C_* */
+        i2c@0,7000c400 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        /* Expansion CAM_I2C_* */
+        i2c@0,7000c500 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        /* HDMI DDC */
+        hdmi_ddc: i2c@0,7000c700 {
+                status = "okay";
+                clock-frequency = <100000>;
+        };
+        /* Expansion PWR_I2C_*, on-board components */
+        i2c@0,7000d000 {
+                status = "okay";
+                clock-frequency = <400000>;
+                pmic: pmic@40 {
+                        compatible = "ams,as3722";
+                        reg = <0x40>;
+                        interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+                        ams,system-power-controller;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&as3722_default>;
+                        as3722_default: pinmux {
+                                gpio0 {
+                                        pins = "gpio0";
+                                        function = "gpio";
+                                        bias-pull-down;
+                                };
+                                gpio1_2_4_7 {
+                                        pins = "gpio1", "gpio2", "gpio4", "gpio7";
+                                        function = "gpio";
+                                        bias-pull-up;
+                                };
+                                gpio3_5_6 {
+                                        pins = "gpio3", "gpio5", "gpio6";
+                                        bias-high-impedance;
+                                };
+                        };
+                        regulators {
+                                vsup-sd2-supply = <&vdd_5v0_sys>;
+                                vsup-sd3-supply = <&vdd_5v0_sys>;
+                                vsup-sd4-supply = <&vdd_5v0_sys>;
+                                vsup-sd5-supply = <&vdd_5v0_sys>;
+                                vin-ldo0-supply = <&vdd_1v35_lp0>;
+                                vin-ldo1-6-supply = <&vdd_3v3_run>;
+                                vin-ldo2-5-7-supply = <&vddio_1v8>;
+                                vin-ldo3-4-supply = <&vdd_3v3_sys>;
+                                vin-ldo9-10-supply = <&vdd_5v0_sys>;
+                                vin-ldo11-supply = <&vdd_3v3_run>;
+                                sd0 {
+                                        regulator-name = "+VDD_CPU_AP";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1400000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <2>;
+                                };
+                                sd1 {
+                                        regulator-name = "+VDD_CORE";
+                                        regulator-min-microvolt = <700000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-min-microamp = <2500000>;
+                                        regulator-max-microamp = <2500000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                        ams,external-control = <1>;
+                                };
+                                vdd_1v35_lp0: sd2 {
+                                        regulator-name = "+1.35V_LP0(sd2)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                sd3 {
+                                        regulator-name = "+1.35V_LP0(sd3)";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                        regulator-boot-on;
+                                };
+                                vdd_1v05_run: sd4 {
+                                        regulator-name = "+1.05V_RUN";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                vddio_1v8: sd5 {
+                                        regulator-name = "+1.8V_VDDIO";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                                sd6 {
+                                        regulator-name = "+VDD_GPU_AP";
+                                        regulator-min-microvolt = <650000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-min-microamp = <3500000>;
+                                        regulator-max-microamp = <3500000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                                ldo0 {
+                                        regulator-name = "+1.05V_RUN_AVDD";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,external-control = <1>;
+                                };
+                                ldo1 {
+                                        regulator-name = "+1.8V_RUN_CAM";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                                ldo2 {
+                                        regulator-name = "+1.2V_GEN_AVDD";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                };
+                                ldo3 {
+                                        regulator-name = "+1.05V_LP0_VDD_RTC";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-boot-on;
+                                        regulator-always-on;
+                                        ams,enable-tracking;
+                                };
+                                ldo4 {
+                                        regulator-name = "+2.8V_RUN_CAM";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo5 {
+                                        regulator-name = "+1.2V_RUN_CAM_FRONT";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                };
+                                vddio_sdmmc3: ldo6 {
+                                        regulator-name = "+VDDIO_SDMMC3";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <3300000>;
+                                };
+                                ldo7 {
+                                        regulator-name = "+1.05V_RUN_CAM_REAR";
+                                        regulator-min-microvolt = <1050000>;
+                                        regulator-max-microvolt = <1050000>;
+                                };
+                                ldo9 {
+                                        regulator-name = "+3.3V_RUN_TOUCH";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo10 {
+                                        regulator-name = "+2.8V_RUN_CAM_AF";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                };
+                                ldo11 {
+                                        regulator-name = "+1.8V_RUN_VPP_FUSE";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                };
+                        };
+                };
+        };
+        /* Expansion TS_SPI_* */
+        spi@0,7000d400 {
+                status = "okay";
+        };
+        /* Internal SPI */
+        spi@0,7000da00 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                spi-flash@0 {
+                        compatible = "winbond,w25q32dw";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                };
+        };
+        pmc@0,7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <1>;
+                nvidia,cpu-pwr-good-time = <500>;
+                nvidia,cpu-pwr-off-time = <300>;
+                nvidia,core-pwr-good-time = <641 3845>;
+                nvidia,core-pwr-off-time = <61036>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+        };
+        /* SD card */
+        sdhci@0,700b0400 {
+                status = "okay";
+                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
+                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_HIGH>;
+                bus-width = <4>;
+                vqmmc-supply = <&vddio_sdmmc3>;
+        };
+        /* eMMC */
+        sdhci@0,700b0600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+        ahub@0,70300000 {
+                i2s@0,70301100 {
+                        status = "okay";
+                };
+        };
+        /* mini-PCIe USB */
+        usb@0,7d004000 {
+                status = "okay";
+        };
+        usb-phy@0,7d004000 {
+                status = "okay";
+        };
+        /* USB A connector */
+        usb@0,7d008000 {
+                status = "okay";
+        };
+        usb-phy@0,7d008000 {
+                status = "okay";
+                vbus-supply = <&vdd_usb3_vbus>;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk32k_in: clock@0 {
+                        compatible = "fixed-clock";
+                        reg = <0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                vdd_mux: regulator@0 {
+                        compatible = "regulator-fixed";
+                        reg = <0>;
+                        regulator-name = "+VDD_MUX";
+                        regulator-min-microvolt = <12000000>;
+                        regulator-max-microvolt = <12000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                };
+                vdd_5v0_sys: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "+5V_SYS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+                vdd_3v3_sys: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "+3.3V_SYS";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&vdd_mux>;
+                };
+                vdd_3v3_run: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "+3.3V_RUN";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+                vdd_3v3_hdmi: regulator@4 {
+                        compatible = "regulator-fixed";
+                        reg = <4>;
+                        regulator-name = "+3.3V_AVDD_HDMI_AP_GATED";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        vin-supply = <&vdd_3v3_run>;
+                };
+                vdd_usb1_vbus: regulator@7 {
+                        compatible = "regulator-fixed";
+                        reg = <7>;
+                        regulator-name = "+USB0_VBUS_SW";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_usb3_vbus: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "+5V_USB_HS";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        gpio-open-drain;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+                vdd_3v3_lp0: regulator@10 {
+                        compatible = "regulator-fixed";
+                        reg = <10>;
+                        regulator-name = "+3.3V_LP0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_3v3_sys>;
+                };
+                vdd_hdmi_pll: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_1v05_run>;
+                };
+                vdd_5v0_hdmi: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "+5V_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
+        };
+        sound {
+                compatible = "nvidia,tegra-audio-rt5640-jetson-tk1",
+                             "nvidia,tegra-audio-rt5640";
+                nvidia,model = "NVIDIA Tegra Jetson TK1";
+                nvidia,audio-routing =
+                        "Headphones", "HPOR",
+                        "Headphones", "HPOL",
+                        "Mic Jack", "MICBIAS1",
+                        "IN2P", "Mic Jack";
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&rt5639>;
+                nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_LOW>;
+                clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
+                         <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
+                         <&tegra_car TEGRA124_CLK_EXTERN1>;
+                clock-names = "pll_a", "pll_a_out0", "mclk";
+        };
+};
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index c17283c04598..f0bb84244025 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -17,6 +17,18 @@
        };
        host1x@0,50000000 {
+                hdmi@0,54280000 {
+                        status = "okay";
+                        vdd-supply = <&vdd_3v3_hdmi>;
+                        pll-supply = <&vdd_hdmi_pll>;
+                        hdmi-supply = <&vdd_5v0_hdmi>;
+                        nvidia,ddc-i2c-bus = <&hdmi_ddc>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                };
                sor@0,54540000 {
                        status = "okay";
@@ -601,7 +613,7 @@
                clock-frequency = <100000>;
        };
-        i2c@0,7000c700 {
+        hdmi_ddc: i2c@0,7000c700 {
                status = "okay";
                clock-frequency = <100000>;
        };
@@ -700,7 +712,7 @@
                                        regulator-boot-on;
                                };
-                                sd4 {
+                                vdd_1v05_run: sd4 {
                                        regulator-name = "+1.05V_RUN";
                                        regulator-min-microvolt = <1050000>;
                                        regulator-max-microvolt = <1050000>;
@@ -931,9 +943,10 @@
        sdhci@0,700b0400 {
                cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
                power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
+                wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
                status = "okay";
                bus-width = <4>;
-                vmmc-supply = <&vddio_sdmmc3>;
+                vqmmc-supply = <&vddio_sdmmc3>;
        };
        sdhci@0,700b0600 {
@@ -1060,6 +1073,8 @@
                        regulator-name = "+3.3V_RUN";
                        regulator-min-microvolt = <3300000>;
                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                        regulator-boot-on;
                        gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                        vin-supply = <&vdd_3v3_sys>;
@@ -1145,6 +1160,27 @@
                        enable-active-high;
                        vin-supply = <&vdd_3v3_sys>;
                };
+                vdd_hdmi_pll: regulator@11 {
+                        compatible = "regulator-fixed";
+                        reg = <11>;
+                        regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL";
+                        regulator-min-microvolt = <1050000>;
+                        regulator-max-microvolt = <1050000>;
+                        gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&vdd_1v05_run>;
+                };
+                vdd_5v0_hdmi: regulator@12 {
+                        compatible = "regulator-fixed";
+                        reg = <12>;
+                        regulator-name = "+5V_HDMI_CON";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_sys>;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index 6d540a025148..6e6bc4e8185c 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -51,6 +51,18 @@
                        nvidia,head = <1>;
                };
+                hdmi@0,54280000 {
+                        compatible = "nvidia,tegra124-hdmi";
+                        reg = <0x0 0x54280000 0x0 0x00040000>;
+                        interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+                        clocks = <&tegra_car TEGRA124_CLK_HDMI>,
+                                 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>;
+                        clock-names = "hdmi", "parent";
+                        resets = <&tegra_car 51>;
+                        reset-names = "hdmi";
+                        status = "disabled";
+                };
                sor@0,54540000 {
                        compatible = "nvidia,tegra124-sor";
                        reg = <0x0 0x54540000 0x0 0x00040000>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 3fb1f50f6d46..f45aad688d9b 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -28,6 +28,7 @@
                hdmi@54280000 {
                        status = "okay";
+                        hdmi-supply = <&vdd_5v0_hdmi>;
                        vdd-supply = <&hdmi_vdd_reg>;
                        pll-supply = <&hdmi_pll_reg>;
@@ -724,6 +725,17 @@
                        gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
                        enable-active-high;
                };
+                vdd_5v0_hdmi: regulator@6 {
+                        compatible = "regulator-fixed";
+                        reg = <6>;
+                        regulator-name = "VDDIO_HDMI";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(T, 2) GPIO_ACTIVE_HIGH>;
+                        enable-active-high;
+                        vin-supply = <&vdd_5v0_reg>;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index e93fe45b7803..3189791a9289 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -40,6 +40,7 @@
                hdmi@54280000 {
                        status = "okay";
+                        hdmi-supply = <&vdd_5v0_hdmi>;
                        vdd-supply = <&sys_3v3_reg>;
                        pll-supply = <&vio_reg>;
@@ -478,6 +479,17 @@
                        gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
                        vin-supply = <&sys_3v3_reg>;
                };
+                vdd_5v0_hdmi: regulator@8 {
+                        compatible = "regulator-fixed";
+                        reg = <8>;
+                        regulator-name = "+VDD_5V_HDMI";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                        regulator-boot-on;
+                        vin-supply = <&sys_3v3_reg>;
+                };
        };
        sound {
diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
new file mode 100644
index 000000000000..7793abd5bef1
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
@@ -0,0 +1,205 @@
+/dts-v1/;
+#include "tegra30-colibri.dtsi"
+/ {
+        model = "Toradex Colibri T30 on Colibri Evaluation Board";
+        compatible = "toradex,colibri_t30-eval-v3", "toradex,colibri_t30", "nvidia,tegra30";
+        aliases {
+                rtc0 = "/i2c@7000c000/rtc@68";
+                rtc1 = "/i2c@7000d000/tps65911@2d";
+                rtc2 = "/rtc@7000e000";
+        };
+        host1x@50000000 {
+                dc@54200000 {
+                        rgb {
+                                status = "okay";
+                                nvidia,panel = <&panel>;
+                        };
+                };
+                hdmi@54280000 {
+                        status = "okay";
+                };
+        };
+        serial@70006000 {
+                status = "okay";
+        };
+        serial@70006040 {
+                compatible = "nvidia,tegra30-hsuart";
+                status = "okay";
+        };
+        serial@70006300 {
+                compatible = "nvidia,tegra30-hsuart";
+                status = "okay";
+        };
+        pwm@7000a000 {
+                status = "okay";
+        };
+        /*
+         * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
+         * board)
+         */
+        i2c@7000c000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                /* M41T0M6 real time clock on carrier board */
+                rtc@68 {
+                        compatible = "stm,m41t00";
+                        reg = <0x68>;
+                };
+        };
+        /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */
+        hdmiddc: i2c@7000c700 {
+                status = "okay";
+        };
+        /* SPI1: Colibri SSP */
+        spi@7000d400 {
+                status = "okay";
+                spi-max-frequency = <25000000>;
+                can0: can@0 {
+                        compatible = "microchip,mcp2515";
+                        reg = <0>;
+                        clocks = <&clk16m>;
+                        interrupt-parent = <&gpio>;
+                        interrupts = <TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
+                        spi-max-frequency = <10000000>;
+                };
+                spidev0: spi@1 {
+                        compatible = "spidev";
+                        reg = <1>;
+                        spi-max-frequency = <25000000>;
+                };
+        };
+        sdhci@78000200 {
+                status = "okay";
+                bus-width = <4>;
+                cd-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_LOW>;
+                no-1-8-v;
+        };
+        /* EHCI instance 0: USB1_DP/N -> USBC_P/N */
+        usb@7d000000 {
+                status = "okay";
+        };
+        usb-phy@7d000000 {
+                status = "okay";
+                dr_mode = "otg";
+                vbus-supply = <&usbc_vbus_reg>;
+        };
+        /* EHCI instance 2: USB3_DP/N -> USBH_P/N */
+        usb@7d008000 {
+                status = "okay";
+        };
+        usb-phy@7d008000 {
+                status = "okay";
+                vbus-supply = <&usbh_vbus_reg>;
+        };
+        backlight: backlight {
+                compatible = "pwm-backlight";
+                /* PWM<A> */
+                pwms = <&pwm 0 5000000>;
+                brightness-levels = <255 128 64 32 16 8 4 0>;
+                default-brightness-level = <6>;
+                /* BL_ON */
+                enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+        };
+        clocks {
+                clk16m: clk@1 {
+                        compatible = "fixed-clock";
+                        reg=<1>;
+                        #clock-cells = <0>;
+                        clock-frequency = <16000000>;
+                        clock-output-names = "clk16m";
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                power {
+                        label = "Power";
+                        gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+                        linux,code = <KEY_POWER>;
+                        debounce-interval = <10>;
+                        gpio-key,wakeup;
+                };
+        };
+        panel: panel {
+                /*
+                 * edt,et057090dhu: EDT 5.7" LCD TFT
+                 * edt,et070080dh6: EDT 7.0" LCD TFT
+                 */
+                compatible = "edt,et057090dhu", "simple-panel";
+                backlight = <&backlight>;
+        };
+        pwmleds {
+                compatible = "pwm-leds";
+                pwmb {
+                        label = "PWM<B>";
+                        pwms = <&pwm 1 19600>;
+                        max-brightness = <255>;
+                };
+                pwmc {
+                        label = "PWM<C>";
+                        pwms = <&pwm 2 19600>;
+                        max-brightness = <255>;
+                };
+                pwmd {
+                        label = "PWM<D>";
+                        pwms = <&pwm 3 19600>;
+                        max-brightness = <255>;
+                };
+        };
+        regulators {
+                sys_5v0_reg: regulator@1 {
+                        compatible = "regulator-fixed";
+                        reg = <1>;
+                        regulator-name = "5v0";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        regulator-always-on;
+                };
+                usbc_vbus_reg: regulator@2 {
+                        compatible = "regulator-fixed";
+                        reg = <2>;
+                        regulator-name = "usbc_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        vin-supply = <&sys_5v0_reg>;
+                };
+                /* USBH_PEN */
+                usbh_vbus_reg: regulator@3 {
+                        compatible = "regulator-fixed";
+                        reg = <3>;
+                        regulator-name = "usbh_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
+                        vin-supply = <&sys_5v0_reg>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi
new file mode 100644
index 000000000000..bf16f8e65627
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-colibri.dtsi
@@ -0,0 +1,377 @@
+#include <dt-bindings/input/input.h>
+#include "tegra30.dtsi"
+/*
+ * Toradex Colibri T30 Device Tree
+ * Compatible for Revisions 1.1B/1.1C/1.1D
+ */
+/ {
+        model = "Toradex Colibri T30";
+        compatible = "toradex,colibri_t30", "nvidia,tegra30";
+        memory {
+                reg = <0x80000000 0x40000000>;
+        };
+        host1x@50000000 {
+                hdmi@54280000 {
+                        vdd-supply = <&sys_3v3_reg>;
+                        pll-supply = <&vio_reg>;
+                        nvidia,hpd-gpio =
+                                <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
+                        nvidia,ddc-i2c-bus = <&hdmiddc>;
+                };
+        };
+        pinmux@70000868 {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+                state_default: pinmux {
+                        /* Colibri BL_ON */
+                        pv2 {
+                                nvidia,pins = "pv2";
+                                nvidia,function = "rsvd4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Colibri Backlight PWM<A> */
+                        sdmmc3_dat3_pb4 {
+                                nvidia,pins =   "sdmmc3_dat3_pb4";
+                                nvidia,function = "pwm0";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Colibri CAN_INT */
+                        kb_row8_ps0 {
+                                nvidia,pins = "kb_row8_ps0";
+                                nvidia,function = "kbc";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /*
+                         * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
+                         * todays display need DE, disable LCD_M1
+                         */
+                        lcd_m1_pw1 {
+                                nvidia,pins = "lcd_m1_pw1";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Thermal alert, need to be disabled */
+                        lcd_dc1_pd2 {
+                                nvidia,pins = "lcd_dc1_pd2";
+                                nvidia,function = "rsvd3";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Colibri MMC */
+                        kb_row10_ps2 {
+                                nvidia,pins = "kb_row10_ps2";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        kb_row11_ps3 {
+                                nvidia,pins =   "kb_row11_ps3",
+                                                "kb_row12_ps4",
+                                                "kb_row13_ps5",
+                                                "kb_row14_ps6",
+                                                "kb_row15_ps7";
+                                nvidia,function = "sdmmc2";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Colibri SSP */
+                        ulpi_clk_py0 {
+                                nvidia,pins =   "ulpi_clk_py0",
+                                                "ulpi_dir_py1",
+                                                "ulpi_nxt_py2",
+                                                "ulpi_stp_py3";
+                                nvidia,function = "spi1";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc3_dat6_pd3 {
+                                nvidia,pins =   "sdmmc3_dat6_pd3",
+                                                "sdmmc3_dat7_pd4";
+                                nvidia,function = "spdif";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                        };
+                        /* Colibri UART_A */
+                        ulpi_data0 {
+                                nvidia,pins =   "ulpi_data0_po1",
+                                                "ulpi_data1_po2",
+                                                "ulpi_data2_po3",
+                                                "ulpi_data3_po4",
+                                                "ulpi_data4_po5",
+                                                "ulpi_data5_po6",
+                                                "ulpi_data6_po7",
+                                                "ulpi_data7_po0";
+                                nvidia,function = "uarta";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Colibri UART_B */
+                        gmi_a16_pj7 {
+                                nvidia,pins =   "gmi_a16_pj7",
+                                                "gmi_a17_pb0",
+                                                "gmi_a18_pb1",
+                                                "gmi_a19_pk7";
+                                nvidia,function = "uartd";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* Colibri UART_C */
+                        uart2_rxd {
+                                nvidia,pins =   "uart2_rxd_pc3",
+                                                "uart2_txd_pc2";
+                                nvidia,function = "uartb";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        /* eMMC */
+                        sdmmc4_clk_pcc4 {
+                                nvidia,pins =   "sdmmc4_clk_pcc4",
+                                                "sdmmc4_rst_n_pcc3";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                        sdmmc4_dat0_paa0 {
+                                nvidia,pins =   "sdmmc4_dat0_paa0",
+                                                "sdmmc4_dat1_paa1",
+                                                "sdmmc4_dat2_paa2",
+                                                "sdmmc4_dat3_paa3",
+                                                "sdmmc4_dat4_paa4",
+                                                "sdmmc4_dat5_paa5",
+                                                "sdmmc4_dat6_paa6",
+                                                "sdmmc4_dat7_paa7";
+                                nvidia,function = "sdmmc4";
+                                nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                        };
+                };
+        };
+        hdmiddc: i2c@7000c700 {
+                clock-frequency = <100000>;
+        };
+        /*
+         * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
+         * touch screen controller
+         */
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+                pmic: tps65911@2d {
+                        compatible = "ti,tps65911";
+                        reg = <0x2d>;
+                        interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                        #interrupt-cells = <2>;
+                        interrupt-controller;
+                        ti,system-power-controller;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        vcc1-supply = <&sys_3v3_reg>;
+                        vcc2-supply = <&sys_3v3_reg>;
+                        vcc3-supply = <&vio_reg>;
+                        vcc4-supply = <&sys_3v3_reg>;
+                        vcc5-supply = <&sys_3v3_reg>;
+                        vcc6-supply = <&vio_reg>;
+                        vcc7-supply = <&sys_5v0_reg>;
+                        vccio-supply = <&sys_3v3_reg>;
+                        regulators {
+                                /* SW1: +V1.35_VDDIO_DDR */
+                                vdd1_reg: vdd1 {
+                                        regulator-name = "vddio_ddr_1v35";
+                                        regulator-min-microvolt = <1350000>;
+                                        regulator-max-microvolt = <1350000>;
+                                        regulator-always-on;
+                                };
+                                /* SW2: unused */
+                                /* SW CTRL: +V1.0_VDD_CPU */
+                                vddctrl_reg: vddctrl {
+                                        regulator-name = "vdd_cpu,vdd_sys";
+                                        regulator-min-microvolt = <1150000>;
+                                        regulator-max-microvolt = <1150000>;
+                                        regulator-always-on;
+                                };
+                                /* SWIO: +V1.8 */
+                                vio_reg: vio {
+                                        regulator-name = "vdd_1v8_gen";
+                                        regulator-min-microvolt = <1800000>;
+                                        regulator-max-microvolt = <1800000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO1: unused */
+                                /*
+                                 * EN_+V3.3 switching via FET:
+                                 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
+                                 * see also v3_3 fixed supply
+                                 */
+                                ldo2_reg: ldo2 {
+                                        regulator-name = "en_3v3";
+                                        regulator-min-microvolt = <3300000>;
+                                        regulator-max-microvolt = <3300000>;
+                                        regulator-always-on;
+                                };
+                                /* LDO3: unused */
+                                /* +V1.2_VDD_RTC */
+                                ldo4_reg: ldo4 {
+                                        regulator-name = "vdd_rtc";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                /*
+                                 * +V2.8_AVDD_VDAC:
+                                 * only required for analog RGB
+                                 */
+                                ldo5_reg: ldo5 {
+                                        regulator-name = "avdd_vdac";
+                                        regulator-min-microvolt = <2800000>;
+                                        regulator-max-microvolt = <2800000>;
+                                        regulator-always-on;
+                                };
+                                /*
+                                 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
+                                 * but LDO6 can't set voltage in 50mV
+                                 * granularity
+                                 */
+                                ldo6_reg: ldo6 {
+                                        regulator-name = "avdd_plle";
+                                        regulator-min-microvolt = <1100000>;
+                                        regulator-max-microvolt = <1100000>;
+                                };
+                                /* +V1.2_AVDD_PLL */
+                                ldo7_reg: ldo7 {
+                                        regulator-name = "avdd_pll";
+                                        regulator-min-microvolt = <1200000>;
+                                        regulator-max-microvolt = <1200000>;
+                                        regulator-always-on;
+                                };
+                                /* +V1.0_VDD_DDR_HS */
+                                ldo8_reg: ldo8 {
+                                        regulator-name = "vdd_ddr_hs";
+                                        regulator-min-microvolt = <1000000>;
+                                        regulator-max-microvolt = <1000000>;
+                                        regulator-always-on;
+                                };
+                        };
+                };
+                /*
+                 * LM95245 temperature sensor
+                 * Note: OVERT_N directly connected to PMIC PWRDN
+                 */
+                temp-sensor@4c {
+                        compatible = "national,lm95245";
+                        reg = <0x4c>;
+                };
+                /* SW: +V1.2_VDD_CORE */
+                tps62362@60 {
+                        compatible = "ti,tps62362";
+                        reg = <0x60>;
+                        regulator-name = "tps62362-vout";
+                        regulator-min-microvolt = <900000>;
+                        regulator-max-microvolt = <1400000>;
+                        regulator-boot-on;
+                        regulator-always-on;
+                        ti,vsel0-state-low;
+                        /* VSEL1: EN_CORE_DVFS_N low for DVFS */
+                        ti,vsel1-state-low;
+                };
+        };
+        pmc@7000e400 {
+                nvidia,invert-interrupt;
+                nvidia,suspend-mode = <1>;
+                nvidia,cpu-pwr-good-time = <5000>;
+                nvidia,cpu-pwr-off-time = <5000>;
+                nvidia,core-pwr-good-time = <3845 3845>;
+                nvidia,core-pwr-off-time = <0>;
+                nvidia,core-power-req-active-high;
+                nvidia,sys-clock-req-active-high;
+        };
+        emmc: sdhci@78000600 {
+                status = "okay";
+                bus-width = <8>;
+                non-removable;
+        };
+        /* EHCI instance 1: USB2_DP/N -> AX88772B */
+        usb@7d004000 {
+                status = "okay";
+        };
+        usb-phy@7d004000 {
+                status = "okay";
+                nvidia,is-wired = <1>;
+        };
+        clocks {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                clk32k_in: clk@0 {
+                        compatible = "fixed-clock";
+                        reg=<0>;
+                        #clock-cells = <0>;
+                        clock-frequency = <32768>;
+                };
+        };
+        regulators {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                sys_3v3_reg: regulator@100 {
+                        compatible = "regulator-fixed";
+                        reg = <100>;
+                        regulator-name = "3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/twl4030.dtsi b/arch/arm/boot/dts/twl4030.dtsi
index 86cfc7d15ca7..36ae9160b558 100644
--- a/arch/arm/boot/dts/twl4030.dtsi
+++ b/arch/arm/boot/dts/twl4030.dtsi
@@ -152,4 +152,10 @@
                keypad,num-rows = <8>;
                keypad,num-columns = <8>;
        };
+        twl_madc: madc {
+                compatible = "ti,twl4030-madc";
+                interrupts = <3>;
+                #io-channel-cells = <1>;
+        };
 };
diff --git a/arch/arm/boot/dts/twl4030_omap3.dtsi b/arch/arm/boot/dts/twl4030_omap3.dtsi
index c353ef0a6ac7..3537ae5b2146 100644
--- a/arch/arm/boot/dts/twl4030_omap3.dtsi
+++ b/arch/arm/boot/dts/twl4030_omap3.dtsi
@@ -8,7 +8,7 @@
 &twl {
        pinctrl-names = "default";
-        pinctrl-0 = <&twl4030_pins>;
+        pinctrl-0 = <&twl4030_pins &twl4030_vpins>;
 };
 &omap3_pmx_core {
@@ -23,3 +23,20 @@
                >;
        };
 };
+/*
+ * If your board is not using the I2C4 pins with twl4030, then don't include
+ * this file. For proper idle mode signaling with sys_clkreq and sys_off_mode
+ * pins we need to configure I2C4, or else use the legacy sys_nvmode1 and
+ * sys_nvmode2 signaling.
+ */
+&omap3_pmx_wkup {
+        twl4030_vpins: pinmux_twl4030_vpins {
+                pinctrl-single,pins = <
+                        OMAP3_WKUP_IOPAD(0x2a00, PIN_INPUT | MUX_MODE0)         /* i2c4_scl.i2c4_scl */
+                        OMAP3_WKUP_IOPAD(0x2a02, PIN_INPUT | MUX_MODE0)         /* i2c4_sda.i2c4_sda */
+                        OMAP3_WKUP_IOPAD(0x2a06, PIN_OUTPUT | MUX_MODE0)        /* sys_clkreq.sys_clkreq */
+                        OMAP3_WKUP_IOPAD(0x2a18, PIN_OUTPUT | MUX_MODE0)        /* sys_off_mode.sys_off_mode */
+                >;
+        };
+};
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index ac870fb3fa0d..756c986995a3 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -74,8 +74,24 @@
                        v2m_sysreg: sysreg@010000 {
                                compatible = "arm,vexpress-sysreg";
                                reg = <0x010000 0x1000>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
+                                v2m_led_gpios: sys_led@08 {
+                                        compatible = "arm,vexpress-sysreg,sys_led";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                                v2m_mmc_gpios: sys_mci@48 {
+                                        compatible = "arm,vexpress-sysreg,sys_mci";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                                v2m_flash_gpios: sys_flash@4c {
+                                        compatible = "arm,vexpress-sysreg,sys_flash";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
                        };
                        v2m_sysctl: sysctl@020000 {
@@ -113,8 +129,8 @@
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x050000 0x1000>;
                                interrupts = <9 10>;
-                                cd-gpios = <&v2m_sysreg 0 0>;
+                                cd-gpios = <&v2m_mmc_gpios 0 0>;
-                                wp-gpios = <&v2m_sysreg 1 0>;
+                                wp-gpios = <&v2m_mmc_gpios 1 0>;
                                max-frequency = <12000000>;
                                vmmc-supply = <&v2m_fixed_3v3>;
                                clocks = <&v2m_clk24mhz>, <&smbclk>;
@@ -265,6 +281,58 @@
                        clock-output-names = "v2m:refclk32khz";
                };
+                leds {
+                        compatible = "gpio-leds";
+                        user@1 {
+                                label = "v2m:green:user1";
+                                gpios = <&v2m_led_gpios 0 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        user@2 {
+                                label = "v2m:green:user2";
+                                gpios = <&v2m_led_gpios 1 0>;
+                                linux,default-trigger = "mmc0";
+                        };
+                        user@3 {
+                                label = "v2m:green:user3";
+                                gpios = <&v2m_led_gpios 2 0>;
+                                linux,default-trigger = "cpu0";
+                        };
+                        user@4 {
+                                label = "v2m:green:user4";
+                                gpios = <&v2m_led_gpios 3 0>;
+                                linux,default-trigger = "cpu1";
+                        };
+                        user@5 {
+                                label = "v2m:green:user5";
+                                gpios = <&v2m_led_gpios 4 0>;
+                                linux,default-trigger = "cpu2";
+                        };
+                        user@6 {
+                                label = "v2m:green:user6";
+                                gpios = <&v2m_led_gpios 5 0>;
+                                linux,default-trigger = "cpu3";
+                        };
+                        user@7 {
+                                label = "v2m:green:user7";
+                                gpios = <&v2m_led_gpios 6 0>;
+                                linux,default-trigger = "cpu4";
+                        };
+                        user@8 {
+                                label = "v2m:green:user8";
+                                gpios = <&v2m_led_gpios 7 0>;
+                                linux,default-trigger = "cpu5";
+                        };
+                };
                mcc {
                        compatible = "arm,vexpress,config-bus";
                        arm,vexpress,config-bridge = <&v2m_sysreg>;
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index f1420368355b..ba856d604fb7 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -73,8 +73,24 @@
                        v2m_sysreg: sysreg@00000 {
                                compatible = "arm,vexpress-sysreg";
                                reg = <0x00000 0x1000>;
-                                gpio-controller;
-                                #gpio-cells = <2>;
+                                v2m_led_gpios: sys_led@08 {
+                                        compatible = "arm,vexpress-sysreg,sys_led";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                                v2m_mmc_gpios: sys_mci@48 {
+                                        compatible = "arm,vexpress-sysreg,sys_mci";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
+                                v2m_flash_gpios: sys_flash@4c {
+                                        compatible = "arm,vexpress-sysreg,sys_flash";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                };
                        };
                        v2m_sysctl: sysctl@01000 {
@@ -112,8 +128,8 @@
                                compatible = "arm,pl180", "arm,primecell";
                                reg = <0x05000 0x1000>;
                                interrupts = <9 10>;
-                                cd-gpios = <&v2m_sysreg 0 0>;
+                                cd-gpios = <&v2m_mmc_gpios 0 0>;
-                                wp-gpios = <&v2m_sysreg 1 0>;
+                                wp-gpios = <&v2m_mmc_gpios 1 0>;
                                max-frequency = <12000000>;
                                vmmc-supply = <&v2m_fixed_3v3>;
                                clocks = <&v2m_clk24mhz>, <&smbclk>;
@@ -264,6 +280,58 @@
                        clock-output-names = "v2m:refclk32khz";
                };
+                leds {
+                        compatible = "gpio-leds";
+                        user@1 {
+                                label = "v2m:green:user1";
+                                gpios = <&v2m_led_gpios 0 0>;
+                                linux,default-trigger = "heartbeat";
+                        };
+                        user@2 {
+                                label = "v2m:green:user2";
+                                gpios = <&v2m_led_gpios 1 0>;
+                                linux,default-trigger = "mmc0";
+                        };
+                        user@3 {
+                                label = "v2m:green:user3";
+                                gpios = <&v2m_led_gpios 2 0>;
+                                linux,default-trigger = "cpu0";
+                        };
+                        user@4 {
+                                label = "v2m:green:user4";
+                                gpios = <&v2m_led_gpios 3 0>;
+                                linux,default-trigger = "cpu1";
+                        };
+                        user@5 {
+                                label = "v2m:green:user5";
+                                gpios = <&v2m_led_gpios 4 0>;
+                                linux,default-trigger = "cpu2";
+                        };
+                        user@6 {
+                                label = "v2m:green:user6";
+                                gpios = <&v2m_led_gpios 5 0>;
+                                linux,default-trigger = "cpu3";
+                        };
+                        user@7 {
+                                label = "v2m:green:user7";
+                                gpios = <&v2m_led_gpios 6 0>;
+                                linux,default-trigger = "cpu4";
+                        };
+                        user@8 {
+                                label = "v2m:green:user8";
+                                gpios = <&v2m_led_gpios 7 0>;
+                                linux,default-trigger = "cpu5";
+                        };
+                };
                mcc {
                        compatible = "arm,vexpress,config-bus";
                        arm,vexpress,config-bridge = <&v2m_sysreg>;
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 15f98cbcb75a..a25c262326dc 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -312,6 +312,7 @@
                        arm,vexpress-sysreg,func = <12 0>;
                        label = "A15 Pcore";
                };
                power@1 {
                        /* Total power for the three A7 cores */
                        compatible = "arm,vexpress-power";
@@ -322,14 +323,14 @@
                energy@0 {
                        /* Total energy for the two A15 cores */
                        compatible = "arm,vexpress-energy";
-                        arm,vexpress-sysreg,func = <13 0>;
+                        arm,vexpress-sysreg,func = <13 0>, <13 1>;
                        label = "A15 Jcore";
                };
                energy@2 {
                        /* Total energy for the three A7 cores */
                        compatible = "arm,vexpress-energy";
-                        arm,vexpress-sysreg,func = <13 2>;
+                        arm,vexpress-sysreg,func = <13 2>, <13 3>;
                        label = "A7 Jcore";
                };
        };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
index c544a5504591..d2709b73316b 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca5s.dts
@@ -88,6 +88,14 @@
                interrupts = <1 13 0x304>;
        };
+        timer@2c000200 {
+                compatible = "arm,cortex-a5-global-timer",
+                             "arm,cortex-a9-global-timer";
+                reg = <0x2c000200 0x20>;
+                interrupts = <1 11 0x304>;
+                clocks = <&oscclk0>;
+        };
        watchdog@2c000620 {
                compatible = "arm,cortex-a5-twd-wdt";
                reg = <0x2c000620 0x20>;
@@ -120,7 +128,7 @@
                compatible = "arm,vexpress,config-bus";
                arm,vexpress,config-bridge = <&v2m_sysreg>;
-                osc@0 {
+                oscclk0: osc@0 {
                        /* CPU and internal AXI reference clock */
                        compatible = "arm,vexpress-osc";
                        arm,vexpress-sysreg,func = <1 0>;
diff --git a/arch/arm/boot/dts/vf610-colibri.dts b/arch/arm/boot/dts/vf610-colibri.dts
new file mode 100644
index 000000000000..aecc7dbc65e8
--- /dev/null
+++ b/arch/arm/boot/dts/vf610-colibri.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright 2014 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+/dts-v1/;
+#include "vf610.dtsi"
+/ {
+        model = "Toradex Colibri VF61 COM";
+        compatible = "toradex,vf610-colibri", "fsl,vf610";
+        chosen {
+                bootargs = "console=ttyLP0,115200";
+        };
+        memory {
+                reg = <0x80000000 0x10000000>;
+        };
+        clocks {
+                enet_ext {
+                        compatible = "fixed-clock";
+                        #clock-cells = <0>;
+                        clock-frequency = <50000000>;
+                };
+        };
+};
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
+&fec1 {
+        phy-mode = "rmii";
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_fec1>;
+        status = "okay";
+};
+&L2 {
+        arm,data-latency = <2 1 2>;
+        arm,tag-latency = <3 2 3>;
+};
+&uart0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart0>;
+        status = "okay";
+};
+&uart1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart1>;
+        status = "okay";
+};
+&uart2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_uart2>;
+        status = "okay";
+};
+&iomuxc {
+        vf610-colibri {
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,fsl,pins = <
+                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                VF610_PAD_PTB20__GPIO_42        0x219d
+                        >;
+                };
+                pinctrl_fec1: fec1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTC9__ENET_RMII1_MDC          0x30d2
+                                VF610_PAD_PTC10__ENET_RMII1_MDIO        0x30d3
+                                VF610_PAD_PTC11__ENET_RMII1_CRS         0x30d1
+                                VF610_PAD_PTC12__ENET_RMII_RXD1         0x30d1
+                                VF610_PAD_PTC13__ENET_RMII1_RXD0        0x30d1
+                                VF610_PAD_PTC14__ENET_RMII1_RXER        0x30d1
+                                VF610_PAD_PTC15__ENET_RMII1_TXD1        0x30d2
+                                VF610_PAD_PTC16__ENET_RMII1_TXD0        0x30d2
+                                VF610_PAD_PTC17__ENET_RMII1_TXEN        0x30d2
+                        >;
+                };
+                pinctrl_uart0: uart0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB10__UART0_TX               0x21a2
+                                VF610_PAD_PTB11__UART0_RX               0x21a1
+                        >;
+                };
+                pinctrl_uart1: uart1grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB4__UART1_TX                0x21a2
+                                VF610_PAD_PTB5__UART1_RX                0x21a1
+                        >;
+                };
+                pinctrl_uart2: uart2grp {
+                        fsl,pins = <
+                                VF610_PAD_PTD0__UART2_TX                0x21a2
+                                VF610_PAD_PTD1__UART2_RX                0x21a1
+                                VF610_PAD_PTD2__UART2_RTS               0x21a2
+                                VF610_PAD_PTD3__UART2_CTS               0x21a1
+                        >;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index ded361075aab..11d733406c7e 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -113,6 +113,13 @@
        };
 };
+&esdhc1 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_esdhc1>;
+        bus-width = <4>;
+        status = "okay";
+};
 &fec0 {
        phy-mode = "rmii";
        pinctrl-names = "default";
@@ -160,6 +167,18 @@
                        >;
                };
+                pinctrl_esdhc1: esdhc1grp {
+                        fsl,fsl,pins = <
+                                VF610_PAD_PTA24__ESDHC1_CLK     0x31ef
+                                VF610_PAD_PTA25__ESDHC1_CMD     0x31ef
+                                VF610_PAD_PTA26__ESDHC1_DAT0    0x31ef
+                                VF610_PAD_PTA27__ESDHC1_DAT1    0x31ef
+                                VF610_PAD_PTA28__ESDHC1_DATA2   0x31ef
+                                VF610_PAD_PTA29__ESDHC1_DAT3    0x31ef
+                                VF610_PAD_PTA7__GPIO_134        0x219d
+                        >;
+                };
                pinctrl_fec0: fec0grp {
                        fsl,pins = <
                                VF610_PAD_PTA6__RMII_CLKIN              0x30d1
@@ -196,6 +215,17 @@
                        >;
                };
+                pinctrl_pwm0: pwm0grp {
+                        fsl,pins = <
+                                VF610_PAD_PTB0__FTM0_CH0                0x1582
+                                VF610_PAD_PTB1__FTM0_CH1                0x1582
+                                VF610_PAD_PTB2__FTM0_CH2                0x1582
+                                VF610_PAD_PTB3__FTM0_CH3                0x1582
+                                VF610_PAD_PTB6__FTM0_CH6                0x1582
+                                VF610_PAD_PTB7__FTM0_CH7                0x1582
+                        >;
+                };
                pinctrl_sai2: sai2grp {
                        fsl,pins = <
                                VF610_PAD_PTA16__SAI2_TX_BCLK           0x02ed
@@ -217,6 +247,12 @@
        };
 };
+&pwm0 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&pinctrl_pwm0>;
+        status = "okay";
+};
 &sai2 {
        #sound-dai-cells = <0>;
        pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index b8ce0aa7b157..6cc314e7b8fb 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -183,6 +183,19 @@
                                clock-names = "pit";
                        };
+                        pwm0: pwm@40038000 {
+                                compatible = "fsl,vf610-ftm-pwm";
+                                #pwm-cells = <3>;
+                                reg = <0x40038000 0x1000>;
+                                clock-names = "ftm_sys", "ftm_ext",
+                                              "ftm_fix", "ftm_cnt_clk_en";
+                                clocks = <&clks VF610_CLK_FTM0>,
+                                        <&clks VF610_CLK_FTM0_EXT_SEL>,
+                                        <&clks VF610_CLK_FTM0_FIX_SEL>,
+                                        <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
                        adc0: adc@4003b000 {
                                compatible = "fsl,vf610-adc";
                                reg = <0x4003b000 0x1000>;
@@ -347,6 +360,30 @@
                                status = "disabled";
                        };
+                        esdhc1: esdhc@400b2000 {
+                                compatible = "fsl,imx53-esdhc";
+                                reg = <0x400b2000 0x4000>;
+                                interrupts = <0 28 0x04>;
+                                clocks = <&clks VF610_CLK_IPG_BUS>,
+                                        <&clks VF610_CLK_PLATFORM_BUS>,
+                                        <&clks VF610_CLK_ESDHC1>;
+                                clock-names = "ipg", "ahb", "per";
+                                status = "disabled";
+                        };
+                        ftm: ftm@400b8000 {
+                                compatible = "fsl,ftm-timer";
+                                reg = <0x400b8000 0x1000 0x400b9000 0x1000>;
+                                interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
+                                clock-names = "ftm-evt", "ftm-src",
+                                        "ftm-evt-counter-en", "ftm-src-counter-en";
+                                clocks = <&clks VF610_CLK_FTM2>,
+                                        <&clks VF610_CLK_FTM3>,
+                                        <&clks VF610_CLK_FTM2_EXT_FIX_EN>,
+                                        <&clks VF610_CLK_FTM3_EXT_FIX_EN>;
+                                status = "disabled";
+                        };
                        fec0: ethernet@400d0000 {
                                compatible = "fsl,mvf600-fec";
                                reg = <0x400d0000 0x1000>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index c1176abc34d9..760bbc463c5b 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2011 Xilinx
+ *  Copyright (C) 2011 - 2014 Xilinx
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
@@ -25,6 +25,7 @@
                        reg = <0>;
                        clocks = <&clkc 3>;
                        clock-latency = <1000>;
+                        cpu0-supply = <&regulator_vccpint>;
                        operating-points = <
                                /* kHz    uV */
                                666667  1000000
@@ -48,6 +49,15 @@
                reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
        };
+        regulator_vccpint: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VCCPINT";
+                regulator-min-microvolt = <1000000>;
+                regulator-max-microvolt = <1000000>;
+                regulator-boot-on;
+                regulator-always-on;
+        };
        amba {
                compatible = "simple-bus";
                #address-cells = <1>;
@@ -55,7 +65,7 @@
                interrupt-parent = <&intc>;
                ranges;
-                i2c0: zynq-i2c@e0004000 {
+                i2c0: i2c@e0004000 {
                        compatible = "cdns,i2c-r1p10";
                        status = "disabled";
                        clocks = <&clkc 38>;
@@ -66,7 +76,7 @@
                        #size-cells = <0>;
                };
-                i2c1: zynq-i2c@e0005000 {
+                i2c1: i2c@e0005000 {
                        compatible = "cdns,i2c-r1p10";
                        status = "disabled";
                        clocks = <&clkc 39>;
@@ -80,7 +90,6 @@
                intc: interrupt-controller@f8f01000 {
                        compatible = "arm,cortex-a9-gic";
                        #interrupt-cells = <3>;
-                        #address-cells = <1>;
                        interrupt-controller;
                        reg = <0xF8F01000 0x1000>,
                              <0xF8F00100 0x100>;
@@ -95,7 +104,7 @@
                        cache-level = <2>;
                };
-                uart0: uart@e0000000 {
+                uart0: serial@e0000000 {
                        compatible = "xlnx,xuartps";
                        status = "disabled";
                        clocks = <&clkc 23>, <&clkc 40>;
@@ -104,7 +113,7 @@
                        interrupts = <0 27 4>;
                };
-                uart1: uart@e0001000 {
+                uart1: serial@e0001000 {
                        compatible = "xlnx,xuartps";
                        status = "disabled";
                        clocks = <&clkc 24>, <&clkc 41>;
@@ -131,7 +140,7 @@
                        clock-names = "pclk", "hclk", "tx_clk";
                };
-                sdhci0: ps7-sdhci@e0100000 {
+                sdhci0: sdhci@e0100000 {
                        compatible = "arasan,sdhci-8.9a";
                        status = "disabled";
                        clock-names = "clk_xin", "clk_ahb";
@@ -141,7 +150,7 @@
                        reg = <0xe0100000 0x1000>;
                } ;
-                sdhci1: ps7-sdhci@e0101000 {
+                sdhci1: sdhci@e0101000 {
                        compatible = "arasan,sdhci-8.9a";
                        status = "disabled";
                        clock-names = "clk_xin", "clk_ahb";
@@ -177,6 +186,11 @@
                        };
                };
+                devcfg: devcfg@f8007000 {
+                        compatible = "xlnx,zynq-devcfg-1.0";
+                        reg = <0xf8007000 0x100>;
+                } ;
                global_timer: timer@f8f00200 {
                        compatible = "arm,cortex-a9-global-timer";
                        reg = <0xf8f00200 0x20>;
@@ -185,26 +199,27 @@
                        clocks = <&clkc 4>;
                };
-                ttc0: ttc0@f8001000 {
+                ttc0: timer@f8001000 {
                        interrupt-parent = <&intc>;
-                        interrupts = < 0 10 4 0 11 4 0 12 4 >;
+                        interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8001000 0x1000>;
                };
-                ttc1: ttc1@f8002000 {
+                ttc1: timer@f8002000 {
                        interrupt-parent = <&intc>;
-                        interrupts = < 0 37 4 0 38 4 0 39 4 >;
+                        interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
                        compatible = "cdns,ttc";
                        clocks = <&clkc 6>;
                        reg = <0xF8002000 0x1000>;
                };
-                scutimer: scutimer@f8f00600 {
+                scutimer: timer@f8f00600 {
                        interrupt-parent = <&intc>;
-                        interrupts = < 1 13 0x301 >;
+                        interrupts = <1 13 0x301>;
                        compatible = "arm,cortex-a9-twd-timer";
-                        reg = < 0xf8f00600 0x20 >;
+                        reg = <0xf8f00600 0x20>;
                        clocks = <&clkc 4>;
                } ;
        };
diff --git a/arch/arm/common/bL_switcher.c b/arch/arm/common/bL_switcher.c
index f01c0ee0c87e..490f3dced749 100644
--- a/arch/arm/common/bL_switcher.c
+++ b/arch/arm/common/bL_switcher.c
@@ -433,8 +433,12 @@ static void bL_switcher_restore_cpus(void)
 {
        int i;
-        for_each_cpu(i, &bL_switcher_removed_logical_cpus)
+        for_each_cpu(i, &bL_switcher_removed_logical_cpus) {
-                cpu_up(i);
+                struct device *cpu_dev = get_cpu_device(i);
+                int ret = device_online(cpu_dev);
+                if (ret)
+                        dev_err(cpu_dev, "switcher: unable to restore CPU\n");
+        }
 }
 static int bL_switcher_halve_cpus(void)
@@ -521,7 +525,7 @@ static int bL_switcher_halve_cpus(void)
                        continue;
                }
-                ret = cpu_down(i);
+                ret = device_offline(get_cpu_device(i));
                if (ret) {
                        bL_switcher_restore_cpus();
                        return ret;
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 41bca32409fc..485be42519b9 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -102,7 +102,13 @@
 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
 #define EDMA_DCHMAP     0x0100  /* 64 registers */
-#define CHMAP_EXIST     BIT(24)
+/* CCCFG register */
+#define GET_NUM_DMACH(x)        (x & 0x7) /* bits 0-2 */
+#define GET_NUM_PAENTRY(x)      ((x & 0x7000) >> 12) /* bits 12-14 */
+#define GET_NUM_EVQUE(x)        ((x & 0x70000) >> 16) /* bits 16-18 */
+#define GET_NUM_REGN(x)         ((x & 0x300000) >> 20) /* bits 20-21 */
+#define CHMAP_EXIST             BIT(24)
 #define EDMA_MAX_DMACH           64
 #define EDMA_MAX_PARAMENTRY     512
@@ -233,7 +239,6 @@ struct edma {
        unsigned        num_region;
        unsigned        num_slots;
        unsigned        num_tc;
-        unsigned        num_cc;
        enum dma_event_q        default_queue;
        /* list of channels with no even trigger; terminated by "-1" */
@@ -290,12 +295,6 @@ static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
                        ~(0x7 << bit), queue_no << bit);
 }
-static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
-{
-        int bit = queue_no * 4;
-        edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
-}
 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
                int priority)
 {
@@ -994,29 +993,23 @@ void edma_set_dest(unsigned slot, dma_addr_t dest_port,
 EXPORT_SYMBOL(edma_set_dest);
 /**
- * edma_get_position - returns the current transfer points
+ * edma_get_position - returns the current transfer point
 * @slot: parameter RAM slot being examined
- * @src: pointer to source port position
+ * @dst:  true selects the dest position, false the source
- * @dst: pointer to destination port position
 *
- * Returns current source and destination addresses for a particular
+ * Returns the position of the current active slot
- * parameter RAM slot.  Its channel should not be active when this is called.
 */
-void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
+dma_addr_t edma_get_position(unsigned slot, bool dst)
 {
-        struct edmacc_param temp;
+        u32 offs, ctlr = EDMA_CTLR(slot);
-        unsigned ctlr;
-        ctlr = EDMA_CTLR(slot);
        slot = EDMA_CHAN_SLOT(slot);
-        edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
+        offs = PARM_OFFSET(slot);
-        if (src != NULL)
+        offs += dst ? PARM_DST : PARM_SRC;
-                *src = temp.src;
-        if (dst != NULL)
+        return edma_read(ctlr, offs);
-                *dst = temp.dst;
 }
-EXPORT_SYMBOL(edma_get_position);
 /**
 * edma_set_src_index - configure DMA source address indexing
@@ -1421,57 +1414,101 @@ void edma_clear_event(unsigned channel)
 }
 EXPORT_SYMBOL(edma_clear_event);
-#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
+static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
+                              struct edma *edma_cc)
-static int edma_of_read_u32_to_s16_array(const struct device_node *np,
-                                         const char *propname, s16 *out_values,
-                                         size_t sz)
 {
-        int ret;
+        int i;
+        u32 value, cccfg;
+        s8 (*queue_priority_map)[2];
-        ret = of_property_read_u16_array(np, propname, out_values, sz);
+        /* Decode the eDMA3 configuration from CCCFG register */
-        if (ret)
+        cccfg = edma_read(0, EDMA_CCCFG);
-                return ret;
+        value = GET_NUM_REGN(cccfg);
+        edma_cc->num_region = BIT(value);
+        value = GET_NUM_DMACH(cccfg);
+        edma_cc->num_channels = BIT(value + 1);
+        value = GET_NUM_PAENTRY(cccfg);
+        edma_cc->num_slots = BIT(value + 4);
-        /* Terminate it */
+        value = GET_NUM_EVQUE(cccfg);
-        *out_values++ = -1;
+        edma_cc->num_tc = value + 1;
-        *out_values++ = -1;
+        dev_dbg(dev, "eDMA3 HW configuration (cccfg: 0x%08x):\n", cccfg);
+        dev_dbg(dev, "num_region: %u\n", edma_cc->num_region);
+        dev_dbg(dev, "num_channel: %u\n", edma_cc->num_channels);
+        dev_dbg(dev, "num_slot: %u\n", edma_cc->num_slots);
+        dev_dbg(dev, "num_tc: %u\n", edma_cc->num_tc);
+        /* Nothing need to be done if queue priority is provided */
+        if (pdata->queue_priority_mapping)
+                return 0;
+        /*
+         * Configure TC/queue priority as follows:
+         * Q0 - priority 0
+         * Q1 - priority 1
+         * Q2 - priority 2
+         * ...
+         * The meaning of priority numbers: 0 highest priority, 7 lowest
+         * priority. So Q0 is the highest priority queue and the last queue has
+         * the lowest priority.
+         */
+        queue_priority_map = devm_kzalloc(dev,
+                                          (edma_cc->num_tc + 1) * sizeof(s8),
+                                          GFP_KERNEL);
+        if (!queue_priority_map)
+                return -ENOMEM;
+        for (i = 0; i < edma_cc->num_tc; i++) {
+                queue_priority_map[i][0] = i;
+                queue_priority_map[i][1] = i;
+        }
+        queue_priority_map[i][0] = -1;
+        queue_priority_map[i][1] = -1;
+        pdata->queue_priority_mapping = queue_priority_map;
+        pdata->default_queue = 0;
        return 0;
 }
-static int edma_xbar_event_map(struct device *dev,
+#if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES)
-                               struct device_node *node,
-                               struct edma_soc_info *pdata, int len)
+static int edma_xbar_event_map(struct device *dev, struct device_node *node,
+                               struct edma_soc_info *pdata, size_t sz)
 {
-        int ret, i;
+        const char pname[] = "ti,edma-xbar-event-map";
        struct resource res;
        void __iomem *xbar;
-        const s16 (*xbar_chans)[2];
+        s16 (*xbar_chans)[2];
+        size_t nelm = sz / sizeof(s16);
        u32 shift, offset, mux;
+        int ret, i;
-        xbar_chans = devm_kzalloc(dev,
+        xbar_chans = devm_kzalloc(dev, (nelm + 2) * sizeof(s16), GFP_KERNEL);
-                                  len/sizeof(s16) + 2*sizeof(s16),
-                                  GFP_KERNEL);
        if (!xbar_chans)
                return -ENOMEM;
        ret = of_address_to_resource(node, 1, &res);
        if (ret)
-                return -EIO;
+                return -ENOMEM;
        xbar = devm_ioremap(dev, res.start, resource_size(&res));
        if (!xbar)
                return -ENOMEM;
-        ret = edma_of_read_u32_to_s16_array(node,
+        ret = of_property_read_u16_array(node, pname, (u16 *)xbar_chans, nelm);
-                                            "ti,edma-xbar-event-map",
-                                            (s16 *)xbar_chans,
-                                            len/sizeof(u32));
        if (ret)
                return -EIO;
-        for (i = 0; xbar_chans[i][0] != -1; i++) {
+        /* Invalidate last entry for the other user of this mess */
+        nelm >>= 1;
+        xbar_chans[nelm][0] = xbar_chans[nelm][1] = -1;
+        for (i = 0; i < nelm; i++) {
                shift = (xbar_chans[i][1] & 0x03) << 3;
                offset = xbar_chans[i][1] & 0xfffffffc;
                mux = readl(xbar + offset);
@@ -1480,8 +1517,7 @@ static int edma_xbar_event_map(struct device *dev,
                writel(mux, (xbar + offset));
        }
-        pdata->xbar_chans = xbar_chans;
+        pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
        return 0;
 }
@@ -1489,65 +1525,16 @@ static int edma_of_parse_dt(struct device *dev,
                            struct device_node *node,
                            struct edma_soc_info *pdata)
 {
-        int ret = 0, i;
+        int ret = 0;
-        u32 value;
        struct property *prop;
        size_t sz;
        struct edma_rsv_info *rsv_info;
-        s8 (*queue_tc_map)[2], (*queue_priority_map)[2];
-        memset(pdata, 0, sizeof(struct edma_soc_info));
-        ret = of_property_read_u32(node, "dma-channels", &value);
-        if (ret < 0)
-                return ret;
-        pdata->n_channel = value;
-        ret = of_property_read_u32(node, "ti,edma-regions", &value);
-        if (ret < 0)
-                return ret;
-        pdata->n_region = value;
-        ret = of_property_read_u32(node, "ti,edma-slots", &value);
-        if (ret < 0)
-                return ret;
-        pdata->n_slot = value;
-        pdata->n_cc = 1;
        rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
        if (!rsv_info)
                return -ENOMEM;
        pdata->rsv = rsv_info;
-        queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
-        if (!queue_tc_map)
-                return -ENOMEM;
-        for (i = 0; i < 3; i++) {
-                queue_tc_map[i][0] = i;
-                queue_tc_map[i][1] = i;
-        }
-        queue_tc_map[i][0] = -1;
-        queue_tc_map[i][1] = -1;
-        pdata->queue_tc_mapping = queue_tc_map;
-        queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL);
-        if (!queue_priority_map)
-                return -ENOMEM;
-        for (i = 0; i < 3; i++) {
-                queue_priority_map[i][0] = i;
-                queue_priority_map[i][1] = i;
-        }
-        queue_priority_map[i][0] = -1;
-        queue_priority_map[i][1] = -1;
-        pdata->queue_priority_mapping = queue_priority_map;
-        pdata->default_queue = 0;
        prop = of_find_property(node, "ti,edma-xbar-event-map", &sz);
        if (prop)
                ret = edma_xbar_event_map(dev, node, pdata, sz);
@@ -1574,6 +1561,7 @@ static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev,
                return ERR_PTR(ret);
        dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap);
+        dma_cap_set(DMA_CYCLIC, edma_filter_info.dma_cap);
        of_dma_controller_register(dev->of_node, of_dma_simple_xlate,
                                   &edma_filter_info);
@@ -1592,7 +1580,6 @@ static int edma_probe(struct platform_device *pdev)
        struct edma_soc_info    **info = pdev->dev.platform_data;
        struct edma_soc_info    *ninfo[EDMA_MAX_CC] = {NULL};
        s8              (*queue_priority_mapping)[2];
-        s8              (*queue_tc_mapping)[2];
        int                     i, j, off, ln, found = 0;
        int                     status = -1;
        const s16               (*rsv_chans)[2];
@@ -1603,7 +1590,6 @@ static int edma_probe(struct platform_device *pdev)
        struct resource         *r[EDMA_MAX_CC] = {NULL};
        struct resource         res[EDMA_MAX_CC];
        char                    res_name[10];
-        char                    irq_name[10];
        struct device_node      *node = pdev->dev.of_node;
        struct device           *dev = &pdev->dev;
        int                     ret;
@@ -1668,12 +1654,10 @@ static int edma_probe(struct platform_device *pdev)
                if (!edma_cc[j])
                        return -ENOMEM;
-                edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel,
+                /* Get eDMA3 configuration from IP */
-                                                        EDMA_MAX_DMACH);
+                ret = edma_setup_from_hw(dev, info[j], edma_cc[j]);
-                edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot,
+                if (ret)
-                                                        EDMA_MAX_PARAMENTRY);
+                        return ret;
-                edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc,
-                                                        EDMA_MAX_CC);
                edma_cc[j]->default_queue = info[j]->default_queue;
@@ -1725,14 +1709,21 @@ static int edma_probe(struct platform_device *pdev)
                if (node) {
                        irq[j] = irq_of_parse_and_map(node, 0);
+                        err_irq[j] = irq_of_parse_and_map(node, 2);
                } else {
+                        char irq_name[10];
                        sprintf(irq_name, "edma%d", j);
                        irq[j] = platform_get_irq_byname(pdev, irq_name);
+                        sprintf(irq_name, "edma%d_err", j);
+                        err_irq[j] = platform_get_irq_byname(pdev, irq_name);
                }
                edma_cc[j]->irq_res_start = irq[j];
-                status = devm_request_irq(&pdev->dev, irq[j],
+                edma_cc[j]->irq_res_end = err_irq[j];
-                                          dma_irq_handler, 0, "edma",
-                                          &pdev->dev);
+                status = devm_request_irq(dev, irq[j], dma_irq_handler, 0,
+                                          "edma", dev);
                if (status < 0) {
                        dev_dbg(&pdev->dev,
                                "devm_request_irq %d failed --> %d\n",
@@ -1740,16 +1731,8 @@ static int edma_probe(struct platform_device *pdev)
                        return status;
                }
-                if (node) {
+                status = devm_request_irq(dev, err_irq[j], dma_ccerr_handler, 0,
-                        err_irq[j] = irq_of_parse_and_map(node, 2);
+                                          "edma_error", dev);
-                } else {
-                        sprintf(irq_name, "edma%d_err", j);
-                        err_irq[j] = platform_get_irq_byname(pdev, irq_name);
-                }
-                edma_cc[j]->irq_res_end = err_irq[j];
-                status = devm_request_irq(&pdev->dev, err_irq[j],
-                                          dma_ccerr_handler, 0,
-                                          "edma_error", &pdev->dev);
                if (status < 0) {
                        dev_dbg(&pdev->dev,
                                "devm_request_irq %d failed --> %d\n",
@@ -1760,14 +1743,8 @@ static int edma_probe(struct platform_device *pdev)
                for (i = 0; i < edma_cc[j]->num_channels; i++)
                        map_dmach_queue(j, i, info[j]->default_queue);
-                queue_tc_mapping = info[j]->queue_tc_mapping;
                queue_priority_mapping = info[j]->queue_priority_mapping;
-                /* Event queue to TC mapping */
-                for (i = 0; queue_tc_mapping[i][0] != -1; i++)
-                        map_queue_tc(j, queue_tc_mapping[i][0],
-                                        queue_tc_mapping[i][1]);
                /* Event queue priority mapping */
                for (i = 0; queue_priority_mapping[i][0] != -1; i++)
                        assign_priority_to_queue(j,
@@ -1780,7 +1757,7 @@ static int edma_probe(struct platform_device *pdev)
                if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
                        map_dmach_param(j);
-                for (i = 0; i < info[j]->n_region; i++) {
+                for (i = 0; i < edma_cc[j]->num_region; i++) {
                        edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
                        edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
                        edma_write_array(j, EDMA_QRAE, i, 0x0);
diff --git a/arch/arm/common/mcpm_entry.c b/arch/arm/common/mcpm_entry.c
index 86fd60fefbc9..f91136ab447e 100644
--- a/arch/arm/common/mcpm_entry.c
+++ b/arch/arm/common/mcpm_entry.c
@@ -106,14 +106,14 @@ void mcpm_cpu_power_down(void)
        BUG();
 }
-int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster)
+int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster)
 {
        int ret;
-        if (WARN_ON_ONCE(!platform_ops || !platform_ops->power_down_finish))
+        if (WARN_ON_ONCE(!platform_ops || !platform_ops->wait_for_powerdown))
                return -EUNATCH;
-        ret = platform_ops->power_down_finish(cpu, cluster);
+        ret = platform_ops->wait_for_powerdown(cpu, cluster);
        if (ret)
                pr_warn("%s: cpu %u, cluster %u failed to power down (%d)\n",
                        __func__, cpu, cluster, ret);
diff --git a/arch/arm/common/mcpm_platsmp.c b/arch/arm/common/mcpm_platsmp.c
index 177251a4dd9a..92e54d7c6f46 100644
--- a/arch/arm/common/mcpm_platsmp.c
+++ b/arch/arm/common/mcpm_platsmp.c
@@ -62,7 +62,7 @@ static int mcpm_cpu_kill(unsigned int cpu)
        cpu_to_pcpu(cpu, &pcpu, &pcluster);
-        return !mcpm_cpu_power_down_finish(pcpu, pcluster);
+        return !mcpm_wait_for_cpu_powerdown(pcpu, pcluster);
 }
 static int mcpm_cpu_disable(unsigned int cpu)
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index e181a50fd65a..c6661a60025d 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -83,7 +83,6 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=m
-CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_ATMEL=y
@@ -146,6 +145,8 @@ CONFIG_DMADEVICES=y
 CONFIG_AT_HDMAC=y
 CONFIG_DMATEST=m
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
 CONFIG_EXT4_FS=y
 CONFIG_FANOTIFY=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/at91sam9rl_defconfig b/arch/arm/configs/at91sam9rl_defconfig
index 85f846ae9ff2..5d7797d43d23 100644
--- a/arch/arm/configs/at91sam9rl_defconfig
+++ b/arch/arm/configs/at91sam9rl_defconfig
@@ -45,7 +45,6 @@ CONFIG_INPUT_EVDEV=y
 # CONFIG_INPUT_KEYBOARD is not set
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
 CONFIG_SERIAL_ATMEL=y
 CONFIG_SERIAL_ATMEL_CONSOLE=y
@@ -65,6 +64,8 @@ CONFIG_MMC=y
 CONFIG_MMC_ATMELMCI=m
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AT91SAM9=y
+CONFIG_IIO=y
+CONFIG_AT91_ADC=y
 CONFIG_EXT2_FS=y
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
new file mode 100644
index 000000000000..d3260d7d5af1
--- /dev/null
+++ b/arch/arm/configs/axm55xx_defconfig
@@ -0,0 +1,248 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_AXXIA=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_ARM_LPAE=y
+CONFIG_ARM_THUMBEE=y
+CONFIG_ARM_ERRATA_430973=y
+CONFIG_ARM_ERRATA_643719=y
+CONFIG_ARM_ERRATA_720789=y
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_754327=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_ARM_ERRATA_775420=y
+CONFIG_ARM_ERRATA_798181=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIE_AXXIA=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=16
+CONFIG_HOTPLUG_CPU=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+CONFIG_HIGHMEM=y
+CONFIG_KSM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_BINFMT_MISC=y
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_NETWORK_PHY_TIMESTAMPING=y
+CONFIG_BRIDGE=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_AFS_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_PATA_PLATFORM=y
+CONFIG_PATA_OF_PLATFORM=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+CONFIG_VIRTIO_NET=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_BROADCOM_PHY=y
+# CONFIG_WLAN is not set
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_SERIO_AMBAKMI=y
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_VIRTIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_AXXIA=y
+CONFIG_SPI=y
+CONFIG_SPI_PL022=y
+CONFIG_DP83640_PHY=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_AXXIA=y
+CONFIG_SENSORS_ADT7475=y
+CONFIG_SENSORS_JC42=y
+CONFIG_SENSORS_LM75=y
+CONFIG_PMBUS=y
+CONFIG_SENSORS_LTC2978=y
+CONFIG_WATCHDOG=y
+CONFIG_ARM_SP805_WATCHDOG=y
+CONFIG_FB=y
+CONFIG_FB_ARMCLCD=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_HID_A4TECH=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_KYE=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_EHCI_HCD=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+CONFIG_USB_EHCI_HCD_AXXIA=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
+CONFIG_DMADEVICES=y
+CONFIG_PL330_DMA=y
+CONFIG_VIRT_DRIVERS=y
+CONFIG_VIRTIO_MMIO=y
+CONFIG_MAILBOX=y
+CONFIG_PL320_MBOX=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_FSCACHE_DEBUG=y
+CONFIG_FSCACHE_OBJECT_LIST=y
+CONFIG_CACHEFILES=y
+CONFIG_CACHEFILES_HISTOGRAM=y
+CONFIG_ISO9660_FS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_CRAMFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFS_FSCACHE=y
+CONFIG_SUNRPC_DEBUG=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_CRYPTO_SHA256=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_VIRTUALIZATION=y
+CONFIG_KVM=y
diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig
index 5b54abbeb0b3..0494c8f229a2 100644
--- a/arch/arm/configs/badge4_defconfig
+++ b/arch/arm/configs/badge4_defconfig
@@ -73,8 +73,6 @@ CONFIG_SA1100_WATCHDOG=m
 CONFIG_SOUND=y
 CONFIG_SOUND_PRIME=y
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_ACM=m
 CONFIG_USB_PRINTER=m
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 3df3f3a79ef4..9d13dae99125 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -91,6 +91,7 @@ CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_UNSAFE_RESUME=y
@@ -104,6 +105,8 @@ CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_PWM=y
+CONFIG_PWM_BCM_KONA=y
 CONFIG_EXT4_FS=y
 CONFIG_EXT4_FS_POSIX_ACL=y
 CONFIG_EXT4_FS_SECURITY=y
diff --git a/arch/arm/configs/cm_x2xx_defconfig b/arch/arm/configs/cm_x2xx_defconfig
index a93ff8da5bab..dc01c049a520 100644
--- a/arch/arm/configs/cm_x2xx_defconfig
+++ b/arch/arm/configs/cm_x2xx_defconfig
@@ -144,7 +144,6 @@ CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index f4b767256f95..7df040e91c1c 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -129,7 +129,6 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig
index 2ef2c5e8aaec..18c311ae1113 100644
--- a/arch/arm/configs/colibri_pxa270_defconfig
+++ b/arch/arm/configs/colibri_pxa270_defconfig
@@ -124,7 +124,6 @@ CONFIG_FONT_8x16=y
 CONFIG_LOGO=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_SERIAL=m
 CONFIG_USB_GADGET=m
diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig
index b985334e42dd..be02fe2b14cb 100644
--- a/arch/arm/configs/colibri_pxa300_defconfig
+++ b/arch/arm/configs/colibri_pxa300_defconfig
@@ -47,9 +47,7 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_LOGO=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index 1fd1d1de3220..c1470a00f55a 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -172,7 +172,6 @@ CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
 CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=m
 CONFIG_USB_SL811_HCD=m
 CONFIG_USB_SL811_CS=m
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 2a282c051cfd..f95f72d62db7 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -157,10 +157,8 @@ CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
 CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=m
 CONFIG_USB_MUSB_HDRC=m
-CONFIG_USB_MUSB_PERIPHERAL=y
 CONFIG_USB_GADGET_MUSB_HDRC=y
 CONFIG_MUSB_PIO_ONLY=y
 CONFIG_USB_STORAGE=m
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index f15955144175..701677f9248c 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -37,7 +37,6 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_JEDECPROBE=y
@@ -48,6 +47,7 @@ CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_STAA=y
 CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
index 60a21e01eb70..4560c9ca6636 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/em_x270_defconfig
@@ -144,7 +144,6 @@ CONFIG_HID_SAMSUNG=y
 CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 6ac5ea73bd0a..1b650c85bdd0 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -80,7 +80,6 @@ CONFIG_I2C_DEBUG_BUS=y
 CONFIG_WATCHDOG=y
 CONFIG_EP93XX_WATCHDOG=y
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 CONFIG_USB_DYNAMIC_MINORS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_HCD_PLATFORM=y
diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig
index 4ce7b70ea901..e07a227ec0db 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -65,6 +65,7 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
 CONFIG_I2C=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_ARB_GPIO_CHALLENGE=y
+CONFIG_I2C_EXYNOS5=y
 CONFIG_I2C_S3C2410=y
 CONFIG_DEBUG_GPIO=y
 # CONFIG_HWMON is not set
diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
index 038518ab39a8..87e020f303ab 100644
--- a/arch/arm/configs/footbridge_defconfig
+++ b/arch/arm/configs/footbridge_defconfig
@@ -100,8 +100,6 @@ CONFIG_FB_CYBER2000=y
 CONFIG_SOUND=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=m
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=m
 CONFIG_USB_PRINTER=m
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index f1aeb7d72712..bada59d93b67 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -80,6 +80,7 @@ CONFIG_MTD_UBI=y
 CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_ATA=y
+CONFIG_BLK_DEV_SD=y
 CONFIG_PATA_IMX=y
 CONFIG_NETDEVICES=y
 CONFIG_CS89x0=y
@@ -153,8 +154,12 @@ CONFIG_USB_HID=m
 CONFIG_USB=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_NOP_USB_XCEIV=y
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -177,7 +182,6 @@ CONFIG_RTC_DRV_MXC=y
 CONFIG_DMADEVICES=y
 CONFIG_IMX_SDMA=y
 CONFIG_IMX_DMA=y
-CONFIG_COMMON_CLK_DEBUG=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 09e974392fa1..ef8815327e5b 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,4 +1,3 @@
-# CONFIG_LOCALVERSION_AUTO is not set
 CONFIG_KERNEL_LZO=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ=y
@@ -33,7 +32,6 @@ CONFIG_MACH_PCM043=y
 CONFIG_MACH_MX35_3DS=y
 CONFIG_MACH_VPR200=y
 CONFIG_MACH_IMX51_DT=y
-CONFIG_MACH_EUKREA_CPUIMX51SD=y
 CONFIG_SOC_IMX50=y
 CONFIG_SOC_IMX53=y
 CONFIG_SOC_IMX6Q=y
@@ -46,7 +44,11 @@ CONFIG_VMSPLIT_2G=y
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
+CONFIG_CMA=y
 CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
 CONFIG_VFP=y
 CONFIG_NEON=y
 CONFIG_BINFMT_MISC=m
@@ -72,6 +74,7 @@ CONFIG_RFKILL_INPUT=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
 CONFIG_IMX_WEIM=y
 CONFIG_CONNECTOR=y
 CONFIG_MTD=y
@@ -89,6 +92,7 @@ CONFIG_MTD_SST25L=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
 CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_RAM=y
@@ -183,6 +187,7 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_CODA=y
 CONFIG_SOC_CAMERA_OV2640=y
 CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_LCD_CLASS_DEVICE=y
 CONFIG_LCD_L4F00242T03=y
@@ -215,7 +220,6 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
@@ -245,7 +249,7 @@ CONFIG_DRM_IMX_TVE=y
 CONFIG_DRM_IMX_LDB=y
 CONFIG_DRM_IMX_IPUV3_CORE=y
 CONFIG_DRM_IMX_IPUV3=y
-CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_DRM_IMX_HDMI=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_PWM=y
 CONFIG_PWM_IMX=y
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index 063e2ab2c8f1..1af665e847d1 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -169,7 +169,6 @@ CONFIG_SENSORS_W83781D=y
 CONFIG_WATCHDOG=y
 CONFIG_IXP4XX_WATCHDOG=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index ec9a41d50680..095bb52671f6 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -135,7 +135,6 @@ CONFIG_WATCHDOG=y
 CONFIG_WATCHDOG_CORE=y
 CONFIG_DAVINCI_WATCHDOG=y
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_XHCI_HCD=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 2e762d94e94b..b9e480c10b10 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -61,6 +61,7 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_EEPROM_AT24=y
 # CONFIG_SCSI_PROC_FS is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 12bd1f63c399..bd097d455f87 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -106,7 +106,6 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_SH4_FSI=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_R8A66597_HCD=y
 CONFIG_USB_RENESAS_USBHS=y
 CONFIG_USB_STORAGE=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index a07948a87caa..9c93f5655248 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -217,7 +217,6 @@ CONFIG_HID_SONY=y
 CONFIG_HID_SUNPLUS=y
 CONFIG_HID_TOPSEED=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=m
diff --git a/arch/arm/configs/msm_defconfig b/arch/arm/configs/msm_defconfig
index c5858b9eb516..7f52dad97f51 100644
--- a/arch/arm/configs/msm_defconfig
+++ b/arch/arm/configs/msm_defconfig
@@ -17,21 +17,14 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_MODULE_FORCE_UNLOAD=y
 CONFIG_MODVERSIONS=y
 CONFIG_PARTITION_ADVANCED=y
-CONFIG_ARCH_MSM_DT=y
+CONFIG_ARCH_MSM=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MSM8960=y
-CONFIG_ARCH_MSM8974=y
-CONFIG_SMP=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_HIGHPTE=y
 CONFIG_CLEANCACHE=y
-CONFIG_CC_STACKPROTECTOR=y
+CONFIG_AUTO_ZRELADDR=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
-CONFIG_NEON=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 CONFIG_NET=y
 CONFIG_PACKET=y
@@ -79,16 +72,12 @@ CONFIG_SERIO_LIBPS2=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_MSM=y
 CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM is not set
-CONFIG_HW_RANDOM_MSM=y
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_SPI=y
 CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_POWER_RESET=y
-CONFIG_POWER_RESET_MSM=y
 CONFIG_THERMAL=y
 CONFIG_REGULATOR=y
 CONFIG_MEDIA_SUPPORT=y
@@ -100,25 +89,17 @@ CONFIG_SND_DYNAMIC_MINORS=y
 # CONFIG_SND_SPI is not set
 # CONFIG_SND_USB is not set
 CONFIG_SND_SOC=y
-CONFIG_HID_BATTERY_STRENGTH=y
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MSM=y
 CONFIG_USB_ACM=y
 CONFIG_USB_SERIAL=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_DEBUG_FILES=y
 CONFIG_USB_GADGET_VBUS_DRAW=500
-CONFIG_NEW_LEDS=y
 CONFIG_RTC_CLASS=y
 CONFIG_STAGING=y
-CONFIG_COMMON_CLK_QCOM=y
-CONFIG_MSM_GCC_8660=y
-CONFIG_MSM_MMCC_8960=y
-CONFIG_MSM_MMCC_8974=y
-CONFIG_MSM_IOMMU=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT3_FS=y
diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
index aa3dfb084fed..5ebfa8bf8509 100644
--- a/arch/arm/configs/multi_v5_defconfig
+++ b/arch/arm/configs/multi_v5_defconfig
@@ -11,7 +11,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_KIRKWOOD=y
-CONFIG_MACH_T5325=y
 CONFIG_ARCH_MXC=y
 CONFIG_MACH_IMX25_DT=y
 CONFIG_MACH_IMX27_DT=y
@@ -108,6 +107,8 @@ CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_KIRKWOOD_SOC=y
 CONFIG_SND_KIRKWOOD_SOC_T5325=y
+CONFIG_SND_SOC_ALC5623=y
+CONFIG_SND_SIMPLE_CARD=y
 # CONFIG_ABX500_CORE is not set
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index d4e8a47a2f7c..e2d62048e198 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -5,9 +5,11 @@ CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
 CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_ARMADA_370=y
 CONFIG_MACH_ARMADA_375=y
@@ -15,12 +17,12 @@ CONFIG_MACH_ARMADA_38X=y
 CONFIG_MACH_ARMADA_XP=y
 CONFIG_MACH_DOVE=y
 CONFIG_ARCH_BCM=y
-CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BCM_MOBILE=y
+CONFIG_ARCH_BCM_5301X=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_MACH_BERLIN_BG2=y
 CONFIG_MACH_BERLIN_BG2CD=y
-CONFIG_GPIO_PCA953X=y
+CONFIG_MACH_BERLIN_BG2Q=y
 CONFIG_ARCH_HIGHBANK=y
 CONFIG_ARCH_HI3xxx=y
 CONFIG_ARCH_KEYSTONE=y
@@ -34,8 +36,8 @@ CONFIG_ARCH_OMAP3=y
 CONFIG_ARCH_OMAP4=y
 CONFIG_SOC_OMAP5=y
 CONFIG_SOC_AM33XX=y
-CONFIG_SOC_DRA7XX=y
 CONFIG_SOC_AM43XX=y
+CONFIG_SOC_DRA7XX=y
 CONFIG_ARCH_QCOM=y
 CONFIG_ARCH_MSM8X60=y
 CONFIG_ARCH_MSM8960=y
@@ -47,6 +49,7 @@ CONFIG_ARCH_SPEAR13XX=y
 CONFIG_MACH_SPEAR1310=y
 CONFIG_MACH_SPEAR1340=y
 CONFIG_ARCH_STI=y
+CONFIG_ARCH_EXYNOS=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_ARCH_SIRF=y
 CONFIG_ARCH_TEGRA=y
@@ -61,7 +64,6 @@ CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_UX500_DT=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_VEXPRESS_CA9X4=y
-CONFIG_ARCH_VIRT=y
 CONFIG_ARCH_WM8850=y
 CONFIG_ARCH_ZYNQ=y
 CONFIG_NEON=y
@@ -71,6 +73,7 @@ CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_PCI_TEGRA=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=8
 CONFIG_HIGHPTE=y
 CONFIG_CMA=y
 CONFIG_ARM_APPENDED_DTB=y
@@ -96,6 +99,11 @@ CONFIG_INET6_IPCOMP=m
 CONFIG_IPV6_MIP6=m
 CONFIG_IPV6_TUNNEL=m
 CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251X=y
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
 CONFIG_RFKILL=y
@@ -112,15 +120,19 @@ CONFIG_BLK_DEV_LOOP=y
 CONFIG_ICS932S401=y
 CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_SUNXI_SID=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
 CONFIG_SCSI_MULTI_LUN=y
 CONFIG_ATA=y
 CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_SUNXI=y
 CONFIG_SATA_HIGHBANK=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
+CONFIG_MACB=y
 CONFIG_NET_CALXEDA_XGMAC=y
 CONFIG_MV643XX_ETH=y
 CONFIG_MVNETA=y
@@ -153,6 +165,8 @@ CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_DW=y
 CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
 CONFIG_SERIAL_SIRFSOC=y
 CONFIG_SERIAL_SIRFSOC_CONSOLE=y
 CONFIG_SERIAL_TEGRA=y
@@ -175,7 +189,9 @@ CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
 CONFIG_I2C_MUX_PINCTRL=y
+CONFIG_I2C_CADENCE=y
 CONFIG_I2C_DESIGNWARE_PLATFORM=y
+CONFIG_I2C_EXYNOS5=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_I2C_SIRF=y
 CONFIG_I2C_TEGRA=y
@@ -184,6 +200,8 @@ CONFIG_SPI_OMAP24XX=y
 CONFIG_SPI_ORION=y
 CONFIG_SPI_PL022=y
 CONFIG_SPI_SIRF=y
+CONFIG_SPI_SUN4I=y
+CONFIG_SPI_SUN6I=y
 CONFIG_SPI_TEGRA114=y
 CONFIG_SPI_TEGRA20_SFLASH=y
 CONFIG_SPI_TEGRA20_SLINK=y
@@ -191,6 +209,8 @@ CONFIG_PINCTRL_AS3722=y
 CONFIG_PINCTRL_PALMAS=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
 CONFIG_GPIO_TWL4030=y
 CONFIG_GPIO_PALMAS=y
@@ -200,16 +220,19 @@ CONFIG_BATTERY_SBS=y
 CONFIG_CHARGER_TPS65090=y
 CONFIG_POWER_RESET_AS3722=y
 CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_SUN6I=y
 CONFIG_SENSORS_LM90=y
 CONFIG_THERMAL=y
 CONFIG_DOVE_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
 CONFIG_WATCHDOG=y
 CONFIG_ORION_WATCHDOG=y
+CONFIG_SUNXI_WATCHDOG=y
 CONFIG_MFD_AS3722=y
 CONFIG_MFD_CROS_EC=y
 CONFIG_MFD_CROS_EC_SPI=y
 CONFIG_MFD_MAX8907=y
+CONFIG_MFD_SEC_CORE=y
 CONFIG_MFD_PALMAS=y
 CONFIG_MFD_TPS65090=y
 CONFIG_MFD_TPS6586X=y
@@ -220,6 +243,8 @@ CONFIG_REGULATOR_AS3722=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_S2MPS11=y
+CONFIG_REGULATOR_S5M8767=y
 CONFIG_REGULATOR_TPS51632=y
 CONFIG_REGULATOR_TPS62360=y
 CONFIG_REGULATOR_TPS65090=y
@@ -254,10 +279,13 @@ CONFIG_SND_SOC_TEGRA_ALC5632=y
 CONFIG_SND_SOC_TEGRA_MAX98090=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MVEBU=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_TEGRA=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_ISP1760_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_HOST=y
@@ -272,20 +300,28 @@ CONFIG_MMC=y
 CONFIG_MMC_BLOCK_MINORS=16
 CONFIG_MMC_ARMMMCI=y
 CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_OF_ARASAN=y
 CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_MMC_SDHCI_TEGRA=y
 CONFIG_MMC_SDHCI_DOVE=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_SDHCI_SPEAR=y
+CONFIG_MMC_SDHCI_S3C=y
+CONFIG_MMC_SDHCI_S3C_DMA=y
 CONFIG_MMC_SDHCI_BCM_KONA=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_MMC_MVSDIO=y
+CONFIG_MMC_SUNXI=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_EXYNOS=y
 CONFIG_EDAC=y
 CONFIG_EDAC_MM_EDAC=y
 CONFIG_EDAC_HIGHBANK_MC=y
 CONFIG_EDAC_HIGHBANK_L2=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AS3722=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TWL4030=y
@@ -294,6 +330,7 @@ CONFIG_RTC_DRV_TPS65910=y
 CONFIG_RTC_DRV_EM3027=y
 CONFIG_RTC_DRV_PL031=y
 CONFIG_RTC_DRV_VT8500=y
+CONFIG_RTC_DRV_SUNXI=y
 CONFIG_RTC_DRV_MV=y
 CONFIG_RTC_DRV_TEGRA=y
 CONFIG_DMADEVICES=y
@@ -328,6 +365,7 @@ CONFIG_PWM=y
 CONFIG_PWM_TEGRA=y
 CONFIG_PWM_VT8500=y
 CONFIG_OMAP_USB2=y
+CONFIG_PHY_SUN4I_USB=y
 CONFIG_EXT4_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
index 1f08219c1b3c..0dae1c1f007a 100644
--- a/arch/arm/configs/mv78xx0_defconfig
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -80,7 +80,6 @@ CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_EHCI_TT_NEWSCHED=y
diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
index 36484a37a1ca..27c732fdf21e 100644
--- a/arch/arm/configs/mvebu_v5_defconfig
+++ b/arch/arm/configs/mvebu_v5_defconfig
@@ -1,4 +1,5 @@
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
@@ -11,7 +12,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_ARCH_MULTI_V7 is not set
 CONFIG_ARCH_MVEBU=y
 CONFIG_MACH_KIRKWOOD=y
-CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
 CONFIG_PCI_MVEBU=y
 CONFIG_PREEMPT=y
@@ -50,6 +50,7 @@ CONFIG_MTD_PHYSMAP=y
 CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_EEPROM_AT24=y
 # CONFIG_SCSI_PROC_FS is not set
@@ -100,6 +101,8 @@ CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_KIRKWOOD_SOC=y
 CONFIG_SND_KIRKWOOD_SOC_T5325=y
+CONFIG_SND_SOC_ALC5623=y
+CONFIG_SND_SIMPLE_CARD=y
 CONFIG_REGULATOR=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_HID_DRAGONRISE=y
diff --git a/arch/arm/configs/mvebu_v7_defconfig b/arch/arm/configs/mvebu_v7_defconfig
index a34713d8db9f..e11170e37442 100644
--- a/arch/arm/configs/mvebu_v7_defconfig
+++ b/arch/arm/configs/mvebu_v7_defconfig
@@ -1,5 +1,6 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
 CONFIG_IRQ_DOMAIN_DEBUG=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=14
@@ -17,6 +18,7 @@ CONFIG_NEON=y
 # CONFIG_CACHE_L2X0 is not set
 # CONFIG_SWP_EMULATE is not set
 CONFIG_PCI=y
+CONFIG_PCI_MSI=y
 CONFIG_PCI_MVEBU=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
@@ -29,6 +31,9 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
 CONFIG_NET=y
 CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
 CONFIG_BT=y
 CONFIG_BT_MRVL=y
 CONFIG_BT_MRVL_SDIO=y
@@ -36,6 +41,7 @@ CONFIG_CFG80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
+CONFIG_AHCI_MVEBU=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
 CONFIG_MVNETA=y
@@ -53,6 +59,7 @@ CONFIG_I2C_MV64XXX=y
 CONFIG_MTD=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_CFI=y
 CONFIG_MTD_CFI_INTELEXT=y
 CONFIG_MTD_CFI_AMDSTD=y
@@ -78,7 +85,9 @@ CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MVEBU=y
 CONFIG_MMC=y
+CONFIG_MMC_SDHCI_PXAV3=y
 CONFIG_MMC_MVSDIO=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_GPIO=y
@@ -103,6 +112,8 @@ CONFIG_UDF_FS=m
 CONFIG_MSDOS_FS=y
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
 CONFIG_NLS_ISO8859_1=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 6150108e15de..a9f992335eb2 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -26,7 +26,6 @@ CONFIG_ARCH_MXS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_PREEMPT_VOLUNTARY=y
 CONFIG_AEABI=y
-CONFIG_FPE_NWFPE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -51,10 +50,10 @@ CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_BLOCK=y
 CONFIG_MTD_DATAFLASH=y
 CONFIG_MTD_M25P80=y
-# CONFIG_M25PXX_USE_FAST_READ is not set
 CONFIG_MTD_SST25L=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=y
 # CONFIG_BLK_DEV is not set
 CONFIG_EEPROM_AT24=y
@@ -120,7 +119,6 @@ CONFIG_USB_GADGET=y
 CONFIG_USB_ETH=m
 CONFIG_USB_MASS_STORAGE=m
 CONFIG_MMC=y
-CONFIG_MMC_UNSAFE_RESUME=y
 CONFIG_MMC_MXS=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
@@ -138,7 +136,6 @@ CONFIG_DMADEVICES=y
 CONFIG_MXS_DMA=y
 CONFIG_STAGING=y
 CONFIG_MXS_LRADC=y
-CONFIG_COMMON_CLK_DEBUG=y
 CONFIG_IIO=y
 CONFIG_IIO_SYSFS_TRIGGER=y
 CONFIG_PWM=y
@@ -180,7 +177,7 @@ CONFIG_BLK_DEV_IO_TRACE=y
 CONFIG_STRICT_DEVMEM=y
 CONFIG_DEBUG_USER=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
-# CONFIG_CRYPTO_HW is not set
+CONFIG_CRYPTO_DEV_MXS_DCP=y
 CONFIG_CRC_ITU_T=m
 CONFIG_CRC7=m
 CONFIG_FONTS=y
diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
index d7dc9922cfff..460dca4a4f98 100644
--- a/arch/arm/configs/neponset_defconfig
+++ b/arch/arm/configs/neponset_defconfig
@@ -68,8 +68,6 @@ CONFIG_SOUND=y
 CONFIG_SOUND_PRIME=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=m
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=m
 CONFIG_USB_OHCI_HCD=m
 CONFIG_USB_STORAGE=m
diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
index d74edbad18fc..ce541bb3c2de 100644
--- a/arch/arm/configs/omap1_defconfig
+++ b/arch/arm/configs/omap1_defconfig
@@ -197,8 +197,6 @@ CONFIG_SND_OMAP_SOC=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
 CONFIG_USB_PHY=y
-CONFIG_USB_DEBUG=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index a4e8d017f25b..59066cf0271a 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -21,6 +21,8 @@ CONFIG_MODULE_SRCVERSION_ALL=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_MULTI_V6=y
+CONFIG_POWER_AVS_OMAP=y
+CONFIG_POWER_AVS_OMAP_CLASS3=y
 CONFIG_OMAP_RESET_CLOCKS=y
 CONFIG_OMAP_MUX_DEBUG=y
 CONFIG_ARCH_OMAP2=y
@@ -42,6 +44,7 @@ CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_CMDLINE="root=/dev/mmcblk0p2 rootwait console=ttyO2,115200"
 CONFIG_KEXEC=y
 CONFIG_FPE_NWFPE=y
+CONFIG_CPU_IDLE=y
 CONFIG_BINFMT_MISC=y
 CONFIG_PM_DEBUG=y
 CONFIG_NET=y
@@ -159,11 +162,14 @@ CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_TWL4030=y
 CONFIG_W1=y
 CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_AVS=y
 CONFIG_SENSORS_LM75=m
 CONFIG_THERMAL=y
 CONFIG_THERMAL_GOV_FAIR_SHARE=y
 CONFIG_THERMAL_GOV_USER_SPACE=y
+CONFIG_CPU_THERMAL=y
 CONFIG_TI_SOC_THERMAL=y
+CONFIG_TI_THERMAL=y
 CONFIG_OMAP4_THERMAL=y
 CONFIG_OMAP5_THERMAL=y
 CONFIG_DRA752_THERMAL=y
@@ -177,6 +183,7 @@ CONFIG_MFD_TPS65910=y
 CONFIG_TWL6040_CORE=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_PALMAS=y
+CONFIG_REGULATOR_TI_ABB=y
 CONFIG_REGULATOR_TPS65023=y
 CONFIG_REGULATOR_TPS6507X=y
 CONFIG_REGULATOR_TPS65217=y
@@ -217,7 +224,6 @@ CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
 CONFIG_SND_OMAP_SOC_OMAP_ABE_TWL6040=m
 CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_WDM=y
@@ -239,6 +245,7 @@ CONFIG_SDIO_UART=y
 CONFIG_MMC_OMAP=y
 CONFIG_MMC_OMAP_HS=y
 CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig
index 2f136c30a989..0a847d04ddc1 100644
--- a/arch/arm/configs/pcm027_defconfig
+++ b/arch/arm/configs/pcm027_defconfig
@@ -76,7 +76,6 @@ CONFIG_SND_PCM_OSS=y
 CONFIG_SND_PXA2XX_AC97=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=y
 CONFIG_MMC=y
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
new file mode 100644
index 000000000000..42ebd72799e6
--- /dev/null
+++ b/arch/arm/configs/qcom_defconfig
@@ -0,0 +1,165 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_KPROBES=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_QCOM=y
+CONFIG_ARCH_MSM8X60=y
+CONFIG_ARCH_MSM8960=y
+CONFIG_ARCH_MSM8974=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_CLEANCACHE=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_CFG80211=y
+CONFIG_RFKILL=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SCSI=y
+CONFIG_SCSI_TGT=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_SLIP=y
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLIP_MODE_SLIP6=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_AX8817X is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_MSM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_QUP=y
+CONFIG_SPI=y
+CONFIG_SPI_QUP=y
+CONFIG_SPMI=y
+CONFIG_PINCTRL_APQ8064=y
+CONFIG_PINCTRL_IPQ8064=y
+CONFIG_PINCTRL_MSM8X74=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_MSM=y
+CONFIG_THERMAL=y
+CONFIG_REGULATOR=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_FB=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_HID_BATTERY_STRENGTH=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_MON=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ACM=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DEBUG_FILES=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_RTC_CLASS=y
+CONFIG_DMADEVICES=y
+CONFIG_QCOM_BAM_DMA=y
+CONFIG_STAGING=y
+CONFIG_QCOM_GSBI=y
+CONFIG_COMMON_CLK_QCOM=y
+CONFIG_MSM_GCC_8660=y
+CONFIG_MSM_MMCC_8960=y
+CONFIG_MSM_MMCC_8974=y
+CONFIG_MSM_IOMMU=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_CIFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
diff --git a/arch/arm/configs/raumfeld_defconfig b/arch/arm/configs/raumfeld_defconfig
index f7caa909b40d..3d833aea545a 100644
--- a/arch/arm/configs/raumfeld_defconfig
+++ b/arch/arm/configs/raumfeld_defconfig
@@ -122,7 +122,6 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index abe61bf379d2..1da5d9e48224 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -76,8 +76,10 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index 7079cbe898a8..d02e9d911bb7 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -75,8 +75,10 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_PL031=y
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index 193448f31284..eb4d204bff47 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -324,7 +324,6 @@ CONFIG_SND_USB_CAIAQ=m
 CONFIG_SND_SOC=y
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=m
diff --git a/arch/arm/configs/s3c6400_defconfig b/arch/arm/configs/s3c6400_defconfig
index 3a186d653dac..e2f9fa5bb54b 100644
--- a/arch/arm/configs/s3c6400_defconfig
+++ b/arch/arm/configs/s3c6400_defconfig
@@ -56,7 +56,6 @@ CONFIG_SND_S3C24XX_SOC=m
 CONFIG_SND_SOC_SMDK_WM9713=m
 CONFIG_USB=y
 CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_ACM=m
 CONFIG_USB_PRINTER=m
diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig
index dc3881e07630..4414990521d3 100644
--- a/arch/arm/configs/sama5_defconfig
+++ b/arch/arm/configs/sama5_defconfig
@@ -122,7 +122,6 @@ CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_ATMEL_MXT=y
-CONFIG_TOUCHSCREEN_ATMEL_TSADCC=y
 # CONFIG_SERIO is not set
 CONFIG_LEGACY_PTY_COUNT=4
 CONFIG_SERIAL_ATMEL=y
@@ -138,6 +137,8 @@ CONFIG_SPI_GPIO=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
 CONFIG_SSB=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_ACT8865=y
 CONFIG_FB=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 # CONFIG_LCD_CLASS_DEVICE is not set
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index 83b07258a385..6d6437cbbc52 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -25,6 +25,7 @@ CONFIG_SCHED_MC=y
 CONFIG_HAVE_ARM_ARCH_TIMER=y
 CONFIG_NR_CPUS=8
 CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
 CONFIG_ZBOOT_ROM_BSS=0x0
 CONFIG_ARM_APPENDED_DTB=y
@@ -43,6 +44,7 @@ CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_EEPROM_AT24=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_ATA=y
 CONFIG_SATA_RCAR=y
@@ -75,9 +77,11 @@ CONFIG_SERIAL_SH_SCI=y
 CONFIG_SERIAL_SH_SCI_NR_UARTS=20
 CONFIG_SERIAL_SH_SCI_CONSOLE=y
 CONFIG_I2C_GPIO=y
+CONFIG_I2C_SH_MOBILE=y
 CONFIG_I2C_RCAR=y
 CONFIG_SPI=y
 CONFIG_SPI_RSPI=y
+CONFIG_SPI_SH_MSIOF=y
 CONFIG_GPIO_EM=y
 CONFIG_GPIO_RCAR=y
 # CONFIG_HWMON is not set
@@ -88,10 +92,14 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_MEDIA_SUPPORT=y
 CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
 CONFIG_V4L_PLATFORM_DRIVERS=y
 CONFIG_SOC_CAMERA=y
 CONFIG_SOC_CAMERA_PLATFORM=y
 CONFIG_VIDEO_RCAR_VIN=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_RENESAS_VSP1=y
 # CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
 CONFIG_VIDEO_ADV7180=y
 CONFIG_DRM=y
@@ -100,7 +108,13 @@ CONFIG_SOUND=y
 CONFIG_SND=y
 CONFIG_SND_SOC=y
 CONFIG_SND_SOC_RCAR=y
+CONFIG_USB=y
 CONFIG_USB_RCAR_GEN2_PHY=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_RENESAS_USBHS=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_RENESAS_USBHS_UDC=y
 CONFIG_MMC=y
 CONFIG_MMC_SDHI=y
 CONFIG_MMC_SH_MMCIF=y
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index 2e0419d1b964..a1ede1966baf 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -166,7 +166,6 @@ CONFIG_HID_SAMSUNG=m
 CONFIG_HID_SONY=m
 CONFIG_HID_SUNPLUS=m
 CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_MON=m
 CONFIG_USB_OHCI_HCD=m
 CONFIG_USB_SL811_HCD=m
diff --git a/arch/arm/configs/sunxi_defconfig b/arch/arm/configs/sunxi_defconfig
index b5df4a511b0a..7209bfd62074 100644
--- a/arch/arm/configs/sunxi_defconfig
+++ b/arch/arm/configs/sunxi_defconfig
@@ -1,13 +1,17 @@
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_BLK_DEV_INITRD=y
+CONFIG_PERF_EVENTS=y
 CONFIG_ARCH_SUNXI=y
 CONFIG_SMP=y
 CONFIG_AEABI=y
 CONFIG_HIGHMEM=y
 CONFIG_HIGHPTE=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
 CONFIG_VFP=y
 CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
 CONFIG_NET=y
 CONFIG_PACKET=y
 CONFIG_UNIX=y
@@ -25,8 +29,12 @@ CONFIG_IP_PNP_BOOTP=y
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 CONFIG_EEPROM_SUNXI_SID=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_AHCI_SUNXI=y
 CONFIG_NETDEVICES=y
 CONFIG_SUN4I_EMAC=y
+# CONFIG_NET_VENDOR_ARC is not set
 # CONFIG_NET_CADENCE is not set
 # CONFIG_NET_VENDOR_BROADCOM is not set
 # CONFIG_NET_VENDOR_CIRRUS is not set
@@ -34,38 +42,66 @@ CONFIG_SUN4I_EMAC=y
 # CONFIG_NET_VENDOR_INTEL is not set
 # CONFIG_NET_VENDOR_MARVELL is not set
 # CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
 # CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
 # CONFIG_NET_VENDOR_SEEQ is not set
 # CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_VIA is not set
 # CONFIG_NET_VENDOR_WIZNET is not set
 # CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_NR_UARTS=8
 CONFIG_SERIAL_8250_RUNTIME_UARTS=8
 CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
-# CONFIG_I2C_COMPAT is not set
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MV64XXX=y
 CONFIG_SPI=y
+CONFIG_SPI_SUN4I=y
 CONFIG_SPI_SUN6I=y
 CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_SUN6I=y
 # CONFIG_HWMON is not set
 CONFIG_WATCHDOG=y
 CONFIG_SUNXI_WATCHDOG=y
-# CONFIG_USB_SUPPORT is not set
+CONFIG_MFD_AXP20X=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_MMC=y
+CONFIG_MMC_SUNXI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_COMMON_CLK_DEBUG=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_INTF_SYSFS is not set
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_DRV_SUNXI=y
 # CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PHY_SUN4I_USB=y
+CONFIG_EXT4_FS=y
+CONFIG_VFAT_FS=y
 CONFIG_TMPFS=y
 CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
 CONFIG_ROOT_NFS=y
-CONFIG_NLS=y
 CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 71277a1591ba..7209a2caefcf 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -47,7 +47,6 @@ CONFIG_BLK_DEV_RAM_SIZE=10240
 # CONFIG_VGA_CONSOLE is not set
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=y
-CONFIG_USB_DEBUG=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_MON=y
 CONFIG_USB_OHCI_HCD=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 2926281368ab..fb25e2982f64 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -73,6 +73,11 @@ CONFIG_INET6_IPCOMP=y
 CONFIG_IPV6_MIP6=y
 CONFIG_IPV6_TUNNEL=y
 CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251X=y
 CONFIG_BT=y
 CONFIG_BT_RFCOMM=y
 CONFIG_BT_BNEP=y
@@ -90,6 +95,7 @@ CONFIG_DMA_CMA=y
 CONFIG_CMA_SIZE_MBYTES=64
 CONFIG_MTD=y
 CONFIG_MTD_M25P80=y
+CONFIG_MTD_SPI_NOR=y
 CONFIG_PROC_DEVICETREE=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_AD525X_DPOT=y
@@ -97,6 +103,7 @@ CONFIG_AD525X_DPOT_I2C=y
 CONFIG_ICS932S401=y
 CONFIG_APDS9802ALS=y
 CONFIG_ISL29003=y
+CONFIG_EEPROM_AT24=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=y
@@ -112,6 +119,7 @@ CONFIG_USB_NET_SMSC95XX=y
 CONFIG_BRCMFMAC=m
 CONFIG_RT2X00=y
 CONFIG_RT2800USB=m
+CONFIG_INPUT_JOYDEV=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 CONFIG_KEYBOARD_TEGRA=y
@@ -181,6 +189,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y
 # CONFIG_BACKLIGHT_GENERIC is not set
 CONFIG_BACKLIGHT_PWM=y
 CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 CONFIG_LOGO=y
 CONFIG_SOUND=y
 CONFIG_SND=y
@@ -222,6 +231,7 @@ CONFIG_LEDS_TRIGGER_TRANSIENT=y
 CONFIG_LEDS_TRIGGER_CAMERA=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_AS3722=y
+CONFIG_RTC_DRV_DS1307=y
 CONFIG_RTC_DRV_MAX8907=y
 CONFIG_RTC_DRV_PALMAS=y
 CONFIG_RTC_DRV_TPS6586X=y
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
index 3162173fa75a..932ee4e4a13a 100644
--- a/arch/arm/configs/trizeps4_defconfig
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -165,7 +165,6 @@ CONFIG_SND_PXA2XX_AC97=y
 CONFIG_SND_USB_AUDIO=m
 # CONFIG_USB_HID is not set
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 # CONFIG_USB_DEVICE_CLASS is not set
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_STORAGE=m
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 073541a50e23..d52b4ffe2012 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -61,6 +61,9 @@ CONFIG_SND_ARMAACI=m
 CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=m
 CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_VERSATILE=y
+CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_HEARTBEAT=y
 CONFIG_LEDS_TRIGGER_CPU=y
 CONFIG_EXT2_FS=y
diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig
index d36e0d3c86ec..0d717a5eff29 100644
--- a/arch/arm/configs/viper_defconfig
+++ b/arch/arm/configs/viper_defconfig
@@ -127,7 +127,6 @@ CONFIG_SND_MIXER_OSS=m
 CONFIG_SND_PCM_OSS=m
 CONFIG_SND_PXA2XX_AC97=m
 CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_ISP116X_HCD=m
 CONFIG_USB_SL811_HCD=m
 CONFIG_USB_R8A66597_HCD=m
diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig
index 731d4f985310..cd11da8b5123 100644
--- a/arch/arm/configs/zeus_defconfig
+++ b/arch/arm/configs/zeus_defconfig
@@ -132,7 +132,6 @@ CONFIG_SND_SOC=m
 CONFIG_SND_PXA2XX_SOC=m
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB=m
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_OHCI_HCD=m
 CONFIG_USB_ACM=m
 CONFIG_USB_STORAGE=m
diff --git a/arch/arm/include/asm/Kbuild b/arch/arm/include/asm/Kbuild
index 23e728ecf8ab..f5a357601983 100644
--- a/arch/arm/include/asm/Kbuild
+++ b/arch/arm/include/asm/Kbuild
@@ -21,6 +21,7 @@ generic-y += parport.h
 generic-y += poll.h
 generic-y += preempt.h
 generic-y += resource.h
+generic-y += rwsem.h
 generic-y += sections.h
 generic-y += segment.h
 generic-y += sembuf.h
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index b974184f9941..57f0584e8d97 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -312,7 +312,7 @@
 * you cannot return to the original mode.
 */
 .macro safe_svcmode_maskall reg:req
-#if __LINUX_ARM_ARCH__ >= 6
+#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
        mrs     \reg , cpsr
        eor     \reg, \reg, #HYP_MODE
        tst     \reg, #MODE_MASK
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 9a92fd7864a8..3040359094d9 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -241,11 +241,6 @@ static inline int __atomic_add_unless(atomic_t *v, int a, int u)
 #define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
-#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__after_atomic_inc()      smp_mb()
 #ifndef CONFIG_GENERIC_ATOMIC64
 typedef struct {
        long long counter;
diff --git a/arch/arm/include/asm/barrier.h b/arch/arm/include/asm/barrier.h
index 2f59f7443396..c6a3e73a6e24 100644
--- a/arch/arm/include/asm/barrier.h
+++ b/arch/arm/include/asm/barrier.h
@@ -79,5 +79,8 @@ do {									\
 #define set_mb(var, value)      do { var = value; smp_mb(); } while (0)
+#define smp_mb__before_atomic() smp_mb()
+#define smp_mb__after_atomic()  smp_mb()
 #endif /* !__ASSEMBLY__ */
 #endif /* __ASM_BARRIER_H */
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index b2e298a90d76..56380995f4c3 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -25,9 +25,7 @@
 #include <linux/compiler.h>
 #include <linux/irqflags.h>
+#include <asm/barrier.h>
-#define smp_mb__before_clear_bit()      smp_mb()
-#define smp_mb__after_clear_bit()       smp_mb()
 /*
 * These functions are the basis of our bit ops.
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index 8b8b61685a34..fd43f7f55b70 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -212,7 +212,7 @@ extern void copy_to_user_page(struct vm_area_struct *, struct page *,
 static inline void __flush_icache_all(void)
 {
        __flush_icache_preferred();
-        dsb();
+        dsb(ishst);
 }
 /*
@@ -487,4 +487,6 @@ int set_memory_rw(unsigned long addr, int numpages);
 int set_memory_x(unsigned long addr, int numpages);
 int set_memory_nx(unsigned long addr, int numpages);
+void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
+                             void *kaddr, unsigned long len);
 #endif
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 6493802f880a..c3f11524f10c 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -42,24 +42,23 @@
 #ifndef __ASSEMBLY__
 #if __LINUX_ARM_ARCH__ >= 4
-#define vectors_high()  (cr_alignment & CR_V)
+#define vectors_high()  (get_cr() & CR_V)
 #else
 #define vectors_high()  (0)
 #endif
 #ifdef CONFIG_CPU_CP15
-extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
-static inline unsigned int get_cr(void)
+static inline unsigned long get_cr(void)
 {
-        unsigned int val;
+        unsigned long val;
        asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
        return val;
 }
-static inline void set_cr(unsigned int val)
+static inline void set_cr(unsigned long val)
 {
        asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
          : : "r" (val) : "cc");
@@ -80,10 +79,6 @@ static inline void set_auxcr(unsigned int val)
        isb();
 }
-#ifndef CONFIG_SMP
-extern void adjust_cr(unsigned long mask, unsigned long set);
-#endif
 #define CPACC_FULL(n)           (3 << (n * 2))
 #define CPACC_SVC(n)            (1 << (n * 2))
 #define CPACC_DISABLE(n)        (0 << (n * 2))
@@ -106,13 +101,17 @@ static inline void set_copro_access(unsigned int val)
 #else /* ifdef CONFIG_CPU_CP15 */
 /*
- * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
+ * cr_alignment is tightly coupled to cp15 (at least in the minds of the
- * minds of the developers). Yielding 0 for machines without a cp15 (and making
+ * developers). Yielding 0 for machines without a cp15 (and making it
- * it read-only) is fine for most cases and saves quite some #ifdeffery.
+ * read-only) is fine for most cases and saves quite some #ifdeffery.
 */
-#define cr_no_alignment UL(0)
 #define cr_alignment    UL(0)
+static inline unsigned long get_cr(void)
+{
+        return 0;
+}
 #endif /* ifdef CONFIG_CPU_CP15 / else */
 #endif /* ifndef __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h
index 4764344367d4..8c2b7321a478 100644
--- a/arch/arm/include/asm/cputype.h
+++ b/arch/arm/include/asm/cputype.h
@@ -72,6 +72,7 @@
 #define ARM_CPU_PART_CORTEX_A15         0xC0F0
 #define ARM_CPU_PART_CORTEX_A7          0xC070
 #define ARM_CPU_PART_CORTEX_A12         0xC0D0
+#define ARM_CPU_PART_CORTEX_A17         0xC0E0
 #define ARM_CPU_XSCALE_ARCH_MASK        0xe000
 #define ARM_CPU_XSCALE_ARCH_V1          0x2000
diff --git a/arch/arm/include/asm/dcc.h b/arch/arm/include/asm/dcc.h
new file mode 100644
index 000000000000..b74899de0774
--- /dev/null
+++ b/arch/arm/include/asm/dcc.h
@@ -0,0 +1,41 @@
+/* Copyright (c) 2010, 2014 The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <asm/barrier.h>
+static inline u32 __dcc_getstatus(void)
+{
+        u32 __ret;
+        asm volatile("mrc p14, 0, %0, c0, c1, 0 @ read comms ctrl reg"
+                : "=r" (__ret) : : "cc");
+        return __ret;
+}
+static inline char __dcc_getchar(void)
+{
+        char __c;
+        asm volatile("mrc p14, 0, %0, c0, c5, 0 @ read comms data reg"
+                : "=r" (__c));
+        isb();
+        return __c;
+}
+static inline void __dcc_putchar(char c)
+{
+        asm volatile("mcr p14, 0, %0, c0, c5, 0 @ write a char"
+                : /* no output register */
+                : "r" (c));
+        isb();
+}
diff --git a/arch/arm/include/asm/dma-iommu.h b/arch/arm/include/asm/dma-iommu.h
index eec0a12c5c1d..8e3fcb924db6 100644
--- a/arch/arm/include/asm/dma-iommu.h
+++ b/arch/arm/include/asm/dma-iommu.h
@@ -18,7 +18,6 @@ struct dma_iommu_mapping {
        unsigned int            extensions;
        size_t                  bitmap_size;    /* size of a single bitmap */
        size_t                  bits;           /* per bitmap */
-        unsigned int            size;           /* per bitmap */
        dma_addr_t              base;
        spinlock_t              lock;
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index e701a4d9aa59..c45b61a4b4a5 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -58,21 +58,37 @@ static inline int dma_set_mask(struct device *dev, u64 mask)
 #ifndef __arch_pfn_to_dma
 static inline dma_addr_t pfn_to_dma(struct device *dev, unsigned long pfn)
 {
+        if (dev)
+                pfn -= dev->dma_pfn_offset;
        return (dma_addr_t)__pfn_to_bus(pfn);
 }
 static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr)
 {
-        return __bus_to_pfn(addr);
+        unsigned long pfn = __bus_to_pfn(addr);
+        if (dev)
+                pfn += dev->dma_pfn_offset;
+        return pfn;
 }
 static inline void *dma_to_virt(struct device *dev, dma_addr_t addr)
 {
+        if (dev) {
+                unsigned long pfn = dma_to_pfn(dev, addr);
+                return phys_to_virt(__pfn_to_phys(pfn));
+        }
        return (void *)__bus_to_virt((unsigned long)addr);
 }
 static inline dma_addr_t virt_to_dma(struct device *dev, void *addr)
 {
+        if (dev)
+                return pfn_to_dma(dev, virt_to_pfn(addr));
        return (dma_addr_t)__virt_to_bus((unsigned long)(addr));
 }
@@ -105,6 +121,13 @@ static inline unsigned long dma_max_pfn(struct device *dev)
 }
 #define dma_max_pfn(dev) dma_max_pfn(dev)
+static inline int set_arch_dma_coherent_ops(struct device *dev)
+{
+        set_dma_ops(dev, &arm_coherent_dma_ops);
+        return 0;
+}
+#define set_arch_dma_coherent_ops(dev)  set_arch_dma_coherent_ops(dev)
 static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
 {
        unsigned int offset = paddr & ~PAGE_MASK;
diff --git a/arch/arm/include/asm/fixmap.h b/arch/arm/include/asm/fixmap.h
index bbae919bceb4..74124b0d0d79 100644
--- a/arch/arm/include/asm/fixmap.h
+++ b/arch/arm/include/asm/fixmap.h
@@ -1,24 +1,11 @@
 #ifndef _ASM_FIXMAP_H
 #define _ASM_FIXMAP_H
-/*
+#define FIXADDR_START           0xffc00000UL
- * Nothing too fancy for now.
+#define FIXADDR_TOP             0xffe00000UL
- *
- * On ARM we already have well known fixed virtual addresses imposed by
- * the architecture such as the vector page which is located at 0xffff0000,
- * therefore a second level page table is already allocated covering
- * 0xfff00000 upwards.
- *
- * The cache flushing code in proc-xscale.S uses the virtual area between
- * 0xfffe0000 and 0xfffeffff.
- */
-#define FIXADDR_START           0xfff00000UL
-#define FIXADDR_TOP             0xfffe0000UL
 #define FIXADDR_SIZE            (FIXADDR_TOP - FIXADDR_START)
-#define FIX_KMAP_BEGIN          0
+#define FIX_KMAP_NR_PTES        (FIXADDR_SIZE >> PAGE_SHIFT)
-#define FIX_KMAP_END            (FIXADDR_SIZE >> PAGE_SHIFT)
 #define __fix_to_virt(x)        (FIXADDR_START + ((x) << PAGE_SHIFT))
 #define __virt_to_fix(x)        (((x) - FIXADDR_START) >> PAGE_SHIFT)
@@ -27,7 +14,7 @@ extern void __this_fixmap_does_not_exist(void);
 static inline unsigned long fix_to_virt(const unsigned int idx)
 {
-        if (idx >= FIX_KMAP_END)
+        if (idx >= FIX_KMAP_NR_PTES)
                __this_fixmap_does_not_exist();
        return __fix_to_virt(idx);
 }
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index f89515adac60..eb577f4f5f70 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -52,15 +52,7 @@ extern inline void *return_address(unsigned int level)
 #endif
-#define HAVE_ARCH_CALLER_ADDR
+#define ftrace_return_addr(n) return_address(n)
-#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
-#define CALLER_ADDR1 ((unsigned long)return_address(1))
-#define CALLER_ADDR2 ((unsigned long)return_address(2))
-#define CALLER_ADDR3 ((unsigned long)return_address(3))
-#define CALLER_ADDR4 ((unsigned long)return_address(4))
-#define CALLER_ADDR5 ((unsigned long)return_address(5))
-#define CALLER_ADDR6 ((unsigned long)return_address(6))
 #endif /* ifndef __ASSEMBLY__ */
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index c81adc08b3fb..a3c24cd5b7c8 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -130,22 +130,22 @@
 #endif
 #ifndef __ASSEMBLER__
-extern inline void nop_flush_icache_all(void) { }
+static inline void nop_flush_icache_all(void) { }
-extern inline void nop_flush_kern_cache_all(void) { }
+static inline void nop_flush_kern_cache_all(void) { }
-extern inline void nop_flush_kern_cache_louis(void) { }
+static inline void nop_flush_kern_cache_louis(void) { }
-extern inline void nop_flush_user_cache_all(void) { }
+static inline void nop_flush_user_cache_all(void) { }
-extern inline void nop_flush_user_cache_range(unsigned long a,
+static inline void nop_flush_user_cache_range(unsigned long a,
                unsigned long b, unsigned int c) { }
-extern inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
+static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
-extern inline int nop_coherent_user_range(unsigned long a,
+static inline int nop_coherent_user_range(unsigned long a,
                unsigned long b) { return 0; }
-extern inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
+static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
-extern inline void nop_dma_flush_range(const void *a, const void *b) { }
+static inline void nop_dma_flush_range(const void *a, const void *b) { }
-extern inline void nop_dma_map_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
-extern inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
+static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
 #endif
 #ifndef MULTI_CACHE
diff --git a/arch/arm/include/asm/glue-df.h b/arch/arm/include/asm/glue-df.h
index 6b70f1b46a6e..04e18b656659 100644
--- a/arch/arm/include/asm/glue-df.h
+++ b/arch/arm/include/asm/glue-df.h
@@ -31,14 +31,6 @@
 #undef CPU_DABORT_HANDLER
 #undef MULTI_DABORT
-#if defined(CONFIG_CPU_ARM710)
-# ifdef CPU_DABORT_HANDLER
-#  define MULTI_DABORT 1
-# else
-#  define CPU_DABORT_HANDLER cpu_arm7_data_abort
-# endif
-#endif
 #ifdef CONFIG_CPU_ABRT_EV4
 # ifdef CPU_DABORT_HANDLER
 #  define MULTI_DABORT 1
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 6795ff743b3d..3a5ec1c25659 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -26,8 +26,8 @@
 #define L2X0_CACHE_TYPE                 0x004
 #define L2X0_CTRL                       0x100
 #define L2X0_AUX_CTRL                   0x104
-#define L2X0_TAG_LATENCY_CTRL           0x108
+#define L310_TAG_LATENCY_CTRL           0x108
-#define L2X0_DATA_LATENCY_CTRL          0x10C
+#define L310_DATA_LATENCY_CTRL          0x10C
 #define L2X0_EVENT_CNT_CTRL             0x200
 #define L2X0_EVENT_CNT1_CFG             0x204
 #define L2X0_EVENT_CNT0_CFG             0x208
@@ -54,53 +54,93 @@
 #define L2X0_LOCKDOWN_WAY_D_BASE        0x900
 #define L2X0_LOCKDOWN_WAY_I_BASE        0x904
 #define L2X0_LOCKDOWN_STRIDE            0x08
-#define L2X0_ADDR_FILTER_START          0xC00
+#define L310_ADDR_FILTER_START          0xC00
-#define L2X0_ADDR_FILTER_END            0xC04
+#define L310_ADDR_FILTER_END            0xC04
 #define L2X0_TEST_OPERATION             0xF00
 #define L2X0_LINE_DATA                  0xF10
 #define L2X0_LINE_TAG                   0xF30
 #define L2X0_DEBUG_CTRL                 0xF40
-#define L2X0_PREFETCH_CTRL              0xF60
+#define L310_PREFETCH_CTRL              0xF60
-#define L2X0_POWER_CTRL                 0xF80
+#define L310_POWER_CTRL                 0xF80
-#define   L2X0_DYNAMIC_CLK_GATING_EN    (1 << 1)
+#define   L310_DYNAMIC_CLK_GATING_EN    (1 << 1)
-#define   L2X0_STNDBY_MODE_EN           (1 << 0)
+#define   L310_STNDBY_MODE_EN           (1 << 0)
 /* Registers shifts and masks */
 #define L2X0_CACHE_ID_PART_MASK         (0xf << 6)
 #define L2X0_CACHE_ID_PART_L210         (1 << 6)
+#define L2X0_CACHE_ID_PART_L220         (2 << 6)
 #define L2X0_CACHE_ID_PART_L310         (3 << 6)
 #define L2X0_CACHE_ID_RTL_MASK          0x3f
-#define L2X0_CACHE_ID_RTL_R0P0          0x0
+#define L210_CACHE_ID_RTL_R0P2_02       0x00
-#define L2X0_CACHE_ID_RTL_R1P0          0x2
+#define L210_CACHE_ID_RTL_R0P1          0x01
-#define L2X0_CACHE_ID_RTL_R2P0          0x4
+#define L210_CACHE_ID_RTL_R0P2_01       0x02
-#define L2X0_CACHE_ID_RTL_R3P0          0x5
+#define L210_CACHE_ID_RTL_R0P3          0x03
-#define L2X0_CACHE_ID_RTL_R3P1          0x6
+#define L210_CACHE_ID_RTL_R0P4          0x0b
-#define L2X0_CACHE_ID_RTL_R3P2          0x8
+#define L210_CACHE_ID_RTL_R0P5          0x0f
+#define L220_CACHE_ID_RTL_R1P7_01REL0   0x06
+#define L310_CACHE_ID_RTL_R0P0          0x00
+#define L310_CACHE_ID_RTL_R1P0          0x02
+#define L310_CACHE_ID_RTL_R2P0          0x04
+#define L310_CACHE_ID_RTL_R3P0          0x05
+#define L310_CACHE_ID_RTL_R3P1          0x06
+#define L310_CACHE_ID_RTL_R3P1_50REL0   0x07
+#define L310_CACHE_ID_RTL_R3P2          0x08
+#define L310_CACHE_ID_RTL_R3P3          0x09
-#define L2X0_AUX_CTRL_MASK                      0xc0000fff
+/* L2C auxiliary control register - bits common to L2C-210/220/310 */
+#define L2C_AUX_CTRL_WAY_SIZE_SHIFT             17
+#define L2C_AUX_CTRL_WAY_SIZE_MASK              (7 << 17)
+#define L2C_AUX_CTRL_WAY_SIZE(n)                ((n) << 17)
+#define L2C_AUX_CTRL_EVTMON_ENABLE              BIT(20)
+#define L2C_AUX_CTRL_PARITY_ENABLE              BIT(21)
+#define L2C_AUX_CTRL_SHARED_OVERRIDE            BIT(22)
+/* L2C-210/220 common bits */
 #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT     0
-#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      0x7
+#define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK      (7 << 0)
 #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT     3
-#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (0x7 << 3)
+#define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK      (7 << 3)
 #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT         6
-#define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (0x7 << 6)
+#define L2X0_AUX_CTRL_TAG_LATENCY_MASK          (7 << 6)
 #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT       9
-#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (0x7 << 9)
+#define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK        (7 << 9)
-#define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT       16
+#define L2X0_AUX_CTRL_ASSOC_SHIFT               13
-#define L2X0_AUX_CTRL_WAY_SIZE_SHIFT            17
+#define L2X0_AUX_CTRL_ASSOC_MASK                (15 << 13)
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK             (0x7 << 17)
+/* L2C-210 specific bits */
-#define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT      22
+#define L210_AUX_CTRL_WRAP_DISABLE              BIT(12)
-#define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT         26
+#define L210_AUX_CTRL_WA_OVERRIDE               BIT(23)
-#define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT         27
+#define L210_AUX_CTRL_EXCLUSIVE_ABORT           BIT(24)
-#define L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT       28
+/* L2C-220 specific bits */
-#define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT      29
+#define L220_AUX_CTRL_EXCLUSIVE_CACHE           BIT(12)
-#define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT         30
+#define L220_AUX_CTRL_FWA_SHIFT                 23
+#define L220_AUX_CTRL_FWA_MASK                  (3 << 23)
+#define L220_AUX_CTRL_NS_LOCKDOWN               BIT(26)
+#define L220_AUX_CTRL_NS_INT_CTRL               BIT(27)
+/* L2C-310 specific bits */
+#define L310_AUX_CTRL_FULL_LINE_ZERO            BIT(0)  /* R2P0+ */
+#define L310_AUX_CTRL_HIGHPRIO_SO_DEV           BIT(10) /* R2P0+ */
+#define L310_AUX_CTRL_STORE_LIMITATION          BIT(11) /* R2P0+ */
+#define L310_AUX_CTRL_EXCLUSIVE_CACHE           BIT(12)
+#define L310_AUX_CTRL_ASSOCIATIVITY_16          BIT(16)
+#define L310_AUX_CTRL_CACHE_REPLACE_RR          BIT(25) /* R2P0+ */
+#define L310_AUX_CTRL_NS_LOCKDOWN               BIT(26)
+#define L310_AUX_CTRL_NS_INT_CTRL               BIT(27)
+#define L310_AUX_CTRL_DATA_PREFETCH             BIT(28)
+#define L310_AUX_CTRL_INSTR_PREFETCH            BIT(29)
+#define L310_AUX_CTRL_EARLY_BRESP               BIT(30) /* R2P0+ */
-#define L2X0_LATENCY_CTRL_SETUP_SHIFT   0
+#define L310_LATENCY_CTRL_SETUP(n)              ((n) << 0)
-#define L2X0_LATENCY_CTRL_RD_SHIFT      4
+#define L310_LATENCY_CTRL_RD(n)                 ((n) << 4)
-#define L2X0_LATENCY_CTRL_WR_SHIFT      8
+#define L310_LATENCY_CTRL_WR(n)                 ((n) << 8)
-#define L2X0_ADDR_FILTER_EN             1
+#define L310_ADDR_FILTER_EN             1
+#define L310_PREFETCH_CTRL_OFFSET_MASK          0x1f
+#define L310_PREFETCH_CTRL_DBL_LINEFILL_INCR    BIT(23)
+#define L310_PREFETCH_CTRL_PREFETCH_DROP        BIT(24)
+#define L310_PREFETCH_CTRL_DBL_LINEFILL_WRAP    BIT(27)
+#define L310_PREFETCH_CTRL_DATA_PREFETCH        BIT(28)
+#define L310_PREFETCH_CTRL_INSTR_PREFETCH       BIT(29)
+#define L310_PREFETCH_CTRL_DBL_LINEFILL         BIT(30)
 #define L2X0_CTRL_EN                    1
diff --git a/arch/arm/include/asm/highmem.h b/arch/arm/include/asm/highmem.h
index 91b99abe7a95..535579511ed0 100644
--- a/arch/arm/include/asm/highmem.h
+++ b/arch/arm/include/asm/highmem.h
@@ -18,6 +18,7 @@
        } while (0)
 extern pte_t *pkmap_page_table;
+extern pte_t *fixmap_page_table;
 extern void *kmap_high(struct page *page);
 extern void kunmap_high(struct page *page);
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 8aa4cca74501..3d23418cbddd 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -179,6 +179,12 @@ static inline void __iomem *__typesafe_io(unsigned long addr)
 /* PCI fixed i/o mapping */
 #define PCI_IO_VIRT_BASE        0xfee00000
+#if defined(CONFIG_PCI)
+void pci_ioremap_set_mem_type(int mem_type);
+#else
+static inline void pci_ioremap_set_mem_type(int mem_type) {}
+#endif
 extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
 /*
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 09af14999c9b..193ceaf01bfd 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -36,7 +36,7 @@
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 #define KVM_HAVE_ONE_REG
-#define KVM_VCPU_MAX_FEATURES 1
+#define KVM_VCPU_MAX_FEATURES 2
 #include <kvm/arm_vgic.h>
diff --git a/arch/arm/include/asm/kvm_psci.h b/arch/arm/include/asm/kvm_psci.h
index 9a83d98bf170..6bda945d31fa 100644
--- a/arch/arm/include/asm/kvm_psci.h
+++ b/arch/arm/include/asm/kvm_psci.h
@@ -18,6 +18,10 @@
 #ifndef __ARM_KVM_PSCI_H__
 #define __ARM_KVM_PSCI_H__
-bool kvm_psci_call(struct kvm_vcpu *vcpu);
+#define KVM_ARM_PSCI_0_1        1
+#define KVM_ARM_PSCI_0_2        2
+int kvm_psci_version(struct kvm_vcpu *vcpu);
+int kvm_psci_call(struct kvm_vcpu *vcpu);
 #endif /* __ARM_KVM_PSCI_H__ */
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 17a3fa2979e8..060a75e99263 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -14,7 +14,6 @@
 #include <linux/reboot.h>
 struct tag;
-struct meminfo;
 struct pt_regs;
 struct smp_operations;
 #ifdef CONFIG_SMP
@@ -45,10 +44,12 @@ struct machine_desc {
        unsigned char           reserve_lp1 :1; /* never has lp1        */
        unsigned char           reserve_lp2 :1; /* never has lp2        */
        enum reboot_mode        reboot_mode;    /* default restart mode */
+        unsigned                l2c_aux_val;    /* L2 cache aux value   */
+        unsigned                l2c_aux_mask;   /* L2 cache aux mask    */
+        void                    (*l2c_write_sec)(unsigned long, unsigned);
        struct smp_operations   *smp;           /* SMP operations       */
        bool                    (*smp_init)(void);
-        void                    (*fixup)(struct tag *, char **,
+        void                    (*fixup)(struct tag *, char **);
-                                         struct meminfo *);
        void                    (*init_meminfo)(void);
        void                    (*reserve)(void);/* reserve mem blocks  */
        void                    (*map_io)(void);/* IO mapping function  */
diff --git a/arch/arm/include/asm/mcpm.h b/arch/arm/include/asm/mcpm.h
index a5ff410dcdb6..d9702eb0b02b 100644
--- a/arch/arm/include/asm/mcpm.h
+++ b/arch/arm/include/asm/mcpm.h
@@ -98,14 +98,14 @@ int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
 * previously in which case the caller should take appropriate action.
 *
 * On success, the CPU is not guaranteed to be truly halted until
- * mcpm_cpu_power_down_finish() subsequently returns non-zero for the
+ * mcpm_wait_for_cpu_powerdown() subsequently returns non-zero for the
 * specified cpu.  Until then, other CPUs should make sure they do not
 * trash memory the target CPU might be executing/accessing.
 */
 void mcpm_cpu_power_down(void);
 /**
- * mcpm_cpu_power_down_finish - wait for a specified CPU to halt, and
+ * mcpm_wait_for_cpu_powerdown - wait for a specified CPU to halt, and
 *      make sure it is powered off
 *
 * @cpu: CPU number within given cluster
@@ -127,7 +127,7 @@ void mcpm_cpu_power_down(void);
 *      - zero if the CPU is in a safely parked state
 *      - nonzero otherwise (e.g., timeout)
 */
-int mcpm_cpu_power_down_finish(unsigned int cpu, unsigned int cluster);
+int mcpm_wait_for_cpu_powerdown(unsigned int cpu, unsigned int cluster);
 /**
 * mcpm_cpu_suspend - bring the calling CPU in a suspended state
@@ -171,7 +171,7 @@ int mcpm_cpu_powered_up(void);
 struct mcpm_platform_ops {
        int (*power_up)(unsigned int cpu, unsigned int cluster);
        void (*power_down)(void);
-        int (*power_down_finish)(unsigned int cpu, unsigned int cluster);
+        int (*wait_for_powerdown)(unsigned int cpu, unsigned int cluster);
        void (*suspend)(u64);
        void (*powered_up)(void);
 };
diff --git a/arch/arm/include/asm/memblock.h b/arch/arm/include/asm/memblock.h
index c2f5102ae659..bf47a6c110a2 100644
--- a/arch/arm/include/asm/memblock.h
+++ b/arch/arm/include/asm/memblock.h
@@ -1,10 +1,9 @@
 #ifndef _ASM_ARM_MEMBLOCK_H
 #define _ASM_ARM_MEMBLOCK_H
-struct meminfo;
 struct machine_desc;
-void arm_memblock_init(struct meminfo *, const struct machine_desc *);
+void arm_memblock_init(const struct machine_desc *);
 phys_addr_t arm_memblock_steal(phys_addr_t size, phys_addr_t align);
 #endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 02fa2558f662..2b751464d6ff 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -83,8 +83,6 @@
 */
 #define IOREMAP_MAX_ORDER       24
-#define CONSISTENT_END          (0xffe00000UL)
 #else /* CONFIG_MMU */
 /*
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index f94784f0e3a6..891a56b35bcf 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -28,53 +28,84 @@ struct outer_cache_fns {
        void (*clean_range)(unsigned long, unsigned long);
        void (*flush_range)(unsigned long, unsigned long);
        void (*flush_all)(void);
-        void (*inv_all)(void);
        void (*disable)(void);
 #ifdef CONFIG_OUTER_CACHE_SYNC
        void (*sync)(void);
 #endif
-        void (*set_debug)(unsigned long);
        void (*resume)(void);
+        /* This is an ARM L2C thing */
+        void (*write_sec)(unsigned long, unsigned);
 };
 extern struct outer_cache_fns outer_cache;
 #ifdef CONFIG_OUTER_CACHE
+/**
+ * outer_inv_range - invalidate range of outer cache lines
+ * @start: starting physical address, inclusive
+ * @end: end physical address, exclusive
+ */
 static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
 {
        if (outer_cache.inv_range)
                outer_cache.inv_range(start, end);
 }
+/**
+ * outer_clean_range - clean dirty outer cache lines
+ * @start: starting physical address, inclusive
+ * @end: end physical address, exclusive
+ */
 static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
 {
        if (outer_cache.clean_range)
                outer_cache.clean_range(start, end);
 }
+/**
+ * outer_flush_range - clean and invalidate outer cache lines
+ * @start: starting physical address, inclusive
+ * @end: end physical address, exclusive
+ */
 static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
 {
        if (outer_cache.flush_range)
                outer_cache.flush_range(start, end);
 }
+/**
+ * outer_flush_all - clean and invalidate all cache lines in the outer cache
+ *
+ * Note: depending on implementation, this may not be atomic - it must
+ * only be called with interrupts disabled and no other active outer
+ * cache masters.
+ *
+ * It is intended that this function is only used by implementations
+ * needing to override the outer_cache.disable() method due to security.
+ * (Some implementations perform this as a clean followed by an invalidate.)
+ */
 static inline void outer_flush_all(void)
 {
        if (outer_cache.flush_all)
                outer_cache.flush_all();
 }
-static inline void outer_inv_all(void)
+/**
-{
+ * outer_disable - clean, invalidate and disable the outer cache
-        if (outer_cache.inv_all)
+ *
-                outer_cache.inv_all();
+ * Disable the outer cache, ensuring that any data contained in the outer
-}
+ * cache is pushed out to lower levels of system memory.  The note and
+ * conditions above concerning outer_flush_all() applies here.
-static inline void outer_disable(void)
+ */
-{
+extern void outer_disable(void);
-        if (outer_cache.disable)
-                outer_cache.disable();
-}
+/**
+ * outer_resume - restore the cache configuration and re-enable outer cache
+ *
+ * Restore any configuration that the cache had when previously enabled,
+ * and re-enable the outer cache.
+ */
 static inline void outer_resume(void)
 {
        if (outer_cache.resume)
@@ -90,13 +121,18 @@ static inline void outer_clean_range(phys_addr_t start, phys_addr_t end)
 static inline void outer_flush_range(phys_addr_t start, phys_addr_t end)
 { }
 static inline void outer_flush_all(void) { }
-static inline void outer_inv_all(void) { }
 static inline void outer_disable(void) { }
 static inline void outer_resume(void) { }
 #endif
 #ifdef CONFIG_OUTER_CACHE_SYNC
+/**
+ * outer_sync - perform a sync point for outer cache
+ *
+ * Ensure that all outer cache operations are complete and any store
+ * buffers are drained.
+ */
 static inline void outer_sync(void)
 {
        if (outer_cache.sync)
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 680a83e94467..7e95d8535e24 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -31,11 +31,6 @@ static inline int pci_proc_domain(struct pci_bus *bus)
 }
 #endif /* CONFIG_PCI_DOMAINS */
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
 /*
 * The PCI address space does equal the physical memory address space.
 * The networking and block device layers use this boolean for bounce
diff --git a/arch/arm/include/asm/prom.h b/arch/arm/include/asm/prom.h
index b681575ad3de..cd94ef2ef283 100644
--- a/arch/arm/include/asm/prom.h
+++ b/arch/arm/include/asm/prom.h
@@ -14,7 +14,6 @@
 #ifdef CONFIG_OF
 extern const struct machine_desc *setup_machine_fdt(unsigned int dt_phys);
-extern void arm_dt_memblock_reserve(void);
 extern void __init arm_dt_init_cpu_maps(void);
 #else /* CONFIG_OF */
@@ -24,7 +23,6 @@ static inline const struct machine_desc *setup_machine_fdt(unsigned int dt_phys)
        return NULL;
 }
-static inline void arm_dt_memblock_reserve(void) { }
 static inline void arm_dt_init_cpu_maps(void) { }
 #endif /* CONFIG_OF */
diff --git a/arch/arm/include/asm/psci.h b/arch/arm/include/asm/psci.h
index c4ae171850f8..c25ef3ec6d1f 100644
--- a/arch/arm/include/asm/psci.h
+++ b/arch/arm/include/asm/psci.h
@@ -29,16 +29,19 @@ struct psci_operations {
        int (*cpu_off)(struct psci_power_state state);
        int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
        int (*migrate)(unsigned long cpuid);
+        int (*affinity_info)(unsigned long target_affinity,
+                        unsigned long lowest_affinity_level);
+        int (*migrate_info_type)(void);
 };
 extern struct psci_operations psci_ops;
 extern struct smp_operations psci_smp_ops;
 #ifdef CONFIG_ARM_PSCI
-void psci_init(void);
+int psci_init(void);
 bool psci_smp_available(void);
 #else
-static inline void psci_init(void) { }
+static inline int psci_init(void) { return 0; }
 static inline bool psci_smp_available(void) { return false; }
 #endif
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 8d6a089dfb76..e0adb9f1bf94 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -21,34 +21,6 @@
 #define __tagtable(tag, fn) \
 static const struct tagtable __tagtable_##fn __tag = { tag, fn }
-/*
- * Memory map description
- */
-#define NR_BANKS        CONFIG_ARM_NR_BANKS
-struct membank {
-        phys_addr_t start;
-        phys_addr_t size;
-        unsigned int highmem;
-};
-struct meminfo {
-        int nr_banks;
-        struct membank bank[NR_BANKS];
-};
-extern struct meminfo meminfo;
-#define for_each_bank(iter,mi)                          \
-        for (iter = 0; iter < (mi)->nr_banks; iter++)
-#define bank_pfn_start(bank)    __phys_to_pfn((bank)->start)
-#define bank_pfn_end(bank)      __phys_to_pfn((bank)->start + (bank)->size)
-#define bank_pfn_size(bank)     ((bank)->size >> PAGE_SHIFT)
-#define bank_phys_start(bank)   (bank)->start
-#define bank_phys_end(bank)     ((bank)->start + (bank)->size)
-#define bank_phys_size(bank)    (bank)->size
 extern int arm_add_memory(u64 start, u64 size);
 extern void early_print(const char *str, ...);
 extern void dump_machine_table(void);
diff --git a/arch/arm/include/asm/trusted_foundations.h b/arch/arm/include/asm/trusted_foundations.h
index b5f7705abcb0..624e1d436c6c 100644
--- a/arch/arm/include/asm/trusted_foundations.h
+++ b/arch/arm/include/asm/trusted_foundations.h
@@ -54,7 +54,9 @@ static inline void register_trusted_foundations(
         */
        pr_err("No support for Trusted Foundations, continuing in degraded mode.\n");
        pr_err("Secondary processors as well as CPU PM will be disabled.\n");
+#if IS_ENABLED(CONFIG_SMP)
        setup_max_cpus = 0;
+#endif
        cpu_idle_poll_ctrl(true);
 }
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 12c3a5decc60..75d95799b6e6 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -171,8 +171,9 @@ extern int __put_user_8(void *, unsigned long long);
 #define __put_user_check(x,p)                                                   \
        ({                                                              \
                unsigned long __limit = current_thread_info()->addr_limit - 1; \
+                const typeof(*(p)) __user *__tmp_p = (p);               \
                register const typeof(*(p)) __r2 asm("r2") = (x);       \
-                register const typeof(*(p)) __user *__p asm("r0") = (p);\
+                register const typeof(*(p)) __user *__p asm("r0") = __tmp_p; \
                register unsigned long __l asm("r1") = __limit;         \
                register int __e asm("r0");                             \
                switch (sizeof(*(__p))) {                               \
diff --git a/arch/arm/include/asm/xen/hypercall.h b/arch/arm/include/asm/xen/hypercall.h
index 7704e28c3483..712b50e0a6dc 100644
--- a/arch/arm/include/asm/xen/hypercall.h
+++ b/arch/arm/include/asm/xen/hypercall.h
@@ -34,6 +34,7 @@
 #define _ASM_ARM_XEN_HYPERCALL_H
 #include <xen/interface/xen.h>
+#include <xen/interface/sched.h>
 long privcmd_call(unsigned call, unsigned long a1,
                unsigned long a2, unsigned long a3,
@@ -48,6 +49,16 @@ int HYPERVISOR_memory_op(unsigned int cmd, void *arg);
 int HYPERVISOR_physdev_op(int cmd, void *arg);
 int HYPERVISOR_vcpu_op(int cmd, int vcpuid, void *extra_args);
 int HYPERVISOR_tmem_op(void *arg);
+int HYPERVISOR_multicall(struct multicall_entry *calls, uint32_t nr);
+static inline int
+HYPERVISOR_suspend(unsigned long start_info_mfn)
+{
+        struct sched_shutdown r = { .reason = SHUTDOWN_suspend };
+        /* start_info_mfn is unused on ARM */
+        return HYPERVISOR_sched_op(SCHEDOP_shutdown, &r);
+}
 static inline void
 MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
@@ -63,9 +74,4 @@ MULTI_mmu_update(struct multicall_entry *mcl, struct mmu_update *req,
        BUG();
 }
-static inline int
-HYPERVISOR_multicall(void *call_list, int nr_calls)
-{
-        BUG();
-}
 #endif /* _ASM_ARM_XEN_HYPERCALL_H */
diff --git a/arch/arm/include/asm/xen/interface.h b/arch/arm/include/asm/xen/interface.h
index 1151188bcd83..50066006e6bd 100644
--- a/arch/arm/include/asm/xen/interface.h
+++ b/arch/arm/include/asm/xen/interface.h
@@ -40,6 +40,8 @@ typedef uint64_t xen_pfn_t;
 #define PRI_xen_pfn "llx"
 typedef uint64_t xen_ulong_t;
 #define PRI_xen_ulong "llx"
+typedef int64_t xen_long_t;
+#define PRI_xen_long "llx"
 /* Guest handles for primitive C types. */
 __DEFINE_GUEST_HANDLE(uchar, unsigned char);
 __DEFINE_GUEST_HANDLE(uint,  unsigned int);
diff --git a/arch/arm/include/asm/xen/page.h b/arch/arm/include/asm/xen/page.h
index cf4f3e867395..ded062f9b358 100644
--- a/arch/arm/include/asm/xen/page.h
+++ b/arch/arm/include/asm/xen/page.h
@@ -77,7 +77,6 @@ static inline xpaddr_t machine_to_phys(xmaddr_t machine)
 }
 /* VIRT <-> MACHINE conversion */
 #define virt_to_machine(v)      (phys_to_machine(XPADDR(__pa(v))))
-#define virt_to_pfn(v)          (PFN_DOWN(__pa(v)))
 #define virt_to_mfn(v)          (pfn_to_mfn(virt_to_pfn(v)))
 #define mfn_to_virt(m)          (__va(mfn_to_pfn(m) << PAGE_SHIFT))
diff --git a/arch/arm/include/debug/imx-uart.h b/arch/arm/include/debug/imx-uart.h
index 42b823cd2d22..032a316eb802 100644
--- a/arch/arm/include/debug/imx-uart.h
+++ b/arch/arm/include/debug/imx-uart.h
@@ -81,6 +81,15 @@
 #define IMX6SL_UART_BASE_ADDR(n) IMX6SL_UART##n##_BASE_ADDR
 #define IMX6SL_UART_BASE(n)     IMX6SL_UART_BASE_ADDR(n)
+#define IMX6SX_UART1_BASE_ADDR  0x02020000
+#define IMX6SX_UART2_BASE_ADDR  0x021e8000
+#define IMX6SX_UART3_BASE_ADDR  0x021ec000
+#define IMX6SX_UART4_BASE_ADDR  0x021f0000
+#define IMX6SX_UART5_BASE_ADDR  0x021f4000
+#define IMX6SX_UART6_BASE_ADDR  0x022a0000
+#define IMX6SX_UART_BASE_ADDR(n) IMX6SX_UART##n##_BASE_ADDR
+#define IMX6SX_UART_BASE(n)     IMX6SX_UART_BASE_ADDR(n)
 #define IMX_DEBUG_UART_BASE(soc) soc##_UART_BASE(CONFIG_DEBUG_IMX_UART_PORT)
 #ifdef CONFIG_DEBUG_IMX1_UART
@@ -103,6 +112,8 @@
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6Q)
 #elif defined(CONFIG_DEBUG_IMX6SL_UART)
 #define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6SL)
+#elif defined(CONFIG_DEBUG_IMX6SX_UART)
+#define UART_PADDR      IMX_DEBUG_UART_BASE(IMX6SX)
 #endif
 #endif /* __DEBUG_IMX_UART_H */
diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
index 9d653d475903..9ef57612811d 100644
--- a/arch/arm/include/debug/msm.S
+++ b/arch/arm/include/debug/msm.S
@@ -15,51 +15,15 @@
 *
 */
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
-#define MSM_UART1_PHYS        0xA9A00000
-#define MSM_UART2_PHYS        0xA9B00000
-#define MSM_UART3_PHYS        0xA9C00000
-#elif defined(CONFIG_ARCH_MSM7X30)
-#define MSM_UART1_PHYS        0xACA00000
-#define MSM_UART2_PHYS        0xACB00000
-#define MSM_UART3_PHYS        0xACC00000
-#endif
-#if defined(CONFIG_DEBUG_MSM_UART1)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART1_PHYS
-#elif defined(CONFIG_DEBUG_MSM_UART2)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART2_PHYS
-#elif defined(CONFIG_DEBUG_MSM_UART3)
-#define MSM_DEBUG_UART_BASE     0xE1000000
-#define MSM_DEBUG_UART_PHYS     MSM_UART3_PHYS
-#endif
-#ifdef CONFIG_DEBUG_MSM8660_UART
-#define MSM_DEBUG_UART_BASE     0xF0040000
-#define MSM_DEBUG_UART_PHYS     0x19C40000
-#endif
-#ifdef CONFIG_DEBUG_MSM8960_UART
-#define MSM_DEBUG_UART_BASE     0xF0040000
-#define MSM_DEBUG_UART_PHYS     0x16440000
-#endif
-#ifdef CONFIG_DEBUG_MSM8974_UART
-#define MSM_DEBUG_UART_BASE     0xFA71E000
-#define MSM_DEBUG_UART_PHYS     0xF991E000
-#endif
        .macro  addruart, rp, rv, tmp
-#ifdef MSM_DEBUG_UART_PHYS
+#ifdef CONFIG_DEBUG_UART_PHYS
-        ldr     \rp, =MSM_DEBUG_UART_PHYS
+        ldr     \rp, =CONFIG_DEBUG_UART_PHYS
-        ldr     \rv, =MSM_DEBUG_UART_BASE
+        ldr     \rv, =CONFIG_DEBUG_UART_VIRT
 #endif
        .endm
        .macro  senduart, rd, rx
-#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+#ifdef CONFIG_DEBUG_QCOM_UARTDM
        @ Write the 1 character to UARTDM_TF
        str     \rd, [\rx, #0x70]
 #else
@@ -68,7 +32,7 @@
        .endm
        .macro  waituart, rd, rx
-#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
+#ifdef CONFIG_DEBUG_QCOM_UARTDM
        @ check for TX_EMT in UARTDM_SR
        ldr     \rd, [\rx, #0x08]
        tst     \rd, #0x08
diff --git a/arch/arm/include/debug/s3c24xx.S b/arch/arm/include/debug/s3c24xx.S
new file mode 100644
index 000000000000..b1f54dc4888c
--- /dev/null
+++ b/arch/arm/include/debug/s3c24xx.S
@@ -0,0 +1,46 @@
+/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Copyright (C) 2005 Simtec Electronics
+ *
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/serial_s3c.h>
+#define S3C2410_UART1_OFF (0x4000)
+        .macro addruart, rp, rv, tmp
+                ldr     \rp, = CONFIG_DEBUG_UART_PHYS
+                ldr     \rv, = CONFIG_DEBUG_UART_VIRT
+        .endm
+        .macro  fifo_full_s3c2410 rd, rx
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
+        .macro fifo_level_s3c2410 rd, rx
+                ldr     \rd, [\rx, # S3C2410_UFSTAT]
+                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
+        .endm
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+#if defined(CONFIG_DEBUG_S3C2410_UART)
+#define fifo_full  fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#endif
+/* include the reset of the code which will do the work */
+#include <debug/samsung.S>
diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
index ba12cc44b2cb..b88933849a17 100644
--- a/arch/arm/include/debug/vf.S
+++ b/arch/arm/include/debug/vf.S
@@ -7,9 +7,20 @@
 *
 */
+#define VF_UART0_BASE_ADDR      0x40027000
+#define VF_UART1_BASE_ADDR      0x40028000
+#define VF_UART2_BASE_ADDR      0x40029000
+#define VF_UART3_BASE_ADDR      0x4002a000
+#define VF_UART_BASE_ADDR(n)    VF_UART##n##_BASE_ADDR
+#define VF_UART_BASE(n)         VF_UART_BASE_ADDR(n)
+#define VF_UART_PHYSICAL_BASE   VF_UART_BASE(CONFIG_DEBUG_VF_UART_PORT)
+#define VF_UART_VIRTUAL_BASE    0xfe000000
        .macro  addruart, rp, rv, tmp
-        ldr     \rp, =0x40028000        @ physical
+        ldr     \rp, =VF_UART_PHYSICAL_BASE     @ physical
-        ldr     \rv, =0xfe028000        @ virtual
+        and     \rv, \rp, #0xffffff             @ offset within 16MB section
+        add     \rv, \rv, #VF_UART_VIRTUAL_BASE
        .endm
        .macro  senduart, rd, rx
diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index 0b762fafa758..bd13dedbdeff 100644
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -20,18 +20,18 @@
 #define UART_SR_TXEMPTY         0x00000008      /* TX FIFO empty */
 #define UART0_PHYS              0xE0000000
+#define UART0_VIRT              0xF0000000
 #define UART1_PHYS              0xE0001000
-#define UART_SIZE               SZ_4K
+#define UART1_VIRT              0xF0001000
-#define UART_VIRT               0xF0001000
 #if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
 # define LL_UART_PADDR          UART1_PHYS
+# define LL_UART_VADDR          UART1_VIRT
 #else
 # define LL_UART_PADDR          UART0_PHYS
+# define LL_UART_VADDR          UART0_VIRT
 #endif
-#define LL_UART_VADDR           UART_VIRT
                .macro  addruart, rp, rv, tmp
                ldr     \rp, =LL_UART_PADDR     @ physical
                ldr     \rv, =LL_UART_VADDR     @ virtual
@@ -43,12 +43,14 @@
                .macro  waituart,rd,rx
 1001:           ldr     \rd, [\rx, #UART_SR_OFFSET]
+ARM_BE8(        rev     \rd, \rd )
                tst     \rd, #UART_SR_TXEMPTY
                beq     1001b
                .endm
                .macro  busyuart,rd,rx
 1002:           ldr     \rd, [\rx, #UART_SR_OFFSET]     @ get status register
+ARM_BE8(        rev     \rd, \rd )
                tst     \rd, #UART_SR_TXFULL            @
                bne     1002b                   @ wait if FIFO is full
                .endm
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index ef0c8785ba16..e6ebdd3471e5 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -20,6 +20,7 @@
 #define __ARM_KVM_H__
 #include <linux/types.h>
+#include <linux/psci.h>
 #include <asm/ptrace.h>
 #define __KVM_HAVE_GUEST_DEBUG
@@ -83,6 +84,7 @@ struct kvm_regs {
 #define KVM_VGIC_V2_CPU_SIZE            0x2000
 #define KVM_ARM_VCPU_POWER_OFF          0 /* CPU is started in OFF state */
+#define KVM_ARM_VCPU_PSCI_0_2           1 /* CPU uses PSCI v0.2 */
 struct kvm_vcpu_init {
        __u32 target;
@@ -201,9 +203,9 @@ struct kvm_arch_memory_slot {
 #define KVM_PSCI_FN_CPU_ON              KVM_PSCI_FN(2)
 #define KVM_PSCI_FN_MIGRATE             KVM_PSCI_FN(3)
-#define KVM_PSCI_RET_SUCCESS            0
+#define KVM_PSCI_RET_SUCCESS            PSCI_RET_SUCCESS
-#define KVM_PSCI_RET_NI                 ((unsigned long)-1)
+#define KVM_PSCI_RET_NI                 PSCI_RET_NOT_SUPPORTED
-#define KVM_PSCI_RET_INVAL              ((unsigned long)-2)
+#define KVM_PSCI_RET_INVAL              PSCI_RET_INVALID_PARAMS
-#define KVM_PSCI_RET_DENIED             ((unsigned long)-3)
+#define KVM_PSCI_RET_DENIED             PSCI_RET_DENIED
 #endif /* __ARM_KVM_H__ */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 040619c32d68..38ddd9f83d0e 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_ARTHUR)		+= arthur.o
 obj-$(CONFIG_ISA_DMA)           += dma-isa.o
 obj-$(CONFIG_PCI)               += bios32.o isa.o
 obj-$(CONFIG_ARM_CPU_SUSPEND)   += sleep.o suspend.o
+obj-$(CONFIG_HIBERNATION)       += hibernate.o
 obj-$(CONFIG_SMP)               += smp.o
 ifdef CONFIG_MMU
 obj-$(CONFIG_SMP)               += smp_tlb.o
diff --git a/arch/arm/kernel/atags_parse.c b/arch/arm/kernel/atags_parse.c
index 8c14de8180c0..7807ef58a2ab 100644
--- a/arch/arm/kernel/atags_parse.c
+++ b/arch/arm/kernel/atags_parse.c
@@ -22,6 +22,7 @@
 #include <linux/fs.h>
 #include <linux/root_dev.h>
 #include <linux/screen_info.h>
+#include <linux/memblock.h>
 #include <asm/setup.h>
 #include <asm/system_info.h>
@@ -222,10 +223,10 @@ setup_machine_tags(phys_addr_t __atags_pointer, unsigned int machine_nr)
        }
        if (mdesc->fixup)
-                mdesc->fixup(tags, &from, &meminfo);
+                mdesc->fixup(tags, &from);
        if (tags->hdr.tag == ATAG_CORE) {
-                if (meminfo.nr_banks != 0)
+                if (memblock_phys_mem_size())
                        squash_mem_tags(tags);
                save_atags(tags);
                parse_tags(tags);
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 16d43cd45619..17a26c17f7f5 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -545,6 +545,18 @@ void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
                 */
                pci_bus_add_devices(bus);
        }
+        list_for_each_entry(sys, &head, node) {
+                struct pci_bus *bus = sys->bus;
+                /* Configure PCI Express settings */
+                if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
+                        struct pci_bus *child;
+                        list_for_each_entry(child, &bus->children, node)
+                                pcie_bus_configure_settings(child);
+                }
+        }
 }
 #ifndef CONFIG_PCI_HOST_ITE8152
diff --git a/arch/arm/kernel/devtree.c b/arch/arm/kernel/devtree.c
index c7419a585ddc..e94a157ddff1 100644
--- a/arch/arm/kernel/devtree.c
+++ b/arch/arm/kernel/devtree.c
@@ -27,56 +27,23 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
-void __init early_init_dt_add_memory_arch(u64 base, u64 size)
-{
-        arm_add_memory(base, size);
-}
-void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
-{
-        return memblock_virt_alloc(size, align);
-}
-void __init arm_dt_memblock_reserve(void)
-{
-        u64 *reserve_map, base, size;
-        if (!initial_boot_params)
-                return;
-        /* Reserve the dtb region */
+#ifdef CONFIG_SMP
-        memblock_reserve(virt_to_phys(initial_boot_params),
+extern struct of_cpu_method __cpu_method_of_table[];
-                         be32_to_cpu(initial_boot_params->totalsize));
-        /*
+static const struct of_cpu_method __cpu_method_of_table_sentinel
-         * Process the reserve map.  This will probably overlap the initrd
+        __used __section(__cpu_method_of_table_end);
-         * and dtb locations which are already reserved, but overlaping
-         * doesn't hurt anything
-         */
-        reserve_map = ((void*)initial_boot_params) +
-                        be32_to_cpu(initial_boot_params->off_mem_rsvmap);
-        while (1) {
-                base = be64_to_cpup(reserve_map++);
-                size = be64_to_cpup(reserve_map++);
-                if (!size)
-                        break;
-                memblock_reserve(base, size);
-        }
-}
-#ifdef CONFIG_SMP
-extern struct of_cpu_method __cpu_method_of_table_begin[];
-extern struct of_cpu_method __cpu_method_of_table_end[];
 static int __init set_smp_ops_by_method(struct device_node *node)
 {
        const char *method;
-        struct of_cpu_method *m = __cpu_method_of_table_begin;
+        struct of_cpu_method *m = __cpu_method_of_table;
        if (of_property_read_string(node, "enable-method", &method))
                return 0;
-        for (; m < __cpu_method_of_table_end; m++)
+        for (; m->method; m++)
                if (!strcmp(m->method, method)) {
                        smp_set_ops(m->ops);
                        return 1;
@@ -252,7 +219,7 @@ const struct machine_desc * __init setup_machine_fdt(unsigned int dt_phys)
        if (!mdesc) {
                const char *prop;
-                long size;
+                int size;
                unsigned long dt_root;
                early_print("\nError: unrecognized/unsupported "
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 1879e8dd2acc..52a949a8077d 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -344,7 +344,7 @@ ENDPROC(__pabt_svc)
        @
        @ Enable the alignment trap while in kernel mode
        @
-        alignment_trap r0
+        alignment_trap r0, .LCcralign
        @
        @ Clear FP to mark the first stack frame
@@ -413,6 +413,11 @@ __und_usr:
        @
        adr     r9, BSYM(ret_from_exception)
+        @ IRQs must be enabled before attempting to read the instruction from
+        @ user space since that could cause a page/translation fault if the
+        @ page table was modified by another CPU.
+        enable_irq
        tst     r3, #PSR_T_BIT                  @ Thumb mode?
        bne     __und_usr_thumb
        sub     r4, r2, #4                      @ ARM instr at LR - 4
@@ -484,7 +489,8 @@ ENDPROC(__und_usr)
 */
        .pushsection .fixup, "ax"
        .align  2
-4:      mov     pc, r9
+4:      str     r4, [sp, #S_PC]                 @ retry current instruction
+        mov     pc, r9
        .popsection
        .pushsection __ex_table,"a"
        .long   1b, 4b
@@ -517,7 +523,7 @@ ENDPROC(__und_usr)
 *  r9  = normal "successful" return address
 *  r10 = this threads thread_info structure
 *  lr  = unrecognised instruction return address
- * IRQs disabled, FIQs enabled.
+ * IRQs enabled, FIQs enabled.
 */
        @
        @ Fall-through from Thumb-2 __und_usr
@@ -624,7 +630,6 @@ call_fpe:
 #endif
 do_fpe:
-        enable_irq
        ldr     r4, .LCfp
        add     r10, r10, #TI_FPSTATE           @ r10 = workspace
        ldr     pc, [r4]                        @ Call FP module USR entry point
@@ -652,8 +657,7 @@ __und_usr_fault_32:
        b       1f
 __und_usr_fault_16:
        mov     r1, #2
-1:      enable_irq
+1:      mov     r0, sp
-        mov     r0, sp
        adr     lr, BSYM(ret_from_exception)
        b       __und_fault
 ENDPROC(__und_usr_fault_32)
@@ -1143,11 +1147,8 @@ __vectors_start:
        .data
        .globl  cr_alignment
-        .globl  cr_no_alignment
 cr_alignment:
        .space  4
-cr_no_alignment:
-        .space  4
 #ifdef CONFIG_MULTI_IRQ_HANDLER
        .globl  handle_arch_irq
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index a2dcafdf1bc8..7139d4a7dea7 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -365,13 +365,7 @@ ENTRY(vector_swi)
        str     r0, [sp, #S_OLD_R0]             @ Save OLD_R0
 #endif
        zero_fp
+        alignment_trap ip, __cr_alignment
-#ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     ip, __cr_alignment
-        ldr     ip, [ip]
-        mcr     p15, 0, ip, c1, c0              @ update control register
-#endif
        enable_irq
        ct_user_exit
        get_thread_info tsk
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 1420725142ca..5d702f8900b1 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -37,9 +37,9 @@
 #endif
        .endm
-        .macro  alignment_trap, rtemp
+        .macro  alignment_trap, rtemp, label
 #ifdef CONFIG_ALIGNMENT_TRAP
-        ldr     \rtemp, .LCcralign
+        ldr     \rtemp, \label
        ldr     \rtemp, [\rtemp]
        mcr     p15, 0, \rtemp, c1, c0
 #endif
@@ -132,6 +132,10 @@
        orrne   r5, V7M_xPSR_FRAMEPTRALIGN
        biceq   r5, V7M_xPSR_FRAMEPTRALIGN
+        @ ensure bit 0 is cleared in the PC, otherwise behaviour is
+        @ unpredictable
+        bic     r4, #1
        @ write basic exception frame
        stmdb   r2!, {r1, r3-r5}
        ldmia   sp, {r1, r3-r5}
diff --git a/arch/arm/kernel/ftrace.c b/arch/arm/kernel/ftrace.c
index c108ddcb9ba4..af9a8a927a4e 100644
--- a/arch/arm/kernel/ftrace.c
+++ b/arch/arm/kernel/ftrace.c
@@ -14,6 +14,7 @@
 #include <linux/ftrace.h>
 #include <linux/uaccess.h>
+#include <linux/module.h>
 #include <asm/cacheflush.h>
 #include <asm/opcodes.h>
@@ -63,6 +64,18 @@ static unsigned long adjust_address(struct dyn_ftrace *rec, unsigned long addr)
 }
 #endif
+int ftrace_arch_code_modify_prepare(void)
+{
+        set_all_modules_text_rw();
+        return 0;
+}
+int ftrace_arch_code_modify_post_process(void)
+{
+        set_all_modules_text_ro();
+        return 0;
+}
 static unsigned long ftrace_call_replace(unsigned long pc, unsigned long addr)
 {
        return arm_gen_branch_link(pc, addr);
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index c96ecacb2021..572a38335c96 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -99,8 +99,7 @@ __mmap_switched:
        str     r1, [r5]                        @ Save machine type
        str     r2, [r6]                        @ Save atags pointer
        cmp     r7, #0
-        bicne   r4, r0, #CR_A                   @ Clear 'A' bit
+        strne   r0, [r7]                        @ Save control register values
-        stmneia r7, {r0, r4}                    @ Save control register values
        b       start_kernel
 ENDPROC(__mmap_switched)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 591d6e4a6492..2c35f0ff2fdc 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -475,7 +475,7 @@ ENDPROC(__turn_mmu_on)
 #ifdef CONFIG_SMP_ON_UP
-        __INIT
+        __HEAD
 __fixup_smp:
        and     r3, r9, #0x000f0000     @ architecture version
        teq     r3, #0x000f0000         @ CPU ID supported?
diff --git a/arch/arm/kernel/hibernate.c b/arch/arm/kernel/hibernate.c
new file mode 100644
index 000000000000..bb8b79648643
--- /dev/null
+++ b/arch/arm/kernel/hibernate.c
@@ -0,0 +1,107 @@
+/*
+ * Hibernation support specific for ARM
+ *
+ * Derived from work on ARM hibernation support by:
+ *
+ * Ubuntu project, hibernation support for mach-dove
+ * Copyright (C) 2010 Nokia Corporation (Hiroshi Doyu)
+ * Copyright (C) 2010 Texas Instruments, Inc. (Teerth Reddy et al.)
+ *  https://lkml.org/lkml/2010/6/18/4
+ *  https://lists.linux-foundation.org/pipermail/linux-pm/2010-June/027422.html
+ *  https://patchwork.kernel.org/patch/96442/
+ *
+ * Copyright (C) 2006 Rafael J. Wysocki <rjw@sisk.pl>
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+#include <linux/mm.h>
+#include <linux/suspend.h>
+#include <asm/system_misc.h>
+#include <asm/idmap.h>
+#include <asm/suspend.h>
+#include <asm/memory.h>
+extern const void __nosave_begin, __nosave_end;
+int pfn_is_nosave(unsigned long pfn)
+{
+        unsigned long nosave_begin_pfn = virt_to_pfn(&__nosave_begin);
+        unsigned long nosave_end_pfn = virt_to_pfn(&__nosave_end - 1);
+        return (pfn >= nosave_begin_pfn) && (pfn <= nosave_end_pfn);
+}
+void notrace save_processor_state(void)
+{
+        WARN_ON(num_online_cpus() != 1);
+        local_fiq_disable();
+}
+void notrace restore_processor_state(void)
+{
+        local_fiq_enable();
+}
+/*
+ * Snapshot kernel memory and reset the system.
+ *
+ * swsusp_save() is executed in the suspend finisher so that the CPU
+ * context pointer and memory are part of the saved image, which is
+ * required by the resume kernel image to restart execution from
+ * swsusp_arch_suspend().
+ *
+ * soft_restart is not technically needed, but is used to get success
+ * returned from cpu_suspend.
+ *
+ * When soft reboot completes, the hibernation snapshot is written out.
+ */
+static int notrace arch_save_image(unsigned long unused)
+{
+        int ret;
+        ret = swsusp_save();
+        if (ret == 0)
+                soft_restart(virt_to_phys(cpu_resume));
+        return ret;
+}
+/*
+ * Save the current CPU state before suspend / poweroff.
+ */
+int notrace swsusp_arch_suspend(void)
+{
+        return cpu_suspend(0, arch_save_image);
+}
+/*
+ * Restore page contents for physical pages that were in use during loading
+ * hibernation image.  Switch to idmap_pgd so the physical page tables
+ * are overwritten with the same contents.
+ */
+static void notrace arch_restore_image(void *unused)
+{
+        struct pbe *pbe;
+        cpu_switch_mm(idmap_pgd, &init_mm);
+        for (pbe = restore_pblist; pbe; pbe = pbe->next)
+                copy_page(pbe->orig_address, pbe->address);
+        soft_restart(virt_to_phys(cpu_resume));
+}
+static u64 resume_stack[PAGE_SIZE/2/sizeof(u64)] __nosavedata;
+/*
+ * Resume from the hibernation image.
+ * Due to the kernel heap / data restore, stack contents change underneath
+ * and that would make function calls impossible; switch to a temporary
+ * stack within the nosave region to avoid that problem.
+ */
+int swsusp_arch_resume(void)
+{
+        extern void call_with_stack(void (*fn)(void *), void *arg, void *sp);
+        call_with_stack(arch_restore_image, 0,
+                resume_stack + ARRAY_SIZE(resume_stack));
+        return 0;
+}
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 9723d17b8f38..2c4257604513 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -37,6 +37,7 @@
 #include <linux/proc_fs.h>
 #include <linux/export.h>
+#include <asm/hardware/cache-l2x0.h>
 #include <asm/exception.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
@@ -115,10 +116,21 @@ EXPORT_SYMBOL_GPL(set_irq_flags);
 void __init init_IRQ(void)
 {
+        int ret;
        if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
                irqchip_init();
        else
                machine_desc->init_irq();
+        if (IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_CACHE_L2X0) &&
+            (machine_desc->l2c_aux_mask || machine_desc->l2c_aux_val)) {
+                outer_cache.write_sec = machine_desc->l2c_write_sec;
+                ret = l2x0_of_init(machine_desc->l2c_aux_val,
+                                   machine_desc->l2c_aux_mask);
+                if (ret)
+                        pr_err("L2C: failed to init: %d\n", ret);
+        }
 }
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/kernel/isa.c b/arch/arm/kernel/isa.c
index 346485910732..9d1cf7156895 100644
--- a/arch/arm/kernel/isa.c
+++ b/arch/arm/kernel/isa.c
@@ -20,7 +20,7 @@
 static unsigned int isa_membase, isa_portbase, isa_portshift;
-static ctl_table ctl_isa_vars[4] = {
+static struct ctl_table ctl_isa_vars[4] = {
        {
                .procname       = "membase",
                .data           = &isa_membase, 
@@ -44,7 +44,7 @@ static ctl_table ctl_isa_vars[4] = {
 static struct ctl_table_header *isa_sysctl_header;
-static ctl_table ctl_isa[2] = {
+static struct ctl_table ctl_isa[2] = {
        {
                .procname       = "isa",
                .mode           = 0555,
@@ -52,7 +52,7 @@ static ctl_table ctl_isa[2] = {
        }, {}
 };
-static ctl_table ctl_bus[2] = {
+static struct ctl_table ctl_bus[2] = {
        {
                .procname       = "bus",
                .mode           = 0555,
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index 2452dd1bef53..a5599cfc43cb 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -18,6 +18,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 #if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
 #define PJ4(code...)            code
@@ -65,17 +66,18 @@
 * r9  = ret_from_exception
 * lr  = undefined instr exit
 *
- * called from prefetch exception handler with interrupts disabled
+ * called from prefetch exception handler with interrupts enabled
 */
 ENTRY(iwmmxt_task_enable)
+        inc_preempt_count r10, r3
        XSC(mrc p15, 0, r2, c15, c1, 0)
        PJ4(mrc p15, 0, r2, c1, c0, 2)
        @ CP0 and CP1 accessible?
        XSC(tst r2, #0x3)
        PJ4(tst r2, #0xf)
-        movne   pc, lr                          @ if so no business here
+        bne     4f                              @ if so no business here
        @ enable access to CP0 and CP1
        XSC(orr r2, r2, #0x3)
        XSC(mcr p15, 0, r2, c15, c1, 0)
@@ -136,7 +138,7 @@ concan_dump:
        wstrd   wR15, [r1, #MMX_WR15]
 2:      teq     r0, #0                          @ anything to load?
-        moveq   pc, lr
+        beq     3f
 concan_load:
@@ -169,8 +171,14 @@ concan_load:
        @ clear CUP/MUP (only if r1 != 0)
        teq     r1, #0
        mov     r2, #0
-        moveq   pc, lr
+        beq     3f
        tmcr    wCon, r2
+3:
+#ifdef CONFIG_PREEMPT_COUNT
+        get_thread_info r10
+#endif
+4:      dec_preempt_count r10, r3
        mov     pc, lr
 /*
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
index 51798d7854ac..a71ae1523620 100644
--- a/arch/arm/kernel/perf_event_cpu.c
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -221,6 +221,7 @@ static struct notifier_block cpu_pmu_hotplug_notifier = {
 * PMU platform driver and devicetree bindings.
 */
 static struct of_device_id cpu_pmu_of_device_ids[] = {
+        {.compatible = "arm,cortex-a17-pmu",    .data = armv7_a17_pmu_init},
        {.compatible = "arm,cortex-a15-pmu",    .data = armv7_a15_pmu_init},
        {.compatible = "arm,cortex-a12-pmu",    .data = armv7_a12_pmu_init},
        {.compatible = "arm,cortex-a9-pmu",     .data = armv7_a9_pmu_init},
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f4ef3981ed02..2037f7205987 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1599,6 +1599,13 @@ static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
        return 0;
 }
+static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        armv7_a12_pmu_init(cpu_pmu);
+        cpu_pmu->name = "ARMv7 Cortex-A17";
+        return 0;
+}
 /*
 * Krait Performance Monitor Region Event Selection Register (PMRESRn)
 *
@@ -2021,6 +2028,11 @@ static inline int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu)
        return -ENODEV;
 }
+static inline int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu)
+{
+        return -ENODEV;
+}
 static inline int krait_pmu_init(struct arm_pmu *cpu_pmu)
 {
        return -ENODEV;
diff --git a/arch/arm/kernel/psci.c b/arch/arm/kernel/psci.c
index 46931880093d..f73891b6b730 100644
--- a/arch/arm/kernel/psci.c
+++ b/arch/arm/kernel/psci.c
@@ -17,63 +17,58 @@
 #include <linux/init.h>
 #include <linux/of.h>
+#include <linux/reboot.h>
+#include <linux/pm.h>
+#include <uapi/linux/psci.h>
 #include <asm/compiler.h>
 #include <asm/errno.h>
 #include <asm/opcodes-sec.h>
 #include <asm/opcodes-virt.h>
 #include <asm/psci.h>
+#include <asm/system_misc.h>
 struct psci_operations psci_ops;
 static int (*invoke_psci_fn)(u32, u32, u32, u32);
+typedef int (*psci_initcall_t)(const struct device_node *);
 enum psci_function {
        PSCI_FN_CPU_SUSPEND,
        PSCI_FN_CPU_ON,
        PSCI_FN_CPU_OFF,
        PSCI_FN_MIGRATE,
+        PSCI_FN_AFFINITY_INFO,
+        PSCI_FN_MIGRATE_INFO_TYPE,
        PSCI_FN_MAX,
 };
 static u32 psci_function_id[PSCI_FN_MAX];
-#define PSCI_RET_SUCCESS                0
-#define PSCI_RET_EOPNOTSUPP             -1
-#define PSCI_RET_EINVAL                 -2
-#define PSCI_RET_EPERM                  -3
 static int psci_to_linux_errno(int errno)
 {
        switch (errno) {
        case PSCI_RET_SUCCESS:
                return 0;
-        case PSCI_RET_EOPNOTSUPP:
+        case PSCI_RET_NOT_SUPPORTED:
                return -EOPNOTSUPP;
-        case PSCI_RET_EINVAL:
+        case PSCI_RET_INVALID_PARAMS:
                return -EINVAL;
-        case PSCI_RET_EPERM:
+        case PSCI_RET_DENIED:
                return -EPERM;
        };
        return -EINVAL;
 }
-#define PSCI_POWER_STATE_ID_MASK        0xffff
-#define PSCI_POWER_STATE_ID_SHIFT       0
-#define PSCI_POWER_STATE_TYPE_MASK      0x1
-#define PSCI_POWER_STATE_TYPE_SHIFT     16
-#define PSCI_POWER_STATE_AFFL_MASK      0x3
-#define PSCI_POWER_STATE_AFFL_SHIFT     24
 static u32 psci_power_state_pack(struct psci_power_state state)
 {
-        return  ((state.id & PSCI_POWER_STATE_ID_MASK)
+        return ((state.id << PSCI_0_2_POWER_STATE_ID_SHIFT)
-                        << PSCI_POWER_STATE_ID_SHIFT)   |
+                        & PSCI_0_2_POWER_STATE_ID_MASK) |
-                ((state.type & PSCI_POWER_STATE_TYPE_MASK)
+                ((state.type << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
-                        << PSCI_POWER_STATE_TYPE_SHIFT) |
+                 & PSCI_0_2_POWER_STATE_TYPE_MASK) |
-                ((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK)
+                ((state.affinity_level << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
-                        << PSCI_POWER_STATE_AFFL_SHIFT);
+                 & PSCI_0_2_POWER_STATE_AFFL_MASK);
 }
 /*
@@ -110,6 +105,14 @@ static noinline int __invoke_psci_fn_smc(u32 function_id, u32 arg0, u32 arg1,
        return function_id;
 }
+static int psci_get_version(void)
+{
+        int err;
+        err = invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0);
+        return err;
+}
 static int psci_cpu_suspend(struct psci_power_state state,
                            unsigned long entry_point)
 {
@@ -153,26 +156,36 @@ static int psci_migrate(unsigned long cpuid)
        return psci_to_linux_errno(err);
 }
-static const struct of_device_id psci_of_match[] __initconst = {
+static int psci_affinity_info(unsigned long target_affinity,
-        { .compatible = "arm,psci",     },
+                unsigned long lowest_affinity_level)
-        {},
+{
-};
+        int err;
+        u32 fn;
+        fn = psci_function_id[PSCI_FN_AFFINITY_INFO];
+        err = invoke_psci_fn(fn, target_affinity, lowest_affinity_level, 0);
+        return err;
+}
-void __init psci_init(void)
+static int psci_migrate_info_type(void)
 {
-        struct device_node *np;
+        int err;
-        const char *method;
+        u32 fn;
-        u32 id;
-        np = of_find_matching_node(NULL, psci_of_match);
+        fn = psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE];
-        if (!np)
+        err = invoke_psci_fn(fn, 0, 0, 0);
-                return;
+        return err;
+}
+static int get_set_conduit_method(struct device_node *np)
+{
+        const char *method;
-        pr_info("probing function IDs from device-tree\n");
+        pr_info("probing for conduit method from DT.\n");
        if (of_property_read_string(np, "method", &method)) {
-                pr_warning("missing \"method\" property\n");
+                pr_warn("missing \"method\" property\n");
-                goto out_put_node;
+                return -ENXIO;
        }
        if (!strcmp("hvc", method)) {
@@ -180,10 +193,99 @@ void __init psci_init(void)
        } else if (!strcmp("smc", method)) {
                invoke_psci_fn = __invoke_psci_fn_smc;
        } else {
-                pr_warning("invalid \"method\" property: %s\n", method);
+                pr_warn("invalid \"method\" property: %s\n", method);
+                return -EINVAL;
+        }
+        return 0;
+}
+static void psci_sys_reset(enum reboot_mode reboot_mode, const char *cmd)
+{
+        invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
+}
+static void psci_sys_poweroff(void)
+{
+        invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
+}
+/*
+ * PSCI Function IDs for v0.2+ are well defined so use
+ * standard values.
+ */
+static int psci_0_2_init(struct device_node *np)
+{
+        int err, ver;
+        err = get_set_conduit_method(np);
+        if (err)
+                goto out_put_node;
+        ver = psci_get_version();
+        if (ver == PSCI_RET_NOT_SUPPORTED) {
+                /* PSCI v0.2 mandates implementation of PSCI_ID_VERSION. */
+                pr_err("PSCI firmware does not comply with the v0.2 spec.\n");
+                err = -EOPNOTSUPP;
                goto out_put_node;
+        } else {
+                pr_info("PSCIv%d.%d detected in firmware.\n",
+                                PSCI_VERSION_MAJOR(ver),
+                                PSCI_VERSION_MINOR(ver));
+                if (PSCI_VERSION_MAJOR(ver) == 0 &&
+                                PSCI_VERSION_MINOR(ver) < 2) {
+                        err = -EINVAL;
+                        pr_err("Conflicting PSCI version detected.\n");
+                        goto out_put_node;
+                }
        }
+        pr_info("Using standard PSCI v0.2 function IDs\n");
+        psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN_CPU_SUSPEND;
+        psci_ops.cpu_suspend = psci_cpu_suspend;
+        psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF;
+        psci_ops.cpu_off = psci_cpu_off;
+        psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN_CPU_ON;
+        psci_ops.cpu_on = psci_cpu_on;
+        psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN_MIGRATE;
+        psci_ops.migrate = psci_migrate;
+        psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN_AFFINITY_INFO;
+        psci_ops.affinity_info = psci_affinity_info;
+        psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] =
+                PSCI_0_2_FN_MIGRATE_INFO_TYPE;
+        psci_ops.migrate_info_type = psci_migrate_info_type;
+        arm_pm_restart = psci_sys_reset;
+        pm_power_off = psci_sys_poweroff;
+out_put_node:
+        of_node_put(np);
+        return err;
+}
+/*
+ * PSCI < v0.2 get PSCI Function IDs via DT.
+ */
+static int psci_0_1_init(struct device_node *np)
+{
+        u32 id;
+        int err;
+        err = get_set_conduit_method(np);
+        if (err)
+                goto out_put_node;
+        pr_info("Using PSCI v0.1 Function IDs from DT\n");
        if (!of_property_read_u32(np, "cpu_suspend", &id)) {
                psci_function_id[PSCI_FN_CPU_SUSPEND] = id;
                psci_ops.cpu_suspend = psci_cpu_suspend;
@@ -206,5 +308,25 @@ void __init psci_init(void)
 out_put_node:
        of_node_put(np);
-        return;
+        return err;
+}
+static const struct of_device_id psci_of_match[] __initconst = {
+        { .compatible = "arm,psci", .data = psci_0_1_init},
+        { .compatible = "arm,psci-0.2", .data = psci_0_2_init},
+        {},
+};
+int __init psci_init(void)
+{
+        struct device_node *np;
+        const struct of_device_id *matched_np;
+        psci_initcall_t init_fn;
+        np = of_find_matching_node_and_match(NULL, psci_of_match, &matched_np);
+        if (!np)
+                return -ENODEV;
+        init_fn = (psci_initcall_t)matched_np->data;
+        return init_fn(np);
 }
diff --git a/arch/arm/kernel/psci_smp.c b/arch/arm/kernel/psci_smp.c
index 570a48cc3d64..28a1db4da704 100644
--- a/arch/arm/kernel/psci_smp.c
+++ b/arch/arm/kernel/psci_smp.c
@@ -16,6 +16,8 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/of.h>
+#include <linux/delay.h>
+#include <uapi/linux/psci.h>
 #include <asm/psci.h>
 #include <asm/smp_plat.h>
@@ -66,6 +68,36 @@ void __ref psci_cpu_die(unsigned int cpu)
       /* We should never return */
       panic("psci: cpu %d failed to shutdown\n", cpu);
 }
+int __ref psci_cpu_kill(unsigned int cpu)
+{
+        int err, i;
+        if (!psci_ops.affinity_info)
+                return 1;
+        /*
+         * cpu_kill could race with cpu_die and we can
+         * potentially end up declaring this cpu undead
+         * while it is dying. So, try again a few times.
+         */
+        for (i = 0; i < 10; i++) {
+                err = psci_ops.affinity_info(cpu_logical_map(cpu), 0);
+                if (err == PSCI_0_2_AFFINITY_LEVEL_OFF) {
+                        pr_info("CPU%d killed.\n", cpu);
+                        return 1;
+                }
+                msleep(10);
+                pr_info("Retrying again to check for CPU kill\n");
+        }
+        pr_warn("CPU%d may not have shut down cleanly (AFFINITY_INFO reports %d)\n",
+                        cpu, err);
+        /* Make platform_cpu_kill() fail. */
+        return 0;
+}
 #endif
 bool __init psci_smp_available(void)
@@ -78,5 +110,6 @@ struct smp_operations __initdata psci_smp_ops = {
        .smp_boot_secondary     = psci_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_die                = psci_cpu_die,
+        .cpu_kill               = psci_cpu_kill,
 #endif
 };
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 50e198c1e9c8..8a16ee5d8a95 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -72,6 +72,7 @@ static int __init fpe_setup(char *line)
 __setup("fpe=", fpe_setup);
 #endif
+extern void init_default_cache_policy(unsigned long);
 extern void paging_init(const struct machine_desc *desc);
 extern void early_paging_init(const struct machine_desc *,
                              struct proc_info_list *);
@@ -590,7 +591,7 @@ static void __init setup_processor(void)
        pr_info("CPU: %s [%08x] revision %d (ARMv%s), cr=%08lx\n",
                cpu_name, read_cpuid_id(), read_cpuid_id() & 15,
-                proc_arch[cpu_architecture()], cr_alignment);
+                proc_arch[cpu_architecture()], get_cr());
        snprintf(init_utsname()->machine, __NEW_UTS_LEN + 1, "%s%c",
                 list->arch_name, ENDIANNESS);
@@ -603,7 +604,9 @@ static void __init setup_processor(void)
 #ifndef CONFIG_ARM_THUMB
        elf_hwcap &= ~(HWCAP_THUMB | HWCAP_IDIVT);
 #endif
+#ifdef CONFIG_MMU
+        init_default_cache_policy(list->__cpu_mm_mmu_flags);
+#endif
        erratum_a15_798181_init();
        feat_v6_fixup();
@@ -628,15 +631,8 @@ void __init dump_machine_table(void)
 int __init arm_add_memory(u64 start, u64 size)
 {
-        struct membank *bank = &meminfo.bank[meminfo.nr_banks];
        u64 aligned_start;
-        if (meminfo.nr_banks >= NR_BANKS) {
-                pr_crit("NR_BANKS too low, ignoring memory at 0x%08llx\n",
-                        (long long)start);
-                return -EINVAL;
-        }
        /*
         * Ensure that start/size are aligned to a page boundary.
         * Size is appropriately rounded down, start is rounded up.
@@ -677,17 +673,17 @@ int __init arm_add_memory(u64 start, u64 size)
                aligned_start = PHYS_OFFSET;
        }
-        bank->start = aligned_start;
+        start = aligned_start;
-        bank->size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
+        size = size & ~(phys_addr_t)(PAGE_SIZE - 1);
        /*
         * Check whether this memory region has non-zero size or
         * invalid node number.
         */
-        if (bank->size == 0)
+        if (size == 0)
                return -EINVAL;
-        meminfo.nr_banks++;
+        memblock_add(start, size);
        return 0;
 }
@@ -695,6 +691,7 @@ int __init arm_add_memory(u64 start, u64 size)
 * Pick out the memory size.  We look for mem=size@start,
 * where start and size are "size[KkMm]"
 */
 static int __init early_mem(char *p)
 {
        static int usermem __initdata = 0;
@@ -709,7 +706,8 @@ static int __init early_mem(char *p)
         */
        if (usermem == 0) {
                usermem = 1;
-                meminfo.nr_banks = 0;
+                memblock_remove(memblock_start_of_DRAM(),
+                        memblock_end_of_DRAM() - memblock_start_of_DRAM());
        }
        start = PHYS_OFFSET;
@@ -854,13 +852,6 @@ static void __init reserve_crashkernel(void)
 static inline void reserve_crashkernel(void) {}
 #endif /* CONFIG_KEXEC */
-static int __init meminfo_cmp(const void *_a, const void *_b)
-{
-        const struct membank *a = _a, *b = _b;
-        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
-        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
-}
 void __init hyp_mode_check(void)
 {
 #ifdef CONFIG_ARM_VIRT_EXT
@@ -903,12 +894,10 @@ void __init setup_arch(char **cmdline_p)
        parse_early_param();
-        sort(&meminfo.bank, meminfo.nr_banks, sizeof(meminfo.bank[0]), meminfo_cmp, NULL);
        early_paging_init(mdesc, lookup_processor_type(read_cpuid_id()));
        setup_dma_zone(mdesc);
        sanity_check_meminfo();
-        arm_memblock_init(&meminfo, mdesc);
+        arm_memblock_init(mdesc);
        paging_init(mdesc);
        request_standard_resources(mdesc);
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index b907d9b790ab..1b880db2a033 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -127,6 +127,10 @@ ENDPROC(cpu_resume_after_mmu)
        .align
 ENTRY(cpu_resume)
 ARM_BE8(setend be)                      @ ensure we are in BE mode
+#ifdef CONFIG_ARM_VIRT_EXT
+        bl      __hyp_stub_install_secondary
+#endif
+        safe_svcmode_maskall r1
        mov     r1, #0
        ALT_SMP(mrc p15, 0, r0, c0, c0, 5)
        ALT_UP_B(1f)
@@ -144,7 +148,6 @@ ARM_BE8(setend be)			@ ensure we are in BE mode
        ldr     r0, [r0, #SLEEP_SAVE_SP_PHYS]
        ldr     r0, [r0, r1, lsl #2]
-        setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1  @ set SVC, irqs off
        @ load phys pgd, stack, resume fn
  ARM(  ldmia   r0!, {r1, sp, pc}       )
 THUMB(  ldmia   r0!, {r1, r2, r3}       )
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index af4e8c8a5422..f065eb05d254 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -3,6 +3,7 @@
 #include <linux/stacktrace.h>
 #include <asm/stacktrace.h>
+#include <asm/traps.h>
 #if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
 /*
@@ -61,6 +62,7 @@ EXPORT_SYMBOL(walk_stackframe);
 #ifdef CONFIG_STACKTRACE
 struct stack_trace_data {
        struct stack_trace *trace;
+        unsigned long last_pc;
        unsigned int no_sched_functions;
        unsigned int skip;
 };
@@ -69,6 +71,7 @@ static int save_trace(struct stackframe *frame, void *d)
 {
        struct stack_trace_data *data = d;
        struct stack_trace *trace = data->trace;
+        struct pt_regs *regs;
        unsigned long addr = frame->pc;
        if (data->no_sched_functions && in_sched_functions(addr))
@@ -80,16 +83,39 @@ static int save_trace(struct stackframe *frame, void *d)
        trace->entries[trace->nr_entries++] = addr;
+        if (trace->nr_entries >= trace->max_entries)
+                return 1;
+        /*
+         * in_exception_text() is designed to test if the PC is one of
+         * the functions which has an exception stack above it, but
+         * unfortunately what is in frame->pc is the return LR value,
+         * not the saved PC value.  So, we need to track the previous
+         * frame PC value when doing this.
+         */
+        addr = data->last_pc;
+        data->last_pc = frame->pc;
+        if (!in_exception_text(addr))
+                return 0;
+        regs = (struct pt_regs *)frame->sp;
+        trace->entries[trace->nr_entries++] = regs->ARM_pc;
        return trace->nr_entries >= trace->max_entries;
 }
-void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+/* This must be noinline to so that our skip calculation works correctly */
+static noinline void __save_stack_trace(struct task_struct *tsk,
+        struct stack_trace *trace, unsigned int nosched)
 {
        struct stack_trace_data data;
        struct stackframe frame;
        data.trace = trace;
+        data.last_pc = ULONG_MAX;
        data.skip = trace->skip;
+        data.no_sched_functions = nosched;
        if (tsk != current) {
 #ifdef CONFIG_SMP
@@ -102,7 +128,6 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
                        trace->entries[trace->nr_entries++] = ULONG_MAX;
                return;
 #else
-                data.no_sched_functions = 1;
                frame.fp = thread_saved_fp(tsk);
                frame.sp = thread_saved_sp(tsk);
                frame.lr = 0;           /* recovered from the stack */
@@ -111,11 +136,12 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
        } else {
                register unsigned long current_sp asm ("sp");
-                data.no_sched_functions = 0;
+                /* We don't want this function nor the caller */
+                data.skip += 2;
                frame.fp = (unsigned long)__builtin_frame_address(0);
                frame.sp = current_sp;
                frame.lr = (unsigned long)__builtin_return_address(0);
-                frame.pc = (unsigned long)save_stack_trace_tsk;
+                frame.pc = (unsigned long)__save_stack_trace;
        }
        walk_stackframe(&frame, save_trace, &data);
@@ -123,9 +149,33 @@ void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
                trace->entries[trace->nr_entries++] = ULONG_MAX;
 }
+void save_stack_trace_regs(struct pt_regs *regs, struct stack_trace *trace)
+{
+        struct stack_trace_data data;
+        struct stackframe frame;
+        data.trace = trace;
+        data.skip = trace->skip;
+        data.no_sched_functions = 0;
+        frame.fp = regs->ARM_fp;
+        frame.sp = regs->ARM_sp;
+        frame.lr = regs->ARM_lr;
+        frame.pc = regs->ARM_pc;
+        walk_stackframe(&frame, save_trace, &data);
+        if (trace->nr_entries < trace->max_entries)
+                trace->entries[trace->nr_entries++] = ULONG_MAX;
+}
+void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
+{
+        __save_stack_trace(tsk, trace, 1);
+}
 void save_stack_trace(struct stack_trace *trace)
 {
-        save_stack_trace_tsk(current, trace);
+        __save_stack_trace(current, trace, 0);
 }
 EXPORT_SYMBOL_GPL(save_stack_trace);
 #endif
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
index 0bc94b1fd1ae..3997c411c140 100644
--- a/arch/arm/kernel/topology.c
+++ b/arch/arm/kernel/topology.c
@@ -91,13 +91,13 @@ static void __init parse_dt_topology(void)
 {
        const struct cpu_efficiency *cpu_eff;
        struct device_node *cn = NULL;
-        unsigned long min_capacity = (unsigned long)(-1);
+        unsigned long min_capacity = ULONG_MAX;
        unsigned long max_capacity = 0;
        unsigned long capacity = 0;
-        int alloc_size, cpu = 0;
+        int cpu = 0;
-        alloc_size = nr_cpu_ids * sizeof(*__cpu_capacity);
+        __cpu_capacity = kcalloc(nr_cpu_ids, sizeof(*__cpu_capacity),
-        __cpu_capacity = kzalloc(alloc_size, GFP_NOWAIT);
+                                 GFP_NOWAIT);
        for_each_possible_cpu(cpu) {
                const u32 *rate;
@@ -185,6 +185,15 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
        return &cpu_topology[cpu].core_sibling;
 }
+/*
+ * The current assumption is that we can power gate each core independently.
+ * This will be superseded by DT binding once available.
+ */
+const struct cpumask *cpu_corepower_mask(int cpu)
+{
+        return &cpu_topology[cpu].thread_sibling;
+}
 static void update_siblings_masks(unsigned int cpuid)
 {
        struct cputopo_arm *cpu_topo, *cpuid_topo = &cpu_topology[cpuid];
@@ -266,6 +275,20 @@ void store_cpu_topology(unsigned int cpuid)
                cpu_topology[cpuid].socket_id, mpidr);
 }
+static inline const int cpu_corepower_flags(void)
+{
+        return SD_SHARE_PKG_RESOURCES  | SD_SHARE_POWERDOMAIN;
+}
+static struct sched_domain_topology_level arm_topology[] = {
+#ifdef CONFIG_SCHED_MC
+        { cpu_corepower_mask, cpu_corepower_flags, SD_INIT_NAME(GMC) },
+        { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
+#endif
+        { cpu_cpu_mask, SD_INIT_NAME(DIE) },
+        { NULL, },
+};
 /*
 * init_cpu_topology is called at boot when only one cpu is running
 * which prevent simultaneous write access to cpu_topology array
@@ -289,4 +312,7 @@ void __init init_cpu_topology(void)
        smp_wmb();
        parse_dt_topology();
+        /* Set scheduler topology descriptor */
+        set_sched_topology(arm_topology);
 }
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index 3c217694ebec..e67682f02cb2 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -31,7 +31,7 @@
 #warning Your compiler does not have EABI support.
 #warning    ARM unwind is known to compile only with EABI compilers.
 #warning    Change compiler or disable ARM_UNWIND option.
-#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2)
+#elif (__GNUC__ == 4 && __GNUC_MINOR__ <= 2) && !defined(__clang__)
 #warning Your compiler is too buggy; it is known to not compile ARM unwind support.
 #warning    Change compiler or disable ARM_UNWIND option.
 #endif
@@ -285,7 +285,7 @@ static int unwind_exec_pop_r4_to_rN(struct unwind_ctrl_block *ctrl,
                if (unwind_pop_register(ctrl, &vsp, reg))
                                return -URC_FAILURE;
-        if (insn & 0x80)
+        if (insn & 0x8)
                if (unwind_pop_register(ctrl, &vsp, 14))
                                return -URC_FAILURE;
diff --git a/arch/arm/kernel/uprobes.c b/arch/arm/kernel/uprobes.c
index f9bacee973bf..56adf9c1fde0 100644
--- a/arch/arm/kernel/uprobes.c
+++ b/arch/arm/kernel/uprobes.c
@@ -113,6 +113,26 @@ int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm,
        return 0;
 }
+void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
+                           void *src, unsigned long len)
+{
+        void *xol_page_kaddr = kmap_atomic(page);
+        void *dst = xol_page_kaddr + (vaddr & ~PAGE_MASK);
+        preempt_disable();
+        /* Initialize the slot */
+        memcpy(dst, src, len);
+        /* flush caches (dcache/icache) */
+        flush_uprobe_xol_access(page, vaddr, dst, len);
+        preempt_enable();
+        kunmap_atomic(xol_page_kaddr);
+}
 int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
 {
        struct uprobe_task *utask = current->utask;
diff --git a/arch/arm/kvm/Kconfig b/arch/arm/kvm/Kconfig
index 466bd299b1a8..4be5bb150bdd 100644
--- a/arch/arm/kvm/Kconfig
+++ b/arch/arm/kvm/Kconfig
@@ -23,7 +23,7 @@ config KVM
        select HAVE_KVM_CPU_RELAX_INTERCEPT
        select KVM_MMIO
        select KVM_ARM_HOST
-        depends on ARM_VIRT_EXT && ARM_LPAE
+        depends on ARM_VIRT_EXT && ARM_LPAE && !CPU_BIG_ENDIAN
        ---help---
          Support hosting virtualized guest machines. You will also
          need to select one or more of the processor modules below.
diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index f0e50a0f3a65..3c82b37c0f9e 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -197,6 +197,7 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_DESTROY_MEMORY_REGION_WORKS:
        case KVM_CAP_ONE_REG:
        case KVM_CAP_ARM_PSCI:
+        case KVM_CAP_ARM_PSCI_0_2:
                r = 1;
                break;
        case KVM_CAP_COALESCED_MMIO:
diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
index 0de91fc6de0f..4c979d466cc1 100644
--- a/arch/arm/kvm/handle_exit.c
+++ b/arch/arm/kvm/handle_exit.c
@@ -38,14 +38,18 @@ static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
 static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
 {
+        int ret;
        trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
                      kvm_vcpu_hvc_get_imm(vcpu));
-        if (kvm_psci_call(vcpu))
+        ret = kvm_psci_call(vcpu);
+        if (ret < 0) {
+                kvm_inject_undefined(vcpu);
                return 1;
+        }
-        kvm_inject_undefined(vcpu);
+        return ret;
-        return 1;
 }
 static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
index 80bb1e6c2c29..16f804938b8f 100644
--- a/arch/arm/kvm/mmu.c
+++ b/arch/arm/kvm/mmu.c
@@ -42,6 +42,8 @@ static unsigned long hyp_idmap_start;
 static unsigned long hyp_idmap_end;
 static phys_addr_t hyp_idmap_vector;
+#define pgd_order get_order(PTRS_PER_PGD * sizeof(pgd_t))
 #define kvm_pmd_huge(_x)        (pmd_huge(_x) || pmd_trans_huge(_x))
 static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
@@ -293,14 +295,14 @@ void free_boot_hyp_pgd(void)
        if (boot_hyp_pgd) {
                unmap_range(NULL, boot_hyp_pgd, hyp_idmap_start, PAGE_SIZE);
                unmap_range(NULL, boot_hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
-                kfree(boot_hyp_pgd);
+                free_pages((unsigned long)boot_hyp_pgd, pgd_order);
                boot_hyp_pgd = NULL;
        }
        if (hyp_pgd)
                unmap_range(NULL, hyp_pgd, TRAMPOLINE_VA, PAGE_SIZE);
-        kfree(init_bounce_page);
+        free_page((unsigned long)init_bounce_page);
        init_bounce_page = NULL;
        mutex_unlock(&kvm_hyp_pgd_mutex);
@@ -330,7 +332,7 @@ void free_hyp_pgds(void)
                for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
                        unmap_range(NULL, hyp_pgd, KERN_TO_HYP(addr), PGDIR_SIZE);
-                kfree(hyp_pgd);
+                free_pages((unsigned long)hyp_pgd, pgd_order);
                hyp_pgd = NULL;
        }
@@ -1024,7 +1026,7 @@ int kvm_mmu_init(void)
                size_t len = __hyp_idmap_text_end - __hyp_idmap_text_start;
                phys_addr_t phys_base;
-                init_bounce_page = kmalloc(PAGE_SIZE, GFP_KERNEL);
+                init_bounce_page = (void *)__get_free_page(GFP_KERNEL);
                if (!init_bounce_page) {
                        kvm_err("Couldn't allocate HYP init bounce page\n");
                        err = -ENOMEM;
@@ -1050,8 +1052,9 @@ int kvm_mmu_init(void)
                         (unsigned long)phys_base);
        }
-        hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, pgd_order);
-        boot_hyp_pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
+        boot_hyp_pgd = (pgd_t *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, pgd_order);
        if (!hyp_pgd || !boot_hyp_pgd) {
                kvm_err("Hyp mode PGD not allocated\n");
                err = -ENOMEM;
diff --git a/arch/arm/kvm/psci.c b/arch/arm/kvm/psci.c
index 448f60e8d23c..09cf37737ee2 100644
--- a/arch/arm/kvm/psci.c
+++ b/arch/arm/kvm/psci.c
@@ -27,6 +27,36 @@
 * as described in ARM document number ARM DEN 0022A.
 */
+#define AFFINITY_MASK(level)    ~((0x1UL << ((level) * MPIDR_LEVEL_BITS)) - 1)
+static unsigned long psci_affinity_mask(unsigned long affinity_level)
+{
+        if (affinity_level <= 3)
+                return MPIDR_HWID_BITMASK & AFFINITY_MASK(affinity_level);
+        return 0;
+}
+static unsigned long kvm_psci_vcpu_suspend(struct kvm_vcpu *vcpu)
+{
+        /*
+         * NOTE: For simplicity, we make VCPU suspend emulation to be
+         * same-as WFI (Wait-for-interrupt) emulation.
+         *
+         * This means for KVM the wakeup events are interrupts and
+         * this is consistent with intended use of StateID as described
+         * in section 5.4.1 of PSCI v0.2 specification (ARM DEN 0022A).
+         *
+         * Further, we also treat power-down request to be same as
+         * stand-by request as-per section 5.4.2 clause 3 of PSCI v0.2
+         * specification (ARM DEN 0022A). This means all suspend states
+         * for KVM will preserve the register state.
+         */
+        kvm_vcpu_block(vcpu);
+        return PSCI_RET_SUCCESS;
+}
 static void kvm_psci_vcpu_off(struct kvm_vcpu *vcpu)
 {
        vcpu->arch.pause = true;
@@ -38,6 +68,7 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
        struct kvm_vcpu *vcpu = NULL, *tmp;
        wait_queue_head_t *wq;
        unsigned long cpu_id;
+        unsigned long context_id;
        unsigned long mpidr;
        phys_addr_t target_pc;
        int i;
@@ -58,10 +89,17 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
         * Make sure the caller requested a valid CPU and that the CPU is
         * turned off.
         */
-        if (!vcpu || !vcpu->arch.pause)
+        if (!vcpu)
-                return KVM_PSCI_RET_INVAL;
+                return PSCI_RET_INVALID_PARAMS;
+        if (!vcpu->arch.pause) {
+                if (kvm_psci_version(source_vcpu) != KVM_ARM_PSCI_0_1)
+                        return PSCI_RET_ALREADY_ON;
+                else
+                        return PSCI_RET_INVALID_PARAMS;
+        }
        target_pc = *vcpu_reg(source_vcpu, 2);
+        context_id = *vcpu_reg(source_vcpu, 3);
        kvm_reset_vcpu(vcpu);
@@ -76,26 +114,160 @@ static unsigned long kvm_psci_vcpu_on(struct kvm_vcpu *source_vcpu)
                kvm_vcpu_set_be(vcpu);
        *vcpu_pc(vcpu) = target_pc;
+        /*
+         * NOTE: We always update r0 (or x0) because for PSCI v0.1
+         * the general puspose registers are undefined upon CPU_ON.
+         */
+        *vcpu_reg(vcpu, 0) = context_id;
        vcpu->arch.pause = false;
        smp_mb();               /* Make sure the above is visible */
        wq = kvm_arch_vcpu_wq(vcpu);
        wake_up_interruptible(wq);
-        return KVM_PSCI_RET_SUCCESS;
+        return PSCI_RET_SUCCESS;
 }
-/**
+static unsigned long kvm_psci_vcpu_affinity_info(struct kvm_vcpu *vcpu)
- * kvm_psci_call - handle PSCI call if r0 value is in range
+{
- * @vcpu: Pointer to the VCPU struct
+        int i;
- *
+        unsigned long mpidr;
- * Handle PSCI calls from guests through traps from HVC instructions.
+        unsigned long target_affinity;
- * The calling convention is similar to SMC calls to the secure world where
+        unsigned long target_affinity_mask;
- * the function number is placed in r0 and this function returns true if the
+        unsigned long lowest_affinity_level;
- * function number specified in r0 is withing the PSCI range, and false
+        struct kvm *kvm = vcpu->kvm;
- * otherwise.
+        struct kvm_vcpu *tmp;
- */
-bool kvm_psci_call(struct kvm_vcpu *vcpu)
+        target_affinity = *vcpu_reg(vcpu, 1);
+        lowest_affinity_level = *vcpu_reg(vcpu, 2);
+        /* Determine target affinity mask */
+        target_affinity_mask = psci_affinity_mask(lowest_affinity_level);
+        if (!target_affinity_mask)
+                return PSCI_RET_INVALID_PARAMS;
+        /* Ignore other bits of target affinity */
+        target_affinity &= target_affinity_mask;
+        /*
+         * If one or more VCPU matching target affinity are running
+         * then ON else OFF
+         */
+        kvm_for_each_vcpu(i, tmp, kvm) {
+                mpidr = kvm_vcpu_get_mpidr(tmp);
+                if (((mpidr & target_affinity_mask) == target_affinity) &&
+                    !tmp->arch.pause) {
+                        return PSCI_0_2_AFFINITY_LEVEL_ON;
+                }
+        }
+        return PSCI_0_2_AFFINITY_LEVEL_OFF;
+}
+static void kvm_prepare_system_event(struct kvm_vcpu *vcpu, u32 type)
+{
+        memset(&vcpu->run->system_event, 0, sizeof(vcpu->run->system_event));
+        vcpu->run->system_event.type = type;
+        vcpu->run->exit_reason = KVM_EXIT_SYSTEM_EVENT;
+}
+static void kvm_psci_system_off(struct kvm_vcpu *vcpu)
+{
+        kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_SHUTDOWN);
+}
+static void kvm_psci_system_reset(struct kvm_vcpu *vcpu)
+{
+        kvm_prepare_system_event(vcpu, KVM_SYSTEM_EVENT_RESET);
+}
+int kvm_psci_version(struct kvm_vcpu *vcpu)
+{
+        if (test_bit(KVM_ARM_VCPU_PSCI_0_2, vcpu->arch.features))
+                return KVM_ARM_PSCI_0_2;
+        return KVM_ARM_PSCI_0_1;
+}
+static int kvm_psci_0_2_call(struct kvm_vcpu *vcpu)
+{
+        int ret = 1;
+        unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
+        unsigned long val;
+        switch (psci_fn) {
+        case PSCI_0_2_FN_PSCI_VERSION:
+                /*
+                 * Bits[31:16] = Major Version = 0
+                 * Bits[15:0] = Minor Version = 2
+                 */
+                val = 2;
+                break;
+        case PSCI_0_2_FN_CPU_SUSPEND:
+        case PSCI_0_2_FN64_CPU_SUSPEND:
+                val = kvm_psci_vcpu_suspend(vcpu);
+                break;
+        case PSCI_0_2_FN_CPU_OFF:
+                kvm_psci_vcpu_off(vcpu);
+                val = PSCI_RET_SUCCESS;
+                break;
+        case PSCI_0_2_FN_CPU_ON:
+        case PSCI_0_2_FN64_CPU_ON:
+                val = kvm_psci_vcpu_on(vcpu);
+                break;
+        case PSCI_0_2_FN_AFFINITY_INFO:
+        case PSCI_0_2_FN64_AFFINITY_INFO:
+                val = kvm_psci_vcpu_affinity_info(vcpu);
+                break;
+        case PSCI_0_2_FN_MIGRATE:
+        case PSCI_0_2_FN64_MIGRATE:
+                val = PSCI_RET_NOT_SUPPORTED;
+                break;
+        case PSCI_0_2_FN_MIGRATE_INFO_TYPE:
+                /*
+                 * Trusted OS is MP hence does not require migration
+                 * or
+                 * Trusted OS is not present
+                 */
+                val = PSCI_0_2_TOS_MP;
+                break;
+        case PSCI_0_2_FN_MIGRATE_INFO_UP_CPU:
+        case PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU:
+                val = PSCI_RET_NOT_SUPPORTED;
+                break;
+        case PSCI_0_2_FN_SYSTEM_OFF:
+                kvm_psci_system_off(vcpu);
+                /*
+                 * We should'nt be going back to guest VCPU after
+                 * receiving SYSTEM_OFF request.
+                 *
+                 * If user space accidently/deliberately resumes
+                 * guest VCPU after SYSTEM_OFF request then guest
+                 * VCPU should see internal failure from PSCI return
+                 * value. To achieve this, we preload r0 (or x0) with
+                 * PSCI return value INTERNAL_FAILURE.
+                 */
+                val = PSCI_RET_INTERNAL_FAILURE;
+                ret = 0;
+                break;
+        case PSCI_0_2_FN_SYSTEM_RESET:
+                kvm_psci_system_reset(vcpu);
+                /*
+                 * Same reason as SYSTEM_OFF for preloading r0 (or x0)
+                 * with PSCI return value INTERNAL_FAILURE.
+                 */
+                val = PSCI_RET_INTERNAL_FAILURE;
+                ret = 0;
+                break;
+        default:
+                return -EINVAL;
+        }
+        *vcpu_reg(vcpu, 0) = val;
+        return ret;
+}
+static int kvm_psci_0_1_call(struct kvm_vcpu *vcpu)
 {
        unsigned long psci_fn = *vcpu_reg(vcpu, 0) & ~((u32) 0);
        unsigned long val;
@@ -103,20 +275,45 @@ bool kvm_psci_call(struct kvm_vcpu *vcpu)
        switch (psci_fn) {
        case KVM_PSCI_FN_CPU_OFF:
                kvm_psci_vcpu_off(vcpu);
-                val = KVM_PSCI_RET_SUCCESS;
+                val = PSCI_RET_SUCCESS;
                break;
        case KVM_PSCI_FN_CPU_ON:
                val = kvm_psci_vcpu_on(vcpu);
                break;
        case KVM_PSCI_FN_CPU_SUSPEND:
        case KVM_PSCI_FN_MIGRATE:
-                val = KVM_PSCI_RET_NI;
+                val = PSCI_RET_NOT_SUPPORTED;
                break;
        default:
-                return false;
+                return -EINVAL;
        }
        *vcpu_reg(vcpu, 0) = val;
-        return true;
+        return 1;
+}
+/**
+ * kvm_psci_call - handle PSCI call if r0 value is in range
+ * @vcpu: Pointer to the VCPU struct
+ *
+ * Handle PSCI calls from guests through traps from HVC instructions.
+ * The calling convention is similar to SMC calls to the secure world
+ * where the function number is placed in r0.
+ *
+ * This function returns: > 0 (success), 0 (success but exit to user
+ * space), and < 0 (errors)
+ *
+ * Errors:
+ * -EINVAL: Unrecognized PSCI function
+ */
+int kvm_psci_call(struct kvm_vcpu *vcpu)
+{
+        switch (kvm_psci_version(vcpu)) {
+        case KVM_ARM_PSCI_0_2:
+                return kvm_psci_0_2_call(vcpu);
+        case KVM_ARM_PSCI_0_1:
+                return kvm_psci_0_1_call(vcpu);
+        default:
+                return -EINVAL;
+        };
 }
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index b2d2cf4dc052..45b55e0f0db6 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -167,7 +167,6 @@ config SOC_AT91SAM9X5
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
        select SOC_AT91SAM9
-        select AT91_USE_OLD_CLK
        select HAVE_AT91_UTMI
        select HAVE_AT91_SMD
        select HAVE_AT91_USB_CLK
@@ -183,7 +182,6 @@ config SOC_AT91SAM9N12
        select HAVE_AT91_DBGU0
        select HAVE_FB_ATMEL
        select SOC_AT91SAM9
-        select AT91_USE_OLD_CLK
        select HAVE_AT91_USB_CLK
        help
          Select this if you are using Atmel's AT91SAM9N12 SoC.
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index f3f19f21352a..3f4bb58aea54 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -15,6 +15,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/gpio.h>
+#include <linux/gpio/driver.h>
 #include <linux/platform_device.h>
 #include <linux/i2c-gpio.h>
@@ -25,6 +26,7 @@
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
@@ -923,7 +925,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -962,7 +963,14 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
+};
+static struct gpiod_lookup_table uart0_gpios_table = {
+        .dev_id = "atmel_usart",
+        .table = {
+                GPIO_LOOKUP("pioA", 21, "rts", GPIO_ACTIVE_LOW),
+                { },
+        },
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -993,7 +1001,7 @@ static inline void configure_usart0_pins(unsigned pins)
                 * We need to drive the pin manually. The serial driver will driver
                 * this to high when initializing.
                 */
-                uart0_data.rts_gpio = AT91_PIN_PA21;
+                gpiod_add_lookup_table(&uart0_gpios_table);
        }
 }
@@ -1013,7 +1021,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1065,7 +1072,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1109,7 +1115,6 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index a0282928e9c1..ef88e0fe4e80 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -24,12 +24,11 @@
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
 #include <mach/at91sam9_smc.h>
-#include <mach/at91_adc.h>
 #include <mach/hardware.h>
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
 *  USB Host
@@ -820,7 +819,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -859,7 +857,6 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -911,7 +908,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -955,7 +951,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -999,7 +994,6 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
@@ -1043,7 +1037,6 @@ static struct resource uart4_resources[] = {
 static struct atmel_uart_data uart4_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart4_dmamask = DMA_BIT_MASK(32);
@@ -1082,7 +1075,6 @@ static struct resource uart5_resources[] = {
 static struct atmel_uart_data uart5_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart5_dmamask = DMA_BIT_MASK(32);
@@ -1308,30 +1300,23 @@ static struct platform_device at91_adc_device = {
 static struct at91_adc_trigger at91_adc_triggers[] = {
        [0] = {
                .name = "timer-counter-0",
-                .value = AT91_ADC_TRGSEL_TC0 | AT91_ADC_TRGEN,
+                .value = 0x1,
        },
        [1] = {
                .name = "timer-counter-1",
-                .value = AT91_ADC_TRGSEL_TC1 | AT91_ADC_TRGEN,
+                .value = 0x3,
        },
        [2] = {
                .name = "timer-counter-2",
-                .value = AT91_ADC_TRGSEL_TC2 | AT91_ADC_TRGEN,
+                .value = 0x5,
        },
        [3] = {
                .name = "external",
-                .value = AT91_ADC_TRGSEL_EXTERNAL | AT91_ADC_TRGEN,
+                .value = 0xd,
                .is_external = true,
        },
 };
-static struct at91_adc_reg_desc at91_adc_register_g20 = {
-        .channel_base = AT91_ADC_CHR(0),
-        .drdy_mask = AT91_ADC_DRDY,
-        .status_register = AT91_ADC_SR,
-        .trigger_register = AT91_ADC_MR,
-};
 void __init at91_add_device_adc(struct at91_adc_data *data)
 {
        if (!data)
@@ -1349,9 +1334,7 @@ void __init at91_add_device_adc(struct at91_adc_data *data)
        if (data->use_external_triggers)
                at91_set_A_periph(AT91_PIN_PA22, 0);
-        data->num_channels = 4;
        data->startup_time = 10;
-        data->registers = &at91_adc_register_g20;
        data->trigger_number = 4;
        data->trigger_list = at91_adc_triggers;
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 80e35895d28f..29baacb5c359 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -29,7 +29,7 @@
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
 *  USB Host
@@ -881,7 +881,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -920,7 +919,6 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -964,7 +962,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1008,7 +1005,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 43d53d6156dd..309390d8e2f8 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -28,6 +28,7 @@
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
@@ -1325,7 +1326,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -1364,7 +1364,6 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1408,7 +1407,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1452,7 +1450,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 5e6f498db0a8..9d3d544ac19c 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -182,7 +182,7 @@ static struct clk vdec_clk = {
 static struct clk adc_op_clk = {
        .name           = "adc_op_clk",
        .type           = CLK_TYPE_PERIPHERAL,
-        .rate_hz        = 13200000,
+        .rate_hz        = 300000,
 };
 /* AES/TDES/SHA clock - Only for sam9m11/sam9g56 */
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index dab362c06487..391ab6bb536a 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -25,7 +25,6 @@
 #include <linux/fb.h>
 #include <video/atmel_lcdc.h>
-#include <mach/at91_adc.h>
 #include <mach/at91sam9g45.h>
 #include <mach/at91sam9g45_matrix.h>
 #include <mach/at91_matrix.h>
@@ -39,6 +38,7 @@
 #include "board.h"
 #include "generic.h"
 #include "clock.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
@@ -1133,58 +1133,7 @@ static void __init at91_add_device_rtc(void) {}
 /* --------------------------------------------------------------------
- *  Touchscreen
+ *  ADC and touchscreen
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
-static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
-static struct at91_tsadcc_data tsadcc_data;
-static struct resource tsadcc_resources[] = {
-        [0] = {
-                .start  = AT91SAM9G45_BASE_TSC,
-                .end    = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
-                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
-                .flags  = IORESOURCE_IRQ,
-        }
-};
-static struct platform_device at91sam9g45_tsadcc_device = {
-        .name           = "atmel_tsadcc",
-        .id             = -1,
-        .dev            = {
-                                .dma_mask               = &tsadcc_dmamask,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &tsadcc_data,
-        },
-        .resource       = tsadcc_resources,
-        .num_resources  = ARRAY_SIZE(tsadcc_resources),
-};
-void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
-{
-        if (!data)
-                return;
-        at91_set_gpio_input(AT91_PIN_PD20, 0);  /* AD0_XR */
-        at91_set_gpio_input(AT91_PIN_PD21, 0);  /* AD1_XL */
-        at91_set_gpio_input(AT91_PIN_PD22, 0);  /* AD2_YT */
-        at91_set_gpio_input(AT91_PIN_PD23, 0);  /* AD3_TB */
-        tsadcc_data = *data;
-        platform_device_register(&at91sam9g45_tsadcc_device);
-}
-#else
-void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
-#endif
-/* --------------------------------------------------------------------
- *  ADC
 * -------------------------------------------------------------------- */
 #if IS_ENABLED(CONFIG_AT91_ADC)
@@ -1236,13 +1185,6 @@ static struct at91_adc_trigger at91_adc_triggers[] = {
        },
 };
-static struct at91_adc_reg_desc at91_adc_register_g45 = {
-        .channel_base = AT91_ADC_CHR(0),
-        .drdy_mask = AT91_ADC_DRDY,
-        .status_register = AT91_ADC_SR,
-        .trigger_register = 0x08,
-};
 void __init at91_add_device_adc(struct at91_adc_data *data)
 {
        if (!data)
@@ -1268,9 +1210,7 @@ void __init at91_add_device_adc(struct at91_adc_data *data)
        if (data->use_external_triggers)
                at91_set_A_periph(AT91_PIN_PD28, 0);
-        data->num_channels = 8;
        data->startup_time = 40;
-        data->registers = &at91_adc_register_g45;
        data->trigger_number = 4;
        data->trigger_list = at91_adc_triggers;
@@ -1588,7 +1528,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -1627,7 +1566,6 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1671,7 +1609,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1715,7 +1652,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1759,7 +1695,6 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index f2ea7b0a02da..c8988fe5ff70 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -19,9 +19,10 @@
 #include "board.h"
 #include "soc.h"
 #include "generic.h"
-#include "clock.h"
 #include "sam9_smc.h"
+#if defined(CONFIG_OLD_CLK_AT91)
+#include "clock.h"
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
@@ -215,6 +216,9 @@ static void __init at91sam9n12_register_clocks(void)
                         ARRAY_SIZE(periph_clocks_lookups));
 }
+#else
+#define at91sam9n12_register_clocks NULL
+#endif
 /* --------------------------------------------------------------------
 *  AT91SAM9N12 processor initialization
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index 57f12d86c0e6..a79960f57e6a 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -153,6 +153,11 @@ static struct clk ac97_clk = {
        .pmc_mask       = 1 << AT91SAM9RL_ID_AC97C,
        .type           = CLK_TYPE_PERIPHERAL,
 };
+static struct clk adc_op_clk = {
+        .name           = "adc_op_clk",
+        .type           = CLK_TYPE_PERIPHERAL,
+        .rate_hz        = 1000000,
+};
 static struct clk *periph_clocks[] __initdata = {
        &pioA_clk,
@@ -178,6 +183,7 @@ static struct clk *periph_clocks[] __initdata = {
        &udphs_clk,
        &lcdc_clk,
        &ac97_clk,
+        &adc_op_clk,
        // irq0
 };
@@ -216,6 +222,7 @@ static struct clk_lookup periph_clocks_lookups[] = {
        CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioB_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioC_clk),
        CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioD_clk),
+        CLKDEV_CON_ID("adc_clk", &tsc_clk),
 };
 static struct clk_lookup usart_clocks_lookups[] = {
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 428fc412aaf1..0b1d71a7d9bf 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -23,9 +23,11 @@
 #include <mach/at91sam9_smc.h>
 #include <mach/hardware.h>
 #include <linux/platform_data/dma-atmel.h>
+#include <linux/platform_data/at91_adc.h>
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 /* --------------------------------------------------------------------
@@ -608,14 +610,13 @@ static void __init at91_add_device_tc(void) { }
 /* --------------------------------------------------------------------
- *  Touchscreen
+ *  ADC and Touchscreen
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
+#if IS_ENABLED(CONFIG_AT91_ADC)
-static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
+static struct at91_adc_data adc_data;
-static struct at91_tsadcc_data tsadcc_data;
-static struct resource tsadcc_resources[] = {
+static struct resource adc_resources[] = {
        [0] = {
                .start  = AT91SAM9RL_BASE_TSC,
                .end    = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
@@ -628,36 +629,71 @@ static struct resource tsadcc_resources[] = {
        }
 };
-static struct platform_device at91sam9rl_tsadcc_device = {
+static struct platform_device at91_adc_device = {
-        .name           = "atmel_tsadcc",
+        .name           = "at91sam9rl-adc",
-        .id             = -1,
+        .id             = -1,
-        .dev            = {
+        .dev            = {
-                                .dma_mask               = &tsadcc_dmamask,
+                .platform_data  = &adc_data,
-                                .coherent_dma_mask      = DMA_BIT_MASK(32),
-                                .platform_data          = &tsadcc_data,
        },
-        .resource       = tsadcc_resources,
+        .resource       = adc_resources,
-        .num_resources  = ARRAY_SIZE(tsadcc_resources),
+        .num_resources  = ARRAY_SIZE(adc_resources),
 };
-void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
+static struct at91_adc_trigger at91_adc_triggers[] = {
+        [0] = {
+                .name = "external-rising",
+                .value = 1,
+                .is_external = true,
+        },
+        [1] = {
+                .name = "external-falling",
+                .value = 2,
+                .is_external = true,
+        },
+        [2] = {
+                .name = "external-any",
+                .value = 3,
+                .is_external = true,
+        },
+        [3] = {
+                .name = "continuous",
+                .value = 6,
+                .is_external = false,
+        },
+};
+void __init at91_add_device_adc(struct at91_adc_data *data)
 {
        if (!data)
                return;
-        at91_set_A_periph(AT91_PIN_PA17, 0);    /* AD0_XR */
+        if (test_bit(0, &data->channels_used))
-        at91_set_A_periph(AT91_PIN_PA18, 0);    /* AD1_XL */
+                at91_set_A_periph(AT91_PIN_PA17, 0);
-        at91_set_A_periph(AT91_PIN_PA19, 0);    /* AD2_YT */
+        if (test_bit(1, &data->channels_used))
-        at91_set_A_periph(AT91_PIN_PA20, 0);    /* AD3_TB */
+                at91_set_A_periph(AT91_PIN_PA18, 0);
+        if (test_bit(2, &data->channels_used))
-        tsadcc_data = *data;
+                at91_set_A_periph(AT91_PIN_PA19, 0);
-        platform_device_register(&at91sam9rl_tsadcc_device);
+        if (test_bit(3, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PA20, 0);
+        if (test_bit(4, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PD6, 0);
+        if (test_bit(5, &data->channels_used))
+                at91_set_A_periph(AT91_PIN_PD7, 0);
+        if (data->use_external_triggers)
+                at91_set_A_periph(AT91_PIN_PB15, 0);
+        data->startup_time = 40;
+        data->trigger_number = 4;
+        data->trigger_list = at91_adc_triggers;
+        adc_data = *data;
+        platform_device_register(&at91_adc_device);
 }
 #else
-void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
+void __init at91_add_device_adc(struct at91_adc_data *data) {}
 #endif
 /* --------------------------------------------------------------------
 *  RTC
 * -------------------------------------------------------------------- */
@@ -957,7 +993,6 @@ static struct resource dbgu_resources[] = {
 static struct atmel_uart_data dbgu_data = {
        .use_dma_tx     = 0,
        .use_dma_rx     = 0,            /* DBGU not capable of receive DMA */
-        .rts_gpio       = -EINVAL,
 };
 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
@@ -996,7 +1031,6 @@ static struct resource uart0_resources[] = {
 static struct atmel_uart_data uart0_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart0_dmamask = DMA_BIT_MASK(32);
@@ -1048,7 +1082,6 @@ static struct resource uart1_resources[] = {
 static struct atmel_uart_data uart1_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart1_dmamask = DMA_BIT_MASK(32);
@@ -1092,7 +1125,6 @@ static struct resource uart2_resources[] = {
 static struct atmel_uart_data uart2_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart2_dmamask = DMA_BIT_MASK(32);
@@ -1136,7 +1168,6 @@ static struct resource uart3_resources[] = {
 static struct atmel_uart_data uart3_data = {
        .use_dma_tx     = 1,
        .use_dma_rx     = 1,
-        .rts_gpio       = -EINVAL,
 };
 static u64 uart3_dmamask = DMA_BIT_MASK(32);
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 9ad781d5ee7c..028268ff3722 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -19,9 +19,10 @@
 #include "board.h"
 #include "soc.h"
 #include "generic.h"
-#include "clock.h"
 #include "sam9_smc.h"
+#if defined(CONFIG_OLD_CLK_AT91)
+#include "clock.h"
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
@@ -313,6 +314,9 @@ static void __init at91sam9x5_register_clocks(void)
        clk_register(&pck0);
        clk_register(&pck1);
 }
+#else
+#define at91sam9x5_register_clocks      NULL
+#endif
 /* --------------------------------------------------------------------
 *  AT91SAM9x5 processor initialization
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 35ab632bbf68..3f6dbcc34022 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -39,7 +39,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init onearm_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index f95e31cda4b3..597c649170aa 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -46,6 +46,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init afeb9260_init_early(void)
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 112e867c4abe..a30502c8d379 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -44,6 +44,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init cam60_init_early(void)
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 92983050a9bd..47313d3ee037 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -39,6 +39,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init carmeva_init_early(void)
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 008527efdbcf..2037f78c84e7 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -48,6 +48,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init cpu9krea_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 42f1353a4baf..c094350c9314 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -43,6 +43,8 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static struct gpio_led cpuat91_leds[] = {
        {
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index e5fde215225b..0e35a45cf8d4 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -42,7 +42,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init csb337_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index fdf11061c577..18d027f529a8 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -39,6 +39,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init csb637_init_early(void)
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index f9be8161bbfa..aa457a8b22f5 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -38,6 +38,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init eb9200_init_early(void)
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index b2fcd71262ba..ede1373ccaba 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -42,6 +42,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ecb_at91init_early(void)
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 77de410efc90..4e75321a8f2a 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -31,6 +31,8 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init eco920_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 737c08563628..68f1ab6bd08f 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -37,6 +37,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init flexibity_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index c20a870ea9c9..8b22c60bb238 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -47,6 +47,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 /*
 * The FOX Board G20 hardware comes as the "Netus G20" board with
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 416bae8435ee..b729dd1271bf 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -39,6 +39,7 @@
 #include "generic.h"
 #include "gsia18s.h"
 #include "stamp9g20.h"
+#include "gpio.h"
 static void __init gsia18s_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index 88e2f5d2d16d..93b1df42f639 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -39,6 +39,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init kafa_init_early(void)
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 0c519d9ebffc..d58d36225e08 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -42,6 +42,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init kb9202_init_early(void)
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 5f25fa54eb93..b48d95ec5152 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -37,6 +37,7 @@
 #include "sam9_smc.h"
 #include "generic.h"
 #include "stamp9g20.h"
+#include "gpio.h"
 static void __init pcontrol_g20_init_early(void)
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index ab2b2ec36c14..2c0f2d554d84 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -43,6 +43,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init picotux200_init_early(void)
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 8b17dadc1aba..953cea416754 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -45,6 +45,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index f6d7f1958c7e..f28e8b74df4b 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -31,6 +31,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init rsi_ews_init_early(void)
 {
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index 43ee4dc43b50..d24dda67e2d3 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -43,6 +43,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index f4f8735315da..65dea12d685e 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -49,6 +49,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 473546b9408b..4637432de08f 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -53,6 +53,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 2f931915c80c..cd2726ee5add 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -52,6 +52,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index f9cd1f2c7146..e1be6e25b380 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -50,6 +50,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 /*
 * board revision encoding
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index ef39078c8ce2..1ea61328f30d 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -50,6 +50,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
@@ -300,21 +301,13 @@ static struct atmel_lcdfb_pdata __initdata ek_lcdc_data;
 /*
- * Touchscreen
+ * ADCs and touchscreen
- */
-static struct at91_tsadcc_data ek_tsadcc_data = {
-        .adc_clock              = 300000,
-        .pendet_debounce        = 0x0d,
-        .ts_sample_hold_time    = 0x0a,
-};
-/*
- * ADCs
 */
 static struct at91_adc_data ek_adc_data = {
        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6) | BIT(7),
        .use_external_triggers = true,
        .vref = 3300,
+        .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
 };
 /*
@@ -485,9 +478,7 @@ static void __init ek_board_init(void)
        at91_add_device_isi(&isi_data, true);
        /* LCD Controller */
        at91_add_device_lcdc(&ek_lcdc_data);
-        /* Touch Screen */
+        /* ADC and touchscreen */
-        at91_add_device_tsadcc(&ek_tsadcc_data);
-        /* ADC */
        at91_add_device_adc(&ek_adc_data);
        /* Push Buttons */
        ek_add_device_buttons();
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index 604eecf6cd70..b64648b4a1fc 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -18,6 +18,7 @@
 #include <linux/clk.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/platform_data/at91_adc.h>
 #include <video/atmel_lcdc.h>
@@ -38,6 +39,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init ek_init_early(void)
@@ -229,12 +231,13 @@ static struct gpio_led ek_leds[] = {
 /*
- * Touchscreen
+ * ADC + Touchscreen
 */
-static struct at91_tsadcc_data ek_tsadcc_data = {
+static struct at91_adc_data ek_adc_data = {
-        .adc_clock              = 1000000,
+        .channels_used = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5),
-        .pendet_debounce        = 0x0f,
+        .use_external_triggers = true,
-        .ts_sample_hold_time    = 0x03,
+        .vref = 3300,
+        .touchscreen_type = ATMEL_ADC_TOUCHSCREEN_4WIRE,
 };
@@ -310,8 +313,8 @@ static void __init ek_board_init(void)
        at91_add_device_lcdc(&ek_lcdc_data);
        /* AC97 */
        at91_add_device_ac97(&ek_ac97_data);
-        /* Touch Screen Controller */
+        /* Touch Screen Controller + ADC */
-        at91_add_device_tsadcc(&ek_tsadcc_data);
+        at91_add_device_adc(&ek_adc_data);
        /* LEDs */
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
        /* Push Buttons */
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index f1d49e929ccb..1b870e6def0c 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -38,6 +38,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 #define SNAPPER9260_IO_EXP_GPIO(x)      (NR_BUILTIN_GPIO + (x))
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index e4a5ac17cdbc..3b575036ff96 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -32,6 +32,7 @@
 #include "board.h"
 #include "sam9_smc.h"
 #include "generic.h"
+#include "gpio.h"
 void __init stamp9g20_init_early(void)
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index be083771df2e..46fdb0c68a68 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -50,6 +50,7 @@
 #include "at91_aic.h"
 #include "board.h"
 #include "generic.h"
+#include "gpio.h"
 static void __init yl9200_init_early(void)
diff --git a/arch/arm/mach-at91/board.h b/arch/arm/mach-at91/board.h
index 6c08b341167d..4e773b55bc2d 100644
--- a/arch/arm/mach-at91/board.h
+++ b/arch/arm/mach-at91/board.h
@@ -118,9 +118,6 @@ struct isi_platform_data;
 extern void __init at91_add_device_isi(struct isi_platform_data *data,
                bool use_pck_as_mck);
- /* Touchscreen Controller */
-extern void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data);
 /* CAN */
 extern void __init at91_add_device_can(struct at91_can_data *data);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index a5afcf76550e..d3f05aaad8ba 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -29,6 +29,7 @@
 #include <mach/at91_pio.h>
 #include "generic.h"
+#include "gpio.h"
 #define MAX_NB_GPIO_PER_BANK    32
@@ -49,6 +50,7 @@ static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
+static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset);
 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                         unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
@@ -60,6 +62,7 @@ static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
                .chip = {                                               \
                        .label            = name,                       \
                        .request          = at91_gpiolib_request,       \
+                        .get_direction    = at91_gpiolib_get_direction, \
                        .direction_input  = at91_gpiolib_direction_input, \
                        .direction_output = at91_gpiolib_direction_output, \
                        .get              = at91_gpiolib_get,           \
@@ -799,6 +802,17 @@ static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
        return 0;
 }
+static int at91_gpiolib_get_direction(struct gpio_chip *chip, unsigned offset)
+{
+        struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
+        void __iomem *pio = at91_gpio->regbase;
+        unsigned mask = 1 << offset;
+        u32 osr;
+        osr = __raw_readl(pio + PIO_OSR);
+        return !(osr & mask);
+}
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset)
 {
diff --git a/arch/arm/mach-at91/include/mach/gpio.h b/arch/arm/mach-at91/gpio.h
index 5fc23771c154..eed465ab0dd7 100644
--- a/arch/arm/mach-at91/include/mach/gpio.h
+++ b/arch/arm/mach-at91/gpio.h
@@ -209,14 +209,6 @@ extern int at91_get_gpio_value(unsigned pin);
 extern void at91_gpio_suspend(void);
 extern void at91_gpio_resume(void);
-#ifdef CONFIG_PINCTRL_AT91
-extern void at91_pinctrl_gpio_suspend(void);
-extern void at91_pinctrl_gpio_resume(void);
-#else
-static inline void at91_pinctrl_gpio_suspend(void) {}
-static inline void at91_pinctrl_gpio_resume(void) {}
-#endif
 #endif  /* __ASSEMBLY__ */
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_adc.h b/arch/arm/mach-at91/include/mach/at91_adc.h
deleted file mode 100644
index c287307b9a3b..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_adc.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_adc.h
- *
- * Copyright (C) SAN People
- *
- * Analog-to-Digital Converter (ADC) registers.
- * Based on AT91SAM9260 datasheet revision D.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91_ADC_H
-#define AT91_ADC_H
-#define AT91_ADC_CR             0x00            /* Control Register */
-#define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
-#define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
-#define AT91_ADC_MR             0x04            /* Mode Register */
-#define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
-#define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
-#define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
-#define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
-#define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
-#define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
-#define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
-#define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
-#define         AT91_ADC_PRESCAL_9260   (0x3f << 8)     /* Prescalar Rate Selection */
-#define         AT91_ADC_PRESCAL_9G45   (0xff << 8)
-#define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
-#define         AT91_ADC_STARTUP_9260   (0x1f << 16)    /* Startup Up Time */
-#define         AT91_ADC_STARTUP_9G45   (0x7f << 16)
-#define         AT91_ADC_STARTUP_9X5    (0xf << 16)
-#define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
-#define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
-#define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
-#define AT91_ADC_CHER           0x10            /* Channel Enable Register */
-#define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
-#define AT91_ADC_CHSR           0x18            /* Channel Status Register */
-#define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
-#define AT91_ADC_SR             0x1C            /* Status Register */
-#define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
-#define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
-#define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
-#define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
-#define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
-#define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
-#define AT91_ADC_SR_9X5         0x30            /* Status Register for 9x5 */
-#define         AT91_ADC_SR_DRDY_9X5    (1 << 24)       /* Data Ready */
-#define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
-#define         AT91_ADC_LDATA          (0x3ff)
-#define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
-#define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
-#define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
-#define         AT91_ADC_IER_PEN        (1 << 29)
-#define         AT91_ADC_IER_NOPEN      (1 << 30)
-#define         AT91_ADC_IER_XRDY       (1 << 20)
-#define         AT91_ADC_IER_YRDY       (1 << 21)
-#define         AT91_ADC_IER_PRDY       (1 << 22)
-#define         AT91_ADC_ISR_PENS       (1 << 31)
-#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4))      /* Channel Data Register N */
-#define         AT91_ADC_DATA           (0x3ff)
-#define AT91_ADC_CDR0_9X5       (0x50)                  /* Channel Data Register 0 for 9X5 */
-#define AT91_ADC_ACR            0x94    /* Analog Control Register */
-#define         AT91_ADC_ACR_PENDETSENS (0x3 << 0)      /* pull-up resistor */
-#define AT91_ADC_TSMR           0xB0
-#define         AT91_ADC_TSMR_TSMODE    (3 << 0)        /* Touch Screen Mode */
-#define                 AT91_ADC_TSMR_TSMODE_NONE               (0 << 0)
-#define                 AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS     (1 << 0)
-#define                 AT91_ADC_TSMR_TSMODE_4WIRE_PRESS        (2 << 0)
-#define                 AT91_ADC_TSMR_TSMODE_5WIRE              (3 << 0)
-#define         AT91_ADC_TSMR_TSAV      (3 << 4)        /* Averages samples */
-#define                 AT91_ADC_TSMR_TSAV_(x)          ((x) << 4)
-#define         AT91_ADC_TSMR_SCTIM     (0x0f << 16)    /* Switch closure time */
-#define         AT91_ADC_TSMR_PENDBC    (0x0f << 28)    /* Pen Debounce time */
-#define                 AT91_ADC_TSMR_PENDBC_(x)        ((x) << 28)
-#define         AT91_ADC_TSMR_NOTSDMA   (1 << 22)       /* No Touchscreen DMA */
-#define         AT91_ADC_TSMR_PENDET_DIS        (0 << 24)       /* Pen contact detection disable */
-#define         AT91_ADC_TSMR_PENDET_ENA        (1 << 24)       /* Pen contact detection enable */
-#define AT91_ADC_TSXPOSR        0xB4
-#define AT91_ADC_TSYPOSR        0xB8
-#define AT91_ADC_TSPRESSR       0xBC
-#define AT91_ADC_TRGR_9260      AT91_ADC_MR
-#define AT91_ADC_TRGR_9G45      0x08
-#define AT91_ADC_TRGR_9X5       0xC0
-/* Trigger Register bit field */
-#define         AT91_ADC_TRGR_TRGPER    (0xffff << 16)
-#define                 AT91_ADC_TRGR_TRGPER_(x)        ((x) << 16)
-#define         AT91_ADC_TRGR_TRGMOD    (0x7 << 0)
-#define                 AT91_ADC_TRGR_MOD_PERIOD_TRIG   (5 << 0)
-#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index f17aa3150019..56338245653a 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -104,5 +104,20 @@
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
+/*
+ * FIXME: this is needed to communicate between the pinctrl driver and
+ * the PM implementation in the machine. Possibly part of the PM
+ * implementation should be moved down into the pinctrl driver and get
+ * called as part of the generic suspend/resume path.
+ */
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PINCTRL_AT91
+extern void at91_pinctrl_gpio_suspend(void);
+extern void at91_pinctrl_gpio_resume(void);
+#else
+static inline void at91_pinctrl_gpio_suspend(void) {}
+static inline void at91_pinctrl_gpio_resume(void) {}
+#endif
+#endif
 #endif
diff --git a/arch/arm/mach-at91/leds.c b/arch/arm/mach-at91/leds.c
index 3e22978b5547..77c4d8fd03fd 100644
--- a/arch/arm/mach-at91/leds.c
+++ b/arch/arm/mach-at91/leds.c
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include "board.h"
+#include "gpio.h"
 /* ------------------------------------------------------------------------- */
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 8bda1cefdf96..e95554532987 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -32,6 +32,7 @@
 #include "at91_aic.h"
 #include "generic.h"
 #include "pm.h"
+#include "gpio.h"
 /*
 * Show the reason for the previous system reset.
diff --git a/arch/arm/mach-at91/sysirq_mask.c b/arch/arm/mach-at91/sysirq_mask.c
index 2ba694f9626b..f8bc3511a8c8 100644
--- a/arch/arm/mach-at91/sysirq_mask.c
+++ b/arch/arm/mach-at91/sysirq_mask.c
@@ -25,24 +25,28 @@
 #include "generic.h"
-#define AT91_RTC_IDR    0x24    /* Interrupt Disable Register */
+#define AT91_RTC_IDR            0x24    /* Interrupt Disable Register */
-#define AT91_RTC_IMR    0x28    /* Interrupt Mask Register */
+#define AT91_RTC_IMR            0x28    /* Interrupt Mask Register */
+#define AT91_RTC_IRQ_MASK       0x1f    /* Available IRQs mask */
 void __init at91_sysirq_mask_rtc(u32 rtc_base)
 {
        void __iomem *base;
-        u32 mask;
        base = ioremap(rtc_base, 64);
        if (!base)
                return;
-        mask = readl_relaxed(base + AT91_RTC_IMR);
+        /*
-        if (mask) {
+         * sam9x5 SoCs have the following errata:
-                pr_info("AT91: Disabling rtc irq\n");
+         * "RTC: Interrupt Mask Register cannot be used
-                writel_relaxed(mask, base + AT91_RTC_IDR);
+         *  Interrupt Mask Register read always returns 0."
-                (void)readl_relaxed(base + AT91_RTC_IMR);       /* flush */
+         *
-        }
+         * Hence we're not relying on IMR values to disable
+         * interrupts.
+         */
+        writel_relaxed(AT91_RTC_IRQ_MASK, base + AT91_RTC_IDR);
+        (void)readl_relaxed(base + AT91_RTC_IMR);       /* flush */
        iounmap(base);
 }
diff --git a/arch/arm/mach-axxia/Kconfig b/arch/arm/mach-axxia/Kconfig
new file mode 100644
index 000000000000..8be7e0ae1922
--- /dev/null
+++ b/arch/arm/mach-axxia/Kconfig
@@ -0,0 +1,16 @@
+config ARCH_AXXIA
+        bool "LSI Axxia platforms" if (ARCH_MULTI_V7 && ARM_LPAE)
+        select ARCH_DMA_ADDR_T_64BIT
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_TIMER_SP804
+        select HAVE_ARM_ARCH_TIMER
+        select MFD_SYSCON
+        select MIGHT_HAVE_PCI
+        select PCI_DOMAINS if PCI
+        select ZONE_DMA
+        help
+          This enables support for the LSI Axxia devices.
+          The LSI Axxia platforms require a Flattened Device Tree to be passed
+          to the kernel.
diff --git a/arch/arm/mach-axxia/Makefile b/arch/arm/mach-axxia/Makefile
new file mode 100644
index 000000000000..ec4f68b460c6
--- /dev/null
+++ b/arch/arm/mach-axxia/Makefile
@@ -0,0 +1,2 @@
+obj-y                           += axxia.o
+obj-$(CONFIG_SMP)               += platsmp.o
diff --git a/arch/arm/mach-axxia/axxia.c b/arch/arm/mach-axxia/axxia.c
new file mode 100644
index 000000000000..19e5a1d95397
--- /dev/null
+++ b/arch/arm/mach-axxia/axxia.c
@@ -0,0 +1,28 @@
+/*
+ * Support for the LSI Axxia SoC devices based on ARM cores.
+ *
+ * Copyright (C) 2012 LSI
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#include <linux/init.h>
+#include <asm/mach/arch.h>
+static const char *axxia_dt_match[] __initconst = {
+        "lsi,axm5516",
+        "lsi,axm5516-sim",
+        "lsi,axm5516-emu",
+        NULL
+};
+DT_MACHINE_START(AXXIA_DT, "LSI Axxia AXM55XX")
+        .dt_compat = axxia_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-axxia/platsmp.c b/arch/arm/mach-axxia/platsmp.c
new file mode 100644
index 000000000000..959d4df3d2b6
--- /dev/null
+++ b/arch/arm/mach-axxia/platsmp.c
@@ -0,0 +1,89 @@
+/*
+ * linux/arch/arm/mach-axxia/platsmp.c
+ *
+ * Copyright (C) 2012 LSI Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/smp.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/cacheflush.h>
+/* Syscon register offsets for releasing cores from reset */
+#define SC_CRIT_WRITE_KEY       0x1000
+#define SC_RST_CPU_HOLD         0x1010
+/*
+ * Write the kernel entry point for secondary CPUs to the specified address
+ */
+static void write_release_addr(u32 release_phys)
+{
+        u32 *virt = (u32 *) phys_to_virt(release_phys);
+        writel_relaxed(virt_to_phys(secondary_startup), virt);
+        /* Make sure this store is visible to other CPUs */
+        smp_wmb();
+        __cpuc_flush_dcache_area(virt, sizeof(u32));
+}
+static int axxia_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+        struct device_node *syscon_np;
+        void __iomem *syscon;
+        u32 tmp;
+        syscon_np = of_find_compatible_node(NULL, NULL, "lsi,axxia-syscon");
+        if (!syscon_np)
+                return -ENOENT;
+        syscon = of_iomap(syscon_np, 0);
+        if (!syscon)
+                return -ENOMEM;
+        tmp = readl(syscon + SC_RST_CPU_HOLD);
+        writel(0xab, syscon + SC_CRIT_WRITE_KEY);
+        tmp &= ~(1 << cpu);
+        writel(tmp, syscon + SC_RST_CPU_HOLD);
+        return 0;
+}
+static void __init axxia_smp_prepare_cpus(unsigned int max_cpus)
+{
+        int cpu_count = 0;
+        int cpu;
+        /*
+         * Initialise the present map, which describes the set of CPUs actually
+         * populated at the present time.
+         */
+        for_each_possible_cpu(cpu) {
+                struct device_node *np;
+                u32 release_phys;
+                np = of_get_cpu_node(cpu, NULL);
+                if (!np)
+                        continue;
+                if (of_property_read_u32(np, "cpu-release-addr", &release_phys))
+                        continue;
+                if (cpu_count < max_cpus) {
+                        set_cpu_present(cpu, true);
+                        cpu_count++;
+                }
+                if (release_phys != 0)
+                        write_release_addr(release_phys);
+        }
+}
+static struct smp_operations axxia_smp_ops __initdata = {
+        .smp_prepare_cpus       = axxia_smp_prepare_cpus,
+        .smp_boot_secondary     = axxia_boot_secondary,
+};
+CPU_METHOD_OF_DECLARE(axxia_smp, "lsi,syscon-release", &axxia_smp_ops);
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 49c914cd9c7a..9bc6db1c1348 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -1,31 +1,58 @@
 config ARCH_BCM
-        bool "Broadcom SoC Support"
+        bool "Broadcom SoC Support" if ARCH_MULTI_V6_V7
-        depends on ARCH_MULTIPLATFORM
        help
-          This enables support for Broadcom ARM based SoC
+          This enables support for Broadcom ARM based SoC chips
-          chips
-if ARCH_BCM
 menu "Broadcom SoC Selection"
+        depends on ARCH_BCM
 config ARCH_BCM_MOBILE
-        bool "Broadcom Mobile SoC" if ARCH_MULTI_V7
+        bool "Broadcom Mobile SoC Support" if ARCH_MULTI_V7
-        depends on MMU
        select ARCH_REQUIRE_GPIOLIB
        select ARM_ERRATA_754322
        select ARM_ERRATA_764369 if SMP
+        select ARM_ERRATA_775420
        select ARM_GIC
        select GPIO_BCM_KONA
        select TICK_ONESHOT
-        select CACHE_L2X0
        select HAVE_ARM_ARCH_TIMER
        select PINCTRL
        help
          This enables support for systems based on Broadcom mobile SoCs.
-          It currently supports the 'BCM281XX' family, which includes
-          BCM11130, BCM11140, BCM11351, BCM28145 and
+if ARCH_BCM_MOBILE
-          BCM28155 variants.
+menu "Broadcom Mobile SoC Selection"
+config ARCH_BCM_281XX
+        bool "Broadcom BCM281XX SoC family"
+        default y
+        help
+          Enable support for the the BCM281XX family, which includes
+          BCM11130, BCM11140, BCM11351, BCM28145 and BCM28155
+          variants.
+config ARCH_BCM_21664
+        bool "Broadcom BCM21664 SoC family"
+        default y
+        help
+          Enable support for the the BCM21664 family, which includes
+          BCM21663 and BCM21664 variants.
+config ARCH_BCM_MOBILE_L2_CACHE
+        bool "Broadcom mobile SoC level 2 cache support"
+        depends on (ARCH_BCM_281XX || ARCH_BCM_21664)
+        default y
+        select CACHE_L2X0
+        select ARCH_BCM_MOBILE_SMC
+config ARCH_BCM_MOBILE_SMC
+        bool
+        depends on ARCH_BCM_281XX || ARCH_BCM_21664
+endmenu
+endif
 config ARCH_BCM2835
        bool "Broadcom BCM2835 family" if ARCH_MULTI_V6
@@ -33,10 +60,7 @@ config ARCH_BCM2835
        select ARM_AMBA
        select ARM_ERRATA_411920
        select ARM_TIMER_SP804
-        select CLKDEV_LOOKUP
        select CLKSRC_OF
-        select CPU_V6
-        select GENERIC_CLOCKEVENTS
        select PINCTRL
        select PINCTRL_BCM2835
        help
@@ -45,17 +69,12 @@ config ARCH_BCM2835
 config ARCH_BCM_5301X
        bool "Broadcom BCM470X / BCM5301X ARM SoC" if ARCH_MULTI_V7
-        depends on MMU
        select ARM_GIC
        select CACHE_L2X0
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select HAVE_SMP
-        select COMMON_CLK
-        select GENERIC_CLOCKEVENTS
        select ARM_GLOBAL_TIMER
        select CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
-        select MIGHT_HAVE_PCI
        help
          Support for Broadcom BCM470X and BCM5301X SoCs with ARM CPU cores.
@@ -70,5 +89,3 @@ config ARCH_BCM_5301X
          network SoC using a MIPS CPU, they are supported by arch/mips/bcm47xx
 endmenu
-endif
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index a326b28c4406..731292114975 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -10,10 +10,23 @@
 # of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
-obj-$(CONFIG_ARCH_BCM_MOBILE)   := board_bcm281xx.o board_bcm21664.o \
+# BCM281XX
-                                bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
+obj-$(CONFIG_ARCH_BCM_281XX)    += board_bcm281xx.o
+# BCM21664
+obj-$(CONFIG_ARCH_BCM_21664)    += board_bcm21664.o
+# BCM281XX and BCM21664 L2 cache control
+obj-$(CONFIG_ARCH_BCM_MOBILE_L2_CACHE) += kona_l2_cache.o
+# Support for secure monitor traps
+obj-$(CONFIG_ARCH_BCM_MOBILE_SMC) += bcm_kona_smc.o
+ifeq ($(call as-instr,.arch_extension sec,as_has_sec),as_has_sec)
+CFLAGS_bcm_kona_smc.o           += -Wa,-march=armv7-a+sec -DREQUIRES_SEC
+endif
+# BCM2835
 obj-$(CONFIG_ARCH_BCM2835)      += board_bcm2835.o
-plus_sec := $(call as-instr,.arch_extension sec,+sec)
+# BCM5301X
-AFLAGS_bcm_kona_smc_asm.o       :=-Wa,-march=armv7-a$(plus_sec)
 obj-$(CONFIG_ARCH_BCM_5301X)    += bcm_5301x.o
diff --git a/arch/arm/mach-bcm/bcm_5301x.c b/arch/arm/mach-bcm/bcm_5301x.c
index edff69761e04..e9bcbdbce555 100644
--- a/arch/arm/mach-bcm/bcm_5301x.c
+++ b/arch/arm/mach-bcm/bcm_5301x.c
@@ -43,19 +43,14 @@ static void __init bcm5301x_init_early(void)
                        "imprecise external abort");
 }
-static void __init bcm5301x_dt_init(void)
-{
-        l2x0_of_init(0, ~0UL);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char __initconst *bcm5301x_dt_compat[] = {
        "brcm,bcm4708",
        NULL,
 };
 DT_MACHINE_START(BCM5301X, "BCM5301X")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .init_early     = bcm5301x_init_early,
-        .init_machine   = bcm5301x_dt_init,
        .dt_compat      = bcm5301x_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 5e31e918f325..a55a7ecf146a 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -21,11 +21,8 @@
 #include "bcm_kona_smc.h"
-struct secure_bridge_data {
+static u32              bcm_smc_buffer_phys;    /* physical address */
-        void __iomem *bounce;           /* virtual address */
+static void __iomem     *bcm_smc_buffer;        /* virtual address */
-        u32 __iomem buffer_addr;        /* physical address */
-        int initialized;
-} bridge_data;
 struct bcm_kona_smc_data {
        unsigned service_id;
@@ -33,6 +30,7 @@ struct bcm_kona_smc_data {
        unsigned arg1;
        unsigned arg2;
        unsigned arg3;
+        unsigned result;
 };
 static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
@@ -41,59 +39,125 @@ static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
        {},
 };
-/* Map in the bounce area */
+/* Map in the args buffer area */
 int __init bcm_kona_smc_init(void)
 {
        struct device_node *node;
+        const __be32 *prop_val;
+        u64 prop_size = 0;
+        unsigned long buffer_size;
+        u32 buffer_phys;
        /* Read buffer addr and size from the device tree node */
        node = of_find_matching_node(NULL, bcm_kona_smc_ids);
        if (!node)
                return -ENODEV;
-        /* Don't care about size or flags of the DT node */
+        prop_val = of_get_address(node, 0, &prop_size, NULL);
-        bridge_data.buffer_addr =
+        if (!prop_val)
-                be32_to_cpu(*of_get_address(node, 0, NULL, NULL));
+                return -EINVAL;
-        BUG_ON(!bridge_data.buffer_addr);
-        bridge_data.bounce = of_iomap(node, 0);
+        /* We assume space for four 32-bit arguments */
-        BUG_ON(!bridge_data.bounce);
+        if (prop_size < 4 * sizeof(u32) || prop_size > (u64)ULONG_MAX)
+                return -EINVAL;
+        buffer_size = (unsigned long)prop_size;
-        bridge_data.initialized = 1;
+        buffer_phys = be32_to_cpup(prop_val);
+        if (!buffer_phys)
+                return -EINVAL;
+        bcm_smc_buffer = ioremap(buffer_phys, buffer_size);
+        if (!bcm_smc_buffer)
+                return -ENOMEM;
+        bcm_smc_buffer_phys = buffer_phys;
        pr_info("Kona Secure API initialized\n");
        return 0;
 }
+/*
+ * int bcm_kona_do_smc(u32 service_id, u32 buffer_addr)
+ *
+ * Only core 0 can run the secure monitor code.  If an "smc" request
+ * is initiated on a different core it must be redirected to core 0
+ * for execution.  We rely on the caller to handle this.
+ *
+ * Each "smc" request supplies a service id and the address of a
+ * buffer containing parameters related to the service to be
+ * performed.  A flags value defines the behavior of the level 2
+ * cache and interrupt handling while the secure monitor executes.
+ *
+ * Parameters to the "smc" request are passed in r4-r6 as follows:
+ *     r4       service id
+ *     r5       flags (SEC_ROM_*)
+ *     r6       physical address of buffer with other parameters
+ *
+ * Execution of an "smc" request produces two distinct results.
+ *
+ * First, the secure monitor call itself (regardless of the specific
+ * service request) can succeed, or can produce an error.  When an
+ * "smc" request completes this value is found in r12; it should
+ * always be SEC_EXIT_NORMAL.
+ *
+ * In addition, the particular service performed produces a result.
+ * The values that should be expected depend on the service.  We
+ * therefore return this value to the caller, so it can handle the
+ * request result appropriately.  This result value is found in r0
+ * when the "smc" request completes.
+ */
+static int bcm_kona_do_smc(u32 service_id, u32 buffer_phys)
+{
+        register u32 ip asm("ip");      /* Also called r12 */
+        register u32 r0 asm("r0");
+        register u32 r4 asm("r4");
+        register u32 r5 asm("r5");
+        register u32 r6 asm("r6");
+        r4 = service_id;
+        r5 = 0x3;               /* Keep IRQ and FIQ off in SM */
+        r6 = buffer_phys;
+        asm volatile (
+                /* Make sure we got the registers we want */
+                __asmeq("%0", "ip")
+                __asmeq("%1", "r0")
+                __asmeq("%2", "r4")
+                __asmeq("%3", "r5")
+                __asmeq("%4", "r6")
+#ifdef REQUIRES_SEC
+                ".arch_extension sec\n"
+#endif
+                "       smc    #0\n"
+                : "=r" (ip), "=r" (r0)
+                : "r" (r4), "r" (r5), "r" (r6)
+                : "r1", "r2", "r3", "r7", "lr");
+        BUG_ON(ip != SEC_EXIT_NORMAL);
+        return r0;
+}
 /* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
 static void __bcm_kona_smc(void *info)
 {
        struct bcm_kona_smc_data *data = info;
-        u32 *args = bridge_data.bounce;
+        u32 *args = bcm_smc_buffer;
-        int rc = 0;
-        /* Must run on CPU 0 */
        BUG_ON(smp_processor_id() != 0);
+        BUG_ON(!args);
-        /* Check map in the bounce area */
+        /* Copy the four 32 bit argument values into the bounce area */
-        BUG_ON(!bridge_data.initialized);
+        writel_relaxed(data->arg0, args++);
+        writel_relaxed(data->arg1, args++);
-        /* Copy one 32 bit word into the bounce area */
+        writel_relaxed(data->arg2, args++);
-        args[0] = data->arg0;
+        writel(data->arg3, args);
-        args[1] = data->arg1;
-        args[2] = data->arg2;
-        args[3] = data->arg3;
        /* Flush caches for input data passed to Secure Monitor */
-        if (data->service_id != SSAPI_BRCM_START_VC_CORE)
+        flush_cache_all();
-                flush_cache_all();
-        /* Trap into Secure Monitor */
-        rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr);
-        if (rc != SEC_ROM_RET_OK)
+        /* Trap into Secure Monitor and record the request result */
-                pr_err("Secure Monitor call failed (0x%x)!\n", rc);
+        data->result = bcm_kona_do_smc(data->service_id, bcm_smc_buffer_phys);
 }
 unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
@@ -106,17 +170,13 @@ unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
        data.arg1 = arg1;
        data.arg2 = arg2;
        data.arg3 = arg3;
+        data.result = 0;
        /*
         * Due to a limitation of the secure monitor, we must use the SMP
         * infrastructure to forward all secure monitor calls to Core 0.
         */
-        if (get_cpu() != 0)
+        smp_call_function_single(0, __bcm_kona_smc, &data, 1);
-                smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1);
-        else
-                __bcm_kona_smc(&data);
-        put_cpu();
+        return data.result;
-        return 0;
 }
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
index d098a7e76744..2e29ec67e414 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.h
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -15,55 +15,12 @@
 #define BCM_KONA_SMC_H
 #include <linux/types.h>
-#define FLAGS   (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \
-                        SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK)
-/*!
+/* Broadcom Secure Service API service IDs, return codes, and exit codes */
- * Definitions for IRQ & FIQ Mask for ARM
+#define SSAPI_ENABLE_L2_CACHE           0x01000002
- */
-#define FIQ_IRQ_MASK                                            0xC0
-#define FIQ_MASK                                                0x40
-#define IRQ_MASK                                                0x80
-/*!
- * Secure Mode FLAGs
- */
-/* When set, enables ICache within the secure mode */
-#define SEC_ROM_ICACHE_ENABLE_MASK                        0x00000001
-/* When set, enables DCache within the secure mode */
-#define SEC_ROM_DCACHE_ENABLE_MASK                        0x00000002
-/* When set, enables IRQ within the secure mode */
-#define SEC_ROM_IRQ_ENABLE_MASK                           0x00000004
-/* When set, enables FIQ within the secure mode */
-#define SEC_ROM_FIQ_ENABLE_MASK                           0x00000008
-/* When set, enables Unified L2 cache within the secure mode */
-#define SEC_ROM_UL2_CACHE_ENABLE_MASK                     0x00000010
-/* Broadcom Secure Service API Service IDs */
-#define SSAPI_DORMANT_ENTRY_SERV                          0x01000000
-#define SSAPI_PUBLIC_OTP_SERV                             0x01000001
-#define SSAPI_ENABLE_L2_CACHE                             0x01000002
-#define SSAPI_DISABLE_L2_CACHE                            0x01000003
-#define SSAPI_WRITE_SCU_STATUS                            0x01000004
-#define SSAPI_WRITE_PWR_GATE                              0x01000005
-/* Broadcom Secure Service API Return Codes */
 #define SEC_ROM_RET_OK                  0x00000001
-#define SEC_ROM_RET_FAIL                0x00000009
-#define SSAPI_RET_FROM_INT_SERV         0x4
 #define SEC_EXIT_NORMAL                 0x1
-#define SSAPI_ROW_AES                   0x0E000006
-#define SSAPI_BRCM_START_VC_CORE        0x0E000008
-#ifndef __ASSEMBLY__
 extern int __init bcm_kona_smc_init(void);
 extern unsigned bcm_kona_smc(unsigned service_id,
@@ -72,9 +29,4 @@ extern unsigned bcm_kona_smc(unsigned service_id,
                             unsigned arg2,
                             unsigned arg3);
-extern int bcm_kona_smc_asm(u32 service_id,
-                            u32 buffer_addr);
-#endif  /* __ASSEMBLY__ */
 #endif /* BCM_KONA_SMC_H */
diff --git a/arch/arm/mach-bcm/bcm_kona_smc_asm.S b/arch/arm/mach-bcm/bcm_kona_smc_asm.S
deleted file mode 100644
index a1608480d60d..000000000000
--- a/arch/arm/mach-bcm/bcm_kona_smc_asm.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/linkage.h>
-#include "bcm_kona_smc.h"
-/*
- * int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr)
- */
-ENTRY(bcm_kona_smc_asm)
-        stmfd   sp!, {r4-r12, lr}
-        mov     r4, r0          @ service_id
-        mov     r5, #3          @ Keep IRQ and FIQ off in SM
-        /*
-         * Since interrupts are disabled in the open mode, we must keep
-         * interrupts disabled in secure mode by setting R5=0x3. If interrupts
-         * are enabled in open mode, we can set R5=0x0 to allow interrupts in
-         * secure mode.  If we did this, the secure monitor would return back
-         * control to the open mode to handle the interrupt prior to completing
-         * the secure service. If this happened, R12 would not be
-         * SEC_EXIT_NORMAL and we would need to call SMC again after resetting
-         * R5 (it gets clobbered by the secure monitor) and setting R4 to
-         * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor
-         * to finish up the previous uncompleted secure service.
-         */
-        mov     r6, r1          @ buffer_addr
-        smc     #0
-        /* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */
-        ldmfd   sp!, {r4-r12, pc}
-ENDPROC(bcm_kona_smc_asm)
diff --git a/arch/arm/mach-bcm/board_bcm21664.c b/arch/arm/mach-bcm/board_bcm21664.c
index acc1573fd005..f0521cc0640d 100644
--- a/arch/arm/mach-bcm/board_bcm21664.c
+++ b/arch/arm/mach-bcm/board_bcm21664.c
@@ -11,14 +11,13 @@
 * GNU General Public License for more details.
 */
-#include <linux/clocksource.h>
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
+#include <linux/io.h>
 #include <asm/mach/arch.h>
-#include "bcm_kona_smc.h"
+#include "kona_l2_cache.h"
-#include "kona.h"
 #define RSTMGR_DT_STRING                "brcm,bcm21664-resetmgr"
diff --git a/arch/arm/mach-bcm/board_bcm281xx.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 6be54c10f8cb..1ac59fc0cb15 100644
--- a/arch/arm/mach-bcm/board_bcm281xx.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -17,7 +17,7 @@
 #include <asm/mach/arch.h>
-#include "kona.h"
+#include "kona_l2_cache.h"
 #define SECWDOG_OFFSET                  0x00000000
 #define SECWDOG_RESERVED_MASK           0xe2000000
diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona_l2_cache.c
index 768bc2837bf5..b31970377c20 100644
--- a/arch/arm/mach-bcm/kona.c
+++ b/arch/arm/mach-bcm/kona_l2_cache.c
@@ -11,19 +11,18 @@
 * GNU General Public License for more details.
 */
-#include <linux/of_platform.h>
+#include <linux/init.h>
+#include <linux/printk.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "bcm_kona_smc.h"
-#include "kona.h"
 void __init kona_l2_cache_init(void)
 {
+        unsigned int result;
        int ret;
-        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
-                return;
        ret = bcm_kona_smc_init();
        if (ret) {
                pr_info("Secure API not available (%d). Skipping L2 init.\n",
@@ -31,7 +30,12 @@ void __init kona_l2_cache_init(void)
                return;
        }
-        bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
+        result = bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
+        if (result != SEC_ROM_RET_OK) {
+                pr_err("Secure Monitor call failed (%u)! Skipping L2 init.\n",
+                        result);
+                return;
+        }
        /*
         * The aux_val and aux_mask have no effect since L2 cache is already
diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona_l2_cache.h
index 3a7a017c29cd..46f84a95ab1c 100644
--- a/arch/arm/mach-bcm/kona.h
+++ b/arch/arm/mach-bcm/kona_l2_cache.h
@@ -11,4 +11,8 @@
 * GNU General Public License for more details.
 */
-void __init kona_l2_cache_init(void);
+#ifdef CONFIG_ARCH_BCM_MOBILE_L2_CACHE
+void    kona_l2_cache_init(void);
+#else
+#define kona_l2_cache_init() ((void)0)
+#endif
diff --git a/arch/arm/mach-berlin/Kconfig b/arch/arm/mach-berlin/Kconfig
index b0cb0722acd2..101e0f356730 100644
--- a/arch/arm/mach-berlin/Kconfig
+++ b/arch/arm/mach-berlin/Kconfig
@@ -1,9 +1,11 @@
 config ARCH_BERLIN
        bool "Marvell Berlin SoCs" if ARCH_MULTI_V7
+        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
        select GENERIC_IRQ_CHIP
        select DW_APB_ICTL
        select DW_APB_TIMER_OF
+        select PINCTRL
 if ARCH_BERLIN
@@ -14,11 +16,19 @@ config MACH_BERLIN_BG2
        select CACHE_L2X0
        select CPU_PJ4B
        select HAVE_ARM_TWD if SMP
+        select PINCTRL_BERLIN_BG2
 config MACH_BERLIN_BG2CD
        bool "Marvell Armada 1500-mini (BG2CD)"
        select CACHE_L2X0
        select HAVE_ARM_TWD if SMP
+        select PINCTRL_BERLIN_BG2CD
+config MACH_BERLIN_BG2Q
+        bool "Marvell Armada 1500 Pro (BG2-Q)"
+        select CACHE_L2X0
+        select HAVE_ARM_TWD if SMP
+        select PINCTRL_BERLIN_BG2Q
 endmenu
diff --git a/arch/arm/mach-berlin/berlin.c b/arch/arm/mach-berlin/berlin.c
index 025bcb5473eb..ac181c6797ee 100644
--- a/arch/arm/mach-berlin/berlin.c
+++ b/arch/arm/mach-berlin/berlin.c
@@ -18,16 +18,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
-static void __init berlin_init_machine(void)
-{
-        /*
-         * with DT probing for L2CCs, berlin_init_machine can be removed.
-         * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
-         */
-        l2x0_of_init(0x70c00000, 0xfeffffff);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const berlin_dt_compat[] = {
        "marvell,berlin",
        NULL,
@@ -35,5 +25,10 @@ static const char * const berlin_dt_compat[] = {
 DT_MACHINE_START(BERLIN_DT, "Marvell Berlin")
        .dt_compat      = berlin_dt_compat,
-        .init_machine   = berlin_init_machine,
+        /*
+         * with DT probing for L2CCs, berlin_init_machine can be removed.
+         * Note: 88DE3005 (Armada 1500-mini) uses pl310 l2cc
+         */
+        .l2c_aux_val    = 0x30c00000,
+        .l2c_aux_mask   = 0xfeffffff,
 MACHINE_END
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c
index 221b9de32dd6..94a7add88a3f 100644
--- a/arch/arm/mach-clps711x/board-clep7312.c
+++ b/arch/arm/mach-clps711x/board-clep7312.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/types.h>
 #include <linux/string.h>
+#include <linux/memblock.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -26,11 +27,9 @@
 #include "common.h"
 static void __init
-fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
+fixup_clep7312(struct tag *tags, char **cmdline)
 {
-        mi->nr_banks=1;
+        memblock_add(0xc0000000, 0x01000000);
-        mi->bank[0].start = 0xc0000000;
-        mi->bank[0].size = 0x01000000;
 }
 MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 077609841f14..f9828f89972a 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -16,6 +16,7 @@
 #include <linux/interrupt.h>
 #include <linux/backlight.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
@@ -133,7 +134,7 @@ static void __init edb7211_reserve(void)
 }
 static void __init
-fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
+fixup_edb7211(struct tag *tags, char **cmdline)
 {
        /*
         * Bank start addresses are not present in the information
@@ -143,11 +144,8 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
         * Banks sizes _are_ present in the param block, but we're
         * not using that information yet.
         */
-        mi->bank[0].start = 0xc0000000;
+        memblock_add(0xc0000000, SZ_8M);
-        mi->bank[0].size = SZ_8M;
+        memblock_add(0xc1000000, SZ_8M);
-        mi->bank[1].start = 0xc1000000;
-        mi->bank[1].size = SZ_8M;
-        mi->nr_banks = 2;
 }
 static void __init edb7211_init(void)
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c
index 67b733744ed7..0cf0e51e6546 100644
--- a/arch/arm/mach-clps711x/board-p720t.c
+++ b/arch/arm/mach-clps711x/board-p720t.c
@@ -295,7 +295,7 @@ static struct generic_bl_info p720t_lcd_backlight_pdata = {
 };
 static void __init
-fixup_p720t(struct tag *tag, char **cmdline, struct meminfo *mi)
+fixup_p720t(struct tag *tag, char **cmdline)
 {
        /*
         * Our bootloader doesn't setup any tags (yet).
diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig
index dce8decd5d46..66838f42037f 100644
--- a/arch/arm/mach-cns3xxx/Kconfig
+++ b/arch/arm/mach-cns3xxx/Kconfig
@@ -1,7 +1,6 @@
 config ARCH_CNS3XXX
        bool "Cavium Networks CNS3XXX family" if ARCH_MULTI_V6
        select ARM_GIC
-        select MIGHT_HAVE_PCI
        select PCI_DOMAINS if PCI
        help
          Support for Cavium Networks CNS3XXX platform.
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 2ae28a69e3e5..f85449a6accd 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -272,9 +272,9 @@ void __init cns3xxx_l2x0_init(void)
         *
         * 1 cycle of latency for setup, read and write accesses
         */
-        val = readl(base + L2X0_TAG_LATENCY_CTRL);
+        val = readl(base + L310_TAG_LATENCY_CTRL);
        val &= 0xfffff888;
-        writel(val, base + L2X0_TAG_LATENCY_CTRL);
+        writel(val, base + L310_TAG_LATENCY_CTRL);
        /*
         * Data RAM Control register
@@ -285,12 +285,12 @@ void __init cns3xxx_l2x0_init(void)
         *
         * 1 cycle of latency for setup, read and write accesses
         */
-        val = readl(base + L2X0_DATA_LATENCY_CTRL);
+        val = readl(base + L310_DATA_LATENCY_CTRL);
        val &= 0xfffff888;
-        writel(val, base + L2X0_DATA_LATENCY_CTRL);
+        writel(val, base + L310_DATA_LATENCY_CTRL);
        /* 32 KiB, 8-way, parity disable */
-        l2x0_init(base, 0x00540000, 0xfe000fff);
+        l2x0_init(base, 0x00500000, 0xfe0f0fff);
 }
 #endif /* CONFIG_CACHE_L2X0 */
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index ecdc7d44fa70..06d63d5651f3 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -350,11 +350,7 @@ static struct davinci_mmc_config dm355evm_mmc_config = {
 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
 * the ID pin won't need any help.
 */
-#ifdef CONFIG_USB_MUSB_PERIPHERAL
-#define USB_ID_VALUE    0       /* ID pulled high; *should* float */
-#else
 #define USB_ID_VALUE    1       /* ID pulled low */
-#endif
 static struct spi_eeprom at25640a = {
        .byte_len       = SZ_64K / 8,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 43bacbf15314..680a7a2d9102 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -208,11 +208,7 @@ static struct davinci_mmc_config dm355leopard_mmc_config = {
 * you have proper Mini-B or Mini-A cables (or Mini-A adapters)
 * the ID pin won't need any help.
 */
-#ifdef CONFIG_USB_MUSB_PERIPHERAL
-#define USB_ID_VALUE    0       /* ID pulled high; *should* float */
-#else
 #define USB_ID_VALUE    1       /* ID pulled low */
-#endif
 static struct spi_eeprom at25640a = {
        .byte_len       = SZ_64K / 8,
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 85399c98f84a..45ce065e7170 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1092,20 +1092,21 @@ int da850_register_cpufreq(char *async_clk)
 static int da850_round_armrate(struct clk *clk, unsigned long rate)
 {
-        int i, ret = 0, diff;
+        int ret = 0, diff;
        unsigned int best = (unsigned int) -1;
        struct cpufreq_frequency_table *table = cpufreq_info.freq_table;
+        struct cpufreq_frequency_table *pos;
        rate /= 1000; /* convert to kHz */
-        for (i = 0; table[i].frequency != CPUFREQ_TABLE_END; i++) {
+        cpufreq_for_each_entry(pos, table) {
-                diff = table[i].frequency - rate;
+                diff = pos->frequency - rate;
                if (diff < 0)
                        diff = -diff;
                if (diff < best) {
                        best = diff;
-                        ret = table[i].frequency;
+                        ret = pos->frequency;
                }
        }
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 56ea41d5f849..b85b781b05fd 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -134,13 +134,6 @@ struct platform_device da8xx_serial_device[] = {
        }
 };
-static s8 da8xx_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1}
-};
 static s8 da8xx_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -148,12 +141,6 @@ static s8 da8xx_queue_priority_mapping[][2] = {
        {-1, -1}
 };
-static s8 da850_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {-1, -1}
-};
 static s8 da850_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -161,12 +148,6 @@ static s8 da850_queue_priority_mapping[][2] = {
 };
 static struct edma_soc_info da830_edma_cc0_info = {
-        .n_channel              = 32,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = da8xx_queue_tc_mapping,
        .queue_priority_mapping = da8xx_queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
@@ -177,22 +158,10 @@ static struct edma_soc_info *da830_edma_info[EDMA_MAX_CC] = {
 static struct edma_soc_info da850_edma_cc_info[] = {
        {
-                .n_channel              = 32,
-                .n_region               = 4,
-                .n_slot                 = 128,
-                .n_tc                   = 2,
-                .n_cc                   = 1,
-                .queue_tc_mapping       = da8xx_queue_tc_mapping,
                .queue_priority_mapping = da8xx_queue_priority_mapping,
                .default_queue          = EVENTQ_1,
        },
        {
-                .n_channel              = 32,
-                .n_region               = 4,
-                .n_slot                 = 128,
-                .n_tc                   = 1,
-                .n_cc                   = 1,
-                .queue_tc_mapping       = da850_queue_tc_mapping,
                .queue_priority_mapping = da850_queue_priority_mapping,
                .default_queue          = EVENTQ_0,
        },
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 07381d8cea62..2f3ed3a58d57 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -569,14 +569,6 @@ static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 static s8
-queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1},
-};
-static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -585,12 +577,6 @@ queue_priority_mapping[][2] = {
 };
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 08a61b938333..0ae8114f5cc9 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -853,16 +853,6 @@ static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /* Four Transfer Controllers on DM365 */
 static s8
-dm365_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {2, 2},
-        {3, 3},
-        {-1, -1},
-};
-static s8
 dm365_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 7},
@@ -873,12 +863,6 @@ dm365_queue_priority_mapping[][2] = {
 };
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 256,
-        .n_tc                   = 4,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = dm365_queue_tc_mapping,
        .queue_priority_mapping = dm365_queue_priority_mapping,
        .default_queue          = EVENTQ_3,
 };
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 5debffba4b24..dc52657909c4 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -499,14 +499,6 @@ static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /*----------------------------------------------------------------------*/
 static s8
-queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {-1, -1},
-};
-static s8
 queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 3},
@@ -515,12 +507,6 @@ queue_priority_mapping[][2] = {
 };
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 4,
-        .n_slot                 = 128,
-        .n_tc                   = 2,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = queue_tc_mapping,
        .queue_priority_mapping = queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 332d00d24dc2..6c3bbea7d77d 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -533,16 +533,6 @@ static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 /* Four Transfer Controllers on DM646x */
 static s8
-dm646x_queue_tc_mapping[][2] = {
-        /* {event queue no, TC no} */
-        {0, 0},
-        {1, 1},
-        {2, 2},
-        {3, 3},
-        {-1, -1},
-};
-static s8
 dm646x_queue_priority_mapping[][2] = {
        /* {event queue no, Priority} */
        {0, 4},
@@ -553,12 +543,6 @@ dm646x_queue_priority_mapping[][2] = {
 };
 static struct edma_soc_info edma_cc0_info = {
-        .n_channel              = 64,
-        .n_region               = 6,    /* 0-1, 4-7 */
-        .n_slot                 = 512,
-        .n_tc                   = 4,
-        .n_cc                   = 1,
-        .queue_tc_mapping       = dm646x_queue_tc_mapping,
        .queue_priority_mapping = dm646x_queue_priority_mapping,
        .default_queue          = EVENTQ_1,
 };
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index bc4344aa1009..4a5a7aedcb76 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -108,6 +108,38 @@ static int __initdata gpio2_irqs[4] = {
        0,
 };
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+static void __iomem *dove_irq_base = IRQ_VIRT_BASE;
+static asmlinkage void
+__exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+        stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_LOW_OFF);
+        stat &= readl_relaxed(dove_irq_base + IRQ_MASK_LOW_OFF);
+        if (stat) {
+                unsigned int hwirq = __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+        stat = readl_relaxed(dove_irq_base + IRQ_CAUSE_HIGH_OFF);
+        stat &= readl_relaxed(dove_irq_base + IRQ_MASK_HIGH_OFF);
+        if (stat) {
+                unsigned int hwirq = 32 + __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+}
+#endif
 void __init dove_init_irq(void)
 {
        int i;
@@ -115,6 +147,10 @@ void __init dove_init_irq(void)
        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        set_handle_irq(dove_legacy_handle_irq);
+#endif
        /*
         * Initialize gpiolib for GPIOs 0-71.
         */
diff --git a/arch/arm/mach-ep93xx/crunch-bits.S b/arch/arm/mach-ep93xx/crunch-bits.S
index 0ec9bb48fab9..e96923a3017b 100644
--- a/arch/arm/mach-ep93xx/crunch-bits.S
+++ b/arch/arm/mach-ep93xx/crunch-bits.S
@@ -16,6 +16,7 @@
 #include <asm/ptrace.h>
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
+#include <asm/assembler.h>
 #include <mach/ep93xx-regs.h>
 /*
@@ -62,14 +63,16 @@
 * r9  = ret_from_exception
 * lr  = undefined instr exit
 *
- * called from prefetch exception handler with interrupts disabled
+ * called from prefetch exception handler with interrupts enabled
 */
 ENTRY(crunch_task_enable)
+        inc_preempt_count r10, r3
        ldr     r8, =(EP93XX_APB_VIRT_BASE + 0x00130000)        @ syscon addr
        ldr     r1, [r8, #0x80]
        tst     r1, #0x00800000                 @ access to crunch enabled?
-        movne   pc, lr                          @ if so no business here
+        bne     2f                              @ if so no business here
        mov     r3, #0xaa                       @ unlock syscon swlock
        str     r3, [r8, #0xc0]
        orr     r1, r1, #0x00800000             @ enable access to crunch
@@ -142,7 +145,7 @@ crunch_save:
        teq             r0, #0                          @ anything to load?
        cfldr64eq       mvdx0, [r1, #CRUNCH_MVDX0]      @ mvdx0 was clobbered
-        moveq           pc, lr
+        beq             1f
 crunch_load:
        cfldr64         mvdx0, [r0, #CRUNCH_DSPSC]      @ load status word
@@ -190,6 +193,11 @@ crunch_load:
        cfldr64         mvdx14, [r0, #CRUNCH_MVDX14]
        cfldr64         mvdx15, [r0, #CRUNCH_MVDX15]
+1:
+#ifdef CONFIG_PREEMPT_COUNT
+        get_thread_info r10
+#endif
+2:      dec_preempt_count r10, r3
        mov     pc, lr
 /*
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index fc8bf18e222d..d58995c9a95a 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -7,97 +7,102 @@
 # Configuration options for the EXYNOS4
+config ARCH_EXYNOS
+        bool "Samsung EXYNOS" if ARCH_MULTI_V7
+        select ARCH_HAS_BANDGAP
+        select ARCH_HAS_CPUFREQ
+        select ARCH_HAS_HOLES_MEMORYMODEL
+        select ARCH_REQUIRE_GPIOLIB
+        select ARM_AMBA
+        select ARM_GIC
+        select COMMON_CLK_SAMSUNG
+        select HAVE_ARM_SCU if SMP
+        select HAVE_S3C2410_I2C if I2C
+        select HAVE_S3C2410_WATCHDOG if WATCHDOG
+        select HAVE_S3C_RTC if RTC_CLASS
+        select PINCTRL
+        select PINCTRL_EXYNOS
+        select PM_GENERIC_DOMAINS if PM_RUNTIME
+        select S5P_DEV_MFC
+        select SRAM
+        help
+          Support for SAMSUNG EXYNOS SoCs (EXYNOS4/5)
 if ARCH_EXYNOS
 menu "SAMSUNG EXYNOS SoCs Support"
+config ARCH_EXYNOS3
+        bool "SAMSUNG EXYNOS3"
+        select ARM_CPU_SUSPEND if PM
+        help
+          Samsung EXYNOS3 (Crotex-A7) SoC based systems
 config ARCH_EXYNOS4
        bool "SAMSUNG EXYNOS4"
        default y
-        select ARM_AMBA
+        select ARM_CPU_SUSPEND if PM_SLEEP
-        select CLKSRC_OF
        select CLKSRC_SAMSUNG_PWM if CPU_EXYNOS4210
        select CPU_EXYNOS4210
        select GIC_NON_BANKED
        select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
-        select HAVE_ARM_SCU if SMP
-        select HAVE_SMP
        select MIGHT_HAVE_CACHE_L2X0
-        select PINCTRL
-        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        select S5P_DEV_MFC
        help
-          Samsung EXYNOS4 SoCs based systems
+          Samsung EXYNOS4 (Cortex-A9) SoC based systems
 config ARCH_EXYNOS5
        bool "SAMSUNG EXYNOS5"
-        select ARM_AMBA
+        default y
-        select CLKSRC_OF
-        select HAVE_ARM_SCU if SMP
-        select HAVE_SMP
-        select PINCTRL
        help
-          Samsung EXYNOS5 (Cortex-A15) SoC based systems
+          Samsung EXYNOS5 (Cortex-A15/A7) SoC based systems
 comment "EXYNOS SoCs"
+config SOC_EXYNOS3250
+        bool "SAMSUNG EXYNOS3250"
+        default y
+        depends on ARCH_EXYNOS3
 config CPU_EXYNOS4210
        bool "SAMSUNG EXYNOS4210"
        default y
        depends on ARCH_EXYNOS4
-        select ARCH_HAS_BANDGAP
-        select ARM_CPU_SUSPEND if PM_SLEEP
-        select PINCTRL_EXYNOS
-        select SAMSUNG_DMADEV
-        help
-          Enable EXYNOS4210 CPU support
 config SOC_EXYNOS4212
        bool "SAMSUNG EXYNOS4212"
        default y
        depends on ARCH_EXYNOS4
-        select ARCH_HAS_BANDGAP
-        select PINCTRL_EXYNOS
-        select SAMSUNG_DMADEV
-        help
-          Enable EXYNOS4212 SoC support
 config SOC_EXYNOS4412
        bool "SAMSUNG EXYNOS4412"
        default y
        depends on ARCH_EXYNOS4
-        select ARCH_HAS_BANDGAP
-        select PINCTRL_EXYNOS
-        select SAMSUNG_DMADEV
-        help
-          Enable EXYNOS4412 SoC support
 config SOC_EXYNOS5250
        bool "SAMSUNG EXYNOS5250"
        default y
        depends on ARCH_EXYNOS5
-        select ARCH_HAS_BANDGAP
-        select PINCTRL_EXYNOS
+config SOC_EXYNOS5260
-        select PM_GENERIC_DOMAINS if PM_RUNTIME
+        bool "SAMSUNG EXYNOS5260"
-        select S5P_DEV_MFC
+        default y
-        select SAMSUNG_DMADEV
+        depends on ARCH_EXYNOS5
-        help
-          Enable EXYNOS5250 SoC support
+config SOC_EXYNOS5410
+        bool "SAMSUNG EXYNOS5410"
+        default y
+        depends on ARCH_EXYNOS5
 config SOC_EXYNOS5420
        bool "SAMSUNG EXYNOS5420"
        default y
        depends on ARCH_EXYNOS5
-        select PM_GENERIC_DOMAINS if PM_RUNTIME
-        help
-          Enable EXYNOS5420 SoC support
 config SOC_EXYNOS5440
        bool "SAMSUNG EXYNOS5440"
        default y
        depends on ARCH_EXYNOS5
        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-        select ARCH_HAS_BANDGAP
        select ARCH_HAS_OPP
        select HAVE_ARM_ARCH_TIMER
        select AUTO_ZRELADDR
@@ -108,6 +113,19 @@ config SOC_EXYNOS5440
        help
          Enable EXYNOS5440 SoC support
+config SOC_EXYNOS5800
+        bool "SAMSUNG EXYNOS5800"
+        default y
+        depends on SOC_EXYNOS5420
 endmenu
+config EXYNOS5420_MCPM
+        bool "Exynos5420 Multi-Cluster PM support"
+        depends on MCPM && SOC_EXYNOS5420
+        select ARM_CCI
+        help
+          This is needed to provide CPU and cluster power management
+          on Exynos5420 implementing big.LITTLE.
 endif
diff --git a/arch/arm/mach-exynos/Makefile b/arch/arm/mach-exynos/Makefile
index a656dbe3b78c..788f26d21141 100644
--- a/arch/arm/mach-exynos/Makefile
+++ b/arch/arm/mach-exynos/Makefile
@@ -5,6 +5,8 @@
 #
 # Licensed under GPLv2
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) += -I$(srctree)/$(src)/include -I$(srctree)/arch/arm/plat-samsung/include
 obj-y                           :=
 obj-m                           :=
 obj-n                           :=
@@ -12,20 +14,18 @@ obj-				:=
 # Core
-obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o
+obj-$(CONFIG_ARCH_EXYNOS)       += exynos.o pmu.o exynos-smc.o firmware.o
 obj-$(CONFIG_PM_SLEEP)          += pm.o sleep.o
 obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
-obj-$(CONFIG_CPU_IDLE)          += cpuidle.o
-obj-$(CONFIG_ARCH_EXYNOS)       += pmu.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
+CFLAGS_hotplug.o                += -march=armv7-a
-obj-$(CONFIG_ARCH_EXYNOS)       += exynos-smc.o
-obj-$(CONFIG_ARCH_EXYNOS)       += firmware.o
 plus_sec := $(call as-instr,.arch_extension sec,+sec)
 AFLAGS_exynos-smc.o             :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_EXYNOS5420_MCPM)   += mcpm-exynos.o
+CFLAGS_mcpm-exynos.o            += -march=armv7-a
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 9ef3f83efaff..16617bdb37a9 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -15,9 +15,107 @@
 #include <linux/reboot.h>
 #include <linux/of.h>
+#define EXYNOS3250_SOC_ID       0xE3472000
+#define EXYNOS3_SOC_MASK        0xFFFFF000
+#define EXYNOS4210_CPU_ID       0x43210000
+#define EXYNOS4212_CPU_ID       0x43220000
+#define EXYNOS4412_CPU_ID       0xE4412200
+#define EXYNOS4_CPU_MASK        0xFFFE0000
+#define EXYNOS5250_SOC_ID       0x43520000
+#define EXYNOS5410_SOC_ID       0xE5410000
+#define EXYNOS5420_SOC_ID       0xE5420000
+#define EXYNOS5440_SOC_ID       0xE5440000
+#define EXYNOS5800_SOC_ID       0xE5422000
+#define EXYNOS5_SOC_MASK        0xFFFFF000
+extern unsigned long samsung_cpu_id;
+#define IS_SAMSUNG_CPU(name, id, mask)          \
+static inline int is_samsung_##name(void)       \
+{                                               \
+        return ((samsung_cpu_id & mask) == (id & mask));        \
+}
+IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK)
+IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
+IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
+IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK)
+#if defined(CONFIG_SOC_EXYNOS3250)
+# define soc_is_exynos3250()    is_samsung_exynos3250()
+#else
+# define soc_is_exynos3250()    0
+#endif
+#if defined(CONFIG_CPU_EXYNOS4210)
+# define soc_is_exynos4210()    is_samsung_exynos4210()
+#else
+# define soc_is_exynos4210()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS4212)
+# define soc_is_exynos4212()    is_samsung_exynos4212()
+#else
+# define soc_is_exynos4212()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS4412)
+# define soc_is_exynos4412()    is_samsung_exynos4412()
+#else
+# define soc_is_exynos4412()    0
+#endif
+#define EXYNOS4210_REV_0        (0x0)
+#define EXYNOS4210_REV_1_0      (0x10)
+#define EXYNOS4210_REV_1_1      (0x11)
+#if defined(CONFIG_SOC_EXYNOS5250)
+# define soc_is_exynos5250()    is_samsung_exynos5250()
+#else
+# define soc_is_exynos5250()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS5410)
+# define soc_is_exynos5410()    is_samsung_exynos5410()
+#else
+# define soc_is_exynos5410()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS5420)
+# define soc_is_exynos5420()    is_samsung_exynos5420()
+#else
+# define soc_is_exynos5420()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS5440)
+# define soc_is_exynos5440()    is_samsung_exynos5440()
+#else
+# define soc_is_exynos5440()    0
+#endif
+#if defined(CONFIG_SOC_EXYNOS5800)
+# define soc_is_exynos5800()    is_samsung_exynos5800()
+#else
+# define soc_is_exynos5800()    0
+#endif
+#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
+                          soc_is_exynos4412())
+#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \
+                          soc_is_exynos5420() || soc_is_exynos5800())
 void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
 struct map_desc;
+extern void __iomem *sysram_ns_base_addr;
+extern void __iomem *sysram_base_addr;
 void exynos_init_io(void);
 void exynos_restart(enum reboot_mode mode, const char *cmd);
 void exynos_cpuidle_init(void);
@@ -55,12 +153,21 @@ enum sys_powerdown {
        NUM_SYS_POWERDOWN,
 };
-extern unsigned long l2x0_regs_phys;
 struct exynos_pmu_conf {
        void __iomem *reg;
        unsigned int val[NUM_SYS_POWERDOWN];
 };
 extern void exynos_sys_powerdown_conf(enum sys_powerdown mode);
+extern void exynos_cpu_power_down(int cpu);
+extern void exynos_cpu_power_up(int cpu);
+extern int  exynos_cpu_power_state(int cpu);
+extern void exynos_cluster_power_down(int cluster);
+extern void exynos_cluster_power_up(int cluster);
+extern int  exynos_cluster_power_state(int cluster);
+extern void exynos_enter_aftr(void);
+extern void s5p_init_cpu(void __iomem *cpuid_addr);
+extern unsigned int samsung_rev(void);
 #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
deleted file mode 100644
index c57cae0e8779..000000000000
--- a/arch/arm/mach-exynos/cpuidle.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/* linux/arch/arm/mach-exynos4/cpuidle.c
- *
- * Copyright (c) 2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/io.h>
-#include <linux/export.h>
-#include <linux/module.h>
-#include <linux/time.h>
-#include <linux/platform_device.h>
-#include <asm/proc-fns.h>
-#include <asm/smp_scu.h>
-#include <asm/suspend.h>
-#include <asm/unified.h>
-#include <asm/cpuidle.h>
-#include <plat/cpu.h>
-#include <plat/pm.h>
-#include <mach/map.h>
-#include "common.h"
-#include "regs-pmu.h"
-#define REG_DIRECTGO_ADDR       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-                        (S5P_VA_SYSRAM + 0x24) : S5P_INFORM0))
-#define REG_DIRECTGO_FLAG       (samsung_rev() == EXYNOS4210_REV_1_1 ? \
-                        S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
-                        (S5P_VA_SYSRAM + 0x20) : S5P_INFORM1))
-#define S5P_CHECK_AFTR          0xFCBA0D10
-#define EXYNOS5_PWR_CTRL1                       (S5P_VA_CMU + 0x01020)
-#define EXYNOS5_PWR_CTRL2                       (S5P_VA_CMU + 0x01024)
-#define PWR_CTRL1_CORE2_DOWN_RATIO              (7 << 28)
-#define PWR_CTRL1_CORE1_DOWN_RATIO              (7 << 16)
-#define PWR_CTRL1_DIV2_DOWN_EN                  (1 << 9)
-#define PWR_CTRL1_DIV1_DOWN_EN                  (1 << 8)
-#define PWR_CTRL1_USE_CORE1_WFE                 (1 << 5)
-#define PWR_CTRL1_USE_CORE0_WFE                 (1 << 4)
-#define PWR_CTRL1_USE_CORE1_WFI                 (1 << 1)
-#define PWR_CTRL1_USE_CORE0_WFI                 (1 << 0)
-#define PWR_CTRL2_DIV2_UP_EN                    (1 << 25)
-#define PWR_CTRL2_DIV1_UP_EN                    (1 << 24)
-#define PWR_CTRL2_DUR_STANDBY2_VAL              (1 << 16)
-#define PWR_CTRL2_DUR_STANDBY1_VAL              (1 << 8)
-#define PWR_CTRL2_CORE2_UP_RATIO                (1 << 4)
-#define PWR_CTRL2_CORE1_UP_RATIO                (1 << 0)
-static int exynos4_enter_lowpower(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index);
-static DEFINE_PER_CPU(struct cpuidle_device, exynos4_cpuidle_device);
-static struct cpuidle_driver exynos4_idle_driver = {
-        .name                   = "exynos4_idle",
-        .owner                  = THIS_MODULE,
-        .states = {
-                [0] = ARM_CPUIDLE_WFI_STATE,
-                [1] = {
-                        .enter                  = exynos4_enter_lowpower,
-                        .exit_latency           = 300,
-                        .target_residency       = 100000,
-                        .flags                  = CPUIDLE_FLAG_TIME_VALID,
-                        .name                   = "C1",
-                        .desc                   = "ARM power down",
-                },
-        },
-        .state_count = 2,
-        .safe_state_index = 0,
-};
-/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
-static void exynos4_set_wakeupmask(void)
-{
-        __raw_writel(0x0000ff3e, S5P_WAKEUP_MASK);
-}
-static unsigned int g_pwr_ctrl, g_diag_reg;
-static void save_cpu_arch_register(void)
-{
-        /*read power control register*/
-        asm("mrc p15, 0, %0, c15, c0, 0" : "=r"(g_pwr_ctrl) : : "cc");
-        /*read diagnostic register*/
-        asm("mrc p15, 0, %0, c15, c0, 1" : "=r"(g_diag_reg) : : "cc");
-        return;
-}
-static void restore_cpu_arch_register(void)
-{
-        /*write power control register*/
-        asm("mcr p15, 0, %0, c15, c0, 0" : : "r"(g_pwr_ctrl) : "cc");
-        /*write diagnostic register*/
-        asm("mcr p15, 0, %0, c15, c0, 1" : : "r"(g_diag_reg) : "cc");
-        return;
-}
-static int idle_finisher(unsigned long flags)
-{
-        cpu_do_idle();
-        return 1;
-}
-static int exynos4_enter_core0_aftr(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
-{
-        unsigned long tmp;
-        exynos4_set_wakeupmask();
-        /* Set value of power down register for aftr mode */
-        exynos_sys_powerdown_conf(SYS_AFTR);
-        __raw_writel(virt_to_phys(exynos_cpu_resume), REG_DIRECTGO_ADDR);
-        __raw_writel(S5P_CHECK_AFTR, REG_DIRECTGO_FLAG);
-        save_cpu_arch_register();
-        /* Setting Central Sequence Register for power down mode */
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
-        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-        cpu_pm_enter();
-        cpu_suspend(0, idle_finisher);
-#ifdef CONFIG_SMP
-        if (!soc_is_exynos5250())
-                scu_enable(S5P_VA_SCU);
-#endif
-        cpu_pm_exit();
-        restore_cpu_arch_register();
-        /*
-         * If PMU failed while entering sleep mode, WFI will be
-         * ignored by PMU and then exiting cpu_do_idle().
-         * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
-         * in this situation.
-         */
-        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
-        if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
-                tmp |= S5P_CENTRAL_LOWPWR_CFG;
-                __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-        }
-        /* Clear wakeup state register */
-        __raw_writel(0x0, S5P_WAKEUP_STAT);
-        return index;
-}
-static int exynos4_enter_lowpower(struct cpuidle_device *dev,
-                                struct cpuidle_driver *drv,
-                                int index)
-{
-        int new_index = index;
-        /* AFTR can only be entered when cores other than CPU0 are offline */
-        if (num_online_cpus() > 1 || dev->cpu != 0)
-                new_index = drv->safe_state_index;
-        if (new_index == 0)
-                return arm_cpuidle_simple_enter(dev, drv, new_index);
-        else
-                return exynos4_enter_core0_aftr(dev, drv, new_index);
-}
-static void __init exynos5_core_down_clk(void)
-{
-        unsigned int tmp;
-        /*
-         * Enable arm clock down (in idle) and set arm divider
-         * ratios in WFI/WFE state.
-         */
-        tmp = PWR_CTRL1_CORE2_DOWN_RATIO | \
-              PWR_CTRL1_CORE1_DOWN_RATIO | \
-              PWR_CTRL1_DIV2_DOWN_EN     | \
-              PWR_CTRL1_DIV1_DOWN_EN     | \
-              PWR_CTRL1_USE_CORE1_WFE    | \
-              PWR_CTRL1_USE_CORE0_WFE    | \
-              PWR_CTRL1_USE_CORE1_WFI    | \
-              PWR_CTRL1_USE_CORE0_WFI;
-        __raw_writel(tmp, EXYNOS5_PWR_CTRL1);
-        /*
-         * Enable arm clock up (on exiting idle). Set arm divider
-         * ratios when not in idle along with the standby duration
-         * ratios.
-         */
-        tmp = PWR_CTRL2_DIV2_UP_EN       | \
-              PWR_CTRL2_DIV1_UP_EN       | \
-              PWR_CTRL2_DUR_STANDBY2_VAL | \
-              PWR_CTRL2_DUR_STANDBY1_VAL | \
-              PWR_CTRL2_CORE2_UP_RATIO   | \
-              PWR_CTRL2_CORE1_UP_RATIO;
-        __raw_writel(tmp, EXYNOS5_PWR_CTRL2);
-}
-static int exynos_cpuidle_probe(struct platform_device *pdev)
-{
-        int cpu_id, ret;
-        struct cpuidle_device *device;
-        if (soc_is_exynos5250())
-                exynos5_core_down_clk();
-        if (soc_is_exynos5440())
-                exynos4_idle_driver.state_count = 1;
-        ret = cpuidle_register_driver(&exynos4_idle_driver);
-        if (ret) {
-                dev_err(&pdev->dev, "failed to register cpuidle driver\n");
-                return ret;
-        }
-        for_each_online_cpu(cpu_id) {
-                device = &per_cpu(exynos4_cpuidle_device, cpu_id);
-                device->cpu = cpu_id;
-                ret = cpuidle_register_device(device);
-                if (ret) {
-                        dev_err(&pdev->dev, "failed to register cpuidle device\n");
-                        return ret;
-                }
-        }
-        return 0;
-}
-static struct platform_driver exynos_cpuidle_driver = {
-        .probe  = exynos_cpuidle_probe,
-        .driver = {
-                .name = "exynos_cpuidle",
-                .owner = THIS_MODULE,
-        },
-};
-module_platform_driver(exynos_cpuidle_driver);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index b32a907d021d..90aab4d75d08 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -26,15 +26,10 @@
 #include <asm/mach/map.h>
 #include <asm/memory.h>
-#include <plat/cpu.h>
 #include "common.h"
 #include "mfc.h"
 #include "regs-pmu.h"
-#define L2_AUX_VAL 0x7C470001
-#define L2_AUX_MASK 0xC200ffff
 static struct map_desc exynos4_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -114,51 +109,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
        },
 };
-static struct map_desc exynos4_iodesc0[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM0),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4_iodesc1[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS4_PA_SYSRAM1),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4210_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
-                .pfn            = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos4x12_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
-                .pfn            = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
-static struct map_desc exynos5250_iodesc[] __initdata = {
-        {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM_NS,
-                .pfn            = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        },
-};
 static struct map_desc exynos5_iodesc[] __initdata = {
        {
                .virtual        = (unsigned long)S3C_VA_SYS,
@@ -181,11 +131,6 @@ static struct map_desc exynos5_iodesc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE,
        }, {
-                .virtual        = (unsigned long)S5P_VA_SYSRAM,
-                .pfn            = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
-                .length         = SZ_4K,
-                .type           = MT_DEVICE,
-        }, {
                .virtual        = (unsigned long)S5P_VA_CMU,
                .pfn            = __phys_to_pfn(EXYNOS5_PA_CMU),
                .length         = 144 * SZ_1K,
@@ -221,12 +166,16 @@ void exynos_restart(enum reboot_mode mode, const char *cmd)
 }
 static struct platform_device exynos_cpuidle = {
-        .name           = "exynos_cpuidle",
+        .name              = "exynos_cpuidle",
-        .id             = -1,
+        .dev.platform_data = exynos_enter_aftr,
+        .id                = -1,
 };
 void __init exynos_cpuidle_init(void)
 {
+        if (soc_is_exynos5440())
+                return;
        platform_device_register(&exynos_cpuidle);
 }
@@ -250,7 +199,7 @@ static int __init exynos_fdt_map_chipid(unsigned long node, const char *uname,
 {
        struct map_desc iodesc;
        __be32 *reg;
-        unsigned long len;
+        int len;
        if (!of_flat_dt_is_compatible(node, "samsung,exynos4210-chipid") &&
                !of_flat_dt_is_compatible(node, "samsung,exynos5440-clock"))
@@ -280,20 +229,6 @@ static void __init exynos_map_io(void)
        if (soc_is_exynos5())
                iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
-        if (soc_is_exynos4210()) {
-                if (samsung_rev() == EXYNOS4210_REV_0)
-                        iotable_init(exynos4_iodesc0,
-                                                ARRAY_SIZE(exynos4_iodesc0));
-                else
-                        iotable_init(exynos4_iodesc1,
-                                                ARRAY_SIZE(exynos4_iodesc1));
-                iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
-        }
-        if (soc_is_exynos4212() || soc_is_exynos4412())
-                iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-        if (soc_is_exynos5250())
-                iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
 }
 void __init exynos_init_io(void)
@@ -308,33 +243,6 @@ void __init exynos_init_io(void)
        exynos_map_io();
 }
-struct bus_type exynos_subsys = {
-        .name           = "exynos-core",
-        .dev_name       = "exynos-core",
-};
-static int __init exynos_core_init(void)
-{
-        return subsys_system_register(&exynos_subsys, NULL);
-}
-core_initcall(exynos_core_init);
-static int __init exynos4_l2x0_cache_init(void)
-{
-        int ret;
-        ret = l2x0_of_init(L2_AUX_VAL, L2_AUX_MASK);
-        if (ret)
-                return ret;
-        if (IS_ENABLED(CONFIG_S5P_SLEEP)) {
-                l2x0_regs_phys = virt_to_phys(&l2x0_saved_regs);
-                clean_dcache_area(&l2x0_regs_phys, sizeof(unsigned long));
-        }
-        return 0;
-}
-early_initcall(exynos4_l2x0_cache_init);
 static void __init exynos_dt_machine_init(void)
 {
        struct device_node *i2c_np;
@@ -370,12 +278,15 @@ static void __init exynos_dt_machine_init(void)
 }
 static char const *exynos_dt_compat[] __initconst = {
+        "samsung,exynos3",
+        "samsung,exynos3250",
        "samsung,exynos4",
        "samsung,exynos4210",
        "samsung,exynos4212",
        "samsung,exynos4412",
        "samsung,exynos5",
        "samsung,exynos5250",
+        "samsung,exynos5260",
        "samsung,exynos5420",
        "samsung,exynos5440",
        NULL
@@ -400,6 +311,8 @@ static void __init exynos_reserve(void)
 DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
        /* Maintainer: Thomas Abraham <thomas.abraham@linaro.org> */
        /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
+        .l2c_aux_val    = 0x3c400001,
+        .l2c_aux_mask   = 0xc20fffff,
        .smp            = smp_ops(exynos_smp_ops),
        .map_io         = exynos_init_io,
        .init_early     = exynos_firmware_init,
diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c
index 932129ef26c6..eb91d2350f8c 100644
--- a/arch/arm/mach-exynos/firmware.c
+++ b/arch/arm/mach-exynos/firmware.c
@@ -18,6 +18,7 @@
 #include <mach/map.h>
+#include "common.h"
 #include "smc.h"
 static int exynos_do_idle(void)
@@ -28,13 +29,36 @@ static int exynos_do_idle(void)
 static int exynos_cpu_boot(int cpu)
 {
+        /*
+         * Exynos3250 doesn't need to send smc command for secondary CPU boot
+         * because Exynos3250 removes WFE in secure mode.
+         */
+        if (soc_is_exynos3250())
+                return 0;
+        /*
+         * The second parameter of SMC_CMD_CPU1BOOT command means CPU id.
+         * But, Exynos4212 has only one secondary CPU so second parameter
+         * isn't used for informing secure firmware about CPU id.
+         */
+        if (soc_is_exynos4212())
+                cpu = 0;
        exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
        return 0;
 }
 static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
 {
-        void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
+        void __iomem *boot_reg;
+        if (!sysram_ns_base_addr)
+                return -ENODEV;
+        boot_reg = sysram_ns_base_addr + 0x1c;
+        if (!soc_is_exynos4212() && !soc_is_exynos3250())
+                boot_reg += 4*cpu;
        __raw_writel(boot_addr, boot_reg);
        return 0;
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c
index 5eead530c6f8..69fa48397394 100644
--- a/arch/arm/mach-exynos/hotplug.c
+++ b/arch/arm/mach-exynos/hotplug.c
@@ -19,61 +19,9 @@
 #include <asm/cp15.h>
 #include <asm/smp_plat.h>
-#include <plat/cpu.h>
 #include "common.h"
 #include "regs-pmu.h"
-static inline void cpu_enter_lowpower_a9(void)
-{
-        unsigned int v;
-        asm volatile(
-        "       mcr     p15, 0, %1, c7, c5, 0\n"
-        "       mcr     p15, 0, %1, c7, c10, 4\n"
-        /*
-         * Turn off coherency
-         */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, %3\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %2\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "r" (0), "Ir" (CR_C), "Ir" (0x40)
-          : "cc");
-}
-static inline void cpu_enter_lowpower_a15(void)
-{
-        unsigned int v;
-        asm volatile(
-        "       mrc     p15, 0, %0, c1, c0, 0\n"
-        "       bic     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 0\n"
-          : "=&r" (v)
-          : "Ir" (CR_C)
-          : "cc");
-        flush_cache_louis();
-        asm volatile(
-        /*
-        * Turn off coherency
-        */
-        "       mrc     p15, 0, %0, c1, c0, 1\n"
-        "       bic     %0, %0, %1\n"
-        "       mcr     p15, 0, %0, c1, c0, 1\n"
-        : "=&r" (v)
-        : "Ir" (0x40)
-        : "cc");
-        isb();
-        dsb();
-}
 static inline void cpu_leave_lowpower(void)
 {
        unsigned int v;
@@ -96,7 +44,7 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
                /* make cpu1 to be turned off at next WFI command */
                if (cpu == 1)
-                        __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+                        exynos_cpu_power_down(cpu);
                /*
                 * here's the WFI
@@ -132,19 +80,8 @@ static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 void __ref exynos_cpu_die(unsigned int cpu)
 {
        int spurious = 0;
-        int primary_part = 0;
-        /*
+        v7_exit_coherency_flush(louis);
-         * we're ready for shutdown now, so do it.
-         * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
-         * number by reading the Main ID register and then perform the
-         * appropriate sequence for entering low power.
-         */
-        asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
-        if ((primary_part & 0xfff0) == 0xc0f0)
-                cpu_enter_lowpower_a15();
-        else
-                cpu_enter_lowpower_a9();
        platform_do_lowpower(cpu, &spurious);
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 7b046b59d9ec..548269a60634 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -23,13 +23,6 @@
 #include <plat/map-s5p.h>
-#define EXYNOS4_PA_SYSRAM0              0x02025000
-#define EXYNOS4_PA_SYSRAM1              0x02020000
-#define EXYNOS5_PA_SYSRAM               0x02020000
-#define EXYNOS4210_PA_SYSRAM_NS         0x0203F000
-#define EXYNOS4x12_PA_SYSRAM_NS         0x0204F000
-#define EXYNOS5250_PA_SYSRAM_NS         0x0204F000
 #define EXYNOS_PA_CHIPID                0x10000000
 #define EXYNOS4_PA_SYSCON               0x10010000
diff --git a/arch/arm/mach-exynos/mcpm-exynos.c b/arch/arm/mach-exynos/mcpm-exynos.c
new file mode 100644
index 000000000000..0498d0b887ef
--- /dev/null
+++ b/arch/arm/mach-exynos/mcpm-exynos.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2014 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com
+ *
+ * arch/arm/mach-exynos/mcpm-exynos.c
+ *
+ * Based on arch/arm/mach-vexpress/dcscb.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/arm-cci.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/of_address.h>
+#include <asm/cputype.h>
+#include <asm/cp15.h>
+#include <asm/mcpm.h>
+#include "regs-pmu.h"
+#include "common.h"
+#define EXYNOS5420_CPUS_PER_CLUSTER     4
+#define EXYNOS5420_NR_CLUSTERS          2
+#define MCPM_BOOT_ADDR_OFFSET           0x1c
+/*
+ * The common v7_exit_coherency_flush API could not be used because of the
+ * Erratum 799270 workaround. This macro is the same as the common one (in
+ * arch/arm/include/asm/cacheflush.h) except for the erratum handling.
+ */
+#define exynos_v7_exit_coherency_flush(level) \
+        asm volatile( \
+        "stmfd  sp!, {fp, ip}\n\t"\
+        "mrc    p15, 0, r0, c1, c0, 0   @ get SCTLR\n\t" \
+        "bic    r0, r0, #"__stringify(CR_C)"\n\t" \
+        "mcr    p15, 0, r0, c1, c0, 0   @ set SCTLR\n\t" \
+        "isb\n\t"\
+        "bl     v7_flush_dcache_"__stringify(level)"\n\t" \
+        "clrex\n\t"\
+        "mrc    p15, 0, r0, c1, c0, 1   @ get ACTLR\n\t" \
+        "bic    r0, r0, #(1 << 6)       @ disable local coherency\n\t" \
+        /* Dummy Load of a device register to avoid Erratum 799270 */ \
+        "ldr    r4, [%0]\n\t" \
+        "and    r4, r4, #0\n\t" \
+        "orr    r0, r0, r4\n\t" \
+        "mcr    p15, 0, r0, c1, c0, 1   @ set ACTLR\n\t" \
+        "isb\n\t" \
+        "dsb\n\t" \
+        "ldmfd  sp!, {fp, ip}" \
+        : \
+        : "Ir" (S5P_INFORM0) \
+        : "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
+          "r9", "r10", "lr", "memory")
+/*
+ * We can't use regular spinlocks. In the switcher case, it is possible
+ * for an outbound CPU to call power_down() after its inbound counterpart
+ * is already live using the same logical CPU number which trips lockdep
+ * debugging.
+ */
+static arch_spinlock_t exynos_mcpm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
+static int
+cpu_use_count[EXYNOS5420_CPUS_PER_CLUSTER][EXYNOS5420_NR_CLUSTERS];
+#define exynos_cluster_usecnt(cluster) \
+        (cpu_use_count[0][cluster] +   \
+         cpu_use_count[1][cluster] +   \
+         cpu_use_count[2][cluster] +   \
+         cpu_use_count[3][cluster])
+#define exynos_cluster_unused(cluster) !exynos_cluster_usecnt(cluster)
+static int exynos_cluster_power_control(unsigned int cluster, int enable)
+{
+        unsigned int tries = 100;
+        unsigned int val;
+        if (enable) {
+                exynos_cluster_power_up(cluster);
+                val = S5P_CORE_LOCAL_PWR_EN;
+        } else {
+                exynos_cluster_power_down(cluster);
+                val = 0;
+        }
+        /* Wait until cluster power control is applied */
+        while (tries--) {
+                if (exynos_cluster_power_state(cluster) == val)
+                        return 0;
+                cpu_relax();
+        }
+        pr_debug("timed out waiting for cluster %u to power %s\n", cluster,
+                enable ? "on" : "off");
+        return -ETIMEDOUT;
+}
+static int exynos_power_up(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+        int err = 0;
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        if (cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                cluster >= EXYNOS5420_NR_CLUSTERS)
+                return -EINVAL;
+        /*
+         * Since this is called with IRQs enabled, and no arch_spin_lock_irq
+         * variant exists, we need to disable IRQs manually here.
+         */
+        local_irq_disable();
+        arch_spin_lock(&exynos_mcpm_lock);
+        cpu_use_count[cpu][cluster]++;
+        if (cpu_use_count[cpu][cluster] == 1) {
+                bool was_cluster_down =
+                        (exynos_cluster_usecnt(cluster) == 1);
+                /*
+                 * Turn on the cluster (L2/COMMON) and then power on the
+                 * cores.
+                 */
+                if (was_cluster_down)
+                        err = exynos_cluster_power_control(cluster, 1);
+                if (!err)
+                        exynos_cpu_power_up(cpunr);
+                else
+                        exynos_cluster_power_control(cluster, 0);
+        } else if (cpu_use_count[cpu][cluster] != 2) {
+                /*
+                 * The only possible values are:
+                 * 0 = CPU down
+                 * 1 = CPU (still) up
+                 * 2 = CPU requested to be up before it had a chance
+                 *     to actually make itself down.
+                 * Any other value is a bug.
+                 */
+                BUG();
+        }
+        arch_spin_unlock(&exynos_mcpm_lock);
+        local_irq_enable();
+        return err;
+}
+/*
+ * NOTE: This function requires the stack data to be visible through power down
+ * and can only be executed on processors like A15 and A7 that hit the cache
+ * with the C bit clear in the SCTLR register.
+ */
+static void exynos_power_down(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        bool last_man = false, skip_wfi = false;
+        unsigned int cpunr;
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        cpunr =  cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                        cluster >= EXYNOS5420_NR_CLUSTERS);
+        __mcpm_cpu_going_down(cpu, cluster);
+        arch_spin_lock(&exynos_mcpm_lock);
+        BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
+        cpu_use_count[cpu][cluster]--;
+        if (cpu_use_count[cpu][cluster] == 0) {
+                exynos_cpu_power_down(cpunr);
+                if (exynos_cluster_unused(cluster))
+                        /* TODO: Turn off the cluster here to save power. */
+                        last_man = true;
+        } else if (cpu_use_count[cpu][cluster] == 1) {
+                /*
+                 * A power_up request went ahead of us.
+                 * Even if we do not want to shut this CPU down,
+                 * the caller expects a certain state as if the WFI
+                 * was aborted.  So let's continue with cache cleaning.
+                 */
+                skip_wfi = true;
+        } else {
+                BUG();
+        }
+        if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
+                arch_spin_unlock(&exynos_mcpm_lock);
+                if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
+                        /*
+                         * On the Cortex-A15 we need to disable
+                         * L2 prefetching before flushing the cache.
+                         */
+                        asm volatile(
+                        "mcr    p15, 1, %0, c15, c0, 3\n\t"
+                        "isb\n\t"
+                        "dsb"
+                        : : "r" (0x400));
+                }
+                /* Flush all cache levels for this cluster. */
+                exynos_v7_exit_coherency_flush(all);
+                /*
+                 * Disable cluster-level coherency by masking
+                 * incoming snoops and DVM messages:
+                 */
+                cci_disable_port_by_cpu(mpidr);
+                __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
+        } else {
+                arch_spin_unlock(&exynos_mcpm_lock);
+                /* Disable and flush the local CPU cache. */
+                exynos_v7_exit_coherency_flush(louis);
+        }
+        __mcpm_cpu_down(cpu, cluster);
+        /* Now we are prepared for power-down, do it: */
+        if (!skip_wfi)
+                wfi();
+        /* Not dead at this point?  Let our caller cope. */
+}
+static int exynos_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
+{
+        unsigned int tries = 100;
+        unsigned int cpunr = cpu + (cluster * EXYNOS5420_CPUS_PER_CLUSTER);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER ||
+                        cluster >= EXYNOS5420_NR_CLUSTERS);
+        /* Wait for the core state to be OFF */
+        while (tries--) {
+                if (ACCESS_ONCE(cpu_use_count[cpu][cluster]) == 0) {
+                        if ((exynos_cpu_power_state(cpunr) == 0))
+                                return 0; /* success: the CPU is halted */
+                }
+                /* Otherwise, wait and retry: */
+                msleep(1);
+        }
+        return -ETIMEDOUT; /* timeout */
+}
+static const struct mcpm_platform_ops exynos_power_ops = {
+        .power_up               = exynos_power_up,
+        .power_down             = exynos_power_down,
+        .wait_for_powerdown     = exynos_wait_for_powerdown,
+};
+static void __init exynos_mcpm_usage_count_init(void)
+{
+        unsigned int mpidr, cpu, cluster;
+        mpidr = read_cpuid_mpidr();
+        cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
+        cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
+        pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
+        BUG_ON(cpu >= EXYNOS5420_CPUS_PER_CLUSTER  ||
+                        cluster >= EXYNOS5420_NR_CLUSTERS);
+        cpu_use_count[cpu][cluster] = 1;
+}
+/*
+ * Enable cluster-level coherency, in preparation for turning on the MMU.
+ */
+static void __naked exynos_pm_power_up_setup(unsigned int affinity_level)
+{
+        asm volatile ("\n"
+        "cmp    r0, #1\n"
+        "bxne   lr\n"
+        "b      cci_enable_port_for_self");
+}
+static const struct of_device_id exynos_dt_mcpm_match[] = {
+        { .compatible = "samsung,exynos5420" },
+        { .compatible = "samsung,exynos5800" },
+        {},
+};
+static int __init exynos_mcpm_init(void)
+{
+        struct device_node *node;
+        void __iomem *ns_sram_base_addr;
+        int ret;
+        node = of_find_matching_node(NULL, exynos_dt_mcpm_match);
+        if (!node)
+                return -ENODEV;
+        of_node_put(node);
+        if (!cci_probed())
+                return -ENODEV;
+        node = of_find_compatible_node(NULL, NULL,
+                        "samsung,exynos4210-sysram-ns");
+        if (!node)
+                return -ENODEV;
+        ns_sram_base_addr = of_iomap(node, 0);
+        of_node_put(node);
+        if (!ns_sram_base_addr) {
+                pr_err("failed to map non-secure iRAM base address\n");
+                return -ENOMEM;
+        }
+        /*
+         * To increase the stability of KFC reset we need to program
+         * the PMU SPARE3 register
+         */
+        __raw_writel(EXYNOS5420_SWRESET_KFC_SEL, S5P_PMU_SPARE3);
+        exynos_mcpm_usage_count_init();
+        ret = mcpm_platform_register(&exynos_power_ops);
+        if (!ret)
+                ret = mcpm_sync_init(exynos_pm_power_up_setup);
+        if (ret) {
+                iounmap(ns_sram_base_addr);
+                return ret;
+        }
+        mcpm_smp_set_ops();
+        pr_info("Exynos MCPM support installed\n");
+        /*
+         * Future entries into the kernel can now go
+         * through the cluster entry vectors.
+         */
+        __raw_writel(virt_to_phys(mcpm_entry_point),
+                        ns_sram_base_addr + MCPM_BOOT_ADDR_OFFSET);
+        iounmap(ns_sram_base_addr);
+        return ret;
+}
+early_initcall(exynos_mcpm_init);
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 03e5e9f94705..ec02422e8499 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,24 +20,45 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
+#include <linux/of_address.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
 #include <asm/firmware.h>
-#include <plat/cpu.h>
 #include "common.h"
 #include "regs-pmu.h"
 extern void exynos4_secondary_startup(void);
+void __iomem *sysram_base_addr;
+void __iomem *sysram_ns_base_addr;
+static void __init exynos_smp_prepare_sysram(void)
+{
+        struct device_node *node;
+        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram") {
+                if (!of_device_is_available(node))
+                        continue;
+                sysram_base_addr = of_iomap(node, 0);
+                break;
+        }
+        for_each_compatible_node(node, NULL, "samsung,exynos4210-sysram-ns") {
+                if (!of_device_is_available(node))
+                        continue;
+                sysram_ns_base_addr = of_iomap(node, 0);
+                break;
+        }
+}
 static inline void __iomem *cpu_boot_reg_base(void)
 {
        if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
                return S5P_INFORM5;
-        return S5P_VA_SYSRAM;
+        return sysram_base_addr;
 }
 static inline void __iomem *cpu_boot_reg(int cpu)
@@ -45,9 +66,11 @@ static inline void __iomem *cpu_boot_reg(int cpu)
        void __iomem *boot_reg;
        boot_reg = cpu_boot_reg_base();
+        if (!boot_reg)
+                return ERR_PTR(-ENODEV);
        if (soc_is_exynos4412())
                boot_reg += 4*cpu;
-        else if (soc_is_exynos5420())
+        else if (soc_is_exynos5420() || soc_is_exynos5800())
                boot_reg += 4;
        return boot_reg;
 }
@@ -90,6 +113,7 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
        unsigned long timeout;
        unsigned long phys_cpu = cpu_logical_map(cpu);
+        int ret = -ENOSYS;
        /*
         * Set synchronisation state between this boot processor
@@ -107,15 +131,12 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
         */
        write_pen_release(phys_cpu);
-        if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+        if (!exynos_cpu_power_state(cpu)) {
-                __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                exynos_cpu_power_up(cpu);
-                             S5P_ARM_CORE1_CONFIGURATION);
                timeout = 10;
                /* wait max 10 ms until cpu1 is on */
-                while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+                while (exynos_cpu_power_state(cpu) != S5P_CORE_LOCAL_PWR_EN) {
-                        & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
                        if (timeout-- == 0)
                                break;
@@ -146,8 +167,18 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
                 * Try to set boot address using firmware first
                 * and fall back to boot register if it fails.
                 */
-                if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
+                ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
+                if (ret && ret != -ENOSYS)
+                        goto fail;
+                if (ret == -ENOSYS) {
+                        void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
+                        if (IS_ERR(boot_reg)) {
+                                ret = PTR_ERR(boot_reg);
+                                goto fail;
+                        }
                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+                }
                call_firmware_op(cpu_boot, phys_cpu);
@@ -163,9 +194,10 @@ static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
         * now the secondary core is starting up let it run its
         * calibrations, then wait for it to finish
         */
+fail:
        spin_unlock(&boot_lock);
-        return pen_release != -1 ? -ENOSYS : 0;
+        return pen_release != -1 ? ret : 0;
 }
 /*
@@ -205,6 +237,8 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
        if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9)
                scu_enable(scu_base_addr());
+        exynos_smp_prepare_sysram();
        /*
         * Write the address of secondary startup into the
         * system-wide flags register. The boot monitor waits
@@ -217,12 +251,21 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
        for (i = 1; i < max_cpus; ++i) {
                unsigned long phys_cpu;
                unsigned long boot_addr;
+                int ret;
                phys_cpu = cpu_logical_map(i);
                boot_addr = virt_to_phys(exynos4_secondary_startup);
-                if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
+                ret = call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr);
+                if (ret && ret != -ENOSYS)
+                        break;
+                if (ret == -ENOSYS) {
+                        void __iomem *boot_reg = cpu_boot_reg(phys_cpu);
+                        if (IS_ERR(boot_reg))
+                                break;
                        __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
+                }
        }
 }
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c
index 15af0ceb0a66..87c0d34c7fba 100644
--- a/arch/arm/mach-exynos/pm.c
+++ b/arch/arm/mach-exynos/pm.c
@@ -16,6 +16,7 @@
 #include <linux/init.h>
 #include <linux/suspend.h>
 #include <linux/syscore_ops.h>
+#include <linux/cpu_pm.h>
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 #include <linux/err.h>
@@ -26,7 +27,6 @@
 #include <asm/smp_scu.h>
 #include <asm/suspend.h>
-#include <plat/cpu.h>
 #include <plat/pm-common.h>
 #include <plat/pll.h>
 #include <plat/regs-srom.h>
@@ -100,9 +100,141 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
        return -ENOENT;
 }
+/**
+ * exynos_core_power_down : power down the specified cpu
+ * @cpu : the cpu to power down
+ *
+ * Power down the specified cpu. The sequence must be finished by a
+ * call to cpu_do_idle()
+ *
+ */
+void exynos_cpu_power_down(int cpu)
+{
+        __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+/**
+ * exynos_cpu_power_up : power up the specified cpu
+ * @cpu : the cpu to power up
+ *
+ * Power up the specified cpu
+ */
+void exynos_cpu_power_up(int cpu)
+{
+        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                     EXYNOS_ARM_CORE_CONFIGURATION(cpu));
+}
+/**
+ * exynos_cpu_power_state : returns the power state of the cpu
+ * @cpu : the cpu to retrieve the power state from
+ *
+ */
+int exynos_cpu_power_state(int cpu)
+{
+        return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
+                        S5P_CORE_LOCAL_PWR_EN);
+}
+/**
+ * exynos_cluster_power_down : power down the specified cluster
+ * @cluster : the cluster to power down
+ */
+void exynos_cluster_power_down(int cluster)
+{
+        __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+/**
+ * exynos_cluster_power_up : power up the specified cluster
+ * @cluster : the cluster to power up
+ */
+void exynos_cluster_power_up(int cluster)
+{
+        __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+                     EXYNOS_COMMON_CONFIGURATION(cluster));
+}
+/**
+ * exynos_cluster_power_state : returns the power state of the cluster
+ * @cluster : the cluster to retrieve the power state from
+ *
+ */
+int exynos_cluster_power_state(int cluster)
+{
+        return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
+                        S5P_CORE_LOCAL_PWR_EN);
+}
+#define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (sysram_base_addr + 0x24) : S5P_INFORM0))
+#define EXYNOS_BOOT_VECTOR_FLAG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
+                        S5P_INFORM6 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \
+                        (sysram_base_addr + 0x20) : S5P_INFORM1))
+#define S5P_CHECK_AFTR  0xFCBA0D10
+#define S5P_CHECK_SLEEP 0x00000BAD
+/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
+static void exynos_set_wakeupmask(long mask)
+{
+        __raw_writel(mask, S5P_WAKEUP_MASK);
+}
+static void exynos_cpu_set_boot_vector(long flags)
+{
+        __raw_writel(virt_to_phys(exynos_cpu_resume), EXYNOS_BOOT_VECTOR_ADDR);
+        __raw_writel(flags, EXYNOS_BOOT_VECTOR_FLAG);
+}
+void exynos_enter_aftr(void)
+{
+        exynos_set_wakeupmask(0x0000ff3e);
+        exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
+        /* Set value of power down register for aftr mode */
+        exynos_sys_powerdown_conf(SYS_AFTR);
+}
 /* For Cortex-A9 Diagnostic and Power control register */
 static unsigned int save_arm_register[2];
+static void exynos_cpu_save_register(void)
+{
+        unsigned long tmp;
+        /* Save Power control register */
+        asm ("mrc p15, 0, %0, c15, c0, 0"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[0] = tmp;
+        /* Save Diagnostic register */
+        asm ("mrc p15, 0, %0, c15, c0, 1"
+             : "=r" (tmp) : : "cc");
+        save_arm_register[1] = tmp;
+}
+static void exynos_cpu_restore_register(void)
+{
+        unsigned long tmp;
+        /* Restore Power control register */
+        tmp = save_arm_register[0];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+                      : : "r" (tmp)
+                      : "cc");
+        /* Restore Diagnostic register */
+        tmp = save_arm_register[1];
+        asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+                      : : "r" (tmp)
+                      : "cc");
+}
 static int exynos_cpu_suspend(unsigned long arg)
 {
 #ifdef CONFIG_CACHE_L2X0
@@ -147,37 +279,34 @@ static void exynos_pm_prepare(void)
        __raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
 }
-static int exynos_pm_suspend(void)
+static void exynos_pm_central_suspend(void)
 {
        unsigned long tmp;
        /* Setting Central Sequence Register for power down mode */
        tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
        __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+}
+static int exynos_pm_suspend(void)
+{
+        unsigned long tmp;
+        exynos_pm_central_suspend();
        /* Setting SEQ_OPTION register */
        tmp = (S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0);
        __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-        if (!soc_is_exynos5250()) {
+        if (!soc_is_exynos5250())
-                /* Save Power control register */
+                exynos_cpu_save_register();
-                asm ("mrc p15, 0, %0, c15, c0, 0"
-                     : "=r" (tmp) : : "cc");
-                save_arm_register[0] = tmp;
-                /* Save Diagnostic register */
-                asm ("mrc p15, 0, %0, c15, c0, 1"
-                     : "=r" (tmp) : : "cc");
-                save_arm_register[1] = tmp;
-        }
        return 0;
 }
-static void exynos_pm_resume(void)
+static int exynos_pm_central_resume(void)
 {
        unsigned long tmp;
@@ -194,22 +323,20 @@ static void exynos_pm_resume(void)
                /* clear the wakeup state register */
                __raw_writel(0x0, S5P_WAKEUP_STAT);
                /* No need to perform below restore code */
-                goto early_wakeup;
+                return -1;
-        }
-        if (!soc_is_exynos5250()) {
-                /* Restore Power control register */
-                tmp = save_arm_register[0];
-                asm volatile ("mcr p15, 0, %0, c15, c0, 0"
-                              : : "r" (tmp)
-                              : "cc");
-                /* Restore Diagnostic register */
-                tmp = save_arm_register[1];
-                asm volatile ("mcr p15, 0, %0, c15, c0, 1"
-                              : : "r" (tmp)
-                              : "cc");
        }
+        return 0;
+}
+static void exynos_pm_resume(void)
+{
+        if (exynos_pm_central_resume())
+                goto early_wakeup;
+        if (!soc_is_exynos5250())
+                exynos_cpu_restore_register();
        /* For release retention */
        __raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -226,7 +353,7 @@ static void exynos_pm_resume(void)
        s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
-        if (IS_ENABLED(CONFIG_SMP) && !soc_is_exynos5250())
+        if (!soc_is_exynos5250())
                scu_enable(S5P_VA_SCU);
 early_wakeup:
@@ -304,10 +431,42 @@ static const struct platform_suspend_ops exynos_suspend_ops = {
        .valid          = suspend_valid_only_mem,
 };
+static int exynos_cpu_pm_notifier(struct notifier_block *self,
+                                  unsigned long cmd, void *v)
+{
+        int cpu = smp_processor_id();
+        switch (cmd) {
+        case CPU_PM_ENTER:
+                if (cpu == 0) {
+                        exynos_pm_central_suspend();
+                        exynos_cpu_save_register();
+                }
+                break;
+        case CPU_PM_EXIT:
+                if (cpu == 0) {
+                        if (!soc_is_exynos5250())
+                                scu_enable(S5P_VA_SCU);
+                        exynos_cpu_restore_register();
+                        exynos_pm_central_resume();
+                }
+                break;
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block exynos_cpu_pm_notifier_block = {
+        .notifier_call = exynos_cpu_pm_notifier,
+};
 void __init exynos_pm_init(void)
 {
        u32 tmp;
+        cpu_pm_register_notifier(&exynos_cpu_pm_notifier_block);
        /* Platform-specific GIC callback */
        gic_arch_extn.irq_set_wake = exynos_irq_set_wake;
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 05c7ce15322a..fb0deda3b3a4 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -13,8 +13,6 @@
 #include <linux/kernel.h>
 #include <linux/bug.h>
-#include <plat/cpu.h>
 #include "common.h"
 #include "regs-pmu.h"
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 4f6a2560d022..1d13b08708f0 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
 #define S5P_INFORM5                             S5P_PMUREG(0x0814)
 #define S5P_INFORM6                             S5P_PMUREG(0x0818)
 #define S5P_INFORM7                             S5P_PMUREG(0x081C)
+#define S5P_PMU_SPARE3                          S5P_PMUREG(0x090C)
 #define S5P_ARM_CORE0_LOWPWR                    S5P_PMUREG(0x1000)
 #define S5P_DIS_IRQ_CORE0                       S5P_PMUREG(0x1004)
@@ -105,8 +106,17 @@
 #define S5P_GPS_LOWPWR                          S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR                    S5P_PMUREG(0x13A0)
-#define S5P_ARM_CORE1_CONFIGURATION             S5P_PMUREG(0x2080)
+#define EXYNOS_ARM_CORE0_CONFIGURATION          S5P_PMUREG(0x2000)
-#define S5P_ARM_CORE1_STATUS                    S5P_PMUREG(0x2084)
+#define EXYNOS_ARM_CORE_CONFIGURATION(_nr)      \
+                        (EXYNOS_ARM_CORE0_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_ARM_CORE_STATUS(_nr)             \
+                        (EXYNOS_ARM_CORE_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_ARM_COMMON_CONFIGURATION         S5P_PMUREG(0x2500)
+#define EXYNOS_COMMON_CONFIGURATION(_nr)        \
+                        (EXYNOS_ARM_COMMON_CONFIGURATION + (0x80 * (_nr)))
+#define EXYNOS_COMMON_STATUS(_nr)               \
+                        (EXYNOS_COMMON_CONFIGURATION(_nr) + 0x4)
 #define S5P_PAD_RET_MAUDIO_OPTION               S5P_PMUREG(0x3028)
 #define S5P_PAD_RET_GPIO_OPTION                 S5P_PMUREG(0x3108)
@@ -119,8 +129,6 @@
 #define S5P_CORE_LOCAL_PWR_EN                   0x3
 #define S5P_INT_LOCAL_PWR_EN                    0x7
-#define S5P_CHECK_SLEEP                         0x00000BAD
 /* Only for EXYNOS4210 */
 #define S5P_CMU_CLKSTOP_LCD1_LOWPWR     S5P_PMUREG(0x1154)
 #define S5P_CMU_RESET_LCD1_LOWPWR       S5P_PMUREG(0x1174)
@@ -313,4 +321,6 @@
 #define EXYNOS5_OPTION_USE_RETENTION                            (1 << 4)
+#define EXYNOS5420_SWRESET_KFC_SEL                              0x3
 #endif /* __ASM_ARCH_REGS_PMU_H */
diff --git a/arch/arm/mach-exynos/sleep.S b/arch/arm/mach-exynos/sleep.S
index a2613e944e10..108a45f4bb62 100644
--- a/arch/arm/mach-exynos/sleep.S
+++ b/arch/arm/mach-exynos/sleep.S
@@ -16,8 +16,6 @@
 */
 #include <linux/linkage.h>
-#include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
 #define CPU_MASK        0xff0ffff0
 #define CPU_CORTEX_A9   0x410fc090
@@ -53,33 +51,7 @@ ENTRY(exynos_cpu_resume)
        and     r0, r0, r1
        ldr     r1, =CPU_CORTEX_A9
        cmp     r0, r1
-        bne     skip_l2_resume
+        bleq    l2c310_early_resume
-        adr     r0, l2x0_regs_phys
-        ldr     r0, [r0]
-        cmp     r0, #0
-        beq     skip_l2_resume
-        ldr     r1, [r0, #L2X0_R_PHY_BASE]
-        ldr     r2, [r1, #L2X0_CTRL]
-        tst     r2, #0x1
-        bne     skip_l2_resume
-        ldr     r2, [r0, #L2X0_R_AUX_CTRL]
-        str     r2, [r1, #L2X0_AUX_CTRL]
-        ldr     r2, [r0, #L2X0_R_TAG_LATENCY]
-        str     r2, [r1, #L2X0_TAG_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_DATA_LATENCY]
-        str     r2, [r1, #L2X0_DATA_LATENCY_CTRL]
-        ldr     r2, [r0, #L2X0_R_PREFETCH_CTRL]
-        str     r2, [r1, #L2X0_PREFETCH_CTRL]
-        ldr     r2, [r0, #L2X0_R_PWR_CTRL]
-        str     r2, [r1, #L2X0_POWER_CTRL]
-        mov     r2, #1
-        str     r2, [r1, #L2X0_CTRL]
-skip_l2_resume:
 #endif
        b       cpu_resume
 ENDPROC(exynos_cpu_resume)
-#ifdef CONFIG_CACHE_L2X0
-        .globl l2x0_regs_phys
-l2x0_regs_phys:
-        .long   0
-#endif
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index da0415094856..8f05489671b7 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -76,7 +76,7 @@ __initcall(cats_hw_init);
 * hard reboots fail on early boards.
 */
 static void __init
-fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
+fixup_cats(struct tag *tags, char **cmdline)
 {
 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
        screen_info.orig_video_lines  = 25;
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index eb1fa5c84723..cdee08c6d239 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -620,7 +620,7 @@ __initcall(nw_hw_init);
 * the parameter page.
 */
 static void __init
-fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
+fixup_netwinder(struct tag *tags, char **cmdline)
 {
 #ifdef CONFIG_ISAPNP
        extern int isapnp_disable;
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index c7de89b263dd..8c35ae4ff176 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -51,11 +51,13 @@ static void __init highbank_scu_map_io(void)
 }
-static void highbank_l2x0_disable(void)
+static void highbank_l2c310_write_sec(unsigned long val, unsigned reg)
 {
-        outer_flush_all();
+        if (reg == L2X0_CTRL)
-        /* Disable PL310 L2 Cache controller */
+                highbank_smc1(0x102, val);
-        highbank_smc1(0x102, 0x0);
+        else
+                WARN_ONCE(1, "Highbank L2C310: ignoring write to reg 0x%x\n",
+                          reg);
 }
 static void __init highbank_init_irq(void)
@@ -64,14 +66,6 @@ static void __init highbank_init_irq(void)
        if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
                highbank_scu_map_io();
-        /* Enable PL310 L2 Cache controller */
-        if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
-            of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
-                highbank_smc1(0x102, 0x1);
-                l2x0_of_init(0, ~0UL);
-                outer_cache.disable = highbank_l2x0_disable;
-        }
 }
 static void highbank_power_off(void)
@@ -185,6 +179,9 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
 #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
        .dma_zone_size  = (4ULL * SZ_1G),
 #endif
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
+        .l2c_write_sec  = highbank_l2c310_write_sec,
        .init_irq       = highbank_init_irq,
        .init_machine   = highbank_init,
        .dt_compat      = highbank_match,
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 5740296dc429..8d42eab76d53 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -702,61 +702,6 @@ endif
 if ARCH_MULTI_V7
-comment "i.MX51 machines:"
-config MACH_IMX51_DT
-        bool "Support i.MX51 platforms from device tree"
-        select SOC_IMX51
-        help
-          Include support for Freescale i.MX51 based platforms
-          using the device tree for discovery
-config MACH_MX51_BABBAGE
-        bool "Support MX51 BABBAGE platforms"
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX51
-        help
-          Include support for MX51 Babbage platform, also known as MX51EVK in
-          u-boot. This includes specific configurations for the board and its
-          peripherals.
-config MACH_EUKREA_CPUIMX51SD
-        bool "Support Eukrea CPUIMX51SD module"
-        select IMX_HAVE_PLATFORM_FSL_USB2_UDC
-        select IMX_HAVE_PLATFORM_IMX2_WDT
-        select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_UART
-        select IMX_HAVE_PLATFORM_MXC_EHCI
-        select IMX_HAVE_PLATFORM_MXC_NAND
-        select IMX_HAVE_PLATFORM_SPI_IMX
-        select SOC_IMX51
-        help
-          Include support for Eukrea CPUIMX51SD platform. This includes
-          specific configurations for the module and its peripherals.
-choice
-        prompt "Baseboard"
-        depends on MACH_EUKREA_CPUIMX51SD
-        default MACH_EUKREA_MBIMXSD51_BASEBOARD
-config MACH_EUKREA_MBIMXSD51_BASEBOARD
-        prompt "Eukrea MBIMXSD development board"
-        bool
-        select IMX_HAVE_PLATFORM_IMX_SSI
-        select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
-        select LEDS_GPIO_REGISTER
-        help
-          This adds board specific devices that can be found on Eukrea's
-          MBIMXSD evaluation board.
-endchoice
 comment "Device tree only"
 config  SOC_IMX50
@@ -768,6 +713,12 @@ config	SOC_IMX50
        help
          This enables support for Freescale i.MX50 processor.
+config MACH_IMX51_DT
+        bool "i.MX51 support"
+        select SOC_IMX51
+        help
+          This enables support for Freescale i.MX51 processor
 config  SOC_IMX53
        bool "i.MX53 support"
        select HAVE_IMX_SRC
@@ -796,7 +747,6 @@ config SOC_IMX6Q
        select ARM_ERRATA_764369 if SMP
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select MIGHT_HAVE_PCI
        select PCI_DOMAINS if PCI
        select PINCTRL_IMX6Q
        select SOC_IMX6
@@ -812,6 +762,14 @@ config SOC_IMX6SL
        help
          This enables support for Freescale i.MX6 SoloLite processor.
+config SOC_IMX6SX
+        bool "i.MX6 SoloX support"
+        select PINCTRL_IMX6SX
+        select SOC_IMX6
+        help
+          This enables support for Freescale i.MX6 SoloX processor.
 config SOC_VF610
        bool "Vybrid Family VF610 support"
        select ARM_GIC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index f4ed83032dd0..bbe93bbfd003 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_SMP) += headsmp.o platsmp.o
 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
 obj-$(CONFIG_SOC_IMX6Q) += clk-imx6q.o mach-imx6q.o
 obj-$(CONFIG_SOC_IMX6SL) += clk-imx6sl.o mach-imx6sl.o
+obj-$(CONFIG_SOC_IMX6SX) += clk-imx6sx.o mach-imx6sx.o
 ifeq ($(CONFIG_SUSPEND),y)
 AFLAGS_suspend-imx6.o :=-Wa,-march=armv7-a
@@ -108,11 +109,6 @@ obj-$(CONFIG_SOC_IMX6) += suspend-imx6.o
 endif
 obj-$(CONFIG_SOC_IMX6) += pm-imx6.o
-# i.MX5 based machines
-obj-$(CONFIG_MACH_MX51_BABBAGE) += mach-mx51_babbage.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += mach-cpuimx51sd.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd51-baseboard.o
 obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
 obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
 obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 8d1df2e4b7ac..24b103c67f82 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -135,7 +135,7 @@ static __init void avic_init_gc(int idx, unsigned int irq_start)
        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
-asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
+static void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
 {
        u32 nivector;
@@ -190,6 +190,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
        for (i = 0; i < 8; i++)
                __raw_writel(0, avic_base + AVIC_NIPRIORITY(i));
+        set_handle_irq(avic_handle_irq);
 #ifdef CONFIG_FIQ
        /* Initialize FIQ */
        init_FIQ(FIQ_START);
diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c
index a2ecc006b322..4ba587da89d2 100644
--- a/arch/arm/mach-imx/clk-gate2.c
+++ b/arch/arm/mach-imx/clk-gate2.c
@@ -27,48 +27,61 @@
 * parent - fixed parent.  No clk_set_parent support
 */
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+struct clk_gate2 {
+        struct clk_hw hw;
+        void __iomem    *reg;
+        u8              bit_idx;
+        u8              flags;
+        spinlock_t      *lock;
+        unsigned int    *share_count;
+};
+#define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw)
 static int clk_gate2_enable(struct clk_hw *hw)
 {
-        struct clk_gate *gate = to_clk_gate(hw);
+        struct clk_gate2 *gate = to_clk_gate2(hw);
        u32 reg;
        unsigned long flags = 0;
-        if (gate->lock)
+        spin_lock_irqsave(gate->lock, flags);
-                spin_lock_irqsave(gate->lock, flags);
+        if (gate->share_count && (*gate->share_count)++ > 0)
+                goto out;
        reg = readl(gate->reg);
        reg |= 3 << gate->bit_idx;
        writel(reg, gate->reg);
-        if (gate->lock)
+out:
-                spin_unlock_irqrestore(gate->lock, flags);
+        spin_unlock_irqrestore(gate->lock, flags);
        return 0;
 }
 static void clk_gate2_disable(struct clk_hw *hw)
 {
-        struct clk_gate *gate = to_clk_gate(hw);
+        struct clk_gate2 *gate = to_clk_gate2(hw);
        u32 reg;
        unsigned long flags = 0;
-        if (gate->lock)
+        spin_lock_irqsave(gate->lock, flags);
-                spin_lock_irqsave(gate->lock, flags);
+        if (gate->share_count && --(*gate->share_count) > 0)
+                goto out;
        reg = readl(gate->reg);
        reg &= ~(3 << gate->bit_idx);
        writel(reg, gate->reg);
-        if (gate->lock)
+out:
-                spin_unlock_irqrestore(gate->lock, flags);
+        spin_unlock_irqrestore(gate->lock, flags);
 }
 static int clk_gate2_is_enabled(struct clk_hw *hw)
 {
        u32 reg;
-        struct clk_gate *gate = to_clk_gate(hw);
+        struct clk_gate2 *gate = to_clk_gate2(hw);
        reg = readl(gate->reg);
@@ -87,21 +100,23 @@ static struct clk_ops clk_gate2_ops = {
 struct clk *clk_register_gate2(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                void __iomem *reg, u8 bit_idx,
-                u8 clk_gate2_flags, spinlock_t *lock)
+                u8 clk_gate2_flags, spinlock_t *lock,
+                unsigned int *share_count)
 {
-        struct clk_gate *gate;
+        struct clk_gate2 *gate;
        struct clk *clk;
        struct clk_init_data init;
-        gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
+        gate = kzalloc(sizeof(struct clk_gate2), GFP_KERNEL);
        if (!gate)
                return ERR_PTR(-ENOMEM);
-        /* struct clk_gate assignments */
+        /* struct clk_gate2 assignments */
        gate->reg = reg;
        gate->bit_idx = bit_idx;
        gate->flags = clk_gate2_flags;
        gate->lock = lock;
+        gate->share_count = share_count;
        init.name = name;
        init.ops = &clk_gate2_ops;
diff --git a/arch/arm/mach-imx/clk-imx1.c b/arch/arm/mach-imx/clk-imx1.c
index 15f9d223cf0b..7f739be3de2c 100644
--- a/arch/arm/mach-imx/clk-imx1.c
+++ b/arch/arm/mach-imx/clk-imx1.c
@@ -40,12 +40,14 @@
 #define SCM_GCCR        IO_ADDR_SCM(0xc)
 static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
-static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m", "prem",
+static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
-                                "fclk", };
+                                       "prem", "fclk", };
 enum imx1_clks {
-        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, spll, mcu,
+        dummy, clk32, clk16m_ext, clk16m, clk32_premult, prem, mpll, mpll_gate,
-        fclk, hclk, clk48m, per1, per2, per3, clko, dma_gate, csi_gate,
+        spll, spll_gate, mcu, fclk, hclk, clk48m, per1, per2, per3, clko,
-        mma_gate, usbd_gate, clk_max
+        uart3_gate, ssi2_gate, brom_gate, dma_gate, csi_gate, mma_gate,
+        usbd_gate, clk_max
 };
 static struct clk *clk[clk_max];
@@ -62,17 +64,22 @@ int __init mx1_clocks_init(unsigned long fref)
        clk[prem] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks,
                        ARRAY_SIZE(prem_sel_clks));
        clk[mpll] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
+        clk[mpll_gate] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
        clk[spll] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
+        clk[spll_gate] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
        clk[mcu] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
-        clk[fclk] = imx_clk_divider("fclk", "mpll", CCM_CSCR, 15, 1);
+        clk[fclk] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
-        clk[hclk] = imx_clk_divider("hclk", "spll", CCM_CSCR, 10, 4);
+        clk[hclk] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
-        clk[clk48m] = imx_clk_divider("clk48m", "spll", CCM_CSCR, 26, 3);
+        clk[clk48m] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
-        clk[per1] = imx_clk_divider("per1", "spll", CCM_PCDR, 0, 4);
+        clk[per1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
-        clk[per2] = imx_clk_divider("per2", "spll", CCM_PCDR, 4, 4);
+        clk[per2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
-        clk[per3] = imx_clk_divider("per3", "spll", CCM_PCDR, 16, 7);
+        clk[per3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
        clk[clko] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks,
                        ARRAY_SIZE(clko_sel_clks));
-        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 4);
+        clk[uart3_gate] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
+        clk[ssi2_gate] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
+        clk[brom_gate] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
+        clk[dma_gate] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
        clk[csi_gate] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
        clk[mma_gate] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
        clk[usbd_gate] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
@@ -84,9 +91,6 @@ int __init mx1_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[dma_gate], "ahb", "imx1-dma");
        clk_register_clkdev(clk[hclk], "ipg", "imx1-dma");
-        clk_register_clkdev(clk[csi_gate], NULL, "mx1-camera.0");
-        clk_register_clkdev(clk[mma_gate], "mma", NULL);
-        clk_register_clkdev(clk[usbd_gate], NULL, "imx_udc.0");
        clk_register_clkdev(clk[per1], "per", "imx-gpt.0");
        clk_register_clkdev(clk[hclk], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[per1], "per", "imx1-uart.0");
@@ -94,20 +98,15 @@ int __init mx1_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[per1], "per", "imx1-uart.1");
        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.1");
        clk_register_clkdev(clk[per1], "per", "imx1-uart.2");
-        clk_register_clkdev(clk[hclk], "ipg", "imx1-uart.2");
+        clk_register_clkdev(clk[uart3_gate], "ipg", "imx1-uart.2");
        clk_register_clkdev(clk[hclk], NULL, "imx1-i2c.0");
        clk_register_clkdev(clk[per2], "per", "imx1-cspi.0");
        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.0");
        clk_register_clkdev(clk[per2], "per", "imx1-cspi.1");
        clk_register_clkdev(clk[dummy], "ipg", "imx1-cspi.1");
-        clk_register_clkdev(clk[per2], NULL, "imx-mmc.0");
        clk_register_clkdev(clk[per2], "per", "imx1-fb.0");
        clk_register_clkdev(clk[dummy], "ipg", "imx1-fb.0");
        clk_register_clkdev(clk[dummy], "ahb", "imx1-fb.0");
-        clk_register_clkdev(clk[hclk], "mshc", NULL);
-        clk_register_clkdev(clk[per3], "ssi", NULL);
-        clk_register_clkdev(clk[clk32], NULL, "imx1-rtc.0");
-        clk_register_clkdev(clk[clko], "clko", NULL);
        mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index dc36e6c2f1da..ae578c096ad8 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -62,6 +62,10 @@ static struct clk_onecell_data clk_data;
 static const char *cpu_sel_clks[] = { "mpll", "mpll_cpu_3_4", };
 static const char *per_sel_clks[] = { "ahb", "upll", };
+static const char *cko_sel_clks[] = { "dummy", "osc", "cpu", "ahb",
+                                      "ipg", "dummy", "dummy", "dummy",
+                                      "dummy", "dummy", "per0", "per2",
+                                      "per13", "per14", "usbotg_ahb", "dummy",};
 enum mx25_clks {
        dummy, osc, mpll, upll, mpll_cpu_3_4, cpu_sel, cpu, ahb, usb_div, ipg,
@@ -82,7 +86,7 @@ enum mx25_clks {
        pwm2_ipg, pwm3_ipg, pwm4_ipg, rngb_ipg, reserved16, scc_ipg, sdma_ipg,
        sim1_ipg, sim2_ipg, slcdc_ipg, spba_ipg, ssi1_ipg, ssi2_ipg, tsc_ipg,
        uart1_ipg, uart2_ipg, uart3_ipg, uart4_ipg, uart5_ipg, reserved17,
-        wdt_ipg, clk_max
+        wdt_ipg, cko_div, cko_sel, cko, clk_max
 };
 static struct clk *clk[clk_max];
@@ -117,6 +121,9 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
        clk[per13_sel] = imx_clk_mux("per13_sel", ccm(CCM_MCR), 13, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
        clk[per14_sel] = imx_clk_mux("per14_sel", ccm(CCM_MCR), 14, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
        clk[per15_sel] = imx_clk_mux("per15_sel", ccm(CCM_MCR), 15, 1, per_sel_clks, ARRAY_SIZE(per_sel_clks));
+        clk[cko_div] = imx_clk_divider("cko_div", "cko_sel", ccm(CCM_MCR), 24, 6);
+        clk[cko_sel] = imx_clk_mux("cko_sel", ccm(CCM_MCR), 20, 4, cko_sel_clks, ARRAY_SIZE(cko_sel_clks));
+        clk[cko] = imx_clk_gate("cko", "cko_div", ccm(CCM_MCR),  30);
        clk[per0] = imx_clk_divider("per0", "per0_sel", ccm(CCM_PCDR0), 0, 6);
        clk[per1] = imx_clk_divider("per1", "per1_sel", ccm(CCM_PCDR0), 8, 6);
        clk[per2] = imx_clk_divider("per2", "per2_sel", ccm(CCM_PCDR0), 16, 6);
@@ -230,6 +237,12 @@ static int __init __mx25_clocks_init(unsigned long osc_rate)
        clk_register_clkdev(clk[ipg], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
+        /*
+         * Let's initially set up CLKO parent as ipg, since this configuration
+         * is used on some imx25 board designs to clock the audio codec.
+         */
+        clk_set_parent(clk[cko_sel], clk[ipg]);
        return 0;
 }
@@ -304,8 +317,6 @@ int __init mx25_clocks_init(void)
 int __init mx25_clocks_init_dt(void)
 {
        struct device_node *np;
-        void __iomem *base;
-        int irq;
        unsigned long osc_rate = 24000000;
        /* retrieve the freqency of fixed clocks from device tree */
@@ -325,12 +336,7 @@ int __init mx25_clocks_init_dt(void)
        __mx25_clocks_init(osc_rate);
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt");
+        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx25-gpt"));
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
        return 0;
 }
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index d2da8908b268..317a662626d6 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -82,7 +82,8 @@ enum mx27_clks {
        csi_ahb_gate, brom_ahb_gate, ata_ahb_gate, wdog_ipg_gate, usb_ipg_gate,
        uart6_ipg_gate, uart5_ipg_gate, uart4_ipg_gate, uart3_ipg_gate,
        uart2_ipg_gate, uart1_ipg_gate, ckih_div1p5, fpm, mpll_osc_sel,
-        mpll_sel, spll_gate, clk_max
+        mpll_sel, spll_gate, mshc_div, rtic_ipg_gate, mshc_ipg_gate,
+        rtic_ahb_gate, mshc_baud_gate, clk_max
 };
 static struct clk *clk[clk_max];
@@ -117,6 +118,7 @@ int __init mx27_clocks_init(unsigned long fref)
                clk[ipg] = imx_clk_divider("ipg", "ahb", CCM_CSCR, 8, 1);
        }
+        clk[mshc_div] = imx_clk_divider("mshc_div", "ahb", CCM_PCDR0, 0, 6);
        clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", CCM_PCDR0, 6, 4);
        clk[per1_div] = imx_clk_divider("per1_div", "mpll_main2", CCM_PCDR1, 0, 6);
        clk[per2_div] = imx_clk_divider("per2_div", "mpll_main2", CCM_PCDR1, 8, 6);
@@ -145,9 +147,11 @@ int __init mx27_clocks_init(unsigned long fref)
        clk[sdhc1_ipg_gate] = imx_clk_gate("sdhc1_ipg_gate", "ipg", CCM_PCCR0, 5);
        clk[scc_ipg_gate] = imx_clk_gate("scc_ipg_gate", "ipg", CCM_PCCR0, 6);
        clk[sahara_ipg_gate] = imx_clk_gate("sahara_ipg_gate", "ipg", CCM_PCCR0, 7);
+        clk[rtic_ipg_gate] = imx_clk_gate("rtic_ipg_gate", "ipg", CCM_PCCR0, 8);
        clk[rtc_ipg_gate] = imx_clk_gate("rtc_ipg_gate", "ipg", CCM_PCCR0, 9);
        clk[pwm_ipg_gate] = imx_clk_gate("pwm_ipg_gate", "ipg", CCM_PCCR0, 11);
        clk[owire_ipg_gate] = imx_clk_gate("owire_ipg_gate", "ipg", CCM_PCCR0, 12);
+        clk[mshc_ipg_gate] = imx_clk_gate("mshc_ipg_gate", "ipg", CCM_PCCR0, 13);
        clk[lcdc_ipg_gate] = imx_clk_gate("lcdc_ipg_gate", "ipg", CCM_PCCR0, 14);
        clk[kpp_ipg_gate] = imx_clk_gate("kpp_ipg_gate", "ipg", CCM_PCCR0, 15);
        clk[iim_ipg_gate] = imx_clk_gate("iim_ipg_gate", "ipg", CCM_PCCR0, 16);
@@ -166,6 +170,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk[cspi3_ipg_gate] = imx_clk_gate("cspi3_ipg_gate", "ipg", CCM_PCCR0, 29);
        clk[cspi2_ipg_gate] = imx_clk_gate("cspi2_ipg_gate", "ipg", CCM_PCCR0, 30);
        clk[cspi1_ipg_gate] = imx_clk_gate("cspi1_ipg_gate", "ipg", CCM_PCCR0, 31);
+        clk[mshc_baud_gate] = imx_clk_gate("mshc_baud_gate", "mshc_div", CCM_PCCR1, 2);
        clk[nfc_baud_gate] = imx_clk_gate("nfc_baud_gate", "nfc_div", CCM_PCCR1,  3);
        clk[ssi2_baud_gate] = imx_clk_gate("ssi2_baud_gate", "ssi2_div", CCM_PCCR1,  4);
        clk[ssi1_baud_gate] = imx_clk_gate("ssi1_baud_gate", "ssi1_div", CCM_PCCR1,  5);
@@ -177,6 +182,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk[usb_ahb_gate] = imx_clk_gate("usb_ahb_gate", "ahb", CCM_PCCR1, 11);
        clk[slcdc_ahb_gate] = imx_clk_gate("slcdc_ahb_gate", "ahb", CCM_PCCR1, 12);
        clk[sahara_ahb_gate] = imx_clk_gate("sahara_ahb_gate", "ahb", CCM_PCCR1, 13);
+        clk[rtic_ahb_gate] = imx_clk_gate("rtic_ahb_gate", "ahb", CCM_PCCR1, 14);
        clk[lcdc_ahb_gate] = imx_clk_gate("lcdc_ahb_gate", "ahb", CCM_PCCR1, 15);
        clk[vpu_ahb_gate] = imx_clk_gate("vpu_ahb_gate", "ahb", CCM_PCCR1, 16);
        clk[fec_ahb_gate] = imx_clk_gate("fec_ahb_gate", "ahb", CCM_PCCR1, 17);
@@ -221,16 +227,6 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[per1_gate], "per", "imx21-uart.5");
        clk_register_clkdev(clk[gpt1_ipg_gate], "ipg", "imx-gpt.0");
        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.0");
-        clk_register_clkdev(clk[gpt2_ipg_gate], "ipg", "imx-gpt.1");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.1");
-        clk_register_clkdev(clk[gpt3_ipg_gate], "ipg", "imx-gpt.2");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.2");
-        clk_register_clkdev(clk[gpt4_ipg_gate], "ipg", "imx-gpt.3");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.3");
-        clk_register_clkdev(clk[gpt5_ipg_gate], "ipg", "imx-gpt.4");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.4");
-        clk_register_clkdev(clk[gpt6_ipg_gate], "ipg", "imx-gpt.5");
-        clk_register_clkdev(clk[per1_gate], "per", "imx-gpt.5");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.0");
        clk_register_clkdev(clk[sdhc1_ipg_gate], "ipg", "imx21-mmc.0");
        clk_register_clkdev(clk[per2_gate], "per", "imx21-mmc.1");
@@ -278,14 +274,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_register_clkdev(clk[emma_ipg_gate], "emma-ipg", "imx27-camera.0");
        clk_register_clkdev(clk[emma_ahb_gate], "ahb", "m2m-emmaprp.0");
        clk_register_clkdev(clk[emma_ipg_gate], "ipg", "m2m-emmaprp.0");
-        clk_register_clkdev(clk[iim_ipg_gate], "iim", NULL);
-        clk_register_clkdev(clk[gpio_ipg_gate], "gpio", NULL);
-        clk_register_clkdev(clk[brom_ahb_gate], "brom", NULL);
-        clk_register_clkdev(clk[ata_ahb_gate], "ata", NULL);
-        clk_register_clkdev(clk[rtc_ipg_gate], NULL, "imx21-rtc");
-        clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
        clk_register_clkdev(clk[cpu_div], NULL, "cpu0");
-        clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
        mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
@@ -296,7 +285,6 @@ int __init mx27_clocks_init(unsigned long fref)
        return 0;
 }
-#ifdef CONFIG_OF
 int __init mx27_clocks_init_dt(void)
 {
        struct device_node *np;
@@ -312,4 +300,3 @@ int __init mx27_clocks_init_dt(void)
        return mx27_clocks_init(fref);
 }
-#endif
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index b5b65f3efaf1..4a9de0835eb1 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -191,7 +191,6 @@ int __init mx31_clocks_init(unsigned long fref)
        return 0;
 }
-#ifdef CONFIG_OF
 int __init mx31_clocks_init_dt(void)
 {
        struct device_node *np;
@@ -207,4 +206,3 @@ int __init mx31_clocks_init_dt(void)
        return mx31_clocks_init(fref);
 }
-#endif
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index a4d5e425cd82..71c86a2f856d 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -289,14 +289,12 @@ int __init mx35_clocks_init(void)
        return 0;
 }
-static int __init mx35_clocks_init_dt(struct device_node *ccm_node)
+static void __init mx35_clocks_init_dt(struct device_node *ccm_node)
 {
        clk_data.clks = clk;
        clk_data.clk_num = ARRAY_SIZE(clk);
        of_clk_add_provider(ccm_node, of_clk_src_onecell_get, &clk_data);
        mx35_clocks_init();
-        return 0;
 }
 CLK_OF_DECLARE(imx35, "fsl,imx35-ccm", mx35_clocks_init_dt);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 568ef0a4de84..21d2b111c83d 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -322,9 +322,8 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 static void __init mx50_clocks_init(struct device_node *np)
 {
-        void __iomem *base;
        unsigned long r;
-        int i, irq;
+        int i;
        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -372,11 +371,7 @@ static void __init mx50_clocks_init(struct device_node *np)
        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");
+        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt"));
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
 }
 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
@@ -436,7 +431,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
        clk_register_clkdev(clk[IMX5_CLK_HSI2C_GATE], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[IMX5_CLK_MX51_MIPI], "mipi_hsp", NULL);
-        clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx51-vpu.0");
        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx27-fec.0");
        clk_register_clkdev(clk[IMX5_CLK_USB_PHY_GATE], "phy", "mxc-ehci.0");
        clk_register_clkdev(clk[IMX5_CLK_ESDHC1_IPG_GATE], "ipg", "sdhci-esdhc-imx51.0");
@@ -492,9 +486,8 @@ CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init_dt);
 static void __init mx53_clocks_init(struct device_node *np)
 {
-        int i, irq;
+        int i;
        unsigned long r;
-        void __iomem *base;
        clk[IMX5_CLK_PLL1_SW]           = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
        clk[IMX5_CLK_PLL2_SW]           = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
@@ -561,7 +554,6 @@ static void __init mx53_clocks_init(struct device_node *np)
        mx5_clocks_common_init(0, 0, 0, 0);
-        clk_register_clkdev(clk[IMX5_CLK_VPU_GATE], NULL, "imx53-vpu.0");
        clk_register_clkdev(clk[IMX5_CLK_I2C3_GATE], NULL, "imx21-i2c.2");
        clk_register_clkdev(clk[IMX5_CLK_FEC_GATE], NULL, "imx25-fec.0");
        clk_register_clkdev(clk[IMX5_CLK_USB_PHY1_GATE], "usb_phy1", "mxc-ehci.0");
@@ -592,10 +584,6 @@ static void __init mx53_clocks_init(struct device_node *np)
        r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
        clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt");
+        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx53-gpt"));
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
 }
 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2b4d6acfa34a..8e795dea02ec 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -107,7 +107,7 @@ enum mx6q_clks {
        sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
        usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
        spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div,
-        lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max
+        lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, esai_ahb, clk_max
 };
 static struct clk *clk[clk_max];
@@ -140,11 +140,13 @@ static struct clk_div_table video_div_table[] = {
        { /* sentinel */ }
 };
+static unsigned int share_count_esai;
 static void __init imx6q_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
-        int i, irq;
+        int i;
        int ret;
        clk[dummy] = imx_clk_fixed("dummy", 0);
@@ -352,9 +354,14 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        clk[ecspi2]       = imx_clk_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
        clk[ecspi3]       = imx_clk_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
        clk[ecspi4]       = imx_clk_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
-        clk[ecspi5]       = imx_clk_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
+        if (cpu_is_imx6dl())
+                /* ecspi5 is replaced with i2c4 on imx6dl & imx6s */
+                clk[ecspi5] = imx_clk_gate2("i2c4",        "ipg_per",           base + 0x6c, 8);
+        else
+                clk[ecspi5] = imx_clk_gate2("ecspi5",      "ecspi_root",        base + 0x6c, 8);
        clk[enet]         = imx_clk_gate2("enet",          "ipg",               base + 0x6c, 10);
-        clk[esai]         = imx_clk_gate2("esai",          "esai_podf",         base + 0x6c, 16);
+        clk[esai]         = imx_clk_gate2_shared("esai",   "esai_podf",         base + 0x6c, 16, &share_count_esai);
+        clk[esai_ahb]     = imx_clk_gate2_shared("esai_ahb", "ahb",             base + 0x6c, 16, &share_count_esai);
        clk[gpt_ipg]      = imx_clk_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
        clk[gpt_ipg_per]  = imx_clk_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
        if (cpu_is_imx6dl())
@@ -489,10 +496,6 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
        /* Set initial power mode */
        imx6q_set_lpm(WAIT_CLOCKED);
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt");
+        mxc_timer_init_dt(of_find_compatible_node(NULL, NULL, "fsl,imx6q-gpt"));
-        base = of_iomap(np, 0);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
 }
 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index f7073c0782fb..21cf06cebade 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -169,7 +169,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
 {
        struct device_node *np;
        void __iomem *base;
-        int irq;
        int i;
        int ret;
@@ -385,9 +384,6 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
        imx6q_set_lpm(WAIT_CLOCKED);
        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-gpt");
-        base = of_iomap(np, 0);
+        mxc_timer_init_dt(np);
-        WARN_ON(!base);
-        irq = irq_of_parse_and_map(np, 0);
-        mxc_timer_init(base, irq);
 }
 CLK_OF_DECLARE(imx6sl, "fsl,imx6sl-ccm", imx6sl_clocks_init);
diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
new file mode 100644
index 000000000000..72f8902235d1
--- /dev/null
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -0,0 +1,524 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <dt-bindings/clock/imx6sx-clock.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/types.h>
+#include "clk.h"
+#include "common.h"
+#define CCDR    0x4
+#define BM_CCM_CCDR_MMDC_CH0_MASK       (0x2 << 16)
+static const char *step_sels[]          = { "osc", "pll2_pfd2_396m", };
+static const char *pll1_sw_sels[]       = { "pll1_sys", "step", };
+static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
+static const char *periph2_pre_sels[]   = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
+static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", };
+static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "osc", };
+static const char *periph_sels[]        = { "periph_pre", "periph_clk2", };
+static const char *periph2_sels[]       = { "periph2_pre", "periph2_clk2", };
+static const char *ocram_sels[]         = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
+static const char *audio_sels[]         = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
+static const char *gpu_axi_sels[]       = { "pll2_pfd2_396m", "pll3_pfd0_720m", "pll3_pfd1_540m", "pll2_bus", };
+static const char *gpu_core_sels[]      = { "pll3_pfd1_540m", "pll3_pfd0_720m", "pll2_bus", "pll2_pfd2_396m", };
+static const char *ldb_di0_div_sels[]   = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
+static const char *ldb_di1_div_sels[]   = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
+static const char *ldb_di0_sels[]       = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
+static const char *ldb_di1_sels[]       = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
+static const char *pcie_axi_sels[]      = { "axi", "ahb", };
+static const char *ssi_sels[]           = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
+static const char *qspi1_sels[]         = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
+static const char *perclk_sels[]        = { "ipg", "osc", };
+static const char *usdhc_sels[]         = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *vid_sels[]           = { "pll3_pfd1_540m", "pll3_usb_otg", "pll3_pfd3_454m", "pll4_audio_div", "pll5_video_div", };
+static const char *can_sels[]           = { "pll3_60m", "osc", "pll3_80m", "dummy", };
+static const char *uart_sels[]          = { "pll3_80m", "osc", };
+static const char *qspi2_sels[]         = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
+static const char *enet_pre_sels[]      = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
+static const char *enet_sels[]          = { "enet_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+static const char *m4_pre_sels[]        = { "pll2_bus", "pll3_usb_otg", "osc", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd3_454m", };
+static const char *m4_sels[]            = { "m4_pre_sel", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+static const char *eim_slow_sels[]      = { "ocram", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
+static const char *ecspi_sels[]         = { "pll3_60m", "osc", };
+static const char *lcdif1_pre_sels[]    = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
+static const char *lcdif1_sels[]        = { "lcdif1_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+static const char *lcdif2_pre_sels[]    = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd3_594m", "pll3_pfd1_540m", };
+static const char *lcdif2_sels[]        = { "lcdif2_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
+static const char *display_sels[]       = { "pll2_bus", "pll2_pfd2_396m", "pll3_usb_otg", "pll3_pfd1_540m", };
+static const char *csi_sels[]           = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
+static const char *cko1_sels[]          = {
+        "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
+        "dummy", "ocram", "dummy", "pxp_axi", "epdc_axi", "lcdif_pix",
+        "epdc_pix", "ahb", "ipg", "perclk", "ckil", "pll4_audio_div",
+};
+static const char *cko2_sels[]          = {
+        "dummy", "mmdc_p0_fast", "usdhc4", "usdhc1", "dummy", "wrck",
+        "ecspi_root", "dummy", "usdhc3", "pcie", "arm", "csi_core",
+        "lcdif_axi", "dummy", "osc", "dummy", "gpu2d_ovg_core",
+        "usdhc2", "ssi1", "ssi2", "ssi3", "gpu2d_core", "dummy",
+        "dummy", "dummy", "dummy", "esai_extal", "eim_slow", "uart_serial",
+        "spdif", "asrc", "dummy",
+};
+static const char *cko_sels[] = { "cko1", "cko2", };
+static const char *lvds_sels[]  = {
+        "arm", "pll1_sys", "dummy", "dummy", "dummy", "dummy", "dummy", "pll5_video_div",
+        "dummy", "dummy", "pcie_ref_125m", "dummy", "usbphy1", "usbphy2",
+};
+static struct clk *clks[IMX6SX_CLK_CLK_END];
+static struct clk_onecell_data clk_data;
+static int const clks_init_on[] __initconst = {
+        IMX6SX_CLK_AIPS_TZ1, IMX6SX_CLK_AIPS_TZ2, IMX6SX_CLK_AIPS_TZ3,
+        IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
+        IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
+        IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
+        IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
+        IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
+        IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
+        IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
+        IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
+        IMX6SX_CLK_EPIT2,
+};
+static struct clk_div_table clk_enet_ref_table[] = {
+        { .val = 0, .div = 20, },
+        { .val = 1, .div = 10, },
+        { .val = 2, .div = 5, },
+        { .val = 3, .div = 4, },
+        { }
+};
+static struct clk_div_table post_div_table[] = {
+        { .val = 2, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 0, .div = 4, },
+        { }
+};
+static struct clk_div_table video_div_table[] = {
+        { .val = 0, .div = 1, },
+        { .val = 1, .div = 2, },
+        { .val = 2, .div = 1, },
+        { .val = 3, .div = 4, },
+        { }
+};
+static u32 share_count_asrc;
+static u32 share_count_audio;
+static u32 share_count_esai;
+static void __init imx6sx_clocks_init(struct device_node *ccm_node)
+{
+        struct device_node *np;
+        void __iomem *base;
+        int i;
+        clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
+        clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil");
+        clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc");
+        /* ipp_di clock is external input */
+        clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0");
+        clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1");
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-anatop");
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        /*                                              type               name             parent_name   base         div_mask */
+        clks[IMX6SX_CLK_PLL1_SYS]       = imx_clk_pllv3(IMX_PLLV3_SYS,     "pll1_sys",      "osc",        base,        0x7f);
+        clks[IMX6SX_CLK_PLL2_BUS]       = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus",      "osc",        base + 0x30, 0x1);
+        clks[IMX6SX_CLK_PLL3_USB_OTG]   = imx_clk_pllv3(IMX_PLLV3_USB,     "pll3_usb_otg",  "osc",        base + 0x10, 0x3);
+        clks[IMX6SX_CLK_PLL4_AUDIO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll4_audio",    "osc",        base + 0x70, 0x7f);
+        clks[IMX6SX_CLK_PLL5_VIDEO]     = imx_clk_pllv3(IMX_PLLV3_AV,      "pll5_video",    "osc",        base + 0xa0, 0x7f);
+        clks[IMX6SX_CLK_PLL6_ENET]      = imx_clk_pllv3(IMX_PLLV3_ENET,    "pll6_enet",     "osc",        base + 0xe0, 0x3);
+        clks[IMX6SX_CLK_PLL7_USB_HOST]  = imx_clk_pllv3(IMX_PLLV3_USB,     "pll7_usb_host", "osc",        base + 0x20, 0x3);
+        /*
+         * Bit 20 is the reserved and read-only bit, we do this only for:
+         * - Do nothing for usbphy clk_enable/disable
+         * - Keep refcount when do usbphy clk_enable/disable, in that case,
+         * the clk framework may need to enable/disable usbphy's parent
+         */
+        clks[IMX6SX_CLK_USBPHY1] = imx_clk_gate("usbphy1", "pll3_usb_otg",  base + 0x10, 20);
+        clks[IMX6SX_CLK_USBPHY2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
+        /*
+         * usbphy*_gate needs to be on after system boots up, and software
+         * never needs to control it anymore.
+         */
+        clks[IMX6SX_CLK_USBPHY1_GATE] = imx_clk_gate("usbphy1_gate", "dummy", base + 0x10, 6);
+        clks[IMX6SX_CLK_USBPHY2_GATE] = imx_clk_gate("usbphy2_gate", "dummy", base + 0x20, 6);
+        /* FIXME 100Mhz is used for pcie ref for all imx6 pcie, excepted imx6q */
+        clks[IMX6SX_CLK_PCIE_REF] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 5);
+        clks[IMX6SX_CLK_PCIE_REF_125M] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
+        clks[IMX6SX_CLK_LVDS1_OUT] = imx_clk_gate("lvds1_out", "lvds1_sel", base + 0x160, 10);
+        clks[IMX6SX_CLK_ENET_REF] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
+                        base + 0xe0, 0, 2, 0, clk_enet_ref_table,
+                        &imx_ccm_lock);
+        clks[IMX6SX_CLK_ENET2_REF] = clk_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
+                        base + 0xe0, 2, 2, 0, clk_enet_ref_table,
+                        &imx_ccm_lock);
+        clks[IMX6SX_CLK_ENET2_REF_125M] = imx_clk_gate("enet2_ref_125m", "enet2_ref", base + 0xe0, 20);
+        clks[IMX6SX_CLK_ENET_PTP_REF] = imx_clk_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
+        clks[IMX6SX_CLK_ENET_PTP] = imx_clk_gate("enet_ptp_25m", "enet_ptp_ref", base + 0xe0, 21);
+        /*                                       name              parent_name     reg           idx */
+        clks[IMX6SX_CLK_PLL2_PFD0] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
+        clks[IMX6SX_CLK_PLL2_PFD1] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
+        clks[IMX6SX_CLK_PLL2_PFD2] = imx_clk_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
+        clks[IMX6SX_CLK_PLL2_PFD3] = imx_clk_pfd("pll2_pfd3_594m", "pll2_bus",     base + 0x100, 3);
+        clks[IMX6SX_CLK_PLL3_PFD0] = imx_clk_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
+        clks[IMX6SX_CLK_PLL3_PFD1] = imx_clk_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
+        clks[IMX6SX_CLK_PLL3_PFD2] = imx_clk_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
+        clks[IMX6SX_CLK_PLL3_PFD3] = imx_clk_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
+        /*                                                name         parent_name       mult div */
+        clks[IMX6SX_CLK_PLL2_198M] = imx_clk_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1,   2);
+        clks[IMX6SX_CLK_PLL3_120M] = imx_clk_fixed_factor("pll3_120m", "pll3_usb_otg",   1,   4);
+        clks[IMX6SX_CLK_PLL3_80M]  = imx_clk_fixed_factor("pll3_80m",  "pll3_usb_otg",   1,   6);
+        clks[IMX6SX_CLK_PLL3_60M]  = imx_clk_fixed_factor("pll3_60m",  "pll3_usb_otg",   1,   8);
+        clks[IMX6SX_CLK_TWD]       = imx_clk_fixed_factor("twd",       "arm",            1,   2);
+        clks[IMX6SX_CLK_GPT_3M]    = imx_clk_fixed_factor("gpt_3m",    "osc",            1,   8);
+        clks[IMX6SX_CLK_PLL4_POST_DIV]  = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
+                                CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SX_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
+                                CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
+        clks[IMX6SX_CLK_PLL5_POST_DIV]  = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video",
+                                CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
+        clks[IMX6SX_CLK_PLL5_VIDEO_DIV] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
+                                CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
+        /*                                                name                reg           shift   width   parent_names       num_parents */
+        clks[IMX6SX_CLK_LVDS1_SEL]          = imx_clk_mux("lvds1_sel",        base + 0x160, 0,      5,      lvds_sels,         ARRAY_SIZE(lvds_sels));
+        np = ccm_node;
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        imx6q_pm_set_ccm_base(base);
+        /*                                                name                reg           shift   width   parent_names       num_parents */
+        clks[IMX6SX_CLK_STEP]               = imx_clk_mux("step",             base + 0xc,   8,      1,      step_sels,         ARRAY_SIZE(step_sels));
+        clks[IMX6SX_CLK_PLL1_SW]            = imx_clk_mux("pll1_sw",          base + 0xc,   2,      1,      pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
+        clks[IMX6SX_CLK_OCRAM_SEL]          = imx_clk_mux("ocram_sel",        base + 0x14,  6,      2,      ocram_sels,        ARRAY_SIZE(ocram_sels));
+        clks[IMX6SX_CLK_PERIPH_PRE]         = imx_clk_mux("periph_pre",       base + 0x18,  18,     2,      periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
+        clks[IMX6SX_CLK_PERIPH2_PRE]        = imx_clk_mux("periph2_pre",      base + 0x18,  21,     2,      periph2_pre_sels,   ARRAY_SIZE(periph2_pre_sels));
+        clks[IMX6SX_CLK_PERIPH_CLK2_SEL]    = imx_clk_mux("periph_clk2_sel",  base + 0x18,  12,     2,      periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
+        clks[IMX6SX_CLK_PERIPH2_CLK2_SEL]   = imx_clk_mux("periph2_clk2_sel", base + 0x18,  20,     1,      periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
+        clks[IMX6SX_CLK_PCIE_AXI_SEL]       = imx_clk_mux("pcie_axi_sel",     base + 0x18,  10,     1,      pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
+        clks[IMX6SX_CLK_GPU_AXI_SEL]        = imx_clk_mux("gpu_axi_sel",      base + 0x18,  8,      2,      gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
+        clks[IMX6SX_CLK_GPU_CORE_SEL]       = imx_clk_mux("gpu_core_sel",     base + 0x18,  4,      2,      gpu_core_sels,     ARRAY_SIZE(gpu_core_sels));
+        clks[IMX6SX_CLK_EIM_SLOW_SEL]       = imx_clk_mux("eim_slow_sel",     base + 0x1c,  29,     2,      eim_slow_sels,     ARRAY_SIZE(eim_slow_sels));
+        clks[IMX6SX_CLK_USDHC1_SEL]         = imx_clk_mux("usdhc1_sel",       base + 0x1c,  16,     1,      usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SX_CLK_USDHC2_SEL]         = imx_clk_mux("usdhc2_sel",       base + 0x1c,  17,     1,      usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SX_CLK_USDHC3_SEL]         = imx_clk_mux("usdhc3_sel",       base + 0x1c,  18,     1,      usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SX_CLK_USDHC4_SEL]         = imx_clk_mux("usdhc4_sel",       base + 0x1c,  19,     1,      usdhc_sels,        ARRAY_SIZE(usdhc_sels));
+        clks[IMX6SX_CLK_SSI3_SEL]           = imx_clk_mux("ssi3_sel",         base + 0x1c,  14,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SX_CLK_SSI2_SEL]           = imx_clk_mux("ssi2_sel",         base + 0x1c,  12,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SX_CLK_SSI1_SEL]           = imx_clk_mux("ssi1_sel",         base + 0x1c,  10,     2,      ssi_sels,          ARRAY_SIZE(ssi_sels));
+        clks[IMX6SX_CLK_QSPI1_SEL]          = imx_clk_mux_flags("qspi1_sel", base + 0x1c,  7, 3, qspi1_sels, ARRAY_SIZE(qspi1_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_PERCLK_SEL]         = imx_clk_mux("perclk_sel",       base + 0x1c,  6,      1,      perclk_sels,       ARRAY_SIZE(perclk_sels));
+        clks[IMX6SX_CLK_VID_SEL]            = imx_clk_mux("vid_sel",          base + 0x20,  21,     3,      vid_sels,          ARRAY_SIZE(vid_sels));
+        clks[IMX6SX_CLK_ESAI_SEL]           = imx_clk_mux("esai_sel",         base + 0x20,  19,     2,      audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SX_CLK_CAN_SEL]            = imx_clk_mux("can_sel",          base + 0x20,  8,      2,      can_sels,          ARRAY_SIZE(can_sels));
+        clks[IMX6SX_CLK_UART_SEL]           = imx_clk_mux("uart_sel",         base + 0x24,  6,      1,      uart_sels,         ARRAY_SIZE(uart_sels));
+        clks[IMX6SX_CLK_QSPI2_SEL]          = imx_clk_mux_flags("qspi2_sel", base + 0x2c, 15, 3, qspi2_sels, ARRAY_SIZE(qspi2_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_SPDIF_SEL]          = imx_clk_mux("spdif_sel",        base + 0x30,  20,     2,      audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SX_CLK_AUDIO_SEL]          = imx_clk_mux("audio_sel",        base + 0x30,  7,      2,      audio_sels,        ARRAY_SIZE(audio_sels));
+        clks[IMX6SX_CLK_ENET_PRE_SEL]       = imx_clk_mux("enet_pre_sel",     base + 0x34,  15,     3,      enet_pre_sels,     ARRAY_SIZE(enet_pre_sels));
+        clks[IMX6SX_CLK_ENET_SEL]           = imx_clk_mux("enet_sel",         base + 0x34,  9,      3,      enet_sels,         ARRAY_SIZE(enet_sels));
+        clks[IMX6SX_CLK_M4_PRE_SEL]         = imx_clk_mux("m4_pre_sel",       base + 0x34,  6,      3,      m4_pre_sels,       ARRAY_SIZE(m4_pre_sels));
+        clks[IMX6SX_CLK_M4_SEL]             = imx_clk_mux("m4_sel",           base + 0x34,  0,      3,      m4_sels,           ARRAY_SIZE(m4_sels));
+        clks[IMX6SX_CLK_ECSPI_SEL]          = imx_clk_mux("ecspi_sel",        base + 0x38,  18,     1,      ecspi_sels,        ARRAY_SIZE(ecspi_sels));
+        clks[IMX6SX_CLK_LCDIF2_PRE_SEL]     = imx_clk_mux("lcdif2_pre_sel",   base + 0x38,  6,      3,      lcdif2_pre_sels,   ARRAY_SIZE(lcdif2_pre_sels));
+        clks[IMX6SX_CLK_LCDIF2_SEL]         = imx_clk_mux("lcdif2_sel",       base + 0x38,  0,      3,      lcdif2_sels,       ARRAY_SIZE(lcdif2_sels));
+        clks[IMX6SX_CLK_DISPLAY_SEL]        = imx_clk_mux("display_sel",      base + 0x3c,  14,     2,      display_sels,      ARRAY_SIZE(display_sels));
+        clks[IMX6SX_CLK_CSI_SEL]            = imx_clk_mux("csi_sel",          base + 0x3c,  9,      2,      csi_sels,          ARRAY_SIZE(csi_sels));
+        clks[IMX6SX_CLK_CKO1_SEL]           = imx_clk_mux("cko1_sel",         base + 0x60,  0,      4,      cko1_sels,         ARRAY_SIZE(cko1_sels));
+        clks[IMX6SX_CLK_CKO2_SEL]           = imx_clk_mux("cko2_sel",         base + 0x60,  16,     5,      cko2_sels,         ARRAY_SIZE(cko2_sels));
+        clks[IMX6SX_CLK_CKO]                = imx_clk_mux("cko",              base + 0x60,  8,      1,      cko_sels,          ARRAY_SIZE(cko_sels));
+        clks[IMX6SX_CLK_LDB_DI1_DIV_SEL]    = imx_clk_mux_flags("ldb_di1_div_sel", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_LDB_DI0_DIV_SEL]    = imx_clk_mux_flags("ldb_di0_div_sel", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_LDB_DI1_SEL]        = imx_clk_mux_flags("ldb_di1_sel",     base + 0x2c, 12, 3, ldb_di1_sels,      ARRAY_SIZE(ldb_di1_sels),    CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_LDB_DI0_SEL]        = imx_clk_mux_flags("ldb_di0_sel",     base + 0x2c, 9,  3, ldb_di0_sels,      ARRAY_SIZE(ldb_di0_sels),    CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_LCDIF1_PRE_SEL]     = imx_clk_mux_flags("lcdif1_pre_sel",  base + 0x38, 15, 3, lcdif1_pre_sels,   ARRAY_SIZE(lcdif1_pre_sels), CLK_SET_RATE_PARENT);
+        clks[IMX6SX_CLK_LCDIF1_SEL]         = imx_clk_mux_flags("lcdif1_sel",      base + 0x38, 9,  3, lcdif1_sels,       ARRAY_SIZE(lcdif1_sels),     CLK_SET_RATE_PARENT);
+        /*                                                    name              parent_name          reg          shift width */
+        clks[IMX6SX_CLK_PERIPH_CLK2]        = imx_clk_divider("periph_clk2",    "periph_clk2_sel",   base + 0x14, 27,   3);
+        clks[IMX6SX_CLK_PERIPH2_CLK2]       = imx_clk_divider("periph2_clk2",   "periph2_clk2_sel",  base + 0x14, 0,    3);
+        clks[IMX6SX_CLK_IPG]                = imx_clk_divider("ipg",            "ahb",               base + 0x14, 8,    2);
+        clks[IMX6SX_CLK_GPU_CORE_PODF]      = imx_clk_divider("gpu_core_podf",  "gpu_core_sel",      base + 0x18, 29,   3);
+        clks[IMX6SX_CLK_GPU_AXI_PODF]       = imx_clk_divider("gpu_axi_podf",   "gpu_axi_sel",       base + 0x18, 26,   3);
+        clks[IMX6SX_CLK_LCDIF1_PODF]        = imx_clk_divider("lcdif1_podf",    "lcdif1_pred",       base + 0x18, 23,   3);
+        clks[IMX6SX_CLK_QSPI1_PODF]         = imx_clk_divider("qspi1_podf",     "qspi1_sel",         base + 0x1c, 26,   3);
+        clks[IMX6SX_CLK_EIM_SLOW_PODF]      = imx_clk_divider("eim_slow_podf",  "eim_slow_sel",      base + 0x1c, 23,   3);
+        clks[IMX6SX_CLK_LCDIF2_PODF]        = imx_clk_divider("lcdif2_podf",    "lcdif2_pred",       base + 0x1c, 20,   3);
+        clks[IMX6SX_CLK_PERCLK]             = imx_clk_divider("perclk",         "perclk_sel",        base + 0x1c, 0,    6);
+        clks[IMX6SX_CLK_VID_PODF]           = imx_clk_divider("vid_podf",       "vid_sel",           base + 0x20, 24,   2);
+        clks[IMX6SX_CLK_CAN_PODF]           = imx_clk_divider("can_podf",       "can_sel",           base + 0x20, 2,    6);
+        clks[IMX6SX_CLK_USDHC4_PODF]        = imx_clk_divider("usdhc4_podf",    "usdhc4_sel",        base + 0x24, 22,   3);
+        clks[IMX6SX_CLK_USDHC3_PODF]        = imx_clk_divider("usdhc3_podf",    "usdhc3_sel",        base + 0x24, 19,   3);
+        clks[IMX6SX_CLK_USDHC2_PODF]        = imx_clk_divider("usdhc2_podf",    "usdhc2_sel",        base + 0x24, 16,   3);
+        clks[IMX6SX_CLK_USDHC1_PODF]        = imx_clk_divider("usdhc1_podf",    "usdhc1_sel",        base + 0x24, 11,   3);
+        clks[IMX6SX_CLK_UART_PODF]          = imx_clk_divider("uart_podf",      "uart_sel",          base + 0x24, 0,    6);
+        clks[IMX6SX_CLK_ESAI_PRED]          = imx_clk_divider("esai_pred",      "esai_sel",          base + 0x28, 9,    3);
+        clks[IMX6SX_CLK_ESAI_PODF]          = imx_clk_divider("esai_podf",      "esai_pred",         base + 0x28, 25,   3);
+        clks[IMX6SX_CLK_SSI3_PRED]          = imx_clk_divider("ssi3_pred",      "ssi3_sel",          base + 0x28, 22,   3);
+        clks[IMX6SX_CLK_SSI3_PODF]          = imx_clk_divider("ssi3_podf",      "ssi3_pred",         base + 0x28, 16,   6);
+        clks[IMX6SX_CLK_SSI1_PRED]          = imx_clk_divider("ssi1_pred",      "ssi1_sel",          base + 0x28, 6,    3);
+        clks[IMX6SX_CLK_SSI1_PODF]          = imx_clk_divider("ssi1_podf",      "ssi1_pred",         base + 0x28, 0,    6);
+        clks[IMX6SX_CLK_QSPI2_PRED]         = imx_clk_divider("qspi2_pred",     "qspi2_sel",         base + 0x2c, 18,   3);
+        clks[IMX6SX_CLK_QSPI2_PODF]         = imx_clk_divider("qspi2_podf",     "qspi2_pred",        base + 0x2c, 21,   6);
+        clks[IMX6SX_CLK_SSI2_PRED]          = imx_clk_divider("ssi2_pred",      "ssi2_sel",          base + 0x2c, 6,    3);
+        clks[IMX6SX_CLK_SSI2_PODF]          = imx_clk_divider("ssi2_podf",      "ssi2_pred",         base + 0x2c, 0,    6);
+        clks[IMX6SX_CLK_SPDIF_PRED]         = imx_clk_divider("spdif_pred",     "spdif_sel",         base + 0x30, 25,   3);
+        clks[IMX6SX_CLK_SPDIF_PODF]         = imx_clk_divider("spdif_podf",     "spdif_pred",        base + 0x30, 22,   3);
+        clks[IMX6SX_CLK_AUDIO_PRED]         = imx_clk_divider("audio_pred",     "audio_sel",         base + 0x30, 12,   3);
+        clks[IMX6SX_CLK_AUDIO_PODF]         = imx_clk_divider("audio_podf",     "audio_pred",        base + 0x30, 9,    3);
+        clks[IMX6SX_CLK_ENET_PODF]          = imx_clk_divider("enet_podf",      "enet_pre_sel",      base + 0x34, 12,   3);
+        clks[IMX6SX_CLK_M4_PODF]            = imx_clk_divider("m4_podf",        "m4_sel",            base + 0x34, 3,    3);
+        clks[IMX6SX_CLK_ECSPI_PODF]         = imx_clk_divider("ecspi_podf",     "ecspi_sel",         base + 0x38, 19,   6);
+        clks[IMX6SX_CLK_LCDIF1_PRED]        = imx_clk_divider("lcdif1_pred",    "lcdif1_pre_sel",    base + 0x38, 12,   3);
+        clks[IMX6SX_CLK_LCDIF2_PRED]        = imx_clk_divider("lcdif2_pred",    "lcdif2_pre_sel",    base + 0x38, 3,    3);
+        clks[IMX6SX_CLK_DISPLAY_PODF]       = imx_clk_divider("display_podf",   "display_sel",       base + 0x3c, 16,   3);
+        clks[IMX6SX_CLK_CSI_PODF]           = imx_clk_divider("csi_podf",       "csi_sel",           base + 0x3c, 11,   3);
+        clks[IMX6SX_CLK_CKO1_PODF]          = imx_clk_divider("cko1_podf",      "cko1_sel",          base + 0x60, 4,    3);
+        clks[IMX6SX_CLK_CKO2_PODF]          = imx_clk_divider("cko2_podf",      "cko2_sel",          base + 0x60, 21,   3);
+        clks[IMX6SX_CLK_LDB_DI0_DIV_3_5]    = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
+        clks[IMX6SX_CLK_LDB_DI0_DIV_7]      = imx_clk_fixed_factor("ldb_di0_div_7",   "ldb_di0_sel", 1, 7);
+        clks[IMX6SX_CLK_LDB_DI1_DIV_3_5]    = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
+        clks[IMX6SX_CLK_LDB_DI1_DIV_7]      = imx_clk_fixed_factor("ldb_di1_div_7",   "ldb_di1_sel", 1, 7);
+        /*                                               name        reg          shift width busy: reg,   shift parent_names       num_parents */
+        clks[IMX6SX_CLK_PERIPH]       = imx_clk_busy_mux("periph",   base + 0x14, 25,   1,    base + 0x48, 5,    periph_sels,       ARRAY_SIZE(periph_sels));
+        clks[IMX6SX_CLK_PERIPH2]      = imx_clk_busy_mux("periph2",  base + 0x14, 26,   1,    base + 0x48, 3,    periph2_sels,      ARRAY_SIZE(periph2_sels));
+        /*                                                   name             parent_name    reg          shift width busy: reg,   shift */
+        clks[IMX6SX_CLK_OCRAM_PODF]   = imx_clk_busy_divider("ocram_podf",    "ocram_sel",   base + 0x14, 16,   3,    base + 0x48, 0);
+        clks[IMX6SX_CLK_AHB]          = imx_clk_busy_divider("ahb",           "periph",      base + 0x14, 10,   3,    base + 0x48, 1);
+        clks[IMX6SX_CLK_MMDC_PODF]    = imx_clk_busy_divider("mmdc_podf",     "periph2",     base + 0x14, 3,    3,    base + 0x48, 2);
+        clks[IMX6SX_CLK_ARM]          = imx_clk_busy_divider("arm",           "pll1_sw",     base + 0x10, 0,    3,    base + 0x48, 16);
+        /*                                            name             parent_name          reg         shift */
+        /* CCGR0 */
+        clks[IMX6SX_CLK_AIPS_TZ1]     = imx_clk_gate2("aips_tz1",      "ahb",               base + 0x68, 0);
+        clks[IMX6SX_CLK_AIPS_TZ2]     = imx_clk_gate2("aips_tz2",      "ahb",               base + 0x68, 2);
+        clks[IMX6SX_CLK_APBH_DMA]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
+        clks[IMX6SX_CLK_ASRC_MEM]     = imx_clk_gate2_shared("asrc_mem", "ahb",             base + 0x68, 6, &share_count_asrc);
+        clks[IMX6SX_CLK_ASRC_IPG]     = imx_clk_gate2_shared("asrc_ipg", "ahb",             base + 0x68, 6, &share_count_asrc);
+        clks[IMX6SX_CLK_CAAM_MEM]     = imx_clk_gate2("caam_mem",      "ahb",               base + 0x68, 8);
+        clks[IMX6SX_CLK_CAAM_ACLK]    = imx_clk_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
+        clks[IMX6SX_CLK_CAAM_IPG]     = imx_clk_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
+        clks[IMX6SX_CLK_CAN1_IPG]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
+        clks[IMX6SX_CLK_CAN1_SERIAL]  = imx_clk_gate2("can1_serial",   "can_podf",          base + 0x68, 16);
+        clks[IMX6SX_CLK_CAN2_IPG]     = imx_clk_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
+        clks[IMX6SX_CLK_CAN2_SERIAL]  = imx_clk_gate2("can2_serial",   "can_podf",          base + 0x68, 20);
+        clks[IMX6SX_CLK_DCIC1]        = imx_clk_gate2("dcic1",         "display_podf",      base + 0x68, 24);
+        clks[IMX6SX_CLK_DCIC2]        = imx_clk_gate2("dcic2",         "display_podf",      base + 0x68, 26);
+        clks[IMX6SX_CLK_AIPS_TZ3]     = imx_clk_gate2("aips_tz3",      "ahb",               base + 0x68, 30);
+        /* CCGR1 */
+        clks[IMX6SX_CLK_ECSPI1]       = imx_clk_gate2("ecspi1",        "ecspi_podf",        base + 0x6c, 0);
+        clks[IMX6SX_CLK_ECSPI2]       = imx_clk_gate2("ecspi2",        "ecspi_podf",        base + 0x6c, 2);
+        clks[IMX6SX_CLK_ECSPI3]       = imx_clk_gate2("ecspi3",        "ecspi_podf",        base + 0x6c, 4);
+        clks[IMX6SX_CLK_ECSPI4]       = imx_clk_gate2("ecspi4",        "ecspi_podf",        base + 0x6c, 6);
+        clks[IMX6SX_CLK_ECSPI5]       = imx_clk_gate2("ecspi5",        "ecspi_podf",        base + 0x6c, 8);
+        clks[IMX6SX_CLK_EPIT1]        = imx_clk_gate2("epit1",         "perclk",            base + 0x6c, 12);
+        clks[IMX6SX_CLK_EPIT2]        = imx_clk_gate2("epit2",         "perclk",            base + 0x6c, 14);
+        clks[IMX6SX_CLK_ESAI_EXTAL]   = imx_clk_gate2_shared("esai_extal", "esai_podf",     base + 0x6c, 16, &share_count_esai);
+        clks[IMX6SX_CLK_ESAI_IPG]     = imx_clk_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);
+        clks[IMX6SX_CLK_ESAI_MEM]     = imx_clk_gate2_shared("esai_mem",   "ahb",           base + 0x6c, 16, &share_count_esai);
+        clks[IMX6SX_CLK_WAKEUP]       = imx_clk_gate2("wakeup",        "ipg",               base + 0x6c, 18);
+        clks[IMX6SX_CLK_GPT_BUS]      = imx_clk_gate2("gpt_bus",       "perclk",            base + 0x6c, 20);
+        clks[IMX6SX_CLK_GPT_SERIAL]   = imx_clk_gate2("gpt_serial",    "perclk",            base + 0x6c, 22);
+        clks[IMX6SX_CLK_GPU]          = imx_clk_gate2("gpu",           "gpu_core_podf",     base + 0x6c, 26);
+        clks[IMX6SX_CLK_CANFD]        = imx_clk_gate2("canfd",         "can_podf",          base + 0x6c, 30);
+        /* CCGR2 */
+        clks[IMX6SX_CLK_CSI]          = imx_clk_gate2("csi",           "csi_podf",          base + 0x70, 2);
+        clks[IMX6SX_CLK_I2C1]         = imx_clk_gate2("i2c1",          "perclk",            base + 0x70, 6);
+        clks[IMX6SX_CLK_I2C2]         = imx_clk_gate2("i2c2",          "perclk",            base + 0x70, 8);
+        clks[IMX6SX_CLK_I2C3]         = imx_clk_gate2("i2c3",          "perclk",            base + 0x70, 10);
+        clks[IMX6SX_CLK_OCOTP]        = imx_clk_gate2("ocotp",         "ipg",               base + 0x70, 12);
+        clks[IMX6SX_CLK_IOMUXC]       = imx_clk_gate2("iomuxc",        "lcdif1_podf",       base + 0x70, 14);
+        clks[IMX6SX_CLK_IPMUX1]       = imx_clk_gate2("ipmux1",        "ahb",               base + 0x70, 16);
+        clks[IMX6SX_CLK_IPMUX2]       = imx_clk_gate2("ipmux2",        "ahb",               base + 0x70, 18);
+        clks[IMX6SX_CLK_IPMUX3]       = imx_clk_gate2("ipmux3",        "ahb",               base + 0x70, 20);
+        clks[IMX6SX_CLK_TZASC1]       = imx_clk_gate2("tzasc1",        "mmdc_podf",         base + 0x70, 22);
+        clks[IMX6SX_CLK_LCDIF_APB]    = imx_clk_gate2("lcdif_apb",     "display_podf",      base + 0x70, 28);
+        clks[IMX6SX_CLK_PXP_AXI]      = imx_clk_gate2("pxp_axi",       "display_podf",      base + 0x70, 30);
+        /* CCGR3 */
+        clks[IMX6SX_CLK_M4]           = imx_clk_gate2("m4",            "m4_podf",           base + 0x74, 2);
+        clks[IMX6SX_CLK_ENET]         = imx_clk_gate2("enet",          "ipg",               base + 0x74, 4);
+        clks[IMX6SX_CLK_ENET_AHB]     = imx_clk_gate2("enet_ahb",      "enet_sel",          base + 0x74, 4);
+        clks[IMX6SX_CLK_DISPLAY_AXI]  = imx_clk_gate2("display_axi",   "display_podf",      base + 0x74, 6);
+        clks[IMX6SX_CLK_LCDIF2_PIX]   = imx_clk_gate2("lcdif2_pix",    "lcdif2_sel",        base + 0x74, 8);
+        clks[IMX6SX_CLK_LCDIF1_PIX]   = imx_clk_gate2("lcdif1_pix",    "lcdif1_sel",        base + 0x74, 10);
+        clks[IMX6SX_CLK_LDB_DI0]      = imx_clk_gate2("ldb_di0",       "ldb_di0_div_sel",   base + 0x74, 12);
+        clks[IMX6SX_CLK_QSPI1]        = imx_clk_gate2("qspi1",         "qspi1_podf",        base + 0x74, 14);
+        clks[IMX6SX_CLK_MLB]          = imx_clk_gate2("mlb",           "ahb",               base + 0x74, 18);
+        clks[IMX6SX_CLK_MMDC_P0_FAST] = imx_clk_gate2("mmdc_p0_fast",  "mmdc_podf",         base + 0x74, 20);
+        clks[IMX6SX_CLK_MMDC_P0_IPG]  = imx_clk_gate2("mmdc_p0_ipg",   "ipg",               base + 0x74, 24);
+        clks[IMX6SX_CLK_OCRAM]        = imx_clk_gate2("ocram",         "ocram_podf",        base + 0x74, 28);
+        /* CCGR4 */
+        clks[IMX6SX_CLK_PCIE_AXI]     = imx_clk_gate2("pcie_axi",      "display_podf",      base + 0x78, 0);
+        clks[IMX6SX_CLK_QSPI2]        = imx_clk_gate2("qspi2",         "qspi2_podf",        base + 0x78, 10);
+        clks[IMX6SX_CLK_PER1_BCH]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
+        clks[IMX6SX_CLK_PER2_MAIN]    = imx_clk_gate2("per2_main",     "ahb",               base + 0x78, 14);
+        clks[IMX6SX_CLK_PWM1]         = imx_clk_gate2("pwm1",          "perclk",            base + 0x78, 16);
+        clks[IMX6SX_CLK_PWM2]         = imx_clk_gate2("pwm2",          "perclk",            base + 0x78, 18);
+        clks[IMX6SX_CLK_PWM3]         = imx_clk_gate2("pwm3",          "perclk",            base + 0x78, 20);
+        clks[IMX6SX_CLK_PWM4]         = imx_clk_gate2("pwm4",          "perclk",            base + 0x78, 22);
+        clks[IMX6SX_CLK_GPMI_BCH_APB] = imx_clk_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
+        clks[IMX6SX_CLK_GPMI_BCH]     = imx_clk_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
+        clks[IMX6SX_CLK_GPMI_IO]      = imx_clk_gate2("gpmi_io",       "qspi2_podf",        base + 0x78, 28);
+        clks[IMX6SX_CLK_GPMI_APB]     = imx_clk_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
+        /* CCGR5 */
+        clks[IMX6SX_CLK_ROM]          = imx_clk_gate2("rom",           "ahb",               base + 0x7c, 0);
+        clks[IMX6SX_CLK_SDMA]         = imx_clk_gate2("sdma",          "ahb",               base + 0x7c, 6);
+        clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
+        clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
+        clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
+        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2("ssi1_ipg",      "ipg",               base + 0x7c, 18);
+        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2("ssi2_ipg",      "ipg",               base + 0x7c, 20);
+        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2("ssi3_ipg",      "ipg",               base + 0x7c, 22);
+        clks[IMX6SX_CLK_SSI1]         = imx_clk_gate2("ssi1",          "ssi1_podf",         base + 0x7c, 18);
+        clks[IMX6SX_CLK_SSI2]         = imx_clk_gate2("ssi2",          "ssi2_podf",         base + 0x7c, 20);
+        clks[IMX6SX_CLK_SSI3]         = imx_clk_gate2("ssi3",          "ssi3_podf",         base + 0x7c, 22);
+        clks[IMX6SX_CLK_UART_IPG]     = imx_clk_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
+        clks[IMX6SX_CLK_UART_SERIAL]  = imx_clk_gate2("uart_serial",   "uart_podf",         base + 0x7c, 26);
+        clks[IMX6SX_CLK_SAI1_IPG]     = imx_clk_gate2("sai1_ipg",      "ipg",               base + 0x7c, 28);
+        clks[IMX6SX_CLK_SAI2_IPG]     = imx_clk_gate2("sai2_ipg",      "ipg",               base + 0x7c, 30);
+        clks[IMX6SX_CLK_SAI1]         = imx_clk_gate2("sai1",          "ssi1_podf",         base + 0x7c, 28);
+        clks[IMX6SX_CLK_SAI2]         = imx_clk_gate2("sai2",          "ssi2_podf",         base + 0x7c, 30);
+        /* CCGR6 */
+        clks[IMX6SX_CLK_USBOH3]       = imx_clk_gate2("usboh3",        "ipg",               base + 0x80, 0);
+        clks[IMX6SX_CLK_USDHC1]       = imx_clk_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
+        clks[IMX6SX_CLK_USDHC2]       = imx_clk_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
+        clks[IMX6SX_CLK_USDHC3]       = imx_clk_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
+        clks[IMX6SX_CLK_USDHC4]       = imx_clk_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
+        clks[IMX6SX_CLK_EIM_SLOW]     = imx_clk_gate2("eim_slow",      "eim_slow_podf",     base + 0x80, 10);
+        clks[IMX6SX_CLK_PWM8]         = imx_clk_gate2("pwm8",          "perclk",            base + 0x80, 16);
+        clks[IMX6SX_CLK_VADC]         = imx_clk_gate2("vadc",          "vid_podf",          base + 0x80, 20);
+        clks[IMX6SX_CLK_GIS]          = imx_clk_gate2("gis",           "display_podf",      base + 0x80, 22);
+        clks[IMX6SX_CLK_I2C4]         = imx_clk_gate2("i2c4",          "perclk",            base + 0x80, 24);
+        clks[IMX6SX_CLK_PWM5]         = imx_clk_gate2("pwm5",          "perclk",            base + 0x80, 26);
+        clks[IMX6SX_CLK_PWM6]         = imx_clk_gate2("pwm6",          "perclk",            base + 0x80, 28);
+        clks[IMX6SX_CLK_PWM7]         = imx_clk_gate2("pwm7",          "perclk",            base + 0x80, 30);
+        clks[IMX6SX_CLK_CKO1]         = imx_clk_gate("cko1",           "cko1_podf",         base + 0x60, 7);
+        clks[IMX6SX_CLK_CKO2]         = imx_clk_gate("cko2",           "cko2_podf",         base + 0x60, 24);
+        /* mask handshake of mmdc */
+        writel_relaxed(BM_CCM_CCDR_MMDC_CH0_MASK, base + CCDR);
+        for (i = 0; i < ARRAY_SIZE(clks); i++)
+                if (IS_ERR(clks[i]))
+                        pr_err("i.MX6sx clk %d: register failed with %ld\n", i, PTR_ERR(clks[i]));
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+        clk_register_clkdev(clks[IMX6SX_CLK_GPT_BUS], "ipg", "imx-gpt.0");
+        clk_register_clkdev(clks[IMX6SX_CLK_GPT_SERIAL], "per", "imx-gpt.0");
+        for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+                clk_prepare_enable(clks[clks_init_on[i]]);
+        if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
+                clk_prepare_enable(clks[IMX6SX_CLK_USBPHY1_GATE]);
+                clk_prepare_enable(clks[IMX6SX_CLK_USBPHY2_GATE]);
+        }
+        /* Set the default 132MHz for EIM module */
+        clk_set_parent(clks[IMX6SX_CLK_EIM_SLOW_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+        clk_set_rate(clks[IMX6SX_CLK_EIM_SLOW], 132000000);
+        /* set parent clock for LCDIF1 pixel clock */
+        clk_set_parent(clks[IMX6SX_CLK_LCDIF1_PRE_SEL], clks[IMX6SX_CLK_PLL5_VIDEO_DIV]);
+        clk_set_parent(clks[IMX6SX_CLK_LCDIF1_SEL], clks[IMX6SX_CLK_LCDIF1_PODF]);
+        /* Set the parent clks of PCIe lvds1 and pcie_axi to be pcie ref, axi */
+        if (clk_set_parent(clks[IMX6SX_CLK_LVDS1_SEL], clks[IMX6SX_CLK_PCIE_REF_125M]))
+                pr_err("Failed to set pcie bus parent clk.\n");
+        if (clk_set_parent(clks[IMX6SX_CLK_PCIE_AXI_SEL], clks[IMX6SX_CLK_AXI]))
+                pr_err("Failed to set pcie parent clk.\n");
+        /*
+         * Init enet system AHB clock, set to 200Mhz
+         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
+         */
+        clk_set_parent(clks[IMX6SX_CLK_ENET_PRE_SEL], clks[IMX6SX_CLK_PLL2_PFD2]);
+        clk_set_parent(clks[IMX6SX_CLK_ENET_SEL], clks[IMX6SX_CLK_ENET_PODF]);
+        clk_set_rate(clks[IMX6SX_CLK_ENET_PODF], 200000000);
+        clk_set_rate(clks[IMX6SX_CLK_ENET_REF], 125000000);
+        clk_set_rate(clks[IMX6SX_CLK_ENET2_REF], 125000000);
+        /* Audio clocks */
+        clk_set_rate(clks[IMX6SX_CLK_PLL4_AUDIO_DIV], 393216000);
+        clk_set_parent(clks[IMX6SX_CLK_SPDIF_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_rate(clks[IMX6SX_CLK_SPDIF_PODF], 98304000);
+        clk_set_parent(clks[IMX6SX_CLK_AUDIO_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+        clk_set_rate(clks[IMX6SX_CLK_AUDIO_PODF], 24000000);
+        clk_set_parent(clks[IMX6SX_CLK_SSI1_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_parent(clks[IMX6SX_CLK_SSI2_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_parent(clks[IMX6SX_CLK_SSI3_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_rate(clks[IMX6SX_CLK_SSI1_PODF], 24576000);
+        clk_set_rate(clks[IMX6SX_CLK_SSI2_PODF], 24576000);
+        clk_set_rate(clks[IMX6SX_CLK_SSI3_PODF], 24576000);
+        clk_set_parent(clks[IMX6SX_CLK_ESAI_SEL], clks[IMX6SX_CLK_PLL4_AUDIO_DIV]);
+        clk_set_rate(clks[IMX6SX_CLK_ESAI_PODF], 24576000);
+        /* Set parent clock for vadc */
+        clk_set_parent(clks[IMX6SX_CLK_VID_SEL], clks[IMX6SX_CLK_PLL3_USB_OTG]);
+        /* default parent of can_sel clock is invalid, manually set it here */
+        clk_set_parent(clks[IMX6SX_CLK_CAN_SEL], clks[IMX6SX_CLK_PLL3_60M]);
+        /* Update gpu clock from default 528M to 720M */
+        clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+        clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
+        /* Set initial power mode */
+        imx6q_set_lpm(WAIT_CLOCKED);
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6sx-gpt");
+        mxc_timer_init_dt(np);
+}
+CLK_OF_DECLARE(imx6sx, "fsl,imx6sx-ccm", imx6sx_clocks_init);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 048c5ad8a80b..e29f6ebe9f39 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -28,7 +28,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
 struct clk *clk_register_gate2(struct device *dev, const char *name,
                const char *parent_name, unsigned long flags,
                void __iomem *reg, u8 bit_idx,
-                u8 clk_gate_flags, spinlock_t *lock);
+                u8 clk_gate_flags, spinlock_t *lock,
+                unsigned int *share_count);
 struct clk * imx_obtain_fixed_clock(
                        const char *name, unsigned long rate);
@@ -37,7 +38,15 @@ static inline struct clk *imx_clk_gate2(const char *name, const char *parent,
                void __iomem *reg, u8 shift)
 {
        return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
-                        shift, 0, &imx_ccm_lock);
+                        shift, 0, &imx_ccm_lock, NULL);
+}
+static inline struct clk *imx_clk_gate2_shared(const char *name,
+                const char *parent, void __iomem *reg, u8 shift,
+                unsigned int *share_count)
+{
+        return clk_register_gate2(NULL, name, parent, CLK_SET_RATE_PARENT, reg,
+                        shift, 0, &imx_ccm_lock, share_count);
 }
 struct clk *imx_clk_pfd(const char *name, const char *parent_name,
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b5241ea76706..9ab785ce13e8 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -17,6 +17,7 @@ struct irq_data;
 struct platform_device;
 struct pt_regs;
 struct clk;
+struct device_node;
 enum mxc_cpu_pwr_mode;
 void mx1_map_io(void);
@@ -56,6 +57,7 @@ void imx51_init_late(void);
 void imx53_init_late(void);
 void epit_timer_init(void __iomem *base, int irq);
 void mxc_timer_init(void __iomem *, int);
+void mxc_timer_init_dt(struct device_node *);
 int mx1_clocks_init(unsigned long fref);
 int mx21_clocks_init(unsigned long lref, unsigned long fref);
 int mx25_clocks_init(void);
@@ -99,19 +101,6 @@ enum mx3_cpu_pwr_mode {
 void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
 void imx_print_silicon_rev(const char *cpu, int srev);
-void avic_handle_irq(struct pt_regs *);
-void tzic_handle_irq(struct pt_regs *);
-#define imx1_handle_irq avic_handle_irq
-#define imx21_handle_irq avic_handle_irq
-#define imx25_handle_irq avic_handle_irq
-#define imx27_handle_irq avic_handle_irq
-#define imx31_handle_irq avic_handle_irq
-#define imx35_handle_irq avic_handle_irq
-#define imx50_handle_irq tzic_handle_irq
-#define imx51_handle_irq tzic_handle_irq
-#define imx53_handle_irq tzic_handle_irq
 void imx_enable_cpu(int cpu, bool enable);
 void imx_set_cpu_jump(int cpu, void *jump_addr);
 u32 imx_get_cpu_arg(int cpu);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index ba3b498a67ec..bbe8ff1f0412 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -111,6 +111,9 @@ struct device * __init imx_soc_device_init(void)
        case MXC_CPU_IMX6DL:
                soc_id = "i.MX6DL";
                break;
+        case MXC_CPU_IMX6SX:
+                soc_id = "i.MX6SX";
+                break;
        case MXC_CPU_IMX6Q:
                soc_id = "i.MX6Q";
                break;
diff --git a/arch/arm/mach-imx/devices/platform-ipu-core.c b/arch/arm/mach-imx/devices/platform-ipu-core.c
index fc4dd7cedc11..6bd7c3f37ac0 100644
--- a/arch/arm/mach-imx/devices/platform-ipu-core.c
+++ b/arch/arm/mach-imx/devices/platform-ipu-core.c
@@ -77,7 +77,7 @@ struct platform_device *__init imx_alloc_mx3_camera(
        pdev = platform_device_alloc("mx3-camera", 0);
        if (!pdev)
-                goto err;
+                return ERR_PTR(-ENOMEM);
        pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
        if (!pdev->dev.dma_mask)
diff --git a/arch/arm/mach-imx/devices/platform-mx2-emma.c b/arch/arm/mach-imx/devices/platform-mx2-emma.c
index 11bd01d402f2..0dc0651825b1 100644
--- a/arch/arm/mach-imx/devices/platform-mx2-emma.c
+++ b/arch/arm/mach-imx/devices/platform-mx2-emma.c
@@ -12,7 +12,7 @@
 #define imx_mx2_emmaprp_data_entry_single(soc)                          \
        {                                                               \
                .iobase = soc ## _EMMAPRP_BASE_ADDR,                    \
-                .iosize = SZ_32,                                        \
+                .iosize = SZ_256,                                       \
                .irq = soc ## _INT_EMMAPRP,                             \
        }
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
deleted file mode 100644
index 9be6c1e69d68..000000000000
--- a/arch/arm/mach-imx/eukrea_mbimxsd51-baseboard.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <video/platform_lcd.h>
-#include <linux/backlight.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include "common.h"
-#include "devices-imx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-static iomux_v3_cfg_t eukrea_mbimxsd51_pads[] = {
-        /* LED */
-        MX51_PAD_NANDF_D10__GPIO3_30,
-        /* SWITCH */
-        NEW_PAD_CTRL(MX51_PAD_NANDF_D9__GPIO3_31, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        /* UART 3 */
-        MX51_PAD_UART3_RXD__UART3_RXD,
-        MX51_PAD_UART3_TXD__UART3_TXD,
-        MX51_PAD_KEY_COL4__UART3_RTS,
-        MX51_PAD_KEY_COL5__UART3_CTS,
-        /* SD */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* SD1 CD */
-        NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        /* SSI */
-        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
-        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
-        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
-        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
-        /* LCD Backlight */
-        MX51_PAD_DI1_D1_CS__GPIO3_4,
-        /* LCD RST */
-        MX51_PAD_CSI1_D9__GPIO3_13,
-};
-#define GPIO_LED1       IMX_GPIO_NR(3, 30)
-#define GPIO_SWITCH1    IMX_GPIO_NR(3, 31)
-#define GPIO_LCDRST     IMX_GPIO_NR(3, 13)
-#define GPIO_LCDBL      IMX_GPIO_NR(3, 4)
-static void eukrea_mbimxsd51_lcd_power_set(struct plat_lcd_data *pd,
-                                   unsigned int power)
-{
-        if (power)
-                gpio_direction_output(GPIO_LCDRST, 1);
-        else
-                gpio_direction_output(GPIO_LCDRST, 0);
-}
-static struct plat_lcd_data eukrea_mbimxsd51_lcd_power_data = {
-        .set_power              = eukrea_mbimxsd51_lcd_power_set,
-};
-static struct platform_device eukrea_mbimxsd51_lcd_powerdev = {
-        .name                   = "platform-lcd",
-        .dev.platform_data      = &eukrea_mbimxsd51_lcd_power_data,
-};
-static void eukrea_mbimxsd51_bl_set_intensity(int intensity)
-{
-        if (intensity)
-                gpio_direction_output(GPIO_LCDBL, 1);
-        else
-                gpio_direction_output(GPIO_LCDBL, 0);
-}
-static struct generic_bl_info eukrea_mbimxsd51_bl_info = {
-        .name                   = "eukrea_mbimxsd51-bl",
-        .max_intensity          = 0xff,
-        .default_intensity      = 0xff,
-        .set_bl_intensity       = eukrea_mbimxsd51_bl_set_intensity,
-};
-static struct platform_device eukrea_mbimxsd51_bl_dev = {
-        .name                   = "generic-bl",
-        .id                     = 1,
-        .dev = {
-                .platform_data  = &eukrea_mbimxsd51_bl_info,
-        },
-};
-static const struct gpio_led eukrea_mbimxsd51_leds[] __initconst = {
-        {
-                .name                   = "led1",
-                .default_trigger        = "heartbeat",
-                .active_low             = 1,
-                .gpio                   = GPIO_LED1,
-        },
-};
-static const struct gpio_led_platform_data
-                eukrea_mbimxsd51_led_info __initconst = {
-        .leds           = eukrea_mbimxsd51_leds,
-        .num_leds       = ARRAY_SIZE(eukrea_mbimxsd51_leds),
-};
-static struct gpio_keys_button eukrea_mbimxsd51_gpio_buttons[] = {
-        {
-                .gpio           = GPIO_SWITCH1,
-                .code           = BTN_0,
-                .desc           = "BP1",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-static const struct gpio_keys_platform_data
-                eukrea_mbimxsd51_button_data __initconst = {
-        .buttons        = eukrea_mbimxsd51_gpio_buttons,
-        .nbuttons       = ARRAY_SIZE(eukrea_mbimxsd51_gpio_buttons),
-};
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static struct i2c_board_info eukrea_mbimxsd51_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("tlv320aic23", 0x1a),
-        },
-};
-static const
-struct imx_ssi_platform_data eukrea_mbimxsd51_ssi_pdata __initconst = {
-        .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-static int screen_type;
-static int __init eukrea_mbimxsd51_screen_type(char *options)
-{
-        if (!strcmp(options, "dvi"))
-                screen_type = 1;
-        else if (!strcmp(options, "tft"))
-                screen_type = 0;
-        return 0;
-}
-__setup("screen_type=", eukrea_mbimxsd51_screen_type);
-/*
- * system init for baseboard usage. Will be called by cpuimx51sd init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd51_baseboard_init(void)
-{
-        if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd51_pads,
-                        ARRAY_SIZE(eukrea_mbimxsd51_pads)))
-                printk(KERN_ERR "error setting mbimxsd pads !\n");
-        imx51_add_imx_uart(1, NULL);
-        imx51_add_imx_uart(2, &uart_pdata);
-        imx51_add_sdhci_esdhc_imx(0, NULL);
-        imx51_add_imx_ssi(0, &eukrea_mbimxsd51_ssi_pdata);
-        gpio_request(GPIO_LED1, "LED1");
-        gpio_direction_output(GPIO_LED1, 1);
-        gpio_free(GPIO_LED1);
-        gpio_request(GPIO_SWITCH1, "SWITCH1");
-        gpio_direction_input(GPIO_SWITCH1);
-        gpio_free(GPIO_SWITCH1);
-        gpio_request(GPIO_LCDRST, "LCDRST");
-        gpio_direction_output(GPIO_LCDRST, 0);
-        gpio_request(GPIO_LCDBL, "LCDBL");
-        gpio_direction_output(GPIO_LCDBL, 0);
-        if (!screen_type) {
-                platform_device_register(&eukrea_mbimxsd51_bl_dev);
-                platform_device_register(&eukrea_mbimxsd51_lcd_powerdev);
-        } else {
-                gpio_free(GPIO_LCDRST);
-                gpio_free(GPIO_LCDBL);
-        }
-        i2c_register_board_info(0, eukrea_mbimxsd51_i2c_devices,
-                                ARRAY_SIZE(eukrea_mbimxsd51_i2c_devices));
-        gpio_led_register_device(-1, &eukrea_mbimxsd51_led_info);
-        imx_add_gpio_keys(&eukrea_mbimxsd51_button_data);
-        imx_add_platform_device("eukrea_tlv320", 0, NULL, 0, NULL, 0);
-}
diff --git a/arch/arm/mach-imx/imx25-dt.c b/arch/arm/mach-imx/imx25-dt.c
index 3e1ec5ffe630..42a65e067443 100644
--- a/arch/arm/mach-imx/imx25-dt.c
+++ b/arch/arm/mach-imx/imx25-dt.c
@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX25_DT, "Freescale i.MX25 (Device Tree Support)")
        .map_io         = mx25_map_io,
        .init_early     = imx25_init_early,
        .init_irq       = mx25_init_irq,
-        .handle_irq     = imx25_handle_irq,
        .init_time      = imx25_timer_init,
        .init_machine   = imx25_dt_init,
        .dt_compat      = imx25_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 4e235ecb4021..17bd4058133d 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX27_DT, "Freescale i.MX27 (Device Tree Support)")
        .map_io         = mx27_map_io,
        .init_early     = imx27_init_early,
        .init_irq       = mx27_init_irq,
-        .handle_irq     = imx27_handle_irq,
        .init_time      = imx27_timer_init,
        .init_machine   = imx27_dt_init,
        .dt_compat      = imx27_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
index e1e70ef7bc2d..581f4d6c9b8a 100644
--- a/arch/arm/mach-imx/imx31-dt.c
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -39,7 +39,6 @@ DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
        .map_io         = mx31_map_io,
        .init_early     = imx31_init_early,
        .init_irq       = mx31_init_irq,
-        .handle_irq     = imx31_handle_irq,
        .init_time      = imx31_dt_timer_init,
        .init_machine   = imx31_dt_init,
        .dt_compat      = imx31_dt_board_compat,
diff --git a/arch/arm/mach-imx/imx35-dt.c b/arch/arm/mach-imx/imx35-dt.c
index 9d48e0065a63..a62854c59240 100644
--- a/arch/arm/mach-imx/imx35-dt.c
+++ b/arch/arm/mach-imx/imx35-dt.c
@@ -43,7 +43,6 @@ DT_MACHINE_START(IMX35_DT, "Freescale i.MX35 (Device Tree Support)")
        .map_io         = mx35_map_io,
        .init_early     = imx35_init_early,
        .init_irq       = imx35_irq_init,
-        .handle_irq     = imx35_handle_irq,
        .init_machine   = imx35_dt_init,
        .dt_compat      = imx35_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/imx51-dt.c b/arch/arm/mach-imx/imx51-dt.c
index 0230d78d1413..b8cd968faa52 100644
--- a/arch/arm/mach-imx/imx51-dt.c
+++ b/arch/arm/mach-imx/imx51-dt.c
@@ -38,7 +38,6 @@ DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
        .map_io         = mx51_map_io,
        .init_early     = imx51_init_early,
        .init_irq       = mx51_init_irq,
-        .handle_irq     = imx51_handle_irq,
        .init_machine   = imx51_dt_init,
        .init_late      = imx51_init_late,
        .dt_compat      = imx51_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 067580b2969b..ebbb5ab63529 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -142,7 +142,6 @@ MACHINE_START(APF9328, "Armadeus APF9328")
        .map_io       = mx1_map_io,
        .init_early   = imx1_init_early,
        .init_irq     = mx1_init_irq,
-        .handle_irq   = imx1_handle_irq,
        .init_time      = apf9328_timer_init,
        .init_machine = apf9328_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index 58b864a3fc20..39406b7e3228 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -562,7 +562,6 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = armadillo5x0_timer_init,
        .init_machine = armadillo5x0_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
index 2d00476f7d2c..c97d7cb39135 100644
--- a/arch/arm/mach-imx/mach-bug.c
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -57,7 +57,6 @@ MACHINE_START(BUG, "BugLabs BUGBase")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = bug_timer_init,
        .init_machine = bug_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index ea50870bda80..75b7b6aa2720 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -314,7 +314,6 @@ MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = eukrea_cpuimx27_timer_init,
        .init_machine = eukrea_cpuimx27_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 65e4c53e1554..1ffa27169045 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -199,7 +199,6 @@ MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
        .init_time      = eukrea_cpuimx35_timer_init,
        .init_machine = eukrea_cpuimx35_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
deleted file mode 100644
index 1fba2b8e983f..000000000000
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- *
- * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
- *
- * based on board-mx51_babbage.c which is
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/i2c-gpio.h>
-#include <linux/spi/spi.h>
-#include <linux/can/platform/mcp251x.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#include "devices-imx51.h"
-#include "eukrea-baseboards.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-#define USBH1_RST               IMX_GPIO_NR(2, 28)
-#define ETH_RST                 IMX_GPIO_NR(2, 31)
-#define TSC2007_IRQGPIO_REV2    IMX_GPIO_NR(3, 12)
-#define TSC2007_IRQGPIO_REV3    IMX_GPIO_NR(4, 0)
-#define CAN_IRQGPIO             IMX_GPIO_NR(1, 1)
-#define CAN_RST                 IMX_GPIO_NR(4, 15)
-#define CAN_NCS                 IMX_GPIO_NR(4, 24)
-#define CAN_RXOBF_REV2          IMX_GPIO_NR(1, 4)
-#define CAN_RXOBF_REV3          IMX_GPIO_NR(3, 12)
-#define CAN_RX1BF               IMX_GPIO_NR(1, 6)
-#define CAN_TXORTS              IMX_GPIO_NR(1, 7)
-#define CAN_TX1RTS              IMX_GPIO_NR(1, 8)
-#define CAN_TX2RTS              IMX_GPIO_NR(1, 9)
-#define I2C_SCL                 IMX_GPIO_NR(4, 16)
-#define I2C_SDA                 IMX_GPIO_NR(4, 17)
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET          0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
-#define MX51_USB_PLLDIV_12_MHZ          0x00
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define MX51_USB_PLL_DIV_24_MHZ         0x02
-static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-        MX51_PAD_USBH1_STP__USBH1_STP,
-        MX51_PAD_EIM_CS3__GPIO2_28,             /* PHY nRESET */
-        /* FEC */
-        MX51_PAD_EIM_DTACK__GPIO2_31,           /* PHY nRESET */
-        /* HSI2C */
-        MX51_PAD_I2C1_CLK__GPIO4_16,
-        MX51_PAD_I2C1_DAT__GPIO4_17,
-        /* I2C1 */
-        MX51_PAD_SD2_CMD__I2C1_SCL,
-        MX51_PAD_SD2_CLK__I2C1_SDA,
-        /* CAN */
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,           /* nCS */
-        MX51_PAD_CSI2_PIXCLK__GPIO4_15,         /* nReset */
-        MX51_PAD_GPIO1_1__GPIO1_1,              /* IRQ */
-        MX51_PAD_GPIO1_4__GPIO1_4,              /* Control signals */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        MX51_PAD_GPIO1_7__GPIO1_7,
-        MX51_PAD_GPIO1_8__GPIO1_8,
-        MX51_PAD_GPIO1_9__GPIO1_9,
-        /* Touchscreen */
-        /* IRQ */
-        NEW_PAD_CTRL(MX51_PAD_GPIO_NAND__GPIO_NAND, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-        NEW_PAD_CTRL(MX51_PAD_NANDF_D8__GPIO4_0, PAD_CTL_PUS_22K_UP |
-                        PAD_CTL_PKE | PAD_CTL_SRE_FAST |
-                        PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
-};
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static int tsc2007_get_pendown_state(struct device *dev)
-{
-        if (mx51_revision() < IMX_CHIP_REVISION_3_0)
-                return !gpio_get_value(TSC2007_IRQGPIO_REV2);
-        else
-                return !gpio_get_value(TSC2007_IRQGPIO_REV3);
-}
-static struct tsc2007_platform_data tsc2007_info = {
-        .model                  = 2007,
-        .x_plate_ohms           = 180,
-        .get_pendown_state      = tsc2007_get_pendown_state,
-};
-static struct i2c_board_info eukrea_cpuimx51sd_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("pcf8563", 0x51),
-        }, {
-                I2C_BOARD_INFO("tsc2007", 0x49),
-                .platform_data  = &tsc2007_info,
-        },
-};
-static const struct mxc_nand_platform_data
-                eukrea_cpuimx51sd_nand_board_info __initconst = {
-        .width          = 1,
-        .hw_ecc         = 1,
-        .flash_bbt      = 1,
-};
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* The clock for the USBH1 ULPI port will come from the PHY. */
-        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN,
-                        usbother_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_ITC_NO_THRESHOLD);
-}
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init           = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-        .init           = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-static bool otg_mode_host __initdata;
-static int __init eukrea_cpuimx51sd_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
-static struct i2c_gpio_platform_data pdata = {
-        .sda_pin                = I2C_SDA,
-        .sda_is_open_drain      = 0,
-        .scl_pin                = I2C_SCL,
-        .scl_is_open_drain      = 0,
-        .udelay                 = 2,
-};
-static struct platform_device hsi2c_gpio_device = {
-        .name                   = "i2c-gpio",
-        .id                     = 0,
-        .dev.platform_data      = &pdata,
-};
-static struct mcp251x_platform_data mcp251x_info = {
-        .oscillator_frequency = 24E6,
-};
-static struct spi_board_info cpuimx51sd_spi_device[] = {
-        {
-                .modalias        = "mcp2515",
-                .max_speed_hz    = 10000000,
-                .bus_num         = 0,
-                .mode           = SPI_MODE_0,
-                .chip_select     = 0,
-                .platform_data   = &mcp251x_info,
-                /* irq number is run-time assigned */
-        },
-};
-static int cpuimx51sd_spi1_cs[] = {
-        CAN_NCS,
-};
-static const struct spi_imx_master cpuimx51sd_ecspi1_pdata __initconst = {
-        .chipselect     = cpuimx51sd_spi1_cs,
-        .num_chipselect = ARRAY_SIZE(cpuimx51sd_spi1_cs),
-};
-static struct platform_device *rev2_platform_devices[] __initdata = {
-        &hsi2c_gpio_device,
-};
-static const struct imxi2c_platform_data cpuimx51sd_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static void __init eukrea_cpuimx51sd_init(void)
-{
-        imx51_soc_init();
-        mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
-                                        ARRAY_SIZE(eukrea_cpuimx51sd_pads));
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
-        imx51_add_imx2_wdt(0);
-        gpio_request(ETH_RST, "eth_rst");
-        gpio_set_value(ETH_RST, 1);
-        imx51_add_fec(NULL);
-        gpio_request(CAN_IRQGPIO, "can_irq");
-        gpio_direction_input(CAN_IRQGPIO);
-        gpio_free(CAN_IRQGPIO);
-        gpio_request(CAN_NCS, "can_ncs");
-        gpio_direction_output(CAN_NCS, 1);
-        gpio_free(CAN_NCS);
-        gpio_request(CAN_RST, "can_rst");
-        gpio_direction_output(CAN_RST, 0);
-        msleep(20);
-        gpio_set_value(CAN_RST, 1);
-        imx51_add_ecspi(0, &cpuimx51sd_ecspi1_pdata);
-        cpuimx51sd_spi_device[0].irq = gpio_to_irq(CAN_IRQGPIO);
-        spi_register_board_info(cpuimx51sd_spi_device,
-                                ARRAY_SIZE(cpuimx51sd_spi_device));
-        if (mx51_revision() < IMX_CHIP_REVISION_3_0) {
-                eukrea_cpuimx51sd_i2c_devices[1].irq =
-                        gpio_to_irq(TSC2007_IRQGPIO_REV2),
-                platform_add_devices(rev2_platform_devices,
-                        ARRAY_SIZE(rev2_platform_devices));
-                gpio_request(TSC2007_IRQGPIO_REV2, "tsc2007_irq");
-                gpio_direction_input(TSC2007_IRQGPIO_REV2);
-                gpio_free(TSC2007_IRQGPIO_REV2);
-        } else {
-                eukrea_cpuimx51sd_i2c_devices[1].irq =
-                        gpio_to_irq(TSC2007_IRQGPIO_REV3),
-                imx51_add_imx_i2c(0, &cpuimx51sd_i2c_data);
-                gpio_request(TSC2007_IRQGPIO_REV3, "tsc2007_irq");
-                gpio_direction_input(TSC2007_IRQGPIO_REV3);
-                gpio_free(TSC2007_IRQGPIO_REV3);
-        }
-        i2c_register_board_info(0, eukrea_cpuimx51sd_i2c_devices,
-                        ARRAY_SIZE(eukrea_cpuimx51sd_i2c_devices));
-        if (otg_mode_host)
-                imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        else {
-                initialize_otg_port(NULL);
-                imx51_add_fsl_usb2_udc(&usb_pdata);
-        }
-        gpio_request(USBH1_RST, "usb_rst");
-        gpio_direction_output(USBH1_RST, 0);
-        msleep(20);
-        gpio_set_value(USBH1_RST, 1);
-        imx51_add_mxc_ehci_hs(1, &usbh1_config);
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD
-        eukrea_mbimxsd51_baseboard_init();
-#endif
-}
-static void __init eukrea_cpuimx51sd_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
-        /* Maintainer: Eric Bénard <eric@eukrea.com> */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .init_time      = eukrea_cpuimx51sd_timer_init,
-        .init_machine = eukrea_cpuimx51sd_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 4bf454424249..e978dda1434c 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -165,7 +165,6 @@ MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
        .map_io = mx25_map_io,
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
-        .handle_irq = imx25_handle_irq,
        .init_time = eukrea_cpuimx25_timer_init,
        .init_machine = eukrea_cpuimx25_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 97f9c6297fcf..b61bd8ed5568 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -604,7 +604,6 @@ MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = visstrim_m10_timer_init,
        .init_machine = visstrim_m10_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 1a851aea6832..bb3ca0429680 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -71,7 +71,6 @@ MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = mx27ipcam_timer_init,
        .init_machine = mx27ipcam_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index 3da2e3e44ce9..9992089d3ad1 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -77,7 +77,6 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = mx27lite_timer_init,
        .init_machine = mx27lite_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx50.c b/arch/arm/mach-imx/mach-imx50.c
index 77b77a92bb5d..b899c0b59afd 100644
--- a/arch/arm/mach-imx/mach-imx50.c
+++ b/arch/arm/mach-imx/mach-imx50.c
@@ -31,7 +31,6 @@ static const char *imx50_dt_board_compat[] __initconst = {
 DT_MACHINE_START(IMX50_DT, "Freescale i.MX50 (Device Tree Support)")
        .map_io         = mx53_map_io,
        .init_irq       = mx53_init_irq,
-        .handle_irq     = imx50_handle_irq,
        .init_machine   = imx50_dt_init,
        .dt_compat      = imx50_dt_board_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-imx53.c b/arch/arm/mach-imx/mach-imx53.c
index 65850908a4b4..2bad387956c0 100644
--- a/arch/arm/mach-imx/mach-imx53.c
+++ b/arch/arm/mach-imx/mach-imx53.c
@@ -40,7 +40,6 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
        .map_io         = mx53_map_io,
        .init_early     = imx53_init_early,
        .init_irq       = mx53_init_irq,
-        .handle_irq     = imx53_handle_irq,
        .init_machine   = imx53_dt_init,
        .init_late      = imx53_init_late,
        .dt_compat      = imx53_dt_board_compat,
diff --git a/arch/arm/mach-imx/mach-imx6sx.c b/arch/arm/mach-imx/mach-imx6sx.c
new file mode 100644
index 000000000000..02fccf6033ac
--- /dev/null
+++ b/arch/arm/mach-imx/mach-imx6sx.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/irqchip.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include "common.h"
+static void __init imx6sx_init_machine(void)
+{
+        struct device *parent;
+        mxc_arch_reset_init_dt();
+        parent = imx_soc_device_init();
+        if (parent == NULL)
+                pr_warn("failed to initialize soc device\n");
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
+        imx_anatop_init();
+}
+static void __init imx6sx_init_irq(void)
+{
+        imx_init_revision_from_anatop();
+        imx_init_l2cache();
+        imx_src_init();
+        imx_gpc_init();
+        irqchip_init();
+}
+static const char *imx6sx_dt_compat[] __initconst = {
+        "fsl,imx6sx",
+        NULL,
+};
+DT_MACHINE_START(IMX6SX, "Freescale i.MX6 SoloX (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = imx6sx_init_irq,
+        .init_machine   = imx6sx_init_machine,
+        .dt_compat      = imx6sx_dt_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index c7bc41d6b468..31df4361996f 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -289,7 +289,6 @@ MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
        .map_io = kzm_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = kzm_timer_init,
        .init_machine = kzm_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 9f883e4d6fc9..77fda3de4290 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -138,7 +138,6 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
        .init_time      = mx1ads_timer_init,
        .init_machine = mx1ads_init,
        .restart        = mxc_restart,
@@ -149,7 +148,6 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
        .init_time      = mx1ads_timer_init,
        .init_machine = mx1ads_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index a06aa4dc37fc..703ce31d7379 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -17,51 +17,46 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/physmap.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/gpio.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include "common.h"
 #include "devices-imx21.h"
 #include "hardware.h"
 #include "iomux-mx21.h"
-/*
+#define MX21ADS_CS8900A_REG             (MX21_CS1_BASE_ADDR + 0x000000)
- * Memory-mapped I/O on MX21ADS base board
+#define MX21ADS_ST16C255_IOBASE_REG     (MX21_CS1_BASE_ADDR + 0x200000)
- */
+#define MX21ADS_VERSION_REG             (MX21_CS1_BASE_ADDR + 0x400000)
-#define MX21ADS_MMIO_BASE_ADDR   0xf5000000
+#define MX21ADS_IO_REG                  (MX21_CS1_BASE_ADDR + 0x800000)
-#define MX21ADS_MMIO_SIZE        0xc00000
-#define MX21ADS_REG_ADDR(offset)    (void __force __iomem *) \
-                (MX21ADS_MMIO_BASE_ADDR + (offset))
-#define MX21ADS_CS8900A_MMIO_SIZE   0x200000
+#define MX21ADS_MMC_CD                  IMX_GPIO_NR(4, 25)
-#define MX21ADS_CS8900A_IRQ_GPIO    IMX_GPIO_NR(5, 11)
+#define MX21ADS_CS8900A_IRQ_GPIO        IMX_GPIO_NR(5, 11)
-#define MX21ADS_ST16C255_IOBASE_REG MX21ADS_REG_ADDR(0x200000)
+#define MX21ADS_MMGPIO_BASE             (6 * 32)
-#define MX21ADS_VERSION_REG         MX21ADS_REG_ADDR(0x400000)
-#define MX21ADS_IO_REG              MX21ADS_REG_ADDR(0x800000)
 /* MX21ADS_IO_REG bit definitions */
-#define MX21ADS_IO_SD_WP        0x0001 /* read */
+#define MX21ADS_IO_SD_WP                (MX21ADS_MMGPIO_BASE + 0)
-#define MX21ADS_IO_TP6          0x0001 /* write */
+#define MX21ADS_IO_TP6                  (MX21ADS_IO_SD_WP)
-#define MX21ADS_IO_SW_SEL       0x0002 /* read */
+#define MX21ADS_IO_SW_SEL               (MX21ADS_MMGPIO_BASE + 1)
-#define MX21ADS_IO_TP7          0x0002 /* write */
+#define MX21ADS_IO_TP7                  (MX21ADS_IO_SW_SEL)
-#define MX21ADS_IO_RESET_E_UART 0x0004
+#define MX21ADS_IO_RESET_E_UART         (MX21ADS_MMGPIO_BASE + 2)
-#define MX21ADS_IO_RESET_BASE   0x0008
+#define MX21ADS_IO_RESET_BASE           (MX21ADS_MMGPIO_BASE + 3)
-#define MX21ADS_IO_CSI_CTL2     0x0010
+#define MX21ADS_IO_CSI_CTL2             (MX21ADS_MMGPIO_BASE + 4)
-#define MX21ADS_IO_CSI_CTL1     0x0020
+#define MX21ADS_IO_CSI_CTL1             (MX21ADS_MMGPIO_BASE + 5)
-#define MX21ADS_IO_CSI_CTL0     0x0040
+#define MX21ADS_IO_CSI_CTL0             (MX21ADS_MMGPIO_BASE + 6)
-#define MX21ADS_IO_UART1_EN     0x0080
+#define MX21ADS_IO_UART1_EN             (MX21ADS_MMGPIO_BASE + 7)
-#define MX21ADS_IO_UART4_EN     0x0100
+#define MX21ADS_IO_UART4_EN             (MX21ADS_MMGPIO_BASE + 8)
-#define MX21ADS_IO_LCDON        0x0200
+#define MX21ADS_IO_LCDON                (MX21ADS_MMGPIO_BASE + 9)
-#define MX21ADS_IO_IRDA_EN      0x0400
+#define MX21ADS_IO_IRDA_EN              (MX21ADS_MMGPIO_BASE + 10)
-#define MX21ADS_IO_IRDA_FIR_SEL 0x0800
+#define MX21ADS_IO_IRDA_FIR_SEL         (MX21ADS_MMGPIO_BASE + 11)
-#define MX21ADS_IO_IRDA_MD0_B   0x1000
+#define MX21ADS_IO_IRDA_MD0_B           (MX21ADS_MMGPIO_BASE + 12)
-#define MX21ADS_IO_IRDA_MD1     0x2000
+#define MX21ADS_IO_IRDA_MD1             (MX21ADS_MMGPIO_BASE + 13)
-#define MX21ADS_IO_LED4_ON      0x4000
+#define MX21ADS_IO_LED4_ON              (MX21ADS_MMGPIO_BASE + 14)
-#define MX21ADS_IO_LED3_ON      0x8000
+#define MX21ADS_IO_LED3_ON              (MX21ADS_MMGPIO_BASE + 15)
 static const int mx21ads_pins[] __initconst = {
@@ -143,11 +138,8 @@ static struct physmap_flash_data mx21ads_flash_data = {
        .width = 4,
 };
-static struct resource mx21ads_flash_resource = {
+static struct resource mx21ads_flash_resource =
-        .start = MX21_CS0_BASE_ADDR,
+        DEFINE_RES_MEM(MX21_CS0_BASE_ADDR, SZ_32M);
-        .end = MX21_CS0_BASE_ADDR + 0x02000000 - 1,
-        .flags = IORESOURCE_MEM,
-};
 static struct platform_device mx21ads_nor_mtd_device = {
        .name = "physmap-flash",
@@ -160,7 +152,7 @@ static struct platform_device mx21ads_nor_mtd_device = {
 };
 static struct resource mx21ads_cs8900_resources[] __initdata = {
-        DEFINE_RES_MEM(MX21_CS1_BASE_ADDR, MX21ADS_CS8900A_MMIO_SIZE),
+        DEFINE_RES_MEM(MX21ADS_CS8900A_REG, SZ_1K),
        /* irq number is run-time assigned */
        DEFINE_RES_IRQ(-1),
 };
@@ -179,24 +171,50 @@ static const struct imxuart_platform_data uart_pdata_rts __initconst = {
 static const struct imxuart_platform_data uart_pdata_norts __initconst = {
 };
-static int mx21ads_fb_init(struct platform_device *pdev)
+static struct resource mx21ads_mmgpio_resource =
-{
+        DEFINE_RES_MEM_NAMED(MX21ADS_IO_REG, SZ_2, "dat");
-        u16 tmp;
-        tmp = __raw_readw(MX21ADS_IO_REG);
+static struct bgpio_pdata mx21ads_mmgpio_pdata = {
-        tmp |= MX21ADS_IO_LCDON;
+        .base   = MX21ADS_MMGPIO_BASE,
-        __raw_writew(tmp, MX21ADS_IO_REG);
+        .ngpio  = 16,
-        return 0;
+};
-}
-static void mx21ads_fb_exit(struct platform_device *pdev)
+static struct platform_device mx21ads_mmgpio = {
-{
+        .name = "basic-mmio-gpio",
-        u16 tmp;
+        .id = PLATFORM_DEVID_AUTO,
+        .resource = &mx21ads_mmgpio_resource,
+        .num_resources = 1,
+        .dev = {
+                .platform_data = &mx21ads_mmgpio_pdata,
+        },
+};
-        tmp = __raw_readw(MX21ADS_IO_REG);
+static struct regulator_consumer_supply mx21ads_lcd_regulator_consumer =
-        tmp &= ~MX21ADS_IO_LCDON;
+        REGULATOR_SUPPLY("lcd", "imx-fb.0");
-        __raw_writew(tmp, MX21ADS_IO_REG);
-}
+static struct regulator_init_data mx21ads_lcd_regulator_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .consumer_supplies      = &mx21ads_lcd_regulator_consumer,
+        .num_consumer_supplies  = 1,
+};
+static struct fixed_voltage_config mx21ads_lcd_regulator_pdata = {
+        .supply_name    = "LCD",
+        .microvolts     = 3300000,
+        .gpio           = MX21ADS_IO_LCDON,
+        .enable_high    = 1,
+        .init_data      = &mx21ads_lcd_regulator_init_data,
+};
+static struct platform_device mx21ads_lcd_regulator = {
+        .name = "reg-fixed-voltage",
+        .id = PLATFORM_DEVID_AUTO,
+        .dev = {
+                .platform_data = &mx21ads_lcd_regulator_pdata,
+        },
+};
 /*
 * Connected is a portrait Sharp-QVGA display
@@ -229,26 +247,30 @@ static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
        .pwmr           = 0x00a903ff,
        .lscr1          = 0x00120300,
        .dmacr          = 0x00020008,
-        .init = mx21ads_fb_init,
-        .exit = mx21ads_fb_exit,
 };
 static int mx21ads_sdhc_get_ro(struct device *dev)
 {
-        return (__raw_readw(MX21ADS_IO_REG) & MX21ADS_IO_SD_WP) ? 1 : 0;
+        return gpio_get_value(MX21ADS_IO_SD_WP);
 }
 static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
        void *data)
 {
-        return request_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), detect_irq,
+        int ret;
-                IRQF_TRIGGER_FALLING, "mmc-detect", data);
+        ret = gpio_request(MX21ADS_IO_SD_WP, "mmc-ro");
+        if (ret)
+                return ret;
+        return request_irq(gpio_to_irq(MX21ADS_MMC_CD), detect_irq,
+                           IRQF_TRIGGER_FALLING, "mmc-detect", data);
 }
 static void mx21ads_sdhc_exit(struct device *dev, void *data)
 {
-        free_irq(gpio_to_irq(IMX_GPIO_NR(4, 25)), data);
+        free_irq(gpio_to_irq(MX21ADS_MMC_CD), data);
+        gpio_free(MX21ADS_IO_SD_WP);
 }
 static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
@@ -264,29 +286,9 @@ mx21ads_nand_board_info __initconst = {
        .hw_ecc = 1,
 };
-static struct map_desc mx21ads_io_desc[] __initdata = {
-        /*
-         * Memory-mapped I/O on MX21ADS Base board:
-         *   - CS8900A Ethernet controller
-         *   - ST16C2552CJ UART
-         *   - CPU and Base board version
-         *   - Base board I/O register
-         */
-        {
-                .virtual = MX21ADS_MMIO_BASE_ADDR,
-                .pfn = __phys_to_pfn(MX21_CS1_BASE_ADDR),
-                .length = MX21ADS_MMIO_SIZE,
-                .type = MT_DEVICE,
-        },
-};
-static void __init mx21ads_map_io(void)
-{
-        mx21_map_io();
-        iotable_init(mx21ads_io_desc, ARRAY_SIZE(mx21ads_io_desc));
-}
 static struct platform_device *platform_devices[] __initdata = {
+        &mx21ads_mmgpio,
+        &mx21ads_lcd_regulator,
        &mx21ads_nor_mtd_device,
 };
@@ -300,12 +302,13 @@ static void __init mx21ads_board_init(void)
        imx21_add_imx_uart0(&uart_pdata_rts);
        imx21_add_imx_uart2(&uart_pdata_norts);
        imx21_add_imx_uart3(&uart_pdata_rts);
-        imx21_add_imx_fb(&mx21ads_fb_data);
        imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
        imx21_add_mxc_nand(&mx21ads_nand_board_info);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+        imx21_add_imx_fb(&mx21ads_fb_data);
        mx21ads_cs8900_resources[1].start =
                        gpio_to_irq(MX21ADS_CS8900A_IRQ_GPIO);
        mx21ads_cs8900_resources[1].end =
@@ -321,10 +324,9 @@ static void __init mx21ads_timer_init(void)
 MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        /* maintainer: Freescale Semiconductor, Inc. */
        .atag_offset = 0x100,
-        .map_io = mx21ads_map_io,
+        .map_io         = mx21_map_io,
        .init_early = imx21_init_early,
        .init_irq = mx21_init_irq,
-        .handle_irq = imx21_handle_irq,
        .init_time      = mx21ads_timer_init,
        .init_machine = mx21ads_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 13490c203050..ea1fa199c148 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -263,7 +263,6 @@ MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
        .map_io = mx25_map_io,
        .init_early = imx25_init_early,
        .init_irq = mx25_init_irq,
-        .handle_irq = imx25_handle_irq,
        .init_time      = mx25pdk_timer_init,
        .init_machine = mx25pdk_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 25b3e4c9bc0a..435a5428a678 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -544,7 +544,6 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = mx27pdk_timer_init,
        .init_machine = mx27pdk_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index a7a4a9c67615..2f834ce8f39c 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -391,7 +391,6 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .map_io = mx27ads_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = mx27ads_timer_init,
        .init_machine = mx27ads_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 50044a21b388..4217871a9653 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -775,7 +775,6 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = mx31_3ds_timer_init,
        .init_machine = mx31_3ds_init,
        .reserve = mx31_3ds_reserve,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index daf8889125cc..d08c37c696f6 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -582,7 +582,6 @@ MACHINE_START(MX31ADS, "Freescale MX31ADS")
        .map_io = mx31ads_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31ads_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = mx31ads_timer_init,
        .init_machine = mx31ads_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 832b1e2f964e..eee042fa2768 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -308,7 +308,6 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = mx31lilly_timer_init,
        .init_machine = mx31lilly_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index bea07299b61a..fa15d0b6118d 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -291,7 +291,6 @@ MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
        .map_io = mx31lite_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = mx31lite_timer_init,
        .init_machine = mx31lite_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 8f45afe785f8..08730f238449 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -600,7 +600,6 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = mx31moboard_timer_init,
        .init_machine = mx31moboard_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index a42f4f07051f..4e8b184d773b 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -615,7 +615,6 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
        .init_time      = mx35pdk_timer_init,
        .init_machine = mx35_3ds_init,
        .reserve = mx35_3ds_reserve,
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
deleted file mode 100644
index f3d264a636fa..000000000000
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/spi/flash.h>
-#include <linux/spi/spi.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include "common.h"
-#include "devices-imx51.h"
-#include "hardware.h"
-#include "iomux-mx51.h"
-#define BABBAGE_USB_HUB_RESET   IMX_GPIO_NR(1, 7)
-#define BABBAGE_USBH1_STP       IMX_GPIO_NR(1, 27)
-#define BABBAGE_USB_PHY_RESET   IMX_GPIO_NR(2, 5)
-#define BABBAGE_FEC_PHY_RESET   IMX_GPIO_NR(2, 14)
-#define BABBAGE_POWER_KEY       IMX_GPIO_NR(2, 21)
-#define BABBAGE_ECSPI1_CS0      IMX_GPIO_NR(4, 24)
-#define BABBAGE_ECSPI1_CS1      IMX_GPIO_NR(4, 25)
-#define BABBAGE_SD2_CD          IMX_GPIO_NR(1, 6)
-#define BABBAGE_SD2_WP          IMX_GPIO_NR(1, 5)
-/* USB_CTRL_1 */
-#define MX51_USB_CTRL_1_OFFSET                  0x10
-#define MX51_USB_CTRL_UH1_EXT_CLK_EN            (1 << 25)
-#define MX51_USB_PLLDIV_12_MHZ          0x00
-#define MX51_USB_PLL_DIV_19_2_MHZ       0x01
-#define MX51_USB_PLL_DIV_24_MHZ 0x02
-static struct gpio_keys_button babbage_buttons[] = {
-        {
-                .gpio           = BABBAGE_POWER_KEY,
-                .code           = BTN_0,
-                .desc           = "PWR",
-                .active_low     = 1,
-                .wakeup         = 1,
-        },
-};
-static const struct gpio_keys_platform_data imx_button_data __initconst = {
-        .buttons        = babbage_buttons,
-        .nbuttons       = ARRAY_SIZE(babbage_buttons),
-};
-static iomux_v3_cfg_t mx51babbage_pads[] = {
-        /* UART1 */
-        MX51_PAD_UART1_RXD__UART1_RXD,
-        MX51_PAD_UART1_TXD__UART1_TXD,
-        MX51_PAD_UART1_RTS__UART1_RTS,
-        MX51_PAD_UART1_CTS__UART1_CTS,
-        /* UART2 */
-        MX51_PAD_UART2_RXD__UART2_RXD,
-        MX51_PAD_UART2_TXD__UART2_TXD,
-        /* UART3 */
-        MX51_PAD_EIM_D25__UART3_RXD,
-        MX51_PAD_EIM_D26__UART3_TXD,
-        MX51_PAD_EIM_D27__UART3_RTS,
-        MX51_PAD_EIM_D24__UART3_CTS,
-        /* I2C1 */
-        MX51_PAD_EIM_D16__I2C1_SDA,
-        MX51_PAD_EIM_D19__I2C1_SCL,
-        /* I2C2 */
-        MX51_PAD_KEY_COL4__I2C2_SCL,
-        MX51_PAD_KEY_COL5__I2C2_SDA,
-        /* HSI2C */
-        MX51_PAD_I2C1_CLK__I2C1_CLK,
-        MX51_PAD_I2C1_DAT__I2C1_DAT,
-        /* USB HOST1 */
-        MX51_PAD_USBH1_CLK__USBH1_CLK,
-        MX51_PAD_USBH1_DIR__USBH1_DIR,
-        MX51_PAD_USBH1_NXT__USBH1_NXT,
-        MX51_PAD_USBH1_DATA0__USBH1_DATA0,
-        MX51_PAD_USBH1_DATA1__USBH1_DATA1,
-        MX51_PAD_USBH1_DATA2__USBH1_DATA2,
-        MX51_PAD_USBH1_DATA3__USBH1_DATA3,
-        MX51_PAD_USBH1_DATA4__USBH1_DATA4,
-        MX51_PAD_USBH1_DATA5__USBH1_DATA5,
-        MX51_PAD_USBH1_DATA6__USBH1_DATA6,
-        MX51_PAD_USBH1_DATA7__USBH1_DATA7,
-        /* USB HUB reset line*/
-        MX51_PAD_GPIO1_7__GPIO1_7,
-        /* USB PHY reset line */
-        MX51_PAD_EIM_D21__GPIO2_5,
-        /* FEC */
-        MX51_PAD_EIM_EB2__FEC_MDIO,
-        MX51_PAD_EIM_EB3__FEC_RDATA1,
-        MX51_PAD_EIM_CS2__FEC_RDATA2,
-        MX51_PAD_EIM_CS3__FEC_RDATA3,
-        MX51_PAD_EIM_CS4__FEC_RX_ER,
-        MX51_PAD_EIM_CS5__FEC_CRS,
-        MX51_PAD_NANDF_RB2__FEC_COL,
-        MX51_PAD_NANDF_RB3__FEC_RX_CLK,
-        MX51_PAD_NANDF_D9__FEC_RDATA0,
-        MX51_PAD_NANDF_D8__FEC_TDATA0,
-        MX51_PAD_NANDF_CS2__FEC_TX_ER,
-        MX51_PAD_NANDF_CS3__FEC_MDC,
-        MX51_PAD_NANDF_CS4__FEC_TDATA1,
-        MX51_PAD_NANDF_CS5__FEC_TDATA2,
-        MX51_PAD_NANDF_CS6__FEC_TDATA3,
-        MX51_PAD_NANDF_CS7__FEC_TX_EN,
-        MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
-        /* FEC PHY reset line */
-        MX51_PAD_EIM_A20__GPIO2_14,
-        /* SD 1 */
-        MX51_PAD_SD1_CMD__SD1_CMD,
-        MX51_PAD_SD1_CLK__SD1_CLK,
-        MX51_PAD_SD1_DATA0__SD1_DATA0,
-        MX51_PAD_SD1_DATA1__SD1_DATA1,
-        MX51_PAD_SD1_DATA2__SD1_DATA2,
-        MX51_PAD_SD1_DATA3__SD1_DATA3,
-        /* CD/WP from controller */
-        MX51_PAD_GPIO1_0__SD1_CD,
-        MX51_PAD_GPIO1_1__SD1_WP,
-        /* SD 2 */
-        MX51_PAD_SD2_CMD__SD2_CMD,
-        MX51_PAD_SD2_CLK__SD2_CLK,
-        MX51_PAD_SD2_DATA0__SD2_DATA0,
-        MX51_PAD_SD2_DATA1__SD2_DATA1,
-        MX51_PAD_SD2_DATA2__SD2_DATA2,
-        MX51_PAD_SD2_DATA3__SD2_DATA3,
-        /* CD/WP gpio */
-        MX51_PAD_GPIO1_6__GPIO1_6,
-        MX51_PAD_GPIO1_5__GPIO1_5,
-        /* eCSPI1 */
-        MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
-        MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
-        MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
-        MX51_PAD_CSPI1_SS0__GPIO4_24,
-        MX51_PAD_CSPI1_SS1__GPIO4_25,
-        /* Audio */
-        MX51_PAD_AUD3_BB_TXD__AUD3_TXD,
-        MX51_PAD_AUD3_BB_RXD__AUD3_RXD,
-        MX51_PAD_AUD3_BB_CK__AUD3_TXC,
-        MX51_PAD_AUD3_BB_FS__AUD3_TXFS,
-};
-/* Serial ports */
-static const struct imxuart_platform_data uart_pdata __initconst = {
-        .flags = IMXUART_HAVE_RTSCTS,
-};
-static const struct imxi2c_platform_data babbage_i2c_data __initconst = {
-        .bitrate = 100000,
-};
-static const struct imxi2c_platform_data babbage_hsi2c_data __initconst = {
-        .bitrate = 400000,
-};
-static struct gpio mx51_babbage_usbh1_gpios[] = {
-        { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
-        { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
-};
-static int gpio_usbh1_active(void)
-{
-        iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
-        int ret;
-        /* Set USBH1_STP to GPIO and toggle it */
-        mxc_iomux_v3_setup_pad(usbh1stp_gpio);
-        ret = gpio_request_array(mx51_babbage_usbh1_gpios,
-                                        ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-        if (ret) {
-                pr_debug("failed to get USBH1 pins: %d\n", ret);
-                return ret;
-        }
-        msleep(100);
-        gpio_set_value(BABBAGE_USBH1_STP, 1);
-        gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
-        gpio_free_array(mx51_babbage_usbh1_gpios,
-                                        ARRAY_SIZE(mx51_babbage_usbh1_gpios));
-        return 0;
-}
-static inline void babbage_usbhub_reset(void)
-{
-        int ret;
-        /* Reset USB hub */
-        ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
-                                        GPIOF_OUT_INIT_LOW, "GPIO1_7");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
-                return;
-        }
-        msleep(2);
-        /* Deassert reset */
-        gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
-}
-static inline void babbage_fec_reset(void)
-{
-        int ret;
-        /* reset FEC PHY */
-        ret = gpio_request_one(BABBAGE_FEC_PHY_RESET,
-                                        GPIOF_OUT_INIT_LOW, "fec-phy-reset");
-        if (ret) {
-                printk(KERN_ERR"failed to get GPIO_FEC_PHY_RESET: %d\n", ret);
-                return;
-        }
-        msleep(1);
-        gpio_set_value(BABBAGE_FEC_PHY_RESET, 1);
-}
-/* This function is board specific as the bit mask for the plldiv will also
-be different for other Freescale SoCs, thus a common bitmask is not
-possible and cannot get place in /plat-mxc/ehci.c.*/
-static int initialize_otg_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* Set the PHY clock to 19.2MHz */
-        v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
-        v |= MX51_USB_PLL_DIV_19_2_MHZ;
-        __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
-}
-static int initialize_usbh1_port(struct platform_device *pdev)
-{
-        u32 v;
-        void __iomem *usb_base;
-        void __iomem *usbother_base;
-        usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K);
-        if (!usb_base)
-                return -ENOMEM;
-        usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
-        /* The clock for the USBH1 ULPI port will come externally from the PHY. */
-        v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
-        __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
-        iounmap(usb_base);
-        mdelay(10);
-        return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
-                        MXC_EHCI_ITC_NO_THRESHOLD);
-}
-static const struct mxc_usbh_platform_data dr_utmi_config __initconst = {
-        .init           = initialize_otg_port,
-        .portsc = MXC_EHCI_UTMI_16BIT,
-};
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
-};
-static const struct mxc_usbh_platform_data usbh1_config __initconst = {
-        .init           = initialize_usbh1_port,
-        .portsc = MXC_EHCI_MODE_ULPI,
-};
-static bool otg_mode_host __initdata;
-static int __init babbage_otg_mode(char *options)
-{
-        if (!strcmp(options, "host"))
-                otg_mode_host = true;
-        else if (!strcmp(options, "device"))
-                otg_mode_host = false;
-        else
-                pr_info("otg_mode neither \"host\" nor \"device\". "
-                        "Defaulting to device\n");
-        return 1;
-}
-__setup("otg_mode=", babbage_otg_mode);
-static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
-        {
-                .modalias = "mtd_dataflash",
-                .max_speed_hz = 25000000,
-                .bus_num = 0,
-                .chip_select = 1,
-                .mode = SPI_MODE_0,
-                .platform_data = NULL,
-        },
-};
-static int mx51_babbage_spi_cs[] = {
-        BABBAGE_ECSPI1_CS0,
-        BABBAGE_ECSPI1_CS1,
-};
-static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
-        .chipselect     = mx51_babbage_spi_cs,
-        .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
-};
-static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
-        .cd_type = ESDHC_CD_CONTROLLER,
-        .wp_type = ESDHC_WP_CONTROLLER,
-};
-static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
-        .cd_gpio = BABBAGE_SD2_CD,
-        .wp_gpio = BABBAGE_SD2_WP,
-        .cd_type = ESDHC_CD_GPIO,
-        .wp_type = ESDHC_WP_GPIO,
-};
-void __init imx51_babbage_common_init(void)
-{
-        mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
-                                         ARRAY_SIZE(mx51babbage_pads));
-}
-/*
- * Board specific initialization.
- */
-static void __init mx51_babbage_init(void)
-{
-        iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
-        iomux_v3_cfg_t power_key = NEW_PAD_CTRL(MX51_PAD_EIM_A27__GPIO2_21,
-                PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH);
-        imx51_soc_init();
-        imx51_babbage_common_init();
-        imx51_add_imx_uart(0, &uart_pdata);
-        imx51_add_imx_uart(1, NULL);
-        imx51_add_imx_uart(2, &uart_pdata);
-        babbage_fec_reset();
-        imx51_add_fec(NULL);
-        /* Set the PAD settings for the pwr key. */
-        mxc_iomux_v3_setup_pad(power_key);
-        imx_add_gpio_keys(&imx_button_data);
-        imx51_add_imx_i2c(0, &babbage_i2c_data);
-        imx51_add_imx_i2c(1, &babbage_i2c_data);
-        imx51_add_hsi2c(&babbage_hsi2c_data);
-        if (otg_mode_host)
-                imx51_add_mxc_ehci_otg(&dr_utmi_config);
-        else {
-                initialize_otg_port(NULL);
-                imx51_add_fsl_usb2_udc(&usb_pdata);
-        }
-        gpio_usbh1_active();
-        imx51_add_mxc_ehci_hs(1, &usbh1_config);
-        /* setback USBH1_STP to be function */
-        mxc_iomux_v3_setup_pad(usbh1stp);
-        babbage_usbhub_reset();
-        imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
-        imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
-        spi_register_board_info(mx51_babbage_spi_board_info,
-                ARRAY_SIZE(mx51_babbage_spi_board_info));
-        imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
-        imx51_add_imx2_wdt(0);
-}
-static void __init mx51_babbage_timer_init(void)
-{
-        mx51_clocks_init(32768, 24000000, 22579200, 0);
-}
-MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
-        /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
-        .atag_offset = 0x100,
-        .map_io = mx51_map_io,
-        .init_early = imx51_init_early,
-        .init_irq = mx51_init_irq,
-        .handle_irq = imx51_handle_irq,
-        .init_time      = mx51_babbage_timer_init,
-        .init_machine = mx51_babbage_init,
-        .init_late      = imx51_init_late,
-        .restart        = mxc_restart,
-MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index c91894003da9..0b5d1ca31b9f 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -267,7 +267,6 @@ MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = mxt_td60_timer_init,
        .init_machine = mxt_td60_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index bf3ac51d5aca..12212378c672 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -245,8 +245,7 @@ static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
        int ret;
        ret = request_irq(gpio_to_irq(IMX_GPIO_NR(3, 29)), detect_irq,
-                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          IRQF_TRIGGER_FALLING, "imx-mmc-detect", data);
-                          "imx-mmc-detect", data);
        if (ret)
                printk(KERN_ERR
                        "pca100: Failed to request irq for sd/mmc detection\n");
@@ -421,7 +420,6 @@ MACHINE_START(PCA100, "phyCARD-i.MX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_machine = pca100_init,
        .init_time      = pca100_timer_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 639a3dfb0092..81b8affb9448 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -703,7 +703,6 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = pcm037_timer_init,
        .init_machine = pcm037_init,
        .init_late = pcm037_init_late,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 592ddbe031ac..6c56fb5553c7 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -351,7 +351,6 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
        .map_io = mx27_map_io,
        .init_early = imx27_init_early,
        .init_irq = mx27_init_irq,
-        .handle_irq = imx27_handle_irq,
        .init_time      = pcm038_timer_init,
        .init_machine = pcm038_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index ac504b67326b..c62b5d261345 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -400,7 +400,6 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
        .init_time = pcm043_timer_init,
        .init_machine = pcm043_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 22af27ed457e..a213e7b9cb1c 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -266,7 +266,6 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .map_io = mx31_map_io,
        .init_early = imx31_init_early,
        .init_irq = mx31_init_irq,
-        .handle_irq = imx31_handle_irq,
        .init_time      = qong_timer_init,
        .init_machine = qong_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index b0fa10dd79fe..1f6bc3f7ae14 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -137,7 +137,6 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .map_io = mx1_map_io,
        .init_early = imx1_init_early,
        .init_irq = mx1_init_irq,
-        .handle_irq = imx1_handle_irq,
        .init_time      = scb9328_timer_init,
        .init_machine = scb9328_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-vf610.c b/arch/arm/mach-imx/mach-vf610.c
index 2d8aef5a6efa..c44602758120 100644
--- a/arch/arm/mach-imx/mach-vf610.c
+++ b/arch/arm/mach-imx/mach-vf610.c
@@ -20,19 +20,14 @@ static void __init vf610_init_machine(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-static void __init vf610_init_irq(void)
-{
-        l2x0_of_init(0, ~0UL);
-        irqchip_init();
-}
 static const char *vf610_dt_compat[] __initconst = {
        "fsl,vf610",
        NULL,
 };
 DT_MACHINE_START(VYBRID_VF610, "Freescale Vybrid VF610 (Device Tree)")
-        .init_irq       = vf610_init_irq,
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .init_machine   = vf610_init_machine,
        .dt_compat      = vf610_dt_compat,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index 8825d1217d18..872b3c6ba408 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -310,7 +310,6 @@ MACHINE_START(VPR200, "VPR200")
        .map_io = mx35_map_io,
        .init_early = imx35_init_early,
        .init_irq = mx35_init_irq,
-        .handle_irq = imx35_handle_irq,
        .init_time = vpr200_timer_init,
        .init_machine = vpr200_board_init,
        .restart        = mxc_restart,
diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h
index b08ab3ad4a6d..75d6a37e1ae4 100644
--- a/arch/arm/mach-imx/mxc.h
+++ b/arch/arm/mach-imx/mxc.h
@@ -36,6 +36,7 @@
 #define MXC_CPU_MX53            53
 #define MXC_CPU_IMX6SL          0x60
 #define MXC_CPU_IMX6DL          0x61
+#define MXC_CPU_IMX6SX          0x62
 #define MXC_CPU_IMX6Q           0x63
 #define IMX_CHIP_REVISION_1_0           0x10
@@ -163,6 +164,11 @@ static inline bool cpu_is_imx6dl(void)
        return __mxc_cpu_type == MXC_CPU_IMX6DL;
 }
+static inline bool cpu_is_imx6sx(void)
+{
+        return __mxc_cpu_type == MXC_CPU_IMX6SX;
+}
 static inline bool cpu_is_imx6q(void)
 {
        return __mxc_cpu_type == MXC_CPU_IMX6Q;
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 20048ff05739..fe123b079c05 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -334,28 +334,10 @@ ENDPROC(imx6_suspend)
 * turned into relative ones.
 */
-#ifdef CONFIG_CACHE_L2X0
-        .macro  pl310_resume
-        adr     r0, l2x0_saved_regs_offset
-        ldr     r2, [r0]
-        add     r2, r2, r0
-        ldr     r0, [r2, #L2X0_R_PHY_BASE]      @ get physical base of l2x0
-        ldr     r1, [r2, #L2X0_R_AUX_CTRL]      @ get aux_ctrl value
-        str     r1, [r0, #L2X0_AUX_CTRL]        @ restore aux_ctrl
-        mov     r1, #0x1
-        str     r1, [r0, #L2X0_CTRL]            @ re-enable L2
-        .endm
-l2x0_saved_regs_offset:
-        .word   l2x0_saved_regs - .
-#else
-        .macro  pl310_resume
-        .endm
-#endif
 ENTRY(v7_cpu_resume)
        bl      v7_invalidate_l1
-        pl310_resume
+#ifdef CONFIG_CACHE_L2X0
+        bl      l2c310_early_resume
+#endif
        b       cpu_resume
 ENDPROC(v7_cpu_resume)
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 5e3027d3692f..3b0733edb68c 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -124,7 +124,7 @@ void __init imx_init_l2cache(void)
        }
        /* Configure the L2 PREFETCH and POWER registers */
-        val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+        val = readl_relaxed(l2x0_base + L310_PREFETCH_CTRL);
        val |= 0x70800000;
        /*
         * The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
@@ -137,14 +137,12 @@ void __init imx_init_l2cache(void)
         */
        if (cpu_is_imx6q())
                val &= ~(1 << 30 | 1 << 23);
-        writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
+        writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
-        val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
-        writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
        iounmap(l2x0_base);
        of_node_put(np);
 out:
-        l2x0_of_init(0, ~0UL);
+        l2x0_of_init(0, ~0);
 }
 #endif
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index 65222ea0df6d..bed081e58262 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -28,6 +28,9 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/sched_clock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <asm/mach/time.h>
@@ -328,3 +331,15 @@ void __init mxc_timer_init(void __iomem *base, int irq)
        /* Make irqs happen */
        setup_irq(irq, &mxc_timer_irq);
 }
+void __init mxc_timer_init_dt(struct device_node *np)
+{
+        void __iomem *base;
+        int irq;
+        base = of_iomap(np, 0);
+        WARN_ON(!base);
+        irq = irq_of_parse_and_map(np, 0);
+        mxc_timer_init(base, irq);
+}
diff --git a/arch/arm/mach-imx/tzic.c b/arch/arm/mach-imx/tzic.c
index 8183178d5aa3..7828af4b2022 100644
--- a/arch/arm/mach-imx/tzic.c
+++ b/arch/arm/mach-imx/tzic.c
@@ -125,7 +125,7 @@ static __init void tzic_init_gc(int idx, unsigned int irq_start)
        irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
 }
-asmlinkage void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
+static void __exception_irq_entry tzic_handle_irq(struct pt_regs *regs)
 {
        u32 stat;
        int i, irqofs, handled;
@@ -189,6 +189,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
        for (i = 0; i < 4; i++, irq_base += 32)
                tzic_init_gc(i, irq_base);
+        set_handle_irq(tzic_handle_irq);
 #ifdef CONFIG_FIQ
        /* Initialize FIQ */
        init_FIQ(FIQ_START);
diff --git a/arch/arm/mach-iop13xx/include/mach/irqs.h b/arch/arm/mach-iop13xx/include/mach/irqs.h
index 054e7acb5bfa..e8d24d32121a 100644
--- a/arch/arm/mach-iop13xx/include/mach/irqs.h
+++ b/arch/arm/mach-iop13xx/include/mach/irqs.h
@@ -191,6 +191,4 @@ static inline u32 read_intpnd_3(void)
 #define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
 #endif
-#define NR_IRQS         NR_IOP13XX_IRQS
 #endif /* _IOP13XX_IRQ_H_ */
diff --git a/arch/arm/mach-iop13xx/include/mach/time.h b/arch/arm/mach-iop13xx/include/mach/time.h
index f1c00d6d560b..15bc9bb78a6b 100644
--- a/arch/arm/mach-iop13xx/include/mach/time.h
+++ b/arch/arm/mach-iop13xx/include/mach/time.h
@@ -1,5 +1,8 @@
 #ifndef _IOP13XX_TIME_H_
 #define _IOP13XX_TIME_H_
+#include <mach/irqs.h>
 #define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
 #define IOP_TMR_EN          0x02
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 02a8228ac2d3..9cd07d396093 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -93,4 +93,5 @@ MACHINE_START(IQ81340MC, "Intel IQ81340MC")
        .init_time      = iq81340mc_timer_init,
        .init_machine   = iq81340mc_init,
        .restart        = iop13xx_restart,
+        .nr_irqs        = NR_IOP13XX_IRQS,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index 1b80f10722b3..b3ec11cb707e 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -95,4 +95,5 @@ MACHINE_START(IQ81340SC, "Intel IQ81340SC")
        .init_time      = iq81340sc_timer_init,
        .init_machine   = iq81340sc_init,
        .restart        = iop13xx_restart,
+        .nr_irqs        = NR_IOP13XX_IRQS,
 MACHINE_END
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index 560d5b2dec22..e7730cf9c15d 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -23,10 +23,7 @@
 #include <linux/msi.h>
 #include <asm/mach/irq.h>
 #include <asm/irq.h>
+#include <mach/irqs.h>
-#define IOP13XX_NUM_MSI_IRQS 128
-static DECLARE_BITMAP(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
 /* IMIPR0 CP6 R8 Page 1
 */
@@ -121,41 +118,6 @@ void __init iop13xx_msi_init(void)
        irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
 }
-/*
- * Dynamic irq allocate and deallocation
- */
-int create_irq(void)
-{
-        int irq, pos;
-again:
-        pos = find_first_zero_bit(msi_irq_in_use, IOP13XX_NUM_MSI_IRQS);
-        irq = IRQ_IOP13XX_MSI_0 + pos;
-        if (irq > NR_IRQS)
-                return -ENOSPC;
-        /* test_and_set_bit operates on 32-bits at a time */
-        if (test_and_set_bit(pos, msi_irq_in_use))
-                goto again;
-        dynamic_irq_init(irq);
-        return irq;
-}
-void destroy_irq(unsigned int irq)
-{
-        int pos = irq - IRQ_IOP13XX_MSI_0;
-        dynamic_irq_cleanup(irq);
-        clear_bit(pos, msi_irq_in_use);
-}
-void arch_teardown_msi_irq(unsigned int irq)
-{
-        destroy_irq(irq);
-}
 static void iop13xx_msi_nop(struct irq_data *d)
 {
        return;
@@ -172,12 +134,17 @@ static struct irq_chip iop13xx_msi_chip = {
 int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 {
-        int id, irq = create_irq();
+        int id, irq = irq_alloc_desc_from(IRQ_IOP13XX_MSI_0, -1);
        struct msi_msg msg;
        if (irq < 0)
                return irq;
+        if (irq >= NR_IOP13XX_IRQS) {
+                irq_free_desc(irq);
+                return -ENOSPC;
+        }
        irq_set_msi_desc(irq, desc);
        msg.address_hi = 0x0;
@@ -191,3 +158,8 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
        return 0;
 }
+void arch_teardown_msi_irq(unsigned int irq)
+{
+        irq_free_desc(irq);
+}
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index 96e6c7a6793b..bca96f433495 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -27,6 +27,7 @@
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/hardware/iop_adma.h>
+#include <mach/irqs.h>
 #define IOP13XX_UART_XTAL 33334000
 #define IOP13XX_SETUP_DEBUG 0
diff --git a/arch/arm/mach-iop13xx/tpmi.c b/arch/arm/mach-iop13xx/tpmi.c
index 6fdad7a0425a..db511ec2b1df 100644
--- a/arch/arm/mach-iop13xx/tpmi.c
+++ b/arch/arm/mach-iop13xx/tpmi.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <asm/irq.h>
 #include <asm/sizes.h>
+#include <mach/irqs.h>
 /* assumes CONTROLLER_ONLY# is never asserted in the ESSR register */
 #define IOP13XX_TPMI_MMR(dev)   IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 2801da49e2a3..ff18ff20f71f 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -195,7 +195,7 @@ static void __init kirkwood_dt_init(void)
 {
        kirkwood_disable_mbus_error_propagation();
-        BUG_ON(mvebu_mbus_dt_init());
+        BUG_ON(mvebu_mbus_dt_init(false));
 #ifdef CONFIG_CACHE_FEROCEON_L2
        feroceon_of_init();
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 2a97a2e4163c..2c47a8ad0e27 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -7,6 +7,7 @@
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */
+#include <asm/exception.h>
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
@@ -30,11 +31,47 @@ static int __initdata gpio1_irqs[4] = {
        0,
 };
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+static void __iomem *kirkwood_irq_base = IRQ_VIRT_BASE;
+asmlinkage void
+__exception_irq_entry kirkwood_legacy_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+        stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_LOW_OFF);
+        stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_LOW_OFF);
+        if (stat) {
+                unsigned int hwirq = __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+        stat = readl_relaxed(kirkwood_irq_base + IRQ_CAUSE_HIGH_OFF);
+        stat &= readl_relaxed(kirkwood_irq_base + IRQ_MASK_HIGH_OFF);
+        if (stat) {
+                unsigned int hwirq = 32 + __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+}
+#endif
 void __init kirkwood_init_irq(void)
 {
        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        set_handle_irq(kirkwood_legacy_handle_irq);
+#endif
        /*
         * Initialize gpiolib for GPIOs 0-49.
         */
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 34932e0e31fa..7858d5b6f6ce 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -202,9 +202,6 @@ static struct mmci_platform_data lpc32xx_mmci_data = {
        .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
                          MMC_VDD_32_33 | MMC_VDD_33_34,
        .ios_handler    = mmc_handle_ios,
-        .dma_filter     = NULL,
-        /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
-         * gather, and the MMCI driver doesn't do it this way */
 };
 static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index a7f959e58c3d..9b26976fb084 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -42,9 +42,6 @@ config ARCH_QSD8X50
 endchoice
-config MSM_HAS_DEBUG_UART_HS
-        bool
 config MSM_SOC_REV_A
        bool
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index a77529887cbc..61bfe584a9d7 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -83,11 +83,6 @@ static void __init halibut_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-static void __init halibut_fixup(struct tag *tags, char **cmdline,
-                                 struct meminfo *mi)
-{
-}
 static void __init halibut_map_io(void)
 {
        msm_map_common_io();
@@ -100,7 +95,6 @@ static void __init halibut_init_late(void)
 MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
        .atag_offset    = 0x100,
-        .fixup          = halibut_fixup,
        .map_io         = halibut_map_io,
        .init_early     = halibut_init_early,
        .init_irq       = halibut_init_irq,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 7d9981cb400e..873c3ca3cd7e 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -22,6 +22,7 @@
 #include <linux/io.h>
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/memblock.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -52,16 +53,10 @@ static void __init mahimahi_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-static void __init mahimahi_fixup(struct tag *tags, char **cmdline,
+static void __init mahimahi_fixup(struct tag *tags, char **cmdline)
-                                  struct meminfo *mi)
 {
-        mi->nr_banks = 2;
+        memblock_add(PHYS_OFFSET, 219*SZ_1M);
-        mi->bank[0].start = PHYS_OFFSET;
+        memblock_add(MSM_HIGHMEM_BASE, MSM_HIGHMEM_SIZE);
-        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
-        mi->bank[0].size = (219*1024*1024);
-        mi->bank[1].start = MSM_HIGHMEM_BASE;
-        mi->bank[1].node = PHYS_TO_NID(MSM_HIGHMEM_BASE);
-        mi->bank[1].size = MSM_HIGHMEM_SIZE;
 }
 static void __init mahimahi_map_io(void)
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 46de789ad3ae..245884319d2e 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -40,8 +40,7 @@
 #include "proc_comm.h"
 #include "common.h"
-static void __init msm7x30_fixup(struct tag *tag, char **cmdline,
+static void __init msm7x30_fixup(struct tag *tag, char **cmdline)
-                struct meminfo *mi)
 {
        for (; tag->hdr.size; tag = tag_next(tag))
                if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) {
@@ -95,7 +94,7 @@ static int hsusb_phy_clk_reset(struct clk *phy_clk)
 static struct msm_otg_platform_data msm_otg_pdata = {
        .phy_init_seq           = hsusb_phy_init_seq,
-        .mode                   = USB_PERIPHERAL,
+        .mode                   = USB_DR_MODE_PERIPHERAL,
        .otg_control            = OTG_PHY_CONTROL,
        .link_clk_reset         = hsusb_link_clk_reset,
        .phy_clk_reset          = hsusb_phy_clk_reset,
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 9169ec324a43..4c748616ef47 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -116,7 +116,7 @@ static int hsusb_phy_clk_reset(struct clk *phy_clk)
 static struct msm_otg_platform_data msm_otg_pdata = {
        .phy_init_seq           = hsusb_phy_init_seq,
-        .mode                   = USB_PERIPHERAL,
+        .mode                   = USB_DR_MODE_PERIPHERAL,
        .otg_control            = OTG_PHY_CONTROL,
        .link_clk_reset         = hsusb_link_clk_reset,
        .phy_clk_reset          = hsusb_phy_clk_reset,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 327605174d63..e50967926dcd 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -35,6 +35,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/memblock.h>
 #include "gpio_chip.h"
 #include "board-sapphire.h"
@@ -74,22 +75,18 @@ static struct map_desc sapphire_io_desc[] __initdata = {
        }
 };
-static void __init sapphire_fixup(struct tag *tags, char **cmdline,
+static void __init sapphire_fixup(struct tag *tags, char **cmdline)
-                                  struct meminfo *mi)
 {
        int smi_sz = parse_tag_smi((const struct tag *)tags);
-        mi->nr_banks = 1;
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].node = PHYS_TO_NID(PHYS_OFFSET);
        if (smi_sz == 32) {
-                mi->bank[0].size = (84*1024*1024);
+                memblock_add(PHYS_OFFSET, 84*SZ_1M);
        } else if (smi_sz == 64) {
-                mi->bank[0].size = (101*1024*1024);
+                memblock_add(PHYS_OFFSET, 101*SZ_1M);
        } else {
+                memblock_add(PHYS_OFFSET, 101*SZ_1M);
                /* Give a default value when not get smi size */
                smi_sz = 64;
-                mi->bank[0].size = (101*1024*1024);
        }
 }
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 87e1d01edecc..2c25050209ce 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -89,7 +89,7 @@ static int trout_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
                        .base             = base_gpio,                  \
                        .ngpio            = 8,                          \
                },                                                      \
-                .reg = (void *) reg_num + TROUT_CPLD_BASE,              \
+                .reg = reg_num + TROUT_CPLD_BASE,                       \
                .shadow = shadow_val,                                   \
        }
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 015d544aa017..f72b07de2152 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/clkdev.h>
+#include <linux/memblock.h>
 #include <asm/system_info.h>
 #include <asm/mach-types.h>
@@ -55,12 +56,9 @@ static void __init trout_init_irq(void)
        msm_init_irq();
 }
-static void __init trout_fixup(struct tag *tags, char **cmdline,
+static void __init trout_fixup(struct tag *tags, char **cmdline)
-                               struct meminfo *mi)
 {
-        mi->nr_banks = 1;
+        memblock_add(PHYS_OFFSET, 101*SZ_1M);
-        mi->bank[0].start = PHYS_OFFSET;
-        mi->bank[0].size = (101*1024*1024);
 }
 static void __init trout_init(void)
@@ -78,7 +76,7 @@ static void __init trout_init(void)
 static struct map_desc trout_io_desc[] __initdata = {
        {
-                .virtual = TROUT_CPLD_BASE,
+                .virtual = (unsigned long)TROUT_CPLD_BASE,
                .pfn     = __phys_to_pfn(TROUT_CPLD_START),
                .length  = TROUT_CPLD_SIZE,
                .type    = MT_DEVICE_NONSHARED
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index b2379ede43bc..adb757abbb92 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -58,7 +58,7 @@
 #define TROUT_4_TP_LS_EN    19
 #define TROUT_5_TP_LS_EN    1
-#define TROUT_CPLD_BASE   0xE8100000
+#define TROUT_CPLD_BASE   IOMEM(0xE8100000)
 #define TROUT_CPLD_START  0x98000000
 #define TROUT_CPLD_SIZE   SZ_4K
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 3f73eecbcfb0..6090b9eb00c8 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -3,15 +3,13 @@ config ARCH_MVEBU
        select ARCH_SUPPORTS_BIG_ENDIAN
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP
-        select IRQ_DOMAIN
        select PINCTRL
        select PLAT_ORION
+        select SOC_BUS
        select MVEBU_MBUS
        select ZONE_DMA if ARM_LPAE
        select ARCH_REQUIRE_GPIOLIB
-        select MIGHT_HAVE_PCI
        select PCI_QUIRKS if PCI
-        select OF_ADDRESS_PCI
 if ARCH_MVEBU
@@ -38,7 +36,9 @@ config MACH_ARMADA_375
        select ARM_ERRATA_753970
        select ARM_GIC
        select ARMADA_375_CLK
-        select CPU_V7
+        select HAVE_ARM_SCU
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
        select MACH_MVEBU_V7
        select PINCTRL_ARMADA_375
        help
@@ -51,7 +51,9 @@ config MACH_ARMADA_38X
        select ARM_ERRATA_753970
        select ARM_GIC
        select ARMADA_38X_CLK
-        select CPU_V7
+        select HAVE_ARM_SCU
+        select HAVE_ARM_TWD if SMP
+        select HAVE_SMP
        select MACH_MVEBU_V7
        select PINCTRL_ARMADA_38X
        help
@@ -86,24 +88,15 @@ config MACH_KIRKWOOD
        select ARCH_REQUIRE_GPIOLIB
        select CPU_FEROCEON
        select KIRKWOOD_CLK
-        select OF_IRQ
        select ORION_IRQCHIP
        select ORION_TIMER
        select PCI
        select PCI_QUIRKS
        select PINCTRL_KIRKWOOD
-        select USE_OF
        help
          Say 'Y' here if you want your kernel to support boards based
          on the Marvell Kirkwood device tree.
-config MACH_T5325
-        bool "HP T5325 thin client"
-        depends on MACH_KIRKWOOD
-        help
-          Say 'Y' here if you want your kernel to support the
-          HP T5325 Thin client
 endmenu
 endif
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index a63e43b6b451..2ecb828e4a8b 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -2,12 +2,15 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
        -I$(srctree)/arch/arm/plat-orion/include
 AFLAGS_coherency_ll.o           := -Wa,-march=armv7-a
+CFLAGS_pmsu.o                   := -march=armv7-a
 obj-y                            += system-controller.o mvebu-soc-id.o
-obj-$(CONFIG_MACH_MVEBU_V7)      += board-v7.o
+ifeq ($(CONFIG_MACH_MVEBU_V7),y)
+obj-y                            += cpu-reset.o board-v7.o coherency.o coherency_ll.o pmsu.o
+obj-$(CONFIG_SMP)                += platsmp.o headsmp.o platsmp-a9.o headsmp-a9.o
+obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
+endif
 obj-$(CONFIG_MACH_DOVE)          += dove.o
-obj-$(CONFIG_ARCH_MVEBU)         += coherency.o coherency_ll.o pmsu.o
-obj-$(CONFIG_SMP)                += platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU)        += hotplug.o
 obj-$(CONFIG_MACH_KIRKWOOD)      += kirkwood.o kirkwood-pm.o
-obj-$(CONFIG_MACH_T5325)         += board-t5325.o
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 237c86b83390..c3465f5b1250 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -20,8 +20,6 @@
 #define ARMADA_XP_MAX_CPUS 4
-void armada_mpic_send_doorbell(const struct cpumask *mask, unsigned int irq);
-void armada_xp_mpic_smp_cpu_init(void);
 void armada_xp_secondary_startup(void);
 extern struct smp_operations armada_xp_smp_ops;
 #endif
diff --git a/arch/arm/mach-mvebu/board-t5325.c b/arch/arm/mach-mvebu/board-t5325.c
deleted file mode 100644
index 65ace6db9f28..000000000000
--- a/arch/arm/mach-mvebu/board-t5325.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * HP T5325 Board Setup
- *
- * Copyright (C) 2014
- *
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/i2c.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <sound/alc5623.h>
-#include "board.h"
-static struct platform_device hp_t5325_audio_device = {
-        .name           = "t5325-audio",
-        .id             = -1,
-};
-static struct alc5623_platform_data alc5621_data = {
-        .add_ctrl = 0x3700,
-        .jack_det_ctrl = 0x4810,
-};
-static struct i2c_board_info i2c_board_info[] __initdata = {
-        {
-                I2C_BOARD_INFO("alc5621", 0x1a),
-                .platform_data = &alc5621_data,
-        },
-};
-void __init t5325_init(void)
-{
-        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
-        platform_device_register(&hp_t5325_audio_device);
-}
diff --git a/arch/arm/mach-mvebu/board-v7.c b/arch/arm/mach-mvebu/board-v7.c
index 333fca8fdc41..8bb742fdf5ca 100644
--- a/arch/arm/mach-mvebu/board-v7.c
+++ b/arch/arm/mach-mvebu/board-v7.c
@@ -27,12 +27,30 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <asm/smp_scu.h>
 #include "armada-370-xp.h"
 #include "common.h"
 #include "coherency.h"
 #include "mvebu-soc-id.h"
 /*
+ * Enables the SCU when available. Obviously, this is only useful on
+ * Cortex-A based SOCs, not on PJ4B based ones.
+ */
+static void __init mvebu_scu_enable(void)
+{
+        void __iomem *scu_base;
+        struct device_node *np =
+                of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
+        if (np) {
+                scu_base = of_iomap(np, 0);
+                scu_enable(scu_base);
+                of_node_put(np);
+        }
+}
+/*
 * Early versions of Armada 375 SoC have a bug where the BootROM
 * leaves an external data abort pending. The kernel is hit by this
 * data abort as soon as it enters userspace, because it unmasks the
@@ -57,11 +75,9 @@ static void __init mvebu_timer_and_clk_init(void)
 {
        of_clk_init(NULL);
        clocksource_of_init();
+        mvebu_scu_enable();
        coherency_init();
-        BUG_ON(mvebu_mbus_dt_init());
+        BUG_ON(mvebu_mbus_dt_init(coherency_available()));
-#ifdef CONFIG_CACHE_L2X0
-        l2x0_of_init(0, ~0UL);
-#endif
        if (of_machine_is_compatible("marvell,armada375"))
                hook_fault_code(16 + 6, armada_375_external_abort_wa, SIGBUS, 0,
@@ -78,7 +94,7 @@ static void __init i2c_quirk(void)
         * mechanism. We can exit only if we are sure that we can
         * get the SoC revision and it is more recent than A0.
         */
-        if (mvebu_get_soc_id(&rev, &dev) == 0 && dev > MV78XX0_A0_REV)
+        if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > MV78XX0_A0_REV)
                return;
        for_each_compatible_node(np, NULL, "marvell,mv78230-i2c") {
@@ -96,10 +112,66 @@ static void __init i2c_quirk(void)
        return;
 }
+#define A375_Z1_THERMAL_FIXUP_OFFSET 0xc
+static void __init thermal_quirk(void)
+{
+        struct device_node *np;
+        u32 dev, rev;
+        if (mvebu_get_soc_id(&dev, &rev) == 0 && rev > ARMADA_375_Z1_REV)
+                return;
+        for_each_compatible_node(np, NULL, "marvell,armada375-thermal") {
+                struct property *prop;
+                __be32 newval, *newprop, *oldprop;
+                int len;
+                /*
+                 * The register offset is at a wrong location. This quirk
+                 * creates a new reg property as a clone of the previous
+                 * one and corrects the offset.
+                 */
+                oldprop = (__be32 *)of_get_property(np, "reg", &len);
+                if (!oldprop)
+                        continue;
+                /* Create a duplicate of the 'reg' property */
+                prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+                prop->length = len;
+                prop->name = kstrdup("reg", GFP_KERNEL);
+                prop->value = kzalloc(len, GFP_KERNEL);
+                memcpy(prop->value, oldprop, len);
+                /* Fixup the register offset of the second entry */
+                oldprop += 2;
+                newprop = (__be32 *)prop->value + 2;
+                newval = cpu_to_be32(be32_to_cpu(*oldprop) -
+                                     A375_Z1_THERMAL_FIXUP_OFFSET);
+                *newprop = newval;
+                of_update_property(np, prop);
+                /*
+                 * The thermal controller needs some quirk too, so let's change
+                 * the compatible string to reflect this.
+                 */
+                prop = kzalloc(sizeof(*prop), GFP_KERNEL);
+                prop->name = kstrdup("compatible", GFP_KERNEL);
+                prop->length = sizeof("marvell,armada375-z1-thermal");
+                prop->value = kstrdup("marvell,armada375-z1-thermal",
+                                                GFP_KERNEL);
+                of_update_property(np, prop);
+        }
+        return;
+}
 static void __init mvebu_dt_init(void)
 {
        if (of_machine_is_compatible("plathome,openblocks-ax3-4"))
                i2c_quirk();
+        if (of_machine_is_compatible("marvell,a375-db"))
+                thermal_quirk();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -109,6 +181,8 @@ static const char * const armada_370_xp_dt_compat[] = {
 };
 DT_MACHINE_START(ARMADA_370_XP_DT, "Marvell Armada 370/XP (Device Tree)")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .smp            = smp_ops(armada_xp_smp_ops),
        .init_machine   = mvebu_dt_init,
        .init_time      = mvebu_timer_and_clk_init,
@@ -122,7 +196,10 @@ static const char * const armada_375_dt_compat[] = {
 };
 DT_MACHINE_START(ARMADA_375_DT, "Marvell Armada 375 (Device Tree)")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .init_time      = mvebu_timer_and_clk_init,
+        .init_machine   = mvebu_dt_init,
        .restart        = mvebu_restart,
        .dt_compat      = armada_375_dt_compat,
 MACHINE_END
@@ -134,6 +211,8 @@ static const char * const armada_38x_dt_compat[] = {
 };
 DT_MACHINE_START(ARMADA_38X_DT, "Marvell Armada 380/385 (Device Tree)")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .init_time      = mvebu_timer_and_clk_init,
        .restart        = mvebu_restart,
        .dt_compat      = armada_38x_dt_compat,
diff --git a/arch/arm/mach-mvebu/board.h b/arch/arm/mach-mvebu/board.h
index de7f0a191394..9c7bb4386f8b 100644
--- a/arch/arm/mach-mvebu/board.h
+++ b/arch/arm/mach-mvebu/board.h
@@ -13,10 +13,4 @@
 #ifndef __ARCH_MVEBU_BOARD_H
 #define __ARCH_MVEBU_BOARD_H
-#ifdef CONFIG_MACH_T5325
-void t5325_init(void);
-#else
-static inline void t5325_init(void) {};
-#endif
 #endif
diff --git a/arch/arm/mach-mvebu/coherency.c b/arch/arm/mach-mvebu/coherency.c
index 4e9d58148ca7..477202fd39cc 100644
--- a/arch/arm/mach-mvebu/coherency.c
+++ b/arch/arm/mach-mvebu/coherency.c
@@ -17,6 +17,8 @@
 * supplies basic routines for configuring and controlling hardware coherency
 */
+#define pr_fmt(fmt) "mvebu-coherency: " fmt
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of_address.h>
@@ -24,13 +26,19 @@
 #include <linux/smp.h>
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/mbus.h>
+#include <linux/clk.h>
+#include <linux/pci.h>
 #include <asm/smp_plat.h>
 #include <asm/cacheflush.h>
+#include <asm/mach/map.h>
 #include "armada-370-xp.h"
 #include "coherency.h"
+#include "mvebu-soc-id.h"
 unsigned long coherency_phys_base;
-static void __iomem *coherency_base;
+void __iomem *coherency_base;
 static void __iomem *coherency_cpu_base;
 /* Coherency fabric registers */
@@ -38,27 +46,190 @@ static void __iomem *coherency_cpu_base;
 #define IO_SYNC_BARRIER_CTL_OFFSET                 0x0
+enum {
+        COHERENCY_FABRIC_TYPE_NONE,
+        COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
+        COHERENCY_FABRIC_TYPE_ARMADA_375,
+        COHERENCY_FABRIC_TYPE_ARMADA_380,
+};
 static struct of_device_id of_coherency_table[] = {
-        {.compatible = "marvell,coherency-fabric"},
+        {.compatible = "marvell,coherency-fabric",
+         .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
+        {.compatible = "marvell,armada-375-coherency-fabric",
+         .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
+        {.compatible = "marvell,armada-380-coherency-fabric",
+         .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
        { /* end of list */ },
 };
-/* Function defined in coherency_ll.S */
+/* Functions defined in coherency_ll.S */
-int ll_set_cpu_coherent(void __iomem *base_addr, unsigned int hw_cpu_id);
+int ll_enable_coherency(void);
+void ll_add_cpu_to_smp_group(void);
-int set_cpu_coherent(unsigned int hw_cpu_id, int smp_group_id)
+int set_cpu_coherent(void)
 {
        if (!coherency_base) {
-                pr_warn("Can't make CPU %d cache coherent.\n", hw_cpu_id);
+                pr_warn("Can't make current CPU cache coherent.\n");
                pr_warn("Coherency fabric is not initialized\n");
                return 1;
        }
-        return ll_set_cpu_coherent(coherency_base, hw_cpu_id);
+        ll_add_cpu_to_smp_group();
+        return ll_enable_coherency();
+}
+/*
+ * The below code implements the I/O coherency workaround on Armada
+ * 375. This workaround consists in using the two channels of the
+ * first XOR engine to trigger a XOR transaction that serves as the
+ * I/O coherency barrier.
+ */
+static void __iomem *xor_base, *xor_high_base;
+static dma_addr_t coherency_wa_buf_phys[CONFIG_NR_CPUS];
+static void *coherency_wa_buf[CONFIG_NR_CPUS];
+static bool coherency_wa_enabled;
+#define XOR_CONFIG(chan)            (0x10 + (chan * 4))
+#define XOR_ACTIVATION(chan)        (0x20 + (chan * 4))
+#define WINDOW_BAR_ENABLE(chan)     (0x240 + ((chan) << 2))
+#define WINDOW_BASE(w)              (0x250 + ((w) << 2))
+#define WINDOW_SIZE(w)              (0x270 + ((w) << 2))
+#define WINDOW_REMAP_HIGH(w)        (0x290 + ((w) << 2))
+#define WINDOW_OVERRIDE_CTRL(chan)  (0x2A0 + ((chan) << 2))
+#define XOR_DEST_POINTER(chan)      (0x2B0 + (chan * 4))
+#define XOR_BLOCK_SIZE(chan)        (0x2C0 + (chan * 4))
+#define XOR_INIT_VALUE_LOW           0x2E0
+#define XOR_INIT_VALUE_HIGH          0x2E4
+static inline void mvebu_hwcc_armada375_sync_io_barrier_wa(void)
+{
+        int idx = smp_processor_id();
+        /* Write '1' to the first word of the buffer */
+        writel(0x1, coherency_wa_buf[idx]);
+        /* Wait until the engine is idle */
+        while ((readl(xor_base + XOR_ACTIVATION(idx)) >> 4) & 0x3)
+                ;
+        dmb();
+        /* Trigger channel */
+        writel(0x1, xor_base + XOR_ACTIVATION(idx));
+        /* Poll the data until it is cleared by the XOR transaction */
+        while (readl(coherency_wa_buf[idx]))
+                ;
+}
+static void __init armada_375_coherency_init_wa(void)
+{
+        const struct mbus_dram_target_info *dram;
+        struct device_node *xor_node;
+        struct property *xor_status;
+        struct clk *xor_clk;
+        u32 win_enable = 0;
+        int i;
+        pr_warn("enabling coherency workaround for Armada 375 Z1, one XOR engine disabled\n");
+        /*
+         * Since the workaround uses one XOR engine, we grab a
+         * reference to its Device Tree node first.
+         */
+        xor_node = of_find_compatible_node(NULL, NULL, "marvell,orion-xor");
+        BUG_ON(!xor_node);
+        /*
+         * Then we mark it as disabled so that the real XOR driver
+         * will not use it.
+         */
+        xor_status = kzalloc(sizeof(struct property), GFP_KERNEL);
+        BUG_ON(!xor_status);
+        xor_status->value = kstrdup("disabled", GFP_KERNEL);
+        BUG_ON(!xor_status->value);
+        xor_status->length = 8;
+        xor_status->name = kstrdup("status", GFP_KERNEL);
+        BUG_ON(!xor_status->name);
+        of_update_property(xor_node, xor_status);
+        /*
+         * And we remap the registers, get the clock, and do the
+         * initial configuration of the XOR engine.
+         */
+        xor_base = of_iomap(xor_node, 0);
+        xor_high_base = of_iomap(xor_node, 1);
+        xor_clk = of_clk_get_by_name(xor_node, NULL);
+        BUG_ON(!xor_clk);
+        clk_prepare_enable(xor_clk);
+        dram = mv_mbus_dram_info();
+        for (i = 0; i < 8; i++) {
+                writel(0, xor_base + WINDOW_BASE(i));
+                writel(0, xor_base + WINDOW_SIZE(i));
+                if (i < 4)
+                        writel(0, xor_base + WINDOW_REMAP_HIGH(i));
+        }
+        for (i = 0; i < dram->num_cs; i++) {
+                const struct mbus_dram_window *cs = dram->cs + i;
+                writel((cs->base & 0xffff0000) |
+                       (cs->mbus_attr << 8) |
+                       dram->mbus_dram_target_id, xor_base + WINDOW_BASE(i));
+                writel((cs->size - 1) & 0xffff0000, xor_base + WINDOW_SIZE(i));
+                win_enable |= (1 << i);
+                win_enable |= 3 << (16 + (2 * i));
+        }
+        writel(win_enable, xor_base + WINDOW_BAR_ENABLE(0));
+        writel(win_enable, xor_base + WINDOW_BAR_ENABLE(1));
+        writel(0, xor_base + WINDOW_OVERRIDE_CTRL(0));
+        writel(0, xor_base + WINDOW_OVERRIDE_CTRL(1));
+        for (i = 0; i < CONFIG_NR_CPUS; i++) {
+                coherency_wa_buf[i] = kzalloc(PAGE_SIZE, GFP_KERNEL);
+                BUG_ON(!coherency_wa_buf[i]);
+                /*
+                 * We can't use the DMA mapping API, since we don't
+                 * have a valid 'struct device' pointer
+                 */
+                coherency_wa_buf_phys[i] =
+                        virt_to_phys(coherency_wa_buf[i]);
+                BUG_ON(!coherency_wa_buf_phys[i]);
+                /*
+                 * Configure the XOR engine for memset operation, with
+                 * a 128 bytes block size
+                 */
+                writel(0x444, xor_base + XOR_CONFIG(i));
+                writel(128, xor_base + XOR_BLOCK_SIZE(i));
+                writel(coherency_wa_buf_phys[i],
+                       xor_base + XOR_DEST_POINTER(i));
+        }
+        writel(0x0, xor_base + XOR_INIT_VALUE_LOW);
+        writel(0x0, xor_base + XOR_INIT_VALUE_HIGH);
+        coherency_wa_enabled = true;
 }
 static inline void mvebu_hwcc_sync_io_barrier(void)
 {
+        if (coherency_wa_enabled) {
+                mvebu_hwcc_armada375_sync_io_barrier_wa();
+                return;
+        }
        writel(0x1, coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET);
        while (readl(coherency_cpu_base + IO_SYNC_BARRIER_CTL_OFFSET) & 0x1);
 }
@@ -105,8 +276,8 @@ static struct dma_map_ops mvebu_hwcc_dma_ops = {
        .set_dma_mask           = arm_dma_set_mask,
 };
-static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
+static int mvebu_hwcc_notifier(struct notifier_block *nb,
-                                       unsigned long event, void *__dev)
+                               unsigned long event, void *__dev)
 {
        struct device *dev = __dev;
@@ -117,47 +288,148 @@ static int mvebu_hwcc_platform_notifier(struct notifier_block *nb,
        return NOTIFY_OK;
 }
-static struct notifier_block mvebu_hwcc_platform_nb = {
+static struct notifier_block mvebu_hwcc_nb = {
-        .notifier_call = mvebu_hwcc_platform_notifier,
+        .notifier_call = mvebu_hwcc_notifier,
 };
-int __init coherency_init(void)
+static void __init armada_370_coherency_init(struct device_node *np)
+{
+        struct resource res;
+        of_address_to_resource(np, 0, &res);
+        coherency_phys_base = res.start;
+        /*
+         * Ensure secondary CPUs will see the updated value,
+         * which they read before they join the coherency
+         * fabric, and therefore before they are coherent with
+         * the boot CPU cache.
+         */
+        sync_cache_w(&coherency_phys_base);
+        coherency_base = of_iomap(np, 0);
+        coherency_cpu_base = of_iomap(np, 1);
+        set_cpu_coherent();
+}
+/*
+ * This ioremap hook is used on Armada 375/38x to ensure that PCIe
+ * memory areas are mapped as MT_UNCACHED instead of MT_DEVICE. This
+ * is needed as a workaround for a deadlock issue between the PCIe
+ * interface and the cache controller.
+ */
+static void __iomem *
+armada_pcie_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
+                              unsigned int mtype, void *caller)
+{
+        struct resource pcie_mem;
+        mvebu_mbus_get_pcie_mem_aperture(&pcie_mem);
+        if (pcie_mem.start <= phys_addr && (phys_addr + size) <= pcie_mem.end)
+                mtype = MT_UNCACHED;
+        return __arm_ioremap_caller(phys_addr, size, mtype, caller);
+}
+static void __init armada_375_380_coherency_init(struct device_node *np)
+{
+        struct device_node *cache_dn;
+        coherency_cpu_base = of_iomap(np, 0);
+        arch_ioremap_caller = armada_pcie_wa_ioremap_caller;
+        /*
+         * Add the PL310 property "arm,io-coherent". This makes sure the
+         * outer sync operation is not used, which allows to
+         * workaround the system erratum that causes deadlocks when
+         * doing PCIe in an SMP situation on Armada 375 and Armada
+         * 38x.
+         */
+        for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
+                struct property *p;
+                p = kzalloc(sizeof(*p), GFP_KERNEL);
+                p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
+                of_add_property(cache_dn, p);
+        }
+}
+static int coherency_type(void)
 {
        struct device_node *np;
+        const struct of_device_id *match;
-        np = of_find_matching_node(NULL, of_coherency_table);
+        np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
        if (np) {
-                struct resource res;
+                int type = (int) match->data;
-                pr_info("Initializing Coherency fabric\n");
-                of_address_to_resource(np, 0, &res);
+                /* Armada 370/XP coherency works in both UP and SMP */
-                coherency_phys_base = res.start;
+                if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
-                /*
+                        return type;
-                 * Ensure secondary CPUs will see the updated value,
-                 * which they read before they join the coherency
+                /* Armada 375 coherency works only on SMP */
-                 * fabric, and therefore before they are coherent with
+                else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 && is_smp())
-                 * the boot CPU cache.
+                        return type;
-                 */
-                sync_cache_w(&coherency_phys_base);
+                /* Armada 380 coherency works only on SMP */
-                coherency_base = of_iomap(np, 0);
+                else if (type == COHERENCY_FABRIC_TYPE_ARMADA_380 && is_smp())
-                coherency_cpu_base = of_iomap(np, 1);
+                        return type;
-                set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
-                of_node_put(np);
        }
-        return 0;
+        return COHERENCY_FABRIC_TYPE_NONE;
 }
-static int __init coherency_late_init(void)
+int coherency_available(void)
+{
+        return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
+}
+int __init coherency_init(void)
 {
+        int type = coherency_type();
        struct device_node *np;
        np = of_find_matching_node(NULL, of_coherency_table);
-        if (np) {
-                bus_register_notifier(&platform_bus_type,
+        if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
-                                      &mvebu_hwcc_platform_nb);
+                armada_370_coherency_init(np);
-                of_node_put(np);
+        else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
+                 type == COHERENCY_FABRIC_TYPE_ARMADA_380)
+                armada_375_380_coherency_init(np);
+        return 0;
+}
+static int __init coherency_late_init(void)
+{
+        int type = coherency_type();
+        if (type == COHERENCY_FABRIC_TYPE_NONE)
+                return 0;
+        if (type == COHERENCY_FABRIC_TYPE_ARMADA_375) {
+                u32 dev, rev;
+                if (mvebu_get_soc_id(&dev, &rev) == 0 &&
+                    rev == ARMADA_375_Z1_REV)
+                        armada_375_coherency_init_wa();
        }
+        bus_register_notifier(&platform_bus_type,
+                              &mvebu_hwcc_nb);
        return 0;
 }
 postcore_initcall(coherency_late_init);
+#if IS_ENABLED(CONFIG_PCI)
+static int __init coherency_pci_init(void)
+{
+        if (coherency_available())
+                bus_register_notifier(&pci_bus_type,
+                                       &mvebu_hwcc_nb);
+        return 0;
+}
+arch_initcall(coherency_pci_init);
+#endif
diff --git a/arch/arm/mach-mvebu/coherency.h b/arch/arm/mach-mvebu/coherency.h
index 760226c41353..54cb7607b526 100644
--- a/arch/arm/mach-mvebu/coherency.h
+++ b/arch/arm/mach-mvebu/coherency.h
@@ -15,8 +15,9 @@
 #define __MACH_370_XP_COHERENCY_H
 extern unsigned long coherency_phys_base;
+int set_cpu_coherent(void);
-int set_cpu_coherent(unsigned int cpu_id, int smp_group_id);
 int coherency_init(void);
+int coherency_available(void);
 #endif  /* __MACH_370_XP_COHERENCY_H */
diff --git a/arch/arm/mach-mvebu/coherency_ll.S b/arch/arm/mach-mvebu/coherency_ll.S
index ee7598fe75db..510c29e079ca 100644
--- a/arch/arm/mach-mvebu/coherency_ll.S
+++ b/arch/arm/mach-mvebu/coherency_ll.S
@@ -21,38 +21,129 @@
 #define ARMADA_XP_CFB_CFG_REG_OFFSET 0x4
 #include <asm/assembler.h>
+#include <asm/cp15.h>
        .text
+/* Returns the coherency base address in r1 (r0 is untouched) */
+ENTRY(ll_get_coherency_base)
+        mrc     p15, 0, r1, c1, c0, 0
+        tst     r1, #CR_M @ Check MMU bit enabled
+        bne     1f
+        /*
+         * MMU is disabled, use the physical address of the coherency
+         * base address.
+         */
+        adr     r1, 3f
+        ldr     r3, [r1]
+        ldr     r1, [r1, r3]
+        b       2f
+1:
+        /*
+         * MMU is enabled, use the virtual address of the coherency
+         * base address.
+         */
+        ldr     r1, =coherency_base
+        ldr     r1, [r1]
+2:
+        mov     pc, lr
+ENDPROC(ll_get_coherency_base)
 /*
- * r0: Coherency fabric base register address
+ * Returns the coherency CPU mask in r3 (r0 is untouched). This
- * r1: HW CPU id
+ * coherency CPU mask can be used with the coherency fabric
+ * configuration and control registers. Note that the mask is already
+ * endian-swapped as appropriate so that the calling functions do not
+ * have to care about endianness issues while accessing the coherency
+ * fabric registers
 */
-ENTRY(ll_set_cpu_coherent)
+ENTRY(ll_get_coherency_cpumask)
-        /* Create bit by cpu index */
+        mrc     15, 0, r3, cr0, cr0, 5
-        mov     r3, #(1 << 24)
+        and     r3, r3, #15
-        lsl     r1, r3, r1
+        mov     r2, #(1 << 24)
-ARM_BE8(rev     r1, r1)
+        lsl     r3, r2, r3
+ARM_BE8(rev     r3, r3)
-        /* Add CPU to SMP group - Atomic */
+        mov     pc, lr
-        add     r3, r0, #ARMADA_XP_CFB_CTL_REG_OFFSET
+ENDPROC(ll_get_coherency_cpumask)
-1:
-        ldrex   r2, [r3]
+/*
-        orr     r2, r2, r1
+ * ll_add_cpu_to_smp_group(), ll_enable_coherency() and
-        strex   r0, r2, [r3]
+ * ll_disable_coherency() use the strex/ldrex instructions while the
-        cmp     r0, #0
+ * MMU can be disabled. The Armada XP SoC has an exclusive monitor
-        bne 1b
+ * that tracks transactions to Device and/or SO memory and thanks to
+ * that, exclusive transactions are functional even when the MMU is
-        /* Enable coherency on CPU - Atomic */
+ * disabled.
-        add     r3, r3, #ARMADA_XP_CFB_CFG_REG_OFFSET
+ */
+ENTRY(ll_add_cpu_to_smp_group)
+        /*
+         * As r0 is not modified by ll_get_coherency_base() and
+         * ll_get_coherency_cpumask(), we use it to temporarly save lr
+         * and avoid it being modified by the branch and link
+         * calls. This function is used very early in the secondary
+         * CPU boot, and no stack is available at this point.
+         */
+        mov     r0, lr
+        bl      ll_get_coherency_base
+        bl      ll_get_coherency_cpumask
+        mov     lr, r0
+        add     r0, r1, #ARMADA_XP_CFB_CFG_REG_OFFSET
 1:
-        ldrex   r2, [r3]
+        ldrex   r2, [r0]
-        orr     r2, r2, r1
+        orr     r2, r2, r3
-        strex   r0, r2, [r3]
+        strex   r1, r2, [r0]
-        cmp     r0, #0
+        cmp     r1, #0
-        bne 1b
+        bne     1b
+        mov     pc, lr
+ENDPROC(ll_add_cpu_to_smp_group)
+ENTRY(ll_enable_coherency)
+        /*
+         * As r0 is not modified by ll_get_coherency_base() and
+         * ll_get_coherency_cpumask(), we use it to temporarly save lr
+         * and avoid it being modified by the branch and link
+         * calls. This function is used very early in the secondary
+         * CPU boot, and no stack is available at this point.
+         */
+        mov r0, lr
+        bl      ll_get_coherency_base
+        bl      ll_get_coherency_cpumask
+        mov lr, r0
+        add     r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
+1:
+        ldrex   r2, [r0]
+        orr     r2, r2, r3
+        strex   r1, r2, [r0]
+        cmp     r1, #0
+        bne     1b
        dsb
        mov     r0, #0
        mov     pc, lr
-ENDPROC(ll_set_cpu_coherent)
+ENDPROC(ll_enable_coherency)
+ENTRY(ll_disable_coherency)
+        /*
+         * As r0 is not modified by ll_get_coherency_base() and
+         * ll_get_coherency_cpumask(), we use it to temporarly save lr
+         * and avoid it being modified by the branch and link
+         * calls. This function is used very early in the secondary
+         * CPU boot, and no stack is available at this point.
+         */
+        mov     r0, lr
+        bl      ll_get_coherency_base
+        bl      ll_get_coherency_cpumask
+        mov     lr, r0
+        add     r0, r1, #ARMADA_XP_CFB_CTL_REG_OFFSET
+1:
+        ldrex   r2, [r0]
+        bic     r2, r2, r3
+        strex   r1, r2, [r0]
+        cmp     r1, #0
+        bne     1b
+        dsb
+        mov     pc, lr
+ENDPROC(ll_disable_coherency)
+        .align 2
+3:
+        .long   coherency_phys_base - .
diff --git a/arch/arm/mach-mvebu/common.h b/arch/arm/mach-mvebu/common.h
index 55449c487c9e..b67fb7a10d8b 100644
--- a/arch/arm/mach-mvebu/common.h
+++ b/arch/arm/mach-mvebu/common.h
@@ -18,6 +18,9 @@
 #include <linux/reboot.h>
 void mvebu_restart(enum reboot_mode mode, const char *cmd);
+int mvebu_cpu_reset_deassert(int cpu);
+void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr);
+void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr);
 void armada_xp_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-mvebu/cpu-reset.c b/arch/arm/mach-mvebu/cpu-reset.c
new file mode 100644
index 000000000000..4a8f9eebebea
--- /dev/null
+++ b/arch/arm/mach-mvebu/cpu-reset.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (C) 2014 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#define pr_fmt(fmt) "mvebu-cpureset: " fmt
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_address.h>
+#include <linux/io.h>
+#include <linux/resource.h>
+#include "armada-370-xp.h"
+static void __iomem *cpu_reset_base;
+static size_t cpu_reset_size;
+#define CPU_RESET_OFFSET(cpu) (cpu * 0x8)
+#define CPU_RESET_ASSERT      BIT(0)
+int mvebu_cpu_reset_deassert(int cpu)
+{
+        u32 reg;
+        if (!cpu_reset_base)
+                return -ENODEV;
+        if (CPU_RESET_OFFSET(cpu) >= cpu_reset_size)
+                return -EINVAL;
+        reg = readl(cpu_reset_base + CPU_RESET_OFFSET(cpu));
+        reg &= ~CPU_RESET_ASSERT;
+        writel(reg, cpu_reset_base + CPU_RESET_OFFSET(cpu));
+        return 0;
+}
+static int mvebu_cpu_reset_map(struct device_node *np, int res_idx)
+{
+        struct resource res;
+        if (of_address_to_resource(np, res_idx, &res)) {
+                pr_err("unable to get resource\n");
+                return -ENOENT;
+        }
+        if (!request_mem_region(res.start, resource_size(&res),
+                                np->full_name)) {
+                pr_err("unable to request region\n");
+                return -EBUSY;
+        }
+        cpu_reset_base = ioremap(res.start, resource_size(&res));
+        if (!cpu_reset_base) {
+                pr_err("unable to map registers\n");
+                release_mem_region(res.start, resource_size(&res));
+                return -ENOMEM;
+        }
+        cpu_reset_size = resource_size(&res);
+        return 0;
+}
+int __init mvebu_cpu_reset_init(void)
+{
+        struct device_node *np;
+        int res_idx;
+        int ret;
+        np = of_find_compatible_node(NULL, NULL,
+                                     "marvell,armada-370-cpu-reset");
+        if (np) {
+                res_idx = 0;
+        } else {
+                /*
+                 * This code is kept for backward compatibility with
+                 * old Device Trees.
+                 */
+                np = of_find_compatible_node(NULL, NULL,
+                                             "marvell,armada-370-xp-pmsu");
+                if (np) {
+                        pr_warn(FW_WARN "deprecated pmsu binding\n");
+                        res_idx = 1;
+                }
+        }
+        /* No reset node found */
+        if (!np)
+                return -ENODEV;
+        ret = mvebu_cpu_reset_map(np, res_idx);
+        of_node_put(np);
+        return ret;
+}
+early_initcall(mvebu_cpu_reset_init);
diff --git a/arch/arm/mach-mvebu/dove.c b/arch/arm/mach-mvebu/dove.c
index 5e5a43624237..b50464ec1130 100644
--- a/arch/arm/mach-mvebu/dove.c
+++ b/arch/arm/mach-mvebu/dove.c
@@ -23,7 +23,7 @@ static void __init dove_init(void)
 #ifdef CONFIG_CACHE_TAUROS2
        tauros2_init(0);
 #endif
-        BUG_ON(mvebu_mbus_dt_init());
+        BUG_ON(mvebu_mbus_dt_init(false));
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
diff --git a/arch/arm/mach-mvebu/headsmp-a9.S b/arch/arm/mach-mvebu/headsmp-a9.S
new file mode 100644
index 000000000000..5925366bc03c
--- /dev/null
+++ b/arch/arm/mach-mvebu/headsmp-a9.S
@@ -0,0 +1,34 @@
+/*
+ * SMP support: Entry point for secondary CPUs of Marvell EBU
+ * Cortex-A9 based SOCs (Armada 375 and Armada 38x).
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/linkage.h>
+#include <linux/init.h>
+        __CPUINIT
+#define CPU_RESUME_ADDR_REG 0xf10182d4
+.global armada_375_smp_cpu1_enable_code_start
+.global armada_375_smp_cpu1_enable_code_end
+armada_375_smp_cpu1_enable_code_start:
+        ldr     r0, [pc, #4]
+        ldr     r1, [r0]
+        mov     pc, r1
+        .word   CPU_RESUME_ADDR_REG
+armada_375_smp_cpu1_enable_code_end:
+ENTRY(mvebu_cortex_a9_secondary_startup)
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(mvebu_cortex_a9_secondary_startup)
diff --git a/arch/arm/mach-mvebu/headsmp.S b/arch/arm/mach-mvebu/headsmp.S
index 3dd80df428f7..2c4032e368ba 100644
--- a/arch/arm/mach-mvebu/headsmp.S
+++ b/arch/arm/mach-mvebu/headsmp.S
@@ -31,21 +31,10 @@
 ENTRY(armada_xp_secondary_startup)
 ARM_BE8(setend be )                    @ go BE8 if entered LE
-        /* Get coherency fabric base physical address */
+        bl      ll_add_cpu_to_smp_group
-        adr     r0, 1f
-        ldr     r1, [r0]
-        ldr     r0, [r0, r1]
-        /* Read CPU id */
+        bl      ll_enable_coherency
-        mrc     p15, 0, r1, c0, c0, 5
-        and     r1, r1, #0xF
-        /* Add CPU to coherency fabric */
-        bl      ll_set_cpu_coherent
        b       secondary_startup
 ENDPROC(armada_xp_secondary_startup)
-        .align 2
-1:
-        .long   coherency_phys_base - .
diff --git a/arch/arm/mach-mvebu/kirkwood.c b/arch/arm/mach-mvebu/kirkwood.c
index 120207fc36f1..46f105913c84 100644
--- a/arch/arm/mach-mvebu/kirkwood.c
+++ b/arch/arm/mach-mvebu/kirkwood.c
@@ -169,7 +169,7 @@ static void __init kirkwood_dt_init(void)
 {
        kirkwood_disable_mbus_error_propagation();
-        BUG_ON(mvebu_mbus_dt_init());
+        BUG_ON(mvebu_mbus_dt_init(false));
 #ifdef CONFIG_CACHE_FEROCEON_L2
        feroceon_of_init();
@@ -180,9 +180,6 @@ static void __init kirkwood_dt_init(void)
        kirkwood_pm_init();
        kirkwood_dt_eth_fixup();
-        if (of_machine_is_compatible("hp,t5325"))
-                t5325_init();
        of_platform_populate(NULL, of_default_bus_match_table, auxdata, NULL);
 }
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.c b/arch/arm/mach-mvebu/mvebu-soc-id.c
index f3d4cf53f746..d0f35b4d4a23 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.c
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.c
@@ -23,6 +23,8 @@
 #include <linux/kernel.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include "mvebu-soc-id.h"
 #define PCIE_DEV_ID_OFF         0x0
@@ -108,7 +110,18 @@ static int __init mvebu_soc_id_init(void)
        iounmap(pci_base);
 res_ioremap:
-        clk_disable_unprepare(clk);
+        /*
+         * If the PCIe unit is actually enabled and we have PCI
+         * support in the kernel, we intentionally do not release the
+         * reference to the clock. We want to keep it running since
+         * the bootloader does some PCIe link configuration that the
+         * kernel is for now unable to do, and gating the clock would
+         * make us loose this precious configuration.
+         */
+        if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
+                clk_disable_unprepare(clk);
+                clk_put(clk);
+        }
 clk_err:
        of_node_put(child);
@@ -116,5 +129,33 @@ clk_err:
        return ret;
 }
-core_initcall(mvebu_soc_id_init);
+early_initcall(mvebu_soc_id_init);
+static int __init mvebu_soc_device(void)
+{
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        /* Also protects against running on non-mvebu systems */
+        if (!is_id_valid)
+                return 0;
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                return -ENOMEM;
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Marvell");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%X", soc_rev);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%X", soc_dev_id);
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+        }
+        return 0;
+}
+postcore_initcall(mvebu_soc_device);
diff --git a/arch/arm/mach-mvebu/mvebu-soc-id.h b/arch/arm/mach-mvebu/mvebu-soc-id.h
index 31654252fe35..c16bb68ca81f 100644
--- a/arch/arm/mach-mvebu/mvebu-soc-id.h
+++ b/arch/arm/mach-mvebu/mvebu-soc-id.h
@@ -20,6 +20,10 @@
 #define MV78XX0_A0_REV      0x1
 #define MV78XX0_B0_REV      0x2
+/* Armada 375 */
+#define ARMADA_375_Z1_REV   0x0
+#define ARMADA_375_A0_REV   0x3
 #ifdef CONFIG_ARCH_MVEBU
 int mvebu_get_soc_id(u32 *dev, u32 *rev);
 #else
diff --git a/arch/arm/mach-mvebu/platsmp-a9.c b/arch/arm/mach-mvebu/platsmp-a9.c
new file mode 100644
index 000000000000..96c2c59e34b6
--- /dev/null
+++ b/arch/arm/mach-mvebu/platsmp-a9.c
@@ -0,0 +1,102 @@
+/*
+ * Symmetric Multi Processing (SMP) support for Marvell EBU Cortex-A9
+ * based SOCs (Armada 375/38x).
+ *
+ * Copyright (C) 2014 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+#include <linux/mbus.h>
+#include <asm/smp_scu.h>
+#include <asm/smp_plat.h>
+#include "common.h"
+#include "mvebu-soc-id.h"
+#include "pmsu.h"
+#define CRYPT0_ENG_ID   41
+#define CRYPT0_ENG_ATTR 0x1
+#define SRAM_PHYS_BASE  0xFFFF0000
+#define BOOTROM_BASE    0xFFF00000
+#define BOOTROM_SIZE    0x100000
+extern unsigned char armada_375_smp_cpu1_enable_code_end;
+extern unsigned char armada_375_smp_cpu1_enable_code_start;
+void armada_375_smp_cpu1_enable_wa(void)
+{
+        void __iomem *sram_virt_base;
+        mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
+        mvebu_mbus_add_window_by_id(CRYPT0_ENG_ID, CRYPT0_ENG_ATTR,
+                                SRAM_PHYS_BASE, SZ_64K);
+        sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
+        memcpy(sram_virt_base, &armada_375_smp_cpu1_enable_code_start,
+               &armada_375_smp_cpu1_enable_code_end
+               - &armada_375_smp_cpu1_enable_code_start);
+}
+extern void mvebu_cortex_a9_secondary_startup(void);
+static int __cpuinit mvebu_cortex_a9_boot_secondary(unsigned int cpu,
+                                                    struct task_struct *idle)
+{
+        int ret, hw_cpu;
+        pr_info("Booting CPU %d\n", cpu);
+        /*
+         * Write the address of secondary startup into the system-wide
+         * flags register. The boot monitor waits until it receives a
+         * soft interrupt, and then the secondary CPU branches to this
+         * address.
+         */
+        hw_cpu = cpu_logical_map(cpu);
+        if (of_machine_is_compatible("marvell,armada375")) {
+                u32 dev, rev;
+                if (mvebu_get_soc_id(&dev, &rev) == 0 &&
+                    rev == ARMADA_375_Z1_REV)
+                        armada_375_smp_cpu1_enable_wa();
+                mvebu_system_controller_set_cpu_boot_addr(mvebu_cortex_a9_secondary_startup);
+        }
+        else {
+                mvebu_pmsu_set_cpu_boot_addr(hw_cpu,
+                                             mvebu_cortex_a9_secondary_startup);
+        }
+        smp_wmb();
+        ret = mvebu_cpu_reset_deassert(hw_cpu);
+        if (ret) {
+                pr_err("Could not start the secondary CPU: %d\n", ret);
+                return ret;
+        }
+        arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+        return 0;
+}
+static struct smp_operations mvebu_cortex_a9_smp_ops __initdata = {
+        .smp_boot_secondary     = mvebu_cortex_a9_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = armada_xp_cpu_die,
+#endif
+};
+CPU_METHOD_OF_DECLARE(mvebu_armada_375_smp, "marvell,armada-375-smp",
+                      &mvebu_cortex_a9_smp_ops);
+CPU_METHOD_OF_DECLARE(mvebu_armada_380_smp, "marvell,armada-380-smp",
+                      &mvebu_cortex_a9_smp_ops);
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index a6da03f5b24e..88b976b31719 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -70,16 +70,19 @@ static void __init set_secondary_cpus_clock(void)
        }
 }
-static void armada_xp_secondary_init(unsigned int cpu)
-{
-        armada_xp_mpic_smp_cpu_init();
-}
 static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
+        int ret, hw_cpu;
        pr_info("Booting CPU %d\n", cpu);
-        armada_xp_boot_cpu(cpu, armada_xp_secondary_startup);
+        hw_cpu = cpu_logical_map(cpu);
+        mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
+        ret = mvebu_cpu_reset_deassert(hw_cpu);
+        if (ret) {
+                pr_warn("unable to boot CPU: %d\n", ret);
+                return ret;
+        }
        return 0;
 }
@@ -90,8 +93,6 @@ static void __init armada_xp_smp_init_cpus(void)
        if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
                panic("Invalid number of CPUs in DT\n");
-        set_smp_cross_call(armada_mpic_send_doorbell);
 }
 static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
@@ -102,7 +103,7 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
        set_secondary_cpus_clock();
        flush_cache_all();
-        set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
+        set_cpu_coherent();
        /*
         * In order to boot the secondary CPUs we need to ensure
@@ -124,9 +125,11 @@ static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations armada_xp_smp_ops __initdata = {
        .smp_init_cpus          = armada_xp_smp_init_cpus,
        .smp_prepare_cpus       = armada_xp_smp_prepare_cpus,
-        .smp_secondary_init     = armada_xp_secondary_init,
        .smp_boot_secondary     = armada_xp_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_die                = armada_xp_cpu_die,
 #endif
 };
+CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
+                      &armada_xp_smp_ops);
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index d71ef53107c4..53a55c8520bf 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c
@@ -16,62 +16,283 @@
 * other SOC units
 */
+#define pr_fmt(fmt) "mvebu-pmsu: " fmt
+#include <linux/cpu_pm.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/of_address.h>
 #include <linux/io.h>
+#include <linux/platform_device.h>
 #include <linux/smp.h>
+#include <linux/resource.h>
+#include <asm/cacheflush.h>
+#include <asm/cp15.h>
 #include <asm/smp_plat.h>
-#include "pmsu.h"
+#include <asm/suspend.h>
+#include <asm/tlbflush.h>
+#include "common.h"
 static void __iomem *pmsu_mp_base;
-static void __iomem *pmsu_reset_base;
-#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu)     ((cpu * 0x100) + 0x24)
+#define PMSU_BASE_OFFSET    0x100
-#define PMSU_RESET_CTL_OFFSET(cpu)              (cpu * 0x8)
+#define PMSU_REG_SIZE       0x1000
+/* PMSU MP registers */
+#define PMSU_CONTROL_AND_CONFIG(cpu)        ((cpu * 0x100) + 0x104)
+#define PMSU_CONTROL_AND_CONFIG_DFS_REQ         BIT(18)
+#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ       BIT(16)
+#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN        BIT(20)
+#define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)
+#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP      BIT(0)
+#define PMSU_STATUS_AND_MASK(cpu)           ((cpu * 0x100) + 0x10c)
+#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT      BIT(16)
+#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT   BIT(17)
+#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP         BIT(20)
+#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP         BIT(21)
+#define PMSU_STATUS_AND_MASK_DBG_WAKEUP         BIT(22)
+#define PMSU_STATUS_AND_MASK_IRQ_MASK           BIT(24)
+#define PMSU_STATUS_AND_MASK_FIQ_MASK           BIT(25)
+#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
+/* PMSU fabric registers */
+#define L2C_NFABRIC_PM_CTL                  0x4
+#define L2C_NFABRIC_PM_CTL_PWR_DOWN             BIT(20)
+extern void ll_disable_coherency(void);
+extern void ll_enable_coherency(void);
+static struct platform_device armada_xp_cpuidle_device = {
+        .name = "cpuidle-armada-370-xp",
+};
 static struct of_device_id of_pmsu_table[] = {
-        {.compatible = "marvell,armada-370-xp-pmsu"},
+        { .compatible = "marvell,armada-370-pmsu", },
+        { .compatible = "marvell,armada-370-xp-pmsu", },
+        { .compatible = "marvell,armada-380-pmsu", },
        { /* end of list */ },
 };
-#ifdef CONFIG_SMP
+void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
-int armada_xp_boot_cpu(unsigned int cpu_id, void *boot_addr)
 {
-        int reg, hw_cpu;
+        writel(virt_to_phys(boot_addr), pmsu_mp_base +
+                PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
+}
+static int __init armada_370_xp_pmsu_init(void)
+{
+        struct device_node *np;
+        struct resource res;
+        int ret = 0;
+        np = of_find_matching_node(NULL, of_pmsu_table);
+        if (!np)
+                return 0;
+        pr_info("Initializing Power Management Service Unit\n");
-        if (!pmsu_mp_base || !pmsu_reset_base) {
+        if (of_address_to_resource(np, 0, &res)) {
-                pr_warn("Can't boot CPU. PMSU is uninitialized\n");
+                pr_err("unable to get resource\n");
-                return 1;
+                ret = -ENOENT;
+                goto out;
        }
-        hw_cpu = cpu_logical_map(cpu_id);
+        if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
+                pr_warn(FW_WARN "deprecated pmsu binding\n");
+                res.start = res.start - PMSU_BASE_OFFSET;
+                res.end = res.start + PMSU_REG_SIZE - 1;
+        }
-        writel(virt_to_phys(boot_addr), pmsu_mp_base +
+        if (!request_mem_region(res.start, resource_size(&res),
-                        PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
+                                np->full_name)) {
+                pr_err("unable to request region\n");
+                ret = -EBUSY;
+                goto out;
+        }
+        pmsu_mp_base = ioremap(res.start, resource_size(&res));
+        if (!pmsu_mp_base) {
+                pr_err("unable to map registers\n");
+                release_mem_region(res.start, resource_size(&res));
+                ret = -ENOMEM;
+                goto out;
+        }
+ out:
+        of_node_put(np);
+        return ret;
+}
+static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void)
+{
+        u32 reg;
+        if (pmsu_mp_base == NULL)
+                return;
+        /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
+        reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
+        reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
+        writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
+}
+static void armada_370_xp_cpu_resume(void)
+{
+        asm volatile("bl    ll_add_cpu_to_smp_group\n\t"
+                     "bl    ll_enable_coherency\n\t"
+                     "b     cpu_resume\n\t");
+}
+/* No locking is needed because we only access per-CPU registers */
+void armada_370_xp_pmsu_idle_prepare(bool deepidle)
+{
+        unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
+        u32 reg;
+        if (pmsu_mp_base == NULL)
+                return;
-        /* Release CPU from reset by clearing reset bit*/
+        /*
-        reg = readl(pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+         * Adjust the PMSU configuration to wait for WFI signal, enable
-        reg &= (~0x1);
+         * IRQ and FIQ as wakeup events, set wait for snoop queue empty
-        writel(reg, pmsu_reset_base + PMSU_RESET_CTL_OFFSET(hw_cpu));
+         * indication and mask IRQ and FIQ from CPU
+         */
+        reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+        reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
+               PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
+               PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
+               PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
+               PMSU_STATUS_AND_MASK_IRQ_MASK         |
+               PMSU_STATUS_AND_MASK_FIQ_MASK;
+        writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+        reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+        /* ask HW to power down the L2 Cache if needed */
+        if (deepidle)
+                reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
+        /* request power down */
+        reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
+        writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+        /* Disable snoop disable by HW - SW is taking care of it */
+        reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+        reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
+        writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
+}
+static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
+{
+        armada_370_xp_pmsu_idle_prepare(deepidle);
+        v7_exit_coherency_flush(all);
+        ll_disable_coherency();
+        dsb();
+        wfi();
+        /* If we are here, wfi failed. As processors run out of
+         * coherency for some time, tlbs might be stale, so flush them
+         */
+        local_flush_tlb_all();
+        ll_enable_coherency();
+        /* Test the CR_C bit and set it if it was cleared */
+        asm volatile(
+        "mrc    p15, 0, %0, c1, c0, 0 \n\t"
+        "tst    %0, #(1 << 2) \n\t"
+        "orreq  %0, %0, #(1 << 2) \n\t"
+        "mcreq  p15, 0, %0, c1, c0, 0 \n\t"
+        "isb    "
+        : : "r" (0));
+        pr_warn("Failed to suspend the system\n");
        return 0;
 }
-#endif
-static int __init armada_370_xp_pmsu_init(void)
+static int armada_370_xp_cpu_suspend(unsigned long deepidle)
+{
+        return cpu_suspend(deepidle, do_armada_370_xp_cpu_suspend);
+}
+/* No locking is needed because we only access per-CPU registers */
+static noinline void armada_370_xp_pmsu_idle_restore(void)
+{
+        unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
+        u32 reg;
+        if (pmsu_mp_base == NULL)
+                return;
+        /* cancel ask HW to power down the L2 Cache if possible */
+        reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+        reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
+        writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
+        /* cancel Enable wakeup events and mask interrupts */
+        reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+        reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
+        reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
+        reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
+        reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
+        writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
+}
+static int armada_370_xp_cpu_pm_notify(struct notifier_block *self,
+                                    unsigned long action, void *hcpu)
+{
+        if (action == CPU_PM_ENTER) {
+                unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
+                mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_370_xp_cpu_resume);
+        } else if (action == CPU_PM_EXIT) {
+                armada_370_xp_pmsu_idle_restore();
+        }
+        return NOTIFY_OK;
+}
+static struct notifier_block armada_370_xp_cpu_pm_notifier = {
+        .notifier_call = armada_370_xp_cpu_pm_notify,
+};
+int __init armada_370_xp_cpu_pm_init(void)
 {
        struct device_node *np;
+        /*
+         * Check that all the requirements are available to enable
+         * cpuidle. So far, it is only supported on Armada XP, cpuidle
+         * needs the coherency fabric and the PMSU enabled
+         */
+        if (!of_machine_is_compatible("marvell,armadaxp"))
+                return 0;
+        np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
+        if (!np)
+                return 0;
+        of_node_put(np);
        np = of_find_matching_node(NULL, of_pmsu_table);
-        if (np) {
+        if (!np)
-                pr_info("Initializing Power Management Service Unit\n");
+                return 0;
-                pmsu_mp_base = of_iomap(np, 0);
+        of_node_put(np);
-                pmsu_reset_base = of_iomap(np, 1);
-                of_node_put(np);
+        armada_370_xp_pmsu_enable_l2_powerdown_onidle();
-        }
+        armada_xp_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
+        platform_device_register(&armada_xp_cpuidle_device);
+        cpu_pm_register_notifier(&armada_370_xp_cpu_pm_notifier);
        return 0;
 }
+arch_initcall(armada_370_xp_cpu_pm_init);
 early_initcall(armada_370_xp_pmsu_init);
diff --git a/arch/arm/mach-mvebu/system-controller.c b/arch/arm/mach-mvebu/system-controller.c
index 614ba6832ff3..0c5524ac75b7 100644
--- a/arch/arm/mach-mvebu/system-controller.c
+++ b/arch/arm/mach-mvebu/system-controller.c
@@ -37,6 +37,8 @@ struct mvebu_system_controller {
        u32 rstoutn_mask_reset_out_en;
        u32 system_soft_reset;
+        u32 resume_boot_addr;
 };
 static struct mvebu_system_controller *mvebu_sc;
@@ -52,6 +54,7 @@ static const struct mvebu_system_controller armada_375_system_controller = {
        .system_soft_reset_offset = 0x58,
        .rstoutn_mask_reset_out_en = 0x1,
        .system_soft_reset = 0x1,
+        .resume_boot_addr = 0xd4,
 };
 static const struct mvebu_system_controller orion_system_controller = {
@@ -98,6 +101,16 @@ void mvebu_restart(enum reboot_mode mode, const char *cmd)
                ;
 }
+#ifdef CONFIG_SMP
+void mvebu_system_controller_set_cpu_boot_addr(void *boot_addr)
+{
+        BUG_ON(system_controller_base == NULL);
+        BUG_ON(mvebu_sc->resume_boot_addr == 0);
+        writel(virt_to_phys(boot_addr), system_controller_base +
+               mvebu_sc->resume_boot_addr);
+}
+#endif
 static int __init mvebu_system_controller_init(void)
 {
        const struct of_device_id *match;
@@ -114,4 +127,4 @@ static int __init mvebu_system_controller_init(void)
        return 0;
 }
-arch_initcall(mvebu_system_controller_init);
+early_initcall(mvebu_system_controller_init);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 4a1065e41e9c..9116ca476d7c 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -143,23 +143,16 @@ static int __init cpu8815_mmcsd_init(void)
 }
 device_initcall(cpu8815_mmcsd_init);
-static void __init cpu8815_init_of(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-        /* At full speed latency must be >=2, so 0x249 in low bits */
-        l2x0_of_init(0x00730249, 0xfe000fff);
-#endif
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * cpu8815_board_compat[] = {
        "calaosystems,usb-s8815",
        NULL,
 };
 DT_MACHINE_START(NOMADIK_DT, "Nomadik STn8815")
+        /* At full speed latency must be >=2, so 0x249 in low bits */
+        .l2c_aux_val    = 0x00700249,
+        .l2c_aux_mask   = 0xfe0fefff,
        .map_io         = cpu8815_map_io,
-        .init_machine   = cpu8815_init_of,
        .restart        = cpu8815_restart,
        .dt_compat      = cpu8815_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 65d2acb31498..5b45d266d83e 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -346,7 +346,7 @@ static struct omap_usb_config h2_usb_config __initdata = {
        /* usb1 has a Mini-AB port and external isp1301 transceiver */
        .otg            = 2,
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
        .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
        /* .hmc_mode    = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
 #elif   defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 816ecd13f81e..bfed4f928663 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -366,7 +366,7 @@ static struct omap_usb_config h3_usb_config __initdata = {
        /* usb1 has a Mini-AB port and external isp1301 transceiver */
        .otg        = 2,
-#ifdef CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
        .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
 #elif  defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
        /* NONSTANDARD CABLE NEEDED (B-to-Mini-B) */
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index bd5f02e9c354..c49ce83cc1eb 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -312,7 +312,7 @@ static struct omap_usb_config h2_usb_config __initdata = {
        /* usb1 has a Mini-AB port and external isp1301 transceiver */
        .otg            = 2,
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
        .hmc_mode       = 19,   /* 0:host(off) 1:dev|otg 2:disabled */
        /* .hmc_mode    = 21,*/ /* 0:host(off) 1:dev(loopback) 2:host(loopback) */
 #elif   defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 3a0262156e93..7436d4cf6596 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -283,7 +283,7 @@ static struct omap_usb_config osk_usb_config __initdata = {
         * be used, with a NONSTANDARD gender-bending cable/dongle, as
         * a peripheral.
         */
-#ifdef  CONFIG_USB_GADGET_OMAP
+#if IS_ENABLED(CONFIG_USB_OMAP)
        .register_dev   = 1,
        .hmc_mode       = 0,
 #else
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0a8d3349149c..29e526235dc2 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -266,31 +266,6 @@ static struct physmap_flash_data sx1_flash_data = {
        .nr_parts       = ARRAY_SIZE(sx1_partitions),
 };
-#ifdef CONFIG_SX1_OLD_FLASH
-/* MTD Intel StrataFlash - old flashes */
-static struct resource sx1_old_flash_resource[] = {
-        [0] = {
-                .start  = OMAP_CS0_PHYS,        /* Physical */
-                .end    = OMAP_CS0_PHYS + SZ_16M - 1,,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = OMAP_CS1_PHYS,
-                .end    = OMAP_CS1_PHYS + SZ_8M - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-};
-static struct platform_device sx1_flash_device = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &sx1_flash_data,
-        },
-        .num_resources  = 2,
-        .resource       = &sx1_old_flash_resource,
-};
-#else
 /* MTD Intel 4000 flash - new flashes */
 static struct resource sx1_new_flash_resource = {
        .start          = OMAP_CS0_PHYS,
@@ -307,7 +282,6 @@ static struct platform_device sx1_flash_device = {
        .num_resources  = 1,
        .resource       = &sx1_new_flash_resource,
 };
-#endif
 /*----------- USB -------------------------*/
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index dbee729e3b6d..34b4c0044961 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -123,19 +123,8 @@ void omap1_pm_idle(void)
 #warning Enable 32kHz OS timer in order to allow sleep states in idle
        use_idlect1 = use_idlect1 & ~(1 << 9);
 #else
+        if (enable_dyn_sleep)
-        while (enable_dyn_sleep) {
-#ifdef CONFIG_CBUS_TAHVO_USB
-                extern int vbus_active;
-                /* Clock requirements? */
-                if (vbus_active)
-                        break;
-#endif
                do_sleep = 1;
-                break;
-        }
 #endif
 #ifdef CONFIG_OMAP_DM_TIMER
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index cb31d4390d52..0ba482638ebf 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -65,6 +65,7 @@ config SOC_AM43XX
        select ARCH_HAS_OPP
        select ARM_GIC
        select MACH_OMAP_GENERIC
+        select MIGHT_HAVE_CACHE_L2X0
 config SOC_DRA7XX
        bool "TI DRA7XX"
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 543d9a882de3..4f9383cecf76 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -262,12 +262,7 @@ static struct usbhs_phy_data phy_data[] __initdata = {
 static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
-#if defined(CONFIG_PANEL_SHARP_LQ043T1DG01) || \
-                defined(CONFIG_PANEL_SHARP_LQ043T1DG01_MODULE)
-        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
-#else
        .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
-#endif
 };
 #ifdef CONFIG_OMAP_MUX
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index ac82512b9c8c..e87f2a83d6bf 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -142,7 +142,7 @@ __init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs,
        board_nand_data.nr_parts        = nr_parts;
        board_nand_data.devsize         = nand_type;
-        board_nand_data.ecc_opt = OMAP_ECC_BCH8_CODE_HW;
+        board_nand_data.ecc_opt = OMAP_ECC_HAM1_CODE_HW;
        gpmc_nand_init(&board_nand_data, gpmc_t);
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -160,13 +160,13 @@ static u8 get_gpmc0_type(void)
        if (!fpga_map_addr)
                return -ENOMEM;
-        if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
+        if (!(readw_relaxed(fpga_map_addr + REG_FPGA_REV)))
                /* we dont have an DEBUG FPGA??? */
                /* Depend on #defines!! default to strata boot return param */
                goto unmap;
        /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
-        cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
+        cs = readw_relaxed(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
        /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
        if (omap_rev() >= OMAP3430_REV_ES1_0)
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b8920b6bc104..9480997ba616 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -43,7 +43,7 @@ static void __init omap_generic_init(void)
 }
 #ifdef CONFIG_SOC_OMAP2420
-static const char *omap242x_boards_compat[] __initdata = {
+static const char *omap242x_boards_compat[] __initconst = {
        "ti,omap2420",
        NULL,
 };
@@ -62,7 +62,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_SOC_OMAP2430
-static const char *omap243x_boards_compat[] __initdata = {
+static const char *omap243x_boards_compat[] __initconst = {
        "ti,omap2430",
        NULL,
 };
@@ -81,7 +81,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-static const char *omap3_boards_compat[] __initdata = {
+static const char *omap3_boards_compat[] __initconst = {
        "ti,omap3430",
        "ti,omap3",
        NULL,
@@ -100,7 +100,7 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
        .restart        = omap3xxx_restart,
 MACHINE_END
-static const char *omap36xx_boards_compat[] __initdata = {
+static const char *omap36xx_boards_compat[] __initconst = {
        "ti,omap36xx",
        NULL,
 };
@@ -118,7 +118,7 @@ DT_MACHINE_START(OMAP36XX_DT, "Generic OMAP36xx (Flattened Device Tree)")
        .restart        = omap3xxx_restart,
 MACHINE_END
-static const char *omap3_gp_boards_compat[] __initdata = {
+static const char *omap3_gp_boards_compat[] __initconst = {
        "ti,omap3-beagle",
        "timll,omap3-devkit8000",
        NULL,
@@ -137,7 +137,7 @@ DT_MACHINE_START(OMAP3_GP_DT, "Generic OMAP3-GP (Flattened Device Tree)")
        .restart        = omap3xxx_restart,
 MACHINE_END
-static const char *am3517_boards_compat[] __initdata = {
+static const char *am3517_boards_compat[] __initconst = {
        "ti,am3517",
        NULL,
 };
@@ -157,7 +157,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_SOC_AM33XX
-static const char *am33xx_boards_compat[] __initdata = {
+static const char *am33xx_boards_compat[] __initconst = {
        "ti,am33xx",
        NULL,
 };
@@ -177,7 +177,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_ARCH_OMAP4
-static const char *omap4_boards_compat[] __initdata = {
+static const char *omap4_boards_compat[] __initconst = {
        "ti,omap4460",
        "ti,omap4430",
        "ti,omap4",
@@ -199,7 +199,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_SOC_OMAP5
-static const char *omap5_boards_compat[] __initdata = {
+static const char *omap5_boards_compat[] __initconst = {
        "ti,omap5432",
        "ti,omap5430",
        "ti,omap5",
@@ -221,7 +221,7 @@ MACHINE_END
 #endif
 #ifdef CONFIG_SOC_AM43XX
-static const char *am43_boards_compat[] __initdata = {
+static const char *am43_boards_compat[] __initconst = {
        "ti,am4372",
        "ti,am43",
        NULL,
@@ -240,13 +240,13 @@ MACHINE_END
 #endif
 #ifdef CONFIG_SOC_DRA7XX
-static const char *dra7xx_boards_compat[] __initdata = {
+static const char *dra74x_boards_compat[] __initconst = {
-        "ti,dra7xx",
+        "ti,dra742",
        "ti,dra7",
        NULL,
 };
-DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
+DT_MACHINE_START(DRA74X_DT, "Generic DRA74X (Flattened Device Tree)")
        .reserve        = omap_reserve,
        .smp            = smp_ops(omap4_smp_ops),
        .map_io         = omap5_map_io,
@@ -255,7 +255,24 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
        .init_irq       = omap_gic_of_init,
        .init_machine   = omap_generic_init,
        .init_time      = omap5_realtime_timer_init,
-        .dt_compat      = dra7xx_boards_compat,
+        .dt_compat      = dra74x_boards_compat,
+        .restart        = omap44xx_restart,
+MACHINE_END
+static const char *dra72x_boards_compat[] __initconst = {
+        "ti,dra722",
+        NULL,
+};
+DT_MACHINE_START(DRA72X_DT, "Generic DRA72X (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = omap5_map_io,
+        .init_early     = dra7xx_init_early,
+        .init_late      = dra7xx_init_late,
+        .init_irq       = omap_gic_of_init,
+        .init_machine   = omap_generic_init,
+        .init_time      = omap5_realtime_timer_init,
+        .dt_compat      = dra72x_boards_compat,
        .restart        = omap44xx_restart,
 MACHINE_END
 #endif
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index d6ed819ff15c..660bfc5a70d7 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -33,7 +33,6 @@
 #include <linux/mtd/nand.h>
 #include <linux/mmc/host.h>
 #include <linux/usb/phy.h>
-#include <linux/usb/usb_phy_gen_xceiv.h>
 #include <linux/regulator/machine.h>
 #include <linux/i2c/twl.h>
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 119efaf5808a..a2e035e0792a 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -121,11 +121,7 @@ static struct platform_device omap3stalker_tfp410_device = {
 static struct connector_atv_platform_data omap3stalker_tv_pdata = {
        .name = "tv",
        .source = "venc.0",
-#if defined(CONFIG_OMAP2_VENC_OUT_TYPE_SVIDEO)
-        .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
-#elif defined(CONFIG_OMAP2_VENC_OUT_TYPE_COMPOSITE)
        .connector_type = OMAP_DSS_VENC_TYPE_COMPOSITE,
-#endif
        .invert_polarity = false,
 };
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 8f5121b89688..eb8c75ec3b1a 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -456,7 +456,8 @@ static struct clk_hw_omap dpll4_m5x2_ck_hw = {
        .clkdm_name     = "dpll4_clkdm",
 };
-DEFINE_STRUCT_CLK(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names, dpll4_m5x2_ck_ops);
+DEFINE_STRUCT_CLK_FLAGS(dpll4_m5x2_ck, dpll4_m5x2_ck_parent_names,
+                        dpll4_m5x2_ck_ops, CLK_SET_RATE_PARENT);
 static struct clk dpll4_m5x2_ck_3630 = {
        .name           = "dpll4_m5x2_ck",
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
index 3ff32543493c..59cf310bc1e9 100644
--- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
+++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c
@@ -138,7 +138,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *hw, unsigned long rate,
                if (!dd)
                        return -EINVAL;
-                tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg);
+                tmpset.cm_clksel1_pll = readl_relaxed(dd->mult_div1_reg);
                tmpset.cm_clksel1_pll &= ~(dd->mult_mask |
                                           dd->div1_mask);
                div = ((curr_prcm_set->xtal_speed / 1000000) - 1);
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index 19f54d433490..0717dff1bc04 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -39,9 +39,9 @@ int omap2_enable_osc_ck(struct clk_hw *clk)
 {
        u32 pcc;
-        pcc = __raw_readl(prcm_clksrc_ctrl);
+        pcc = readl_relaxed(prcm_clksrc_ctrl);
-        __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+        writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
        return 0;
 }
@@ -57,9 +57,9 @@ void omap2_disable_osc_ck(struct clk_hw *clk)
 {
        u32 pcc;
-        pcc = __raw_readl(prcm_clksrc_ctrl);
+        pcc = readl_relaxed(prcm_clksrc_ctrl);
-        __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
+        writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
 }
 unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
index f467d072cd02..58dd3a9b726c 100644
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ b/arch/arm/mach-omap2/clkt2xxx_sys.c
@@ -33,7 +33,7 @@ u32 omap2xxx_get_sysclkdiv(void)
 {
        u32 div;
-        div = __raw_readl(prcm_clksrc_ctrl);
+        div = readl_relaxed(prcm_clksrc_ctrl);
        div &= OMAP_SYSCLKDIV_MASK;
        div >>= OMAP_SYSCLKDIV_SHIFT;
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f17f00697cc0..82c37b1becc4 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -18,7 +18,6 @@
 #include "powerdomain.h"
 #include "clock.h"
-#include "omap_hwmod.h"
 /*
 * Clockdomain flags
@@ -98,6 +97,8 @@ struct clkdm_dep {
 /* Possible flags for struct clockdomain._flags */
 #define _CLKDM_FLAG_HWSUP_ENABLED               BIT(0)
+struct omap_hwmod;
 /**
 * struct clockdomain - OMAP clockdomain
 * @name: clockdomain name
diff --git a/arch/arm/mach-omap2/cm2xxx.c b/arch/arm/mach-omap2/cm2xxx.c
index ce25abbcffae..8be6ea50c092 100644
--- a/arch/arm/mach-omap2/cm2xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx.c
@@ -18,9 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
 #include "prm2xxx.h"
 #include "cm.h"
 #include "cm2xxx.h"
@@ -390,7 +387,7 @@ void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core, u32 mdm)
        tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) &
                OMAP24XX_CLKSEL_DSS2_MASK;
        omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1);
-        if (cpu_is_omap2430())
+        if (mdm)
                omap2_cm_write_mod_reg(mdm, OMAP2430_MDM_MOD, CM_CLKSEL);
 }
@@ -405,19 +402,11 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
 int __init omap2xxx_cm_init(void)
 {
-        if (!cpu_is_omap24xx())
-                return 0;
        return cm_register(&omap2xxx_cm_ll_data);
 }
 static void __exit omap2xxx_cm_exit(void)
 {
-        if (!cpu_is_omap24xx())
+        cm_unregister(&omap2xxx_cm_ll_data);
-                return;
-        /* Should never happen */
-        WARN(cm_unregister(&omap2xxx_cm_ll_data),
-             "%s: cm_ll_data function pointer mismatch\n", __func__);
 }
 __exitcall(omap2xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index bfbd16fe9151..72928a3ce2aa 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -52,12 +52,12 @@
 static inline u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
 {
-        return __raw_readl(cm_base + module + idx);
+        return readl_relaxed(cm_base + module + idx);
 }
 static inline void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-        __raw_writel(val, cm_base + module + idx);
+        writel_relaxed(val, cm_base + module + idx);
 }
 /* Read-modify-write a register in a CM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 40a22e5649ae..b3f99e93def0 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -50,13 +50,13 @@
 /* Read a register in a CM instance */
 static inline u32 am33xx_cm_read_reg(u16 inst, u16 idx)
 {
-        return __raw_readl(cm_base + inst + idx);
+        return readl_relaxed(cm_base + inst + idx);
 }
 /* Write into a register in a CM */
 static inline void am33xx_cm_write_reg(u32 val, u16 inst, u16 idx)
 {
-        __raw_writel(val, cm_base + inst + idx);
+        writel_relaxed(val, cm_base + inst + idx);
 }
 /* Read-modify-write a register in CM */
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index cfb8891b0c0e..15a778ce7707 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,11 +17,8 @@
 #ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
 #define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
-#include "common.h"
 #include "cm.h"
 #include "cm-regbits-33xx.h"
-#include "iomap.h"
 /* CM base address */
 #define AM33XX_CM_BASE          0x44e00000
diff --git a/arch/arm/mach-omap2/cm3xxx.c b/arch/arm/mach-omap2/cm3xxx.c
index f6f028867bfe..129a4e7f6ef5 100644
--- a/arch/arm/mach-omap2/cm3xxx.c
+++ b/arch/arm/mach-omap2/cm3xxx.c
@@ -18,9 +18,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "soc.h"
-#include "iomap.h"
-#include "common.h"
 #include "prm2xxx_3xxx.h"
 #include "cm.h"
 #include "cm3xxx.h"
@@ -388,7 +385,8 @@ void omap3_cm_save_context(void)
                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
        cm_context.iva2_cm_clksel2 =
                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
-        cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
+        cm_context.cm_sysconfig =
+                omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG);
        cm_context.sgx_cm_clksel =
                omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
        cm_context.dss_cm_clksel =
@@ -418,7 +416,8 @@ void omap3_cm_save_context(void)
                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
        cm_context.pll_cm_clken2 =
                omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
-        cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
+        cm_context.cm_polctrl =
+                omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL);
        cm_context.iva2_cm_fclken =
                omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
        cm_context.iva2_cm_clken_pll =
@@ -519,7 +518,8 @@ void omap3_cm_restore_context(void)
                               CM_CLKSEL1);
        omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
                               CM_CLKSEL2);
-        __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
+        omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD,
+                               OMAP3430_CM_SYSCONFIG);
        omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
                               CM_CLKSEL);
        omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
@@ -547,7 +547,8 @@ void omap3_cm_restore_context(void)
                               OMAP3430ES2_CM_CLKSEL5);
        omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD,
                               OMAP3430ES2_CM_CLKEN2);
-        __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
+        omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD,
+                               OMAP3430_CM_POLCTRL);
        omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
                               CM_FCLKEN);
        omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
@@ -669,19 +670,11 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
 int __init omap3xxx_cm_init(void)
 {
-        if (!cpu_is_omap34xx())
-                return 0;
        return cm_register(&omap3xxx_cm_ll_data);
 }
 static void __exit omap3xxx_cm_exit(void)
 {
-        if (!cpu_is_omap34xx())
+        cm_unregister(&omap3xxx_cm_ll_data);
-                return;
-        /* Should never happen */
-        WARN(cm_unregister(&omap3xxx_cm_ll_data),
-             "%s: cm_ll_data function pointer mismatch\n", __func__);
 }
 __exitcall(omap3xxx_cm_exit);
diff --git a/arch/arm/mach-omap2/cm3xxx.h b/arch/arm/mach-omap2/cm3xxx.h
index 8224c91b4d7a..7a16b5598127 100644
--- a/arch/arm/mach-omap2/cm3xxx.h
+++ b/arch/arm/mach-omap2/cm3xxx.h
@@ -29,9 +29,8 @@
 * These registers appear once per CM module.
 */
-#define OMAP3430_CM_REVISION            OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000)
+#define OMAP3430_CM_SYSCONFIG           0x0010
-#define OMAP3430_CM_SYSCONFIG           OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010)
+#define OMAP3430_CM_POLCTRL             0x009c
-#define OMAP3430_CM_POLCTRL             OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c)
 #define OMAP3_CM_CLKOUT_CTRL_OFFSET     0x0070
 #define OMAP3430_CM_CLKOUT_CTRL         OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070)
diff --git a/arch/arm/mach-omap2/cm44xx.c b/arch/arm/mach-omap2/cm44xx.c
index 535d66e2822c..fe5cc7bae489 100644
--- a/arch/arm/mach-omap2/cm44xx.c
+++ b/arch/arm/mach-omap2/cm44xx.c
@@ -18,35 +18,32 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "iomap.h"
-#include "common.h"
 #include "cm.h"
 #include "cm1_44xx.h"
 #include "cm2_44xx.h"
-#include "cm-regbits-44xx.h"
 /* CM1 hardware module low-level functions */
 /* Read a register in CM1 */
 u32 omap4_cm1_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_CM1_REGADDR(inst, reg));
+        return readl_relaxed(cm_base + inst + reg);
 }
 /* Write into a register in CM1 */
 void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_CM1_REGADDR(inst, reg));
+        writel_relaxed(val, cm_base + inst + reg);
 }
 /* Read a register in CM2 */
 u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg));
+        return readl_relaxed(cm2_base + inst + reg);
 }
 /* Write into a register in CM2 */
 void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_CM2_REGADDR(inst, reg));
+        writel_relaxed(val, cm2_base + inst + reg);
 }
diff --git a/arch/arm/mach-omap2/cm_common.c b/arch/arm/mach-omap2/cm_common.c
index 40b3b5a84458..8f6c4710877e 100644
--- a/arch/arm/mach-omap2/cm_common.c
+++ b/arch/arm/mach-omap2/cm_common.c
@@ -14,11 +14,11 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/errno.h>
+#include <linux/bug.h>
 #include "cm2xxx.h"
 #include "cm3xxx.h"
 #include "cm44xx.h"
-#include "common.h"
 /*
 * cm_ll_data: function pointers to SoC-specific implementations of
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index f5c4731b6f06..12aca56942c0 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -21,8 +21,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "iomap.h"
-#include "common.h"
 #include "clockdomain.h"
 #include "cm.h"
 #include "cm1_44xx.h"
@@ -30,12 +28,18 @@
 #include "cm44xx.h"
 #include "cminst44xx.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prcm44xx.h"
 #include "prm44xx.h"
 #include "prcm_mpu44xx.h"
 #include "prcm-common.h"
+#define OMAP4430_IDLEST_SHIFT           16
+#define OMAP4430_IDLEST_MASK            (0x3 << 16)
+#define OMAP4430_CLKTRCTRL_SHIFT        0
+#define OMAP4430_CLKTRCTRL_MASK         (0x3 << 0)
+#define OMAP4430_MODULEMODE_SHIFT       0
+#define OMAP4430_MODULEMODE_MASK        (0x3 << 0)
 /*
 * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
 *
@@ -116,7 +120,7 @@ u32 omap4_cminst_read_inst_reg(u8 part, u16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_cm_bases[part]);
-        return __raw_readl(_cm_bases[part] + inst + idx);
+        return readl_relaxed(_cm_bases[part] + inst + idx);
 }
 /* Write into a register in a CM instance */
@@ -125,7 +129,7 @@ void omap4_cminst_write_inst_reg(u32 val, u8 part, u16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_cm_bases[part]);
-        __raw_writel(val, _cm_bases[part] + inst + idx);
+        writel_relaxed(val, _cm_bases[part] + inst + idx);
 }
 /* Read-modify-write a register in CM1. Caller must lock */
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index d88aff7baff8..ff029737c8f0 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -91,6 +91,7 @@ extern void omap3_sync32k_timer_init(void);
 extern void omap3_secure_sync32k_timer_init(void);
 extern void omap3_gptimer_timer_init(void);
 extern void omap4_local_timer_init(void);
+int omap_l2_cache_init(void);
 extern void omap5_realtime_timer_init(void);
 void omap2420_init_early(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 44bb4d544dcf..751f3549bf6f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -151,32 +151,32 @@ void __iomem *omap_ctrl_base_get(void)
 u8 omap_ctrl_readb(u16 offset)
 {
-        return __raw_readb(OMAP_CTRL_REGADDR(offset));
+        return readb_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 u16 omap_ctrl_readw(u16 offset)
 {
-        return __raw_readw(OMAP_CTRL_REGADDR(offset));
+        return readw_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 u32 omap_ctrl_readl(u16 offset)
 {
-        return __raw_readl(OMAP_CTRL_REGADDR(offset));
+        return readl_relaxed(OMAP_CTRL_REGADDR(offset));
 }
 void omap_ctrl_writeb(u8 val, u16 offset)
 {
-        __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
+        writeb_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 void omap_ctrl_writew(u16 val, u16 offset)
 {
-        __raw_writew(val, OMAP_CTRL_REGADDR(offset));
+        writew_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 void omap_ctrl_writel(u32 val, u16 offset)
 {
-        __raw_writel(val, OMAP_CTRL_REGADDR(offset));
+        writel_relaxed(val, OMAP_CTRL_REGADDR(offset));
 }
 /*
@@ -188,12 +188,12 @@ void omap_ctrl_writel(u32 val, u16 offset)
 u32 omap4_ctrl_pad_readl(u16 offset)
 {
-        return __raw_readl(OMAP4_CTRL_PAD_REGADDR(offset));
+        return readl_relaxed(OMAP4_CTRL_PAD_REGADDR(offset));
 }
 void omap4_ctrl_pad_writel(u32 val, u16 offset)
 {
-        __raw_writel(val, OMAP4_CTRL_PAD_REGADDR(offset));
+        writel_relaxed(val, OMAP4_CTRL_PAD_REGADDR(offset));
 }
 #ifdef CONFIG_ARCH_OMAP3
@@ -222,7 +222,7 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
         *
         * XXX This should use some omap_ctrl_writel()-type function
         */
-        __raw_writel(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
+        writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4));
 }
 #endif
@@ -285,7 +285,7 @@ void omap3_clear_scratchpad_contents(void)
        if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
            OMAP3430_GLOBAL_COLD_RST_MASK) {
                for ( ; offset <= max_offset; offset += 0x4)
-                        __raw_writel(0x0, (v_addr + offset));
+                        writel_relaxed(0x0, (v_addr + offset));
                omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK,
                                           OMAP3430_GR_MOD,
                                           OMAP3_PRM_RSTST_OFFSET);
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 01fc710c8181..2498ab025fa2 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -14,6 +14,7 @@
 #include <linux/cpuidle.h>
 #include <linux/cpu_pm.h>
 #include <linux/export.h>
+#include <linux/clockchips.h>
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
@@ -83,6 +84,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
 {
        struct idle_statedata *cx = state_ptr + index;
        u32 mpuss_can_lose_context = 0;
+        int cpu_id = smp_processor_id();
        /*
         * CPU0 has to wait and stay ON until CPU1 is OFF state.
@@ -110,6 +112,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
        mpuss_can_lose_context = (cx->mpu_state == PWRDM_POWER_RET) &&
                                 (cx->mpu_logic_state == PWRDM_POWER_OFF);
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu_id);
        /*
         * Call idle CPU PM enter notifier chain so that
         * VFP and per CPU interrupt context is saved.
@@ -165,6 +169,8 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
        if (dev->cpu == 0 && mpuss_can_lose_context)
                cpu_cluster_pm_exit();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu_id);
 fail:
        cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
        cpu_done[dev->cpu] = false;
@@ -172,6 +178,16 @@ fail:
        return index;
 }
+/*
+ * For each cpu, setup the broadcast timer because local timers
+ * stops for the states above C1.
+ */
+static void omap_setup_broadcast_timer(void *arg)
+{
+        int cpu = smp_processor_id();
+        clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu);
+}
 static struct cpuidle_driver omap4_idle_driver = {
        .name                           = "omap4_idle",
        .owner                          = THIS_MODULE,
@@ -189,8 +205,7 @@ static struct cpuidle_driver omap4_idle_driver = {
                        /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
                        .exit_latency = 328 + 440,
                        .target_residency = 960,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
-                                 CPUIDLE_FLAG_TIMER_STOP,
                        .enter = omap_enter_idle_coupled,
                        .name = "C2",
                        .desc = "CPUx OFF, MPUSS CSWR",
@@ -199,8 +214,7 @@ static struct cpuidle_driver omap4_idle_driver = {
                        /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
                        .exit_latency = 460 + 518,
                        .target_residency = 1100,
-                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED |
+                        .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED,
-                                 CPUIDLE_FLAG_TIMER_STOP,
                        .enter = omap_enter_idle_coupled,
                        .name = "C3",
                        .desc = "CPUx OFF, MPUSS OSWR",
@@ -231,5 +245,8 @@ int __init omap4_idle_init(void)
        if (!cpu_clkdm[0] || !cpu_clkdm[1])
                return -ENODEV;
+        /* Configure the broadcast timer on each cpu */
+        on_each_cpu(omap_setup_broadcast_timer, NULL, 1);
        return cpuidle_register(&omap4_idle_driver, cpu_online_mask);
 }
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 16d33d831287..bf852d7ae951 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -279,6 +279,8 @@ static enum omapdss_version __init omap_display_get_version(void)
                return OMAPDSS_VER_OMAP4;
        else if (soc_is_omap54xx())
                return OMAPDSS_VER_OMAP5;
+        else if (soc_is_am43xx())
+                return OMAPDSS_VER_AM43xx;
        else
                return OMAPDSS_VER_UNKNOWN;
 }
@@ -555,65 +557,9 @@ int omap_dss_reset(struct omap_hwmod *oh)
        return r;
 }
-/* list of 'compatible' nodes to convert to omapdss specific */
-static const char * const dss_compat_conv_list[] __initconst = {
-        "composite-connector",
-        "dvi-connector",
-        "hdmi-connector",
-        "panel-dpi",
-        "panel-dsi-cm",
-        "sony,acx565akm",
-        "svideo-connector",
-        "ti,tfp410",
-        "ti,tpd12s015",
-};
-/* prepend compatible string with "omapdss," */
-static __init void omapdss_omapify_node(struct device_node *node,
-        const char *compat)
-{
-        char *new_compat;
-        struct property *prop;
-        new_compat = kasprintf(GFP_KERNEL, "omapdss,%s", compat);
-        prop = kzalloc(sizeof(*prop), GFP_KERNEL);
-        if (!prop) {
-                pr_err("omapdss_omapify_node: kzalloc failed\n");
-                return;
-        }
-        prop->name = "compatible";
-        prop->value = new_compat;
-        prop->length = strlen(new_compat) + 1;
-        of_update_property(node, prop);
-}
-/*
- * As omapdss panel drivers are omapdss specific, but we want to define the
- * DT-data in generic manner, we convert the compatible strings of the panel
- * nodes from "panel-foo" to "omapdss,panel-foo". This way we can have both
- * correct DT data and omapdss specific drivers.
- *
- * When we get generic panel drivers to the kernel, this will be removed.
- */
 void __init omapdss_early_init_of(void)
 {
-        int i;
-        for (i = 0; i < ARRAY_SIZE(dss_compat_conv_list); ++i) {
-                const char *compat = dss_compat_conv_list[i];
-                struct device_node *node = NULL;
-                while ((node = of_find_compatible_node(node, NULL, compat))) {
-                        if (!of_device_is_available(node))
-                                continue;
-                        omapdss_omapify_node(node, compat);
-                }
-        }
 }
 struct device_node * __init omapdss_find_dss_of_node(void)
@@ -632,6 +578,10 @@ struct device_node * __init omapdss_find_dss_of_node(void)
        if (node)
                return node;
+        node = of_find_compatible_node(NULL, NULL, "ti,omap5-dss");
+        if (node)
+                return node;
        return NULL;
 }
diff --git a/arch/arm/mach-omap2/dma.c b/arch/arm/mach-omap2/dma.c
index 5689c88d986d..a6d2cf1f8d02 100644
--- a/arch/arm/mach-omap2/dma.c
+++ b/arch/arm/mach-omap2/dma.c
@@ -91,7 +91,7 @@ static inline void dma_write(u32 val, int reg, int lch)
        addr += reg_map[reg].offset;
        addr += reg_map[reg].stride * lch;
-        __raw_writel(val, addr);
+        writel_relaxed(val, addr);
 }
 static inline u32 dma_read(int reg, int lch)
@@ -101,7 +101,7 @@ static inline u32 dma_read(int reg, int lch)
        addr += reg_map[reg].offset;
        addr += reg_map[reg].stride * lch;
-        return __raw_readl(addr);
+        return readl_relaxed(addr);
 }
 static void omap2_clear_dma(int lch)
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 4349e82debfe..17cd39360afe 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -46,7 +46,7 @@ static struct platform_device gpmc_nand_device = {
 static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt)
 {
        /* platforms which support all ECC schemes */
-        if (soc_is_am33xx() || cpu_is_omap44xx() ||
+        if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() ||
                 soc_is_omap54xx() || soc_is_dra7xx())
                return 1;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 9fe8c949305c..852b19a367f0 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -170,12 +170,12 @@ static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 static void gpmc_write_reg(int idx, u32 val)
 {
-        __raw_writel(val, gpmc_base + idx);
+        writel_relaxed(val, gpmc_base + idx);
 }
 static u32 gpmc_read_reg(int idx)
 {
-        return __raw_readl(gpmc_base + idx);
+        return readl_relaxed(gpmc_base + idx);
 }
 void gpmc_cs_write_reg(int cs, int idx, u32 val)
@@ -183,7 +183,7 @@ void gpmc_cs_write_reg(int cs, int idx, u32 val)
        void __iomem *reg_addr;
        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        __raw_writel(val, reg_addr);
+        writel_relaxed(val, reg_addr);
 }
 static u32 gpmc_cs_read_reg(int cs, int idx)
@@ -191,7 +191,7 @@ static u32 gpmc_cs_read_reg(int cs, int idx)
        void __iomem *reg_addr;
        reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
-        return __raw_readl(reg_addr);
+        return readl_relaxed(reg_addr);
 }
 /* TODO: Add support for gpmc_fck to clock framework and use it */
diff --git a/arch/arm/mach-omap2/hdq1w.c b/arch/arm/mach-omap2/hdq1w.c
index cbc8e3c480e0..f78b4a161959 100644
--- a/arch/arm/mach-omap2/hdq1w.c
+++ b/arch/arm/mach-omap2/hdq1w.c
@@ -76,6 +76,7 @@ int omap_hdq1w_reset(struct omap_hwmod *oh)
        return 0;
 }
+#ifndef CONFIG_OF
 static int __init omap_init_hdq(void)
 {
        int id = -1;
@@ -95,3 +96,4 @@ static int __init omap_init_hdq(void)
        return 0;
 }
 omap_arch_initcall(omap_init_hdq);
+#endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 157412e4273a..43969da5d50b 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -94,7 +94,7 @@ EXPORT_SYMBOL(omap_type);
 #define OMAP_TAP_DIE_ID_44XX_2  0x020c
 #define OMAP_TAP_DIE_ID_44XX_3  0x0210
-#define read_tap_reg(reg)       __raw_readl(tap_base  + (reg))
+#define read_tap_reg(reg)       readl_relaxed(tap_base  + (reg))
 struct omap_id {
        u16     hawkeye;        /* Silicon type (Hawkeye id) */
@@ -628,6 +628,41 @@ void __init omap5xxx_check_revision(void)
        pr_info("%s %s\n", soc_name, soc_rev);
 }
+void __init dra7xxx_check_revision(void)
+{
+        u32 idcode;
+        u16 hawkeye;
+        u8 rev;
+        idcode = read_tap_reg(OMAP_TAP_IDCODE);
+        hawkeye = (idcode >> 12) & 0xffff;
+        rev = (idcode >> 28) & 0xff;
+        switch (hawkeye) {
+        case 0xb990:
+                switch (rev) {
+                case 0:
+                        omap_revision = DRA752_REV_ES1_0;
+                        break;
+                case 1:
+                default:
+                        omap_revision = DRA752_REV_ES1_1;
+                }
+                break;
+        default:
+                /* Unknown default to latest silicon rev as default*/
+                pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%d)\n",
+                        __func__, idcode, hawkeye, rev);
+                omap_revision = DRA752_REV_ES1_1;
+        }
+        sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
+        sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
+                (omap_rev() >> 8) & 0xf);
+        pr_info("%s %s\n", soc_name, soc_rev);
+}
 /*
 * Set up things for map_io and processor detection later on. Gets called
 * pretty much first thing from board init. For multi-omap, this gets
@@ -669,6 +704,8 @@ static const char * __init omap_get_family(void)
                return kasprintf(GFP_KERNEL, "OMAP5");
        else if (soc_is_am43xx())
                return kasprintf(GFP_KERNEL, "AM43xx");
+        else if (soc_is_dra7xx())
+                return kasprintf(GFP_KERNEL, "DRA7");
        else
                return kasprintf(GFP_KERNEL, "Unknown");
 }
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index f14f9ac2dca1..8f559450c876 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -609,6 +609,7 @@ void __init am43xx_init_early(void)
        am43xx_clockdomains_init();
        am43xx_hwmod_init();
        omap_hwmod_init_postsetup();
+        omap_l2_cache_init();
        omap_clk_soc_init = am43xx_dt_clk_init;
 }
@@ -640,6 +641,7 @@ void __init omap4430_init_early(void)
        omap44xx_clockdomains_init();
        omap44xx_hwmod_init();
        omap_hwmod_init_postsetup();
+        omap_l2_cache_init();
        omap_clk_soc_init = omap4xxx_dt_clk_init;
 }
@@ -693,6 +695,7 @@ void __init dra7xx_init_early(void)
        omap_prm_base_init();
        omap_cm_base_init();
        omap44xx_prm_init();
+        dra7xxx_check_revision();
        dra7xx_powerdomains_init();
        dra7xx_clockdomains_init();
        dra7xx_hwmod_init();
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6037a9a01ed5..35b8590c322e 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -83,12 +83,12 @@ struct omap3_intc_regs {
 static void intc_bank_write_reg(u32 val, struct omap_irq_bank *bank, u16 reg)
 {
-        __raw_writel(val, bank->base_reg + reg);
+        writel_relaxed(val, bank->base_reg + reg);
 }
 static u32 intc_bank_read_reg(struct omap_irq_bank *bank, u16 reg)
 {
-        return __raw_readl(bank->base_reg + reg);
+        return readl_relaxed(bank->base_reg + reg);
 }
 /* XXX: FIQ and additional INTC support (only MPU at the moment) */
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 48094b58c88f..fd88edeb027f 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -70,18 +70,18 @@ struct omap_mux_partition *omap_mux_get(const char *name)
 u16 omap_mux_read(struct omap_mux_partition *partition, u16 reg)
 {
        if (partition->flags & OMAP_MUX_REG_8BIT)
-                return __raw_readb(partition->base + reg);
+                return readb_relaxed(partition->base + reg);
        else
-                return __raw_readw(partition->base + reg);
+                return readw_relaxed(partition->base + reg);
 }
 void omap_mux_write(struct omap_mux_partition *partition, u16 val,
                           u16 reg)
 {
        if (partition->flags & OMAP_MUX_REG_8BIT)
-                __raw_writeb(val, partition->base + reg);
+                writeb_relaxed(val, partition->base + reg);
        else
-                __raw_writew(val, partition->base + reg);
+                writew_relaxed(val, partition->base + reg);
 }
 void omap_mux_write_array(struct omap_mux_partition *partition,
diff --git a/arch/arm/mach-omap2/omap-headsmp.S b/arch/arm/mach-omap2/omap-headsmp.S
index 75e92952c18e..4993d4bfe9b2 100644
--- a/arch/arm/mach-omap2/omap-headsmp.S
+++ b/arch/arm/mach-omap2/omap-headsmp.S
@@ -1,7 +1,7 @@
 /*
 * Secondary CPU startup routine source file.
 *
- * Copyright (C) 2009 Texas Instruments, Inc.
+ * Copyright (C) 2009-2014 Texas Instruments, Inc.
 *
 * Author:
 *      Santosh Shilimkar <santosh.shilimkar@ti.com>
@@ -28,7 +28,7 @@
 * code.  This routine also provides a holding flag into which
 * secondary core is held until we're ready for it to initialise.
 * The primary core will update this flag using a hardware
-+ * register AuxCoreBoot0.
+ * register AuxCoreBoot0.
 */
 ENTRY(omap5_secondary_startup)
 wait:   ldr     r2, =AUX_CORE_BOOT0_PA  @ read from AuxCoreBoot0
@@ -39,7 +39,7 @@ wait:	ldr	r2, =AUX_CORE_BOOT0_PA	@ read from AuxCoreBoot0
        cmp     r0, r4
        bne     wait
        b       secondary_startup
-END(omap5_secondary_startup)
+ENDPROC(omap5_secondary_startup)
 /*
 * OMAP4 specific entry point for secondary CPU to jump from ROM
 * code.  This routine also provides a holding flag into which
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index 458f72f9dc8f..971791fe9a3f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -39,7 +39,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
                if (omap_modify_auxcoreboot0(0x0, 0x200) != 0x0)
                        pr_err("Secure clear status failed\n");
        } else {
-                __raw_writel(0, base + OMAP_AUX_CORE_BOOT_0);
+                writel_relaxed(0, base + OMAP_AUX_CORE_BOOT_0);
        }
@@ -53,7 +53,7 @@ void __ref omap4_cpu_die(unsigned int cpu)
                        boot_cpu = omap_read_auxcoreboot0();
                else
                        boot_cpu =
-                                __raw_readl(base + OMAP_AUX_CORE_BOOT_0) >> 5;
+                                readl_relaxed(base + OMAP_AUX_CORE_BOOT_0) >> 5;
                if (boot_cpu == smp_processor_id()) {
                        /*
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index 667915d236f3..4001325f90fb 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -116,7 +116,7 @@ static inline void set_cpu_wakeup_addr(unsigned int cpu_id, u32 addr)
 {
        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-        __raw_writel(addr, pm_info->wkup_sar_addr);
+        writel_relaxed(addr, pm_info->wkup_sar_addr);
 }
 /*
@@ -141,7 +141,7 @@ static void scu_pwrst_prepare(unsigned int cpu_id, unsigned int cpu_state)
                break;
        }
-        __raw_writel(scu_pwr_st, pm_info->scu_sar_addr);
+        writel_relaxed(scu_pwr_st, pm_info->scu_sar_addr);
 }
 /* Helper functions for MPUSS OSWR */
@@ -179,7 +179,7 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 {
        struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu_id);
-        __raw_writel(save_state, pm_info->l2x0_sar_addr);
+        writel_relaxed(save_state, pm_info->l2x0_sar_addr);
 }
 /*
@@ -187,19 +187,15 @@ static void l2x0_pwrst_prepare(unsigned int cpu_id, unsigned int save_state)
 * in every restore MPUSS OFF path.
 */
 #ifdef CONFIG_CACHE_L2X0
-static void save_l2x0_context(void)
+static void __init save_l2x0_context(void)
 {
-        u32 val;
+        writel_relaxed(l2x0_saved_regs.aux_ctrl,
-        void __iomem *l2x0_base = omap4_get_l2cache_base();
+                     sar_base + L2X0_AUXCTRL_OFFSET);
-        if (l2x0_base) {
+        writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                val = __raw_readl(l2x0_base + L2X0_AUX_CTRL);
+                     sar_base + L2X0_PREFETCH_CTRL_OFFSET);
-                __raw_writel(val, sar_base + L2X0_AUXCTRL_OFFSET);
-                val = __raw_readl(l2x0_base + L2X0_PREFETCH_CTRL);
-                __raw_writel(val, sar_base + L2X0_PREFETCH_CTRL_OFFSET);
-        }
 }
 #else
-static void save_l2x0_context(void)
+static void __init save_l2x0_context(void)
 {}
 #endif
@@ -386,9 +382,9 @@ int __init omap4_mpuss_init(void)
        /* Save device type on scratchpad for low level code to use */
        if (omap_type() != OMAP2_DEVICE_TYPE_GP)
-                __raw_writel(1, sar_base + OMAP_TYPE_OFFSET);
+                writel_relaxed(1, sar_base + OMAP_TYPE_OFFSET);
        else
-                __raw_writel(0, sar_base + OMAP_TYPE_OFFSET);
+                writel_relaxed(0, sar_base + OMAP_TYPE_OFFSET);
        save_l2x0_context();
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index 17550aa39d0f..256e84ef0f67 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -99,7 +99,7 @@ static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
        if (omap_secure_apis_support())
                omap_modify_auxcoreboot0(0x200, 0xfffffdff);
        else
-                __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
+                writel_relaxed(0x20, base + OMAP_AUX_CORE_BOOT_0);
        if (!cpu1_clkdm && !cpu1_pwrdm) {
                cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
@@ -227,8 +227,8 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
        if (omap_secure_apis_support())
                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
        else
-                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                writel_relaxed(virt_to_phys(omap5_secondary_startup),
-                                                base + OMAP_AUX_CORE_BOOT_1);
+                               base + OMAP_AUX_CORE_BOOT_1);
 }
diff --git a/arch/arm/mach-omap2/omap-wakeupgen.c b/arch/arm/mach-omap2/omap-wakeupgen.c
index 693fe486e917..37843a7d3639 100644
--- a/arch/arm/mach-omap2/omap-wakeupgen.c
+++ b/arch/arm/mach-omap2/omap-wakeupgen.c
@@ -60,19 +60,19 @@ static unsigned int omap_secure_apis;
 */
 static inline u32 wakeupgen_readl(u8 idx, u32 cpu)
 {
-        return __raw_readl(wakeupgen_base + OMAP_WKG_ENB_A_0 +
+        return readl_relaxed(wakeupgen_base + OMAP_WKG_ENB_A_0 +
                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
 }
 static inline void wakeupgen_writel(u32 val, u8 idx, u32 cpu)
 {
-        __raw_writel(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
+        writel_relaxed(val, wakeupgen_base + OMAP_WKG_ENB_A_0 +
                                (cpu * CPU_ENA_OFFSET) + (idx * 4));
 }
 static inline void sar_writel(u32 val, u32 offset, u8 idx)
 {
-        __raw_writel(val, sar_base + offset + (idx * 4));
+        writel_relaxed(val, sar_base + offset + (idx * 4));
 }
 static inline int _wakeupgen_get_irq_info(u32 irq, u32 *bit_posn, u8 *reg_index)
@@ -231,21 +231,21 @@ static inline void omap4_irq_save_context(void)
        }
        /* Save AuxBoot* registers */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + AUXCOREBOOT0_OFFSET);
+        writel_relaxed(val, sar_base + AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_1);
-        __raw_writel(val, sar_base + AUXCOREBOOT1_OFFSET);
+        writel_relaxed(val, sar_base + AUXCOREBOOT1_OFFSET);
        /* Save SyncReq generation logic */
-        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
+        val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_MASK);
-        __raw_writel(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
+        writel_relaxed(val, sar_base + PTMSYNCREQ_MASK_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
+        val = readl_relaxed(wakeupgen_base + OMAP_PTMSYNCREQ_EN);
-        __raw_writel(val, sar_base + PTMSYNCREQ_EN_OFFSET);
+        writel_relaxed(val, sar_base + PTMSYNCREQ_EN_OFFSET);
        /* Set the Backup Bit Mask status */
-        val = __raw_readl(sar_base + SAR_BACKUP_STATUS_OFFSET);
+        val = readl_relaxed(sar_base + SAR_BACKUP_STATUS_OFFSET);
        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
+        writel_relaxed(val, sar_base + SAR_BACKUP_STATUS_OFFSET);
 }
@@ -264,15 +264,15 @@ static inline void omap5_irq_save_context(void)
        }
        /* Save AuxBoot* registers */
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
+        writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT0_OFFSET);
-        val = __raw_readl(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
+        val = readl_relaxed(wakeupgen_base + OMAP_AUX_CORE_BOOT_0);
-        __raw_writel(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
+        writel_relaxed(val, sar_base + OMAP5_AUXCOREBOOT1_OFFSET);
        /* Set the Backup Bit Mask status */
-        val = __raw_readl(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        val = readl_relaxed(sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
        val |= SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
+        writel_relaxed(val, sar_base + OMAP5_SAR_BACKUP_STATUS_OFFSET);
 }
@@ -306,9 +306,9 @@ static void irq_sar_clear(void)
        if (soc_is_omap54xx())
                offset = OMAP5_SAR_BACKUP_STATUS_OFFSET;
-        val = __raw_readl(sar_base + offset);
+        val = readl_relaxed(sar_base + offset);
        val &= ~SAR_BACKUP_STATUS_WAKEUPGEN;
-        __raw_writel(val, sar_base + offset);
+        writel_relaxed(val, sar_base + offset);
 }
 /*
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 95e171a055f3..326cd982a3cb 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -125,25 +125,25 @@ void __init gic_init_irq(void)
 void gic_dist_disable(void)
 {
        if (gic_dist_base_addr)
-                __raw_writel(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
+                writel_relaxed(0x0, gic_dist_base_addr + GIC_DIST_CTRL);
 }
 void gic_dist_enable(void)
 {
        if (gic_dist_base_addr)
-                __raw_writel(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
+                writel_relaxed(0x1, gic_dist_base_addr + GIC_DIST_CTRL);
 }
 bool gic_dist_disabled(void)
 {
-        return !(__raw_readl(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
+        return !(readl_relaxed(gic_dist_base_addr + GIC_DIST_CTRL) & 0x1);
 }
 void gic_timer_retrigger(void)
 {
-        u32 twd_int = __raw_readl(twd_base + TWD_TIMER_INTSTAT);
+        u32 twd_int = readl_relaxed(twd_base + TWD_TIMER_INTSTAT);
-        u32 gic_int = __raw_readl(gic_dist_base_addr + GIC_DIST_PENDING_SET);
+        u32 gic_int = readl_relaxed(gic_dist_base_addr + GIC_DIST_PENDING_SET);
-        u32 twd_ctrl = __raw_readl(twd_base + TWD_TIMER_CONTROL);
+        u32 twd_ctrl = readl_relaxed(twd_base + TWD_TIMER_CONTROL);
        if (twd_int && !(gic_int & BIT(IRQ_LOCALTIMER))) {
                /*
@@ -151,11 +151,11 @@ void gic_timer_retrigger(void)
                 * disabled.  Ack the pending interrupt, and retrigger it.
                 */
                pr_warn("%s: lost localtimer interrupt\n", __func__);
-                __raw_writel(1, twd_base + TWD_TIMER_INTSTAT);
+                writel_relaxed(1, twd_base + TWD_TIMER_INTSTAT);
                if (!(twd_ctrl & TWD_TIMER_CONTROL_PERIODIC)) {
-                        __raw_writel(1, twd_base + TWD_TIMER_COUNTER);
+                        writel_relaxed(1, twd_base + TWD_TIMER_COUNTER);
                        twd_ctrl |= TWD_TIMER_CONTROL_ENABLE;
-                        __raw_writel(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
+                        writel_relaxed(twd_ctrl, twd_base + TWD_TIMER_CONTROL);
                }
        }
 }
@@ -167,75 +167,57 @@ void __iomem *omap4_get_l2cache_base(void)
        return l2cache_base;
 }
-static void omap4_l2x0_disable(void)
+static void omap4_l2c310_write_sec(unsigned long val, unsigned reg)
 {
-        outer_flush_all();
+        unsigned smc_op;
-        /* Disable PL310 L2 Cache controller */
-        omap_smc1(0x102, 0x0);
-}
-static void omap4_l2x0_set_debug(unsigned long val)
+        switch (reg) {
-{
+        case L2X0_CTRL:
-        /* Program PL310 L2 Cache controller debug register */
+                smc_op = OMAP4_MON_L2X0_CTRL_INDEX;
-        omap_smc1(0x100, val);
+                break;
+        case L2X0_AUX_CTRL:
+                smc_op = OMAP4_MON_L2X0_AUXCTRL_INDEX;
+                break;
+        case L2X0_DEBUG_CTRL:
+                smc_op = OMAP4_MON_L2X0_DBG_CTRL_INDEX;
+                break;
+        case L310_PREFETCH_CTRL:
+                smc_op = OMAP4_MON_L2X0_PREFETCH_INDEX;
+                break;
+        default:
+                WARN_ONCE(1, "OMAP L2C310: ignoring write to reg 0x%x\n", reg);
+                return;
+        }
+        omap_smc1(smc_op, val);
 }
-static int __init omap_l2_cache_init(void)
+int __init omap_l2_cache_init(void)
 {
-        u32 aux_ctrl = 0;
+        u32 aux_ctrl;
-        /*
-         * To avoid code running on other OMAPs in
-         * multi-omap builds
-         */
-        if (!cpu_is_omap44xx())
-                return -ENODEV;
        /* Static mapping, never released */
        l2cache_base = ioremap(OMAP44XX_L2CACHE_BASE, SZ_4K);
        if (WARN_ON(!l2cache_base))
                return -ENOMEM;
-        /*
+        /* 16-way associativity, parity disabled, way size - 64KB (es2.0 +) */
-         * 16-way associativity, parity disabled
+        aux_ctrl = L2C_AUX_CTRL_SHARED_OVERRIDE |
-         * Way size - 32KB (es1.0)
+                   L310_AUX_CTRL_DATA_PREFETCH |
-         * Way size - 64KB (es2.0 +)
+                   L310_AUX_CTRL_INSTR_PREFETCH;
-         */
-        aux_ctrl = ((1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT) |
-                        (0x1 << 25) |
-                        (0x1 << L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT) |
-                        (0x1 << L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT));
-        if (omap_rev() == OMAP4430_REV_ES1_0) {
-                aux_ctrl |= 0x2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT;
-        } else {
-                aux_ctrl |= ((0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
-                        (1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
-                        (1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
-                        (1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
-                        (1 << L2X0_AUX_CTRL_EARLY_BRESP_SHIFT));
-        }
-        if (omap_rev() != OMAP4430_REV_ES1_0)
-                omap_smc1(0x109, aux_ctrl);
-        /* Enable PL310 L2 Cache controller */
-        omap_smc1(0x102, 0x1);
+        outer_cache.write_sec = omap4_l2c310_write_sec;
        if (of_have_populated_dt())
-                l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
+                l2x0_of_init(aux_ctrl, 0xcf9fffff);
        else
-                l2x0_init(l2cache_base, aux_ctrl, L2X0_AUX_CTRL_MASK);
+                l2x0_init(l2cache_base, aux_ctrl, 0xcf9fffff);
-        /*
-         * Override default outer_cache.disable with a OMAP4
-         * specific one
-        */
-        outer_cache.disable = omap4_l2x0_disable;
-        outer_cache.set_debug = omap4_l2x0_set_debug;
        return 0;
 }
-omap_early_initcall(omap_l2_cache_init);
 #endif
 void __iomem *omap4_get_sar_ram_base(void)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 66c60fe1104c..f7bb435bb543 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -72,7 +72,7 @@
 *            | (../mach-omap2/omap_hwmod*)   |
 *            +-------------------------------+
 *            | OMAP clock/PRCM/register fns  |
- *            | (__raw_{read,write}l, clk*)   |
+ *            | ({read,write}l_relaxed, clk*) |
 *            +-------------------------------+
 *
 * Device drivers should not contain any OMAP-specific code or data in
@@ -3230,17 +3230,17 @@ static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh,
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
 {
        if (oh->flags & HWMOD_16BIT_REG)
-                return __raw_readw(oh->_mpu_rt_va + reg_offs);
+                return readw_relaxed(oh->_mpu_rt_va + reg_offs);
        else
-                return __raw_readl(oh->_mpu_rt_va + reg_offs);
+                return readl_relaxed(oh->_mpu_rt_va + reg_offs);
 }
 void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
 {
        if (oh->flags & HWMOD_16BIT_REG)
-                __raw_writew(v, oh->_mpu_rt_va + reg_offs);
+                writew_relaxed(v, oh->_mpu_rt_va + reg_offs);
        else
-                __raw_writel(v, oh->_mpu_rt_va + reg_offs);
+                writel_relaxed(v, oh->_mpu_rt_va + reg_offs);
 }
 /**
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
index 0f178623e7da..a579b89ce9b7 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c
@@ -24,6 +24,7 @@
 #include "prm33xx.h"
 #include "omap_hwmod_33xx_43xx_common_data.h"
 #include "prcm43xx.h"
+#include "common.h"
 #define CLKCTRL(oh, clkctrl) ((oh).prcm.omap4.clkctrl_offs = (clkctrl))
 #define RSTCTRL(oh, rstctrl) ((oh).prcm.omap4.rstctrl_offs = (rstctrl))
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 71ac7d5f3385..1cd0cfdc03e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3689,12 +3689,9 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
        .rev_offs       = 0x0000,
        .sysc_offs      = 0x0010,
        .syss_offs      = 0x0014,
-        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_MIDLEMODE |
-                           SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
-                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
-        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
-                           SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
-                           MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
        .sysc_fields    = &omap_hwmod_sysc_type1,
 };
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 1219280bb976..41e54f759934 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -3635,15 +3635,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_dmic_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> dmic (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_dmic_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* dsp -> iva */
@@ -4209,15 +4201,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp1_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> mcbsp1 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp1_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_abe -> mcbsp2 */
@@ -4225,15 +4209,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp2_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> mcbsp2 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp2_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_abe -> mcbsp3 */
@@ -4241,15 +4217,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcbsp3_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> mcbsp3 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcbsp3_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_per -> mcbsp4 */
@@ -4265,15 +4233,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_mcpdm_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> mcpdm (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_mcpdm_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_per -> mcspi1 */
@@ -4575,15 +4535,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer5_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> timer5 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer5_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_abe -> timer6 */
@@ -4591,15 +4543,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer6_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> timer6 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer6_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_abe -> timer7 */
@@ -4607,15 +4551,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer7_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> timer7 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer7_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_abe -> timer8 */
@@ -4623,15 +4559,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
        .master         = &omap44xx_l4_abe_hwmod,
        .slave          = &omap44xx_timer8_hwmod,
        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_MPU,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
-};
-/* l4_abe -> timer8 (dma) */
-static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
-        .master         = &omap44xx_l4_abe_hwmod,
-        .slave          = &omap44xx_timer8_hwmod,
-        .clk            = "ocp_abe_iclk",
-        .user           = OCP_USER_SDMA,
 };
 /* l4_per -> timer9 */
@@ -4831,7 +4759,6 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l3_instr__debugss,
        &omap44xx_l4_cfg__dma_system,
        &omap44xx_l4_abe__dmic,
-        &omap44xx_l4_abe__dmic_dma,
        &omap44xx_dsp__iva,
        /* &omap44xx_dsp__sl2if, */
        &omap44xx_l4_cfg__dsp,
@@ -4874,14 +4801,10 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_abe__mcasp,
        &omap44xx_l4_abe__mcasp_dma,
        &omap44xx_l4_abe__mcbsp1,
-        &omap44xx_l4_abe__mcbsp1_dma,
        &omap44xx_l4_abe__mcbsp2,
-        &omap44xx_l4_abe__mcbsp2_dma,
        &omap44xx_l4_abe__mcbsp3,
-        &omap44xx_l4_abe__mcbsp3_dma,
        &omap44xx_l4_per__mcbsp4,
        &omap44xx_l4_abe__mcpdm,
-        &omap44xx_l4_abe__mcpdm_dma,
        &omap44xx_l4_per__mcspi1,
        &omap44xx_l4_per__mcspi2,
        &omap44xx_l4_per__mcspi3,
@@ -4913,13 +4836,9 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
        &omap44xx_l4_per__timer3,
        &omap44xx_l4_per__timer4,
        &omap44xx_l4_abe__timer5,
-        &omap44xx_l4_abe__timer5_dma,
        &omap44xx_l4_abe__timer6,
-        &omap44xx_l4_abe__timer6_dma,
        &omap44xx_l4_abe__timer7,
-        &omap44xx_l4_abe__timer7_dma,
        &omap44xx_l4_abe__timer8,
-        &omap44xx_l4_abe__timer8_dma,
        &omap44xx_l4_per__timer9,
        &omap44xx_l4_per__timer10,
        &omap44xx_l4_per__timer11,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 892317294fdc..290213f2cbe3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -334,6 +334,235 @@ static struct omap_hwmod omap54xx_dmic_hwmod = {
 };
 /*
+ * 'dss' class
+ * display sub-system
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_dss_sysc = {
+        .rev_offs       = 0x0000,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = SYSS_HAS_RESET_STATUS,
+};
+static struct omap_hwmod_class omap54xx_dss_hwmod_class = {
+        .name   = "dss",
+        .sysc   = &omap54xx_dss_sysc,
+        .reset  = omap_dss_reset,
+};
+/* dss */
+static struct omap_hwmod_opt_clk dss_opt_clks[] = {
+        { .role = "32khz_clk", .clk = "dss_32khz_clk" },
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+        { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
+};
+static struct omap_hwmod omap54xx_dss_hwmod = {
+        .name           = "dss_core",
+        .class          = &omap54xx_dss_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .context_offs = OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_SWCTRL,
+                },
+        },
+        .opt_clks       = dss_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_opt_clks),
+};
+/*
+ * 'dispc' class
+ * display controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_dispc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+                           SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_dispc_hwmod_class = {
+        .name   = "dispc",
+        .sysc   = &omap54xx_dispc_sysc,
+};
+/* dss_dispc */
+static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+/* dss_dispc dev_attr */
+static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
+        .has_framedonetv_irq    = 1,
+        .manager_count          = 4,
+};
+static struct omap_hwmod omap54xx_dss_dispc_hwmod = {
+        .name           = "dss_dispc",
+        .class          = &omap54xx_dispc_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_dispc_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dispc_opt_clks),
+        .dev_attr       = &dss_dispc_dev_attr,
+};
+/*
+ * 'dsi1' class
+ * display serial interface controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_dsi1_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_dsi1_hwmod_class = {
+        .name   = "dsi1",
+        .sysc   = &omap54xx_dsi1_sysc,
+};
+/* dss_dsi1_a */
+static struct omap_hwmod_opt_clk dss_dsi1_a_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+static struct omap_hwmod omap54xx_dss_dsi1_a_hwmod = {
+        .name           = "dss_dsi1",
+        .class          = &omap54xx_dsi1_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_dsi1_a_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_a_opt_clks),
+};
+/* dss_dsi1_c */
+static struct omap_hwmod_opt_clk dss_dsi1_c_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+static struct omap_hwmod omap54xx_dss_dsi1_c_hwmod = {
+        .name           = "dss_dsi2",
+        .class          = &omap54xx_dsi1_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_dss_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_dsi1_c_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_dsi1_c_opt_clks),
+};
+/*
+ * 'hdmi' class
+ * hdmi controller
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_hdmi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+                           SIDLE_SMART_WKUP),
+        .sysc_fields    = &omap_hwmod_sysc_type2,
+};
+static struct omap_hwmod_class omap54xx_hdmi_hwmod_class = {
+        .name   = "hdmi",
+        .sysc   = &omap54xx_hdmi_sysc,
+};
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+        { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+static struct omap_hwmod omap54xx_dss_hdmi_hwmod = {
+        .name           = "dss_hdmi",
+        .class          = &omap54xx_hdmi_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .main_clk       = "dss_48mhz_clk",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_hdmi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_hdmi_opt_clks),
+};
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+static struct omap_hwmod_class_sysconfig omap54xx_rfbi_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+static struct omap_hwmod_class omap54xx_rfbi_hwmod_class = {
+        .name   = "rfbi",
+        .sysc   = &omap54xx_rfbi_sysc,
+};
+/* dss_rfbi */
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+        { .role = "ick", .clk = "l3_iclk_div" },
+};
+static struct omap_hwmod omap54xx_dss_rfbi_hwmod = {
+        .name           = "dss_rfbi",
+        .class          = &omap54xx_rfbi_hwmod_class,
+        .clkdm_name     = "dss_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET,
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
+        .opt_clks       = dss_rfbi_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(dss_rfbi_opt_clks),
+};
+/*
 * 'emif' class
 * external memory interface no1 (wrapper)
 */
@@ -895,7 +1124,7 @@ static struct omap_hwmod omap54xx_mcpdm_hwmod = {
         * current exception.
         */
-        .flags          = HWMOD_EXT_OPT_MAIN_CLK,
+        .flags          = HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
        .main_clk       = "pad_clks_ck",
        .prcm = {
                .omap4 = {
@@ -1974,6 +2203,54 @@ static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
        .user           = OCP_USER_MPU,
 };
+/* l3_main_2 -> dss */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> dss_dispc */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dispc = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_dispc_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> dss_dsi1_a */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_a = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_dsi1_a_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> dss_dsi1_c */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_dsi1_c = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_dsi1_c_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> dss_hdmi */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_hdmi = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_hdmi_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+/* l3_main_2 -> dss_rfbi */
+static struct omap_hwmod_ocp_if omap54xx_l3_main_2__dss_rfbi = {
+        .master         = &omap54xx_l3_main_2_hwmod,
+        .slave          = &omap54xx_dss_rfbi_hwmod,
+        .clk            = "l3_iclk_div",
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
 /* mpu -> emif1 */
 static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
        .master         = &omap54xx_mpu_hwmod,
@@ -2427,6 +2704,12 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
        &omap54xx_l4_cfg__dma_system,
        &omap54xx_l4_abe__dmic,
        &omap54xx_l4_cfg__mmu_dsp,
+        &omap54xx_l3_main_2__dss,
+        &omap54xx_l3_main_2__dss_dispc,
+        &omap54xx_l3_main_2__dss_dsi1_a,
+        &omap54xx_l3_main_2__dss_dsi1_c,
+        &omap54xx_l3_main_2__dss_hdmi,
+        &omap54xx_l3_main_2__dss_rfbi,
        &omap54xx_mpu__emif1,
        &omap54xx_mpu__emif2,
        &omap54xx_l4_wkup__gpio1,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index 810c205d668b..20b4398cec05 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -2318,21 +2318,11 @@ static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
-static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
-        {
-                .pa_start       = 0x4a080000,
-                .pa_end         = 0x4a08001f,
-                .flags          = ADDR_TYPE_RT
-        },
-        { }
-};
 /* l4_cfg -> ocp2scp1 */
 static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
        .master         = &dra7xx_l4_cfg_hwmod,
        .slave          = &dra7xx_ocp2scp1_hwmod,
        .clk            = "l4_root_clk_div",
-        .addr           = dra7xx_ocp2scp1_addrs,
        .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
diff --git a/arch/arm/mach-omap2/omap_phy_internal.c b/arch/arm/mach-omap2/omap_phy_internal.c
index eb8a25de67ed..50640b38f0bf 100644
--- a/arch/arm/mach-omap2/omap_phy_internal.c
+++ b/arch/arm/mach-omap2/omap_phy_internal.c
@@ -57,7 +57,7 @@ static int __init omap4430_phy_power_down(void)
        }
        /* Power down the phy */
-        __raw_writel(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
+        writel_relaxed(PHY_PD, ctrl_base + CONTROL_DEV_CONF);
        iounmap(ctrl_base);
@@ -162,7 +162,7 @@ void ti81xx_musb_phy_power(u8 on)
                return;
        }
-        usbphycfg = __raw_readl(scm_base + USBCTRL0);
+        usbphycfg = readl_relaxed(scm_base + USBCTRL0);
        if (on) {
                if (cpu_is_ti816x()) {
@@ -181,7 +181,7 @@ void ti81xx_musb_phy_power(u8 on)
                        usbphycfg |= USBPHY_CM_PWRDN | USBPHY_OTG_PWRDN;
        }
-        __raw_writel(usbphycfg, scm_base + USBCTRL0);
+        writel_relaxed(usbphycfg, scm_base + USBCTRL0);
        iounmap(scm_base);
 }
diff --git a/arch/arm/mach-omap2/omap_twl.c b/arch/arm/mach-omap2/omap_twl.c
index 615e5b1fb025..6bf626700557 100644
--- a/arch/arm/mach-omap2/omap_twl.c
+++ b/arch/arm/mach-omap2/omap_twl.c
@@ -46,15 +46,8 @@
 static bool is_offset_valid;
 static u8 smps_offset;
-/*
- * Flag to ensure Smartreflex bit in TWL
- * being cleared in board file is not overwritten.
- */
-static bool __initdata twl_sr_enable_autoinit;
-#define TWL4030_DCDC_GLOBAL_CFG        0x06
 #define REG_SMPS_OFFSET         0xE0
-#define SMARTREFLEX_ENABLE     BIT(3)
 static unsigned long twl4030_vsel_to_uv(const u8 vsel)
 {
@@ -251,18 +244,6 @@ int __init omap3_twl_init(void)
        if (!cpu_is_omap34xx())
                return -ENODEV;
-        /*
-         * The smartreflex bit on twl4030 specifies if the setting of voltage
-         * is done over the I2C_SR path. Since this setting is independent of
-         * the actual usage of smartreflex AVS module, we enable TWL SR bit
-         * by default irrespective of whether smartreflex AVS module is enabled
-         * on the OMAP side or not. This is because without this bit enabled,
-         * the voltage scaling through vp forceupdate/bypass mechanism of
-         * voltage scaling will not function on TWL over I2C_SR.
-         */
-        if (!twl_sr_enable_autoinit)
-                omap3_twl_set_sr_bit(true);
        voltdm = voltdm_lookup("mpu_iva");
        omap_voltage_register_pmic(voltdm, &omap3_mpu_pmic);
@@ -271,44 +252,3 @@ int __init omap3_twl_init(void)
        return 0;
 }
-/**
- * omap3_twl_set_sr_bit() - Set/Clear SR bit on TWL
- * @enable: enable SR mode in twl or not
- *
- * If 'enable' is true, enables Smartreflex bit on TWL 4030 to make sure
- * voltage scaling through OMAP SR works. Else, the smartreflex bit
- * on twl4030 is cleared as there are platforms which use OMAP3 and T2 but
- * use Synchronized Scaling Hardware Strategy (ENABLE_VMODE=1) and Direct
- * Strategy Software Scaling Mode (ENABLE_VMODE=0), for setting the voltages,
- * in those scenarios this bit is to be cleared (enable = false).
- *
- * Returns 0 on success, error is returned if I2C read/write fails.
- */
-int __init omap3_twl_set_sr_bit(bool enable)
-{
-        u8 temp;
-        int ret;
-        if (twl_sr_enable_autoinit)
-                pr_warning("%s: unexpected multiple calls\n", __func__);
-        ret = twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &temp,
-                              TWL4030_DCDC_GLOBAL_CFG);
-        if (ret)
-                goto err;
-        if (enable)
-                temp |= SMARTREFLEX_ENABLE;
-        else
-                temp &= ~SMARTREFLEX_ENABLE;
-        ret = twl_i2c_write_u8(TWL_MODULE_PM_RECEIVER, temp,
-                               TWL4030_DCDC_GLOBAL_CFG);
-        if (!ret) {
-                twl_sr_enable_autoinit = true;
-                return 0;
-        }
-err:
-        pr_err("%s: Error access to TWL4030 (%d)\n", __func__, ret);
-        return ret;
-}
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index c3b73351cb7a..90c88d498485 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -226,6 +226,14 @@ static void __init am3517_evm_legacy_init(void)
        am35xx_emac_reset();
 }
+static struct platform_device omap3_rom_rng_device = {
+        .name           = "omap3-rom-rng",
+        .id             = -1,
+        .dev    = {
+                .platform_data  = rx51_secure_rng_call,
+        },
+};
 static void __init nokia_n900_legacy_init(void)
 {
        hsmmc2_internal_input_clk();
@@ -239,6 +247,10 @@ static void __init nokia_n900_legacy_init(void)
                        pr_warning("RX-51: Not enabling ARM errata 430973 workaround\n");
                        pr_warning("Thumb binaries may crash randomly without this workaround\n");
                }
+                pr_info("RX-51: Registring OMAP3 HWRNG device\n");
+                platform_device_register(&omap3_rom_rng_device);
        }
 }
 #endif /* CONFIG_ARCH_OMAP3 */
@@ -254,6 +266,11 @@ static void __init omap4_panda_legacy_init(void)
 {
        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 53);
 }
+static void __init var_som_om44_legacy_init(void)
+{
+        legacy_init_wl12xx(WL12XX_REFCLOCK_38, 0, 41);
+}
 #endif
 #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
@@ -364,6 +381,8 @@ static struct pdata_init pdata_quirks[] __initdata = {
 #ifdef CONFIG_ARCH_OMAP4
        { "ti,omap4-sdp", omap4_sdp_legacy_init, },
        { "ti,omap4-panda", omap4_panda_legacy_init, },
+        { "variscite,var-dvk-om44", var_som_om44_legacy_init, },
+        { "variscite,var-stk-om44", var_som_om44_legacy_init, },
 #endif
 #ifdef CONFIG_SOC_AM33XX
        { "ti,am335x-evmsk", am335x_evmsk_legacy_init, },
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index e1b41416fbf1..828aee9ea6a8 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -32,11 +32,13 @@
 #include "pm.h"
 #include "twl-common.h"
+#ifdef CONFIG_SUSPEND
 /*
 * omap_pm_suspend: points to a function that does the SoC-specific
 * suspend work
 */
-int (*omap_pm_suspend)(void);
+static int (*omap_pm_suspend)(void);
+#endif
 #ifdef CONFIG_PM
 /**
@@ -243,6 +245,15 @@ static const struct platform_suspend_ops omap_pm_ops = {
        .valid          = suspend_valid_only_mem,
 };
+/**
+ * omap_common_suspend_init - Set common suspend routines for OMAP SoCs
+ * @pm_suspend: function pointer to SoC specific suspend function
+ */
+void omap_common_suspend_init(void *pm_suspend)
+{
+        omap_pm_suspend = pm_suspend;
+        suspend_set_ops(&omap_pm_ops);
+}
 #endif /* CONFIG_SUSPEND */
 static void __init omap3_init_voltages(void)
@@ -287,32 +298,24 @@ omap_postcore_initcall(omap2_common_pm_init);
 int __init omap2_common_pm_late_init(void)
 {
-        /*
+        if (of_have_populated_dt()) {
-         * In the case of DT, the PMIC and SR initialization will be done using
+                omap3_twl_init();
-         * a completely different mechanism.
+                omap4_twl_init();
-         * Disable this part if a DT blob is available.
+        }
-         */
-        if (!of_have_populated_dt()) {
-                /* Init the voltage layer */
-                omap_pmic_late_init();
-                omap_voltage_late_init();
-                /* Initialize the voltages */
+        /* Init the voltage layer */
-                omap3_init_voltages();
+        omap_pmic_late_init();
-                omap4_init_voltages();
+        omap_voltage_late_init();
-                /* Smartreflex device init */
+        /* Initialize the voltages */
-                omap_devinit_smartreflex();
+        omap3_init_voltages();
+        omap4_init_voltages();
-        }
+        /* Smartreflex device init */
+        omap_devinit_smartreflex();
        /* cpufreq dummy device instantiation */
        omap_init_cpufreq();
-#ifdef CONFIG_SUSPEND
-        suspend_set_ops(&omap_pm_ops);
-#endif
        return 0;
 }
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index d4d0fce325c7..e150102d6c06 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -34,7 +34,6 @@ extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
-extern int (*omap_pm_suspend)(void);
 #if defined(CONFIG_PM_OPP)
 extern int omap3_opp_init(void);
@@ -147,4 +146,11 @@ static inline void omap_pm_get_oscillator(u32 *tstart, u32 *tshut) { *tstart = *
 static inline void omap_pm_setup_sr_i2c_pcb_length(u32 mm) { }
 #endif
+#ifdef CONFIG_SUSPEND
+void omap_common_suspend_init(void *pm_suspend);
+#else
+static inline void omap_common_suspend_init(void *pm_suspend)
+{
+}
+#endif /* CONFIG_SUSPEND */
 #endif
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index 8c0759496c8d..a5ea988ff340 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -229,9 +229,7 @@ static void __init prcm_setup_regs(void)
        clkdm_for_each(omap_pm_clkdms_setup, NULL);
        clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
-#ifdef CONFIG_SUSPEND
+        omap_common_suspend_init(omap2_enter_full_retention);
-        omap_pm_suspend = omap2_enter_full_retention;
-#endif
        /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
         * stabilisation */
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 87099bb6de69..507d8eeaab95 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -50,6 +50,7 @@
 #include "sdrc.h"
 #include "sram.h"
 #include "control.h"
+#include "vc.h"
 /* pm34xx errata defined in pm.h */
 u16 pm34xx_errata;
@@ -288,6 +289,9 @@ void omap_sram_idle(void)
                }
        }
+        /* Configure PMIC signaling for I2C4 or sys_off_mode */
+        omap3_vc_set_pmic_signaling(core_next_state);
        omap3_intc_prepare_idle();
        /*
@@ -391,7 +395,8 @@ restore:
        return ret;
 }
+#else
+#define omap3_pm_suspend NULL
 #endif /* CONFIG_SUSPEND */
@@ -705,9 +710,7 @@ int __init omap3_pm_init(void)
        per_clkdm = clkdm_lookup("per_clkdm");
        wkup_clkdm = clkdm_lookup("wkup_clkdm");
-#ifdef CONFIG_SUSPEND
+        omap_common_suspend_init(omap3_pm_suspend);
-        omap_pm_suspend = omap3_pm_suspend;
-#endif
        arm_pm_idle = omap3_pm_idle;
        omap3_idle_init();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index eefb30cfcabd..0dda6cf8b855 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -96,6 +96,8 @@ static int omap4_pm_suspend(void)
        return 0;
 }
+#else
+#define omap4_pm_suspend NULL
 #endif /* CONFIG_SUSPEND */
 static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
@@ -251,9 +253,7 @@ int __init omap4_pm_init(void)
        (void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
-#ifdef CONFIG_SUSPEND
+        omap_common_suspend_init(omap4_pm_suspend);
-        omap_pm_suspend = omap4_pm_suspend;
-#endif
        /* Overwrite the default cpu_do_idle() */
        arm_pm_idle = omap_default_idle;
diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c
index c0aeabfcf009..c40e5f009826 100644
--- a/arch/arm/mach-omap2/powerdomain-common.c
+++ b/arch/arm/mach-omap2/powerdomain-common.c
@@ -17,7 +17,6 @@
 #include "pm.h"
 #include "cm.h"
 #include "cm-regbits-34xx.h"
-#include "cm-regbits-44xx.h"
 #include "prm-regbits-34xx.h"
 #include "prm-regbits-44xx.h"
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 93a2a6e4260f..faebd5f076af 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -32,6 +32,7 @@
 #include "powerdomain.h"
 #include "clockdomain.h"
+#include "voltage.h"
 #include "soc.h"
 #include "pm.h"
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index da5a59ae77b6..f4727117f6cc 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -21,8 +21,6 @@
 #include <linux/list.h>
 #include <linux/spinlock.h>
-#include "voltage.h"
 /* Powerdomain basic power states */
 #define PWRDM_POWER_OFF         0x0
 #define PWRDM_POWER_RET         0x1
@@ -75,6 +73,7 @@
 struct clockdomain;
 struct powerdomain;
+struct voltagedomain;
 /**
 * struct powerdomain - OMAP powerdomain
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 0e841fd9498a..a8e4b582c527 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -428,6 +428,28 @@
 #define MAX_IOPAD_LATCH_TIME                    100
 # ifndef __ASSEMBLER__
+#include <linux/delay.h>
+/**
+ * omap_test_timeout - busy-loop, testing a condition
+ * @cond: condition to test until it evaluates to true
+ * @timeout: maximum number of microseconds in the timeout
+ * @index: loop index (integer)
+ *
+ * Loop waiting for @cond to become true or until at least @timeout
+ * microseconds have passed.  To use, define some integer @index in the
+ * calling code.  After running, if @index == @timeout, then the loop has
+ * timed out.
+ */
+#define omap_test_timeout(cond, timeout, index)                 \
+({                                                              \
+        for (index = 0; index < timeout; index++) {             \
+                if (cond)                                       \
+                        break;                                  \
+                udelay(1);                                      \
+        }                                                       \
+})
 /**
 * struct omap_prcm_irq - describes a PRCM interrupt bit
 * @name: a short name describing the interrupt type, e.g. "wkup" or "io"
@@ -458,6 +480,7 @@ struct omap_prcm_irq {
 * @ocp_barrier: fn ptr to force buffered PRM writes to complete
 * @save_and_clear_irqen: fn ptr to save and clear IRQENABLE regs
 * @restore_irqen: fn ptr to save and clear IRQENABLE regs
+ * @reconfigure_io_chain: fn ptr to reconfigure IO chain
 * @saved_mask: IRQENABLE regs are saved here during suspend
 * @priority_mask: 1 bit per IRQ, set to 1 if omap_prcm_irq.priority = true
 * @base_irq: base dynamic IRQ number, returned from irq_alloc_descs() in init
@@ -479,6 +502,7 @@ struct omap_prcm_irq_setup {
        void (*ocp_barrier)(void);
        void (*save_and_clear_irqen)(u32 *saved_mask);
        void (*restore_irqen)(u32 *saved_mask);
+        void (*reconfigure_io_chain)(void);
        u32 *saved_mask;
        u32 *priority_mask;
        int base_irq;
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.c b/arch/arm/mach-omap2/prcm_mpu44xx.c
index c30e44a7fab0..cdbee6326d29 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.c
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.c
@@ -30,12 +30,12 @@ void __iomem *prcm_mpu_base;
 u32 omap4_prcm_mpu_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+        return readl_relaxed(OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
 }
 void omap4_prcm_mpu_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
+        writel_relaxed(val, OMAP44XX_PRCM_MPU_REGADDR(inst, reg));
 }
 u32 omap4_prcm_mpu_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 059bd4f49035..ac9cb4550239 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -26,7 +26,6 @@
 #define __ARCH_ARM_MACH_OMAP2_PRCM_MPU44XX_H
 #include "prcm_mpu_44xx_54xx.h"
-#include "common.h"
 #define OMAP4430_PRCM_MPU_BASE                  0x48243000
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index cebad565ed37..106132db532b 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -123,8 +123,15 @@
 #define OMAP3430_GLOBAL_SW_RST_SHIFT                    1
 #define OMAP3430_GLOBAL_COLD_RST_SHIFT                  0
 #define OMAP3430_GLOBAL_COLD_RST_MASK                   (1 << 0)
-#define OMAP3430_SEL_OFF_MASK                           (1 << 3)
+#define OMAP3430_PRM_VOLTCTRL_SEL_VMODE                 (1 << 4)
-#define OMAP3430_AUTO_OFF_MASK                          (1 << 2)
+#define OMAP3430_PRM_VOLTCTRL_SEL_OFF                   (1 << 3)
+#define OMAP3430_PRM_VOLTCTRL_AUTO_OFF                  (1 << 2)
+#define OMAP3430_PRM_VOLTCTRL_AUTO_RET                  (1 << 1)
+#define OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP                (1 << 0)
 #define OMAP3430_SETUP_TIME2_MASK                       (0xffff << 16)
 #define OMAP3430_SETUP_TIME1_MASK                       (0xffff << 0)
+#define OMAP3430_PRM_POLCTRL_OFFMODE_POL                (1 << 3)
+#define OMAP3430_PRM_POLCTRL_CLKOUT_POL                 (1 << 2)
+#define OMAP3430_PRM_POLCTRL_CLKREQ_POL                 (1 << 1)
+#define OMAP3430_PRM_POLCTRL_EXTVOL_POL                 (1 << 0)
 #endif
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 623db40fdbbd..48480d557b61 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -17,10 +17,18 @@
 # ifndef __ASSEMBLER__
 extern void __iomem *prm_base;
+extern u16 prm_features;
 extern void omap2_set_globals_prm(void __iomem *prm);
 int of_prcm_init(void);
 # endif
+/*
+ * prm_features flag values
+ *
+ * PRM_HAS_IO_WAKEUP: has IO wakeup capability
+ * PRM_HAS_VOLTAGE: has voltage domains
+ */
+#define PRM_HAS_IO_WAKEUP       (1 << 0)
 /*
 * MAX_MODULE_SOFTRESET_WAIT: Maximum microseconds to wait for OMAP
@@ -118,6 +126,7 @@ struct prm_reset_src_map {
 * @read_reset_sources: ptr to the SoC PRM-specific get_reset_source impl
 * @was_any_context_lost_old: ptr to the SoC PRM context loss test fn
 * @clear_context_loss_flags_old: ptr to the SoC PRM context loss flag clear fn
+ * @late_init: ptr to the late init function
 *
 * XXX @was_any_context_lost_old and @clear_context_loss_flags_old are
 * deprecated.
@@ -126,6 +135,7 @@ struct prm_ll_data {
        u32 (*read_reset_sources)(void);
        bool (*was_any_context_lost_old)(u8 part, s16 inst, u16 idx);
        void (*clear_context_loss_flags_old)(u8 part, s16 inst, u16 idx);
+        int (*late_init)(void);
 };
 extern int prm_register(struct prm_ll_data *pld);
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c
index 418de9c3b319..a3a3cca2bcc4 100644
--- a/arch/arm/mach-omap2/prm2xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx.c
@@ -18,9 +18,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
-#include "soc.h"
-#include "common.h"
-#include "vp.h"
 #include "powerdomain.h"
 #include "clockdomain.h"
 #include "prm2xxx.h"
@@ -201,19 +198,11 @@ static struct prm_ll_data omap2xxx_prm_ll_data = {
 int __init omap2xxx_prm_init(void)
 {
-        if (!cpu_is_omap24xx())
-                return 0;
        return prm_register(&omap2xxx_prm_ll_data);
 }
 static void __exit omap2xxx_prm_exit(void)
 {
-        if (!cpu_is_omap24xx())
+        prm_unregister(&omap2xxx_prm_ll_data);
-                return;
-        /* Should never happen */
-        WARN(prm_unregister(&omap2xxx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
 }
 __exitcall(omap2xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h
index 3194dd87e0e4..d2cb6365716f 100644
--- a/arch/arm/mach-omap2/prm2xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx.h
@@ -27,7 +27,7 @@
 /*
 * OMAP2-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
 *
 * With a few exceptions, these are the register names beginning with
 * PRCM_* on 24xx.  (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c
index 947f6adfed0c..c13b4e293ffa 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c
@@ -16,7 +16,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "common.h"
 #include "powerdomain.h"
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h
index 9624b40836d4..1a3a96392b97 100644
--- a/arch/arm/mach-omap2/prm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h
@@ -55,12 +55,12 @@
 /* Power/reset management domain register get/set */
 static inline u32 omap2_prm_read_mod_reg(s16 module, u16 idx)
 {
-        return __raw_readl(prm_base + module + idx);
+        return readl_relaxed(prm_base + module + idx);
 }
 static inline void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx)
 {
-        __raw_writel(val, prm_base + module + idx);
+        writel_relaxed(val, prm_base + module + idx);
 }
 /* Read-modify-write a register in a PRM module. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 720440737744..62709cd2f9c5 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -19,7 +19,6 @@
 #include <linux/err.h>
 #include <linux/io.h>
-#include "common.h"
 #include "powerdomain.h"
 #include "prm33xx.h"
 #include "prm-regbits-33xx.h"
@@ -27,13 +26,13 @@
 /* Read a register in a PRM instance */
 u32 am33xx_prm_read_reg(s16 inst, u16 idx)
 {
-        return __raw_readl(prm_base + inst + idx);
+        return readl_relaxed(prm_base + inst + idx);
 }
 /* Write into a register in a PRM instance */
 void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
 {
-        __raw_writel(val, prm_base + inst + idx);
+        writel_relaxed(val, prm_base + inst + idx);
 }
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c
index 7721990d2006..4bd7a2dca8af 100644
--- a/arch/arm/mach-omap2/prm3xxx.c
+++ b/arch/arm/mach-omap2/prm3xxx.c
@@ -43,6 +43,7 @@ static struct omap_prcm_irq_setup omap3_prcm_irq_setup = {
        .ocp_barrier            = &omap3xxx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap3xxx_prm_save_and_clear_irqen,
        .restore_irqen          = &omap3xxx_prm_restore_irqen,
+        .reconfigure_io_chain   = &omap3xxx_prm_reconfigure_io_chain,
 };
 /*
@@ -246,7 +247,7 @@ void omap3xxx_prm_reconfigure_io_chain(void)
 */
 static void __init omap3xxx_prm_enable_io_wakeup(void)
 {
-        if (omap3_has_io_wakeup())
+        if (prm_features & PRM_HAS_IO_WAKEUP)
                omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
                                           PM_WKEN);
 }
@@ -400,23 +401,26 @@ struct pwrdm_ops omap3_pwrdm_operations = {
 *
 */
+static int omap3xxx_prm_late_init(void);
 static struct prm_ll_data omap3xxx_prm_ll_data = {
        .read_reset_sources = &omap3xxx_prm_read_reset_sources,
+        .late_init = &omap3xxx_prm_late_init,
 };
 int __init omap3xxx_prm_init(void)
 {
-        if (!cpu_is_omap34xx())
+        if (omap3_has_io_wakeup())
-                return 0;
+                prm_features |= PRM_HAS_IO_WAKEUP;
        return prm_register(&omap3xxx_prm_ll_data);
 }
-static int __init omap3xxx_prm_late_init(void)
+static int omap3xxx_prm_late_init(void)
 {
        int ret;
-        if (!cpu_is_omap34xx())
+        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                return 0;
        omap3xxx_prm_enable_io_wakeup();
@@ -427,15 +431,9 @@ static int __init omap3xxx_prm_late_init(void)
        return ret;
 }
-omap_subsys_initcall(omap3xxx_prm_late_init);
 static void __exit omap3xxx_prm_exit(void)
 {
-        if (!cpu_is_omap34xx())
+        prm_unregister(&omap3xxx_prm_ll_data);
-                return;
-        /* Should never happen */
-        WARN(prm_unregister(&omap3xxx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
 }
 __exitcall(omap3xxx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h
index f8eb83323b1a..1dacfc5b1959 100644
--- a/arch/arm/mach-omap2/prm3xxx.h
+++ b/arch/arm/mach-omap2/prm3xxx.h
@@ -26,7 +26,7 @@
 /*
 * OMAP3-specific global PRM registers
- * Use __raw_{read,write}l() with these registers.
+ * Use {read,write}l_relaxed() with these registers.
 *
 * With a few exceptions, these are the register names beginning with
 * PRM_* on 34xx.  (The exceptions are the IRQSTATUS and IRQENABLE
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 03a603476cfc..a7f6ea27180a 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -47,6 +47,7 @@ static struct omap_prcm_irq_setup omap4_prcm_irq_setup = {
        .ocp_barrier            = &omap44xx_prm_ocp_barrier,
        .save_and_clear_irqen   = &omap44xx_prm_save_and_clear_irqen,
        .restore_irqen          = &omap44xx_prm_restore_irqen,
+        .reconfigure_io_chain   = &omap44xx_prm_reconfigure_io_chain,
 };
 /*
@@ -81,13 +82,13 @@ static struct prm_reset_src_map omap44xx_prm_reset_src_map[] = {
 /* Read a register in a CM/PRM instance in the PRM module */
 u32 omap4_prm_read_inst_reg(s16 inst, u16 reg)
 {
-        return __raw_readl(prm_base + inst + reg);
+        return readl_relaxed(prm_base + inst + reg);
 }
 /* Write into a register in a CM/PRM instance in the PRM module */
 void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 reg)
 {
-        __raw_writel(val, prm_base + inst + reg);
+        writel_relaxed(val, prm_base + inst + reg);
 }
 /* Read-modify-write a register in a PRM module. Caller must lock */
@@ -649,6 +650,8 @@ struct pwrdm_ops omap4_pwrdm_operations = {
        .pwrdm_has_voltdm       = omap4_check_vcvp,
 };
+static int omap44xx_prm_late_init(void);
 /*
 * XXX document
 */
@@ -656,34 +659,29 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
        .read_reset_sources = &omap44xx_prm_read_reset_sources,
        .was_any_context_lost_old = &omap44xx_prm_was_any_context_lost_old,
        .clear_context_loss_flags_old = &omap44xx_prm_clear_context_loss_flags_old,
+        .late_init = &omap44xx_prm_late_init,
 };
 int __init omap44xx_prm_init(void)
 {
-        if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
+        if (cpu_is_omap44xx())
-                return 0;
+                prm_features |= PRM_HAS_IO_WAKEUP;
        return prm_register(&omap44xx_prm_ll_data);
 }
-static int __init omap44xx_prm_late_init(void)
+static int omap44xx_prm_late_init(void)
 {
-        if (!cpu_is_omap44xx())
+        if (!(prm_features & PRM_HAS_IO_WAKEUP))
                return 0;
        omap44xx_prm_enable_io_wakeup();
        return omap_prcm_register_chain_handler(&omap4_prcm_irq_setup);
 }
-omap_subsys_initcall(omap44xx_prm_late_init);
 static void __exit omap44xx_prm_exit(void)
 {
-        if (!cpu_is_omap44xx())
+        prm_unregister(&omap44xx_prm_ll_data);
-                return;
-        /* Should never happen */
-        WARN(prm_unregister(&omap44xx_prm_ll_data),
-             "%s: prm_ll_data function pointer mismatch\n", __func__);
 }
 __exitcall(omap44xx_prm_exit);
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index b4c4ab9c8044..25e8b8232115 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -62,6 +62,8 @@ static struct omap_prcm_irq_setup *prcm_irq_setup;
 /* prm_base: base virtual address of the PRM IP block */
 void __iomem *prm_base;
+u16 prm_features;
 /*
 * prm_ll_data: function pointers to SoC-specific implementations of
 * common PRM functions
@@ -330,12 +332,7 @@ int omap_prcm_register_chain_handler(struct omap_prcm_irq_setup *irq_setup)
        if (of_have_populated_dt()) {
                int irq = omap_prcm_event_to_irq("io");
-                if (cpu_is_omap34xx())
+                omap_pcs_legacy_init(irq, irq_setup->reconfigure_io_chain);
-                        omap_pcs_legacy_init(irq,
-                                omap3xxx_prm_reconfigure_io_chain);
-                else
-                        omap_pcs_legacy_init(irq,
-                                omap44xx_prm_reconfigure_io_chain);
        }
        return 0;
@@ -530,3 +527,11 @@ int __init of_prcm_init(void)
        return 0;
 }
+static int __init prm_late_init(void)
+{
+        if (prm_ll_data->late_init)
+                return prm_ll_data->late_init();
+        return 0;
+}
+subsys_initcall(prm_late_init);
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index 05fcf6de44ee..69f0dd08629c 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -49,7 +49,7 @@ u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_prm_bases[part]);
-        return __raw_readl(_prm_bases[part] + inst + idx);
+        return readl_relaxed(_prm_bases[part] + inst + idx);
 }
 /* Write into a register in a PRM instance */
@@ -58,7 +58,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
        BUG_ON(part >= OMAP4_MAX_PRCM_PARTITIONS ||
               part == OMAP4430_INVALID_PRCM_PARTITION ||
               !_prm_bases[part]);
-        __raw_writel(val, _prm_bases[part] + inst + idx);
+        writel_relaxed(val, _prm_bases[part] + inst + idx);
 }
 /* Read-modify-write a register in PRM. Caller must lock */
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index 446aa13511fd..645a2a46b213 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -31,24 +31,24 @@ extern void __iomem *omap2_sms_base;
 static inline void sdrc_write_reg(u32 val, u16 reg)
 {
-        __raw_writel(val, OMAP_SDRC_REGADDR(reg));
+        writel_relaxed(val, OMAP_SDRC_REGADDR(reg));
 }
 static inline u32 sdrc_read_reg(u16 reg)
 {
-        return __raw_readl(OMAP_SDRC_REGADDR(reg));
+        return readl_relaxed(OMAP_SDRC_REGADDR(reg));
 }
 /* SMS global register get/set */
 static inline void sms_write_reg(u32 val, u16 reg)
 {
-        __raw_writel(val, OMAP_SMS_REGADDR(reg));
+        writel_relaxed(val, OMAP_SMS_REGADDR(reg));
 }
 static inline u32 sms_read_reg(u16 reg)
 {
-        return __raw_readl(OMAP_SMS_REGADDR(reg));
+        return readl_relaxed(OMAP_SMS_REGADDR(reg));
 }
 extern void omap2_set_globals_sdrc(void __iomem *sdrc, void __iomem *sms);
diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c
index 907291714643..ae3f1553158d 100644
--- a/arch/arm/mach-omap2/sdrc2xxx.c
+++ b/arch/arm/mach-omap2/sdrc2xxx.c
@@ -103,9 +103,9 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force)
         * prm2xxx.c function
         */
        if (cpu_is_omap2420())
-                __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP);
+                writel_relaxed(0xffff, OMAP2420_PRCM_VOLTSETUP);
        else
-                __raw_writel(0xffff, OMAP2430_PRCM_VOLTSETUP);
+                writel_relaxed(0xffff, OMAP2430_PRCM_VOLTSETUP);
        omap2_sram_reprogram_sdrc(level, dll_ctrl, m_type);
        curr_perf_level = level;
        local_irq_restore(flags);
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 30abcc8b20e0..de2a34c423a7 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -459,10 +459,15 @@ IS_OMAP_TYPE(3430, 0x3430)
 #define OMAP5430_REV_ES2_0      (OMAP54XX_CLASS | (0x30 << 16) | (0x20 << 8))
 #define OMAP5432_REV_ES2_0      (OMAP54XX_CLASS | (0x32 << 16) | (0x20 << 8))
+#define DRA7XX_CLASS            0x07000000
+#define DRA752_REV_ES1_0        (DRA7XX_CLASS | (0x52 << 16) | (0x10 << 8))
+#define DRA752_REV_ES1_1        (DRA7XX_CLASS | (0x52 << 16) | (0x11 << 8))
 void omap2xxx_check_revision(void);
 void omap3xxx_check_revision(void);
 void omap4xxx_check_revision(void);
 void omap5xxx_check_revision(void);
+void dra7xxx_check_revision(void);
 void omap3xxx_check_features(void);
 void ti81xx_check_features(void);
 void am33xx_check_features(void);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d7bc33f15344..1b91ef0c182a 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -57,7 +57,7 @@ static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
                /*
                 * In OMAP4 the efuse registers are 24 bit aligned.
-                 * A __raw_readl will fail for non-32 bit aligned address
+                 * A readl_relaxed will fail for non-32 bit aligned address
                 * and hence the 8-bit read and shift.
                 */
                if (cpu_is_omap44xx()) {
diff --git a/arch/arm/mach-omap2/sram.c b/arch/arm/mach-omap2/sram.c
index 4bd096836235..ddf1818af228 100644
--- a/arch/arm/mach-omap2/sram.c
+++ b/arch/arm/mach-omap2/sram.c
@@ -70,16 +70,16 @@ static int is_sram_locked(void)
        if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
                /* RAMFW: R/W access to all initiators for all qualifier sets */
                if (cpu_is_omap242x()) {
-                        __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
+                        writel_relaxed(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
+                        writel_relaxed(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
+                        writel_relaxed(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
                }
                if (cpu_is_omap34xx()) {
-                        __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
-                        __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
+                        writel_relaxed(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
-                        __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
+                        writel_relaxed(0x0, OMAP34XX_VA_ADDR_MATCH2);
-                        __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
+                        writel_relaxed(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
                }
                return 0;
        } else
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b62de9f9d05c..43d03fbf4c0b 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -361,7 +361,7 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
 /* Clocksource code */
 static struct omap_dm_timer clksrc;
-static bool use_gptimer_clksrc;
+static bool use_gptimer_clksrc __initdata;
 /*
 * clocksource
@@ -546,15 +546,15 @@ static void __init realtime_counter_init(void)
        }
        /* Program numerator and denumerator registers */
-        reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) &
+        reg = readl_relaxed(base + INCREMENTER_NUMERATOR_OFFSET) &
                        NUMERATOR_DENUMERATOR_MASK;
        reg |= num;
-        __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
+        writel_relaxed(reg, base + INCREMENTER_NUMERATOR_OFFSET);
-        reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
+        reg = readl_relaxed(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
                        NUMERATOR_DENUMERATOR_MASK;
        reg |= den;
-        __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+        writel_relaxed(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
        arch_timer_freq = (rate / den) * num;
        set_cntfreq();
diff --git a/arch/arm/mach-omap2/usb-host.c b/arch/arm/mach-omap2/usb-host.c
index 10855eb4ccc1..745367c0c2bb 100644
--- a/arch/arm/mach-omap2/usb-host.c
+++ b/arch/arm/mach-omap2/usb-host.c
@@ -28,7 +28,7 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/usb/phy.h>
-#include <linux/usb/usb_phy_gen_xceiv.h>
+#include <linux/usb/usb_phy_generic.h>
 #include "soc.h"
 #include "omap_device.h"
@@ -349,7 +349,7 @@ static struct fixed_voltage_config hsusb_reg_config = {
        /* .init_data filled later */
 };
-static const char *nop_name = "usb_phy_gen_xceiv"; /* NOP PHY driver */
+static const char *nop_name = "usb_phy_generic"; /* NOP PHY driver */
 static const char *reg_name = "reg-fixed-voltage"; /* Regulator driver */
 /**
@@ -435,7 +435,7 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
        struct platform_device *pdev;
        char *phy_id;
        struct platform_device_info pdevinfo;
-        struct usb_phy_gen_xceiv_platform_data nop_pdata;
+        struct usb_phy_generic_platform_data nop_pdata;
        for (i = 0; i < num_phys; i++) {
@@ -469,8 +469,8 @@ int usbhs_init_phys(struct usbhs_phy_data *phy, int num_phys)
                pdevinfo.id = phy->port;
                pdevinfo.data = &nop_pdata;
                pdevinfo.size_data =
-                        sizeof(struct usb_phy_gen_xceiv_platform_data);
+                        sizeof(struct usb_phy_generic_platform_data);
-                scnprintf(phy_id, MAX_STR, "usb_phy_gen_xceiv.%d",
+                scnprintf(phy_id, MAX_STR, "usb_phy_generic.%d",
                                        phy->port);
                pdev = platform_device_register_full(&pdevinfo);
                if (IS_ERR(pdev)) {
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index 49ac7977e03e..a4628a9e760c 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -220,10 +220,126 @@ static inline u32 omap_usec_to_32k(u32 usec)
        return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
 }
-/* Set oscillator setup time for omap3 */
+struct omap3_vc_timings {
-static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
+        u32 voltsetup1;
+        u32 voltsetup2;
+};
+struct omap3_vc {
+        struct voltagedomain *vd;
+        u32 voltctrl;
+        u32 voltsetup1;
+        u32 voltsetup2;
+        struct omap3_vc_timings timings[2];
+};
+static struct omap3_vc vc;
+void omap3_vc_set_pmic_signaling(int core_next_state)
+{
+        struct voltagedomain *vd = vc.vd;
+        struct omap3_vc_timings *c = vc.timings;
+        u32 voltctrl, voltsetup1, voltsetup2;
+        voltctrl = vc.voltctrl;
+        voltsetup1 = vc.voltsetup1;
+        voltsetup2 = vc.voltsetup2;
+        switch (core_next_state) {
+        case PWRDM_POWER_OFF:
+                voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
+                              OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
+                voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
+                if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
+                        voltsetup2 = c->voltsetup2;
+                else
+                        voltsetup1 = c->voltsetup1;
+                break;
+        case PWRDM_POWER_RET:
+        default:
+                c++;
+                voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
+                              OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
+                voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
+                voltsetup1 = c->voltsetup1;
+                break;
+        }
+        if (voltctrl != vc.voltctrl) {
+                vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
+                vc.voltctrl = voltctrl;
+        }
+        if (voltsetup1 != vc.voltsetup1) {
+                vd->write(c->voltsetup1,
+                          OMAP3_PRM_VOLTSETUP1_OFFSET);
+                vc.voltsetup1 = voltsetup1;
+        }
+        if (voltsetup2 != vc.voltsetup2) {
+                vd->write(c->voltsetup2,
+                          OMAP3_PRM_VOLTSETUP2_OFFSET);
+                vc.voltsetup2 = voltsetup2;
+        }
+}
+#define PRM_POLCTRL_TWL_MASK    (OMAP3430_PRM_POLCTRL_CLKREQ_POL | \
+                                        OMAP3430_PRM_POLCTRL_CLKREQ_POL)
+#define PRM_POLCTRL_TWL_VAL     OMAP3430_PRM_POLCTRL_CLKREQ_POL
+/*
+ * Configure signal polarity for sys_clkreq and sys_off_mode pins
+ * as the default values are wrong and can cause the system to hang
+ * if any twl4030 scripts are loaded.
+ */
+static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
+{
+        u32 val;
+        if (vc.vd)
+                return;
+        vc.vd = voltdm;
+        val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
+        if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
+            (val & OMAP3430_PRM_POLCTRL_CLKREQ_POL)) {
+                val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
+                val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
+                pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
+                         val);
+                voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
+        }
+        /*
+         * By default let's use I2C4 signaling for retention idle
+         * and sys_off_mode pin signaling for off idle. This way we
+         * have sys_clk_req pin go down for retention and both
+         * sys_clk_req and sys_off_mode pins will go down for off
+         * idle. And we can also scale voltages to zero for off-idle.
+         * Note that no actual voltage scaling during off-idle will
+         * happen unless the board specific twl4030 PMIC scripts are
+         * loaded.
+         */
+        val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
+        if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
+                val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
+                pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
+                         val);
+                voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
+        }
+        vc.voltctrl = val;
+        omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
+}
+static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
+                                  struct omap3_vc_timings *c, u32 idle)
 {
-        voltdm->write(omap_usec_to_32k(usec), OMAP3_PRM_CLKSETUP_OFFSET);
+        unsigned long val;
+        val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
+        val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
+        val <<= __ffs(voltdm->vfsm->voltsetup_mask);
+        c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
+        c->voltsetup1 |= val;
 }
 /**
@@ -236,37 +352,21 @@ static void omap3_set_clksetup(u32 usec, struct voltagedomain *voltdm)
 * or retention. Off mode has additionally an option to use sys_off_mode
 * pad, which uses a global signal to program the whole power IC to
 * off-mode.
+ *
+ * Note that pmic is not controlling the voltage scaling during
+ * retention signaled over I2C4, so we can keep voltsetup2 as 0.
+ * And the oscillator is not shut off over I2C4, so no need to
+ * set clksetup.
 */
-static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
+static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
 {
-        unsigned long voltsetup1;
+        struct omap3_vc_timings *c = vc.timings;
-        u32 tgt_volt;
-        /*
-         * Oscillator is shut down only if we are using sys_off_mode pad,
-         * thus we set a minimal setup time here
-         */
-        omap3_set_clksetup(1, voltdm);
-        if (off_mode)
+        /* Configure PRWDM_POWER_OFF over I2C4 */
-                tgt_volt = voltdm->vc_param->off;
+        omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
-        else
+        c++;
-                tgt_volt = voltdm->vc_param->ret;
+        /* Configure PRWDM_POWER_RET over I2C4 */
+        omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
-        voltsetup1 = (voltdm->vc_param->on - tgt_volt) /
-                        voltdm->pmic->slew_rate;
-        voltsetup1 = voltsetup1 * voltdm->sys_clk.rate / 8 / 1000000 + 1;
-        voltdm->rmw(voltdm->vfsm->voltsetup_mask,
-                voltsetup1 << __ffs(voltdm->vfsm->voltsetup_mask),
-                voltdm->vfsm->voltsetup_reg);
-        /*
-         * pmic is not controlling the voltage scaling during retention,
-         * thus set voltsetup2 to 0
-         */
-        voltdm->write(0, OMAP3_PRM_VOLTSETUP2_OFFSET);
 }
 /**
@@ -275,69 +375,49 @@ static void omap3_set_i2c_timings(struct voltagedomain *voltdm, bool off_mode)
 *
 * Calculates and sets up off-mode timings for a channel. Off-mode
 * can use either I2C based voltage scaling, or alternatively
- * sys_off_mode pad can be used to send a global command to power IC.
+ * sys_off_mode pad can be used to send a global command to power IC.n,
- * This function first checks which mode is being used, and calls
- * omap3_set_i2c_timings() if the system is using I2C control mode.
 * sys_off_mode has the additional benefit that voltages can be
 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
 * scale to 600mV.
+ *
+ * Note that omap is not controlling the voltage scaling during
+ * off idle signaled by sys_off_mode, so we can keep voltsetup1
+ * as 0.
 */
 static void omap3_set_off_timings(struct voltagedomain *voltdm)
 {
-        unsigned long clksetup;
+        struct omap3_vc_timings *c = vc.timings;
-        unsigned long voltsetup2;
+        u32 tstart, tshut, clksetup, voltoffset;
-        unsigned long voltsetup2_old;
-        u32 val;
-        u32 tstart, tshut;
-        /* check if sys_off_mode is used to control off-mode voltages */
+        if (c->voltsetup2)
-        val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
-        if (!(val & OMAP3430_SEL_OFF_MASK)) {
-                /* No, omap is controlling them over I2C */
-                omap3_set_i2c_timings(voltdm, true);
                return;
-        }
        omap_pm_get_oscillator(&tstart, &tshut);
-        omap3_set_clksetup(tstart, voltdm);
+        if (tstart == ULONG_MAX) {
+                pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
-        clksetup = voltdm->read(OMAP3_PRM_CLKSETUP_OFFSET);
+                clksetup = omap_usec_to_32k(10000);
+        } else {
-        /* voltsetup 2 in us */
+                clksetup = omap_usec_to_32k(tstart);
-        voltsetup2 = voltdm->vc_param->on / voltdm->pmic->slew_rate;
+        }
-        /* convert to 32k clk cycles */
-        voltsetup2 = DIV_ROUND_UP(voltsetup2 * 32768, 1000000);
-        voltsetup2_old = voltdm->read(OMAP3_PRM_VOLTSETUP2_OFFSET);
-        /*
-         * Update voltsetup2 if higher than current value (needed because
-         * we have multiple channels with different ramp times), also
-         * update voltoffset always to value recommended by TRM
-         */
-        if (voltsetup2 > voltsetup2_old) {
-                voltdm->write(voltsetup2, OMAP3_PRM_VOLTSETUP2_OFFSET);
-                voltdm->write(clksetup - voltsetup2,
-                        OMAP3_PRM_VOLTOFFSET_OFFSET);
-        } else
-                voltdm->write(clksetup - voltsetup2_old,
-                        OMAP3_PRM_VOLTOFFSET_OFFSET);
        /*
-         * omap is not controlling voltage scaling during off-mode,
+         * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
-         * thus set voltsetup1 to 0
+         * switch from HFCLKIN to internal oscillator. That means timings
+         * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
+         * that means we can calculate the value based on the oscillator
+         * start-up time since voltoffset2 = clksetup - voltoffset.
         */
-        voltdm->rmw(voltdm->vfsm->voltsetup_mask, 0,
+        voltoffset = omap_usec_to_32k(488);
-                voltdm->vfsm->voltsetup_reg);
+        c->voltsetup2 = clksetup - voltoffset;
+        voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
-        /* voltoffset must be clksetup minus voltsetup2 according to TRM */
+        voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
-        voltdm->write(clksetup - voltsetup2, OMAP3_PRM_VOLTOFFSET_OFFSET);
 }
 static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 {
+        omap3_vc_init_pmic_signaling(voltdm);
        omap3_set_off_timings(voltdm);
+        omap3_set_i2c_timings(voltdm);
 }
 /**
@@ -462,7 +542,7 @@ static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
        val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
                OMAP4_DOWNTIME_MASK);
-        __raw_writel(val, OMAP4_SCRM_CLKSETUPTIME);
+        writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
 }
 /* OMAP4 specific voltage init functions */
@@ -584,7 +664,7 @@ static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
        val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
        /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
-        __raw_writel(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
+        writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
                                OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
        /* HSSCLH can always be zero */
diff --git a/arch/arm/mach-omap2/vc.h b/arch/arm/mach-omap2/vc.h
index 91c8d75bf2ea..cdbdd78e755e 100644
--- a/arch/arm/mach-omap2/vc.h
+++ b/arch/arm/mach-omap2/vc.h
@@ -117,6 +117,9 @@ extern struct omap_vc_param omap4_mpu_vc_data;
 extern struct omap_vc_param omap4_iva_vc_data;
 extern struct omap_vc_param omap4_core_vc_data;
+void omap3_vc_set_pmic_signaling(int core_next_state);
 void omap_vc_init_channel(struct voltagedomain *voltdm);
 int omap_vc_pre_scale(struct voltagedomain *voltdm,
                      unsigned long target_volt,
diff --git a/arch/arm/mach-omap2/wd_timer.c b/arch/arm/mach-omap2/wd_timer.c
index d15c7bbab8e2..97d6607d447a 100644
--- a/arch/arm/mach-omap2/wd_timer.c
+++ b/arch/arm/mach-omap2/wd_timer.c
@@ -49,12 +49,12 @@ int omap2_wd_timer_disable(struct omap_hwmod *oh)
        }
        /* sequence required to disable watchdog */
-        __raw_writel(0xAAAA, base + OMAP_WDT_SPR);
+        writel_relaxed(0xAAAA, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+        while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
                cpu_relax();
-        __raw_writel(0x5555, base + OMAP_WDT_SPR);
+        writel_relaxed(0x5555, base + OMAP_WDT_SPR);
-        while (__raw_readl(base + OMAP_WDT_WPS) & 0x10)
+        while (readl_relaxed(base + OMAP_WDT_WPS) & 0x10)
                cpu_relax();
        return 0;
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 14f2cae4109c..2412efb6cdd9 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -5,6 +5,11 @@ menu "Orion Implementations"
 config ARCH_ORION5X_DT
        bool "Marvell Orion5x Flattened Device Tree"
        select USE_OF
+        select ORION_CLK
+        select ORION_IRQCHIP
+        select ORION_TIMER
+        select PINCTRL
+        select PINCTRL_ORION
        help
          Say 'Y' here if you want your kernel to support the
          Marvell Orion5x using flattened device tree.
@@ -23,6 +28,14 @@ config MACH_RD88F5182
          Say 'Y' here if you want your kernel to support the
          Marvell Orion-NAS (88F5182) RD2
+config MACH_RD88F5182_DT
+        bool "Marvell Orion-NAS Reference Design (Flattened Device Tree)"
+        select ARCH_ORION5X_DT
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the Marvell
+          Orion-NAS (88F5182) RD2, Flattened Device Tree.
 config MACH_KUROBOX_PRO
        bool "KuroBox Pro"
        select I2C_BOARDINFO
@@ -102,28 +115,13 @@ config MACH_MV2120
          Say 'Y' here if you want your kernel to support the
          HP Media Vault mv2120 or mv5100.
-config MACH_EDMINI_V2_DT
+config MACH_D2NET_DT
-        bool "LaCie Ethernet Disk mini V2 (Flattened Device Tree)"
+        bool "LaCie d2 Network / Big Disk Network (Flattened Device Tree)"
-        select I2C_BOARDINFO
        select ARCH_ORION5X_DT
        help
          Say 'Y' here if you want your kernel to support the
-          LaCie Ethernet Disk mini V2 (Flattened Device Tree).
-config MACH_D2NET
-        bool "LaCie d2 Network"
-        select I2C_BOARDINFO
-        help
-          Say 'Y' here if you want your kernel to support the
          LaCie d2 Network NAS.
-config MACH_BIGDISK
-        bool "LaCie Big Disk Network"
-        select I2C_BOARDINFO
-        help
-          Say 'Y' here if you want your kernel to support the
-          LaCie Big Disk Network NAS.
 config MACH_NET2BIG
        bool "LaCie 2Big Network"
        select I2C_BOARDINFO
@@ -131,8 +129,9 @@ config MACH_NET2BIG
          Say 'Y' here if you want your kernel to support the
          LaCie 2Big Network NAS.
-config MACH_MSS2
+config MACH_MSS2_DT
-        bool "Maxtor Shared Storage II"
+        bool "Maxtor Shared Storage II (Flattened Device Tree)"
+        select ARCH_ORION5X_DT
        help
          Say 'Y' here if you want your kernel to support the
          Maxtor Shared Storage II platform.
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 45da805fb236..a40b5c9a58c4 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,10 +12,7 @@ obj-$(CONFIG_MACH_TS409)	+= ts409-setup.o tsx09-common.o
 obj-$(CONFIG_MACH_WRT350N_V2)   += wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
-obj-$(CONFIG_MACH_D2NET)        += d2net-setup.o
-obj-$(CONFIG_MACH_BIGDISK)      += d2net-setup.o
 obj-$(CONFIG_MACH_NET2BIG)      += net2big-setup.o
-obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_FXO)       += rd88f5181l-fxo-setup.o
@@ -23,4 +20,6 @@ obj-$(CONFIG_MACH_RD88F6183AP_GE)	+= rd88f6183ap-ge-setup.o
 obj-$(CONFIG_MACH_LINKSTATION_LSCHL)    += ls-chl-setup.o
 obj-$(CONFIG_ARCH_ORION5X_DT)           += board-dt.o
-obj-$(CONFIG_MACH_EDMINI_V2_DT) += edmini_v2-setup.o
+obj-$(CONFIG_MACH_D2NET_DT)     += board-d2net.o
+obj-$(CONFIG_MACH_MSS2_DT)      += board-mss2.o
+obj-$(CONFIG_MACH_RD88F5182_DT) += board-rd88f5182.o
diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c
new file mode 100644
index 000000000000..8a7284124153
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-d2net.c
@@ -0,0 +1,109 @@
+/*
+ * arch/arm/mach-orion5x/board-d2net.c
+ *
+ * LaCie d2Network and Big Disk Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/leds.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include <plat/orion-gpio.h>
+#include "common.h"
+/*****************************************************************************
+ * LaCie d2 Network Info
+ ****************************************************************************/
+/*****************************************************************************
+ * GPIO LED's
+ ****************************************************************************/
+/*
+ * The blue front LED is wired to the CPLD and can blink in relation with the
+ * SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ * led_off   | blink_ctrl | SATA active | LED state
+ *           |            |             |
+ *    1      |     x      |      x      |  off
+ *    0      |     0      |      0      |  off
+ *    0      |     1      |      0      |  blink (rate 300ms)
+ *    0      |     x      |      1      |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Red LED have priority.
+ */
+#define D2NET_GPIO_RED_LED              6
+#define D2NET_GPIO_BLUE_LED_BLINK_CTRL  16
+#define D2NET_GPIO_BLUE_LED_OFF         23
+static struct gpio_led d2net_leds[] = {
+        {
+                .name = "d2net:blue:sata",
+                .default_trigger = "default-on",
+                .gpio = D2NET_GPIO_BLUE_LED_OFF,
+                .active_low = 1,
+        },
+        {
+                .name = "d2net:red:fail",
+                .gpio = D2NET_GPIO_RED_LED,
+        },
+};
+static struct gpio_led_platform_data d2net_led_data = {
+        .num_leds = ARRAY_SIZE(d2net_leds),
+        .leds = d2net_leds,
+};
+static struct platform_device d2net_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_led_data,
+        },
+};
+static void __init d2net_gpio_leds_init(void)
+{
+        int err;
+        /* Configure register blink_ctrl to allow SATA activity LED blinking. */
+        err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL);
+        }
+        if (err)
+                pr_err("d2net: failed to configure blue LED blink GPIO\n");
+        platform_device_register(&d2net_gpio_leds);
+}
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+void __init d2net_init(void)
+{
+        d2net_gpio_leds_init();
+        pr_notice("d2net: Flash write are not yet supported.\n");
+}
diff --git a/arch/arm/mach-orion5x/board-dt.c b/arch/arm/mach-orion5x/board-dt.c
index c134a826070a..35d418faf8f1 100644
--- a/arch/arm/mach-orion5x/board-dt.c
+++ b/arch/arm/mach-orion5x/board-dt.c
@@ -15,10 +15,16 @@
 #include <linux/of.h>
 #include <linux/of_platform.h>
 #include <linux/cpu.h>
+#include <linux/mbus.h>
+#include <linux/clk-provider.h>
+#include <linux/clocksource.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
 #include <plat/irq.h>
+#include <plat/time.h>
 #include "common.h"
 static struct of_dev_auxdata orion5x_auxdata_lookup[] __initdata = {
@@ -39,14 +45,13 @@ static void __init orion5x_dt_init(void)
        orion5x_id(&dev, &rev, &dev_name);
        printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
+        BUG_ON(mvebu_mbus_dt_init());
        /*
         * Setup Orion address map
         */
        orion5x_setup_wins();
-        /* Setup root of clk tree */
-        clk_init();
        /*
         * Don't issue "Wait for Interrupt" instruction if we are
         * running on D0 5281 silicon.
@@ -56,8 +61,8 @@ static void __init orion5x_dt_init(void)
                cpu_idle_poll_ctrl(true);
        }
-        if (of_machine_is_compatible("lacie,ethernet-disk-mini-v2"))
+        if (of_machine_is_compatible("maxtor,shared-storage-2"))
-                edmini_v2_init();
+                mss2_init();
        of_platform_populate(NULL, of_default_bus_match_table,
                             orion5x_auxdata_lookup, NULL);
@@ -71,9 +76,6 @@ static const char *orion5x_dt_compat[] = {
 DT_MACHINE_START(ORION5X_DT, "Marvell Orion5x (Flattened Device Tree)")
        /* Maintainer: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> */
        .map_io         = orion5x_map_io,
-        .init_early     = orion5x_init_early,
-        .init_irq       = orion_dt_init_irq,
-        .init_time      = orion5x_timer_init,
        .init_machine   = orion5x_dt_init,
        .restart        = orion5x_restart,
        .dt_compat      = orion5x_dt_compat,
diff --git a/arch/arm/mach-orion5x/board-mss2.c b/arch/arm/mach-orion5x/board-mss2.c
new file mode 100644
index 000000000000..66f9c3ba86cc
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-mss2.c
@@ -0,0 +1,90 @@
+/*
+ * Maxtor Shared Storage II Board Setup
+ *
+ * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include <mach/bridge-regs.h>
+#include "common.h"
+/*****************************************************************************
+ * Maxtor Shared Storage II Info
+ ****************************************************************************/
+/****************************************************************************
+ * PCI setup
+ ****************************************************************************/
+static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        int irq;
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+        return -1;
+}
+static struct hw_pci mss2_pci __initdata = {
+        .nr_controllers = 2,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = mss2_pci_map_irq,
+};
+static int __init mss2_pci_init(void)
+{
+        if (machine_is_mss2())
+                pci_common_init(&mss2_pci);
+        return 0;
+}
+subsys_initcall(mss2_pci_init);
+/*****************************************************************************
+ * MSS2 power off method
+ ****************************************************************************/
+/*
+ * On the Maxtor Shared Storage II, the shutdown process is the following :
+ * - Userland modifies U-boot env to tell U-boot to go idle at next boot
+ * - The board reboots
+ * - U-boot starts and go into an idle mode until the user press "power"
+ */
+static void mss2_power_off(void)
+{
+        u32 reg;
+        /*
+         * Enable and issue soft reset
+         */
+        reg = readl(RSTOUTn_MASK);
+        reg |= 1 << 2;
+        writel(reg, RSTOUTn_MASK);
+        reg = readl(CPU_SOFT_RESET);
+        reg |= 1;
+        writel(reg, CPU_SOFT_RESET);
+}
+void __init mss2_init(void)
+{
+        /* register mss2 specific power-off method */
+        pm_power_off = mss2_power_off;
+}
diff --git a/arch/arm/mach-orion5x/board-rd88f5182.c b/arch/arm/mach-orion5x/board-rd88f5182.c
new file mode 100644
index 000000000000..270824b0e50f
--- /dev/null
+++ b/arch/arm/mach-orion5x/board-rd88f5182.c
@@ -0,0 +1,116 @@
+/*
+ * arch/arm/mach-orion5x/rd88f5182-setup.c
+ *
+ * Marvell Orion-NAS Reference Design Setup
+ *
+ * Maintainer: Ronen Shitrit <rshitrit@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/gpio.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+/*****************************************************************************
+ * RD-88F5182 Info
+ ****************************************************************************/
+/*
+ * PCI
+ */
+#define RD88F5182_PCI_SLOT0_OFFS        7
+#define RD88F5182_PCI_SLOT0_IRQ_A_PIN   7
+#define RD88F5182_PCI_SLOT0_IRQ_B_PIN   6
+/*****************************************************************************
+ * PCI
+ ****************************************************************************/
+static void __init rd88f5182_pci_preinit(void)
+{
+        int pin;
+        /*
+         * Configure PCI GPIO IRQ pins
+         */
+        pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
+        if (gpio_request(pin, "PCI IntA") == 0) {
+                if (gpio_direction_input(pin) == 0) {
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                } else {
+                        printk(KERN_ERR "rd88f5182_pci_preinit failed to "
+                                        "set_irq_type pin %d\n", pin);
+                        gpio_free(pin);
+                }
+        } else {
+                printk(KERN_ERR "rd88f5182_pci_preinit failed to request gpio %d\n", pin);
+        }
+        pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
+        if (gpio_request(pin, "PCI IntB") == 0) {
+                if (gpio_direction_input(pin) == 0) {
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                } else {
+                        printk(KERN_ERR "rd88f5182_pci_preinit failed to "
+                                        "set_irq_type pin %d\n", pin);
+                        gpio_free(pin);
+                }
+        } else {
+                printk(KERN_ERR "rd88f5182_pci_preinit failed to gpio_request %d\n", pin);
+        }
+}
+static int __init rd88f5182_pci_map_irq(const struct pci_dev *dev, u8 slot,
+        u8 pin)
+{
+        int irq;
+        /*
+         * Check for devices with hard-wired IRQs.
+         */
+        irq = orion5x_pci_map_irq(dev, slot, pin);
+        if (irq != -1)
+                return irq;
+        /*
+         * PCI IRQs are connected via GPIOs
+         */
+        switch (slot - RD88F5182_PCI_SLOT0_OFFS) {
+        case 0:
+                if (pin == 1)
+                        return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_A_PIN);
+                else
+                        return gpio_to_irq(RD88F5182_PCI_SLOT0_IRQ_B_PIN);
+        default:
+                return -1;
+        }
+}
+static struct hw_pci rd88f5182_pci __initdata = {
+        .nr_controllers = 2,
+        .preinit        = rd88f5182_pci_preinit,
+        .setup          = orion5x_pci_sys_setup,
+        .scan           = orion5x_pci_sys_scan_bus,
+        .map_irq        = rd88f5182_pci_map_irq,
+};
+static int __init rd88f5182_pci_init(void)
+{
+        if (of_machine_is_compatible("marvell,rd-88f5182-nas"))
+                pci_common_init(&rd88f5182_pci);
+        return 0;
+}
+subsys_initcall(rd88f5182_pci_init);
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 3f1de1111e0f..6bbb7b55c6d1 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -365,8 +365,7 @@ void orion5x_restart(enum reboot_mode mode, const char *cmd)
 * Many orion-based systems have buggy bootloader implementations.
 * This is a common fixup for bogus memory tags.
 */
-void __init tag_fixup_mem32(struct tag *t, char **from,
+void __init tag_fixup_mem32(struct tag *t, char **from)
-                            struct meminfo *meminfo)
 {
        for (; t->hdr.size; t = tag_next(t))
                if (t->hdr.tag == ATAG_MEM &&
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index f565f9944af2..cd0389c6e822 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -21,7 +21,7 @@ struct mv_sata_platform_data;
 #define ORION_MBUS_DEVBUS_BOOT_ATTR   0x0f
 #define ORION_MBUS_DEVBUS_TARGET(cs)  0x01
 #define ORION_MBUS_DEVBUS_ATTR(cs)    (~(1 << cs))
-#define ORION_MBUS_SRAM_TARGET        0x00
+#define ORION_MBUS_SRAM_TARGET        0x09
 #define ORION_MBUS_SRAM_ATTR          0x00
 /*
@@ -64,17 +64,15 @@ int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
 int orion5x_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-/* board init functions for boards not fully converted to fdt */
+struct tag;
-#ifdef CONFIG_MACH_EDMINI_V2_DT
+extern void __init tag_fixup_mem32(struct tag *, char **);
-void edmini_v2_init(void);
+#ifdef CONFIG_MACH_MSS2_DT
+extern void mss2_init(void);
 #else
-static inline void edmini_v2_init(void) {};
+static inline void mss2_init(void) {}
 #endif
-struct meminfo;
-struct tag;
-extern void __init tag_fixup_mem32(struct tag *, char **, struct meminfo *);
 /*****************************************************************************
 * Helpers to access Orion registers
 ****************************************************************************/
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
deleted file mode 100644
index 8f68b745c1d5..000000000000
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * arch/arm/mach-orion5x/d2net-setup.c
- *
- * LaCie d2Network and Big Disk Network NAS setup
- *
- * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/orion5x.h>
-#include <plat/orion-gpio.h>
-#include "common.h"
-#include "mpp.h"
-/*****************************************************************************
- * LaCie d2 Network Info
- ****************************************************************************/
-/*
- * 512KB NOR flash Device bus boot chip select
- */
-#define D2NET_NOR_BOOT_BASE             0xfff80000
-#define D2NET_NOR_BOOT_SIZE             SZ_512K
-/*****************************************************************************
- * 512KB NOR Flash on Boot Device
- ****************************************************************************/
-/*
- * TODO: Check write support on flash MX29LV400CBTC-70G
- */
-static struct mtd_partition d2net_partitions[] = {
-        {
-                .name           = "Full512kb",
-                .size           = MTDPART_SIZ_FULL,
-                .offset         = 0,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-};
-static struct physmap_flash_data d2net_nor_flash_data = {
-        .width          = 1,
-        .parts          = d2net_partitions,
-        .nr_parts       = ARRAY_SIZE(d2net_partitions),
-};
-static struct resource d2net_nor_flash_resource = {
-        .flags                  = IORESOURCE_MEM,
-        .start                  = D2NET_NOR_BOOT_BASE,
-        .end                    = D2NET_NOR_BOOT_BASE
-                                        + D2NET_NOR_BOOT_SIZE - 1,
-};
-static struct platform_device d2net_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = 0,
-        .dev            = {
-                .platform_data  = &d2net_nor_flash_data,
-        },
-        .num_resources          = 1,
-        .resource               = &d2net_nor_flash_resource,
-};
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-static struct mv643xx_eth_platform_data d2net_eth_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-/*****************************************************************************
- * I2C devices
- ****************************************************************************/
-/*
- * i2c addr | chip         | description
- * 0x32     | Ricoh 5C372b | RTC
- * 0x3e     | GMT G762     | PWM fan controller
- * 0x50     | HT24LC08     | eeprom (1kB)
- *
- * TODO: Add G762 support to the g760a driver.
- */
-static struct i2c_board_info __initdata d2net_i2c_devices[] = {
-        {
-                I2C_BOARD_INFO("rs5c372b", 0x32),
-        }, {
-                I2C_BOARD_INFO("24c08", 0x50),
-        },
-};
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data d2net_sata_data = {
-        .n_ports        = 2,
-};
-#define D2NET_GPIO_SATA0_POWER  3
-#define D2NET_GPIO_SATA1_POWER  12
-static void __init d2net_sata_power_init(void)
-{
-        int err;
-        err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power");
-        if (err == 0) {
-                err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1);
-                if (err)
-                        gpio_free(D2NET_GPIO_SATA0_POWER);
-        }
-        if (err)
-                pr_err("d2net: failed to configure SATA0 power GPIO\n");
-        err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power");
-        if (err == 0) {
-                err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1);
-                if (err)
-                        gpio_free(D2NET_GPIO_SATA1_POWER);
-        }
-        if (err)
-                pr_err("d2net: failed to configure SATA1 power GPIO\n");
-}
-/*****************************************************************************
- * GPIO LED's
- ****************************************************************************/
-/*
- * The blue front LED is wired to the CPLD and can blink in relation with the
- * SATA activity.
- *
- * The following array detail the different LED registers and the combination
- * of their possible values:
- *
- * led_off   | blink_ctrl | SATA active | LED state
- *           |            |             |
- *    1      |     x      |      x      |  off
- *    0      |     0      |      0      |  off
- *    0      |     1      |      0      |  blink (rate 300ms)
- *    0      |     x      |      1      |  on
- *
- * Notes: The blue and the red front LED's can't be on at the same time.
- *        Red LED have priority.
- */
-#define D2NET_GPIO_RED_LED              6
-#define D2NET_GPIO_BLUE_LED_BLINK_CTRL  16
-#define D2NET_GPIO_BLUE_LED_OFF         23
-static struct gpio_led d2net_leds[] = {
-        {
-                .name = "d2net:blue:sata",
-                .default_trigger = "default-on",
-                .gpio = D2NET_GPIO_BLUE_LED_OFF,
-                .active_low = 1,
-        },
-        {
-                .name = "d2net:red:fail",
-                .gpio = D2NET_GPIO_RED_LED,
-        },
-};
-static struct gpio_led_platform_data d2net_led_data = {
-        .num_leds = ARRAY_SIZE(d2net_leds),
-        .leds = d2net_leds,
-};
-static struct platform_device d2net_gpio_leds = {
-        .name           = "leds-gpio",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &d2net_led_data,
-        },
-};
-static void __init d2net_gpio_leds_init(void)
-{
-        int err;
-        /* Configure GPIO over MPP max number. */
-        orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1);
-        /* Configure register blink_ctrl to allow SATA activity LED blinking. */
-        err = gpio_request(D2NET_GPIO_BLUE_LED_BLINK_CTRL, "blue LED blink");
-        if (err == 0) {
-                err = gpio_direction_output(D2NET_GPIO_BLUE_LED_BLINK_CTRL, 1);
-                if (err)
-                        gpio_free(D2NET_GPIO_BLUE_LED_BLINK_CTRL);
-        }
-        if (err)
-                pr_err("d2net: failed to configure blue LED blink GPIO\n");
-        platform_device_register(&d2net_gpio_leds);
-}
-/****************************************************************************
- * GPIO keys
- ****************************************************************************/
-#define D2NET_GPIO_PUSH_BUTTON          18
-#define D2NET_GPIO_POWER_SWITCH_ON      8
-#define D2NET_GPIO_POWER_SWITCH_OFF     9
-#define D2NET_SWITCH_POWER_ON           0x1
-#define D2NET_SWITCH_POWER_OFF          0x2
-static struct gpio_keys_button d2net_buttons[] = {
-        {
-                .type           = EV_SW,
-                .code           = D2NET_SWITCH_POWER_OFF,
-                .gpio           = D2NET_GPIO_POWER_SWITCH_OFF,
-                .desc           = "Power rocker switch (auto|off)",
-                .active_low     = 0,
-        },
-        {
-                .type           = EV_SW,
-                .code           = D2NET_SWITCH_POWER_ON,
-                .gpio           = D2NET_GPIO_POWER_SWITCH_ON,
-                .desc           = "Power rocker switch (on|auto)",
-                .active_low     = 0,
-        },
-        {
-                .type           = EV_KEY,
-                .code           = KEY_POWER,
-                .gpio           = D2NET_GPIO_PUSH_BUTTON,
-                .desc           = "Front Push Button",
-                .active_low     = 0,
-        },
-};
-static struct gpio_keys_platform_data d2net_button_data = {
-        .buttons        = d2net_buttons,
-        .nbuttons       = ARRAY_SIZE(d2net_buttons),
-};
-static struct platform_device d2net_gpio_buttons = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &d2net_button_data,
-        },
-};
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int d2net_mpp_modes[] __initdata = {
-        MPP0_GPIO,      /* Board ID (bit 0) */
-        MPP1_GPIO,      /* Board ID (bit 1) */
-        MPP2_GPIO,      /* Board ID (bit 2) */
-        MPP3_GPIO,      /* SATA 0 power */
-        MPP4_UNUSED,
-        MPP5_GPIO,      /* Fan fail detection */
-        MPP6_GPIO,      /* Red front LED */
-        MPP7_UNUSED,
-        MPP8_GPIO,      /* Rear power switch (on|auto) */
-        MPP9_GPIO,      /* Rear power switch (auto|off) */
-        MPP10_UNUSED,
-        MPP11_UNUSED,
-        MPP12_GPIO,     /* SATA 1 power */
-        MPP13_UNUSED,
-        MPP14_SATA_LED, /* SATA 0 active */
-        MPP15_SATA_LED, /* SATA 1 active */
-        MPP16_GPIO,     /* Blue front LED blink control */
-        MPP17_UNUSED,
-        MPP18_GPIO,     /* Front button (0 = Released, 1 = Pushed ) */
-        MPP19_UNUSED,
-        0,
-        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
-        /* 23: Blue front LED off */
-        /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
-};
-#define D2NET_GPIO_INHIBIT_POWER_OFF    24
-static void __init d2net_init(void)
-{
-        /*
-         * Setup basic Orion functions. Need to be called early.
-         */
-        orion5x_init();
-        orion5x_mpp_conf(d2net_mpp_modes);
-        /*
-         * Configure peripherals.
-         */
-        orion5x_ehci0_init();
-        orion5x_eth_init(&d2net_eth_data);
-        orion5x_i2c_init();
-        orion5x_uart0_init();
-        d2net_sata_power_init();
-        orion5x_sata_init(&d2net_sata_data);
-        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
-                                    D2NET_NOR_BOOT_BASE,
-                                    D2NET_NOR_BOOT_SIZE);
-        platform_device_register(&d2net_nor_flash);
-        platform_device_register(&d2net_gpio_buttons);
-        d2net_gpio_leds_init();
-        pr_notice("d2net: Flash write are not yet supported.\n");
-        i2c_register_board_info(0, d2net_i2c_devices,
-                                ARRAY_SIZE(d2net_i2c_devices));
-        orion_gpio_set_valid(D2NET_GPIO_INHIBIT_POWER_OFF, 1);
-}
-/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
-#ifdef CONFIG_MACH_D2NET
-MACHINE_START(D2NET, "LaCie d2 Network")
-        .atag_offset    = 0x100,
-        .init_machine   = d2net_init,
-        .map_io         = orion5x_map_io,
-        .init_early     = orion5x_init_early,
-        .init_irq       = orion5x_init_irq,
-        .init_time      = orion5x_timer_init,
-        .fixup          = tag_fixup_mem32,
-        .restart        = orion5x_restart,
-MACHINE_END
-#endif
-#ifdef CONFIG_MACH_BIGDISK
-MACHINE_START(BIGDISK, "LaCie Big Disk Network")
-        .atag_offset    = 0x100,
-        .init_machine   = d2net_init,
-        .map_io         = orion5x_map_io,
-        .init_early     = orion5x_init_early,
-        .init_irq       = orion5x_init_irq,
-        .init_time      = orion5x_timer_init,
-        .fixup          = tag_fixup_mem32,
-        .restart        = orion5x_restart,
-MACHINE_END
-#endif
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
deleted file mode 100644
index f66c1b2ee8c1..000000000000
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * arch/arm/mach-orion5x/edmini_v2-setup.c
- *
- * LaCie Ethernet Disk mini V2 Setup
- *
- * Copyright (C) 2008 Christopher Moore <moore@free.fr>
- * Copyright (C) 2008 Albert Aribaud <albert.aribaud@free.fr>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-/*
- * TODO: add Orion USB device port init when kernel.org support is added.
- * TODO: add flash write support: see below.
- * TODO: add power-off support.
- * TODO: add I2C EEPROM support.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mbus.h>
-#include <linux/mtd/physmap.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/orion5x.h>
-#include "common.h"
-#include "mpp.h"
-/*****************************************************************************
- * EDMINI_V2 Info
- ****************************************************************************/
-/*
- * 512KB NOR flash Device bus boot chip select
- */
-#define EDMINI_V2_NOR_BOOT_BASE         0xfff80000
-#define EDMINI_V2_NOR_BOOT_SIZE         SZ_512K
-/*****************************************************************************
- * 512KB NOR Flash on BOOT Device
- ****************************************************************************/
-/*
- * Currently the MTD code does not recognize the MX29LV400CBCT as a bottom
- * -type device. This could cause risks of accidentally erasing critical
- * flash sectors. We thus define a single, write-protected partition covering
- * the whole flash.
- * TODO: once the flash part TOP/BOTTOM detection issue is sorted out in the MTD
- * code, break this into at least three partitions: 'u-boot code', 'u-boot
- * environment' and 'whatever is left'.
- */
-static struct mtd_partition edmini_v2_partitions[] = {
-        {
-                .name           = "Full512kb",
-                .size           = 0x00080000,
-                .offset         = 0x00000000,
-                .mask_flags     = MTD_WRITEABLE,
-        },
-};
-static struct physmap_flash_data edmini_v2_nor_flash_data = {
-        .width          = 1,
-        .parts          = edmini_v2_partitions,
-        .nr_parts       = ARRAY_SIZE(edmini_v2_partitions),
-};
-static struct resource edmini_v2_nor_flash_resource = {
-        .flags                  = IORESOURCE_MEM,
-        .start                  = EDMINI_V2_NOR_BOOT_BASE,
-        .end                    = EDMINI_V2_NOR_BOOT_BASE
-                + EDMINI_V2_NOR_BOOT_SIZE - 1,
-};
-static struct platform_device edmini_v2_nor_flash = {
-        .name                   = "physmap-flash",
-        .id                     = 0,
-        .dev            = {
-                .platform_data  = &edmini_v2_nor_flash_data,
-        },
-        .num_resources          = 1,
-        .resource               = &edmini_v2_nor_flash_resource,
-};
-/*****************************************************************************
- * RTC 5C372a on I2C bus
- ****************************************************************************/
-#define EDMINIV2_RTC_GPIO       3
-static struct i2c_board_info __initdata edmini_v2_i2c_rtc = {
-        I2C_BOARD_INFO("rs5c372a", 0x32),
-        .irq = 0,
-};
-/*****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int edminiv2_mpp_modes[] __initdata = {
-        MPP0_UNUSED,
-        MPP1_UNUSED,
-        MPP2_UNUSED,
-        MPP3_GPIO,      /* RTC interrupt */
-        MPP4_UNUSED,
-        MPP5_UNUSED,
-        MPP6_UNUSED,
-        MPP7_UNUSED,
-        MPP8_UNUSED,
-        MPP9_UNUSED,
-        MPP10_UNUSED,
-        MPP11_UNUSED,
-        MPP12_SATA_LED, /* SATA 0 presence */
-        MPP13_SATA_LED, /* SATA 1 presence */
-        MPP14_SATA_LED, /* SATA 0 active */
-        MPP15_SATA_LED, /* SATA 1 active */
-        /* 16: Power LED control (0 = On, 1 = Off) */
-        MPP16_GPIO,
-        /* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
-        MPP17_GPIO,
-        /* 18: Power button status (0 = Released, 1 = Pressed) */
-        MPP18_GPIO,
-        MPP19_UNUSED,
-        0,
-};
-void __init edmini_v2_init(void)
-{
-        orion5x_mpp_conf(edminiv2_mpp_modes);
-        /*
-         * Configure peripherals.
-         */
-        orion5x_ehci0_init();
-        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
-                                    EDMINI_V2_NOR_BOOT_BASE,
-                                    EDMINI_V2_NOR_BOOT_SIZE);
-        platform_device_register(&edmini_v2_nor_flash);
-        pr_notice("edmini_v2: USB device port, flash write and power-off "
-                  "are not yet supported.\n");
-        /* Get RTC IRQ and register the chip */
-        if (gpio_request(EDMINIV2_RTC_GPIO, "rtc") == 0) {
-                if (gpio_direction_input(EDMINIV2_RTC_GPIO) == 0)
-                        edmini_v2_i2c_rtc.irq = gpio_to_irq(EDMINIV2_RTC_GPIO);
-                else
-                        gpio_free(EDMINIV2_RTC_GPIO);
-        }
-        if (edmini_v2_i2c_rtc.irq == 0)
-                pr_warning("edmini_v2: failed to get RTC IRQ\n");
-        i2c_register_board_info(0, &edmini_v2_i2c_rtc, 1);
-}
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index 9654b0cc5892..cd4bac4d7e43 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -16,6 +16,7 @@
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
+#include <asm/exception.h>
 #include "common.h"
 static int __initdata gpio0_irqs[4] = {
@@ -25,10 +26,37 @@ static int __initdata gpio0_irqs[4] = {
        IRQ_ORION5X_GPIO_24_31,
 };
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+/*
+ * Compiling with both non-DT and DT support enabled, will
+ * break asm irq handler used by non-DT boards. Therefore,
+ * we provide a C-style irq handler even for non-DT boards,
+ * if MULTI_IRQ_HANDLER is set.
+ */
+asmlinkage void
+__exception_irq_entry orion5x_legacy_handle_irq(struct pt_regs *regs)
+{
+        u32 stat;
+        stat = readl_relaxed(MAIN_IRQ_CAUSE);
+        stat &= readl_relaxed(MAIN_IRQ_MASK);
+        if (stat) {
+                unsigned int hwirq = __fls(stat);
+                handle_IRQ(hwirq, regs);
+                return;
+        }
+}
+#endif
 void __init orion5x_init_irq(void)
 {
        orion_irq_init(0, MAIN_IRQ_MASK);
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+        set_handle_irq(orion5x_legacy_handle_irq);
+#endif
        /*
         * Initialize gpiolib for GPIOs 0-31.
         */
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
deleted file mode 100644
index e105130ba51c..000000000000
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * Maxtor Shared Storage II Board Setup
- *
- * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/pci.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/leds.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/ata_platform.h>
-#include <linux/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/pci.h>
-#include <mach/orion5x.h>
-#include <mach/bridge-regs.h>
-#include "common.h"
-#include "mpp.h"
-#define MSS2_NOR_BOOT_BASE      0xff800000
-#define MSS2_NOR_BOOT_SIZE      SZ_256K
-/*****************************************************************************
- * Maxtor Shared Storage II Info
- ****************************************************************************/
-/*
- * Maxtor Shared Storage II hardware :
- * - Marvell 88F5182-A2 C500
- * - Marvell 88E1111 Gigabit Ethernet PHY
- * - RTC M41T81 (@0x68) on I2C bus
- * - 256KB NOR flash
- * - 64MB of RAM
- */
-/*****************************************************************************
- * 256KB NOR Flash on BOOT Device
- ****************************************************************************/
-static struct physmap_flash_data mss2_nor_flash_data = {
-        .width          = 1,
-};
-static struct resource mss2_nor_flash_resource = {
-        .flags          = IORESOURCE_MEM,
-        .start          = MSS2_NOR_BOOT_BASE,
-        .end            = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1,
-};
-static struct platform_device mss2_nor_flash = {
-        .name           = "physmap-flash",
-        .id             = 0,
-        .dev            = {
-                .platform_data  = &mss2_nor_flash_data,
-        },
-        .resource       = &mss2_nor_flash_resource,
-        .num_resources  = 1,
-};
-/****************************************************************************
- * PCI setup
- ****************************************************************************/
-static int __init mss2_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
-{
-        int irq;
-        /*
-         * Check for devices with hard-wired IRQs.
-         */
-        irq = orion5x_pci_map_irq(dev, slot, pin);
-        if (irq != -1)
-                return irq;
-        return -1;
-}
-static struct hw_pci mss2_pci __initdata = {
-        .nr_controllers = 2,
-        .setup          = orion5x_pci_sys_setup,
-        .scan           = orion5x_pci_sys_scan_bus,
-        .map_irq        = mss2_pci_map_irq,
-};
-static int __init mss2_pci_init(void)
-{
-        if (machine_is_mss2())
-                pci_common_init(&mss2_pci);
-        return 0;
-}
-subsys_initcall(mss2_pci_init);
-/*****************************************************************************
- * Ethernet
- ****************************************************************************/
-static struct mv643xx_eth_platform_data mss2_eth_data = {
-        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
-};
-/*****************************************************************************
- * SATA
- ****************************************************************************/
-static struct mv_sata_platform_data mss2_sata_data = {
-        .n_ports        = 2,
-};
-/*****************************************************************************
- * GPIO buttons
- ****************************************************************************/
-#define MSS2_GPIO_KEY_RESET     12
-#define MSS2_GPIO_KEY_POWER     11
-static struct gpio_keys_button mss2_buttons[] = {
-        {
-                .code           = KEY_POWER,
-                .gpio           = MSS2_GPIO_KEY_POWER,
-                .desc           = "Power",
-                .active_low     = 1,
-        }, {
-                .code           = KEY_RESTART,
-                .gpio           = MSS2_GPIO_KEY_RESET,
-                .desc           = "Reset",
-                .active_low     = 1,
-        },
-};
-static struct gpio_keys_platform_data mss2_button_data = {
-        .buttons        = mss2_buttons,
-        .nbuttons       = ARRAY_SIZE(mss2_buttons),
-};
-static struct platform_device mss2_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &mss2_button_data,
-        },
-};
-/*****************************************************************************
- * RTC m41t81 on I2C bus
- ****************************************************************************/
-#define MSS2_GPIO_RTC_IRQ       3
-static struct i2c_board_info __initdata mss2_i2c_rtc = {
-        I2C_BOARD_INFO("m41t81", 0x68),
-};
-/*****************************************************************************
- * MSS2 power off method
- ****************************************************************************/
-/*
- * On the Maxtor Shared Storage II, the shutdown process is the following :
- * - Userland modifies U-boot env to tell U-boot to go idle at next boot
- * - The board reboots
- * - U-boot starts and go into an idle mode until the user press "power"
- */
-static void mss2_power_off(void)
-{
-        u32 reg;
-        /*
-         * Enable and issue soft reset
-         */
-        reg = readl(RSTOUTn_MASK);
-        reg |= 1 << 2;
-        writel(reg, RSTOUTn_MASK);
-        reg = readl(CPU_SOFT_RESET);
-        reg |= 1;
-        writel(reg, CPU_SOFT_RESET);
-}
-/****************************************************************************
- * General Setup
- ****************************************************************************/
-static unsigned int mss2_mpp_modes[] __initdata = {
-        MPP0_GPIO,              /* Power LED */
-        MPP1_GPIO,              /* Error LED */
-        MPP2_UNUSED,
-        MPP3_GPIO,              /* RTC interrupt */
-        MPP4_GPIO,              /* HDD ind. (Single/Dual)*/
-        MPP5_GPIO,              /* HD0 5V control */
-        MPP6_GPIO,              /* HD0 12V control */
-        MPP7_GPIO,              /* HD1 5V control */
-        MPP8_GPIO,              /* HD1 12V control */
-        MPP9_UNUSED,
-        MPP10_GPIO,             /* Fan control */
-        MPP11_GPIO,             /* Power button */
-        MPP12_GPIO,             /* Reset button */
-        MPP13_UNUSED,
-        MPP14_SATA_LED,         /* SATA 0 active */
-        MPP15_SATA_LED,         /* SATA 1 active */
-        MPP16_UNUSED,
-        MPP17_UNUSED,
-        MPP18_UNUSED,
-        MPP19_UNUSED,
-        0,
-};
-static void __init mss2_init(void)
-{
-        /* Setup basic Orion functions. Need to be called early. */
-        orion5x_init();
-        orion5x_mpp_conf(mss2_mpp_modes);
-        /*
-         * MPP[20] Unused
-         * MPP[21] PCI clock
-         * MPP[22] USB 0 over current
-         * MPP[23] USB 1 over current
-         */
-        /*
-         * Configure peripherals.
-         */
-        orion5x_ehci0_init();
-        orion5x_ehci1_init();
-        orion5x_eth_init(&mss2_eth_data);
-        orion5x_i2c_init();
-        orion5x_sata_init(&mss2_sata_data);
-        orion5x_uart0_init();
-        orion5x_xor_init();
-        mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
-                                    ORION_MBUS_DEVBUS_BOOT_ATTR,
-                                    MSS2_NOR_BOOT_BASE,
-                                    MSS2_NOR_BOOT_SIZE);
-        platform_device_register(&mss2_nor_flash);
-        platform_device_register(&mss2_button_device);
-        if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) {
-                if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0)
-                        mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ);
-                else
-                        gpio_free(MSS2_GPIO_RTC_IRQ);
-        }
-        i2c_register_board_info(0, &mss2_i2c_rtc, 1);
-        /* register mss2 specific power-off method */
-        pm_power_off = mss2_power_off;
-}
-MACHINE_START(MSS2, "Maxtor Shared Storage II")
-        /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
-        .atag_offset    = 0x100,
-        .init_machine   = mss2_init,
-        .map_io         = orion5x_map_io,
-        .init_early     = orion5x_init_early,
-        .init_irq       = orion5x_init_irq,
-        .init_time      = orion5x_timer_init,
-        .fixup          = tag_fixup_mem32,
-        .restart        = orion5x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 7a6b4a323125..8846e7d87ea5 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -2,7 +2,6 @@ obj-y += rstc.o
 obj-y += common.o
 obj-y += rtciobrg.o
 obj-$(CONFIG_DEBUG_LL) += lluart.o
-obj-$(CONFIG_CACHE_L2X0) += l2x0.o
 obj-$(CONFIG_SUSPEND) += pm.o sleep.o
 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)  += hotplug.o
diff --git a/arch/arm/mach-prima2/common.c b/arch/arm/mach-prima2/common.c
index 47c7819edb9b..a860ea27e8ae 100644
--- a/arch/arm/mach-prima2/common.c
+++ b/arch/arm/mach-prima2/common.c
@@ -34,6 +34,8 @@ static const char *atlas6_dt_match[] __initconst = {
 DT_MACHINE_START(ATLAS6_DT, "Generic ATLAS6 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .map_io         = sirfsoc_map_io,
        .init_late      = sirfsoc_init_late,
        .dt_compat      = atlas6_dt_match,
@@ -48,6 +50,8 @@ static const char *prima2_dt_match[] __initconst = {
 DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .map_io         = sirfsoc_map_io,
        .dma_zone_size  = SZ_256M,
        .init_late      = sirfsoc_init_late,
@@ -63,6 +67,8 @@ static const char *marco_dt_match[] __initconst = {
 DT_MACHINE_START(MARCO_DT, "Generic MARCO (Flattened Device Tree)")
        /* Maintainer: Barry Song <baohua.song@csr.com> */
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .smp            = smp_ops(sirfsoc_smp_ops),
        .map_io         = sirfsoc_map_io,
        .init_late      = sirfsoc_init_late,
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
deleted file mode 100644
index c7102539c0b0..000000000000
--- a/arch/arm/mach-prima2/l2x0.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * l2 cache initialization for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <asm/hardware/cache-l2x0.h>
-struct l2x0_aux {
-        u32 val;
-        u32 mask;
-};
-static const struct l2x0_aux prima2_l2x0_aux __initconst = {
-        .val = 2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT,
-        .mask = 0,
-};
-static const struct l2x0_aux marco_l2x0_aux __initconst = {
-        .val = (2 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT) |
-                (1 << L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT),
-        .mask = L2X0_AUX_CTRL_MASK,
-};
-static const struct of_device_id sirf_l2x0_ids[] __initconst = {
-        { .compatible = "sirf,prima2-pl310-cache", .data = &prima2_l2x0_aux, },
-        { .compatible = "sirf,marco-pl310-cache", .data = &marco_l2x0_aux, },
-        {},
-};
-static int __init sirfsoc_l2x0_init(void)
-{
-        struct device_node *np;
-        const struct l2x0_aux *aux;
-        np = of_find_matching_node(NULL, sirf_l2x0_ids);
-        if (np) {
-                aux = of_match_node(sirf_l2x0_ids, np)->data;
-                return l2x0_of_init(aux->val, aux->mask);
-        }
-        return 0;
-}
-early_initcall(sirfsoc_l2x0_init);
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index c4525a88e5da..96e9bc102117 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -71,7 +71,6 @@ static int sirfsoc_pm_enter(suspend_state_t state)
        case PM_SUSPEND_MEM:
                sirfsoc_pre_suspend_power_off();
-                outer_flush_all();
                outer_disable();
                /* go zzz */
                cpu_suspend(0, sirfsoc_finish_suspend);
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
index 4887a2a4c698..3dffcb2d714e 100644
--- a/arch/arm/mach-prima2/rstc.c
+++ b/arch/arm/mach-prima2/rstc.c
@@ -36,27 +36,33 @@ static int sirfsoc_reset_module(struct reset_controller_dev *rcdev,
        if (of_device_is_compatible(rcdev->of_node, "sirf,prima2-rstc")) {
                /*
-                 * Writing 1 to this bit resets corresponding block. Writing 0 to this
+                 * Writing 1 to this bit resets corresponding block.
-                 * bit de-asserts reset signal of the corresponding block.
+                 * Writing 0 to this bit de-asserts reset signal of the
-                 * datasheet doesn't require explicit delay between the set and clear
+                 * corresponding block. datasheet doesn't require explicit
-                 * of reset bit. it could be shorter if tests pass.
+                 * delay between the set and clear of reset bit. it could
+                 * be shorter if tests pass.
                 */
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | (1 << reset_bit),
+                writel(readl(sirfsoc_rstc_base +
+                        (reset_bit / 32) * 4) | (1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
-                msleep(10);
+                msleep(20);
-                writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~(1 << reset_bit),
+                writel(readl(sirfsoc_rstc_base +
+                        (reset_bit / 32) * 4) & ~(1 << reset_bit),
                        sirfsoc_rstc_base + (reset_bit / 32) * 4);
        } else {
                /*
                 * For MARCO and POLO
-                 * Writing 1 to SET register resets corresponding block. Writing 1 to CLEAR
+                 * Writing 1 to SET register resets corresponding block.
-                 * register de-asserts reset signal of the corresponding block.
+                 * Writing 1 to CLEAR register de-asserts reset signal of the
-                 * datasheet doesn't require explicit delay between the set and clear
+                 * corresponding block.
-                 * of reset bit. it could be shorter if tests pass.
+                 * datasheet doesn't require explicit delay between the set and
+                 * clear of reset bit. it could be shorter if tests pass.
                 */
-                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8);
+                writel(1 << reset_bit,
-                msleep(10);
+                        sirfsoc_rstc_base + (reset_bit / 32) * 8);
-                writel(1 << reset_bit, sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
+                msleep(20);
+                writel(1 << reset_bit,
+                        sirfsoc_rstc_base + (reset_bit / 32) * 8 + 4);
        }
        mutex_unlock(&rstc_lock);
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 584439bfa59f..4d3588d26c2a 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -837,8 +837,7 @@ static void __init cm_x300_init(void)
        cm_x300_init_bl();
 }
-static void __init cm_x300_fixup(struct tag *tags, char **cmdline,
+static void __init cm_x300_fixup(struct tag *tags, char **cmdline)
-                                 struct meminfo *mi)
 {
        /* Make sure that mi->bank[0].start = PHYS_ADDR */
        for (; tags->hdr.size; tags = tag_next(tags))
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 57d60542f982..91dd1c7cdbcd 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -34,6 +34,7 @@
 #include <linux/input/matrix_keypad.h>
 #include <linux/gpio_keys.h>
 #include <linux/module.h>
+#include <linux/memblock.h>
 #include <video/w100fb.h>
 #include <asm/setup.h>
@@ -753,16 +754,13 @@ static void __init corgi_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-static void __init fixup_corgi(struct tag *tags, char **cmdline,
+static void __init fixup_corgi(struct tag *tags, char **cmdline)
-                               struct meminfo *mi)
 {
        sharpsl_save_param();
-        mi->nr_banks=1;
-        mi->bank[0].start = 0xa0000000;
        if (machine_is_corgi())
-                mi->bank[0].size = (32*1024*1024);
+                memblock_add(0xa0000000, SZ_32M);
        else
-                mi->bank[0].size = (64*1024*1024);
+                memblock_add(0xa0000000, SZ_64M);
 }
 #ifdef CONFIG_MACH_CORGI
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 8280ebcaab9f..cfb864173ce3 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -21,6 +21,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/partitions.h>
 #include <linux/usb/gpio_vbus.h>
+#include <linux/memblock.h>
 #include <video/w100fb.h>
@@ -41,14 +42,12 @@
 #include "clock.h"
 /* Only e800 has 128MB RAM */
-void __init eseries_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
+void __init eseries_fixup(struct tag *tags, char **cmdline)
 {
-        mi->nr_banks=1;
-        mi->bank[0].start = 0xa0000000;
        if (machine_is_e800())
-                mi->bank[0].size = (128*1024*1024);
+                memblock_add(0xa0000000, SZ_128M);
        else
-                mi->bank[0].size = (64*1024*1024);
+                memblock_add(0xa0000000, SZ_64M);
 }
 struct gpio_vbus_mach_info e7xx_udc_info = {
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index aedf053a1de5..131991629116 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -29,6 +29,7 @@
 #include <linux/spi/ads7846.h>
 #include <linux/spi/pxa2xx_spi.h>
 #include <linux/mtd/sharpsl.h>
+#include <linux/memblock.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
@@ -456,13 +457,10 @@ static void __init poodle_init(void)
        poodle_init_spi();
 }
-static void __init fixup_poodle(struct tag *tags, char **cmdline,
+static void __init fixup_poodle(struct tag *tags, char **cmdline)
-                                struct meminfo *mi)
 {
        sharpsl_save_param();
-        mi->nr_banks=1;
+        memblock_add(0xa0000000, SZ_32M);
-        mi->bank[0].start = 0xa0000000;
-        mi->bank[0].size = (32*1024*1024);
 }
 MACHINE_START(POODLE, "SHARP Poodle")
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 0b11c1af51c4..840c3a48e720 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -32,6 +32,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/reboot.h>
+#include <linux/memblock.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -971,13 +972,10 @@ static void __init spitz_init(void)
        spitz_i2c_init();
 }
-static void __init spitz_fixup(struct tag *tags, char **cmdline,
+static void __init spitz_fixup(struct tag *tags, char **cmdline)
-                               struct meminfo *mi)
 {
        sharpsl_save_param();
-        mi->nr_banks = 1;
+        memblock_add(0xa0000000, SZ_64M);
-        mi->bank[0].start = 0xa0000000;
-        mi->bank[0].size = (64*1024*1024);
 }
 #ifdef CONFIG_MACH_SPITZ
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index ef5557b807ed..c158a6e3e0aa 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -37,6 +37,7 @@
 #include <linux/i2c/pxa-i2c.h>
 #include <linux/usb/gpio_vbus.h>
 #include <linux/reboot.h>
+#include <linux/memblock.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -960,13 +961,10 @@ static void __init tosa_init(void)
        platform_add_devices(devices, ARRAY_SIZE(devices));
 }
-static void __init fixup_tosa(struct tag *tags, char **cmdline,
+static void __init fixup_tosa(struct tag *tags, char **cmdline)
-                              struct meminfo *mi)
 {
        sharpsl_save_param();
-        mi->nr_banks=1;
+        memblock_add(0xa0000000, SZ_64M);
-        mi->bank[0].start = 0xa0000000;
-        mi->bank[0].size = (64*1024*1024);
 }
 MACHINE_START(TOSA, "SHARP Tosa")
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index b19d1c361cab..205f9bf3821e 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -413,7 +413,7 @@ static struct fixed_voltage_config can_regulator_pdata = {
 static struct platform_device can_regulator_device = {
        .name   = "reg-fixed-volage",
-        .id     = -1,
+        .id     = 0,
        .dev    = {
                .platform_data  = &can_regulator_pdata,
        },
@@ -510,18 +510,6 @@ struct platform_device zeus_max6369_device = {
        .num_resources  = 1,
 };
-static struct platform_device *zeus_devices[] __initdata = {
-        &zeus_serial_device,
-        &zeus_mtd_devices[0],
-        &zeus_dm9k0_device,
-        &zeus_dm9k1_device,
-        &zeus_sram_device,
-        &zeus_leds_device,
-        &zeus_pcmcia_device,
-        &zeus_max6369_device,
-        &can_regulator_device,
-};
 /* AC'97 */
 static pxa2xx_audio_ops_t zeus_ac97_info = {
        .reset_gpio = 95,
@@ -532,44 +520,50 @@ static pxa2xx_audio_ops_t zeus_ac97_info = {
 * USB host
 */
-static int zeus_ohci_init(struct device *dev)
+static struct regulator_consumer_supply zeus_ohci_regulator_supplies[] = {
-{
+        REGULATOR_SUPPLY("vbus2", "pxa27x-ohci"),
-        int err;
+};
-        /* Switch on port 2. */
-        if ((err = gpio_request(ZEUS_USB2_PWREN_GPIO, "USB2_PWREN"))) {
-                dev_err(dev, "Can't request USB2_PWREN\n");
-                return err;
-        }
-        if ((err = gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 1))) {
-                gpio_free(ZEUS_USB2_PWREN_GPIO);
-                dev_err(dev, "Can't enable USB2_PWREN\n");
-                return err;
-        }
-        /* Port 2 is shared between host and client interface. */
+static struct regulator_init_data zeus_ohci_regulator_data = {
-        UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+        .constraints = {
+                .valid_ops_mask         = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(zeus_ohci_regulator_supplies),
+        .consumer_supplies      = zeus_ohci_regulator_supplies,
+};
-        return 0;
+static struct fixed_voltage_config zeus_ohci_regulator_config = {
-}
+        .supply_name            = "vbus2",
+        .microvolts             = 5000000, /* 5.0V */
+        .gpio                   = ZEUS_USB2_PWREN_GPIO,
+        .enable_high            = 1,
+        .startup_delay          = 0,
+        .init_data              = &zeus_ohci_regulator_data,
+};
-static void zeus_ohci_exit(struct device *dev)
+static struct platform_device zeus_ohci_regulator_device = {
-{
+        .name           = "reg-fixed-voltage",
-        /* Power-off port 2 */
+        .id             = 1,
-        gpio_direction_output(ZEUS_USB2_PWREN_GPIO, 0);
+        .dev = {
-        gpio_free(ZEUS_USB2_PWREN_GPIO);
+                .platform_data = &zeus_ohci_regulator_config,
-}
+        },
+};
 static struct pxaohci_platform_data zeus_ohci_platform_data = {
        .port_mode      = PMM_NPS_MODE,
        /* Clear Power Control Polarity Low and set Power Sense
         * Polarity Low. Supply power to USB ports. */
        .flags          = ENABLE_PORT_ALL | POWER_SENSE_LOW,
-        .init           = zeus_ohci_init,
-        .exit           = zeus_ohci_exit,
 };
+static void zeus_register_ohci(void)
+{
+        /* Port 2 is shared between host and client interface. */
+        UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
+        pxa_set_ohci_info(&zeus_ohci_platform_data);
+}
 /*
 * Flat Panel
 */
@@ -677,6 +671,19 @@ static struct pxa2xx_udc_mach_info zeus_udc_info = {
        .udc_command = zeus_udc_command,
 };
+static struct platform_device *zeus_devices[] __initdata = {
+        &zeus_serial_device,
+        &zeus_mtd_devices[0],
+        &zeus_dm9k0_device,
+        &zeus_dm9k1_device,
+        &zeus_sram_device,
+        &zeus_leds_device,
+        &zeus_pcmcia_device,
+        &zeus_max6369_device,
+        &can_regulator_device,
+        &zeus_ohci_regulator_device,
+};
 #ifdef CONFIG_PM
 static void zeus_power_off(void)
 {
@@ -847,7 +854,7 @@ static void __init zeus_init(void)
        platform_add_devices(zeus_devices, ARRAY_SIZE(zeus_devices));
-        pxa_set_ohci_info(&zeus_ohci_platform_data);
+        zeus_register_ohci();
        if (zeus_setup_fb_gpios())
                pr_err("Failed to setup fb gpios\n");
diff --git a/arch/arm/mach-qcom/Kconfig b/arch/arm/mach-qcom/Kconfig
index a028be234334..fd2b99dceb89 100644
--- a/arch/arm/mach-qcom/Kconfig
+++ b/arch/arm/mach-qcom/Kconfig
@@ -2,9 +2,9 @@ config ARCH_QCOM
        bool "Qualcomm Support" if ARCH_MULTI_V7
        select ARCH_REQUIRE_GPIOLIB
        select ARM_GIC
+        select ARM_AMBA
        select CLKSRC_OF
-        select GENERIC_CLOCKEVENTS
+        select PINCTRL
-        select HAVE_SMP
        select QCOM_SCM if SMP
        help
          Support for Qualcomm's devicetree based systems.
diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c
index bae617ef0b31..c437a9941726 100644
--- a/arch/arm/mach-qcom/board.c
+++ b/arch/arm/mach-qcom/board.c
@@ -15,9 +15,11 @@
 #include <asm/mach/arch.h>
 static const char * const qcom_dt_match[] __initconst = {
+        "qcom,apq8064",
+        "qcom,apq8074-dragonboard",
+        "qcom,apq8084",
        "qcom,msm8660-surf",
        "qcom,msm8960-cdp",
-        "qcom,apq8074-dragonboard",
        NULL
 };
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 1d5ee5c9a1dc..8c1b39a0caa0 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -31,6 +31,7 @@
 #include <linux/amba/mmci.h>
 #include <linux/gfp.h>
 #include <linux/mtd/physmap.h>
+#include <linux/memblock.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -148,6 +149,21 @@ struct platform_device realview_cf_device = {
        },
 };
+static struct resource realview_leds_resources[] = {
+        {
+                .start  = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET,
+                .end    = REALVIEW_SYS_BASE + REALVIEW_SYS_LED_OFFSET + 4,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+struct platform_device realview_leds_device = {
+        .name           = "versatile-leds",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(realview_leds_resources),
+        .resource       = realview_leds_resources,
+};
 static struct resource realview_i2c_resource = {
        .start          = REALVIEW_I2C_BASE,
        .end            = REALVIEW_I2C_BASE + SZ_4K - 1,
@@ -370,19 +386,15 @@ void __init realview_timer_init(unsigned int timer_irq)
 /*
 * Setup the memory banks.
 */
-void realview_fixup(struct tag *tags, char **from, struct meminfo *meminfo)
+void realview_fixup(struct tag *tags, char **from)
 {
        /*
         * Most RealView platforms have 512MB contiguous RAM at 0x70000000.
         * Half of this is mirrored at 0.
         */
 #ifdef CONFIG_REALVIEW_HIGH_PHYS_OFFSET
-        meminfo->bank[0].start = 0x70000000;
+        memblock_add(0x70000000, SZ_512M);
-        meminfo->bank[0].size = SZ_512M;
-        meminfo->nr_banks = 1;
 #else
-        meminfo->bank[0].start = 0;
+        memblock_add(0, SZ_256M);
-        meminfo->bank[0].size = SZ_256M;
-        meminfo->nr_banks = 1;
 #endif
 }
diff --git a/arch/arm/mach-realview/core.h b/arch/arm/mach-realview/core.h
index 602ca5ec52c5..868ece221978 100644
--- a/arch/arm/mach-realview/core.h
+++ b/arch/arm/mach-realview/core.h
@@ -37,6 +37,7 @@ struct machine_desc;
 extern struct platform_device realview_flash_device;
 extern struct platform_device realview_cf_device;
+extern struct platform_device realview_leds_device;
 extern struct platform_device realview_i2c_device;
 extern struct mmci_platform_data realview_mmc0_plat_data;
 extern struct mmci_platform_data realview_mmc1_plat_data;
@@ -51,8 +52,7 @@ extern int realview_flash_register(struct resource *res, u32 num);
 extern int realview_eth_register(const char *name, struct resource *res);
 extern int realview_usb_register(struct resource *res);
 extern void realview_init_early(void);
-extern void realview_fixup(struct tag *tags, char **from,
+extern void realview_fixup(struct tag *tags, char **from);
-                           struct meminfo *meminfo);
 extern struct smp_operations realview_smp_ops;
 extern void realview_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index c85ddb2a0ad0..739d4f113097 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -442,8 +442,13 @@ static void __init realview_eb_init(void)
                realview_eb11mp_fixup();
 #ifdef CONFIG_CACHE_L2X0
-                /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+                /*
-                 * Bits:  .... ...0 0111 1001 0000 .... .... .... */
+                 * The PL220 needs to be manually configured as the hardware
+                 * doesn't report the correct sizes.
+                 * 1MB (128KB/way), 8-way associativity, event monitor and
+                 * parity enabled, ignore share bit, no force write allocate
+                 * Bits:  .... ...0 0111 1001 0000 .... .... ....
+                 */
                l2x0_init(__io_address(REALVIEW_EB11MP_L220_BASE), 0x00790000, 0xfe000fff);
 #endif
                platform_device_register(&pmu_device);
@@ -452,6 +457,7 @@ static void __init realview_eb_init(void)
        realview_flash_register(&realview_eb_flash_resource, 1);
        platform_device_register(&realview_i2c_device);
        platform_device_register(&char_lcd_device);
+        platform_device_register(&realview_leds_device);
        eth_device_register();
        realview_usb_register(realview_eb_isp1761_resources);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index c5eade76461b..b0e0dcaed944 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -32,6 +32,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <linux/reboot.h>
+#include <linux/memblock.h>
 #include <mach/hardware.h>
 #include <asm/irq.h>
@@ -339,15 +340,12 @@ static void realview_pb1176_restart(enum reboot_mode mode, const char *cmd)
        dsb();
 }
-static void realview_pb1176_fixup(struct tag *tags, char **from,
+static void realview_pb1176_fixup(struct tag *tags, char **from)
-                                  struct meminfo *meminfo)
 {
        /*
         * RealView PB1176 only has 128MB of RAM mapped at 0.
         */
-        meminfo->bank[0].start = 0;
+        memblock_add(0, SZ_128M);
-        meminfo->bank[0].size = SZ_128M;
-        meminfo->nr_banks = 1;
 }
 static void __init realview_pb1176_init(void)
@@ -355,7 +353,13 @@ static void __init realview_pb1176_init(void)
        int i;
 #ifdef CONFIG_CACHE_L2X0
-        /* 128Kb (16Kb/way) 8-way associativity. evmon/parity/share enabled. */
+        /*
+         * The PL220 needs to be manually configured as the hardware
+         * doesn't report the correct sizes.
+         * 128kB (16kB/way), 8-way associativity, event monitor and
+         * parity enabled, ignore share bit, no force write allocate
+         * Bits:  .... ...0 0111 0011 0000 .... .... ....
+         */
        l2x0_init(__io_address(REALVIEW_PB1176_L220_BASE), 0x00730000, 0xfe000fff);
 #endif
@@ -367,6 +371,7 @@ static void __init realview_pb1176_init(void)
        realview_usb_register(realview_pb1176_isp1761_resources);
        platform_device_register(&pmu_device);
        platform_device_register(&char_lcd_device);
+        platform_device_register(&realview_leds_device);
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index f4b0962578fe..47bf55fdbf27 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -337,8 +337,13 @@ static void __init realview_pb11mp_init(void)
        int i;
 #ifdef CONFIG_CACHE_L2X0
-        /* 1MB (128KB/way), 8-way associativity, evmon/parity/share enabled
+        /*
-         * Bits:  .... ...0 0111 1001 0000 .... .... .... */
+         * The PL220 needs to be manually configured as the hardware
+         * doesn't report the correct sizes.
+         * 1MB (128KB/way), 8-way associativity, event monitor and
+         * parity enabled, ignore share bit, no force write allocate
+         * Bits:  .... ...0 0111 1001 0000 .... .... ....
+         */
        l2x0_init(__io_address(REALVIEW_TC11MP_L220_BASE), 0x00790000, 0xfe000fff);
 #endif
@@ -347,6 +352,7 @@ static void __init realview_pb11mp_init(void)
        realview_eth_register(NULL, realview_pb11mp_smsc911x_resources);
        platform_device_register(&realview_i2c_device);
        platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
        realview_usb_register(realview_pb11mp_isp1761_resources);
        platform_device_register(&pmu_device);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 10a3e1d76891..4e57a8599265 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -289,6 +289,7 @@ static void __init realview_pba8_init(void)
        realview_eth_register(NULL, realview_pba8_smsc911x_resources);
        platform_device_register(&realview_i2c_device);
        platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
        realview_usb_register(realview_pba8_isp1761_resources);
        platform_device_register(&pmu_device);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 9d75493e3f0c..d89eb4023467 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -29,6 +29,7 @@
 #include <linux/irqchip/arm-gic.h>
 #include <linux/platform_data/clk-realview.h>
 #include <linux/reboot.h>
+#include <linux/memblock.h>
 #include <asm/irq.h>
 #include <asm/mach-types.h>
@@ -325,23 +326,19 @@ static void __init realview_pbx_timer_init(void)
        realview_pbx_twd_init();
 }
-static void realview_pbx_fixup(struct tag *tags, char **from,
+static void realview_pbx_fixup(struct tag *tags, char **from)
-                               struct meminfo *meminfo)
 {
 #ifdef CONFIG_SPARSEMEM
        /*
         * Memory configuration with SPARSEMEM enabled on RealView PBX (see
         * asm/mach/memory.h for more information).
         */
-        meminfo->bank[0].start = 0;
-        meminfo->bank[0].size = SZ_256M;
+        memblock_add(0, SZ_256M);
-        meminfo->bank[1].start = 0x20000000;
+        memblock_add(0x20000000, SZ_512M);
-        meminfo->bank[1].size = SZ_512M;
+        memblock_add(0x80000000, SZ_256M);
-        meminfo->bank[2].start = 0x80000000;
-        meminfo->bank[2].size = SZ_256M;
-        meminfo->nr_banks = 3;
 #else
-        realview_fixup(tags, from, meminfo);
+        realview_fixup(tags, from);
 #endif
 }
@@ -370,8 +367,8 @@ static void __init realview_pbx_init(void)
                        __io_address(REALVIEW_PBX_TILE_L220_BASE);
                /* set RAM latencies to 1 cycle for eASIC */
-                writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
+                writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
-                writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
+                writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
                /* 16KB way size, 8-way associativity, parity disabled
                 * Bits:  .. 0 0 0 0 1 00 1 0 1 001 0 000 0 .... .... .... */
@@ -385,6 +382,7 @@ static void __init realview_pbx_init(void)
        realview_eth_register(NULL, realview_pbx_smsc911x_resources);
        platform_device_register(&realview_i2c_device);
        platform_device_register(&realview_cf_device);
+        platform_device_register(&realview_leds_device);
        realview_usb_register(realview_pbx_isp1761_resources);
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
diff --git a/arch/arm/mach-rockchip/core.h b/arch/arm/mach-rockchip/core.h
index e2e7c9dbb200..39bca96b555a 100644
--- a/arch/arm/mach-rockchip/core.h
+++ b/arch/arm/mach-rockchip/core.h
@@ -18,5 +18,3 @@ extern char rockchip_secondary_trampoline_end;
 extern unsigned long rockchip_boot_fn;
 extern void rockchip_secondary_startup(void);
-extern struct smp_operations rockchip_smp_ops;
diff --git a/arch/arm/mach-rockchip/platsmp.c b/arch/arm/mach-rockchip/platsmp.c
index 072842f6491b..910835d4ccf4 100644
--- a/arch/arm/mach-rockchip/platsmp.c
+++ b/arch/arm/mach-rockchip/platsmp.c
@@ -178,7 +178,8 @@ static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
                pmu_set_power_domain(0 + i, false);
 }
-struct smp_operations rockchip_smp_ops __initdata = {
+static struct smp_operations rockchip_smp_ops __initdata = {
        .smp_prepare_cpus       = rockchip_smp_prepare_cpus,
        .smp_boot_secondary     = rockchip_boot_secondary,
 };
+CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index d211d6fa0d98..968cc348e624 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -24,12 +24,6 @@
 #include <asm/hardware/cache-l2x0.h>
 #include "core.h"
-static void __init rockchip_dt_init(void)
-{
-        l2x0_of_init(0, ~0UL);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const rockchip_board_dt_compat[] = {
        "rockchip,rk2928",
        "rockchip,rk3066a",
@@ -39,7 +33,7 @@ static const char * const rockchip_board_dt_compat[] = {
 };
 DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
-        .smp            = smp_ops(rockchip_smp_ops),
+        .l2c_aux_val    = 0,
-        .init_machine   = rockchip_dt_init,
+        .l2c_aux_mask   = ~0,
        .dt_compat      = rockchip_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 40cf50b9940c..04284de7aca5 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -18,6 +18,8 @@ config PLAT_S3C24XX
        help
          Base platform code for any Samsung S3C24XX device
 menu "SAMSUNG S3C24XX SoCs Support"
 comment "S3C24XX SoCs"
@@ -26,8 +28,7 @@ config CPU_S3C2410
        bool "SAMSUNG S3C2410"
        default y
        select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2410
+        select S3C2410_COMMON_CLK
-        select S3C2410_CLOCK
        select S3C2410_DMA if S3C24XX_DMA
        select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
        select S3C2410_PM if PM
@@ -39,7 +40,7 @@ config CPU_S3C2410
 config CPU_S3C2412
        bool "SAMSUNG S3C2412"
        select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
+        select S3C2412_COMMON_CLK
        select S3C2412_DMA if S3C24XX_DMA
        select S3C2412_PM if PM
        help
@@ -48,19 +49,16 @@ config CPU_S3C2412
 config CPU_S3C2416
        bool "SAMSUNG S3C2416/S3C2450"
        select CPU_ARM926T
-        select CPU_LLSERIAL_S3C2440
        select S3C2416_PM if PM
-        select S3C2443_COMMON
+        select S3C2443_COMMON_CLK
        select S3C2443_DMA if S3C24XX_DMA
-        select SAMSUNG_CLKSRC
        help
          Support for the S3C2416 SoC from the S3C24XX line
 config CPU_S3C2440
        bool "SAMSUNG S3C2440"
        select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
+        select S3C2410_COMMON_CLK
-        select S3C2410_CLOCK
        select S3C2410_PM if PM
        select S3C2440_DMA if S3C24XX_DMA
        help
@@ -69,8 +67,7 @@ config CPU_S3C2440
 config CPU_S3C2442
        bool "SAMSUNG S3C2442"
        select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
+        select S3C2410_COMMON_CLK
-        select S3C2410_CLOCK
        select S3C2410_DMA if S3C24XX_DMA
        select S3C2410_PM if PM
        help
@@ -84,26 +81,13 @@ config CPU_S3C244X
 config CPU_S3C2443
        bool "SAMSUNG S3C2443"
        select CPU_ARM920T
-        select CPU_LLSERIAL_S3C2440
+        select S3C2443_COMMON_CLK
-        select S3C2443_COMMON
        select S3C2443_DMA if S3C24XX_DMA
-        select SAMSUNG_CLKSRC
        help
          Support for the S3C2443 SoC from the S3C24XX line
 # common code
-config S3C2410_CLOCK
-        bool
-        help
-          Clock code for the S3C2410, and similar processors which
-          is currently includes the S3C2410, S3C2440, S3C2442.
-config S3C24XX_DCLK
-        bool
-        help
-          Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
 config S3C24XX_SMDK
        bool
        help
@@ -158,28 +142,6 @@ config S3C2410_PM
        help
          Power Management code common to S3C2410 and better
-# low-level serial option nodes
-config CPU_LLSERIAL_S3C2410_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2410 && !CPU_LLSERIAL_S3C2440
-config CPU_LLSERIAL_S3C2440_ONLY
-        bool
-        default y if CPU_LLSERIAL_S3C2440 && !CPU_LLSERIAL_S3C2410
-config CPU_LLSERIAL_S3C2410
-        bool
-        help
-          Selected if there is an S3C2410 (or register compatible) serial
-          low-level implementation needed
-config CPU_LLSERIAL_S3C2440
-        bool
-        help
-          Selected if there is an S3C2440 (or register compatible) serial
-          low-level implementation needed
 config S3C24XX_PLL
        bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
        depends on ARM_S3C24XX_CPUFREQ
@@ -258,8 +220,8 @@ config ARCH_BAST
        bool "Simtec Electronics BAST (EB2410ITX)"
        select ISA
        select MACH_BAST_IDE
+        select S3C2410_COMMON_DCLK
        select S3C2410_IOTIMING if ARM_S3C2410_CPUFREQ
-        select S3C24XX_DCLK
        select S3C24XX_SIMTEC_NOR
        select S3C24XX_SIMTEC_PM if PM
        select S3C24XX_SIMTEC_USB
@@ -340,7 +302,7 @@ config MACH_TCT_HAMMER
 config MACH_VR1000
        bool "Thorcom VR1000"
        select MACH_BAST_IDE
-        select S3C24XX_DCLK
+        select S3C2410_COMMON_DCLK
        select S3C24XX_SIMTEC_NOR
        select S3C24XX_SIMTEC_PM if PM
        select S3C24XX_SIMTEC_USB
@@ -519,8 +481,8 @@ comment "S3C2440 Boards"
 config MACH_ANUBIS
        bool "Simtec Electronics ANUBIS"
        select HAVE_PATA_PLATFORM
+        select S3C2410_COMMON_DCLK
        select S3C2440_XTAL_12000000
-        select S3C24XX_DCLK
        select S3C24XX_SIMTEC_PM if PM
        select S3C_DEV_USB_HOST
        help
@@ -558,9 +520,9 @@ config MACH_NEXCODER_2440
 config MACH_OSIRIS
        bool "Simtec IM2440D20 (OSIRIS) module"
+        select S3C2410_COMMON_DCLK
        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
        select S3C2440_XTAL_12000000
-        select S3C24XX_DCLK
        select S3C24XX_SIMTEC_PM if PM
        select S3C_DEV_NAND
        select S3C_DEV_USB_HOST
@@ -629,9 +591,9 @@ config MACH_RX1950
        bool "HP iPAQ rx1950"
        select I2C
        select PM_H1940 if PM
+        select S3C2410_COMMON_DCLK
        select S3C2410_IOTIMING if ARM_S3C2440_CPUFREQ
        select S3C2440_XTAL_16934400
-        select S3C24XX_DCLK
        select S3C24XX_PWM
        select S3C_DEV_NAND
        help
@@ -641,12 +603,6 @@ endif	# CPU_S3C2442
 if CPU_S3C2443 || CPU_S3C2416
-config S3C2443_COMMON
-        bool
-        help
-          Common code for the S3C2443 and similar processors, which includes
-          the S3C2416 and S3C2450.
 config S3C2443_DMA
        bool
        help
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 7f54e5b954ca..2235d0d3b38d 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -21,22 +21,22 @@ obj-$(CONFIG_S3C2410_DMA)	+= dma-s3c2410.o
 obj-$(CONFIG_S3C2410_PLL)       += pll-s3c2410.o
 obj-$(CONFIG_S3C2410_PM)        += pm-s3c2410.o sleep-s3c2410.o
-obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o clock-s3c2412.o
+obj-$(CONFIG_CPU_S3C2412)       += s3c2412.o
 obj-$(CONFIG_S3C2412_DMA)       += dma-s3c2412.o
 obj-$(CONFIG_S3C2412_PM)        += pm-s3c2412.o
 obj-$(CONFIG_S3C2412_PM_SLEEP)  += sleep-s3c2412.o
-obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o clock-s3c2416.o
+obj-$(CONFIG_CPU_S3C2416)       += s3c2416.o
 obj-$(CONFIG_S3C2416_PM)        += pm-s3c2416.o
-obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o clock-s3c2440.o
+obj-$(CONFIG_CPU_S3C2440)       += s3c2440.o
 obj-$(CONFIG_CPU_S3C2442)       += s3c2442.o
-obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o clock-s3c244x.o
+obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
 obj-$(CONFIG_S3C2440_DMA)       += dma-s3c2440.o
 obj-$(CONFIG_S3C2440_PLL_12000000) += pll-s3c2440-12000000.o
 obj-$(CONFIG_S3C2440_PLL_16934400) += pll-s3c2440-16934400.o
-obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o clock-s3c2443.o
+obj-$(CONFIG_CPU_S3C2443)       += s3c2443.o
 # PM
@@ -44,16 +44,13 @@ obj-$(CONFIG_PM)		+= pm.o irq-pm.o sleep.o
 # common code
-obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
 obj-$(CONFIG_S3C24XX_DMA)       += dma.o
-obj-$(CONFIG_S3C2410_CLOCK)     += clock-s3c2410.o
 obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += cpufreq-utils.o
 obj-$(CONFIG_S3C2410_IOTIMING)  += iotiming-s3c2410.o
 obj-$(CONFIG_S3C2412_IOTIMING)  += iotiming-s3c2412.o
-obj-$(CONFIG_S3C2443_COMMON)    += common-s3c2443.o
 obj-$(CONFIG_S3C2443_DMA)       += dma-s3c2443.o
 #
diff --git a/arch/arm/mach-s3c24xx/clock-dclk.c b/arch/arm/mach-s3c24xx/clock-dclk.c
deleted file mode 100644
index 1edd9b2369c5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-dclk.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * Copyright (c) 2004-2008 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24XX - definitions for DCLK and CLKOUT registers
- */
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-/* clocks that could be registered by external code */
-static int s3c24xx_dclk_enable(struct clk *clk, int enable)
-{
-        unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
-        if (enable)
-                dclkcon |= clk->ctrlbit;
-        else
-                dclkcon &= ~clk->ctrlbit;
-        __raw_writel(dclkcon, S3C24XX_DCLKCON);
-        return 0;
-}
-static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
-{
-        unsigned long dclkcon;
-        unsigned int uclk;
-        if (parent == &clk_upll)
-                uclk = 1;
-        else if (parent == &clk_p)
-                uclk = 0;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        dclkcon = __raw_readl(S3C24XX_DCLKCON);
-        if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
-                if (uclk)
-                        dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
-                else
-                        dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
-        } else {
-                if (uclk)
-                        dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
-                else
-                        dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
-        }
-        __raw_writel(dclkcon, S3C24XX_DCLKCON);
-        return 0;
-}
-static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
-{
-        unsigned long div;
-        if ((rate == 0) || !clk->parent)
-                return 0;
-        div = clk_get_rate(clk->parent) / rate;
-        if (div < 2)
-                div = 2;
-        else if (div > 16)
-                div = 16;
-        return div;
-}
-static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
-        unsigned long rate)
-{
-        unsigned long div = s3c24xx_calc_div(clk, rate);
-        if (div == 0)
-                return 0;
-        return clk_get_rate(clk->parent) / div;
-}
-static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
-{
-        unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
-        if (div == 0)
-                return -EINVAL;
-        if (clk == &s3c24xx_dclk0) {
-                mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
-                        S3C2410_DCLKCON_DCLK0_CMP_MASK;
-                data = S3C2410_DCLKCON_DCLK0_DIV(div) |
-                        S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
-        } else if (clk == &s3c24xx_dclk1) {
-                mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
-                        S3C2410_DCLKCON_DCLK1_CMP_MASK;
-                data = S3C2410_DCLKCON_DCLK1_DIV(div) |
-                        S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
-        } else
-                return -EINVAL;
-        clk->rate = clk_get_rate(clk->parent) / div;
-        __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
-                S3C24XX_DCLKCON);
-        return clk->rate;
-}
-static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
-{
-        unsigned long mask;
-        unsigned long source;
-        /* calculate the MISCCR setting for the clock */
-        if (parent == &clk_mpll)
-                source = S3C2410_MISCCR_CLK0_MPLL;
-        else if (parent == &clk_upll)
-                source = S3C2410_MISCCR_CLK0_UPLL;
-        else if (parent == &clk_f)
-                source = S3C2410_MISCCR_CLK0_FCLK;
-        else if (parent == &clk_h)
-                source = S3C2410_MISCCR_CLK0_HCLK;
-        else if (parent == &clk_p)
-                source = S3C2410_MISCCR_CLK0_PCLK;
-        else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
-                source = S3C2410_MISCCR_CLK0_DCLK0;
-        else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
-                source = S3C2410_MISCCR_CLK0_DCLK0;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        if (clk == &s3c24xx_clkout0)
-                mask = S3C2410_MISCCR_CLK0_MASK;
-        else {
-                source <<= 4;
-                mask = S3C2410_MISCCR_CLK1_MASK;
-        }
-        s3c2410_modify_misccr(mask, source);
-        return 0;
-}
-/* external clock definitions */
-static struct clk_ops dclk_ops = {
-        .set_parent     = s3c24xx_dclk_setparent,
-        .set_rate       = s3c24xx_set_dclk_rate,
-        .round_rate     = s3c24xx_round_dclk_rate,
-};
-struct clk s3c24xx_dclk0 = {
-        .name           = "dclk0",
-        .ctrlbit        = S3C2410_DCLKCON_DCLK0EN,
-        .enable         = s3c24xx_dclk_enable,
-        .ops            = &dclk_ops,
-};
-struct clk s3c24xx_dclk1 = {
-        .name           = "dclk1",
-        .ctrlbit        = S3C2410_DCLKCON_DCLK1EN,
-        .enable         = s3c24xx_dclk_enable,
-        .ops            = &dclk_ops,
-};
-static struct clk_ops clkout_ops = {
-        .set_parent     = s3c24xx_clkout_setparent,
-};
-struct clk s3c24xx_clkout0 = {
-        .name           = "clkout0",
-        .ops            = &clkout_ops,
-};
-struct clk s3c24xx_clkout1 = {
-        .name           = "clkout1",
-        .ops            = &clkout_ops,
-};
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
deleted file mode 100644
index d1afcf9252d1..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ /dev/null
@@ -1,284 +0,0 @@
-/*
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410,S3C2440,S3C2442 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-int s3c2410_clkcon_enable(struct clk *clk, int enable)
-{
-        unsigned int clocks = clk->ctrlbit;
-        unsigned long clkcon;
-        clkcon = __raw_readl(S3C2410_CLKCON);
-        if (enable)
-                clkcon |= clocks;
-        else
-                clkcon &= ~clocks;
-        /* ensure none of the special function bits set */
-        clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
-        __raw_writel(clkcon, S3C2410_CLKCON);
-        return 0;
-}
-static int s3c2410_upll_enable(struct clk *clk, int enable)
-{
-        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
-        unsigned long orig = clkslow;
-        if (enable)
-                clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
-        else
-                clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
-        __raw_writel(clkslow, S3C2410_CLKSLOW);
-        /* if we started the UPLL, then allow to settle */
-        if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
-                udelay(200);
-        return 0;
-}
-/* standard clock definitions */
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_h,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_NAND,
-        }, {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_SDI,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_IIC,
-        }, {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_IIS,
-        }, {
-                .name           = "spi",
-                .parent         = &clk_p,
-                .enable         = s3c2410_clkcon_enable,
-                .ctrlbit        = S3C2410_CLKCON_SPI,
-        }
-};
-static struct clk clk_lcd = {
-        .name           = "lcd",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_LCDC,
-};
-static struct clk clk_gpio = {
-        .name           = "gpio",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_GPIO,
-};
-static struct clk clk_usb_host = {
-        .name           = "usb-host",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_USBH,
-};
-static struct clk clk_usb_device = {
-        .name           = "usb-device",
-        .parent         = &clk_h,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_USBD,
-};
-static struct clk clk_timers = {
-        .name           = "timers",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_PWMT,
-};
-struct clk s3c24xx_clk_uart0 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.0",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART0,
-};
-struct clk s3c24xx_clk_uart1 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.1",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART1,
-};
-struct clk s3c24xx_clk_uart2 = {
-        .name           = "uart",
-        .devname        = "s3c2410-uart.2",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_UART2,
-};
-static struct clk clk_rtc = {
-        .name           = "rtc",
-        .parent         = &clk_p,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2410_CLKCON_RTC,
-};
-static struct clk clk_watchdog = {
-        .name           = "watchdog",
-        .parent         = &clk_p,
-        .ctrlbit        = 0,
-};
-static struct clk clk_usb_bus_host = {
-        .name           = "usb-bus-host",
-        .parent         = &clk_usb_bus,
-};
-static struct clk clk_usb_bus_gadget = {
-        .name           = "usb-bus-gadget",
-        .parent         = &clk_usb_bus,
-};
-static struct clk *init_clocks[] = {
-        &clk_lcd,
-        &clk_gpio,
-        &clk_usb_host,
-        &clk_usb_device,
-        &clk_timers,
-        &s3c24xx_clk_uart0,
-        &s3c24xx_clk_uart1,
-        &s3c24xx_clk_uart2,
-        &clk_rtc,
-        &clk_watchdog,
-        &clk_usb_bus_host,
-        &clk_usb_bus_gadget,
-};
-/* s3c2410_baseclk_add()
- *
- * Add all the clocks used by the s3c2410 or compatible CPUs
- * such as the S3C2440 and S3C2442.
- *
- * We cannot use a system device as we are needed before any
- * of the init-calls that initialise the devices are actually
- * done.
-*/
-int __init s3c2410_baseclk_add(void)
-{
-        unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
-        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
-        struct clk *xtal;
-        int ret;
-        int ptr;
-        clk_upll.enable = s3c2410_upll_enable;
-        if (s3c24xx_register_clock(&clk_usb_bus) < 0)
-                printk(KERN_ERR "failed to register usb bus clock\n");
-        /* register clocks from clock array */
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
-                struct clk *clkp = init_clocks[ptr];
-                /* ensure that we note the clock state */
-                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-        /* install (and disable) the clocks we do not need immediately */
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        /* show the clock-slow value */
-        xtal = clk_get(NULL, "xtal");
-        printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
-               print_mhz(clk_get_rate(xtal) /
-                         ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
-               (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
-               (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
-               (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
-        return 0;
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
deleted file mode 100644
index 192a5b2550b0..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ /dev/null
@@ -1,760 +0,0 @@
-/* linux/arch/arm/mach-s3c2412/clock.c
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2412,S3C2413 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/delay.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <linux/io.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-gpio.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-/* We currently have to assume that the system is running
- * from the XTPll input, and that all ***REFCLKs are being
- * fed from it, as we cannot read the state of OM[4] from
- * software.
- *
- * It would be possible for each board initialisation to
- * set the correct muxing at initialisation
-*/
-static int s3c2412_clkcon_enable(struct clk *clk, int enable)
-{
-        unsigned int clocks = clk->ctrlbit;
-        unsigned long clkcon;
-        clkcon = __raw_readl(S3C2410_CLKCON);
-        if (enable)
-                clkcon |= clocks;
-        else
-                clkcon &= ~clocks;
-        __raw_writel(clkcon, S3C2410_CLKCON);
-        return 0;
-}
-static int s3c2412_upll_enable(struct clk *clk, int enable)
-{
-        unsigned long upllcon = __raw_readl(S3C2410_UPLLCON);
-        unsigned long orig = upllcon;
-        if (!enable)
-                upllcon |= S3C2412_PLLCON_OFF;
-        else
-                upllcon &= ~S3C2412_PLLCON_OFF;
-        __raw_writel(upllcon, S3C2410_UPLLCON);
-        /* allow ~150uS for the PLL to settle and lock */
-        if (enable && (orig & S3C2412_PLLCON_OFF))
-                udelay(150);
-        return 0;
-}
-/* clock selections */
-static struct clk clk_erefclk = {
-        .name           = "erefclk",
-};
-static struct clk clk_urefclk = {
-        .name           = "urefclk",
-};
-static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_urefclk)
-                clksrc &= ~S3C2412_CLKSRC_USYSCLK_UPLL;
-        else if (parent == &clk_upll)
-                clksrc |= S3C2412_CLKSRC_USYSCLK_UPLL;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static struct clk clk_usysclk = {
-        .name           = "usysclk",
-        .parent         = &clk_xtal,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_usysclk,
-        },
-};
-static struct clk clk_mrefclk = {
-        .name           = "mrefclk",
-        .parent         = &clk_xtal,
-};
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_xtal,
-};
-static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_usysclk)
-                clksrc &= ~S3C2412_CLKSRC_USBCLK_HCLK;
-        else if (parent == &clk_h)
-                clksrc |= S3C2412_CLKSRC_USBCLK_HCLK;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static unsigned long s3c2412_roundrate_usbsrc(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-        if (rate > parent_rate)
-                return parent_rate;
-        div = parent_rate / rate;
-        if (div > 2)
-                div = 2;
-        return parent_rate / div;
-}
-static unsigned long s3c2412_getrate_usbsrc(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-        return parent_rate / ((div & S3C2412_CLKDIVN_USB48DIV) ? 2 : 1);
-}
-static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-        rate = s3c2412_roundrate_usbsrc(clk, rate);
-        if ((parent_rate / rate) == 2)
-                clkdivn |= S3C2412_CLKDIVN_USB48DIV;
-        else
-                clkdivn &= ~S3C2412_CLKDIVN_USB48DIV;
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-static struct clk clk_usbsrc = {
-        .name           = "usbsrc",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_usbsrc,
-                .set_rate       = s3c2412_setrate_usbsrc,
-                .round_rate     = s3c2412_roundrate_usbsrc,
-                .set_parent     = s3c2412_setparent_usbsrc,
-        },
-};
-static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_mdivclk)
-                clksrc &= ~S3C2412_CLKSRC_MSYSCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_MSYSCLK_MPLL;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static struct clk clk_msysclk = {
-        .name           = "msysclk",
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_msysclk,
-        },
-};
-static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long flags;
-        unsigned long clkdiv;
-        unsigned long dvs;
-        /* Note, we current equate fclk andf msysclk for S3C2412 */
-        if (parent == &clk_msysclk || parent == &clk_f)
-                dvs = 0;
-        else if (parent == &clk_h)
-                dvs = S3C2412_CLKDIVN_DVSEN;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        /* update this under irq lockdown, clkdivn is not protected
-         * by the clock system. */
-        local_irq_save(flags);
-        clkdiv  = __raw_readl(S3C2410_CLKDIVN);
-        clkdiv &= ~S3C2412_CLKDIVN_DVSEN;
-        clkdiv |= dvs;
-        __raw_writel(clkdiv, S3C2410_CLKDIVN);
-        local_irq_restore(flags);
-        return 0;
-}
-static struct clk clk_armclk = {
-        .name           = "armclk",
-        .parent         = &clk_msysclk,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2412_setparent_armclk,
-        },
-};
-/* these next clocks have an divider immediately after them,
- * so we can register them with their divider and leave out the
- * intermediate clock stage
-*/
-static unsigned long s3c2412_roundrate_clksrc(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-        if (rate > parent_rate)
-                return parent_rate;
-        /* note, we remove the +/- 1 calculations as they cancel out */
-        div = (rate / parent_rate);
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-        return parent_rate / div;
-}
-static int s3c2412_setparent_uart(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_erefclk)
-                clksrc &= ~S3C2412_CLKSRC_UARTCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_UARTCLK_MPLL;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static unsigned long s3c2412_getrate_uart(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-        div &= S3C2412_CLKDIVN_UARTDIV_MASK;
-        div >>= S3C2412_CLKDIVN_UARTDIV_SHIFT;
-        return parent_rate / (div + 1);
-}
-static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-        clkdivn &= ~S3C2412_CLKDIVN_UARTDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_UARTDIV_SHIFT;
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-static struct clk clk_uart = {
-        .name           = "uartclk",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_uart,
-                .set_rate       = s3c2412_setrate_uart,
-                .set_parent     = s3c2412_setparent_uart,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-static int s3c2412_setparent_i2s(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_erefclk)
-                clksrc &= ~S3C2412_CLKSRC_I2SCLK_MPLL;
-        else if (parent == &clk_mpll)
-                clksrc |= S3C2412_CLKSRC_I2SCLK_MPLL;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static unsigned long s3c2412_getrate_i2s(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-        div &= S3C2412_CLKDIVN_I2SDIV_MASK;
-        div >>= S3C2412_CLKDIVN_I2SDIV_SHIFT;
-        return parent_rate / (div + 1);
-}
-static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-        clkdivn &= ~S3C2412_CLKDIVN_I2SDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_I2SDIV_SHIFT;
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-static struct clk clk_i2s = {
-        .name           = "i2sclk",
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_i2s,
-                .set_rate       = s3c2412_setrate_i2s,
-                .set_parent     = s3c2412_setparent_i2s,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-static int s3c2412_setparent_cam(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        if (parent == &clk_usysclk)
-                clksrc &= ~S3C2412_CLKSRC_CAMCLK_HCLK;
-        else if (parent == &clk_h)
-                clksrc |= S3C2412_CLKSRC_CAMCLK_HCLK;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        __raw_writel(clksrc, S3C2412_CLKSRC);
-        return 0;
-}
-static unsigned long s3c2412_getrate_cam(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2410_CLKDIVN);
-        div &= S3C2412_CLKDIVN_CAMDIV_MASK;
-        div >>= S3C2412_CLKDIVN_CAMDIV_SHIFT;
-        return parent_rate / (div + 1);
-}
-static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long clkdivn = __raw_readl(S3C2410_CLKDIVN);
-        rate = s3c2412_roundrate_clksrc(clk, rate);
-        clkdivn &= ~S3C2412_CLKDIVN_CAMDIV_MASK;
-        clkdivn |= ((parent_rate / rate) - 1) << S3C2412_CLKDIVN_CAMDIV_SHIFT;
-        __raw_writel(clkdivn, S3C2410_CLKDIVN);
-        return 0;
-}
-static struct clk clk_cam = {
-        .name           = "camif-upll", /* same as 2440 name */
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2412_getrate_cam,
-                .set_rate       = s3c2412_setrate_cam,
-                .set_parent     = s3c2412_setparent_cam,
-                .round_rate     = s3c2412_roundrate_clksrc,
-        },
-};
-/* standard clock definitions */
-static struct clk init_clocks_disable[] = {
-        {
-                .name           = "nand",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_NAND,
-        }, {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_SDI,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_IIC,
-        }, {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_IIS,
-        }, {
-                .name           = "spi",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_SPI,
-        }
-};
-static struct clk init_clocks[] = {
-        {
-                .name           = "dma.0",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA0,
-        }, {
-                .name           = "dma.1",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA1,
-        }, {
-                .name           = "dma.2",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA2,
-        }, {
-                .name           = "dma.3",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_DMA3,
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_LCDC,
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .parent         = &clk_h,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USBD,
-        }, {
-                .name           = "timers",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_PWMT,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.0",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.1",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2412-uart.2",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_UART2,
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_p,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_p,
-                .ctrlbit        = 0,
-        }, {
-                .name           = "usb-bus-gadget",
-                .parent         = &clk_usb_bus,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USB_DEV48,
-        }, {
-                .name           = "usb-bus-host",
-                .parent         = &clk_usb_bus,
-                .enable         = s3c2412_clkcon_enable,
-                .ctrlbit        = S3C2412_CLKCON_USB_HOST48,
-        }
-};
-/* clocks to add where we need to check their parentage */
-struct clk_init {
-        struct clk      *clk;
-        unsigned int     bit;
-        struct clk      *src_0;
-        struct clk      *src_1;
-};
-static struct clk_init clks_src[] __initdata = {
-        {
-                .clk    = &clk_usysclk,
-                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
-                .src_0  = &clk_urefclk,
-                .src_1  = &clk_upll,
-        }, {
-                .clk    = &clk_i2s,
-                .bit    = S3C2412_CLKSRC_I2SCLK_MPLL,
-                .src_0  = &clk_erefclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_cam,
-                .bit    = S3C2412_CLKSRC_CAMCLK_HCLK,
-                .src_0  = &clk_usysclk,
-                .src_1  = &clk_h,
-        }, {
-                .clk    = &clk_msysclk,
-                .bit    = S3C2412_CLKSRC_MSYSCLK_MPLL,
-                .src_0  = &clk_mdivclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_uart,
-                .bit    = S3C2412_CLKSRC_UARTCLK_MPLL,
-                .src_0  = &clk_erefclk,
-                .src_1  = &clk_mpll,
-        }, {
-                .clk    = &clk_usbsrc,
-                .bit    = S3C2412_CLKSRC_USBCLK_HCLK,
-                .src_0  = &clk_usysclk,
-                .src_1  = &clk_h,
-        /* here we assume  OM[4] select xtal */
-        }, {
-                .clk    = &clk_erefclk,
-                .bit    = S3C2412_CLKSRC_EREFCLK_EXTCLK,
-                .src_0  = &clk_xtal,
-                .src_1  = &clk_ext,
-        }, {
-                .clk    = &clk_urefclk,
-                .bit    = S3C2412_CLKSRC_UREFCLK_EXTCLK,
-                .src_0  = &clk_xtal,
-                .src_1  = &clk_ext,
-        },
-};
-/* s3c2412_clk_initparents
- *
- * Initialise the parents for the clocks that we get at start-time
-*/
-static void __init s3c2412_clk_initparents(void)
-{
-        unsigned long clksrc = __raw_readl(S3C2412_CLKSRC);
-        struct clk_init *cip = clks_src;
-        struct clk *src;
-        int ptr;
-        int ret;
-        for (ptr = 0; ptr < ARRAY_SIZE(clks_src); ptr++, cip++) {
-                ret = s3c24xx_register_clock(cip->clk);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               cip->clk->name, ret);
-                }
-                src = (clksrc & cip->bit) ? cip->src_1 : cip->src_0;
-                printk(KERN_INFO "%s: parent %s\n", cip->clk->name, src->name);
-                clk_set_parent(cip->clk, src);
-        }
-}
-/* clocks to add straight away */
-static struct clk *clks[] __initdata = {
-        &clk_ext,
-        &clk_usb_bus,
-        &clk_mrefclk,
-        &clk_armclk,
-};
-static struct clk_lookup s3c2412_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_usysclk),
-};
-int __init s3c2412_baseclk_add(void)
-{
-        unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
-        unsigned int dvs;
-        struct clk *clkp;
-        int ret;
-        int ptr;
-        clk_upll.enable = s3c2412_upll_enable;
-        clk_usb_bus.parent = &clk_usbsrc;
-        clk_usb_bus.rate = 0x0;
-        clk_f.parent = &clk_msysclk;
-        s3c2412_clk_initparents();
-        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
-                clkp = clks[ptr];
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-        /* set the dvs state according to what we got at boot time */
-        dvs = __raw_readl(S3C2410_CLKDIVN) & S3C2412_CLKDIVN_DVSEN;
-        if (dvs)
-                clk_armclk.parent = &clk_h;
-        printk(KERN_INFO "S3C2412: DVS is %s\n", dvs ? "on" : "off");
-        /* ensure usb bus clock is within correct rate of 48MHz */
-        if (clk_get_rate(&clk_usb_bus) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB bus clock not at 48MHz\n");
-                /* for the moment, let's use the UPLL, and see if we can
-                 * get 48MHz */
-                clk_set_parent(&clk_usysclk, &clk_upll);
-                clk_set_parent(&clk_usbsrc, &clk_usysclk);
-                clk_set_rate(&clk_usbsrc, 48*1000*1000);
-        }
-        printk("S3C2412: upll %s, %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (__raw_readl(S3C2410_UPLLCON) & S3C2412_PLLCON_OFF) ? "off":"on",
-               print_mhz(clk_get_rate(&clk_upll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-        /* register clocks from clock array */
-        clkp = init_clocks;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
-                /* ensure that we note the clock state */
-                clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-        }
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-        /* install (and disable) the clocks we do not need immediately */
-        clkp = init_clocks_disable;
-        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
-                ret = s3c24xx_register_clock(clkp);
-                if (ret < 0) {
-                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
-                               clkp->name, ret);
-                }
-                s3c2412_clkcon_enable(clkp, 0);
-        }
-        clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
-        return 0;
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
deleted file mode 100644
index d421a72920a5..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/* linux/arch/arm/mach-s3c2416/clock.c
- *
- * Copyright (c) 2010 Simtec Electronics
- * Copyright (c) 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * S3C2416 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq.h>
-#include <plat/pll.h>
-#include <asm/mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-s3c2443-clock.h>
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
- * The real clock definition is done in s3c2443-clock.c,
- * only the armdiv divisor table must be defined here.
-*/
-static unsigned int armdiv[8] = {
-        [0] = 1,
-        [1] = 2,
-        [2] = 3,
-        [3] = 4,
-        [5] = 6,
-        [7] = 8,
-};
-static struct clksrc_clk hsspi_eplldiv = {
-        .clk = {
-                .name   = "hsspi-eplldiv",
-                .parent = &clk_esysclk.clk,
-                .ctrlbit = (1 << 14),
-                .enable = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 24 },
-};
-static struct clk *hsspi_sources[] = {
-        [0] = &hsspi_eplldiv.clk,
-        [1] = NULL, /* to fix */
-};
-static struct clksrc_clk hsspi_mux = {
-        .clk    = {
-                .name   = "hsspi-if",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = hsspi_sources,
-                .nr_sources = ARRAY_SIZE(hsspi_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 18 },
-};
-static struct clksrc_clk hsmmc_div[] = {
-        [0] = {
-                .clk = {
-                        .name   = "hsmmc-div",
-                        .devname        = "s3c-sdhci.0",
-                        .parent = &clk_esysclk.clk,
-                },
-                .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
-        },
-        [1] = {
-                .clk = {
-                        .name   = "hsmmc-div",
-                        .devname        = "s3c-sdhci.1",
-                        .parent = &clk_esysclk.clk,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
-        },
-};
-static struct clksrc_clk hsmmc_mux0 = {
-        .clk    = {
-                .name           = "hsmmc-if",
-                .devname        = "s3c-sdhci.0",
-                .ctrlbit        = (1 << 6),
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .sources        = &(struct clksrc_sources) {
-                .nr_sources     = 2,
-                .sources        = (struct clk * []) {
-                        [0]     = &hsmmc_div[0].clk,
-                        [1]     = NULL, /* to fix */
-                },
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 16 },
-};
-static struct clksrc_clk hsmmc_mux1 = {
-        .clk    = {
-                .name           = "hsmmc-if",
-                .devname        = "s3c-sdhci.1",
-                .ctrlbit        = (1 << 12),
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .sources        = &(struct clksrc_sources) {
-                .nr_sources     = 2,
-                .sources        = (struct clk * []) {
-                        [0]     = &hsmmc_div[1].clk,
-                        [1]     = NULL, /* to fix */
-                },
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 17 },
-};
-static struct clk hsmmc0_clk = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.0",
-        .parent         = &clk_h,
-        .enable         = s3c2443_clkcon_enable_h,
-        .ctrlbit        = S3C2416_HCLKCON_HSMMC0,
-};
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &hsspi_eplldiv,
-        &hsspi_mux,
-        &hsmmc_div[0],
-        &hsmmc_div[1],
-        &hsmmc_mux0,
-        &hsmmc_mux1,
-};
-static struct clk_lookup s3c2416_clk_lookup[] = {
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-        /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
-};
-void __init s3c2416_init_clocks(int xtal)
-{
-        u32 epllcon = __raw_readl(S3C2443_EPLLCON);
-        u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4);
-        int ptr;
-        /* s3c2416 EPLL compatible with s3c64xx */
-        clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1);
-        clk_epll.parent = &clk_epllref.clk;
-        s3c2443_common_init_clocks(xtal, s3c2416_get_pll,
-                                   armdiv, ARRAY_SIZE(armdiv),
-                                   S3C2416_CLKDIV0_ARMDIV_MASK);
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-        s3c24xx_register_clock(&hsmmc0_clk);
-        clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
deleted file mode 100644
index 5527226fd61f..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ /dev/null
@@ -1,217 +0,0 @@
-/* linux/arch/arm/mach-s3c2440/clock.c
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2440 Clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mutex.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/serial_core.h>
-#include <linux/serial_s3c.h>
-#include <mach/hardware.h>
-#include <linux/atomic.h>
-#include <asm/irq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-/* S3C2440 extended clock support */
-static unsigned long s3c2440_camif_upll_round(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-        if (rate > parent_rate)
-                return parent_rate;
-        /* note, we remove the +/- 1 calculations for the divisor */
-        div = (parent_rate / rate) / 2;
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-        return parent_rate / (div * 2);
-}
-static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-        rate = s3c2440_camif_upll_round(clk, rate);
-        camdivn &= ~(S3C2440_CAMDIVN_CAMCLK_SEL | S3C2440_CAMDIVN_CAMCLK_MASK);
-        if (rate != parent_rate) {
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= (((parent_rate / rate) / 2) - 1);
-        }
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-        return 0;
-}
-static unsigned long s3c2440_camif_upll_getrate(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-        if (!(camdivn & S3C2440_CAMDIVN_CAMCLK_SEL))
-                return parent_rate;
-        camdivn &= S3C2440_CAMDIVN_CAMCLK_MASK;
-        return parent_rate / (camdivn + 1) / 2;
-}
-/* Extra S3C2440 clocks */
-static struct clk s3c2440_clk_cam = {
-        .name           = "camif",
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
-};
-static struct clk s3c2440_clk_cam_upll = {
-        .name           = "camif-upll",
-        .ops            = &(struct clk_ops) {
-                .set_rate       = s3c2440_camif_upll_setrate,
-                .get_rate       = s3c2440_camif_upll_getrate,
-                .round_rate     = s3c2440_camif_upll_round,
-        },
-};
-static struct clk s3c2440_clk_ac97 = {
-        .name           = "ac97",
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_AC97,
-};
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
-{
-        unsigned long ucon0, ucon1, ucon2, divisor;
-        /* the fun of calculating the uart divisors on the s3c2440 */
-        ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
-        ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
-        ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
-        ucon0 &= S3C2440_UCON0_DIVMASK;
-        ucon1 &= S3C2440_UCON1_DIVMASK;
-        ucon2 &= S3C2440_UCON2_DIVMASK;
-        if (ucon0 != 0)
-                divisor = (ucon0 >> S3C2440_UCON_DIVSHIFT) + 6;
-        else if (ucon1 != 0)
-                divisor = (ucon1 >> S3C2440_UCON_DIVSHIFT) + 21;
-        else if (ucon2 != 0)
-                divisor = (ucon2 >> S3C2440_UCON_DIVSHIFT) + 36;
-        else
-                /* manual calims 44, seems to be 9 */
-                divisor = 9;
-        return clk_get_rate(clk->parent) / divisor;
-}
-static struct clk s3c2440_clk_fclk_n = {
-        .name           = "fclk_n",
-        .parent         = &clk_f,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2440_fclk_n_getrate,
-        },
-};
-static struct clk_lookup s3c2440_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &s3c2440_clk_fclk_n),
-        CLKDEV_INIT("s3c2440-uart.0", "uart", &s3c24xx_clk_uart0),
-        CLKDEV_INIT("s3c2440-uart.1", "uart", &s3c24xx_clk_uart1),
-        CLKDEV_INIT("s3c2440-uart.2", "uart", &s3c24xx_clk_uart2),
-        CLKDEV_INIT("s3c2440-camif", "camera", &s3c2440_clk_cam_upll),
-};
-static int __init_refok s3c2440_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        struct clk *clock_upll;
-        struct clk *clock_h;
-        struct clk *clock_p;
-        clock_p = clk_get(NULL, "pclk");
-        clock_h = clk_get(NULL, "hclk");
-        clock_upll = clk_get(NULL, "upll");
-        if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C2440: Failed to get parent clocks\n");
-                return -EINVAL;
-        }
-        s3c2440_clk_cam.parent = clock_h;
-        s3c2440_clk_ac97.parent = clock_p;
-        s3c2440_clk_cam_upll.parent = clock_upll;
-        s3c24xx_register_clock(&s3c2440_clk_fclk_n);
-        s3c24xx_register_clock(&s3c2440_clk_ac97);
-        s3c24xx_register_clock(&s3c2440_clk_cam);
-        s3c24xx_register_clock(&s3c2440_clk_cam_upll);
-        clkdev_add_table(s3c2440_clk_lookup, ARRAY_SIZE(s3c2440_clk_lookup));
-        clk_disable(&s3c2440_clk_ac97);
-        clk_disable(&s3c2440_clk_cam);
-        return 0;
-}
-static struct subsys_interface s3c2440_clk_interface = {
-        .name           = "s3c2440_clk",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c2440_clk_add,
-};
-static __init int s3c24xx_clk_init(void)
-{
-        return subsys_interface_register(&s3c2440_clk_interface);
-}
-arch_initcall(s3c24xx_clk_init);
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
deleted file mode 100644
index 76cd31f7804e..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ /dev/null
@@ -1,212 +0,0 @@
-/* linux/arch/arm/mach-s3c2443/clock.c
- *
- * Copyright (c) 2007, 2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2443 Clock control support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/serial_core.h>
-#include <linux/io.h>
-#include <asm/mach/map.h>
-#include <mach/hardware.h>
-#include <mach/regs-s3c2443-clock.h>
-#include <plat/cpu-freq.h>
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-/* We currently have to assume that the system is running
- * from the XTPll input, and that all ***REFCLKs are being
- * fed from it, as we cannot read the state of OM[4] from
- * software.
- *
- * It would be possible for each board initialisation to
- * set the correct muxing at initialisation
-*/
-/* clock selections */
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
- * The real clock definition is done in s3c2443-clock.c,
- * only the armdiv divisor table must be defined here.
-*/
-static unsigned int armdiv[16] = {
-        [S3C2443_CLKDIV0_ARMDIV_1 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 1,
-        [S3C2443_CLKDIV0_ARMDIV_2 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 2,
-        [S3C2443_CLKDIV0_ARMDIV_3 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 3,
-        [S3C2443_CLKDIV0_ARMDIV_4 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 4,
-        [S3C2443_CLKDIV0_ARMDIV_6 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 6,
-        [S3C2443_CLKDIV0_ARMDIV_8 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]      = 8,
-        [S3C2443_CLKDIV0_ARMDIV_12 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 12,
-        [S3C2443_CLKDIV0_ARMDIV_16 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]     = 16,
-};
-/* hsspi
- *
- * high-speed spi clock, sourced from esysclk
-*/
-static struct clksrc_clk clk_hsspi = {
-        .clk    = {
-                .name           = "hsspi-if",
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_HSSPICLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
-/* clk_hsmcc_div
- *
- * this clock is sourced from epll, and is fed through a divider,
- * to a mux controlled by sclkcon where either it or a extclk can
- * be fed to the hsmmc block
-*/
-static struct clksrc_clk clk_hsmmc_div = {
-        .clk    = {
-                .name           = "hsmmc-div",
-                .devname        = "s3c-sdhci.1",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
-};
-static int s3c2443_setparent_hsmmc(struct clk *clk, struct clk *parent)
-{
-        unsigned long clksrc = __raw_readl(S3C2443_SCLKCON);
-        clksrc &= ~(S3C2443_SCLKCON_HSMMCCLK_EXT |
-                    S3C2443_SCLKCON_HSMMCCLK_EPLL);
-        if (parent == &clk_epll)
-                clksrc |= S3C2443_SCLKCON_HSMMCCLK_EPLL;
-        else if (parent == &clk_ext)
-                clksrc |= S3C2443_SCLKCON_HSMMCCLK_EXT;
-        else
-                return -EINVAL;
-        if (clk->usage > 0) {
-                __raw_writel(clksrc, S3C2443_SCLKCON);
-        }
-        clk->parent = parent;
-        return 0;
-}
-static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
-{
-        return s3c2443_setparent_hsmmc(clk, clk->parent);
-}
-static struct clk clk_hsmmc = {
-        .name           = "hsmmc-if",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_hsmmc_div.clk,
-        .enable         = s3c2443_enable_hsmmc,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2443_setparent_hsmmc,
-        },
-};
-/* standard clock definitions */
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "sdi",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_SDI,
-        }, {
-                .name           = "spi",
-                .devname        = "s3c2410-spi.0",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_SPI1,
-        }
-};
-/* clocks to add straight away */
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_hsspi,
-        &clk_hsmmc_div,
-};
-static struct clk *clks[] __initdata = {
-        &clk_hsmmc,
-};
-static struct clk_lookup s3c2443_clk_lookup[] = {
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
-};
-void __init s3c2443_init_clocks(int xtal)
-{
-        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        int ptr;
-        clk_epll.rate = s3c2443_get_epll(epllcon, xtal);
-        clk_epll.parent = &clk_epllref.clk;
-        s3c2443_common_init_clocks(xtal, s3c2443_get_mpll,
-                                   armdiv, ARRAY_SIZE(armdiv),
-                                   S3C2443_CLKDIV0_ARMDIV_MASK);
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-        /* We must be careful disabling the clocks we are not intending to
-         * be using at boot time, as subsystems such as the LCD which do
-         * their own DMA requests to the bus can cause the system to lockup
-         * if they where in the middle of requesting bus access.
-         *
-         * Disabling the LCD clock if the LCD is active is very dangerous,
-         * and therefore the bootloader should be careful to not enable
-         * the LCD clock if it is not needed.
-        */
-        /* install (and disable) the clocks we do not need immediately */
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
-}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c244x.c b/arch/arm/mach-s3c24xx/clock-s3c244x.c
deleted file mode 100644
index 6d9b688c442b..000000000000
--- a/arch/arm/mach-s3c24xx/clock-s3c244x.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
- *
- * Copyright (c) 2004-2008 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2440/S3C2442 Common clock support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <linux/atomic.h>
-#include <asm/irq.h>
-#include <mach/regs-clock.h>
-#include <plat/clock.h>
-#include <plat/cpu.h>
-static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
-{
-        unsigned long camdivn;
-        unsigned long dvs;
-        if (parent == &clk_f)
-                dvs = 0;
-        else if (parent == &clk_h)
-                dvs = S3C2440_CAMDIVN_DVSEN;
-        else
-                return -EINVAL;
-        clk->parent = parent;
-        camdivn  = __raw_readl(S3C2440_CAMDIVN);
-        camdivn &= ~S3C2440_CAMDIVN_DVSEN;
-        camdivn |= dvs;
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-        return 0;
-}
-static struct clk clk_arm = {
-        .name           = "armclk",
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .set_parent     = s3c2440_setparent_armclk,
-        },
-};
-static int s3c244x_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
-        unsigned long clkdivn;
-        struct clk *clock_upll;
-        int ret;
-        printk("S3C244X: Clock Support, DVS %s\n",
-               (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
-        clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
-        ret = s3c24xx_register_clock(&clk_arm);
-        if (ret < 0) {
-                printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
-                return ret;
-        }
-        clock_upll = clk_get(NULL, "upll");
-        if (IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
-                return -ENOENT;
-        }
-        /* check rate of UPLL, and if it is near 96MHz, then change
-         * to using half the UPLL rate for the system */
-        if (clk_get_rate(clock_upll) > (94 * MHZ)) {
-                clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
-                spin_lock(&clocks_lock);
-                clkdivn = __raw_readl(S3C2410_CLKDIVN);
-                clkdivn |= S3C2440_CLKDIVN_UCLK;
-                __raw_writel(clkdivn, S3C2410_CLKDIVN);
-                spin_unlock(&clocks_lock);
-        }
-        return 0;
-}
-static struct subsys_interface s3c2440_clk_interface = {
-        .name           = "s3c2440_clk",
-        .subsys         = &s3c2440_subsys,
-        .add_dev        = s3c244x_clk_add,
-};
-static int s3c2440_clk_init(void)
-{
-        return subsys_interface_register(&s3c2440_clk_interface);
-}
-arch_initcall(s3c2440_clk_init);
-static struct subsys_interface s3c2442_clk_interface = {
-        .name           = "s3c2442_clk",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c244x_clk_add,
-};
-static int s3c2442_clk_init(void)
-{
-        return subsys_interface_register(&s3c2442_clk_interface);
-}
-arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
deleted file mode 100644
index 65d3eef73090..000000000000
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Common code for SoCs starting with the S3C2443
- *
- * Copyright (c) 2007, 2010 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <mach/regs-s3c2443-clock.h>
-#include <plat/clock.h>
-#include <plat/clock-clksrc.h>
-#include <plat/cpu.h>
-#include <plat/cpu-freq.h>
-static int s3c2443_gate(void __iomem *reg, struct clk *clk, int enable)
-{
-        u32 ctrlbit = clk->ctrlbit;
-        u32 con = __raw_readl(reg);
-        if (enable)
-                con |= ctrlbit;
-        else
-                con &= ~ctrlbit;
-        __raw_writel(con, reg);
-        return 0;
-}
-int s3c2443_clkcon_enable_h(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_HCLKCON, clk, enable);
-}
-int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_PCLKCON, clk, enable);
-}
-int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
-{
-        return s3c2443_gate(S3C2443_SCLKCON, clk, enable);
-}
-/* mpllref is a direct descendant of clk_xtal by default, but it is not
- * elided as the EPLL can be either sourced by the XTAL or EXTCLK and as
- * such directly equating the two source clocks is impossible.
- */
-static struct clk clk_mpllref = {
-        .name           = "mpllref",
-        .parent         = &clk_xtal,
-};
-static struct clk *clk_epllref_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpllref,
-        [2] = &clk_xtal,
-        [3] = &clk_ext,
-};
-struct clksrc_clk clk_epllref = {
-        .clk    = {
-                .name           = "epllref",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_epllref_sources,
-                .nr_sources = ARRAY_SIZE(clk_epllref_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 7 },
-};
-/* esysclk
- *
- * this is sourced from either the EPLL or the EPLLref clock
-*/
-static struct clk *clk_sysclk_sources[] = {
-        [0] = &clk_epllref.clk,
-        [1] = &clk_epll,
-};
-struct clksrc_clk clk_esysclk = {
-        .clk    = {
-                .name           = "esysclk",
-                .parent         = &clk_epll,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_sysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_sysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 1, .shift = 6 },
-};
-static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long div = __raw_readl(S3C2443_CLKDIV0);
-        div  &= S3C2443_CLKDIV0_EXTDIV_MASK;
-        div >>= (S3C2443_CLKDIV0_EXTDIV_SHIFT-1);       /* x2 */
-        return parent_rate / (div + 1);
-}
-static struct clk clk_mdivclk = {
-        .name           = "mdivclk",
-        .parent         = &clk_mpllref,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_getrate_mdivclk,
-        },
-};
-static struct clk *clk_msysclk_sources[] = {
-        [0] = &clk_mpllref,
-        [1] = &clk_mpll,
-        [2] = &clk_mdivclk,
-        [3] = &clk_mpllref,
-};
-static struct clksrc_clk clk_msysclk = {
-        .clk    = {
-                .name           = "msysclk",
-                .parent         = &clk_xtal,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_msysclk_sources,
-                .nr_sources = ARRAY_SIZE(clk_msysclk_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 3 },
-};
-/* prediv
- *
- * this divides the msysclk down to pass to h/p/etc.
- */
-static unsigned long s3c2443_prediv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-        clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
-        clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
-        return rate / (clkdiv0 + 1);
-}
-static struct clk clk_prediv = {
-        .name           = "prediv",
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .get_rate       = s3c2443_prediv_getrate,
-        },
-};
-/* hclk divider
- *
- * divides the prediv and provides the hclk.
- */
-static unsigned long s3c2443_hclkdiv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-        clkdiv0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
-        return rate / (clkdiv0 + 1);
-}
-static struct clk_ops clk_h_ops = {
-        .get_rate       = s3c2443_hclkdiv_getrate,
-};
-/* pclk divider
- *
- * divides the hclk and provides the pclk.
- */
-static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
-        clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0);
-        return rate / (clkdiv0 + 1);
-}
-static struct clk_ops clk_p_ops = {
-        .get_rate       = s3c2443_pclkdiv_getrate,
-};
-/* armdiv
- *
- * this clock is sourced from msysclk and can have a number of
- * divider values applied to it to then be fed into armclk.
-*/
-static unsigned int *armdiv;
-static int nr_armdiv;
-static int armdivmask;
-static unsigned long s3c2443_armclk_roundrate(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        unsigned long calc;
-        unsigned best = 256; /* bigger than any value */
-        unsigned div;
-        int ptr;
-        if (!nr_armdiv)
-                return -EINVAL;
-        for (ptr = 0; ptr < nr_armdiv; ptr++) {
-                div = armdiv[ptr];
-                if (div) {
-                        /* cpufreq provides 266mhz as 266666000 not 266666666 */
-                        calc = (parent / div / 1000) * 1000;
-                        if (calc <= rate && div < best)
-                                best = div;
-                }
-        }
-        return parent / best;
-}
-static unsigned long s3c2443_armclk_getrate(struct clk *clk)
-{
-        unsigned long rate = clk_get_rate(clk->parent);
-        unsigned long clkcon0;
-        int val;
-        if (!nr_armdiv || !armdivmask)
-                return -EINVAL;
-        clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-        clkcon0 &= armdivmask;
-        val = clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT;
-        return rate / armdiv[val];
-}
-static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent = clk_get_rate(clk->parent);
-        unsigned long calc;
-        unsigned div;
-        unsigned best = 256; /* bigger than any value */
-        int ptr;
-        int val = -1;
-        if (!nr_armdiv || !armdivmask)
-                return -EINVAL;
-        for (ptr = 0; ptr < nr_armdiv; ptr++) {
-                div = armdiv[ptr];
-                if (div) {
-                        /* cpufreq provides 266mhz as 266666000 not 266666666 */
-                        calc = (parent / div / 1000) * 1000;
-                        if (calc <= rate && div < best) {
-                                best = div;
-                                val = ptr;
-                        }
-                }
-        }
-        if (val >= 0) {
-                unsigned long clkcon0;
-                clkcon0 = __raw_readl(S3C2443_CLKDIV0);
-                clkcon0 &= ~armdivmask;
-                clkcon0 |= val << S3C2443_CLKDIV0_ARMDIV_SHIFT;
-                __raw_writel(clkcon0, S3C2443_CLKDIV0);
-        }
-        return (val == -1) ? -EINVAL : 0;
-}
-static struct clk clk_armdiv = {
-        .name           = "armdiv",
-        .parent         = &clk_msysclk.clk,
-        .ops            = &(struct clk_ops) {
-                .round_rate = s3c2443_armclk_roundrate,
-                .get_rate = s3c2443_armclk_getrate,
-                .set_rate = s3c2443_armclk_setrate,
-        },
-};
-/* armclk
- *
- * this is the clock fed into the ARM core itself, from armdiv or from hclk.
- */
-static struct clk *clk_arm_sources[] = {
-        [0] = &clk_armdiv,
-        [1] = &clk_h,
-};
-static struct clksrc_clk clk_arm = {
-        .clk    = {
-                .name           = "armclk",
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_arm_sources,
-                .nr_sources = ARRAY_SIZE(clk_arm_sources),
-        },
-        .reg_src = { .reg = S3C2443_CLKDIV0, .size = 1, .shift = 13 },
-};
-/* usbhost
- *
- * usb host bus-clock, usually 48MHz to provide USB bus clock timing
-*/
-static struct clksrc_clk clk_usb_bus_host = {
-        .clk    = {
-                .name           = "usb-bus-host-parent",
-                .parent         = &clk_esysclk.clk,
-                .ctrlbit        = S3C2443_SCLKCON_USBHOST,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 4 },
-};
-/* common clksrc clocks */
-static struct clksrc_clk clksrc_clks[] = {
-        {
-                /* camera interface bus-clock, divided down from esysclk */
-                .clk    = {
-                        .name           = "camif-upll", /* same as 2440 name */
-                        .parent         = &clk_esysclk.clk,
-                        .ctrlbit        = S3C2443_SCLKCON_CAMCLK,
-                        .enable         = s3c2443_clkcon_enable_s,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 26 },
-        }, {
-                .clk    = {
-                        .name           = "display-if",
-                        .parent         = &clk_esysclk.clk,
-                        .ctrlbit        = S3C2443_SCLKCON_DISPCLK,
-                        .enable         = s3c2443_clkcon_enable_s,
-                },
-                .reg_div = { .reg = S3C2443_CLKDIV1, .size = 8, .shift = 16 },
-        },
-};
-static struct clksrc_clk clk_esys_uart = {
-        /* ART baud-rate clock sourced from esysclk via a divisor */
-        .clk    = {
-                .name           = "uartclk",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
-};
-static struct clk clk_i2s_ext = {
-        .name           = "i2s-ext",
-};
-/* i2s_eplldiv
- *
- * This clock is the output from the I2S divisor of ESYSCLK, and is separate
- * from the mux that comes after it (cannot merge into one single clock)
-*/
-static struct clksrc_clk clk_i2s_eplldiv = {
-        .clk    = {
-                .name           = "i2s-eplldiv",
-                .parent         = &clk_esysclk.clk,
-        },
-        .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
-};
-/* i2s-ref
- *
- * i2s bus reference clock, selectable from external, esysclk or epllref
- *
- * Note, this used to be two clocks, but was compressed into one.
-*/
-static struct clk *clk_i2s_srclist[] = {
-        [0] = &clk_i2s_eplldiv.clk,
-        [1] = &clk_i2s_ext,
-        [2] = &clk_epllref.clk,
-        [3] = &clk_epllref.clk,
-};
-static struct clksrc_clk clk_i2s = {
-        .clk    = {
-                .name           = "i2s-if",
-                .ctrlbit        = S3C2443_SCLKCON_I2SCLK,
-                .enable         = s3c2443_clkcon_enable_s,
-        },
-        .sources = &(struct clksrc_sources) {
-                .sources = clk_i2s_srclist,
-                .nr_sources = ARRAY_SIZE(clk_i2s_srclist),
-        },
-        .reg_src = { .reg = S3C2443_CLKSRC, .size = 2, .shift = 14 },
-};
-static struct clk init_clocks_off[] = {
-        {
-                .name           = "iis",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIS,
-        }, {
-                .name           = "adc",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_ADC,
-        }, {
-                .name           = "i2c",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_IIC,
-        }
-};
-static struct clk init_clocks[] = {
-        {
-                .name           = "dma.0",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA0,
-        }, {
-                .name           = "dma.1",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA1,
-        }, {
-                .name           = "dma.2",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA2,
-        }, {
-                .name           = "dma.3",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA3,
-        }, {
-                .name           = "dma.4",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA4,
-        }, {
-                .name           = "dma.5",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_DMA5,
-        }, {
-                .name           = "gpio",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_GPIO,
-        }, {
-                .name           = "usb-host",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBH,
-        }, {
-                .name           = "usb-device",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_USBD,
-        }, {
-                .name           = "lcd",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_LCDC,
-        }, {
-                .name           = "timers",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_PWMT,
-        }, {
-                .name           = "cfc",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_CFC,
-        }, {
-                .name           = "ssmc",
-                .parent         = &clk_h,
-                .enable         = s3c2443_clkcon_enable_h,
-                .ctrlbit        = S3C2443_HCLKCON_SSMC,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.0",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART0,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.1",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART1,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.2",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART2,
-        }, {
-                .name           = "uart",
-                .devname        = "s3c2440-uart.3",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_UART3,
-        }, {
-                .name           = "rtc",
-                .parent         = &clk_p,
-                .enable         = s3c2443_clkcon_enable_p,
-                .ctrlbit        = S3C2443_PCLKCON_RTC,
-        }, {
-                .name           = "watchdog",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_WDT,
-        }, {
-                .name           = "ac97",
-                .parent         = &clk_p,
-                .ctrlbit        = S3C2443_PCLKCON_AC97,
-        }, {
-                .name           = "nand",
-                .parent         = &clk_h,
-        }, {
-                .name           = "usb-bus-host",
-                .parent         = &clk_usb_bus_host.clk,
-        }
-};
-static struct clk hsmmc1_clk = {
-        .name           = "hsmmc",
-        .devname        = "s3c-sdhci.1",
-        .parent         = &clk_h,
-        .enable         = s3c2443_clkcon_enable_h,
-        .ctrlbit        = S3C2443_HCLKCON_HSMMC,
-};
-static struct clk hsspi_clk = {
-        .name           = "spi",
-        .devname        = "s3c2443-spi.0",
-        .parent         = &clk_p,
-        .enable         = s3c2443_clkcon_enable_p,
-        .ctrlbit        = S3C2443_PCLKCON_HSSPI,
-};
-/* EPLLCON compatible enough to get on/off information */
-void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll)
-{
-        unsigned long epllcon = __raw_readl(S3C2443_EPLLCON);
-        unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON);
-        struct clk *xtal_clk;
-        unsigned long xtal;
-        unsigned long pll;
-        int ptr;
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-        pll = get_mpll(mpllcon, xtal);
-        clk_msysclk.clk.rate = pll;
-        clk_mpll.rate = pll;
-        printk("CPU: MPLL %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n",
-               (mpllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
-               print_mhz(pll), print_mhz(clk_get_rate(&clk_armdiv)),
-               print_mhz(clk_get_rate(&clk_h)),
-               print_mhz(clk_get_rate(&clk_p)));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrc_clks); ptr++)
-                s3c_set_clksrc(&clksrc_clks[ptr], true);
-        /* ensure usb bus clock is within correct rate of 48MHz */
-        if (clk_get_rate(&clk_usb_bus_host.clk) != (48 * 1000 * 1000)) {
-                printk(KERN_INFO "Warning: USB host bus not at 48MHz\n");
-                clk_set_rate(&clk_usb_bus_host.clk, 48*1000*1000);
-        }
-        printk("CPU: EPLL %s %ld.%03ld MHz, usb-bus %ld.%03ld MHz\n",
-               (epllcon & S3C2443_PLLCON_OFF) ? "off" : "on",
-               print_mhz(clk_get_rate(&clk_epll)),
-               print_mhz(clk_get_rate(&clk_usb_bus)));
-}
-static struct clk *clks[] __initdata = {
-        &clk_prediv,
-        &clk_mpllref,
-        &clk_mdivclk,
-        &clk_ext,
-        &clk_epll,
-        &clk_usb_bus,
-        &clk_armdiv,
-        &hsmmc1_clk,
-        &hsspi_clk,
-};
-static struct clksrc_clk *clksrcs[] __initdata = {
-        &clk_i2s_eplldiv,
-        &clk_i2s,
-        &clk_usb_bus_host,
-        &clk_epllref,
-        &clk_esysclk,
-        &clk_msysclk,
-        &clk_arm,
-};
-static struct clk_lookup s3c2443_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-        CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
-};
-void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
-                                       unsigned int *divs, int nr_divs,
-                                       int divmask)
-{
-        int ptr;
-        armdiv = divs;
-        nr_armdiv = nr_divs;
-        armdivmask = divmask;
-        /* s3c2443 parents h clock from prediv */
-        clk_h.parent = &clk_prediv;
-        clk_h.ops = &clk_h_ops;
-        /* and p clock from h clock */
-        clk_p.parent = &clk_h;
-        clk_p.ops = &clk_p_ops;
-        clk_usb_bus.parent = &clk_usb_bus_host.clk;
-        clk_epll.parent = &clk_epllref.clk;
-        s3c24xx_register_baseclocks(xtal);
-        s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
-        for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
-                s3c_register_clksrc(clksrcs[ptr], 1);
-        s3c_register_clksrc(clksrc_clks, ARRAY_SIZE(clksrc_clks));
-        s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
-        /* See s3c2443/etc notes on disabling clocks at init time */
-        s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
-        clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
-        s3c2443_common_setup_clocks(get_mpll);
-}
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 1bc8e73c94f9..c0763b837745 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -53,6 +53,7 @@
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 #include <plat/pwm-core.h>
+#include <plat/watchdog-reset.h>
 #include "common.h"
@@ -73,7 +74,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32410000,
                .idmask         = 0xffffffff,
                .map_io         = s3c2410_map_io,
-                .init_clocks    = s3c2410_init_clocks,
                .init_uarts     = s3c2410_init_uarts,
                .init           = s3c2410_init,
                .name           = name_s3c2410
@@ -82,7 +82,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32410002,
                .idmask         = 0xffffffff,
                .map_io         = s3c2410_map_io,
-                .init_clocks    = s3c2410_init_clocks,
                .init_uarts     = s3c2410_init_uarts,
                .init           = s3c2410a_init,
                .name           = name_s3c2410a
@@ -91,7 +90,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32440000,
                .idmask         = 0xffffffff,
                .map_io         = s3c2440_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2440_init,
                .name           = name_s3c2440
@@ -100,7 +98,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32440001,
                .idmask         = 0xffffffff,
                .map_io         = s3c2440_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2440_init,
                .name           = name_s3c2440a
@@ -109,7 +106,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32440aaa,
                .idmask         = 0xffffffff,
                .map_io         = s3c2442_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2442_init,
                .name           = name_s3c2442
@@ -118,7 +114,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32440aab,
                .idmask         = 0xffffffff,
                .map_io         = s3c2442_map_io,
-                .init_clocks    = s3c244x_init_clocks,
                .init_uarts     = s3c244x_init_uarts,
                .init           = s3c2442_init,
                .name           = name_s3c2442b
@@ -127,7 +122,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32412001,
                .idmask         = 0xffffffff,
                .map_io         = s3c2412_map_io,
-                .init_clocks    = s3c2412_init_clocks,
                .init_uarts     = s3c2412_init_uarts,
                .init           = s3c2412_init,
                .name           = name_s3c2412,
@@ -136,7 +130,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32412003,
                .idmask         = 0xffffffff,
                .map_io         = s3c2412_map_io,
-                .init_clocks    = s3c2412_init_clocks,
                .init_uarts     = s3c2412_init_uarts,
                .init           = s3c2412_init,
                .name           = name_s3c2412,
@@ -145,7 +138,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32450003,
                .idmask         = 0xffffffff,
                .map_io         = s3c2416_map_io,
-                .init_clocks    = s3c2416_init_clocks,
                .init_uarts     = s3c2416_init_uarts,
                .init           = s3c2416_init,
                .name           = name_s3c2416,
@@ -154,7 +146,6 @@ static struct cpu_table cpu_ids[] __initdata = {
                .idcode         = 0x32443001,
                .idmask         = 0xffffffff,
                .map_io         = s3c2443_map_io,
-                .init_clocks    = s3c2443_init_clocks,
                .init_uarts     = s3c2443_init_uarts,
                .init           = s3c2443_init,
                .name           = name_s3c2443,
@@ -316,21 +307,6 @@ struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
        },
 };
-/* initialise all the clocks */
-void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk,
-                                           unsigned long hclk,
-                                           unsigned long pclk)
-{
-        clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON),
-                                        clk_xtal.rate);
-        clk_mpll.rate = fclk;
-        clk_h.rate = hclk;
-        clk_p.rate = pclk;
-        clk_f.rate = fclk;
-}
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
        defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 static struct resource s3c2410_dma_resource[] = {
@@ -534,3 +510,62 @@ struct platform_device s3c2443_device_dma = {
        },
 };
 #endif
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2410)
+void __init s3c2410_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+#ifdef CONFIG_CPU_S3C2412
+void __init s3c2412_init_clocks(int xtal)
+{
+        s3c2412_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+}
+#endif
+#ifdef CONFIG_CPU_S3C2416
+void __init s3c2416_init_clocks(int xtal)
+{
+        s3c2443_common_clk_init(NULL, xtal, 0, S3C24XX_VA_CLKPWR);
+}
+#endif
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2440)
+void __init s3c2440_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+#if defined(CONFIG_COMMON_CLK) && defined(CONFIG_CPU_S3C2442)
+void __init s3c2442_init_clocks(int xtal)
+{
+        s3c2410_common_clk_init(NULL, xtal, 2, S3C24XX_VA_CLKPWR);
+        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
+}
+#endif
+#ifdef CONFIG_CPU_S3C2443
+void __init s3c2443_init_clocks(int xtal)
+{
+        s3c2443_common_clk_init(NULL, xtal, 1, S3C24XX_VA_CLKPWR);
+}
+#endif
+#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2440) || \
+        defined(CONFIG_CPU_S3C2442)
+static struct resource s3c2410_dclk_resource[] = {
+        [0] = DEFINE_RES_MEM(0x56000084, 0x4),
+};
+struct platform_device s3c2410_device_dclk = {
+        .name           = "s3c2410-dclk",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(s3c2410_dclk_resource),
+        .resource       = s3c2410_dclk_resource,
+};
+#endif
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index e46c10417216..ac3ff12a0601 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -67,16 +67,15 @@ extern struct syscore_ops s3c2416_irq_syscore_ops;
 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
 extern void s3c244x_map_io(void);
 extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-extern void s3c244x_init_clocks(int xtal);
 extern void s3c244x_restart(enum reboot_mode mode, const char *cmd);
 #else
-#define s3c244x_init_clocks NULL
 #define s3c244x_init_uarts NULL
 #endif
 #ifdef CONFIG_CPU_S3C2440
 extern  int s3c2440_init(void);
 extern void s3c2440_map_io(void);
+extern void s3c2440_init_clocks(int xtal);
 extern void s3c2440_init_irq(void);
 #else
 #define s3c2440_init NULL
@@ -86,6 +85,7 @@ extern void s3c2440_init_irq(void);
 #ifdef CONFIG_CPU_S3C2442
 extern  int s3c2442_init(void);
 extern void s3c2442_map_io(void);
+extern void s3c2442_init_clocks(int xtal);
 extern void s3c2442_init_irq(void);
 #else
 #define s3c2442_init NULL
@@ -114,4 +114,21 @@ extern struct platform_device s3c2412_device_dma;
 extern struct platform_device s3c2440_device_dma;
 extern struct platform_device s3c2443_device_dma;
+extern struct platform_device s3c2410_device_dclk;
+#ifdef CONFIG_S3C2410_COMMON_CLK
+void __init s3c2410_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                    int current_soc,
+                                    void __iomem *reg_base);
+#endif
+#ifdef CONFIG_S3C2412_COMMON_CLK
+void __init s3c2412_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                unsigned long ext_f, void __iomem *reg_base);
+#endif
+#ifdef CONFIG_S3C2443_COMMON_CLK
+void __init s3c2443_common_clk_init(struct device_node *np, unsigned long xti_f,
+                                    int current_soc,
+                                    void __iomem *reg_base);
+#endif
 #endif /* __ARCH_ARM_MACH_S3C24XX_COMMON_H */
diff --git a/arch/arm/mach-s3c24xx/cpufreq-utils.c b/arch/arm/mach-s3c24xx/cpufreq-utils.c
index 2a0aa5684e72..d4d9514335f4 100644
--- a/arch/arm/mach-s3c24xx/cpufreq-utils.c
+++ b/arch/arm/mach-s3c24xx/cpufreq-utils.c
@@ -14,6 +14,7 @@
 #include <linux/errno.h>
 #include <linux/cpufreq.h>
 #include <linux/io.h>
+#include <linux/clk.h>
 #include <mach/map.h>
 #include <mach/regs-clock.h>
@@ -60,5 +61,6 @@ void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
 */
 void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
 {
-        __raw_writel(cfg->pll.driver_data, S3C2410_MPLLCON);
+        if (!IS_ERR(cfg->mpll))
+                clk_set_rate(cfg->mpll, cfg->pll.frequency);
 }
diff --git a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S b/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
deleted file mode 100644
index 2f39737544c0..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,101 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Copyright (C) 2005 Simtec Electronics
- *
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <mach/map.h>
-#include <mach/regs-gpio.h>
-#include <linux/serial_s3c.h>
-#define S3C2410_UART1_OFF (0x4000)
-#define SHIFT_2440TXF (14-9)
-        .macro addruart, rp, rv, tmp
-                ldr     \rp, = S3C24XX_PA_UART
-                ldr     \rv, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-                add     \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-#endif
-        .endm
-        .macro fifo_full_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     1004f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-1004:
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                moveq   \rd, \rd, lsr #SHIFT_2440TXF
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-        .macro  fifo_full_s3c2410 rd, rx
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                tst     \rd, #S3C2410_UFSTAT_TXFULL
-        .endm
-/* fifo level reading */
-        .macro fifo_level_s3c24xx rd, rx
-                @ check for arm920 vs arm926. currently assume all arm926
-                @ devices have an 64 byte FIFO identical to the s3c2440
-                mrc     p15, 0, \rd, c0, c0
-                and     \rd, \rd, #0xff0
-                teq     \rd, #0x260
-                beq     10000f
-                mrc     p15, 0, \rd, c1, c0
-                tst     \rd, #1
-                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
-                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
-                bic     \rd, \rd, #0xff000
-                ldr     \rd, [\rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0)]
-                and     \rd, \rd, #0x00ff0000
-                teq     \rd, #0x00440000                @ is it 2440?
-10000:
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
-                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
-        .endm
-        .macro fifo_level_s3c2410 rd, rx
-                ldr     \rd, [\rx, # S3C2410_UFSTAT]
-                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
-        .endm
-/* Select the correct implementation depending on the configuration. The
- * S3C2440 will get selected by default, as these are the most widely
- * used variants of these
-*/
-#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
-#define fifo_full  fifo_full_s3c2410
-#define fifo_level fifo_level_s3c2410
-#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
-#define fifo_full  fifo_full_s3c24xx
-#define fifo_level fifo_level_s3c24xx
-#endif
-/* include the reset of the code which will do the work */
-#include <debug/samsung.S>
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
index 3415b60082d7..3db6c10de023 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-clock.h
@@ -42,24 +42,6 @@
 #define S3C2410_CLKCON_IIS           (1<<17)
 #define S3C2410_CLKCON_SPI           (1<<18)
-/* DCLKCON register addresses in gpio.h */
-#define S3C2410_DCLKCON_DCLK0EN      (1<<0)
-#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
-#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
-#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
-#define S3C2410_DCLKCON_DCLK0_DIV_MASK ((0xf)<<4)
-#define S3C2410_DCLKCON_DCLK0_CMP_MASK ((0xf)<<8)
-#define S3C2410_DCLKCON_DCLK1EN      (1<<16)
-#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
-#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
-#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP(x) (((x) - 1) <<24)
-#define S3C2410_DCLKCON_DCLK1_DIV_MASK ((0xf) <<20)
-#define S3C2410_DCLKCON_DCLK1_CMP_MASK ((0xf) <<24)
 #define S3C2410_CLKDIVN_PDIVN        (1<<0)
 #define S3C2410_CLKDIVN_HDIVN        (1<<1)
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index c2ef016032ab..c6583cfa5835 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -457,9 +457,6 @@
 /* miscellaneous control */
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
-#define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
-#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
 /* see clock.h for dclk definitions */
diff --git a/arch/arm/mach-s3c24xx/mach-amlm5900.c b/arch/arm/mach-s3c24xx/mach-amlm5900.c
index 8ac9554aa996..5157e250dd13 100644
--- a/arch/arm/mach-s3c24xx/mach-amlm5900.c
+++ b/arch/arm/mach-s3c24xx/mach-amlm5900.c
@@ -161,11 +161,16 @@ static struct platform_device *amlm5900_devices[] __initdata = {
 static void __init amlm5900_map_io(void)
 {
        s3c24xx_init_io(amlm5900_iodesc, ARRAY_SIZE(amlm5900_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(amlm5900_uartcfgs, ARRAY_SIZE(amlm5900_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init amlm5900_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 #ifdef CONFIG_FB_S3C2410
 static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
        .width          = 160,
@@ -241,6 +246,6 @@ MACHINE_START(AML_M5900, "AML_M5900")
        .map_io         = amlm5900_map_io,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = amlm5900_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = amlm5900_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-anubis.c b/arch/arm/mach-s3c24xx/mach-anubis.c
index 81a270af2336..e053581cab0b 100644
--- a/arch/arm/mach-s3c24xx/mach-anubis.c
+++ b/arch/arm/mach-s3c24xx/mach-anubis.c
@@ -46,7 +46,6 @@
 #include <net/ax88796.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/asoc-s3c24xx_simtec.h>
@@ -352,6 +351,7 @@ static struct platform_device anubis_device_sm501 = {
 /* Standard Anubis devices */
 static struct platform_device *anubis_devices[] __initdata = {
+        &s3c2410_device_dclk,
        &s3c_device_ohci,
        &s3c_device_wdt,
        &s3c_device_adc,
@@ -364,14 +364,6 @@ static struct platform_device *anubis_devices[] __initdata = {
        &anubis_device_sm501,
 };
-static struct clk *anubis_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
 /* I2C devices. */
 static struct i2c_board_info anubis_i2c_devs[] __initdata = {
@@ -394,23 +386,7 @@ static struct s3c24xx_audio_simtec_pdata __initdata anubis_audio = {
 static void __init anubis_map_io(void)
 {
-        /* initialise the clocks */
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-        s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
        s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
@@ -428,6 +404,12 @@ static void __init anubis_map_io(void)
        }
 }
+static void __init anubis_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init anubis_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -447,6 +429,6 @@ MACHINE_START(ANUBIS, "Simtec-Anubis")
        .map_io         = anubis_map_io,
        .init_machine   = anubis_init,
        .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = anubis_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-at2440evb.c b/arch/arm/mach-s3c24xx/mach-at2440evb.c
index d8f6bb1096cb..9db768f448a5 100644
--- a/arch/arm/mach-s3c24xx/mach-at2440evb.c
+++ b/arch/arm/mach-s3c24xx/mach-at2440evb.c
@@ -45,7 +45,6 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <linux/platform_data/mmc-s3cmci.h>
@@ -192,11 +191,16 @@ static struct platform_device *at2440evb_devices[] __initdata = {
 static void __init at2440evb_map_io(void)
 {
        s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
-        s3c24xx_init_clocks(16934400);
        s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init at2440evb_init_time(void)
+{
+        s3c2440_init_clocks(16934400);
+        samsung_timer_init();
+}
 static void __init at2440evb_init(void)
 {
        s3c24xx_fb_set_platdata(&at2440evb_fb_info);
@@ -213,6 +217,6 @@ MACHINE_START(AT2440EVB, "AT2440EVB")
        .map_io         = at2440evb_map_io,
        .init_machine   = at2440evb_init,
        .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = at2440evb_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-bast.c b/arch/arm/mach-s3c24xx/mach-bast.c
index e371ff53a408..f9112b801a33 100644
--- a/arch/arm/mach-s3c24xx/mach-bast.c
+++ b/arch/arm/mach-s3c24xx/mach-bast.c
@@ -51,7 +51,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
@@ -523,6 +522,7 @@ static struct s3c_hwmon_pdata bast_hwmon_info = {
 // cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 static struct platform_device *bast_devices[] __initdata = {
+        &s3c2410_device_dclk,
        &s3c_device_ohci,
        &s3c_device_lcd,
        &s3c_device_wdt,
@@ -537,14 +537,6 @@ static struct platform_device *bast_devices[] __initdata = {
        &bast_sio,
 };
-static struct clk *bast_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
 static struct s3c_cpufreq_board __initdata bast_cpufreq = {
        .refresh        = 7800, /* 7.8usec */
        .auto_io        = 1,
@@ -558,29 +550,19 @@ static struct s3c24xx_audio_simtec_pdata __initdata bast_audio = {
 static void __init bast_map_io(void)
 {
-        /* initialise the clocks */
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
        s3c_hwmon_set_platdata(&bast_hwmon_info);
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init bast_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init bast_init(void)
 {
        register_syscore_ops(&bast_pm_syscore_ops);
@@ -608,6 +590,6 @@ MACHINE_START(BAST, "Simtec-BAST")
        .map_io         = bast_map_io,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = bast_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = bast_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index dc4db849f0fd..fc3a08d0cb3f 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -501,7 +501,6 @@ static struct platform_device gta02_buttons_device = {
 static void __init gta02_map_io(void)
 {
        s3c24xx_init_io(gta02_iodesc, ARRAY_SIZE(gta02_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(gta02_uartcfgs, ARRAY_SIZE(gta02_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
@@ -585,6 +584,11 @@ static void __init gta02_machine_init(void)
        regulator_has_full_constraints();
 }
+static void __init gta02_init_time(void)
+{
+        s3c2442_init_clocks(12000000);
+        samsung_timer_init();
+}
 MACHINE_START(NEO1973_GTA02, "GTA02")
        /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
@@ -592,6 +596,6 @@ MACHINE_START(NEO1973_GTA02, "GTA02")
        .map_io         = gta02_map_io,
        .init_irq       = s3c2442_init_irq,
        .init_machine   = gta02_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = gta02_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index e453acd92cbf..fbf5487ae5d1 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -57,7 +57,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/gpio-cfg.h>
@@ -646,7 +645,6 @@ static struct platform_device *h1940_devices[] __initdata = {
 static void __init h1940_map_io(void)
 {
        s3c24xx_init_io(h1940_iodesc, ARRAY_SIZE(h1940_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(h1940_uartcfgs, ARRAY_SIZE(h1940_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
@@ -662,6 +660,12 @@ static void __init h1940_map_io(void)
        WARN_ON(gpiochip_add(&h1940_latch_gpiochip));
 }
+static void __init h1940_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 /* H1940 and RX3715 need to reserve this for suspend */
 static void __init h1940_reserve(void)
 {
@@ -739,6 +743,6 @@ MACHINE_START(H1940, "IPAQ-H1940")
        .reserve        = h1940_reserve,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = h1940_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = h1940_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 5faa7239e7d6..e81ea82c55f9 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -507,11 +507,16 @@ static struct syscore_ops jive_pm_syscore_ops = {
 static void __init jive_map_io(void)
 {
        s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init jive_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void jive_power_off(void)
 {
        printk(KERN_INFO "powering system down...\n");
@@ -665,6 +670,6 @@ MACHINE_START(JIVE, "JIVE")
        .init_irq       = s3c2412_init_irq,
        .map_io         = jive_map_io,
        .init_machine   = jive_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = jive_init_time,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index 9e57fd9f4f3b..5cc40ec1d254 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -54,7 +54,6 @@
 #include <linux/mtd/partitions.h>
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -525,11 +524,16 @@ static struct platform_device *mini2440_devices[] __initdata = {
 static void __init mini2440_map_io(void)
 {
        s3c24xx_init_io(mini2440_iodesc, ARRAY_SIZE(mini2440_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(mini2440_uartcfgs, ARRAY_SIZE(mini2440_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init mini2440_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
 /*
 * mini2440_features string
 *
@@ -690,6 +694,6 @@ MACHINE_START(MINI2440, "MINI2440")
        .map_io         = mini2440_map_io,
        .init_machine   = mini2440_init,
        .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = mini2440_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index 4cccaad34847..3ac2a54348d6 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -45,7 +45,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
@@ -535,11 +534,16 @@ static void __init n30_map_io(void)
 {
        s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
        n30_hwinit();
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init n30_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 /* GPB3 is the line that controls the pull-up for the USB D+ line */
 static void __init n30_init(void)
@@ -591,7 +595,7 @@ MACHINE_START(N30, "Acer-N30")
                                Ben Dooks <ben-linux@fluff.org>
        */
        .atag_offset    = 0x100,
-        .init_time      = samsung_timer_init,
+        .init_time      = n30_init_time,
        .init_machine   = n30_init,
        .init_irq       = s3c2410_init_irq,
        .map_io         = n30_map_io,
@@ -602,7 +606,7 @@ MACHINE_START(N35, "Acer-N35")
        /* Maintainer: Christer Weinigel <christer@weinigel.se>
        */
        .atag_offset    = 0x100,
-        .init_time      = samsung_timer_init,
+        .init_time      = n30_init_time,
        .init_machine   = n30_init,
        .init_irq       = s3c2410_init_irq,
        .map_io         = n30_map_io,
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index 3066851f584d..c82c281ce351 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <plat/gpio-cfg.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -135,13 +134,18 @@ static void __init nexcoder_sensorboard_init(void)
 static void __init nexcoder_map_io(void)
 {
        s3c24xx_init_io(nexcoder_iodesc, ARRAY_SIZE(nexcoder_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(nexcoder_uartcfgs, ARRAY_SIZE(nexcoder_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
        nexcoder_sensorboard_init();
 }
+static void __init nexcoder_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init nexcoder_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -154,6 +158,6 @@ MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
        .map_io         = nexcoder_map_io,
        .init_machine   = nexcoder_init,
        .init_irq       = s3c2440_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = nexcoder_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-osiris.c b/arch/arm/mach-s3c24xx/mach-osiris.c
index a4ae4bb3666d..189147b80eca 100644
--- a/arch/arm/mach-s3c24xx/mach-osiris.c
+++ b/arch/arm/mach-s3c24xx/mach-osiris.c
@@ -40,7 +40,6 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/cpu-freq.h>
 #include <plat/devs.h>
@@ -344,20 +343,13 @@ static struct i2c_board_info osiris_i2c_devs[] __initdata = {
 /* Standard Osiris devices */
 static struct platform_device *osiris_devices[] __initdata = {
+        &s3c2410_device_dclk,
        &s3c_device_i2c0,
        &s3c_device_wdt,
        &s3c_device_nand,
        &osiris_pcmcia,
 };
-static struct clk *osiris_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
 static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
        .refresh        = 7800, /* refresh period is 7.8usec */
        .auto_io        = 1,
@@ -368,23 +360,7 @@ static void __init osiris_map_io(void)
 {
        unsigned long flags;
-        /* initialise the clocks */
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-        s3c24xx_dclk1.parent = &clk_upll;
-        s3c24xx_dclk1.rate   = 24*1000*1000;
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-        s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
        s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
@@ -408,6 +384,12 @@ static void __init osiris_map_io(void)
        local_irq_restore(flags);
 }
+static void __init osiris_init_time(void)
+{
+        s3c2440_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init osiris_init(void)
 {
        register_syscore_ops(&osiris_pm_syscore_ops);
@@ -429,6 +411,6 @@ MACHINE_START(OSIRIS, "Simtec-OSIRIS")
        .map_io         = osiris_map_io,
        .init_irq       = s3c2440_init_irq,
        .init_machine   = osiris_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = osiris_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index bdb3faac2d9b..45833001186d 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -30,7 +30,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/samsung-time.h>
@@ -100,11 +99,16 @@ static struct platform_device *otom11_devices[] __initdata = {
 static void __init otom11_map_io(void)
 {
        s3c24xx_init_io(otom11_iodesc, ARRAY_SIZE(otom11_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(otom11_uartcfgs, ARRAY_SIZE(otom11_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init otom11_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init otom11_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -117,6 +121,6 @@ MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
        .map_io         = otom11_map_io,
        .init_machine   = otom11_init,
        .init_irq       = s3c2410_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = otom11_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 8c12787a8fd3..228c9094519d 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -304,11 +304,16 @@ __setup("tft=", qt2410_tft_setup);
 static void __init qt2410_map_io(void)
 {
        s3c24xx_init_io(qt2410_iodesc, ARRAY_SIZE(qt2410_iodesc));
-        s3c24xx_init_clocks(12*1000*1000);
        s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init qt2410_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init qt2410_machine_init(void)
 {
        s3c_nand_set_platdata(&qt2410_nand_info);
@@ -346,6 +351,6 @@ MACHINE_START(QT2410, "QT2410")
        .map_io         = qt2410_map_io,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = qt2410_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = qt2410_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index afb784e934c8..e2c6541909c1 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -54,7 +54,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
@@ -710,6 +709,7 @@ static struct i2c_board_info rx1950_i2c_devices[] = {
 };
 static struct platform_device *rx1950_devices[] __initdata = {
+        &s3c2410_device_dclk,
        &s3c_device_lcd,
        &s3c_device_wdt,
        &s3c_device_i2c0,
@@ -728,20 +728,9 @@ static struct platform_device *rx1950_devices[] __initdata = {
        &rx1950_leds,
 };
-static struct clk *rx1950_clocks[] __initdata = {
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-};
 static void __init rx1950_map_io(void)
 {
-        s3c24xx_clkout0.parent  = &clk_h;
-        s3c24xx_clkout1.parent  = &clk_f;
-        s3c24xx_register_clocks(rx1950_clocks, ARRAY_SIZE(rx1950_clocks));
        s3c24xx_init_io(rx1950_iodesc, ARRAY_SIZE(rx1950_iodesc));
-        s3c24xx_init_clocks(16934000);
        s3c24xx_init_uarts(rx1950_uartcfgs, ARRAY_SIZE(rx1950_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
@@ -754,6 +743,12 @@ static void __init rx1950_map_io(void)
        s3c_pm_init();
 }
+static void __init rx1950_init_time(void)
+{
+        s3c2442_init_clocks(16934000);
+        samsung_timer_init();
+}
 static void __init rx1950_init_machine(void)
 {
        int i;
@@ -816,6 +811,6 @@ MACHINE_START(RX1950, "HP iPAQ RX1950")
        .reserve        = rx1950_reserve,
        .init_irq       = s3c2442_init_irq,
        .init_machine = rx1950_init_machine,
-        .init_time      = samsung_timer_init,
+        .init_time      = rx1950_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-rx3715.c b/arch/arm/mach-s3c24xx/mach-rx3715.c
index e6535ce1bc5c..6e749ec3a2ea 100644
--- a/arch/arm/mach-s3c24xx/mach-rx3715.c
+++ b/arch/arm/mach-s3c24xx/mach-rx3715.c
@@ -46,7 +46,6 @@
 #include <mach/regs-lcd.h>
 #include <mach/gpio-samsung.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
@@ -179,11 +178,16 @@ static struct platform_device *rx3715_devices[] __initdata = {
 static void __init rx3715_map_io(void)
 {
        s3c24xx_init_io(rx3715_iodesc, ARRAY_SIZE(rx3715_iodesc));
-        s3c24xx_init_clocks(16934000);
        s3c24xx_init_uarts(rx3715_uartcfgs, ARRAY_SIZE(rx3715_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init rx3715_init_time(void)
+{
+        s3c2440_init_clocks(16934000);
+        samsung_timer_init();
+}
 /* H1940 and RX3715 need to reserve this for suspend */
 static void __init rx3715_reserve(void)
 {
@@ -210,6 +214,6 @@ MACHINE_START(RX3715, "IPAQ-RX3715")
        .reserve        = rx3715_reserve,
        .init_irq       = s3c2440_init_irq,
        .init_machine   = rx3715_init_machine,
-        .init_time      = samsung_timer_init,
+        .init_time      = rx3715_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
index 70f0900d4bca..e4dcb9aa2ca2 100644
--- a/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
+++ b/arch/arm/mach-s3c24xx/mach-s3c2416-dt.c
@@ -18,7 +18,6 @@
 #include <linux/clocksource.h>
 #include <linux/irqchip.h>
 #include <linux/of_platform.h>
-#include <linux/serial_core.h>
 #include <linux/serial_s3c.h>
 #include <asm/mach/arch.h>
@@ -29,48 +28,14 @@
 #include "common.h"
-/*
- * The following lookup table is used to override device names when devices
- * are registered from device tree. This is temporarily added to enable
- * device tree support addition for the S3C2416 architecture.
- *
- * For drivers that require platform data to be provided from the machine
- * file, a platform data pointer can also be supplied along with the
- * devices names. Usually, the platform data elements that cannot be parsed
- * from the device tree by the drivers (example: function pointers) are
- * supplied. But it should be noted that this is a temporary mechanism and
- * at some point, the drivers should be capable of parsing all the platform
- * data from the device tree.
- */
-static const struct of_dev_auxdata s3c2416_auxdata_lookup[] __initconst = {
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART,
-                                "s3c2440-uart.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x4000,
-                                "s3c2440-uart.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0x8000,
-                                "s3c2440-uart.2", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-uart", S3C24XX_PA_UART + 0xC000,
-                                "s3c2440-uart.3", NULL),
-        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC0,
-                                "s3c-sdhci.0", NULL),
-        OF_DEV_AUXDATA("samsung,s3c6410-sdhci", S3C_PA_HSMMC1,
-                                "s3c-sdhci.1", NULL),
-        OF_DEV_AUXDATA("samsung,s3c2440-i2c", S3C_PA_IIC,
-                                "s3c2440-i2c.0", NULL),
-        {},
-};
 static void __init s3c2416_dt_map_io(void)
 {
        s3c24xx_init_io(NULL, 0);
-        s3c24xx_init_clocks(12000000);
 }
 static void __init s3c2416_dt_machine_init(void)
 {
-        of_platform_populate(NULL, of_default_bus_match_table,
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-                                s3c2416_auxdata_lookup, NULL);
        s3c_pm_init();
 }
@@ -86,6 +51,5 @@ DT_MACHINE_START(S3C2416_DT, "Samsung S3C2416 (Flattened Device Tree)")
        .map_io         = s3c2416_dt_map_io,
        .init_irq       = irqchip_init,
        .init_machine   = s3c2416_dt_machine_init,
-         .init_time     = clocksource_of_init,
        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index f32924ee0e9f..419fadd6e446 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -99,11 +99,16 @@ static struct platform_device *smdk2410_devices[] __initdata = {
 static void __init smdk2410_map_io(void)
 {
        s3c24xx_init_io(smdk2410_iodesc, ARRAY_SIZE(smdk2410_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(smdk2410_uartcfgs, ARRAY_SIZE(smdk2410_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init smdk2410_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init smdk2410_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -118,6 +123,6 @@ MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switc
        .map_io         = smdk2410_map_io,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = smdk2410_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2410_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 233fe52d2015..fb3b80e44595 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -22,6 +22,7 @@
 #include <linux/serial_s3c.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/memblock.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -93,24 +94,26 @@ static struct platform_device *smdk2413_devices[] __initdata = {
        &s3c2412_device_dma,
 };
-static void __init smdk2413_fixup(struct tag *tags, char **cmdline,
+static void __init smdk2413_fixup(struct tag *tags, char **cmdline)
-                                  struct meminfo *mi)
 {
        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
-                mi->nr_banks=1;
+                memblock_add(0x30000000, SZ_64M);
-                mi->bank[0].start = 0x30000000;
-                mi->bank[0].size = SZ_64M;
        }
 }
 static void __init smdk2413_map_io(void)
 {
        s3c24xx_init_io(smdk2413_iodesc, ARRAY_SIZE(smdk2413_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk2413_uartcfgs, ARRAY_SIZE(smdk2413_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init smdk2413_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init smdk2413_machine_init(void)
 {       /* Turn off suspend on both USB ports, and switch the
         * selectable USB port to USB device mode. */
@@ -159,6 +162,6 @@ MACHINE_START(SMDK2413, "SMDK2413")
        .init_irq       = s3c2412_init_irq,
        .map_io         = smdk2413_map_io,
        .init_machine   = smdk2413_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2413_init_time,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index b3b54d8e1410..fa6f30d23601 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -219,10 +219,15 @@ static struct platform_device *smdk2416_devices[] __initdata = {
        &s3c2443_device_dma,
 };
+static void __init smdk2416_init_time(void)
+{
+        s3c2416_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init smdk2416_map_io(void)
 {
        s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
@@ -257,6 +262,6 @@ MACHINE_START(SMDK2416, "SMDK2416")
        .init_irq       = s3c2416_init_irq,
        .map_io         = smdk2416_map_io,
        .init_machine   = smdk2416_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2416_init_time,
        .restart        = s3c2416_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index d071dcfea548..5fb89c0ae17a 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,7 +38,6 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
-#include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/samsung-time.h>
@@ -159,11 +158,16 @@ static struct platform_device *smdk2440_devices[] __initdata = {
 static void __init smdk2440_map_io(void)
 {
        s3c24xx_init_io(smdk2440_iodesc, ARRAY_SIZE(smdk2440_iodesc));
-        s3c24xx_init_clocks(16934400);
        s3c24xx_init_uarts(smdk2440_uartcfgs, ARRAY_SIZE(smdk2440_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init smdk2440_init_time(void)
+{
+        s3c2440_init_clocks(16934400);
+        samsung_timer_init();
+}
 static void __init smdk2440_machine_init(void)
 {
        s3c24xx_fb_set_platdata(&smdk2440_fb_info);
@@ -180,6 +184,6 @@ MACHINE_START(S3C2440, "SMDK2440")
        .init_irq       = s3c2440_init_irq,
        .map_io         = smdk2440_map_io,
        .init_machine   = smdk2440_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2440_init_time,
        .restart        = s3c244x_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index 06c4d77de3a5..ef5d5ea33182 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -121,11 +121,16 @@ static struct platform_device *smdk2443_devices[] __initdata = {
 static void __init smdk2443_map_io(void)
 {
        s3c24xx_init_io(smdk2443_iodesc, ARRAY_SIZE(smdk2443_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(smdk2443_uartcfgs, ARRAY_SIZE(smdk2443_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init smdk2443_init_time(void)
+{
+        s3c2443_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init smdk2443_machine_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -145,6 +150,6 @@ MACHINE_START(SMDK2443, "SMDK2443")
        .init_irq       = s3c2443_init_irq,
        .map_io         = smdk2443_map_io,
        .init_machine   = smdk2443_machine_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = smdk2443_init_time,
        .restart        = s3c2443_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-tct_hammer.c b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
index 4108b2f0cede..c616ca2d409e 100644
--- a/arch/arm/mach-s3c24xx/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c24xx/mach-tct_hammer.c
@@ -135,11 +135,16 @@ static struct platform_device *tct_hammer_devices[] __initdata = {
 static void __init tct_hammer_map_io(void)
 {
        s3c24xx_init_io(tct_hammer_iodesc, ARRAY_SIZE(tct_hammer_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(tct_hammer_uartcfgs, ARRAY_SIZE(tct_hammer_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init tct_hammer_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init tct_hammer_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -151,6 +156,6 @@ MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
        .map_io         = tct_hammer_map_io,
        .init_irq       = s3c2410_init_irq,
        .init_machine   = tct_hammer_init,
-        .init_time      = samsung_timer_init,
+        .init_time      = tct_hammer_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 1cc5b1bd51cd..f88c584c3001 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -43,7 +43,6 @@
 #include <mach/regs-gpio.h>
 #include <mach/gpio-samsung.h>
-#include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/samsung-time.h>
@@ -286,6 +285,7 @@ static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
 /* devices for this board */
 static struct platform_device *vr1000_devices[] __initdata = {
+        &s3c2410_device_dclk,
        &s3c_device_ohci,
        &s3c_device_lcd,
        &s3c_device_wdt,
@@ -299,14 +299,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
        &vr1000_led3,
 };
-static struct clk *vr1000_clocks[] __initdata = {
-        &s3c24xx_dclk0,
-        &s3c24xx_dclk1,
-        &s3c24xx_clkout0,
-        &s3c24xx_clkout1,
-        &s3c24xx_uclk,
-};
 static void vr1000_power_off(void)
 {
        gpio_direction_output(S3C2410_GPB(9), 1);
@@ -314,29 +306,19 @@ static void vr1000_power_off(void)
 static void __init vr1000_map_io(void)
 {
-        /* initialise clock sources */
-        s3c24xx_dclk0.parent = &clk_upll;
-        s3c24xx_dclk0.rate   = 12*1000*1000;
-        s3c24xx_dclk1.parent = NULL;
-        s3c24xx_dclk1.rate   = 3692307;
-        s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
-        s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
-        s3c24xx_uclk.parent  = &s3c24xx_clkout1;
-        s3c24xx_register_clocks(vr1000_clocks, ARRAY_SIZE(vr1000_clocks));
        pm_power_off = vr1000_power_off;
        s3c24xx_init_io(vr1000_iodesc, ARRAY_SIZE(vr1000_iodesc));
-        s3c24xx_init_clocks(0);
        s3c24xx_init_uarts(vr1000_uartcfgs, ARRAY_SIZE(vr1000_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init vr1000_init_time(void)
+{
+        s3c2410_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init vr1000_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -357,6 +339,6 @@ MACHINE_START(VR1000, "Thorcom-VR1000")
        .map_io         = vr1000_map_io,
        .init_machine   = vr1000_init,
        .init_irq       = s3c2410_init_irq,
-        .init_time      = samsung_timer_init,
+        .init_time      = vr1000_init_time,
        .restart        = s3c2410_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 40868c0e0a68..9104c2be36c9 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -23,6 +23,7 @@
 #include <linux/mtd/nand.h>
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
+#include <linux/memblock.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -129,24 +130,26 @@ static struct platform_device *vstms_devices[] __initdata = {
        &s3c2412_device_dma,
 };
-static void __init vstms_fixup(struct tag *tags, char **cmdline,
+static void __init vstms_fixup(struct tag *tags, char **cmdline)
-                               struct meminfo *mi)
 {
        if (tags != phys_to_virt(S3C2410_SDRAM_PA + 0x100)) {
-                mi->nr_banks=1;
+                memblock_add(0x30000000, SZ_64M);
-                mi->bank[0].start = 0x30000000;
-                mi->bank[0].size = SZ_64M;
        }
 }
 static void __init vstms_map_io(void)
 {
        s3c24xx_init_io(vstms_iodesc, ARRAY_SIZE(vstms_iodesc));
-        s3c24xx_init_clocks(12000000);
        s3c24xx_init_uarts(vstms_uartcfgs, ARRAY_SIZE(vstms_uartcfgs));
        samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
 }
+static void __init vstms_init_time(void)
+{
+        s3c2412_init_clocks(12000000);
+        samsung_timer_init();
+}
 static void __init vstms_init(void)
 {
        s3c_i2c0_set_platdata(NULL);
@@ -162,6 +165,6 @@ MACHINE_START(VSTMS, "VSTMS")
        .init_irq       = s3c2412_init_irq,
        .init_machine   = vstms_init,
        .map_io         = vstms_map_io,
-        .init_time      = samsung_timer_init,
+        .init_time      = vstms_init_time,
        .restart        = s3c2412_restart,
 MACHINE_END
diff --git a/arch/arm/mach-s3c24xx/pm.c b/arch/arm/mach-s3c24xx/pm.c
index 68ea5b7e5dc7..b19256ec8d40 100644
--- a/arch/arm/mach-s3c24xx/pm.c
+++ b/arch/arm/mach-s3c24xx/pm.c
@@ -51,9 +51,6 @@
 #define PFX "s3c24xx-pm: "
 static struct sleep_save core_save[] = {
-        SAVE_ITEM(S3C2410_LOCKTIME),
-        SAVE_ITEM(S3C2410_CLKCON),
        /* we restore the timings here, with the proviso that the board
         * brings the system up in an slower, or equal frequency setting
         * to the original system.
@@ -69,18 +66,6 @@ static struct sleep_save core_save[] = {
        SAVE_ITEM(S3C2410_BANKCON3),
        SAVE_ITEM(S3C2410_BANKCON4),
        SAVE_ITEM(S3C2410_BANKCON5),
-#ifndef CONFIG_CPU_FREQ
-        SAVE_ITEM(S3C2410_CLKDIVN),
-        SAVE_ITEM(S3C2410_MPLLCON),
-        SAVE_ITEM(S3C2410_REFRESH),
-#endif
-        SAVE_ITEM(S3C2410_UPLLCON),
-        SAVE_ITEM(S3C2410_CLKSLOW),
-};
-static struct sleep_save misc_save[] = {
-        SAVE_ITEM(S3C2410_DCLKCON),
 };
 /* s3c_pm_check_resume_pin
@@ -140,12 +125,10 @@ void s3c_pm_configure_extint(void)
 void s3c_pm_restore_core(void)
 {
        s3c_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
-        s3c_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
 }
 void s3c_pm_save_core(void)
 {
-        s3c_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
        s3c_pm_do_save(core_save, ARRAY_SIZE(core_save));
 }
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 04b58cb49888..7eab88829883 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -85,62 +85,6 @@ void __init s3c2410_map_io(void)
 void __init_or_cpufreq s3c2410_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long tmp;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-        /* now we've got our machine bits initialised, work out what
-         * clocks we've got */
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal);
-        tmp = __raw_readl(S3C2410_CLKDIVN);
-        /* work out clock scalings */
-        hclk = fclk / ((tmp & S3C2410_CLKDIVN_HDIVN) ? 2 : 1);
-        pclk = hclk / ((tmp & S3C2410_CLKDIVN_PDIVN) ? 2 : 1);
-        /* print brieft summary of clocks, etc */
-        printk("S3C2410: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-        /* initialise the clocks here, to allow other things like the
-         * console to use them
-         */
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-/* fake ARMCLK for use with cpufreq, etc. */
-static struct clk s3c2410_armclk = {
-        .name   = "armclk",
-        .parent = &clk_f,
-        .id     = -1,
-};
-static struct clk_lookup s3c2410_clk_lookup[] = {
-        CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p),
-        CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk),
-};
-void __init s3c2410_init_clocks(int xtal)
-{
-        s3c24xx_register_baseclocks(xtal);
-        s3c2410_setup_clocks();
-        s3c2410_baseclk_add();
-        s3c24xx_register_clock(&s3c2410_armclk);
-        clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup));
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 struct bus_type s3c2410_subsys = {
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 657cbaca80ac..d49f52fbc842 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -173,49 +173,6 @@ void __init s3c2412_map_io(void)
 void __init_or_cpufreq s3c2412_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long tmp;
-        unsigned long xtal;
-        unsigned long fclk;
-        unsigned long hclk;
-        unsigned long pclk;
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-        /* now we've got our machine bits initialised, work out what
-         * clocks we've got */
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2);
-        clk_mpll.rate = fclk;
-        tmp = __raw_readl(S3C2410_CLKDIVN);
-        /* work out clock scalings */
-        hclk = fclk / ((tmp & S3C2412_CLKDIVN_HDIVN_MASK) + 1);
-        hclk /= ((tmp & S3C2412_CLKDIVN_ARMDIVN) ? 2 : 1);
-        pclk = hclk / ((tmp & S3C2412_CLKDIVN_PDIVN) ? 2 : 1);
-        /* print brieft summary of clocks, etc */
-        printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-void __init s3c2412_init_clocks(int xtal)
-{
-        /* initialise the clocks here, to allow other things like the
-         * console to use them
-         */
-        s3c24xx_register_baseclocks(xtal);
-        s3c2412_setup_clocks();
-        s3c2412_baseclk_add();
 }
 /* need to register the subsystem before we actually register the device, and
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index 2c8adc028538..fb9da2b603a2 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -53,117 +53,6 @@
 #include "common.h"
-/* S3C2442 extended clock support */
-static unsigned long s3c2442_camif_upll_round(struct clk *clk,
-                                              unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        int div;
-        if (rate > parent_rate)
-                return parent_rate;
-        div = parent_rate / rate;
-        if (div == 3)
-                return parent_rate / 3;
-        /* note, we remove the +/- 1 calculations for the divisor */
-        div /= 2;
-        if (div < 1)
-                div = 1;
-        else if (div > 16)
-                div = 16;
-        return parent_rate / (div * 2);
-}
-static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
-{
-        unsigned long parent_rate = clk_get_rate(clk->parent);
-        unsigned long camdivn =  __raw_readl(S3C2440_CAMDIVN);
-        rate = s3c2442_camif_upll_round(clk, rate);
-        camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
-        if (rate == parent_rate) {
-                camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
-        } else if ((parent_rate / rate) == 3) {
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
-        } else {
-                camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
-                camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
-                camdivn |= (((parent_rate / rate) / 2) - 1);
-        }
-        __raw_writel(camdivn, S3C2440_CAMDIVN);
-        return 0;
-}
-/* Extra S3C2442 clocks */
-static struct clk s3c2442_clk_cam = {
-        .name           = "camif",
-        .id             = -1,
-        .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
-};
-static struct clk s3c2442_clk_cam_upll = {
-        .name           = "camif-upll",
-        .id             = -1,
-        .ops            = &(struct clk_ops) {
-                .set_rate       = s3c2442_camif_upll_setrate,
-                .round_rate     = s3c2442_camif_upll_round,
-        },
-};
-static int s3c2442_clk_add(struct device *dev, struct subsys_interface *sif)
-{
-        struct clk *clock_upll;
-        struct clk *clock_h;
-        struct clk *clock_p;
-        clock_p = clk_get(NULL, "pclk");
-        clock_h = clk_get(NULL, "hclk");
-        clock_upll = clk_get(NULL, "upll");
-        if (IS_ERR(clock_p) || IS_ERR(clock_h) || IS_ERR(clock_upll)) {
-                printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
-                return -EINVAL;
-        }
-        s3c2442_clk_cam.parent = clock_h;
-        s3c2442_clk_cam_upll.parent = clock_upll;
-        s3c24xx_register_clock(&s3c2442_clk_cam);
-        s3c24xx_register_clock(&s3c2442_clk_cam_upll);
-        clk_disable(&s3c2442_clk_cam);
-        return 0;
-}
-static struct subsys_interface s3c2442_clk_interface = {
-        .name           = "s3c2442_clk",
-        .subsys         = &s3c2442_subsys,
-        .add_dev        = s3c2442_clk_add,
-};
-static __init int s3c2442_clk_init(void)
-{
-        return subsys_interface_register(&s3c2442_clk_interface);
-}
-arch_initcall(s3c2442_clk_init);
 static struct device s3c2442_dev = {
        .bus            = &s3c2442_subsys,
 };
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index fe30ebb234d2..4a64bcc9eb51 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -46,6 +46,7 @@
 #include <plat/nand-core.h>
 #include <plat/watchdog-reset.h>
+#include "common.h"
 #include "regs-dsc.h"
 static struct map_desc s3c244x_iodesc[] __initdata = {
@@ -74,67 +75,11 @@ void __init s3c244x_map_io(void)
        s3c_nand_setname("s3c2440-nand");
        s3c_device_ts.name = "s3c2440-ts";
        s3c_device_usbgadget.name = "s3c2440-usbgadget";
+        s3c2410_device_dclk.name = "s3c2440-dclk";
 }
 void __init_or_cpufreq s3c244x_setup_clocks(void)
 {
-        struct clk *xtal_clk;
-        unsigned long clkdiv;
-        unsigned long camdiv;
-        unsigned long xtal;
-        unsigned long hclk, fclk, pclk;
-        int hdiv = 1;
-        xtal_clk = clk_get(NULL, "xtal");
-        xtal = clk_get_rate(xtal_clk);
-        clk_put(xtal_clk);
-        fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
-        clkdiv = __raw_readl(S3C2410_CLKDIVN);
-        camdiv = __raw_readl(S3C2440_CAMDIVN);
-        /* work out clock scalings */
-        switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
-        case S3C2440_CLKDIVN_HDIVN_1:
-                hdiv = 1;
-                break;
-        case S3C2440_CLKDIVN_HDIVN_2:
-                hdiv = 2;
-                break;
-        case S3C2440_CLKDIVN_HDIVN_4_8:
-                hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
-                break;
-        case S3C2440_CLKDIVN_HDIVN_3_6:
-                hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
-                break;
-        }
-        hclk = fclk / hdiv;
-        pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1);
-        /* print brief summary of clocks, etc */
-        printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
-               print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
-        s3c24xx_setup_clocks(fclk, hclk, pclk);
-}
-void __init s3c244x_init_clocks(int xtal)
-{
-        /* initialise the clocks here, to allow other things like the
-         * console to use them, and to add new ones after the initialisation
-         */
-        s3c24xx_register_baseclocks(xtal);
-        s3c244x_setup_clocks();
-        s3c2410_baseclk_add();
-        samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG);
 }
 /* Since the S3C2442 and S3C2440 share items, put both subsystems here */
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index b41a38a75844..6c719eccb94e 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -49,11 +49,6 @@
 #include <plat/clock.h>
 #include <plat/samsung-time.h>
 #include <plat/mfc.h>
-#include <plat/camport.h>
-#include <media/v4l2-mediabus.h>
-#include <media/s5p_fimc.h>
-#include <media/noon010pc30.h>
 #include "common.h"
@@ -285,14 +280,6 @@ static void __init goni_tsp_init(void)
 /* USB OTG */
 static struct s3c_hsotg_plat goni_hsotg_pdata;
-static void goni_camera_init(void)
-{
-        s5pv210_fimc_setup_gpio(S5P_CAMPORT_A);
-        /* Set max driver strength on CAM_A_CLKOUT pin. */
-        s5p_gpio_set_drvstr(S5PV210_GPE1(3), S5P_GPIO_DRVSTR_LV4);
-}
 /* MAX8998 regulators */
 #if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
@@ -825,34 +812,6 @@ static void goni_setup_sdhci(void)
        s3c_sdhci2_set_platdata(&goni_hsmmc2_data);
 };
-static struct noon010pc30_platform_data noon010pc30_pldata = {
-        .clk_rate       = 16000000UL,
-        .gpio_nreset    = S5PV210_GPB(2), /* CAM_CIF_NRST */
-        .gpio_nstby     = S5PV210_GPB(0), /* CAM_CIF_NSTBY */
-};
-static struct i2c_board_info noon010pc30_board_info = {
-        I2C_BOARD_INFO("NOON010PC30", 0x60 >> 1),
-        .platform_data = &noon010pc30_pldata,
-};
-static struct fimc_source_info goni_camera_sensors[] = {
-        {
-                .mux_id         = 0,
-                .flags          = V4L2_MBUS_PCLK_SAMPLE_FALLING |
-                                  V4L2_MBUS_VSYNC_ACTIVE_LOW,
-                .fimc_bus_type  = FIMC_BUS_TYPE_ITU_601,
-                .board_info     = &noon010pc30_board_info,
-                .i2c_bus_num    = 0,
-                .clk_frequency  = 16000000UL,
-        },
-};
-static struct s5p_platform_fimc goni_fimc_md_platdata __initdata = {
-        .source_info    = goni_camera_sensors,
-        .num_clients    = ARRAY_SIZE(goni_camera_sensors),
-};
 /* Audio device */
 static struct platform_device goni_device_audio = {
        .name = "smdk-audio",
@@ -874,10 +833,6 @@ static struct platform_device *goni_devices[] __initdata = {
        &s5p_device_mixer,
        &s5p_device_sdo,
        &s3c_device_i2c0,
-        &s5p_device_fimc0,
-        &s5p_device_fimc1,
-        &s5p_device_fimc2,
-        &s5p_device_fimc_md,
        &s3c_device_hsmmc0,
        &s3c_device_hsmmc1,
        &s3c_device_hsmmc2,
@@ -946,14 +901,8 @@ static void __init goni_machine_init(void)
        /* FB */
        s3c_fb_set_platdata(&goni_lcd_pdata);
-        /* FIMC */
-        s3c_set_platdata(&goni_fimc_md_platdata, sizeof(goni_fimc_md_platdata),
-                         &s5p_device_fimc_md);
        s3c_hsotg_set_platdata(&goni_hsotg_pdata);
-        goni_camera_init();
        /* SPI */
        spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 8443a27bca2f..7dd894ece9ae 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -531,7 +531,7 @@ static void __init get_assabet_scr(void)
 }
 static void __init
-fixup_assabet(struct tag *tags, char **cmdline, struct meminfo *mi)
+fixup_assabet(struct tag *tags, char **cmdline)
 {
        /* This must be done before any call to machine_has_neponset() */
        map_sa1100_gpio_regs();
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 0f92ba8e7884..dbd954e61aa7 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -8,7 +8,6 @@ config ARCH_SHMOBILE_MULTI
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select ARM_GIC
-        select MIGHT_HAVE_PCI
        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
        select NO_IOPORT_MAP
        select PINCTRL
@@ -108,6 +107,7 @@ config ARCH_R8A7778
        select SH_CLK_CPG
        select ARM_GIC
        select SYS_SUPPORTS_SH_TMU
+        select RENESAS_INTC_IRQPIN
 config ARCH_R8A7779
        bool "R-Car H1 (R8A77790)"
@@ -140,16 +140,6 @@ config ARCH_R8A7791
        select SYS_SUPPORTS_SH_CMT
        select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
-config ARCH_EMEV2
-        bool "Emma Mobile EV2"
-        select ARCH_WANT_OPTIONAL_GPIOLIB
-        select ARM_GIC
-        select CPU_V7
-        select MIGHT_HAVE_PCI
-        select USE_OF
-        select AUTO_ZRELADDR
-        select SYS_SUPPORTS_EM_STI
 config ARCH_R7S72100
        bool "RZ/A1H (R7S72100)"
        select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -205,8 +195,8 @@ config MACH_ARMADILLO800EVA_REFERENCE
        select SND_SOC_WM8978 if SND_SIMPLE_CARD
        select USE_OF
        ---help---
-           Use reference implementation of Aramdillo800 EVA board support
+           Use reference implementation of Armadillo800 EVA board support
-           which makes a greater use of device tree at the expense
+           which makes greater use of device tree at the expense
           of not supporting a number of devices.
           This is intended to aid developers
@@ -216,7 +206,6 @@ config MACH_BOCKW
        depends on ARCH_R8A7778
        select ARCH_REQUIRE_GPIOLIB
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
-        select RENESAS_INTC_IRQPIN
        select SND_SOC_AK4554 if SND_SIMPLE_CARD
        select SND_SOC_AK4642 if SND_SIMPLE_CARD
        select USE_OF
@@ -225,7 +214,6 @@ config MACH_BOCKW_REFERENCE
        bool "BOCK-W  - Reference Device Tree Implementation"
        depends on ARCH_R8A7778
        select ARCH_REQUIRE_GPIOLIB
-        select RENESAS_INTC_IRQPIN
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select USE_OF
        ---help---
@@ -240,17 +228,6 @@ config MACH_GENMAI
        depends on ARCH_R7S72100
        select USE_OF
-config MACH_GENMAI_REFERENCE
-        bool "Genmai board - Reference Device Tree Implementation"
-        depends on ARCH_R7S72100
-        select USE_OF
-        ---help---
-           Use reference implementation of Genmai board support
-           which makes use of device tree at the expense
-           of not supporting a number of devices.
-           This is intended to aid developers
 config MACH_MARZEN
        bool "MARZEN board"
        depends on ARCH_R8A7779
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 4caffc912a81..38d5fe825e93 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -21,8 +21,8 @@ obj-$(CONFIG_ARCH_EMEV2)	+= setup-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)     += setup-r7s72100.o
 # Clock objects
-ifndef CONFIG_COMMON_CLK
 obj-y                           += clock.o
+ifndef CONFIG_COMMON_CLK
 obj-$(CONFIG_ARCH_SH7372)       += clock-sh7372.o
 obj-$(CONFIG_ARCH_SH73A0)       += clock-sh73a0.o
 obj-$(CONFIG_ARCH_R8A73A4)      += clock-r8a73a4.o
@@ -31,7 +31,6 @@ obj-$(CONFIG_ARCH_R8A7778)	+= clock-r8a7778.o
 obj-$(CONFIG_ARCH_R8A7779)      += clock-r8a7779.o
 obj-$(CONFIG_ARCH_R8A7790)      += clock-r8a7790.o
 obj-$(CONFIG_ARCH_R8A7791)      += clock-r8a7791.o
-obj-$(CONFIG_ARCH_EMEV2)        += clock-emev2.o
 obj-$(CONFIG_ARCH_R7S72100)     += clock-r7s72100.o
 endif
@@ -67,7 +66,6 @@ obj-$(CONFIG_MACH_MACKEREL)	+= board-mackerel.o
 obj-$(CONFIG_MACH_BOCKW)        += board-bockw.o
 obj-$(CONFIG_MACH_BOCKW_REFERENCE)      += board-bockw-reference.o
 obj-$(CONFIG_MACH_GENMAI)       += board-genmai.o
-obj-$(CONFIG_MACH_GENMAI_REFERENCE)     += board-genmai-reference.o
 obj-$(CONFIG_MACH_MARZEN)       += board-marzen.o
 obj-$(CONFIG_MACH_MARZEN_REFERENCE)     += board-marzen-reference.o
 obj-$(CONFIG_MACH_LAGER)        += board-lager.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 99455ecafa05..918fccffa1b6 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -7,7 +7,6 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
 loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
 loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
 loadaddr-$(CONFIG_MACH_GENMAI) += 0x08008000
-loadaddr-$(CONFIG_MACH_GENMAI_REFERENCE) += 0x08008000
 loadaddr-$(CONFIG_MACH_KOELSCH) += 0x40008000
 loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
 loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 57d1a78367b6..f660fbb96e0b 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -164,8 +164,8 @@ static void __init eva_init(void)
        r8a7740_meram_workaround();
 #ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        /* Shared attribute override enable, 32K*8way */
-        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+        l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
 #endif
        r8a7740_add_standard_devices_dt();
@@ -187,7 +187,7 @@ static const char *eva_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
        .map_io         = r8a7740_map_io,
-        .init_early     = r8a7740_init_delay,
+        .init_early     = shmobile_init_delay,
        .init_irq       = r8a7740_init_irq_of,
        .init_machine   = eva_init,
        .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 486063db2a2f..01f81100c330 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -1017,7 +1017,7 @@ static struct asoc_simple_card_info fsi2_hdmi_info = {
        .platform       = "sh_fsi2",
        .cpu_dai = {
                .name   = "fsib-dai",
-                .fmt    = SND_SOC_DAIFMT_CBM_CFM,
+                .fmt    = SND_SOC_DAIFMT_CBS_CFS,
        },
        .codec_dai = {
                .name = "sh_mobile_hdmi-hifi",
@@ -1271,8 +1271,8 @@ static void __init eva_init(void)
 #ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 32K*8way */
+        /* Shared attribute override enable, 32K*8way */
-        l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
+        l2x0_init(IOMEM(0xf0002000), 0x00400000, 0xc20f0fff);
 #endif
        i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
@@ -1300,11 +1300,6 @@ static void __init eva_earlytimer_init(void)
        eva_clock_init();
 }
-static void __init eva_add_early_devices(void)
-{
-        r8a7740_add_early_devices();
-}
 #define RESCNT2 IOMEM(0xe6188020)
 static void eva_restart(enum reboot_mode mode, const char *cmd)
 {
@@ -1319,7 +1314,7 @@ static const char *eva_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
        .map_io         = r8a7740_map_io,
-        .init_early     = eva_add_early_devices,
+        .init_early     = r8a7740_add_early_devices,
        .init_irq       = r8a7740_init_irq_of,
        .init_machine   = eva_init,
        .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index b4122f8cb8d9..f444be2f241e 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -345,24 +345,39 @@ static struct rsnd_ssi_platform_info rsnd_ssi[] = {
        RSND_SSI_UNUSED, /* SSI 0 */
        RSND_SSI_UNUSED, /* SSI 1 */
        RSND_SSI_UNUSED, /* SSI 2 */
-        RSND_SSI_SET(1, HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), RSND_SSI_PLAY),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF3_TX, gic_iid(0x85), 0),
-        RSND_SSI_SET(2, HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF4_RX, gic_iid(0x85), RSND_SSI_CLK_PIN_SHARE),
-        RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), RSND_SSI_PLAY),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF5_TX, gic_iid(0x86), 0),
-        RSND_SSI_SET(0, HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF6_RX, gic_iid(0x86), 0),
-        RSND_SSI_SET(3, HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), RSND_SSI_PLAY),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF7_TX, gic_iid(0x86), 0),
-        RSND_SSI_SET(4, HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
+        RSND_SSI(HPBDMA_SLAVE_HPBIF8_RX, gic_iid(0x86), RSND_SSI_CLK_PIN_SHARE),
 };
-static struct rsnd_scu_platform_info rsnd_scu[9] = {
+static struct rsnd_src_platform_info rsnd_src[9] = {
-        { .flags = 0, }, /* SRU 0 */
+        RSND_SRC_UNUSED, /* SRU 0 */
-        { .flags = 0, }, /* SRU 1 */
+        RSND_SRC_UNUSED, /* SRU 1 */
-        { .flags = 0, }, /* SRU 2 */
+        RSND_SRC_UNUSED, /* SRU 2 */
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
-        { .flags = RSND_SCU_USE_HPBIF, },
+        RSND_SRC(0, 0),
+};
+static struct rsnd_dai_platform_info rsnd_dai[] = {
+        {
+                .playback = { .ssi = &rsnd_ssi[5], .src = &rsnd_src[5] },
+                .capture  = { .ssi = &rsnd_ssi[6], .src = &rsnd_src[6] },
+        }, {
+                .playback = { .ssi = &rsnd_ssi[3], .src = &rsnd_src[3] },
+        }, {
+                .capture  = { .ssi = &rsnd_ssi[4], .src = &rsnd_src[4] },
+        }, {
+                .playback = { .ssi = &rsnd_ssi[7], .src = &rsnd_src[7] },
+        }, {
+                .capture  = { .ssi = &rsnd_ssi[8], .src = &rsnd_src[8] },
+        },
 };
 enum {
@@ -437,8 +452,10 @@ static struct rcar_snd_info rsnd_info = {
        .flags          = RSND_GEN1,
        .ssi_info       = rsnd_ssi,
        .ssi_info_nr    = ARRAY_SIZE(rsnd_ssi),
-        .scu_info       = rsnd_scu,
+        .src_info       = rsnd_src,
-        .scu_info_nr    = ARRAY_SIZE(rsnd_scu),
+        .src_info_nr    = ARRAY_SIZE(rsnd_src),
+        .dai_info       = rsnd_dai,
+        .dai_info_nr    = ARRAY_SIZE(rsnd_dai),
        .start          = rsnd_start,
        .stop           = rsnd_stop,
 };
@@ -591,6 +608,7 @@ static void __init bockw_init(void)
 {
        void __iomem *base;
        struct clk *clk;
+        struct platform_device *pdev;
        int i;
        r8a7778_clock_init();
@@ -673,9 +691,6 @@ static void __init bockw_init(void)
        }
        /* for Audio */
-        clk = clk_get(NULL, "audio_clk_b");
-        clk_set_rate(clk, 24576000);
-        clk_put(clk);
        rsnd_codec_power(5, 1); /* enable ak4642 */
        platform_device_register_simple(
@@ -684,11 +699,15 @@ static void __init bockw_init(void)
        platform_device_register_simple(
                "ak4554-adc-dac", 1, NULL, 0);
-        platform_device_register_resndata(
+        pdev = platform_device_register_resndata(
                &platform_bus, "rcar_sound", -1,
                rsnd_resources, ARRAY_SIZE(rsnd_resources),
                &rsnd_info, sizeof(rsnd_info));
+        clk = clk_get(&pdev->dev, "clk_b");
+        clk_set_rate(clk, 24576000);
+        clk_put(clk);
        for (i = 0; i < ARRAY_SIZE(rsnd_card_info); i++) {
                struct platform_device_info cardinfo = {
                        .parent         = &platform_bus,
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c
index 7630c1053e32..2ff6ad6e608e 100644
--- a/arch/arm/mach-shmobile/board-genmai-reference.c
+++ b/arch/arm/mach-shmobile/board-genmai-reference.c
@@ -18,27 +18,31 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <linux/clk-provider.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/r7s72100.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+/*
+ * This is a really crude hack to provide clkdev support to platform
+ * devices until they get moved to DT.
+ */
+static const struct clk_name clk_names[] = {
+        { "mtu2", "fck", "sh-mtu2" },
+};
 static void __init genmai_add_standard_devices(void)
 {
-#ifdef CONFIG_COMMON_CLK
+        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), true);
-        of_clk_init(NULL);
-#else
-        r7s72100_clock_init();
-#endif
        r7s72100_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
 static const char * const genmai_boards_compat_dt[] __initconst = {
-        "renesas,genmai-reference",
+        "renesas,genmai",
        NULL,
 };
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c
index 6c328d63b819..c94201ee8596 100644
--- a/arch/arm/mach-shmobile/board-genmai.c
+++ b/arch/arm/mach-shmobile/board-genmai.c
@@ -21,6 +21,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
+#include <linux/serial_sci.h>
 #include <linux/sh_eth.h>
 #include <linux/spi/rspi.h>
 #include <linux/spi/spi.h>
@@ -89,6 +90,40 @@ static const struct spi_board_info spi_info[] __initconst = {
        },
 };
+/* SCIF */
+#define R7S72100_SCIF(index, baseaddr, irq)                             \
+static const struct plat_sci_port scif##index##_platform_data = {       \
+        .type           = PORT_SCIF,                                    \
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,               \
+        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
+                          SCSCR_REIE,                                   \
+};                                                                      \
+                                                                        \
+static struct resource scif##index##_resources[] = {                    \
+        DEFINE_RES_MEM(baseaddr, 0x100),                                \
+        DEFINE_RES_IRQ(irq + 1),                                        \
+        DEFINE_RES_IRQ(irq + 2),                                        \
+        DEFINE_RES_IRQ(irq + 3),                                        \
+        DEFINE_RES_IRQ(irq),                                            \
+}                                                                       \
+R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
+R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
+R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
+R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
+R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
+R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
+R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
+R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
+#define r7s72100_register_scif(index)                                          \
+        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
+                                          scif##index##_resources,             \
+                                          ARRAY_SIZE(scif##index##_resources), \
+                                          &scif##index##_platform_data,        \
+                                          sizeof(scif##index##_platform_data))
 static void __init genmai_add_standard_devices(void)
 {
        r7s72100_clock_init();
@@ -102,6 +137,15 @@ static void __init genmai_add_standard_devices(void)
        r7s72100_register_rspi(3);
        r7s72100_register_rspi(4);
        spi_register_board_info(spi_info, ARRAY_SIZE(spi_info));
+        r7s72100_register_scif(0);
+        r7s72100_register_scif(1);
+        r7s72100_register_scif(2);
+        r7s72100_register_scif(3);
+        r7s72100_register_scif(4);
+        r7s72100_register_scif(5);
+        r7s72100_register_scif(6);
+        r7s72100_register_scif(7);
 }
 static const char * const genmai_boards_compat_dt[] __initconst = {
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c
index a3fd30242bd8..d322a162b4b0 100644
--- a/arch/arm/mach-shmobile/board-koelsch-reference.c
+++ b/arch/arm/mach-shmobile/board-koelsch-reference.c
@@ -19,12 +19,11 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/dma-mapping.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/rcar-gen2.h>
@@ -82,49 +81,35 @@ static void __init koelsch_add_du_device(void)
        platform_device_register_full(&info);
 }
-static void __init koelsch_add_standard_devices(void)
+/*
-{
+ * This is a really crude hack to provide clkdev support to platform
-        /*
+ * devices until they get moved to DT.
-         * This is a really crude hack to provide clkdev support to the CMT and
+ */
-         * DU devices until they get moved to DT.
+static const struct clk_name clk_names[] __initconst = {
-         */
+        { "cmt0", "fck", "sh-cmt-48-gen2.0" },
-        static const struct clk_name {
+        { "du0", "du.0", "rcar-du-r8a7791" },
-                const char *clk;
+        { "du1", "du.1", "rcar-du-r8a7791" },
-                const char *con_id;
+        { "lvds0", "lvds.0", "rcar-du-r8a7791" },
-                const char *dev_id;
+};
-        } clk_names[] = {
-                { "cmt0", NULL, "sh_cmt.0" },
-                { "scifa0", NULL, "sh-sci.0" },
-                { "scifa1", NULL, "sh-sci.1" },
-                { "scifb0", NULL, "sh-sci.2" },
-                { "scifb1", NULL, "sh-sci.3" },
-                { "scifb2", NULL, "sh-sci.4" },
-                { "scifa2", NULL, "sh-sci.5" },
-                { "scif0", NULL, "sh-sci.6" },
-                { "scif1", NULL, "sh-sci.7" },
-                { "scif2", NULL, "sh-sci.8" },
-                { "scif3", NULL, "sh-sci.9" },
-                { "scif4", NULL, "sh-sci.10" },
-                { "scif5", NULL, "sh-sci.11" },
-                { "scifa3", NULL, "sh-sci.12" },
-                { "scifa4", NULL, "sh-sci.13" },
-                { "scifa5", NULL, "sh-sci.14" },
-                { "du0", "du.0", "rcar-du-r8a7791" },
-                { "du1", "du.1", "rcar-du-r8a7791" },
-                { "lvds0", "lvds.0", "rcar-du-r8a7791" },
-        };
-        struct clk *clk;
-        unsigned int i;
-        for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
+/*
-                clk = clk_get(NULL, clk_names[i].clk);
+ * This is a really crude hack to work around core platform clock issues
-                if (!IS_ERR(clk)) {
+ */
-                        clk_register_clkdev(clk, clk_names[i].con_id,
+static const struct clk_name clk_enables[] __initconst = {
-                                            clk_names[i].dev_id);
+        { "ether", NULL, "ee700000.ethernet" },
-                        clk_put(clk);
+        { "i2c2", NULL, "e6530000.i2c" },
-                }
+        { "msiof0", NULL, "e6e20000.spi" },
-        }
+        { "qspi_mod", NULL, "e6b10000.spi" },
+        { "sdhi0", NULL, "ee100000.sd" },
+        { "sdhi1", NULL, "ee140000.sd" },
+        { "sdhi2", NULL, "ee160000.sd" },
+        { "thermal", NULL, "e61f0000.thermal" },
+};
+static void __init koelsch_add_standard_devices(void)
+{
+        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
+        shmobile_clk_workaround(clk_enables, ARRAY_SIZE(clk_enables), true);
        r8a7791_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -139,7 +124,7 @@ static const char * const koelsch_boards_compat_dt[] __initconst = {
 DT_MACHINE_START(KOELSCH_DT, "koelsch")
        .smp            = smp_ops(r8a7791_smp_ops),
-        .init_early     = r8a7791_init_early,
+        .init_early     = shmobile_init_delay,
        .init_time      = rcar_gen2_timer_init,
        .init_machine   = koelsch_add_standard_devices,
        .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c
index 5a034ff405d0..c6c68892caa3 100644
--- a/arch/arm/mach-shmobile/board-koelsch.c
+++ b/arch/arm/mach-shmobile/board-koelsch.c
@@ -216,7 +216,7 @@ static const struct spi_board_info spi_info[] __initconst = {
        {
                .modalias       = "m25p80",
                .platform_data  = &spi_flash_data,
-                .mode           = SPI_MODE_0,
+                .mode           = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
                .max_speed_hz   = 30000000,
                .bus_num        = 0,
                .chip_select    = 0,
@@ -522,7 +522,7 @@ static const char * const koelsch_boards_compat_dt[] __initconst = {
 DT_MACHINE_START(KOELSCH_DT, "koelsch")
        .smp            = smp_ops(r8a7791_smp_ops),
-        .init_early     = r8a7791_init_early,
+        .init_early     = shmobile_init_delay,
        .init_time      = rcar_gen2_timer_init,
        .init_machine   = koelsch_init,
        .init_late      = shmobile_init_late,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 598e32488410..a735a1d80c28 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -36,8 +36,8 @@ static void __init kzm_init(void)
        sh73a0_add_standard_devices_dt();
 #ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+        /* Shared attribute override enable, 64K*8way */
-        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+        l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 #endif
 }
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 03dc3ac84502..f94ec8ca42c1 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -876,8 +876,8 @@ static void __init kzm_init(void)
        gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
 #ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 64K*8way */
+        /* Shared attribute override enable, 64K*8way */
-        l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
+        l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 #endif
        i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices));
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
index 440aac36d693..749832e3f33c 100644
--- a/arch/arm/mach-shmobile/board-lager-reference.c
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -18,12 +18,11 @@
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
-#include <linux/clk.h>
-#include <linux/clkdev.h>
 #include <linux/dma-mapping.h>
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <linux/platform_data/rcar-du.h>
+#include <mach/clock.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/rcar-gen2.h>
@@ -86,46 +85,36 @@ static void __init lager_add_du_device(void)
        platform_device_register_full(&info);
 }
-static void __init lager_add_standard_devices(void)
+/*
-{
+ * This is a really crude hack to provide clkdev support to platform
-        /*
+ * devices until they get moved to DT.
-         * This is a really crude hack to provide clkdev support to platform
+ */
-         * devices until they get moved to DT.
+static const struct clk_name clk_names[] __initconst = {
-         */
+        { "cmt0", "fck", "sh-cmt-48-gen2.0" },
-        static const struct clk_name {
+        { "du0", "du.0", "rcar-du-r8a7790" },
-                const char *clk;
+        { "du1", "du.1", "rcar-du-r8a7790" },
-                const char *con_id;
+        { "du2", "du.2", "rcar-du-r8a7790" },
-                const char *dev_id;
+        { "lvds0", "lvds.0", "rcar-du-r8a7790" },
-        } clk_names[] = {
+        { "lvds1", "lvds.1", "rcar-du-r8a7790" },
-                { "cmt0", NULL, "sh_cmt.0" },
+};
-                { "scifa0", NULL, "sh-sci.0" },
-                { "scifa1", NULL, "sh-sci.1" },
-                { "scifb0", NULL, "sh-sci.2" },
-                { "scifb1", NULL, "sh-sci.3" },
-                { "scifb2", NULL, "sh-sci.4" },
-                { "scifa2", NULL, "sh-sci.5" },
-                { "scif0", NULL, "sh-sci.6" },
-                { "scif1", NULL, "sh-sci.7" },
-                { "hscif0", NULL, "sh-sci.8" },
-                { "hscif1", NULL, "sh-sci.9" },
-                { "du0", "du.0", "rcar-du-r8a7790" },
-                { "du1", "du.1", "rcar-du-r8a7790" },
-                { "du2", "du.2", "rcar-du-r8a7790" },
-                { "lvds0", "lvds.0", "rcar-du-r8a7790" },
-                { "lvds1", "lvds.1", "rcar-du-r8a7790" },
-        };
-        struct clk *clk;
-        unsigned int i;
-        for (i = 0; i < ARRAY_SIZE(clk_names); ++i) {
+/*
-                clk = clk_get(NULL, clk_names[i].clk);
+ * This is a really crude hack to work around core platform clock issues
-                if (!IS_ERR(clk)) {
+ */
-                        clk_register_clkdev(clk, clk_names[i].con_id,
+static const struct clk_name clk_enables[] __initconst = {
-                                            clk_names[i].dev_id);
+        { "ether", NULL, "ee700000.ethernet" },
-                        clk_put(clk);
+        { "msiof1", NULL, "e6e10000.spi" },
-                }
+        { "mmcif1", NULL, "ee220000.mmc" },
-        }
+        { "qspi_mod", NULL, "e6b10000.spi" },
+        { "sdhi0", NULL, "ee100000.sd" },
+        { "sdhi2", NULL, "ee140000.sd" },
+        { "thermal", NULL, "e61f0000.thermal" },
+};
+static void __init lager_add_standard_devices(void)
+{
+        shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false);
+        shmobile_clk_workaround(clk_enables, ARRAY_SIZE(clk_enables), true);
        r8a7790_add_dt_devices();
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 18c7e0311aa6..f8b1e05463cc 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -325,12 +325,12 @@ static const struct rspi_plat_data qspi_pdata __initconst = {
 static const struct spi_board_info spi_info[] __initconst = {
        {
-                .modalias               = "m25p80",
+                .modalias       = "m25p80",
-                .platform_data          = &spi_flash_data,
+                .platform_data  = &spi_flash_data,
-                .mode                   = SPI_MODE_0,
+                .mode           = SPI_MODE_0 | SPI_TX_QUAD | SPI_RX_QUAD,
-                .max_speed_hz           = 30000000,
+                .max_speed_hz   = 30000000,
-                .bus_num                = 0,
+                .bus_num        = 0,
-                .chip_select            = 0,
+                .chip_select    = 0,
        },
 };
@@ -567,20 +567,27 @@ static struct resource rsnd_resources[] __initdata = {
 };
 static struct rsnd_ssi_platform_info rsnd_ssi[] = {
-        RSND_SSI_SET(0, 0, gic_spi(370), RSND_SSI_PLAY),
+        RSND_SSI(0, gic_spi(370), 0),
-        RSND_SSI_SET(0, 0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
+        RSND_SSI(0, gic_spi(371), RSND_SSI_CLK_PIN_SHARE),
 };
-static struct rsnd_scu_platform_info rsnd_scu[2] = {
+static struct rsnd_src_platform_info rsnd_src[2] = {
        /* no member at this point */
 };
+static struct rsnd_dai_platform_info rsnd_dai = {
+        .playback = { .ssi = &rsnd_ssi[0], },
+        .capture  = { .ssi = &rsnd_ssi[1], },
+};
 static struct rcar_snd_info rsnd_info = {
        .flags          = RSND_GEN2,
        .ssi_info       = rsnd_ssi,
        .ssi_info_nr    = ARRAY_SIZE(rsnd_ssi),
-        .scu_info       = rsnd_scu,
+        .src_info       = rsnd_src,
-        .scu_info_nr    = ARRAY_SIZE(rsnd_scu),
+        .src_info_nr    = ARRAY_SIZE(rsnd_src),
+        .dai_info       = &rsnd_dai,
+        .dai_info_nr    = 1,
 };
 static struct asoc_simple_card_info rsnd_card_info = {
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
deleted file mode 100644
index 5ac13ba71d54..000000000000
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Emma Mobile EV2 clock framework support
- *
- * Copyright (C) 2012  Magnus Damm
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/io.h>
-#include <linux/sh_clk.h>
-#include <linux/clkdev.h>
-#include <mach/common.h>
-#define EMEV2_SMU_BASE 0xe0110000
-/* EMEV2 SMU registers */
-#define USIAU0_RSTCTRL 0x094
-#define USIBU1_RSTCTRL 0x0ac
-#define USIBU2_RSTCTRL 0x0b0
-#define USIBU3_RSTCTRL 0x0b4
-#define STI_RSTCTRL 0x124
-#define USIAU0GCLKCTRL 0x4a0
-#define USIBU1GCLKCTRL 0x4b8
-#define USIBU2GCLKCTRL 0x4bc
-#define USIBU3GCLKCTRL 0x04c0
-#define STIGCLKCTRL 0x528
-#define USIAU0SCLKDIV 0x61c
-#define USIB2SCLKDIV 0x65c
-#define USIB3SCLKDIV 0x660
-#define STI_CLKSEL 0x688
-/* not pretty, but hey */
-static void __iomem *smu_base;
-static void emev2_smu_write(unsigned long value, int offs)
-{
-        BUG_ON(!smu_base || (offs >= PAGE_SIZE));
-        iowrite32(value, smu_base + offs);
-}
-static struct clk_mapping smu_mapping = {
-        .phys   = EMEV2_SMU_BASE,
-        .len    = PAGE_SIZE,
-};
-/* Fixed 32 KHz root clock from C32K pin */
-static struct clk c32k_clk = {
-        .rate           = 32768,
-        .mapping        = &smu_mapping,
-};
-/* PLL3 multiplies C32K with 7000 */
-static unsigned long pll3_recalc(struct clk *clk)
-{
-        return clk->parent->rate * 7000;
-}
-static struct sh_clk_ops pll3_clk_ops = {
-        .recalc         = pll3_recalc,
-};
-static struct clk pll3_clk = {
-        .ops            = &pll3_clk_ops,
-        .parent         = &c32k_clk,
-};
-static struct clk *main_clks[] = {
-        &c32k_clk,
-        &pll3_clk,
-};
-enum { SCLKDIV_USIAU0, SCLKDIV_USIBU2, SCLKDIV_USIBU1, SCLKDIV_USIBU3,
-        SCLKDIV_NR };
-#define SCLKDIV(_reg, _shift)                   \
-{                                                               \
-        .parent         = &pll3_clk,                            \
-        .enable_reg     = IOMEM(EMEV2_SMU_BASE + (_reg)),       \
-        .enable_bit     = _shift,                               \
-}
-static struct clk sclkdiv_clks[SCLKDIV_NR] = {
-        [SCLKDIV_USIAU0] = SCLKDIV(USIAU0SCLKDIV, 0),
-        [SCLKDIV_USIBU2] = SCLKDIV(USIB2SCLKDIV, 16),
-        [SCLKDIV_USIBU1] = SCLKDIV(USIB2SCLKDIV, 0),
-        [SCLKDIV_USIBU3] = SCLKDIV(USIB3SCLKDIV, 0),
-};
-enum { GCLK_USIAU0_SCLK, GCLK_USIBU1_SCLK, GCLK_USIBU2_SCLK, GCLK_USIBU3_SCLK,
-        GCLK_STI_SCLK,
-        GCLK_NR };
-#define GCLK_SCLK(_parent, _reg) \
-{                                                               \
-        .parent         = _parent,                              \
-        .enable_reg     = IOMEM(EMEV2_SMU_BASE + (_reg)),       \
-        .enable_bit     = 1, /* SCLK_GCC */                     \
-}
-static struct clk gclk_clks[GCLK_NR] = {
-        [GCLK_USIAU0_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIAU0],
-                                       USIAU0GCLKCTRL),
-        [GCLK_USIBU1_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU1],
-                                       USIBU1GCLKCTRL),
-        [GCLK_USIBU2_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU2],
-                                       USIBU2GCLKCTRL),
-        [GCLK_USIBU3_SCLK] = GCLK_SCLK(&sclkdiv_clks[SCLKDIV_USIBU3],
-                                       USIBU3GCLKCTRL),
-        [GCLK_STI_SCLK] = GCLK_SCLK(&c32k_clk, STIGCLKCTRL),
-};
-static int emev2_gclk_enable(struct clk *clk)
-{
-        iowrite32(ioread32(clk->mapped_reg) | (1 << clk->enable_bit),
-                  clk->mapped_reg);
-        return 0;
-}
-static void emev2_gclk_disable(struct clk *clk)
-{
-        iowrite32(ioread32(clk->mapped_reg) & ~(1 << clk->enable_bit),
-                  clk->mapped_reg);
-}
-static struct sh_clk_ops emev2_gclk_clk_ops = {
-        .enable         = emev2_gclk_enable,
-        .disable        = emev2_gclk_disable,
-        .recalc         = followparent_recalc,
-};
-static int __init emev2_gclk_register(struct clk *clks, int nr)
-{
-        struct clk *clkp;
-        int ret = 0;
-        int k;
-        for (k = 0; !ret && (k < nr); k++) {
-                clkp = clks + k;
-                clkp->ops = &emev2_gclk_clk_ops;
-                ret |= clk_register(clkp);
-        }
-        return ret;
-}
-static unsigned long emev2_sclkdiv_recalc(struct clk *clk)
-{
-        unsigned int sclk_div;
-        sclk_div = (ioread32(clk->mapped_reg) >> clk->enable_bit) & 0xff;
-        return clk->parent->rate / (sclk_div + 1);
-}
-static struct sh_clk_ops emev2_sclkdiv_clk_ops = {
-        .recalc         = emev2_sclkdiv_recalc,
-};
-static int __init emev2_sclkdiv_register(struct clk *clks, int nr)
-{
-        struct clk *clkp;
-        int ret = 0;
-        int k;
-        for (k = 0; !ret && (k < nr); k++) {
-                clkp = clks + k;
-                clkp->ops = &emev2_sclkdiv_clk_ops;
-                ret |= clk_register(clkp);
-        }
-        return ret;
-}
-static struct clk_lookup lookups[] = {
-        CLKDEV_DEV_ID("serial8250-em.0", &gclk_clks[GCLK_USIAU0_SCLK]),
-        CLKDEV_DEV_ID("e1020000.uart", &gclk_clks[GCLK_USIAU0_SCLK]),
-        CLKDEV_DEV_ID("serial8250-em.1", &gclk_clks[GCLK_USIBU1_SCLK]),
-        CLKDEV_DEV_ID("e1030000.uart", &gclk_clks[GCLK_USIBU1_SCLK]),
-        CLKDEV_DEV_ID("serial8250-em.2", &gclk_clks[GCLK_USIBU2_SCLK]),
-        CLKDEV_DEV_ID("e1040000.uart", &gclk_clks[GCLK_USIBU2_SCLK]),
-        CLKDEV_DEV_ID("serial8250-em.3", &gclk_clks[GCLK_USIBU3_SCLK]),
-        CLKDEV_DEV_ID("e1050000.uart", &gclk_clks[GCLK_USIBU3_SCLK]),
-        CLKDEV_DEV_ID("em_sti.0", &gclk_clks[GCLK_STI_SCLK]),
-        CLKDEV_DEV_ID("e0180000.sti", &gclk_clks[GCLK_STI_SCLK]),
-};
-void __init emev2_clock_init(void)
-{
-        int k, ret = 0;
-        smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
-        BUG_ON(!smu_base);
-        /* setup STI timer to run on 32.768 kHz and deassert reset */
-        emev2_smu_write(0, STI_CLKSEL);
-        emev2_smu_write(1, STI_RSTCTRL);
-        /* deassert reset for UART0->UART3 */
-        emev2_smu_write(2, USIAU0_RSTCTRL);
-        emev2_smu_write(2, USIBU1_RSTCTRL);
-        emev2_smu_write(2, USIBU2_RSTCTRL);
-        emev2_smu_write(2, USIBU3_RSTCTRL);
-        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
-                ret = clk_register(main_clks[k]);
-        if (!ret)
-                ret = emev2_sclkdiv_register(sclkdiv_clks, SCLKDIV_NR);
-        if (!ret)
-                ret = emev2_gclk_register(gclk_clks, GCLK_NR);
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        if (!ret)
-                shmobile_clk_init();
-        else
-                panic("failed to setup emev2 clocks\n");
-}
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c
index bee0073c9b64..df187484de5d 100644
--- a/arch/arm/mach-shmobile/clock-r7s72100.c
+++ b/arch/arm/mach-shmobile/clock-r7s72100.c
@@ -194,17 +194,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
        CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
        CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
-        CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
-        CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
-        CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
-        CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
-        CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
-        CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
-        CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
-        CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
-        CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
        CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
-        CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
        /* ICK */
        CLKDEV_ICK_ID("sci_fck", "sh-sci.0", &mstp_clks[MSTP47]),
@@ -215,6 +205,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("sci_fck", "sh-sci.5", &mstp_clks[MSTP42]),
        CLKDEV_ICK_ID("sci_fck", "sh-sci.6", &mstp_clks[MSTP41]),
        CLKDEV_ICK_ID("sci_fck", "sh-sci.7", &mstp_clks[MSTP40]),
+        CLKDEV_ICK_ID("fck", "sh-mtu2", &mstp_clks[MSTP33]),
 };
 void __init r7s72100_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 7348d58f500e..b5bc22c6a858 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -597,7 +597,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
        CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
        CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
+        CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
        CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
        CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
        CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index dd989f93498f..50931e3c97c7 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -548,15 +548,9 @@ static struct clk_lookup lookups[] = {
        /* MSTP32 clocks */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0",    &mstp_clks[MSTP100]),
-        CLKDEV_DEV_ID("sh_tmu.3",               &mstp_clks[MSTP111]),
-        CLKDEV_DEV_ID("sh_tmu.4",               &mstp_clks[MSTP111]),
-        CLKDEV_DEV_ID("sh_tmu.5",               &mstp_clks[MSTP111]),
        CLKDEV_DEV_ID("i2c-sh_mobile.0",        &mstp_clks[MSTP116]),
        CLKDEV_DEV_ID("fff20000.i2c",           &mstp_clks[MSTP116]),
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1",    &mstp_clks[MSTP117]),
-        CLKDEV_DEV_ID("sh_tmu.0",               &mstp_clks[MSTP125]),
-        CLKDEV_DEV_ID("sh_tmu.1",               &mstp_clks[MSTP125]),
-        CLKDEV_DEV_ID("sh_tmu.2",               &mstp_clks[MSTP125]),
        CLKDEV_DEV_ID("sh_mobile_ceu.0",        &mstp_clks[MSTP127]),
        CLKDEV_DEV_ID("sh_mobile_ceu.1",        &mstp_clks[MSTP128]),
@@ -583,7 +577,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.6",               &mstp_clks[MSTP230]),
        CLKDEV_DEV_ID("e6cc0000.sci",           &mstp_clks[MSTP230]),
-        CLKDEV_DEV_ID("sh_cmt.10",              &mstp_clks[MSTP329]),
        CLKDEV_DEV_ID("sh_fsi2",                &mstp_clks[MSTP328]),
        CLKDEV_DEV_ID("fe1f0000.sound",         &mstp_clks[MSTP328]),
        CLKDEV_DEV_ID("i2c-sh_mobile.1",        &mstp_clks[MSTP323]),
@@ -596,7 +589,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_mmcif",               &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("e6bd0000.mmc",           &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("r8a7740-gether",         &mstp_clks[MSTP309]),
-        CLKDEV_DEV_ID("e9a00000.sh-eth",        &mstp_clks[MSTP309]),
+        CLKDEV_DEV_ID("e9a00000.ethernet",      &mstp_clks[MSTP309]),
        CLKDEV_DEV_ID("renesas-tpu-pwm",        &mstp_clks[MSTP304]),
        CLKDEV_DEV_ID("e6600000.pwm",           &mstp_clks[MSTP304]),
@@ -604,6 +597,9 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("e6870000.sd",            &mstp_clks[MSTP415]),
        /* ICK */
+        CLKDEV_ICK_ID("fck",    "sh-tmu.1",             &mstp_clks[MSTP111]),
+        CLKDEV_ICK_ID("fck",    "sh-tmu.0",             &mstp_clks[MSTP125]),
+        CLKDEV_ICK_ID("fck",    "sh-cmt-48.1",          &mstp_clks[MSTP329]),
        CLKDEV_ICK_ID("host",   "renesas_usbhs",        &mstp_clks[MSTP416]),
        CLKDEV_ICK_ID("func",   "renesas_usbhs",        &mstp_clks[MSTP407]),
        CLKDEV_ICK_ID("phy",    "renesas_usbhs",        &mstp_clks[MSTP406]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 9989b1b06ffd..13f8f3ab8840 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -175,10 +175,6 @@ static struct clk mstp_clks[MSTP_NR] = {
 static struct clk_lookup lookups[] = {
        /* main */
-        CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
-        CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
-        CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
-        CLKDEV_CON_ID("audio_clk_internal",     &s1_clk),
        CLKDEV_CON_ID("shyway_clk",     &s_clk),
        CLKDEV_CON_ID("peripheral_clk", &p_clk),
@@ -211,8 +207,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
        CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
-        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
-        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
        CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
        CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
        CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
@@ -234,15 +228,17 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
        CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
        CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
-        CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
+        CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP531]),
-        CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
+        CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP530]),
-        CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
+        CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP529]),
-        CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
+        CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP528]),
-        CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
+        CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP527]),
-        CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
+        CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP526]),
-        CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
+        CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP525]),
-        CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
+        CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
-        CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
+        CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
+        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
+        CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
 };
 void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 8e403ae0c7b2..a13298bd37a8 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -173,9 +173,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
        CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
        CLKDEV_DEV_ID("ohci-platform.0", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
-        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
+        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), /* TMU0 */
-        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP016]), /* TMU01 */
-        CLKDEV_DEV_ID("sh_tmu.2", &mstp_clks[MSTP016]), /* TMU02 */
        CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
        CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
        CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 3f93503f5b96..296a057109e4 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -249,10 +249,10 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP1007] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 7, MSTPSR10, 0), /* SSI8 */
        [MSTP1006] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 6, MSTPSR10, 0), /* SSI9 */
        [MSTP1005] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR10, 5, MSTPSR10, 0), /* SSI ALL */
-        [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
+        [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
-        [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
+        [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
-        [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
+        [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
-        [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
+        [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
        [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
        [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
@@ -294,10 +294,6 @@ static struct clk mstp_clks[MSTP_NR] = {
 static struct clk_lookup lookups[] = {
        /* main clocks */
-        CLKDEV_CON_ID("audio_clk_a",    &audio_clk_a),
-        CLKDEV_CON_ID("audio_clk_b",    &audio_clk_b),
-        CLKDEV_CON_ID("audio_clk_c",    &audio_clk_c),
-        CLKDEV_CON_ID("audio_clk_internal",     &m2_clk),
        CLKDEV_CON_ID("extal",          &extal_clk),
        CLKDEV_CON_ID("extal_div2",     &extal_div2_clk),
        CLKDEV_CON_ID("main",           &main_clk),
@@ -361,7 +357,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
        CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
-        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
        CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP704]),
        CLKDEV_DEV_ID("pci-rcar-gen2.0", &mstp_clks[MSTP703]),
@@ -371,6 +366,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sata-r8a7790.1", &mstp_clks[MSTP814]),
        /* ICK */
+        CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
        CLKDEV_ICK_ID("usbhs", "usb_phy_rcar_gen2", &mstp_clks[MSTP704]),
        CLKDEV_ICK_ID("lvds.0", "rcar-du-r8a7790", &mstp_clks[MSTP726]),
        CLKDEV_ICK_ID("lvds.1", "rcar-du-r8a7790", &mstp_clks[MSTP725]),
@@ -381,16 +377,16 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
        CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
        CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
-        CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP1031]),
+        CLKDEV_ICK_ID("src.0", "rcar_sound", &mstp_clks[MSTP1031]),
-        CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP1030]),
+        CLKDEV_ICK_ID("src.1", "rcar_sound", &mstp_clks[MSTP1030]),
-        CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP1029]),
+        CLKDEV_ICK_ID("src.2", "rcar_sound", &mstp_clks[MSTP1029]),
-        CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP1028]),
+        CLKDEV_ICK_ID("src.3", "rcar_sound", &mstp_clks[MSTP1028]),
-        CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP1027]),
+        CLKDEV_ICK_ID("src.4", "rcar_sound", &mstp_clks[MSTP1027]),
-        CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP1026]),
+        CLKDEV_ICK_ID("src.5", "rcar_sound", &mstp_clks[MSTP1026]),
-        CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP1025]),
+        CLKDEV_ICK_ID("src.6", "rcar_sound", &mstp_clks[MSTP1025]),
-        CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP1024]),
+        CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP1024]),
-        CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP1023]),
+        CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP1023]),
-        CLKDEV_ICK_ID("scu.9", "rcar_sound", &mstp_clks[MSTP1022]),
+        CLKDEV_ICK_ID("src.9", "rcar_sound", &mstp_clks[MSTP1022]),
        CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
        CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
        CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c
index 701383fe3267..e2fdfcc14436 100644
--- a/arch/arm/mach-shmobile/clock-r8a7791.c
+++ b/arch/arm/mach-shmobile/clock-r8a7791.c
@@ -25,6 +25,7 @@
 #include <linux/clkdev.h>
 #include <mach/clock.h>
 #include <mach/common.h>
+#include <mach/rcar-gen2.h>
 /*
 *   MD         EXTAL           PLL0    PLL1    PLL3
@@ -43,8 +44,6 @@
 *      see "p1 / 2" on R8A7791_CLOCK_ROOT() below
 */
-#define MD(nr)  (1 << nr)
 #define CPG_BASE 0xe6150000
 #define CPG_LEN 0x1000
@@ -68,7 +67,6 @@
 #define MSTPSR9         IOMEM(0xe61509a4)
 #define MSTPSR11        IOMEM(0xe61509ac)
-#define MODEMR          0xE6160060
 #define SDCKCR          0xE6150074
 #define SD1CKCR         0xE6150078
 #define SD2CKCR         0xE615026c
@@ -190,12 +188,12 @@ static struct clk mstp_clks[MSTP_NR] = {
        [MSTP1108] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 8, MSTPSR11, 0), /* SCIFA5 */
        [MSTP1107] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 7, MSTPSR11, 0), /* SCIFA4 */
        [MSTP1106] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR11, 6, MSTPSR11, 0), /* SCIFA3 */
-        [MSTP931] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
+        [MSTP931] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 31, MSTPSR9, 0), /* I2C0 */
-        [MSTP930] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
+        [MSTP930] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 30, MSTPSR9, 0), /* I2C1 */
-        [MSTP929] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
+        [MSTP929] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 29, MSTPSR9, 0), /* I2C2 */
-        [MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
+        [MSTP928] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
-        [MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
+        [MSTP927] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
-        [MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
+        [MSTP925] = SH_CLK_MSTP32_STS(&hp_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
        [MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
        [MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
        [MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
@@ -266,7 +264,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
        CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
-        CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
+        CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.0", &mstp_clks[MSTP124]),
        CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
        CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
        CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
@@ -295,14 +293,9 @@ static struct clk_lookup lookups[] = {
 void __init r8a7791_clock_init(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
+        u32 mode = rcar_gen2_read_mode_pins();
-        u32 mode;
        int k, ret = 0;
-        BUG_ON(!modemr);
-        mode = ioread32(modemr);
-        iounmap(modemr);
        switch (mode & (MD(14) | MD(13))) {
        case 0:
                R8A7791_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 28489978b09c..d16d9ca7f79e 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -515,8 +515,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
-        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
-        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
        CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
@@ -565,10 +563,7 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
        CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
-        CLKDEV_DEV_ID("sh_cmt.4", &mstp_clks[MSTP405]), /* CMT4 */
-        CLKDEV_DEV_ID("sh_cmt.3", &mstp_clks[MSTP404]), /* CMT3 */
        CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
-        CLKDEV_DEV_ID("sh_cmt.2", &mstp_clks[MSTP400]), /* CMT2 */
        /* ICK */
        CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
@@ -580,7 +575,11 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
        CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
        CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
+        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
        CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
+        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.4", &mstp_clks[MSTP405]), /* CMT4 */
+        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.3", &mstp_clks[MSTP404]), /* CMT3 */
+        CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.2", &mstp_clks[MSTP400]), /* CMT2 */
        CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
        CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
        CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 23edf8360c27..0d9cd1fe0212 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -633,8 +633,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-mobile-csi2.1", &mstp_clks[MSTP128]), /* CSI2-RX1 */
        CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU0 */
        CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2-RX0 */
-        CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
-        CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
        CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
        CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* I2C0 */
        CLKDEV_DEV_ID("e6820000.i2c", &mstp_clks[MSTP116]), /* I2C0 */
@@ -650,7 +648,6 @@ static struct clk_lookup lookups[] = {
        CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
        CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
        CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
-        CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
        CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI */
        CLKDEV_DEV_ID("ec230000.sound", &mstp_clks[MSTP328]), /* FSI */
        CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
@@ -683,6 +680,8 @@ static struct clk_lookup lookups[] = {
        CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
        CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
+        CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */
+        CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
 };
 void __init sh73a0_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index ad7df629d995..e7232a0373b9 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -21,6 +21,32 @@
 */
 #include <linux/kernel.h>
 #include <linux/init.h>
+#ifdef CONFIG_COMMON_CLK
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <mach/clock.h>
+void __init shmobile_clk_workaround(const struct clk_name *clks,
+                                    int nr_clks, bool enable)
+{
+        const struct clk_name *clkn;
+        struct clk *clk;
+        unsigned int i;
+        for (i = 0; i < nr_clks; ++i) {
+                clkn = clks + i;
+                clk = clk_get(NULL, clkn->clk);
+                if (!IS_ERR(clk)) {
+                        clk_register_clkdev(clk, clkn->con_id, clkn->dev_id);
+                        if (enable)
+                                clk_prepare_enable(clk);
+                        clk_put(clk);
+                }
+        }
+}
+#else /* CONFIG_COMMON_CLK */
 #include <linux/sh_clk.h>
 #include <linux/export.h>
 #include <mach/clock.h>
@@ -58,3 +84,5 @@ void __clk_put(struct clk *clk)
 {
 }
 EXPORT_SYMBOL(__clk_put);
+#endif /* CONFIG_COMMON_CLK */
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/include/mach/clock.h
index 03e56074928c..31b6417463e6 100644
--- a/arch/arm/mach-shmobile/include/mach/clock.h
+++ b/arch/arm/mach-shmobile/include/mach/clock.h
@@ -1,6 +1,22 @@
 #ifndef CLOCK_H
 #define CLOCK_H
+#ifdef CONFIG_COMMON_CLK
+/* temporary clock configuration helper for platform devices */
+struct clk_name {
+        const char *clk;
+        const char *con_id;
+        const char *dev_id;
+};
+void shmobile_clk_workaround(const struct clk_name *clks, int nr_clks,
+                             bool enable);
+#else /* CONFIG_COMMON_CLK */
+/* legacy clock implementation */
+struct clk;
 unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk);
 extern struct sh_clk_ops shmobile_fixed_ratio_clk_ops;
@@ -36,4 +52,5 @@ do {			\
        (p)->div = d;   \
 } while (0)
+#endif /* CONFIG_COMMON_CLK */
 #endif
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index cb8e32deb2a3..f7a360edcc35 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -4,6 +4,7 @@
 extern void shmobile_earlytimer_init(void);
 extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                         unsigned int mult, unsigned int div);
+extern void shmobile_init_delay(void);
 struct twd_local_timer;
 extern void shmobile_setup_console(void);
 extern void shmobile_boot_vector(void);
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
deleted file mode 100644
index fcb142a14e07..000000000000
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_EMEV2_H__
-#define __ASM_EMEV2_H__
-extern void emev2_map_io(void);
-extern void emev2_init_delay(void);
-extern void emev2_clock_init(void);
-extern struct smp_operations emev2_smp_ops;
-#endif /* __ASM_EMEV2_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index d07932f872b6..5e3c9ec06303 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -47,7 +47,6 @@ enum {
 };
 extern void r8a7740_meram_workaround(void);
-extern void r8a7740_init_delay(void);
 extern void r8a7740_init_irq_of(void);
 extern void r8a7740_map_io(void);
 extern void r8a7740_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7791.h b/arch/arm/mach-shmobile/include/mach/r8a7791.h
index 200fa699f730..664274cc4b64 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7791.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7791.h
@@ -5,7 +5,6 @@ void r8a7791_add_standard_devices(void);
 void r8a7791_add_dt_devices(void);
 void r8a7791_clock_init(void);
 void r8a7791_pinmux_init(void);
-void r8a7791_init_early(void);
 extern struct smp_operations r8a7791_smp_ops;
 #endif /* __ASM_R8A7791_H__ */
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c
index 1fc05d9453d0..f710235aff2f 100644
--- a/arch/arm/mach-shmobile/pm-rmobile.c
+++ b/arch/arm/mach-shmobile/pm-rmobile.c
@@ -99,39 +99,7 @@ static int rmobile_pd_power_up(struct generic_pm_domain *genpd)
 static bool rmobile_pd_active_wakeup(struct device *dev)
 {
-        bool (*active_wakeup)(struct device *dev);
+        return true;
-        active_wakeup = dev_gpd_data(dev)->ops.active_wakeup;
-        return active_wakeup ? active_wakeup(dev) : true;
-}
-static int rmobile_pd_stop_dev(struct device *dev)
-{
-        int (*stop)(struct device *dev);
-        stop = dev_gpd_data(dev)->ops.stop;
-        if (stop) {
-                int ret = stop(dev);
-                if (ret)
-                        return ret;
-        }
-        return pm_clk_suspend(dev);
-}
-static int rmobile_pd_start_dev(struct device *dev)
-{
-        int (*start)(struct device *dev);
-        int ret;
-        ret = pm_clk_resume(dev);
-        if (ret)
-                return ret;
-        start = dev_gpd_data(dev)->ops.start;
-        if (start)
-                ret = start(dev);
-        return ret;
 }
 static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
@@ -140,8 +108,8 @@ static void rmobile_init_pm_domain(struct rmobile_pm_domain *rmobile_pd)
        struct dev_power_governor *gov = rmobile_pd->gov;
        pm_genpd_init(genpd, gov ? : &simple_qos_governor, false);
-        genpd->dev_ops.stop             = rmobile_pd_stop_dev;
+        genpd->dev_ops.stop             = pm_clk_suspend;
-        genpd->dev_ops.start            = rmobile_pd_start_dev;
+        genpd->dev_ops.start            = pm_clk_resume;
        genpd->dev_ops.active_wakeup    = rmobile_pd_active_wakeup;
        genpd->dev_irq_safe             = true;
        genpd->power_off                = rmobile_pd_power_down;
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index c71d667007b8..d953ff6e78a2 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -21,7 +21,6 @@
 #include <linux/init.h>
 #include <linux/of_platform.h>
 #include <mach/common.h>
-#include <mach/emev2.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -38,23 +37,19 @@ static struct map_desc emev2_io_desc[] __initdata = {
 #endif
 };
-void __init emev2_map_io(void)
+static void __init emev2_map_io(void)
 {
        iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc));
 }
-void __init emev2_init_delay(void)
+static void __init emev2_init_delay(void)
 {
        shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
 }
 static void __init emev2_add_standard_devices_dt(void)
 {
-#ifdef CONFIG_COMMON_CLK
        of_clk_init(NULL);
-#else
-        emev2_clock_init();
-#endif
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
@@ -63,6 +58,8 @@ static const char *emev2_boards_compat_dt[] __initconst = {
        NULL,
 };
+extern struct smp_operations emev2_smp_ops;
 DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
        .smp            = smp_ops(emev2_smp_ops),
        .map_io         = emev2_map_io,
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c
index 9c0b3a9d5f7a..412e179429cd 100644
--- a/arch/arm/mach-shmobile/setup-r7s72100.c
+++ b/arch/arm/mach-shmobile/setup-r7s72100.c
@@ -21,77 +21,26 @@
 #include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/of_platform.h>
-#include <linux/serial_sci.h>
 #include <linux/sh_timer.h>
 #include <mach/common.h>
 #include <mach/irqs.h>
 #include <mach/r7s72100.h>
 #include <asm/mach/arch.h>
-#define R7S72100_SCIF(index, baseaddr, irq)                             \
+static struct resource mtu2_resources[] __initdata = {
-static const struct plat_sci_port scif##index##_platform_data = {       \
+        DEFINE_RES_MEM(0xfcff0000, 0x400),
-        .type           = PORT_SCIF,                                    \
+        DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"),
-        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,               \
-        .flags          = UPF_BOOT_AUTOCONF | UPF_IOREMAP,              \
-        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE | \
-                          SCSCR_REIE,                                   \
-};                                                                      \
-                                                                        \
-static struct resource scif##index##_resources[] = {                    \
-        DEFINE_RES_MEM(baseaddr, 0x100),                                \
-        DEFINE_RES_IRQ(irq + 1),                                        \
-        DEFINE_RES_IRQ(irq + 2),                                        \
-        DEFINE_RES_IRQ(irq + 3),                                        \
-        DEFINE_RES_IRQ(irq),                                            \
-}                                                                       \
-R7S72100_SCIF(0, 0xe8007000, gic_iid(221));
-R7S72100_SCIF(1, 0xe8007800, gic_iid(225));
-R7S72100_SCIF(2, 0xe8008000, gic_iid(229));
-R7S72100_SCIF(3, 0xe8008800, gic_iid(233));
-R7S72100_SCIF(4, 0xe8009000, gic_iid(237));
-R7S72100_SCIF(5, 0xe8009800, gic_iid(241));
-R7S72100_SCIF(6, 0xe800a000, gic_iid(245));
-R7S72100_SCIF(7, 0xe800a800, gic_iid(249));
-#define r7s72100_register_scif(index)                                          \
-        platform_device_register_resndata(&platform_bus, "sh-sci", index,      \
-                                          scif##index##_resources,             \
-                                          ARRAY_SIZE(scif##index##_resources), \
-                                          &scif##index##_platform_data,        \
-                                          sizeof(scif##index##_platform_data))
-static struct sh_timer_config mtu2_0_platform_data __initdata = {
-        .name = "MTU2_0",
-        .timer_bit = 0,
-        .channel_offset = -0x80,
-        .clockevent_rating = 200,
-};
-static struct resource mtu2_0_resources[] __initdata = {
-        DEFINE_RES_MEM(0xfcff0300, 0x27),
-        DEFINE_RES_IRQ(gic_iid(139)), /* MTU2 TGI0A */
 };
-#define r7s72100_register_mtu2(idx)                                     \
+#define r7s72100_register_mtu2()                                        \
-        platform_device_register_resndata(&platform_bus, "sh_mtu2",     \
+        platform_device_register_resndata(&platform_bus, "sh-mtu2",     \
-                                          idx, mtu2_##idx##_resources,  \
+                                          -1, mtu2_resources,           \
-                                          ARRAY_SIZE(mtu2_##idx##_resources), \
+                                          ARRAY_SIZE(mtu2_resources),   \
-                                          &mtu2_##idx##_platform_data,  \
+                                          NULL, 0)
-                                          sizeof(struct sh_timer_config))
 void __init r7s72100_add_dt_devices(void)
 {
-        r7s72100_register_scif(0);
+        r7s72100_register_mtu2();
-        r7s72100_register_scif(1);
-        r7s72100_register_scif(2);
-        r7s72100_register_scif(3);
-        r7s72100_register_scif(4);
-        r7s72100_register_scif(5);
-        r7s72100_register_scif(6);
-        r7s72100_register_scif(7);
-        r7s72100_register_mtu2(0);
 }
 void __init r7s72100_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index cd36f8078325..9333770cfac2 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -169,20 +169,17 @@ static const struct resource thermal0_resources[] = {
                                        thermal0_resources,             \
                                        ARRAY_SIZE(thermal0_resources))
-static struct sh_timer_config cmt10_platform_data = {
+static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT10",
+        .channels_mask = 0xff,
-        .timer_bit = 0,
-        .clockevent_rating = 80,
 };
-static struct resource cmt10_resources[] = {
+static struct resource cmt1_resources[] = {
-        DEFINE_RES_MEM(0xe6130010, 0x0c),
+        DEFINE_RES_MEM(0xe6130000, 0x1004),
-        DEFINE_RES_MEM(0xe6130000, 0x04),
+        DEFINE_RES_IRQ(gic_spi(120)),
-        DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
 };
 #define r8a7790_register_cmt(idx)                                       \
-        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+        platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
                                          idx, cmt##idx##_resources,    \
                                          ARRAY_SIZE(cmt##idx##_resources), \
                                          &cmt##idx##_platform_data,    \
@@ -196,7 +193,7 @@ void __init r8a73a4_add_dt_devices(void)
        r8a73a4_register_scif(3);
        r8a73a4_register_scif(4);
        r8a73a4_register_scif(5);
-        r8a7790_register_cmt(10);
+        r8a7790_register_cmt(1);
 }
 /* DMA */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 8f3c68101d59..35dec233301e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -237,126 +237,45 @@ R8A7740_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(107));
 R8A7740_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(108));
 /* CMT */
-static struct sh_timer_config cmt10_platform_data = {
+static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT10",
+        .channels_mask = 0x3f,
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
 };
-static struct resource cmt10_resources[] = {
+static struct resource cmt1_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xe6138000, 0x170),
-                .name   = "CMT10",
+        DEFINE_RES_IRQ(gic_spi(58)),
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_spi(58),
-                .flags  = IORESOURCE_IRQ,
-        },
 };
-static struct platform_device cmt10_device = {
+static struct platform_device cmt1_device = {
-        .name           = "sh_cmt",
+        .name           = "sh-cmt-48",
-        .id             = 10,
+        .id             = 1,
        .dev = {
-                .platform_data  = &cmt10_platform_data,
+                .platform_data  = &cmt1_platform_data,
        },
-        .resource       = cmt10_resources,
+        .resource       = cmt1_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
 };
 /* TMU */
-static struct sh_timer_config tmu00_platform_data = {
+static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU00",
+        .channels_mask = 7,
-        .channel_offset = 0x4,
-        .timer_bit = 0,
-        .clockevent_rating = 200,
 };
-static struct resource tmu00_resources[] = {
+static struct resource tmu0_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xfff80000, 0x2c),
-                .name   = "TMU00",
+        DEFINE_RES_IRQ(gic_spi(198)),
-                .start  = 0xfff80008,
+        DEFINE_RES_IRQ(gic_spi(199)),
-                .end    = 0xfff80014 - 1,
+        DEFINE_RES_IRQ(gic_spi(200)),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_spi(198),
-                .flags  = IORESOURCE_IRQ,
-        },
 };
-static struct platform_device tmu00_device = {
+static struct platform_device tmu0_device = {
-        .name           = "sh_tmu",
+        .name           = "sh-tmu",
        .id             = 0,
        .dev = {
-                .platform_data  = &tmu00_platform_data,
+                .platform_data  = &tmu0_platform_data,
-        },
-        .resource       = tmu00_resources,
-        .num_resources  = ARRAY_SIZE(tmu00_resources),
-};
-static struct sh_timer_config tmu01_platform_data = {
-        .name = "TMU01",
-        .channel_offset = 0x10,
-        .timer_bit = 1,
-        .clocksource_rating = 200,
-};
-static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff80014,
-                .end    = 0xfff80020 - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_spi(199),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tmu01_device = {
-        .name           = "sh_tmu",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &tmu01_platform_data,
        },
-        .resource       = tmu01_resources,
+        .resource       = tmu0_resources,
-        .num_resources  = ARRAY_SIZE(tmu01_resources),
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
-};
-static struct sh_timer_config tmu02_platform_data = {
-        .name = "TMU02",
-        .channel_offset = 0x1C,
-        .timer_bit = 2,
-        .clocksource_rating = 200,
-};
-static struct resource tmu02_resources[] = {
-        [0] = {
-                .name   = "TMU02",
-                .start  = 0xfff80020,
-                .end    = 0xfff8002C - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_spi(200),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tmu02_device = {
-        .name           = "sh_tmu",
-        .id             = 2,
-        .dev = {
-                .platform_data  = &tmu02_platform_data,
-        },
-        .resource       = tmu02_resources,
-        .num_resources  = ARRAY_SIZE(tmu02_resources),
 };
 /* IPMMUI (an IPMMU module for ICB/LMB) */
@@ -400,7 +319,7 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
        &scif6_device,
        &scif7_device,
        &scif8_device,
-        &cmt10_device,
+        &cmt1_device,
 };
 static struct platform_device *r8a7740_early_devices[] __initdata = {
@@ -408,9 +327,7 @@ static struct platform_device *r8a7740_early_devices[] __initdata = {
        &irqpin1_device,
        &irqpin2_device,
        &irqpin3_device,
-        &tmu00_device,
+        &tmu0_device,
-        &tmu01_device,
-        &tmu02_device,
        &ipmmu_device,
 };
@@ -765,7 +682,7 @@ static struct platform_device *r8a7740_late_devices[] __initdata = {
 *      "Media RAM (MERAM)" on r8a7740 documentation
 */
 #define MEBUFCNTR       0xFE950098
-void r8a7740_meram_workaround(void)
+void __init r8a7740_meram_workaround(void)
 {
        void __iomem *reg;
@@ -869,17 +786,6 @@ void __init r8a7740_add_early_devices(void)
 #ifdef CONFIG_USE_OF
-void __init r8a7740_add_early_devices_dt(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-        early_platform_add_devices(r8a7740_early_devices,
-                                   ARRAY_SIZE(r8a7740_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
-}
 void __init r8a7740_add_standard_devices_dt(void)
 {
        platform_add_devices(r8a7740_devices_dt,
@@ -887,11 +793,6 @@ void __init r8a7740_add_standard_devices_dt(void)
        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 }
-void __init r8a7740_init_delay(void)
-{
-        shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
-};
 void __init r8a7740_init_irq_of(void)
 {
        void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
@@ -935,9 +836,10 @@ static const char *r8a7740_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
        .map_io         = r8a7740_map_io,
-        .init_early     = r8a7740_init_delay,
+        .init_early     = shmobile_init_delay,
        .init_irq       = r8a7740_init_irq_of,
        .init_machine   = r8a7740_generic_init,
+        .init_late      = shmobile_init_late,
        .dt_compat      = r8a7740_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 6d694526e4ca..d311ef903b39 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -71,33 +71,20 @@ R8A7778_SCIF(5, 0xffe45000, gic_iid(0x6b));
                                          sizeof(scif##index##_platform_data))
 /* TMU */
-static struct resource sh_tmu0_resources[] __initdata = {
+static struct sh_timer_config sh_tmu0_platform_data = {
-        DEFINE_RES_MEM(0xffd80008, 12),
+        .channels_mask = 7,
-        DEFINE_RES_IRQ(gic_iid(0x40)),
-};
-static struct sh_timer_config sh_tmu0_platform_data __initdata = {
-        .name                   = "TMU00",
-        .channel_offset         = 0x4,
-        .timer_bit              = 0,
-        .clockevent_rating      = 200,
 };
-static struct resource sh_tmu1_resources[] __initdata = {
+static struct resource sh_tmu0_resources[] = {
-        DEFINE_RES_MEM(0xffd80014, 12),
+        DEFINE_RES_MEM(0xffd80000, 0x30),
+        DEFINE_RES_IRQ(gic_iid(0x40)),
        DEFINE_RES_IRQ(gic_iid(0x41)),
-};
+        DEFINE_RES_IRQ(gic_iid(0x42)),
-static struct sh_timer_config sh_tmu1_platform_data __initdata = {
-        .name                   = "TMU01",
-        .channel_offset         = 0x10,
-        .timer_bit              = 1,
-        .clocksource_rating     = 200,
 };
 #define r8a7778_register_tmu(idx)                       \
        platform_device_register_resndata(              \
-                &platform_bus, "sh_tmu", idx,           \
+                &platform_bus, "sh-tmu", idx,           \
                sh_tmu##idx##_resources,                \
                ARRAY_SIZE(sh_tmu##idx##_resources),    \
                &sh_tmu##idx##_platform_data,           \
@@ -298,10 +285,10 @@ void __init r8a7778_add_dt_devices(void)
        void __iomem *base = ioremap_nocache(0xf0100000, 0x1000);
        if (base) {
                /*
-                 * Early BRESP enable, Shared attribute override enable, 64K*16way
+                 * Shared attribute override enable, 64K*16way
                 * don't call iounmap(base)
                 */
-                l2x0_init(base, 0x40470000, 0x82000fff);
+                l2x0_init(base, 0x00400000, 0xc20f0fff);
        }
 #endif
@@ -312,7 +299,6 @@ void __init r8a7778_add_dt_devices(void)
        r8a7778_register_scif(4);
        r8a7778_register_scif(5);
        r8a7778_register_tmu(0);
-        r8a7778_register_tmu(1);
 }
 /* HPB-DMA */
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 8e860b36997a..aba4ed652d54 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -219,64 +219,25 @@ R8A7779_SCIF(4, 0xffe44000, gic_iid(0x7c));
 R8A7779_SCIF(5, 0xffe45000, gic_iid(0x7d));
 /* TMU */
-static struct sh_timer_config tmu00_platform_data = {
+static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU00",
+        .channels_mask = 7,
-        .channel_offset = 0x4,
-        .timer_bit = 0,
-        .clockevent_rating = 200,
 };
-static struct resource tmu00_resources[] = {
+static struct resource tmu0_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xffd80000, 0x30),
-                .name   = "TMU00",
+        DEFINE_RES_IRQ(gic_iid(0x40)),
-                .start  = 0xffd80008,
+        DEFINE_RES_IRQ(gic_iid(0x41)),
-                .end    = 0xffd80013,
+        DEFINE_RES_IRQ(gic_iid(0x42)),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x40),
-                .flags  = IORESOURCE_IRQ,
-        },
 };
-static struct platform_device tmu00_device = {
+static struct platform_device tmu0_device = {
-        .name           = "sh_tmu",
+        .name           = "sh-tmu",
        .id             = 0,
        .dev = {
-                .platform_data  = &tmu00_platform_data,
+                .platform_data  = &tmu0_platform_data,
-        },
-        .resource       = tmu00_resources,
-        .num_resources  = ARRAY_SIZE(tmu00_resources),
-};
-static struct sh_timer_config tmu01_platform_data = {
-        .name = "TMU01",
-        .channel_offset = 0x10,
-        .timer_bit = 1,
-        .clocksource_rating = 200,
-};
-static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xffd80014,
-                .end    = 0xffd8001f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_iid(0x41),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tmu01_device = {
-        .name           = "sh_tmu",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &tmu01_platform_data,
        },
-        .resource       = tmu01_resources,
+        .resource       = tmu0_resources,
-        .num_resources  = ARRAY_SIZE(tmu01_resources),
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
 };
 /* I2C */
@@ -685,8 +646,7 @@ static struct platform_device *r8a7779_devices_dt[] __initdata = {
        &scif3_device,
        &scif4_device,
        &scif5_device,
-        &tmu00_device,
+        &tmu0_device,
-        &tmu01_device,
 };
 static struct platform_device *r8a7779_standard_devices[] __initdata = {
@@ -700,8 +660,8 @@ static struct platform_device *r8a7779_standard_devices[] __initdata = {
 void __init r8a7779_add_standard_devices(void)
 {
 #ifdef CONFIG_CACHE_L2X0
-        /* Early BRESP enable, Shared attribute override enable, 64K*16way */
+        /* Shared attribute override enable, 64K*16way */
-        l2x0_init(IOMEM(0xf0100000), 0x40470000, 0x82000fff);
+        l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
 #endif
        r8a7779_pm_init();
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index c4616f0698c6..6bd08b127fa4 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -185,12 +185,6 @@ void __init r8a7790_pinmux_init(void)
        r8a7790_register_gpio(3);
        r8a7790_register_gpio(4);
        r8a7790_register_gpio(5);
-        r8a7790_register_i2c(0);
-        r8a7790_register_i2c(1);
-        r8a7790_register_i2c(2);
-        r8a7790_register_i2c(3);
-        r8a7790_register_audio_dmac(0);
-        r8a7790_register_audio_dmac(1);
 }
 #define __R8A7790_SCIF(scif_type, _scscr, index, baseaddr, irq)         \
@@ -269,20 +263,17 @@ static const struct resource thermal_resources[] __initconst = {
                                        thermal_resources,              \
                                        ARRAY_SIZE(thermal_resources))
-static const struct sh_timer_config cmt00_platform_data __initconst = {
+static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT00",
+        .channels_mask = 0x60,
-        .timer_bit = 0,
-        .clockevent_rating = 80,
 };
-static const struct resource cmt00_resources[] __initconst = {
+static struct resource cmt0_resources[] = {
-        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0000, 0x1004),
-        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)),
-        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
 };
 #define r8a7790_register_cmt(idx)                                       \
-        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+        platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
                                          idx, cmt##idx##_resources,    \
                                          ARRAY_SIZE(cmt##idx##_resources), \
                                          &cmt##idx##_platform_data,    \
@@ -290,6 +281,11 @@ static const struct resource cmt00_resources[] __initconst = {
 void __init r8a7790_add_dt_devices(void)
 {
+        r8a7790_register_cmt(0);
+}
+void __init r8a7790_add_standard_devices(void)
+{
        r8a7790_register_scif(0);
        r8a7790_register_scif(1);
        r8a7790_register_scif(2);
@@ -300,14 +296,15 @@ void __init r8a7790_add_dt_devices(void)
        r8a7790_register_scif(7);
        r8a7790_register_scif(8);
        r8a7790_register_scif(9);
-        r8a7790_register_cmt(00);
-}
-void __init r8a7790_add_standard_devices(void)
-{
        r8a7790_add_dt_devices();
        r8a7790_register_irqc(0);
        r8a7790_register_thermal();
+        r8a7790_register_i2c(0);
+        r8a7790_register_i2c(1);
+        r8a7790_register_i2c(2);
+        r8a7790_register_i2c(3);
+        r8a7790_register_audio_dmac(0);
+        r8a7790_register_audio_dmac(1);
 }
 void __init r8a7790_init_early(void)
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c
index e28404e43860..04a96ddb3224 100644
--- a/arch/arm/mach-shmobile/setup-r8a7791.c
+++ b/arch/arm/mach-shmobile/setup-r8a7791.c
@@ -128,20 +128,17 @@ R8A7791_SCIFA(14, 0xe6c80000, gic_spi(31)); /* SCIFA5 */
                                          &scif##index##_platform_data,        \
                                          sizeof(scif##index##_platform_data))
-static const struct sh_timer_config cmt00_platform_data __initconst = {
+static struct sh_timer_config cmt0_platform_data = {
-        .name = "CMT00",
+        .channels_mask = 0x60,
-        .timer_bit = 0,
-        .clockevent_rating = 80,
 };
-static const struct resource cmt00_resources[] __initconst = {
+static struct resource cmt0_resources[] = {
-        DEFINE_RES_MEM(0xffca0510, 0x0c),
+        DEFINE_RES_MEM(0xffca0000, 0x1004),
-        DEFINE_RES_MEM(0xffca0500, 0x04),
+        DEFINE_RES_IRQ(gic_spi(142)),
-        DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
 };
 #define r8a7791_register_cmt(idx)                                       \
-        platform_device_register_resndata(&platform_bus, "sh_cmt",      \
+        platform_device_register_resndata(&platform_bus, "sh-cmt-48-gen2", \
                                          idx, cmt##idx##_resources,    \
                                          ARRAY_SIZE(cmt##idx##_resources), \
                                          &cmt##idx##_platform_data,    \
@@ -185,6 +182,11 @@ static const struct resource thermal_resources[] __initconst = {
 void __init r8a7791_add_dt_devices(void)
 {
+        r8a7791_register_cmt(0);
+}
+void __init r8a7791_add_standard_devices(void)
+{
        r8a7791_register_scif(0);
        r8a7791_register_scif(1);
        r8a7791_register_scif(2);
@@ -200,23 +202,11 @@ void __init r8a7791_add_dt_devices(void)
        r8a7791_register_scif(12);
        r8a7791_register_scif(13);
        r8a7791_register_scif(14);
-        r8a7791_register_cmt(00);
-}
-void __init r8a7791_add_standard_devices(void)
-{
        r8a7791_add_dt_devices();
        r8a7791_register_irqc(0);
        r8a7791_register_thermal();
 }
-void __init r8a7791_init_early(void)
-{
-#ifndef CONFIG_ARM_ARCH_TIMER
-        shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
-#endif
-}
 #ifdef CONFIG_USE_OF
 static const char *r8a7791_boards_compat_dt[] __initdata = {
        "renesas,r8a7791",
@@ -225,7 +215,7 @@ static const char *r8a7791_boards_compat_dt[] __initdata = {
 DT_MACHINE_START(R8A7791_DT, "Generic R8A7791 (Flattened Device Tree)")
        .smp            = smp_ops(r8a7791_smp_ops),
-        .init_early     = r8a7791_init_early,
+        .init_early     = shmobile_init_delay,
        .init_time      = rcar_gen2_timer_init,
        .dt_compat      = r8a7791_boards_compat_dt,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c
index 10604480f325..542c5a47173f 100644
--- a/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -30,12 +30,16 @@
 u32 rcar_gen2_read_mode_pins(void)
 {
-        void __iomem *modemr = ioremap_nocache(MODEMR, 4);
+        static u32 mode;
-        u32 mode;
+        static bool mode_valid;
-        BUG_ON(!modemr);
+        if (!mode_valid) {
-        mode = ioread32(modemr);
+                void __iomem *modemr = ioremap_nocache(MODEMR, 4);
-        iounmap(modemr);
+                BUG_ON(!modemr);
+                mode = ioread32(modemr);
+                iounmap(modemr);
+                mode_valid = true;
+        }
        return mode;
 }
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 27301278c208..2a8b9f2a2f54 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -119,28 +119,16 @@ SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
 /* CMT */
 static struct sh_timer_config cmt2_platform_data = {
-        .name = "CMT2",
+        .channels_mask = 0x20,
-        .channel_offset = 0x40,
-        .timer_bit = 5,
-        .clockevent_rating = 125,
-        .clocksource_rating = 125,
 };
 static struct resource cmt2_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xe6130000, 0x50),
-                .name   = "CMT2",
+        DEFINE_RES_IRQ(evt2irq(0x0b80)),
-                .start  = 0xe6130040,
-                .end    = 0xe613004b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = evt2irq(0x0b80), /* CMT2 */
-                .flags  = IORESOURCE_IRQ,
-        },
 };
 static struct platform_device cmt2_device = {
-        .name           = "sh_cmt",
+        .name           = "sh-cmt-32-fast",
        .id             = 2,
        .dev = {
                .platform_data  = &cmt2_platform_data,
@@ -150,64 +138,25 @@ static struct platform_device cmt2_device = {
 };
 /* TMU */
-static struct sh_timer_config tmu00_platform_data = {
+static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU00",
+        .channels_mask = 7,
-        .channel_offset = 0x4,
-        .timer_bit = 0,
-        .clockevent_rating = 200,
 };
-static struct resource tmu00_resources[] = {
+static struct resource tmu0_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xfff60000, 0x2c),
-                .name   = "TMU00",
+        DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
-                .start  = 0xfff60008,
+        DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
-                .end    = 0xfff60013,
+        DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
-                .flags  = IORESOURCE_IRQ,
-        },
 };
-static struct platform_device tmu00_device = {
+static struct platform_device tmu0_device = {
-        .name           = "sh_tmu",
+        .name           = "sh-tmu",
        .id             = 0,
        .dev = {
-                .platform_data  = &tmu00_platform_data,
+                .platform_data  = &tmu0_platform_data,
-        },
-        .resource       = tmu00_resources,
-        .num_resources  = ARRAY_SIZE(tmu00_resources),
-};
-static struct sh_timer_config tmu01_platform_data = {
-        .name = "TMU01",
-        .channel_offset = 0x10,
-        .timer_bit = 1,
-        .clocksource_rating = 200,
-};
-static struct resource tmu01_resources[] = {
-        [0] = {
-                .name   = "TMU01",
-                .start  = 0xfff60014,
-                .end    = 0xfff6001f,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tmu01_device = {
-        .name           = "sh_tmu",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &tmu01_platform_data,
        },
-        .resource       = tmu01_resources,
+        .resource       = tmu0_resources,
-        .num_resources  = ARRAY_SIZE(tmu01_resources),
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
 };
 /* I2C */
@@ -952,8 +901,7 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
        &scif5_device,
        &scif6_device,
        &cmt2_device,
-        &tmu00_device,
+        &tmu0_device,
-        &tmu01_device,
        &ipmmu_device,
 };
@@ -1000,8 +948,7 @@ void __init sh7372_add_standard_devices(void)
                { "A4R", &veu2_device, },
                { "A4R", &veu3_device, },
                { "A4R", &jpu_device, },
-                { "A4R", &tmu00_device, },
+                { "A4R", &tmu0_device, },
-                { "A4R", &tmu01_device, },
        };
        sh7372_init_pm_domains();
@@ -1037,11 +984,7 @@ void __init sh7372_add_early_devices_dt(void)
 {
        shmobile_setup_delay(800, 1, 3); /* Cortex-A8 @ 800MHz */
-        early_platform_add_devices(sh7372_early_devices,
+        sh7372_add_early_devices();
-                                   ARRAY_SIZE(sh7372_early_devices));
-        /* setup early console here as well */
-        shmobile_setup_console();
 }
 void __init sh7372_add_standard_devices_dt(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index f74ab530c71d..ad00724a2269 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -104,86 +104,45 @@ SH73A0_SCIF(PORT_SCIFA, 6, 0xe6cc0000, gic_spi(156));
 SH73A0_SCIF(PORT_SCIFA, 7, 0xe6cd0000, gic_spi(143));
 SH73A0_SCIF(PORT_SCIFB, 8, 0xe6c30000, gic_spi(80));
-static struct sh_timer_config cmt10_platform_data = {
+static struct sh_timer_config cmt1_platform_data = {
-        .name = "CMT10",
+        .channels_mask = 0x3f,
-        .channel_offset = 0x10,
-        .timer_bit = 0,
-        .clockevent_rating = 80,
-        .clocksource_rating = 125,
 };
-static struct resource cmt10_resources[] = {
+static struct resource cmt1_resources[] = {
-        [0] = {
+        DEFINE_RES_MEM(0xe6138000, 0x200),
-                .name   = "CMT10",
+        DEFINE_RES_IRQ(gic_spi(65)),
-                .start  = 0xe6138010,
-                .end    = 0xe613801b,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = gic_spi(65),
-                .flags  = IORESOURCE_IRQ,
-        },
 };
-static struct platform_device cmt10_device = {
+static struct platform_device cmt1_device = {
-        .name           = "sh_cmt",
+        .name           = "sh-cmt-48",
-        .id             = 10,
+        .id             = 1,
        .dev = {
-                .platform_data  = &cmt10_platform_data,
+                .platform_data  = &cmt1_platform_data,
        },
-        .resource       = cmt10_resources,
+        .resource       = cmt1_resources,
-        .num_resources  = ARRAY_SIZE(cmt10_resources),
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
 };
 /* TMU */
-static struct sh_timer_config tmu00_platform_data = {
+static struct sh_timer_config tmu0_platform_data = {
-        .name = "TMU00",
+        .channels_mask = 7,
-        .channel_offset = 0x4,
-        .timer_bit = 0,
-        .clockevent_rating = 200,
 };
-static struct resource tmu00_resources[] = {
+static struct resource tmu0_resources[] = {
-        [0] = DEFINE_RES_MEM(0xfff60008, 0xc),
+        DEFINE_RES_MEM(0xfff60000, 0x2c),
-        [1] = {
+        DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
-                .start  = intcs_evt2irq(0x0e80), /* TMU0_TUNI00 */
+        DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
-                .flags  = IORESOURCE_IRQ,
+        DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
-        },
 };
-static struct platform_device tmu00_device = {
+static struct platform_device tmu0_device = {
-        .name           = "sh_tmu",
+        .name           = "sh-tmu",
        .id             = 0,
        .dev = {
-                .platform_data  = &tmu00_platform_data,
+                .platform_data  = &tmu0_platform_data,
-        },
-        .resource       = tmu00_resources,
-        .num_resources  = ARRAY_SIZE(tmu00_resources),
-};
-static struct sh_timer_config tmu01_platform_data = {
-        .name = "TMU01",
-        .channel_offset = 0x10,
-        .timer_bit = 1,
-        .clocksource_rating = 200,
-};
-static struct resource tmu01_resources[] = {
-        [0] = DEFINE_RES_MEM(0xfff60014, 0xc),
-        [1] = {
-                .start  = intcs_evt2irq(0x0ea0), /* TMU0_TUNI01 */
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-static struct platform_device tmu01_device = {
-        .name           = "sh_tmu",
-        .id             = 1,
-        .dev = {
-                .platform_data  = &tmu01_platform_data,
        },
-        .resource       = tmu01_resources,
+        .resource       = tmu0_resources,
-        .num_resources  = ARRAY_SIZE(tmu01_resources),
+        .num_resources  = ARRAY_SIZE(tmu0_resources),
 };
 static struct resource i2c0_resources[] = {
@@ -746,12 +705,11 @@ static struct platform_device *sh73a0_devices_dt[] __initdata = {
        &scif6_device,
        &scif7_device,
        &scif8_device,
-        &cmt10_device,
+        &cmt1_device,
 };
 static struct platform_device *sh73a0_early_devices[] __initdata = {
-        &tmu00_device,
+        &tmu0_device,
-        &tmu01_device,
        &ipmmu_device,
 };
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index f2ca92308f75..2dfd748da7f3 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -24,7 +24,6 @@
 #include <linux/io.h>
 #include <linux/delay.h>
 #include <mach/common.h>
-#include <mach/emev2.h>
 #include <asm/smp_plat.h>
 #include <asm/smp_scu.h>
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 2df5bd190fe4..ec979529f30f 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -20,6 +20,7 @@
 #include <asm/smp_plat.h>
 #include <mach/common.h>
 #include <mach/r8a7791.h>
+#include <mach/rcar-gen2.h>
 #define RST             0xe6160000
 #define CA15BAR         0x0020
@@ -51,9 +52,21 @@ static void __init r8a7791_smp_prepare_cpus(unsigned int max_cpus)
        iounmap(p);
 }
+static int r8a7791_smp_boot_secondary(unsigned int cpu,
+                                      struct task_struct *idle)
+{
+        /* Error out when hardware debug mode is enabled */
+        if (rcar_gen2_read_mode_pins() & BIT(21)) {
+                pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
+                return -ENOTSUPP;
+        }
+        return shmobile_smp_apmu_boot_secondary(cpu, idle);
+}
 struct smp_operations r8a7791_smp_ops __initdata = {
        .smp_prepare_cpus       = r8a7791_smp_prepare_cpus,
-        .smp_boot_secondary     = shmobile_smp_apmu_boot_secondary,
+        .smp_boot_secondary     = r8a7791_smp_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
        .cpu_disable            = shmobile_smp_cpu_disable,
        .cpu_die                = shmobile_smp_apmu_cpu_die,
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index 62d7052d6f21..68bc0b82226d 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -21,6 +21,24 @@
 #include <linux/platform_device.h>
 #include <linux/clocksource.h>
 #include <linux/delay.h>
+#include <linux/of_address.h>
+void __init shmobile_setup_delay_hz(unsigned int max_cpu_core_hz,
+                                    unsigned int mult, unsigned int div)
+{
+        /* calculate a worst-case loops-per-jiffy value
+         * based on maximum cpu core hz setting and the
+         * __delay() implementation in arch/arm/lib/delay.S
+         *
+         * this will result in a longer delay than expected
+         * when the cpu core runs on lower frequencies.
+         */
+        unsigned int value = HZ * div / mult;
+        if (!preset_lpj)
+                preset_lpj = max_cpu_core_hz / value;
+}
 void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                                 unsigned int mult, unsigned int div)
@@ -39,6 +57,33 @@ void __init shmobile_setup_delay(unsigned int max_cpu_core_mhz,
                preset_lpj = max_cpu_core_mhz * value;
 }
+void __init shmobile_init_delay(void)
+{
+        struct device_node *np, *parent;
+        u32 max_freq, freq;
+        max_freq = 0;
+        parent = of_find_node_by_path("/cpus");
+        if (parent) {
+                for_each_child_of_node(parent, np) {
+                        if (!of_property_read_u32(np, "clock-frequency", &freq))
+                                max_freq = max(max_freq, freq);
+                }
+                of_node_put(parent);
+        }
+        if (max_freq) {
+                if (of_find_compatible_node(NULL, NULL, "arm,cortex-a8"))
+                        shmobile_setup_delay_hz(max_freq, 1, 3);
+                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
+                        shmobile_setup_delay_hz(max_freq, 1, 3);
+                else if (of_find_compatible_node(NULL, NULL, "arm,cortex-a15"))
+                        if (!IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
+                                shmobile_setup_delay_hz(max_freq, 2, 4);
+        }
+}
 static void __init shmobile_late_time_init(void)
 {
        /*
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index d86231e11b34..adbf38314ca8 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -98,22 +98,17 @@ static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
        writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
 }
-static void __init socfpga_cyclone5_init(void)
-{
-        l2x0_of_init(0, ~0UL);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char *altera_dt_match[] = {
        "altr,socfpga",
        NULL
 };
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
+        .l2c_aux_val    = 0,
+        .l2c_aux_mask   = ~0,
        .smp            = smp_ops(socfpga_smp_ops),
        .map_io         = socfpga_map_io,
        .init_irq       = socfpga_init_irq,
-        .init_machine   = socfpga_cyclone5_init,
        .restart        = socfpga_cyclone5_restart,
        .dt_compat      = altera_dt_match,
 MACHINE_END
diff --git a/arch/arm/mach-spear/platsmp.c b/arch/arm/mach-spear/platsmp.c
index c19751fff2c6..fd4297713d67 100644
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -20,6 +20,18 @@
 #include <mach/spear.h>
 #include "generic.h"
+/*
+ * Write pen_release in a way that is guaranteed to be visible to all
+ * observers, irrespective of whether they're taking part in coherency
+ * or not.  This is necessary for the hotplug code to work reliably.
+ */
+static void write_pen_release(int val)
+{
+        pen_release = val;
+        smp_wmb();
+        sync_cache_w(&pen_release);
+}
 static DEFINE_SPINLOCK(boot_lock);
 static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
@@ -30,8 +42,7 @@ static void spear13xx_secondary_init(unsigned int cpu)
         * let the primary processor know we're out of the
         * pen, then head off into the C entry point
         */
-        pen_release = -1;
+        write_pen_release(-1);
-        smp_wmb();
        /*
         * Synchronise with the boot thread.
@@ -58,9 +69,7 @@ static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
         * Note that "pen_release" is the hardware CPU ID, whereas
         * "cpu" is Linux's internal ID.
         */
-        pen_release = cpu;
+        write_pen_release(cpu);
-        flush_cache_all();
-        outer_flush_all();
        timeout = jiffies + (1 * HZ);
        while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c
index 7aa6e8cf830f..c9897ea38980 100644
--- a/arch/arm/mach-spear/spear13xx.c
+++ b/arch/arm/mach-spear/spear13xx.c
@@ -38,15 +38,15 @@ void __init spear13xx_l2x0_init(void)
        if (!IS_ENABLED(CONFIG_CACHE_L2X0))
                return;
-        writel_relaxed(0x06, VA_L2CC_BASE + L2X0_PREFETCH_CTRL);
+        writel_relaxed(0x06, VA_L2CC_BASE + L310_PREFETCH_CTRL);
        /*
         * Program following latencies in order to make
         * SPEAr1340 work at 600 MHz
         */
-        writel_relaxed(0x221, VA_L2CC_BASE + L2X0_TAG_LATENCY_CTRL);
+        writel_relaxed(0x221, VA_L2CC_BASE + L310_TAG_LATENCY_CTRL);
-        writel_relaxed(0x441, VA_L2CC_BASE + L2X0_DATA_LATENCY_CTRL);
+        writel_relaxed(0x441, VA_L2CC_BASE + L310_DATA_LATENCY_CTRL);
-        l2x0_init(VA_L2CC_BASE, 0x70A60001, 0xfe00ffff);
+        l2x0_init(VA_L2CC_BASE, 0x30a00001, 0xfe0fffff);
 }
 /*
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 1217fb598cfd..3cf6ef8d4317 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -14,33 +14,19 @@
 #include "smp.h"
-void __init stih41x_l2x0_init(void)
-{
-        u32 way_size = 0x4;
-        u32 aux_ctrl;
-        /* may be this can be encoded in macros like BIT*() */
-        aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
-                (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
-                (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) |
-                (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
-        l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK);
-}
-static void __init stih41x_machine_init(void)
-{
-        stih41x_l2x0_init();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char *stih41x_dt_match[] __initdata = {
        "st,stih415",
        "st,stih416",
+        "st,stih407",
        NULL
 };
 DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree")
-        .init_machine   = stih41x_machine_init,
-        .smp            = smp_ops(sti_smp_ops),
        .dt_compat      = stih41x_dt_match,
+        .l2c_aux_val    = L2C_AUX_CTRL_SHARED_OVERRIDE |
+                          L310_AUX_CTRL_DATA_PREFETCH |
+                          L310_AUX_CTRL_INSTR_PREFETCH |
+                          L2C_AUX_CTRL_WAY_SIZE(4),
+        .l2c_aux_mask   = 0xc0000fff,
+        .smp            = smp_ops(sti_smp_ops),
 MACHINE_END
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index b57d7d53b9d3..0fbd4f156bfa 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,14 +1,38 @@
-config ARCH_SUNXI
+menuconfig ARCH_SUNXI
-        bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
+        bool "Allwinner SoCs" if ARCH_MULTI_V7
-        select ARCH_HAS_RESET_CONTROLLER
        select ARCH_REQUIRE_GPIOLIB
-        select ARM_GIC
-        select ARM_PSCI
        select CLKSRC_MMIO
        select GENERIC_IRQ_CHIP
-        select HAVE_ARM_ARCH_TIMER
        select PINCTRL
        select PINCTRL_SUNXI
-        select RESET_CONTROLLER
        select SUN4I_TIMER
+if ARCH_SUNXI
+config MACH_SUN4I
+        bool "Allwinner A10 (sun4i) SoCs support"
+        default ARCH_SUNXI
+config MACH_SUN5I
+        bool "Allwinner A10s / A13 (sun5i) SoCs support"
+        default ARCH_SUNXI
+        select SUN5I_HSTIMER
+config MACH_SUN6I
+        bool "Allwinner A31 (sun6i) SoCs support"
+        default ARCH_SUNXI
+        select ARCH_HAS_RESET_CONTROLLER
+        select ARM_GIC
+        select MFD_SUN6I_PRCM
+        select RESET_CONTROLLER
+        select SUN5I_HSTIMER
+config MACH_SUN7I
+        bool "Allwinner A20 (sun7i) SoCs support"
+        default ARCH_SUNXI
+        select ARM_GIC
+        select ARM_PSCI
+        select HAVE_ARM_ARCH_TIMER
        select SUN5I_HSTIMER
+endif
diff --git a/arch/arm/mach-sunxi/common.h b/arch/arm/mach-sunxi/common.h
deleted file mode 100644
index 9e5ac4756cbb..000000000000
--- a/arch/arm/mach-sunxi/common.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Core functions for Allwinner SoCs
- *
- * Copyright (C) 2013 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef __ARCH_SUNXI_COMMON_H_
-#define __ARCH_SUNXI_COMMON_H_
-void sun6i_secondary_startup(void);
-extern struct smp_operations sun6i_smp_ops;
-#endif /* __ARCH_SUNXI_COMMON_H_ */
diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c
index 0c7dbce033cc..c53077bb8c3f 100644
--- a/arch/arm/mach-sunxi/platsmp.c
+++ b/arch/arm/mach-sunxi/platsmp.c
@@ -21,8 +21,6 @@
 #include <linux/of_address.h>
 #include <linux/smp.h>
-#include "common.h"
 #define CPUCFG_CPU_PWR_CLAMP_STATUS_REG(cpu)    ((cpu) * 0x40 + 0x64)
 #define CPUCFG_CPU_RST_CTRL_REG(cpu)            (((cpu) + 1) * 0x40)
 #define CPUCFG_CPU_CTRL_REG(cpu)                (((cpu) + 1) * 0x40 + 0x04)
@@ -122,3 +120,4 @@ struct smp_operations sun6i_smp_ops __initdata = {
        .smp_prepare_cpus       = sun6i_smp_prepare_cpus,
        .smp_boot_secondary     = sun6i_smp_boot_secondary,
 };
+CPU_METHOD_OF_DECLARE(sun6i_smp, "allwinner,sun6i-a31", &sun6i_smp_ops);
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 460b5a4962ef..3f9587bb51f6 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -12,111 +12,8 @@
 #include <linux/clk-provider.h>
 #include <linux/clocksource.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-#include <linux/io.h>
-#include <linux/reboot.h>
 #include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/system_misc.h>
-#include "common.h"
-#define SUN4I_WATCHDOG_CTRL_REG         0x00
-#define SUN4I_WATCHDOG_CTRL_RESTART             BIT(0)
-#define SUN4I_WATCHDOG_MODE_REG         0x04
-#define SUN4I_WATCHDOG_MODE_ENABLE              BIT(0)
-#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        BIT(1)
-#define SUN6I_WATCHDOG1_IRQ_REG         0x00
-#define SUN6I_WATCHDOG1_CTRL_REG        0x10
-#define SUN6I_WATCHDOG1_CTRL_RESTART            BIT(0)
-#define SUN6I_WATCHDOG1_CONFIG_REG      0x14
-#define SUN6I_WATCHDOG1_CONFIG_RESTART          BIT(0)
-#define SUN6I_WATCHDOG1_CONFIG_IRQ              BIT(1)
-#define SUN6I_WATCHDOG1_MODE_REG        0x18
-#define SUN6I_WATCHDOG1_MODE_ENABLE             BIT(0)
-static void __iomem *wdt_base;
-static void sun4i_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (!wdt_base)
-                return;
-        /* Enable timer and set reset bit in the watchdog */
-        writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
-               wdt_base + SUN4I_WATCHDOG_MODE_REG);
-        /*
-         * Restart the watchdog. The default (and lowest) interval
-         * value for the watchdog is 0.5s.
-         */
-        writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
-        while (1) {
-                mdelay(5);
-                writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
-                       wdt_base + SUN4I_WATCHDOG_MODE_REG);
-        }
-}
-static void sun6i_restart(enum reboot_mode mode, const char *cmd)
-{
-        if (!wdt_base)
-                return;
-        /* Disable interrupts */
-        writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
-        /* We want to disable the IRQ and just reset the whole system */
-        writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
-                wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
-        /* Enable timer. The default and lowest interval value is 0.5s */
-        writel(SUN6I_WATCHDOG1_MODE_ENABLE,
-                wdt_base + SUN6I_WATCHDOG1_MODE_REG);
-        /* Restart the watchdog. */
-        writel(SUN6I_WATCHDOG1_CTRL_RESTART,
-                wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
-        while (1) {
-                mdelay(5);
-                writel(SUN6I_WATCHDOG1_MODE_ENABLE,
-                        wdt_base + SUN6I_WATCHDOG1_MODE_REG);
-        }
-}
-static struct of_device_id sunxi_restart_ids[] = {
-        { .compatible = "allwinner,sun4i-a10-wdt" },
-        { .compatible = "allwinner,sun6i-a31-wdt" },
-        { /*sentinel*/ }
-};
-static void sunxi_setup_restart(void)
-{
-        struct device_node *np;
-        np = of_find_matching_node(NULL, sunxi_restart_ids);
-        if (WARN(!np, "unable to setup watchdog restart"))
-                return;
-        wdt_base = of_iomap(np, 0);
-        WARN(!wdt_base, "failed to map watchdog base address");
-}
-static void __init sunxi_dt_init(void)
-{
-        sunxi_setup_restart();
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
 static const char * const sunxi_board_dt_compat[] = {
        "allwinner,sun4i-a10",
@@ -126,9 +23,7 @@ static const char * const sunxi_board_dt_compat[] = {
 };
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
-        .init_machine   = sunxi_dt_init,
        .dt_compat      = sunxi_board_dt_compat,
-        .restart        = sun4i_restart,
 MACHINE_END
 static const char * const sun6i_board_dt_compat[] = {
@@ -140,16 +35,14 @@ extern void __init sun6i_reset_init(void);
 static void __init sun6i_timer_init(void)
 {
        of_clk_init(NULL);
-        sun6i_reset_init();
+        if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
+                sun6i_reset_init();
        clocksource_of_init();
 }
 DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")
-        .init_machine   = sunxi_dt_init,
        .init_time      = sun6i_timer_init,
        .dt_compat      = sun6i_board_dt_compat,
-        .restart        = sun6i_restart,
-        .smp            = smp_ops(sun6i_smp_ops),
 MACHINE_END
 static const char * const sun7i_board_dt_compat[] = {
@@ -158,7 +51,5 @@ static const char * const sun7i_board_dt_compat[] = {
 };
 DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family")
-        .init_machine   = sunxi_dt_init,
        .dt_compat      = sun7i_board_dt_compat,
-        .restart        = sun4i_restart,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 55b305d51669..e16999e5b735 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -7,7 +7,6 @@ config ARCH_TEGRA
        select CLKSRC_MMIO
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
-        select MIGHT_HAVE_PCI
        select PINCTRL
        select ARCH_HAS_RESET_CONTROLLER
        select RESET_CONTROLLER
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 6e92a7c2ecbd..f4a89698e5b0 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -35,8 +35,6 @@ void tegra20_sleep_core_init(void);
 void tegra30_lp1_iram_hook(void);
 void tegra30_sleep_core_init(void);
-extern unsigned long l2x0_saved_regs_addr;
 void tegra_clear_cpu_in_lp2(void);
 bool tegra_set_cpu_in_lp2(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index fb7920201ab4..7c7123e7557b 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -41,6 +41,14 @@
 #define PMC_REMOVE_CLAMPING             0x34
 #define PMC_PWRGATE_STATUS              0x38
+#define PMC_SCRATCH0                    0x50
+#define PMC_SCRATCH0_MODE_RECOVERY      (1 << 31)
+#define PMC_SCRATCH0_MODE_BOOTLOADER    (1 << 30)
+#define PMC_SCRATCH0_MODE_RCM           (1 << 1)
+#define PMC_SCRATCH0_MODE_MASK          (PMC_SCRATCH0_MODE_RECOVERY | \
+                                         PMC_SCRATCH0_MODE_BOOTLOADER | \
+                                         PMC_SCRATCH0_MODE_RCM)
 #define PMC_CPUPWRGOOD_TIMER    0xc8
 #define PMC_CPUPWROFF_TIMER     0xcc
@@ -165,6 +173,22 @@ void tegra_pmc_restart(enum reboot_mode mode, const char *cmd)
 {
        u32 val;
+        val = tegra_pmc_readl(PMC_SCRATCH0);
+        val &= ~PMC_SCRATCH0_MODE_MASK;
+        if (cmd) {
+                if (strcmp(cmd, "recovery") == 0)
+                        val |= PMC_SCRATCH0_MODE_RECOVERY;
+                if (strcmp(cmd, "bootloader") == 0)
+                        val |= PMC_SCRATCH0_MODE_BOOTLOADER;
+                if (strcmp(cmd, "forced-recovery") == 0)
+                        val |= PMC_SCRATCH0_MODE_RCM;
+        }
+        tegra_pmc_writel(val, PMC_SCRATCH0);
        val = tegra_pmc_readl(0);
        val |= 0x10;
        tegra_pmc_writel(val, 0);
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 8c1ba4fea384..578d4d1ad648 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -19,7 +19,6 @@
 #include <asm/cache.h>
 #include <asm/asm-offsets.h>
-#include <asm/hardware/cache-l2x0.h>
 #include "flowctrl.h"
 #include "fuse.h"
@@ -78,8 +77,10 @@ ENTRY(tegra_resume)
        str     r1, [r0]
 #endif
+#ifdef CONFIG_CACHE_L2X0
        /* L2 cache resume & re-enable */
-        l2_cache_resume r0, r1, r2, l2x0_saved_regs_addr
+        bl      l2c310_early_resume
+#endif
 end_ca9_scu_l2_resume:
        mov32   r9, 0xc0f
        cmp     r8, r9
@@ -89,12 +90,6 @@ end_ca9_scu_l2_resume:
 ENDPROC(tegra_resume)
 #endif
-#ifdef CONFIG_CACHE_L2X0
-        .globl  l2x0_saved_regs_addr
-l2x0_saved_regs_addr:
-        .long   0
-#endif
        .align L1_CACHE_SHIFT
 ENTRY(__tegra_cpu_reset_handler_start)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index a4edbb3abd3d..339fe42cd6fb 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -120,37 +120,6 @@
        mov     \tmp1, \tmp1, lsr #8
 .endm
-/* Macro to resume & re-enable L2 cache */
-#ifndef L2X0_CTRL_EN
-#define L2X0_CTRL_EN    1
-#endif
-#ifdef CONFIG_CACHE_L2X0
-.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
-        W(adr)  \tmp1, \phys_l2x0_saved_regs
-        ldr     \tmp1, [\tmp1]
-        ldr     \tmp2, [\tmp1, #L2X0_R_PHY_BASE]
-        ldr     \tmp3, [\tmp2, #L2X0_CTRL]
-        tst     \tmp3, #L2X0_CTRL_EN
-        bne     exit_l2_resume
-        ldr     \tmp3, [\tmp1, #L2X0_R_TAG_LATENCY]
-        str     \tmp3, [\tmp2, #L2X0_TAG_LATENCY_CTRL]
-        ldr     \tmp3, [\tmp1, #L2X0_R_DATA_LATENCY]
-        str     \tmp3, [\tmp2, #L2X0_DATA_LATENCY_CTRL]
-        ldr     \tmp3, [\tmp1, #L2X0_R_PREFETCH_CTRL]
-        str     \tmp3, [\tmp2, #L2X0_PREFETCH_CTRL]
-        ldr     \tmp3, [\tmp1, #L2X0_R_PWR_CTRL]
-        str     \tmp3, [\tmp2, #L2X0_POWER_CTRL]
-        ldr     \tmp3, [\tmp1, #L2X0_R_AUX_CTRL]
-        str     \tmp3, [\tmp2, #L2X0_AUX_CTRL]
-        mov     \tmp3, #L2X0_CTRL_EN
-        str     \tmp3, [\tmp2, #L2X0_CTRL]
-exit_l2_resume:
-.endm
-#else /* CONFIG_CACHE_L2X0 */
-.macro l2_cache_resume, tmp1, tmp2, tmp3, phys_l2x0_saved_regs
-.endm
-#endif /* CONFIG_CACHE_L2X0 */
 #else
 void tegra_pen_lock(void);
 void tegra_pen_unlock(void);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 6191603379e1..15ac9fcc96b1 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -70,40 +70,12 @@ u32 tegra_uart_config[3] = {
        0,
 };
-static void __init tegra_init_cache(void)
-{
-#ifdef CONFIG_CACHE_L2X0
-        static const struct of_device_id pl310_ids[] __initconst = {
-                { .compatible = "arm,pl310-cache",  },
-                {}
-        };
-        struct device_node *np;
-        int ret;
-        void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
-        u32 aux_ctrl, cache_type;
-        np = of_find_matching_node(NULL, pl310_ids);
-        if (!np)
-                return;
-        cache_type = readl(p + L2X0_CACHE_TYPE);
-        aux_ctrl = (cache_type & 0x700) << (17-8);
-        aux_ctrl |= 0x7C400001;
-        ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
-        if (!ret)
-                l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
-#endif
-}
 static void __init tegra_init_early(void)
 {
        of_register_trusted_foundations();
        tegra_apb_io_init();
        tegra_init_fuse();
        tegra_cpu_reset_handler_init();
-        tegra_init_cache();
        tegra_powergate_init();
        tegra_hotplug_init();
 }
@@ -191,8 +163,10 @@ static const char * const tegra_dt_board_compat[] = {
 };
 DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
-        .map_io         = tegra_map_common_io,
+        .l2c_aux_val    = 0x3c400001,
+        .l2c_aux_mask   = 0xc20fc3fe,
        .smp            = smp_ops(tegra_smp_ops),
+        .map_io         = tegra_map_common_io,
        .init_early     = tegra_init_early,
        .init_irq       = tegra_dt_init_irq,
        .init_machine   = tegra_dt_init,
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index de544aabf292..9741de956b3e 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,8 +5,7 @@
 obj-y                           := cpu.o id.o timer.o pm.o
 obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
 obj-$(CONFIG_UX500_SOC_DB8500)  += cpu-db8500.o
-obj-$(CONFIG_MACH_MOP500)       += board-mop500-sdi.o \
+obj-$(CONFIG_MACH_MOP500)       += board-mop500-regulators.o \
-                                board-mop500-regulators.o \
                                board-mop500-audio.o
 obj-$(CONFIG_SMP)               += platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)       += hotplug.o
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
deleted file mode 100644
index fcbf3a13a539..000000000000
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
- * License terms: GNU General Public License (GPL) version 2
- */
-#include <linux/kernel.h>
-#include <linux/gpio.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/mmci.h>
-#include <linux/mmc/host.h>
-#include <linux/platform_device.h>
-#include <linux/platform_data/dma-ste-dma40.h>
-#include <asm/mach-types.h>
-#include "db8500-regs.h"
-#include "board-mop500.h"
-#include "ste-dma40-db8500.h"
-/*
- * v2 has a new version of this block that need to be forced, the number found
- * in hardware is incorrect
- */
-#define U8500_SDI_V2_PERIPHID 0x10480180
-/*
- * SDI 0 (MicroSD slot)
- */
-#ifdef CONFIG_STE_DMA40
-struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type = DB8500_DMA_DEV29_SD_MM0,
-};
-static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV29_SD_MM0,
-};
-#endif
-struct mmci_platform_data mop500_sdi0_data = {
-        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_SD_HIGHSPEED |
-                                MMC_CAP_MMC_HIGHSPEED |
-                                MMC_CAP_ERASE |
-                                MMC_CAP_UHS_SDR12 |
-                                MMC_CAP_UHS_SDR25,
-        .gpio_wp        = -1,
-        .sigdir         = MCI_ST_FBCLKEN |
-                                MCI_ST_CMDDIREN |
-                                MCI_ST_DATA0DIREN |
-                                MCI_ST_DATA2DIREN,
-#ifdef CONFIG_STE_DMA40
-        .dma_filter     = stedma40_filter,
-        .dma_rx_param   = &mop500_sdi0_dma_cfg_rx,
-        .dma_tx_param   = &mop500_sdi0_dma_cfg_tx,
-#endif
-};
-/*
- * SDI1 (SDIO WLAN)
- */
-#ifdef CONFIG_STE_DMA40
-static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type = DB8500_DMA_DEV32_SD_MM1,
-};
-static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV32_SD_MM1,
-};
-#endif
-struct mmci_platform_data mop500_sdi1_data = {
-        .ocr_mask       = MMC_VDD_29_30,
-        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_NONREMOVABLE,
-        .gpio_cd        = -1,
-        .gpio_wp        = -1,
-#ifdef CONFIG_STE_DMA40
-        .dma_filter     = stedma40_filter,
-        .dma_rx_param   = &sdi1_dma_cfg_rx,
-        .dma_tx_param   = &sdi1_dma_cfg_tx,
-#endif
-};
-/*
- * SDI 2 (POP eMMC, not on DB8500ed)
- */
-#ifdef CONFIG_STE_DMA40
-struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type =  DB8500_DMA_DEV28_SD_MM2,
-};
-static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV28_SD_MM2,
-};
-#endif
-struct mmci_platform_data mop500_sdi2_data = {
-        .ocr_mask       = MMC_VDD_165_195,
-        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_8_BIT_DATA |
-                                MMC_CAP_NONREMOVABLE |
-                                MMC_CAP_MMC_HIGHSPEED |
-                                MMC_CAP_ERASE |
-                                MMC_CAP_CMD23,
-        .gpio_cd        = -1,
-        .gpio_wp        = -1,
-#ifdef CONFIG_STE_DMA40
-        .dma_filter     = stedma40_filter,
-        .dma_rx_param   = &mop500_sdi2_dma_cfg_rx,
-        .dma_tx_param   = &mop500_sdi2_dma_cfg_tx,
-#endif
-};
-/*
- * SDI 4 (on-board eMMC)
- */
-#ifdef CONFIG_STE_DMA40
-struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_DEV_TO_MEM,
-        .dev_type =  DB8500_DMA_DEV42_SD_MM4,
-};
-static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
-        .mode = STEDMA40_MODE_LOGICAL,
-        .dir = DMA_MEM_TO_DEV,
-        .dev_type = DB8500_DMA_DEV42_SD_MM4,
-};
-#endif
-struct mmci_platform_data mop500_sdi4_data = {
-        .f_max          = 100000000,
-        .capabilities   = MMC_CAP_4_BIT_DATA |
-                                MMC_CAP_8_BIT_DATA |
-                                MMC_CAP_NONREMOVABLE |
-                                MMC_CAP_MMC_HIGHSPEED |
-                                MMC_CAP_ERASE |
-                                MMC_CAP_CMD23,
-        .gpio_cd        = -1,
-        .gpio_wp        = -1,
-#ifdef CONFIG_STE_DMA40
-        .dma_filter     = stedma40_filter,
-        .dma_rx_param   = &mop500_sdi4_dma_cfg_rx,
-        .dma_tx_param   = &mop500_sdi4_dma_cfg_tx,
-#endif
-};
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 32cc0d8d8a0e..7c7b0adca582 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -8,12 +8,7 @@
 #define __BOARD_MOP500_H
 #include <linux/platform_data/asoc-ux500-msp.h>
-#include <linux/amba/mmci.h>
-extern struct mmci_platform_data mop500_sdi0_data;
-extern struct mmci_platform_data mop500_sdi1_data;
-extern struct mmci_platform_data mop500_sdi2_data;
-extern struct mmci_platform_data mop500_sdi4_data;
 extern struct msp_i2s_platform_data msp0_platform_data;
 extern struct msp_i2s_platform_data msp1_platform_data;
 extern struct msp_i2s_platform_data msp2_platform_data;
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index 264f894c0e3d..842ebedbdd1c 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -35,10 +35,16 @@ static int __init ux500_l2x0_unlock(void)
        return 0;
 }
-static int __init ux500_l2x0_init(void)
+static void ux500_l2c310_write_sec(unsigned long val, unsigned reg)
 {
-        u32 aux_val = 0x3e000000;
+        /*
+         * We can't write to secure registers as we are in non-secure
+         * mode, until we have some SMI service available.
+         */
+}
+static int __init ux500_l2x0_init(void)
+{
        if (cpu_is_u8500_family() || cpu_is_ux540_family())
                l2x0_base = __io_address(U8500_L2CC_BASE);
        else
@@ -48,28 +54,12 @@ static int __init ux500_l2x0_init(void)
        /* Unlock before init */
        ux500_l2x0_unlock();
-        /* DBx540's L2 has 128KB way size */
+        outer_cache.write_sec = ux500_l2c310_write_sec;
-        if (cpu_is_ux540_family())
-                /* 128KB way size */
-                aux_val |= (0x4 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
-        else
-                /* 64KB way size */
-                aux_val |= (0x3 << L2X0_AUX_CTRL_WAY_SIZE_SHIFT);
-        /* 64KB way size, 8 way associativity, force WA */
        if (of_have_populated_dt())
-                l2x0_of_init(aux_val, 0xc0000fff);
+                l2x0_of_init(0, ~0);
        else
-                l2x0_init(l2x0_base, aux_val, 0xc0000fff);
+                l2x0_init(l2x0_base, 0, ~0);
-        /*
-         * We can't disable l2 as we are in non secure mode, currently
-         * this seems be called only during kexec path. So let's
-         * override outer.disable with nasty assignment until we have
-         * some SMI service available.
-         */
-        outer_cache.disable = NULL;
-        outer_cache.set_debug = NULL;
        return 0;
 }
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 8820f602fcd2..fa308f07fae5 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -146,10 +146,6 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
        /* Requires call-back bindings. */
        OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
        /* Requires DMA bindings. */
-        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1",  &mop500_sdi1_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2",  &mop500_sdi2_data),
-        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
                       "ux500-msp-i2s.0", &msp0_platform_data),
        OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index f2c89fb8fca9..be83ba25f81b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -310,6 +310,21 @@ static struct platform_device char_lcd_device = {
        .resource       =       char_lcd_resources,
 };
+static struct resource leds_resources[] = {
+        {
+                .start  = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET,
+                .end    = VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET + 4,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device leds_device = {
+        .name           = "versatile-leds",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(leds_resources),
+        .resource       = leds_resources,
+};
 /*
 * Clock handling
 */
@@ -795,6 +810,7 @@ void __init versatile_init(void)
        platform_device_register(&versatile_i2c_device);
        platform_device_register(&smc91x_device);
        platform_device_register(&char_lcd_device);
+        platform_device_register(&leds_device);
        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
                struct amba_device *d = amba_devs[i];
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index 657d52d0391f..90249cfc37b3 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -4,6 +4,7 @@ config ARCH_VEXPRESS
        select ARCH_SUPPORTS_BIG_ENDIAN
        select ARM_AMBA
        select ARM_GIC
+        select ARM_GLOBAL_TIMER
        select ARM_TIMER_SP804
        select COMMON_CLK_VERSATILE
        select HAVE_ARM_SCU if SMP
@@ -18,6 +19,8 @@ config ARCH_VEXPRESS
        select POWER_SUPPLY
        select REGULATOR_FIXED_VOLTAGE if REGULATOR
        select VEXPRESS_CONFIG
+        select VEXPRESS_SYSCFG
+        select MFD_VEXPRESS_SYSREG
        help
          This option enables support for systems using Cortex processor based
          ARM core and logic (FPGA) tiles on the Versatile Express motherboard,
diff --git a/arch/arm/mach-vexpress/core.h b/arch/arm/mach-vexpress/core.h
index bde4374ab6d5..152fad91b3ae 100644
--- a/arch/arm/mach-vexpress/core.h
+++ b/arch/arm/mach-vexpress/core.h
@@ -4,10 +4,9 @@
 /* Tile's peripherals static mappings should start here */
 #define V2T_PERIPH 0xf8200000
-void vexpress_dt_smp_map_io(void);
 bool vexpress_smp_init_ops(void);
 extern struct smp_operations    vexpress_smp_ops;
+extern struct smp_operations    vexpress_smp_dt_ops;
 extern void vexpress_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 6f34497a4245..86150d7a2e7d 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -45,6 +45,23 @@ static void __init ct_ca9x4_map_io(void)
        iotable_init(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
 }
+static void __init ca9x4_l2_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
+        if (l2x0_base) {
+                /* set RAM latencies to 1 cycle for this core tile. */
+                writel(0, l2x0_base + L310_TAG_LATENCY_CTRL);
+                writel(0, l2x0_base + L310_DATA_LATENCY_CTRL);
+                l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
+        } else {
+                pr_err("L2C: unable to map L2 cache controller\n");
+        }
+#endif
+}
 #ifdef CONFIG_HAVE_ARM_TWD
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, A9_MPCORE_TWD, IRQ_LOCALTIMER);
@@ -63,6 +80,7 @@ static void __init ct_ca9x4_init_irq(void)
        gic_init(0, 29, ioremap(A9_MPCORE_GIC_DIST, SZ_4K),
                 ioremap(A9_MPCORE_GIC_CPU, SZ_256));
        ca9x4_twd_init();
+        ca9x4_l2_init();
 }
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -128,6 +146,10 @@ static struct platform_device pmu_device = {
        .resource       = pmu_resources,
 };
+static struct clk_lookup osc1_lookup = {
+        .dev_id         = "ct:clcd",
+};
 static struct platform_device osc1_device = {
        .name           = "vexpress-osc",
        .id             = 1,
@@ -135,30 +157,18 @@ static struct platform_device osc1_device = {
        .resource       = (struct resource []) {
                VEXPRESS_RES_FUNC(0xf, 1),
        },
+        .dev.platform_data = &osc1_lookup,
 };
 static void __init ct_ca9x4_init(void)
 {
        int i;
-#ifdef CONFIG_CACHE_L2X0
-        void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
-        /* set RAM latencies to 1 cycle for this core tile. */
-        writel(0, l2x0_base + L2X0_TAG_LATENCY_CTRL);
-        writel(0, l2x0_base + L2X0_DATA_LATENCY_CTRL);
-        l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
-#endif
        for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
        platform_device_register(&pmu_device);
-        platform_device_register(&osc1_device);
+        vexpress_syscfg_device_register(&osc1_device);
-        WARN_ON(clk_register_clkdev(vexpress_osc_setup(&osc1_device.dev),
-                        NULL, "ct:clcd"));
 }
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/platsmp.c b/arch/arm/mach-vexpress/platsmp.c
index 993c9ae5dc5e..a1f3804fd5a5 100644
--- a/arch/arm/mach-vexpress/platsmp.c
+++ b/arch/arm/mach-vexpress/platsmp.c
@@ -12,8 +12,7 @@
 #include <linux/errno.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/of.h>
+#include <linux/of_address.h>
-#include <linux/of_fdt.h>
 #include <linux/vexpress.h>
 #include <asm/mcpm.h>
@@ -26,154 +25,13 @@
 #include "core.h"
-#if defined(CONFIG_OF)
-static enum {
-        GENERIC_SCU,
-        CORTEX_A9_SCU,
-} vexpress_dt_scu __initdata = GENERIC_SCU;
-static struct map_desc vexpress_dt_cortex_a9_scu_map __initdata = {
-        .virtual        = V2T_PERIPH,
-        /* .pfn set in vexpress_dt_init_cortex_a9_scu() */
-        .length         = SZ_128,
-        .type           = MT_DEVICE,
-};
-static void *vexpress_dt_cortex_a9_scu_base __initdata;
-const static char *vexpress_dt_cortex_a9_match[] __initconst = {
-        "arm,cortex-a5-scu",
-        "arm,cortex-a9-scu",
-        NULL
-};
-static int __init vexpress_dt_find_scu(unsigned long node,
-                const char *uname, int depth, void *data)
-{
-        if (of_flat_dt_match(node, vexpress_dt_cortex_a9_match)) {
-                phys_addr_t phys_addr;
-                __be32 *reg = of_get_flat_dt_prop(node, "reg", NULL);
-                if (WARN_ON(!reg))
-                        return -EINVAL;
-                phys_addr = be32_to_cpup(reg);
-                vexpress_dt_scu = CORTEX_A9_SCU;
-                vexpress_dt_cortex_a9_scu_map.pfn = __phys_to_pfn(phys_addr);
-                iotable_init(&vexpress_dt_cortex_a9_scu_map, 1);
-                vexpress_dt_cortex_a9_scu_base = ioremap(phys_addr, SZ_256);
-                if (WARN_ON(!vexpress_dt_cortex_a9_scu_base))
-                        return -EFAULT;
-        }
-        return 0;
-}
-void __init vexpress_dt_smp_map_io(void)
-{
-        if (initial_boot_params)
-                WARN_ON(of_scan_flat_dt(vexpress_dt_find_scu, NULL));
-}
-static int __init vexpress_dt_cpus_num(unsigned long node, const char *uname,
-                int depth, void *data)
-{
-        static int prev_depth = -1;
-        static int nr_cpus = -1;
-        if (prev_depth > depth && nr_cpus > 0)
-                return nr_cpus;
-        if (nr_cpus < 0 && strcmp(uname, "cpus") == 0)
-                nr_cpus = 0;
-        if (nr_cpus >= 0) {
-                const char *device_type = of_get_flat_dt_prop(node,
-                                "device_type", NULL);
-                if (device_type && strcmp(device_type, "cpu") == 0)
-                        nr_cpus++;
-        }
-        prev_depth = depth;
-        return 0;
-}
-static void __init vexpress_dt_smp_init_cpus(void)
-{
-        int ncores = 0, i;
-        switch (vexpress_dt_scu) {
-        case GENERIC_SCU:
-                ncores = of_scan_flat_dt(vexpress_dt_cpus_num, NULL);
-                break;
-        case CORTEX_A9_SCU:
-                ncores = scu_get_core_count(vexpress_dt_cortex_a9_scu_base);
-                break;
-        default:
-                WARN_ON(1);
-                break;
-        }
-        if (ncores < 2)
-                return;
-        if (ncores > nr_cpu_ids) {
-                pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
-                                ncores, nr_cpu_ids);
-                ncores = nr_cpu_ids;
-        }
-        for (i = 0; i < ncores; ++i)
-                set_cpu_possible(i, true);
-}
-static void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
-{
-        int i;
-        switch (vexpress_dt_scu) {
-        case GENERIC_SCU:
-                for (i = 0; i < max_cpus; i++)
-                        set_cpu_present(i, true);
-                break;
-        case CORTEX_A9_SCU:
-                scu_enable(vexpress_dt_cortex_a9_scu_base);
-                break;
-        default:
-                WARN_ON(1);
-                break;
-        }
-}
-#else
-static void __init vexpress_dt_smp_init_cpus(void)
-{
-        WARN_ON(1);
-}
-void __init vexpress_dt_smp_prepare_cpus(unsigned int max_cpus)
-{
-        WARN_ON(1);
-}
-#endif
 /*
 * Initialise the CPU possible map early - this describes the CPUs
 * which may be present or become present in the system.
 */
 static void __init vexpress_smp_init_cpus(void)
 {
-        if (ct_desc)
+        ct_desc->init_cpu_map();
-                ct_desc->init_cpu_map();
-        else
-                vexpress_dt_smp_init_cpus();
 }
 static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
@@ -182,10 +40,7 @@ static void __init vexpress_smp_prepare_cpus(unsigned int max_cpus)
         * Initialise the present map, which describes the set of CPUs
         * actually populated at the present time.
         */
-        if (ct_desc)
+        ct_desc->smp_enable(max_cpus);
-                ct_desc->smp_enable(max_cpus);
-        else
-                vexpress_dt_smp_prepare_cpus(max_cpus);
        /*
         * Write the address of secondary startup into the
@@ -223,3 +78,39 @@ bool __init vexpress_smp_init_ops(void)
 #endif
        return false;
 }
+#if defined(CONFIG_OF)
+static const struct of_device_id vexpress_smp_dt_scu_match[] __initconst = {
+        { .compatible = "arm,cortex-a5-scu", },
+        { .compatible = "arm,cortex-a9-scu", },
+        {}
+};
+static void __init vexpress_smp_dt_prepare_cpus(unsigned int max_cpus)
+{
+        struct device_node *scu = of_find_matching_node(NULL,
+                        vexpress_smp_dt_scu_match);
+        if (scu)
+                scu_enable(of_iomap(scu, 0));
+        /*
+         * Write the address of secondary startup into the
+         * system-wide flags register. The boot monitor waits
+         * until it receives a soft interrupt, and then the
+         * secondary CPU branches to this address.
+         */
+        vexpress_flags_set(virt_to_phys(versatile_secondary_startup));
+}
+struct smp_operations __initdata vexpress_smp_dt_ops = {
+        .smp_prepare_cpus       = vexpress_smp_dt_prepare_cpus,
+        .smp_secondary_init     = versatile_secondary_init,
+        .smp_boot_secondary     = versatile_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+        .cpu_die                = vexpress_cpu_die,
+#endif
+};
+#endif
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
index 29e7785a54bc..b743a0ae02ce 100644
--- a/arch/arm/mach-vexpress/tc2_pm.c
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -209,7 +209,7 @@ static int tc2_core_in_reset(unsigned int cpu, unsigned int cluster)
 #define POLL_MSEC 10
 #define TIMEOUT_MSEC 1000
-static int tc2_pm_power_down_finish(unsigned int cpu, unsigned int cluster)
+static int tc2_pm_wait_for_powerdown(unsigned int cpu, unsigned int cluster)
 {
        unsigned tries;
@@ -290,7 +290,7 @@ static void tc2_pm_powered_up(void)
 static const struct mcpm_platform_ops tc2_pm_power_ops = {
        .power_up               = tc2_pm_power_up,
        .power_down             = tc2_pm_power_down,
-        .power_down_finish      = tc2_pm_power_down_finish,
+        .wait_for_powerdown     = tc2_pm_wait_for_powerdown,
        .suspend                = tc2_pm_suspend,
        .powered_up             = tc2_pm_powered_up,
 };
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 4f8b8cb17ff5..6ff681a24ba7 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -201,8 +201,9 @@ static struct platform_device v2m_cf_device = {
 static struct mmci_platform_data v2m_mmci_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
-        .gpio_wp        = VEXPRESS_GPIO_MMC_WPROT,
+        .status         = vexpress_get_mci_cardin,
-        .gpio_cd        = VEXPRESS_GPIO_MMC_CARDIN,
+        .gpio_cd        = -1,
+        .gpio_wp        = -1,
 };
 static struct resource v2m_sysreg_resources[] = {
@@ -340,11 +341,6 @@ static void __init v2m_init(void)
        regulator_register_fixed(0, v2m_eth_supplies,
                        ARRAY_SIZE(v2m_eth_supplies));
-        platform_device_register(&v2m_muxfpga_device);
-        platform_device_register(&v2m_shutdown_device);
-        platform_device_register(&v2m_reboot_device);
-        platform_device_register(&v2m_dvimode_device);
        platform_device_register(&v2m_sysreg_device);
        platform_device_register(&v2m_pcie_i2c_device);
        platform_device_register(&v2m_ddc_i2c_device);
@@ -356,6 +352,11 @@ static void __init v2m_init(void)
        for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++)
                amba_device_register(v2m_amba_devs[i], &iomem_resource);
+        vexpress_syscfg_device_register(&v2m_muxfpga_device);
+        vexpress_syscfg_device_register(&v2m_shutdown_device);
+        vexpress_syscfg_device_register(&v2m_reboot_device);
+        vexpress_syscfg_device_register(&v2m_dvimode_device);
        ct_desc->init_tile();
 }
@@ -369,71 +370,9 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
        .init_machine   = v2m_init,
 MACHINE_END
-static struct map_desc v2m_rs1_io_desc __initdata = {
-        .virtual        = V2M_PERIPH,
-        .pfn            = __phys_to_pfn(0x1c000000),
-        .length         = SZ_2M,
-        .type           = MT_DEVICE,
-};
-static int __init v2m_dt_scan_memory_map(unsigned long node, const char *uname,
-                int depth, void *data)
-{
-        const char **map = data;
-        if (strcmp(uname, "motherboard") != 0)
-                return 0;
-        *map = of_get_flat_dt_prop(node, "arm,v2m-memory-map", NULL);
-        return 1;
-}
-void __init v2m_dt_map_io(void)
-{
-        const char *map = NULL;
-        of_scan_flat_dt(v2m_dt_scan_memory_map, &map);
-        if (map && strcmp(map, "rs1") == 0)
-                iotable_init(&v2m_rs1_io_desc, 1);
-        else
-                iotable_init(v2m_io_desc, ARRAY_SIZE(v2m_io_desc));
-#if defined(CONFIG_SMP)
-        vexpress_dt_smp_map_io();
-#endif
-}
-void __init v2m_dt_init_early(void)
-{
-        u32 dt_hbi;
-        vexpress_sysreg_of_early_init();
-        /* Confirm board type against DT property, if available */
-        if (of_property_read_u32(of_allnodes, "arm,hbi", &dt_hbi) == 0) {
-                u32 hbi = vexpress_get_hbi(VEXPRESS_SITE_MASTER);
-                if (WARN_ON(dt_hbi != hbi))
-                        pr_warning("vexpress: DT HBI (%x) is not matching "
-                                        "hardware (%x)!\n", dt_hbi, hbi);
-        }
-        versatile_sched_clock_init(vexpress_get_24mhz_clock_base(), 24000000);
-}
-static const struct of_device_id v2m_dt_bus_match[] __initconst = {
-        { .compatible = "simple-bus", },
-        { .compatible = "arm,amba-bus", },
-        { .compatible = "arm,vexpress,config-bus", },
-        {}
-};
 static void __init v2m_dt_init(void)
 {
-        l2x0_of_init(0x00400000, 0xfe0fffff);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-        of_platform_populate(NULL, v2m_dt_bus_match, NULL, NULL);
 }
 static const char * const v2m_dt_match[] __initconst = {
@@ -443,9 +382,9 @@ static const char * const v2m_dt_match[] __initconst = {
 DT_MACHINE_START(VEXPRESS_DT, "ARM-Versatile Express")
        .dt_compat      = v2m_dt_match,
-        .smp            = smp_ops(vexpress_smp_ops),
+        .l2c_aux_val    = 0x00400000,
+        .l2c_aux_mask   = 0xfe0fffff,
+        .smp            = smp_ops(vexpress_smp_dt_ops),
        .smp_init       = smp_init_ops(vexpress_smp_init_ops),
-        .map_io         = v2m_dt_map_io,
-        .init_early     = v2m_dt_init_early,
        .init_machine   = v2m_dt_init,
 MACHINE_END
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 58c2b844e0a3..573e0db1d0f0 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -1,14 +1,16 @@
 config ARCH_ZYNQ
        bool "Xilinx Zynq ARM Cortex A9 Platform" if ARCH_MULTI_V7
-        select ARM_AMBA
-        select ARM_GIC
        select ARCH_HAS_CPUFREQ
        select ARCH_HAS_OPP
+        select ARCH_SUPPORTS_BIG_ENDIAN
+        select ARM_AMBA
+        select ARM_GIC
+        select ARM_GLOBAL_TIMER if !CPU_FREQ
+        select CADENCE_TTC_TIMER
        select HAVE_ARM_SCU if SMP
        select HAVE_ARM_TWD if SMP
        select ICST
-        select CADENCE_TTC_TIMER
-        select ARM_GLOBAL_TIMER if !CPU_FREQ
        select MFD_SYSCON
+        select SOC_BUS
        help
          Support for Xilinx Zynq ARM Cortex A9 Platform
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 6fcc584c1a11..31a6fa40ba37 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -29,6 +29,8 @@
 #include <linux/memblock.h>
 #include <linux/irqchip.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/slab.h>
+#include <linux/sys_soc.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -37,10 +39,15 @@
 #include <asm/page.h>
 #include <asm/pgtable.h>
 #include <asm/smp_scu.h>
+#include <asm/system_info.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "common.h"
+#define ZYNQ_DEVCFG_MCTRL               0x80
+#define ZYNQ_DEVCFG_PS_VERSION_SHIFT    28
+#define ZYNQ_DEVCFG_PS_VERSION_MASK     0xF
 void __iomem *zynq_scu_base;
 /**
@@ -60,19 +67,76 @@ static struct platform_device zynq_cpuidle_device = {
 };
 /**
+ * zynq_get_revision - Get Zynq silicon revision
+ *
+ * Return: Silicon version or -1 otherwise
+ */
+static int __init zynq_get_revision(void)
+{
+        struct device_node *np;
+        void __iomem *zynq_devcfg_base;
+        u32 revision;
+        np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-devcfg-1.0");
+        if (!np) {
+                pr_err("%s: no devcfg node found\n", __func__);
+                return -1;
+        }
+        zynq_devcfg_base = of_iomap(np, 0);
+        if (!zynq_devcfg_base) {
+                pr_err("%s: Unable to map I/O memory\n", __func__);
+                return -1;
+        }
+        revision = readl(zynq_devcfg_base + ZYNQ_DEVCFG_MCTRL);
+        revision >>= ZYNQ_DEVCFG_PS_VERSION_SHIFT;
+        revision &= ZYNQ_DEVCFG_PS_VERSION_MASK;
+        iounmap(zynq_devcfg_base);
+        return revision;
+}
+/**
 * zynq_init_machine - System specific initialization, intended to be
 *                     called from board specific initialization.
 */
 static void __init zynq_init_machine(void)
 {
        struct platform_device_info devinfo = { .name = "cpufreq-cpu0", };
+        struct soc_device_attribute *soc_dev_attr;
+        struct soc_device *soc_dev;
+        struct device *parent = NULL;
+        soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
+        if (!soc_dev_attr)
+                goto out;
+        system_rev = zynq_get_revision();
+        soc_dev_attr->family = kasprintf(GFP_KERNEL, "Xilinx Zynq");
+        soc_dev_attr->revision = kasprintf(GFP_KERNEL, "0x%x", system_rev);
+        soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "0x%x",
+                                         zynq_slcr_get_device_id());
+        soc_dev = soc_device_register(soc_dev_attr);
+        if (IS_ERR(soc_dev)) {
+                kfree(soc_dev_attr->family);
+                kfree(soc_dev_attr->revision);
+                kfree(soc_dev_attr->soc_id);
+                kfree(soc_dev_attr);
+                goto out;
+        }
+        parent = soc_device_to_device(soc_dev);
+out:
        /*
-         * 64KB way size, 8-way associativity, parity disabled
+         * Finished with the static registrations now; fill in the missing
+         * devices
         */
-        l2x0_of_init(0x02060000, 0xF0F0FFFF);
+        of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
        platform_device_register(&zynq_cpuidle_device);
        platform_device_register_full(&devinfo);
@@ -133,6 +197,9 @@ static const char * const zynq_dt_match[] = {
 };
 DT_MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
+        /* 64KB way size, 8-way associativity, parity disabled */
+        .l2c_aux_val    = 0x02000000,
+        .l2c_aux_mask   = 0xf0ffffff,
        .smp            = smp_ops(zynq_smp_ops),
        .map_io         = zynq_map_io,
        .init_irq       = zynq_irq_init,
diff --git a/arch/arm/mach-zynq/common.h b/arch/arm/mach-zynq/common.h
index b097844d3175..f652f0a884a6 100644
--- a/arch/arm/mach-zynq/common.h
+++ b/arch/arm/mach-zynq/common.h
@@ -24,6 +24,7 @@ extern int zynq_early_slcr_init(void);
 extern void zynq_slcr_system_reset(void);
 extern void zynq_slcr_cpu_stop(int cpu);
 extern void zynq_slcr_cpu_start(int cpu);
+extern u32 zynq_slcr_get_device_id(void);
 #ifdef CONFIG_SMP
 extern void secondary_startup(void);
diff --git a/arch/arm/mach-zynq/headsmp.S b/arch/arm/mach-zynq/headsmp.S
index 57a32869f0aa..dd8c071941e7 100644
--- a/arch/arm/mach-zynq/headsmp.S
+++ b/arch/arm/mach-zynq/headsmp.S
@@ -8,9 +8,12 @@
 */
 #include <linux/linkage.h>
 #include <linux/init.h>
+#include <asm/assembler.h>
 ENTRY(zynq_secondary_trampoline)
-        ldr     r0, [pc]
+ARM_BE8(setend  be)                             @ ensure we are in BE8 mode
+        ldr     r0, zynq_secondary_trampoline_jump
+ARM_BE8(rev     r0, r0)
        bx      r0
 .globl zynq_secondary_trampoline_jump
 zynq_secondary_trampoline_jump:
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index a37d49a6e657..c43a2d16e223 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -26,10 +26,13 @@
 #define SLCR_PS_RST_CTRL_OFFSET         0x200 /* PS Software Reset Control */
 #define SLCR_A9_CPU_RST_CTRL_OFFSET     0x244 /* CPU Software Reset Control */
 #define SLCR_REBOOT_STATUS_OFFSET       0x258 /* PS Reboot Status */
+#define SLCR_PSS_IDCODE                 0x530 /* PS IDCODE */
 #define SLCR_UNLOCK_MAGIC               0xDF0D
 #define SLCR_A9_CPU_CLKSTOP             0x10
 #define SLCR_A9_CPU_RST                 0x1
+#define SLCR_PSS_IDCODE_DEVICE_SHIFT    12
+#define SLCR_PSS_IDCODE_DEVICE_MASK     0x1F
 static void __iomem *zynq_slcr_base;
 static struct regmap *zynq_slcr_regmap;
@@ -83,6 +86,22 @@ static inline int zynq_slcr_unlock(void)
 }
 /**
+ * zynq_slcr_get_device_id - Read device code id
+ *
+ * Return:      Device code id
+ */
+u32 zynq_slcr_get_device_id(void)
+{
+        u32 val;
+        zynq_slcr_read(&val, SLCR_PSS_IDCODE);
+        val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT;
+        val &= SLCR_PSS_IDCODE_DEVICE_MASK;
+        return val;
+}
+/**
 * zynq_slcr_system_reset - Reset the entire system.
 */
 void zynq_slcr_system_reset(void)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 5bf7c3c3b301..eda0dd0ab97b 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -897,6 +897,57 @@ config CACHE_PL310
          This option enables optimisations for the PL310 cache
          controller.
+config PL310_ERRATA_588369
+        bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
+        depends on CACHE_L2X0
+        help
+           The PL310 L2 cache controller implements three types of Clean &
+           Invalidate maintenance operations: by Physical Address
+           (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
+           They are architecturally defined to behave as the execution of a
+           clean operation followed immediately by an invalidate operation,
+           both performing to the same memory location. This functionality
+           is not correctly implemented in PL310 as clean lines are not
+           invalidated as a result of these operations.
+config PL310_ERRATA_727915
+        bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
+        depends on CACHE_L2X0
+        help
+          PL310 implements the Clean & Invalidate by Way L2 cache maintenance
+          operation (offset 0x7FC). This operation runs in background so that
+          PL310 can handle normal accesses while it is in progress. Under very
+          rare circumstances, due to this erratum, write data can be lost when
+          PL310 treats a cacheable write transaction during a Clean &
+          Invalidate by Way operation.
+config PL310_ERRATA_753970
+        bool "PL310 errata: cache sync operation may be faulty"
+        depends on CACHE_PL310
+        help
+          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+          Under some condition the effect of cache sync operation on
+          the store buffer still remains when the operation completes.
+          This means that the store buffer is always asked to drain and
+          this prevents it from merging any further writes. The workaround
+          is to replace the normal offset of cache sync operation (0x730)
+          by another offset targeting an unmapped PL310 register 0x740.
+          This has the same effect as the cache sync operation: store buffer
+          drain and waiting for all buffers empty.
+config PL310_ERRATA_769419
+        bool "PL310 errata: no automatic Store Buffer drain"
+        depends on CACHE_L2X0
+        help
+          On revisions of the PL310 prior to r3p2, the Store Buffer does
+          not automatically drain. This can cause normal, non-cacheable
+          writes to be retained when the memory system is idle, leading
+          to suboptimal I/O performance for drivers using coherent DMA.
+          This option adds a write barrier to the cpu_idle loop so that,
+          on systems with an outer cache, the store buffer is drained
+          explicitly.
 config CACHE_TAUROS2
        bool "Enable the Tauros2 L2 cache controller"
        depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f39ce2f841f..91da64de440f 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -95,7 +95,8 @@ obj-$(CONFIG_CPU_V7M)		+= proc-v7m.o
 AFLAGS_proc-v6.o        :=-Wa,-march=armv6
 AFLAGS_proc-v7.o        :=-Wa,-march=armv7-a
+obj-$(CONFIG_OUTER_CACHE)       += l2c-common.o
 obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
-obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o
+obj-$(CONFIG_CACHE_L2X0)        += cache-l2x0.o l2c-l2x0-resume.o
 obj-$(CONFIG_CACHE_XSC3L2)      += cache-xsc3l2.o
 obj-$(CONFIG_CACHE_TAUROS2)     += cache-tauros2.o
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 924036473b16..b8cb1a2688a0 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -28,6 +28,7 @@
 #include <asm/opcodes.h>
 #include "fault.h"
+#include "mm.h"
 /*
 * 32-bit misaligned trap handler (c) 1998 San Mehat (CCC) -July 1998
@@ -81,6 +82,7 @@ static unsigned long ai_word;
 static unsigned long ai_dword;
 static unsigned long ai_multi;
 static int ai_usermode;
+static unsigned long cr_no_alignment;
 core_param(alignment, ai_usermode, int, 0600);
@@ -91,7 +93,7 @@ core_param(alignment, ai_usermode, int, 0600);
 /* Return true if and only if the ARMv6 unaligned access model is in use. */
 static bool cpu_is_v6_unaligned(void)
 {
-        return cpu_architecture() >= CPU_ARCH_ARMv6 && (cr_alignment & CR_U);
+        return cpu_architecture() >= CPU_ARCH_ARMv6 && get_cr() & CR_U;
 }
 static int safe_usermode(int new_usermode, bool warn)
@@ -949,6 +951,13 @@ do_alignment(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
        return 0;
 }
+static int __init noalign_setup(char *__unused)
+{
+        set_cr(__clear_cr(CR_A));
+        return 1;
+}
+__setup("noalign", noalign_setup);
 /*
 * This needs to be done after sysctl_init, otherwise sys/ will be
 * overwritten.  Actually, this shouldn't be in sys/ at all since
@@ -966,14 +975,12 @@ static int __init alignment_init(void)
                return -ENOMEM;
 #endif
-#ifdef CONFIG_CPU_CP15
        if (cpu_is_v6_unaligned()) {
-                cr_alignment &= ~CR_A;
+                set_cr(__clear_cr(CR_A));
-                cr_no_alignment &= ~CR_A;
-                set_cr(cr_alignment);
                ai_usermode = safe_usermode(ai_usermode, false);
        }
-#endif
+        cr_no_alignment = get_cr() & ~CR_A;
        hook_fault_code(FAULT_CODE_ALIGNMENT, do_alignment, SIGBUS, BUS_ADRALN,
                        "alignment exception");
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
index dc814a548056..e028a7f2ebcc 100644
--- a/arch/arm/mm/cache-feroceon-l2.c
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -350,7 +350,6 @@ void __init feroceon_l2_init(int __l2_wt_override)
        outer_cache.inv_range = feroceon_l2_inv_range;
        outer_cache.clean_range = feroceon_l2_clean_range;
        outer_cache.flush_range = feroceon_l2_flush_range;
-        outer_cache.inv_all = l2_inv_all;
        enable_l2();
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 7abde2ce8973..efc5cabf70e0 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -16,18 +16,33 @@
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
+#include <linux/cpu.h>
 #include <linux/err.h>
 #include <linux/init.h>
+#include <linux/smp.h>
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <asm/cacheflush.h>
+#include <asm/cp15.h>
+#include <asm/cputype.h>
 #include <asm/hardware/cache-l2x0.h>
 #include "cache-tauros3.h"
 #include "cache-aurora-l2.h"
+struct l2c_init_data {
+        const char *type;
+        unsigned way_size_0;
+        unsigned num_lock;
+        void (*of_parse)(const struct device_node *, u32 *, u32 *);
+        void (*enable)(void __iomem *, u32, unsigned);
+        void (*fixup)(void __iomem *, u32, struct outer_cache_fns *);
+        void (*save)(void __iomem *);
+        struct outer_cache_fns outer_cache;
+};
 #define CACHE_LINE_SIZE         32
 static void __iomem *l2x0_base;
@@ -36,96 +51,116 @@ static u32 l2x0_way_mask;	/* Bitmask of active ways */
 static u32 l2x0_size;
 static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
-/* Aurora don't have the cache ID register available, so we have to
- * pass it though the device tree */
-static u32  cache_id_part_number_from_dt;
 struct l2x0_regs l2x0_saved_regs;
-struct l2x0_of_data {
+/*
-        void (*setup)(const struct device_node *, u32 *, u32 *);
+ * Common code for all cache controllers.
-        void (*save)(void);
+ */
-        struct outer_cache_fns outer_cache;
+static inline void l2c_wait_mask(void __iomem *reg, unsigned long mask)
-};
-static bool of_init = false;
-static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
 {
        /* wait for cache operation by line or way to complete */
        while (readl_relaxed(reg) & mask)
                cpu_relax();
 }
-#ifdef CONFIG_CACHE_PL310
+/*
-static inline void cache_wait(void __iomem *reg, unsigned long mask)
+ * By default, we write directly to secure registers.  Platforms must
+ * override this if they are running non-secure.
+ */
+static void l2c_write_sec(unsigned long val, void __iomem *base, unsigned reg)
 {
-        /* cache operations by line are atomic on PL310 */
+        if (val == readl_relaxed(base + reg))
+                return;
+        if (outer_cache.write_sec)
+                outer_cache.write_sec(val, reg);
+        else
+                writel_relaxed(val, base + reg);
 }
-#else
-#define cache_wait      cache_wait_way
-#endif
-static inline void cache_sync(void)
+/*
+ * This should only be called when we have a requirement that the
+ * register be written due to a work-around, as platforms running
+ * in non-secure mode may not be able to access this register.
+ */
+static inline void l2c_set_debug(void __iomem *base, unsigned long val)
 {
-        void __iomem *base = l2x0_base;
+        l2c_write_sec(val, base, L2X0_DEBUG_CTRL);
-        writel_relaxed(0, base + sync_reg_offset);
-        cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
-static inline void l2x0_clean_line(unsigned long addr)
+static void __l2c_op_way(void __iomem *reg)
 {
-        void __iomem *base = l2x0_base;
+        writel_relaxed(l2x0_way_mask, reg);
-        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        l2c_wait_mask(reg, l2x0_way_mask);
-        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
 }
-static inline void l2x0_inv_line(unsigned long addr)
+static inline void l2c_unlock(void __iomem *base, unsigned num)
 {
-        void __iomem *base = l2x0_base;
+        unsigned i;
-        cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
+        for (i = 0; i < num; i++) {
+                writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_D_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+                writel_relaxed(0, base + L2X0_LOCKDOWN_WAY_I_BASE +
+                               i * L2X0_LOCKDOWN_STRIDE);
+        }
 }
-#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+/*
-static inline void debug_writel(unsigned long val)
+ * Enable the L2 cache controller.  This function must only be
+ * called when the cache controller is known to be disabled.
+ */
+static void l2c_enable(void __iomem *base, u32 aux, unsigned num_lock)
 {
-        if (outer_cache.set_debug)
+        unsigned long flags;
-                outer_cache.set_debug(val);
+        l2c_write_sec(aux, base, L2X0_AUX_CTRL);
+        l2c_unlock(base, num_lock);
+        local_irq_save(flags);
+        __l2c_op_way(base + L2X0_INV_WAY);
+        writel_relaxed(0, base + sync_reg_offset);
+        l2c_wait_mask(base + sync_reg_offset, 1);
+        local_irq_restore(flags);
+        l2c_write_sec(L2X0_CTRL_EN, base, L2X0_CTRL);
 }
-static void pl310_set_debug(unsigned long val)
+static void l2c_disable(void)
 {
-        writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
+        void __iomem *base = l2x0_base;
+        outer_cache.flush_all();
+        l2c_write_sec(0, base, L2X0_CTRL);
+        dsb(st);
 }
-#else
-/* Optimised out for non-errata case */
+#ifdef CONFIG_CACHE_PL310
-static inline void debug_writel(unsigned long val)
+static inline void cache_wait(void __iomem *reg, unsigned long mask)
 {
+        /* cache operations by line are atomic on PL310 */
 }
+#else
-#define pl310_set_debug NULL
+#define cache_wait      l2c_wait_mask
 #endif
-#ifdef CONFIG_PL310_ERRATA_588369
+static inline void cache_sync(void)
-static inline void l2x0_flush_line(unsigned long addr)
 {
        void __iomem *base = l2x0_base;
-        /* Clean by PA followed by Invalidate by PA */
+        writel_relaxed(0, base + sync_reg_offset);
-        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
+        cache_wait(base + L2X0_CACHE_SYNC, 1);
-        writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
-        cache_wait(base + L2X0_INV_LINE_PA, 1);
-        writel_relaxed(addr, base + L2X0_INV_LINE_PA);
 }
-#else
-static inline void l2x0_flush_line(unsigned long addr)
+#if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static inline void debug_writel(unsigned long val)
+{
+        l2c_set_debug(l2x0_base, val);
+}
+#else
+/* Optimised out for non-errata case */
+static inline void debug_writel(unsigned long val)
 {
-        void __iomem *base = l2x0_base;
-        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
-        writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
 }
 #endif
@@ -141,8 +176,7 @@ static void l2x0_cache_sync(void)
 static void __l2x0_flush_all(void)
 {
        debug_writel(0x03);
-        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
+        __l2c_op_way(l2x0_base + L2X0_CLEAN_INV_WAY);
-        cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
        cache_sync();
        debug_writel(0x00);
 }
@@ -157,275 +191,883 @@ static void l2x0_flush_all(void)
        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_clean_all(void)
+static void l2x0_disable(void)
 {
        unsigned long flags;
-        /* clean all ways */
        raw_spin_lock_irqsave(&l2x0_lock, flags);
-        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
+        __l2x0_flush_all();
-        cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
+        l2c_write_sec(0, l2x0_base, L2X0_CTRL);
-        cache_sync();
+        dsb(st);
        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_inv_all(void)
+static void l2c_save(void __iomem *base)
 {
-        unsigned long flags;
+        l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
-        /* invalidate all ways */
+/*
-        raw_spin_lock_irqsave(&l2x0_lock, flags);
+ * L2C-210 specific code.
-        /* Invalidating when L2 is enabled is a nono */
+ *
-        BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
+ * The L2C-2x0 PA, set/way and sync operations are atomic, but we must
-        writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
+ * ensure that no background operation is running.  The way operations
-        cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
+ * are all background tasks.
-        cache_sync();
+ *
-        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+ * While a background operation is in progress, any new operation is
+ * ignored (unspecified whether this causes an error.)  Thankfully, not
+ * used on SMP.
+ *
+ * Never has a different sync register other than L2X0_CACHE_SYNC, but
+ * we use sync_reg_offset here so we can share some of this with L2C-310.
+ */
+static void __l2c210_cache_sync(void __iomem *base)
+{
+        writel_relaxed(0, base + sync_reg_offset);
 }
-static void l2x0_inv_range(unsigned long start, unsigned long end)
+static void __l2c210_op_pa_range(void __iomem *reg, unsigned long start,
+        unsigned long end)
+{
+        while (start < end) {
+                writel_relaxed(start, reg);
+                start += CACHE_LINE_SIZE;
+        }
+}
+static void l2c210_inv_range(unsigned long start, unsigned long end)
 {
        void __iomem *base = l2x0_base;
-        unsigned long flags;
-        raw_spin_lock_irqsave(&l2x0_lock, flags);
        if (start & (CACHE_LINE_SIZE - 1)) {
                start &= ~(CACHE_LINE_SIZE - 1);
-                debug_writel(0x03);
+                writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
-                l2x0_flush_line(start);
-                debug_writel(0x00);
                start += CACHE_LINE_SIZE;
        }
        if (end & (CACHE_LINE_SIZE - 1)) {
                end &= ~(CACHE_LINE_SIZE - 1);
-                debug_writel(0x03);
+                writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
-                l2x0_flush_line(end);
-                debug_writel(0x00);
        }
+        __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
+        __l2c210_cache_sync(base);
+}
+static void l2c210_clean_range(unsigned long start, unsigned long end)
+{
+        void __iomem *base = l2x0_base;
+        start &= ~(CACHE_LINE_SIZE - 1);
+        __l2c210_op_pa_range(base + L2X0_CLEAN_LINE_PA, start, end);
+        __l2c210_cache_sync(base);
+}
+static void l2c210_flush_range(unsigned long start, unsigned long end)
+{
+        void __iomem *base = l2x0_base;
+        start &= ~(CACHE_LINE_SIZE - 1);
+        __l2c210_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA, start, end);
+        __l2c210_cache_sync(base);
+}
+static void l2c210_flush_all(void)
+{
+        void __iomem *base = l2x0_base;
+        BUG_ON(!irqs_disabled());
+        __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
+        __l2c210_cache_sync(base);
+}
+static void l2c210_sync(void)
+{
+        __l2c210_cache_sync(l2x0_base);
+}
+static void l2c210_resume(void)
+{
+        void __iomem *base = l2x0_base;
+        if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN))
+                l2c_enable(base, l2x0_saved_regs.aux_ctrl, 1);
+}
+static const struct l2c_init_data l2c210_data __initconst = {
+        .type = "L2C-210",
+        .way_size_0 = SZ_8K,
+        .num_lock = 1,
+        .enable = l2c_enable,
+        .save = l2c_save,
+        .outer_cache = {
+                .inv_range = l2c210_inv_range,
+                .clean_range = l2c210_clean_range,
+                .flush_range = l2c210_flush_range,
+                .flush_all = l2c210_flush_all,
+                .disable = l2c_disable,
+                .sync = l2c210_sync,
+                .resume = l2c210_resume,
+        },
+};
+/*
+ * L2C-220 specific code.
+ *
+ * All operations are background operations: they have to be waited for.
+ * Conflicting requests generate a slave error (which will cause an
+ * imprecise abort.)  Never uses sync_reg_offset, so we hard-code the
+ * sync register here.
+ *
+ * However, we can re-use the l2c210_resume call.
+ */
+static inline void __l2c220_cache_sync(void __iomem *base)
+{
+        writel_relaxed(0, base + L2X0_CACHE_SYNC);
+        l2c_wait_mask(base + L2X0_CACHE_SYNC, 1);
+}
+static void l2c220_op_way(void __iomem *base, unsigned reg)
+{
+        unsigned long flags;
+        raw_spin_lock_irqsave(&l2x0_lock, flags);
+        __l2c_op_way(base + reg);
+        __l2c220_cache_sync(base);
+        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+static unsigned long l2c220_op_pa_range(void __iomem *reg, unsigned long start,
+        unsigned long end, unsigned long flags)
+{
+        raw_spinlock_t *lock = &l2x0_lock;
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
                while (start < blk_end) {
-                        l2x0_inv_line(start);
+                        l2c_wait_mask(reg, 1);
+                        writel_relaxed(start, reg);
                        start += CACHE_LINE_SIZE;
                }
                if (blk_end < end) {
-                        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                        raw_spin_unlock_irqrestore(lock, flags);
-                        raw_spin_lock_irqsave(&l2x0_lock, flags);
+                        raw_spin_lock_irqsave(lock, flags);
                }
        }
-        cache_wait(base + L2X0_INV_LINE_PA, 1);
-        cache_sync();
+        return flags;
-        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_clean_range(unsigned long start, unsigned long end)
+static void l2c220_inv_range(unsigned long start, unsigned long end)
 {
        void __iomem *base = l2x0_base;
        unsigned long flags;
-        if ((end - start) >= l2x0_size) {
-                l2x0_clean_all();
-                return;
-        }
        raw_spin_lock_irqsave(&l2x0_lock, flags);
-        start &= ~(CACHE_LINE_SIZE - 1);
+        if ((start | end) & (CACHE_LINE_SIZE - 1)) {
-        while (start < end) {
+                if (start & (CACHE_LINE_SIZE - 1)) {
-                unsigned long blk_end = start + min(end - start, 4096UL);
+                        start &= ~(CACHE_LINE_SIZE - 1);
+                        writel_relaxed(start, base + L2X0_CLEAN_INV_LINE_PA);
-                while (start < blk_end) {
-                        l2x0_clean_line(start);
                        start += CACHE_LINE_SIZE;
                }
-                if (blk_end < end) {
+                if (end & (CACHE_LINE_SIZE - 1)) {
-                        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                        end &= ~(CACHE_LINE_SIZE - 1);
-                        raw_spin_lock_irqsave(&l2x0_lock, flags);
+                        l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
+                        writel_relaxed(end, base + L2X0_CLEAN_INV_LINE_PA);
                }
        }
-        cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
-        cache_sync();
+        flags = l2c220_op_pa_range(base + L2X0_INV_LINE_PA,
+                                   start, end, flags);
+        l2c_wait_mask(base + L2X0_INV_LINE_PA, 1);
+        __l2c220_cache_sync(base);
        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_flush_range(unsigned long start, unsigned long end)
+static void l2c220_clean_range(unsigned long start, unsigned long end)
 {
        void __iomem *base = l2x0_base;
        unsigned long flags;
+        start &= ~(CACHE_LINE_SIZE - 1);
        if ((end - start) >= l2x0_size) {
-                l2x0_flush_all();
+                l2c220_op_way(base, L2X0_CLEAN_WAY);
                return;
        }
        raw_spin_lock_irqsave(&l2x0_lock, flags);
+        flags = l2c220_op_pa_range(base + L2X0_CLEAN_LINE_PA,
+                                   start, end, flags);
+        l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        __l2c220_cache_sync(base);
+        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+static void l2c220_flush_range(unsigned long start, unsigned long end)
+{
+        void __iomem *base = l2x0_base;
+        unsigned long flags;
        start &= ~(CACHE_LINE_SIZE - 1);
+        if ((end - start) >= l2x0_size) {
+                l2c220_op_way(base, L2X0_CLEAN_INV_WAY);
+                return;
+        }
+        raw_spin_lock_irqsave(&l2x0_lock, flags);
+        flags = l2c220_op_pa_range(base + L2X0_CLEAN_INV_LINE_PA,
+                                   start, end, flags);
+        l2c_wait_mask(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        __l2c220_cache_sync(base);
+        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+static void l2c220_flush_all(void)
+{
+        l2c220_op_way(l2x0_base, L2X0_CLEAN_INV_WAY);
+}
+static void l2c220_sync(void)
+{
+        unsigned long flags;
+        raw_spin_lock_irqsave(&l2x0_lock, flags);
+        __l2c220_cache_sync(l2x0_base);
+        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+}
+static void l2c220_enable(void __iomem *base, u32 aux, unsigned num_lock)
+{
+        /*
+         * Always enable non-secure access to the lockdown registers -
+         * we write to them as part of the L2C enable sequence so they
+         * need to be accessible.
+         */
+        aux |= L220_AUX_CTRL_NS_LOCKDOWN;
+        l2c_enable(base, aux, num_lock);
+}
+static const struct l2c_init_data l2c220_data = {
+        .type = "L2C-220",
+        .way_size_0 = SZ_8K,
+        .num_lock = 1,
+        .enable = l2c220_enable,
+        .save = l2c_save,
+        .outer_cache = {
+                .inv_range = l2c220_inv_range,
+                .clean_range = l2c220_clean_range,
+                .flush_range = l2c220_flush_range,
+                .flush_all = l2c220_flush_all,
+                .disable = l2c_disable,
+                .sync = l2c220_sync,
+                .resume = l2c210_resume,
+        },
+};
+/*
+ * L2C-310 specific code.
+ *
+ * Very similar to L2C-210, the PA, set/way and sync operations are atomic,
+ * and the way operations are all background tasks.  However, issuing an
+ * operation while a background operation is in progress results in a
+ * SLVERR response.  We can reuse:
+ *
+ *  __l2c210_cache_sync (using sync_reg_offset)
+ *  l2c210_sync
+ *  l2c210_inv_range (if 588369 is not applicable)
+ *  l2c210_clean_range
+ *  l2c210_flush_range (if 588369 is not applicable)
+ *  l2c210_flush_all (if 727915 is not applicable)
+ *
+ * Errata:
+ * 588369: PL310 R0P0->R1P0, fixed R2P0.
+ *      Affects: all clean+invalidate operations
+ *      clean and invalidate skips the invalidate step, so we need to issue
+ *      separate operations.  We also require the above debug workaround
+ *      enclosing this code fragment on affected parts.  On unaffected parts,
+ *      we must not use this workaround without the debug register writes
+ *      to avoid exposing a problem similar to 727915.
+ *
+ * 727915: PL310 R2P0->R3P0, fixed R3P1.
+ *      Affects: clean+invalidate by way
+ *      clean and invalidate by way runs in the background, and a store can
+ *      hit the line between the clean operation and invalidate operation,
+ *      resulting in the store being lost.
+ *
+ * 752271: PL310 R3P0->R3P1-50REL0, fixed R3P2.
+ *      Affects: 8x64-bit (double fill) line fetches
+ *      double fill line fetches can fail to cause dirty data to be evicted
+ *      from the cache before the new data overwrites the second line.
+ *
+ * 753970: PL310 R3P0, fixed R3P1.
+ *      Affects: sync
+ *      prevents merging writes after the sync operation, until another L2C
+ *      operation is performed (or a number of other conditions.)
+ *
+ * 769419: PL310 R0P0->R3P1, fixed R3P2.
+ *      Affects: store buffer
+ *      store buffer is not automatically drained.
+ */
+static void l2c310_inv_range_erratum(unsigned long start, unsigned long end)
+{
+        void __iomem *base = l2x0_base;
+        if ((start | end) & (CACHE_LINE_SIZE - 1)) {
+                unsigned long flags;
+                /* Erratum 588369 for both clean+invalidate operations */
+                raw_spin_lock_irqsave(&l2x0_lock, flags);
+                l2c_set_debug(base, 0x03);
+                if (start & (CACHE_LINE_SIZE - 1)) {
+                        start &= ~(CACHE_LINE_SIZE - 1);
+                        writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
+                        writel_relaxed(start, base + L2X0_INV_LINE_PA);
+                        start += CACHE_LINE_SIZE;
+                }
+                if (end & (CACHE_LINE_SIZE - 1)) {
+                        end &= ~(CACHE_LINE_SIZE - 1);
+                        writel_relaxed(end, base + L2X0_CLEAN_LINE_PA);
+                        writel_relaxed(end, base + L2X0_INV_LINE_PA);
+                }
+                l2c_set_debug(base, 0x00);
+                raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+        }
+        __l2c210_op_pa_range(base + L2X0_INV_LINE_PA, start, end);
+        __l2c210_cache_sync(base);
+}
+static void l2c310_flush_range_erratum(unsigned long start, unsigned long end)
+{
+        raw_spinlock_t *lock = &l2x0_lock;
+        unsigned long flags;
+        void __iomem *base = l2x0_base;
+        raw_spin_lock_irqsave(lock, flags);
        while (start < end) {
                unsigned long blk_end = start + min(end - start, 4096UL);
-                debug_writel(0x03);
+                l2c_set_debug(base, 0x03);
                while (start < blk_end) {
-                        l2x0_flush_line(start);
+                        writel_relaxed(start, base + L2X0_CLEAN_LINE_PA);
+                        writel_relaxed(start, base + L2X0_INV_LINE_PA);
                        start += CACHE_LINE_SIZE;
                }
-                debug_writel(0x00);
+                l2c_set_debug(base, 0x00);
                if (blk_end < end) {
-                        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
+                        raw_spin_unlock_irqrestore(lock, flags);
-                        raw_spin_lock_irqsave(&l2x0_lock, flags);
+                        raw_spin_lock_irqsave(lock, flags);
                }
        }
-        cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
+        raw_spin_unlock_irqrestore(lock, flags);
-        cache_sync();
+        __l2c210_cache_sync(base);
-        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_disable(void)
+static void l2c310_flush_all_erratum(void)
 {
+        void __iomem *base = l2x0_base;
        unsigned long flags;
        raw_spin_lock_irqsave(&l2x0_lock, flags);
-        __l2x0_flush_all();
+        l2c_set_debug(base, 0x03);
-        writel_relaxed(0, l2x0_base + L2X0_CTRL);
+        __l2c_op_way(base + L2X0_CLEAN_INV_WAY);
-        dsb(st);
+        l2c_set_debug(base, 0x00);
+        __l2c210_cache_sync(base);
        raw_spin_unlock_irqrestore(&l2x0_lock, flags);
 }
-static void l2x0_unlock(u32 cache_id)
+static void __init l2c310_save(void __iomem *base)
 {
-        int lockregs;
+        unsigned revision;
-        int i;
-        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+        l2c_save(base);
-        case L2X0_CACHE_ID_PART_L310:
-                lockregs = 8;
+        l2x0_saved_regs.tag_latency = readl_relaxed(base +
-                break;
+                L310_TAG_LATENCY_CTRL);
-        case AURORA_CACHE_ID:
+        l2x0_saved_regs.data_latency = readl_relaxed(base +
-                lockregs = 4;
+                L310_DATA_LATENCY_CTRL);
+        l2x0_saved_regs.filter_end = readl_relaxed(base +
+                L310_ADDR_FILTER_END);
+        l2x0_saved_regs.filter_start = readl_relaxed(base +
+                L310_ADDR_FILTER_START);
+        revision = readl_relaxed(base + L2X0_CACHE_ID) &
+                        L2X0_CACHE_ID_RTL_MASK;
+        /* From r2p0, there is Prefetch offset/control register */
+        if (revision >= L310_CACHE_ID_RTL_R2P0)
+                l2x0_saved_regs.prefetch_ctrl = readl_relaxed(base +
+                                                        L310_PREFETCH_CTRL);
+        /* From r3p0, there is Power control register */
+        if (revision >= L310_CACHE_ID_RTL_R3P0)
+                l2x0_saved_regs.pwr_ctrl = readl_relaxed(base +
+                                                        L310_POWER_CTRL);
+}
+static void l2c310_resume(void)
+{
+        void __iomem *base = l2x0_base;
+        if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+                unsigned revision;
+                /* restore pl310 setup */
+                writel_relaxed(l2x0_saved_regs.tag_latency,
+                               base + L310_TAG_LATENCY_CTRL);
+                writel_relaxed(l2x0_saved_regs.data_latency,
+                               base + L310_DATA_LATENCY_CTRL);
+                writel_relaxed(l2x0_saved_regs.filter_end,
+                               base + L310_ADDR_FILTER_END);
+                writel_relaxed(l2x0_saved_regs.filter_start,
+                               base + L310_ADDR_FILTER_START);
+                revision = readl_relaxed(base + L2X0_CACHE_ID) &
+                                L2X0_CACHE_ID_RTL_MASK;
+                if (revision >= L310_CACHE_ID_RTL_R2P0)
+                        l2c_write_sec(l2x0_saved_regs.prefetch_ctrl, base,
+                                      L310_PREFETCH_CTRL);
+                if (revision >= L310_CACHE_ID_RTL_R3P0)
+                        l2c_write_sec(l2x0_saved_regs.pwr_ctrl, base,
+                                      L310_POWER_CTRL);
+                l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
+                /* Re-enable full-line-of-zeros for Cortex-A9 */
+                if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
+                        set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
+        }
+}
+static int l2c310_cpu_enable_flz(struct notifier_block *nb, unsigned long act, void *data)
+{
+        switch (act & ~CPU_TASKS_FROZEN) {
+        case CPU_STARTING:
+                set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
                break;
-        default:
+        case CPU_DYING:
-                /* L210 and unknown types */
+                set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
-                lockregs = 1;
                break;
        }
+        return NOTIFY_OK;
+}
-        for (i = 0; i < lockregs; i++) {
+static void __init l2c310_enable(void __iomem *base, u32 aux, unsigned num_lock)
-                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
+{
-                               i * L2X0_LOCKDOWN_STRIDE);
+        unsigned rev = readl_relaxed(base + L2X0_CACHE_ID) & L2X0_CACHE_ID_PART_MASK;
-                writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
+        bool cortex_a9 = read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A9;
-                               i * L2X0_LOCKDOWN_STRIDE);
+        if (rev >= L310_CACHE_ID_RTL_R2P0) {
+                if (cortex_a9) {
+                        aux |= L310_AUX_CTRL_EARLY_BRESP;
+                        pr_info("L2C-310 enabling early BRESP for Cortex-A9\n");
+                } else if (aux & L310_AUX_CTRL_EARLY_BRESP) {
+                        pr_warn("L2C-310 early BRESP only supported with Cortex-A9\n");
+                        aux &= ~L310_AUX_CTRL_EARLY_BRESP;
+                }
+        }
+        if (cortex_a9) {
+                u32 aux_cur = readl_relaxed(base + L2X0_AUX_CTRL);
+                u32 acr = get_auxcr();
+                pr_debug("Cortex-A9 ACR=0x%08x\n", acr);
+                if (acr & BIT(3) && !(aux_cur & L310_AUX_CTRL_FULL_LINE_ZERO))
+                        pr_err("L2C-310: full line of zeros enabled in Cortex-A9 but not L2C-310 - invalid\n");
+                if (aux & L310_AUX_CTRL_FULL_LINE_ZERO && !(acr & BIT(3)))
+                        pr_err("L2C-310: enabling full line of zeros but not enabled in Cortex-A9\n");
+                if (!(aux & L310_AUX_CTRL_FULL_LINE_ZERO) && !outer_cache.write_sec) {
+                        aux |= L310_AUX_CTRL_FULL_LINE_ZERO;
+                        pr_info("L2C-310 full line of zeros enabled for Cortex-A9\n");
+                }
+        } else if (aux & (L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP)) {
+                pr_err("L2C-310: disabling Cortex-A9 specific feature bits\n");
+                aux &= ~(L310_AUX_CTRL_FULL_LINE_ZERO | L310_AUX_CTRL_EARLY_BRESP);
+        }
+        if (aux & (L310_AUX_CTRL_DATA_PREFETCH | L310_AUX_CTRL_INSTR_PREFETCH)) {
+                u32 prefetch = readl_relaxed(base + L310_PREFETCH_CTRL);
+                pr_info("L2C-310 %s%s prefetch enabled, offset %u lines\n",
+                        aux & L310_AUX_CTRL_INSTR_PREFETCH ? "I" : "",
+                        aux & L310_AUX_CTRL_DATA_PREFETCH ? "D" : "",
+                        1 + (prefetch & L310_PREFETCH_CTRL_OFFSET_MASK));
+        }
+        /* r3p0 or later has power control register */
+        if (rev >= L310_CACHE_ID_RTL_R3P0) {
+                u32 power_ctrl;
+                l2c_write_sec(L310_DYNAMIC_CLK_GATING_EN | L310_STNDBY_MODE_EN,
+                              base, L310_POWER_CTRL);
+                power_ctrl = readl_relaxed(base + L310_POWER_CTRL);
+                pr_info("L2C-310 dynamic clock gating %sabled, standby mode %sabled\n",
+                        power_ctrl & L310_DYNAMIC_CLK_GATING_EN ? "en" : "dis",
+                        power_ctrl & L310_STNDBY_MODE_EN ? "en" : "dis");
+        }
+        /*
+         * Always enable non-secure access to the lockdown registers -
+         * we write to them as part of the L2C enable sequence so they
+         * need to be accessible.
+         */
+        aux |= L310_AUX_CTRL_NS_LOCKDOWN;
+        l2c_enable(base, aux, num_lock);
+        if (aux & L310_AUX_CTRL_FULL_LINE_ZERO) {
+                set_auxcr(get_auxcr() | BIT(3) | BIT(2) | BIT(1));
+                cpu_notifier(l2c310_cpu_enable_flz, 0);
        }
 }
-void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
+static void __init l2c310_fixup(void __iomem *base, u32 cache_id,
+        struct outer_cache_fns *fns)
 {
-        u32 aux;
+        unsigned revision = cache_id & L2X0_CACHE_ID_RTL_MASK;
-        u32 cache_id;
+        const char *errata[8];
-        u32 way_size = 0;
+        unsigned n = 0;
-        int ways;
-        int way_size_shift = L2X0_WAY_SIZE_SHIFT;
+        if (IS_ENABLED(CONFIG_PL310_ERRATA_588369) &&
-        const char *type;
+            revision < L310_CACHE_ID_RTL_R2P0 &&
+            /* For bcm compatibility */
+            fns->inv_range == l2c210_inv_range) {
+                fns->inv_range = l2c310_inv_range_erratum;
+                fns->flush_range = l2c310_flush_range_erratum;
+                errata[n++] = "588369";
+        }
-        l2x0_base = base;
+        if (IS_ENABLED(CONFIG_PL310_ERRATA_727915) &&
-        if (cache_id_part_number_from_dt)
+            revision >= L310_CACHE_ID_RTL_R2P0 &&
-                cache_id = cache_id_part_number_from_dt;
+            revision < L310_CACHE_ID_RTL_R3P1) {
-        else
+                fns->flush_all = l2c310_flush_all_erratum;
-                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
+                errata[n++] = "727915";
-        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+        }
+        if (revision >= L310_CACHE_ID_RTL_R3P0 &&
+            revision < L310_CACHE_ID_RTL_R3P2) {
+                u32 val = readl_relaxed(base + L310_PREFETCH_CTRL);
+                /* I don't think bit23 is required here... but iMX6 does so */
+                if (val & (BIT(30) | BIT(23))) {
+                        val &= ~(BIT(30) | BIT(23));
+                        l2c_write_sec(val, base, L310_PREFETCH_CTRL);
+                        errata[n++] = "752271";
+                }
+        }
+        if (IS_ENABLED(CONFIG_PL310_ERRATA_753970) &&
+            revision == L310_CACHE_ID_RTL_R3P0) {
+                sync_reg_offset = L2X0_DUMMY_REG;
+                errata[n++] = "753970";
+        }
+        if (IS_ENABLED(CONFIG_PL310_ERRATA_769419))
+                errata[n++] = "769419";
+        if (n) {
+                unsigned i;
+                pr_info("L2C-310 errat%s", n > 1 ? "a" : "um");
+                for (i = 0; i < n; i++)
+                        pr_cont(" %s", errata[i]);
+                pr_cont(" enabled\n");
+        }
+}
+static void l2c310_disable(void)
+{
+        /*
+         * If full-line-of-zeros is enabled, we must first disable it in the
+         * Cortex-A9 auxiliary control register before disabling the L2 cache.
+         */
+        if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_FULL_LINE_ZERO)
+                set_auxcr(get_auxcr() & ~(BIT(3) | BIT(2) | BIT(1)));
+        l2c_disable();
+}
+static const struct l2c_init_data l2c310_init_fns __initconst = {
+        .type = "L2C-310",
+        .way_size_0 = SZ_8K,
+        .num_lock = 8,
+        .enable = l2c310_enable,
+        .fixup = l2c310_fixup,
+        .save = l2c310_save,
+        .outer_cache = {
+                .inv_range = l2c210_inv_range,
+                .clean_range = l2c210_clean_range,
+                .flush_range = l2c210_flush_range,
+                .flush_all = l2c210_flush_all,
+                .disable = l2c310_disable,
+                .sync = l2c210_sync,
+                .resume = l2c310_resume,
+        },
+};
+static void __init __l2c_init(const struct l2c_init_data *data,
+        u32 aux_val, u32 aux_mask, u32 cache_id)
+{
+        struct outer_cache_fns fns;
+        unsigned way_size_bits, ways;
+        u32 aux, old_aux;
+        /*
+         * Sanity check the aux values.  aux_mask is the bits we preserve
+         * from reading the hardware register, and aux_val is the bits we
+         * set.
+         */
+        if (aux_val & aux_mask)
+                pr_alert("L2C: platform provided aux values permit register corruption.\n");
+        old_aux = aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
        aux &= aux_mask;
        aux |= aux_val;
+        if (old_aux != aux)
+                pr_warn("L2C: DT/platform modifies aux control register: 0x%08x -> 0x%08x\n",
+                        old_aux, aux);
        /* Determine the number of ways */
        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
        case L2X0_CACHE_ID_PART_L310:
+                if ((aux_val | ~aux_mask) & (L2C_AUX_CTRL_WAY_SIZE_MASK | L310_AUX_CTRL_ASSOCIATIVITY_16))
+                        pr_warn("L2C: DT/platform tries to modify or specify cache size\n");
                if (aux & (1 << 16))
                        ways = 16;
                else
                        ways = 8;
-                type = "L310";
-#ifdef CONFIG_PL310_ERRATA_753970
-                /* Unmapped register. */
-                sync_reg_offset = L2X0_DUMMY_REG;
-#endif
-                if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
-                        outer_cache.set_debug = pl310_set_debug;
                break;
        case L2X0_CACHE_ID_PART_L210:
+        case L2X0_CACHE_ID_PART_L220:
                ways = (aux >> 13) & 0xf;
-                type = "L210";
                break;
        case AURORA_CACHE_ID:
-                sync_reg_offset = AURORA_SYNC_REG;
                ways = (aux >> 13) & 0xf;
                ways = 2 << ((ways + 1) >> 2);
-                way_size_shift = AURORA_WAY_SIZE_SHIFT;
-                type = "Aurora";
                break;
        default:
                /* Assume unknown chips have 8 ways */
                ways = 8;
-                type = "L2x0 series";
                break;
        }
        l2x0_way_mask = (1 << ways) - 1;
        /*
-         * L2 cache Size =  Way size * Number of ways
+         * way_size_0 is the size that a way_size value of zero would be
+         * given the calculation: way_size = way_size_0 << way_size_bits.
+         * So, if way_size_bits=0 is reserved, but way_size_bits=1 is 16k,
+         * then way_size_0 would be 8k.
+         *
+         * L2 cache size = number of ways * way size.
         */
-        way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
+        way_size_bits = (aux & L2C_AUX_CTRL_WAY_SIZE_MASK) >>
-        way_size = 1 << (way_size + way_size_shift);
+                        L2C_AUX_CTRL_WAY_SIZE_SHIFT;
+        l2x0_size = ways * (data->way_size_0 << way_size_bits);
-        l2x0_size = ways * way_size * SZ_1K;
+        fns = data->outer_cache;
+        fns.write_sec = outer_cache.write_sec;
+        if (data->fixup)
+                data->fixup(l2x0_base, cache_id, &fns);
        /*
-         * Check if l2x0 controller is already enabled.
+         * Check if l2x0 controller is already enabled.  If we are booting
-         * If you are booting from non-secure mode
+         * in non-secure mode accessing the below registers will fault.
-         * accessing the below registers will fault.
         */
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
-                /* Make sure that I&D is not locked down when starting */
+                data->enable(l2x0_base, aux, data->num_lock);
-                l2x0_unlock(cache_id);
-                /* l2x0 controller is disabled */
+        outer_cache = fns;
-                writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
-                l2x0_inv_all();
+        /*
+         * It is strange to save the register state before initialisation,
-                /* enable L2X0 */
+         * but hey, this is what the DT implementations decided to do.
-                writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
+         */
-        }
+        if (data->save)
+                data->save(l2x0_base);
        /* Re-read it in case some bits are reserved. */
        aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
-        /* Save the value for resuming. */
+        pr_info("%s cache controller enabled, %d ways, %d kB\n",
-        l2x0_saved_regs.aux_ctrl = aux;
+                data->type, ways, l2x0_size >> 10);
+        pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
+                data->type, cache_id, aux);
+}
+void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
+{
+        const struct l2c_init_data *data;
+        u32 cache_id;
+        l2x0_base = base;
+        cache_id = readl_relaxed(base + L2X0_CACHE_ID);
+        switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
+        default:
+        case L2X0_CACHE_ID_PART_L210:
+                data = &l2c210_data;
+                break;
-        if (!of_init) {
+        case L2X0_CACHE_ID_PART_L220:
-                outer_cache.inv_range = l2x0_inv_range;
+                data = &l2c220_data;
-                outer_cache.clean_range = l2x0_clean_range;
+                break;
-                outer_cache.flush_range = l2x0_flush_range;
-                outer_cache.sync = l2x0_cache_sync;
+        case L2X0_CACHE_ID_PART_L310:
-                outer_cache.flush_all = l2x0_flush_all;
+                data = &l2c310_init_fns;
-                outer_cache.inv_all = l2x0_inv_all;
+                break;
-                outer_cache.disable = l2x0_disable;
        }
-        pr_info("%s cache controller enabled\n", type);
+        __l2c_init(data, aux_val, aux_mask, cache_id);
-        pr_info("l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d kB\n",
-                ways, cache_id, aux, l2x0_size >> 10);
 }
 #ifdef CONFIG_OF
 static int l2_wt_override;
+/* Aurora don't have the cache ID register available, so we have to
+ * pass it though the device tree */
+static u32 cache_id_part_number_from_dt;
+static void __init l2x0_of_parse(const struct device_node *np,
+                                 u32 *aux_val, u32 *aux_mask)
+{
+        u32 data[2] = { 0, 0 };
+        u32 tag = 0;
+        u32 dirty = 0;
+        u32 val = 0, mask = 0;
+        of_property_read_u32(np, "arm,tag-latency", &tag);
+        if (tag) {
+                mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
+                val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
+        }
+        of_property_read_u32_array(np, "arm,data-latency",
+                                   data, ARRAY_SIZE(data));
+        if (data[0] && data[1]) {
+                mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
+                        L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
+                val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
+                       ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
+        }
+        of_property_read_u32(np, "arm,dirty-latency", &dirty);
+        if (dirty) {
+                mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
+                val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
+        }
+        *aux_val &= ~mask;
+        *aux_val |= val;
+        *aux_mask &= ~mask;
+}
+static const struct l2c_init_data of_l2c210_data __initconst = {
+        .type = "L2C-210",
+        .way_size_0 = SZ_8K,
+        .num_lock = 1,
+        .of_parse = l2x0_of_parse,
+        .enable = l2c_enable,
+        .save = l2c_save,
+        .outer_cache = {
+                .inv_range   = l2c210_inv_range,
+                .clean_range = l2c210_clean_range,
+                .flush_range = l2c210_flush_range,
+                .flush_all   = l2c210_flush_all,
+                .disable     = l2c_disable,
+                .sync        = l2c210_sync,
+                .resume      = l2c210_resume,
+        },
+};
+static const struct l2c_init_data of_l2c220_data __initconst = {
+        .type = "L2C-220",
+        .way_size_0 = SZ_8K,
+        .num_lock = 1,
+        .of_parse = l2x0_of_parse,
+        .enable = l2c220_enable,
+        .save = l2c_save,
+        .outer_cache = {
+                .inv_range   = l2c220_inv_range,
+                .clean_range = l2c220_clean_range,
+                .flush_range = l2c220_flush_range,
+                .flush_all   = l2c220_flush_all,
+                .disable     = l2c_disable,
+                .sync        = l2c220_sync,
+                .resume      = l2c210_resume,
+        },
+};
+static void __init l2c310_of_parse(const struct device_node *np,
+        u32 *aux_val, u32 *aux_mask)
+{
+        u32 data[3] = { 0, 0, 0 };
+        u32 tag[3] = { 0, 0, 0 };
+        u32 filter[2] = { 0, 0 };
+        of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
+        if (tag[0] && tag[1] && tag[2])
+                writel_relaxed(
+                        L310_LATENCY_CTRL_RD(tag[0] - 1) |
+                        L310_LATENCY_CTRL_WR(tag[1] - 1) |
+                        L310_LATENCY_CTRL_SETUP(tag[2] - 1),
+                        l2x0_base + L310_TAG_LATENCY_CTRL);
+        of_property_read_u32_array(np, "arm,data-latency",
+                                   data, ARRAY_SIZE(data));
+        if (data[0] && data[1] && data[2])
+                writel_relaxed(
+                        L310_LATENCY_CTRL_RD(data[0] - 1) |
+                        L310_LATENCY_CTRL_WR(data[1] - 1) |
+                        L310_LATENCY_CTRL_SETUP(data[2] - 1),
+                        l2x0_base + L310_DATA_LATENCY_CTRL);
+        of_property_read_u32_array(np, "arm,filter-ranges",
+                                   filter, ARRAY_SIZE(filter));
+        if (filter[1]) {
+                writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
+                               l2x0_base + L310_ADDR_FILTER_END);
+                writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L310_ADDR_FILTER_EN,
+                               l2x0_base + L310_ADDR_FILTER_START);
+        }
+}
+static const struct l2c_init_data of_l2c310_data __initconst = {
+        .type = "L2C-310",
+        .way_size_0 = SZ_8K,
+        .num_lock = 8,
+        .of_parse = l2c310_of_parse,
+        .enable = l2c310_enable,
+        .fixup = l2c310_fixup,
+        .save  = l2c310_save,
+        .outer_cache = {
+                .inv_range   = l2c210_inv_range,
+                .clean_range = l2c210_clean_range,
+                .flush_range = l2c210_flush_range,
+                .flush_all   = l2c210_flush_all,
+                .disable     = l2c310_disable,
+                .sync        = l2c210_sync,
+                .resume      = l2c310_resume,
+        },
+};
 /*
 * Note that the end addresses passed to Linux primitives are
 * noninclusive, while the hardware cache range operations use
@@ -524,6 +1166,100 @@ static void aurora_flush_range(unsigned long start, unsigned long end)
        }
 }
+static void aurora_save(void __iomem *base)
+{
+        l2x0_saved_regs.ctrl = readl_relaxed(base + L2X0_CTRL);
+        l2x0_saved_regs.aux_ctrl = readl_relaxed(base + L2X0_AUX_CTRL);
+}
+static void aurora_resume(void)
+{
+        void __iomem *base = l2x0_base;
+        if (!(readl(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+                writel_relaxed(l2x0_saved_regs.aux_ctrl, base + L2X0_AUX_CTRL);
+                writel_relaxed(l2x0_saved_regs.ctrl, base + L2X0_CTRL);
+        }
+}
+/*
+ * For Aurora cache in no outer mode, enable via the CP15 coprocessor
+ * broadcasting of cache commands to L2.
+ */
+static void __init aurora_enable_no_outer(void __iomem *base, u32 aux,
+        unsigned num_lock)
+{
+        u32 u;
+        asm volatile("mrc p15, 1, %0, c15, c2, 0" : "=r" (u));
+        u |= AURORA_CTRL_FW;            /* Set the FW bit */
+        asm volatile("mcr p15, 1, %0, c15, c2, 0" : : "r" (u));
+        isb();
+        l2c_enable(base, aux, num_lock);
+}
+static void __init aurora_fixup(void __iomem *base, u32 cache_id,
+        struct outer_cache_fns *fns)
+{
+        sync_reg_offset = AURORA_SYNC_REG;
+}
+static void __init aurora_of_parse(const struct device_node *np,
+                                u32 *aux_val, u32 *aux_mask)
+{
+        u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
+        u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
+        of_property_read_u32(np, "cache-id-part",
+                        &cache_id_part_number_from_dt);
+        /* Determine and save the write policy */
+        l2_wt_override = of_property_read_bool(np, "wt-override");
+        if (l2_wt_override) {
+                val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
+                mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
+        }
+        *aux_val &= ~mask;
+        *aux_val |= val;
+        *aux_mask &= ~mask;
+}
+static const struct l2c_init_data of_aurora_with_outer_data __initconst = {
+        .type = "Aurora",
+        .way_size_0 = SZ_4K,
+        .num_lock = 4,
+        .of_parse = aurora_of_parse,
+        .enable = l2c_enable,
+        .fixup = aurora_fixup,
+        .save  = aurora_save,
+        .outer_cache = {
+                .inv_range   = aurora_inv_range,
+                .clean_range = aurora_clean_range,
+                .flush_range = aurora_flush_range,
+                .flush_all   = l2x0_flush_all,
+                .disable     = l2x0_disable,
+                .sync        = l2x0_cache_sync,
+                .resume      = aurora_resume,
+        },
+};
+static const struct l2c_init_data of_aurora_no_outer_data __initconst = {
+        .type = "Aurora",
+        .way_size_0 = SZ_4K,
+        .num_lock = 4,
+        .of_parse = aurora_of_parse,
+        .enable = aurora_enable_no_outer,
+        .fixup = aurora_fixup,
+        .save  = aurora_save,
+        .outer_cache = {
+                .resume      = aurora_resume,
+        },
+};
 /*
 * For certain Broadcom SoCs, depending on the address range, different offsets
 * need to be added to the address before passing it to L2 for
@@ -588,16 +1324,16 @@ static void bcm_inv_range(unsigned long start, unsigned long end)
        /* normal case, no cross section between start and end */
        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
-                l2x0_inv_range(new_start, new_end);
+                l2c210_inv_range(new_start, new_end);
                return;
        }
        /* They cross sections, so it can only be a cross from section
         * 2 to section 3
         */
-        l2x0_inv_range(new_start,
+        l2c210_inv_range(new_start,
                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
-        l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+        l2c210_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
                new_end);
 }
@@ -610,26 +1346,21 @@ static void bcm_clean_range(unsigned long start, unsigned long end)
        if (unlikely(end <= start))
                return;
-        if ((end - start) >= l2x0_size) {
-                l2x0_clean_all();
-                return;
-        }
        new_start = bcm_l2_phys_addr(start);
        new_end = bcm_l2_phys_addr(end);
        /* normal case, no cross section between start and end */
        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
-                l2x0_clean_range(new_start, new_end);
+                l2c210_clean_range(new_start, new_end);
                return;
        }
        /* They cross sections, so it can only be a cross from section
         * 2 to section 3
         */
-        l2x0_clean_range(new_start,
+        l2c210_clean_range(new_start,
                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
-        l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+        l2c210_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
                new_end);
 }
@@ -643,7 +1374,7 @@ static void bcm_flush_range(unsigned long start, unsigned long end)
                return;
        if ((end - start) >= l2x0_size) {
-                l2x0_flush_all();
+                outer_cache.flush_all();
                return;
        }
@@ -652,283 +1383,67 @@ static void bcm_flush_range(unsigned long start, unsigned long end)
        /* normal case, no cross section between start and end */
        if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
-                l2x0_flush_range(new_start, new_end);
+                l2c210_flush_range(new_start, new_end);
                return;
        }
        /* They cross sections, so it can only be a cross from section
         * 2 to section 3
         */
-        l2x0_flush_range(new_start,
+        l2c210_flush_range(new_start,
                bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
-        l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
+        l2c210_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
                new_end);
 }
-static void __init l2x0_of_setup(const struct device_node *np,
+/* Broadcom L2C-310 start from ARMs R3P2 or later, and require no fixups */
-                                 u32 *aux_val, u32 *aux_mask)
+static const struct l2c_init_data of_bcm_l2x0_data __initconst = {
-{
+        .type = "BCM-L2C-310",
-        u32 data[2] = { 0, 0 };
+        .way_size_0 = SZ_8K,
-        u32 tag = 0;
+        .num_lock = 8,
-        u32 dirty = 0;
+        .of_parse = l2c310_of_parse,
-        u32 val = 0, mask = 0;
+        .enable = l2c310_enable,
+        .save  = l2c310_save,
-        of_property_read_u32(np, "arm,tag-latency", &tag);
+        .outer_cache = {
-        if (tag) {
+                .inv_range   = bcm_inv_range,
-                mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
+                .clean_range = bcm_clean_range,
-                val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
+                .flush_range = bcm_flush_range,
-        }
+                .flush_all   = l2c210_flush_all,
+                .disable     = l2c310_disable,
-        of_property_read_u32_array(np, "arm,data-latency",
+                .sync        = l2c210_sync,
-                                   data, ARRAY_SIZE(data));
+                .resume      = l2c310_resume,
-        if (data[0] && data[1]) {
+        },
-                mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
+};
-                        L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
-                val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
-                       ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
-        }
-        of_property_read_u32(np, "arm,dirty-latency", &dirty);
-        if (dirty) {
-                mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
-                val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
-        }
-        *aux_val &= ~mask;
-        *aux_val |= val;
-        *aux_mask &= ~mask;
-}
-static void __init pl310_of_setup(const struct device_node *np,
-                                  u32 *aux_val, u32 *aux_mask)
-{
-        u32 data[3] = { 0, 0, 0 };
-        u32 tag[3] = { 0, 0, 0 };
-        u32 filter[2] = { 0, 0 };
-        of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
-        if (tag[0] && tag[1] && tag[2])
-                writel_relaxed(
-                        ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
-                        ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
-                        ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
-                        l2x0_base + L2X0_TAG_LATENCY_CTRL);
-        of_property_read_u32_array(np, "arm,data-latency",
-                                   data, ARRAY_SIZE(data));
-        if (data[0] && data[1] && data[2])
-                writel_relaxed(
-                        ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
-                        ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
-                        ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
-                        l2x0_base + L2X0_DATA_LATENCY_CTRL);
-        of_property_read_u32_array(np, "arm,filter-ranges",
-                                   filter, ARRAY_SIZE(filter));
-        if (filter[1]) {
-                writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
-                               l2x0_base + L2X0_ADDR_FILTER_END);
-                writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
-                               l2x0_base + L2X0_ADDR_FILTER_START);
-        }
-}
-static void __init pl310_save(void)
-{
-        u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
-                L2X0_CACHE_ID_RTL_MASK;
-        l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
-                L2X0_TAG_LATENCY_CTRL);
-        l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
-                L2X0_DATA_LATENCY_CTRL);
-        l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
-                L2X0_ADDR_FILTER_END);
-        l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
-                L2X0_ADDR_FILTER_START);
-        if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
-                /*
-                 * From r2p0, there is Prefetch offset/control register
-                 */
-                l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
-                        L2X0_PREFETCH_CTRL);
-                /*
-                 * From r3p0, there is Power control register
-                 */
-                if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
-                        l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
-                                L2X0_POWER_CTRL);
-        }
-}
-static void aurora_save(void)
+static void __init tauros3_save(void __iomem *base)
 {
-        l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
+        l2c_save(base);
-        l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
-}
-static void __init tauros3_save(void)
-{
        l2x0_saved_regs.aux2_ctrl =
-                readl_relaxed(l2x0_base + TAUROS3_AUX2_CTRL);
+                readl_relaxed(base + TAUROS3_AUX2_CTRL);
        l2x0_saved_regs.prefetch_ctrl =
-                readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
+                readl_relaxed(base + L310_PREFETCH_CTRL);
-}
-static void l2x0_resume(void)
-{
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-                /* restore aux ctrl and enable l2 */
-                l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
-                writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
-                        L2X0_AUX_CTRL);
-                l2x0_inv_all();
-                writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
-        }
-}
-static void pl310_resume(void)
-{
-        u32 l2x0_revision;
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-                /* restore pl310 setup */
-                writel_relaxed(l2x0_saved_regs.tag_latency,
-                        l2x0_base + L2X0_TAG_LATENCY_CTRL);
-                writel_relaxed(l2x0_saved_regs.data_latency,
-                        l2x0_base + L2X0_DATA_LATENCY_CTRL);
-                writel_relaxed(l2x0_saved_regs.filter_end,
-                        l2x0_base + L2X0_ADDR_FILTER_END);
-                writel_relaxed(l2x0_saved_regs.filter_start,
-                        l2x0_base + L2X0_ADDR_FILTER_START);
-                l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
-                        L2X0_CACHE_ID_RTL_MASK;
-                if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
-                        writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                                l2x0_base + L2X0_PREFETCH_CTRL);
-                        if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
-                                writel_relaxed(l2x0_saved_regs.pwr_ctrl,
-                                        l2x0_base + L2X0_POWER_CTRL);
-                }
-        }
-        l2x0_resume();
-}
-static void aurora_resume(void)
-{
-        if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
-                writel_relaxed(l2x0_saved_regs.aux_ctrl,
-                                l2x0_base + L2X0_AUX_CTRL);
-                writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
-        }
 }
 static void tauros3_resume(void)
 {
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+        void __iomem *base = l2x0_base;
+        if (!(readl_relaxed(base + L2X0_CTRL) & L2X0_CTRL_EN)) {
                writel_relaxed(l2x0_saved_regs.aux2_ctrl,
-                               l2x0_base + TAUROS3_AUX2_CTRL);
+                               base + TAUROS3_AUX2_CTRL);
                writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
-                               l2x0_base + L2X0_PREFETCH_CTRL);
+                               base + L310_PREFETCH_CTRL);
-        }
-        l2x0_resume();
+                l2c_enable(base, l2x0_saved_regs.aux_ctrl, 8);
-}
-static void __init aurora_broadcast_l2_commands(void)
-{
-        __u32 u;
-        /* Enable Broadcasting of cache commands to L2*/
-        __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
-        u |= AURORA_CTRL_FW;            /* Set the FW bit */
-        __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
-        isb();
-}
-static void __init aurora_of_setup(const struct device_node *np,
-                                u32 *aux_val, u32 *aux_mask)
-{
-        u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
-        u32 mask =  AURORA_ACR_REPLACEMENT_MASK;
-        of_property_read_u32(np, "cache-id-part",
-                        &cache_id_part_number_from_dt);
-        /* Determine and save the write policy */
-        l2_wt_override = of_property_read_bool(np, "wt-override");
-        if (l2_wt_override) {
-                val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
-                mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
        }
-        *aux_val &= ~mask;
-        *aux_val |= val;
-        *aux_mask &= ~mask;
 }
-static const struct l2x0_of_data pl310_data = {
+static const struct l2c_init_data of_tauros3_data __initconst = {
-        .setup = pl310_of_setup,
+        .type = "Tauros3",
-        .save  = pl310_save,
+        .way_size_0 = SZ_8K,
-        .outer_cache = {
+        .num_lock = 8,
-                .resume      = pl310_resume,
+        .enable = l2c_enable,
-                .inv_range   = l2x0_inv_range,
-                .clean_range = l2x0_clean_range,
-                .flush_range = l2x0_flush_range,
-                .sync        = l2x0_cache_sync,
-                .flush_all   = l2x0_flush_all,
-                .inv_all     = l2x0_inv_all,
-                .disable     = l2x0_disable,
-        },
-};
-static const struct l2x0_of_data l2x0_data = {
-        .setup = l2x0_of_setup,
-        .save  = NULL,
-        .outer_cache = {
-                .resume      = l2x0_resume,
-                .inv_range   = l2x0_inv_range,
-                .clean_range = l2x0_clean_range,
-                .flush_range = l2x0_flush_range,
-                .sync        = l2x0_cache_sync,
-                .flush_all   = l2x0_flush_all,
-                .inv_all     = l2x0_inv_all,
-                .disable     = l2x0_disable,
-        },
-};
-static const struct l2x0_of_data aurora_with_outer_data = {
-        .setup = aurora_of_setup,
-        .save  = aurora_save,
-        .outer_cache = {
-                .resume      = aurora_resume,
-                .inv_range   = aurora_inv_range,
-                .clean_range = aurora_clean_range,
-                .flush_range = aurora_flush_range,
-                .sync        = l2x0_cache_sync,
-                .flush_all   = l2x0_flush_all,
-                .inv_all     = l2x0_inv_all,
-                .disable     = l2x0_disable,
-        },
-};
-static const struct l2x0_of_data aurora_no_outer_data = {
-        .setup = aurora_of_setup,
-        .save  = aurora_save,
-        .outer_cache = {
-                .resume      = aurora_resume,
-        },
-};
-static const struct l2x0_of_data tauros3_data = {
-        .setup = NULL,
        .save  = tauros3_save,
        /* Tauros3 broadcasts L1 cache operations to L2 */
        .outer_cache = {
@@ -936,43 +1451,26 @@ static const struct l2x0_of_data tauros3_data = {
        },
 };
-static const struct l2x0_of_data bcm_l2x0_data = {
+#define L2C_ID(name, fns) { .compatible = name, .data = (void *)&fns }
-        .setup = pl310_of_setup,
-        .save  = pl310_save,
-        .outer_cache = {
-                .resume      = pl310_resume,
-                .inv_range   = bcm_inv_range,
-                .clean_range = bcm_clean_range,
-                .flush_range = bcm_flush_range,
-                .sync        = l2x0_cache_sync,
-                .flush_all   = l2x0_flush_all,
-                .inv_all     = l2x0_inv_all,
-                .disable     = l2x0_disable,
-        },
-};
 static const struct of_device_id l2x0_ids[] __initconst = {
-        { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
+        L2C_ID("arm,l210-cache", of_l2c210_data),
-        { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
+        L2C_ID("arm,l220-cache", of_l2c220_data),
-        { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
+        L2C_ID("arm,pl310-cache", of_l2c310_data),
-        { .compatible = "bcm,bcm11351-a2-pl310-cache", /* deprecated name */
+        L2C_ID("brcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
-          .data = (void *)&bcm_l2x0_data},
+        L2C_ID("marvell,aurora-outer-cache", of_aurora_with_outer_data),
-        { .compatible = "brcm,bcm11351-a2-pl310-cache",
+        L2C_ID("marvell,aurora-system-cache", of_aurora_no_outer_data),
-          .data = (void *)&bcm_l2x0_data},
+        L2C_ID("marvell,tauros3-cache", of_tauros3_data),
-        { .compatible = "marvell,aurora-outer-cache",
+        /* Deprecated IDs */
-          .data = (void *)&aurora_with_outer_data},
+        L2C_ID("bcm,bcm11351-a2-pl310-cache", of_bcm_l2x0_data),
-        { .compatible = "marvell,aurora-system-cache",
-          .data = (void *)&aurora_no_outer_data},
-        { .compatible = "marvell,tauros3-cache",
-          .data = (void *)&tauros3_data },
        {}
 };
 int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
 {
+        const struct l2c_init_data *data;
        struct device_node *np;
-        const struct l2x0_of_data *data;
        struct resource res;
+        u32 cache_id, old_aux;
        np = of_find_matching_node(NULL, l2x0_ids);
        if (!np)
@@ -989,23 +1487,29 @@ int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
        data = of_match_node(l2x0_ids, np)->data;
-        /* L2 configuration can only be changed if the cache is disabled */
+        old_aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
-        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
+        if (old_aux != ((old_aux & aux_mask) | aux_val)) {
-                if (data->setup)
+                pr_warn("L2C: platform modifies aux control register: 0x%08x -> 0x%08x\n",
-                        data->setup(np, &aux_val, &aux_mask);
+                        old_aux, (old_aux & aux_mask) | aux_val);
+        } else if (aux_mask != ~0U && aux_val != 0) {
-                /* For aurora cache in no outer mode select the
+                pr_alert("L2C: platform provided aux values match the hardware, so have no effect.  Please remove them.\n");
-                 * correct mode using the coprocessor*/
-                if (data == &aurora_no_outer_data)
-                        aurora_broadcast_l2_commands();
        }
-        if (data->save)
+        /* All L2 caches are unified, so this property should be specified */
-                data->save();
+        if (!of_property_read_bool(np, "cache-unified"))
+                pr_err("L2C: device tree omits to specify unified cache\n");
+        /* L2 configuration can only be changed if the cache is disabled */
+        if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
+                if (data->of_parse)
+                        data->of_parse(np, &aux_val, &aux_mask);
+        if (cache_id_part_number_from_dt)
+                cache_id = cache_id_part_number_from_dt;
+        else
+                cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
-        of_init = true;
+        __l2c_init(data, aux_val, aux_mask, cache_id);
-        memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
-        l2x0_init(l2x0_base, aux_val, aux_mask);
        return 0;
 }
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 778bcf88ee79..615c99e38ba1 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -59,7 +59,7 @@ ENTRY(v7_invalidate_l1)
       bgt     2b
       cmp     r2, #0
       bgt     1b
-       dsb
+       dsb     st
       isb
       mov     pc, lr
 ENDPROC(v7_invalidate_l1)
@@ -166,7 +166,7 @@ skip:
 finished:
        mov     r10, #0                         @ swith back to cache level 0
        mcr     p15, 2, r10, c0, c0, 0          @ select current cache level in cssr
-        dsb
+        dsb     st
        isb
        mov     pc, lr
 ENDPROC(v7_flush_dcache_all)
@@ -335,7 +335,7 @@ ENTRY(v7_flush_kern_dcache_area)
        add     r0, r0, r2
        cmp     r0, r1
        blo     1b
-        dsb
+        dsb     st
        mov     pc, lr
 ENDPROC(v7_flush_kern_dcache_area)
@@ -368,7 +368,7 @@ v7_dma_inv_range:
        add     r0, r0, r2
        cmp     r0, r1
        blo     1b
-        dsb
+        dsb     st
        mov     pc, lr
 ENDPROC(v7_dma_inv_range)
@@ -390,7 +390,7 @@ v7_dma_clean_range:
        add     r0, r0, r2
        cmp     r0, r1
        blo     1b
-        dsb
+        dsb     st
        mov     pc, lr
 ENDPROC(v7_dma_clean_range)
@@ -412,7 +412,7 @@ ENTRY(v7_dma_flush_range)
        add     r0, r0, r2
        cmp     r0, r1
        blo     1b
-        dsb
+        dsb     st
        mov     pc, lr
 ENDPROC(v7_dma_flush_range)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 6b00be1f971e..4c88935654ca 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -390,7 +390,7 @@ static int __init atomic_pool_init(void)
        if (!pages)
                goto no_pages;
-        if (IS_ENABLED(CONFIG_DMA_CMA))
+        if (dev_get_cma_area(NULL))
                ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
                                              atomic_pool_init);
        else
@@ -701,7 +701,7 @@ static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
                addr = __alloc_simple_buffer(dev, size, gfp, &page);
        else if (!(gfp & __GFP_WAIT))
                addr = __alloc_from_pool(size, &page);
-        else if (!IS_ENABLED(CONFIG_DMA_CMA))
+        else if (!dev_get_cma_area(dev))
                addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
        else
                addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
@@ -790,7 +790,7 @@ static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
                __dma_free_buffer(page, size);
        } else if (__free_from_pool(cpu_addr, size)) {
                return;
-        } else if (!IS_ENABLED(CONFIG_DMA_CMA)) {
+        } else if (!dev_get_cma_area(dev)) {
                __dma_free_remap(cpu_addr, size);
                __dma_free_buffer(page, size);
        } else {
@@ -885,7 +885,7 @@ static void dma_cache_maint_page(struct page *page, unsigned long offset,
 static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
        size_t size, enum dma_data_direction dir)
 {
-        unsigned long paddr;
+        phys_addr_t paddr;
        dma_cache_maint_page(page, off, size, dir, dmac_map_area);
@@ -901,14 +901,15 @@ static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
 static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
        size_t size, enum dma_data_direction dir)
 {
-        unsigned long paddr = page_to_phys(page) + off;
+        phys_addr_t paddr = page_to_phys(page) + off;
        /* FIXME: non-speculating: not required */
-        /* don't bother invalidating if DMA to device */
+        /* in any case, don't bother invalidating if DMA to device */
-        if (dir != DMA_TO_DEVICE)
+        if (dir != DMA_TO_DEVICE) {
                outer_inv_range(paddr, paddr + size);
-        dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+                dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
+        }
        /*
         * Mark the D-cache clean for these pages to avoid extra flushing.
@@ -1074,6 +1075,7 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
        unsigned int order = get_order(size);
        unsigned int align = 0;
        unsigned int count, start;
+        size_t mapping_size = mapping->bits << PAGE_SHIFT;
        unsigned long flags;
        dma_addr_t iova;
        int i;
@@ -1119,7 +1121,7 @@ static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
        }
        spin_unlock_irqrestore(&mapping->lock, flags);
-        iova = mapping->base + (mapping->size * i);
+        iova = mapping->base + (mapping_size * i);
        iova += start << PAGE_SHIFT;
        return iova;
@@ -1129,6 +1131,7 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
                               dma_addr_t addr, size_t size)
 {
        unsigned int start, count;
+        size_t mapping_size = mapping->bits << PAGE_SHIFT;
        unsigned long flags;
        dma_addr_t bitmap_base;
        u32 bitmap_index;
@@ -1136,14 +1139,14 @@ static inline void __free_iova(struct dma_iommu_mapping *mapping,
        if (!size)
                return;
-        bitmap_index = (u32) (addr - mapping->base) / (u32) mapping->size;
+        bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size;
        BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions);
-        bitmap_base = mapping->base + mapping->size * bitmap_index;
+        bitmap_base = mapping->base + mapping_size * bitmap_index;
        start = (addr - bitmap_base) >> PAGE_SHIFT;
-        if (addr + size > bitmap_base + mapping->size) {
+        if (addr + size > bitmap_base + mapping_size) {
                /*
                 * The address range to be freed reaches into the iova
                 * range of the next bitmap. This should not happen as
@@ -1964,7 +1967,6 @@ arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size)
        mapping->extensions = extensions;
        mapping->base = base;
        mapping->bits = BITS_PER_BYTE * bitmap_size;
-        mapping->size = mapping->bits << PAGE_SHIFT;
        spin_lock_init(&mapping->lock);
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 3387e60e4ea3..43d54f5b26b9 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -104,17 +104,20 @@ void flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsig
 #define flush_icache_alias(pfn,vaddr,len)       do { } while (0)
 #endif
+#define FLAG_PA_IS_EXEC 1
+#define FLAG_PA_CORE_IN_MM 2
 static void flush_ptrace_access_other(void *args)
 {
        __flush_icache_all();
 }
-static
+static inline
-void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+void __flush_ptrace_access(struct page *page, unsigned long uaddr, void *kaddr,
-                         unsigned long uaddr, void *kaddr, unsigned long len)
+                           unsigned long len, unsigned int flags)
 {
        if (cache_is_vivt()) {
-                if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm))) {
+                if (flags & FLAG_PA_CORE_IN_MM) {
                        unsigned long addr = (unsigned long)kaddr;
                        __cpuc_coherent_kern_range(addr, addr + len);
                }
@@ -128,7 +131,7 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
        }
        /* VIPT non-aliasing D-cache */
-        if (vma->vm_flags & VM_EXEC) {
+        if (flags & FLAG_PA_IS_EXEC) {
                unsigned long addr = (unsigned long)kaddr;
                if (icache_is_vipt_aliasing())
                        flush_icache_alias(page_to_pfn(page), uaddr, len);
@@ -140,6 +143,26 @@ void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
        }
 }
+static
+void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
+                         unsigned long uaddr, void *kaddr, unsigned long len)
+{
+        unsigned int flags = 0;
+        if (cpumask_test_cpu(smp_processor_id(), mm_cpumask(vma->vm_mm)))
+                flags |= FLAG_PA_CORE_IN_MM;
+        if (vma->vm_flags & VM_EXEC)
+                flags |= FLAG_PA_IS_EXEC;
+        __flush_ptrace_access(page, uaddr, kaddr, len, flags);
+}
+void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,
+                             void *kaddr, unsigned long len)
+{
+        unsigned int flags = FLAG_PA_CORE_IN_MM|FLAG_PA_IS_EXEC;
+        __flush_ptrace_access(page, uaddr, kaddr, len, flags);
+}
 /*
 * Copy user data from/to a page which is mapped into a different
 * processes address space.  Really, we want to allow our "user
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index 21b9e1bf9b77..45aeaaca9052 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -18,6 +18,21 @@
 #include <asm/tlbflush.h>
 #include "mm.h"
+pte_t *fixmap_page_table;
+static inline void set_fixmap_pte(int idx, pte_t pte)
+{
+        unsigned long vaddr = __fix_to_virt(idx);
+        set_pte_ext(fixmap_page_table + idx, pte, 0);
+        local_flush_tlb_kernel_page(vaddr);
+}
+static inline pte_t get_fixmap_pte(unsigned long vaddr)
+{
+        unsigned long idx = __virt_to_fix(vaddr);
+        return *(fixmap_page_table + idx);
+}
 void *kmap(struct page *page)
 {
        might_sleep();
@@ -63,20 +78,20 @@ void *kmap_atomic(struct page *page)
        type = kmap_atomic_idx_push();
        idx = type + KM_TYPE_NR * smp_processor_id();
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        vaddr = __fix_to_virt(idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
        /*
         * With debugging enabled, kunmap_atomic forces that entry to 0.
         * Make sure it was indeed properly unmapped.
         */
-        BUG_ON(!pte_none(get_top_pte(vaddr)));
+        BUG_ON(!pte_none(*(fixmap_page_table + idx)));
 #endif
        /*
         * When debugging is off, kunmap_atomic leaves the previous mapping
         * in place, so the contained TLB flush ensures the TLB is updated
         * with the new mapping.
         */
-        set_top_pte(vaddr, mk_pte(page, kmap_prot));
+        set_fixmap_pte(idx, mk_pte(page, kmap_prot));
        return (void *)vaddr;
 }
@@ -94,8 +109,8 @@ void __kunmap_atomic(void *kvaddr)
                if (cache_is_vivt())
                        __cpuc_flush_dcache_area((void *)vaddr, PAGE_SIZE);
 #ifdef CONFIG_DEBUG_HIGHMEM
-                BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx));
+                BUG_ON(vaddr != __fix_to_virt(idx));
-                set_top_pte(vaddr, __pte(0));
+                set_fixmap_pte(idx, __pte(0));
 #else
                (void) idx;  /* to kill a warning */
 #endif
@@ -117,11 +132,11 @@ void *kmap_atomic_pfn(unsigned long pfn)
        type = kmap_atomic_idx_push();
        idx = type + KM_TYPE_NR * smp_processor_id();
-        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
+        vaddr = __fix_to_virt(idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
-        BUG_ON(!pte_none(get_top_pte(vaddr)));
+        BUG_ON(!pte_none(*(fixmap_page_table + idx)));
 #endif
-        set_top_pte(vaddr, pfn_pte(pfn, kmap_prot));
+        set_fixmap_pte(idx, pfn_pte(pfn, kmap_prot));
        return (void *)vaddr;
 }
@@ -133,5 +148,5 @@ struct page *kmap_atomic_to_page(const void *ptr)
        if (vaddr < FIXADDR_START)
                return virt_to_page(ptr);
-        return pte_page(get_top_pte(vaddr));
+        return pte_page(get_fixmap_pte(vaddr));
 }
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
index 54ee6163c181..66781bf34077 100644
--- a/arch/arm/mm/hugetlbpage.c
+++ b/arch/arm/mm/hugetlbpage.c
@@ -56,8 +56,3 @@ int pmd_huge(pmd_t pmd)
 {
        return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
 }
-int pmd_huge_support(void)
-{
-        return 1;
-}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 2a77ba8796ae..659c75d808dc 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -23,6 +23,7 @@
 #include <linux/dma-contiguous.h>
 #include <linux/sizes.h>
+#include <asm/cp15.h>
 #include <asm/mach-types.h>
 #include <asm/memblock.h>
 #include <asm/prom.h>
@@ -36,6 +37,14 @@
 #include "mm.h"
+#ifdef CONFIG_CPU_CP15_MMU
+unsigned long __init __clear_cr(unsigned long mask)
+{
+        cr_alignment = cr_alignment & ~mask;
+        return cr_alignment;
+}
+#endif
 static phys_addr_t phys_initrd_start __initdata = 0;
 static unsigned long phys_initrd_size __initdata = 0;
@@ -81,24 +90,21 @@ __tagtable(ATAG_INITRD2, parse_tag_initrd2);
 * initialization functions, as well as show_mem() for the skipping
 * of holes in the memory map.  It is populated by arm_add_memory().
 */
-struct meminfo meminfo;
 void show_mem(unsigned int filter)
 {
        int free = 0, total = 0, reserved = 0;
-        int shared = 0, cached = 0, slab = 0, i;
+        int shared = 0, cached = 0, slab = 0;
-        struct meminfo * mi = &meminfo;
+        struct memblock_region *reg;
        printk("Mem-info:\n");
        show_free_areas(filter);
-        for_each_bank (i, mi) {
+        for_each_memblock (memory, reg) {
-                struct membank *bank = &mi->bank[i];
                unsigned int pfn1, pfn2;
                struct page *page, *end;
-                pfn1 = bank_pfn_start(bank);
+                pfn1 = memblock_region_memory_base_pfn(reg);
-                pfn2 = bank_pfn_end(bank);
+                pfn2 = memblock_region_memory_end_pfn(reg);
                page = pfn_to_page(pfn1);
                end  = pfn_to_page(pfn2 - 1) + 1;
@@ -115,8 +121,9 @@ void show_mem(unsigned int filter)
                                free++;
                        else
                                shared += page_count(page) - 1;
-                        page++;
+                        pfn1++;
-                } while (page < end);
+                        page = pfn_to_page(pfn1);
+                } while (pfn1 < pfn2);
        }
        printk("%d pages of RAM\n", total);
@@ -130,16 +137,9 @@ void show_mem(unsigned int filter)
 static void __init find_limits(unsigned long *min, unsigned long *max_low,
                               unsigned long *max_high)
 {
-        struct meminfo *mi = &meminfo;
+        *max_low = PFN_DOWN(memblock_get_current_limit());
-        int i;
+        *min = PFN_UP(memblock_start_of_DRAM());
+        *max_high = PFN_DOWN(memblock_end_of_DRAM());
-        /* This assumes the meminfo array is properly sorted */
-        *min = bank_pfn_start(&mi->bank[0]);
-        for_each_bank (i, mi)
-                if (mi->bank[i].highmem)
-                                break;
-        *max_low = bank_pfn_end(&mi->bank[i - 1]);
-        *max_high = bank_pfn_end(&mi->bank[mi->nr_banks - 1]);
 }
 #ifdef CONFIG_ZONE_DMA
@@ -274,14 +274,8 @@ phys_addr_t __init arm_memblock_steal(phys_addr_t size, phys_addr_t align)
        return phys;
 }
-void __init arm_memblock_init(struct meminfo *mi,
+void __init arm_memblock_init(const struct machine_desc *mdesc)
-        const struct machine_desc *mdesc)
 {
-        int i;
-        for (i = 0; i < mi->nr_banks; i++)
-                memblock_add(mi->bank[i].start, mi->bank[i].size);
        /* Register the kernel text, kernel data and initrd with memblock. */
 #ifdef CONFIG_XIP_KERNEL
        memblock_reserve(__pa(_sdata), _end - _sdata);
@@ -317,7 +311,6 @@ void __init arm_memblock_init(struct meminfo *mi,
 #endif
        arm_mm_memblock_reserve();
-        arm_dt_memblock_reserve();
        /* reserve any platform specific memblock areas */
        if (mdesc->reserve)
@@ -413,54 +406,53 @@ free_memmap(unsigned long start_pfn, unsigned long end_pfn)
 /*
 * The mem_map array can get very big.  Free the unused area of the memory map.
 */
-static void __init free_unused_memmap(struct meminfo *mi)
+static void __init free_unused_memmap(void)
 {
-        unsigned long bank_start, prev_bank_end = 0;
+        unsigned long start, prev_end = 0;
-        unsigned int i;
+        struct memblock_region *reg;
        /*
         * This relies on each bank being in address order.
         * The banks are sorted previously in bootmem_init().
         */
-        for_each_bank(i, mi) {
+        for_each_memblock(memory, reg) {
-                struct membank *bank = &mi->bank[i];
+                start = memblock_region_memory_base_pfn(reg);
-                bank_start = bank_pfn_start(bank);
 #ifdef CONFIG_SPARSEMEM
                /*
                 * Take care not to free memmap entries that don't exist
                 * due to SPARSEMEM sections which aren't present.
                 */
-                bank_start = min(bank_start,
+                start = min(start,
-                                 ALIGN(prev_bank_end, PAGES_PER_SECTION));
+                                 ALIGN(prev_end, PAGES_PER_SECTION));
 #else
                /*
                 * Align down here since the VM subsystem insists that the
                 * memmap entries are valid from the bank start aligned to
                 * MAX_ORDER_NR_PAGES.
                 */
-                bank_start = round_down(bank_start, MAX_ORDER_NR_PAGES);
+                start = round_down(start, MAX_ORDER_NR_PAGES);
 #endif
                /*
                 * If we had a previous bank, and there is a space
                 * between the current bank and the previous, free it.
                 */
-                if (prev_bank_end && prev_bank_end < bank_start)
+                if (prev_end && prev_end < start)
-                        free_memmap(prev_bank_end, bank_start);
+                        free_memmap(prev_end, start);
                /*
                 * Align up here since the VM subsystem insists that the
                 * memmap entries are valid from the bank end aligned to
                 * MAX_ORDER_NR_PAGES.
                 */
-                prev_bank_end = ALIGN(bank_pfn_end(bank), MAX_ORDER_NR_PAGES);
+                prev_end = ALIGN(memblock_region_memory_end_pfn(reg),
+                                 MAX_ORDER_NR_PAGES);
        }
 #ifdef CONFIG_SPARSEMEM
-        if (!IS_ALIGNED(prev_bank_end, PAGES_PER_SECTION))
+        if (!IS_ALIGNED(prev_end, PAGES_PER_SECTION))
-                free_memmap(prev_bank_end,
+                free_memmap(prev_end,
-                            ALIGN(prev_bank_end, PAGES_PER_SECTION));
+                            ALIGN(prev_end, PAGES_PER_SECTION));
 #endif
 }
@@ -536,7 +528,7 @@ void __init mem_init(void)
        set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
        /* this will put all unused low memory onto the freelists */
-        free_unused_memmap(&meminfo);
+        free_unused_memmap();
        free_all_bootmem();
 #ifdef CONFIG_SA1111
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index f9c32ba73544..d1e5ad7ab3bc 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -438,6 +438,13 @@ void __arm_iounmap(volatile void __iomem *io_addr)
 EXPORT_SYMBOL(__arm_iounmap);
 #ifdef CONFIG_PCI
+static int pci_ioremap_mem_type = MT_DEVICE;
+void pci_ioremap_set_mem_type(int mem_type)
+{
+        pci_ioremap_mem_type = mem_type;
+}
 int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
 {
        BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
@@ -445,7 +452,7 @@ int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
        return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
                                  PCI_IO_VIRT_BASE + offset + SZ_64K,
                                  phys_addr,
-                                  __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
+                                  __pgprot(get_mem_type(pci_ioremap_mem_type)->prot_pte));
 }
 EXPORT_SYMBOL_GPL(pci_ioremap_io);
 #endif
diff --git a/arch/arm/mm/l2c-common.c b/arch/arm/mm/l2c-common.c
new file mode 100644
index 000000000000..10a3cf28c362
--- /dev/null
+++ b/arch/arm/mm/l2c-common.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 ARM Ltd.
+ * Written by Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/bug.h>
+#include <linux/smp.h>
+#include <asm/outercache.h>
+void outer_disable(void)
+{
+        WARN_ON(!irqs_disabled());
+        WARN_ON(num_online_cpus() > 1);
+        if (outer_cache.disable)
+                outer_cache.disable();
+}
diff --git a/arch/arm/mm/l2c-l2x0-resume.S b/arch/arm/mm/l2c-l2x0-resume.S
new file mode 100644
index 000000000000..99b05f21a59a
--- /dev/null
+++ b/arch/arm/mm/l2c-l2x0-resume.S
@@ -0,0 +1,58 @@
+/*
+ * L2C-310 early resume code.  This can be used by platforms to restore
+ * the settings of their L2 cache controller before restoring the
+ * processor state.
+ *
+ * This code can only be used to if you are running in the secure world.
+ */
+#include <linux/linkage.h>
+#include <asm/hardware/cache-l2x0.h>
+        .text
+ENTRY(l2c310_early_resume)
+        adr     r0, 1f
+        ldr     r2, [r0]
+        add     r0, r2, r0
+        ldmia   r0, {r1, r2, r3, r4, r5, r6, r7, r8}
+        @ r1 = phys address of L2C-310 controller
+        @ r2 = aux_ctrl
+        @ r3 = tag_latency
+        @ r4 = data_latency
+        @ r5 = filter_start
+        @ r6 = filter_end
+        @ r7 = prefetch_ctrl
+        @ r8 = pwr_ctrl
+        @ Check that the address has been initialised
+        teq     r1, #0
+        moveq   pc, lr
+        @ The prefetch and power control registers are revision dependent
+        @ and can be written whether or not the L2 cache is enabled
+        ldr     r0, [r1, #L2X0_CACHE_ID]
+        and     r0, r0, #L2X0_CACHE_ID_RTL_MASK
+        cmp     r0, #L310_CACHE_ID_RTL_R2P0
+        strcs   r7, [r1, #L310_PREFETCH_CTRL]
+        cmp     r0, #L310_CACHE_ID_RTL_R3P0
+        strcs   r8, [r1, #L310_POWER_CTRL]
+        @ Don't setup the L2 cache if it is already enabled
+        ldr     r0, [r1, #L2X0_CTRL]
+        tst     r0, #L2X0_CTRL_EN
+        movne   pc, lr
+        str     r3, [r1, #L310_TAG_LATENCY_CTRL]
+        str     r4, [r1, #L310_DATA_LATENCY_CTRL]
+        str     r6, [r1, #L310_ADDR_FILTER_END]
+        str     r5, [r1, #L310_ADDR_FILTER_START]
+        str     r2, [r1, #L2X0_AUX_CTRL]
+        mov     r9, #L2X0_CTRL_EN
+        str     r9, [r1, #L2X0_CTRL]
+        mov     pc, lr
+ENDPROC(l2c310_early_resume)
+        .align
+1:      .long   l2x0_saved_regs - .
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 7ea641b7aa7d..ce727d47275c 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -2,6 +2,8 @@
 #include <linux/list.h>
 #include <linux/vmalloc.h>
+#include <asm/pgtable.h>
 /* the upper-most page table pointer */
 extern pmd_t *top_pmd;
@@ -93,3 +95,5 @@ extern phys_addr_t arm_lowmem_limit;
 void __init bootmem_init(void);
 void arm_mm_memblock_reserve(void);
 void dma_contiguous_remap(void);
+unsigned long __clear_cr(unsigned long mask);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b68c6b22e1c8..ab14b79b03f0 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -35,6 +35,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/pci.h>
+#include <asm/fixmap.h>
 #include "mm.h"
 #include "tcm.h"
@@ -117,28 +118,54 @@ static struct cachepolicy cache_policies[] __initdata = {
 };
 #ifdef CONFIG_CPU_CP15
+static unsigned long initial_pmd_value __initdata = 0;
 /*
- * These are useful for identifying cache coherency
+ * Initialise the cache_policy variable with the initial state specified
- * problems by allowing the cache or the cache and
+ * via the "pmd" value.  This is used to ensure that on ARMv6 and later,
- * writebuffer to be turned off.  (Note: the write
+ * the C code sets the page tables up with the same policy as the head
- * buffer should not be on and the cache off).
+ * assembly code, which avoids an illegal state where the TLBs can get
+ * confused.  See comments in early_cachepolicy() for more information.
 */
-static int __init early_cachepolicy(char *p)
+void __init init_default_cache_policy(unsigned long pmd)
 {
        int i;
+        initial_pmd_value = pmd;
+        pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
+        for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
+                if (cache_policies[i].pmd == pmd) {
+                        cachepolicy = i;
+                        break;
+                }
+        if (i == ARRAY_SIZE(cache_policies))
+                pr_err("ERROR: could not find cache policy\n");
+}
+/*
+ * These are useful for identifying cache coherency problems by allowing
+ * the cache or the cache and writebuffer to be turned off.  (Note: the
+ * write buffer should not be on and the cache off).
+ */
+static int __init early_cachepolicy(char *p)
+{
+        int i, selected = -1;
        for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
                int len = strlen(cache_policies[i].policy);
                if (memcmp(p, cache_policies[i].policy, len) == 0) {
-                        cachepolicy = i;
+                        selected = i;
-                        cr_alignment &= ~cache_policies[i].cr_mask;
-                        cr_no_alignment &= ~cache_policies[i].cr_mask;
                        break;
                }
        }
-        if (i == ARRAY_SIZE(cache_policies))
-                printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n");
+        if (selected == -1)
+                pr_err("ERROR: unknown or unsupported cache policy\n");
        /*
         * This restriction is partly to do with the way we boot; it is
         * unpredictable to have memory mapped using two different sets of
@@ -146,12 +173,18 @@ static int __init early_cachepolicy(char *p)
         * change these attributes once the initial assembly has setup the
         * page tables.
         */
-        if (cpu_architecture() >= CPU_ARCH_ARMv6) {
+        if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
-                printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n");
+                pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
-                cachepolicy = CPOLICY_WRITEBACK;
+                        cache_policies[cachepolicy].policy);
+                return 0;
+        }
+        if (selected != cachepolicy) {
+                unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
+                cachepolicy = selected;
+                flush_cache_all();
+                set_cr(cr);
        }
-        flush_cache_all();
-        set_cr(cr_alignment);
        return 0;
 }
 early_param("cachepolicy", early_cachepolicy);
@@ -186,35 +219,6 @@ static int __init early_ecc(char *p)
 early_param("ecc", early_ecc);
 #endif
-static int __init noalign_setup(char *__unused)
-{
-        cr_alignment &= ~CR_A;
-        cr_no_alignment &= ~CR_A;
-        set_cr(cr_alignment);
-        return 1;
-}
-__setup("noalign", noalign_setup);
-#ifndef CONFIG_SMP
-void adjust_cr(unsigned long mask, unsigned long set)
-{
-        unsigned long flags;
-        mask &= ~CR_A;
-        set &= mask;
-        local_irq_save(flags);
-        cr_no_alignment = (cr_no_alignment & ~mask) | set;
-        cr_alignment = (cr_alignment & ~mask) | set;
-        set_cr((get_cr() & ~mask) | set);
-        local_irq_restore(flags);
-}
-#endif
 #else /* ifdef CONFIG_CPU_CP15 */
 static int __init early_cachepolicy(char *p)
@@ -414,8 +418,17 @@ static void __init build_mem_type_table(void)
                        cachepolicy = CPOLICY_WRITEBACK;
                ecc_mask = 0;
        }
-        if (is_smp())
-                cachepolicy = CPOLICY_WRITEALLOC;
+        if (is_smp()) {
+                if (cachepolicy != CPOLICY_WRITEALLOC) {
+                        pr_warn("Forcing write-allocate cache policy for SMP\n");
+                        cachepolicy = CPOLICY_WRITEALLOC;
+                }
+                if (!(initial_pmd_value & PMD_SECT_S)) {
+                        pr_warn("Forcing shared mappings for SMP\n");
+                        initial_pmd_value |= PMD_SECT_S;
+                }
+        }
        /*
         * Strip out features not present on earlier architectures.
@@ -539,11 +552,12 @@ static void __init build_mem_type_table(void)
                mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
 #endif
-                if (is_smp()) {
+                /*
-                        /*
+                 * If the initial page tables were created with the S bit
-                         * Mark memory with the "shared" attribute
+                 * set, then we need to do the same here for the same
-                         * for SMP systems
+                 * reasons given in early_cachepolicy().
-                         */
+                 */
+                if (initial_pmd_value & PMD_SECT_S) {
                        user_pgprot |= L_PTE_SHARED;
                        kern_pgprot |= L_PTE_SHARED;
                        vecs_pgprot |= L_PTE_SHARED;
@@ -1061,74 +1075,47 @@ phys_addr_t arm_lowmem_limit __initdata = 0;
 void __init sanity_check_meminfo(void)
 {
        phys_addr_t memblock_limit = 0;
-        int i, j, highmem = 0;
+        int highmem = 0;
        phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
+        struct memblock_region *reg;
-        for (i = 0, j = 0; i < meminfo.nr_banks; i++) {
+        for_each_memblock(memory, reg) {
-                struct membank *bank = &meminfo.bank[j];
+                phys_addr_t block_start = reg->base;
-                phys_addr_t size_limit;
+                phys_addr_t block_end = reg->base + reg->size;
+                phys_addr_t size_limit = reg->size;
-                *bank = meminfo.bank[i];
-                size_limit = bank->size;
-                if (bank->start >= vmalloc_limit)
+                if (reg->base >= vmalloc_limit)
                        highmem = 1;
                else
-                        size_limit = vmalloc_limit - bank->start;
+                        size_limit = vmalloc_limit - reg->base;
-                bank->highmem = highmem;
-#ifdef CONFIG_HIGHMEM
+                if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
-                /*
-                 * Split those memory banks which are partially overlapping
+                        if (highmem) {
-                 * the vmalloc area greatly simplifying things later.
+                                pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
-                 */
+                                        &block_start, &block_end);
-                if (!highmem && bank->size > size_limit) {
+                                memblock_remove(reg->base, reg->size);
-                        if (meminfo.nr_banks >= NR_BANKS) {
+                                continue;
-                                printk(KERN_CRIT "NR_BANKS too low, "
-                                                 "ignoring high memory\n");
-                        } else {
-                                memmove(bank + 1, bank,
-                                        (meminfo.nr_banks - i) * sizeof(*bank));
-                                meminfo.nr_banks++;
-                                i++;
-                                bank[1].size -= size_limit;
-                                bank[1].start = vmalloc_limit;
-                                bank[1].highmem = highmem = 1;
-                                j++;
                        }
-                        bank->size = size_limit;
-                }
-#else
-                /*
-                 * Highmem banks not allowed with !CONFIG_HIGHMEM.
-                 */
-                if (highmem) {
-                        printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx "
-                               "(!CONFIG_HIGHMEM).\n",
-                               (unsigned long long)bank->start,
-                               (unsigned long long)bank->start + bank->size - 1);
-                        continue;
-                }
-                /*
+                        if (reg->size > size_limit) {
-                 * Check whether this memory bank would partially overlap
+                                phys_addr_t overlap_size = reg->size - size_limit;
-                 * the vmalloc area.
-                 */
+                                pr_notice("Truncating RAM at %pa-%pa to -%pa",
-                if (bank->size > size_limit) {
+                                      &block_start, &block_end, &vmalloc_limit);
-                        printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx "
+                                memblock_remove(vmalloc_limit, overlap_size);
-                               "to -%.8llx (vmalloc region overlap).\n",
+                                block_end = vmalloc_limit;
-                               (unsigned long long)bank->start,
+                        }
-                               (unsigned long long)bank->start + bank->size - 1,
-                               (unsigned long long)bank->start + size_limit - 1);
-                        bank->size = size_limit;
                }
-#endif
-                if (!bank->highmem) {
-                        phys_addr_t bank_end = bank->start + bank->size;
-                        if (bank_end > arm_lowmem_limit)
+                if (!highmem) {
-                                arm_lowmem_limit = bank_end;
+                        if (block_end > arm_lowmem_limit) {
+                                if (reg->size > size_limit)
+                                        arm_lowmem_limit = vmalloc_limit;
+                                else
+                                        arm_lowmem_limit = block_end;
+                        }
                        /*
                         * Find the first non-section-aligned page, and point
@@ -1144,35 +1131,15 @@ void __init sanity_check_meminfo(void)
                         * occurs before any free memory is mapped.
                         */
                        if (!memblock_limit) {
-                                if (!IS_ALIGNED(bank->start, SECTION_SIZE))
+                                if (!IS_ALIGNED(block_start, SECTION_SIZE))
-                                        memblock_limit = bank->start;
+                                        memblock_limit = block_start;
-                                else if (!IS_ALIGNED(bank_end, SECTION_SIZE))
+                                else if (!IS_ALIGNED(block_end, SECTION_SIZE))
-                                        memblock_limit = bank_end;
+                                        memblock_limit = arm_lowmem_limit;
                        }
-                }
-                j++;
-        }
-#ifdef CONFIG_HIGHMEM
-        if (highmem) {
-                const char *reason = NULL;
-                if (cache_is_vipt_aliasing()) {
-                        /*
-                         * Interactions between kmap and other mappings
-                         * make highmem support with aliasing VIPT caches
-                         * rather difficult.
-                         */
-                        reason = "with VIPT aliasing cache";
-                }
-                if (reason) {
-                        printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n",
-                                reason);
-                        while (j > 0 && meminfo.bank[j - 1].highmem)
-                                j--;
                }
        }
-#endif
-        meminfo.nr_banks = j;
        high_memory = __va(arm_lowmem_limit - 1) + 1;
        /*
@@ -1359,6 +1326,9 @@ static void __init kmap_init(void)
 #ifdef CONFIG_HIGHMEM
        pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
                PKMAP_BASE, _PAGE_KERNEL_TABLE);
+        fixmap_page_table = early_pte_alloc(pmd_off_k(FIXADDR_START),
+                FIXADDR_START, _PAGE_KERNEL_TABLE);
 #endif
 }
@@ -1461,7 +1431,7 @@ void __init early_paging_init(const struct machine_desc *mdesc,
         * just complicate the code.
         */
        flush_cache_louis();
-        dsb();
+        dsb(ishst);
        isb();
        /* remap level 1 table */
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index 55764a7ef1f0..da1874f9f8cf 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -88,30 +88,35 @@ static unsigned long irbar_read(void)
 void __init sanity_check_meminfo_mpu(void)
 {
        int i;
-        struct membank *bank = meminfo.bank;
        phys_addr_t phys_offset = PHYS_OFFSET;
        phys_addr_t aligned_region_size, specified_mem_size, rounded_mem_size;
+        struct memblock_region *reg;
-        /* Initially only use memory continuous from PHYS_OFFSET */
+        bool first = true;
-        if (bank_phys_start(&bank[0]) != phys_offset)
+        phys_addr_t mem_start;
-                panic("First memory bank must be contiguous from PHYS_OFFSET");
+        phys_addr_t mem_end;
-        /* Banks have already been sorted by start address */
+        for_each_memblock(memory, reg) {
-        for (i = 1; i < meminfo.nr_banks; i++) {
+                if (first) {
-                if (bank[i].start <= bank_phys_end(&bank[0]) &&
+                        /*
-                    bank_phys_end(&bank[i]) > bank_phys_end(&bank[0])) {
+                         * Initially only use memory continuous from
-                        bank[0].size = bank_phys_end(&bank[i]) - bank[0].start;
+                         * PHYS_OFFSET */
+                        if (reg->base != phys_offset)
+                                panic("First memory bank must be contiguous from PHYS_OFFSET");
+                        mem_start = reg->base;
+                        mem_end = reg->base + reg->size;
+                        specified_mem_size = reg->size;
+                        first = false;
                } else {
-                        pr_notice("Ignoring RAM after 0x%.8lx. "
+                        /*
-                        "First non-contiguous (ignored) bank start: 0x%.8lx\n",
+                         * memblock auto merges contiguous blocks, remove
-                                (unsigned long)bank_phys_end(&bank[0]),
+                         * all blocks afterwards
-                                (unsigned long)bank_phys_start(&bank[i]));
+                         */
-                        break;
+                        pr_notice("Ignoring RAM after %pa, memory at %pa ignored\n",
+                                  &mem_start, &reg->base);
+                        memblock_remove(reg->base, reg->size);
                }
        }
-        /* All contiguous banks are now merged in to the first bank */
-        meminfo.nr_banks = 1;
-        specified_mem_size = bank[0].size;
        /*
         * MPU has curious alignment requirements: Size must be power of 2, and
@@ -128,23 +133,24 @@ void __init sanity_check_meminfo_mpu(void)
         */
        aligned_region_size = (phys_offset - 1) ^ (phys_offset);
        /* Find the max power-of-two sized region that fits inside our bank */
-        rounded_mem_size = (1 <<  __fls(bank[0].size)) - 1;
+        rounded_mem_size = (1 <<  __fls(specified_mem_size)) - 1;
        /* The actual region size is the smaller of the two */
        aligned_region_size = aligned_region_size < rounded_mem_size
                                ? aligned_region_size + 1
                                : rounded_mem_size + 1;
-        if (aligned_region_size != specified_mem_size)
+        if (aligned_region_size != specified_mem_size) {
-                pr_warn("Truncating memory from 0x%.8lx to 0x%.8lx (MPU region constraints)",
+                pr_warn("Truncating memory from %pa to %pa (MPU region constraints)",
-                                (unsigned long)specified_mem_size,
+                                &specified_mem_size, &aligned_region_size);
-                                (unsigned long)aligned_region_size);
+                memblock_remove(mem_start + aligned_region_size,
+                                specified_mem_size - aligned_round_size);
+                mem_end = mem_start + aligned_region_size;
+        }
-        meminfo.bank[0].size = aligned_region_size;
+        pr_debug("MPU Region from %pa size %pa (end %pa))\n",
-        pr_debug("MPU Region from 0x%.8lx size 0x%.8lx (end 0x%.8lx))\n",
+                &phys_offset, &aligned_region_size, &mem_end);
-                (unsigned long)phys_offset,
-                (unsigned long)aligned_region_size,
-                (unsigned long)bank_phys_end(&bank[0]));
 }
@@ -292,7 +298,7 @@ void __init sanity_check_meminfo(void)
 {
        phys_addr_t end;
        sanity_check_meminfo_mpu();
-        end = bank_phys_end(&meminfo.bank[meminfo.nr_banks - 1]);
+        end = memblock_end_of_DRAM();
        high_memory = __va(end - 1) + 1;
 }
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 01a719e18bb0..22e3ad63500c 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -64,6 +64,14 @@ ENTRY(cpu_v7_switch_mm)
        mov     pc, lr
 ENDPROC(cpu_v7_switch_mm)
+#ifdef __ARMEB__
+#define rl r3
+#define rh r2
+#else
+#define rl r2
+#define rh r3
+#endif
 /*
 * cpu_v7_set_pte_ext(ptep, pte)
 *
@@ -73,13 +81,13 @@ ENDPROC(cpu_v7_switch_mm)
 */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-        tst     r2, #L_PTE_VALID
+        tst     rl, #L_PTE_VALID
        beq     1f
-        tst     r3, #1 << (57 - 32)             @ L_PTE_NONE
+        tst     rh, #1 << (57 - 32)             @ L_PTE_NONE
-        bicne   r2, #L_PTE_VALID
+        bicne   rl, #L_PTE_VALID
        bne     1f
-        tst     r3, #1 << (55 - 32)             @ L_PTE_DIRTY
+        tst     rh, #1 << (55 - 32)             @ L_PTE_DIRTY
-        orreq   r2, #L_PTE_RDONLY
+        orreq   rl, #L_PTE_RDONLY
 1:      strd    r2, r3, [r0]
        ALT_SMP(W(nop))
        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 195731d3813b..3db2c2f04a30 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -169,9 +169,31 @@ ENDPROC(cpu_pj4b_do_idle)
        globl_equ       cpu_pj4b_do_idle,       cpu_v7_do_idle
 #endif
        globl_equ       cpu_pj4b_dcache_clean_area,     cpu_v7_dcache_clean_area
-        globl_equ       cpu_pj4b_do_suspend,    cpu_v7_do_suspend
+#ifdef CONFIG_ARM_CPU_SUSPEND
-        globl_equ       cpu_pj4b_do_resume,     cpu_v7_do_resume
+ENTRY(cpu_pj4b_do_suspend)
-        globl_equ       cpu_pj4b_suspend_size,  cpu_v7_suspend_size
+        stmfd   sp!, {r6 - r10}
+        mrc     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
+        mrc     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
+        mrc     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
+        mrc     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
+        mrc     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
+        stmia   r0!, {r6 - r10}
+        ldmfd   sp!, {r6 - r10}
+        b cpu_v7_do_suspend
+ENDPROC(cpu_pj4b_do_suspend)
+ENTRY(cpu_pj4b_do_resume)
+        ldmia   r0!, {r6 - r10}
+        mcr     p15, 1, r6, c15, c1, 0  @ save CP15 - extra features
+        mcr     p15, 1, r7, c15, c2, 0  @ save CP15 - Aux Func Modes Ctrl 0
+        mcr     p15, 1, r8, c15, c1, 2  @ save CP15 - Aux Debug Modes Ctrl 2
+        mcr     p15, 1, r9, c15, c1, 1  @ save CP15 - Aux Debug Modes Ctrl 1
+        mcr     p15, 0, r10, c9, c14, 0  @ save CP15 - PMC
+        b cpu_v7_do_resume
+ENDPROC(cpu_pj4b_do_resume)
+#endif
+.globl  cpu_pj4b_suspend_size
+.equ    cpu_pj4b_suspend_size, 4 * 14
 #endif
@@ -194,6 +216,7 @@ __v7_cr7mp_setup:
 __v7_ca7mp_setup:
 __v7_ca12mp_setup:
 __v7_ca15mp_setup:
+__v7_ca17mp_setup:
        mov     r10, #0
 1:
 #ifdef CONFIG_SMP
@@ -505,6 +528,16 @@ __v7_ca15mp_proc_info:
        .size   __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
        /*
+         * ARM Ltd. Cortex A17 processor.
+         */
+        .type   __v7_ca17mp_proc_info, #object
+__v7_ca17mp_proc_info:
+        .long   0x410fc0e0
+        .long   0xff0ffff0
+        __v7_proc __v7_ca17mp_setup
+        .size   __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
+        /*
         * Qualcomm Inc. Krait processors.
         */
        .type   __krait_proc_info, #object
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S
index 0c93588fcb91..1ca37c72f12f 100644
--- a/arch/arm/mm/proc-v7m.S
+++ b/arch/arm/mm/proc-v7m.S
@@ -123,6 +123,11 @@ __v7m_setup:
        mov     pc, lr
 ENDPROC(__v7m_setup)
+        .align 2
+__v7m_setup_stack:
+        .space  4 * 8                           @ 8 registers
+__v7m_setup_stack_top:
        define_processor_functions v7m, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
        .section ".rodata"
@@ -152,6 +157,3 @@ __v7m_proc_info:
        .long   nop_cache_fns           @ proc_info_list.cache
        .size   __v7m_proc_info, . - __v7m_proc_info
-__v7m_setup_stack:
-        .space  4 * 8                           @ 8 registers
-__v7m_setup_stack_top:
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index 384a776d8eb2..61b4d705c267 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -40,7 +40,7 @@ static void __iomem *sync32k_cnt_reg;
 static u64 notrace omap_32k_read_sched_clock(void)
 {
-        return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+        return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
 }
 /**
@@ -64,7 +64,7 @@ static void omap_read_persistent_clock(struct timespec *ts)
        spin_lock_irqsave(&read_persistent_clock_lock, flags);
        last_cycles = cycles;
-        cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0;
+        cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0;
        nsecs = clocksource_cyc2ns(cycles - last_cycles,
                                        persistent_mult, persistent_shift);
@@ -95,7 +95,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase)
         * The 'SCHEME' bits(30-31) of the revision register is used
         * to identify the version.
         */
-        if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) &
+        if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) &
                                                OMAP2_32KSYNCNT_REV_SCHEME)
                sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH;
        else
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index aa7ebc6bcd65..48b69de89a5d 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -85,12 +85,12 @@ static void dbg_led_set(struct led_classdev *cdev,
        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
        u16 reg;
-        reg = __raw_readw(&fpga->leds);
+        reg = readw_relaxed(&fpga->leds);
        if (b != LED_OFF)
                reg |= led->mask;
        else
                reg &= ~led->mask;
-        __raw_writew(reg, &fpga->leds);
+        writew_relaxed(reg, &fpga->leds);
 }
 static enum led_brightness dbg_led_get(struct led_classdev *cdev)
@@ -98,7 +98,7 @@ static enum led_brightness dbg_led_get(struct led_classdev *cdev)
        struct dbg_led *led = container_of(cdev, struct dbg_led, cdev);
        u16 reg;
-        reg = __raw_readw(&fpga->leds);
+        reg = readw_relaxed(&fpga->leds);
        return (reg & led->mask) ? LED_FULL : LED_OFF;
 }
@@ -112,7 +112,7 @@ static int fpga_probe(struct platform_device *pdev)
                return -ENODEV;
        fpga = ioremap(iomem->start, resource_size(iomem));
-        __raw_writew(0xff, &fpga->leds);
+        writew_relaxed(0xff, &fpga->leds);
        for (i = 0; i < ARRAY_SIZE(dbg_leds); i++) {
                struct dbg_led *led;
@@ -138,15 +138,15 @@ static int fpga_probe(struct platform_device *pdev)
 static int fpga_suspend_noirq(struct device *dev)
 {
-        fpga_led_state = __raw_readw(&fpga->leds);
+        fpga_led_state = readw_relaxed(&fpga->leds);
-        __raw_writew(0xff, &fpga->leds);
+        writew_relaxed(0xff, &fpga->leds);
        return 0;
 }
 static int fpga_resume_noirq(struct device *dev)
 {
-        __raw_writew(~fpga_led_state, &fpga->leds);
+        writew_relaxed(~fpga_led_state, &fpga->leds);
        return 0;
 }
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 5f5b975887fc..b5608b1f9fbd 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -70,6 +70,7 @@ static u32 errata;
 static struct omap_dma_global_context_registers {
        u32 dma_irqenable_l0;
+        u32 dma_irqenable_l1;
        u32 dma_ocp_sysconfig;
        u32 dma_gcr;
 } omap_dma_global_context;
@@ -1973,10 +1974,17 @@ static struct irqaction omap24xx_dma_irq;
 /*----------------------------------------------------------------------------*/
+/*
+ * Note that we are currently using only IRQENABLE_L0 and L1.
+ * As the DSP may be using IRQENABLE_L2 and L3, let's not
+ * touch those for now.
+ */
 void omap_dma_global_context_save(void)
 {
        omap_dma_global_context.dma_irqenable_l0 =
                p->dma_read(IRQENABLE_L0, 0);
+        omap_dma_global_context.dma_irqenable_l1 =
+                p->dma_read(IRQENABLE_L1, 0);
        omap_dma_global_context.dma_ocp_sysconfig =
                p->dma_read(OCP_SYSCONFIG, 0);
        omap_dma_global_context.dma_gcr = p->dma_read(GCR, 0);
@@ -1991,6 +1999,8 @@ void omap_dma_global_context_restore(void)
                OCP_SYSCONFIG, 0);
        p->dma_write(omap_dma_global_context.dma_irqenable_l0,
                IRQENABLE_L0, 0);
+        p->dma_write(omap_dma_global_context.dma_irqenable_l1,
+                IRQENABLE_L1, 0);
        if (IS_DMA_ERRATA(DMA_ROMCODE_BUG))
                p->dma_write(0x3 , IRQSTATUS_L0, 0);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 869254cebf84..db10169a08de 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -103,7 +103,7 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
                                timer->context.tmar);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
                                timer->context.tsicr);
-        __raw_writel(timer->context.tier, timer->irq_ena);
+        writel_relaxed(timer->context.tier, timer->irq_ena);
        omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG,
                                timer->context.tclr);
 }
@@ -699,9 +699,9 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
        omap_dm_timer_enable(timer);
        if (timer->revision == 1)
-                l = __raw_readl(timer->irq_ena) & ~mask;
+                l = readl_relaxed(timer->irq_ena) & ~mask;
-        __raw_writel(l, timer->irq_dis);
+        writel_relaxed(l, timer->irq_dis);
        l = omap_dm_timer_read_reg(timer, OMAP_TIMER_WAKEUP_EN_REG) & ~mask;
        omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, l);
@@ -722,7 +722,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
                return 0;
        }
-        l = __raw_readl(timer->irq_stat);
+        l = readl_relaxed(timer->irq_stat);
        return l;
 }
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 2861b155485a..dd79f3005cdf 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -280,20 +280,20 @@ static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
                                                int posted)
 {
        if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
                        cpu_relax();
-        return __raw_readl(timer->func_base + (reg & 0xff));
+        return readl_relaxed(timer->func_base + (reg & 0xff));
 }
 static inline void __omap_dm_timer_write(struct omap_dm_timer *timer,
                                        u32 reg, u32 val, int posted)
 {
        if (posted)
-                while (__raw_readl(timer->pend) & (reg >> WPSHIFT))
+                while (readl_relaxed(timer->pend) & (reg >> WPSHIFT))
                        cpu_relax();
-        __raw_writel(val, timer->func_base + (reg & 0xff));
+        writel_relaxed(val, timer->func_base + (reg & 0xff));
 }
 static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
@@ -301,7 +301,7 @@ static inline void __omap_dm_timer_init_regs(struct omap_dm_timer *timer)
        u32 tidr;
        /* Assume v1 ip if bits [31:16] are zero */
-        tidr = __raw_readl(timer->io_base);
+        tidr = readl_relaxed(timer->io_base);
        if (!(tidr >> 16)) {
                timer->revision = 1;
                timer->irq_stat = timer->io_base + OMAP_TIMER_V1_STAT_OFFSET;
@@ -385,7 +385,7 @@ static inline void __omap_dm_timer_stop(struct omap_dm_timer *timer,
        }
        /* Ack possibly pending interrupt */
-        __raw_writel(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
+        writel_relaxed(OMAP_TIMER_INT_OVERFLOW, timer->irq_stat);
 }
 static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
@@ -399,7 +399,7 @@ static inline void __omap_dm_timer_load_start(struct omap_dm_timer *timer,
 static inline void __omap_dm_timer_int_enable(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __raw_writel(value, timer->irq_ena);
+        writel_relaxed(value, timer->irq_ena);
        __omap_dm_timer_write(timer, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
 }
@@ -412,7 +412,7 @@ __omap_dm_timer_read_counter(struct omap_dm_timer *timer, int posted)
 static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
                                                unsigned int value)
 {
-        __raw_writel(value, timer->irq_stat);
+        writel_relaxed(value, timer->irq_stat);
 }
 #endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 6816192a7561..b61a3bcc2fa8 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -597,51 +597,3 @@ void __init orion_gpio_init(struct device_node *np,
        orion_gpio_chip_count++;
 }
-#ifdef CONFIG_OF
-static void __init orion_gpio_of_init_one(struct device_node *np,
-                                          int irq_gpio_base)
-{
-        int ngpio, gpio_base, mask_offset;
-        void __iomem *base;
-        int ret, i;
-        int irqs[4];
-        int secondary_irq_base;
-        ret = of_property_read_u32(np, "ngpio", &ngpio);
-        if (ret)
-                goto out;
-        ret = of_property_read_u32(np, "mask-offset", &mask_offset);
-        if (ret == -EINVAL)
-                mask_offset = 0;
-        else
-                goto out;
-        base = of_iomap(np, 0);
-        if (!base)
-                goto out;
-        secondary_irq_base = irq_gpio_base + (32 * orion_gpio_chip_count);
-        gpio_base = 32 * orion_gpio_chip_count;
-        /* Get the interrupt numbers. Each chip can have up to 4
-         * interrupt handlers, with each handler dealing with 8 GPIO
-         * pins. */
-        for (i = 0; i < 4; i++)
-                irqs[i] = irq_of_parse_and_map(np, i);
-        orion_gpio_init(np, gpio_base, ngpio, base, mask_offset,
-                        secondary_irq_base, irqs);
-        return;
-out:
-        pr_err("%s: %s: missing mandatory property\n", __func__, np->name);
-}
-void __init orion_gpio_of_init(int irq_gpio_base)
-{
-        struct device_node *np;
-        for_each_compatible_node(np, NULL, "marvell,orion-gpio")
-                orion_gpio_of_init_one(np, irq_gpio_base);
-}
-#endif
diff --git a/arch/arm/plat-orion/include/plat/irq.h b/arch/arm/plat-orion/include/plat/irq.h
index 50547e417936..96be19e9bd93 100644
--- a/arch/arm/plat-orion/include/plat/irq.h
+++ b/arch/arm/plat-orion/include/plat/irq.h
@@ -12,5 +12,4 @@
 #define __PLAT_IRQ_H
 void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
-void __init orion_dt_init_irq(void);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/orion-gpio.h b/arch/arm/plat-orion/include/plat/orion-gpio.h
index 614dcac9dc52..e763988b04b9 100644
--- a/arch/arm/plat-orion/include/plat/orion-gpio.h
+++ b/arch/arm/plat-orion/include/plat/orion-gpio.h
@@ -33,5 +33,4 @@ void __init orion_gpio_init(struct device_node *np,
                            int secondary_irq_base,
                            int irq[4]);
-void __init orion_gpio_of_init(int irq_gpio_base);
 #endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 807df142444b..8c1fc06007c0 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -20,47 +20,6 @@
 #include <plat/orion-gpio.h>
 #include <mach/bridge-regs.h>
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-/*
- * Compiling with both non-DT and DT support enabled, will
- * break asm irq handler used by non-DT boards. Therefore,
- * we provide a C-style irq handler even for non-DT boards,
- * if MULTI_IRQ_HANDLER is set.
- *
- * Notes:
- * - this is prepared for Kirkwood and Dove only, update
- *   accordingly if you add Orion5x or MV78x00.
- * - Orion5x uses different macro names and has only one
- *   set of CAUSE/MASK registers.
- * - MV78x00 uses the same macro names but has a third
- *   set of CAUSE/MASK registers.
- *
- */
-static void __iomem *orion_irq_base = IRQ_VIRT_BASE;
-asmlinkage void
-__exception_irq_entry orion_legacy_handle_irq(struct pt_regs *regs)
-{
-        u32 stat;
-        stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_LOW_OFF);
-        stat &= readl_relaxed(orion_irq_base + IRQ_MASK_LOW_OFF);
-        if (stat) {
-                unsigned int hwirq = __fls(stat);
-                handle_IRQ(hwirq, regs);
-                return;
-        }
-        stat = readl_relaxed(orion_irq_base + IRQ_CAUSE_HIGH_OFF);
-        stat &= readl_relaxed(orion_irq_base + IRQ_MASK_HIGH_OFF);
-        if (stat) {
-                unsigned int hwirq = 32 + __fls(stat);
-                handle_IRQ(hwirq, regs);
-                return;
-        }
-}
-#endif
 void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
 {
        struct irq_chip_generic *gc;
@@ -78,40 +37,4 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
        ct->chip.irq_unmask = irq_gc_mask_set_bit;
        irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-        set_handle_irq(orion_legacy_handle_irq);
-#endif
-}
-#ifdef CONFIG_OF
-static int __init orion_add_irq_domain(struct device_node *np,
-                                       struct device_node *interrupt_parent)
-{
-        int i = 0;
-        void __iomem *base;
-        do {
-                base = of_iomap(np, i);
-                if (base) {
-                        orion_irq_init(i * 32, base + 0x04);
-                        i++;
-                }
-        } while (base);
-        irq_domain_add_legacy(np, i * 32, 0, 0,
-                              &irq_domain_simple_ops, NULL);
-        return 0;
-}
-static const struct of_device_id orion_irq_match[] = {
-        { .compatible = "marvell,orion-intc",
-          .data = orion_add_irq_domain, },
-        {},
-};
-void __init orion_dt_init_irq(void)
-{
-        of_irq_init(orion_irq_match);
 }
-#endif
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 25c826ed3b65..5e5beaa9ae15 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -4,6 +4,9 @@
 #
 # Licensed under GPLv2
+ccflags-$(CONFIG_ARCH_MULTI_V7) += -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_EXYNOS)   += -I$(srctree)/arch/arm/mach-exynos/include
 obj-y                           :=
 obj-m                           :=
 obj-n                           := dummy.o
diff --git a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
index 7231c8e4975e..72d4178ad23b 100644
--- a/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
+++ b/arch/arm/plat-samsung/include/plat/cpu-freq-core.h
@@ -119,6 +119,7 @@ struct s3c_plltab {
 struct s3c_cpufreq_config {
        struct s3c_freq         freq;
        struct s3c_freq         max;
+        struct clk              *mpll;
        struct cpufreq_frequency_table pll;
        struct s3c_clkdivs      divs;
        struct s3c_cpufreq_info *info;  /* for core, not drivers */
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5992b8dd9b89..5a237db9f9eb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -43,16 +43,6 @@ extern unsigned long samsung_cpu_id;
 #define S5PV210_CPU_ID          0x43110000
 #define S5PV210_CPU_MASK        0xFFFFF000
-#define EXYNOS4210_CPU_ID       0x43210000
-#define EXYNOS4212_CPU_ID       0x43220000
-#define EXYNOS4412_CPU_ID       0xE4412200
-#define EXYNOS4_CPU_MASK        0xFFFE0000
-#define EXYNOS5250_SOC_ID       0x43520000
-#define EXYNOS5420_SOC_ID       0xE5420000
-#define EXYNOS5440_SOC_ID       0xE5440000
-#define EXYNOS5_SOC_MASK        0xFFFFF000
 #define IS_SAMSUNG_CPU(name, id, mask)          \
 static inline int is_samsung_##name(void)       \
 {                                               \
@@ -68,12 +58,6 @@ IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
 IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
 IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
-IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
-IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
-IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
    defined(CONFIG_CPU_S3C2416) || defined(CONFIG_CPU_S3C2440) || \
@@ -126,50 +110,6 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
 # define soc_is_s5pv210()       0
 #endif
-#if defined(CONFIG_CPU_EXYNOS4210)
-# define soc_is_exynos4210()    is_samsung_exynos4210()
-#else
-# define soc_is_exynos4210()    0
-#endif
-#if defined(CONFIG_SOC_EXYNOS4212)
-# define soc_is_exynos4212()    is_samsung_exynos4212()
-#else
-# define soc_is_exynos4212()    0
-#endif
-#if defined(CONFIG_SOC_EXYNOS4412)
-# define soc_is_exynos4412()    is_samsung_exynos4412()
-#else
-# define soc_is_exynos4412()    0
-#endif
-#define EXYNOS4210_REV_0        (0x0)
-#define EXYNOS4210_REV_1_0      (0x10)
-#define EXYNOS4210_REV_1_1      (0x11)
-#if defined(CONFIG_SOC_EXYNOS5250)
-# define soc_is_exynos5250()    is_samsung_exynos5250()
-#else
-# define soc_is_exynos5250()    0
-#endif
-#if defined(CONFIG_SOC_EXYNOS5420)
-# define soc_is_exynos5420()    is_samsung_exynos5420()
-#else
-# define soc_is_exynos5420()    0
-#endif
-#if defined(CONFIG_SOC_EXYNOS5440)
-# define soc_is_exynos5440()    is_samsung_exynos5440()
-#else
-# define soc_is_exynos5440()    0
-#endif
-#define soc_is_exynos4() (soc_is_exynos4210() || soc_is_exynos4212() || \
-                          soc_is_exynos4412())
-#define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5420())
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 #ifndef KHZ
@@ -239,7 +179,6 @@ extern struct bus_type s3c2443_subsys;
 extern struct bus_type s3c6410_subsys;
 extern struct bus_type s5p64x0_subsys;
 extern struct bus_type s5pv210_subsys;
-extern struct bus_type exynos_subsys;
 extern void (*s5pc1xx_idle)(void);
diff --git a/arch/arm/plat-samsung/s5p-dev-mfc.c b/arch/arm/plat-samsung/s5p-dev-mfc.c
index 98087b655df0..469b86260fe3 100644
--- a/arch/arm/plat-samsung/s5p-dev-mfc.c
+++ b/arch/arm/plat-samsung/s5p-dev-mfc.c
@@ -125,8 +125,8 @@ device_initcall(s5p_mfc_memory_init);
 int __init s5p_fdt_alloc_mfc_mem(unsigned long node, const char *uname,
                                int depth, void *data)
 {
-        __be32 *prop;
+        const __be32 *prop;
-        unsigned long len;
+        int len;
        struct s5p_mfc_dt_meminfo mfc_mem;
        if (!data)
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S
index c5001659bdf8..25c68ceb9e2b 100644
--- a/arch/arm/plat-samsung/s5p-sleep.S
+++ b/arch/arm/plat-samsung/s5p-sleep.S
@@ -22,7 +22,6 @@
 */
 #include <linux/linkage.h>
-#include <asm/asm-offsets.h>
        .data
        .align
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 2c4332b9f948..fce41e93b6a4 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -6,12 +6,6 @@ config PLAT_VERSATILE_CLOCK
 config PLAT_VERSATILE_CLCD
        bool
-config PLAT_VERSATILE_LEDS
-        def_bool y if NEW_LEDS
-        depends on ARCH_REALVIEW || ARCH_VERSATILE
-        select LEDS_CLASS
-        select LEDS_TRIGGERS
 config PLAT_VERSATILE_SCHED_CLOCK
        def_bool y
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index f88d448b629c..2e0c472958ae 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -2,6 +2,5 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
-obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
 obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
 obj-$(CONFIG_SMP) += headsmp.o platsmp.o
diff --git a/arch/arm/plat-versatile/leds.c b/arch/arm/plat-versatile/leds.c
deleted file mode 100644
index d2490d00b46c..000000000000
--- a/arch/arm/plat-versatile/leds.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Driver for the 8 user LEDs found on the RealViews and Versatiles
- * Based on DaVinci's DM365 board code
- *
- * License terms: GNU General Public License (GPL) version 2
- * Author: Linus Walleij <triad@df.lth.se>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/leds.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#ifdef VERSATILE_SYS_BASE
-#define LEDREG  (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_LED_OFFSET)
-#endif
-#ifdef REALVIEW_SYS_BASE
-#define LEDREG  (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_LED_OFFSET)
-#endif
-struct versatile_led {
-        struct led_classdev     cdev;
-        u8                      mask;
-};
-/*
- * The triggers lines up below will only be used if the
- * LED triggers are compiled in.
- */
-static const struct {
-        const char *name;
-        const char *trigger;
-} versatile_leds[] = {
-        { "versatile:0", "heartbeat", },
-        { "versatile:1", "mmc0", },
-        { "versatile:2", "cpu0" },
-        { "versatile:3", "cpu1" },
-        { "versatile:4", "cpu2" },
-        { "versatile:5", "cpu3" },
-        { "versatile:6", },
-        { "versatile:7", },
-};
-static void versatile_led_set(struct led_classdev *cdev,
-                              enum led_brightness b)
-{
-        struct versatile_led *led = container_of(cdev,
-                                                 struct versatile_led, cdev);
-        u32 reg = readl(LEDREG);
-        if (b != LED_OFF)
-                reg |= led->mask;
-        else
-                reg &= ~led->mask;
-        writel(reg, LEDREG);
-}
-static enum led_brightness versatile_led_get(struct led_classdev *cdev)
-{
-        struct versatile_led *led = container_of(cdev,
-                                                 struct versatile_led, cdev);
-        u32 reg = readl(LEDREG);
-        return (reg & led->mask) ? LED_FULL : LED_OFF;
-}
-static int __init versatile_leds_init(void)
-{
-        int i;
-        /* All ON */
-        writel(0xff, LEDREG);
-        for (i = 0; i < ARRAY_SIZE(versatile_leds); i++) {
-                struct versatile_led *led;
-                led = kzalloc(sizeof(*led), GFP_KERNEL);
-                if (!led)
-                        break;
-                led->cdev.name = versatile_leds[i].name;
-                led->cdev.brightness_set = versatile_led_set;
-                led->cdev.brightness_get = versatile_led_get;
-                led->cdev.default_trigger = versatile_leds[i].trigger;
-                led->mask = BIT(i);
-                if (led_classdev_register(NULL, &led->cdev) < 0) {
-                        kfree(led);
-                        break;
-                }
-        }
-        return 0;
-}
-/*
- * Since we may have triggers on any subsystem, defer registration
- * until after subsystem_init.
- */
-fs_initcall(versatile_leds_init);
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index f0759e70fb86..fe6ca574d093 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -22,11 +22,10 @@
 @  r9  = normal "successful" return address
 @  r10 = this threads thread_info structure
 @  lr  = unrecognised instruction return address
-@  IRQs disabled.
+@  IRQs enabled.
 @
 ENTRY(do_vfp)
        inc_preempt_count r10, r4
-        enable_irq
        ldr     r4, .LCvfp
        ldr     r11, [r10, #TI_CPU]     @ CPU number
        add     r10, r10, #TI_VFPSTATE  @ r10 = workspace
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index b96723e258a0..1e632430570b 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -339,6 +339,14 @@ static int __init xen_pm_init(void)
 }
 late_initcall(xen_pm_init);
+/* empty stubs */
+void xen_arch_pre_suspend(void) { }
+void xen_arch_post_suspend(int suspend_cancelled) { }
+void xen_timer_resume(void) { }
+void xen_arch_resume(void) { }
 /* In the hypervisor.S file. */
 EXPORT_SYMBOL_GPL(HYPERVISOR_event_channel_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_grant_table_op);
@@ -350,4 +358,5 @@ EXPORT_SYMBOL_GPL(HYPERVISOR_memory_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_physdev_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_vcpu_op);
 EXPORT_SYMBOL_GPL(HYPERVISOR_tmem_op);
+EXPORT_SYMBOL_GPL(HYPERVISOR_multicall);
 EXPORT_SYMBOL_GPL(privcmd_call);
diff --git a/arch/arm/xen/hypercall.S b/arch/arm/xen/hypercall.S
index d1cf7b7c2200..44e3a5f10c4c 100644
--- a/arch/arm/xen/hypercall.S
+++ b/arch/arm/xen/hypercall.S
@@ -89,6 +89,7 @@ HYPERCALL2(memory_op);
 HYPERCALL2(physdev_op);
 HYPERCALL3(vcpu_op);
 HYPERCALL1(tmem_op);
+HYPERCALL2(multicall);
 ENTRY(privcmd_call)
        stmdb sp!, {r4}