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-rw-r--r--arch/arm/mach-tegra/gpio.c4
-rw-r--r--arch/arm/mach-tegra/include/mach/clk.h2
-rw-r--r--arch/arm/mach-tegra/include/mach/clkdev.h2
-rw-r--r--arch/arm/mach-tegra/irq.c18
4 files changed, 15 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index bd066206e110..ad8048801513 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -207,9 +207,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
207 spin_unlock_irqrestore(&bank->lvl_lock[port], flags); 207 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
208 208
209 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 209 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
210 __set_irq_handler_unlocked(irq, handle_level_irq); 210 __set_irq_handler_unlocked(d->irq, handle_level_irq);
211 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 211 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
212 __set_irq_handler_unlocked(irq, handle_edge_irq); 212 __set_irq_handler_unlocked(d->irq, handle_edge_irq);
213 213
214 return 0; 214 return 0;
215} 215}
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d7723955dac7..a217f68ba57c 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -20,6 +20,8 @@
20#ifndef __MACH_CLK_H 20#ifndef __MACH_CLK_H
21#define __MACH_CLK_H 21#define __MACH_CLK_H
22 22
23struct clk;
24
23void tegra_periph_reset_deassert(struct clk *c); 25void tegra_periph_reset_deassert(struct clk *c);
24void tegra_periph_reset_assert(struct clk *c); 26void tegra_periph_reset_assert(struct clk *c);
25 27
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-tegra/include/mach/clkdev.h
index 412f5c63e65a..66cd3f4fc896 100644
--- a/arch/arm/mach-tegra/include/mach/clkdev.h
+++ b/arch/arm/mach-tegra/include/mach/clkdev.h
@@ -20,6 +20,8 @@
20#ifndef __MACH_CLKDEV_H 20#ifndef __MACH_CLKDEV_H
21#define __MACH_CLKDEV_H 21#define __MACH_CLKDEV_H
22 22
23struct clk;
24
23static inline int __clk_get(struct clk *clk) 25static inline int __clk_get(struct clk *clk)
24{ 26{
25 return 1; 27 return 1;
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index de7dfad6f769..17c74d21077c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -46,24 +46,24 @@
46#define ICTLR_COP_IER_CLR 0x38 46#define ICTLR_COP_IER_CLR 0x38
47#define ICTLR_COP_IEP_CLASS 0x3c 47#define ICTLR_COP_IEP_CLASS 0x3c
48 48
49static void (*gic_mask_irq)(struct irq_data *d); 49static void (*tegra_gic_mask_irq)(struct irq_data *d);
50static void (*gic_unmask_irq)(struct irq_data *d); 50static void (*tegra_gic_unmask_irq)(struct irq_data *d);
51 51
52#define irq_to_ictlr(irq) (((irq)-32) >> 5) 52#define irq_to_ictlr(irq) (((irq) - 32) >> 5)
53static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE); 53static void __iomem *tegra_ictlr_base = IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE);
54#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr)*0x100) 54#define ictlr_to_virt(ictlr) (tegra_ictlr_base + (ictlr) * 0x100)
55 55
56static void tegra_mask(struct irq_data *d) 56static void tegra_mask(struct irq_data *d)
57{ 57{
58 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); 58 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
59 gic_mask_irq(d); 59 tegra_gic_mask_irq(d);
60 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_CLR); 60 writel(1 << (d->irq & 31), addr+ICTLR_CPU_IER_CLR);
61} 61}
62 62
63static void tegra_unmask(struct irq_data *d) 63static void tegra_unmask(struct irq_data *d)
64{ 64{
65 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq)); 65 void __iomem *addr = ictlr_to_virt(irq_to_ictlr(d->irq));
66 gic_unmask_irq(d); 66 tegra_gic_unmask_irq(d);
67 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET); 67 writel(1<<(d->irq&31), addr+ICTLR_CPU_IER_SET);
68} 68}
69 69
@@ -98,8 +98,8 @@ void __init tegra_init_irq(void)
98 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 98 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
99 99
100 gic = get_irq_chip(29); 100 gic = get_irq_chip(29);
101 gic_unmask_irq = gic->irq_unmask; 101 tegra_gic_unmask_irq = gic->irq_unmask;
102 gic_mask_irq = gic->irq_mask; 102 tegra_gic_mask_irq = gic->irq_mask;
103 tegra_irq.irq_ack = gic->irq_ack; 103 tegra_irq.irq_ack = gic->irq_ack;
104#ifdef CONFIG_SMP 104#ifdef CONFIG_SMP
105 tegra_irq.irq_set_affinity = gic->irq_set_affinity; 105 tegra_irq.irq_set_affinity = gic->irq_set_affinity;