147 files changed, 8332 insertions, 2606 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 26d45e5b636b..166efa2a19cd 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
           visible impact on the overall performance or power consumption of the
           processor.
 
+config ARM_ERRATA_751472
+        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 751472 Cortex-A9 (prior
+          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
+          completion of a following broadcasted operation if the second
+          operation is received by a CPU before the ICIALLUIS has completed,
+          potentially leading to corrupted entries in the cache or TLB.
+
+config ARM_ERRATA_753970
+        bool "ARM errata: cache sync operation may be faulty"
+        depends on CACHE_PL310
+        help
+          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+
+          Under some condition the effect of cache sync operation on
+          the store buffer still remains when the operation completes.
+          This means that the store buffer is always asked to drain and
+          this prevents it from merging any further writes. The workaround
+          is to replace the normal offset of cache sync operation (0x730)
+          by another offset targeting an unmapped PL310 register 0x740.
+          This has the same effect as the cache sync operation: store buffer
+          drain and waiting for all buffers empty.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1adfedd6..6f7b29294c80 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
 
-OBJCOPYFLAGS    :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
+OBJCOPYFLAGS    :=-O binary -R .comment -S
 GZFLAGS         :=-9
 #KBUILD_CFLAGS  +=-pipe
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index ab204db594d3..c6028967d336 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,3 +1,7 @@
 font.c
-piggy.gz
+lib1funcs.S
+piggy.gzip
+piggy.lzo
+piggy.lzma
+vmlinux
 vmlinux.lds
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index ae890caa17a7..019fb7c67dc3 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -58,6 +58,7 @@ CONFIG_ARM_ERRATA_411920=y
 CONFIG_NO_HZ=y
 CONFIG_HIGH_RES_TIMERS=y
 CONFIG_SMP=y
+CONFIG_NR_CPUS=2
 # CONFIG_LOCAL_TIMERS is not set
 CONFIG_AEABI=y
 CONFIG_LEDS=y
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5aeec1e1735c..16bd48031583 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -36,6 +36,7 @@
 #define L2X0_RAW_INTR_STAT              0x21C
 #define L2X0_INTR_CLEAR                 0x220
 #define L2X0_CACHE_SYNC                 0x730
+#define L2X0_DUMMY_REG                  0x740
 #define L2X0_INV_LINE_PA                0x770
 #define L2X0_INV_WAY                    0x77C
 #define L2X0_CLEAN_LINE_PA              0x7B0
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index 721847dc68ab..e0d1c0cfa548 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -58,6 +58,9 @@
 
 static inline void sysctl_soft_reset(void __iomem *base)
 {
+        /* switch to slow mode */
+        writel(0x2, base + SCCTRL);
+
         /* writing any value to SCSYSSTAT reg will reset system */
         writel(0, base + SCSYSSTAT);
 }
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f41a6f57cd12..82dfe5d0c41e 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -18,16 +18,34 @@
 #define __ASMARM_TLB_H
 
 #include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
 
 #ifndef CONFIG_MMU
 
 #include <linux/pagemap.h>
+
+#define tlb_flush(tlb)  ((void) tlb)
+
 #include <asm-generic/tlb.h>
 
 #else /* !CONFIG_MMU */
 
+#include <linux/swap.h>
 #include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+/*
+ * We need to delay page freeing for SMP as other CPUs can access pages
+ * which have been removed but not yet had their TLB entries invalidated.
+ * Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
+ * we need to apply this same delaying tactic to ensure correct operation.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
+#define tlb_fast_mode(tlb)      0
+#define FREE_PTE_NR             500
+#else
+#define tlb_fast_mode(tlb)      1
+#define FREE_PTE_NR             0
+#endif
 
 /*
  * TLB handling.  This allows us to remove pages from the page
@@ -36,12 +54,58 @@
 struct mmu_gather {
         struct mm_struct        *mm;
         unsigned int            fullmm;
+        struct vm_area_struct   *vma;
         unsigned long           range_start;
         unsigned long           range_end;
+        unsigned int            nr;
+        struct page             *pages[FREE_PTE_NR];
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 
+/*
+ * This is unnecessarily complex.  There's three ways the TLB shootdown
+ * code is used:
+ *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
+ *     tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.
+ *  2. Unmapping all vmas.  See exit_mmap().
+ *     tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.  Additionally, page tables will be freed.
+ *  3. Unmapping argument pages.  See shift_arg_pages().
+ *     tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
+ *     tlb->vma will be NULL.
+ */
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+        if (tlb->fullmm || !tlb->vma)
+                flush_tlb_mm(tlb->mm);
+        else if (tlb->range_end > 0) {
+                flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
+                tlb->range_start = TASK_SIZE;
+                tlb->range_end = 0;
+        }
+}
+
+static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
+{
+        if (!tlb->fullmm) {
+                if (addr < tlb->range_start)
+                        tlb->range_start = addr;
+                if (addr + PAGE_SIZE > tlb->range_end)
+                        tlb->range_end = addr + PAGE_SIZE;
+        }
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+        tlb_flush(tlb);
+        if (!tlb_fast_mode(tlb)) {
+                free_pages_and_swap_cache(tlb->pages, tlb->nr);
+                tlb->nr = 0;
+        }
+}
+
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
@@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 
         tlb->mm = mm;
         tlb->fullmm = full_mm_flush;
+        tlb->vma = NULL;
+        tlb->nr = 0;
 
         return tlb;
 }
@@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        if (tlb->fullmm)
-                flush_tlb_mm(tlb->mm);
+        tlb_flush_mmu(tlb);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
@@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 static inline void
 tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
 {
-        if (!tlb->fullmm) {
-                if (addr < tlb->range_start)
-                        tlb->range_start = addr;
-                if (addr + PAGE_SIZE > tlb->range_end)
-                        tlb->range_end = addr + PAGE_SIZE;
-        }
+        tlb_add_flush(tlb, addr);
 }
 
 /*
@@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
         if (!tlb->fullmm) {
                 flush_cache_range(vma, vma->vm_start, vma->vm_end);
+                tlb->vma = vma;
                 tlb->range_start = TASK_SIZE;
                 tlb->range_end = 0;
         }
@@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 static inline void
 tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
-        if (!tlb->fullmm && tlb->range_end > 0)
-                flush_tlb_range(vma, tlb->range_start, tlb->range_end);
+        if (!tlb->fullmm)
+                tlb_flush(tlb);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        if (tlb_fast_mode(tlb)) {
+                free_page_and_swap_cache(page);
+        } else {
+                tlb->pages[tlb->nr++] = page;
+                if (tlb->nr >= FREE_PTE_NR)
+                        tlb_flush_mmu(tlb);
+        }
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
+        unsigned long addr)
+{
+        pgtable_page_dtor(pte);
+        tlb_add_flush(tlb, addr);
+        tlb_remove_page(tlb, pte);
 }
 
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
-#define pte_free_tlb(tlb, ptep, addr)   pte_free((tlb)->mm, ptep)
+#define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
 
 #define tlb_migrate_finish(mm)          do { } while (0)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index ce7378ea15a2..d2005de383b8 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -10,12 +10,7 @@
 #ifndef _ASMARM_TLBFLUSH_H
 #define _ASMARM_TLBFLUSH_H
 
-
-#ifndef CONFIG_MMU
-
-#define tlb_flush(tlb)  ((void) tlb)
-
-#else /* CONFIG_MMU */
+#ifdef CONFIG_MMU
 
 #include <asm/glue.h>
 
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 2c1f0050c9c4..8f6ed43861f1 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
                 return space_cccc_1100_010x(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x0c400000) {
+        } else if ((insn & 0x0e000000) == 0x0c000000) {
 
                 return space_cccc_110x(insn, asi);
 
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index b8af96ea62e6..2c79eec19262 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -97,28 +97,34 @@ set_irq_affinity(int irq,
                            irq, cpu);
         return err;
 #else
-        return 0;
+        return -EINVAL;
 #endif
 }
 
 static int
 init_cpu_pmu(void)
 {
-        int i, err = 0;
+        int i, irqs, err = 0;
         struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
 
-        if (!pdev) {
-                err = -ENODEV;
-                goto out;
-        }
+        if (!pdev)
+                return -ENODEV;
+
+        irqs = pdev->num_resources;
+
+        /*
+         * If we have a single PMU interrupt that we can't shift, assume that
+         * we're running on a uniprocessor machine and continue.
+         */
+        if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
+                return 0;
 
-        for (i = 0; i < pdev->num_resources; ++i) {
+        for (i = 0; i < irqs; ++i) {
                 err = set_irq_affinity(platform_get_irq(pdev, i), i);
                 if (err)
                         break;
         }
 
-out:
         return err;
 }
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 420b8d6485d6..5ea4fb718b97 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -226,8 +226,8 @@ int cpu_architecture(void)
                  * Register 0 and check for VMSAv7 or PMSAv7 */
                 asm("mrc        p15, 0, %0, c0, c1, 4"
                     : "=r" (mmfr0));
-                if ((mmfr0 & 0x0000000f) == 0x00000003 ||
-                    (mmfr0 & 0x000000f0) == 0x00000030)
+                if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
+                    (mmfr0 & 0x000000f0) >= 0x00000030)
                         cpu_arch = CPU_ARCH_ARMv7;
                 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
                          (mmfr0 & 0x000000f0) == 0x00000020)
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 907d5a620bca..abaf8445ce25 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
         unsigned long handler = (unsigned long)ka->sa.sa_handler;
         unsigned long retcode;
         int thumb = 0;
-        unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
+        unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
+
+        cpsr |= PSR_ENDSTATE;
 
         /*
          * Maybe we need to deliver a 32-bit signal to a 26-bit task.
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 86b66f3f2031..61462790757f 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -21,6 +21,12 @@
 #define ARM_CPU_KEEP(x)
 #endif
 
+#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
+#define ARM_EXIT_KEEP(x)        x
+#else
+#define ARM_EXIT_KEEP(x)
+#endif
+
 OUTPUT_ARCH(arm)
 ENTRY(stext)
 
@@ -43,6 +49,7 @@ SECTIONS
                 _sinittext = .;
                         HEAD_TEXT
                         INIT_TEXT
+                        ARM_EXIT_KEEP(EXIT_TEXT)
                 _einittext = .;
                 ARM_CPU_DISCARD(PROC_INFO)
                 __arch_info_begin = .;
@@ -67,6 +74,7 @@ SECTIONS
 #ifndef CONFIG_XIP_KERNEL
                 __init_begin = _stext;
                 INIT_DATA
+                ARM_EXIT_KEEP(EXIT_DATA)
 #endif
         }
 
@@ -162,6 +170,7 @@ SECTIONS
                 . = ALIGN(PAGE_SIZE);
                 __init_begin = .;
                 INIT_DATA
+                ARM_EXIT_KEEP(EXIT_DATA)
                 . = ALIGN(PAGE_SIZE);
                 __init_end = .;
 #endif
@@ -247,6 +256,8 @@ SECTIONS
         }
 #endif
 
+        NOTES
+
         BSS_SECTION(0, 0, 0)
         _end = .;
 
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index 820973666f34..d9af9811dedd 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -10,6 +10,7 @@
  *
  * Multichannel mode not supported.
  */
+#include <linux/ioport.h>
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/clk.h>
@@ -78,100 +79,294 @@ static struct omap_mcbsp_ops omap1_mcbsp_ops = {
 };
 
 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+struct resource omap7xx_mcbsp_res[][6] = {
+        {
+                {
+                        .start = OMAP7XX_MCBSP1_BASE,
+                        .end   = OMAP7XX_MCBSP1_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_7XX_McBSP1RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_7XX_McBSP1TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP1_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP1_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+        {
+                {
+                        .start = OMAP7XX_MCBSP2_BASE,
+                        .end   = OMAP7XX_MCBSP2_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_7XX_McBSP2RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_7XX_McBSP2TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP3_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP3_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+};
+
+#define omap7xx_mcbsp_res_0             omap7xx_mcbsp_res[0]
+
 static struct omap_mcbsp_platform_data omap7xx_mcbsp_pdata[] = {
         {
-                .phys_base      = OMAP7XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
-                .rx_irq         = INT_7XX_McBSP1RX,
-                .tx_irq         = INT_7XX_McBSP1TX,
                 .ops            = &omap1_mcbsp_ops,
         },
         {
-                .phys_base      = OMAP7XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
-                .rx_irq         = INT_7XX_McBSP2RX,
-                .tx_irq         = INT_7XX_McBSP2TX,
                 .ops            = &omap1_mcbsp_ops,
         },
 };
-#define OMAP7XX_MCBSP_PDATA_SZ          ARRAY_SIZE(omap7xx_mcbsp_pdata)
-#define OMAP7XX_MCBSP_REG_NUM           (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
+#define OMAP7XX_MCBSP_RES_SZ            ARRAY_SIZE(omap7xx_mcbsp_res[1])
+#define OMAP7XX_MCBSP_COUNT             ARRAY_SIZE(omap7xx_mcbsp_res)
 #else
+#define omap7xx_mcbsp_res_0             NULL
 #define omap7xx_mcbsp_pdata             NULL
-#define OMAP7XX_MCBSP_PDATA_SZ          0
-#define OMAP7XX_MCBSP_REG_NUM           0
+#define OMAP7XX_MCBSP_RES_SZ            0
+#define OMAP7XX_MCBSP_COUNT             0
 #endif
 
 #ifdef CONFIG_ARCH_OMAP15XX
+struct resource omap15xx_mcbsp_res[][6] = {
+        {
+                {
+                        .start = OMAP1510_MCBSP1_BASE,
+                        .end   = OMAP1510_MCBSP1_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_McBSP1RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_McBSP1TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP1_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP1_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+        {
+                {
+                        .start = OMAP1510_MCBSP2_BASE,
+                        .end   = OMAP1510_MCBSP2_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_1510_SPI_RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_1510_SPI_TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP2_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP2_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+        {
+                {
+                        .start = OMAP1510_MCBSP3_BASE,
+                        .end   = OMAP1510_MCBSP3_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_McBSP3RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_McBSP3TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP3_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP3_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+};
+
+#define omap15xx_mcbsp_res_0            omap15xx_mcbsp_res[0]
+
 static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
         {
-                .phys_base      = OMAP1510_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
-                .rx_irq         = INT_McBSP1RX,
-                .tx_irq         = INT_McBSP1TX,
                 .ops            = &omap1_mcbsp_ops,
         },
         {
-                .phys_base      = OMAP1510_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
-                .rx_irq         = INT_1510_SPI_RX,
-                .tx_irq         = INT_1510_SPI_TX,
                 .ops            = &omap1_mcbsp_ops,
         },
         {
-                .phys_base      = OMAP1510_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
-                .rx_irq         = INT_McBSP3RX,
-                .tx_irq         = INT_McBSP3TX,
                 .ops            = &omap1_mcbsp_ops,
         },
 };
-#define OMAP15XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap15xx_mcbsp_pdata)
-#define OMAP15XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
+#define OMAP15XX_MCBSP_RES_SZ           ARRAY_SIZE(omap15xx_mcbsp_res[1])
+#define OMAP15XX_MCBSP_COUNT            ARRAY_SIZE(omap15xx_mcbsp_res)
 #else
+#define omap15xx_mcbsp_res_0            NULL
 #define omap15xx_mcbsp_pdata            NULL
-#define OMAP15XX_MCBSP_PDATA_SZ         0
-#define OMAP15XX_MCBSP_REG_NUM          0
+#define OMAP15XX_MCBSP_RES_SZ           0
+#define OMAP15XX_MCBSP_COUNT            0
 #endif
 
 #ifdef CONFIG_ARCH_OMAP16XX
+struct resource omap16xx_mcbsp_res[][6] = {
+        {
+                {
+                        .start = OMAP1610_MCBSP1_BASE,
+                        .end   = OMAP1610_MCBSP1_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_McBSP1RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_McBSP1TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP1_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP1_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+        {
+                {
+                        .start = OMAP1610_MCBSP2_BASE,
+                        .end   = OMAP1610_MCBSP2_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_1610_McBSP2_RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_1610_McBSP2_TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP2_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP2_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+        {
+                {
+                        .start = OMAP1610_MCBSP3_BASE,
+                        .end   = OMAP1610_MCBSP3_BASE + SZ_256,
+                        .flags = IORESOURCE_MEM,
+                },
+                {
+                        .name  = "rx",
+                        .start = INT_McBSP3RX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "tx",
+                        .start = INT_McBSP3TX,
+                        .flags = IORESOURCE_IRQ,
+                },
+                {
+                        .name  = "rx",
+                        .start = OMAP_DMA_MCBSP3_RX,
+                        .flags = IORESOURCE_DMA,
+                },
+                {
+                        .name  = "tx",
+                        .start = OMAP_DMA_MCBSP3_TX,
+                        .flags = IORESOURCE_DMA,
+                },
+        },
+};
+
+#define omap16xx_mcbsp_res_0            omap16xx_mcbsp_res[0]
+
 static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
         {
-                .phys_base      = OMAP1610_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP1_TX,
-                .rx_irq         = INT_McBSP1RX,
-                .tx_irq         = INT_McBSP1TX,
                 .ops            = &omap1_mcbsp_ops,
         },
         {
-                .phys_base      = OMAP1610_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP2_TX,
-                .rx_irq         = INT_1610_McBSP2_RX,
-                .tx_irq         = INT_1610_McBSP2_TX,
                 .ops            = &omap1_mcbsp_ops,
         },
         {
-                .phys_base      = OMAP1610_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP_DMA_MCBSP3_TX,
-                .rx_irq         = INT_McBSP3RX,
-                .tx_irq         = INT_McBSP3TX,
                 .ops            = &omap1_mcbsp_ops,
         },
 };
-#define OMAP16XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap16xx_mcbsp_pdata)
-#define OMAP16XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_XCERH / sizeof(u16) + 1)
+#define OMAP16XX_MCBSP_RES_SZ           ARRAY_SIZE(omap16xx_mcbsp_res[1])
+#define OMAP16XX_MCBSP_COUNT            ARRAY_SIZE(omap16xx_mcbsp_res)
 #else
+#define omap16xx_mcbsp_res_0            NULL
 #define omap16xx_mcbsp_pdata            NULL
-#define OMAP16XX_MCBSP_PDATA_SZ         0
-#define OMAP16XX_MCBSP_REG_NUM          0
+#define OMAP16XX_MCBSP_RES_SZ           0
+#define OMAP16XX_MCBSP_COUNT            0
 #endif
 
 static int __init omap1_mcbsp_init(void)
@@ -179,16 +374,12 @@ static int __init omap1_mcbsp_init(void)
         if (!cpu_class_is_omap1())
                 return -ENODEV;
 
-        if (cpu_is_omap7xx()) {
-                omap_mcbsp_count = OMAP7XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP7XX_MCBSP_REG_NUM * sizeof(u16);
-        } else if (cpu_is_omap15xx()) {
-                omap_mcbsp_count = OMAP15XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP15XX_MCBSP_REG_NUM * sizeof(u16);
-        } else if (cpu_is_omap16xx()) {
-                omap_mcbsp_count = OMAP16XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP16XX_MCBSP_REG_NUM * sizeof(u16);
-        }
+        if (cpu_is_omap7xx())
+                omap_mcbsp_count = OMAP7XX_MCBSP_COUNT;
+        else if (cpu_is_omap15xx())
+                omap_mcbsp_count = OMAP15XX_MCBSP_COUNT;
+        else if (cpu_is_omap16xx())
+                omap_mcbsp_count = OMAP16XX_MCBSP_COUNT;
 
         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                 GFP_KERNEL);
@@ -196,16 +387,22 @@ static int __init omap1_mcbsp_init(void)
                 return -ENOMEM;
 
         if (cpu_is_omap7xx())
-                omap_mcbsp_register_board_cfg(omap7xx_mcbsp_pdata,
-                                                OMAP7XX_MCBSP_PDATA_SZ);
+                omap_mcbsp_register_board_cfg(omap7xx_mcbsp_res_0,
+                                        OMAP7XX_MCBSP_RES_SZ,
+                                        omap7xx_mcbsp_pdata,
+                                        OMAP7XX_MCBSP_COUNT);
 
         if (cpu_is_omap15xx())
-                omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
-                                                OMAP15XX_MCBSP_PDATA_SZ);
+                omap_mcbsp_register_board_cfg(omap15xx_mcbsp_res_0,
+                                        OMAP15XX_MCBSP_RES_SZ,
+                                        omap15xx_mcbsp_pdata,
+                                        OMAP15XX_MCBSP_COUNT);
 
         if (cpu_is_omap16xx())
-                omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
-                                                OMAP16XX_MCBSP_PDATA_SZ);
+                omap_mcbsp_register_board_cfg(omap16xx_mcbsp_res_0,
+                                        OMAP16XX_MCBSP_RES_SZ,
+                                        omap16xx_mcbsp_pdata,
+                                        OMAP16XX_MCBSP_COUNT);
 
         return omap_mcbsp_init();
 }
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 9b4e78fe3d1c..b9d8a7b2a862 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -310,6 +310,7 @@ config MACH_OMAP_4430SDP
         depends on ARCH_OMAP4
         select OMAP_PACKAGE_CBL
         select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config MACH_OMAP4_PANDA
         bool "OMAP4 Panda Board"
@@ -317,6 +318,7 @@ config MACH_OMAP4_PANDA
         depends on ARCH_OMAP4
         select OMAP_PACKAGE_CBL
         select OMAP_PACKAGE_CBS
+        select REGULATOR_FIXED_VOLTAGE
 
 config OMAP3_EMU
         bool "OMAP3 debugging peripherals"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 10c3c8f16eaa..534d89a60dd9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -110,20 +110,23 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomain.o \
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain.o \
                                            clockdomain44xx.o \
                                            clockdomains44xx_data.o
+
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o \
                                            clkt2xxx_sys.o \
                                            clkt2xxx_dpllcore.o \
                                            clkt2xxx_virt_prcm_set.o \
-                                           clkt2xxx_apll.o clkt2xxx_osc.o
+                                           clkt2xxx_apll.o clkt2xxx_osc.o \
+                                           clkt2xxx_dpll.o clkt_iclk.o
 obj-$(CONFIG_SOC_OMAP2420)              += clock2420_data.o
 obj-$(CONFIG_SOC_OMAP2430)              += clock2430.o clock2430_data.o
 obj-$(CONFIG_ARCH_OMAP3)                += $(clock-common) clock3xxx.o \
                                            clock34xx.o clkt34xx_dpll3m2.o \
                                            clock3517.o clock36xx.o \
-                                           dpll3xxx.o clock3xxx_data.o
+                                           dpll3xxx.o clock3xxx_data.o \
+                                           clkt_iclk.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clock-common) clock44xx_data.o \
-                                           dpll3xxx.o
+                                           dpll3xxx.o dpll44xx.o
 
 # OMAP2 clock rate set data (old "OPP" data)
 obj-$(CONFIG_SOC_OMAP2420)              += opp2420_data.o
@@ -138,6 +141,10 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
 
+# L3 interconnect
+obj-$(CONFIG_ARCH_OMAP3)                += omap_l3_smx.o
+obj-$(CONFIG_ARCH_OMAP4)                += omap_l3_noc.o
+
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
 
@@ -248,3 +255,6 @@ obj-y					+= $(smc91x-m) $(smc91x-y)
 smsc911x-$(CONFIG_SMSC911X)             := gpmc-smsc911x.o
 obj-y                                   += $(smsc911x-m) $(smsc911x-y)
 obj-$(CONFIG_ARCH_OMAP4)                += hwspinlock.o
+
+disp-$(CONFIG_OMAP2_DSS)                := display.o
+obj-y                                   += $(disp-m) $(disp-y)
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index ec74c0f2051c..1fa6bb896f41 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -22,6 +22,7 @@
 #include <linux/mmc/host.h>
 #include <linux/delay.h>
 #include <linux/i2c/twl.h>
+#include <linux/regulator/machine.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
@@ -141,12 +142,29 @@ static struct omap_board_config_kernel sdp2430_config[] __initdata = {
 
 static void __init omap_2430sdp_init_early(void)
 {
-        omap_board_config = sdp2430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
 
+static struct regulator_consumer_supply sdp2430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
+static struct regulator_init_data sdp2430_vmmc1 = {
+        .constraints = {
+                .min_uV                 = 1850000,
+                .max_uV                 = 3150000,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE
+                                        | REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = ARRAY_SIZE(sdp2430_vmmc1_supplies),
+        .consumer_supplies      = &sdp2430_vmmc1_supplies[0],
+};
+
 static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
         .gpio_base      = OMAP_MAX_GPIO_LINES,
         .irq_base       = TWL4030_GPIO_IRQ_BASE,
@@ -159,6 +177,7 @@ static struct twl4030_platform_data sdp2430_twldata = {
 
         /* platform_data for children goes here */
         .gpio           = &sdp2430_gpio_data,
+        .vmmc1          = &sdp2430_vmmc1,
 };
 
 static struct i2c_board_info __initdata sdp2430_i2c_boardinfo[] = {
@@ -225,6 +244,9 @@ static void __init omap_2430sdp_init(void)
 
         omap2430_mux_init(board_mux, OMAP_PACKAGE_ZAC);
 
+        omap_board_config = sdp2430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp2430_config);
+
         omap2430_i2c_init();
 
         platform_add_devices(sdp2430_devices, ARRAY_SIZE(sdp2430_devices));
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 31085883199e..5464bec156ad 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -307,31 +307,14 @@ static struct omap_dss_board_info sdp3430_dss_data = {
         .default_device = &sdp3430_lcd_device,
 };
 
-static struct platform_device sdp3430_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &sdp3430_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply sdp3430_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &sdp3430_dss_device.dev,
-};
-
-static struct platform_device *sdp3430_devices[] __initdata = {
-        &sdp3430_dss_device,
-};
+static struct regulator_consumer_supply sdp3430_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 static struct omap_board_config_kernel sdp3430_config[] __initdata = {
 };
 
 static void __init omap_3430sdp_init_early(void)
 {
-        omap_board_config = sdp3430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
-        omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
 }
@@ -369,18 +352,6 @@ static struct omap2_hsmmc_info mmc[] = {
         {}      /* Terminator */
 };
 
-static struct regulator_consumer_supply sdp3430_vmmc1_supply = {
-        .supply                 = "vmmc",
-};
-
-static struct regulator_consumer_supply sdp3430_vsim_supply = {
-        .supply                 = "vmmc_aux",
-};
-
-static struct regulator_consumer_supply sdp3430_vmmc2_supply = {
-        .supply                 = "vmmc",
-};
-
 static int sdp3430_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
@@ -391,13 +362,6 @@ static int sdp3430_twl_gpio_setup(struct device *dev,
         mmc[1].gpio_cd = gpio + 1;
         omap2_hsmmc_init(mmc);
 
-        /* link regulators to MMC adapters ... we "know" the
-         * regulators will be set up only *after* we return.
-         */
-        sdp3430_vmmc1_supply.dev = mmc[0].dev;
-        sdp3430_vsim_supply.dev = mmc[0].dev;
-        sdp3430_vmmc2_supply.dev = mmc[1].dev;
-
         /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
         gpio_request(gpio + 7, "sub_lcd_en_bkl");
         gpio_direction_output(gpio + 7, 0);
@@ -426,6 +390,34 @@ static struct twl4030_madc_platform_data sdp3430_madc_data = {
         .irq_line       = 1,
 };
 
+/* regulator consumer mappings */
+
+/* ads7846 on SPI */
+static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
+        REGULATOR_SUPPLY("vdda_dac", "omapdss"),
+};
+
+/* VPLL2 for digital video outputs */
+static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
+};
+
+static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
+
 /*
  * Apply all the fixed voltages since most versions of U-Boot
  * don't bother with that initialization.
@@ -468,6 +460,8 @@ static struct regulator_init_data sdp3430_vaux3 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
+        .num_consumer_supplies          = ARRAY_SIZE(sdp3430_vaux3_supplies),
+        .consumer_supplies              = sdp3430_vaux3_supplies,
 };
 
 /* VAUX4 for OMAP VDD_CSI2 (camera) */
@@ -494,8 +488,8 @@ static struct regulator_init_data sdp3430_vmmc1 = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc1_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc1_supplies),
+        .consumer_supplies      = sdp3430_vmmc1_supplies,
 };
 
 /* VMMC2 for MMC2 card */
@@ -509,8 +503,8 @@ static struct regulator_init_data sdp3430_vmmc2 = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vmmc2_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vmmc2_supplies),
+        .consumer_supplies      = sdp3430_vmmc2_supplies,
 };
 
 /* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -524,8 +518,8 @@ static struct regulator_init_data sdp3430_vsim = {
                                         | REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vsim_supply,
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vsim_supplies),
+        .consumer_supplies      = sdp3430_vsim_supplies,
 };
 
 /* VDAC for DSS driving S-Video */
@@ -539,16 +533,8 @@ static struct regulator_init_data sdp3430_vdac = {
                 .valid_ops_mask         = REGULATOR_CHANGE_MODE
                                         | REGULATOR_CHANGE_STATUS,
         },
-        .num_consumer_supplies  = 1,
-        .consumer_supplies      = &sdp3430_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
-        {
-                .supply         = "vdds_dsi",
-                .dev            = &sdp3430_dss_device.dev,
-        }
+        .num_consumer_supplies  = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
+        .consumer_supplies      = sdp3430_vdda_dac_supplies,
 };
 
 static struct regulator_init_data sdp3430_vpll2 = {
@@ -566,9 +552,7 @@ static struct regulator_init_data sdp3430_vpll2 = {
         .consumer_supplies      = sdp3430_vpll2_supplies,
 };
 
-static struct twl4030_codec_audio_data sdp3430_audio = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data sdp3430_audio;
 
 static struct twl4030_codec_data sdp3430_codec = {
         .audio_mclk = 26000000,
@@ -799,8 +783,11 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap_3430sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = sdp3430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp3430_config);
+        omap3_pm_init_cpuidle(omap3_cpuidle_params_table);
         omap3430_i2c_init();
-        platform_add_devices(sdp3430_devices, ARRAY_SIZE(sdp3430_devices));
+        omap_display_init(&sdp3430_dss_data);
         if (omap_rev() > OMAP3430_REV_ES1_0)
                 ts_gpio = SDP3430_TS_GPIO_IRQ_SDPV2;
         else
@@ -812,7 +799,7 @@ static void __init omap_3430sdp_init(void)
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_3430);
+        board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
         sdp3430_display_init();
         enable_board_wakeup_source();
         usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index 16538757291a..c4e22b32e47f 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -11,6 +11,7 @@
 #include <linux/platform_device.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -71,8 +72,6 @@ static struct omap_board_config_kernel sdp_config[] __initdata = {
 
 static void __init omap_sdp_init_early(void)
 {
-        omap_board_config = sdp_config;
-        omap_board_config_size = ARRAY_SIZE(sdp_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(h8mbx00u0mer0em_sdrc_params,
                                   h8mbx00u0mer0em_sdrc_params);
@@ -205,10 +204,12 @@ static struct flash_partitions sdp_flash_partitions[] = {
 static void __init omap_sdp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBP);
+        omap_board_config = sdp_config;
+        omap_board_config_size = ARRAY_SIZE(sdp_config);
         zoom_peripherals_init();
         zoom_display_init();
         board_smc91x_init();
-        board_flash_init(sdp_flash_partitions, chip_sel_sdp);
+        board_flash_init(sdp_flash_partitions, chip_sel_sdp, NAND_BUSWIDTH_16);
         enable_board_wakeup_source();
         usb_ehci_init(&ehci_pdata);
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index bf8268438d00..85805d432e38 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -35,6 +35,7 @@
 #include <plat/common.h>
 #include <plat/usb.h>
 #include <plat/mmc.h>
+#include <plat/omap4-keypad.h>
 
 #include "mux.h"
 #include "hsmmc.h"
@@ -47,6 +48,90 @@
 #define OMAP4_SFH7741_SENSOR_OUTPUT_GPIO        184
 #define OMAP4_SFH7741_ENABLE_GPIO               188
 
+static const int sdp4430_keymap[] = {
+        KEY(0, 0, KEY_E),
+        KEY(0, 1, KEY_R),
+        KEY(0, 2, KEY_T),
+        KEY(0, 3, KEY_HOME),
+        KEY(0, 4, KEY_F5),
+        KEY(0, 5, KEY_UNKNOWN),
+        KEY(0, 6, KEY_I),
+        KEY(0, 7, KEY_LEFTSHIFT),
+
+        KEY(1, 0, KEY_D),
+        KEY(1, 1, KEY_F),
+        KEY(1, 2, KEY_G),
+        KEY(1, 3, KEY_SEND),
+        KEY(1, 4, KEY_F6),
+        KEY(1, 5, KEY_UNKNOWN),
+        KEY(1, 6, KEY_K),
+        KEY(1, 7, KEY_ENTER),
+
+        KEY(2, 0, KEY_X),
+        KEY(2, 1, KEY_C),
+        KEY(2, 2, KEY_V),
+        KEY(2, 3, KEY_END),
+        KEY(2, 4, KEY_F7),
+        KEY(2, 5, KEY_UNKNOWN),
+        KEY(2, 6, KEY_DOT),
+        KEY(2, 7, KEY_CAPSLOCK),
+
+        KEY(3, 0, KEY_Z),
+        KEY(3, 1, KEY_KPPLUS),
+        KEY(3, 2, KEY_B),
+        KEY(3, 3, KEY_F1),
+        KEY(3, 4, KEY_F8),
+        KEY(3, 5, KEY_UNKNOWN),
+        KEY(3, 6, KEY_O),
+        KEY(3, 7, KEY_SPACE),
+
+        KEY(4, 0, KEY_W),
+        KEY(4, 1, KEY_Y),
+        KEY(4, 2, KEY_U),
+        KEY(4, 3, KEY_F2),
+        KEY(4, 4, KEY_VOLUMEUP),
+        KEY(4, 5, KEY_UNKNOWN),
+        KEY(4, 6, KEY_L),
+        KEY(4, 7, KEY_LEFT),
+
+        KEY(5, 0, KEY_S),
+        KEY(5, 1, KEY_H),
+        KEY(5, 2, KEY_J),
+        KEY(5, 3, KEY_F3),
+        KEY(5, 4, KEY_F9),
+        KEY(5, 5, KEY_VOLUMEDOWN),
+        KEY(5, 6, KEY_M),
+        KEY(5, 7, KEY_RIGHT),
+
+        KEY(6, 0, KEY_Q),
+        KEY(6, 1, KEY_A),
+        KEY(6, 2, KEY_N),
+        KEY(6, 3, KEY_BACK),
+        KEY(6, 4, KEY_BACKSPACE),
+        KEY(6, 5, KEY_UNKNOWN),
+        KEY(6, 6, KEY_P),
+        KEY(6, 7, KEY_UP),
+
+        KEY(7, 0, KEY_PROG1),
+        KEY(7, 1, KEY_PROG2),
+        KEY(7, 2, KEY_PROG3),
+        KEY(7, 3, KEY_PROG4),
+        KEY(7, 4, KEY_F4),
+        KEY(7, 5, KEY_UNKNOWN),
+        KEY(7, 6, KEY_OK),
+        KEY(7, 7, KEY_DOWN),
+};
+
+static struct matrix_keymap_data sdp4430_keymap_data = {
+        .keymap                 = sdp4430_keymap,
+        .keymap_size            = ARRAY_SIZE(sdp4430_keymap),
+};
+
+static struct omap4_keypad_platform_data sdp4430_keypad_data = {
+        .keymap_data            = &sdp4430_keymap_data,
+        .rows                   = 8,
+        .cols                   = 8,
+};
 static struct gpio_led sdp4430_gpio_leds[] = {
         {
                 .name   = "omap4:green:debug0",
@@ -240,8 +325,6 @@ static struct omap_board_config_kernel sdp4430_config[] __initdata = {
 
 static void __init omap_4430sdp_init_early(void)
 {
-        omap_board_config = sdp4430_config;
-        omap_board_config_size = ARRAY_SIZE(sdp4430_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 #ifdef CONFIG_OMAP_32K_TIMER
@@ -264,11 +347,6 @@ static struct twl4030_usb_data omap4_usbphy_data = {
 
 static struct omap2_hsmmc_info mmc[] = {
         {
-                .mmc            = 1,
-                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
-                .gpio_wp        = -EINVAL,
-        },
-        {
                 .mmc            = 2,
                 .caps           =  MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
                 .gpio_cd        = -EINVAL,
@@ -276,19 +354,24 @@ static struct omap2_hsmmc_info mmc[] = {
                 .nonremovable   = true,
                 .ocr_mask       = MMC_VDD_29_30,
         },
+        {
+                .mmc            = 1,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+                .gpio_wp        = -EINVAL,
+        },
         {}      /* Terminator */
 };
 
 static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.1",
+                .dev_name = "omap_hsmmc.1",
         },
 };
 static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.0",
+                .dev_name = "omap_hsmmc.0",
         },
 };
 
@@ -422,7 +505,6 @@ static struct regulator_init_data sdp4430_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -434,7 +516,6 @@ static struct regulator_init_data sdp4430_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -446,7 +527,6 @@ static struct regulator_init_data sdp4430_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -558,6 +638,9 @@ static void __init omap_4430sdp_init(void)
                 package = OMAP_PACKAGE_CBL;
         omap4_mux_init(board_mux, package);
 
+        omap_board_config = sdp4430_config;
+        omap_board_config_size = ARRAY_SIZE(sdp4430_config);
+
         omap4_i2c_init();
         omap_sfh7741prox_init();
         platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
@@ -574,6 +657,10 @@ static void __init omap_4430sdp_init(void)
                 spi_register_board_info(sdp4430_spi_board_info,
                                 ARRAY_SIZE(sdp4430_spi_board_info));
         }
+
+        status = omap4_keyboard_init(&sdp4430_keypad_data);
+        if (status)
+                pr_err("Keypad initialization failed: %d\n", status);
 }
 
 static void __init omap_4430sdp_map_io(void)
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index ae3a83d47dab..f53bbb2c3478 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -51,9 +51,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 
 static void __init am3517_crane_init_early(void)
 {
-        omap_board_config = am3517_crane_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
-
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -76,6 +73,9 @@ static void __init am3517_crane_init(void)
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
 
+        omap_board_config = am3517_crane_config;
+        omap_board_config_size = ARRAY_SIZE(am3517_crane_config);
+
         /* Configure GPIO for EHCI port */
         if (omap_mux_init_gpio(GPIO_USB_NRESET, OMAP_PIN_OUTPUT)) {
                 pr_err("Can not configure mux for GPIO_USB_NRESET %d\n",
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 8532d6e0d53a..77541cf59bd4 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -200,6 +200,9 @@ static struct pca953x_platform_data am3517evm_gpio_expander_info_0 = {
 };
 static struct i2c_board_info __initdata am3517evm_i2c2_boardinfo[] = {
         {
+                I2C_BOARD_INFO("tlv320aic23", 0x1A),
+        },
+        {
                 I2C_BOARD_INFO("tca6416", 0x21),
                 .platform_data = &am3517evm_gpio_expander_info_0,
         },
@@ -378,28 +381,11 @@ static struct omap_dss_board_info am3517_evm_dss_data = {
         .default_device = &am3517_evm_lcd_device,
 };
 
-static struct platform_device am3517_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data  = &am3517_evm_dss_data,
-        },
-};
-
 /*
  * Board initialization
  */
-static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
-};
-
-static struct platform_device *am3517_evm_devices[] __initdata = {
-        &am3517_evm_dss_device,
-};
-
 static void __init am3517_evm_init_early(void)
 {
-        omap_board_config = am3517_evm_config;
-        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -493,14 +479,17 @@ static void am3517_evm_hecc_init(struct ti_hecc_platform_data *pdata)
         platform_device_register(&am3517_hecc_device);
 }
 
+static struct omap_board_config_kernel am3517_evm_config[] __initdata = {
+};
+
 static void __init am3517_evm_init(void)
 {
+        omap_board_config = am3517_evm_config;
+        omap_board_config_size = ARRAY_SIZE(am3517_evm_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         am3517_evm_i2c_init();
-        platform_add_devices(am3517_evm_devices,
-                                ARRAY_SIZE(am3517_evm_devices));
-
+        omap_display_init(&am3517_evm_dss_data);
         omap_serial_init();
 
         /* Configure GPIO for EHCI port */
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 4ef4aad4e719..f4f8374a0298 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -276,8 +276,6 @@ static struct omap_board_config_kernel apollon_config[] __initdata = {
 
 static void __init omap_apollon_init_early(void)
 {
-        omap_board_config = apollon_config;
-        omap_board_config_size = ARRAY_SIZE(apollon_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -319,6 +317,8 @@ static void __init omap_apollon_init(void)
         u32 v;
 
         omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
+        omap_board_config = apollon_config;
+        omap_board_config_size = ARRAY_SIZE(apollon_config);
 
         apollon_init_smc91x();
         apollon_led_init();
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 9e4de92a5798..27bea540ccbb 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -401,14 +401,6 @@ static struct omap_dss_board_info cm_t35_dss_data = {
         .default_device = &cm_t35_dvi_device,
 };
 
-static struct platform_device cm_t35_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &cm_t35_dss_data,
-        },
-};
-
 static struct omap2_mcspi_device_config tdo24m_mcspi_config = {
         .turbo_mode     = 0,
         .single_channel = 1,    /* 0: slave, 1: master */
@@ -468,7 +460,7 @@ static void __init cm_t35_init_display(void)
         msleep(50);
         gpio_set_value(lcd_en_gpio, 1);
 
-        err = platform_device_register(&cm_t35_dss_device);
+        err = omap_display_init(&cm_t35_dss_data);
         if (err) {
                 pr_err("CM-T35: failed to register DSS device\n");
                 goto err_dev_reg;
@@ -495,15 +487,11 @@ static struct regulator_consumer_supply cm_t35_vsim_supply = {
         .supply                 = "vmmc_aux",
 };
 
-static struct regulator_consumer_supply cm_t35_vdac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
-static struct regulator_consumer_supply cm_t35_vdvi_supply = {
-        .supply         = "vdvi",
-        .dev            = &cm_t35_dss_device.dev,
-};
+static struct regulator_consumer_supply cm_t35_vdvi_supply =
+        REGULATOR_SUPPLY("vdvi", "omapdss");
 
 /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
 static struct regulator_init_data cm_t35_vmmc1 = {
@@ -680,14 +668,8 @@ static void __init cm_t35_init_i2c(void)
                               ARRAY_SIZE(cm_t35_i2c_boardinfo));
 }
 
-static struct omap_board_config_kernel cm_t35_config[] __initdata = {
-};
-
 static void __init cm_t35_init_early(void)
 {
-        omap_board_config = cm_t35_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
-
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                              mt46h32m32lf6_sdrc_params);
@@ -797,8 +779,13 @@ static struct omap_musb_board_data musb_board_data = {
         .power                  = 100,
 };
 
+static struct omap_board_config_kernel cm_t35_config[] __initdata = {
+};
+
 static void __init cm_t35_init(void)
 {
+        omap_board_config = cm_t35_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t35_config);
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
         omap_serial_init();
         cm_t35_init_i2c();
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 38bef6d004c9..9da6e8240e8b 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -256,9 +256,6 @@ static struct omap_board_config_kernel cm_t3517_config[] __initdata = {
 
 static void __init cm_t3517_init_early(void)
 {
-        omap_board_config = cm_t3517_config;
-        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
-
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -293,6 +290,8 @@ static void __init cm_t3517_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
         omap_serial_init();
+        omap_board_config = cm_t3517_config;
+        omap_board_config_size = ARRAY_SIZE(cm_t3517_config);
         cm_t3517_init_leds();
         cm_t3517_init_nand();
         cm_t3517_init_rtc();
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index af742887e834..728f27c5bcb1 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -140,7 +140,7 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
 }
 
 static struct regulator_consumer_supply devkit8000_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 
 /* ads7846 on SPI */
@@ -195,14 +195,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
         .default_device = &devkit8000_lcd_device,
 };
 
-static struct platform_device devkit8000_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &devkit8000_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -350,9 +342,7 @@ static struct twl4030_usb_data devkit8000_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data devkit8000_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data devkit8000_audio_data;
 
 static struct twl4030_codec_data devkit8000_codec_data = {
         .audio_mclk = 26000000,
@@ -579,7 +569,6 @@ static void __init omap_dm9000_init(void)
 }
 
 static struct platform_device *devkit8000_devices[] __initdata = {
-        &devkit8000_dss_device,
         &leds_gpio,
         &keys_gpio,
         &omap_dm9000_dev,
@@ -801,6 +790,7 @@ static void __init devkit8000_init(void)
         platform_add_devices(devkit8000_devices,
                         ARRAY_SIZE(devkit8000_devices));
 
+        omap_display_init(&devkit8000_dss_data);
         spi_register_board_info(devkit8000_spi_board_info,
         ARRAY_SIZE(devkit8000_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index fd38c05bb47f..729892fdcf2e 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -1,5 +1,5 @@
 /*
- * board-sdp-flash.c
+ * board-flash.c
  * Modified from mach-omap2/board-3430sdp-flash.c
  *
  * Copyright (C) 2009 Nokia Corporation
@@ -16,6 +16,7 @@
 #include <linux/platform_device.h>
 #include <linux/mtd/physmap.h>
 #include <linux/io.h>
+#include <plat/irqs.h>
 
 #include <plat/gpmc.h>
 #include <plat/nand.h>
@@ -73,11 +74,11 @@ __init board_nor_init(struct mtd_partition *nor_parts, u8 nr_parts, u8 cs)
                                         + FLASH_SIZE_SDPV1 - 1;
         }
         if (err < 0) {
-                printk(KERN_ERR "NOR: Can't request GPMC CS\n");
+                pr_err("NOR: Can't request GPMC CS\n");
                 return;
         }
         if (platform_device_register(&board_nor_device) < 0)
-                printk(KERN_ERR "Unable to register NOR device\n");
+                pr_err("Unable to register NOR device\n");
 }
 
 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
@@ -139,17 +140,21 @@ static struct omap_nand_platform_data board_nand_data = {
 };
 
 void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
+__init board_nand_init(struct mtd_partition *nand_parts,
+                        u8 nr_parts, u8 cs, int nand_type)
 {
         board_nand_data.cs              = cs;
         board_nand_data.parts           = nand_parts;
-        board_nand_data.nr_parts                = nr_parts;
+        board_nand_data.nr_parts        = nr_parts;
+        board_nand_data.devsize         = nand_type;
 
+        board_nand_data.ecc_opt = OMAP_ECC_HAMMING_CODE_DEFAULT;
+        board_nand_data.gpmc_irq = OMAP_GPMC_IRQ_BASE + cs;
         gpmc_nand_init(&board_nand_data);
 }
 #else
 void
-__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs)
+__init board_nand_init(struct mtd_partition *nand_parts, u8 nr_parts, u8 cs, int nand_type)
 {
 }
 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
@@ -189,12 +194,12 @@ unmap:
 }
 
 /**
- * sdp3430_flash_init - Identify devices connected to GPMC and register.
+ * board_flash_init - Identify devices connected to GPMC and register.
  *
  * @return - void.
  */
 void board_flash_init(struct flash_partitions partition_info[],
-                                        char chip_sel_board[][GPMC_CS_NUM])
+                        char chip_sel_board[][GPMC_CS_NUM], int nand_type)
 {
         u8              cs = 0;
         u8              norcs = GPMC_CS_NUM + 1;
@@ -208,7 +213,7 @@ void board_flash_init(struct flash_partitions partition_info[],
          */
         idx = get_gpmc0_type();
         if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
-                printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
+                pr_err("%s: Invalid chip select: %d\n", __func__, cs);
                 return;
         }
         config_sel = (unsigned char *)(chip_sel_board[idx]);
@@ -232,23 +237,20 @@ void board_flash_init(struct flash_partitions partition_info[],
         }
 
         if (norcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NOR: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NOR: Unable to find configuration in GPMC\n");
         else
                 board_nor_init(partition_info[0].parts,
                                 partition_info[0].nr_parts, norcs);
 
         if (onenandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "OneNAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("OneNAND: Unable to find configuration in GPMC\n");
         else
                 board_onenand_init(partition_info[1].parts,
                                         partition_info[1].nr_parts, onenandcs);
 
         if (nandcs > GPMC_CS_NUM)
-                printk(KERN_INFO "NAND: Unable to find configuration "
-                                "in GPMC\n");
+                pr_err("NAND: Unable to find configuration in GPMC\n");
         else
                 board_nand_init(partition_info[2].parts,
-                                partition_info[2].nr_parts, nandcs);
+                        partition_info[2].nr_parts, nandcs, nand_type);
 }
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 69befe00dd2f..c240a3f8d163 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -25,6 +25,6 @@ struct flash_partitions {
 };
 
 extern void board_flash_init(struct flash_partitions [],
-                                char chip_sel[][GPMC_CS_NUM]);
+                                char chip_sel[][GPMC_CS_NUM], int nand_type);
 extern void board_nand_init(struct mtd_partition *nand_parts,
-                                        u8 nr_parts, u8 cs);
+                                        u8 nr_parts, u8 cs, int nand_type);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 682da9251db6..73e3c31e8508 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -35,8 +35,6 @@ static struct omap_board_config_kernel generic_config[] = {
 
 static void __init omap_generic_init_early(void)
 {
-        omap_board_config = generic_config;
-        omap_board_config_size = ARRAY_SIZE(generic_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -44,6 +42,8 @@ static void __init omap_generic_init_early(void)
 static void __init omap_generic_init(void)
 {
         omap_serial_init();
+        omap_board_config = generic_config;
+        omap_board_config_size = ARRAY_SIZE(generic_config);
 }
 
 static void __init omap_generic_map_io(void)
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f6a3872f72fa..7e6bf4fa1535 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -292,8 +292,6 @@ static struct omap_board_config_kernel h4_config[] __initdata = {
 
 static void __init omap_h4_init_early(void)
 {
-        omap_board_config = h4_config;
-        omap_board_config_size = ARRAY_SIZE(h4_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -334,6 +332,9 @@ static void __init omap_h4_init(void)
 {
         omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAF);
 
+        omap_board_config = h4_config;
+        omap_board_config_size = ARRAY_SIZE(h4_config);
+
         /*
          * Make sure the serial ports are muxed on at this point.
          * You have to mux them off in device drivers later on
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index dd0b1ac3b662..c4b3c1c47ec6 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -250,7 +250,7 @@ static inline void __init igep2_init_smsc911x(void) { }
 #endif
 
 static struct regulator_consumer_supply igep2_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep2_vmmc1 = {
@@ -268,7 +268,7 @@ static struct regulator_init_data igep2_vmmc1 = {
 };
 
 static struct regulator_consumer_supply igep2_vio_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
 
 static struct regulator_init_data igep2_vio = {
         .constraints = {
@@ -286,7 +286,7 @@ static struct regulator_init_data igep2_vio = {
 };
 
 static struct regulator_consumer_supply igep2_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
 static struct regulator_init_data igep2_vmmc2 = {
         .constraints            = {
@@ -485,18 +485,8 @@ static struct omap_dss_board_info igep2_dss_data = {
         .default_device = &igep2_dvi_device,
 };
 
-static struct platform_device igep2_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &igep2_dss_data,
-        },
-};
-
-static struct regulator_consumer_supply igep2_vpll2_supply = {
-        .supply = "vdds_dsi",
-        .dev    = &igep2_dss_device.dev,
-};
+static struct regulator_consumer_supply igep2_vpll2_supply =
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 static struct regulator_init_data igep2_vpll2 = {
         .constraints = {
@@ -521,7 +511,6 @@ static void __init igep2_display_init(void)
 }
 
 static struct platform_device *igep2_devices[] __initdata = {
-        &igep2_dss_device,
         &igep2_vwlan_device,
 };
 
@@ -532,9 +521,7 @@ static void __init igep2_init_early(void)
                                   m65kxxxxam_sdrc_params);
 }
 
-static struct twl4030_codec_audio_data igep2_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data igep2_audio_data;
 
 static struct twl4030_codec_data igep2_codec_data = {
         .audio_mclk = 26000000,
@@ -696,6 +683,7 @@ static void __init igep2_init(void)
         /* Register I2C busses and drivers */
         igep2_i2c_init();
         platform_add_devices(igep2_devices, ARRAY_SIZE(igep2_devices));
+        omap_display_init(&igep2_dss_data);
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         usb_ehci_init(&ehci_pdata);
diff --git a/arch/arm/mach-omap2/board-igep0030.c b/arch/arm/mach-omap2/board-igep0030.c
index d75028e48f5d..4273d0672ef6 100644
--- a/arch/arm/mach-omap2/board-igep0030.c
+++ b/arch/arm/mach-omap2/board-igep0030.c
@@ -142,7 +142,7 @@ static void __init igep3_flash_init(void) {}
 #endif
 
 static struct regulator_consumer_supply igep3_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
 static struct regulator_init_data igep3_vmmc1 = {
@@ -160,7 +160,7 @@ static struct regulator_init_data igep3_vmmc1 = {
 };
 
 static struct regulator_consumer_supply igep3_vio_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
 
 static struct regulator_init_data igep3_vio = {
         .constraints = {
@@ -178,7 +178,7 @@ static struct regulator_init_data igep3_vio = {
 };
 
 static struct regulator_consumer_supply igep3_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
 static struct regulator_init_data igep3_vmmc2 = {
         .constraints    = {
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index d8eb2cb7cbc7..e2ba77957a8c 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -290,8 +290,6 @@ static struct omap_board_config_kernel ldp_config[] __initdata = {
 
 static void __init omap_ldp_init_early(void)
 {
-        omap_board_config = ldp_config;
-        omap_board_config_size = ARRAY_SIZE(ldp_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -329,6 +327,26 @@ static struct regulator_init_data ldp_vmmc1 = {
         .consumer_supplies      = &ldp_vmmc1_supply,
 };
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply ldp_vaux1_supplies[] = {
+        REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
+
+/* VAUX1 */
+static struct regulator_init_data ldp_vaux1 = {
+        .constraints = {
+                .min_uV                 = 3000000,
+                .max_uV                 = 3000000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies          = ARRAY_SIZE(ldp_vaux1_supplies),
+        .consumer_supplies              = ldp_vaux1_supplies,
+};
+
 static struct twl4030_platform_data ldp_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -337,6 +355,7 @@ static struct twl4030_platform_data ldp_twldata = {
         .madc           = &ldp_madc_data,
         .usb            = &ldp_usb_data,
         .vmmc1          = &ldp_vmmc1,
+        .vaux1          = &ldp_vaux1,
         .gpio           = &ldp_gpio_data,
         .keypad         = &ldp_kp_twl4030_data,
 };
@@ -422,6 +441,8 @@ static struct mtd_partition ldp_nand_partitions[] = {
 static void __init omap_ldp_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = ldp_config;
+        omap_board_config_size = ARRAY_SIZE(ldp_config);
         ldp_init_smsc911x();
         omap_i2c_init();
         platform_add_devices(ldp_devices, ARRAY_SIZE(ldp_devices));
@@ -433,7 +454,7 @@ static void __init omap_ldp_init(void)
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         board_nand_init(ldp_nand_partitions,
-                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS);
+                ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
 
         omap2_hsmmc_init(mmc);
         /* link regulators to MMC adapters */
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index b36cbd21e2d0..e710cd9e079b 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -536,7 +536,7 @@ static void __init n8x0_mmc_init(void)
         }
 
         mmc_data[0] = &mmc1_data;
-        omap2_init_mmc(mmc_data, OMAP24XX_NR_MMC);
+        omap242x_init_mmc(mmc_data);
 }
 #else
 
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 19bcd004d604..b6752ac5b97e 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -228,14 +228,6 @@ static struct omap_dss_board_info beagle_dss_data = {
         .default_device = &beagle_dvi_device,
 };
 
-static struct platform_device beagle_dss_device = {
-        .name          = "omapdss",
-        .id            = -1,
-        .dev            = {
-                .platform_data = &beagle_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply beagle_vdac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
@@ -435,9 +427,7 @@ static struct twl4030_usb_data beagle_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data beagle_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data beagle_audio_data;
 
 static struct twl4030_codec_data beagle_codec_data = {
         .audio_mclk = 26000000,
@@ -554,7 +544,6 @@ static void __init omap3_beagle_init_irq(void)
 static struct platform_device *omap3_beagle_devices[] __initdata = {
         &leds_gpio,
         &keys_gpio,
-        &beagle_dss_device,
 };
 
 static void __init omap3beagle_flash_init(void)
@@ -621,6 +610,7 @@ static void __init omap3_beagle_init(void)
         omap3_beagle_i2c_init();
         platform_add_devices(omap3_beagle_devices,
                         ARRAY_SIZE(omap3_beagle_devices));
+        omap_display_init(&beagle_dss_data);
         omap_serial_init();
 
         omap_mux_init_gpio(170, OMAP_PIN_INPUT);
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c2a0fca4aa53..b65848c59e1d 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -30,6 +30,8 @@
 #include <linux/usb/otg.h>
 #include <linux/smsc911x.h>
 
+#include <linux/wl12xx.h>
+#include <linux/regulator/fixed.h>
 #include <linux/regulator/machine.h>
 #include <linux/mmc/host.h>
 
@@ -58,6 +60,13 @@
 #define OMAP3EVM_ETHR_ID_REV    0x50
 #define OMAP3EVM_ETHR_GPIO_IRQ  176
 #define OMAP3EVM_SMSC911X_CS    5
+/*
+ * Eth Reset signal
+ *      64 = Generation 1 (<=RevD)
+ *      7 = Generation 2 (>=RevE)
+ */
+#define OMAP3EVM_GEN1_ETHR_GPIO_RST     64
+#define OMAP3EVM_GEN2_ETHR_GPIO_RST     7
 
 static u8 omap3_evm_version;
 
@@ -124,10 +133,15 @@ static struct platform_device omap3evm_smsc911x_device = {
 
 static inline void __init omap3evm_init_smsc911x(void)
 {
-        int eth_cs;
+        int eth_cs, eth_rst;
         struct clk *l3ck;
         unsigned int rate;
 
+        if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1)
+                eth_rst = OMAP3EVM_GEN1_ETHR_GPIO_RST;
+        else
+                eth_rst = OMAP3EVM_GEN2_ETHR_GPIO_RST;
+
         eth_cs = OMAP3EVM_SMSC911X_CS;
 
         l3ck = clk_get(NULL, "l3_ck");
@@ -136,6 +150,27 @@ static inline void __init omap3evm_init_smsc911x(void)
         else
                 rate = clk_get_rate(l3ck);
 
+        /* Configure ethernet controller reset gpio */
+        if (cpu_is_omap3430()) {
+                if (gpio_request(eth_rst, "SMSC911x gpio") < 0) {
+                        pr_err(KERN_ERR "Failed to request %d for smsc911x\n",
+                                        eth_rst);
+                        return;
+                }
+
+                if (gpio_direction_output(eth_rst, 1) < 0) {
+                        pr_err(KERN_ERR "Failed to set direction of %d for" \
+                                        " smsc911x\n", eth_rst);
+                        return;
+                }
+                /* reset pulse to ethernet controller*/
+                usleep_range(150, 220);
+                gpio_set_value(eth_rst, 0);
+                usleep_range(150, 220);
+                gpio_set_value(eth_rst, 1);
+                usleep_range(1, 2);
+        }
+
         if (gpio_request(OMAP3EVM_ETHR_GPIO_IRQ, "SMSC911x irq") < 0) {
                 printk(KERN_ERR "Failed to request GPIO%d for smsc911x IRQ\n",
                         OMAP3EVM_ETHR_GPIO_IRQ);
@@ -235,9 +270,9 @@ static int omap3_evm_enable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 0);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
 
         lcd_enabled = 1;
         return 0;
@@ -248,9 +283,9 @@ static void omap3_evm_disable_lcd(struct omap_dss_device *dssdev)
         gpio_set_value(OMAP3EVM_LCD_PANEL_ENVDD, 1);
 
         if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 1);
         else
-                gpio_set_value(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
+                gpio_set_value_cansleep(OMAP3EVM_LCD_PANEL_BKLIGHT_GPIO, 0);
 
         lcd_enabled = 0;
 }
@@ -289,7 +324,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
                 return -EINVAL;
         }
 
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 1);
 
         dvi_enabled = 1;
         return 0;
@@ -297,7 +332,7 @@ static int omap3_evm_enable_dvi(struct omap_dss_device *dssdev)
 
 static void omap3_evm_disable_dvi(struct omap_dss_device *dssdev)
 {
-        gpio_set_value(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
+        gpio_set_value_cansleep(OMAP3EVM_DVI_PANEL_EN_GPIO, 0);
 
         dvi_enabled = 0;
 }
@@ -328,14 +363,6 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
         .default_device = &omap3_evm_lcd_device,
 };
 
-static struct platform_device omap3_evm_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &omap3_evm_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
         .supply                 = "vmmc",
 };
@@ -381,6 +408,16 @@ static struct omap2_hsmmc_info mmc[] = {
                 .gpio_cd        = -EINVAL,
                 .gpio_wp        = 63,
         },
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        {
+                .name           = "wl1271",
+                .mmc            = 2,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .nonremovable   = true,
+        },
+#endif
         {}      /* Terminator */
 };
 
@@ -411,6 +448,8 @@ static struct platform_device leds_gpio = {
 static int omap3evm_twl_gpio_setup(struct device *dev,
                 unsigned gpio, unsigned ngpio)
 {
+        int r;
+
         /* gpio + 0 is "mmc0_cd" (input/IRQ) */
         omap_mux_init_gpio(63, OMAP_PIN_INPUT);
         mmc[0].gpio_cd = gpio + 0;
@@ -426,8 +465,12 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
          */
 
         /* TWL4030_GPIO_MAX + 0 == ledA, LCD Backlight control */
-        gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
-        gpio_direction_output(gpio + TWL4030_GPIO_MAX, 0);
+        r = gpio_request(gpio + TWL4030_GPIO_MAX, "EN_LCD_BKL");
+        if (!r)
+                r = gpio_direction_output(gpio + TWL4030_GPIO_MAX,
+                        (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2) ? 1 : 0);
+        if (r)
+                printk(KERN_ERR "failed to get/set lcd_bkl gpio\n");
 
         /* gpio + 7 == DVI Enable */
         gpio_request(gpio + 7, "EN_DVI");
@@ -491,19 +534,15 @@ static struct twl4030_madc_platform_data omap3evm_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data omap3evm_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data omap3evm_audio_data;
 
 static struct twl4030_codec_data omap3evm_codec_data = {
         .audio_mclk = 26000000,
         .audio = &omap3evm_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_evm_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_evm_vdac = {
@@ -538,6 +577,66 @@ static struct regulator_init_data omap3_evm_vpll2 = {
         .consumer_supplies      = &omap3_evm_vpll2_supply,
 };
 
+/* ads7846 on SPI */
+static struct regulator_consumer_supply omap3evm_vio_supply =
+        REGULATOR_SUPPLY("vcc", "spi1.0");
+
+/* VIO for ads7846 */
+static struct regulator_init_data omap3evm_vio = {
+        .constraints = {
+                .min_uV                 = 1800000,
+                .max_uV                 = 1800000,
+                .apply_uV               = true,
+                .valid_modes_mask       = REGULATOR_MODE_NORMAL
+                                        | REGULATOR_MODE_STANDBY,
+                .valid_ops_mask         = REGULATOR_CHANGE_MODE
+                                        | REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies      = &omap3evm_vio_supply,
+};
+
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+
+#define OMAP3EVM_WLAN_PMENA_GPIO        (150)
+#define OMAP3EVM_WLAN_IRQ_GPIO          (149)
+
+static struct regulator_consumer_supply omap3evm_vmmc2_supply =
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+
+/* VMMC2 for driving the WL12xx module */
+static struct regulator_init_data omap3evm_vmmc2 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies  = 1,
+        .consumer_supplies = &omap3evm_vmmc2_supply,
+};
+
+static struct fixed_voltage_config omap3evm_vwlan = {
+        .supply_name            = "vwl1271",
+        .microvolts             = 1800000, /* 1.80V */
+        .gpio                   = OMAP3EVM_WLAN_PMENA_GPIO,
+        .startup_delay          = 70000, /* 70ms */
+        .enable_high            = 1,
+        .enabled_at_boot        = 0,
+        .init_data              = &omap3evm_vmmc2,
+};
+
+static struct platform_device omap3evm_wlan_regulator = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &omap3evm_vwlan,
+        },
+};
+
+struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
+        .irq = OMAP_GPIO_IRQ(OMAP3EVM_WLAN_IRQ_GPIO),
+        .board_ref_clock = WL12XX_REFCLOCK_38, /* 38.4 MHz */
+};
+#endif
+
 static struct twl4030_platform_data omap3evm_twldata = {
         .irq_base       = TWL4030_IRQ_BASE,
         .irq_end        = TWL4030_IRQ_END,
@@ -550,6 +649,7 @@ static struct twl4030_platform_data omap3evm_twldata = {
         .codec          = &omap3evm_codec_data,
         .vdac           = &omap3_evm_vdac,
         .vpll2          = &omap3_evm_vpll2,
+        .vio            = &omap3evm_vio,
 };
 
 static struct i2c_board_info __initdata omap3evm_i2c_boardinfo[] = {
@@ -627,16 +727,10 @@ static struct omap_board_config_kernel omap3_evm_config[] __initdata = {
 
 static void __init omap3_evm_init_early(void)
 {
-        omap_board_config = omap3_evm_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
 }
 
-static struct platform_device *omap3_evm_devices[] __initdata = {
-        &omap3_evm_dss_device,
-};
-
 static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
 
         .port_mode[0] = EHCI_HCD_OMAP_MODE_UNKNOWN,
@@ -651,14 +745,76 @@ static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = {
 };
 
 #ifdef CONFIG_OMAP_MUX
-static struct omap_board_mux board_mux[] __initdata = {
+static struct omap_board_mux omap35x_board_mux[] __initdata = {
         OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
                                 OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
                                 OMAP_PIN_OFF_WAKEUPENABLE),
         OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
-                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW),
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(GPMC_WAIT2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
+
+static struct omap_board_mux omap36x_board_mux[] __initdata = {
+        OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        OMAP3_MUX(MCSPI1_CS1, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP |
+                                OMAP_PIN_OFF_INPUT_PULLUP | OMAP_PIN_OFF_OUTPUT_LOW |
+                                OMAP_PIN_OFF_WAKEUPENABLE),
+        /* AM/DM37x EVM: DSS data bus muxed with sys_boot */
+        OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT0, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT1, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT3, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT4, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT5, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+        OMAP3_MUX(SYS_BOOT6, OMAP_MUX_MODE3 | OMAP_PIN_OFF_NONE),
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WLAN IRQ - GPIO 149 */
+        OMAP3_MUX(UART1_RTS, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
+
+        /* WLAN POWER ENABLE - GPIO 150 */
+        OMAP3_MUX(UART1_CTS, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
+
+        /* MMC2 SDIO pin muxes for WL12xx */
+        OMAP3_MUX(SDMMC2_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP3_MUX(SDMMC2_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+#endif
+
+        { .reg_offset = OMAP_MUX_TERMINATOR },
+};
+#else
+#define omap35x_board_mux       NULL
+#define omap36x_board_mux       NULL
 #endif
 
 static struct omap_musb_board_data musb_board_data = {
@@ -670,11 +826,18 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap3_evm_init(void)
 {
         omap3_evm_get_revision();
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+
+        if (cpu_is_omap3630())
+                omap3_mux_init(omap36x_board_mux, OMAP_PACKAGE_CBB);
+        else
+                omap3_mux_init(omap35x_board_mux, OMAP_PACKAGE_CBB);
+
+        omap_board_config = omap3_evm_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_evm_config);
 
         omap3_evm_i2c_init();
 
-        platform_add_devices(omap3_evm_devices, ARRAY_SIZE(omap3_evm_devices));
+        omap_display_init(&omap3_evm_dss_data);
 
         spi_register_board_info(omap3evm_spi_board_info,
                                 ARRAY_SIZE(omap3evm_spi_board_info));
@@ -714,6 +877,13 @@ static void __init omap3_evm_init(void)
         ads7846_dev_init();
         omap3evm_init_smsc911x();
         omap3_evm_display_init();
+
+#ifdef CONFIG_WL12XX_PLATFORM_DATA
+        /* WL12xx WLAN Init */
+        if (wl12xx_set_platform_data(&omap3evm_wlan_data))
+                pr_err("error setting wl12xx data\n");
+        platform_device_register(&omap3evm_wlan_regulator);
+#endif
 }
 
 MACHINE_START(OMAP3EVM, "OMAP3 EVM")
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index b91f74ce3a9f..5386a8190ea1 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -253,14 +253,6 @@ static struct omap_dss_board_info pandora_dss_data = {
         .default_device = &pandora_lcd_device,
 };
 
-static struct platform_device pandora_dss_device = {
-        .name           = "omapdss",
-        .id             = -1,
-        .dev            = {
-                .platform_data = &pandora_dss_data,
-        },
-};
-
 static void pandora_wl1251_init_card(struct mmc_card *card)
 {
         /*
@@ -341,13 +333,13 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
 };
 
 static struct regulator_consumer_supply pandora_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 static struct regulator_consumer_supply pandora_vmmc2_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
 static struct regulator_consumer_supply pandora_vmmc3_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.2");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
 
 static struct regulator_consumer_supply pandora_vdda_dac_supply =
         REGULATOR_SUPPLY("vdda_dac", "omapdss");
@@ -524,9 +516,7 @@ static struct twl4030_usb_data omap3pandora_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data omap3pandora_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data omap3pandora_audio_data;
 
 static struct twl4030_codec_data omap3pandora_codec_data = {
         .audio_mclk = 26000000,
@@ -676,7 +666,6 @@ fail:
 static struct platform_device *omap3pandora_devices[] __initdata = {
         &pandora_leds_gpio,
         &pandora_keys_gpio,
-        &pandora_dss_device,
         &pandora_vwlan_device,
 };
 
@@ -711,6 +700,7 @@ static void __init omap3pandora_init(void)
         pandora_wl1251_init();
         platform_add_devices(omap3pandora_devices,
                         ARRAY_SIZE(omap3pandora_devices));
+        omap_display_init(&pandora_dss_data);
         omap_serial_init();
         spi_register_board_info(omap3pandora_spi_board_info,
                         ARRAY_SIZE(omap3pandora_spi_board_info));
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 5d1ccef69164..15ede8b49815 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -240,14 +240,6 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
         .default_device = &omap3_stalker_dvi_device,
 };
 
-static struct platform_device omap3_stalker_dss_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &omap3_stalker_dss_data,
-        },
-};
-
 static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
         .supply         = "vmmc",
 };
@@ -439,19 +431,15 @@ static struct twl4030_madc_platform_data omap3stalker_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data omap3stalker_audio_data = {
-        .audio_mclk     = 26000000,
-};
+static struct twl4030_codec_audio_data omap3stalker_audio_data;
 
 static struct twl4030_codec_data omap3stalker_codec_data = {
         .audio_mclk     = 26000000,
         .audio          = &omap3stalker_audio_data,
 };
 
-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply = {
-        .supply         = "vdda_dac",
-        .dev            = &omap3_stalker_dss_device.dev,
-};
+static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
+        REGULATOR_SUPPLY("vdda_dac", "omapdss");
 
 /* VDAC for DSS driving S-Video */
 static struct regulator_init_data omap3_stalker_vdac = {
@@ -469,10 +457,8 @@ static struct regulator_init_data omap3_stalker_vdac = {
 };
 
 /* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_stalker_vpll2_supply = {
-        .supply         = "vdds_dsi",
-        .dev            = &omap3_stalker_lcd_device.dev,
-};
+static struct regulator_consumer_supply omap3_stalker_vpll2_supply =
+        REGULATOR_SUPPLY("vdds_dsi", "omapdss");
 
 static struct regulator_init_data omap3_stalker_vpll2 = {
         .constraints            = {
@@ -593,8 +579,6 @@ static struct omap_board_config_kernel omap3_stalker_config[] __initdata = {
 
 static void __init omap3_stalker_init_early(void)
 {
-        omap_board_config = omap3_stalker_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params, NULL);
 }
@@ -608,7 +592,6 @@ static void __init omap3_stalker_init_irq(void)
 }
 
 static struct platform_device *omap3_stalker_devices[] __initdata = {
-        &omap3_stalker_dss_device,
         &keys_gpio,
 };
 
@@ -642,12 +625,15 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init omap3_stalker_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
+        omap_board_config = omap3_stalker_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_stalker_config);
 
         omap3_stalker_i2c_init();
 
         platform_add_devices(omap3_stalker_devices,
                              ARRAY_SIZE(omap3_stalker_devices));
 
+        omap_display_init(&omap3_stalker_dss_data);
         spi_register_board_info(omap3stalker_spi_board_info,
                                 ARRAY_SIZE(omap3stalker_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 6a60f79dcccb..5554f5814aa4 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -252,9 +252,7 @@ static struct twl4030_usb_data touchbook_usb_data = {
         .usb_mode       = T2_USB_MODE_ULPI,
 };
 
-static struct twl4030_codec_audio_data touchbook_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data touchbook_audio_data;
 
 static struct twl4030_codec_data touchbook_codec_data = {
         .audio_mclk = 26000000,
@@ -417,9 +415,6 @@ static struct omap_board_mux board_mux[] __initdata = {
 
 static void __init omap3_touchbook_init_early(void)
 {
-        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
-        omap_board_config = omap3_touchbook_config;
-        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
@@ -514,6 +509,10 @@ static struct omap_musb_board_data musb_board_data = {
 
 static void __init omap3_touchbook_init(void)
 {
+        omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = omap3_touchbook_config;
+        omap_board_config_size = ARRAY_SIZE(omap3_touchbook_config);
+
         pm_power_off = omap3_touchbook_poweroff;
 
         omap3_touchbook_i2c_init();
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index fca5b9e80c18..a94ce07be72f 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -26,6 +26,8 @@
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
 #include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/wl12xx.h>
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
@@ -45,6 +47,18 @@
 
 #define GPIO_HUB_POWER          1
 #define GPIO_HUB_NRESET         62
+#define GPIO_WIFI_PMENA         43
+#define GPIO_WIFI_IRQ           53
+
+/* wl127x BT, FM, GPS connectivity chip */
+static int wl1271_gpios[] = {46, -1, -1};
+static struct platform_device wl1271_device = {
+        .name   = "kim",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &wl1271_gpios,
+        },
+};
 
 static struct gpio_led gpio_leds[] = {
         {
@@ -74,6 +88,7 @@ static struct platform_device leds_gpio = {
 
 static struct platform_device *panda_devices[] __initdata = {
         &leds_gpio,
+        &wl1271_device,
 };
 
 static void __init omap4_panda_init_early(void)
@@ -161,16 +176,62 @@ static struct omap2_hsmmc_info mmc[] = {
                 .gpio_wp        = -EINVAL,
                 .gpio_cd        = -EINVAL,
         },
+        {
+                .name           = "wl1271",
+                .mmc            = 5,
+                .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+                .gpio_wp        = -EINVAL,
+                .gpio_cd        = -EINVAL,
+                .ocr_mask       = MMC_VDD_165_195,
+                .nonremovable   = true,
+        },
         {}      /* Terminator */
 };
 
 static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
         {
                 .supply = "vmmc",
-                .dev_name = "mmci-omap-hs.0",
+                .dev_name = "omap_hsmmc.0",
+        },
+};
+
+static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
+        .supply = "vmmc",
+        .dev_name = "omap_hsmmc.4",
+};
+
+static struct regulator_init_data panda_vmmc5 = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = 1,
+        .consumer_supplies = &omap4_panda_vmmc5_supply,
+};
+
+static struct fixed_voltage_config panda_vwlan = {
+        .supply_name = "vwl1271",
+        .microvolts = 1800000, /* 1.8V */
+        .gpio = GPIO_WIFI_PMENA,
+        .startup_delay = 70000, /* 70msec */
+        .enable_high = 1,
+        .enabled_at_boot = 0,
+        .init_data = &panda_vmmc5,
+};
+
+static struct platform_device omap_vwlan_device = {
+        .name           = "reg-fixed-voltage",
+        .id             = 1,
+        .dev = {
+                .platform_data = &panda_vwlan,
         },
 };
 
+struct wl12xx_platform_data omap_panda_wlan_data  __initdata = {
+        .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
+        /* PANDA ref clock is 38.4 MHz */
+        .board_ref_clock = 2,
+};
+
 static int omap4_twl6030_hsmmc_late_init(struct device *dev)
 {
         int ret = 0;
@@ -304,7 +365,6 @@ static struct regulator_init_data omap4_panda_vana = {
         .constraints = {
                 .min_uV                 = 2100000,
                 .max_uV                 = 2100000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -316,7 +376,6 @@ static struct regulator_init_data omap4_panda_vcxio = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -328,7 +387,6 @@ static struct regulator_init_data omap4_panda_vdac = {
         .constraints = {
                 .min_uV                 = 1800000,
                 .max_uV                 = 1800000,
-                .apply_uV               = true,
                 .valid_modes_mask       = REGULATOR_MODE_NORMAL
                                         | REGULATOR_MODE_STANDBY,
                 .valid_ops_mask  = REGULATOR_CHANGE_MODE
@@ -390,6 +448,19 @@ static int __init omap4_panda_i2c_init(void)
 
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
+        /* WLAN IRQ - GPIO 53 */
+        OMAP4_MUX(GPMC_NCS3, OMAP_MUX_MODE3 | OMAP_PIN_INPUT),
+        /* WLAN POWER ENABLE - GPIO 43 */
+        OMAP4_MUX(GPMC_A19, OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT),
+        /* WLAN SDIO: MMC5 CMD */
+        OMAP4_MUX(SDMMC5_CMD, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 CLK */
+        OMAP4_MUX(SDMMC5_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        /* WLAN SDIO: MMC5 DAT[0-3] */
+        OMAP4_MUX(SDMMC5_DAT0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
+        OMAP4_MUX(SDMMC5_DAT3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP),
         { .reg_offset = OMAP_MUX_TERMINATOR },
 };
 #else
@@ -404,8 +475,12 @@ static void __init omap4_panda_init(void)
                 package = OMAP_PACKAGE_CBL;
         omap4_mux_init(board_mux, package);
 
+        if (wl12xx_set_platform_data(&omap_panda_wlan_data))
+                pr_err("error setting wl12xx data\n");
+
         omap4_panda_i2c_init();
         platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
+        platform_device_register(&omap_vwlan_device);
         omap_serial_init();
         omap4_twl6030_hsmmc_init(mmc);
         omap4_ehci_init();
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index a33ec0edec13..60f8db31763c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -358,9 +358,7 @@ static struct regulator_init_data overo_vmmc1 = {
         .consumer_supplies      = &overo_vmmc1_supply,
 };
 
-static struct twl4030_codec_audio_data overo_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data overo_audio_data;
 
 static struct twl4030_codec_data overo_codec_data = {
         .audio_mclk = 26000000,
@@ -411,8 +409,6 @@ static struct omap_board_config_kernel overo_config[] __initdata = {
 
 static void __init overo_init_early(void)
 {
-        omap_board_config = overo_config;
-        omap_board_config_size = ARRAY_SIZE(overo_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(mt46h32m32lf6_sdrc_params,
                                   mt46h32m32lf6_sdrc_params);
@@ -448,6 +444,8 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init overo_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = overo_config;
+        omap_board_config_size = ARRAY_SIZE(overo_config);
         overo_i2c_init();
         platform_add_devices(overo_devices, ARRAY_SIZE(overo_devices));
         omap_serial_init();
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index bdebcb7328e6..2af8b05e786d 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -33,7 +33,7 @@
 #include "sdram-nokia.h"
 
 static struct regulator_consumer_supply rm680_vemmc_consumers[] = {
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
 };
 
 /* Fixed regulator for internal eMMC */
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index e75e240cad67..5f1900c532ec 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -36,6 +36,8 @@
 
 #include <sound/tlv320aic3x.h>
 #include <sound/tpa6130a2-plat.h>
+#include <media/radio-si4713.h>
+#include <media/si4713.h>
 
 #include <../drivers/staging/iio/light/tsl2563.h>
 
@@ -47,6 +49,8 @@
 
 #define RX51_WL1251_POWER_GPIO          87
 #define RX51_WL1251_IRQ_GPIO            42
+#define RX51_FMTX_RESET_GPIO            163
+#define RX51_FMTX_IRQ                   53
 
 /* list all spi devices here */
 enum {
@@ -331,13 +335,13 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
 };
 
 static struct regulator_consumer_supply rx51_vmmc1_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.0");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
 
 static struct regulator_consumer_supply rx51_vaux3_supply =
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
 
 static struct regulator_consumer_supply rx51_vsim_supply =
-        REGULATOR_SUPPLY("vmmc_aux", "mmci-omap-hs.1");
+        REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
 
 static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
         /* tlv320aic3x analog supplies */
@@ -348,7 +352,7 @@ static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
         /* tpa6130a2 */
         REGULATOR_SUPPLY("Vdd", "2-0060"),
         /* Keep vmmc as last item. It is not iterated for newer boards */
-        REGULATOR_SUPPLY("vmmc", "mmci-omap-hs.1"),
+        REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
 };
 
 static struct regulator_consumer_supply rx51_vio_supplies[] = {
@@ -357,10 +361,14 @@ static struct regulator_consumer_supply rx51_vio_supplies[] = {
         REGULATOR_SUPPLY("DVDD", "2-0018"),
         REGULATOR_SUPPLY("IOVDD", "2-0019"),
         REGULATOR_SUPPLY("DVDD", "2-0019"),
+        /* Si4713 IO supply */
+        REGULATOR_SUPPLY("vio", "2-0063"),
 };
 
 static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
         REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
+        /* Si4713 supply */
+        REGULATOR_SUPPLY("vdd", "2-0063"),
 };
 
 static struct regulator_consumer_supply rx51_vdac_supply[] = {
@@ -511,6 +519,41 @@ static struct regulator_init_data rx51_vio = {
         .consumer_supplies      = rx51_vio_supplies,
 };
 
+static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
+        .gpio_reset     = RX51_FMTX_RESET_GPIO,
+};
+
+static struct i2c_board_info rx51_si4713_board_info __initdata_or_module = {
+        I2C_BOARD_INFO("si4713", SI4713_I2C_ADDR_BUSEN_HIGH),
+        .platform_data  = &rx51_si4713_i2c_data,
+};
+
+static struct radio_si4713_platform_data rx51_si4713_data __initdata_or_module = {
+        .i2c_bus        = 2,
+        .subdev_board_info = &rx51_si4713_board_info,
+};
+
+static struct platform_device rx51_si4713_dev __initdata_or_module = {
+        .name   = "radio-si4713",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &rx51_si4713_data,
+        },
+};
+
+static __init void rx51_init_si4713(void)
+{
+        int err;
+
+        err = gpio_request_one(RX51_FMTX_IRQ, GPIOF_DIR_IN, "si4713 irq");
+        if (err) {
+                printk(KERN_ERR "Cannot request si4713 irq gpio. %d\n", err);
+                return;
+        }
+        rx51_si4713_board_info.irq = gpio_to_irq(RX51_FMTX_IRQ);
+        platform_device_register(&rx51_si4713_dev);
+}
+
 static int rx51_twlgpio_setup(struct device *dev, unsigned gpio, unsigned n)
 {
         /* FIXME this gpio setup is just a placeholder for now */
@@ -699,6 +742,14 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
         .resource_config = twl4030_rconfig,
 };
 
+struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
+        .coexist        = 0,
+};
+
+struct twl4030_codec_data rx51_codec_data __initdata = {
+        .audio_mclk     = 26000000,
+        .vibra          = &rx51_vibra_data,
+};
 
 static struct twl4030_platform_data rx51_twldata __initdata = {
         .irq_base               = TWL4030_IRQ_BASE,
@@ -710,6 +761,7 @@ static struct twl4030_platform_data rx51_twldata __initdata = {
         .madc                   = &rx51_madc_data,
         .usb                    = &rx51_usb_data,
         .power                  = &rx51_t2scripts_data,
+        .codec                  = &rx51_codec_data,
 
         .vaux1                  = &rx51_vaux1,
         .vaux2                  = &rx51_vaux2,
@@ -921,6 +973,7 @@ void __init rx51_peripherals_init(void)
         board_smc91x_init();
         rx51_add_gpio_keys();
         rx51_init_wl1251();
+        rx51_init_si4713();
         spi_register_board_info(rx51_peripherals_spi_board_info,
                                 ARRAY_SIZE(rx51_peripherals_spi_board_info));
 
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index acd670054d9a..89a66db8b77d 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -66,18 +66,6 @@ static struct omap_dss_board_info rx51_dss_board_info = {
         .default_device = &rx51_lcd_device,
 };
 
-struct platform_device rx51_display_device = {
-        .name   = "omapdss",
-        .id     = -1,
-        .dev    = {
-                .platform_data = &rx51_dss_board_info,
-        },
-};
-
-static struct platform_device *rx51_video_devices[] __initdata = {
-        &rx51_display_device,
-};
-
 static int __init rx51_video_init(void)
 {
         if (!machine_is_nokia_rx51())
@@ -95,8 +83,7 @@ static int __init rx51_video_init(void)
 
         gpio_direction_output(RX51_LCD_RESET_GPIO, 1);
 
-        platform_add_devices(rx51_video_devices,
-                                ARRAY_SIZE(rx51_video_devices));
+        omap_display_init(&rx51_dss_board_info);
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 3cf72fe6d75b..e964895b80e8 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -102,9 +102,6 @@ static void __init rx51_init_early(void)
 {
         struct omap_sdrc_params *sdrc_params;
 
-        omap_board_config = rx51_config;
-        omap_board_config_size = ARRAY_SIZE(rx51_config);
-        omap3_pm_init_cpuidle(rx51_cpuidle_params);
         omap2_init_common_infrastructure();
         sdrc_params = nokia_get_sdram_timings();
         omap2_init_common_devices(sdrc_params, sdrc_params);
@@ -127,6 +124,9 @@ static struct omap_musb_board_data musb_board_data = {
 static void __init rx51_init(void)
 {
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
+        omap_board_config = rx51_config;
+        omap_board_config_size = ARRAY_SIZE(rx51_config);
+        omap3_pm_init_cpuidle(rx51_cpuidle_params);
         omap_serial_init();
         usb_musb_init(&musb_board_data);
         rx51_peripherals_init();
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index f2b097190e07..09fa7bfff8d6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -29,8 +29,6 @@ static struct omap_board_config_kernel ti8168_evm_config[] __initdata = {
 
 static void __init ti8168_init_early(void)
 {
-        omap_board_config = ti8168_evm_config;
-        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
         omap2_init_common_infrastructure();
         omap2_init_common_devices(NULL, NULL);
 }
@@ -43,6 +41,8 @@ static void __init ti8168_evm_init_irq(void)
 static void __init ti8168_evm_init(void)
 {
         omap_serial_init();
+        omap_board_config = ti8168_evm_config;
+        omap_board_config_size = ARRAY_SIZE(ti8168_evm_config);
 }
 
 static void __init ti8168_evm_map_io(void)
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 6bcd43657aed..37b84c2b850f 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -130,14 +130,6 @@ static struct omap_dss_board_info zoom_dss_data = {
         .default_device         = &zoom_lcd_device,
 };
 
-static struct platform_device zoom_dss_device = {
-        .name                           = "omapdss",
-        .id                             = -1,
-        .dev                            = {
-                .platform_data          = &zoom_dss_data,
-        },
-};
-
 static struct omap2_mcspi_device_config dss_lcd_mcspi_config = {
         .turbo_mode             = 1,
         .single_channel = 1,  /* 0: slave, 1: master */
@@ -153,14 +145,9 @@ static struct spi_board_info nec_8048_spi_board_info[] __initdata = {
         },
 };
 
-static struct platform_device *zoom_display_devices[] __initdata = {
-        &zoom_dss_device,
-};
-
 void __init zoom_display_init(void)
 {
-        platform_add_devices(zoom_display_devices,
-                                ARRAY_SIZE(zoom_display_devices));
+        omap_display_init(&zoom_dss_data);
         spi_register_board_info(nec_8048_spi_board_info,
                                 ARRAY_SIZE(nec_8048_spi_board_info));
         zoom_lcd_panel_init();
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index e0e040f34c68..448ab60195d5 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -118,7 +118,7 @@ static struct regulator_consumer_supply zoom_vmmc2_supply = {
 
 static struct regulator_consumer_supply zoom_vmmc3_supply = {
         .supply         = "vmmc",
-        .dev_name       = "mmci-omap-hs.2",
+        .dev_name       = "omap_hsmmc.2",
 };
 
 /* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -322,9 +322,7 @@ static struct twl4030_madc_platform_data zoom_madc_data = {
         .irq_line       = 1,
 };
 
-static struct twl4030_codec_audio_data zoom_audio_data = {
-        .audio_mclk = 26000000,
-};
+static struct twl4030_codec_audio_data zoom_audio_data;
 
 static struct twl4030_codec_data zoom_codec_data = {
         .audio_mclk = 26000000,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 85d4170f30ab..7e3f1595d77b 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -16,6 +16,7 @@
 #include <linux/input.h>
 #include <linux/gpio.h>
 #include <linux/i2c/twl.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -124,8 +125,8 @@ static void __init omap_zoom_init(void)
                 usb_ehci_init(&ehci_pdata);
         }
 
-        board_nand_init(zoom_nand_partitions,
-                        ARRAY_SIZE(zoom_nand_partitions), ZOOM_NAND_CS);
+        board_nand_init(zoom_nand_partitions, ARRAY_SIZE(zoom_nand_partitions),
+                                                ZOOM_NAND_CS, NAND_BUSWIDTH_16);
         zoom_debugboard_init();
         zoom_peripherals_init();
         zoom_display_init();
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index f51cffd1fc53..b19a1f7234ae 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -78,6 +78,26 @@ static int omap2_clk_apll54_enable(struct clk *clk)
         return omap2_clk_apll_enable(clk, OMAP24XX_ST_54M_APLL_MASK);
 }
 
+static void _apll96_allow_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll96_auto_low_power_stop();
+}
+
+static void _apll96_deny_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll96_disable_autoidle();
+}
+
+static void _apll54_allow_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll54_auto_low_power_stop();
+}
+
+static void _apll54_deny_idle(struct clk *clk)
+{
+        omap2xxx_cm_set_apll54_disable_autoidle();
+}
+
 /* Stop APLL */
 static void omap2_clk_apll_disable(struct clk *clk)
 {
@@ -93,11 +113,15 @@ static void omap2_clk_apll_disable(struct clk *clk)
 const struct clkops clkops_apll96 = {
         .enable         = omap2_clk_apll96_enable,
         .disable        = omap2_clk_apll_disable,
+        .allow_idle     = _apll96_allow_idle,
+        .deny_idle      = _apll96_deny_idle,
 };
 
 const struct clkops clkops_apll54 = {
         .enable         = omap2_clk_apll54_enable,
         .disable        = omap2_clk_apll_disable,
+        .allow_idle     = _apll54_allow_idle,
+        .deny_idle      = _apll54_deny_idle,
 };
 
 /* Public functions */
diff --git a/arch/arm/mach-omap2/clkt2xxx_dpll.c b/arch/arm/mach-omap2/clkt2xxx_dpll.c
new file mode 100644
index 000000000000..1502a7bc20bb
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt2xxx_dpll.c
@@ -0,0 +1,63 @@
+/*
+ * OMAP2-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/**
+ * _allow_idle - enable DPLL autoidle bits
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Enable DPLL automatic idle control.  The DPLL will enter low-power
+ * stop when its downstream clocks are gated.  No return value.
+ * REVISIT: DPLL can optionally enter low-power bypass by writing 0x1
+ * instead.  Add some mechanism to optionally enter this mode.
+ */
+static void _allow_idle(struct clk *clk)
+{
+        if (!clk || !clk->dpll_data)
+                return;
+
+        omap2xxx_cm_set_dpll_auto_low_power_stop();
+}
+
+/**
+ * _deny_idle - prevent DPLL from automatically idling
+ * @clk: struct clk * of the DPLL to operate on
+ *
+ * Disable DPLL automatic idle control.  No return value.
+ */
+static void _deny_idle(struct clk *clk)
+{
+        if (!clk || !clk->dpll_data)
+                return;
+
+        omap2xxx_cm_set_dpll_disable_autoidle();
+}
+
+
+/* Public data */
+
+const struct clkops clkops_omap2xxx_dpll_ops = {
+        .allow_idle     = _allow_idle,
+        .deny_idle      = _deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
index df7b80506483..c3460928b5e0 100644
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ b/arch/arm/mach-omap2/clkt2xxx_osc.c
@@ -30,6 +30,13 @@
 #include "prm2xxx_3xxx.h"
 #include "prm-regbits-24xx.h"
 
+/*
+ * XXX This does not actually enable the osc_ck, since the osc_ck must
+ * be running for this function to be called.  Instead, this function
+ * is used to disable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static int omap2_enable_osc_ck(struct clk *clk)
 {
         u32 pcc;
@@ -41,6 +48,13 @@ static int omap2_enable_osc_ck(struct clk *clk)
         return 0;
 }
 
+/*
+ * XXX This does not actually disable the osc_ck, since doing so would
+ * immediately halt the system.  Instead, this function is used to
+ * enable an autoidle mode on the osc_ck.  The existing
+ * clk_enable/clk_disable()-based usecounting for osc_ck should be
+ * replaced with autoidle-based usecounting.
+ */
 static void omap2_disable_osc_ck(struct clk *clk)
 {
         u32 pcc;
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index a781cd6795a4..e25364de028a 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -97,7 +97,7 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
                                 u32 *field_val)
 {
         const struct clksel *clks;
-        const struct clksel_rate *clkr, *max_clkr;
+        const struct clksel_rate *clkr, *max_clkr = NULL;
         u8 max_div = 0;
 
         clks = _get_clksel_by_parent(clk, src_clk);
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 337392c3f549..bcffee001bfa 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -77,7 +77,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         dd = clk->dpll_data;
 
         /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / (n + 1);
+        fint = clk->parent->rate / n;
         if (fint < DPLL_FINT_BAND1_MIN) {
 
                 pr_debug("rejecting n=%d due to Fint failure, "
@@ -178,12 +178,11 @@ void omap2_init_dpll_parent(struct clk *clk)
         if (!dd)
                 return;
 
-        /* Return bypass rate if DPLL is bypassed */
         v = __raw_readl(dd->control_reg);
         v &= dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
 
-        /* Reparent in case the dpll is in bypass */
+        /* Reparent the struct clk in case the dpll is in bypass */
         if (cpu_is_omap24xx()) {
                 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP2XXX_EN_DPLL_FRBYPASS)
@@ -260,50 +259,22 @@ u32 omap2_get_dpll_rate(struct clk *clk)
 /* DPLL rate rounding code */
 
 /**
- * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
- * @clk: struct clk * of the DPLL
- * @tolerance: maximum rate error tolerance
- *
- * Set the maximum DPLL rate error tolerance for the rate rounding
- * algorithm.  The rate tolerance is an attempt to balance DPLL power
- * saving (the least divider value "n") vs. rate fidelity (the least
- * difference between the desired DPLL target rate and the rounded
- * rate out of the algorithm).  So, increasing the tolerance is likely
- * to decrease DPLL power consumption and increase DPLL rate error.
- * Returns -EINVAL if provided a null clock ptr or a clk that is not a
- * DPLL; or 0 upon success.
- */
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
-{
-        if (!clk || !clk->dpll_data)
-                return -EINVAL;
-
-        clk->dpll_data->rate_tolerance = tolerance;
-
-        return 0;
-}
-
-/**
  * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
  * @clk: struct clk * for a DPLL
  * @target_rate: desired DPLL clock rate
  *
- * Given a DPLL, a desired target rate, and a rate tolerance, round
- * the target rate to a possible, programmable rate for this DPLL.
- * Rate tolerance is assumed to be set by the caller before this
- * function is called.  Attempts to select the minimum possible n
- * within the tolerance to reduce power consumption.  Stores the
- * computed (m, n) in the DPLL's dpll_data structure so set_rate()
- * will not need to call this (expensive) function again.  Returns ~0
- * if the target rate cannot be rounded, either because the rate is
- * too low or because the rate tolerance is set too tightly; or the
- * rounded rate upon success.
+ * Given a DPLL and a desired target rate, round the target rate to a
+ * possible, programmable rate for this DPLL.  Attempts to select the
+ * minimum possible n.  Stores the computed (m, n) in the DPLL's
+ * dpll_data structure so set_rate() will not need to call this
+ * (expensive) function again.  Returns ~0 if the target rate cannot
+ * be rounded, or the rounded rate upon success.
  */
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 {
-        int m, n, r, e, scaled_max_m;
-        unsigned long scaled_rt_rp, new_rate;
-        int min_e = -1, min_e_m = -1, min_e_n = -1;
+        int m, n, r, scaled_max_m;
+        unsigned long scaled_rt_rp;
+        unsigned long new_rate = 0;
         struct dpll_data *dd;
 
         if (!clk || !clk->dpll_data)
@@ -311,8 +282,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
 
         dd = clk->dpll_data;
 
-        pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
-                 "%ld\n", clk->name, target_rate);
+        pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
+                 clk->name, target_rate);
 
         scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
         scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
@@ -347,39 +318,23 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
-                e = target_rate - new_rate;
-                pr_debug("clock: n = %d: m = %d: rate error is %d "
-                         "(new_rate = %ld)\n", n, m, e, new_rate);
-
-                if (min_e == -1 ||
-                    min_e >= (int)(abs(e) - dd->rate_tolerance)) {
-                        min_e = e;
-                        min_e_m = m;
-                        min_e_n = n;
-
-                        pr_debug("clock: found new least error %d\n", min_e);
+                pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
+                         clk->name, m, n, new_rate);
 
-                        /* We found good settings -- bail out now */
-                        if (min_e <= dd->rate_tolerance)
-                                break;
+                if (target_rate == new_rate) {
+                        dd->last_rounded_m = m;
+                        dd->last_rounded_n = n;
+                        dd->last_rounded_rate = target_rate;
+                        break;
                 }
         }
 
-        if (min_e < 0) {
-                pr_debug("clock: error: target rate or tolerance too low\n");
+        if (target_rate != new_rate) {
+                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
+                         target_rate);
                 return ~0;
         }
 
-        dd->last_rounded_m = min_e_m;
-        dd->last_rounded_n = min_e_n;
-        dd->last_rounded_rate = _dpll_compute_new_rate(dd->clk_ref->rate,
-                                                       min_e_m,  min_e_n);
-
-        pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
-                 min_e, min_e_m, min_e_n);
-        pr_debug("clock: final rate: %ld  (target rate: %ld)\n",
-                 dd->last_rounded_rate, target_rate);
-
-        return dd->last_rounded_rate;
+        return target_rate;
 }
 
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c
new file mode 100644
index 000000000000..3d43fba2542f
--- /dev/null
+++ b/arch/arm/mach-omap2/clkt_iclk.c
@@ -0,0 +1,82 @@
+/*
+ * OMAP2/3 interface clock control
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#undef DEBUG
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+
+#include <plat/clock.h>
+#include <plat/prcm.h>
+
+#include "clock.h"
+#include "clock2xxx.h"
+#include "cm2xxx_3xxx.h"
+#include "cm-regbits-24xx.h"
+
+/* Private functions */
+
+/* XXX */
+void omap2_clkt_iclk_allow_idle(struct clk *clk)
+{
+        u32 v, r;
+
+        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+        v = __raw_readl((__force void __iomem *)r);
+        v |= (1 << clk->enable_bit);
+        __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* XXX */
+void omap2_clkt_iclk_deny_idle(struct clk *clk)
+{
+        u32 v, r;
+
+        r = ((__force u32)clk->enable_reg ^ (CM_AUTOIDLE ^ CM_ICLKEN));
+
+        v = __raw_readl((__force void __iomem *)r);
+        v &= ~(1 << clk->enable_bit);
+        __raw_writel(v, (__force void __iomem *)r);
+}
+
+/* Public data */
+
+const struct clkops clkops_omap2_iclk_dflt_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_dflt = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_iclk_idle_only = {
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
+const struct clkops clkops_omap2_mdmclk_dflt_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .find_idlest    = omap2_clk_dflt_find_idlest,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e9625fcf6390..46d03ccc2806 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -261,7 +261,8 @@ void omap2_clk_disable(struct clk *clk)
 
         pr_debug("clock: %s: disabling in hardware\n", clk->name);
 
-        clk->ops->disable(clk);
+        if (clk->ops && clk->ops->disable)
+                clk->ops->disable(clk);
 
         if (clk->clkdm)
                 clkdm_clk_disable(clk->clkdm, clk);
@@ -312,10 +313,13 @@ int omap2_clk_enable(struct clk *clk)
                 }
         }
 
-        ret = clk->ops->enable(clk);
-        if (ret) {
-                WARN(1, "clock: %s: could not enable: %d\n", clk->name, ret);
-                goto oce_err3;
+        if (clk->ops && clk->ops->enable) {
+                ret = clk->ops->enable(clk);
+                if (ret) {
+                        WARN(1, "clock: %s: could not enable: %d\n",
+                             clk->name, ret);
+                        goto oce_err3;
+                }
         }
 
         return 0;
@@ -373,10 +377,16 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
 const struct clkops clkops_omap3_noncore_dpll_ops = {
         .enable         = omap3_noncore_dpll_enable,
         .disable        = omap3_noncore_dpll_disable,
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
 };
 
-#endif
+const struct clkops clkops_omap3_core_dpll_ops = {
+        .allow_idle     = omap3_dpll_allow_idle,
+        .deny_idle      = omap3_dpll_deny_idle,
+};
 
+#endif
 
 /*
  * OMAP2+ clock reset and init functions
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 896584e3c4ab..e10ff2b54844 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -2,7 +2,7 @@
  *  linux/arch/arm/mach-omap2/clock.h
  *
  *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2009 Nokia Corporation
+ *  Copyright (C) 2004-2011 Nokia Corporation
  *
  *  Contacts:
  *  Richard Woodruff <r-woodruff2@ti.com>
@@ -18,9 +18,6 @@
 
 #include <plat/clock.h>
 
-/* The maximum error between a target DPLL rate and the rounded rate in Hz */
-#define DEFAULT_DPLL_RATE_TOLERANCE     50000
-
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
 #define CORE_CLK_SRC_32K                0x0
 #define CORE_CLK_SRC_DPLL               0x1
@@ -55,7 +52,6 @@ void omap2_clk_disable(struct clk *clk);
 long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
-int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
 unsigned long omap3_dpll_recalc(struct clk *clk);
 unsigned long omap3_clkoutx2_recalc(struct clk *clk);
@@ -65,6 +61,9 @@ u32 omap3_dpll_autoidle_read(struct clk *clk);
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
 int omap3_noncore_dpll_enable(struct clk *clk);
 void omap3_noncore_dpll_disable(struct clk *clk);
+int omap4_dpllmx_gatectrl_read(struct clk *clk);
+void omap4_dpllmx_allow_gatectrl(struct clk *clk);
+void omap4_dpllmx_deny_gatectrl(struct clk *clk);
 
 #ifdef CONFIG_OMAP_RESET_CLOCKS
 void omap2_clk_disable_unused(struct clk *clk);
@@ -83,6 +82,10 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent);
 
+/* clkt_iclk.c public functions */
+extern void omap2_clkt_iclk_allow_idle(struct clk *clk);
+extern void omap2_clkt_iclk_deny_idle(struct clk *clk);
+
 u32 omap2_get_dpll_rate(struct clk *clk);
 void omap2_init_dpll_parent(struct clk *clk);
 
@@ -136,6 +139,7 @@ extern struct clk *vclk, *sclk;
 extern const struct clksel_rate gpt_32k_rates[];
 extern const struct clksel_rate gpt_sys_rates[];
 extern const struct clksel_rate gfx_l3_rates[];
+extern const struct clksel_rate dsp_ick_rates[];
 
 #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ)
 extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
@@ -145,6 +149,13 @@ extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 #define omap2_clk_exit_cpufreq_table    0
 #endif
 
+extern const struct clkops clkops_omap2_iclk_dflt_wait;
+extern const struct clkops clkops_omap2_iclk_dflt;
+extern const struct clkops clkops_omap2_iclk_idle_only;
+extern const struct clkops clkops_omap2_mdmclk_dflt_wait;
+extern const struct clkops clkops_omap2xxx_dpll_ops;
 extern const struct clkops clkops_omap3_noncore_dpll_ops;
+extern const struct clkops clkops_omap3_core_dpll_ops;
+extern const struct clkops clkops_omap4_dpllmx_ops;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 0a992bc8d0d8..b6f65d4ac97d 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1,12 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap2/clock2420_data.c
+ * OMAP2420 clock data
  *
- *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
  *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -34,18 +34,15 @@
 /*
  * 2420 clock tree.
  *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
  *
  *      Several sources are given initial rates which may be wrong, this will
  *      be fixed up in the init func.
  *
  *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
+ *      noteworthy that most peripherals have dependencies on multiple clock
  *      domains. Many get their interface clocks from the L4 domain, but get
  *      functional clocks from fixed sources or other core domain derived
  *      clocks.
@@ -55,7 +52,7 @@
 static struct clk func_32k_ck = {
         .name           = "func_32k_ck",
         .ops            = &clkops_null,
-        .rate           = 32000,
+        .rate           = 32768,
         .clkdm_name     = "wkup_clkdm",
 };
 
@@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
         .max_multiplier         = 1023,
         .min_divider            = 1,
         .max_divider            = 16,
-        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 /*
@@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2xxx_dpll_ops,
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .clkdm_name     = "wkup_clkdm",
@@ -455,36 +451,22 @@ static struct clk dsp_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DSP interface clock */
-static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 0 },
-};
-
-static const struct clksel dsp_irate_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
         { .parent = NULL }
 };
 
-/* This clock does not exist as such in the TRM. */
-static struct clk dsp_irate_ick = {
-        .name           = "dsp_irate_ick",
-        .ops            = &clkops_null,
-        .parent         = &dsp_fck,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_irate_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
-/* 2420 only */
 static struct clk dsp_ick = {
         .name           = "dsp_ick",     /* apparently ipi and isp */
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dsp_irate_ick,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2420_EN_DSP_IPI_SHIFT,          /* for ipi */
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /*
@@ -579,7 +561,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,7 +643,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
         .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -716,6 +698,7 @@ static struct clk gfx_2d_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
         .name           = "gfx_ick",            /* From l3 */
         .ops            = &clkops_omap2_dflt_wait,
@@ -763,7 +746,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,       /* really both l3 and l4 */
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -825,6 +808,14 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
         .recalc         = &followparent_recalc,
 };
 
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /*
  * CORE power domain ICLK & FCLK defines.
  * Many of the these can have more than one possible parent. Entries
@@ -845,9 +836,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -871,7 +862,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -895,7 +886,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -919,7 +910,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -943,7 +934,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -967,7 +958,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -991,8 +982,9 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1014,7 +1006,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1038,7 +1030,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1062,7 +1054,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1086,7 +1078,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1110,7 +1102,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1134,7 +1126,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1174,7 +1166,7 @@ static struct clk mcbsp1_fck = {
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1198,7 +1190,7 @@ static struct clk mcbsp2_fck = {
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1218,7 +1210,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1238,7 +1230,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1258,7 +1250,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1270,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1298,9 +1290,9 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
         .name           = "gpios_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1318,9 +1310,9 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
         .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1338,10 +1330,10 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
         .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1349,9 +1341,9 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1359,10 +1351,10 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1370,7 +1362,7 @@ static struct clk omapctrl_ick = {
 
 static struct clk cam_ick = {
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1395,7 +1387,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1405,7 +1397,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
         .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1425,7 +1417,7 @@ static struct clk wdt4_fck = {
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1445,7 +1437,7 @@ static struct clk wdt3_fck = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1465,7 +1457,7 @@ static struct clk mspro_fck = {
 
 static struct clk mmc_ick = {
         .name           = "mmc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1477,7 @@ static struct clk mmc_fck = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1505,7 +1497,7 @@ static struct clk fac_fck = {
 
 static struct clk eac_ick = {
         .name           = "eac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1525,7 +1517,7 @@ static struct clk eac_fck = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1545,7 +1537,7 @@ static struct clk hdq_fck = {
 
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1565,7 +1557,7 @@ static struct clk i2c2_fck = {
 
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1583,12 +1575,18 @@ static struct clk i2c1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
+        .ops            = &clkops_omap2_iclk_idle_only,
         .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
@@ -1600,17 +1598,38 @@ static struct clk sdma_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
         .name           = "sdma_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
+        .recalc         = &followparent_recalc,
+};
+
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
+static struct clk sdrc_ick = {
+        .name           = "sdrc_ick",
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
+        .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDRC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk vlynq_ick = {
         .name           = "vlynq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1659,7 +1678,7 @@ static struct clk vlynq_fck = {
 
 static struct clk des_ick = {
         .name           = "des_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1688,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
         .name           = "sha_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1698,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1708,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
         .name           = "aes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1718,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1777,7 +1796,6 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
         /* dsp domain clocks */
         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_242X),
         CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
         CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
         CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
@@ -1797,6 +1815,7 @@ static struct omap_clk omap2420_clks[] = {
         /* L4 domain clocks */
         CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_242X),
         /* virtual meta-group clock */
         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
         /* general l4 interface ck, multi-parent functional clk */
@@ -1869,6 +1888,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
         CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
         CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
@@ -1913,6 +1933,9 @@ int __init omap2420_clk_init(void)
                 omap2_init_clk_clkdm(c->lk.clk);
         }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         /* Check the MPU rate set by bootloader */
         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index c047dcd007e5..bba018331a71 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1,12 +1,12 @@
 /*
- *  linux/arch/arm/mach-omap2/clock2430_data.c
+ * OMAP2430 clock data
  *
- *  Copyright (C) 2005-2009 Texas Instruments, Inc.
- *  Copyright (C) 2004-2010 Nokia Corporation
+ * Copyright (C) 2005-2009 Texas Instruments, Inc.
+ * Copyright (C) 2004-2011 Nokia Corporation
  *
- *  Contacts:
- *  Richard Woodruff <r-woodruff2@ti.com>
- *  Paul Walmsley
+ * Contacts:
+ * Richard Woodruff <r-woodruff2@ti.com>
+ * Paul Walmsley
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -34,18 +34,15 @@
 /*
  * 2430 clock tree.
  *
- * NOTE:In many cases here we are assigning a 'default' parent. In many
- *      cases the parent is selectable. The get/set parent calls will also
- *      switch sources.
- *
- *      Many some clocks say always_enabled, but they can be auto idled for
- *      power savings. They will always be available upon clock request.
+ * NOTE:In many cases here we are assigning a 'default' parent. In
+ *      many cases the parent is selectable. The set parent calls will
+ *      also switch sources.
  *
  *      Several sources are given initial rates which may be wrong, this will
  *      be fixed up in the init func.
  *
  *      Things are broadly separated below by clock domains. It is
- *      noteworthy that most periferals have dependencies on multiple clock
+ *      noteworthy that most peripherals have dependencies on multiple clock
  *      domains. Many get their interface clocks from the L4 domain, but get
  *      functional clocks from fixed sources or other core domain derived
  *      clocks.
@@ -55,7 +52,7 @@
 static struct clk func_32k_ck = {
         .name           = "func_32k_ck",
         .ops            = &clkops_null,
-        .rate           = 32000,
+        .rate           = 32768,
         .clkdm_name     = "wkup_clkdm",
 };
 
@@ -116,7 +113,6 @@ static struct dpll_data dpll_dd = {
         .max_multiplier         = 1023,
         .min_divider            = 1,
         .max_divider            = 16,
-        .rate_tolerance         = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 /*
@@ -125,7 +121,7 @@ static struct dpll_data dpll_dd = {
  */
 static struct clk dpll_ck = {
         .name           = "dpll_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap2xxx_dpll_ops,
         .parent         = &sys_ck,              /* Can be func_32k also */
         .dpll_data      = &dpll_dd,
         .clkdm_name     = "wkup_clkdm",
@@ -434,37 +430,23 @@ static struct clk dsp_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
-/* DSP interface clock */
-static const struct clksel_rate dsp_irate_ick_rates[] = {
-        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
-        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
-        { .div = 3, .val = 3, .flags = RATE_IN_243X },
-        { .div = 0 },
-};
-
-static const struct clksel dsp_irate_ick_clksel[] = {
-        { .parent = &dsp_fck, .rates = dsp_irate_ick_rates },
+static const struct clksel dsp_ick_clksel[] = {
+        { .parent = &dsp_fck, .rates = dsp_ick_rates },
         { .parent = NULL }
 };
 
-/* This clock does not exist as such in the TRM. */
-static struct clk dsp_irate_ick = {
-        .name           = "dsp_irate_ick",
-        .ops            = &clkops_null,
-        .parent         = &dsp_fck,
-        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
-        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
-        .clksel         = dsp_irate_ick_clksel,
-        .recalc         = &omap2_clksel_recalc,
-};
-
 /* 2430 only - EN_DSP controls both dsp fclk and iclk on 2430 */
 static struct clk iva2_1_ick = {
         .name           = "iva2_1_ick",
         .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &dsp_irate_ick,
+        .parent         = &dsp_fck,
+        .clkdm_name     = "dsp_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
+        .clksel_reg     = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
+        .clksel_mask    = OMAP24XX_CLKSEL_DSP_IF_MASK,
+        .clksel         = dsp_ick_clksel,
+        .recalc         = &omap2_clksel_recalc,
 };
 
 /*
@@ -525,7 +507,7 @@ static const struct clksel usb_l4_ick_clksel[] = {
 /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
 static struct clk usb_l4_ick = {        /* FS-USB interface clock */
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -606,7 +588,7 @@ static struct clk ssi_ssr_sst_fck = {
  */
 static struct clk ssi_l4_ick = {
         .name           = "ssi_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -661,6 +643,7 @@ static struct clk gfx_2d_fck = {
         .recalc         = &omap2_clksel_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk gfx_ick = {
         .name           = "gfx_ick",            /* From l3 */
         .ops            = &clkops_omap2_dflt_wait,
@@ -693,7 +676,7 @@ static const struct clksel mdm_ick_clksel[] = {
 
 static struct clk mdm_ick = {           /* used both as a ick and fck */
         .name           = "mdm_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_ck,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
@@ -706,7 +689,7 @@ static struct clk mdm_ick = {		/* used both as a ick and fck */
 
 static struct clk mdm_osc_ck = {
         .name           = "mdm_osc_ck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
         .parent         = &osc_ck,
         .clkdm_name     = "mdm_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
@@ -751,7 +734,7 @@ static const struct clksel dss1_fck_clksel[] = {
 
 static struct clk dss_ick = {           /* Enables both L3,L4 ICLK's */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,       /* really both l3 and l4 */
         .clkdm_name     = "dss_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -813,6 +796,14 @@ static struct clk dss_54m_fck = {	/* Alt clk used in power management */
         .recalc         = &followparent_recalc,
 };
 
+static struct clk wu_l4_ick = {
+        .name           = "wu_l4_ick",
+        .ops            = &clkops_null,
+        .parent         = &sys_ck,
+        .clkdm_name     = "wkup_clkdm",
+        .recalc         = &followparent_recalc,
+};
+
 /*
  * CORE power domain ICLK & FCLK defines.
  * Many of the these can have more than one possible parent. Entries
@@ -833,9 +824,9 @@ static const struct clksel omap24xx_gpt_clksel[] = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -859,7 +850,7 @@ static struct clk gpt1_fck = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -883,7 +874,7 @@ static struct clk gpt2_fck = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -907,7 +898,7 @@ static struct clk gpt3_fck = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -931,7 +922,7 @@ static struct clk gpt4_fck = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -955,7 +946,7 @@ static struct clk gpt5_fck = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -979,8 +970,9 @@ static struct clk gpt6_fck = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP24XX_EN_GPT7_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1002,7 +994,7 @@ static struct clk gpt7_fck = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1026,7 +1018,7 @@ static struct clk gpt8_fck = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1050,7 +1042,7 @@ static struct clk gpt9_fck = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1074,7 +1066,7 @@ static struct clk gpt10_fck = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1098,7 +1090,7 @@ static struct clk gpt11_fck = {
 
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1122,7 +1114,7 @@ static struct clk gpt12_fck = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1162,7 +1154,7 @@ static struct clk mcbsp1_fck = {
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1186,7 +1178,7 @@ static struct clk mcbsp2_fck = {
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1210,7 +1202,7 @@ static struct clk mcbsp3_fck = {
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1234,7 +1226,7 @@ static struct clk mcbsp4_fck = {
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1258,7 +1250,7 @@ static struct clk mcbsp5_fck = {
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1278,7 +1270,7 @@ static struct clk mcspi1_fck = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1298,7 +1290,7 @@ static struct clk mcspi2_fck = {
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1318,7 +1310,7 @@ static struct clk mcspi3_fck = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1338,7 +1330,7 @@ static struct clk uart1_fck = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1358,7 +1350,7 @@ static struct clk uart2_fck = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1378,9 +1370,9 @@ static struct clk uart3_fck = {
 
 static struct clk gpios_ick = {
         .name           = "gpios_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_GPIOS_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1398,9 +1390,9 @@ static struct clk gpios_fck = {
 
 static struct clk mpu_wdt_ick = {
         .name           = "mpu_wdt_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_MPU_WDT_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1418,10 +1410,10 @@ static struct clk mpu_wdt_fck = {
 
 static struct clk sync_32k_ick = {
         .name           = "sync_32k_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_32KSYNC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1429,9 +1421,9 @@ static struct clk sync_32k_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_WDT1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1439,10 +1431,10 @@ static struct clk wdt1_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP24XX_EN_OMAPCTRL_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1450,9 +1442,9 @@ static struct clk omapctrl_ick = {
 
 static struct clk icr_ick = {
         .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
-        .clkdm_name     = "core_l4_clkdm",
+        .ops            = &clkops_omap2_iclk_dflt_wait,
+        .parent         = &wu_l4_ick,
+        .clkdm_name     = "wkup_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP2430_EN_ICR_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1460,7 +1452,7 @@ static struct clk icr_ick = {
 
 static struct clk cam_ick = {
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1485,7 +1477,7 @@ static struct clk cam_fck = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1495,7 +1487,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk wdt4_ick = {
         .name           = "wdt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1515,7 +1507,7 @@ static struct clk wdt4_fck = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1535,7 +1527,7 @@ static struct clk mspro_fck = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1555,7 +1547,7 @@ static struct clk fac_fck = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1579,7 +1571,7 @@ static struct clk hdq_fck = {
  */
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1603,7 +1595,7 @@ static struct clk i2chs2_fck = {
  */
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1621,12 +1613,18 @@ static struct clk i2chs1_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk gpmc_fck = {
         .name           = "gpmc_fck",
-        .ops            = &clkops_null, /* RMK: missing? */
+        .ops            = &clkops_omap2_iclk_idle_only,
         .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_GPMC_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
@@ -1638,20 +1636,26 @@ static struct clk sdma_fck = {
         .recalc         = &followparent_recalc,
 };
 
+/*
+ * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
+ * accesses derived from this data.
+ */
 static struct clk sdma_ick = {
         .name           = "sdma_ick",
-        .ops            = &clkops_null, /* RMK: missing? */
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
+        .enable_bit     = OMAP24XX_AUTO_SDMA_SHIFT,
         .recalc         = &followparent_recalc,
 };
 
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &l4_ck,
+        .ops            = &clkops_omap2_iclk_idle_only,
+        .parent         = &core_l3_ck,
         .flags          = ENABLE_ON_INIT,
-        .clkdm_name     = "core_l4_clkdm",
+        .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP2430_EN_SDRC_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1659,7 +1663,7 @@ static struct clk sdrc_ick = {
 
 static struct clk des_ick = {
         .name           = "des_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1669,7 +1673,7 @@ static struct clk des_ick = {
 
 static struct clk sha_ick = {
         .name           = "sha_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1679,7 +1683,7 @@ static struct clk sha_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1689,7 +1693,7 @@ static struct clk rng_ick = {
 
 static struct clk aes_ick = {
         .name           = "aes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1699,7 +1703,7 @@ static struct clk aes_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
@@ -1719,7 +1723,7 @@ static struct clk usb_fck = {
 
 static struct clk usbhs_ick = {
         .name           = "usbhs_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l3_ck,
         .clkdm_name     = "core_l3_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1729,7 +1733,7 @@ static struct clk usbhs_ick = {
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1741,7 +1745,7 @@ static struct clk mmchs1_fck = {
         .name           = "mmchs1_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
-        .clkdm_name     = "core_l3_clkdm",
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS1_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1749,7 +1753,7 @@ static struct clk mmchs1_fck = {
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1761,6 +1765,7 @@ static struct clk mmchs2_fck = {
         .name           = "mmchs2_fck",
         .ops            = &clkops_omap2_dflt_wait,
         .parent         = &func_96m_ck,
+        .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
         .enable_bit     = OMAP2430_EN_MMCHS2_SHIFT,
         .recalc         = &followparent_recalc,
@@ -1768,7 +1773,7 @@ static struct clk mmchs2_fck = {
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1788,7 +1793,7 @@ static struct clk gpio5_fck = {
 
 static struct clk mdm_intc_ick = {
         .name           = "mdm_intc_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ck,
         .clkdm_name     = "core_l4_clkdm",
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1880,7 +1885,6 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
         /* dsp domain clocks */
         CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
-        CLK(NULL,       "dsp_irate_ick", &dsp_irate_ick, CK_243X),
         CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
         /* GFX domain clocks */
         CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
@@ -1901,6 +1905,7 @@ static struct omap_clk omap2430_clks[] = {
         /* L4 domain clocks */
         CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
         CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "wu_l4_ick",    &wu_l4_ick,     CK_243X),
         /* virtual meta-group clock */
         CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
         /* general l4 interface ck, multi-parent functional clk */
@@ -1984,15 +1989,15 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
-        CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
-        CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
-        CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
-        CLK("mmci-omap-hs.1", "fck",    &mmchs2_fck,    CK_243X),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK("omap_hsmmc.0", "fck",      &mmchs1_fck,    CK_243X),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK("omap_hsmmc.1", "fck",      &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("mmci-omap-hs.0", "mmchsdb_fck",    &mmchsdb1_fck,  CK_243X),
-        CLK("mmci-omap-hs.1", "mmchsdb_fck",    &mmchsdb2_fck,  CK_243X),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
 };
 
 /*
@@ -2028,6 +2033,9 @@ int __init omap2430_clk_init(void)
                 omap2_init_clk_clkdm(c->lk.clk);
         }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         /* Check the MPU rate set by bootloader */
         clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index cc5c8d422c5b..cb6df8ca9e4a 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -23,13 +23,13 @@ void omap2xxx_clk_prepare_for_reboot(void);
 #ifdef CONFIG_SOC_OMAP2420
 int omap2420_clk_init(void);
 #else
-#define omap2420_clk_init()     0
+#define omap2420_clk_init()     do { } while(0)
 #endif
 
 #ifdef CONFIG_SOC_OMAP2430
 int omap2430_clk_init(void);
 #else
-#define omap2430_clk_init()     0
+#define omap2430_clk_init()     do { } while(0)
 #endif
 
 extern void __iomem *prcm_clksrc_ctrl, *cm_idlest_pll;
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 287abc480924..1fc96b9ee330 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -2,7 +2,7 @@
  * OMAP3-specific clock framework functions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley
  * Jouni Högander
@@ -59,6 +59,15 @@ const struct clkops clkops_omap3430es2_ssi_wait = {
         .find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_ssi_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_ssi_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_dss_usbhost_find_idlest - CM_IDLEST info for DSS, USBHOST
  * @clk: struct clk * being enabled
@@ -94,6 +103,15 @@ const struct clkops clkops_omap3430es2_dss_usbhost_wait = {
         .find_companion = omap2_clk_dflt_find_companion,
 };
 
+const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_dss_usbhost_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
+
 /**
  * omap3430es2_clk_hsotgusb_find_idlest - return CM_IDLEST info for HSOTGUSB
  * @clk: struct clk * being enabled
@@ -124,3 +142,12 @@ const struct clkops clkops_omap3430es2_hsotgusb_wait = {
         .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
         .find_companion = omap2_clk_dflt_find_companion,
 };
+
+const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait = {
+        .enable         = omap2_dflt_clk_enable,
+        .disable        = omap2_dflt_clk_disable,
+        .find_idlest    = omap3430es2_clk_hsotgusb_find_idlest,
+        .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
+};
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 628e8de57680..084ba71b2b31 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2,14 +2,17 @@
  * OMAP34xx clock function prototypes and macros
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  */
 
 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
 
 extern const struct clkops clkops_omap3430es2_ssi_wait;
+extern const struct clkops clkops_omap3430es2_iclk_ssi_wait;
 extern const struct clkops clkops_omap3430es2_hsotgusb_wait;
+extern const struct clkops clkops_omap3430es2_iclk_hsotgusb_wait;
 extern const struct clkops clkops_omap3430es2_dss_usbhost_wait;
+extern const struct clkops clkops_omap3430es2_iclk_dss_usbhost_wait;
 
 #endif
diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c
index 74116a3cf099..2e97d08f0e56 100644
--- a/arch/arm/mach-omap2/clock3517.c
+++ b/arch/arm/mach-omap2/clock3517.c
@@ -2,7 +2,7 @@
  * OMAP3517/3505-specific clock framework functions
  *
  * Copyright (C) 2010 Texas Instruments, Inc.
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Nokia Corporation
  *
  * Ranjith Lohithakshan
  * Paul Walmsley
@@ -119,6 +119,8 @@ const struct clkops clkops_am35xx_ipss_wait = {
         .disable        = omap2_dflt_clk_disable,
         .find_idlest    = am35xx_clk_ipss_find_idlest,
         .find_companion = omap2_clk_dflt_find_companion,
+        .allow_idle     = omap2_clkt_iclk_allow_idle,
+        .deny_idle      = omap2_clkt_iclk_deny_idle,
 };
 
 
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index e9f66b6dec18..952c3e01c9eb 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -65,9 +65,6 @@ void __init omap3_clk_lock_dpll5(void)
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
         clk_enable(dpll5_clk);
 
-        /* Enable autoidle to allow it to enter low power bypass */
-        omap3_dpll_allow_idle(dpll5_clk);
-
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
         clk_enable(dpll5_m2_clk);
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index f14d986f0b5d..d905ecc7989a 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2,7 +2,7 @@
  * OMAP3 clock data
  *
  * Copyright (C) 2007-2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
  * With many device clock fixes by Kevin Hilman and Jouni Högander
@@ -291,12 +291,11 @@ static struct dpll_data dpll1_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll1_ck = {
         .name           = "dpll1_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_noncore_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll1_dd,
         .round_rate     = &omap2_dpll_round_rate,
@@ -364,7 +363,6 @@ static struct dpll_data dpll2_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll2_ck = {
@@ -424,12 +422,11 @@ static struct dpll_data dpll3_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll3_ck = {
         .name           = "dpll3_ck",
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_core_dpll_ops,
         .parent         = &sys_ck,
         .dpll_data      = &dpll3_dd,
         .round_rate     = &omap2_dpll_round_rate,
@@ -583,7 +580,6 @@ static struct dpll_data dpll4_dd_34xx __initdata = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct dpll_data dpll4_dd_3630 __initdata = {
@@ -607,7 +603,6 @@ static struct dpll_data dpll4_dd_3630 __initdata = {
         .max_multiplier = OMAP3630_MAX_JTYPE_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE,
         .flags          = DPLL_J_TYPE
 };
 
@@ -939,7 +934,6 @@ static struct dpll_data dpll5_dd = {
         .max_multiplier = OMAP3_MAX_DPLL_MULT,
         .min_divider    = 1,
         .max_divider    = OMAP3_MAX_DPLL_DIV,
-        .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
 };
 
 static struct clk dpll5_ck = {
@@ -1205,7 +1199,10 @@ static const struct clksel gfx_l3_clksel[] = {
         { .parent = NULL }
 };
 
-/* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */
+/*
+ * Virtual parent clock for gfx_l3_ick and gfx_l3_fck
+ * This interface clock does not have a CM_AUTOIDLE bit
+ */
 static struct clk gfx_l3_ck = {
         .name           = "gfx_l3_ck",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1304,6 +1301,7 @@ static struct clk sgx_fck = {
         .round_rate     = &omap2_clksel_round_rate
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk sgx_ick = {
         .name           = "sgx_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1328,7 +1326,7 @@ static struct clk d2d_26m_fck = {
 
 static struct clk modem_fck = {
         .name           = "modem_fck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_mdmclk_dflt_wait,
         .parent         = &sys_ck,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
         .enable_bit     = OMAP3430_EN_MODEM_SHIFT,
@@ -1338,7 +1336,7 @@ static struct clk modem_fck = {
 
 static struct clk sad2d_ick = {
         .name           = "sad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SAD2D_SHIFT,
@@ -1348,7 +1346,7 @@ static struct clk sad2d_ick = {
 
 static struct clk mad2d_ick = {
         .name           = "mad2d_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP3430_EN_MAD2D_SHIFT,
@@ -1718,7 +1716,7 @@ static struct clk core_l3_ick = {
 
 static struct clk hsotgusb_ick_3430es1 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1728,7 +1726,7 @@ static struct clk hsotgusb_ick_3430es1 = {
 
 static struct clk hsotgusb_ick_3430es2 = {
         .name           = "hsotgusb_ick",
-        .ops            = &clkops_omap3430es2_hsotgusb_wait,
+        .ops            = &clkops_omap3430es2_iclk_hsotgusb_wait,
         .parent         = &core_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HSOTGUSB_SHIFT,
@@ -1736,6 +1734,7 @@ static struct clk hsotgusb_ick_3430es2 = {
         .recalc         = &followparent_recalc,
 };
 
+/* This interface clock does not have a CM_AUTOIDLE bit */
 static struct clk sdrc_ick = {
         .name           = "sdrc_ick",
         .ops            = &clkops_omap2_dflt_wait,
@@ -1767,7 +1766,7 @@ static struct clk security_l3_ick = {
 
 static struct clk pka_ick = {
         .name           = "pka_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l3_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_PKA_SHIFT,
@@ -1786,7 +1785,7 @@ static struct clk core_l4_ick = {
 
 static struct clk usbtll_ick = {
         .name           = "usbtll_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
         .enable_bit     = OMAP3430ES2_EN_USBTLL_SHIFT,
@@ -1796,7 +1795,7 @@ static struct clk usbtll_ick = {
 
 static struct clk mmchs3_ick = {
         .name           = "mmchs3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES2_EN_MMC3_SHIFT,
@@ -1807,7 +1806,7 @@ static struct clk mmchs3_ick = {
 /* Intersystem Communication Registers - chassis mode only */
 static struct clk icr_ick = {
         .name           = "icr_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_ICR_SHIFT,
@@ -1817,7 +1816,7 @@ static struct clk icr_ick = {
 
 static struct clk aes2_ick = {
         .name           = "aes2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_AES2_SHIFT,
@@ -1827,7 +1826,7 @@ static struct clk aes2_ick = {
 
 static struct clk sha12_ick = {
         .name           = "sha12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SHA12_SHIFT,
@@ -1837,7 +1836,7 @@ static struct clk sha12_ick = {
 
 static struct clk des2_ick = {
         .name           = "des2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_DES2_SHIFT,
@@ -1847,7 +1846,7 @@ static struct clk des2_ick = {
 
 static struct clk mmchs2_ick = {
         .name           = "mmchs2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC2_SHIFT,
@@ -1857,7 +1856,7 @@ static struct clk mmchs2_ick = {
 
 static struct clk mmchs1_ick = {
         .name           = "mmchs1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MMC1_SHIFT,
@@ -1867,7 +1866,7 @@ static struct clk mmchs1_ick = {
 
 static struct clk mspro_ick = {
         .name           = "mspro_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MSPRO_SHIFT,
@@ -1877,7 +1876,7 @@ static struct clk mspro_ick = {
 
 static struct clk hdq_ick = {
         .name           = "hdq_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_HDQ_SHIFT,
@@ -1887,7 +1886,7 @@ static struct clk hdq_ick = {
 
 static struct clk mcspi4_ick = {
         .name           = "mcspi4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
@@ -1897,7 +1896,7 @@ static struct clk mcspi4_ick = {
 
 static struct clk mcspi3_ick = {
         .name           = "mcspi3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
@@ -1907,7 +1906,7 @@ static struct clk mcspi3_ick = {
 
 static struct clk mcspi2_ick = {
         .name           = "mcspi2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
@@ -1917,7 +1916,7 @@ static struct clk mcspi2_ick = {
 
 static struct clk mcspi1_ick = {
         .name           = "mcspi1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
@@ -1927,7 +1926,7 @@ static struct clk mcspi1_ick = {
 
 static struct clk i2c3_ick = {
         .name           = "i2c3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C3_SHIFT,
@@ -1937,7 +1936,7 @@ static struct clk i2c3_ick = {
 
 static struct clk i2c2_ick = {
         .name           = "i2c2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C2_SHIFT,
@@ -1947,7 +1946,7 @@ static struct clk i2c2_ick = {
 
 static struct clk i2c1_ick = {
         .name           = "i2c1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_I2C1_SHIFT,
@@ -1957,7 +1956,7 @@ static struct clk i2c1_ick = {
 
 static struct clk uart2_ick = {
         .name           = "uart2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART2_SHIFT,
@@ -1967,7 +1966,7 @@ static struct clk uart2_ick = {
 
 static struct clk uart1_ick = {
         .name           = "uart1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_UART1_SHIFT,
@@ -1977,7 +1976,7 @@ static struct clk uart1_ick = {
 
 static struct clk gpt11_ick = {
         .name           = "gpt11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT11_SHIFT,
@@ -1987,7 +1986,7 @@ static struct clk gpt11_ick = {
 
 static struct clk gpt10_ick = {
         .name           = "gpt10_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_GPT10_SHIFT,
@@ -1997,7 +1996,7 @@ static struct clk gpt10_ick = {
 
 static struct clk mcbsp5_ick = {
         .name           = "mcbsp5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP5_SHIFT,
@@ -2007,7 +2006,7 @@ static struct clk mcbsp5_ick = {
 
 static struct clk mcbsp1_ick = {
         .name           = "mcbsp1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MCBSP1_SHIFT,
@@ -2017,7 +2016,7 @@ static struct clk mcbsp1_ick = {
 
 static struct clk fac_ick = {
         .name           = "fac_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430ES1_EN_FAC_SHIFT,
@@ -2027,7 +2026,7 @@ static struct clk fac_ick = {
 
 static struct clk mailboxes_ick = {
         .name           = "mailboxes_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_MAILBOXES_SHIFT,
@@ -2037,7 +2036,7 @@ static struct clk mailboxes_ick = {
 
 static struct clk omapctrl_ick = {
         .name           = "omapctrl_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_OMAPCTRL_SHIFT,
@@ -2057,7 +2056,7 @@ static struct clk ssi_l4_ick = {
 
 static struct clk ssi_ick_3430es1 = {
         .name           = "ssi_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &ssi_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
@@ -2067,7 +2066,7 @@ static struct clk ssi_ick_3430es1 = {
 
 static struct clk ssi_ick_3430es2 = {
         .name           = "ssi_ick",
-        .ops            = &clkops_omap3430es2_ssi_wait,
+        .ops            = &clkops_omap3430es2_iclk_ssi_wait,
         .parent         = &ssi_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = OMAP3430_EN_SSI_SHIFT,
@@ -2085,7 +2084,7 @@ static const struct clksel usb_l4_clksel[] = {
 
 static struct clk usb_l4_ick = {
         .name           = "usb_l4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &l4_ick,
         .init           = &omap2_init_clksel_parent,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -2107,7 +2106,7 @@ static struct clk security_l4_ick2 = {
 
 static struct clk aes1_ick = {
         .name           = "aes1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_AES1_SHIFT,
@@ -2116,7 +2115,7 @@ static struct clk aes1_ick = {
 
 static struct clk rng_ick = {
         .name           = "rng_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_RNG_SHIFT,
@@ -2125,7 +2124,7 @@ static struct clk rng_ick = {
 
 static struct clk sha11_ick = {
         .name           = "sha11_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_SHA11_SHIFT,
@@ -2134,7 +2133,7 @@ static struct clk sha11_ick = {
 
 static struct clk des1_ick = {
         .name           = "des1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &security_l4_ick2,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
         .enable_bit     = OMAP3430_EN_DES1_SHIFT,
@@ -2195,7 +2194,7 @@ static struct clk dss2_alwon_fck = {
 static struct clk dss_ick_3430es1 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2206,7 +2205,7 @@ static struct clk dss_ick_3430es1 = {
 static struct clk dss_ick_3430es2 = {
         /* Handles both L3 and L4 clocks */
         .name           = "dss_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT,
@@ -2229,7 +2228,7 @@ static struct clk cam_mclk = {
 static struct clk cam_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "cam_ick",
-        .ops            = &clkops_omap2_dflt,
+        .ops            = &clkops_omap2_iclk_dflt,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_CAM_SHIFT,
@@ -2272,7 +2271,7 @@ static struct clk usbhost_48m_fck = {
 static struct clk usbhost_ick = {
         /* Handles both L3 and L4 clocks */
         .name           = "usbhost_ick",
-        .ops            = &clkops_omap3430es2_dss_usbhost_wait,
+        .ops            = &clkops_omap3430es2_iclk_dss_usbhost_wait,
         .parent         = &l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USBHOST_SHIFT,
@@ -2372,7 +2371,7 @@ static struct clk wkup_l4_ick = {
 /* Never specifically named in the TRM, so we have to infer a likely name */
 static struct clk usim_ick = {
         .name           = "usim_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430ES2_EN_USIMOCP_SHIFT,
@@ -2382,7 +2381,7 @@ static struct clk usim_ick = {
 
 static struct clk wdt2_ick = {
         .name           = "wdt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT2_SHIFT,
@@ -2392,7 +2391,7 @@ static struct clk wdt2_ick = {
 
 static struct clk wdt1_ick = {
         .name           = "wdt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT1_SHIFT,
@@ -2402,7 +2401,7 @@ static struct clk wdt1_ick = {
 
 static struct clk gpio1_ick = {
         .name           = "gpio1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
@@ -2412,7 +2411,7 @@ static struct clk gpio1_ick = {
 
 static struct clk omap_32ksync_ick = {
         .name           = "omap_32ksync_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_32KSYNC_SHIFT,
@@ -2423,7 +2422,7 @@ static struct clk omap_32ksync_ick = {
 /* XXX This clock no longer exists in 3430 TRM rev F */
 static struct clk gpt12_ick = {
         .name           = "gpt12_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT12_SHIFT,
@@ -2433,7 +2432,7 @@ static struct clk gpt12_ick = {
 
 static struct clk gpt1_ick = {
         .name           = "gpt1_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &wkup_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT1_SHIFT,
@@ -2663,7 +2662,7 @@ static struct clk per_l4_ick = {
 
 static struct clk gpio6_ick = {
         .name           = "gpio6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
@@ -2673,7 +2672,7 @@ static struct clk gpio6_ick = {
 
 static struct clk gpio5_ick = {
         .name           = "gpio5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
@@ -2683,7 +2682,7 @@ static struct clk gpio5_ick = {
 
 static struct clk gpio4_ick = {
         .name           = "gpio4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
@@ -2693,7 +2692,7 @@ static struct clk gpio4_ick = {
 
 static struct clk gpio3_ick = {
         .name           = "gpio3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
@@ -2703,7 +2702,7 @@ static struct clk gpio3_ick = {
 
 static struct clk gpio2_ick = {
         .name           = "gpio2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
@@ -2713,7 +2712,7 @@ static struct clk gpio2_ick = {
 
 static struct clk wdt3_ick = {
         .name           = "wdt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_WDT3_SHIFT,
@@ -2723,7 +2722,7 @@ static struct clk wdt3_ick = {
 
 static struct clk uart3_ick = {
         .name           = "uart3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_UART3_SHIFT,
@@ -2733,7 +2732,7 @@ static struct clk uart3_ick = {
 
 static struct clk uart4_ick = {
         .name           = "uart4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3630_EN_UART4_SHIFT,
@@ -2743,7 +2742,7 @@ static struct clk uart4_ick = {
 
 static struct clk gpt9_ick = {
         .name           = "gpt9_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT9_SHIFT,
@@ -2753,7 +2752,7 @@ static struct clk gpt9_ick = {
 
 static struct clk gpt8_ick = {
         .name           = "gpt8_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT8_SHIFT,
@@ -2763,7 +2762,7 @@ static struct clk gpt8_ick = {
 
 static struct clk gpt7_ick = {
         .name           = "gpt7_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT7_SHIFT,
@@ -2773,7 +2772,7 @@ static struct clk gpt7_ick = {
 
 static struct clk gpt6_ick = {
         .name           = "gpt6_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT6_SHIFT,
@@ -2783,7 +2782,7 @@ static struct clk gpt6_ick = {
 
 static struct clk gpt5_ick = {
         .name           = "gpt5_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT5_SHIFT,
@@ -2793,7 +2792,7 @@ static struct clk gpt5_ick = {
 
 static struct clk gpt4_ick = {
         .name           = "gpt4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT4_SHIFT,
@@ -2803,7 +2802,7 @@ static struct clk gpt4_ick = {
 
 static struct clk gpt3_ick = {
         .name           = "gpt3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT3_SHIFT,
@@ -2813,7 +2812,7 @@ static struct clk gpt3_ick = {
 
 static struct clk gpt2_ick = {
         .name           = "gpt2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_GPT2_SHIFT,
@@ -2823,7 +2822,7 @@ static struct clk gpt2_ick = {
 
 static struct clk mcbsp2_ick = {
         .name           = "mcbsp2_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2833,7 +2832,7 @@ static struct clk mcbsp2_ick = {
 
 static struct clk mcbsp3_ick = {
         .name           = "mcbsp3_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2843,7 +2842,7 @@ static struct clk mcbsp3_ick = {
 
 static struct clk mcbsp4_ick = {
         .name           = "mcbsp4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &per_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
         .enable_bit     = OMAP3430_EN_MCBSP4_SHIFT,
@@ -3186,7 +3185,7 @@ static struct clk vpfe_fck = {
  */
 static struct clk uart4_ick_am35xx = {
         .name           = "uart4_ick",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_iclk_dflt_wait,
         .parent         = &core_l4_ick,
         .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
         .enable_bit     = AM35XX_EN_UART4_SHIFT,
@@ -3290,10 +3289,10 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK("mmci-omap-hs.2",   "fck",  &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("mmci-omap-hs.1",   "fck",  &mmchs2_fck,    CK_3XXX),
+        CLK("omap_hsmmc.2",     "fck",  &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.1",     "fck",  &mmchs2_fck,    CK_3XXX),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
-        CLK("mmci-omap-hs.0",   "fck",  &mmchs1_fck,    CK_3XXX),
+        CLK("omap_hsmmc.0",     "fck",  &mmchs1_fck,    CK_3XXX),
         CLK("omap_i2c.3", "fck",        &i2c3_fck,      CK_3XXX),
         CLK("omap_i2c.2", "fck",        &i2c2_fck,      CK_3XXX),
         CLK("omap_i2c.1", "fck",        &i2c1_fck,      CK_3XXX),
@@ -3323,13 +3322,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("ehci-omap.0",      "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("mmci-omap-hs.2",   "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
-        CLK("mmci-omap-hs.1",   "ick",  &mmchs2_ick,    CK_3XXX),
-        CLK("mmci-omap-hs.0",   "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
@@ -3538,6 +3537,9 @@ int __init omap3xxx_clk_init(void)
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         recalculate_root_clocks();
 
         pr_info("Clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
@@ -3551,7 +3553,8 @@ int __init omap3xxx_clk_init(void)
         clk_enable_init_clocks();
 
         /*
-         * Lock DPLL5 and put it in autoidle.
+         * Lock DPLL5 -- here only until other device init code can
+         * handle this
          */
         if (!cpu_is_ti816x() && (omap_rev() >= OMAP3430_REV_ES2_0))
                 omap3_clk_lock_dpll5();
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index de9ec8ddd2ae..f1fedb71ae08 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -278,8 +278,10 @@ static struct clk dpll_abe_ck = {
 static struct clk dpll_abe_x2_ck = {
         .name           = "dpll_abe_x2_ck",
         .parent         = &dpll_abe_ck,
-        .ops            = &clkops_null,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
 };
 
 static const struct clksel_rate div31_1to31_rates[] = {
@@ -328,7 +330,7 @@ static struct clk dpll_abe_m2x2_ck = {
         .clksel         = dpll_abe_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -395,7 +397,7 @@ static struct clk dpll_abe_m3x2_ck = {
         .clksel         = dpll_abe_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M3_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -443,13 +445,14 @@ static struct clk dpll_core_ck = {
         .parent         = &sys_clkin_ck,
         .dpll_data      = &dpll_core_dd,
         .init           = &omap2_init_dpll_parent,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap3_core_dpll_ops,
         .recalc         = &omap3_dpll_recalc,
 };
 
 static struct clk dpll_core_x2_ck = {
         .name           = "dpll_core_x2_ck",
         .parent         = &dpll_core_ck,
+        .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_null,
         .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -465,7 +468,7 @@ static struct clk dpll_core_m6x2_ck = {
         .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -495,7 +498,7 @@ static struct clk dpll_core_m2_ck = {
         .clksel         = dpll_core_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_CORE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -515,7 +518,7 @@ static struct clk dpll_core_m5x2_ck = {
         .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -581,7 +584,7 @@ static struct clk dpll_core_m4x2_ck = {
         .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -606,7 +609,7 @@ static struct clk dpll_abe_m2_ck = {
         .clksel         = dpll_abe_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_ABE,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -632,7 +635,7 @@ static struct clk dpll_core_m7x2_ck = {
         .clksel         = dpll_core_m6x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_CORE,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -689,6 +692,7 @@ static struct clk dpll_iva_ck = {
 static struct clk dpll_iva_x2_ck = {
         .name           = "dpll_iva_x2_ck",
         .parent         = &dpll_iva_ck,
+        .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_null,
         .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -704,7 +708,7 @@ static struct clk dpll_iva_m4x2_ck = {
         .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -716,7 +720,7 @@ static struct clk dpll_iva_m5x2_ck = {
         .clksel         = dpll_iva_m4x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_IVA,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -764,7 +768,7 @@ static struct clk dpll_mpu_m2_ck = {
         .clksel         = dpll_mpu_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_MPU,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -837,7 +841,7 @@ static struct clk dpll_per_m2_ck = {
         .clksel         = dpll_per_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -846,8 +850,10 @@ static struct clk dpll_per_m2_ck = {
 static struct clk dpll_per_x2_ck = {
         .name           = "dpll_per_x2_ck",
         .parent         = &dpll_per_ck,
-        .ops            = &clkops_null,
+        .flags          = CLOCK_CLKOUTX2,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap3_clkoutx2_recalc,
+        .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
 };
 
 static const struct clksel dpll_per_m2x2_div[] = {
@@ -861,7 +867,7 @@ static struct clk dpll_per_m2x2_ck = {
         .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_PER,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -887,7 +893,7 @@ static struct clk dpll_per_m4x2_ck = {
         .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M4_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -899,7 +905,7 @@ static struct clk dpll_per_m5x2_ck = {
         .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M5_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -911,7 +917,7 @@ static struct clk dpll_per_m6x2_ck = {
         .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M6_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -923,7 +929,7 @@ static struct clk dpll_per_m7x2_ck = {
         .clksel         = dpll_per_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M7_DPLL_PER,
         .clksel_mask    = OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -964,6 +970,7 @@ static struct clk dpll_unipro_ck = {
 static struct clk dpll_unipro_x2_ck = {
         .name           = "dpll_unipro_x2_ck",
         .parent         = &dpll_unipro_ck,
+        .flags          = CLOCK_CLKOUTX2,
         .ops            = &clkops_null,
         .recalc         = &omap3_clkoutx2_recalc,
 };
@@ -979,7 +986,7 @@ static struct clk dpll_unipro_m2x2_ck = {
         .clksel         = dpll_unipro_m2x2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -1028,7 +1035,8 @@ static struct clk dpll_usb_ck = {
 static struct clk dpll_usb_clkdcoldo_ck = {
         .name           = "dpll_usb_clkdcoldo_ck",
         .parent         = &dpll_usb_ck,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
+        .clksel_reg     = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
         .recalc         = &followparent_recalc,
 };
 
@@ -1043,7 +1051,7 @@ static struct clk dpll_usb_m2_ck = {
         .clksel         = dpll_usb_m2_div,
         .clksel_reg     = OMAP4430_CM_DIV_M2_DPLL_USB,
         .clksel_mask    = OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK,
-        .ops            = &clkops_null,
+        .ops            = &clkops_omap4_dpllmx_ops,
         .recalc         = &omap2_clksel_recalc,
         .round_rate     = &omap2_clksel_round_rate,
         .set_rate       = &omap2_clksel_set_rate,
@@ -3158,11 +3166,11 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap2_mcspi.2",    "fck",                          &mcspi2_fck,    CK_443X),
         CLK("omap2_mcspi.3",    "fck",                          &mcspi3_fck,    CK_443X),
         CLK("omap2_mcspi.4",    "fck",                          &mcspi4_fck,    CK_443X),
-        CLK("mmci-omap-hs.0",   "fck",                          &mmc1_fck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "fck",                          &mmc2_fck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "fck",                          &mmc3_fck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "fck",                          &mmc4_fck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "fck",                          &mmc5_fck,      CK_443X),
+        CLK("omap_hsmmc.0",     "fck",                          &mmc1_fck,      CK_443X),
+        CLK("omap_hsmmc.1",     "fck",                          &mmc2_fck,      CK_443X),
+        CLK("omap_hsmmc.2",     "fck",                          &mmc3_fck,      CK_443X),
+        CLK("omap_hsmmc.3",     "fck",                          &mmc4_fck,      CK_443X),
+        CLK("omap_hsmmc.4",     "fck",                          &mmc5_fck,      CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
@@ -3245,11 +3253,11 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_i2c.2",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.3",       "ick",                          &dummy_ck,      CK_443X),
         CLK("omap_i2c.4",       "ick",                          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.0",   "ick",                          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.1",   "ick",                          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.2",   "ick",                          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.3",   "ick",                          &dummy_ck,      CK_443X),
-        CLK("mmci-omap-hs.4",   "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.0",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.1",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.2",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.3",     "ick",                          &dummy_ck,      CK_443X),
+        CLK("omap_hsmmc.4",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.1",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.2",     "ick",                          &dummy_ck,      CK_443X),
         CLK("omap-mcbsp.3",     "ick",                          &dummy_ck,      CK_443X),
@@ -3301,6 +3309,9 @@ int __init omap4xxx_clk_init(void)
                         omap2_init_clk_clkdm(c->lk.clk);
                 }
 
+        /* Disable autoidle on all clocks; let the PM code enable it later */
+        omap_clk_disable_autoidle_all();
+
         recalculate_root_clocks();
 
         /*
diff --git a/arch/arm/mach-omap2/clock_common_data.c b/arch/arm/mach-omap2/clock_common_data.c
index 1cf8131205fa..6424d46be14a 100644
--- a/arch/arm/mach-omap2/clock_common_data.c
+++ b/arch/arm/mach-omap2/clock_common_data.c
@@ -37,3 +37,9 @@ const struct clksel_rate gfx_l3_rates[] = {
         { .div = 0 }
 };
 
+const struct clksel_rate dsp_ick_rates[] = {
+        { .div = 1, .val = 1, .flags = RATE_IN_24XX },
+        { .div = 2, .val = 2, .flags = RATE_IN_24XX },
+        { .div = 3, .val = 3, .flags = RATE_IN_243X },
+        { .div = 0 },
+};
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index a0341dee1c3a..ab878545bd9b 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -173,7 +173,7 @@ void _clkdm_add_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_autodep *autodep;
 
-        if (!autodeps)
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
                 return;
 
         for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
@@ -207,7 +207,7 @@ void _clkdm_del_autodeps(struct clockdomain *clkdm)
 {
         struct clkdm_autodep *autodep;
 
-        if (!autodeps)
+        if (!autodeps || clkdm->flags & CLKDM_NO_AUTODEPS)
                 return;
 
         for (autodep = autodeps; autodep->clkdm.ptr; autodep++) {
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index de52f059f9e2..85b3dce65640 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -4,7 +4,7 @@
  * OMAP2/3 clockdomain framework functions
  *
  * Copyright (C) 2008 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
+ * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Paul Walmsley
  *
@@ -22,11 +22,19 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
-/* Clockdomain capability flags */
+/*
+ * Clockdomain flags
+ *
+ * XXX Document CLKDM_CAN_* flags
+ *
+ * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
+ *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
 #define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
+#define CLKDM_NO_AUTODEPS                       (1 << 4)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index ffdfe54f3264..13bde95b6790 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -89,6 +89,8 @@ static struct clkdm_dep gfx_sgx_wkdeps[] = {
 
 /* 24XX-specific possible dependencies */
 
+#ifdef CONFIG_ARCH_OMAP2
+
 /* Wakeup dependency source arrays */
 
 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
@@ -168,6 +170,7 @@ static struct clkdm_dep core_24xx_wkdeps[] = {
         { NULL },
 };
 
+#endif /* CONFIG_ARCH_OMAP2 */
 
 /* 2430-specific possible wakeup dependencies */
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index f53258acd1da..a607ec196e8b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -514,7 +514,7 @@ static struct clockdomain mpu0_44xx_clkdm = {
         .pwrdm            = { .name = "cpu0_pwrdm" },
         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .cm_inst          = OMAP4430_PRCM_MPU_CPU0_INST,
-        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
@@ -524,7 +524,7 @@ static struct clockdomain mpu1_44xx_clkdm = {
         .pwrdm            = { .name = "cpu1_pwrdm" },
         .prcm_partition   = OMAP4430_PRCM_MPU_PARTITION,
         .cm_inst          = OMAP4430_PRCM_MPU_CPU1_INST,
-        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS,
+        .clkdm_offs       = OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS,
         .flags            = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index d70660e82fe6..686290437568 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -210,8 +210,11 @@
 #define OMAP24XX_AUTO_USB_MASK                          (1 << 0)
 
 /* CM_AUTOIDLE3_CORE */
+#define OMAP24XX_AUTO_SDRC_SHIFT                        2
 #define OMAP24XX_AUTO_SDRC_MASK                         (1 << 2)
+#define OMAP24XX_AUTO_GPMC_SHIFT                        1
 #define OMAP24XX_AUTO_GPMC_MASK                         (1 << 1)
+#define OMAP24XX_AUTO_SDMA_SHIFT                        0
 #define OMAP24XX_AUTO_SDMA_MASK                         (1 << 0)
 
 /* CM_AUTOIDLE4_CORE */
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index 96954aa48671..9d0dec806e92 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -25,6 +25,14 @@
 #include "cm-regbits-24xx.h"
 #include "cm-regbits-34xx.h"
 
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */
+#define DPLL_AUTOIDLE_DISABLE                           0x0
+#define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
+/* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */
+#define OMAP2XXX_APLL_AUTOIDLE_DISABLE                  0x0
+#define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
+
 static const u8 cm_idlest_offs[] = {
         CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
 };
@@ -125,6 +133,67 @@ void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask)
         _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask);
 }
 
+/*
+ * DPLL autoidle control
+ */
+
+static void _omap2xxx_set_dpll_autoidle(u8 m)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~OMAP24XX_AUTO_DPLL_MASK;
+        v |= m << OMAP24XX_AUTO_DPLL_SHIFT;
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_dpll_disable_autoidle(void)
+{
+        _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP);
+}
+
+void omap2xxx_cm_set_dpll_auto_low_power_stop(void)
+{
+        _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE);
+}
+
+/*
+ * APLL autoidle control
+ */
+
+static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask)
+{
+        u32 v;
+
+        v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE);
+        v &= ~mask;
+        v |= m << __ffs(mask);
+        omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE);
+}
+
+void omap2xxx_cm_set_apll54_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll54_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_54M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_disable_autoidle(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
+
+void omap2xxx_cm_set_apll96_auto_low_power_stop(void)
+{
+        _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE,
+                                    OMAP24XX_AUTO_96M_MASK);
+}
 
 /*
  *
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 5e9ea5bd60b9..088bbad73db5 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -122,6 +122,14 @@ extern void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask);
 extern void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask);
 extern void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask);
 
+extern void omap2xxx_cm_set_dpll_disable_autoidle(void);
+extern void omap2xxx_cm_set_dpll_auto_low_power_stop(void);
+
+extern void omap2xxx_cm_set_apll54_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll54_auto_low_power_stop(void);
+extern void omap2xxx_cm_set_apll96_disable_autoidle(void);
+extern void omap2xxx_cm_set_apll96_auto_low_power_stop(void);
+
 #endif
 
 /* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 71f099b85e7c..0d2d6a9c303c 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -31,10 +31,75 @@
 #include <plat/dma.h>
 #include <plat/omap_hwmod.h>
 #include <plat/omap_device.h>
+#include <plat/omap4-keypad.h>
 
 #include "mux.h"
 #include "control.h"
 
+#define L3_MODULES_MAX_LEN 12
+#define L3_MODULES 3
+
+static int __init omap3_l3_init(void)
+{
+        int l;
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        char oh_name[L3_MODULES_MAX_LEN];
+
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!(cpu_is_omap34xx()))
+                return -ENODEV;
+
+        l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main");
+
+        oh = omap_hwmod_lookup(oh_name);
+
+        if (!oh)
+                pr_err("could not look up %s\n", oh_name);
+
+        od = omap_device_build("omap_l3_smx", 0, oh, NULL, 0,
+                                                           NULL, 0, 0);
+
+        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+
+        return PTR_ERR(od);
+}
+postcore_initcall(omap3_l3_init);
+
+static int __init omap4_l3_init(void)
+{
+        int l, i;
+        struct omap_hwmod *oh[3];
+        struct omap_device *od;
+        char oh_name[L3_MODULES_MAX_LEN];
+
+        /*
+         * To avoid code running on other OMAPs in
+         * multi-omap builds
+         */
+        if (!(cpu_is_omap44xx()))
+                return -ENODEV;
+
+        for (i = 0; i < L3_MODULES; i++) {
+                l = snprintf(oh_name, L3_MODULES_MAX_LEN, "l3_main_%d", i+1);
+
+                oh[i] = omap_hwmod_lookup(oh_name);
+                if (!(oh[i]))
+                        pr_err("could not look up %s\n", oh_name);
+        }
+
+        od = omap_device_build_ss("omap_l3_noc", 0, oh, 3, NULL,
+                                                     0, NULL, 0, 0);
+
+        WARN(IS_ERR(od), "could not build omap_device for %s\n", oh_name);
+
+        return PTR_ERR(od);
+}
+postcore_initcall(omap4_l3_init);
+
 #if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
 
 static struct resource cam_resources[] = {
@@ -142,96 +207,70 @@ static inline void omap_init_camera(void)
 }
 #endif
 
-#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
-
-#define MBOX_REG_SIZE   0x120
-
-#ifdef CONFIG_ARCH_OMAP2
-static struct resource omap2_mbox_resources[] = {
+struct omap_device_pm_latency omap_keyboard_latency[] = {
         {
-                .start          = OMAP24XX_MAILBOX_BASE,
-                .end            = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = INT_24XX_MAIL_U0_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "dsp",
-        },
-        {
-                .start          = INT_24XX_MAIL_U3_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "iva",
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
-#else
-#define omap2_mbox_resources            NULL
-#define omap2_mbox_resources_sz         0
-#endif
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct resource omap3_mbox_resources[] = {
-        {
-                .start          = OMAP34XX_MAILBOX_BASE,
-                .end            = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = INT_24XX_MAIL_U0_MPU,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "dsp",
-        },
-};
-static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
-#else
-#define omap3_mbox_resources            NULL
-#define omap3_mbox_resources_sz         0
-#endif
+int __init omap4_keyboard_init(struct omap4_keypad_platform_data
+                                                *sdp4430_keypad_data)
+{
+        struct omap_device *od;
+        struct omap_hwmod *oh;
+        struct omap4_keypad_platform_data *keypad_data;
+        unsigned int id = -1;
+        char *oh_name = "kbd";
+        char *name = "omap4-keypad";
 
-#ifdef CONFIG_ARCH_OMAP4
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
 
-#define OMAP4_MBOX_REG_SIZE     0x130
-static struct resource omap4_mbox_resources[] = {
-        {
-                .start          = OMAP44XX_MAILBOX_BASE,
-                .end            = OMAP44XX_MAILBOX_BASE +
-                                        OMAP4_MBOX_REG_SIZE - 1,
-                .flags          = IORESOURCE_MEM,
-        },
-        {
-                .start          = OMAP44XX_IRQ_MAIL_U0,
-                .flags          = IORESOURCE_IRQ,
-                .name           = "mbox",
-        },
-};
-static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
-#else
-#define omap4_mbox_resources            NULL
-#define omap4_mbox_resources_sz         0
-#endif
+        keypad_data = sdp4430_keypad_data;
 
-static struct platform_device mbox_device = {
-        .name           = "omap-mailbox",
-        .id             = -1,
+        od = omap_device_build(name, id, oh, keypad_data,
+                        sizeof(struct omap4_keypad_platform_data),
+                        omap_keyboard_latency,
+                        ARRAY_SIZE(omap_keyboard_latency), 0);
+
+        if (IS_ERR(od)) {
+                WARN(1, "Cant build omap_device for %s:%s.\n",
+                                                name, oh->name);
+                return PTR_ERR(od);
+        }
+
+        return 0;
+}
+
+#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
+static struct omap_device_pm_latency mbox_latencies[] = {
+        [0] = {
+                .activate_func = omap_device_enable_hwmods,
+                .deactivate_func = omap_device_idle_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
 };
 
 static inline void omap_init_mbox(void)
 {
-        if (cpu_is_omap24xx()) {
-                mbox_device.resource = omap2_mbox_resources;
-                mbox_device.num_resources = omap2_mbox_resources_sz;
-        } else if (cpu_is_omap34xx()) {
-                mbox_device.resource = omap3_mbox_resources;
-                mbox_device.num_resources = omap3_mbox_resources_sz;
-        } else if (cpu_is_omap44xx()) {
-                mbox_device.resource = omap4_mbox_resources;
-                mbox_device.num_resources = omap4_mbox_resources_sz;
-        } else {
-                pr_err("%s: platform not supported\n", __func__);
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+
+        oh = omap_hwmod_lookup("mailbox");
+        if (!oh) {
+                pr_err("%s: unable to find hwmod\n", __func__);
                 return;
         }
-        platform_device_register(&mbox_device);
+
+        od = omap_device_build("omap-mailbox", -1, oh, NULL, 0,
+                                mbox_latencies, ARRAY_SIZE(mbox_latencies), 0);
+        WARN(IS_ERR(od), "%s: could not build device, err %ld\n",
+                                                __func__, PTR_ERR(od));
 }
 #else
 static inline void omap_init_mbox(void) { }
@@ -503,117 +542,10 @@ static inline void omap_init_aes(void) { }
 
 /*-------------------------------------------------------------------------*/
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-
-#define MMCHS_SYSCONFIG                 0x0010
-#define MMCHS_SYSCONFIG_SWRESET         (1 << 1)
-#define MMCHS_SYSSTATUS                 0x0014
-#define MMCHS_SYSSTATUS_RESETDONE       (1 << 0)
-
-static struct platform_device dummy_pdev = {
-        .dev = {
-                .bus = &platform_bus_type,
-        },
-};
-
-/**
- * omap_hsmmc_reset() - Full reset of each HS-MMC controller
- *
- * Ensure that each MMC controller is fully reset.  Controllers
- * left in an unknown state (by bootloader) may prevent retention
- * or OFF-mode.  This is especially important in cases where the
- * MMC driver is not enabled, _or_ built as a module.
- *
- * In order for reset to work, interface, functional and debounce
- * clocks must be enabled.  The debounce clock comes from func_32k_clk
- * and is not under SW control, so we only enable i- and f-clocks.
- **/
-static void __init omap_hsmmc_reset(void)
-{
-        u32 i, nr_controllers;
-        struct clk *iclk, *fclk;
-
-        if (cpu_is_omap242x())
-                return;
-
-        nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
-                (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
-
-        for (i = 0; i < nr_controllers; i++) {
-                u32 v, base = 0;
-                struct device *dev = &dummy_pdev.dev;
-
-                switch (i) {
-                case 0:
-                        base = OMAP2_MMC1_BASE;
-                        break;
-                case 1:
-                        base = OMAP2_MMC2_BASE;
-                        break;
-                case 2:
-                        base = OMAP3_MMC3_BASE;
-                        break;
-                case 3:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC4_BASE;
-                        break;
-                case 4:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC5_BASE;
-                        break;
-                }
-
-                if (cpu_is_omap44xx())
-                        base += OMAP4_MMC_REG_OFFSET;
-
-                dummy_pdev.id = i;
-                dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
-                iclk = clk_get(dev, "ick");
-                if (IS_ERR(iclk))
-                        goto err1;
-                if (clk_enable(iclk))
-                        goto err2;
-
-                fclk = clk_get(dev, "fck");
-                if (IS_ERR(fclk))
-                        goto err3;
-                if (clk_enable(fclk))
-                        goto err4;
-
-                omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
-                v = omap_readl(base + MMCHS_SYSSTATUS);
-                while (!(omap_readl(base + MMCHS_SYSSTATUS) &
-                         MMCHS_SYSSTATUS_RESETDONE))
-                        cpu_relax();
-
-                clk_disable(fclk);
-                clk_put(fclk);
-                clk_disable(iclk);
-                clk_put(iclk);
-        }
-        return;
-
-err4:
-        clk_put(fclk);
-err3:
-        clk_disable(iclk);
-err2:
-        clk_put(iclk);
-err1:
-        printk(KERN_WARNING "%s: Unable to enable clocks for MMC%d, "
-                            "cannot reset.\n",  __func__, i);
-}
-#else
-static inline void omap_hsmmc_reset(void) {}
-#endif
-
-#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
-        defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
+#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
 
-static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
-                        int controller_nr)
+static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
+                                                        *mmc_controller)
 {
         if ((mmc_controller->slots[0].switch_pin > 0) && \
                 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
@@ -624,163 +556,44 @@ static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
                 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
                                         OMAP_PIN_INPUT_PULLUP);
 
-        if (cpu_is_omap2420() && controller_nr == 0) {
-                omap_mux_init_signal("sdmmc_cmd", 0);
-                omap_mux_init_signal("sdmmc_clki", 0);
-                omap_mux_init_signal("sdmmc_clko", 0);
-                omap_mux_init_signal("sdmmc_dat0", 0);
-                omap_mux_init_signal("sdmmc_dat_dir0", 0);
-                omap_mux_init_signal("sdmmc_cmd_dir", 0);
-                if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
-                        omap_mux_init_signal("sdmmc_dat1", 0);
-                        omap_mux_init_signal("sdmmc_dat2", 0);
-                        omap_mux_init_signal("sdmmc_dat3", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir1", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir2", 0);
-                        omap_mux_init_signal("sdmmc_dat_dir3", 0);
-                }
-
-                /*
-                 * Use internal loop-back in MMC/SDIO Module Input Clock
-                 * selection
-                 */
-                if (mmc_controller->slots[0].internal_clock) {
-                        u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-                        v |= (1 << 24);
-                        omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
-                }
+        omap_mux_init_signal("sdmmc_cmd", 0);
+        omap_mux_init_signal("sdmmc_clki", 0);
+        omap_mux_init_signal("sdmmc_clko", 0);
+        omap_mux_init_signal("sdmmc_dat0", 0);
+        omap_mux_init_signal("sdmmc_dat_dir0", 0);
+        omap_mux_init_signal("sdmmc_cmd_dir", 0);
+        if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
+                omap_mux_init_signal("sdmmc_dat1", 0);
+                omap_mux_init_signal("sdmmc_dat2", 0);
+                omap_mux_init_signal("sdmmc_dat3", 0);
+                omap_mux_init_signal("sdmmc_dat_dir1", 0);
+                omap_mux_init_signal("sdmmc_dat_dir2", 0);
+                omap_mux_init_signal("sdmmc_dat_dir3", 0);
         }
 
-        if (cpu_is_omap34xx()) {
-                if (controller_nr == 0) {
-                        omap_mux_init_signal("sdmmc1_clk",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc1_cmd",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc1_dat0",
-                                OMAP_PIN_INPUT_PULLUP);
-                        if (mmc_controller->slots[0].caps &
-                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
-                                omap_mux_init_signal("sdmmc1_dat1",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat2",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat3",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                        if (mmc_controller->slots[0].caps &
-                                                MMC_CAP_8_BIT_DATA) {
-                                omap_mux_init_signal("sdmmc1_dat4",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat5",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat6",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc1_dat7",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                }
-                if (controller_nr == 1) {
-                        /* MMC2 */
-                        omap_mux_init_signal("sdmmc2_clk",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc2_cmd",
-                                OMAP_PIN_INPUT_PULLUP);
-                        omap_mux_init_signal("sdmmc2_dat0",
-                                OMAP_PIN_INPUT_PULLUP);
-
-                        /*
-                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
-                         * in the board-*.c files
-                         */
-                        if (mmc_controller->slots[0].caps &
-                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
-                                omap_mux_init_signal("sdmmc2_dat1",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat2",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat3",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                        if (mmc_controller->slots[0].caps &
-                                                        MMC_CAP_8_BIT_DATA) {
-                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
-                                        OMAP_PIN_INPUT_PULLUP);
-                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
-                                        OMAP_PIN_INPUT_PULLUP);
-                        }
-                }
-
-                /*
-                 * For MMC3 the pins need to be muxed in the board-*.c files
-                 */
+        /*
+         * Use internal loop-back in MMC/SDIO Module Input Clock
+         * selection
+         */
+        if (mmc_controller->slots[0].internal_clock) {
+                u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
+                v |= (1 << 24);
+                omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
         }
 }
 
-void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                        int nr_controllers)
+void __init omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
-        int i;
-        char *name;
-
-        for (i = 0; i < nr_controllers; i++) {
-                unsigned long base, size;
-                unsigned int irq = 0;
+        char *name = "mmci-omap";
 
-                if (!mmc_data[i])
-                        continue;
-
-                omap2_mmc_mux(mmc_data[i], i);
+        if (!mmc_data[0]) {
+                pr_err("%s fails: Incomplete platform data\n", __func__);
+                return;
+        }
 
-                switch (i) {
-                case 0:
-                        base = OMAP2_MMC1_BASE;
-                        irq = INT_24XX_MMC_IRQ;
-                        break;
-                case 1:
-                        base = OMAP2_MMC2_BASE;
-                        irq = INT_24XX_MMC2_IRQ;
-                        break;
-                case 2:
-                        if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
-                                return;
-                        base = OMAP3_MMC3_BASE;
-                        irq = INT_34XX_MMC3_IRQ;
-                        break;
-                case 3:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC4_BASE;
-                        irq = OMAP44XX_IRQ_MMC4;
-                        break;
-                case 4:
-                        if (!cpu_is_omap44xx())
-                                return;
-                        base = OMAP4_MMC5_BASE;
-                        irq = OMAP44XX_IRQ_MMC5;
-                        break;
-                default:
-                        continue;
-                }
-
-                if (cpu_is_omap2420()) {
-                        size = OMAP2420_MMC_SIZE;
-                        name = "mmci-omap";
-                } else if (cpu_is_omap44xx()) {
-                        if (i < 3)
-                                irq += OMAP44XX_IRQ_GIC_START;
-                        size = OMAP4_HSMMC_SIZE;
-                        name = "mmci-omap-hs";
-                } else {
-                        size = OMAP3_HSMMC_SIZE;
-                        name = "mmci-omap-hs";
-                }
-                omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
-        };
+        omap242x_mmc_mux(mmc_data[0]);
+        omap_mmc_add(name, 0, OMAP2_MMC1_BASE, OMAP2420_MMC_SIZE,
+                                        INT_24XX_MMC_IRQ, mmc_data[0]);
 }
 
 #endif
@@ -854,7 +667,6 @@ static int __init omap2_init_devices(void)
          * please keep these calls, and their implementations above,
          * in alphabetical order so they're easier to sort through.
          */
-        omap_hsmmc_reset();
         omap_init_audio();
         omap_init_camera();
         omap_init_mbox();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
new file mode 100644
index 000000000000..b18db84b0349
--- /dev/null
+++ b/arch/arm/mach-omap2/display.c
@@ -0,0 +1,45 @@
+/*
+ * OMAP2plus display device setup / initialization.
+ *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ *      Senthilvadivu Guruswamy
+ *      Sumit Semwal
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+
+#include <plat/display.h>
+
+static struct platform_device omap_display_device = {
+        .name          = "omapdss",
+        .id            = -1,
+        .dev            = {
+                .platform_data = NULL,
+        },
+};
+
+int __init omap_display_init(struct omap_dss_board_info *board_data)
+{
+        int r = 0;
+        omap_display_device.dev.platform_data = board_data;
+
+        r = platform_device_register(&omap_display_device);
+        if (r < 0)
+                printk(KERN_ERR "Unable to register OMAP-Display device\n");
+
+        return r;
+}
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c
new file mode 100644
index 000000000000..4e4da6160d05
--- /dev/null
+++ b/arch/arm/mach-omap2/dpll44xx.c
@@ -0,0 +1,84 @@
+/*
+ * OMAP4-specific DPLL control functions
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc.
+ * Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+
+#include <plat/cpu.h>
+#include <plat/clock.h>
+
+#include "clock.h"
+#include "cm-regbits-44xx.h"
+
+/* Supported only on OMAP4 */
+int omap4_dpllmx_gatectrl_read(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return -EINVAL;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+void omap4_dpllmx_allow_gatectrl(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        /* Clear the bit to allow gatectrl */
+        v &= ~mask;
+        __raw_writel(v, clk->clksel_reg);
+}
+
+void omap4_dpllmx_deny_gatectrl(struct clk *clk)
+{
+        u32 v;
+        u32 mask;
+
+        if (!clk || !clk->clksel_reg || !cpu_is_omap44xx())
+                return;
+
+        mask = clk->flags & CLOCK_CLKOUTX2 ?
+                        OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK :
+                        OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK;
+
+        v = __raw_readl(clk->clksel_reg);
+        /* Set the bit to deny gatectrl */
+        v |= mask;
+        __raw_writel(v, clk->clksel_reg);
+}
+
+const struct clkops clkops_omap4_dpllmx_ops = {
+        .allow_idle     = omap4_dpllmx_allow_gatectrl,
+        .deny_idle      = omap4_dpllmx_deny_gatectrl,
+};
+
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index 2bb29c160702..c1791d08ae56 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,6 +12,7 @@
 #include <linux/kernel.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/mtd/nand.h>
 
 #include <asm/mach/flash.h>
 
@@ -69,8 +70,10 @@ static int omap2_nand_gpmc_retime(void)
         t.wr_cycle  = gpmc_round_ns_to_ticks(gpmc_nand_data->gpmc_t->wr_cycle);
 
         /* Configure GPMC */
-        gpmc_cs_configure(gpmc_nand_data->cs,
-                                GPMC_CONFIG_DEV_SIZE, gpmc_nand_data->devsize);
+        if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16)
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 1);
+        else
+                gpmc_cs_configure(gpmc_nand_data->cs, GPMC_CONFIG_DEV_SIZE, 0);
         gpmc_cs_configure(gpmc_nand_data->cs,
                         GPMC_CONFIG_DEV_TYPE, GPMC_DEVICETYPE_NAND);
         err = gpmc_cs_set_timings(gpmc_nand_data->cs, &t);
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 3a7d25fb00ef..d776ded9830d 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -94,7 +94,7 @@ static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base)
 }
 
 static void set_onenand_cfg(void __iomem *onenand_base, int latency,
-                                int sync_read, int sync_write, int hf)
+                                int sync_read, int sync_write, int hf, int vhf)
 {
         u32 reg;
 
@@ -114,12 +114,57 @@ static void set_onenand_cfg(void __iomem *onenand_base, int latency,
                 reg |= ONENAND_SYS_CFG1_HF;
         else
                 reg &= ~ONENAND_SYS_CFG1_HF;
+        if (vhf)
+                reg |= ONENAND_SYS_CFG1_VHF;
+        else
+                reg &= ~ONENAND_SYS_CFG1_VHF;
         writew(reg, onenand_base + ONENAND_REG_SYS_CFG1);
 }
 
+static int omap2_onenand_get_freq(struct omap_onenand_platform_data *cfg,
+                                  void __iomem *onenand_base, bool *clk_dep)
+{
+        u16 ver = readw(onenand_base + ONENAND_REG_VERSION_ID);
+        int freq = 0;
+
+        if (cfg->get_freq) {
+                struct onenand_freq_info fi;
+
+                fi.maf_id = readw(onenand_base + ONENAND_REG_MANUFACTURER_ID);
+                fi.dev_id = readw(onenand_base + ONENAND_REG_DEVICE_ID);
+                fi.ver_id = ver;
+                freq = cfg->get_freq(&fi, clk_dep);
+                if (freq)
+                        return freq;
+        }
+
+        switch ((ver >> 4) & 0xf) {
+        case 0:
+                freq = 40;
+                break;
+        case 1:
+                freq = 54;
+                break;
+        case 2:
+                freq = 66;
+                break;
+        case 3:
+                freq = 83;
+                break;
+        case 4:
+                freq = 104;
+                break;
+        default:
+                freq = 54;
+                break;
+        }
+
+        return freq;
+}
+
 static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                                         void __iomem *onenand_base,
-                                        int freq)
+                                        int *freq_ptr)
 {
         struct gpmc_timings t;
         const int t_cer  = 15;
@@ -130,10 +175,11 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         const int t_wph  = 30;
         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
         int tick_ns, div, fclk_offset_ns, fclk_offset, gpmc_clk_ns, latency;
-        int first_time = 0, hf = 0, sync_read = 0, sync_write = 0;
+        int first_time = 0, hf = 0, vhf = 0, sync_read = 0, sync_write = 0;
         int err, ticks_cez;
-        int cs = cfg->cs;
+        int cs = cfg->cs, freq = *freq_ptr;
         u32 reg;
+        bool clk_dep = false;
 
         if (cfg->flags & ONENAND_SYNC_READ) {
                 sync_read = 1;
@@ -148,27 +194,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 err = omap2_onenand_set_async_mode(cs, onenand_base);
                 if (err)
                         return err;
-                reg = readw(onenand_base + ONENAND_REG_VERSION_ID);
-                switch ((reg >> 4) & 0xf) {
-                case 0:
-                        freq = 40;
-                        break;
-                case 1:
-                        freq = 54;
-                        break;
-                case 2:
-                        freq = 66;
-                        break;
-                case 3:
-                        freq = 83;
-                        break;
-                case 4:
-                        freq = 104;
-                        break;
-                default:
-                        freq = 54;
-                        break;
-                }
+                freq = omap2_onenand_get_freq(cfg, onenand_base, &clk_dep);
                 first_time = 1;
         }
 
@@ -180,7 +206,7 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
                 t_avdh  = 2;
                 t_ach   = 3;
                 t_aavdh = 6;
-                t_rdyo  = 9;
+                t_rdyo  = 6;
                 break;
         case 83:
                 min_gpmc_clk_period = 12000; /* 83 MHz */
@@ -217,16 +243,36 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         gpmc_clk_ns = gpmc_ticks_to_ns(div);
         if (gpmc_clk_ns < 15) /* >66Mhz */
                 hf = 1;
-        if (hf)
+        if (gpmc_clk_ns < 12) /* >83Mhz */
+                vhf = 1;
+        if (vhf)
+                latency = 8;
+        else if (hf)
                 latency = 6;
         else if (gpmc_clk_ns >= 25) /* 40 MHz*/
                 latency = 3;
         else
                 latency = 4;
 
+        if (clk_dep) {
+                if (gpmc_clk_ns < 12) { /* >83Mhz */
+                        t_ces   = 3;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 15) { /* >66Mhz */
+                        t_ces   = 5;
+                        t_avds  = 4;
+                } else if (gpmc_clk_ns < 25) { /* >40Mhz */
+                        t_ces   = 6;
+                        t_avds  = 5;
+                } else {
+                        t_ces   = 7;
+                        t_avds  = 7;
+                }
+        }
+
         if (first_time)
                 set_onenand_cfg(onenand_base, latency,
-                                        sync_read, sync_write, hf);
+                                        sync_read, sync_write, hf, vhf);
 
         if (div == 1) {
                 reg = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG2);
@@ -264,6 +310,9 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         /* Read */
         t.adv_rd_off = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_avdh));
         t.oe_on = gpmc_ticks_to_ns(fclk_offset + gpmc_ns_to_ticks(t_ach));
+        /* Force at least 1 clk between AVD High to OE Low */
+        if (t.oe_on <= t.adv_rd_off)
+                t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(1);
         t.access = gpmc_ticks_to_ns(fclk_offset + (latency + 1) * div);
         t.oe_off = t.access + gpmc_round_ns_to_ticks(1);
         t.cs_rd_off = t.oe_off;
@@ -317,18 +366,20 @@ static int omap2_onenand_set_sync_mode(struct omap_onenand_platform_data *cfg,
         if (err)
                 return err;
 
-        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf);
+        set_onenand_cfg(onenand_base, latency, sync_read, sync_write, hf, vhf);
+
+        *freq_ptr = freq;
 
         return 0;
 }
 
-static int gpmc_onenand_setup(void __iomem *onenand_base, int freq)
+static int gpmc_onenand_setup(void __iomem *onenand_base, int *freq_ptr)
 {
         struct device *dev = &gpmc_onenand_device.dev;
 
         /* Set sync timings in GPMC */
         if (omap2_onenand_set_sync_mode(gpmc_onenand_data, onenand_base,
-                        freq) < 0) {
+                        freq_ptr) < 0) {
                 dev_err(dev, "Unable to set synchronous mode\n");
                 return -EINVAL;
         }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 1b7b3e7d02f7..674174365f78 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -14,6 +14,7 @@
  */
 #undef DEBUG
 
+#include <linux/irq.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/err.h>
@@ -22,6 +23,7 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/module.h>
+#include <linux/interrupt.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -58,7 +60,6 @@
 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 
-#define PREFETCH_FIFOTHRESHOLD  (0x40 << 8)
 #define CS_NUM_SHIFT            24
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
@@ -100,6 +101,8 @@ static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
 
+static irqreturn_t gpmc_handle_irq(int irq, void *dev);
+
 static void gpmc_write_reg(int idx, u32 val)
 {
         __raw_writel(val, gpmc_base + idx);
@@ -497,6 +500,10 @@ int gpmc_cs_configure(int cs, int cmd, int wval)
         u32 regval = 0;
 
         switch (cmd) {
+        case GPMC_ENABLE_IRQ:
+                gpmc_write_reg(GPMC_IRQENABLE, wval);
+                break;
+
         case GPMC_SET_IRQ_STATUS:
                 gpmc_write_reg(GPMC_IRQSTATUS, wval);
                 break;
@@ -598,15 +605,19 @@ EXPORT_SYMBOL(gpmc_nand_write);
 /**
  * gpmc_prefetch_enable - configures and starts prefetch transfer
  * @cs: cs (chip select) number
+ * @fifo_th: fifo threshold to be used for read/ write
  * @dma_mode: dma mode enable (1) or disable (0)
  * @u32_count: number of bytes to be transferred
  * @is_write: prefetch read(0) or write post(1) mode
  */
-int gpmc_prefetch_enable(int cs, int dma_mode,
+int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                 unsigned int u32_count, int is_write)
 {
 
-        if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
+        if (fifo_th > PREFETCH_FIFOTHRESHOLD_MAX) {
+                pr_err("gpmc: fifo threshold is not supported\n");
+                return -1;
+        } else if (!(gpmc_read_reg(GPMC_PREFETCH_CONTROL))) {
                 /* Set the amount of bytes to be prefetched */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, u32_count);
 
@@ -614,7 +625,7 @@ int gpmc_prefetch_enable(int cs, int dma_mode,
                  * enable the engine. Set which cs is has requested for.
                  */
                 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, ((cs << CS_NUM_SHIFT) |
-                                        PREFETCH_FIFOTHRESHOLD |
+                                        PREFETCH_FIFOTHRESHOLD(fifo_th) |
                                         ENABLE_PREFETCH |
                                         (dma_mode << DMA_MPU_MODE) |
                                         (0x1 & is_write)));
@@ -678,9 +689,10 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-void __init gpmc_init(void)
+static int __init gpmc_init(void)
 {
-        u32 l;
+        u32 l, irq;
+        int cs, ret = -EINVAL;
         char *ck = NULL;
 
         if (cpu_is_omap24xx()) {
@@ -698,7 +710,7 @@ void __init gpmc_init(void)
         }
 
         if (WARN_ON(!ck))
-                return;
+                return ret;
 
         gpmc_l3_clk = clk_get(NULL, ck);
         if (IS_ERR(gpmc_l3_clk)) {
@@ -723,6 +735,36 @@ void __init gpmc_init(void)
         l |= (0x02 << 3) | (1 << 0);
         gpmc_write_reg(GPMC_SYSCONFIG, l);
         gpmc_mem_init();
+
+        /* initalize the irq_chained */
+        irq = OMAP_GPMC_IRQ_BASE;
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                set_irq_handler(irq, handle_simple_irq);
+                set_irq_flags(irq, IRQF_VALID);
+                irq++;
+        }
+
+        ret = request_irq(INT_34XX_GPMC_IRQ,
+                        gpmc_handle_irq, IRQF_SHARED, "gpmc", gpmc_base);
+        if (ret)
+                pr_err("gpmc: irq-%d could not claim: err %d\n",
+                                                INT_34XX_GPMC_IRQ, ret);
+        return ret;
+}
+postcore_initcall(gpmc_init);
+
+static irqreturn_t gpmc_handle_irq(int irq, void *dev)
+{
+        u8 cs;
+
+        if (irq != INT_34XX_GPMC_IRQ)
+                return IRQ_HANDLED;
+        /* check cs to invoke the irq */
+        cs = ((gpmc_read_reg(GPMC_PREFETCH_CONFIG1)) >> CS_NUM_SHIFT) & 0x7;
+        if (OMAP_GPMC_IRQ_BASE+cs <= OMAP_GPMC_IRQ_END)
+                generic_handle_irq(OMAP_GPMC_IRQ_BASE+cs);
+
+        return IRQ_HANDLED;
 }
 
 #ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 34272e4863fd..137e1a5f3d85 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -16,7 +16,10 @@
 #include <mach/hardware.h>
 #include <plat/mmc.h>
 #include <plat/omap-pm.h>
+#include <plat/mux.h>
+#include <plat/omap_device.h>
 
+#include "mux.h"
 #include "hsmmc.h"
 #include "control.h"
 
@@ -28,10 +31,6 @@ static u16 control_mmc1;
 
 #define HSMMC_NAME_LEN  9
 
-static struct hsmmc_controller {
-        char                            name[HSMMC_NAME_LEN + 1];
-} hsmmc[OMAP34XX_NR_MMC];
-
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 
 static int hsmmc_get_context_loss(struct device *dev)
@@ -204,174 +203,312 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
         return 0;
 }
 
-static struct omap_mmc_platform_data *hsmmc_data[OMAP34XX_NR_MMC] __initdata;
-
-void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
+                        int controller_nr)
 {
-        struct omap2_hsmmc_info *c;
-        int nr_hsmmc = ARRAY_SIZE(hsmmc_data);
-        int i;
-        u32 reg;
-
-        if (!cpu_is_omap44xx()) {
-                if (cpu_is_omap2430()) {
-                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
-                } else {
-                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
-                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
-                }
-        } else {
-                control_pbias_offset =
-                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
-                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
-                reg = omap4_ctrl_pad_readl(control_mmc1);
-                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
-                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
-                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
-                reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
-                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
-                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
-                omap4_ctrl_pad_writel(reg, control_mmc1);
-        }
-
-        for (c = controllers; c->mmc; c++) {
-                struct hsmmc_controller *hc = hsmmc + c->mmc - 1;
-                struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
-
-                if (!c->mmc || c->mmc > nr_hsmmc) {
-                        pr_debug("MMC%d: no such controller\n", c->mmc);
-                        continue;
-                }
-                if (mmc) {
-                        pr_debug("MMC%d: already configured\n", c->mmc);
-                        continue;
+        if ((mmc_controller->slots[0].switch_pin > 0) && \
+                (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
+                                        OMAP_PIN_INPUT_PULLUP);
+        if ((mmc_controller->slots[0].gpio_wp > 0) && \
+                (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+                omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
+                                        OMAP_PIN_INPUT_PULLUP);
+        if (cpu_is_omap34xx()) {
+                if (controller_nr == 0) {
+                        omap_mux_init_signal("sdmmc1_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc1_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+                                omap_mux_init_signal("sdmmc1_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
+                        if (mmc_controller->slots[0].caps &
+                                                MMC_CAP_8_BIT_DATA) {
+                                omap_mux_init_signal("sdmmc1_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc1_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
                 }
-
-                mmc = kzalloc(sizeof(struct omap_mmc_platform_data),
-                              GFP_KERNEL);
-                if (!mmc) {
-                        pr_err("Cannot allocate memory for mmc device!\n");
-                        goto done;
+                if (controller_nr == 1) {
+                        /* MMC2 */
+                        omap_mux_init_signal("sdmmc2_clk",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_cmd",
+                                OMAP_PIN_INPUT_PULLUP);
+                        omap_mux_init_signal("sdmmc2_dat0",
+                                OMAP_PIN_INPUT_PULLUP);
+
+                        /*
+                         * For 8 wire configurations, Lines DAT4, 5, 6 and 7
+                         * need to be muxed in the board-*.c files
+                         */
+                        if (mmc_controller->slots[0].caps &
+                                (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+                                omap_mux_init_signal("sdmmc2_dat1",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat2",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat3",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
+                        if (mmc_controller->slots[0].caps &
+                                                        MMC_CAP_8_BIT_DATA) {
+                                omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
+                                        OMAP_PIN_INPUT_PULLUP);
+                                omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
+                                        OMAP_PIN_INPUT_PULLUP);
+                        }
                 }
 
-                if (c->name)
-                        strncpy(hc->name, c->name, HSMMC_NAME_LEN);
-                else
-                        snprintf(hc->name, ARRAY_SIZE(hc->name),
-                                "mmc%islot%i", c->mmc, 1);
-                mmc->slots[0].name = hc->name;
-                mmc->nr_slots = 1;
-                mmc->slots[0].caps = c->caps;
-                mmc->slots[0].internal_clock = !c->ext_clock;
-                mmc->dma_mask = 0xffffffff;
-                if (cpu_is_omap44xx())
-                        mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
-                else
-                        mmc->reg_offset = 0;
+                /*
+                 * For MMC3 the pins need to be muxed in the board-*.c files
+                 */
+        }
+}
 
-                mmc->get_context_loss_count = hsmmc_get_context_loss;
+static int __init omap_hsmmc_pdata_init(struct omap2_hsmmc_info *c,
+                                        struct omap_mmc_platform_data *mmc)
+{
+        char *hc_name;
 
-                mmc->slots[0].switch_pin = c->gpio_cd;
-                mmc->slots[0].gpio_wp = c->gpio_wp;
+        hc_name = kzalloc(sizeof(char) * (HSMMC_NAME_LEN + 1), GFP_KERNEL);
+        if (!hc_name) {
+                pr_err("Cannot allocate memory for controller slot name\n");
+                kfree(hc_name);
+                return -ENOMEM;
+        }
 
-                mmc->slots[0].remux = c->remux;
-                mmc->slots[0].init_card = c->init_card;
+        if (c->name)
+                strncpy(hc_name, c->name, HSMMC_NAME_LEN);
+        else
+                snprintf(hc_name, (HSMMC_NAME_LEN + 1), "mmc%islot%i",
+                                                                c->mmc, 1);
+        mmc->slots[0].name = hc_name;
+        mmc->nr_slots = 1;
+        mmc->slots[0].caps = c->caps;
+        mmc->slots[0].internal_clock = !c->ext_clock;
+        mmc->dma_mask = 0xffffffff;
+        if (cpu_is_omap44xx())
+                mmc->reg_offset = OMAP4_MMC_REG_OFFSET;
+        else
+                mmc->reg_offset = 0;
 
-                if (c->cover_only)
-                        mmc->slots[0].cover = 1;
+        mmc->get_context_loss_count = hsmmc_get_context_loss;
 
-                if (c->nonremovable)
-                        mmc->slots[0].nonremovable = 1;
+        mmc->slots[0].switch_pin = c->gpio_cd;
+        mmc->slots[0].gpio_wp = c->gpio_wp;
 
-                if (c->power_saving)
-                        mmc->slots[0].power_saving = 1;
+        mmc->slots[0].remux = c->remux;
+        mmc->slots[0].init_card = c->init_card;
 
-                if (c->no_off)
-                        mmc->slots[0].no_off = 1;
+        if (c->cover_only)
+                mmc->slots[0].cover = 1;
 
-                if (c->vcc_aux_disable_is_sleep)
-                        mmc->slots[0].vcc_aux_disable_is_sleep = 1;
+        if (c->nonremovable)
+                mmc->slots[0].nonremovable = 1;
 
-                /* NOTE:  MMC slots should have a Vcc regulator set up.
-                 * This may be from a TWL4030-family chip, another
-                 * controllable regulator, or a fixed supply.
-                 *
-                 * temporary HACK: ocr_mask instead of fixed supply
-                 */
-                mmc->slots[0].ocr_mask = c->ocr_mask;
+        if (c->power_saving)
+                mmc->slots[0].power_saving = 1;
 
-                if (cpu_is_omap3517() || cpu_is_omap3505())
-                        mmc->slots[0].set_power = nop_mmc_set_power;
-                else
-                        mmc->slots[0].features |= HSMMC_HAS_PBIAS;
+        if (c->no_off)
+                mmc->slots[0].no_off = 1;
 
-                if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
-                        mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+        if (c->vcc_aux_disable_is_sleep)
+                mmc->slots[0].vcc_aux_disable_is_sleep = 1;
 
-                switch (c->mmc) {
-                case 1:
-                        if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
-                                /* on-chip level shifting via PBIAS0/PBIAS1 */
-                                if (cpu_is_omap44xx()) {
-                                        mmc->slots[0].before_set_reg =
+        /*
+         * NOTE:  MMC slots should have a Vcc regulator set up.
+         * This may be from a TWL4030-family chip, another
+         * controllable regulator, or a fixed supply.
+         *
+         * temporary HACK: ocr_mask instead of fixed supply
+         */
+        mmc->slots[0].ocr_mask = c->ocr_mask;
+
+        if (cpu_is_omap3517() || cpu_is_omap3505())
+                mmc->slots[0].set_power = nop_mmc_set_power;
+        else
+                mmc->slots[0].features |= HSMMC_HAS_PBIAS;
+
+        if (cpu_is_omap44xx() && (omap_rev() > OMAP4430_REV_ES1_0))
+                mmc->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
+
+        switch (c->mmc) {
+        case 1:
+                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                        /* on-chip level shifting via PBIAS0/PBIAS1 */
+                        if (cpu_is_omap44xx()) {
+                                mmc->slots[0].before_set_reg =
                                                 omap4_hsmmc1_before_set_reg;
-                                        mmc->slots[0].after_set_reg =
+                                mmc->slots[0].after_set_reg =
                                                 omap4_hsmmc1_after_set_reg;
-                                } else {
-                                        mmc->slots[0].before_set_reg =
+                        } else {
+                                mmc->slots[0].before_set_reg =
                                                 omap_hsmmc1_before_set_reg;
-                                        mmc->slots[0].after_set_reg =
+                                mmc->slots[0].after_set_reg =
                                                 omap_hsmmc1_after_set_reg;
-                                }
                         }
+                }
 
-                        /* Omap3630 HSMMC1 supports only 4-bit */
-                        if (cpu_is_omap3630() &&
-                                        (c->caps & MMC_CAP_8_BIT_DATA)) {
-                                c->caps &= ~MMC_CAP_8_BIT_DATA;
-                                c->caps |= MMC_CAP_4_BIT_DATA;
-                                mmc->slots[0].caps = c->caps;
-                        }
-                        break;
-                case 2:
-                        if (c->ext_clock)
-                                c->transceiver = 1;
-                        if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
-                                c->caps &= ~MMC_CAP_8_BIT_DATA;
-                                c->caps |= MMC_CAP_4_BIT_DATA;
-                        }
-                        /* FALLTHROUGH */
-                case 3:
-                        if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
-                                /* off-chip level shifting, or none */
-                                mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
-                                mmc->slots[0].after_set_reg = NULL;
-                        }
-                        break;
-                default:
-                        pr_err("MMC%d configuration not supported!\n", c->mmc);
-                        kfree(mmc);
-                        continue;
+                /* OMAP3630 HSMMC1 supports only 4-bit */
+                if (cpu_is_omap3630() &&
+                                (c->caps & MMC_CAP_8_BIT_DATA)) {
+                        c->caps &= ~MMC_CAP_8_BIT_DATA;
+                        c->caps |= MMC_CAP_4_BIT_DATA;
+                        mmc->slots[0].caps = c->caps;
+                }
+                break;
+        case 2:
+                if (c->ext_clock)
+                        c->transceiver = 1;
+                if (c->transceiver && (c->caps & MMC_CAP_8_BIT_DATA)) {
+                        c->caps &= ~MMC_CAP_8_BIT_DATA;
+                        c->caps |= MMC_CAP_4_BIT_DATA;
                 }
-                hsmmc_data[c->mmc - 1] = mmc;
+                /* FALLTHROUGH */
+        case 3:
+                if (mmc->slots[0].features & HSMMC_HAS_PBIAS) {
+                        /* off-chip level shifting, or none */
+                        mmc->slots[0].before_set_reg = hsmmc23_before_set_reg;
+                        mmc->slots[0].after_set_reg = NULL;
+                }
+                break;
+        case 4:
+        case 5:
+                mmc->slots[0].before_set_reg = NULL;
+                mmc->slots[0].after_set_reg = NULL;
+                break;
+        default:
+                pr_err("MMC%d configuration not supported!\n", c->mmc);
+                kfree(hc_name);
+                return -ENODEV;
+        }
+        return 0;
+}
+
+static struct omap_device_pm_latency omap_hsmmc_latency[] = {
+        [0] = {
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+        },
+        /*
+         * XXX There should also be an entry here to power off/on the
+         * MMC regulators/PBIAS cells, etc.
+         */
+};
+
+#define MAX_OMAP_MMC_HWMOD_NAME_LEN             16
+
+void __init omap_init_hsmmc(struct omap2_hsmmc_info *hsmmcinfo, int ctrl_nr)
+{
+        struct omap_hwmod *oh;
+        struct omap_device *od;
+        struct omap_device_pm_latency *ohl;
+        char oh_name[MAX_OMAP_MMC_HWMOD_NAME_LEN];
+        struct omap_mmc_platform_data *mmc_data;
+        struct omap_mmc_dev_attr *mmc_dev_attr;
+        char *name;
+        int l;
+        int ohl_cnt = 0;
+
+        mmc_data = kzalloc(sizeof(struct omap_mmc_platform_data), GFP_KERNEL);
+        if (!mmc_data) {
+                pr_err("Cannot allocate memory for mmc device!\n");
+                goto done;
         }
 
-        omap2_init_mmc(hsmmc_data, OMAP34XX_NR_MMC);
+        if (omap_hsmmc_pdata_init(hsmmcinfo, mmc_data) < 0) {
+                pr_err("%s fails!\n", __func__);
+                goto done;
+        }
+        omap_hsmmc_mux(mmc_data, (ctrl_nr - 1));
+
+        name = "omap_hsmmc";
+        ohl = omap_hsmmc_latency;
+        ohl_cnt = ARRAY_SIZE(omap_hsmmc_latency);
+
+        l = snprintf(oh_name, MAX_OMAP_MMC_HWMOD_NAME_LEN,
+                     "mmc%d", ctrl_nr);
+        WARN(l >= MAX_OMAP_MMC_HWMOD_NAME_LEN,
+             "String buffer overflow in MMC%d device setup\n", ctrl_nr);
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                kfree(mmc_data->slots[0].name);
+                goto done;
+        }
 
-        /* pass the device nodes back to board setup code */
-        for (c = controllers; c->mmc; c++) {
-                struct omap_mmc_platform_data *mmc = hsmmc_data[c->mmc - 1];
+        if (oh->dev_attr != NULL) {
+                mmc_dev_attr = oh->dev_attr;
+                mmc_data->controller_flags = mmc_dev_attr->flags;
+        }
 
-                if (!c->mmc || c->mmc > nr_hsmmc)
-                        continue;
-                c->dev = mmc->dev;
+        od = omap_device_build(name, ctrl_nr - 1, oh, mmc_data,
+                sizeof(struct omap_mmc_platform_data), ohl, ohl_cnt, false);
+        if (IS_ERR(od)) {
+                WARN(1, "Cant build omap_device for %s:%s.\n", name, oh->name);
+                kfree(mmc_data->slots[0].name);
+                goto done;
         }
+        /*
+         * return device handle to board setup code
+         * required to populate for regulator framework structure
+         */
+        hsmmcinfo->dev = &od->pdev.dev;
 
 done:
-        for (i = 0; i < nr_hsmmc; i++)
-                kfree(hsmmc_data[i]);
+        kfree(mmc_data);
+}
+
+void __init omap2_hsmmc_init(struct omap2_hsmmc_info *controllers)
+{
+        u32 reg;
+
+        if (!cpu_is_omap44xx()) {
+                if (cpu_is_omap2430()) {
+                        control_pbias_offset = OMAP243X_CONTROL_PBIAS_LITE;
+                        control_devconf1_offset = OMAP243X_CONTROL_DEVCONF1;
+                } else {
+                        control_pbias_offset = OMAP343X_CONTROL_PBIAS_LITE;
+                        control_devconf1_offset = OMAP343X_CONTROL_DEVCONF1;
+                }
+        } else {
+                control_pbias_offset =
+                        OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE;
+                control_mmc1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1;
+                reg = omap4_ctrl_pad_readl(control_mmc1);
+                reg |= (OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK);
+                reg &= ~(OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK |
+                        OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK);
+                reg |= (OMAP4_USBC1_DR0_SPEEDCTRL_MASK|
+                        OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK |
+                        OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK);
+                omap4_ctrl_pad_writel(reg, control_mmc1);
+        }
+
+        for (; controllers->mmc; controllers++)
+                omap_init_hsmmc(controllers, controllers->mmc);
+
 }
 
 #endif
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 5c25f1b55235..3168b17bc264 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -6,7 +6,7 @@
  * Copyright (C) 2005 Nokia Corporation
  * Written by Tony Lindgren <tony@atomide.com>
  *
- * Copyright (C) 2009 Texas Instruments
+ * Copyright (C) 2009-11 Texas Instruments
  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  *
  * This program is free software; you can redistribute it and/or modify
@@ -328,7 +328,7 @@ static void __init omap4_check_revision(void)
          */
         idcode = read_tap_reg(OMAP_TAP_IDCODE);
         hawkeye = (idcode >> 12) & 0xffff;
-        rev = (idcode >> 28) & 0xff;
+        rev = (idcode >> 28) & 0xf;
 
         /*
          * Few initial ES2.0 samples IDCODE is same as ES1.0
@@ -347,22 +347,31 @@ static void __init omap4_check_revision(void)
                         omap_chip.oc |= CHIP_IS_OMAP4430ES1;
                         break;
                 case 1:
+                default:
                         omap_revision = OMAP4430_REV_ES2_0;
                         omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                }
+                break;
+        case 0xb95c:
+                switch (rev) {
+                case 3:
+                        omap_revision = OMAP4430_REV_ES2_1;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_1;
                         break;
+                case 4:
                 default:
-                        omap_revision = OMAP4430_REV_ES2_0;
-                        omap_chip.oc |= CHIP_IS_OMAP4430ES2;
-        }
-        break;
+                        omap_revision = OMAP4430_REV_ES2_2;
+                        omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
+                }
+                break;
         default:
-                /* Unknown default to latest silicon rev as default*/
-                omap_revision = OMAP4430_REV_ES2_0;
-                omap_chip.oc |= CHIP_IS_OMAP4430ES2;
+                /* Unknown default to latest silicon rev as default */
+                omap_revision = OMAP4430_REV_ES2_2;
+                omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
         }
 
-        pr_info("OMAP%04x ES%d.0\n",
-                        omap_rev() >> 16, ((omap_rev() >> 12) & 0xf) + 1);
+        pr_info("OMAP%04x ES%d.%d\n", omap_rev() >> 16,
+                ((omap_rev() >> 12) & 0xf), ((omap_rev() >> 8) & 0xf));
 }
 
 #define OMAP3_SHOW_FEATURE(feat)                \
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 03f71ec3cd82..441e79d043a7 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -30,7 +30,6 @@
 
 #include <plat/sram.h>
 #include <plat/sdrc.h>
-#include <plat/gpmc.h>
 #include <plat/serial.h>
 
 #include "clock2xxx.h"
@@ -422,7 +421,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
                 omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
                 _omap2_init_reprogram_sdrc();
         }
-        gpmc_init();
 
         omap_irq_base_init();
 }
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index 14ee686b6492..adb083e41acd 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -145,35 +145,32 @@ static void omap2_iommu_set_twl(struct iommu *obj, bool on)
 
 static u32 omap2_iommu_fault_isr(struct iommu *obj, u32 *ra)
 {
-        int i;
         u32 stat, da;
-        const char *err_msg[] = {
-                "tlb miss",
-                "translation fault",
-                "emulation miss",
-                "table walk fault",
-                "multi hit fault",
-        };
+        u32 errs = 0;
 
         stat = iommu_read_reg(obj, MMU_IRQSTATUS);
         stat &= MMU_IRQ_MASK;
-        if (!stat)
+        if (!stat) {
+                *ra = 0;
                 return 0;
+        }
 
         da = iommu_read_reg(obj, MMU_FAULT_AD);
         *ra = da;
 
-        dev_err(obj->dev, "%s:\tda:%08x ", __func__, da);
-
-        for (i = 0; i < ARRAY_SIZE(err_msg); i++) {
-                if (stat & (1 << i))
-                        printk("%s ", err_msg[i]);
-        }
-        printk("\n");
-
+        if (stat & MMU_IRQ_TLBMISS)
+                errs |= OMAP_IOMMU_ERR_TLB_MISS;
+        if (stat & MMU_IRQ_TRANSLATIONFAULT)
+                errs |= OMAP_IOMMU_ERR_TRANS_FAULT;
+        if (stat & MMU_IRQ_EMUMISS)
+                errs |= OMAP_IOMMU_ERR_EMU_MISS;
+        if (stat & MMU_IRQ_TABLEWALKFAULT)
+                errs |= OMAP_IOMMU_ERR_TBLWALK_FAULT;
+        if (stat & MMU_IRQ_MULTIHITFAULT)
+                errs |= OMAP_IOMMU_ERR_MULTIHIT_FAULT;
         iommu_write_reg(obj, stat, MMU_IRQSTATUS);
 
-        return stat;
+        return errs;
 }
 
 static void omap2_tlb_read_cr(struct iommu *obj, struct cr_regs *cr)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 29b9dc3917af..6e15e3d7c65e 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -14,12 +14,11 @@
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/pm_runtime.h>
 #include <plat/mailbox.h>
 #include <mach/irqs.h>
 
 #define MAILBOX_REVISION                0x000
-#define MAILBOX_SYSCONFIG               0x010
-#define MAILBOX_SYSSTATUS               0x014
 #define MAILBOX_MESSAGE(m)              (0x040 + 4 * (m))
 #define MAILBOX_FIFOSTATUS(m)           (0x080 + 4 * (m))
 #define MAILBOX_MSGSTATUS(m)            (0x0c0 + 4 * (m))
@@ -33,17 +32,6 @@
 #define MAILBOX_IRQ_NEWMSG(m)           (1 << (2 * (m)))
 #define MAILBOX_IRQ_NOTFULL(m)          (1 << (2 * (m) + 1))
 
-/* SYSCONFIG: register bit definition */
-#define AUTOIDLE        (1 << 0)
-#define SOFTRESET       (1 << 1)
-#define SMARTIDLE       (2 << 3)
-#define OMAP4_SOFTRESET (1 << 0)
-#define OMAP4_NOIDLE    (1 << 2)
-#define OMAP4_SMARTIDLE (2 << 2)
-
-/* SYSSTATUS: register bit definition */
-#define RESETDONE       (1 << 0)
-
 #define MBOX_REG_SIZE                   0x120
 
 #define OMAP4_MBOX_REG_SIZE             0x130
@@ -70,8 +58,6 @@ struct omap_mbox2_priv {
         unsigned long irqdisable;
 };
 
-static struct clk *mbox_ick_handle;
-
 static void omap2_mbox_enable_irq(struct omap_mbox *mbox,
                                   omap_mbox_type_t irq);
 
@@ -89,53 +75,13 @@ static inline void mbox_write_reg(u32 val, size_t ofs)
 static int omap2_mbox_startup(struct omap_mbox *mbox)
 {
         u32 l;
-        unsigned long timeout;
 
-        mbox_ick_handle = clk_get(NULL, "mailboxes_ick");
-        if (IS_ERR(mbox_ick_handle)) {
-                printk(KERN_ERR "Could not get mailboxes_ick: %ld\n",
-                        PTR_ERR(mbox_ick_handle));
-                return PTR_ERR(mbox_ick_handle);
-        }
-        clk_enable(mbox_ick_handle);
-
-        if (cpu_is_omap44xx()) {
-                mbox_write_reg(OMAP4_SOFTRESET, MAILBOX_SYSCONFIG);
-                timeout = jiffies + msecs_to_jiffies(20);
-                do {
-                        l = mbox_read_reg(MAILBOX_SYSCONFIG);
-                        if (!(l & OMAP4_SOFTRESET))
-                                break;
-                } while (!time_after(jiffies, timeout));
-
-                if (l & OMAP4_SOFTRESET) {
-                        pr_err("Can't take mailbox out of reset\n");
-                        return -ENODEV;
-                }
-        } else {
-                mbox_write_reg(SOFTRESET, MAILBOX_SYSCONFIG);
-                timeout = jiffies + msecs_to_jiffies(20);
-                do {
-                        l = mbox_read_reg(MAILBOX_SYSSTATUS);
-                        if (l & RESETDONE)
-                                break;
-                } while (!time_after(jiffies, timeout));
-
-                if (!(l & RESETDONE)) {
-                        pr_err("Can't take mailbox out of reset\n");
-                        return -ENODEV;
-                }
-        }
+        pm_runtime_enable(mbox->dev->parent);
+        pm_runtime_get_sync(mbox->dev->parent);
 
         l = mbox_read_reg(MAILBOX_REVISION);
         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 
-        if (cpu_is_omap44xx())
-                l = OMAP4_SMARTIDLE;
-        else
-                l = SMARTIDLE | AUTOIDLE;
-        mbox_write_reg(l, MAILBOX_SYSCONFIG);
-
         omap2_mbox_enable_irq(mbox, IRQ_RX);
 
         return 0;
@@ -143,9 +89,8 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
 
 static void omap2_mbox_shutdown(struct omap_mbox *mbox)
 {
-        clk_disable(mbox_ick_handle);
-        clk_put(mbox_ick_handle);
-        mbox_ick_handle = NULL;
+        pm_runtime_put_sync(mbox->dev->parent);
+        pm_runtime_disable(mbox->dev->parent);
 }
 
 /* Mailbox FIFO handle functions */
@@ -334,7 +279,7 @@ static struct omap_mbox mbox_iva_info = {
         .priv   = &omap2_mbox_iva_priv,
 };
 
-struct omap_mbox *omap2_mboxes[] = { &mbox_iva_info, &mbox_dsp_info, NULL };
+struct omap_mbox *omap2_mboxes[] = { &mbox_dsp_info, &mbox_iva_info, NULL };
 #endif
 
 #if defined(CONFIG_ARCH_OMAP4)
@@ -398,14 +343,14 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
         else if (cpu_is_omap34xx()) {
                 list = omap3_mboxes;
 
-                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+                list[0]->irq = platform_get_irq(pdev, 0);
         }
 #endif
 #if defined(CONFIG_ARCH_OMAP2)
         else if (cpu_is_omap2430()) {
                 list = omap2_mboxes;
 
-                list[0]->irq = platform_get_irq_byname(pdev, "dsp");
+                list[0]->irq = platform_get_irq(pdev, 0);
         } else if (cpu_is_omap2420()) {
                 list = omap2_mboxes;
 
@@ -417,8 +362,7 @@ static int __devinit omap2_mbox_probe(struct platform_device *pdev)
         else if (cpu_is_omap44xx()) {
                 list = omap4_mboxes;
 
-                list[0]->irq = list[1]->irq =
-                        platform_get_irq_byname(pdev, "mbox");
+                list[0]->irq = list[1]->irq = platform_get_irq(pdev, 0);
         }
 #endif
         else {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 0526b758bdcc..565b9064a328 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -22,10 +22,11 @@
 #include <plat/dma.h>
 #include <plat/cpu.h>
 #include <plat/mcbsp.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
 
 #include "control.h"
 
-
 /* McBSP internal signal muxing functions */
 
 void omap2_mcbsp1_mux_clkr_src(u8 mux)
@@ -83,7 +84,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
                 return -EINVAL;
         }
 
-        clk_disable(mcbsp->fclk);
+        pm_runtime_put_sync(mcbsp->dev);
 
         r = clk_set_parent(mcbsp->fclk, fck_src);
         if (IS_ERR_VALUE(r)) {
@@ -93,7 +94,7 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
                 return -EINVAL;
         }
 
-        clk_enable(mcbsp->fclk);
+        pm_runtime_get_sync(mcbsp->dev);
 
         clk_put(fck_src);
 
@@ -101,196 +102,70 @@ int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
 }
 EXPORT_SYMBOL(omap2_mcbsp_set_clks_src);
 
-
-/* Platform data */
-
-#ifdef CONFIG_SOC_OMAP2420
-static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
+struct omap_device_pm_latency omap2_mcbsp_latency[] = {
         {
-                .phys_base      = OMAP24XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-        },
-        {
-                .phys_base      = OMAP24XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .deactivate_func = omap_device_idle_hwmods,
+                .activate_func   = omap_device_enable_hwmods,
+                .flags = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
         },
 };
-#define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
-#define OMAP2420_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap2420_mcbsp_pdata            NULL
-#define OMAP2420_MCBSP_PDATA_SZ         0
-#define OMAP2420_MCBSP_REG_NUM          0
-#endif
 
-#ifdef CONFIG_SOC_OMAP2430
-static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP24XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-        },
-        {
-                .phys_base      = OMAP24XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
-                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
-                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-        },
-        {
-                .phys_base      = OMAP2430_MCBSP5_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
-                .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-        },
-};
-#define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
-#define OMAP2430_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap2430_mcbsp_pdata            NULL
-#define OMAP2430_MCBSP_PDATA_SZ         0
-#define OMAP2430_MCBSP_REG_NUM          0
-#endif
+static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
+{
+        int id, count = 1;
+        char *name = "omap-mcbsp";
+        struct omap_hwmod *oh_device[2];
+        struct omap_mcbsp_platform_data *pdata = NULL;
+        struct omap_device *od;
 
-#ifdef CONFIG_ARCH_OMAP3
-static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP34XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
-                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP2_BASE,
-                .phys_base_st   = OMAP34XX_MCBSP2_ST_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
-                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
-                .buffer_size    = 0x500, /* The FIFO has 1024 + 256 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP3_BASE,
-                .phys_base_st   = OMAP34XX_MCBSP3_ST_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
-                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
-                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-        {
-                .phys_base      = OMAP34XX_MCBSP5_BASE,
-                .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
-                .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
-                .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
-                .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
-                .buffer_size    = 0x80, /* The FIFO has 128 locations */
-        },
-};
-#define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
-#define OMAP34XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
-#else
-#define omap34xx_mcbsp_pdata            NULL
-#define OMAP34XX_MCBSP_PDATA_SZ         0
-#define OMAP34XX_MCBSP_REG_NUM          0
-#endif
+        sscanf(oh->name, "mcbsp%d", &id);
 
-static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
-        {
-                .phys_base      = OMAP44XX_MCBSP1_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP1,
-        },
-        {
-                .phys_base      = OMAP44XX_MCBSP2_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP2,
-        },
-        {
-                .phys_base      = OMAP44XX_MCBSP3_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP3,
-        },
-        {
-                .phys_base      = OMAP44XX_MCBSP4_BASE,
-                .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
-                .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
-                .tx_irq         = OMAP44XX_IRQ_MCBSP4,
-        },
-};
-#define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
-#define OMAP44XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
+        pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
+        if (!pdata) {
+                pr_err("%s: No memory for mcbsp\n", __func__);
+                return -ENOMEM;
+        }
+
+        pdata->mcbsp_config_type = oh->class->rev;
+
+        if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
+                if (id == 2)
+                        /* The FIFO has 1024 + 256 locations */
+                        pdata->buffer_size = 0x500;
+                else
+                        /* The FIFO has 128 locations */
+                        pdata->buffer_size = 0x80;
+        }
+
+        oh_device[0] = oh;
+
+        if (oh->dev_attr) {
+                oh_device[1] = omap_hwmod_lookup((
+                (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
+                count++;
+        }
+        od = omap_device_build_ss(name, id, oh_device, count, pdata,
+                                sizeof(*pdata), omap2_mcbsp_latency,
+                                ARRAY_SIZE(omap2_mcbsp_latency), false);
+        kfree(pdata);
+        if (IS_ERR(od))  {
+                pr_err("%s: Cant build omap_device for %s:%s.\n", __func__,
+                                        name, oh->name);
+                return PTR_ERR(od);
+        }
+        omap_mcbsp_count++;
+        return 0;
+}
 
 static int __init omap2_mcbsp_init(void)
 {
-        if (cpu_is_omap2420()) {
-                omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
-        } else if (cpu_is_omap2430()) {
-                omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
-        } else if (cpu_is_omap34xx()) {
-                omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
-        } else if (cpu_is_omap44xx()) {
-                omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
-                omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
-        }
+        omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
 
         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                 GFP_KERNEL);
         if (!mcbsp_ptr)
                 return -ENOMEM;
 
-        if (cpu_is_omap2420())
-                omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
-                                                OMAP2420_MCBSP_PDATA_SZ);
-        if (cpu_is_omap2430())
-                omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
-                                                OMAP2430_MCBSP_PDATA_SZ);
-        if (cpu_is_omap34xx())
-                omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
-                                                OMAP34XX_MCBSP_PDATA_SZ);
-        if (cpu_is_omap44xx())
-                omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
-                                                OMAP44XX_MCBSP_PDATA_SZ);
-
         return omap_mcbsp_init();
 }
 arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 98148b6c36e9..6c84659cf846 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -605,7 +605,7 @@ static void __init omap_mux_dbg_create_entry(
         list_for_each_entry(e, &partition->muxmodes, node) {
                 struct omap_mux *m = &e->mux;
 
-                (void)debugfs_create_file(m->muxnames[0], S_IWUGO, mux_dbg_dir,
+                (void)debugfs_create_file(m->muxnames[0], S_IWUSR, mux_dbg_dir,
                                           m, &omap_mux_dbg_signal_fops);
         }
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9e89a58711b7..e39772beaedd 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod implementation for OMAP2/3/4
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Paul Walmsley, Benoît Cousson, Kevin Hilman
  *
@@ -162,9 +162,6 @@ static LIST_HEAD(omap_hwmod_list);
 /* mpu_oh: used to add/remove MPU initiator from sleepdep list */
 static struct omap_hwmod *mpu_oh;
 
-/* inited: 0 if omap_hwmod_init() has not yet been called; 1 otherwise */
-static u8 inited;
-
 
 /* Private functions */
 
@@ -460,14 +457,18 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
  * will be accessed by a particular initiator (e.g., if a module will
  * be accessed by the IVA, there should be a sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
- * mode.  Returns -EINVAL upon error or passes along
- * clkdm_add_sleepdep() value upon success.
+ * mode.  If the clockdomain is marked as not needing autodeps, return
+ * 0 without doing anything.  Otherwise, returns -EINVAL upon error or
+ * passes along clkdm_add_sleepdep() value upon success.
  */
 static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
+        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+                return 0;
+
         return clkdm_add_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
@@ -480,14 +481,18 @@ static int _add_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
  * be accessed by a particular initiator (e.g., if a module will not
  * be accessed by the IVA, there should be no sleepdep between the IVA
  * initiator and the module).  Only applies to modules in smart-idle
- * mode.  Returns -EINVAL upon error or passes along
- * clkdm_del_sleepdep() value upon success.
+ * mode.  If the clockdomain is marked as not needing autodeps, return
+ * 0 without doing anything.  Returns -EINVAL upon error or passes
+ * along clkdm_del_sleepdep() value upon success.
  */
 static int _del_initiator_dep(struct omap_hwmod *oh, struct omap_hwmod *init_oh)
 {
         if (!oh->_clk)
                 return -EINVAL;
 
+        if (oh->_clk->clkdm && oh->_clk->clkdm->flags & CLKDM_NO_AUTODEPS)
+                return 0;
+
         return clkdm_del_sleepdep(oh->_clk->clkdm, init_oh->_clk->clkdm);
 }
 
@@ -904,18 +909,16 @@ static struct omap_hwmod *_lookup(const char *name)
  * @oh: struct omap_hwmod *
  * @data: not used; pass NULL
  *
- * Called by omap_hwmod_late_init() (after omap2_clk_init()).
- * Resolves all clock names embedded in the hwmod.  Returns -EINVAL if
- * the omap_hwmod has not yet been registered or if the clocks have
- * already been initialized, 0 on success, or a non-zero error on
- * failure.
+ * Called by omap_hwmod_setup_*() (after omap2_clk_init()).
+ * Resolves all clock names embedded in the hwmod.  Returns 0 on
+ * success, or a negative error code on failure.
  */
 static int _init_clocks(struct omap_hwmod *oh, void *data)
 {
         int ret = 0;
 
-        if (!oh || (oh->_state != _HWMOD_STATE_REGISTERED))
-                return -EINVAL;
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
+                return 0;
 
         pr_debug("omap_hwmod: %s: looking up clocks\n", oh->name);
 
@@ -1288,6 +1291,42 @@ static int _idle(struct omap_hwmod *oh)
 }
 
 /**
+ * omap_hwmod_set_ocp_autoidle - set the hwmod's OCP autoidle bit
+ * @oh: struct omap_hwmod *
+ * @autoidle: desired AUTOIDLE bitfield value (0 or 1)
+ *
+ * Sets the IP block's OCP autoidle bit in hardware, and updates our
+ * local copy. Intended to be used by drivers that require
+ * direct manipulation of the AUTOIDLE bits.
+ * Returns -EINVAL if @oh is null or is not in the ENABLED state, or passes
+ * along the return value from _set_module_autoidle().
+ *
+ * Any users of this function should be scrutinized carefully.
+ */
+int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle)
+{
+        u32 v;
+        int retval = 0;
+        unsigned long flags;
+
+        if (!oh || oh->_state != _HWMOD_STATE_ENABLED)
+                return -EINVAL;
+
+        spin_lock_irqsave(&oh->_lock, flags);
+
+        v = oh->_sysc_cache;
+
+        retval = _set_module_autoidle(oh, autoidle, &v);
+
+        if (!retval)
+                _write_sysconfig(v, oh);
+
+        spin_unlock_irqrestore(&oh->_lock, flags);
+
+        return retval;
+}
+
+/**
  * _shutdown - shutdown an omap_hwmod
  * @oh: struct omap_hwmod *
  *
@@ -1354,14 +1393,16 @@ static int _shutdown(struct omap_hwmod *oh)
  * @oh: struct omap_hwmod *
  *
  * Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
- * OCP_SYSCONFIG register.  Returns -EINVAL if the hwmod is in the
- * wrong state or returns 0.
+ * OCP_SYSCONFIG register.  Returns 0.
  */
 static int _setup(struct omap_hwmod *oh, void *data)
 {
         int i, r;
         u8 postsetup_state;
 
+        if (oh->_state != _HWMOD_STATE_CLKS_INITED)
+                return 0;
+
         /* Set iclk autoidle mode */
         if (oh->slaves_cnt > 0) {
                 for (i = 0; i < oh->slaves_cnt; i++) {
@@ -1455,7 +1496,7 @@ static int _setup(struct omap_hwmod *oh, void *data)
  */
 static int __init _register(struct omap_hwmod *oh)
 {
-        int ret, ms_id;
+        int ms_id;
 
         if (!oh || !oh->name || !oh->class || !oh->class->name ||
             (oh->_state != _HWMOD_STATE_UNKNOWN))
@@ -1478,9 +1519,14 @@ static int __init _register(struct omap_hwmod *oh)
 
         oh->_state = _HWMOD_STATE_REGISTERED;
 
-        ret = 0;
+        /*
+         * XXX Rather than doing a strcmp(), this should test a flag
+         * set in the hwmod data, inserted by the autogenerator code.
+         */
+        if (!strcmp(oh->name, MPU_INITIATOR_NAME))
+                mpu_oh = oh;
 
-        return ret;
+        return 0;
 }
 
 
@@ -1583,38 +1629,30 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
         return ret;
 }
 
-
 /**
- * omap_hwmod_init - init omap_hwmod code and register hwmods
+ * omap_hwmod_register - register an array of hwmods
  * @ohs: pointer to an array of omap_hwmods to register
  *
  * Intended to be called early in boot before the clock framework is
  * initialized.  If @ohs is not null, will register all omap_hwmods
- * listed in @ohs that are valid for this chip.  Returns -EINVAL if
- * omap_hwmod_init() has already been called or 0 otherwise.
+ * listed in @ohs that are valid for this chip.  Returns 0.
  */
-int __init omap_hwmod_init(struct omap_hwmod **ohs)
+int __init omap_hwmod_register(struct omap_hwmod **ohs)
 {
-        struct omap_hwmod *oh;
-        int r;
-
-        if (inited)
-                return -EINVAL;
-
-        inited = 1;
+        int r, i;
 
         if (!ohs)
                 return 0;
 
-        oh = *ohs;
-        while (oh) {
-                if (omap_chip_is(oh->omap_chip)) {
-                        r = _register(oh);
-                        WARN(r, "omap_hwmod: %s: _register returned "
-                             "%d\n", oh->name, r);
-                }
-                oh = *++ohs;
-        }
+        i = 0;
+        do {
+                if (!omap_chip_is(ohs[i]->omap_chip))
+                        continue;
+
+                r = _register(ohs[i]);
+                WARN(r, "omap_hwmod: %s: _register returned %d\n", ohs[i]->name,
+                     r);
+        } while (ohs[++i]);
 
         return 0;
 }
@@ -1622,12 +1660,14 @@ int __init omap_hwmod_init(struct omap_hwmod **ohs)
 /*
  * _populate_mpu_rt_base - populate the virtual address for a hwmod
  *
- * Must be called only from omap_hwmod_late_init so ioremap works properly.
+ * Must be called only from omap_hwmod_setup_*() so ioremap works properly.
  * Assumes the caller takes care of locking if needed.
- *
  */
 static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
 {
+        if (oh->_state != _HWMOD_STATE_REGISTERED)
+                return 0;
+
         if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
                 return 0;
 
@@ -1640,31 +1680,81 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
 }
 
 /**
- * omap_hwmod_late_init - do some post-clock framework initialization
+ * omap_hwmod_setup_one - set up a single hwmod
+ * @oh_name: const char * name of the already-registered hwmod to set up
+ *
+ * Must be called after omap2_clk_init().  Resolves the struct clk
+ * names to struct clk pointers for each registered omap_hwmod.  Also
+ * calls _setup() on each hwmod.  Returns -EINVAL upon error or 0 upon
+ * success.
+ */
+int __init omap_hwmod_setup_one(const char *oh_name)
+{
+        struct omap_hwmod *oh;
+        int r;
+
+        pr_debug("omap_hwmod: %s: %s\n", oh_name, __func__);
+
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: cannot setup_one: MPU initiator hwmod %s not yet registered\n",
+                       oh_name, MPU_INITIATOR_NAME);
+                return -EINVAL;
+        }
+
+        oh = _lookup(oh_name);
+        if (!oh) {
+                WARN(1, "omap_hwmod: %s: hwmod not yet registered\n", oh_name);
+                return -EINVAL;
+        }
+
+        if (mpu_oh->_state == _HWMOD_STATE_REGISTERED && oh != mpu_oh)
+                omap_hwmod_setup_one(MPU_INITIATOR_NAME);
+
+        r = _populate_mpu_rt_base(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't set mpu_rt_base\n", oh_name);
+                return -EINVAL;
+        }
+
+        r = _init_clocks(oh, NULL);
+        if (IS_ERR_VALUE(r)) {
+                WARN(1, "omap_hwmod: %s: couldn't init clocks\n", oh_name);
+                return -EINVAL;
+        }
+
+        _setup(oh, NULL);
+
+        return 0;
+}
+
+/**
+ * omap_hwmod_setup - do some post-clock framework initialization
  *
  * Must be called after omap2_clk_init().  Resolves the struct clk names
  * to struct clk pointers for each registered omap_hwmod.  Also calls
- * _setup() on each hwmod.  Returns 0.
+ * _setup() on each hwmod.  Returns 0 upon success.
  */
-static int __init omap_hwmod_late_init(void)
+static int __init omap_hwmod_setup_all(void)
 {
         int r;
 
+        if (!mpu_oh) {
+                pr_err("omap_hwmod: %s: MPU initiator hwmod %s not yet registered\n",
+                       __func__, MPU_INITIATOR_NAME);
+                return -EINVAL;
+        }
+
         r = omap_hwmod_for_each(_populate_mpu_rt_base, NULL);
 
-        /* XXX check return value */
         r = omap_hwmod_for_each(_init_clocks, NULL);
-        WARN(r, "omap_hwmod: omap_hwmod_late_init(): _init_clocks failed\n");
-
-        mpu_oh = omap_hwmod_lookup(MPU_INITIATOR_NAME);
-        WARN(!mpu_oh, "omap_hwmod: could not find MPU initiator hwmod %s\n",
-             MPU_INITIATOR_NAME);
+        WARN(IS_ERR_VALUE(r),
+             "omap_hwmod: %s: _init_clocks failed\n", __func__);
 
         omap_hwmod_for_each(_setup, NULL);
 
         return 0;
 }
-core_initcall(omap_hwmod_late_init);
+core_initcall(omap_hwmod_setup_all);
 
 /**
  * omap_hwmod_enable - enable an omap_hwmod
@@ -1883,6 +1973,7 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
                 os = oh->slaves[i];
 
                 for (j = 0; j < os->addr_cnt; j++) {
+                        (res + r)->name = (os->addr + j)->name;
                         (res + r)->start = (os->addr + j)->pa_start;
                         (res + r)->end = (os->addr + j)->pa_end;
                         (res + r)->flags = IORESOURCE_MEM;
@@ -2183,11 +2274,11 @@ int omap_hwmod_for_each_by_class(const char *classname,
  * @oh: struct omap_hwmod *
  * @state: state that _setup() should leave the hwmod in
  *
- * Sets the hwmod state that @oh will enter at the end of _setup() (called by
- * omap_hwmod_late_init()).  Only valid to call between calls to
- * omap_hwmod_init() and omap_hwmod_late_init().  Returns 0 upon success or
- * -EINVAL if there is a problem with the arguments or if the hwmod is
- * in the wrong state.
+ * Sets the hwmod state that @oh will enter at the end of _setup()
+ * (called by omap_hwmod_setup_*()).  Only valid to call between
+ * calling omap_hwmod_register() and omap_hwmod_setup_*().  Returns
+ * 0 upon success or -EINVAL if there is a problem with the arguments
+ * or if the hwmod is in the wrong state.
  */
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state)
 {
@@ -2239,3 +2330,29 @@ u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh)
 
         return ret;
 }
+
+/**
+ * omap_hwmod_no_setup_reset - prevent a hwmod from being reset upon setup
+ * @oh: struct omap_hwmod *
+ *
+ * Prevent the hwmod @oh from being reset during the setup process.
+ * Intended for use by board-*.c files on boards with devices that
+ * cannot tolerate being reset.  Must be called before the hwmod has
+ * been set up.  Returns 0 upon success or negative error code upon
+ * failure.
+ */
+int omap_hwmod_no_setup_reset(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->_state != _HWMOD_STATE_REGISTERED) {
+                pr_err("omap_hwmod: %s: cannot prevent setup reset; in wrong state\n",
+                        oh->name);
+                return -EINVAL;
+        }
+
+        oh->flags |= HWMOD_INIT_NO_RESET;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index f323c6bb22de..61e58bd27aec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -19,6 +19,7 @@
 #include <plat/i2c.h>
 #include <plat/gpio.h>
 #include <plat/mcspi.h>
+#include <plat/dmtimer.h>
 #include <plat/l3_2xxx.h>
 #include <plat/l4_2xxx.h>
 
@@ -109,6 +110,8 @@ static struct omap_hwmod omap2420_uart2_hwmod;
 static struct omap_hwmod omap2420_uart3_hwmod;
 static struct omap_hwmod omap2420_i2c1_hwmod;
 static struct omap_hwmod omap2420_i2c2_hwmod;
+static struct omap_hwmod omap2420_mcbsp1_hwmod;
+static struct omap_hwmod omap2420_mcbsp2_hwmod;
 
 /* l4 core -> mcspi1 interface */
 static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
@@ -337,6 +340,625 @@ static struct omap_hwmod omap2420_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2420_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2420_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48028000,
+                .pa_end         = 0x48028000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
+        .master         = &omap2420_l4_wkup_hwmod,
+        .slave          = &omap2420_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2420_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
+        &omap2420_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2420_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2420_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer1_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2420_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2420_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
+        &omap2420_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2420_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2420_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer2_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2420_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2420_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
+        &omap2420_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2420_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2420_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer3_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2420_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2420_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
+        &omap2420_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2420_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2420_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer4_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2420_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2420_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
+        &omap2420_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2420_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2420_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer5_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+
+/* timer6 */
+static struct omap_hwmod omap2420_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2420_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
+        &omap2420_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2420_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2420_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer6_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2420_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2420_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
+        &omap2420_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2420_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2420_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer7_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2420_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2420_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
+        &omap2420_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2420_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2420_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer8_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2420_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2420_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
+        &omap2420_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2420_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2420_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer9_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2420_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2420_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
+        &omap2420_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2420_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2420_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer10_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2420_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2420_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
+        &omap2420_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2420_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2420_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer11_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2420_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2420_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
+        &omap2420_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2420_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2420_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2420_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_timer12_slaves),
+        .class          = &omap2420_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
         {
@@ -788,6 +1410,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
                         .flags  = OMAP_FIREWALL_L4,
                 }
         },
+        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1208,6 +1831,76 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap2420_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2420_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
+        { .name = "dsp", .irq = 26 },
+        { .name = "iva", .irq = 34 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mailbox_hwmod,
+        .addr           = omap2420_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
+        &omap2420_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2420_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2420_mailbox_hwmod_class,
+        .mpu_irqs       = omap2420_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/*
  * 'mcspi' class
  * multichannel serial port interface (mcspi) / master/slave synchronous serial
  * bus
@@ -1320,12 +2013,149 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 };
 
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2420_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mcbsp1_slaves[] = {
+        &omap2420_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap2420_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp1_irqs),
+        .sdma_reqs      = omap2420_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
+};
+
+static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
+        .master         = &omap2420_l4_core_hwmod,
+        .slave          = &omap2420_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2420_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2420_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap2420_mcbsp2_slaves[] = {
+        &omap2420_l4_core__mcbsp2,
+};
+
+static struct omap_hwmod omap2420_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2420_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2420_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2420_mcbsp2_irqs),
+        .sdma_reqs      = omap2420_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap2420_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2420_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         &omap2420_l3_main_hwmod,
         &omap2420_l4_core_hwmod,
         &omap2420_l4_wkup_hwmod,
         &omap2420_mpu_hwmod,
         &omap2420_iva_hwmod,
+
+        &omap2420_timer1_hwmod,
+        &omap2420_timer2_hwmod,
+        &omap2420_timer3_hwmod,
+        &omap2420_timer4_hwmod,
+        &omap2420_timer5_hwmod,
+        &omap2420_timer6_hwmod,
+        &omap2420_timer7_hwmod,
+        &omap2420_timer8_hwmod,
+        &omap2420_timer9_hwmod,
+        &omap2420_timer10_hwmod,
+        &omap2420_timer11_hwmod,
+        &omap2420_timer12_hwmod,
+
         &omap2420_wd_timer2_hwmod,
         &omap2420_uart1_hwmod,
         &omap2420_uart2_hwmod,
@@ -1348,6 +2178,13 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
         /* dma_system class*/
         &omap2420_dma_system_hwmod,
 
+        /* mailbox class */
+        &omap2420_mailbox_hwmod,
+
+        /* mcbsp class */
+        &omap2420_mcbsp1_hwmod,
+        &omap2420_mcbsp2_hwmod,
+
         /* mcspi class */
         &omap2420_mcspi1_hwmod,
         &omap2420_mcspi2_hwmod,
@@ -1356,5 +2193,5 @@ static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 
 int __init omap2420_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2420_hwmods);
+        return omap_hwmod_register(omap2420_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index de0015d38433..490789a6bed0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,10 @@
 #include <plat/serial.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
+#include <plat/mcbsp.h>
 #include <plat/mcspi.h>
+#include <plat/dmtimer.h>
+#include <plat/mmc.h>
 #include <plat/l3_2xxx.h>
 
 #include "omap_hwmod_common_data.h"
@@ -51,9 +54,16 @@ static struct omap_hwmod omap2430_gpio3_hwmod;
 static struct omap_hwmod omap2430_gpio4_hwmod;
 static struct omap_hwmod omap2430_gpio5_hwmod;
 static struct omap_hwmod omap2430_dma_system_hwmod;
+static struct omap_hwmod omap2430_mcbsp1_hwmod;
+static struct omap_hwmod omap2430_mcbsp2_hwmod;
+static struct omap_hwmod omap2430_mcbsp3_hwmod;
+static struct omap_hwmod omap2430_mcbsp4_hwmod;
+static struct omap_hwmod omap2430_mcbsp5_hwmod;
 static struct omap_hwmod omap2430_mcspi1_hwmod;
 static struct omap_hwmod omap2430_mcspi2_hwmod;
 static struct omap_hwmod omap2430_mcspi3_hwmod;
+static struct omap_hwmod omap2430_mmc1_hwmod;
+static struct omap_hwmod omap2430_mmc2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2430_l3_main__l4_core = {
@@ -250,6 +260,42 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
         &omap2430_l4_core__usbhsotg,
 };
 
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap2430_mmc1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mmc2_hwmod,
+        .addr           = omap2430_mmc2_addr_space,
+        .clk            = "mmchs2_ick",
+        .addr_cnt       = ARRAY_SIZE(omap2430_mmc2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
         &omap2430_l3_main__l4_core,
@@ -258,6 +304,8 @@ static struct omap_hwmod_ocp_if *omap2430_l4_core_slaves[] = {
 /* Master interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap2430_l4_core_masters[] = {
         &omap2430_l4_core__l4_wkup,
+        &omap2430_l4_core__mmc1,
+        &omap2430_l4_core__mmc2,
 };
 
 /* L4 CORE */
@@ -393,6 +441,624 @@ static struct omap_hwmod omap2430_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* Timer Common */
+static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap2430_timer_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap2430_timer1_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
+        {
+                .pa_start       = 0x49018000,
+                .pa_end         = 0x49018000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
+        .master         = &omap2430_l4_wkup_hwmod,
+        .slave          = &omap2430_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap2430_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
+        &omap2430_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap2430_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap2430_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer1_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap2430_timer2_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
+        {
+                .pa_start       = 0x4802a000,
+                .pa_end         = 0x4802a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap2430_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
+        &omap2430_l4_core__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap2430_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap2430_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer2_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap2430_timer3_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
+        {
+                .pa_start       = 0x48078000,
+                .pa_end         = 0x48078000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap2430_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
+        &omap2430_l4_core__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap2430_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap2430_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer3_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap2430_timer4_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
+        {
+                .pa_start       = 0x4807a000,
+                .pa_end         = 0x4807a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap2430_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
+        &omap2430_l4_core__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap2430_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap2430_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer4_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap2430_timer5_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
+        {
+                .pa_start       = 0x4807c000,
+                .pa_end         = 0x4807c000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap2430_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
+        &omap2430_l4_core__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap2430_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap2430_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer5_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap2430_timer6_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4807e000,
+                .pa_end         = 0x4807e000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer6 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap2430_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
+        &omap2430_l4_core__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap2430_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap2430_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT6_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer6_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap2430_timer7_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
+        {
+                .pa_start       = 0x48080000,
+                .pa_end         = 0x48080000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer7 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap2430_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
+        &omap2430_l4_core__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap2430_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap2430_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT7_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer7_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap2430_timer8_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
+        {
+                .pa_start       = 0x48082000,
+                .pa_end         = 0x48082000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer8 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap2430_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
+        &omap2430_l4_core__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap2430_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap2430_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT8_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer8_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap2430_timer9_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
+        {
+                .pa_start       = 0x48084000,
+                .pa_end         = 0x48084000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer9 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap2430_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
+        &omap2430_l4_core__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap2430_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap2430_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT9_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer9_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap2430_timer10_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap2430_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
+        &omap2430_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap2430_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap2430_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer10_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap2430_timer11_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap2430_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
+        &omap2430_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap2430_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap2430_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer11_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
+/* timer12 */
+static struct omap_hwmod omap2430_timer12_hwmod;
+static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
+        { .irq = 48, },
+};
+
+static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
+        {
+                .pa_start       = 0x4808a000,
+                .pa_end         = 0x4808a000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap2430_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
+        &omap2430_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap2430_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap2430_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_GPT12_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap2430_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_timer12_slaves),
+        .class          = &omap2430_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
         {
@@ -819,6 +1485,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
         .clk            = "dss_54m_fck",
         .addr           = omap2430_dss_venc_addrs,
         .addr_cnt       = ARRAY_SIZE(omap2430_dss_venc_addrs),
+        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1295,6 +1962,75 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
 };
 
 /*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap2430_mailbox_sysc,
+};
+
+/* mailbox */
+static struct omap_hwmod omap2430_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
+        { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mailbox_hwmod,
+        .addr           = omap2430_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
+        &omap2430_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap2430_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap2430_mailbox_hwmod_class,
+        .mpu_irqs       = omap2430_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/*
  * 'mcspi' class
  * multichannel serial port interface (mcspi) / master/slave synchronous serial
  * bus
@@ -1506,7 +2242,425 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2430_mcbsp_sysc = {
+        .rev_offs       = 0x007C,
+        .sysc_offs      = 0x008C,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
 
+static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+        .sysc = &omap2430_mcbsp_sysc,
+        .rev  = MCBSP_CONFIG_TYPE2,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
+        { .name = "tx",         .irq = 59 },
+        { .name = "rx",         .irq = 60 },
+        { .name = "ovr",        .irq = 61 },
+        { .name = "common",     .irq = 64 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap2430_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp1_slaves[] = {
+        &omap2430_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap2430_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp1_irqs),
+        .sdma_reqs      = omap2430_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
+        { .name = "tx",         .irq = 62 },
+        { .name = "rx",         .irq = 63 },
+        { .name = "common",     .irq = 16 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48076000,
+                .pa_end         = 0x480760ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap2430_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp2_slaves[] = {
+        &omap2430_l4_core__mcbsp2,
+};
+
+static struct omap_hwmod omap2430_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp2_irqs),
+        .sdma_reqs      = omap2430_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp2_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
+        { .name = "tx",         .irq = 89 },
+        { .name = "rx",         .irq = 90 },
+        { .name = "common",     .irq = 17 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808C000,
+                .pa_end         = 0x4808C0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap2430_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp3_slaves[] = {
+        &omap2430_l4_core__mcbsp3,
+};
+
+static struct omap_hwmod omap2430_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp3_irqs),
+        .sdma_reqs      = omap2430_mcbsp3_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp3_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
+        { .name = "tx",         .irq = 54 },
+        { .name = "rx",         .irq = 55 },
+        { .name = "common",     .irq = 18 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
+        { .name = "rx", .dma_req = 20 },
+        { .name = "tx", .dma_req = 19 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x4808E000,
+                .pa_end         = 0x4808E0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap2430_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp4_slaves[] = {
+        &omap2430_l4_core__mcbsp4,
+};
+
+static struct omap_hwmod omap2430_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp4_irqs),
+        .sdma_reqs      = omap2430_mcbsp4_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
+        { .name = "tx",         .irq = 81 },
+        { .name = "rx",         .irq = 82 },
+        { .name = "common",     .irq = 19 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
+        { .name = "rx", .dma_req = 22 },
+        { .name = "tx", .dma_req = 21 },
+};
+
+static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
+        .master         = &omap2430_l4_core_hwmod,
+        .slave          = &omap2430_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap2430_mcbsp5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap2430_mcbsp5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp5 slave ports */
+static struct omap_hwmod_ocp_if *omap2430_mcbsp5_slaves[] = {
+        &omap2430_l4_core__mcbsp5,
+};
+
+static struct omap_hwmod omap2430_mcbsp5_hwmod = {
+        .name           = "mcbsp5",
+        .class          = &omap2430_mcbsp_hwmod_class,
+        .mpu_irqs       = omap2430_mcbsp5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mcbsp5_irqs),
+        .sdma_reqs      = omap2430_mcbsp5_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
+        .main_clk       = "mcbsp5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mcbsp5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mcbsp5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig omap2430_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mmc_class = {
+        .name = "mmc",
+        .sysc = &omap2430_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
+        { .irq = 83 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
+        { .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb1_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc1_slaves[] = {
+        &omap2430_l4_core__mmc1,
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap2430_mmc1_hwmod = {
+        .name           = "mmc1",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
+        .opt_clks       = omap2430_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS1_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap2430_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc1_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* MMC/SD/SDIO2 */
+
+static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
+        { .irq = 86 },
+};
+
+static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
+        { .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+};
+
+static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
+        { .role = "dbck", .clk = "mmchsdb2_fck" },
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mmc2_slaves[] = {
+        &omap2430_l4_core__mmc2,
+};
+
+static struct omap_hwmod omap2430_mmc2_hwmod = {
+        .name           = "mmc2",
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
+        .mpu_irqs       = omap2430_mmc2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
+        .sdma_reqs      = omap2430_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
+        .opt_clks       = omap2430_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap2430_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 2,
+                        .module_bit  = OMAP2430_EN_MMCHS2_SHIFT,
+                        .idlest_reg_id = 2,
+                        .idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
+                },
+        },
+        .slaves         = omap2430_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap2430_mmc2_slaves),
+        .class          = &omap2430_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
 
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l3_main_hwmod,
@@ -1514,6 +2668,20 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         &omap2430_l4_wkup_hwmod,
         &omap2430_mpu_hwmod,
         &omap2430_iva_hwmod,
+
+        &omap2430_timer1_hwmod,
+        &omap2430_timer2_hwmod,
+        &omap2430_timer3_hwmod,
+        &omap2430_timer4_hwmod,
+        &omap2430_timer5_hwmod,
+        &omap2430_timer6_hwmod,
+        &omap2430_timer7_hwmod,
+        &omap2430_timer8_hwmod,
+        &omap2430_timer9_hwmod,
+        &omap2430_timer10_hwmod,
+        &omap2430_timer11_hwmod,
+        &omap2430_timer12_hwmod,
+
         &omap2430_wd_timer2_hwmod,
         &omap2430_uart1_hwmod,
         &omap2430_uart2_hwmod,
@@ -1526,6 +2694,8 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         /* i2c class */
         &omap2430_i2c1_hwmod,
         &omap2430_i2c2_hwmod,
+        &omap2430_mmc1_hwmod,
+        &omap2430_mmc2_hwmod,
 
         /* gpio class */
         &omap2430_gpio1_hwmod,
@@ -1537,6 +2707,16 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
         /* dma_system class*/
         &omap2430_dma_system_hwmod,
 
+        /* mcbsp class */
+        &omap2430_mcbsp1_hwmod,
+        &omap2430_mcbsp2_hwmod,
+        &omap2430_mcbsp3_hwmod,
+        &omap2430_mcbsp4_hwmod,
+        &omap2430_mcbsp5_hwmod,
+
+        /* mailbox class */
+        &omap2430_mailbox_hwmod,
+
         /* mcspi class */
         &omap2430_mcspi1_hwmod,
         &omap2430_mcspi2_hwmod,
@@ -1550,5 +2730,5 @@ static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 
 int __init omap2430_hwmod_init(void)
 {
-        return omap_hwmod_init(omap2430_hwmods);
+        return omap_hwmod_register(omap2430_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index e9d001228568..2e275cbcd654 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -22,8 +22,11 @@
 #include <plat/l4_3xxx.h>
 #include <plat/i2c.h>
 #include <plat/gpio.h>
+#include <plat/mmc.h>
 #include <plat/smartreflex.h>
+#include <plat/mcbsp.h>
 #include <plat/mcspi.h>
+#include <plat/dmtimer.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -68,10 +71,21 @@ static struct omap_hwmod omap34xx_mcspi1;
 static struct omap_hwmod omap34xx_mcspi2;
 static struct omap_hwmod omap34xx_mcspi3;
 static struct omap_hwmod omap34xx_mcspi4;
+static struct omap_hwmod omap3xxx_mmc1_hwmod;
+static struct omap_hwmod omap3xxx_mmc2_hwmod;
+static struct omap_hwmod omap3xxx_mmc3_hwmod;
 static struct omap_hwmod am35xx_usbhsotg_hwmod;
 
 static struct omap_hwmod omap3xxx_dma_system_hwmod;
 
+static struct omap_hwmod omap3xxx_mcbsp1_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp2_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp3_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp4_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp5_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod;
+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod;
+
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
         .master = &omap3xxx_l3_main_hwmod,
@@ -86,10 +100,26 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L3 taret configuration and error log registers */
+static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
+        { .irq = INT_34XX_L3_DBG_IRQ },
+        { .irq = INT_34XX_L3_APP_IRQ },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
+        {
+                .pa_start       = 0x68000000,
+                .pa_end         = 0x6800ffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
 /* MPU -> L3 interface */
 static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
-        .master = &omap3xxx_mpu_hwmod,
-        .slave  = &omap3xxx_l3_main_hwmod,
+        .master   = &omap3xxx_mpu_hwmod,
+        .slave    = &omap3xxx_l3_main_hwmod,
+        .addr     = omap3xxx_l3_main_addrs,
+        .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
         .user   = OCP_USER_MPU,
 };
 
@@ -121,6 +151,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
 static struct omap_hwmod omap3xxx_l3_main_hwmod = {
         .name           = "l3_main",
         .class          = &l3_hwmod_class,
+        .mpu_irqs       = omap3xxx_l3_main_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_l3_main_irqs),
         .masters        = omap3xxx_l3_main_masters,
         .masters_cnt    = ARRAY_SIZE(omap3xxx_l3_main_masters),
         .slaves         = omap3xxx_l3_main_slaves,
@@ -158,6 +190,63 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .user   = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L4 CORE -> MMC1 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
+        {
+                .pa_start       = 0x4809c000,
+                .pa_end         = 0x4809c1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc1_hwmod,
+        .clk            = "mmchs1_ick",
+        .addr           = omap3xxx_mmc1_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC2 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
+        {
+                .pa_start       = 0x480b4000,
+                .pa_end         = 0x480b41ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc2_hwmod,
+        .clk            = "mmchs2_ick",
+        .addr           = omap3xxx_mmc2_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
+/* L4 CORE -> MMC3 interface */
+static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
+        {
+                .pa_start       = 0x480ad000,
+                .pa_end         = 0x480ad1ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmc3_hwmod,
+        .clk            = "mmchs3_ick",
+        .addr           = omap3xxx_mmc3_addr_space,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+        .flags          = OMAP_FIREWALL_L4
+};
+
 /* L4 CORE -> UART1 interface */
 static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
         {
@@ -402,26 +491,12 @@ static struct omap_hwmod_ocp_if *am35xx_usbhsotg_slaves[] = {
 /* Slave interfaces on the L4_CORE interconnect */
 static struct omap_hwmod_ocp_if *omap3xxx_l4_core_slaves[] = {
         &omap3xxx_l3_main__l4_core,
-        &omap3_l4_core__sr1,
-        &omap3_l4_core__sr2,
-};
-
-/* Master interfaces on the L4_CORE interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_core_masters[] = {
-        &omap3xxx_l4_core__l4_wkup,
-        &omap3_l4_core__uart1,
-        &omap3_l4_core__uart2,
-        &omap3_l4_core__i2c1,
-        &omap3_l4_core__i2c2,
-        &omap3_l4_core__i2c3,
 };
 
 /* L4 CORE */
 static struct omap_hwmod omap3xxx_l4_core_hwmod = {
         .name           = "l4_core",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_core_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_core_masters),
         .slaves         = omap3xxx_l4_core_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_core_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -433,18 +508,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_per_slaves[] = {
         &omap3xxx_l3_main__l4_per,
 };
 
-/* Master interfaces on the L4_PER interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_per_masters[] = {
-        &omap3_l4_per__uart3,
-        &omap3_l4_per__uart4,
-};
-
 /* L4 PER */
 static struct omap_hwmod omap3xxx_l4_per_hwmod = {
         .name           = "l4_per",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_per_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_per_masters),
         .slaves         = omap3xxx_l4_per_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_per_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -456,16 +523,10 @@ static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_slaves[] = {
         &omap3xxx_l4_core__l4_wkup,
 };
 
-/* Master interfaces on the L4_WKUP interconnect */
-static struct omap_hwmod_ocp_if *omap3xxx_l4_wkup_masters[] = {
-};
-
 /* L4 WKUP */
 static struct omap_hwmod omap3xxx_l4_wkup_hwmod = {
         .name           = "l4_wkup",
         .class          = &l4_hwmod_class,
-        .masters        = omap3xxx_l4_wkup_masters,
-        .masters_cnt    = ARRAY_SIZE(omap3xxx_l4_wkup_masters),
         .slaves         = omap3xxx_l4_wkup_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_l4_wkup_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
@@ -515,6 +576,640 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* timer class */
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+                                SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                                SYSC_HAS_EMUFREE | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_1ms_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_1ms_sysc,
+        .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+static struct omap_hwmod_class_sysconfig omap3xxx_timer_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
+        .name = "timer",
+        .sysc = &omap3xxx_timer_sysc,
+        .rev =  OMAP_TIMER_IP_VERSION_1,
+};
+
+/* timer1 */
+static struct omap_hwmod omap3xxx_timer1_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
+        { .irq = 37, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
+        {
+                .pa_start       = 0x48318000,
+                .pa_end         = 0x48318000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_wkup -> timer1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
+        .master         = &omap3xxx_l4_wkup_hwmod,
+        .slave          = &omap3xxx_timer1_hwmod,
+        .clk            = "gpt1_ick",
+        .addr           = omap3xxx_timer1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer1 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
+        &omap3xxx_l4_wkup__timer1,
+};
+
+/* timer1 hwmod */
+static struct omap_hwmod omap3xxx_timer1_hwmod = {
+        .name           = "timer1",
+        .mpu_irqs       = omap3xxx_timer1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+        .main_clk       = "gpt1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT1_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer1_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer2 */
+static struct omap_hwmod omap3xxx_timer2_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
+        { .irq = 38, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
+        {
+                .pa_start       = 0x49032000,
+                .pa_end         = 0x49032000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer2_hwmod,
+        .clk            = "gpt2_ick",
+        .addr           = omap3xxx_timer2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer2 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
+        &omap3xxx_l4_per__timer2,
+};
+
+/* timer2 hwmod */
+static struct omap_hwmod omap3xxx_timer2_hwmod = {
+        .name           = "timer2",
+        .mpu_irqs       = omap3xxx_timer2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+        .main_clk       = "gpt2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer2_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer3 */
+static struct omap_hwmod omap3xxx_timer3_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
+        { .irq = 39, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
+        {
+                .pa_start       = 0x49034000,
+                .pa_end         = 0x49034000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer3_hwmod,
+        .clk            = "gpt3_ick",
+        .addr           = omap3xxx_timer3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer3 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
+        &omap3xxx_l4_per__timer3,
+};
+
+/* timer3 hwmod */
+static struct omap_hwmod omap3xxx_timer3_hwmod = {
+        .name           = "timer3",
+        .mpu_irqs       = omap3xxx_timer3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+        .main_clk       = "gpt3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer3_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer4 */
+static struct omap_hwmod omap3xxx_timer4_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
+        { .irq = 40, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
+        {
+                .pa_start       = 0x49036000,
+                .pa_end         = 0x49036000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer4_hwmod,
+        .clk            = "gpt4_ick",
+        .addr           = omap3xxx_timer4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer4 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
+        &omap3xxx_l4_per__timer4,
+};
+
+/* timer4 hwmod */
+static struct omap_hwmod omap3xxx_timer4_hwmod = {
+        .name           = "timer4",
+        .mpu_irqs       = omap3xxx_timer4_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+        .main_clk       = "gpt4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer4_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer5 */
+static struct omap_hwmod omap3xxx_timer5_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
+        { .irq = 41, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
+        {
+                .pa_start       = 0x49038000,
+                .pa_end         = 0x49038000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer5_hwmod,
+        .clk            = "gpt5_ick",
+        .addr           = omap3xxx_timer5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer5 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
+        &omap3xxx_l4_per__timer5,
+};
+
+/* timer5 hwmod */
+static struct omap_hwmod omap3xxx_timer5_hwmod = {
+        .name           = "timer5",
+        .mpu_irqs       = omap3xxx_timer5_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+        .main_clk       = "gpt5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT5_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer5_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer6 */
+static struct omap_hwmod omap3xxx_timer6_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
+        { .irq = 42, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
+        {
+                .pa_start       = 0x4903A000,
+                .pa_end         = 0x4903A000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer6 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer6_hwmod,
+        .clk            = "gpt6_ick",
+        .addr           = omap3xxx_timer6_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer6_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer6 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
+        &omap3xxx_l4_per__timer6,
+};
+
+/* timer6 hwmod */
+static struct omap_hwmod omap3xxx_timer6_hwmod = {
+        .name           = "timer6",
+        .mpu_irqs       = omap3xxx_timer6_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+        .main_clk       = "gpt6_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT6_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer6_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer6_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer7 */
+static struct omap_hwmod omap3xxx_timer7_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
+        { .irq = 43, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
+        {
+                .pa_start       = 0x4903C000,
+                .pa_end         = 0x4903C000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer7 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer7_hwmod,
+        .clk            = "gpt7_ick",
+        .addr           = omap3xxx_timer7_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer7_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer7 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
+        &omap3xxx_l4_per__timer7,
+};
+
+/* timer7 hwmod */
+static struct omap_hwmod omap3xxx_timer7_hwmod = {
+        .name           = "timer7",
+        .mpu_irqs       = omap3xxx_timer7_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+        .main_clk       = "gpt7_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT7_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer7_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer7_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer8 */
+static struct omap_hwmod omap3xxx_timer8_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
+        { .irq = 44, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
+        {
+                .pa_start       = 0x4903E000,
+                .pa_end         = 0x4903E000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer8 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer8_hwmod,
+        .clk            = "gpt8_ick",
+        .addr           = omap3xxx_timer8_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer8_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer8 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
+        &omap3xxx_l4_per__timer8,
+};
+
+/* timer8 hwmod */
+static struct omap_hwmod omap3xxx_timer8_hwmod = {
+        .name           = "timer8",
+        .mpu_irqs       = omap3xxx_timer8_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+        .main_clk       = "gpt8_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT8_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer8_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer8_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer9 */
+static struct omap_hwmod omap3xxx_timer9_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
+        { .irq = 45, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
+        {
+                .pa_start       = 0x49040000,
+                .pa_end         = 0x49040000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> timer9 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_timer9_hwmod,
+        .clk            = "gpt9_ick",
+        .addr           = omap3xxx_timer9_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer9_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer9 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
+        &omap3xxx_l4_per__timer9,
+};
+
+/* timer9 hwmod */
+static struct omap_hwmod omap3xxx_timer9_hwmod = {
+        .name           = "timer9",
+        .mpu_irqs       = omap3xxx_timer9_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+        .main_clk       = "gpt9_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT9_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer9_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer9_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer10 */
+static struct omap_hwmod omap3xxx_timer10_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
+        { .irq = 46, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
+        {
+                .pa_start       = 0x48086000,
+                .pa_end         = 0x48086000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer10 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer10_hwmod,
+        .clk            = "gpt10_ick",
+        .addr           = omap3xxx_timer10_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer10_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer10 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
+        &omap3xxx_l4_core__timer10,
+};
+
+/* timer10 hwmod */
+static struct omap_hwmod omap3xxx_timer10_hwmod = {
+        .name           = "timer10",
+        .mpu_irqs       = omap3xxx_timer10_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+        .main_clk       = "gpt10_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT10_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer10_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer10_slaves),
+        .class          = &omap3xxx_timer_1ms_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer11 */
+static struct omap_hwmod omap3xxx_timer11_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
+        { .irq = 47, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
+        {
+                .pa_start       = 0x48088000,
+                .pa_end         = 0x48088000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer11 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer11_hwmod,
+        .clk            = "gpt11_ick",
+        .addr           = omap3xxx_timer11_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer11_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer11 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
+        &omap3xxx_l4_core__timer11,
+};
+
+/* timer11 hwmod */
+static struct omap_hwmod omap3xxx_timer11_hwmod = {
+        .name           = "timer11",
+        .mpu_irqs       = omap3xxx_timer11_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+        .main_clk       = "gpt11_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT11_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer11_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer11_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
+/* timer12*/
+static struct omap_hwmod omap3xxx_timer12_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
+        { .irq = 95, },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
+        {
+                .pa_start       = 0x48304000,
+                .pa_end         = 0x48304000 + SZ_1K - 1,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> timer12 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_timer12_hwmod,
+        .clk            = "gpt12_ick",
+        .addr           = omap3xxx_timer12_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_timer12_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* timer12 slave port */
+static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
+        &omap3xxx_l4_core__timer12,
+};
+
+/* timer12 hwmod */
+static struct omap_hwmod omap3xxx_timer12_hwmod = {
+        .name           = "timer12",
+        .mpu_irqs       = omap3xxx_timer12_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
+        .main_clk       = "gpt12_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_GPT12_SHIFT,
+                        .module_offs = WKUP_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_timer12_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_timer12_slaves),
+        .class          = &omap3xxx_timer_hwmod_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
+};
+
 /* l4_wkup -> wd_timer2 */
 static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
         {
@@ -589,6 +1284,11 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
         .slaves         = omap3xxx_wd_timer2_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap3xxx_wd_timer2_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+        /*
+         * XXX: Use software supervised mode, HW supervised smartidle seems to
+         * block CORE power domain idle transitions. Maybe a HW bug in wdt2?
+         */
+        .flags          = HWMOD_SWSUP_SIDLE,
 };
 
 /* UART common */
@@ -1139,6 +1839,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
                         .flags  = OMAP_FIREWALL_L4,
                 }
         },
+        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -1729,6 +2430,437 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
         .flags          = HWMOD_NO_IDLEST,
 };
 
+/*
+ * 'mcbsp' class
+ * multi channel buffered serial port controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sysc = {
+        .sysc_offs      = 0x008c,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
+                           SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+        .clockact       = 0x2,
+};
+
+static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
+        .name = "mcbsp",
+        .sysc = &omap3xxx_mcbsp_sysc,
+        .rev  = MCBSP_CONFIG_TYPE3,
+};
+
+/* mcbsp1 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
+        { .name = "irq", .irq = 16 },
+        { .name = "tx", .irq = 59 },
+        { .name = "rx", .irq = 60 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
+        { .name = "rx", .dma_req = 32 },
+        { .name = "tx", .dma_req = 31 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48074000,
+                .pa_end         = 0x480740ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp1 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp1_hwmod,
+        .clk            = "mcbsp1_ick",
+        .addr           = omap3xxx_mcbsp1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp1 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp1_slaves[] = {
+        &omap3xxx_l4_core__mcbsp1,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
+        .name           = "mcbsp1",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp1_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp1_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+        .main_clk       = "mcbsp1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp1_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp2 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
+        { .name = "irq", .irq = 17 },
+        { .name = "tx", .irq = 62 },
+        { .name = "rx", .irq = 63 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
+        { .name = "rx", .dma_req = 34 },
+        { .name = "tx", .dma_req = 33 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49022000,
+                .pa_end         = 0x490220ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp2 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp2 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_slaves[] = {
+        &omap3xxx_l4_per__mcbsp2,
+};
+
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp2_dev_attr = {
+        .sidetone       = "mcbsp2_sidetone",
+};
+
+static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
+        .name           = "mcbsp2",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp2_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp2_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_slaves),
+        .dev_attr       = &omap34xx_mcbsp2_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp3 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
+        { .name = "irq", .irq = 22 },
+        { .name = "tx", .irq = 89 },
+        { .name = "rx", .irq = 90 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
+        { .name = "rx", .dma_req = 18 },
+        { .name = "tx", .dma_req = 17 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49024000,
+                .pa_end         = 0x490240ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp3 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp3 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_slaves[] = {
+        &omap3xxx_l4_per__mcbsp3,
+};
+
+static struct omap_mcbsp_dev_attr omap34xx_mcbsp3_dev_attr = {
+        .sidetone       = "mcbsp3_sidetone",
+};
+
+static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
+        .name           = "mcbsp3",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp3_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp3_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_slaves),
+        .dev_attr       = &omap34xx_mcbsp3_dev_attr,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp4 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
+        { .name = "irq", .irq = 23 },
+        { .name = "tx", .irq = 54 },
+        { .name = "rx", .irq = 55 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
+        { .name = "rx", .dma_req = 20 },
+        { .name = "tx", .dma_req = 19 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x49026000,
+                .pa_end         = 0x490260ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp4 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp4_hwmod,
+        .clk            = "mcbsp4_ick",
+        .addr           = omap3xxx_mcbsp4_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp4 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp4_slaves[] = {
+        &omap3xxx_l4_per__mcbsp4,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
+        .name           = "mcbsp4",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp4_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp4_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
+        .main_clk       = "mcbsp4_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp4_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp4_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp5 */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
+        { .name = "irq", .irq = 27 },
+        { .name = "tx", .irq = 81 },
+        { .name = "rx", .irq = 82 },
+};
+
+static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
+        { .name = "rx", .dma_req = 22 },
+        { .name = "tx", .dma_req = 21 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
+        {
+                .name           = "mpu",
+                .pa_start       = 0x48096000,
+                .pa_end         = 0x480960ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_core -> mcbsp5 */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mcbsp5_hwmod,
+        .clk            = "mcbsp5_ick",
+        .addr           = omap3xxx_mcbsp5_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcbsp5 slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp5_slaves[] = {
+        &omap3xxx_l4_core__mcbsp5,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
+        .name           = "mcbsp5",
+        .class          = &omap3xxx_mcbsp_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp5_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
+        .sdma_reqs      = omap3xxx_mcbsp5_sdma_chs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
+        .main_clk       = "mcbsp5_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp5_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp5_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+/* 'mcbsp sidetone' class */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mcbsp_sidetone_sysc = {
+        .sysc_offs      = 0x0010,
+        .sysc_flags     = SYSC_HAS_AUTOIDLE,
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
+        .name = "mcbsp_sidetone",
+        .sysc = &omap3xxx_mcbsp_sidetone_sysc,
+};
+
+/* mcbsp2_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
+        { .name = "irq", .irq = 4 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x49028000,
+                .pa_end         = 0x490280ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp2_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp2_sidetone_hwmod,
+        .clk            = "mcbsp2_ick",
+        .addr           = omap3xxx_mcbsp2_sidetone_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* mcbsp2_sidetone slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp2_sidetone_slaves[] = {
+        &omap3xxx_l4_per__mcbsp2_sidetone,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
+        .name           = "mcbsp2_sidetone",
+        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp2_sidetone_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
+        .main_clk       = "mcbsp2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                         .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp2_sidetone_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* mcbsp3_sidetone */
+static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
+        { .name = "irq", .irq = 5 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
+        {
+                .name           = "sidetone",
+                .pa_start       = 0x4902A000,
+                .pa_end         = 0x4902A0ff,
+                .flags          = ADDR_TYPE_RT
+        },
+};
+
+/* l4_per -> mcbsp3_sidetone */
+static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
+        .master         = &omap3xxx_l4_per_hwmod,
+        .slave          = &omap3xxx_mcbsp3_sidetone_hwmod,
+        .clk            = "mcbsp3_ick",
+        .addr           = omap3xxx_mcbsp3_sidetone_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
+        .user           = OCP_USER_MPU,
+};
+
+/* mcbsp3_sidetone slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mcbsp3_sidetone_slaves[] = {
+        &omap3xxx_l4_per__mcbsp3_sidetone,
+};
+
+static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
+        .name           = "mcbsp3_sidetone",
+        .class          = &omap3xxx_mcbsp_sidetone_hwmod_class,
+        .mpu_irqs       = omap3xxx_mcbsp3_sidetone_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
+        .main_clk       = "mcbsp3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
+                        .module_offs = OMAP3430_PER_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mcbsp3_sidetone_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+
 /* SR common */
 static struct omap_hwmod_sysc_fields omap34xx_sr_sysc_fields = {
         .clkact_shift   = 20,
@@ -1858,6 +2990,74 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
 };
 
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_mailbox_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                                SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
+        .name = "mailbox",
+        .sysc = &omap3xxx_mailbox_sysc,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
+        { .irq = 26 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
+        {
+                .pa_start       = 0x48094000,
+                .pa_end         = 0x480941ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
+/* l4_core -> mailbox */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mailbox_hwmod,
+        .addr           = omap3xxx_mailbox_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap3xxx_mailbox_addrs),
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mailbox slave ports */
+static struct omap_hwmod_ocp_if *omap3xxx_mailbox_slaves[] = {
+        &omap3xxx_l4_core__mailbox,
+};
+
+static struct omap_hwmod omap3xxx_mailbox_hwmod = {
+        .name           = "mailbox",
+        .class          = &omap3xxx_mailbox_hwmod_class,
+        .mpu_irqs       = omap3xxx_mailbox_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap3xxx_mailbox_irqs),
+        .main_clk       = "mailboxes_ick",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
+                        .module_offs = CORE_MOD,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mailbox_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mailbox_slaves),
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 /* l4 core -> mcspi1 interface */
 static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
         {
@@ -2212,13 +3412,181 @@ static struct omap_hwmod am35xx_usbhsotg_hwmod = {
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES3_1)
 };
 
+/* MMC/SD/SDIO common */
+
+static struct omap_hwmod_class_sysconfig omap34xx_mmc_sysc = {
+        .rev_offs       = 0x1fc,
+        .sysc_offs      = 0x10,
+        .syss_offs      = 0x14,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+                           SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_mmc_class = {
+        .name = "mmc",
+        .sysc = &omap34xx_mmc_sysc,
+};
+
+/* MMC/SD/SDIO1 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
+        { .irq = 83, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 61, },
+        { .name = "rx", .dma_req = 62, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc1_slaves[] = {
+        &omap3xxx_l4_core__mmc1,
+};
+
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
+static struct omap_hwmod omap3xxx_mmc1_hwmod = {
+        .name           = "mmc1",
+        .mpu_irqs       = omap34xx_mmc1_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc1_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
+        .opt_clks       = omap34xx_mmc1_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
+        .main_clk       = "mmchs1_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC1_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
+                },
+        },
+        .dev_attr       = &mmc1_dev_attr,
+        .slaves         = omap3xxx_mmc1_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc1_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* MMC/SD/SDIO2 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
+        { .irq = INT_24XX_MMC2_IRQ, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 47, },
+        { .name = "rx", .dma_req = 48, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
+        &omap3xxx_l4_core__mmc2,
+};
+
+static struct omap_hwmod omap3xxx_mmc2_hwmod = {
+        .name           = "mmc2",
+        .mpu_irqs       = omap34xx_mmc2_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc2_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
+        .opt_clks       = omap34xx_mmc2_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
+        .main_clk       = "mmchs2_fck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC2_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mmc2_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc2_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* MMC/SD/SDIO3 */
+
+static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
+        { .irq = 94, },
+};
+
+static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
+        { .name = "tx", .dma_req = 77, },
+        { .name = "rx", .dma_req = 78, },
+};
+
+static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
+        { .role = "dbck", .clk = "omap_32k_fck", },
+};
+
+static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
+        &omap3xxx_l4_core__mmc3,
+};
+
+static struct omap_hwmod omap3xxx_mmc3_hwmod = {
+        .name           = "mmc3",
+        .mpu_irqs       = omap34xx_mmc3_mpu_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
+        .sdma_reqs      = omap34xx_mmc3_sdma_reqs,
+        .sdma_reqs_cnt  = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
+        .opt_clks       = omap34xx_mmc3_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
+        .main_clk       = "mmchs3_fck",
+        .prcm           = {
+                .omap2 = {
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_MMC3_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
+                },
+        },
+        .slaves         = omap3xxx_mmc3_slaves,
+        .slaves_cnt     = ARRAY_SIZE(omap3xxx_mmc3_slaves),
+        .class          = &omap34xx_mmc_class,
+        .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         &omap3xxx_l3_main_hwmod,
         &omap3xxx_l4_core_hwmod,
         &omap3xxx_l4_per_hwmod,
         &omap3xxx_l4_wkup_hwmod,
+        &omap3xxx_mmc1_hwmod,
+        &omap3xxx_mmc2_hwmod,
+        &omap3xxx_mmc3_hwmod,
         &omap3xxx_mpu_hwmod,
         &omap3xxx_iva_hwmod,
+
+        &omap3xxx_timer1_hwmod,
+        &omap3xxx_timer2_hwmod,
+        &omap3xxx_timer3_hwmod,
+        &omap3xxx_timer4_hwmod,
+        &omap3xxx_timer5_hwmod,
+        &omap3xxx_timer6_hwmod,
+        &omap3xxx_timer7_hwmod,
+        &omap3xxx_timer8_hwmod,
+        &omap3xxx_timer9_hwmod,
+        &omap3xxx_timer10_hwmod,
+        &omap3xxx_timer11_hwmod,
+        &omap3xxx_timer12_hwmod,
+
         &omap3xxx_wd_timer2_hwmod,
         &omap3xxx_uart1_hwmod,
         &omap3xxx_uart2_hwmod,
@@ -2253,6 +3621,18 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
         /* dma_system class*/
         &omap3xxx_dma_system_hwmod,
 
+        /* mcbsp class */
+        &omap3xxx_mcbsp1_hwmod,
+        &omap3xxx_mcbsp2_hwmod,
+        &omap3xxx_mcbsp3_hwmod,
+        &omap3xxx_mcbsp4_hwmod,
+        &omap3xxx_mcbsp5_hwmod,
+        &omap3xxx_mcbsp2_sidetone_hwmod,
+        &omap3xxx_mcbsp3_sidetone_hwmod,
+
+        /* mailbox class */
+        &omap3xxx_mailbox_hwmod,
+
         /* mcspi class */
         &omap34xx_mcspi1,
         &omap34xx_mcspi2,
@@ -2270,5 +3650,5 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 
 int __init omap3xxx_hwmod_init(void)
 {
-        return omap_hwmod_init(omap3xxx_hwmods);
+        return omap_hwmod_register(omap3xxx_hwmods);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 79a860178913..3e88dd3f8ef3 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -25,6 +25,8 @@
 #include <plat/gpio.h>
 #include <plat/dma.h>
 #include <plat/mcspi.h>
+#include <plat/mcbsp.h>
+#include <plat/mmc.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -262,11 +264,27 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* L3 target configuration and error log registers */
+static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
+        { .irq = 9  + OMAP44XX_IRQ_GIC_START },
+        { .irq = 10 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
+        {
+                .pa_start       = 0x44000000,
+                .pa_end         = 0x44000fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
 /* mpu -> l3_main_1 */
 static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
         .master         = &omap44xx_mpu_hwmod,
         .slave          = &omap44xx_l3_main_1_hwmod,
         .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_1_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -284,6 +302,8 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
 static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
         .name           = "l3_main_1",
         .class          = &omap44xx_l3_hwmod_class,
+        .mpu_irqs       = omap44xx_l3_targ_irqs,
+        .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_l3_targ_irqs),
         .slaves         = omap44xx_l3_main_1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -330,11 +350,21 @@ static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
+        {
+                .pa_start       = 0x44800000,
+                .pa_end         = 0x44801fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
 /* l3_main_1 -> l3_main_2 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
         .master         = &omap44xx_l3_main_1_hwmod,
         .slave          = &omap44xx_l3_main_2_hwmod,
         .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_2_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -375,11 +405,21 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 };
 
 /* l3_main_3 interface data */
+static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
+        {
+                .pa_start       = 0x45000000,
+                .pa_end         = 0x45000fff,
+                .flags          = ADDR_TYPE_RT,
+        },
+};
+
 /* l3_main_1 -> l3_main_3 */
 static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
         .master         = &omap44xx_l3_main_1_hwmod,
         .slave          = &omap44xx_l3_main_3_hwmod,
         .clk            = "l3_div_ck",
+        .addr           = omap44xx_l3_main_3_addrs,
+        .addr_cnt       = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -2737,6 +2777,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
 static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
         .name   = "mcbsp",
         .sysc   = &omap44xx_mcbsp_sysc,
+        .rev    = MCBSP_CONFIG_TYPE4,
 };
 
 /* mcbsp1 */
@@ -2752,6 +2793,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
         {
+                .name           = "mpu",
                 .pa_start       = 0x40122000,
                 .pa_end         = 0x401220ff,
                 .flags          = ADDR_TYPE_RT
@@ -2770,6 +2812,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
         {
+                .name           = "dma",
                 .pa_start       = 0x49022000,
                 .pa_end         = 0x490220ff,
                 .flags          = ADDR_TYPE_RT
@@ -2823,6 +2866,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
         {
+                .name           = "mpu",
                 .pa_start       = 0x40124000,
                 .pa_end         = 0x401240ff,
                 .flags          = ADDR_TYPE_RT
@@ -2841,6 +2885,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
         {
+                .name           = "dma",
                 .pa_start       = 0x49024000,
                 .pa_end         = 0x490240ff,
                 .flags          = ADDR_TYPE_RT
@@ -2894,6 +2939,7 @@ static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
         {
+                .name           = "mpu",
                 .pa_start       = 0x40126000,
                 .pa_end         = 0x401260ff,
                 .flags          = ADDR_TYPE_RT
@@ -2912,6 +2958,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
 
 static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
         {
+                .name           = "dma",
                 .pa_start       = 0x49026000,
                 .pa_end         = 0x490260ff,
                 .flags          = ADDR_TYPE_RT
@@ -3383,6 +3430,7 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
 };
 
 /* mmc1 */
+
 static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
         { .irq = 83 + OMAP44XX_IRQ_GIC_START },
 };
@@ -3420,6 +3468,11 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc1_slaves[] = {
         &omap44xx_l4_per__mmc1,
 };
 
+/* mmc1 dev_attr */
+static struct omap_mmc_dev_attr mmc1_dev_attr = {
+        .flags  = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
+};
+
 static struct omap_hwmod omap44xx_mmc1_hwmod = {
         .name           = "mmc1",
         .class          = &omap44xx_mmc_hwmod_class,
@@ -3433,6 +3486,7 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
                         .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
                 },
         },
+        .dev_attr       = &mmc1_dev_attr,
         .slaves         = omap44xx_mmc1_slaves,
         .slaves_cnt     = ARRAY_SIZE(omap44xx_mmc1_slaves),
         .masters        = omap44xx_mmc1_masters,
@@ -3989,7 +4043,6 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
 static struct omap_hwmod omap44xx_timer1_hwmod = {
         .name           = "timer1",
         .class          = &omap44xx_timer_1ms_hwmod_class,
-        .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_timer1_irqs,
         .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_timer1_irqs),
         .main_clk       = "timer1_fck",
@@ -5077,11 +5130,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
         &omap44xx_mcspi4_hwmod,
 
         /* mmc class */
-/*      &omap44xx_mmc1_hwmod, */
-/*      &omap44xx_mmc2_hwmod, */
-/*      &omap44xx_mmc3_hwmod, */
-/*      &omap44xx_mmc4_hwmod, */
-/*      &omap44xx_mmc5_hwmod, */
+        &omap44xx_mmc1_hwmod,
+        &omap44xx_mmc2_hwmod,
+        &omap44xx_mmc3_hwmod,
+        &omap44xx_mmc4_hwmod,
+        &omap44xx_mmc5_hwmod,
 
         /* mpu class */
         &omap44xx_mpu_hwmod,
@@ -5125,6 +5178,6 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 int __init omap44xx_hwmod_init(void)
 {
-        return omap_hwmod_init(omap44xx_hwmods);
+        return omap_hwmod_register(omap44xx_hwmods);
 }
 
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c
new file mode 100644
index 000000000000..82632c24076f
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.c
@@ -0,0 +1,253 @@
+/*
+  * OMAP4XXX L3 Interconnect error handling driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+#include "omap_l3_noc.h"
+
+/*
+ * Interrupt Handler for L3 error detection.
+ *      1) Identify the L3 clockdomain partition to which the error belongs to.
+ *      2) Identify the slave where the error information is logged
+ *      3) Print the logged information.
+ *      4) Add dump stack to provide kernel trace.
+ *
+ * Two Types of errors :
+ *      1) Custom errors in L3 :
+ *              Target like DMM/FW/EMIF generates SRESP=ERR error
+ *      2) Standard L3 error:
+ *              - Unsupported CMD.
+ *                      L3 tries to access target while it is idle
+ *              - OCP disconnect.
+ *              - Address hole error:
+ *                      If DSS/ISS/FDIF/USBHOSTFS access a target where they
+ *                      do not have connectivity, the error is logged in
+ *                      their default target which is DMM2.
+ *
+ *      On High Secure devices, firewall errors are possible and those
+ *      can be trapped as well. But the trapping is implemented as part
+ *      secure software and hence need not be implemented here.
+ */
+static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
+{
+
+        struct omap4_l3         *l3 = _l3;
+        int inttype, i, j;
+        int err_src = 0;
+        u32 std_err_main_addr, std_err_main, err_reg;
+        u32 base, slave_addr, clear;
+        char *source_name;
+
+        /* Get the Type of interrupt */
+        if (irq == l3->app_irq)
+                inttype = L3_APPLICATION_ERROR;
+        else
+                inttype = L3_DEBUG_ERROR;
+
+        for (i = 0; i < L3_MODULES; i++) {
+                /*
+                 * Read the regerr register of the clock domain
+                 * to determine the source
+                 */
+                base = (u32)l3->l3_base[i];
+                err_reg =  readl(base + l3_flagmux[i] + (inttype << 3));
+
+                /* Get the corresponding error and analyse */
+                if (err_reg) {
+                        /* Identify the source from control status register */
+                        for (j = 0; !(err_reg & (1 << j)); j++)
+                                                                        ;
+
+                        err_src = j;
+                        /* Read the stderrlog_main_source from clk domain */
+                        std_err_main_addr = base + (*(l3_targ[i] + err_src));
+                        std_err_main =  readl(std_err_main_addr);
+
+                        switch ((std_err_main & CUSTOM_ERROR)) {
+                        case STANDARD_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+
+                                slave_addr = std_err_main_addr +
+                                                L3_SLAVE_ADDRESS_OFFSET;
+                                WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n",
+                                        source_name, readl(slave_addr));
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+
+                        case CUSTOM_ERROR:
+                                source_name =
+                                l3_targ_stderrlog_main_name[i][err_src];
+
+                                WARN(true, "CUSTOM SRESP error with SOURCE:%s\n",
+                                                        source_name);
+                                /* clear the std error log*/
+                                clear = std_err_main | CLEAR_STDERR_LOG;
+                                writel(clear, std_err_main_addr);
+                                break;
+
+                        default:
+                                /* Nothing to be handled here as of now */
+                                break;
+                        }
+                /* Error found so break the for loop */
+                break;
+                }
+        }
+        return IRQ_HANDLED;
+}
+
+static int __init omap4_l3_probe(struct platform_device *pdev)
+{
+        static struct omap4_l3          *l3;
+        struct resource         *res;
+        int                     ret;
+        int                     irq;
+
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3)
+                ret = -ENOMEM;
+
+        platform_set_drvdata(pdev, l3);
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 0\n");
+                ret = -ENODEV;
+                goto err1;
+        }
+
+        l3->l3_base[0] = ioremap(res->start, resource_size(res));
+        if (!(l3->l3_base[0])) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 1\n");
+                ret = -ENODEV;
+                goto err3;
+        }
+
+        l3->l3_base[1] = ioremap(res->start, resource_size(res));
+        if (!(l3->l3_base[1])) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err4;
+        }
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource 2\n");
+                ret = -ENODEV;
+                goto err5;
+        }
+
+        l3->l3_base[2] = ioremap(res->start, resource_size(res));
+        if (!(l3->l3_base[2])) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err6;
+        }
+
+        /*
+         * Setup interrupt Handlers
+         */
+        irq = platform_get_irq(pdev, 0);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-dbg-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_DBG);
+                goto err7;
+        }
+        l3->debug_irq = irq;
+
+        irq = platform_get_irq(pdev, 1);
+        ret = request_irq(irq,
+                        l3_interrupt_handler,
+                        IRQF_DISABLED, "l3-app-irq", l3);
+        if (ret) {
+                pr_crit("L3: request_irq failed to register for 0x%x\n",
+                                         OMAP44XX_IRQ_L3_APP);
+                goto err8;
+        }
+        l3->app_irq = irq;
+
+        goto err0;
+err8:
+err7:
+        iounmap(l3->l3_base[2]);
+err6:
+err5:
+        iounmap(l3->l3_base[1]);
+err4:
+err3:
+        iounmap(l3->l3_base[0]);
+err2:
+err1:
+        kfree(l3);
+err0:
+        return ret;
+}
+
+static int __exit omap4_l3_remove(struct platform_device *pdev)
+{
+        struct omap4_l3         *l3 = platform_get_drvdata(pdev);
+
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->l3_base[0]);
+        iounmap(l3->l3_base[1]);
+        iounmap(l3->l3_base[2]);
+        kfree(l3);
+
+        return 0;
+}
+
+static struct platform_driver omap4_l3_driver = {
+        .remove         = __exit_p(omap4_l3_remove),
+        .driver         = {
+        .name           = "omap_l3_noc",
+        },
+};
+
+static int __init omap4_l3_init(void)
+{
+        return platform_driver_probe(&omap4_l3_driver, omap4_l3_probe);
+}
+postcore_initcall_sync(omap4_l3_init);
+
+static void __exit omap4_l3_exit(void)
+{
+        platform_driver_unregister(&omap4_l3_driver);
+}
+module_exit(omap4_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h
new file mode 100644
index 000000000000..359b83348aed
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_noc.h
@@ -0,0 +1,132 @@
+ /*
+  * OMAP4XXX L3 Interconnect  error handling driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+
+/*
+ * L3 register offsets
+ */
+#define L3_MODULES                      3
+#define CLEAR_STDERR_LOG                (1 << 31)
+#define CUSTOM_ERROR                    0x2
+#define STANDARD_ERROR                  0x0
+#define INBAND_ERROR                    0x0
+#define EMIF_KERRLOG_OFFSET             0x10
+#define L3_SLAVE_ADDRESS_OFFSET         0x14
+#define LOGICAL_ADDR_ERRORLOG           0x4
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+
+u32 l3_flagmux[L3_MODULES] = {
+        0x50C,
+        0x100C,
+        0X020C
+};
+
+/*
+ * L3 Target standard Error register offsets
+ */
+u32 l3_targ_stderrlog_main_clk1[] = {
+        0x148, /* DMM1 */
+        0x248, /* DMM2 */
+        0x348, /* ABE */
+        0x448, /* L4CFG */
+        0x648  /* CLK2 PWR DISC */
+};
+
+u32 l3_targ_stderrlog_main_clk2[] = {
+        0x548,          /* CORTEX M3 */
+        0x348,          /* DSS */
+        0x148,          /* GPMC */
+        0x448,          /* ISS */
+        0x748,          /* IVAHD */
+        0xD48,          /* missing in TRM  corresponds to AES1*/
+        0x948,          /* L4 PER0*/
+        0x248,          /* OCMRAM */
+        0x148,          /* missing in TRM corresponds to GPMC sERROR*/
+        0x648,          /* SGX */
+        0x848,          /* SL2 */
+        0x1648,         /* C2C */
+        0x1148,         /* missing in TRM corresponds PWR DISC CLK1*/
+        0xF48,          /* missing in TRM corrsponds to SHA1*/
+        0xE48,          /* missing in TRM corresponds to AES2*/
+        0xC48,          /* L4 PER3 */
+        0xA48,          /* L4 PER1*/
+        0xB48           /* L4 PER2*/
+};
+
+u32 l3_targ_stderrlog_main_clk3[] = {
+        0x0148  /* EMUSS */
+};
+
+char *l3_targ_stderrlog_main_name[L3_MODULES][18] = {
+        {
+        "DMM1",
+        "DMM2",
+        "ABE",
+        "L4CFG",
+        "CLK2 PWR DISC",
+        },
+        {
+        "CORTEX M3" ,
+        "DSS ",
+        "GPMC ",
+        "ISS ",
+        "IVAHD ",
+        "AES1",
+        "L4 PER0",
+        "OCMRAM ",
+        "GPMC sERROR",
+        "SGX ",
+        "SL2 ",
+        "C2C ",
+        "PWR DISC CLK1",
+        "SHA1",
+        "AES2",
+        "L4 PER3",
+        "L4 PER1",
+        "L4 PER2",
+        },
+        {
+        "EMUSS",
+        },
+};
+
+u32 *l3_targ[L3_MODULES] = {
+        l3_targ_stderrlog_main_clk1,
+        l3_targ_stderrlog_main_clk2,
+        l3_targ_stderrlog_main_clk3,
+};
+
+struct omap4_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+
+        /* memory base */
+        void __iomem *l3_base[4];
+
+        int             debug_irq;
+        int             app_irq;
+};
+
+#endif
diff --git a/arch/arm/mach-omap2/omap_l3_smx.c b/arch/arm/mach-omap2/omap_l3_smx.c
new file mode 100644
index 000000000000..265bff3acb9e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.c
@@ -0,0 +1,314 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     Sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include "omap_l3_smx.h"
+
+static inline u64 omap3_l3_readll(void __iomem *base, u16 reg)
+{
+        return __raw_readll(base + reg);
+}
+
+static inline void omap3_l3_writell(void __iomem *base, u16 reg, u64 value)
+{
+        __raw_writell(value, base + reg);
+}
+
+static inline enum omap3_l3_code omap3_l3_decode_error_code(u64 error)
+{
+        return (error & 0x0f000000) >> L3_ERROR_LOG_CODE;
+}
+
+static inline u32 omap3_l3_decode_addr(u64 error_addr)
+{
+        return error_addr & 0xffffffff;
+}
+
+static inline unsigned omap3_l3_decode_cmd(u64 error)
+{
+        return (error & 0x07) >> L3_ERROR_LOG_CMD;
+}
+
+static inline enum omap3_l3_initiator_id omap3_l3_decode_initid(u64 error)
+{
+        return (error & 0xff00) >> L3_ERROR_LOG_INITID;
+}
+
+static inline unsigned omap3_l3_decode_req_info(u64 error)
+{
+        return (error >> 32) & 0xffff;
+}
+
+static char *omap3_l3_code_string(u8 code)
+{
+        switch (code) {
+        case OMAP_L3_CODE_NOERROR:
+                return "No Error";
+        case OMAP_L3_CODE_UNSUP_CMD:
+                return "Unsupported Command";
+        case OMAP_L3_CODE_ADDR_HOLE:
+                return "Address Hole";
+        case OMAP_L3_CODE_PROTECT_VIOLATION:
+                return "Protection Violation";
+        case OMAP_L3_CODE_IN_BAND_ERR:
+                return "In-band Error";
+        case OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT:
+                return "Request Timeout Not Accepted";
+        case OMAP_L3_CODE_REQ_TOUT_NO_RESP:
+                return "Request Timeout, no response";
+        default:
+                return "UNKNOWN error";
+        }
+}
+
+static char *omap3_l3_initiator_string(u8 initid)
+{
+        switch (initid) {
+        case OMAP_L3_LCD:
+                return "LCD";
+        case OMAP_L3_SAD2D:
+                return "SAD2D";
+        case OMAP_L3_IA_MPU_SS_1:
+        case OMAP_L3_IA_MPU_SS_2:
+        case OMAP_L3_IA_MPU_SS_3:
+        case OMAP_L3_IA_MPU_SS_4:
+        case OMAP_L3_IA_MPU_SS_5:
+                return "MPU";
+        case OMAP_L3_IA_IVA_SS_1:
+        case OMAP_L3_IA_IVA_SS_2:
+        case OMAP_L3_IA_IVA_SS_3:
+                return "IVA_SS";
+        case OMAP_L3_IA_IVA_SS_DMA_1:
+        case OMAP_L3_IA_IVA_SS_DMA_2:
+        case OMAP_L3_IA_IVA_SS_DMA_3:
+        case OMAP_L3_IA_IVA_SS_DMA_4:
+        case OMAP_L3_IA_IVA_SS_DMA_5:
+        case OMAP_L3_IA_IVA_SS_DMA_6:
+                return "IVA_SS_DMA";
+        case OMAP_L3_IA_SGX:
+                return "SGX";
+        case OMAP_L3_IA_CAM_1:
+        case OMAP_L3_IA_CAM_2:
+        case OMAP_L3_IA_CAM_3:
+                return "CAM";
+        case OMAP_L3_IA_DAP:
+                return "DAP";
+        case OMAP_L3_SDMA_WR_1:
+        case OMAP_L3_SDMA_WR_2:
+                return "SDMA_WR";
+        case OMAP_L3_SDMA_RD_1:
+        case OMAP_L3_SDMA_RD_2:
+        case OMAP_L3_SDMA_RD_3:
+        case OMAP_L3_SDMA_RD_4:
+                return "SDMA_RD";
+        case OMAP_L3_USBOTG:
+                return "USB_OTG";
+        case OMAP_L3_USBHOST:
+                return "USB_HOST";
+        default:
+                return "UNKNOWN Initiator";
+        }
+}
+
+/**
+ * omap3_l3_block_irq - handles a register block's irq
+ * @l3: struct omap3_l3 *
+ * @base: register block base address
+ * @error: L3_ERROR_LOG register of our block
+ *
+ * Called in hard-irq context. Caller should take care of locking
+ *
+ * OMAP36xx TRM gives, on page 2001, Figure 9-10, the Typical Error
+ * Analysis Sequence, we are following that sequence here, please
+ * refer to that Figure for more information on the subject.
+ */
+static irqreturn_t omap3_l3_block_irq(struct omap3_l3 *l3,
+                                        u64 error, int error_addr)
+{
+        u8                      code = omap3_l3_decode_error_code(error);
+        u8                      initid = omap3_l3_decode_initid(error);
+        u8                      multi = error & L3_ERROR_LOG_MULTI;
+        u32                     address = omap3_l3_decode_addr(error_addr);
+
+        WARN(true, "%s Error seen by %s %s at address %x\n",
+                                 omap3_l3_code_string(code),
+                          omap3_l3_initiator_string(initid),
+                             multi ? "Multiple Errors" : "",
+                                                   address);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t omap3_l3_app_irq(int irq, void *_l3)
+{
+        struct omap3_l3         *l3 = _l3;
+
+        u64                     status, clear;
+        u64                     error;
+        u64                     error_addr;
+        u64                     err_source = 0;
+        void                    __iomem *base;
+        int                     int_type;
+
+        irqreturn_t             ret = IRQ_NONE;
+
+        if (irq == l3->app_irq)
+                int_type = L3_APPLICATION_ERROR;
+        else
+                int_type = L3_DEBUG_ERROR;
+
+        if (!int_type) {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0);
+                /*
+                 * if we have a timeout error, there's nothing we can
+                 * do besides rebooting the board. So let's BUG on any
+                 * of such errors and handle the others. timeout error
+                 * is severe and not expected to occur.
+                 */
+                BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK);
+        } else {
+                status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1);
+                /* No timeout error for debug sources */
+        }
+
+        base = ((l3->rt) + (*(omap3_l3_bases[int_type] + err_source)));
+
+        /* identify the error source */
+        for (err_source = 0; !(status & (1 << err_source)); err_source++)
+                                                                        ;
+        error = omap3_l3_readll(base, L3_ERROR_LOG);
+
+        if (error) {
+                error_addr = omap3_l3_readll(base, L3_ERROR_LOG_ADDR);
+
+                ret |= omap3_l3_block_irq(l3, error, error_addr);
+        }
+
+        /* Clear the status register */
+        clear = ((L3_AGENT_STATUS_CLEAR_IA << int_type) |
+                 (L3_AGENT_STATUS_CLEAR_TA));
+
+        omap3_l3_writell(base, L3_AGENT_STATUS, clear);
+
+        /* clear the error log register */
+        omap3_l3_writell(base, L3_ERROR_LOG, error);
+
+        return ret;
+}
+
+static int __init omap3_l3_probe(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3;
+        struct resource         *res;
+        int                     ret;
+        int                     irq;
+
+        l3 = kzalloc(sizeof(*l3), GFP_KERNEL);
+        if (!l3) {
+                ret = -ENOMEM;
+                goto err0;
+        }
+
+        platform_set_drvdata(pdev, l3);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!res) {
+                dev_err(&pdev->dev, "couldn't find resource\n");
+                ret = -ENODEV;
+                goto err1;
+        }
+        l3->rt = ioremap(res->start, resource_size(res));
+        if (!(l3->rt)) {
+                dev_err(&pdev->dev, "ioremap failed\n");
+                ret = -ENOMEM;
+                goto err2;
+        }
+
+        irq = platform_get_irq(pdev, 0);
+        ret = request_irq(irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-debug-irq", l3);
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request debug irq\n");
+                goto err3;
+        }
+        l3->debug_irq = irq;
+
+        irq = platform_get_irq(pdev, 1);
+        ret = request_irq(irq, omap3_l3_app_irq,
+                IRQF_DISABLED | IRQF_TRIGGER_RISING,
+                "l3-app-irq", l3);
+
+        if (ret) {
+                dev_err(&pdev->dev, "couldn't request app irq\n");
+                goto err4;
+        }
+
+        l3->app_irq = irq;
+        goto err0;
+
+err4:
+err3:
+        iounmap(l3->rt);
+err2:
+err1:
+        kfree(l3);
+err0:
+        return ret;
+}
+
+static int __exit omap3_l3_remove(struct platform_device *pdev)
+{
+        struct omap3_l3         *l3 = platform_get_drvdata(pdev);
+
+        free_irq(l3->app_irq, l3);
+        free_irq(l3->debug_irq, l3);
+        iounmap(l3->rt);
+        kfree(l3);
+
+        return 0;
+}
+
+static struct platform_driver omap3_l3_driver = {
+        .remove         = __exit_p(omap3_l3_remove),
+        .driver         = {
+        .name   = "omap_l3_smx",
+        },
+};
+
+static int __init omap3_l3_init(void)
+{
+        return platform_driver_probe(&omap3_l3_driver, omap3_l3_probe);
+}
+postcore_initcall_sync(omap3_l3_init);
+
+static void __exit omap3_l3_exit(void)
+{
+        platform_driver_unregister(&omap3_l3_driver);
+}
+module_exit(omap3_l3_exit);
diff --git a/arch/arm/mach-omap2/omap_l3_smx.h b/arch/arm/mach-omap2/omap_l3_smx.h
new file mode 100644
index 000000000000..ba2ed9a850cc
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_l3_smx.h
@@ -0,0 +1,338 @@
+ /*
+  * OMAP3XXX L3 Interconnect Driver header
+  *
+  * Copyright (C) 2011 Texas Corporation
+  *     Felipe Balbi <balbi@ti.com>
+  *     Santosh Shilimkar <santosh.shilimkar@ti.com>
+  *     sricharan <r.sricharan@ti.com>
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2 of the License, or
+  * (at your option) any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; if not, write to the Free Software
+  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
+  * USA
+  */
+#ifndef __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+#define __ARCH_ARM_MACH_OMAP2_L3_INTERCONNECT_3XXX_H
+
+/* Register definitions. All 64-bit wide */
+#define L3_COMPONENT                    0x000
+#define L3_CORE                         0x018
+#define L3_AGENT_CONTROL                0x020
+#define L3_AGENT_STATUS                 0x028
+#define L3_ERROR_LOG                    0x058
+
+#define L3_ERROR_LOG_MULTI              (1 << 31)
+#define L3_ERROR_LOG_SECONDARY          (1 << 30)
+
+#define L3_ERROR_LOG_ADDR               0x060
+
+/* Register definitions for Sideband Interconnect */
+#define L3_SI_CONTROL                   0x020
+#define L3_SI_FLAG_STATUS_0             0x510
+
+const u64 shift = 1;
+
+#define L3_STATUS_0_MPUIA_BRST          (shift << 0)
+#define L3_STATUS_0_MPUIA_RSP           (shift << 1)
+#define L3_STATUS_0_MPUIA_INBAND        (shift << 2)
+#define L3_STATUS_0_IVAIA_BRST          (shift << 6)
+#define L3_STATUS_0_IVAIA_RSP           (shift << 7)
+#define L3_STATUS_0_IVAIA_INBAND        (shift << 8)
+#define L3_STATUS_0_SGXIA_BRST          (shift << 9)
+#define L3_STATUS_0_SGXIA_RSP           (shift << 10)
+#define L3_STATUS_0_SGXIA_MERROR        (shift << 11)
+#define L3_STATUS_0_CAMIA_BRST          (shift << 12)
+#define L3_STATUS_0_CAMIA_RSP           (shift << 13)
+#define L3_STATUS_0_CAMIA_INBAND        (shift << 14)
+#define L3_STATUS_0_DISPIA_BRST         (shift << 15)
+#define L3_STATUS_0_DISPIA_RSP          (shift << 16)
+#define L3_STATUS_0_DMARDIA_BRST        (shift << 18)
+#define L3_STATUS_0_DMARDIA_RSP         (shift << 19)
+#define L3_STATUS_0_DMAWRIA_BRST        (shift << 21)
+#define L3_STATUS_0_DMAWRIA_RSP         (shift << 22)
+#define L3_STATUS_0_USBOTGIA_BRST       (shift << 24)
+#define L3_STATUS_0_USBOTGIA_RSP        (shift << 25)
+#define L3_STATUS_0_USBOTGIA_INBAND     (shift << 26)
+#define L3_STATUS_0_USBHOSTIA_BRST      (shift << 27)
+#define L3_STATUS_0_USBHOSTIA_INBAND    (shift << 28)
+#define L3_STATUS_0_SMSTA_REQ           (shift << 48)
+#define L3_STATUS_0_GPMCTA_REQ          (shift << 49)
+#define L3_STATUS_0_OCMRAMTA_REQ        (shift << 50)
+#define L3_STATUS_0_OCMROMTA_REQ        (shift << 51)
+#define L3_STATUS_0_IVATA_REQ           (shift << 54)
+#define L3_STATUS_0_SGXTA_REQ           (shift << 55)
+#define L3_STATUS_0_SGXTA_SERROR        (shift << 56)
+#define L3_STATUS_0_GPMCTA_SERROR       (shift << 57)
+#define L3_STATUS_0_L4CORETA_REQ        (shift << 58)
+#define L3_STATUS_0_L4PERTA_REQ         (shift << 59)
+#define L3_STATUS_0_L4EMUTA_REQ         (shift << 60)
+#define L3_STATUS_0_MAD2DTA_REQ         (shift << 61)
+
+#define L3_STATUS_0_TIMEOUT_MASK        (L3_STATUS_0_MPUIA_BRST         \
+                                        | L3_STATUS_0_MPUIA_RSP         \
+                                        | L3_STATUS_0_IVAIA_BRST        \
+                                        | L3_STATUS_0_IVAIA_RSP         \
+                                        | L3_STATUS_0_SGXIA_BRST        \
+                                        | L3_STATUS_0_SGXIA_RSP         \
+                                        | L3_STATUS_0_CAMIA_BRST        \
+                                        | L3_STATUS_0_CAMIA_RSP         \
+                                        | L3_STATUS_0_DISPIA_BRST       \
+                                        | L3_STATUS_0_DISPIA_RSP        \
+                                        | L3_STATUS_0_DMARDIA_BRST      \
+                                        | L3_STATUS_0_DMARDIA_RSP       \
+                                        | L3_STATUS_0_DMAWRIA_BRST      \
+                                        | L3_STATUS_0_DMAWRIA_RSP       \
+                                        | L3_STATUS_0_USBOTGIA_BRST     \
+                                        | L3_STATUS_0_USBOTGIA_RSP      \
+                                        | L3_STATUS_0_USBHOSTIA_BRST    \
+                                        | L3_STATUS_0_SMSTA_REQ         \
+                                        | L3_STATUS_0_GPMCTA_REQ        \
+                                        | L3_STATUS_0_OCMRAMTA_REQ      \
+                                        | L3_STATUS_0_OCMROMTA_REQ      \
+                                        | L3_STATUS_0_IVATA_REQ         \
+                                        | L3_STATUS_0_SGXTA_REQ         \
+                                        | L3_STATUS_0_L4CORETA_REQ      \
+                                        | L3_STATUS_0_L4PERTA_REQ       \
+                                        | L3_STATUS_0_L4EMUTA_REQ       \
+                                        | L3_STATUS_0_MAD2DTA_REQ)
+
+#define L3_SI_FLAG_STATUS_1             0x530
+
+#define L3_STATUS_1_MPU_DATAIA          (1 << 0)
+#define L3_STATUS_1_DAPIA0              (1 << 3)
+#define L3_STATUS_1_DAPIA1              (1 << 4)
+#define L3_STATUS_1_IVAIA               (1 << 6)
+
+#define L3_PM_ERROR_LOG                 0x020
+#define L3_PM_CONTROL                   0x028
+#define L3_PM_ERROR_CLEAR_SINGLE        0x030
+#define L3_PM_ERROR_CLEAR_MULTI         0x038
+#define L3_PM_REQ_INFO_PERMISSION(n)    (0x048 + (0x020 * n))
+#define L3_PM_READ_PERMISSION(n)        (0x050 + (0x020 * n))
+#define L3_PM_WRITE_PERMISSION(n)       (0x058 + (0x020 * n))
+#define L3_PM_ADDR_MATCH(n)             (0x060 + (0x020 * n))
+
+/* L3 error log bit fields. Common for IA and TA */
+#define L3_ERROR_LOG_CODE               24
+#define L3_ERROR_LOG_INITID             8
+#define L3_ERROR_LOG_CMD                0
+
+/* L3 agent status bit fields. */
+#define L3_AGENT_STATUS_CLEAR_IA        0x10000000
+#define L3_AGENT_STATUS_CLEAR_TA        0x01000000
+
+#define OMAP34xx_IRQ_L3_APP             10
+#define L3_APPLICATION_ERROR            0x0
+#define L3_DEBUG_ERROR                  0x1
+
+enum omap3_l3_initiator_id {
+        /* LCD has 1 ID */
+        OMAP_L3_LCD             = 29,
+        /* SAD2D has 1 ID */
+        OMAP_L3_SAD2D           = 28,
+        /* MPU has 5 IDs */
+        OMAP_L3_IA_MPU_SS_1     = 27,
+        OMAP_L3_IA_MPU_SS_2     = 26,
+        OMAP_L3_IA_MPU_SS_3     = 25,
+        OMAP_L3_IA_MPU_SS_4     = 24,
+        OMAP_L3_IA_MPU_SS_5     = 23,
+        /* IVA2.2 SS has 3 IDs*/
+        OMAP_L3_IA_IVA_SS_1     = 22,
+        OMAP_L3_IA_IVA_SS_2     = 21,
+        OMAP_L3_IA_IVA_SS_3     = 20,
+        /* IVA 2.2 SS DMA has 6 IDS */
+        OMAP_L3_IA_IVA_SS_DMA_1 = 19,
+        OMAP_L3_IA_IVA_SS_DMA_2 = 18,
+        OMAP_L3_IA_IVA_SS_DMA_3 = 17,
+        OMAP_L3_IA_IVA_SS_DMA_4 = 16,
+        OMAP_L3_IA_IVA_SS_DMA_5 = 15,
+        OMAP_L3_IA_IVA_SS_DMA_6 = 14,
+        /* SGX has 1 ID */
+        OMAP_L3_IA_SGX          = 13,
+        /* CAM has 3 ID */
+        OMAP_L3_IA_CAM_1        = 12,
+        OMAP_L3_IA_CAM_2        = 11,
+        OMAP_L3_IA_CAM_3        = 10,
+        /* DAP has 1 ID */
+        OMAP_L3_IA_DAP          = 9,
+        /* SDMA WR has 2 IDs */
+        OMAP_L3_SDMA_WR_1       = 8,
+        OMAP_L3_SDMA_WR_2       = 7,
+        /* SDMA RD has 4 IDs */
+        OMAP_L3_SDMA_RD_1       = 6,
+        OMAP_L3_SDMA_RD_2       = 5,
+        OMAP_L3_SDMA_RD_3       = 4,
+        OMAP_L3_SDMA_RD_4       = 3,
+        /* HSUSB OTG has 1 ID */
+        OMAP_L3_USBOTG          = 2,
+        /* HSUSB HOST has 1 ID */
+        OMAP_L3_USBHOST         = 1,
+};
+
+enum omap3_l3_code {
+        OMAP_L3_CODE_NOERROR = 0,
+        OMAP_L3_CODE_UNSUP_CMD = 1,
+        OMAP_L3_CODE_ADDR_HOLE = 2,
+        OMAP_L3_CODE_PROTECT_VIOLATION = 3,
+        OMAP_L3_CODE_IN_BAND_ERR = 4,
+        /* codes 5 and 6 are reserved */
+        OMAP_L3_CODE_REQ_TOUT_NOT_ACCEPT = 7,
+        OMAP_L3_CODE_REQ_TOUT_NO_RESP = 8,
+        /* codes 9 - 15 are also reserved */
+};
+
+struct omap3_l3 {
+        struct device   *dev;
+        struct clk      *ick;
+
+        /* memory base*/
+        void __iomem    *rt;
+
+        int             debug_irq;
+        int             app_irq;
+
+        /* true when and inband functional error occurs */
+        unsigned        inband:1;
+};
+
+/* offsets for l3 agents in order with the Flag status register */
+unsigned int __iomem omap3_l3_app_bases[] = {
+        /* MPU IA */
+        0x1400,
+        0x1400,
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        0x1800,
+        0x1800,
+        /* SGX IA */
+        0x1c00,
+        0x1c00,
+        /* RESERVED */
+        0,
+        /* CAMERA IA */
+        0x5800,
+        0x5800,
+        0x5800,
+        /* DISPLAY IA */
+        0x5400,
+        0x5400,
+        /* RESERVED */
+        0,
+        /*SDMA RD IA */
+        0x4c00,
+        0x4c00,
+        /* RESERVED */
+        0,
+        /* SDMA WR IA */
+        0x5000,
+        0x5000,
+        /* RESERVED */
+        0,
+        /* USB OTG IA */
+        0x4400,
+        0x4400,
+        0x4400,
+        /* USB HOST IA */
+        0x4000,
+        0x4000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        /* SAD2D IA */
+        0x3000,
+        0x3000,
+        0x3000,
+        /* RESERVED */
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        /* SMA TA */
+        0x2000,
+        /* GPMC TA */
+        0x2400,
+        /* OCM RAM TA */
+        0x2800,
+        /* OCM ROM TA */
+        0x2C00,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* IVA 2.2 TA */
+        0x6000,
+        /* SGX TA */
+        0x6400,
+        /* L4 EMU TA */
+        0x7000,
+        /* GPMC TA */
+        0x2400,
+        /* L4 CORE TA */
+        0x6800,
+        /* L4 PER TA */
+        0x6c00,
+        /* L4 EMU TA */
+        0x7000,
+        /* MAD2D TA */
+        0x3400,
+        /* RESERVED */
+        0,
+        0,
+};
+
+unsigned int __iomem omap3_l3_debug_bases[] = {
+        /* MPU DATA IA */
+        0x1400,
+        /* RESERVED */
+        0,
+        0,
+        /* DAP IA */
+        0x5c00,
+        0x5c00,
+        /* RESERVED */
+        0,
+        /* IVA 2.2 IA */
+        0x1800,
+        /* REST RESERVED */
+};
+
+u32 *omap3_l3_bases[] = {
+        omap3_l3_app_bases,
+        omap3_l3_debug_bases,
+};
+
+/*
+ * REVISIT define __raw_readll/__raw_writell here, but move them to
+ * <asm/io.h> at some point
+ */
+#define __raw_writell(v, a)     (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a) = (v))
+#define __raw_readll(a)         (__chk_io_ptr(a), \
+                                *(volatile u64 __force *)(a))
+
+#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index 125f56591fb5..a5a83b358ddd 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -637,14 +637,14 @@ static int __init pm_dbg_init(void)
 
                 }
 
-        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
                                    &enable_off_mode, &pm_dbg_option_fops);
-        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
                                    &sleep_while_idle, &pm_dbg_option_fops);
-        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUGO, d,
+        (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
                                    &wakeup_timer_seconds, &pm_dbg_option_fops);
         (void) debugfs_create_file("wakeup_timer_milliseconds",
-                        S_IRUGO | S_IWUGO, d, &wakeup_timer_milliseconds,
+                        S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
                         &pm_dbg_option_fops);
         pm_dbg_init_done = 1;
 
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index e983c8301f55..96907da1910a 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -379,7 +379,10 @@ static void __init prcm_setup_regs(void)
         int i, num_mem_banks;
         struct powerdomain *pwrdm;
 
-        /* Enable autoidle */
+        /*
+         * Enable autoidle
+         * XXX This should be handled by hwmod code or PRCM init code
+         */
         omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD,
                           OMAP2_PRCM_SYSCONFIG_OFFSET);
 
@@ -418,70 +421,6 @@ static void __init prcm_setup_regs(void)
         clkdm_for_each(clkdms_setup, NULL);
         clkdm_add_wkdep(mpu_clkdm, wkup_clkdm);
 
-        /* Enable clock autoidle for all domains */
-        omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK |
-                               OMAP24XX_AUTO_MAILBOXES_MASK |
-                               OMAP24XX_AUTO_WDT4_MASK |
-                               OMAP2420_AUTO_WDT3_MASK |
-                               OMAP24XX_AUTO_MSPRO_MASK |
-                               OMAP2420_AUTO_MMC_MASK |
-                               OMAP24XX_AUTO_FAC_MASK |
-                               OMAP2420_AUTO_EAC_MASK |
-                               OMAP24XX_AUTO_HDQ_MASK |
-                               OMAP24XX_AUTO_UART2_MASK |
-                               OMAP24XX_AUTO_UART1_MASK |
-                               OMAP24XX_AUTO_I2C2_MASK |
-                               OMAP24XX_AUTO_I2C1_MASK |
-                               OMAP24XX_AUTO_MCSPI2_MASK |
-                               OMAP24XX_AUTO_MCSPI1_MASK |
-                               OMAP24XX_AUTO_MCBSP2_MASK |
-                               OMAP24XX_AUTO_MCBSP1_MASK |
-                               OMAP24XX_AUTO_GPT12_MASK |
-                               OMAP24XX_AUTO_GPT11_MASK |
-                               OMAP24XX_AUTO_GPT10_MASK |
-                               OMAP24XX_AUTO_GPT9_MASK |
-                               OMAP24XX_AUTO_GPT8_MASK |
-                               OMAP24XX_AUTO_GPT7_MASK |
-                               OMAP24XX_AUTO_GPT6_MASK |
-                               OMAP24XX_AUTO_GPT5_MASK |
-                               OMAP24XX_AUTO_GPT4_MASK |
-                               OMAP24XX_AUTO_GPT3_MASK |
-                               OMAP24XX_AUTO_GPT2_MASK |
-                               OMAP2420_AUTO_VLYNQ_MASK |
-                               OMAP24XX_AUTO_DSS_MASK,
-                               CORE_MOD, CM_AUTOIDLE1);
-        omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK |
-                               OMAP24XX_AUTO_SSI_MASK |
-                               OMAP24XX_AUTO_USB_MASK,
-                               CORE_MOD, CM_AUTOIDLE2);
-        omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK |
-                               OMAP24XX_AUTO_GPMC_MASK |
-                               OMAP24XX_AUTO_SDMA_MASK,
-                               CORE_MOD, CM_AUTOIDLE3);
-        omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK |
-                               OMAP24XX_AUTO_AES_MASK |
-                               OMAP24XX_AUTO_RNG_MASK |
-                               OMAP24XX_AUTO_SHA_MASK |
-                               OMAP24XX_AUTO_DES_MASK,
-                               CORE_MOD, OMAP24XX_CM_AUTOIDLE4);
-
-        omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD,
-                               CM_AUTOIDLE);
-
-        /* Put DPLL and both APLLs into autoidle mode */
-        omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) |
-                               (0x03 << OMAP24XX_AUTO_96M_SHIFT) |
-                               (0x03 << OMAP24XX_AUTO_54M_SHIFT),
-                               PLL_MOD, CM_AUTOIDLE);
-
-        omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK |
-                               OMAP24XX_AUTO_WDT1_MASK |
-                               OMAP24XX_AUTO_MPU_WDT_MASK |
-                               OMAP24XX_AUTO_GPIOS_MASK |
-                               OMAP24XX_AUTO_32KSYNC_MASK |
-                               OMAP24XX_AUTO_GPT1_MASK,
-                               WKUP_MOD, CM_AUTOIDLE);
-
         /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
          * stabilisation */
         omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD,
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index eda9a4e99a89..3d6a00e07a5b 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -688,14 +688,11 @@ static void __init omap3_d2d_idle(void)
 
 static void __init prcm_setup_regs(void)
 {
-        u32 omap3630_auto_uart4_mask = cpu_is_omap3630() ?
-                                        OMAP3630_AUTO_UART4_MASK : 0;
         u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
                                         OMAP3630_EN_UART4_MASK : 0;
         u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
                                         OMAP3630_GRPSEL_UART4_MASK : 0;
 
-
         /* XXX Reset all wkdeps. This should be done when initializing
          * powerdomains */
         omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP);
@@ -710,127 +707,10 @@ static void __init prcm_setup_regs(void)
         } else
                 omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP);
 
-        /*
-         * Enable interface clock autoidle for all modules.
-         * Note that in the long run this should be done by clockfw
-         */
-        omap2_cm_write_mod_reg(
-                OMAP3430_AUTO_MODEM_MASK |
-                OMAP3430ES2_AUTO_MMC3_MASK |
-                OMAP3430ES2_AUTO_ICR_MASK |
-                OMAP3430_AUTO_AES2_MASK |
-                OMAP3430_AUTO_SHA12_MASK |
-                OMAP3430_AUTO_DES2_MASK |
-                OMAP3430_AUTO_MMC2_MASK |
-                OMAP3430_AUTO_MMC1_MASK |
-                OMAP3430_AUTO_MSPRO_MASK |
-                OMAP3430_AUTO_HDQ_MASK |
-                OMAP3430_AUTO_MCSPI4_MASK |
-                OMAP3430_AUTO_MCSPI3_MASK |
-                OMAP3430_AUTO_MCSPI2_MASK |
-                OMAP3430_AUTO_MCSPI1_MASK |
-                OMAP3430_AUTO_I2C3_MASK |
-                OMAP3430_AUTO_I2C2_MASK |
-                OMAP3430_AUTO_I2C1_MASK |
-                OMAP3430_AUTO_UART2_MASK |
-                OMAP3430_AUTO_UART1_MASK |
-                OMAP3430_AUTO_GPT11_MASK |
-                OMAP3430_AUTO_GPT10_MASK |
-                OMAP3430_AUTO_MCBSP5_MASK |
-                OMAP3430_AUTO_MCBSP1_MASK |
-                OMAP3430ES1_AUTO_FAC_MASK | /* This is es1 only */
-                OMAP3430_AUTO_MAILBOXES_MASK |
-                OMAP3430_AUTO_OMAPCTRL_MASK |
-                OMAP3430ES1_AUTO_FSHOSTUSB_MASK |
-                OMAP3430_AUTO_HSOTGUSB_MASK |
-                OMAP3430_AUTO_SAD2D_MASK |
-                OMAP3430_AUTO_SSI_MASK,
-                CORE_MOD, CM_AUTOIDLE1);
-
-        omap2_cm_write_mod_reg(
-                OMAP3430_AUTO_PKA_MASK |
-                OMAP3430_AUTO_AES1_MASK |
-                OMAP3430_AUTO_RNG_MASK |
-                OMAP3430_AUTO_SHA11_MASK |
-                OMAP3430_AUTO_DES1_MASK,
-                CORE_MOD, CM_AUTOIDLE2);
-
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                omap2_cm_write_mod_reg(
-                        OMAP3430_AUTO_MAD2D_MASK |
-                        OMAP3430ES2_AUTO_USBTLL_MASK,
-                        CORE_MOD, CM_AUTOIDLE3);
-        }
-
-        omap2_cm_write_mod_reg(
-                OMAP3430_AUTO_WDT2_MASK |
-                OMAP3430_AUTO_WDT1_MASK |
-                OMAP3430_AUTO_GPIO1_MASK |
-                OMAP3430_AUTO_32KSYNC_MASK |
-                OMAP3430_AUTO_GPT12_MASK |
-                OMAP3430_AUTO_GPT1_MASK,
-                WKUP_MOD, CM_AUTOIDLE);
-
-        omap2_cm_write_mod_reg(
-                OMAP3430_AUTO_DSS_MASK,
-                OMAP3430_DSS_MOD,
-                CM_AUTOIDLE);
-
-        omap2_cm_write_mod_reg(
-                OMAP3430_AUTO_CAM_MASK,
-                OMAP3430_CAM_MOD,
-                CM_AUTOIDLE);
-
-        omap2_cm_write_mod_reg(
-                omap3630_auto_uart4_mask |
-                OMAP3430_AUTO_GPIO6_MASK |
-                OMAP3430_AUTO_GPIO5_MASK |
-                OMAP3430_AUTO_GPIO4_MASK |
-                OMAP3430_AUTO_GPIO3_MASK |
-                OMAP3430_AUTO_GPIO2_MASK |
-                OMAP3430_AUTO_WDT3_MASK |
-                OMAP3430_AUTO_UART3_MASK |
-                OMAP3430_AUTO_GPT9_MASK |
-                OMAP3430_AUTO_GPT8_MASK |
-                OMAP3430_AUTO_GPT7_MASK |
-                OMAP3430_AUTO_GPT6_MASK |
-                OMAP3430_AUTO_GPT5_MASK |
-                OMAP3430_AUTO_GPT4_MASK |
-                OMAP3430_AUTO_GPT3_MASK |
-                OMAP3430_AUTO_GPT2_MASK |
-                OMAP3430_AUTO_MCBSP4_MASK |
-                OMAP3430_AUTO_MCBSP3_MASK |
-                OMAP3430_AUTO_MCBSP2_MASK,
-                OMAP3430_PER_MOD,
-                CM_AUTOIDLE);
-
-        if (omap_rev() > OMAP3430_REV_ES1_0) {
-                omap2_cm_write_mod_reg(
-                        OMAP3430ES2_AUTO_USBHOST_MASK,
-                        OMAP3430ES2_USBHOST_MOD,
-                        CM_AUTOIDLE);
-        }
-
+        /* XXX This should be handled by hwmod code or SCM init code */
         omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
 
         /*
-         * Set all plls to autoidle. This is needed until autoidle is
-         * enabled by clockfw
-         */
-        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
-                         OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
-        omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT,
-                         MPU_MOD,
-                         CM_AUTOIDLE2);
-        omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) |
-                         (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT),
-                         PLL_MOD,
-                         CM_AUTOIDLE);
-        omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT,
-                         PLL_MOD,
-                         CM_AUTOIDLE2);
-
-        /*
          * Enable control of expternal oscillator through
          * sys_clkreq. In the long run clock framework should
          * take care of this.
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index eaed0df16699..a11be81997c5 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -2,7 +2,7 @@
  * OMAP powerdomain control
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2009 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Written by Paul Walmsley
  * Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -938,3 +938,44 @@ u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm)
 
         return count;
 }
+
+/**
+ * pwrdm_can_ever_lose_context - can this powerdomain ever lose context?
+ * @pwrdm: struct powerdomain *
+ *
+ * Given a struct powerdomain * @pwrdm, returns 1 if the powerdomain
+ * can lose either memory or logic context or if @pwrdm is invalid, or
+ * returns 0 otherwise.  This function is not concerned with how the
+ * powerdomain registers are programmed (i.e., to go off or not); it's
+ * concerned with whether it's ever possible for this powerdomain to
+ * go off while some other part of the chip is active.  This function
+ * assumes that every powerdomain can go to either ON or INACTIVE.
+ */
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm)
+{
+        int i;
+
+        if (IS_ERR_OR_NULL(pwrdm)) {
+                pr_debug("powerdomain: %s: invalid powerdomain pointer\n",
+                         __func__);
+                return 1;
+        }
+
+        if (pwrdm->pwrsts & PWRSTS_OFF)
+                return 1;
+
+        if (pwrdm->pwrsts & PWRSTS_RET) {
+                if (pwrdm->pwrsts_logic_ret & PWRSTS_OFF)
+                        return 1;
+
+                for (i = 0; i < pwrdm->banks; i++)
+                        if (pwrdm->pwrsts_mem_ret[i] & PWRSTS_OFF)
+                                return 1;
+        }
+
+        for (i = 0; i < pwrdm->banks; i++)
+                if (pwrdm->pwrsts_mem_on[i] & PWRSTS_OFF)
+                        return 1;
+
+        return 0;
+}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 0b7a357cb38e..027f40bd235d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -2,7 +2,7 @@
  * OMAP2/3/4 powerdomain control
  *
  * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley
  *
@@ -34,17 +34,14 @@
 
 /* Powerdomain allowable state bitfields */
 #define PWRSTS_ON               (1 << PWRDM_POWER_ON)
+#define PWRSTS_INACTIVE         (1 << PWRDM_POWER_INACTIVE)
+#define PWRSTS_RET              (1 << PWRDM_POWER_RET)
 #define PWRSTS_OFF              (1 << PWRDM_POWER_OFF)
-#define PWRSTS_OFF_ON           ((1 << PWRDM_POWER_OFF) | \
-                                 (1 << PWRDM_POWER_ON))
 
-#define PWRSTS_OFF_RET          ((1 << PWRDM_POWER_OFF) | \
-                                 (1 << PWRDM_POWER_RET))
-
-#define PWRSTS_RET_ON           ((1 << PWRDM_POWER_RET) | \
-                                 (1 << PWRDM_POWER_ON))
-
-#define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON))
+#define PWRSTS_OFF_ON           (PWRSTS_OFF | PWRSTS_ON)
+#define PWRSTS_OFF_RET          (PWRSTS_OFF | PWRSTS_RET)
+#define PWRSTS_RET_ON           (PWRSTS_RET | PWRSTS_ON)
+#define PWRSTS_OFF_RET_ON       (PWRSTS_OFF_RET | PWRSTS_ON)
 
 
 /* Powerdomain flags */
@@ -211,6 +208,7 @@ int pwrdm_pre_transition(void);
 int pwrdm_post_transition(void);
 int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
 u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
+bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 
 extern void omap2xxx_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
index 5b4dd971320a..4210c3399769 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c
@@ -2,7 +2,7 @@
  * OMAP2/3 common powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
  *
@@ -62,13 +62,13 @@ struct powerdomain gfx_omap2_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
                                            CHIP_IS_OMAP3430ES1),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -76,4 +76,5 @@ struct powerdomain wkup_omap2_pwrdm = {
         .name           = "wkup_pwrdm",
         .prcm_offs      = WKUP_MOD,
         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
+        .pwrsts         = PWRSTS_ON,
 };
diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c
index 78739e10f5b9..cc389fb2005d 100644
--- a/arch/arm/mach-omap2/powerdomains2xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c
@@ -2,7 +2,7 @@
  * OMAP2XXX powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
  *
@@ -30,13 +30,13 @@ static struct powerdomain dsp_pwrdm = {
         .prcm_offs        = OMAP24XX_DSP_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET,
+                [0] = PWRSTS_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
         },
 };
 
@@ -48,10 +48,10 @@ static struct powerdomain mpu_24xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET,
+                [0] = PWRSTS_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
         },
 };
 
@@ -87,13 +87,13 @@ static struct powerdomain mdm_pwrdm = {
         .prcm_offs        = OMAP2430_MDM_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e1bec562625b..9c9c113788b9 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -2,7 +2,7 @@
  * OMAP3 powerdomain definitions
  *
  * Copyright (C) 2007-2008 Texas Instruments, Inc.
- * Copyright (C) 2007-2010 Nokia Corporation
+ * Copyright (C) 2007-2011 Nokia Corporation
  *
  * Paul Walmsley, Jouni Högander
  *
@@ -47,10 +47,10 @@ static struct powerdomain iva2_pwrdm = {
                 [3] = PWRSTS_OFF_RET,
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,
-                [1] = PWRDM_POWER_ON,
+                [0] = PWRSTS_ON,
+                [1] = PWRSTS_ON,
                 [2] = PWRSTS_OFF_ON,
-                [3] = PWRDM_POWER_ON,
+                [3] = PWRSTS_ON,
         },
 };
 
@@ -128,13 +128,13 @@ static struct powerdomain dss_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_DSS_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -149,13 +149,13 @@ static struct powerdomain sgx_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         /* XXX This is accurate for 3430 SGX, but what about GFX? */
         .pwrsts           = PWRSTS_OFF_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -164,13 +164,13 @@ static struct powerdomain cam_pwrdm = {
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .prcm_offs        = OMAP3430_CAM_MOD,
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -182,10 +182,10 @@ static struct powerdomain per_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
@@ -200,7 +200,7 @@ static struct powerdomain neon_pwrdm = {
         .prcm_offs        = OMAP3430_NEON_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
 };
 
 static struct powerdomain usbhost_pwrdm = {
@@ -208,7 +208,7 @@ static struct powerdomain usbhost_pwrdm = {
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_RET,
+        .pwrsts_logic_ret = PWRSTS_RET,
         /*
          * REVISIT: Enabling usb host save and restore mechanism seems to
          * leave the usb host domain permanently in ACTIVE mode after
@@ -218,10 +218,10 @@ static struct powerdomain usbhost_pwrdm = {
         /*.flags          = PWRDM_HAS_HDWR_SAR,*/ /* for USBHOST ctrlr only */
         .banks            = 1,
         .pwrsts_mem_ret   = {
-                [0] = PWRDM_POWER_RET, /* MEMRETSTATE */
+                [0] = PWRSTS_RET, /* MEMRETSTATE */
         },
         .pwrsts_mem_on    = {
-                [0] = PWRDM_POWER_ON,  /* MEMONSTATE */
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
         },
 };
 
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index 26d7641076d7..c4222c7036a5 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -2,7 +2,7 @@
  * OMAP4 Power domains framework
  *
  * Copyright (C) 2009-2010 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  *
  * Abhijit Pagare (abhijitpagare@ti.com)
  * Benoit Cousson (b-cousson@ti.com)
@@ -40,18 +40,18 @@ static struct powerdomain core_44xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 5,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* core_nret_bank */
+                [0] = PWRSTS_OFF,       /* core_nret_bank */
                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
-                [2] = PWRDM_POWER_RET,  /* core_other_bank */
+                [2] = PWRSTS_RET,       /* core_other_bank */
                 [3] = PWRSTS_OFF_RET,   /* ducati_l2ram */
                 [4] = PWRSTS_OFF_RET,   /* ducati_unicache */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* core_nret_bank */
+                [0] = PWRSTS_ON,        /* core_nret_bank */
                 [1] = PWRSTS_OFF_RET,   /* core_ocmram */
-                [2] = PWRDM_POWER_ON,   /* core_other_bank */
-                [3] = PWRDM_POWER_ON,   /* ducati_l2ram */
-                [4] = PWRDM_POWER_ON,   /* ducati_unicache */
+                [2] = PWRSTS_ON,        /* core_other_bank */
+                [3] = PWRSTS_ON,        /* ducati_l2ram */
+                [4] = PWRSTS_ON,        /* ducati_unicache */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -65,10 +65,10 @@ static struct powerdomain gfx_44xx_pwrdm = {
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* gfx_mem */
+                [0] = PWRSTS_OFF,       /* gfx_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* gfx_mem */
+                [0] = PWRSTS_ON,        /* gfx_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -80,15 +80,15 @@ static struct powerdomain abe_44xx_pwrdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 2,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_RET,  /* aessmem */
-                [1] = PWRDM_POWER_OFF,  /* periphmem */
+                [0] = PWRSTS_RET,       /* aessmem */
+                [1] = PWRSTS_OFF,       /* periphmem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* aessmem */
-                [1] = PWRDM_POWER_ON,   /* periphmem */
+                [0] = PWRSTS_ON,        /* aessmem */
+                [1] = PWRSTS_ON,        /* periphmem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -103,10 +103,10 @@ static struct powerdomain dss_44xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* dss_mem */
+                [0] = PWRSTS_OFF,       /* dss_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* dss_mem */
+                [0] = PWRSTS_ON,        /* dss_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -121,14 +121,14 @@ static struct powerdomain tesla_44xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 3,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_RET,  /* tesla_edma */
+                [0] = PWRSTS_RET,       /* tesla_edma */
                 [1] = PWRSTS_OFF_RET,   /* tesla_l1 */
                 [2] = PWRSTS_OFF_RET,   /* tesla_l2 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* tesla_edma */
-                [1] = PWRDM_POWER_ON,   /* tesla_l1 */
-                [2] = PWRDM_POWER_ON,   /* tesla_l2 */
+                [0] = PWRSTS_ON,        /* tesla_edma */
+                [1] = PWRSTS_ON,        /* tesla_l1 */
+                [2] = PWRSTS_ON,        /* tesla_l2 */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -142,10 +142,10 @@ static struct powerdomain wkup_44xx_pwrdm = {
         .pwrsts           = PWRSTS_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* wkup_bank */
+                [0] = PWRSTS_OFF,       /* wkup_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* wkup_bank */
+                [0] = PWRSTS_ON,        /* wkup_bank */
         },
 };
 
@@ -162,7 +162,7 @@ static struct powerdomain cpu0_44xx_pwrdm = {
                 [0] = PWRSTS_OFF_RET,   /* cpu0_l1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cpu0_l1 */
+                [0] = PWRSTS_ON,        /* cpu0_l1 */
         },
 };
 
@@ -179,7 +179,7 @@ static struct powerdomain cpu1_44xx_pwrdm = {
                 [0] = PWRSTS_OFF_RET,   /* cpu1_l1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cpu1_l1 */
+                [0] = PWRSTS_ON,        /* cpu1_l1 */
         },
 };
 
@@ -192,10 +192,10 @@ static struct powerdomain emu_44xx_pwrdm = {
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* emu_bank */
+                [0] = PWRSTS_OFF,       /* emu_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* emu_bank */
+                [0] = PWRSTS_ON,        /* emu_bank */
         },
 };
 
@@ -211,12 +211,12 @@ static struct powerdomain mpu_44xx_pwrdm = {
         .pwrsts_mem_ret = {
                 [0] = PWRSTS_OFF_RET,   /* mpu_l1 */
                 [1] = PWRSTS_OFF_RET,   /* mpu_l2 */
-                [2] = PWRDM_POWER_RET,  /* mpu_ram */
+                [2] = PWRSTS_RET,       /* mpu_ram */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* mpu_l1 */
-                [1] = PWRDM_POWER_ON,   /* mpu_l2 */
-                [2] = PWRDM_POWER_ON,   /* mpu_ram */
+                [0] = PWRSTS_ON,        /* mpu_l1 */
+                [1] = PWRSTS_ON,        /* mpu_l2 */
+                [2] = PWRSTS_ON,        /* mpu_ram */
         },
 };
 
@@ -227,19 +227,19 @@ static struct powerdomain ivahd_44xx_pwrdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .omap_chip        = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
         .pwrsts           = PWRSTS_OFF_RET_ON,
-        .pwrsts_logic_ret = PWRDM_POWER_OFF,
+        .pwrsts_logic_ret = PWRSTS_OFF,
         .banks            = 4,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* hwa_mem */
+                [0] = PWRSTS_OFF,       /* hwa_mem */
                 [1] = PWRSTS_OFF_RET,   /* sl2_mem */
                 [2] = PWRSTS_OFF_RET,   /* tcm1_mem */
                 [3] = PWRSTS_OFF_RET,   /* tcm2_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* hwa_mem */
-                [1] = PWRDM_POWER_ON,   /* sl2_mem */
-                [2] = PWRDM_POWER_ON,   /* tcm1_mem */
-                [3] = PWRDM_POWER_ON,   /* tcm2_mem */
+                [0] = PWRSTS_ON,        /* hwa_mem */
+                [1] = PWRSTS_ON,        /* sl2_mem */
+                [2] = PWRSTS_ON,        /* tcm1_mem */
+                [3] = PWRSTS_ON,        /* tcm2_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -253,10 +253,10 @@ static struct powerdomain cam_44xx_pwrdm = {
         .pwrsts           = PWRSTS_OFF_ON,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* cam_mem */
+                [0] = PWRSTS_OFF,       /* cam_mem */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* cam_mem */
+                [0] = PWRSTS_ON,        /* cam_mem */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -271,10 +271,10 @@ static struct powerdomain l3init_44xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 1,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* l3init_bank1 */
+                [0] = PWRSTS_OFF,       /* l3init_bank1 */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* l3init_bank1 */
+                [0] = PWRSTS_ON,        /* l3init_bank1 */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
@@ -289,12 +289,12 @@ static struct powerdomain l4per_44xx_pwrdm = {
         .pwrsts_logic_ret = PWRSTS_OFF_RET,
         .banks            = 2,
         .pwrsts_mem_ret = {
-                [0] = PWRDM_POWER_OFF,  /* nonretained_bank */
-                [1] = PWRDM_POWER_RET,  /* retained_bank */
+                [0] = PWRSTS_OFF,       /* nonretained_bank */
+                [1] = PWRSTS_RET,       /* retained_bank */
         },
         .pwrsts_mem_on  = {
-                [0] = PWRDM_POWER_ON,   /* nonretained_bank */
-                [1] = PWRDM_POWER_ON,   /* retained_bank */
+                [0] = PWRSTS_ON,        /* nonretained_bank */
+                [1] = PWRSTS_ON,        /* retained_bank */
         },
         .flags          = PWRDM_HAS_LOWPOWERSTATECHANGE,
 };
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 87486f559784..0363dcb0ef93 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -121,6 +121,10 @@
 #define OMAP24XX_ST_MCSPI2_MASK                         (1 << 18)
 #define OMAP24XX_ST_MCSPI1_SHIFT                        17
 #define OMAP24XX_ST_MCSPI1_MASK                         (1 << 17)
+#define OMAP24XX_ST_MCBSP2_SHIFT                        16
+#define OMAP24XX_ST_MCBSP2_MASK                         (1 << 16)
+#define OMAP24XX_ST_MCBSP1_SHIFT                        15
+#define OMAP24XX_ST_MCBSP1_MASK                         (1 << 15)
 #define OMAP24XX_ST_GPT12_SHIFT                         14
 #define OMAP24XX_ST_GPT12_MASK                          (1 << 14)
 #define OMAP24XX_ST_GPT11_SHIFT                         13
@@ -191,6 +195,8 @@
 #define OMAP3430_AUTOIDLE_MASK                          (1 << 0)
 
 /* CM_FCLKEN1_CORE, CM_ICLKEN1_CORE, PM_WKEN1_CORE shared bits */
+#define OMAP3430_EN_MMC3_MASK                           (1 << 30)
+#define OMAP3430_EN_MMC3_SHIFT                          30
 #define OMAP3430_EN_MMC2_MASK                           (1 << 25)
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
@@ -231,6 +237,8 @@
 #define OMAP3430_EN_HSOTGUSB_SHIFT                      4
 
 /* PM_WKST1_CORE, CM_IDLEST1_CORE shared bits */
+#define OMAP3430_ST_MMC3_SHIFT                          30
+#define OMAP3430_ST_MMC3_MASK                           (1 << 30)
 #define OMAP3430_ST_MMC2_SHIFT                          25
 #define OMAP3430_ST_MMC2_MASK                           (1 << 25)
 #define OMAP3430_ST_MMC1_SHIFT                          24
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index 729a644ce852..d22d1b43bccd 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -38,8 +38,8 @@
 #define OMAP4430_PRCM_MPU_CPU1_INST             0x0800
 
 /* PRCM_MPU clockdomain register offsets (from instance start) */
-#define OMAP4430_PRCM_MPU_CPU0_MPU_CDOFFS       0x0000
-#define OMAP4430_PRCM_MPU_CPU1_MPU_CDOFFS       0x0000
+#define OMAP4430_PRCM_MPU_CPU0_CPU0_CDOFFS      0x0018
+#define OMAP4430_PRCM_MPU_CPU1_CPU1_CDOFFS      0x0018
 
 
 /*
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 47eef48b8830..1ac361b7b8cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -680,7 +680,7 @@ static int __init omap_serial_early_init(void)
                 num_uarts++;
 
                 /*
-                 * NOTE: omap_hwmod_init() has not yet been called,
+                 * NOTE: omap_hwmod_setup*() has not yet been called,
                  *       so no hwmod functions will work yet.
                  */
 
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index c37e823266d3..95ac336fe3f7 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -900,7 +900,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 return PTR_ERR(dbg_dir);
         }
 
-        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUGO, dbg_dir,
+        (void) debugfs_create_file("autocomp", S_IRUGO | S_IWUSR, dbg_dir,
                                 (void *)sr_info, &pm_sr_fops);
         (void) debugfs_create_x32("errweight", S_IRUGO, dbg_dir,
                         &sr_info->err_weight);
@@ -939,7 +939,7 @@ static int __init omap_sr_probe(struct platform_device *pdev)
                 strcpy(name, "volt_");
                 sprintf(volt_name, "%d", volt_data[i].volt_nominal);
                 strcat(name, volt_name);
-                (void) debugfs_create_x32(name, S_IRUGO | S_IWUGO, nvalue_dir,
+                (void) debugfs_create_x32(name, S_IRUGO | S_IWUSR, nvalue_dir,
                                 &(sr_info->nvalue_table[i].nvalue));
         }
 
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 7b7c2683ae7b..3b9cf85f4bb9 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -39,10 +39,12 @@
 #include <asm/mach/time.h>
 #include <plat/dmtimer.h>
 #include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
 
 #include "timer-gp.h"
 
-#include <plat/common.h>
 
 /* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
 #define MAX_GPTIMER_ID          12
@@ -132,9 +134,13 @@ static void __init omap2_gp_clockevent_init(void)
 {
         u32 tick_rate;
         int src;
+        char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
 
         inited = 1;
 
+        sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
+        omap_hwmod_setup_one(clockevent_hwmod_name);
+
         gptimer = omap_dm_timer_request_specific(gptimer_id);
         BUG_ON(gptimer == NULL);
         gptimer_wakeup = gptimer;
@@ -190,6 +196,7 @@ static void __init omap2_gp_clocksource_init(void)
 /*
  * clocksource
  */
+static DEFINE_CLOCK_DATA(cd);
 static struct omap_dm_timer *gpt_clocksource;
 static cycle_t clocksource_read_cycles(struct clocksource *cs)
 {
@@ -204,6 +211,15 @@ static struct clocksource clocksource_gpt = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
+static void notrace dmtimer_update_sched_clock(void)
+{
+        u32 cyc;
+
+        cyc = omap_dm_timer_read_counter(gpt_clocksource);
+
+        update_sched_clock(&cd, cyc, (u32)~0);
+}
+
 /* Setup free-running counter for clocksource */
 static void __init omap2_gp_clocksource_init(void)
 {
@@ -224,6 +240,8 @@ static void __init omap2_gp_clocksource_init(void)
 
         omap_dm_timer_set_load_start(gpt, 1, 0);
 
+        init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
+
         if (clocksource_register_hz(&clocksource_gpt, tick_rate))
                 printk(err2, clocksource_gpt.name);
 }
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 203dd5a18bd5..058dab4482a1 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p6442/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5P6442 - Memory map definitions
@@ -16,56 +16,61 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P6442_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P6442_PA_CHIPID
+#define S5P6442_PA_SDRAM        0x20000000
 
-#define S5P6442_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5P6442_PA_SYSCON
+#define S5P6442_PA_I2S0         0xC0B00000
+#define S5P6442_PA_I2S1         0xF2200000
 
-#define S5P6442_PA_GPIO         (0xE0200000)
+#define S5P6442_PA_CHIPID       0xE0000000
 
-#define S5P6442_PA_VIC0         (0xE4000000)
-#define S5P6442_PA_VIC1         (0xE4100000)
-#define S5P6442_PA_VIC2         (0xE4200000)
+#define S5P6442_PA_SYSCON       0xE0100000
 
-#define S5P6442_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5P6442_PA_SROMC
+#define S5P6442_PA_GPIO         0xE0200000
 
-#define S5P6442_PA_MDMA         0xE8000000
-#define S5P6442_PA_PDMA         0xE9000000
+#define S5P6442_PA_VIC0         0xE4000000
+#define S5P6442_PA_VIC1         0xE4100000
+#define S5P6442_PA_VIC2         0xE4200000
 
-#define S5P6442_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P6442_PA_TIMER
+#define S5P6442_PA_SROMC        0xE7000000
 
-#define S5P6442_PA_SYSTIMER     (0xEA100000)
+#define S5P6442_PA_MDMA         0xE8000000
+#define S5P6442_PA_PDMA         0xE9000000
 
-#define S5P6442_PA_WATCHDOG     (0xEA200000)
+#define S5P6442_PA_TIMER        0xEA000000
 
-#define S5P6442_PA_UART         (0xEC000000)
+#define S5P6442_PA_SYSTIMER     0xEA100000
 
-#define S5P_PA_UART0            (S5P6442_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5P6442_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5P6442_PA_UART + 0x800)
-#define S5P_SZ_UART             SZ_256
+#define S5P6442_PA_WATCHDOG     0xEA200000
 
-#define S5P6442_PA_IIC0         (0xEC100000)
+#define S5P6442_PA_UART         0xEC000000
 
-#define S5P6442_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5P6442_PA_SDRAM
+#define S5P6442_PA_IIC0         0xEC100000
 
 #define S5P6442_PA_SPI          0xEC300000
 
-/* I2S */
-#define S5P6442_PA_I2S0         0xC0B00000
-#define S5P6442_PA_I2S1         0xF2200000
-
-/* PCM */
 #define S5P6442_PA_PCM0         0xF2400000
 #define S5P6442_PA_PCM1         0xF2500000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
+
+#define S3C_PA_IIC              S5P6442_PA_IIC0
 #define S3C_PA_WDT              S5P6442_PA_WATCHDOG
+
+#define S5P_PA_CHIPID           S5P6442_PA_CHIPID
+#define S5P_PA_SDRAM            S5P6442_PA_SDRAM
+#define S5P_PA_SROMC            S5P6442_PA_SROMC
+#define S5P_PA_SYSCON           S5P6442_PA_SYSCON
+#define S5P_PA_TIMER            S5P6442_PA_TIMER
+
+/* UART */
+
 #define S3C_PA_UART             S5P6442_PA_UART
-#define S3C_PA_IIC              S5P6442_PA_IIC0
+
+#define S5P_PA_UART(x)          (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0            S5P_PA_UART(0)
+#define S5P_PA_UART1            S5P_PA_UART(1)
+#define S5P_PA_UART2            S5P_PA_UART(2)
+
+#define S5P_SZ_UART             SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index a9365e5ba614..95c91257c7ca 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p64x0/include/mach/map.h
  *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * S5P64X0 - Memory map definitions
@@ -16,64 +16,46 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P64X0_PA_SDRAM        (0x20000000)
+#define S5P64X0_PA_SDRAM        0x20000000
 
-#define S5P64X0_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
-
-#define S5P64X0_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
-
-#define S5P64X0_PA_GPIO         (0xE0308000)
-
-#define S5P64X0_PA_VIC0         (0xE4000000)
-#define S5P64X0_PA_VIC1         (0xE4100000)
+#define S5P64X0_PA_CHIPID       0xE0000000
 
-#define S5P64X0_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5P64X0_PA_SROMC
-
-#define S5P64X0_PA_PDMA         (0xE9000000)
-
-#define S5P64X0_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+#define S5P64X0_PA_SYSCON       0xE0100000
 
-#define S5P64X0_PA_RTC          (0xEA100000)
+#define S5P64X0_PA_GPIO         0xE0308000
 
-#define S5P64X0_PA_WDT          (0xEA200000)
+#define S5P64X0_PA_VIC0         0xE4000000
+#define S5P64X0_PA_VIC1         0xE4100000
 
-#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
-#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+#define S5P64X0_PA_SROMC        0xE7000000
 
-#define S5P_PA_UART0            S5P6450_PA_UART(0)
-#define S5P_PA_UART1            S5P6450_PA_UART(1)
-#define S5P_PA_UART2            S5P6450_PA_UART(2)
-#define S5P_PA_UART3            S5P6450_PA_UART(3)
-#define S5P_PA_UART4            S5P6450_PA_UART(4)
-#define S5P_PA_UART5            S5P6450_PA_UART(5)
+#define S5P64X0_PA_PDMA         0xE9000000
 
-#define S5P_SZ_UART             SZ_256
+#define S5P64X0_PA_TIMER        0xEA000000
+#define S5P64X0_PA_RTC          0xEA100000
+#define S5P64X0_PA_WDT          0xEA200000
 
-#define S5P6440_PA_IIC0         (0xEC104000)
-#define S5P6440_PA_IIC1         (0xEC20F000)
-#define S5P6450_PA_IIC0         (0xEC100000)
-#define S5P6450_PA_IIC1         (0xEC200000)
+#define S5P6440_PA_IIC0         0xEC104000
+#define S5P6440_PA_IIC1         0xEC20F000
+#define S5P6450_PA_IIC0         0xEC100000
+#define S5P6450_PA_IIC1         0xEC200000
 
-#define S5P64X0_PA_SPI0         (0xEC400000)
-#define S5P64X0_PA_SPI1         (0xEC500000)
+#define S5P64X0_PA_SPI0         0xEC400000
+#define S5P64X0_PA_SPI1         0xEC500000
 
-#define S5P64X0_PA_HSOTG        (0xED100000)
+#define S5P64X0_PA_HSOTG        0xED100000
 
 #define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
-#define S5P64X0_PA_I2S          (0xF2000000)
+#define S5P64X0_PA_I2S          0xF2000000
 #define S5P6450_PA_I2S1         0xF2800000
 #define S5P6450_PA_I2S2         0xF2900000
 
-#define S5P64X0_PA_PCM          (0xF2100000)
+#define S5P64X0_PA_PCM          0xF2100000
 
-#define S5P64X0_PA_ADC          (0xF3000000)
+#define S5P64X0_PA_ADC          0xF3000000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
 
 #define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
 #define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
@@ -83,6 +65,25 @@
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
 
+#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
+#define S5P_PA_SROMC            S5P64X0_PA_SROMC
+#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
+#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+
 #define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
 
+/* UART */
+
+#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0            S5P6450_PA_UART(0)
+#define S5P_PA_UART1            S5P6450_PA_UART(1)
+#define S5P_PA_UART2            S5P6450_PA_UART(2)
+#define S5P_PA_UART3            S5P6450_PA_UART(3)
+#define S5P_PA_UART4            S5P6450_PA_UART(4)
+#define S5P_PA_UART5            S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART             SZ_256
+
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 328467b346aa..ccbe6b767f7d 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -1,5 +1,8 @@
 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
  *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
@@ -16,145 +19,115 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-/*
- * map-base.h has already defined virtual memory address
- * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
- * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
- * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
- * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
- * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
- * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
- *
- * S5PC100 specific virtual memory address can be defined here
- * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
- *
- */
+#define S5PC100_PA_SDRAM                0x20000000
+
+#define S5PC100_PA_ONENAND              0xE7100000
+#define S5PC100_PA_ONENAND_BUF          0xB0000000
+
+#define S5PC100_PA_CHIPID               0xE0000000
 
-#define S5PC100_PA_ONENAND_BUF  (0xB0000000)
-#define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
+#define S5PC100_PA_SYSCON               0xE0100000
 
-/* Chip ID */
+#define S5PC100_PA_OTHERS               0xE0200000
 
-#define S5PC100_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5PC100_PA_CHIPID
+#define S5PC100_PA_GPIO                 0xE0300000
 
-#define S5PC100_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5PC100_PA_SYSCON
+#define S5PC100_PA_VIC0                 0xE4000000
+#define S5PC100_PA_VIC1                 0xE4100000
+#define S5PC100_PA_VIC2                 0xE4200000
 
-#define S5PC100_PA_OTHERS       (0xE0200000)
-#define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
+#define S5PC100_PA_SROMC                0xE7000000
 
-#define S5PC100_PA_GPIO         (0xE0300000)
-#define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
+#define S5PC100_PA_CFCON                0xE7800000
 
-/* Interrupt */
-#define S5PC100_PA_VIC0         (0xE4000000)
-#define S5PC100_PA_VIC1         (0xE4100000)
-#define S5PC100_PA_VIC2         (0xE4200000)
-#define S5PC100_VA_VIC          S3C_VA_IRQ
-#define S5PC100_VA_VIC_OFFSET   0x10000
-#define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+#define S5PC100_PA_MDMA                 0xE8100000
+#define S5PC100_PA_PDMA0                0xE9000000
+#define S5PC100_PA_PDMA1                0xE9200000
 
-#define S5PC100_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5PC100_PA_SROMC
+#define S5PC100_PA_TIMER                0xEA000000
+#define S5PC100_PA_SYSTIMER             0xEA100000
+#define S5PC100_PA_WATCHDOG             0xEA200000
+#define S5PC100_PA_RTC                  0xEA300000
 
-#define S5PC100_PA_ONENAND      (0xE7100000)
+#define S5PC100_PA_UART                 0xEC000000
 
-#define S5PC100_PA_CFCON        (0xE7800000)
+#define S5PC100_PA_IIC0                 0xEC100000
+#define S5PC100_PA_IIC1                 0xEC200000
 
-/* DMA */
-#define S5PC100_PA_MDMA         (0xE8100000)
-#define S5PC100_PA_PDMA0        (0xE9000000)
-#define S5PC100_PA_PDMA1        (0xE9200000)
+#define S5PC100_PA_SPI0                 0xEC300000
+#define S5PC100_PA_SPI1                 0xEC400000
+#define S5PC100_PA_SPI2                 0xEC500000
 
-/* Timer */
-#define S5PC100_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5PC100_PA_TIMER
+#define S5PC100_PA_USB_HSOTG            0xED200000
+#define S5PC100_PA_USB_HSPHY            0xED300000
 
-#define S5PC100_PA_SYSTIMER     (0xEA100000)
+#define S5PC100_PA_HSMMC(x)             (0xED800000 + ((x) * 0x100000))
 
-#define S5PC100_PA_WATCHDOG     (0xEA200000)
-#define S5PC100_PA_RTC          (0xEA300000)
+#define S5PC100_PA_FB                   0xEE000000
 
-#define S5PC100_PA_UART         (0xEC000000)
+#define S5PC100_PA_FIMC0                0xEE200000
+#define S5PC100_PA_FIMC1                0xEE300000
+#define S5PC100_PA_FIMC2                0xEE400000
 
-#define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
-#define S5P_SZ_UART             SZ_256
+#define S5PC100_PA_I2S0                 0xF2000000
+#define S5PC100_PA_I2S1                 0xF2100000
+#define S5PC100_PA_I2S2                 0xF2200000
 
-#define S5PC100_PA_IIC0         (0xEC100000)
-#define S5PC100_PA_IIC1         (0xEC200000)
+#define S5PC100_PA_AC97                 0xF2300000
 
-/* SPI */
-#define S5PC100_PA_SPI0         0xEC300000
-#define S5PC100_PA_SPI1         0xEC400000
-#define S5PC100_PA_SPI2         0xEC500000
+#define S5PC100_PA_PCM0                 0xF2400000
+#define S5PC100_PA_PCM1                 0xF2500000
 
-/* USB HS OTG */
-#define S5PC100_PA_USB_HSOTG    (0xED200000)
-#define S5PC100_PA_USB_HSPHY    (0xED300000)
+#define S5PC100_PA_SPDIF                0xF2600000
 
-#define S5PC100_PA_FB           (0xEE000000)
+#define S5PC100_PA_TSADC                0xF3000000
 
-#define S5PC100_PA_FIMC0        (0xEE200000)
-#define S5PC100_PA_FIMC1        (0xEE300000)
-#define S5PC100_PA_FIMC2        (0xEE400000)
+#define S5PC100_PA_KEYPAD               0xF3100000
 
-#define S5PC100_PA_I2S0         (0xF2000000)
-#define S5PC100_PA_I2S1         (0xF2100000)
-#define S5PC100_PA_I2S2         (0xF2200000)
+/* Compatibiltiy Defines */
 
-#define S5PC100_PA_AC97         0xF2300000
+#define S3C_PA_FB                       S5PC100_PA_FB
+#define S3C_PA_HSMMC0                   S5PC100_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   S5PC100_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   S5PC100_PA_HSMMC(2)
+#define S3C_PA_IIC                      S5PC100_PA_IIC0
+#define S3C_PA_IIC1                     S5PC100_PA_IIC1
+#define S3C_PA_KEYPAD                   S5PC100_PA_KEYPAD
+#define S3C_PA_ONENAND                  S5PC100_PA_ONENAND
+#define S3C_PA_ONENAND_BUF              S5PC100_PA_ONENAND_BUF
+#define S3C_PA_RTC                      S5PC100_PA_RTC
+#define S3C_PA_TSADC                    S5PC100_PA_TSADC
+#define S3C_PA_USB_HSOTG                S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY                S5PC100_PA_USB_HSPHY
+#define S3C_PA_WDT                      S5PC100_PA_WATCHDOG
 
-/* PCM */
-#define S5PC100_PA_PCM0         0xF2400000
-#define S5PC100_PA_PCM1         0xF2500000
+#define S5P_PA_CHIPID                   S5PC100_PA_CHIPID
+#define S5P_PA_FIMC0                    S5PC100_PA_FIMC0
+#define S5P_PA_FIMC1                    S5PC100_PA_FIMC1
+#define S5P_PA_FIMC2                    S5PC100_PA_FIMC2
+#define S5P_PA_SDRAM                    S5PC100_PA_SDRAM
+#define S5P_PA_SROMC                    S5PC100_PA_SROMC
+#define S5P_PA_SYSCON                   S5PC100_PA_SYSCON
+#define S5P_PA_TIMER                    S5PC100_PA_TIMER
 
-#define S5PC100_PA_SPDIF        0xF2600000
+#define SAMSUNG_PA_ADC                  S5PC100_PA_TSADC
+#define SAMSUNG_PA_CFCON                S5PC100_PA_CFCON
+#define SAMSUNG_PA_KEYPAD               S5PC100_PA_KEYPAD
 
-#define S5PC100_PA_TSADC        (0xF3000000)
+#define S5PC100_VA_OTHERS               (S3C_VA_SYS + 0x10000)
 
-/* KEYPAD */
-#define S5PC100_PA_KEYPAD       (0xF3100000)
+#define S3C_SZ_ONENAND_BUF              (SZ_256M - SZ_32M)
 
-#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+/* UART */
 
-#define S5PC100_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5PC100_PA_SDRAM
+#define S3C_PA_UART                     S5PC100_PA_UART
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5PC100_PA_UART
-#define S3C_PA_IIC              S5PC100_PA_IIC0
-#define S3C_PA_IIC1             S5PC100_PA_IIC1
-#define S3C_PA_FB               S5PC100_PA_FB
-#define S3C_PA_G2D              S5PC100_PA_G2D
-#define S3C_PA_G3D              S5PC100_PA_G3D
-#define S3C_PA_JPEG             S5PC100_PA_JPEG
-#define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
-#define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
-#define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
-#define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
-#define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
-#define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
-#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
-#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
-#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
-#define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
-#define S3C_PA_WDT              S5PC100_PA_WATCHDOG
-#define S3C_PA_TSADC            S5PC100_PA_TSADC
-#define S3C_PA_ONENAND          S5PC100_PA_ONENAND
-#define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
-#define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
-#define S3C_PA_RTC              S5PC100_PA_RTC
-
-#define SAMSUNG_PA_ADC          S5PC100_PA_TSADC
-#define SAMSUNG_PA_CFCON        S5PC100_PA_CFCON
-#define SAMSUNG_PA_KEYPAD       S5PC100_PA_KEYPAD
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
 
-#define S5P_PA_FIMC0            S5PC100_PA_FIMC0
-#define S5P_PA_FIMC1            S5PC100_PA_FIMC1
-#define S5P_PA_FIMC2            S5PC100_PA_FIMC2
+#define S5P_SZ_UART                     SZ_256
 
-#endif /* __ASM_ARCH_C100_MAP_H */
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 3611492ad681..1dd58836fd4f 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv210/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5PV210 - Memory map definitions
@@ -16,122 +16,120 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5PV210_PA_SROM_BANK5   (0xA8000000)
+#define S5PV210_PA_SDRAM                0x20000000
 
-#define S5PC110_PA_ONENAND      (0xB0000000)
-#define S5P_PA_ONENAND          S5PC110_PA_ONENAND
+#define S5PV210_PA_SROM_BANK5           0xA8000000
 
-#define S5PC110_PA_ONENAND_DMA  (0xB0600000)
-#define S5P_PA_ONENAND_DMA      S5PC110_PA_ONENAND_DMA
+#define S5PC110_PA_ONENAND              0xB0000000
+#define S5PC110_PA_ONENAND_DMA          0xB0600000
 
-#define S5PV210_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5PV210_PA_CHIPID
+#define S5PV210_PA_CHIPID               0xE0000000
 
-#define S5PV210_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5PV210_PA_SYSCON
+#define S5PV210_PA_SYSCON               0xE0100000
 
-#define S5PV210_PA_GPIO         (0xE0200000)
+#define S5PV210_PA_GPIO                 0xE0200000
 
-/* SPI */
-#define S5PV210_PA_SPI0         0xE1300000
-#define S5PV210_PA_SPI1         0xE1400000
+#define S5PV210_PA_SPDIF                0xE1100000
 
-#define S5PV210_PA_KEYPAD       (0xE1600000)
+#define S5PV210_PA_SPI0                 0xE1300000
+#define S5PV210_PA_SPI1                 0xE1400000
 
-#define S5PV210_PA_IIC0         (0xE1800000)
-#define S5PV210_PA_IIC1         (0xFAB00000)
-#define S5PV210_PA_IIC2         (0xE1A00000)
+#define S5PV210_PA_KEYPAD               0xE1600000
 
-#define S5PV210_PA_TIMER        (0xE2500000)
-#define S5P_PA_TIMER            S5PV210_PA_TIMER
+#define S5PV210_PA_ADC                  0xE1700000
 
-#define S5PV210_PA_SYSTIMER     (0xE2600000)
+#define S5PV210_PA_IIC0                 0xE1800000
+#define S5PV210_PA_IIC1                 0xFAB00000
+#define S5PV210_PA_IIC2                 0xE1A00000
 
-#define S5PV210_PA_WATCHDOG     (0xE2700000)
+#define S5PV210_PA_AC97                 0xE2200000
 
-#define S5PV210_PA_RTC          (0xE2800000)
-#define S5PV210_PA_UART         (0xE2900000)
+#define S5PV210_PA_PCM0                 0xE2300000
+#define S5PV210_PA_PCM1                 0xE1200000
+#define S5PV210_PA_PCM2                 0xE2B00000
 
-#define S5P_PA_UART0            (S5PV210_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5PV210_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5PV210_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5PV210_PA_UART + 0xC00)
+#define S5PV210_PA_TIMER                0xE2500000
+#define S5PV210_PA_SYSTIMER             0xE2600000
+#define S5PV210_PA_WATCHDOG             0xE2700000
+#define S5PV210_PA_RTC                  0xE2800000
 
-#define S5P_SZ_UART             SZ_256
+#define S5PV210_PA_UART                 0xE2900000
 
-#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S5PV210_PA_SROMC                0xE8000000
 
-#define S5PV210_PA_SROMC        (0xE8000000)
-#define S5P_PA_SROMC            S5PV210_PA_SROMC
+#define S5PV210_PA_CFCON                0xE8200000
 
-#define S5PV210_PA_CFCON        (0xE8200000)
+#define S5PV210_PA_HSMMC(x)             (0xEB000000 + ((x) * 0x100000))
 
-#define S5PV210_PA_MDMA         0xFA200000
-#define S5PV210_PA_PDMA0        0xE0900000
-#define S5PV210_PA_PDMA1        0xE0A00000
+#define S5PV210_PA_HSOTG                0xEC000000
+#define S5PV210_PA_HSPHY                0xEC100000
 
-#define S5PV210_PA_FB           (0xF8000000)
+#define S5PV210_PA_IIS0                 0xEEE30000
+#define S5PV210_PA_IIS1                 0xE2100000
+#define S5PV210_PA_IIS2                 0xE2A00000
 
-#define S5PV210_PA_FIMC0        (0xFB200000)
-#define S5PV210_PA_FIMC1        (0xFB300000)
-#define S5PV210_PA_FIMC2        (0xFB400000)
+#define S5PV210_PA_DMC0                 0xF0000000
+#define S5PV210_PA_DMC1                 0xF1400000
 
-#define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
+#define S5PV210_PA_VIC0                 0xF2000000
+#define S5PV210_PA_VIC1                 0xF2100000
+#define S5PV210_PA_VIC2                 0xF2200000
+#define S5PV210_PA_VIC3                 0xF2300000
 
-#define S5PV210_PA_HSOTG        (0xEC000000)
-#define S5PV210_PA_HSPHY        (0xEC100000)
+#define S5PV210_PA_FB                   0xF8000000
 
-#define S5PV210_PA_VIC0         (0xF2000000)
-#define S5PV210_PA_VIC1         (0xF2100000)
-#define S5PV210_PA_VIC2         (0xF2200000)
-#define S5PV210_PA_VIC3         (0xF2300000)
+#define S5PV210_PA_MDMA                 0xFA200000
+#define S5PV210_PA_PDMA0                0xE0900000
+#define S5PV210_PA_PDMA1                0xE0A00000
 
-#define S5PV210_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5PV210_PA_SDRAM
+#define S5PV210_PA_MIPI_CSIS            0xFA600000
 
-/* S/PDIF */
-#define S5PV210_PA_SPDIF        0xE1100000
+#define S5PV210_PA_FIMC0                0xFB200000
+#define S5PV210_PA_FIMC1                0xFB300000
+#define S5PV210_PA_FIMC2                0xFB400000
 
-/* I2S */
-#define S5PV210_PA_IIS0         0xEEE30000
-#define S5PV210_PA_IIS1         0xE2100000
-#define S5PV210_PA_IIS2         0xE2A00000
+/* Compatibiltiy Defines */
 
-/* PCM */
-#define S5PV210_PA_PCM0         0xE2300000
-#define S5PV210_PA_PCM1         0xE1200000
-#define S5PV210_PA_PCM2         0xE2B00000
+#define S3C_PA_FB                       S5PV210_PA_FB
+#define S3C_PA_HSMMC0                   S5PV210_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   S5PV210_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   S5PV210_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                   S5PV210_PA_HSMMC(3)
+#define S3C_PA_IIC                      S5PV210_PA_IIC0
+#define S3C_PA_IIC1                     S5PV210_PA_IIC1
+#define S3C_PA_IIC2                     S5PV210_PA_IIC2
+#define S3C_PA_RTC                      S5PV210_PA_RTC
+#define S3C_PA_USB_HSOTG                S5PV210_PA_HSOTG
+#define S3C_PA_WDT                      S5PV210_PA_WATCHDOG
 
-/* AC97 */
-#define S5PV210_PA_AC97         0xE2200000
+#define S5P_PA_CHIPID                   S5PV210_PA_CHIPID
+#define S5P_PA_FIMC0                    S5PV210_PA_FIMC0
+#define S5P_PA_FIMC1                    S5PV210_PA_FIMC1
+#define S5P_PA_FIMC2                    S5PV210_PA_FIMC2
+#define S5P_PA_MIPI_CSIS0               S5PV210_PA_MIPI_CSIS
+#define S5P_PA_ONENAND                  S5PC110_PA_ONENAND
+#define S5P_PA_ONENAND_DMA              S5PC110_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                    S5PV210_PA_SDRAM
+#define S5P_PA_SROMC                    S5PV210_PA_SROMC
+#define S5P_PA_SYSCON                   S5PV210_PA_SYSCON
+#define S5P_PA_TIMER                    S5PV210_PA_TIMER
 
-#define S5PV210_PA_ADC          (0xE1700000)
+#define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
+#define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
+#define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
 
-#define S5PV210_PA_DMC0         (0xF0000000)
-#define S5PV210_PA_DMC1         (0xF1400000)
+/* UART */
 
-#define S5PV210_PA_MIPI_CSIS    0xFA600000
+#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5PV210_PA_UART
-#define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
-#define S3C_PA_HSMMC1           S5PV210_PA_HSMMC(1)
-#define S3C_PA_HSMMC2           S5PV210_PA_HSMMC(2)
-#define S3C_PA_HSMMC3           S5PV210_PA_HSMMC(3)
-#define S3C_PA_IIC              S5PV210_PA_IIC0
-#define S3C_PA_IIC1             S5PV210_PA_IIC1
-#define S3C_PA_IIC2             S5PV210_PA_IIC2
-#define S3C_PA_FB               S5PV210_PA_FB
-#define S3C_PA_RTC              S5PV210_PA_RTC
-#define S3C_PA_WDT              S5PV210_PA_WATCHDOG
-#define S3C_PA_USB_HSOTG        S5PV210_PA_HSOTG
-#define S5P_PA_FIMC0            S5PV210_PA_FIMC0
-#define S5P_PA_FIMC1            S5PV210_PA_FIMC1
-#define S5P_PA_FIMC2            S5PV210_PA_FIMC2
-#define S5P_PA_MIPI_CSIS0       S5PV210_PA_MIPI_CSIS
+#define S3C_PA_UART                     S5PV210_PA_UART
 
-#define SAMSUNG_PA_ADC          S5PV210_PA_ADC
-#define SAMSUNG_PA_CFCON        S5PV210_PA_CFCON
-#define SAMSUNG_PA_KEYPAD       S5PV210_PA_KEYPAD
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
+
+#define S5P_SZ_UART                     SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 461aa035afc0..557add4fc56c 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
 
 static struct regulator_init_data aquila_ldo3_data = {
         .constraints    = {
-                .name           = "VUSB/MIPI_1.1V",
+                .name           = "VUSB+MIPI_1.1V",
                 .min_uV         = 1100000,
                 .max_uV         = 1100000,
                 .apply_uV       = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
 
 static struct regulator_init_data aquila_ldo8_data = {
         .constraints    = {
-                .name           = "VUSB/VADC_3.3V",
+                .name           = "VUSB+VADC_3.3V",
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
 
 static struct regulator_init_data aquila_ldo9_data = {
         .constraints    = {
-                .name           = "VCC/VCAM_2.8V",
+                .name           = "VCC+VCAM_2.8V",
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
         .buck1_set1     = S5PV210_GPH0(3),
         .buck1_set2     = S5PV210_GPH0(4),
         .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_max_voltage1 = 1200000,
-        .buck1_max_voltage2 = 1200000,
-        .buck2_max_voltage = 1200000,
+        .buck1_voltage1 = 1200000,
+        .buck1_voltage2 = 1200000,
+        .buck1_voltage3 = 1200000,
+        .buck1_voltage4 = 1200000,
+        .buck2_voltage1 = 1200000,
+        .buck2_voltage2 = 1200000,
 };
 #endif
 
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e22d5112fd44..056f5c769b0a 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
 
 static struct regulator_init_data goni_ldo3_data = {
         .constraints    = {
-                .name           = "VUSB/MIPI_1.1V",
+                .name           = "VUSB+MIPI_1.1V",
                 .min_uV         = 1100000,
                 .max_uV         = 1100000,
                 .apply_uV       = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
 
 static struct regulator_init_data goni_ldo8_data = {
         .constraints    = {
-                .name           = "VUSB/VADC_3.3V",
+                .name           = "VUSB+VADC_3.3V",
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
 
 static struct regulator_init_data goni_ldo9_data = {
         .constraints    = {
-                .name           = "VCC/VCAM_2.8V",
+                .name           = "VCC+VCAM_2.8V",
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
         .buck1_set1     = S5PV210_GPH0(3),
         .buck1_set2     = S5PV210_GPH0(4),
         .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_max_voltage1 = 1200000,
-        .buck1_max_voltage2 = 1200000,
-        .buck2_max_voltage = 1200000,
+        .buck1_voltage1 = 1200000,
+        .buck1_voltage2 = 1200000,
+        .buck1_voltage3 = 1200000,
+        .buck1_voltage4 = 1200000,
+        .buck2_voltage1 = 1200000,
+        .buck2_voltage2 = 1200000,
 };
 #endif
 
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 3060f78e12ab..901657fa7a12 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv310/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5PV310 - Memory map definitions
@@ -23,90 +23,43 @@
 
 #include <plat/map-s5p.h>
 
-#define S5PV310_PA_SYSRAM               (0x02025000)
+#define S5PV310_PA_SYSRAM               0x02025000
 
-#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-
-#define S5PC210_PA_ONENAND              (0x0C000000)
-#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
-
-#define S5PC210_PA_ONENAND_DMA          (0x0C600000)
-#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
-
-#define S5PV310_PA_CHIPID               (0x10000000)
-#define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
-
-#define S5PV310_PA_SYSCON               (0x10010000)
-#define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
+#define S5PV310_PA_I2S0                 0x03830000
+#define S5PV310_PA_I2S1                 0xE3100000
+#define S5PV310_PA_I2S2                 0xE2A00000
 
-#define S5PV310_PA_PMU                  (0x10020000)
+#define S5PV310_PA_PCM0                 0x03840000
+#define S5PV310_PA_PCM1                 0x13980000
+#define S5PV310_PA_PCM2                 0x13990000
 
-#define S5PV310_PA_CMU                  (0x10030000)
-
-#define S5PV310_PA_WATCHDOG             (0x10060000)
-#define S5PV310_PA_RTC                  (0x10070000)
-
-#define S5PV310_PA_DMC0                 (0x10400000)
-
-#define S5PV310_PA_COMBINER             (0x10448000)
-
-#define S5PV310_PA_COREPERI             (0x10500000)
-#define S5PV310_PA_GIC_CPU              (0x10500100)
-#define S5PV310_PA_TWD                  (0x10500600)
-#define S5PV310_PA_GIC_DIST             (0x10501000)
-#define S5PV310_PA_L2CC                 (0x10502000)
-
-/* DMA */
-#define S5PV310_PA_MDMA         0x10810000
-#define S5PV310_PA_PDMA0        0x12680000
-#define S5PV310_PA_PDMA1        0x12690000
-
-#define S5PV310_PA_GPIO1                (0x11400000)
-#define S5PV310_PA_GPIO2                (0x11000000)
-#define S5PV310_PA_GPIO3                (0x03860000)
-
-#define S5PV310_PA_MIPI_CSIS0           0x11880000
-#define S5PV310_PA_MIPI_CSIS1           0x11890000
+#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
 
-#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+#define S5PC210_PA_ONENAND              0x0C000000
+#define S5PC210_PA_ONENAND_DMA          0x0C600000
 
-#define S5PV310_PA_SROMC                (0x12570000)
-#define S5P_PA_SROMC                    S5PV310_PA_SROMC
+#define S5PV310_PA_CHIPID               0x10000000
 
-/* S/PDIF */
-#define S5PV310_PA_SPDIF        0xE1100000
+#define S5PV310_PA_SYSCON               0x10010000
+#define S5PV310_PA_PMU                  0x10020000
+#define S5PV310_PA_CMU                  0x10030000
 
-/* I2S */
-#define S5PV310_PA_I2S0         0x03830000
-#define S5PV310_PA_I2S1         0xE3100000
-#define S5PV310_PA_I2S2         0xE2A00000
+#define S5PV310_PA_WATCHDOG             0x10060000
+#define S5PV310_PA_RTC                  0x10070000
 
-/* PCM */
-#define S5PV310_PA_PCM0         0x03840000
-#define S5PV310_PA_PCM1         0x13980000
-#define S5PV310_PA_PCM2         0x13990000
+#define S5PV310_PA_DMC0                 0x10400000
 
-/* AC97 */
-#define S5PV310_PA_AC97         0x139A0000
+#define S5PV310_PA_COMBINER             0x10448000
 
-#define S5PV310_PA_UART                 (0x13800000)
+#define S5PV310_PA_COREPERI             0x10500000
+#define S5PV310_PA_GIC_CPU              0x10500100
+#define S5PV310_PA_TWD                  0x10500600
+#define S5PV310_PA_GIC_DIST             0x10501000
+#define S5PV310_PA_L2CC                 0x10502000
 
-#define S5P_PA_UART(x)                  (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-#define S5P_PA_UART4                    S5P_PA_UART(4)
-
-#define S5P_SZ_UART                     SZ_256
-
-#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-
-#define S5PV310_PA_TIMER                (0x139D0000)
-#define S5P_PA_TIMER                    S5PV310_PA_TIMER
-
-#define S5PV310_PA_SDRAM                (0x40000000)
-#define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
+#define S5PV310_PA_MDMA                 0x10810000
+#define S5PV310_PA_PDMA0                0x12680000
+#define S5PV310_PA_PDMA1                0x12690000
 
 #define S5PV310_PA_SYSMMU_MDMA          0x10A40000
 #define S5PV310_PA_SYSMMU_SSS           0x10A50000
@@ -125,8 +78,31 @@
 #define S5PV310_PA_SYSMMU_MFC_L         0x13620000
 #define S5PV310_PA_SYSMMU_MFC_R         0x13630000
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART                     S5PV310_PA_UART
+#define S5PV310_PA_GPIO1                0x11400000
+#define S5PV310_PA_GPIO2                0x11000000
+#define S5PV310_PA_GPIO3                0x03860000
+
+#define S5PV310_PA_MIPI_CSIS0           0x11880000
+#define S5PV310_PA_MIPI_CSIS1           0x11890000
+
+#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+
+#define S5PV310_PA_SROMC                0x12570000
+
+#define S5PV310_PA_UART                 0x13800000
+
+#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+
+#define S5PV310_PA_AC97                 0x139A0000
+
+#define S5PV310_PA_TIMER                0x139D0000
+
+#define S5PV310_PA_SDRAM                0x40000000
+
+#define S5PV310_PA_SPDIF                0xE1100000
+
+/* Compatibiltiy Defines */
+
 #define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
 #define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
 #define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
@@ -141,7 +117,28 @@
 #define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
 #define S3C_PA_RTC                      S5PV310_PA_RTC
 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
+
+#define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 #define S5P_PA_MIPI_CSIS0               S5PV310_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1               S5PV310_PA_MIPI_CSIS1
+#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
+#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
+#define S5P_PA_SROMC                    S5PV310_PA_SROMC
+#define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
+#define S5P_PA_TIMER                    S5PV310_PA_TIMER
+
+/* UART */
+
+#define S3C_PA_UART                     S5PV310_PA_UART
+
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
+#define S5P_PA_UART4                    S5P_PA_UART(4)
+
+#define S5P_SZ_UART                     SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958cd..53677e464d4b 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -62,7 +62,7 @@
 #define SPEAR320_SMII1_BASE             0xAB000000
 #define SPEAR320_SMII1_SIZE             0x01000000
 
-#define SPEAR320_SOC_CONFIG_BASE        0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE        0xB3000000
 #define SPEAR320_SOC_CONFIG_SIZE        0x00000070
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 66ad2760c621..04c779832c78 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -57,5 +57,6 @@ struct tegra_kbc_platform_data {
         const struct matrix_keymap_data *keymap_data;
 
         bool wakeup;
+        bool use_fn_map;
 };
 #endif
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb95866..f2ce38e085d2 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
 static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
+
+#ifdef CONFIG_ARM_ERRATA_753970
+        /* write to an unmmapped register */
+        writel_relaxed(0, base + L2X0_DUMMY_REG);
+#else
         writel_relaxed(0, base + L2X0_CACHE_SYNC);
+#endif
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b56b4e..8e3356239136 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -264,6 +264,12 @@ __v7_setup:
         orreq   r10, r10, #1 << 6               @ set bit #6
         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_751472
+        cmp     r6, #0x30                       @ present prior to r3p0
+        mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orrlt   r10, r10, #1 << 11              @ set bit #11
+        mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
 
 3:      mov     r10, #0
 #ifdef HARVARD_CACHE
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index fc62fb5fc20b..c9122dd6ee8d 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -37,14 +37,16 @@ static struct clk_functions *arch_clock;
 int clk_enable(struct clk *clk)
 {
         unsigned long flags;
-        int ret = 0;
+        int ret;
 
         if (clk == NULL || IS_ERR(clk))
                 return -EINVAL;
 
+        if (!arch_clock || !arch_clock->clk_enable)
+                return -EINVAL;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_enable)
-                ret = arch_clock->clk_enable(clk);
+        ret = arch_clock->clk_enable(clk);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -58,6 +60,9 @@ void clk_disable(struct clk *clk)
         if (clk == NULL || IS_ERR(clk))
                 return;
 
+        if (!arch_clock || !arch_clock->clk_disable)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->usecount == 0) {
                 pr_err("Trying disable clock %s with 0 usecount\n",
@@ -66,8 +71,7 @@ void clk_disable(struct clk *clk)
                 goto out;
         }
 
-        if (arch_clock->clk_disable)
-                arch_clock->clk_disable(clk);
+        arch_clock->clk_disable(clk);
 
 out:
         spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -77,7 +81,7 @@ EXPORT_SYMBOL(clk_disable);
 unsigned long clk_get_rate(struct clk *clk)
 {
         unsigned long flags;
-        unsigned long ret = 0;
+        unsigned long ret;
 
         if (clk == NULL || IS_ERR(clk))
                 return 0;
@@ -97,14 +101,16 @@ EXPORT_SYMBOL(clk_get_rate);
 long clk_round_rate(struct clk *clk, unsigned long rate)
 {
         unsigned long flags;
-        long ret = 0;
+        long ret;
 
         if (clk == NULL || IS_ERR(clk))
-                return ret;
+                return 0;
+
+        if (!arch_clock || !arch_clock->clk_round_rate)
+                return 0;
 
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_round_rate)
-                ret = arch_clock->clk_round_rate(clk, rate);
+        ret = arch_clock->clk_round_rate(clk, rate);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -119,14 +125,13 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
         if (clk == NULL || IS_ERR(clk))
                 return ret;
 
+        if (!arch_clock || !arch_clock->clk_set_rate)
+                return ret;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_set_rate)
-                ret = arch_clock->clk_set_rate(clk, rate);
-        if (ret == 0) {
-                if (clk->recalc)
-                        clk->rate = clk->recalc(clk);
+        ret = arch_clock->clk_set_rate(clk, rate);
+        if (ret == 0)
                 propagate_rate(clk);
-        }
         spin_unlock_irqrestore(&clockfw_lock, flags);
 
         return ret;
@@ -141,15 +146,14 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
         if (clk == NULL || IS_ERR(clk) || parent == NULL || IS_ERR(parent))
                 return ret;
 
+        if (!arch_clock || !arch_clock->clk_set_parent)
+                return ret;
+
         spin_lock_irqsave(&clockfw_lock, flags);
         if (clk->usecount == 0) {
-                if (arch_clock->clk_set_parent)
-                        ret = arch_clock->clk_set_parent(clk, parent);
-                if (ret == 0) {
-                        if (clk->recalc)
-                                clk->rate = clk->recalc(clk);
+                ret = arch_clock->clk_set_parent(clk, parent);
+                if (ret == 0)
                         propagate_rate(clk);
-                }
         } else
                 ret = -EBUSY;
         spin_unlock_irqrestore(&clockfw_lock, flags);
@@ -335,6 +339,38 @@ struct clk *omap_clk_get_by_name(const char *name)
         return ret;
 }
 
+int omap_clk_enable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->allow_idle)
+                        c->ops->allow_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
+int omap_clk_disable_autoidle_all(void)
+{
+        struct clk *c;
+        unsigned long flags;
+
+        spin_lock_irqsave(&clockfw_lock, flags);
+
+        list_for_each_entry(c, &clocks, node)
+                if (c->ops->deny_idle)
+                        c->ops->deny_idle(c);
+
+        spin_unlock_irqrestore(&clockfw_lock, flags);
+
+        return 0;
+}
+
 /*
  * Low level helpers
  */
@@ -367,9 +403,11 @@ void clk_init_cpufreq_table(struct cpufreq_frequency_table **table)
 {
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_init_cpufreq_table)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_init_cpufreq_table)
-                arch_clock->clk_init_cpufreq_table(table);
+        arch_clock->clk_init_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 
@@ -377,9 +415,11 @@ void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table)
 {
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_exit_cpufreq_table)
+                return;
+
         spin_lock_irqsave(&clockfw_lock, flags);
-        if (arch_clock->clk_exit_cpufreq_table)
-                arch_clock->clk_exit_cpufreq_table(table);
+        arch_clock->clk_exit_cpufreq_table(table);
         spin_unlock_irqrestore(&clockfw_lock, flags);
 }
 #endif
@@ -397,6 +437,9 @@ static int __init clk_disable_unused(void)
         struct clk *ck;
         unsigned long flags;
 
+        if (!arch_clock || !arch_clock->clk_disable_unused)
+                return 0;
+
         pr_info("clock: disabling unused clocks to save power\n");
         list_for_each_entry(ck, &clocks, node) {
                 if (ck->ops == &clkops_null)
@@ -406,14 +449,14 @@ static int __init clk_disable_unused(void)
                         continue;
 
                 spin_lock_irqsave(&clockfw_lock, flags);
-                if (arch_clock->clk_disable_unused)
-                        arch_clock->clk_disable_unused(ck);
+                arch_clock->clk_disable_unused(ck);
                 spin_unlock_irqrestore(&clockfw_lock, flags);
         }
 
         return 0;
 }
 late_initcall(clk_disable_unused);
+late_initcall(omap_clk_enable_autoidle_all);
 #endif
 
 int __init clk_init(struct clk_functions * custom_clocks)
diff --git a/arch/arm/plat-omap/cpu-omap.c b/arch/arm/plat-omap/cpu-omap.c
index 11c54ec8d47f..da4f68dbba1d 100644
--- a/arch/arm/plat-omap/cpu-omap.c
+++ b/arch/arm/plat-omap/cpu-omap.c
@@ -101,7 +101,7 @@ static int omap_target(struct cpufreq_policy *policy,
         return ret;
 }
 
-static int __init omap_cpu_init(struct cpufreq_policy *policy)
+static int __cpuinit omap_cpu_init(struct cpufreq_policy *policy)
 {
         int result = 0;
 
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 10245b837c10..7d9f815cedec 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -35,8 +35,8 @@
 
 static struct platform_device **omap_mcbsp_devices;
 
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size)
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
 {
         int i;
 
@@ -54,6 +54,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
                 if (!new_mcbsp)
                         continue;
+                platform_device_add_resources(new_mcbsp, &res[i * res_count],
+                                        res_count);
                 new_mcbsp->dev.platform_data = &config[i];
                 ret = platform_device_add(new_mcbsp);
                 if (ret) {
@@ -65,8 +67,8 @@ void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
 }
 
 #else
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size)
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size)
 {  }
 #endif
 
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 1d706cf63ca0..ee9f6ebba29b 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -342,6 +342,10 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
         l |= 0x02 << 3;  /* Set to smart-idle mode */
         l |= 0x2 << 8;   /* Set clock activity to perserve f-clock on idle */
 
+        /* Enable autoidle on OMAP2 / OMAP3 */
+        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+                l |= 0x1 << 0;
+
         /*
          * Enable wake-up on OMAP2 CPUs.
          */
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d43e6234dbbb..006e599c6613 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -25,6 +25,8 @@ struct clockdomain;
  * @disable: fn ptr that enables the current clock in hardware
  * @find_idlest: function returning the IDLEST register for the clock's IP blk
  * @find_companion: function returning the "companion" clk reg for the clock
+ * @allow_idle: fn ptr that enables autoidle for the current clock in hardware
+ * @deny_idle: fn ptr that disables autoidle for the current clock in hardware
  *
  * A "companion" clk is an accompanying clock to the one being queried
  * that must be enabled for the IP module connected to the clock to
@@ -42,6 +44,8 @@ struct clkops {
                                                u8 *, u8 *);
         void                    (*find_companion)(struct clk *, void __iomem **,
                                                   u8 *);
+        void                    (*allow_idle)(struct clk *);
+        void                    (*deny_idle)(struct clk *);
 };
 
 #ifdef CONFIG_ARCH_OMAP2PLUS
@@ -105,7 +109,6 @@ struct clksel {
  * @clk_ref: struct clk pointer to the clock's reference clock input
  * @control_reg: register containing the DPLL mode bitfield
  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
- * @rate_tolerance: maximum variance allowed from target rate (in Hz)
  * @last_rounded_rate: cache of the last rate result of omap2_dpll_round_rate()
  * @last_rounded_m: cache of the last M result of omap2_dpll_round_rate()
  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
@@ -131,12 +134,9 @@ struct clksel {
  * XXX Some DPLLs have multiple bypass inputs, so it's not technically
  * correct to only have one @clk_bypass pointer.
  *
- * XXX @rate_tolerance should probably be deprecated - currently there
- * don't seem to be any usecases for DPLL rounding that is not exact.
- *
  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
  * @last_rounded_n) should be separated from the runtime-fixed fields
- * and placed into a differenct structure, so that the runtime-fixed data
+ * and placed into a different structure, so that the runtime-fixed data
  * can be placed into read-only space.
  */
 struct dpll_data {
@@ -147,7 +147,6 @@ struct dpll_data {
         struct clk              *clk_ref;
         void __iomem            *control_reg;
         u32                     enable_mask;
-        unsigned int            rate_tolerance;
         unsigned long           last_rounded_rate;
         u16                     last_rounded_m;
         u16                     max_multiplier;
@@ -172,12 +171,24 @@ struct dpll_data {
 
 #endif
 
-/* struct clk.flags possibilities */
+/*
+ * struct clk.flags possibilities
+ *
+ * XXX document the rest of the clock flags here
+ *
+ * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
+ *     bits share the same register.  This flag allows the
+ *     omap4_dpllmx*() code to determine which GATE_CTRL bit field
+ *     should be used.  This is a temporary solution - a better approach
+ *     would be to associate clock type-specific data with the clock,
+ *     similar to the struct dpll_data approach.
+ */
 #define ENABLE_REG_32BIT        (1 << 0)        /* Use 32-bit access */
 #define CLOCK_IDLE_CONTROL      (1 << 1)
 #define CLOCK_NO_IDLE_PARENT    (1 << 2)
 #define ENABLE_ON_INIT          (1 << 3)        /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 4)        /* 0 enables, 1 disables */
+#define CLOCK_CLKOUTX2          (1 << 5)
 
 /**
  * struct clk - OMAP struct clk
@@ -293,6 +304,8 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 extern void clk_exit_cpufreq_table(struct cpufreq_frequency_table **table);
 #endif
 extern struct clk *omap_clk_get_by_name(const char *name);
+extern int omap_clk_enable_autoidle_all(void);
+extern int omap_clk_disable_autoidle_all(void);
 
 extern const struct clkops clkops_null;
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index be99438d385e..8198bb6cdb5e 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -5,7 +5,7 @@
  *
  * Copyright (C) 2004, 2008 Nokia Corporation
  *
- * Copyright (C) 2009 Texas Instruments.
+ * Copyright (C) 2009-11 Texas Instruments.
  *
  * Written by Tony Lindgren <tony.lindgren@nokia.com>
  *
@@ -405,8 +405,10 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define TI8168_REV_ES1_1        (TI816X_CLASS | (OMAP_REVBITS_01 << 8))
 
 #define OMAP443X_CLASS          0x44300044
-#define OMAP4430_REV_ES1_0      OMAP443X_CLASS
-#define OMAP4430_REV_ES2_0      0x44301044
+#define OMAP4430_REV_ES1_0      (OMAP443X_CLASS | (0x10 << 8))
+#define OMAP4430_REV_ES2_0      (OMAP443X_CLASS | (0x20 << 8))
+#define OMAP4430_REV_ES2_1      (OMAP443X_CLASS | (0x21 << 8))
+#define OMAP4430_REV_ES2_2      (OMAP443X_CLASS | (0x22 << 8))
 
 /*
  * omap_chip bits
@@ -434,12 +436,16 @@ IS_OMAP_TYPE(3517, 0x3517)
 #define CHIP_IS_OMAP3630ES1_1           (1 << 9)
 #define CHIP_IS_OMAP3630ES1_2           (1 << 10)
 #define CHIP_IS_OMAP4430ES2             (1 << 11)
+#define CHIP_IS_OMAP4430ES2_1           (1 << 12)
+#define CHIP_IS_OMAP4430ES2_2           (1 << 13)
 #define CHIP_IS_TI816X                  (1 << 14)
 
 #define CHIP_IS_OMAP24XX                (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
 
-#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 | \
-                                                 CHIP_IS_OMAP4430ES2)
+#define CHIP_IS_OMAP4430                (CHIP_IS_OMAP4430ES1 |          \
+                                         CHIP_IS_OMAP4430ES2 |          \
+                                         CHIP_IS_OMAP4430ES2_1 |        \
+                                         CHIP_IS_OMAP4430ES2_2)
 
 /*
  * "GE" here represents "greater than or equal to" in terms of ES
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
index 537f4e449f50..0f140ecedb01 100644
--- a/arch/arm/plat-omap/include/plat/display.h
+++ b/arch/arm/plat-omap/include/plat/display.h
@@ -23,6 +23,7 @@
 #include <linux/list.h>
 #include <linux/kobject.h>
 #include <linux/device.h>
+#include <linux/platform_device.h>
 #include <asm/atomic.h>
 
 #define DISPC_IRQ_FRAMEDONE             (1 << 0)
@@ -226,6 +227,16 @@ struct omap_dss_board_info {
         struct omap_dss_device *default_device;
 };
 
+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
+/* Init with the board info */
+extern int omap_display_init(struct omap_dss_board_info *board_data);
+#else
+static inline int omap_display_init(struct omap_dss_board_info *board_data)
+{
+        return 0;
+}
+#endif
+
 struct omap_video_timings {
         /* Unit: pixels */
         u16 x_res;
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dfa3aff9761b..d6c70d2f4030 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -3,6 +3,12 @@
  *
  * OMAP Dual-Mode Timers
  *
+ * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
+ * Tarun Kanti DebBarma <tarun.kanti@ti.com>
+ * Thara Gopinath <thara@ti.com>
+ *
+ * Platform device conversion and hwmod support.
+ *
  * Copyright (C) 2005 Nokia Corporation
  * Author: Lauri Leukkunen <lauri.leukkunen@nokia.com>
  * PWM and clock framwork support by Timo Teras.
@@ -44,6 +50,11 @@
 #define OMAP_TIMER_TRIGGER_OVERFLOW             0x01
 #define OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE 0x02
 
+/*
+ * IP revision identifier so that Highlander IP
+ * in OMAP4 can be distinguished.
+ */
+#define OMAP_TIMER_IP_VERSION_1                        0x1
 struct omap_dm_timer;
 extern struct omap_dm_timer *gptimer_wakeup;
 extern struct sys_timer omap_timer;
diff --git a/arch/arm/plat-omap/include/plat/gpmc.h b/arch/arm/plat-omap/include/plat/gpmc.h
index 85ded598853e..12b316165037 100644
--- a/arch/arm/plat-omap/include/plat/gpmc.h
+++ b/arch/arm/plat-omap/include/plat/gpmc.h
@@ -41,6 +41,8 @@
 #define GPMC_NAND_ADDRESS       0x0000000b
 #define GPMC_NAND_DATA          0x0000000c
 
+#define GPMC_ENABLE_IRQ         0x0000000d
+
 /* ECC commands */
 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
@@ -78,6 +80,19 @@
 #define WR_RD_PIN_MONITORING            0x00600000
 #define GPMC_PREFETCH_STATUS_FIFO_CNT(val)      ((val >> 24) & 0x7F)
 #define GPMC_PREFETCH_STATUS_COUNT(val) (val & 0x00003fff)
+#define GPMC_IRQ_FIFOEVENTENABLE        0x01
+#define GPMC_IRQ_COUNT_EVENT            0x02
+
+#define PREFETCH_FIFOTHRESHOLD_MAX      0x40
+#define PREFETCH_FIFOTHRESHOLD(val)     ((val) << 8)
+
+enum omap_ecc {
+                /* 1-bit ecc: stored at end of spare area */
+        OMAP_ECC_HAMMING_CODE_DEFAULT = 0, /* Default, s/w method */
+        OMAP_ECC_HAMMING_CODE_HW, /* gpmc to detect the error */
+                /* 1-bit ecc: stored at begining of spare area as romcode */
+        OMAP_ECC_HAMMING_CODE_HW_ROMCODE, /* gpmc method & romcode layout */
+};
 
 /*
  * Note that all values in this struct are in nanoseconds except sync_clk
@@ -130,12 +145,11 @@ extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
 extern void gpmc_cs_free(int cs);
 extern int gpmc_cs_set_reserved(int cs, int reserved);
 extern int gpmc_cs_reserved(int cs);
-extern int gpmc_prefetch_enable(int cs, int dma_mode,
+extern int gpmc_prefetch_enable(int cs, int fifo_th, int dma_mode,
                                         unsigned int u32_count, int is_write);
 extern int gpmc_prefetch_reset(int cs);
 extern void omap3_gpmc_save_context(void);
 extern void omap3_gpmc_restore_context(void);
-extern void gpmc_init(void);
 extern int gpmc_read_status(int cmd);
 extern int gpmc_cs_configure(int cs, int cmd, int wval);
 extern int gpmc_nand_read(int cs, int cmd);
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 69230d685538..174f1b9c8c03 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -31,6 +31,7 @@ struct iommu {
         struct clk      *clk;
         void __iomem    *regbase;
         struct device   *dev;
+        void            *isr_priv;
 
         unsigned int    refcount;
         struct mutex    iommu_lock;     /* global for this whole object */
@@ -47,7 +48,7 @@ struct iommu {
         struct list_head        mmap;
         struct mutex            mmap_lock; /* protect mmap */
 
-        int (*isr)(struct iommu *obj);
+        int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs, void *priv);
 
         void *ctx; /* iommu context: registres saved area */
         u32 da_start;
@@ -109,6 +110,13 @@ struct iommu_platform_data {
         u32 da_end;
 };
 
+/* IOMMU errors */
+#define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
+#define OMAP_IOMMU_ERR_TRANS_FAULT      (1 << 1)
+#define OMAP_IOMMU_ERR_EMU_MISS         (1 << 2)
+#define OMAP_IOMMU_ERR_TBLWALK_FAULT    (1 << 3)
+#define OMAP_IOMMU_ERR_MULTIHIT_FAULT   (1 << 4)
+
 #if defined(CONFIG_ARCH_OMAP1)
 #error "iommu for this processor not implemented yet"
 #else
@@ -154,11 +162,17 @@ extern void flush_iotlb_range(struct iommu *obj, u32 start, u32 end);
 extern void flush_iotlb_all(struct iommu *obj);
 
 extern int iopgtable_store_entry(struct iommu *obj, struct iotlb_entry *e);
+extern void iopgtable_lookup_entry(struct iommu *obj, u32 da, u32 **ppgd,
+                                   u32 **ppte);
 extern size_t iopgtable_clear_entry(struct iommu *obj, u32 iova);
 
 extern int iommu_set_da_range(struct iommu *obj, u32 start, u32 end);
 extern struct iommu *iommu_get(const char *name);
 extern void iommu_put(struct iommu *obj);
+extern int iommu_set_isr(const char *name,
+                         int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                                    void *priv),
+                         void *isr_priv);
 
 extern void iommu_save_ctx(struct iommu *obj);
 extern void iommu_restore_ctx(struct iommu *obj);
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 2910de921c52..d77928370463 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -315,9 +315,12 @@
 #define INT_34XX_SSM_ABORT_IRQ  6
 #define INT_34XX_SYS_NIRQ       7
 #define INT_34XX_D2D_FW_IRQ     8
+#define INT_34XX_L3_DBG_IRQ     9
+#define INT_34XX_L3_APP_IRQ     10
 #define INT_34XX_PRCM_MPU_IRQ   11
 #define INT_34XX_MCBSP1_IRQ     16
 #define INT_34XX_MCBSP2_IRQ     17
+#define INT_34XX_GPMC_IRQ       20
 #define INT_34XX_MCBSP3_IRQ     22
 #define INT_34XX_MCBSP4_IRQ     23
 #define INT_34XX_CAM_IRQ        24
@@ -411,7 +414,13 @@
 #define TWL_IRQ_END             TWL6030_IRQ_END
 #endif
 
-#define NR_IRQS                 TWL_IRQ_END
+/* GPMC related */
+#define OMAP_GPMC_IRQ_BASE      (TWL_IRQ_END)
+#define OMAP_GPMC_NR_IRQS       7
+#define OMAP_GPMC_IRQ_END       (OMAP_GPMC_IRQ_BASE + OMAP_GPMC_NR_IRQS)
+
+
+#define NR_IRQS                 OMAP_GPMC_IRQ_END
 
 #define OMAP_IRQ_BIT(irq)       (1 << ((irq) % 32))
 
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index 6ecf1051e5f4..f8f690ab2997 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -37,6 +37,10 @@ static struct platform_device omap_mcbsp##port_nr = {	\
         .id     = OMAP_MCBSP##port_nr,                  \
 }
 
+#define MCBSP_CONFIG_TYPE2      0x2
+#define MCBSP_CONFIG_TYPE3      0x3
+#define MCBSP_CONFIG_TYPE4      0x4
+
 #define OMAP7XX_MCBSP1_BASE     0xfffb1000
 #define OMAP7XX_MCBSP2_BASE     0xfffb1800
 
@@ -48,32 +52,14 @@ static struct platform_device omap_mcbsp##port_nr = {	\
 #define OMAP1610_MCBSP2_BASE    0xfffb1000
 #define OMAP1610_MCBSP3_BASE    0xe1017000
 
-#define OMAP24XX_MCBSP1_BASE    0x48074000
-#define OMAP24XX_MCBSP2_BASE    0x48076000
-#define OMAP2430_MCBSP3_BASE    0x4808c000
-#define OMAP2430_MCBSP4_BASE    0x4808e000
-#define OMAP2430_MCBSP5_BASE    0x48096000
-
-#define OMAP34XX_MCBSP1_BASE    0x48074000
-#define OMAP34XX_MCBSP2_BASE    0x49022000
-#define OMAP34XX_MCBSP2_ST_BASE 0x49028000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP3_ST_BASE 0x4902A000
-#define OMAP34XX_MCBSP3_BASE    0x49024000
-#define OMAP34XX_MCBSP4_BASE    0x49026000
-#define OMAP34XX_MCBSP5_BASE    0x48096000
-
-#define OMAP44XX_MCBSP1_BASE    0x49022000
-#define OMAP44XX_MCBSP2_BASE    0x49024000
-#define OMAP44XX_MCBSP3_BASE    0x49026000
-#define OMAP44XX_MCBSP4_BASE    0x48096000
-
-#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
+#ifdef CONFIG_ARCH_OMAP1
 
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x02
 #define OMAP_MCBSP_REG_DXR2     0x04
 #define OMAP_MCBSP_REG_DXR1     0x06
+#define OMAP_MCBSP_REG_DRR      0x02
+#define OMAP_MCBSP_REG_DXR      0x06
 #define OMAP_MCBSP_REG_SPCR2    0x08
 #define OMAP_MCBSP_REG_SPCR1    0x0a
 #define OMAP_MCBSP_REG_RCR2     0x0c
@@ -414,8 +400,9 @@ struct omap_mcbsp_platform_data {
 #ifdef CONFIG_ARCH_OMAP3
         /* Sidetone block for McBSP 2 and 3 */
         unsigned long phys_base_st;
-        u16 buffer_size;
 #endif
+        u16 buffer_size;
+        unsigned int mcbsp_config_type;
 };
 
 struct omap_mcbsp_st_data {
@@ -431,6 +418,7 @@ struct omap_mcbsp_st_data {
 struct omap_mcbsp {
         struct device *dev;
         unsigned long phys_base;
+        unsigned long phys_dma_base;
         void __iomem *io_base;
         u8 id;
         u8 free;
@@ -457,7 +445,6 @@ struct omap_mcbsp {
         /* Protect the field .free, while checking if the mcbsp is in use */
         spinlock_t lock;
         struct omap_mcbsp_platform_data *pdata;
-        struct clk *iclk;
         struct clk *fclk;
 #ifdef CONFIG_ARCH_OMAP3
         struct omap_mcbsp_st_data *st_data;
@@ -466,7 +453,17 @@ struct omap_mcbsp {
         u16 max_rx_thres;
 #endif
         void *reg_cache;
+        unsigned int mcbsp_config_type;
 };
+
+/**
+ * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
+ * @sidetone: name of the sidetone device
+ */
+struct omap_mcbsp_dev_attr {
+        const char *sidetone;
+};
+
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 
@@ -474,8 +471,8 @@ extern int omap_mcbsp_count, omap_mcbsp_cache_size;
 #define id_to_mcbsp_ptr(id)             mcbsp_ptr[id];
 
 int omap_mcbsp_init(void);
-void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
-                                        int size);
+void omap_mcbsp_register_board_cfg(struct resource *res, int res_count,
+                        struct omap_mcbsp_platform_data *config, int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
 #ifdef CONFIG_ARCH_OMAP3
 void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
@@ -525,6 +522,9 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
 void omap2_mcbsp1_mux_clkr_src(u8 mux);
 void omap2_mcbsp1_mux_fsr_src(u8 mux);
 
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
+
 #ifdef CONFIG_ARCH_OMAP3
 /* Sidetone specific API */
 int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
diff --git a/arch/arm/plat-omap/include/plat/mmc.h b/arch/arm/plat-omap/include/plat/mmc.h
index f57f36abb07e..f38fef9f1310 100644
--- a/arch/arm/plat-omap/include/plat/mmc.h
+++ b/arch/arm/plat-omap/include/plat/mmc.h
@@ -24,25 +24,19 @@
 #define OMAP1_MMC2_BASE         0xfffb7c00      /* omap16xx only */
 
 #define OMAP24XX_NR_MMC         2
-#define OMAP34XX_NR_MMC         3
-#define OMAP44XX_NR_MMC         5
 #define OMAP2420_MMC_SIZE       OMAP1_MMC_SIZE
-#define OMAP3_HSMMC_SIZE        0x200
-#define OMAP4_HSMMC_SIZE        0x1000
 #define OMAP2_MMC1_BASE         0x4809c000
-#define OMAP2_MMC2_BASE         0x480b4000
-#define OMAP3_MMC3_BASE         0x480ad000
-#define OMAP4_MMC4_BASE         0x480d1000
-#define OMAP4_MMC5_BASE         0x480d5000
+
 #define OMAP4_MMC_REG_OFFSET    0x100
-#define HSMMC5                  (1 << 4)
-#define HSMMC4                  (1 << 3)
-#define HSMMC3                  (1 << 2)
-#define HSMMC2                  (1 << 1)
-#define HSMMC1                  (1 << 0)
 
 #define OMAP_MMC_MAX_SLOTS      2
 
+#define OMAP_HSMMC_SUPPORTS_DUAL_VOLT   BIT(1)
+
+struct omap_mmc_dev_attr {
+        u8 flags;
+};
+
 struct omap_mmc_platform_data {
         /* back-link to device */
         struct device *dev;
@@ -71,6 +65,9 @@ struct omap_mmc_platform_data {
 
         u64 dma_mask;
 
+        /* Integrating attributes from the omap_hwmod layer */
+        u8 controller_flags;
+
         /* Register offset deviation */
         u16 reg_offset;
 
@@ -159,8 +156,7 @@ extern void omap_mmc_notify_cover_event(struct device *dev, int slot,
         defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
 void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                 int nr_controllers);
-void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers);
+void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data);
 int omap_mmc_add(const char *name, int id, unsigned long base,
                                 unsigned long size, unsigned int irq,
                                 struct omap_mmc_platform_data *data);
@@ -169,8 +165,7 @@ static inline void omap1_init_mmc(struct omap_mmc_platform_data **mmc_data,
                                 int nr_controllers)
 {
 }
-static inline void omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
-                                int nr_controllers)
+static inline void omap242x_init_mmc(struct omap_mmc_platform_data **mmc_data)
 {
 }
 static inline int omap_mmc_add(const char *name, int id, unsigned long base,
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index 6562cd082bb1..d86d1ecf0068 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -8,8 +8,16 @@
  * published by the Free Software Foundation.
  */
 
+#include <plat/gpmc.h>
 #include <linux/mtd/partitions.h>
 
+enum nand_io {
+        NAND_OMAP_PREFETCH_POLLED = 0,  /* prefetch polled mode, default */
+        NAND_OMAP_POLLED,               /* polled mode, without prefetch */
+        NAND_OMAP_PREFETCH_DMA,         /* prefetch enabled sDMA mode */
+        NAND_OMAP_PREFETCH_IRQ          /* prefetch enabled irq mode */
+};
+
 struct omap_nand_platform_data {
         unsigned int            options;
         int                     cs;
@@ -20,8 +28,11 @@ struct omap_nand_platform_data {
         int                     (*nand_setup)(void);
         int                     (*dev_ready)(struct omap_nand_platform_data *);
         int                     dma_channel;
+        int                     gpmc_irq;
+        enum nand_io            xfer_type;
         unsigned long           phys_base;
         int                     devsize;
+        enum omap_ecc           ecc_opt;
 };
 
 /* minimum size for IO mapping */
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index fedd82971c9e..8a1368fbbbd3 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -1,7 +1,7 @@
 /*
  * omap_hwmod macros, structures
  *
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -30,6 +30,7 @@
 #define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_OMAP_HWMOD_H
 
 #include <linux/kernel.h>
+#include <linux/init.h>
 #include <linux/list.h>
 #include <linux/ioport.h>
 #include <linux/spinlock.h>
@@ -178,7 +179,8 @@ struct omap_hwmod_omap2_firewall {
 #define ADDR_TYPE_RT            (1 << 1)
 
 /**
- * struct omap_hwmod_addr_space - MPU address space handled by the hwmod
+ * struct omap_hwmod_addr_space - address space handled by the hwmod
+ * @name: name of the address space
  * @pa_start: starting physical address
  * @pa_end: ending physical address
  * @flags: (see omap_hwmod_addr_space.flags macros above)
@@ -187,6 +189,7 @@ struct omap_hwmod_omap2_firewall {
  * structure.  GPMC is one example.
  */
 struct omap_hwmod_addr_space {
+        const char *name;
         u32 pa_start;
         u32 pa_end;
         u8 flags;
@@ -370,8 +373,10 @@ struct omap_hwmod_omap4_prcm {
  *     of standby, rather than relying on module smart-standby
  * HWMOD_INIT_NO_RESET: don't reset this module at boot - important for
  *     SDRAM controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_RESET
  * HWMOD_INIT_NO_IDLE: don't idle this module at boot - important for SDRAM
  *     controller, etc. XXX probably belongs outside the main hwmod file
+ *     XXX Should be HWMOD_SETUP_NO_IDLE
  * HWMOD_NO_AUTOIDLE: disable module autoidle (OCP_SYSCONFIG.AUTOIDLE)
  *     when module is enabled, rather than the default, which is to
  *     enable autoidle
@@ -535,11 +540,13 @@ struct omap_hwmod {
         const struct omap_chip_id       omap_chip;
 };
 
-int omap_hwmod_init(struct omap_hwmod **ohs);
+int omap_hwmod_register(struct omap_hwmod **ohs);
 struct omap_hwmod *omap_hwmod_lookup(const char *name);
 int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
                         void *data);
 
+int __init omap_hwmod_setup_one(const char *name);
+
 int omap_hwmod_enable(struct omap_hwmod *oh);
 int _omap_hwmod_enable(struct omap_hwmod *oh);
 int omap_hwmod_idle(struct omap_hwmod *oh);
@@ -554,6 +561,7 @@ int omap_hwmod_enable_clocks(struct omap_hwmod *oh);
 int omap_hwmod_disable_clocks(struct omap_hwmod *oh);
 
 int omap_hwmod_set_slave_idlemode(struct omap_hwmod *oh, u8 idlemode);
+int omap_hwmod_set_ocp_autoidle(struct omap_hwmod *oh, u8 autoidle);
 
 int omap_hwmod_reset(struct omap_hwmod *oh);
 void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
@@ -588,6 +596,8 @@ int omap_hwmod_for_each_by_class(const char *classname,
 int omap_hwmod_set_postsetup_state(struct omap_hwmod *oh, u8 state);
 u32 omap_hwmod_get_context_loss_count(struct omap_hwmod *oh);
 
+int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/onenand.h b/arch/arm/plat-omap/include/plat/onenand.h
index affe87e9ece7..cbe897ca7f9e 100644
--- a/arch/arm/plat-omap/include/plat/onenand.h
+++ b/arch/arm/plat-omap/include/plat/onenand.h
@@ -15,12 +15,20 @@
 #define ONENAND_SYNC_READ       (1 << 0)
 #define ONENAND_SYNC_READWRITE  (1 << 1)
 
+struct onenand_freq_info {
+        u16                     maf_id;
+        u16                     dev_id;
+        u16                     ver_id;
+};
+
 struct omap_onenand_platform_data {
         int                     cs;
         int                     gpio_irq;
         struct mtd_partition    *parts;
         int                     nr_parts;
-        int                     (*onenand_setup)(void __iomem *, int freq);
+        int                     (*onenand_setup)(void __iomem *, int *freq_ptr);
+        int             (*get_freq)(const struct onenand_freq_info *freq_info,
+                                    bool *clk_dep);
         int                     dma_channel;
         u8                      flags;
         u8                      regulator_can_sleep;
diff --git a/arch/arm/plat-omap/include/plat/sdrc.h b/arch/arm/plat-omap/include/plat/sdrc.h
index efd87c8dda69..925b12b500dc 100644
--- a/arch/arm/plat-omap/include/plat/sdrc.h
+++ b/arch/arm/plat-omap/include/plat/sdrc.h
@@ -124,8 +124,14 @@ struct omap_sdrc_params {
         u32 mr;
 };
 
-void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+void omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
                             struct omap_sdrc_params *sdrc_cs1);
+#else
+static inline void __init omap2_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
+                                          struct omap_sdrc_params *sdrc_cs1) {};
+#endif
+
 int omap2_sdrc_get_params(unsigned long r,
                           struct omap_sdrc_params **sdrc_cs0,
                           struct omap_sdrc_params **sdrc_cs1);
diff --git a/arch/arm/plat-omap/iommu.c b/arch/arm/plat-omap/iommu.c
index b1107c08da56..e3eb0380090a 100644
--- a/arch/arm/plat-omap/iommu.c
+++ b/arch/arm/plat-omap/iommu.c
@@ -104,6 +104,9 @@ static int iommu_enable(struct iommu *obj)
         if (!obj)
                 return -EINVAL;
 
+        if (!arch_iommu)
+                return -ENODEV;
+
         clk_enable(obj->clk);
 
         err = arch_iommu->enable(obj);
@@ -780,25 +783,19 @@ static void iopgtable_clear_entry_all(struct iommu *obj)
  */
 static irqreturn_t iommu_fault_handler(int irq, void *data)
 {
-        u32 stat, da;
+        u32 da, errs;
         u32 *iopgd, *iopte;
-        int err = -EIO;
         struct iommu *obj = data;
 
         if (!obj->refcount)
                 return IRQ_NONE;
 
-        /* Dynamic loading TLB or PTE */
-        if (obj->isr)
-                err = obj->isr(obj);
-
-        if (!err)
-                return IRQ_HANDLED;
-
         clk_enable(obj->clk);
-        stat = iommu_report_fault(obj, &da);
+        errs = iommu_report_fault(obj, &da);
         clk_disable(obj->clk);
-        if (!stat)
+
+        /* Fault callback or TLB/PTE Dynamic loading */
+        if (obj->isr && !obj->isr(obj, da, errs, obj->isr_priv))
                 return IRQ_HANDLED;
 
         iommu_disable(obj);
@@ -806,15 +803,16 @@ static irqreturn_t iommu_fault_handler(int irq, void *data)
         iopgd = iopgd_offset(obj, da);
 
         if (!iopgd_is_table(*iopgd)) {
-                dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x\n", __func__,
-                        da, iopgd, *iopgd);
+                dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p "
+                        "*pgd:px%08x\n", obj->name, errs, da, iopgd, *iopgd);
                 return IRQ_NONE;
         }
 
         iopte = iopte_offset(iopgd, da);
 
-        dev_err(obj->dev, "%s: da:%08x pgd:%p *pgd:%08x pte:%p *pte:%08x\n",
-                __func__, da, iopgd, *iopgd, iopte, *iopte);
+        dev_err(obj->dev, "%s: errs:0x%08x da:0x%08x pgd:0x%p *pgd:0x%08x "
+                "pte:0x%p *pte:0x%08x\n", obj->name, errs, da, iopgd, *iopgd,
+                iopte, *iopte);
 
         return IRQ_NONE;
 }
@@ -917,6 +915,33 @@ void iommu_put(struct iommu *obj)
 }
 EXPORT_SYMBOL_GPL(iommu_put);
 
+int iommu_set_isr(const char *name,
+                  int (*isr)(struct iommu *obj, u32 da, u32 iommu_errs,
+                             void *priv),
+                  void *isr_priv)
+{
+        struct device *dev;
+        struct iommu *obj;
+
+        dev = driver_find_device(&omap_iommu_driver.driver, NULL, (void *)name,
+                                 device_match_by_alias);
+        if (!dev)
+                return -ENODEV;
+
+        obj = to_iommu(dev);
+        mutex_lock(&obj->iommu_lock);
+        if (obj->refcount != 0) {
+                mutex_unlock(&obj->iommu_lock);
+                return -EBUSY;
+        }
+        obj->isr = isr;
+        obj->isr_priv = isr_priv;
+        mutex_unlock(&obj->iommu_lock);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(iommu_set_isr);
+
 /*
  *      OMAP Device MMU(IOMMU) detection
  */
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index 459b319a9fad..49d3208793e5 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -322,15 +322,18 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
 
 struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
 {
-        struct omap_mbox *mbox;
-        int ret;
+        struct omap_mbox *_mbox, *mbox = NULL;
+        int i, ret;
 
         if (!mboxes)
                 return ERR_PTR(-EINVAL);
 
-        for (mbox = *mboxes; mbox; mbox++)
-                if (!strcmp(mbox->name, name))
+        for (i = 0; (_mbox = mboxes[i]); i++) {
+                if (!strcmp(_mbox->name, name)) {
+                        mbox = _mbox;
                         break;
+                }
+        }
 
         if (!mbox)
                 return ERR_PTR(-ENOENT);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index b5a6e178a7f9..d598d9fd65ac 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -27,6 +27,8 @@
 
 #include <plat/dma.h>
 #include <plat/mcbsp.h>
+#include <plat/omap_device.h>
+#include <linux/pm_runtime.h>
 
 /* XXX These "sideways" includes are a sign that something is wrong */
 #include "../mach-omap2/cm2xxx_3xxx.h"
@@ -227,10 +229,83 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
 
+/**
+ * omap_mcbsp_dma_params - returns the dma channel number
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the dma channel number for the rx channel or tx channel
+ * based on the value of @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        if (stream)
+                return mcbsp->dma_rx_sync;
+        else
+                return mcbsp->dma_tx_sync;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_ch_params);
+
+/**
+ * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
+ * @id - mcbsp id
+ * @stream - indicates the direction of data flow (rx or tx)
+ *
+ * Returns the address of mcbsp data transmit register or data receive register
+ * to be used by DMA for transferring/receiving data based on the value of
+ * @stream for the requested mcbsp given by @id
+ */
+int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream)
+{
+        struct omap_mcbsp *mcbsp;
+        int data_reg;
+
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+
+        data_reg = mcbsp->phys_dma_base;
+
+        if (mcbsp->mcbsp_config_type < MCBSP_CONFIG_TYPE2) {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR1;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR1;
+        } else {
+                if (stream)
+                        data_reg += OMAP_MCBSP_REG_DRR;
+                else
+                        data_reg += OMAP_MCBSP_REG_DXR;
+        }
+
+        return data_reg;
+}
+EXPORT_SYMBOL(omap_mcbsp_dma_reg_params);
+
 #ifdef CONFIG_ARCH_OMAP3
+static struct omap_device *find_omap_device_by_dev(struct device *dev)
+{
+        struct platform_device *pdev = container_of(dev,
+                                        struct platform_device, dev);
+        return container_of(pdev, struct omap_device, pdev);
+}
+
 static void omap_st_on(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         /*
          * Sidetone uses McBSP ICLK - which must not idle when sidetones
@@ -244,9 +319,6 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w | SIDETONEEN);
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
-
         /* Enable Sidetone from Sidetone Core */
         w = MCBSP_ST_READ(mcbsp, SSELCR);
         MCBSP_ST_WRITE(mcbsp, SSELCR, w | ST_SIDETONEEN);
@@ -255,13 +327,13 @@ static void omap_st_on(struct omap_mcbsp *mcbsp)
 static void omap_st_off(struct omap_mcbsp *mcbsp)
 {
         unsigned int w;
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
         MCBSP_ST_WRITE(mcbsp, SSELCR, w & ~(ST_SIDETONEEN));
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w | ST_AUTOIDLE);
-
         w = MCBSP_READ(mcbsp, SSELCR);
         MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN));
 
@@ -273,9 +345,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp)
 static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir)
 {
         u16 val, i;
+        struct omap_device *od;
 
-        val = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, val & ~(ST_AUTOIDLE));
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         val = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -303,9 +375,9 @@ static void omap_st_chgain(struct omap_mcbsp *mcbsp)
 {
         u16 w;
         struct omap_mcbsp_st_data *st_data = mcbsp->st_data;
+        struct omap_device *od;
 
-        w = MCBSP_ST_READ(mcbsp, SYSCONFIG);
-        MCBSP_ST_WRITE(mcbsp, SYSCONFIG, w & ~(ST_AUTOIDLE));
+        od = find_omap_device_by_dev(mcbsp->dev);
 
         w = MCBSP_ST_READ(mcbsp, SSELCR);
 
@@ -648,48 +720,33 @@ EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
 
 static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
         /*
          * Enable wakup behavior, smart idle and all wakeups
          * REVISIT: some wakeups may be unnecessary
          */
         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
-
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
-
-                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
-                        syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
-                                        CLOCKACTIVITY(0x02));
-                        MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
-                } else {
-                        syscon |= SIDLEMODE(0x01);
-                }
-
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
+                MCBSP_WRITE(mcbsp, WAKEUPEN, XRDYEN | RRDYEN);
         }
 }
 
 static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
 {
+        struct omap_device *od;
+
+        od = find_omap_device_by_dev(mcbsp->dev);
+
         /*
          * Disable wakup behavior, smart idle and all wakeups
          */
         if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
-                u16 syscon;
-
-                syscon = MCBSP_READ(mcbsp, SYSCON);
-                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
                 /*
                  * HW bug workaround - If no_idle mode is taken, we need to
                  * go to smart_idle before going to always_idle, or the
                  * device will not hit retention anymore.
                  */
-                syscon |= SIDLEMODE(0x02);
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
-
-                syscon &= ~(SIDLEMODE(0x03));
-                MCBSP_WRITE(mcbsp, SYSCON, syscon);
 
                 MCBSP_WRITE(mcbsp, WAKEUPEN, 0);
         }
@@ -764,8 +821,7 @@ int omap_mcbsp_request(unsigned int id)
         if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->request)
                 mcbsp->pdata->ops->request(id);
 
-        clk_enable(mcbsp->iclk);
-        clk_enable(mcbsp->fclk);
+        pm_runtime_get_sync(mcbsp->dev);
 
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_request(mcbsp);
@@ -813,8 +869,7 @@ err_clk_disable:
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_free(mcbsp);
 
-        clk_disable(mcbsp->fclk);
-        clk_disable(mcbsp->iclk);
+        pm_runtime_put_sync(mcbsp->dev);
 
         spin_lock(&mcbsp->lock);
         mcbsp->free = true;
@@ -844,8 +899,7 @@ void omap_mcbsp_free(unsigned int id)
         /* Do procedure specific to omap34xx arch, if applicable */
         omap34xx_mcbsp_free(mcbsp);
 
-        clk_disable(mcbsp->fclk);
-        clk_disable(mcbsp->iclk);
+        pm_runtime_put_sync(mcbsp->dev);
 
         if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
                 /* Free IRQs */
@@ -1649,7 +1703,8 @@ static const struct attribute_group sidetone_attr_group = {
 
 static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
 {
-        struct omap_mcbsp_platform_data *pdata = mcbsp->pdata;
+        struct platform_device *pdev;
+        struct resource *res;
         struct omap_mcbsp_st_data *st_data;
         int err;
 
@@ -1659,7 +1714,10 @@ static int __devinit omap_st_add(struct omap_mcbsp *mcbsp)
                 goto err1;
         }
 
-        st_data->io_base_st = ioremap(pdata->phys_base_st, SZ_4K);
+        pdev = container_of(mcbsp->dev, struct platform_device, dev);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sidetone");
+        st_data->io_base_st = ioremap(res->start, resource_size(res));
         if (!st_data->io_base_st) {
                 err = -ENOMEM;
                 goto err2;
@@ -1748,6 +1806,7 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
         struct omap_mcbsp *mcbsp;
         int id = pdev->id - 1;
+        struct resource *res;
         int ret = 0;
 
         if (!pdata) {
@@ -1777,47 +1836,78 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
         mcbsp->dma_tx_lch = -1;
         mcbsp->dma_rx_lch = -1;
 
-        mcbsp->phys_base = pdata->phys_base;
-        mcbsp->io_base = ioremap(pdata->phys_base, SZ_4K);
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
+        if (!res) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+                if (!res) {
+                        dev_err(&pdev->dev, "%s:mcbsp%d has invalid memory"
+                                        "resource\n", __func__, pdev->id);
+                        ret = -ENOMEM;
+                        goto exit;
+                }
+        }
+        mcbsp->phys_base = res->start;
+        omap_mcbsp_cache_size = resource_size(res);
+        mcbsp->io_base = ioremap(res->start, resource_size(res));
         if (!mcbsp->io_base) {
                 ret = -ENOMEM;
                 goto err_ioremap;
         }
 
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
+        if (!res)
+                mcbsp->phys_dma_base = mcbsp->phys_base;
+        else
+                mcbsp->phys_dma_base = res->start;
+
         /* Default I/O is IRQ based */
         mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
-        mcbsp->tx_irq = pdata->tx_irq;
-        mcbsp->rx_irq = pdata->rx_irq;
-        mcbsp->dma_rx_sync = pdata->dma_rx_sync;
-        mcbsp->dma_tx_sync = pdata->dma_tx_sync;
 
-        mcbsp->iclk = clk_get(&pdev->dev, "ick");
-        if (IS_ERR(mcbsp->iclk)) {
-                ret = PTR_ERR(mcbsp->iclk);
-                dev_err(&pdev->dev, "unable to get ick: %d\n", ret);
-                goto err_iclk;
+        mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
+        mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
+
+        /* From OMAP4 there will be a single irq line */
+        if (mcbsp->tx_irq == -ENXIO)
+                mcbsp->tx_irq = platform_get_irq(pdev, 0);
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid rx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
+        }
+        mcbsp->dma_rx_sync = res->start;
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+        if (!res) {
+                dev_err(&pdev->dev, "%s:mcbsp%d has invalid tx DMA channel\n",
+                                        __func__, pdev->id);
+                ret = -ENODEV;
+                goto err_res;
         }
+        mcbsp->dma_tx_sync = res->start;
 
         mcbsp->fclk = clk_get(&pdev->dev, "fck");
         if (IS_ERR(mcbsp->fclk)) {
                 ret = PTR_ERR(mcbsp->fclk);
                 dev_err(&pdev->dev, "unable to get fck: %d\n", ret);
-                goto err_fclk;
+                goto err_res;
         }
 
         mcbsp->pdata = pdata;
         mcbsp->dev = &pdev->dev;
         mcbsp_ptr[id] = mcbsp;
+        mcbsp->mcbsp_config_type = pdata->mcbsp_config_type;
         platform_set_drvdata(pdev, mcbsp);
+        pm_runtime_enable(mcbsp->dev);
 
         /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
         omap34xx_device_init(mcbsp);
 
         return 0;
 
-err_fclk:
-        clk_put(mcbsp->iclk);
-err_iclk:
+err_res:
         iounmap(mcbsp->io_base);
 err_ioremap:
         kfree(mcbsp);
@@ -1839,7 +1929,6 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                 omap34xx_device_exit(mcbsp);
 
                 clk_put(mcbsp->fclk);
-                clk_put(mcbsp->iclk);
 
                 iounmap(mcbsp->io_base);
                 kfree(mcbsp);
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 57adb270767b..9bbda9acb73b 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -83,9 +83,11 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/clkdev.h>
 
 #include <plat/omap_device.h>
 #include <plat/omap_hwmod.h>
+#include <plat/clock.h>
 
 /* These parameters are passed to _omap_device_{de,}activate() */
 #define USE_WAKEUP_LAT                  0
@@ -239,12 +241,12 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
 }
 
 /**
- * _add_optional_clock_alias - Add clock alias for hwmod optional clocks
+ * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
  * @od: struct omap_device *od
  *
  * For every optional clock present per hwmod per omap_device, this function
- * adds an entry in the clocks list of the form <dev-id=dev_name, con-id=role>
- * if an entry is already present in it with the form <dev-id=NULL, con-id=role>
+ * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
+ * if it does not exist already.
  *
  * The function is called from inside omap_device_build_ss(), after
  * omap_device_register.
@@ -254,25 +256,39 @@ static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
  *
  * No return value.
  */
-static void _add_optional_clock_alias(struct omap_device *od,
+static void _add_optional_clock_clkdev(struct omap_device *od,
                                       struct omap_hwmod *oh)
 {
         int i;
 
         for (i = 0; i < oh->opt_clks_cnt; i++) {
                 struct omap_hwmod_opt_clk *oc;
-                int r;
+                struct clk *r;
+                struct clk_lookup *l;
 
                 oc = &oh->opt_clks[i];
 
                 if (!oc->_clk)
                         continue;
 
-                r = clk_add_alias(oc->role, dev_name(&od->pdev.dev),
-                                  (char *)oc->clk, &od->pdev.dev);
-                if (r)
-                        pr_err("omap_device: %s: clk_add_alias for %s failed\n",
+                r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
+                if (!IS_ERR(r))
+                        continue; /* clkdev entry exists */
+
+                r = omap_clk_get_by_name((char *)oc->clk);
+                if (IS_ERR(r)) {
+                        pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+                               dev_name(&od->pdev.dev), oc->clk);
+                        continue;
+                }
+
+                l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
+                if (!l) {
+                        pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
                                dev_name(&od->pdev.dev), oc->role);
+                        return;
+                }
+                clkdev_add(l);
         }
 }
 
@@ -480,7 +496,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
 
         for (i = 0; i < oh_cnt; i++) {
                 hwmods[i]->od = od;
-                _add_optional_clock_alias(od, hwmods[i]);
+                _add_optional_clock_clkdev(od, hwmods[i]);
         }
 
         if (ret)
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index aedcb3be4e66..9d80064e979b 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -405,20 +405,6 @@ static inline int omap34xx_sram_init(void)
 }
 #endif
 
-#ifdef CONFIG_ARCH_OMAP4
-static int __init omap44xx_sram_init(void)
-{
-        printk(KERN_ERR "FIXME: %s not implemented\n", __func__);
-
-        return -ENODEV;
-}
-#else
-static inline int omap44xx_sram_init(void)
-{
-        return 0;
-}
-#endif
-
 int __init omap_sram_init(void)
 {
         omap_detect_sram();
@@ -432,8 +418,6 @@ int __init omap_sram_init(void)
                 omap243x_sram_init();
         else if (cpu_is_omap34xx())
                 omap34xx_sram_init();
-        else if (cpu_is_omap44xx())
-                omap44xx_sram_init();
 
         return 0;
 }
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index 6a7342886171..afaf87fdb93e 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -28,7 +28,7 @@
 static struct resource s5p_uart0_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART0,
-                .end    = S5P_PA_UART0 + S5P_SZ_UART,
+                .end    = S5P_PA_UART0 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -51,7 +51,7 @@ static struct resource s5p_uart0_resource[] = {
 static struct resource s5p_uart1_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART1,
-                .end    = S5P_PA_UART1 + S5P_SZ_UART,
+                .end    = S5P_PA_UART1 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -74,7 +74,7 @@ static struct resource s5p_uart1_resource[] = {
 static struct resource s5p_uart2_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART2,
-                .end    = S5P_PA_UART2 + S5P_SZ_UART,
+                .end    = S5P_PA_UART2 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -98,7 +98,7 @@ static struct resource s5p_uart3_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
         [0] = {
                 .start  = S5P_PA_UART3,
-                .end    = S5P_PA_UART3 + S5P_SZ_UART,
+                .end    = S5P_PA_UART3 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -123,7 +123,7 @@ static struct resource s5p_uart4_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 4
         [0] = {
                 .start  = S5P_PA_UART4,
-                .end    = S5P_PA_UART4 + S5P_SZ_UART,
+                .end    = S5P_PA_UART4 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -148,7 +148,7 @@ static struct resource s5p_uart5_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 5
         [0] = {
                 .start  = S5P_PA_UART5,
-                .end    = S5P_PA_UART5 + S5P_SZ_UART,
+                .end    = S5P_PA_UART5 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 236ef8427d7d..3e4bd8147bf4 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 
         s3c_device_ts.dev.platform_data = npd;
 }
-EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 99ba6789cc97..6dd455bafdfd 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -24,10 +24,10 @@ static inline void putc(int c)
 {
         void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
 
-        while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+        while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
                 barrier();
 
-        writel(c, base + UART01x_DR);
+        writel_relaxed(c, base + UART01x_DR);
 }
 
 static inline void flush(void)
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
index 09e9372aea21..8c8b24d07046 100644
--- a/arch/arm/plat-spear/include/plat/vmalloc.h
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -14,6 +14,6 @@
 #ifndef __PLAT_VMALLOC_H
 #define __PLAT_VMALLOC_H
 
-#define VMALLOC_END             0xF0000000
+#define VMALLOC_END             0xF0000000UL
 
 #endif /* __PLAT_VMALLOC_H */