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-rw-r--r--arch/arm/Kconfig28
-rw-r--r--arch/arm/Kconfig.debug9
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/head-shmobile.S43
-rw-r--r--arch/arm/boot/dts/Makefile43
-rw-r--r--arch/arm/boot/dts/armada-370-db.dts5
-rw-r--r--arch/arm/boot/dts/armada-370-mirabox.dts37
-rw-r--r--arch/arm/boot/dts/armada-370-netgear-rn102.dts179
-rw-r--r--arch/arm/boot/dts/armada-370-rd.dts37
-rw-r--r--arch/arm/boot/dts/armada-370-xp.dtsi113
-rw-r--r--arch/arm/boot/dts/armada-370.dtsi123
-rw-r--r--arch/arm/boot/dts/armada-xp-axpwifiap.dts164
-rw-r--r--arch/arm/boot/dts/armada-xp-db.dts131
-rw-r--r--arch/arm/boot/dts/armada-xp-gp.dts107
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi228
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi269
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi417
-rw-r--r--arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts88
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi11
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi1
-rw-r--r--arch/arm/boot/dts/at91rm9200_pqfp.dtsi17
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi1
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts18
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi3
-rw-r--r--arch/arm/boot/dts/at91sam9x5ek.dtsi24
-rw-r--r--arch/arm/boot/dts/bcm11351-brt.dts8
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi33
-rw-r--r--arch/arm/boot/dts/bcm28155-ap.dts45
-rw-r--r--arch/arm/boot/dts/ccu8540.dts41
-rw-r--r--arch/arm/boot/dts/da850-evm.dts11
-rw-r--r--arch/arm/boot/dts/da850.dtsi46
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts37
-rw-r--r--arch/arm/boot/dts/dove-d2plug.dts69
-rw-r--r--arch/arm/boot/dts/dove.dtsi285
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d-reference.dts57
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts2
-rw-r--r--arch/arm/boot/dts/emev2.dtsi65
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi124
-rw-r--r--arch/arm/boot/dts/exynos4210-pinctrl.dtsi23
-rw-r--r--arch/arm/boot/dts/exynos4210-trats.dts100
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi32
-rw-r--r--arch/arm/boot/dts/exynos4412-origen.dts5
-rw-r--r--arch/arm/boot/dts/exynos4412-trats2.dts579
-rw-r--r--arch/arm/boot/dts/exynos4x12-pinctrl.dtsi61
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi105
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi21
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts105
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts32
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi66
-rw-r--r--arch/arm/boot/dts/exynos5420-pinctrl.dtsi7
-rw-r--r--arch/arm/boot/dts/exynos5420-smdk5420.dts31
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi94
-rw-r--r--arch/arm/boot/dts/exynos5440.dtsi29
-rw-r--r--arch/arm/boot/dts/imx23-evk.dts15
-rw-r--r--arch/arm/boot/dts/imx23-olinuxino.dts4
-rw-r--r--arch/arm/boot/dts/imx23.dtsi17
-rw-r--r--arch/arm/boot/dts/imx25.dtsi35
-rw-r--r--arch/arm/boot/dts/imx27-apf27dev.dts5
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts93
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts44
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts13
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dts125
-rw-r--r--arch/arm/boot/dts/imx27.dtsi120
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts7
-rw-r--r--arch/arm/boot/dts/imx28-cfa10037.dts19
-rw-r--r--arch/arm/boot/dts/imx28-cfa10049.dts73
-rw-r--r--arch/arm/boot/dts/imx28-cfa10055.dts38
-rw-r--r--arch/arm/boot/dts/imx28-cfa10056.dts119
-rw-r--r--arch/arm/boot/dts/imx28-cfa10057.dts23
-rw-r--r--arch/arm/boot/dts/imx28-cfa10058.dts141
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts13
-rw-r--r--arch/arm/boot/dts/imx28.dtsi143
-rw-r--r--arch/arm/boot/dts/imx31.dtsi17
-rw-r--r--arch/arm/boot/dts/imx51-apf51.dts4
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts5
-rw-r--r--arch/arm/boot/dts/imx51.dtsi632
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts18
-rw-r--r--arch/arm/boot/dts/imx53.dtsi56
-rw-r--r--arch/arm/boot/dts/imx6dl-pinfunc.h2138
-rw-r--r--arch/arm/boot/dts/imx6dl-sabreauto.dts22
-rw-r--r--arch/arm/boot/dts/imx6dl-sabresd.dts19
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard.dts24
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi254
-rw-r--r--arch/arm/boot/dts/imx6q-arm2.dts14
-rw-r--r--arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi112
-rw-r--r--arch/arm/boot/dts/imx6q-pinfunc.h2050
-rw-r--r--arch/arm/boot/dts/imx6q-sabreauto.dts22
-rw-r--r--arch/arm/boot/dts/imx6q-sabrelite.dts22
-rw-r--r--arch/arm/boot/dts/imx6q-sabresd.dts19
-rw-r--r--arch/arm/boot/dts/imx6q-wandboard.dts26
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi393
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabreauto.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi92
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi137
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi770
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi35
-rw-r--r--arch/arm/boot/dts/keystone.dts29
-rw-r--r--arch/arm/boot/dts/kirkwood-6281.dtsi66
-rw-r--r--arch/arm/boot/dts/kirkwood-6282.dtsi102
-rw-r--r--arch/arm/boot/dts/kirkwood-cloudbox.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6281.dts7
-rw-r--r--arch/arm/boot/dts/kirkwood-db-88f6282.dts7
-rw-r--r--arch/arm/boot/dts/kirkwood-db.dtsi22
-rw-r--r--arch/arm/boot/dts/kirkwood-dns320.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-dns325.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-dnskw.dtsi20
-rw-r--r--arch/arm/boot/dts/kirkwood-dockstar.dts21
-rw-r--r--arch/arm/boot/dts/kirkwood-dreamplug.dts32
-rw-r--r--arch/arm/boot/dts/kirkwood-goflexnet.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts34
-rw-r--r--arch/arm/boot/dts/kirkwood-ib62x0.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-iconnect.dts39
-rw-r--r--arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts28
-rw-r--r--arch/arm/boot/dts/kirkwood-is2.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-km_kirkwood.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-lschlv2.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxhl.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-lsxl.dtsi32
-rw-r--r--arch/arm/boot/dts/kirkwood-mplcec4.dts50
-rw-r--r--arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts125
-rw-r--r--arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts59
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2-common.dtsi20
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2lite.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2max.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-ns2mini.dts4
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310-common.dtsi107
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310.dts111
-rw-r--r--arch/arm/boot/dts/kirkwood-nsa310a.dts165
-rw-r--r--arch/arm/boot/dts/kirkwood-openblocks_a6.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi20
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-sheevaplug.dts2
-rw-r--r--arch/arm/boot/dts/kirkwood-topkick.dts20
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6281.dts10
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219-6282.dts29
-rw-r--r--arch/arm/boot/dts/kirkwood-ts219.dtsi31
-rw-r--r--arch/arm/boot/dts/kirkwood.dtsi102
-rw-r--r--arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts17
-rw-r--r--arch/arm/boot/dts/orion5x.dtsi34
-rw-r--r--arch/arm/boot/dts/pxa3xx.dtsi11
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts65
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm.dts24
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi133
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts36
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva.dts2
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi20
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts32
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts2
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi66
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen-reference.dts51
-rw-r--r--arch/arm/boot/dts/r8a7779-marzen.dts27
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi98
-rw-r--r--arch/arm/boot/dts/r8a7790-lager-reference.dts45
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts2
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi132
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi24
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi2
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi8
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts92
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts2
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi14
-rw-r--r--arch/arm/boot/dts/skeleton64.dtsi2
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi8
-rw-r--r--arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi196
-rw-r--r--arch/arm/boot/dts/ste-ccu8540.dts86
-rw-r--r--arch/arm/boot/dts/ste-ccu9540.dts (renamed from arch/arm/boot/dts/ccu9540.dts)2
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi (renamed from arch/arm/boot/dts/dbx5x0.dtsi)30
-rw-r--r--arch/arm/boot/dts/ste-href.dtsi (renamed from arch/arm/boot/dts/href.dtsi)2
-rw-r--r--arch/arm/boot/dts/ste-hrefprev60.dts (renamed from arch/arm/boot/dts/hrefprev60.dts)6
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dts (renamed from arch/arm/boot/dts/hrefv60plus.dts)6
-rw-r--r--arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi95
-rw-r--r--arch/arm/boot/dts/ste-nomadik-stn8815.dtsi42
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts (renamed from arch/arm/boot/dts/snowball.dts)44
-rw-r--r--arch/arm/boot/dts/ste-stuib.dtsi (renamed from arch/arm/boot/dts/stuib.dtsi)0
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts101
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts6
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts2
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts2
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi3
-rw-r--r--arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi93
-rw-r--r--arch/arm/boot/dts/sun5i-a13-olinuxino.dts2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi3
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts32
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi299
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts61
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi311
-rw-r--r--arch/arm/boot/dts/tegra114-dalmore.dts237
-rw-r--r--arch/arm/boot/dts/tegra114-pluto.dts33
-rw-r--r--arch/arm/boot/dts/tegra114.dtsi62
-rw-r--r--arch/arm/boot/dts/tegra20-colibri-512.dtsi2
-rw-r--r--arch/arm/boot/dts/tegra20-harmony.dts22
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-seaboard.dts4
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi19
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts8
-rw-r--r--arch/arm/boot/dts/tegra20-trimslice.dts32
-rw-r--r--arch/arm/boot/dts/tegra20-ventana.dts2
-rw-r--r--arch/arm/boot/dts/tegra20-whistler.dts2
-rw-r--r--arch/arm/boot/dts/tegra20.dtsi55
-rw-r--r--arch/arm/boot/dts/tegra30-beaver.dts64
-rw-r--r--arch/arm/boot/dts/tegra30-cardhu.dtsi64
-rw-r--r--arch/arm/boot/dts/tegra30.dtsi156
-rw-r--r--arch/arm/boot/dts/u9540.dts72
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts31
-rw-r--r--arch/arm/boot/dts/vf610-twr.dts7
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi4
-rw-r--r--arch/arm/common/edma.c17
-rw-r--r--arch/arm/configs/ag5evm_defconfig83
-rw-r--r--arch/arm/configs/ape6evm_defconfig6
-rw-r--r--arch/arm/configs/at91_dt_defconfig4
-rw-r--r--arch/arm/configs/bcm_defconfig13
-rw-r--r--arch/arm/configs/dove_defconfig4
-rw-r--r--arch/arm/configs/exynos4_defconfig68
-rw-r--r--arch/arm/configs/imx_v4_v5_defconfig19
-rw-r--r--arch/arm/configs/imx_v6_v7_defconfig51
-rw-r--r--arch/arm/configs/kirkwood_defconfig51
-rw-r--r--arch/arm/configs/lager_defconfig (renamed from arch/arm/configs/kota2_defconfig)111
-rw-r--r--arch/arm/configs/marzen_defconfig1
-rw-r--r--arch/arm/configs/mvebu_defconfig2
-rw-r--r--arch/arm/configs/mxs_defconfig19
-rw-r--r--arch/arm/configs/omap2plus_defconfig1
-rw-r--r--arch/arm/configs/tegra_defconfig9
-rw-r--r--arch/arm/include/asm/dma-contiguous.h1
-rw-r--r--arch/arm/include/asm/localtimer.h34
-rw-r--r--arch/arm/include/asm/mach/arch.h2
-rw-r--r--arch/arm/include/asm/mach/pci.h4
-rw-r--r--arch/arm/include/asm/outercache.h4
-rw-r--r--arch/arm/include/debug/msm.S (renamed from arch/arm/mach-msm/include/mach/debug-macro.S)32
-rw-r--r--arch/arm/kernel/bios32.c16
-rw-r--r--arch/arm/kernel/smp.c87
-rw-r--r--arch/arm/kernel/smp_twd.c64
-rw-r--r--arch/arm/mach-at91/board-dt-sama5.c17
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c2
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h8
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h13
-rw-r--r--arch/arm/mach-bcm/Kconfig1
-rw-r--r--arch/arm/mach-bcm/Makefile4
-rw-r--r--arch/arm/mach-bcm/bcm_kona_smc.c12
-rw-r--r--arch/arm/mach-bcm/bcm_kona_smc.h2
-rw-r--r--arch/arm/mach-bcm/board_bcm281xx.c (renamed from arch/arm/mach-bcm/board_bcm.c)30
-rw-r--r--arch/arm/mach-bcm/kona.c65
-rw-r--r--arch/arm/mach-bcm/kona.h17
-rw-r--r--arch/arm/mach-clps711x/Kconfig3
-rw-r--r--arch/arm/mach-clps711x/Makefile1
-rw-r--r--arch/arm/mach-clps711x/board-autcpu12.c6
-rw-r--r--arch/arm/mach-clps711x/board-edb7211.c17
-rw-r--r--arch/arm/mach-clps711x/board-fortunet.c85
-rw-r--r--arch/arm/mach-clps711x/devices.c2
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c8
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c6
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c6
-rw-r--r--arch/arm/mach-davinci/board-mityomapl138.c6
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c6
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c6
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c6
-rw-r--r--arch/arm/mach-davinci/da830.c8
-rw-r--r--arch/arm/mach-davinci/da850.c8
-rw-r--r--arch/arm/mach-davinci/da8xx-dt.c14
-rw-r--r--arch/arm/mach-davinci/davinci.h5
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c59
-rw-r--r--arch/arm/mach-davinci/devices-tnetv107x.c39
-rw-r--r--arch/arm/mach-davinci/dm355.c51
-rw-r--r--arch/arm/mach-davinci/dm365.c40
-rw-r--r--arch/arm/mach-davinci/dm644x.c54
-rw-r--r--arch/arm/mach-davinci/dm646x.c54
-rw-r--r--arch/arm/mach-davinci/include/mach/common.h1
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
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-rw-r--r--arch/arm/mach-tegra/Makefile6
-rw-r--r--arch/arm/mach-tegra/board-harmony-pcie.c89
-rw-r--r--arch/arm/mach-tegra/board.h8
-rw-r--r--arch/arm/mach-tegra/common.h1
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra114.c51
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra20.c12
-rw-r--r--arch/arm/mach-tegra/cpuidle.c10
-rw-r--r--arch/arm/mach-tegra/cpuidle.h1
-rw-r--r--arch/arm/mach-tegra/flowctrl.c2
-rw-r--r--arch/arm/mach-tegra/flowctrl.h9
-rw-r--r--arch/arm/mach-tegra/headsmp.S3
-rw-r--r--arch/arm/mach-tegra/hotplug.c13
-rw-r--r--arch/arm/mach-tegra/iomap.h11
-rw-r--r--arch/arm/mach-tegra/irq.c40
-rw-r--r--arch/arm/mach-tegra/pcie.c886
-rw-r--r--arch/arm/mach-tegra/platsmp.c1
-rw-r--r--arch/arm/mach-tegra/pm-tegra20.c34
-rw-r--r--arch/arm/mach-tegra/pm-tegra30.c34
-rw-r--r--arch/arm/mach-tegra/pm.c148
-rw-r--r--arch/arm/mach-tegra/pm.h12
-rw-r--r--arch/arm/mach-tegra/pmc.c53
-rw-r--r--arch/arm/mach-tegra/pmc.h3
-rw-r--r--arch/arm/mach-tegra/reset-handler.S21
-rw-r--r--arch/arm/mach-tegra/reset.c2
-rw-r--r--arch/arm/mach-tegra/reset.h4
-rw-r--r--arch/arm/mach-tegra/sleep-tegra20.S297
-rw-r--r--arch/arm/mach-tegra/sleep-tegra30.S616
-rw-r--r--arch/arm/mach-tegra/sleep.S37
-rw-r--r--arch/arm/mach-tegra/sleep.h14
-rw-r--r--arch/arm/mach-tegra/tegra.c24
-rw-r--r--arch/arm/mach-ux500/Kconfig2
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500.c38
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c13
-rw-r--r--arch/arm/mach-ux500/cpu.c8
-rw-r--r--arch/arm/mach-ux500/devices-db8500.c1
-rw-r--r--arch/arm/mach-ux500/headsmp.S2
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h746
-rw-r--r--arch/arm/mach-ux500/setup.h3
-rw-r--r--arch/arm/mach-vexpress/Kconfig10
-rw-r--r--arch/arm/mach-vexpress/Makefile1
-rw-r--r--arch/arm/mach-vexpress/dcscb.c66
-rw-r--r--arch/arm/mach-vexpress/spc.c180
-rw-r--r--arch/arm/mach-vexpress/spc.h24
-rw-r--r--arch/arm/mach-vexpress/tc2_pm.c354
-rw-r--r--arch/arm/mach-zynq/Kconfig2
-rw-r--r--arch/arm/mach-zynq/hotplug.c55
-rw-r--r--arch/arm/mach-zynq/slcr.c45
-rw-r--r--arch/arm/mm/hugetlbpage.c5
-rw-r--r--arch/arm/mm/init.c7
-rw-r--r--arch/arm/plat-omap/Kconfig2
-rw-r--r--arch/arm/plat-omap/dma.c1
-rw-r--r--arch/arm/plat-orion/irq.c2
-rw-r--r--arch/arm/plat-samsung/Kconfig14
-rw-r--r--arch/arm/plat-samsung/Makefile3
-rw-r--r--arch/arm/plat-samsung/dev-backlight.c61
-rw-r--r--arch/arm/plat-samsung/devs.c42
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h4
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/irq-vic-timer.h13
-rw-r--r--arch/arm/plat-samsung/include/plat/irqs.h9
-rw-r--r--arch/arm/plat-samsung/include/plat/pwm-clock.h81
-rw-r--r--arch/arm/plat-samsung/include/plat/pwm-core.h22
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-timer.h124
-rw-r--r--arch/arm/plat-samsung/include/plat/samsung-time.h23
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h38
-rw-r--r--arch/arm/plat-samsung/irq-vic-timer.c98
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c474
-rw-r--r--arch/arm/plat-samsung/s5p-irq.c4
-rw-r--r--arch/arm/plat-samsung/samsung-time.c394
-rw-r--r--arch/arm/xen/enlighten.c14
639 files changed, 23615 insertions, 28891 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d1f5704a284..c8a916fcd54b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -442,7 +442,6 @@ config ARCH_NETX
442config ARCH_IOP13XX 442config ARCH_IOP13XX
443 bool "IOP13xx-based" 443 bool "IOP13xx-based"
444 depends on MMU 444 depends on MMU
445 select ARCH_SUPPORTS_MSI
446 select CPU_XSC3 445 select CPU_XSC3
447 select NEED_MACH_MEMORY_H 446 select NEED_MACH_MEMORY_H
448 select NEED_RET_TO_USER 447 select NEED_RET_TO_USER
@@ -558,6 +557,7 @@ config ARCH_MMP
558 select GENERIC_CLOCKEVENTS 557 select GENERIC_CLOCKEVENTS
559 select GPIO_PXA 558 select GPIO_PXA
560 select IRQ_DOMAIN 559 select IRQ_DOMAIN
560 select MULTI_IRQ_HANDLER
561 select NEED_MACH_GPIO_H 561 select NEED_MACH_GPIO_H
562 select PINCTRL 562 select PINCTRL
563 select PLAT_PXA 563 select PLAT_PXA
@@ -631,6 +631,7 @@ config ARCH_MSM
631 bool "Qualcomm MSM" 631 bool "Qualcomm MSM"
632 select ARCH_REQUIRE_GPIOLIB 632 select ARCH_REQUIRE_GPIOLIB
633 select CLKDEV_LOOKUP 633 select CLKDEV_LOOKUP
634 select CLKSRC_OF if OF
634 select COMMON_CLK 635 select COMMON_CLK
635 select GENERIC_CLOCKEVENTS 636 select GENERIC_CLOCKEVENTS
636 help 637 help
@@ -646,7 +647,7 @@ config ARCH_SHMOBILE
646 select CLKDEV_LOOKUP 647 select CLKDEV_LOOKUP
647 select GENERIC_CLOCKEVENTS 648 select GENERIC_CLOCKEVENTS
648 select HAVE_ARM_SCU if SMP 649 select HAVE_ARM_SCU if SMP
649 select HAVE_ARM_TWD if LOCAL_TIMERS 650 select HAVE_ARM_TWD if SMP
650 select HAVE_CLK 651 select HAVE_CLK
651 select HAVE_MACH_CLKDEV 652 select HAVE_MACH_CLKDEV
652 select HAVE_SMP 653 select HAVE_SMP
@@ -701,7 +702,7 @@ config ARCH_S3C24XX
701 select ARCH_HAS_CPUFREQ 702 select ARCH_HAS_CPUFREQ
702 select ARCH_REQUIRE_GPIOLIB 703 select ARCH_REQUIRE_GPIOLIB
703 select CLKDEV_LOOKUP 704 select CLKDEV_LOOKUP
704 select CLKSRC_MMIO 705 select CLKSRC_SAMSUNG_PWM
705 select GENERIC_CLOCKEVENTS 706 select GENERIC_CLOCKEVENTS
706 select GPIO_SAMSUNG 707 select GPIO_SAMSUNG
707 select HAVE_CLK 708 select HAVE_CLK
@@ -724,7 +725,7 @@ config ARCH_S3C64XX
724 select ARCH_REQUIRE_GPIOLIB 725 select ARCH_REQUIRE_GPIOLIB
725 select ARM_VIC 726 select ARM_VIC
726 select CLKDEV_LOOKUP 727 select CLKDEV_LOOKUP
727 select CLKSRC_MMIO 728 select CLKSRC_SAMSUNG_PWM
728 select CPU_V6 729 select CPU_V6
729 select GENERIC_CLOCKEVENTS 730 select GENERIC_CLOCKEVENTS
730 select GPIO_SAMSUNG 731 select GPIO_SAMSUNG
@@ -740,7 +741,6 @@ config ARCH_S3C64XX
740 select SAMSUNG_ATAGS 741 select SAMSUNG_ATAGS
741 select SAMSUNG_CLKSRC 742 select SAMSUNG_CLKSRC
742 select SAMSUNG_GPIOLIB_4BIT 743 select SAMSUNG_GPIOLIB_4BIT
743 select SAMSUNG_IRQ_VIC_TIMER
744 select SAMSUNG_WDT_RESET 744 select SAMSUNG_WDT_RESET
745 select USB_ARCH_HAS_OHCI 745 select USB_ARCH_HAS_OHCI
746 help 746 help
@@ -749,7 +749,7 @@ config ARCH_S3C64XX
749config ARCH_S5P64X0 749config ARCH_S5P64X0
750 bool "Samsung S5P6440 S5P6450" 750 bool "Samsung S5P6440 S5P6450"
751 select CLKDEV_LOOKUP 751 select CLKDEV_LOOKUP
752 select CLKSRC_MMIO 752 select CLKSRC_SAMSUNG_PWM
753 select CPU_V6 753 select CPU_V6
754 select GENERIC_CLOCKEVENTS 754 select GENERIC_CLOCKEVENTS
755 select GPIO_SAMSUNG 755 select GPIO_SAMSUNG
@@ -768,7 +768,7 @@ config ARCH_S5PC100
768 bool "Samsung S5PC100" 768 bool "Samsung S5PC100"
769 select ARCH_REQUIRE_GPIOLIB 769 select ARCH_REQUIRE_GPIOLIB
770 select CLKDEV_LOOKUP 770 select CLKDEV_LOOKUP
771 select CLKSRC_MMIO 771 select CLKSRC_SAMSUNG_PWM
772 select CPU_V7 772 select CPU_V7
773 select GENERIC_CLOCKEVENTS 773 select GENERIC_CLOCKEVENTS
774 select GPIO_SAMSUNG 774 select GPIO_SAMSUNG
@@ -788,7 +788,7 @@ config ARCH_S5PV210
788 select ARCH_HAS_HOLES_MEMORYMODEL 788 select ARCH_HAS_HOLES_MEMORYMODEL
789 select ARCH_SPARSEMEM_ENABLE 789 select ARCH_SPARSEMEM_ENABLE
790 select CLKDEV_LOOKUP 790 select CLKDEV_LOOKUP
791 select CLKSRC_MMIO 791 select CLKSRC_SAMSUNG_PWM
792 select CPU_V7 792 select CPU_V7
793 select GENERIC_CLOCKEVENTS 793 select GENERIC_CLOCKEVENTS
794 select GPIO_SAMSUNG 794 select GPIO_SAMSUNG
@@ -1594,23 +1594,13 @@ config ARM_PSCI
1594 0022A ("Power State Coordination Interface System Software on 1594 0022A ("Power State Coordination Interface System Software on
1595 ARM processors"). 1595 ARM processors").
1596 1596
1597config LOCAL_TIMERS
1598 bool "Use local timer interrupts"
1599 depends on SMP
1600 default y
1601 help
1602 Enable support for local timers on SMP platforms, rather then the
1603 legacy IPI broadcast method. Local timers allows the system
1604 accounting to be spread across the timer interval, preventing a
1605 "thundering herd" at every timer tick.
1606
1607# The GPIO number here must be sorted by descending number. In case of 1597# The GPIO number here must be sorted by descending number. In case of
1608# a multiplatform kernel, we just want the highest value required by the 1598# a multiplatform kernel, we just want the highest value required by the
1609# selected platforms. 1599# selected platforms.
1610config ARCH_NR_GPIO 1600config ARCH_NR_GPIO
1611 int 1601 int
1612 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA 1602 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1613 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 1603 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1614 default 392 if ARCH_U8500 1604 default 392 if ARCH_U8500
1615 default 352 if ARCH_VT8500 1605 default 352 if ARCH_VT8500
1616 default 288 if ARCH_SUNXI 1606 default 288 if ARCH_SUNXI
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 4137529850cb..9762c84b4198 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -895,6 +895,11 @@ config DEBUG_LL_INCLUDE
895 DEBUG_IMX53_UART ||\ 895 DEBUG_IMX53_UART ||\
896 DEBUG_IMX6Q_UART || \ 896 DEBUG_IMX6Q_UART || \
897 DEBUG_IMX6SL_UART 897 DEBUG_IMX6SL_UART
898 default "debug/msm.S" if DEBUG_MSM_UART1 || \
899 DEBUG_MSM_UART2 || \
900 DEBUG_MSM_UART3 || \
901 DEBUG_MSM8660_UART || \
902 DEBUG_MSM8960_UART
898 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART 903 default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
899 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 904 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
900 default "debug/sti.S" if DEBUG_STI_UART 905 default "debug/sti.S" if DEBUG_STI_UART
@@ -1056,7 +1061,7 @@ config DEBUG_UART_8250_FLOW_CONTROL
1056 1061
1057config DEBUG_UNCOMPRESS 1062config DEBUG_UNCOMPRESS
1058 bool 1063 bool
1059 depends on ARCH_MULTIPLATFORM 1064 depends on ARCH_MULTIPLATFORM || ARCH_MSM
1060 default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \ 1065 default y if DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
1061 (!DEBUG_TEGRA_UART || !ZBOOT_ROM) 1066 (!DEBUG_TEGRA_UART || !ZBOOT_ROM)
1062 help 1067 help
@@ -1072,7 +1077,7 @@ config DEBUG_UNCOMPRESS
1072 1077
1073config UNCOMPRESS_INCLUDE 1078config UNCOMPRESS_INCLUDE
1074 string 1079 string
1075 default "debug/uncompress.h" if ARCH_MULTIPLATFORM 1080 default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM
1076 default "mach/uncompress.h" 1081 default "mach/uncompress.h"
1077 1082
1078config EARLY_PRINTK 1083config EARLY_PRINTK
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6fd2ceae305a..a37a50f575a2 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -190,6 +190,7 @@ machine-$(CONFIG_ARCH_S5PV210) += s5pv210
190machine-$(CONFIG_ARCH_SA1100) += sa1100 190machine-$(CONFIG_ARCH_SA1100) += sa1100
191machine-$(CONFIG_ARCH_SHARK) += shark 191machine-$(CONFIG_ARCH_SHARK) += shark
192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
193machine-$(CONFIG_ARCH_SHMOBILE_MULTI) += shmobile
193machine-$(CONFIG_ARCH_SIRF) += prima2 194machine-$(CONFIG_ARCH_SIRF) += prima2
194machine-$(CONFIG_ARCH_SOCFPGA) += socfpga 195machine-$(CONFIG_ARCH_SOCFPGA) += socfpga
195machine-$(CONFIG_ARCH_STI) += sti 196machine-$(CONFIG_ARCH_STI) += sti
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index e2d636336b7c..e7f80928949c 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -55,12 +55,47 @@ __tmp_stack:
55__continue: 55__continue:
56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ 56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
57 57
58 /* Set board ID necessary for boot */ 58 adr r0, dtb_info
59 ldr r7, 1f @ Set machine type register 59 ldmia r0, {r1, r3, r4, r5, r7}
60 mov r8, #0 @ pass null pointer as atag 60
61 sub r0, r0, r1 @ calculate the delta offset
62 add r5, r5, r0 @ _edata
63
64 ldr lr, [r5, #0] @ check if valid DTB is present
65 cmp lr, r3
66 bne 0f
67
68 add r9, r7, #31 @ rounded up to a multiple
69 bic r9, r9, #31 @ ... of 32 bytes
70
71 add r6, r9, r5 @ copy from _edata
72 add r9, r9, r4 @ to MEMORY_START
73
741: ldmdb r6!, {r0 - r3, r10 - r12, lr}
75 cmp r6, r5
76 stmdb r9!, {r0 - r3, r10 - r12, lr}
77 bhi 1b
78
79 /* Success: Zero board ID, pointer to start of memory for atag/dtb */
80 mov r7, #0
81 mov r8, r4
61 b 2f 82 b 2f
62 83
631 : .long MACH_TYPE 84 .align 2
85dtb_info:
86 .word dtb_info
87#ifndef __ARMEB__
88 .word 0xedfe0dd0 @ sig is 0xd00dfeed big endian
89#else
90 .word 0xd00dfeed
91#endif
92 .word MEMORY_START
93 .word _edata
94 .word 0x4000 @ maximum DTB size
950:
96 /* Failure: Zero board ID, NULL atag/dtb */
97 mov r7, #0
98 mov r8, #0 @ pass null pointer as atag
642 : 992 :
65 100
66#endif /* CONFIG_ZBOOT_ROM */ 101#endif /* CONFIG_ZBOOT_ROM */
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 641b3c9a7028..cc0f1fb61753 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -42,24 +42,27 @@ dtb-$(CONFIG_ARCH_AT91) += sama5d34ek.dtb
42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb 42dtb-$(CONFIG_ARCH_AT91) += sama5d35ek.dtb
43 43
44dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb 44dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
45dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb 45dtb-$(CONFIG_ARCH_BCM) += bcm11351-brt.dtb \
46 bcm28155-ap.dtb
46dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 47dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
47 da850-evm.dtb 48 da850-evm.dtb
48dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \ 49dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
49 dove-cubox.dtb \ 50 dove-cubox.dtb \
51 dove-d2plug.dtb \
50 dove-dove-db.dtb 52 dove-dove-db.dtb
51dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \ 53dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
52 exynos4210-smdkv310.dtb \ 54 exynos4210-smdkv310.dtb \
53 exynos4210-trats.dtb \ 55 exynos4210-trats.dtb \
54 exynos4210-universal_c210.dtb \ 56 exynos4210-universal_c210.dtb \
55 exynos4412-odroidx.dtb \ 57 exynos4412-odroidx.dtb \
56 exynos4412-smdk4412.dtb \
57 exynos4412-origen.dtb \ 58 exynos4412-origen.dtb \
59 exynos4412-smdk4412.dtb \
60 exynos4412-trats2.dtb \
58 exynos5250-arndale.dtb \ 61 exynos5250-arndale.dtb \
59 exynos5440-sd5v1.dtb \
60 exynos5250-smdk5250.dtb \ 62 exynos5250-smdk5250.dtb \
61 exynos5250-snow.dtb \ 63 exynos5250-snow.dtb \
62 exynos5420-smdk5420.dtb \ 64 exynos5420-smdk5420.dtb \
65 exynos5440-sd5v1.dtb \
63 exynos5440-ssdk5440.dtb 66 exynos5440-ssdk5440.dtb
64dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \ 67dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
65 ecx-2000.dtb 68 ecx-2000.dtb
@@ -83,12 +86,14 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
83 kirkwood-lschlv2.dtb \ 86 kirkwood-lschlv2.dtb \
84 kirkwood-lsxhl.dtb \ 87 kirkwood-lsxhl.dtb \
85 kirkwood-mplcec4.dtb \ 88 kirkwood-mplcec4.dtb \
89 kirkwood-mv88f6281gtw-ge.dtb \
86 kirkwood-netgear_readynas_duo_v2.dtb \ 90 kirkwood-netgear_readynas_duo_v2.dtb \
87 kirkwood-ns2.dtb \ 91 kirkwood-ns2.dtb \
88 kirkwood-ns2lite.dtb \ 92 kirkwood-ns2lite.dtb \
89 kirkwood-ns2max.dtb \ 93 kirkwood-ns2max.dtb \
90 kirkwood-ns2mini.dtb \ 94 kirkwood-ns2mini.dtb \
91 kirkwood-nsa310.dtb \ 95 kirkwood-nsa310.dtb \
96 kirkwood-nsa310a.dtb \
92 kirkwood-sheevaplug.dtb \ 97 kirkwood-sheevaplug.dtb \
93 kirkwood-sheevaplug-esata.dtb \ 98 kirkwood-sheevaplug-esata.dtb \
94 kirkwood-topkick.dtb \ 99 kirkwood-topkick.dtb \
@@ -100,7 +105,9 @@ dtb-$(CONFIG_ARCH_MSM) += msm8660-surf.dtb \
100 msm8960-cdp.dtb 105 msm8960-cdp.dtb
101dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \ 106dtb-$(CONFIG_ARCH_MVEBU) += armada-370-db.dtb \
102 armada-370-mirabox.dtb \ 107 armada-370-mirabox.dtb \
108 armada-370-netgear-rn102.dtb \
103 armada-370-rd.dtb \ 109 armada-370-rd.dtb \
110 armada-xp-axpwifiap.dtb \
104 armada-xp-db.dtb \ 111 armada-xp-db.dtb \
105 armada-xp-gp.dtb \ 112 armada-xp-gp.dtb \
106 armada-xp-openblocks-ax3-4.dtb 113 armada-xp-openblocks-ax3-4.dtb
@@ -112,6 +119,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
112 imx27-pdk.dtb \ 119 imx27-pdk.dtb \
113 imx27-phytec-phycore-som.dtb \ 120 imx27-phytec-phycore-som.dtb \
114 imx27-phytec-phycore-rdk.dtb \ 121 imx27-phytec-phycore-rdk.dtb \
122 imx27-phytec-phycard-s-som.dtb \
123 imx27-phytec-phycard-s-rdk.dtb \
115 imx31-bug.dtb \ 124 imx31-bug.dtb \
116 imx51-apf51.dtb \ 125 imx51-apf51.dtb \
117 imx51-apf51dev.dtb \ 126 imx51-apf51dev.dtb \
@@ -131,6 +140,7 @@ dtb-$(CONFIG_ARCH_MXC) += \
131 imx6q-sabrelite.dtb \ 140 imx6q-sabrelite.dtb \
132 imx6q-sabresd.dtb \ 141 imx6q-sabresd.dtb \
133 imx6q-sbc6x.dtb \ 142 imx6q-sbc6x.dtb \
143 imx6q-wandboard.dtb \
134 imx6sl-evk.dtb \ 144 imx6sl-evk.dtb \
135 vf610-twr.dtb 145 vf610-twr.dtb
136dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \ 146dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
@@ -143,7 +153,9 @@ dtb-$(CONFIG_ARCH_MXS) += imx23-evk.dtb \
143 imx28-cfa10037.dtb \ 153 imx28-cfa10037.dtb \
144 imx28-cfa10049.dtb \ 154 imx28-cfa10049.dtb \
145 imx28-cfa10055.dtb \ 155 imx28-cfa10055.dtb \
156 imx28-cfa10056.dtb \
146 imx28-cfa10057.dtb \ 157 imx28-cfa10057.dtb \
158 imx28-cfa10058.dtb \
147 imx28-evk.dtb \ 159 imx28-evk.dtb \
148 imx28-m28evk.dtb \ 160 imx28-m28evk.dtb \
149 imx28-sps1.dtb \ 161 imx28-sps1.dtb \
@@ -176,22 +188,28 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
176 am43x-epos-evm.dtb 188 am43x-epos-evm.dtb
177dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 189dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
178dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 190dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
179dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \ 191dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
180 hrefprev60.dtb \ 192 ste-hrefprev60.dtb \
181 hrefv60plus.dtb \ 193 ste-hrefv60plus.dtb \
182 ccu8540.dtb \ 194 ste-ccu8540.dtb \
183 ccu9540.dtb 195 ste-ccu9540.dtb
184dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 196dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
185dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \ 197dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
198 emev2-kzm9d-reference.dtb \
186 r8a7740-armadillo800eva.dtb \ 199 r8a7740-armadillo800eva.dtb \
187 r8a7778-bockw.dtb \ 200 r8a7778-bockw.dtb \
201 r8a7778-bockw-reference.dtb \
188 r8a7740-armadillo800eva-reference.dtb \ 202 r8a7740-armadillo800eva-reference.dtb \
203 r8a7779-marzen.dtb \
189 r8a7779-marzen-reference.dtb \ 204 r8a7779-marzen-reference.dtb \
190 r8a7790-lager.dtb \ 205 r8a7790-lager.dtb \
206 r8a7790-lager-reference.dtb \
191 sh73a0-kzm9g.dtb \ 207 sh73a0-kzm9g.dtb \
192 sh73a0-kzm9g-reference.dtb \ 208 sh73a0-kzm9g-reference.dtb \
193 r8a73a4-ape6evm.dtb \ 209 r8a73a4-ape6evm.dtb \
210 r8a73a4-ape6evm-reference.dtb \
194 sh7372-mackerel.dtb 211 sh7372-mackerel.dtb
212dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += emev2-kzm9d-reference.dtb
195dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \ 213dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
196 socfpga_vt.dtb 214 socfpga_vt.dtb
197dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \ 215dtb-$(CONFIG_ARCH_SPEAR13XX) += spear1310-evb.dtb \
@@ -206,11 +224,15 @@ dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
206 stih415-b2020.dtb \ 224 stih415-b2020.dtb \
207 stih416-b2020.dtb 225 stih416-b2020.dtb
208dtb-$(CONFIG_ARCH_SUNXI) += \ 226dtb-$(CONFIG_ARCH_SUNXI) += \
227 sun4i-a10-a1000.dtb \
209 sun4i-a10-cubieboard.dtb \ 228 sun4i-a10-cubieboard.dtb \
210 sun4i-a10-mini-xplus.dtb \ 229 sun4i-a10-mini-xplus.dtb \
211 sun4i-a10-hackberry.dtb \ 230 sun4i-a10-hackberry.dtb \
212 sun5i-a10s-olinuxino-micro.dtb \ 231 sun5i-a10s-olinuxino-micro.dtb \
213 sun5i-a13-olinuxino.dtb 232 sun5i-a13-olinuxino.dtb \
233 sun6i-a31-colombus.dtb \
234 sun7i-a20-cubieboard2.dtb \
235 sun7i-a20-olinuxino-micro.dtb
214dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 236dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
215 tegra20-iris-512.dtb \ 237 tegra20-iris-512.dtb \
216 tegra20-medcom-wide.dtb \ 238 tegra20-medcom-wide.dtb \
@@ -224,8 +246,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
224 tegra30-beaver.dtb \ 246 tegra30-beaver.dtb \
225 tegra30-cardhu-a02.dtb \ 247 tegra30-cardhu-a02.dtb \
226 tegra30-cardhu-a04.dtb \ 248 tegra30-cardhu-a04.dtb \
227 tegra114-dalmore.dtb \ 249 tegra114-dalmore.dtb
228 tegra114-pluto.dtb
229dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \ 250dtb-$(CONFIG_ARCH_VERSATILE) += versatile-ab.dtb \
230 versatile-pb.dtb 251 versatile-pb.dtb
231dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb 252dtb-$(CONFIG_ARCH_U300) += ste-u300.dtb
diff --git a/arch/arm/boot/dts/armada-370-db.dts b/arch/arm/boot/dts/armada-370-db.dts
index beee1699d49e..90ce29dbe119 100644
--- a/arch/arm/boot/dts/armada-370-db.dts
+++ b/arch/arm/boot/dts/armada-370-db.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-370.dtsi" 17#include "armada-370.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada 370 Evaluation Board"; 20 model = "Marvell Armada 370 Evaluation Board";
@@ -30,6 +30,9 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
34 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
35
33 internal-regs { 36 internal-regs {
34 serial@12000 { 37 serial@12000 {
35 clock-frequency = <200000000>; 38 clock-frequency = <200000000>;
diff --git a/arch/arm/boot/dts/armada-370-mirabox.dts b/arch/arm/boot/dts/armada-370-mirabox.dts
index 45b107763e3b..2471d9da767b 100644
--- a/arch/arm/boot/dts/armada-370-mirabox.dts
+++ b/arch/arm/boot/dts/armada-370-mirabox.dts
@@ -9,7 +9,7 @@
9 */ 9 */
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "armada-370.dtsi" 12#include "armada-370.dtsi"
13 13
14/ { 14/ {
15 model = "Globalscale Mirabox"; 15 model = "Globalscale Mirabox";
@@ -25,6 +25,25 @@
25 }; 25 };
26 26
27 soc { 27 soc {
28 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
29 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
30
31 pcie-controller {
32 status = "okay";
33
34 /* Internal mini-PCIe connector */
35 pcie@1,0 {
36 /* Port 0, Lane 0 */
37 status = "okay";
38 };
39
40 /* Connected on the PCB to a USB 3.0 XHCI controller */
41 pcie@2,0 {
42 /* Port 1, Lane 0 */
43 status = "okay";
44 };
45 };
46
28 internal-regs { 47 internal-regs {
29 serial@12000 { 48 serial@12000 {
30 clock-frequency = <200000000>; 49 clock-frequency = <200000000>;
@@ -120,22 +139,6 @@
120 reg = <0x25>; 139 reg = <0x25>;
121 }; 140 };
122 }; 141 };
123
124 pcie-controller {
125 status = "okay";
126
127 /* Internal mini-PCIe connector */
128 pcie@1,0 {
129 /* Port 0, Lane 0 */
130 status = "okay";
131 };
132
133 /* Connected on the PCB to a USB 3.0 XHCI controller */
134 pcie@2,0 {
135 /* Port 1, Lane 0 */
136 status = "okay";
137 };
138 };
139 }; 142 };
140 }; 143 };
141}; 144};
diff --git a/arch/arm/boot/dts/armada-370-netgear-rn102.dts b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
new file mode 100644
index 000000000000..05e4485a8225
--- /dev/null
+++ b/arch/arm/boot/dts/armada-370-netgear-rn102.dts
@@ -0,0 +1,179 @@
1/*
2 * Device Tree file for NETGEAR ReadyNAS 102
3 *
4 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include "armada-370.dtsi"
15
16/ {
17 model = "NETGEAR ReadyNAS 102";
18 compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
19
20 chosen {
21 bootargs = "console=ttyS0,115200 earlyprintk";
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x20000000>; /* 512 MB */
27 };
28
29 soc {
30 internal-regs {
31 serial@12000 {
32 clock-frequency = <200000000>;
33 status = "okay";
34 };
35
36 sata@a0000 {
37 nr-ports = <2>;
38 status = "okay";
39 };
40
41 pinctrl {
42 power_led_pin: power-led-pin {
43 marvell,pins = "mpp57";
44 marvell,function = "gpio";
45 };
46 sata1_led_pin: sata1-led-pin {
47 marvell,pins = "mpp15";
48 marvell,function = "gpio";
49 };
50
51 sata2_led_pin: sata2-led-pin {
52 marvell,pins = "mpp14";
53 marvell,function = "gpio";
54 };
55
56 backup_led_pin: backup-led-pin {
57 marvell,pins = "mpp56";
58 marvell,function = "gpio";
59 };
60 };
61
62 mdio {
63 phy0: ethernet-phy@0 {
64 reg = <0>;
65 };
66 };
67
68 ethernet@74000 {
69 status = "okay";
70 phy = <&phy0>;
71 phy-mode = "rgmii-id";
72 };
73
74 usb@50000 {
75 status = "okay";
76 };
77
78 i2c@11000 {
79 compatible = "marvell,mv64xxx-i2c";
80 clock-frequency = <100000>;
81 status = "okay";
82
83 g762: g762@3e {
84 compatible = "gmt,g762";
85 reg = <0x3e>;
86 clocks = <&g762_clk>; /* input clock */
87 fan_gear_mode = <0>;
88 fan_startv = <1>;
89 pwm_polarity = <0>;
90 };
91 };
92
93 pcie-controller {
94 status = "okay";
95
96 /* Connected to Marvell SATA controller */
97 pcie@1,0 {
98 /* Port 0, Lane 0 */
99 status = "okay";
100 };
101
102 /* Connected to FL1009 USB 3.0 controller */
103 pcie@2,0 {
104 /* Port 1, Lane 0 */
105 status = "okay";
106 };
107 };
108 };
109 };
110
111 clocks {
112 #address-cells = <1>;
113 #size-cells = <0>;
114
115 g762_clk: fixedclk {
116 compatible = "fixed-clock";
117 #clock-cells = <0>;
118 clock-frequency = <8192>;
119 };
120 };
121
122 gpio_leds {
123 compatible = "gpio-leds";
124 pinctrl-0 = < &power_led_pin
125 &sata1_led_pin
126 &sata2_led_pin
127 &backup_led_pin >;
128 pinctrl-names = "default";
129
130 blue_power_led {
131 label = "rn102:blue:pwr";
132 gpios = <&gpio1 25 1>; /* GPIO 57 Active Low */
133 linux,default-trigger = "heartbeat";
134 };
135
136 green_sata1_led {
137 label = "rn102:green:sata1";
138 gpios = <&gpio0 15 1>; /* GPIO 15 Active Low */
139 default-state = "on";
140 };
141
142 green_sata2_led {
143 label = "rn102:green:sata2";
144 gpios = <&gpio0 14 1>; /* GPIO 14 Active Low */
145 default-state = "on";
146 };
147
148 green_backup_led {
149 label = "rn102:green:backup";
150 gpios = <&gpio1 24 1>; /* GPIO 56 Active Low */
151 default-state = "on";
152 };
153 };
154
155 gpio_keys {
156 compatible = "gpio-keys";
157 #address-cells = <1>;
158 #size-cells = <0>;
159
160 button@1 {
161 label = "Power Button";
162 linux,code = <116>; /* KEY_POWER */
163 gpios = <&gpio1 30 1>;
164 };
165
166 button@2 {
167 label = "Reset Button";
168 linux,code = <0x198>; /* KEY_RESTART */
169 gpios = <&gpio0 6 1>;
170 };
171
172 button@3 {
173 label = "Backup Button";
174 linux,code = <133>; /* KEY_COPY */
175 gpios = <&gpio1 26 1>;
176 };
177 };
178
179};
diff --git a/arch/arm/boot/dts/armada-370-rd.dts b/arch/arm/boot/dts/armada-370-rd.dts
index a3a2fedb8726..f81810a59629 100644
--- a/arch/arm/boot/dts/armada-370-rd.dts
+++ b/arch/arm/boot/dts/armada-370-rd.dts
@@ -12,7 +12,7 @@
12 */ 12 */
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "armada-370.dtsi" 15#include "armada-370.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell Armada 370 Reference Design"; 18 model = "Marvell Armada 370 Reference Design";
@@ -28,6 +28,25 @@
28 }; 28 };
29 29
30 soc { 30 soc {
31 ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
32 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
33
34 pcie-controller {
35 status = "okay";
36
37 /* Internal mini-PCIe connector */
38 pcie@1,0 {
39 /* Port 0, Lane 0 */
40 status = "okay";
41 };
42
43 /* Internal mini-PCIe connector */
44 pcie@2,0 {
45 /* Port 1, Lane 0 */
46 status = "okay";
47 };
48 };
49
31 internal-regs { 50 internal-regs {
32 serial@12000 { 51 serial@12000 {
33 clock-frequency = <200000000>; 52 clock-frequency = <200000000>;
@@ -85,22 +104,6 @@
85 gpios = <&gpio0 6 1>; 104 gpios = <&gpio0 6 1>;
86 }; 105 };
87 }; 106 };
88
89 pcie-controller {
90 status = "okay";
91
92 /* Internal mini-PCIe connector */
93 pcie@1,0 {
94 /* Port 0, Lane 0 */
95 status = "okay";
96 };
97
98 /* Internal mini-PCIe connector */
99 pcie@2,0 {
100 /* Port 1, Lane 0 */
101 status = "okay";
102 };
103 };
104 }; 107 };
105 }; 108 };
106 }; 109 };
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 90b117624abb..1de2dae0fdae 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -18,6 +18,8 @@
18 18
19/include/ "skeleton64.dtsi" 19/include/ "skeleton64.dtsi"
20 20
21#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
22
21/ { 23/ {
22 model = "Marvell Armada 370 and XP SoC"; 24 model = "Marvell Armada 370 and XP SoC";
23 compatible = "marvell,armada-370-xp"; 25 compatible = "marvell,armada-370-xp";
@@ -38,18 +40,73 @@
38 }; 40 };
39 41
40 soc { 42 soc {
41 #address-cells = <1>; 43 #address-cells = <2>;
42 #size-cells = <1>; 44 #size-cells = <1>;
43 compatible = "simple-bus"; 45 controller = <&mbusc>;
44 interrupt-parent = <&mpic>; 46 interrupt-parent = <&mpic>;
45 ranges = <0 0 0xd0000000 0x0100000 /* internal registers */ 47 pcie-mem-aperture = <0xe0000000 0x8000000>;
46 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */>; 48 pcie-io-aperture = <0xe8000000 0x100000>;
49
50 devbus-bootcs {
51 compatible = "marvell,mvebu-devbus";
52 reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
53 ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56 clocks = <&coreclk 0>;
57 status = "disabled";
58 };
59
60 devbus-cs0 {
61 compatible = "marvell,mvebu-devbus";
62 reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
63 ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
64 #address-cells = <1>;
65 #size-cells = <1>;
66 clocks = <&coreclk 0>;
67 status = "disabled";
68 };
69
70 devbus-cs1 {
71 compatible = "marvell,mvebu-devbus";
72 reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
73 ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
74 #address-cells = <1>;
75 #size-cells = <1>;
76 clocks = <&coreclk 0>;
77 status = "disabled";
78 };
79
80 devbus-cs2 {
81 compatible = "marvell,mvebu-devbus";
82 reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
83 ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
84 #address-cells = <1>;
85 #size-cells = <1>;
86 clocks = <&coreclk 0>;
87 status = "disabled";
88 };
89
90 devbus-cs3 {
91 compatible = "marvell,mvebu-devbus";
92 reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
93 ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
94 #address-cells = <1>;
95 #size-cells = <1>;
96 clocks = <&coreclk 0>;
97 status = "disabled";
98 };
47 99
48 internal-regs { 100 internal-regs {
49 compatible = "simple-bus"; 101 compatible = "simple-bus";
50 #address-cells = <1>; 102 #address-cells = <1>;
51 #size-cells = <1>; 103 #size-cells = <1>;
52 ranges; 104 ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
105
106 mbusc: mbus-controller@20000 {
107 compatible = "marvell,mbus-controller";
108 reg = <0x20000 0x100>, <0x20180 0x20>;
109 };
53 110
54 mpic: interrupt-controller@20000 { 111 mpic: interrupt-controller@20000 {
55 compatible = "marvell,mpic"; 112 compatible = "marvell,mpic";
@@ -81,10 +138,8 @@
81 }; 138 };
82 139
83 timer@20300 { 140 timer@20300 {
84 compatible = "marvell,armada-370-xp-timer";
85 reg = <0x20300 0x30>, <0x21040 0x30>; 141 reg = <0x20300 0x30>, <0x21040 0x30>;
86 interrupts = <37>, <38>, <39>, <40>, <5>, <6>; 142 interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
87 clocks = <&coreclk 2>;
88 }; 143 };
89 144
90 sata@a0000 { 145 sata@a0000 {
@@ -195,50 +250,6 @@
195 status = "disabled"; 250 status = "disabled";
196 }; 251 };
197 252
198 devbus-bootcs@10400 {
199 compatible = "marvell,mvebu-devbus";
200 reg = <0x10400 0x8>;
201 #address-cells = <1>;
202 #size-cells = <1>;
203 clocks = <&coreclk 0>;
204 status = "disabled";
205 };
206
207 devbus-cs0@10408 {
208 compatible = "marvell,mvebu-devbus";
209 reg = <0x10408 0x8>;
210 #address-cells = <1>;
211 #size-cells = <1>;
212 clocks = <&coreclk 0>;
213 status = "disabled";
214 };
215
216 devbus-cs1@10410 {
217 compatible = "marvell,mvebu-devbus";
218 reg = <0x10410 0x8>;
219 #address-cells = <1>;
220 #size-cells = <1>;
221 clocks = <&coreclk 0>;
222 status = "disabled";
223 };
224
225 devbus-cs2@10418 {
226 compatible = "marvell,mvebu-devbus";
227 reg = <0x10418 0x8>;
228 #address-cells = <1>;
229 #size-cells = <1>;
230 clocks = <&coreclk 0>;
231 status = "disabled";
232 };
233
234 devbus-cs3@10420 {
235 compatible = "marvell,mvebu-devbus";
236 reg = <0x10420 0x8>;
237 #address-cells = <1>;
238 #size-cells = <1>;
239 clocks = <&coreclk 0>;
240 status = "disabled";
241 };
242 }; 253 };
243 }; 254 };
244 }; 255 };
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index fa3dfc6b4c6a..e134d7a90c9a 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -15,7 +15,7 @@
15 * common to all Armada SoCs. 15 * common to all Armada SoCs.
16 */ 16 */
17 17
18/include/ "armada-370-xp.dtsi" 18#include "armada-370-xp.dtsi"
19/include/ "skeleton.dtsi" 19/include/ "skeleton.dtsi"
20 20
21/ { 21/ {
@@ -29,8 +29,66 @@
29 }; 29 };
30 30
31 soc { 31 soc {
32 ranges = <0 0xd0000000 0x0100000 /* internal registers */ 32 compatible = "marvell,armada370-mbus", "simple-bus";
33 0xe0000000 0xe0000000 0x8100000 /* PCIe */>; 33
34 bootrom {
35 compatible = "marvell,bootrom";
36 reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
37 };
38
39 pcie-controller {
40 compatible = "marvell,armada-370-pcie";
41 status = "disabled";
42 device_type = "pci";
43
44 #address-cells = <3>;
45 #size-cells = <2>;
46
47 bus-range = <0x00 0xff>;
48
49 ranges =
50 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
51 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
52 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
53 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
54 0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
55 0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
56
57 pcie@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
60 reg = <0x0800 0 0 0 0>;
61 #address-cells = <3>;
62 #size-cells = <2>;
63 #interrupt-cells = <1>;
64 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
65 0x81000000 0 0 0x81000000 0x1 0 1 0>;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &mpic 58>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gateclk 5>;
71 status = "disabled";
72 };
73
74 pcie@2,0 {
75 device_type = "pci";
76 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
77 reg = <0x1000 0 0 0 0>;
78 #address-cells = <3>;
79 #size-cells = <2>;
80 #interrupt-cells = <1>;
81 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
82 0x81000000 0 0 0x81000000 0x2 0 1 0>;
83 interrupt-map-mask = <0 0 0 0>;
84 interrupt-map = <0 0 0 0 &mpic 62>;
85 marvell,pcie-port = <1>;
86 marvell,pcie-lane = <0>;
87 clocks = <&gateclk 9>;
88 status = "disabled";
89 };
90 };
91
34 internal-regs { 92 internal-regs {
35 system-controller@18200 { 93 system-controller@18200 {
36 compatible = "marvell,armada-370-xp-system-controller"; 94 compatible = "marvell,armada-370-xp-system-controller";
@@ -78,7 +136,7 @@
78 gpio-controller; 136 gpio-controller;
79 #gpio-cells = <2>; 137 #gpio-cells = <2>;
80 interrupt-controller; 138 interrupt-controller;
81 #interrupts-cells = <2>; 139 #interrupt-cells = <2>;
82 interrupts = <82>, <83>, <84>, <85>; 140 interrupts = <82>, <83>, <84>, <85>;
83 }; 141 };
84 142
@@ -89,7 +147,7 @@
89 gpio-controller; 147 gpio-controller;
90 #gpio-cells = <2>; 148 #gpio-cells = <2>;
91 interrupt-controller; 149 interrupt-controller;
92 #interrupts-cells = <2>; 150 #interrupt-cells = <2>;
93 interrupts = <87>, <88>, <89>, <90>; 151 interrupts = <87>, <88>, <89>, <90>;
94 }; 152 };
95 153
@@ -100,10 +158,15 @@
100 gpio-controller; 158 gpio-controller;
101 #gpio-cells = <2>; 159 #gpio-cells = <2>;
102 interrupt-controller; 160 interrupt-controller;
103 #interrupts-cells = <2>; 161 #interrupt-cells = <2>;
104 interrupts = <91>; 162 interrupts = <91>;
105 }; 163 };
106 164
165 timer@20300 {
166 compatible = "marvell,armada-370-timer";
167 clocks = <&coreclk 2>;
168 };
169
107 coreclk: mvebu-sar@18230 { 170 coreclk: mvebu-sar@18230 {
108 compatible = "marvell,armada-370-core-clock"; 171 compatible = "marvell,armada-370-core-clock";
109 reg = <0x18230 0x08>; 172 reg = <0x18230 0x08>;
@@ -169,54 +232,6 @@
169 0x18304 0x4>; 232 0x18304 0x4>;
170 status = "okay"; 233 status = "okay";
171 }; 234 };
172
173 pcie-controller {
174 compatible = "marvell,armada-370-pcie";
175 status = "disabled";
176 device_type = "pci";
177
178 #address-cells = <3>;
179 #size-cells = <2>;
180
181 bus-range = <0x00 0xff>;
182
183 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
184 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
185 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
186 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
187
188 pcie@1,0 {
189 device_type = "pci";
190 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
191 reg = <0x0800 0 0 0 0>;
192 #address-cells = <3>;
193 #size-cells = <2>;
194 #interrupt-cells = <1>;
195 ranges;
196 interrupt-map-mask = <0 0 0 0>;
197 interrupt-map = <0 0 0 0 &mpic 58>;
198 marvell,pcie-port = <0>;
199 marvell,pcie-lane = <0>;
200 clocks = <&gateclk 5>;
201 status = "disabled";
202 };
203
204 pcie@2,0 {
205 device_type = "pci";
206 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
207 reg = <0x1000 0 0 0 0>;
208 #address-cells = <3>;
209 #size-cells = <2>;
210 #interrupt-cells = <1>;
211 ranges;
212 interrupt-map-mask = <0 0 0 0>;
213 interrupt-map = <0 0 0 0 &mpic 62>;
214 marvell,pcie-port = <1>;
215 marvell,pcie-lane = <0>;
216 clocks = <&gateclk 9>;
217 status = "disabled";
218 };
219 };
220 }; 235 };
221 }; 236 };
222}; 237};
diff --git a/arch/arm/boot/dts/armada-xp-axpwifiap.dts b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
new file mode 100644
index 000000000000..c5fe57269f5a
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-axpwifiap.dts
@@ -0,0 +1,164 @@
1/*
2 * Device Tree file for Marvell RD-AXPWiFiAP.
3 *
4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6 * is used, the CONFIG_DEBUG_MVEBU_UART_ALTERNATE option should be
7 * used.
8 *
9 * Copyright (C) 2013 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18/dts-v1/;
19#include "armada-xp-mv78230.dtsi"
20
21/ {
22 model = "Marvell RD-AXPWiFiAP";
23 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
24
25 chosen {
26 bootargs = "console=ttyS0,115200 earlyprintk";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
32 };
33
34 soc {
35 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
36 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
37
38 pcie-controller {
39 status = "okay";
40
41 /* First mini-PCIe port */
42 pcie@1,0 {
43 /* Port 0, Lane 0 */
44 status = "okay";
45 };
46
47 /* Second mini-PCIe port */
48 pcie@2,0 {
49 /* Port 0, Lane 1 */
50 status = "okay";
51 };
52
53 /* Renesas uPD720202 USB 3.0 controller */
54 pcie@3,0 {
55 /* Port 0, Lane 3 */
56 status = "okay";
57 };
58 };
59
60 internal-regs {
61 pinctrl {
62 pinctrl-0 = <&pmx_phy_int>;
63 pinctrl-names = "default";
64
65 pmx_ge0: pmx-ge0 {
66 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
67 "mpp4", "mpp5", "mpp6", "mpp7",
68 "mpp8", "mpp9", "mpp10", "mpp11";
69 marvell,function = "ge0";
70 };
71
72 pmx_ge1: pmx-ge1 {
73 marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15",
74 "mpp16", "mpp17", "mpp18", "mpp19",
75 "mpp20", "mpp21", "mpp22", "mpp23";
76 marvell,function = "ge1";
77 };
78
79 pmx_keys: pmx-keys {
80 marvell,pins = "mpp33";
81 marvell,function = "gpio";
82 };
83
84 pmx_spi: pmx-spi {
85 marvell,pins = "mpp36", "mpp37", "mpp38", "mpp39";
86 marvell,function = "spi";
87 };
88
89 pmx_phy_int: pmx-phy-int {
90 marvell,pins = "mpp32";
91 marvell,function = "gpio";
92 };
93 };
94
95 serial@12000 {
96 clock-frequency = <250000000>;
97 status = "okay";
98 };
99
100 serial@12100 {
101 clock-frequency = <250000000>;
102 status = "okay";
103 };
104
105 sata@a0000 {
106 nr-ports = <1>;
107 status = "okay";
108 };
109
110 mdio {
111 phy0: ethernet-phy@0 {
112 reg = <0>;
113 };
114
115 phy1: ethernet-phy@1 {
116 reg = <1>;
117 };
118 };
119
120 ethernet@70000 {
121 pinctrl-0 = <&pmx_ge0>;
122 pinctrl-names = "default";
123 status = "okay";
124 phy = <&phy0>;
125 phy-mode = "rgmii-id";
126 };
127 ethernet@74000 {
128 pinctrl-0 = <&pmx_ge1>;
129 pinctrl-names = "default";
130 status = "okay";
131 phy = <&phy1>;
132 phy-mode = "rgmii-id";
133 };
134
135 spi0: spi@10600 {
136 status = "okay";
137 pinctrl-0 = <&pmx_spi>;
138 pinctrl-names = "default";
139
140 spi-flash@0 {
141 #address-cells = <1>;
142 #size-cells = <1>;
143 compatible = "n25q128a13";
144 reg = <0>; /* Chip select 0 */
145 spi-max-frequency = <108000000>;
146 };
147 };
148 };
149 };
150
151 gpio_keys {
152 compatible = "gpio-keys";
153 #address-cells = <1>;
154 #size-cells = <0>;
155 pinctrl-0 = <&pmx_keys>;
156 pinctrl-names = "default";
157
158 button@1 {
159 label = "Factory Reset Button";
160 linux,code = <141>; /* KEY_SETUP */
161 gpios = <&gpio1 1 1>;
162 };
163 };
164};
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index e28e68ff864d..bcf6d79a57ec 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-xp-mv78460.dtsi" 17#include "armada-xp-mv78460.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada XP Evaluation Board"; 20 model = "Marvell Armada XP Evaluation Board";
@@ -30,9 +30,70 @@
30 }; 30 };
31 31
32 soc { 32 soc {
33 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 33 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
34 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 34 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
35 0xf0000000 0 0xf0000000 0x1000000>; /* Device Bus, NOR 16MiB */ 35 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
36
37 devbus-bootcs {
38 status = "okay";
39
40 /* Device Bus parameters are required */
41
42 /* Read parameters */
43 devbus,bus-width = <8>;
44 devbus,turn-off-ps = <60000>;
45 devbus,badr-skew-ps = <0>;
46 devbus,acc-first-ps = <124000>;
47 devbus,acc-next-ps = <248000>;
48 devbus,rd-setup-ps = <0>;
49 devbus,rd-hold-ps = <0>;
50
51 /* Write parameters */
52 devbus,sync-enable = <0>;
53 devbus,wr-high-ps = <60000>;
54 devbus,wr-low-ps = <60000>;
55 devbus,ale-wr-ps = <60000>;
56
57 /* NOR 16 MiB */
58 nor@0 {
59 compatible = "cfi-flash";
60 reg = <0 0x1000000>;
61 bank-width = <2>;
62 };
63 };
64
65 pcie-controller {
66 status = "okay";
67
68 /*
69 * All 6 slots are physically present as
70 * standard PCIe slots on the board.
71 */
72 pcie@1,0 {
73 /* Port 0, Lane 0 */
74 status = "okay";
75 };
76 pcie@2,0 {
77 /* Port 0, Lane 1 */
78 status = "okay";
79 };
80 pcie@3,0 {
81 /* Port 0, Lane 2 */
82 status = "okay";
83 };
84 pcie@4,0 {
85 /* Port 0, Lane 3 */
86 status = "okay";
87 };
88 pcie@9,0 {
89 /* Port 2, Lane 0 */
90 status = "okay";
91 };
92 pcie@10,0 {
93 /* Port 3, Lane 0 */
94 status = "okay";
95 };
96 };
36 97
37 internal-regs { 98 internal-regs {
38 serial@12000 { 99 serial@12000 {
@@ -127,68 +188,6 @@
127 spi-max-frequency = <20000000>; 188 spi-max-frequency = <20000000>;
128 }; 189 };
129 }; 190 };
130
131 pcie-controller {
132 status = "okay";
133
134 /*
135 * All 6 slots are physically present as
136 * standard PCIe slots on the board.
137 */
138 pcie@1,0 {
139 /* Port 0, Lane 0 */
140 status = "okay";
141 };
142 pcie@2,0 {
143 /* Port 0, Lane 1 */
144 status = "okay";
145 };
146 pcie@3,0 {
147 /* Port 0, Lane 2 */
148 status = "okay";
149 };
150 pcie@4,0 {
151 /* Port 0, Lane 3 */
152 status = "okay";
153 };
154 pcie@9,0 {
155 /* Port 2, Lane 0 */
156 status = "okay";
157 };
158 pcie@10,0 {
159 /* Port 3, Lane 0 */
160 status = "okay";
161 };
162 };
163
164 devbus-bootcs@10400 {
165 status = "okay";
166 ranges = <0 0xf0000000 0x1000000>;
167
168 /* Device Bus parameters are required */
169
170 /* Read parameters */
171 devbus,bus-width = <8>;
172 devbus,turn-off-ps = <60000>;
173 devbus,badr-skew-ps = <0>;
174 devbus,acc-first-ps = <124000>;
175 devbus,acc-next-ps = <248000>;
176 devbus,rd-setup-ps = <0>;
177 devbus,rd-hold-ps = <0>;
178
179 /* Write parameters */
180 devbus,sync-enable = <0>;
181 devbus,wr-high-ps = <60000>;
182 devbus,wr-low-ps = <60000>;
183 devbus,ale-wr-ps = <60000>;
184
185 /* NOR 16 MiB */
186 nor@0 {
187 compatible = "cfi-flash";
188 reg = <0 0x1000000>;
189 bank-width = <2>;
190 };
191 };
192 }; 191 };
193 }; 192 };
194}; 193};
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts b/arch/arm/boot/dts/armada-xp-gp.dts
index c87b2de29c30..2298e4a910e2 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -14,7 +14,7 @@
14 */ 14 */
15 15
16/dts-v1/; 16/dts-v1/;
17/include/ "armada-xp-mv78460.dtsi" 17#include "armada-xp-mv78460.dtsi"
18 18
19/ { 19/ {
20 model = "Marvell Armada XP Development Board DB-MV784MP-GP"; 20 model = "Marvell Armada XP Development Board DB-MV784MP-GP";
@@ -39,9 +39,58 @@
39 }; 39 };
40 40
41 soc { 41 soc {
42 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 42 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
43 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 43 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
44 0xf0000000 0 0xf0000000 0x1000000 /* Device Bus, NOR 16MiB */>; 44 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
45
46 devbus-bootcs {
47 status = "okay";
48
49 /* Device Bus parameters are required */
50
51 /* Read parameters */
52 devbus,bus-width = <8>;
53 devbus,turn-off-ps = <60000>;
54 devbus,badr-skew-ps = <0>;
55 devbus,acc-first-ps = <124000>;
56 devbus,acc-next-ps = <248000>;
57 devbus,rd-setup-ps = <0>;
58 devbus,rd-hold-ps = <0>;
59
60 /* Write parameters */
61 devbus,sync-enable = <0>;
62 devbus,wr-high-ps = <60000>;
63 devbus,wr-low-ps = <60000>;
64 devbus,ale-wr-ps = <60000>;
65
66 /* NOR 16 MiB */
67 nor@0 {
68 compatible = "cfi-flash";
69 reg = <0 0x1000000>;
70 bank-width = <2>;
71 };
72 };
73
74 pcie-controller {
75 status = "okay";
76
77 /*
78 * The 3 slots are physically present as
79 * standard PCIe slots on the board.
80 */
81 pcie@1,0 {
82 /* Port 0, Lane 0 */
83 status = "okay";
84 };
85 pcie@9,0 {
86 /* Port 2, Lane 0 */
87 status = "okay";
88 };
89 pcie@10,0 {
90 /* Port 3, Lane 0 */
91 status = "okay";
92 };
93 };
45 94
46 internal-regs { 95 internal-regs {
47 serial@12000 { 96 serial@12000 {
@@ -126,56 +175,6 @@
126 spi-max-frequency = <108000000>; 175 spi-max-frequency = <108000000>;
127 }; 176 };
128 }; 177 };
129
130 devbus-bootcs@10400 {
131 status = "okay";
132 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf000000, size 0x1000000 */
133
134 /* Device Bus parameters are required */
135
136 /* Read parameters */
137 devbus,bus-width = <8>;
138 devbus,turn-off-ps = <60000>;
139 devbus,badr-skew-ps = <0>;
140 devbus,acc-first-ps = <124000>;
141 devbus,acc-next-ps = <248000>;
142 devbus,rd-setup-ps = <0>;
143 devbus,rd-hold-ps = <0>;
144
145 /* Write parameters */
146 devbus,sync-enable = <0>;
147 devbus,wr-high-ps = <60000>;
148 devbus,wr-low-ps = <60000>;
149 devbus,ale-wr-ps = <60000>;
150
151 /* NOR 16 MiB */
152 nor@0 {
153 compatible = "cfi-flash";
154 reg = <0 0x1000000>;
155 bank-width = <2>;
156 };
157 };
158
159 pcie-controller {
160 status = "okay";
161
162 /*
163 * The 3 slots are physically present as
164 * standard PCIe slots on the board.
165 */
166 pcie@1,0 {
167 /* Port 0, Lane 0 */
168 status = "okay";
169 };
170 pcie@9,0 {
171 /* Port 2, Lane 0 */
172 status = "okay";
173 };
174 pcie@10,0 {
175 /* Port 3, Lane 0 */
176 status = "okay";
177 };
178 };
179 }; 178 };
180 }; 179 };
181}; 180};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index f8eaa383e07f..0358a33cba48 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78230 SoC"; 19 model = "Marvell Armada XP MV78230 SoC";
@@ -44,6 +44,124 @@
44 }; 44 };
45 45
46 soc { 46 soc {
47 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
50 * x4/x1.
51 */
52 pcie-controller {
53 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
60 bus-range = <0x00 0xff>;
61
62 ranges =
63 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
64 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
65 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
68 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
69 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
70 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
71 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
72 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
73 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
74 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
75 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
76 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
77 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
78
79 pcie@1,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
82 reg = <0x0800 0 0 0 0>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85 #interrupt-cells = <1>;
86 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
87 0x81000000 0 0 0x81000000 0x1 0 1 0>;
88 interrupt-map-mask = <0 0 0 0>;
89 interrupt-map = <0 0 0 0 &mpic 58>;
90 marvell,pcie-port = <0>;
91 marvell,pcie-lane = <0>;
92 clocks = <&gateclk 5>;
93 status = "disabled";
94 };
95
96 pcie@2,0 {
97 device_type = "pci";
98 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
99 reg = <0x1000 0 0 0 0>;
100 #address-cells = <3>;
101 #size-cells = <2>;
102 #interrupt-cells = <1>;
103 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
104 0x81000000 0 0 0x81000000 0x2 0 1 0>;
105 interrupt-map-mask = <0 0 0 0>;
106 interrupt-map = <0 0 0 0 &mpic 59>;
107 marvell,pcie-port = <0>;
108 marvell,pcie-lane = <1>;
109 clocks = <&gateclk 6>;
110 status = "disabled";
111 };
112
113 pcie@3,0 {
114 device_type = "pci";
115 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
116 reg = <0x1800 0 0 0 0>;
117 #address-cells = <3>;
118 #size-cells = <2>;
119 #interrupt-cells = <1>;
120 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
121 0x81000000 0 0 0x81000000 0x3 0 1 0>;
122 interrupt-map-mask = <0 0 0 0>;
123 interrupt-map = <0 0 0 0 &mpic 60>;
124 marvell,pcie-port = <0>;
125 marvell,pcie-lane = <2>;
126 clocks = <&gateclk 7>;
127 status = "disabled";
128 };
129
130 pcie@4,0 {
131 device_type = "pci";
132 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
133 reg = <0x2000 0 0 0 0>;
134 #address-cells = <3>;
135 #size-cells = <2>;
136 #interrupt-cells = <1>;
137 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
138 0x81000000 0 0 0x81000000 0x4 0 1 0>;
139 interrupt-map-mask = <0 0 0 0>;
140 interrupt-map = <0 0 0 0 &mpic 61>;
141 marvell,pcie-port = <0>;
142 marvell,pcie-lane = <3>;
143 clocks = <&gateclk 8>;
144 status = "disabled";
145 };
146
147 pcie@9,0 {
148 device_type = "pci";
149 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
150 reg = <0x4800 0 0 0 0>;
151 #address-cells = <3>;
152 #size-cells = <2>;
153 #interrupt-cells = <1>;
154 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
155 0x81000000 0 0 0x81000000 0x9 0 1 0>;
156 interrupt-map-mask = <0 0 0 0>;
157 interrupt-map = <0 0 0 0 &mpic 99>;
158 marvell,pcie-port = <2>;
159 marvell,pcie-lane = <0>;
160 clocks = <&gateclk 26>;
161 status = "disabled";
162 };
163 };
164
47 internal-regs { 165 internal-regs {
48 pinctrl { 166 pinctrl {
49 compatible = "marvell,mv78230-pinctrl"; 167 compatible = "marvell,mv78230-pinctrl";
@@ -63,7 +181,7 @@
63 gpio-controller; 181 gpio-controller;
64 #gpio-cells = <2>; 182 #gpio-cells = <2>;
65 interrupt-controller; 183 interrupt-controller;
66 #interrupts-cells = <2>; 184 #interrupt-cells = <2>;
67 interrupts = <82>, <83>, <84>, <85>; 185 interrupts = <82>, <83>, <84>, <85>;
68 }; 186 };
69 187
@@ -74,113 +192,9 @@
74 gpio-controller; 192 gpio-controller;
75 #gpio-cells = <2>; 193 #gpio-cells = <2>;
76 interrupt-controller; 194 interrupt-controller;
77 #interrupts-cells = <2>; 195 #interrupt-cells = <2>;
78 interrupts = <87>, <88>, <89>; 196 interrupts = <87>, <88>, <89>;
79 }; 197 };
80
81 /*
82 * MV78230 has 2 PCIe units Gen2.0: One unit can be
83 * configured as x4 or quad x1 lanes. One unit is
84 * x4/x1.
85 */
86 pcie-controller {
87 compatible = "marvell,armada-xp-pcie";
88 status = "disabled";
89 device_type = "pci";
90
91#address-cells = <3>;
92#size-cells = <2>;
93
94 bus-range = <0x00 0xff>;
95
96 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
97 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
98 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
99 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
100 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
101 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
102 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
103
104 pcie@1,0 {
105 device_type = "pci";
106 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
107 reg = <0x0800 0 0 0 0>;
108 #address-cells = <3>;
109 #size-cells = <2>;
110 #interrupt-cells = <1>;
111 ranges;
112 interrupt-map-mask = <0 0 0 0>;
113 interrupt-map = <0 0 0 0 &mpic 58>;
114 marvell,pcie-port = <0>;
115 marvell,pcie-lane = <0>;
116 clocks = <&gateclk 5>;
117 status = "disabled";
118 };
119
120 pcie@2,0 {
121 device_type = "pci";
122 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
123 reg = <0x1000 0 0 0 0>;
124 #address-cells = <3>;
125 #size-cells = <2>;
126 #interrupt-cells = <1>;
127 ranges;
128 interrupt-map-mask = <0 0 0 0>;
129 interrupt-map = <0 0 0 0 &mpic 59>;
130 marvell,pcie-port = <0>;
131 marvell,pcie-lane = <1>;
132 clocks = <&gateclk 6>;
133 status = "disabled";
134 };
135
136 pcie@3,0 {
137 device_type = "pci";
138 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
139 reg = <0x1800 0 0 0 0>;
140 #address-cells = <3>;
141 #size-cells = <2>;
142 #interrupt-cells = <1>;
143 ranges;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 60>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <2>;
148 clocks = <&gateclk 7>;
149 status = "disabled";
150 };
151
152 pcie@4,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
155 reg = <0x2000 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges;
160 interrupt-map-mask = <0 0 0 0>;
161 interrupt-map = <0 0 0 0 &mpic 61>;
162 marvell,pcie-port = <0>;
163 marvell,pcie-lane = <3>;
164 clocks = <&gateclk 8>;
165 status = "disabled";
166 };
167
168 pcie@9,0 {
169 device_type = "pci";
170 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
171 reg = <0x4800 0 0 0 0>;
172 #address-cells = <3>;
173 #size-cells = <2>;
174 #interrupt-cells = <1>;
175 ranges;
176 interrupt-map-mask = <0 0 0 0>;
177 interrupt-map = <0 0 0 0 &mpic 99>;
178 marvell,pcie-port = <2>;
179 marvell,pcie-lane = <0>;
180 clocks = <&gateclk 26>;
181 status = "disabled";
182 };
183 };
184 }; 198 };
185 }; 199 };
186}; 200};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 2d9335da210c..0e82c5062243 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78260 SoC"; 19 model = "Marvell Armada XP MV78260 SoC";
@@ -45,6 +45,145 @@
45 }; 45 };
46 46
47 soc { 47 soc {
48 /*
49 * MV78260 has 3 PCIe units Gen2.0: Two units can be
50 * configured as x4 or quad x1 lanes. One unit is
51 * x4/x1.
52 */
53 pcie-controller {
54 compatible = "marvell,armada-xp-pcie";
55 status = "disabled";
56 device_type = "pci";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60
61 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
65 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
66 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
67 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
68 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
69 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
70 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
71 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
72 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
73 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
74 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
75 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
76 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
77 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
78 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
79 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
80 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
81 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
82 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
83
84 pcie@1,0 {
85 device_type = "pci";
86 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
87 reg = <0x0800 0 0 0 0>;
88 #address-cells = <3>;
89 #size-cells = <2>;
90 #interrupt-cells = <1>;
91 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
92 0x81000000 0 0 0x81000000 0x1 0 1 0>;
93 interrupt-map-mask = <0 0 0 0>;
94 interrupt-map = <0 0 0 0 &mpic 58>;
95 marvell,pcie-port = <0>;
96 marvell,pcie-lane = <0>;
97 clocks = <&gateclk 5>;
98 status = "disabled";
99 };
100
101 pcie@2,0 {
102 device_type = "pci";
103 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
104 reg = <0x1000 0 0 0 0>;
105 #address-cells = <3>;
106 #size-cells = <2>;
107 #interrupt-cells = <1>;
108 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
109 0x81000000 0 0 0x81000000 0x2 0 1 0>;
110 interrupt-map-mask = <0 0 0 0>;
111 interrupt-map = <0 0 0 0 &mpic 59>;
112 marvell,pcie-port = <0>;
113 marvell,pcie-lane = <1>;
114 clocks = <&gateclk 6>;
115 status = "disabled";
116 };
117
118 pcie@3,0 {
119 device_type = "pci";
120 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
121 reg = <0x1800 0 0 0 0>;
122 #address-cells = <3>;
123 #size-cells = <2>;
124 #interrupt-cells = <1>;
125 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
126 0x81000000 0 0 0x81000000 0x3 0 1 0>;
127 interrupt-map-mask = <0 0 0 0>;
128 interrupt-map = <0 0 0 0 &mpic 60>;
129 marvell,pcie-port = <0>;
130 marvell,pcie-lane = <2>;
131 clocks = <&gateclk 7>;
132 status = "disabled";
133 };
134
135 pcie@4,0 {
136 device_type = "pci";
137 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
138 reg = <0x2000 0 0 0 0>;
139 #address-cells = <3>;
140 #size-cells = <2>;
141 #interrupt-cells = <1>;
142 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
143 0x81000000 0 0 0x81000000 0x4 0 1 0>;
144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
149 status = "disabled";
150 };
151
152 pcie@9,0 {
153 device_type = "pci";
154 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
155 reg = <0x4800 0 0 0 0>;
156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
159 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
160 0x81000000 0 0 0x81000000 0x9 0 1 0>;
161 interrupt-map-mask = <0 0 0 0>;
162 interrupt-map = <0 0 0 0 &mpic 99>;
163 marvell,pcie-port = <2>;
164 marvell,pcie-lane = <0>;
165 clocks = <&gateclk 26>;
166 status = "disabled";
167 };
168
169 pcie@10,0 {
170 device_type = "pci";
171 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
172 reg = <0x5000 0 0 0 0>;
173 #address-cells = <3>;
174 #size-cells = <2>;
175 #interrupt-cells = <1>;
176 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
177 0x81000000 0 0 0x81000000 0xa 0 1 0>;
178 interrupt-map-mask = <0 0 0 0>;
179 interrupt-map = <0 0 0 0 &mpic 103>;
180 marvell,pcie-port = <3>;
181 marvell,pcie-lane = <0>;
182 clocks = <&gateclk 27>;
183 status = "disabled";
184 };
185 };
186
48 internal-regs { 187 internal-regs {
49 pinctrl { 188 pinctrl {
50 compatible = "marvell,mv78260-pinctrl"; 189 compatible = "marvell,mv78260-pinctrl";
@@ -64,7 +203,7 @@
64 gpio-controller; 203 gpio-controller;
65 #gpio-cells = <2>; 204 #gpio-cells = <2>;
66 interrupt-controller; 205 interrupt-controller;
67 #interrupts-cells = <2>; 206 #interrupt-cells = <2>;
68 interrupts = <82>, <83>, <84>, <85>; 207 interrupts = <82>, <83>, <84>, <85>;
69 }; 208 };
70 209
@@ -75,7 +214,7 @@
75 gpio-controller; 214 gpio-controller;
76 #gpio-cells = <2>; 215 #gpio-cells = <2>;
77 interrupt-controller; 216 interrupt-controller;
78 #interrupts-cells = <2>; 217 #interrupt-cells = <2>;
79 interrupts = <87>, <88>, <89>, <90>; 218 interrupts = <87>, <88>, <89>, <90>;
80 }; 219 };
81 220
@@ -86,7 +225,7 @@
86 gpio-controller; 225 gpio-controller;
87 #gpio-cells = <2>; 226 #gpio-cells = <2>;
88 interrupt-controller; 227 interrupt-controller;
89 #interrupts-cells = <2>; 228 #interrupt-cells = <2>;
90 interrupts = <91>; 229 interrupts = <91>;
91 }; 230 };
92 231
@@ -97,128 +236,6 @@
97 clocks = <&gateclk 1>; 236 clocks = <&gateclk 1>;
98 status = "disabled"; 237 status = "disabled";
99 }; 238 };
100
101 /*
102 * MV78260 has 3 PCIe units Gen2.0: Two units can be
103 * configured as x4 or quad x1 lanes. One unit is
104 * x4/x1.
105 */
106 pcie-controller {
107 compatible = "marvell,armada-xp-pcie";
108 status = "disabled";
109 device_type = "pci";
110
111 #address-cells = <3>;
112 #size-cells = <2>;
113
114 bus-range = <0x00 0xff>;
115
116 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
117 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
118 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
119 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
120 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
121 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
122 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
123 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
124 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
125
126 pcie@1,0 {
127 device_type = "pci";
128 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
129 reg = <0x0800 0 0 0 0>;
130 #address-cells = <3>;
131 #size-cells = <2>;
132 #interrupt-cells = <1>;
133 ranges;
134 interrupt-map-mask = <0 0 0 0>;
135 interrupt-map = <0 0 0 0 &mpic 58>;
136 marvell,pcie-port = <0>;
137 marvell,pcie-lane = <0>;
138 clocks = <&gateclk 5>;
139 status = "disabled";
140 };
141
142 pcie@2,0 {
143 device_type = "pci";
144 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
145 reg = <0x1000 0 0 0 0>;
146 #address-cells = <3>;
147 #size-cells = <2>;
148 #interrupt-cells = <1>;
149 ranges;
150 interrupt-map-mask = <0 0 0 0>;
151 interrupt-map = <0 0 0 0 &mpic 59>;
152 marvell,pcie-port = <0>;
153 marvell,pcie-lane = <1>;
154 clocks = <&gateclk 6>;
155 status = "disabled";
156 };
157
158 pcie@3,0 {
159 device_type = "pci";
160 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
161 reg = <0x1800 0 0 0 0>;
162 #address-cells = <3>;
163 #size-cells = <2>;
164 #interrupt-cells = <1>;
165 ranges;
166 interrupt-map-mask = <0 0 0 0>;
167 interrupt-map = <0 0 0 0 &mpic 60>;
168 marvell,pcie-port = <0>;
169 marvell,pcie-lane = <2>;
170 clocks = <&gateclk 7>;
171 status = "disabled";
172 };
173
174 pcie@4,0 {
175 device_type = "pci";
176 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
177 reg = <0x2000 0 0 0 0>;
178 #address-cells = <3>;
179 #size-cells = <2>;
180 #interrupt-cells = <1>;
181 ranges;
182 interrupt-map-mask = <0 0 0 0>;
183 interrupt-map = <0 0 0 0 &mpic 61>;
184 marvell,pcie-port = <0>;
185 marvell,pcie-lane = <3>;
186 clocks = <&gateclk 8>;
187 status = "disabled";
188 };
189
190 pcie@9,0 {
191 device_type = "pci";
192 assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
193 reg = <0x4800 0 0 0 0>;
194 #address-cells = <3>;
195 #size-cells = <2>;
196 #interrupt-cells = <1>;
197 ranges;
198 interrupt-map-mask = <0 0 0 0>;
199 interrupt-map = <0 0 0 0 &mpic 99>;
200 marvell,pcie-port = <2>;
201 marvell,pcie-lane = <0>;
202 clocks = <&gateclk 26>;
203 status = "disabled";
204 };
205
206 pcie@10,0 {
207 device_type = "pci";
208 assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
209 reg = <0x5000 0 0 0 0>;
210 #address-cells = <3>;
211 #size-cells = <2>;
212 #interrupt-cells = <1>;
213 ranges;
214 interrupt-map-mask = <0 0 0 0>;
215 interrupt-map = <0 0 0 0 &mpic 103>;
216 marvell,pcie-port = <3>;
217 marvell,pcie-lane = <0>;
218 clocks = <&gateclk 27>;
219 status = "disabled";
220 };
221 };
222 }; 239 };
223 }; 240 };
224}; 241};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index c7b1f4d5c1c7..e82c1b80af17 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -13,7 +13,7 @@
13 * common to all Armada XP SoCs. 13 * common to all Armada XP SoCs.
14 */ 14 */
15 15
16/include/ "armada-xp.dtsi" 16#include "armada-xp.dtsi"
17 17
18/ { 18/ {
19 model = "Marvell Armada XP MV78460 SoC"; 19 model = "Marvell Armada XP MV78460 SoC";
@@ -61,6 +61,227 @@
61 }; 61 };
62 62
63 soc { 63 soc {
64 /*
65 * MV78460 has 4 PCIe units Gen2.0: Two units can be
66 * configured as x4 or quad x1 lanes. Two units are
67 * x4/x1.
68 */
69 pcie-controller {
70 compatible = "marvell,armada-xp-pcie";
71 status = "disabled";
72 device_type = "pci";
73
74 #address-cells = <3>;
75 #size-cells = <2>;
76
77 bus-range = <0x00 0xff>;
78
79 ranges =
80 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
81 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
82 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
83 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
84 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
85 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
86 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
87 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
88 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
89 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
90 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
91 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
92 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
93 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
94 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
95 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
96 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
97 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
98
99 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
100 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
101 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
102 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
103 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
104 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
105 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
106 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
107
108 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
109 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
110
111 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
112 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
113
114 pcie@1,0 {
115 device_type = "pci";
116 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
117 reg = <0x0800 0 0 0 0>;
118 #address-cells = <3>;
119 #size-cells = <2>;
120 #interrupt-cells = <1>;
121 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
122 0x81000000 0 0 0x81000000 0x1 0 1 0>;
123 interrupt-map-mask = <0 0 0 0>;
124 interrupt-map = <0 0 0 0 &mpic 58>;
125 marvell,pcie-port = <0>;
126 marvell,pcie-lane = <0>;
127 clocks = <&gateclk 5>;
128 status = "disabled";
129 };
130
131 pcie@2,0 {
132 device_type = "pci";
133 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
134 reg = <0x1000 0 0 0 0>;
135 #address-cells = <3>;
136 #size-cells = <2>;
137 #interrupt-cells = <1>;
138 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
139 0x81000000 0 0 0x81000000 0x2 0 1 0>;
140 interrupt-map-mask = <0 0 0 0>;
141 interrupt-map = <0 0 0 0 &mpic 59>;
142 marvell,pcie-port = <0>;
143 marvell,pcie-lane = <1>;
144 clocks = <&gateclk 6>;
145 status = "disabled";
146 };
147
148 pcie@3,0 {
149 device_type = "pci";
150 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
151 reg = <0x1800 0 0 0 0>;
152 #address-cells = <3>;
153 #size-cells = <2>;
154 #interrupt-cells = <1>;
155 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
156 0x81000000 0 0 0x81000000 0x3 0 1 0>;
157 interrupt-map-mask = <0 0 0 0>;
158 interrupt-map = <0 0 0 0 &mpic 60>;
159 marvell,pcie-port = <0>;
160 marvell,pcie-lane = <2>;
161 clocks = <&gateclk 7>;
162 status = "disabled";
163 };
164
165 pcie@4,0 {
166 device_type = "pci";
167 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
168 reg = <0x2000 0 0 0 0>;
169 #address-cells = <3>;
170 #size-cells = <2>;
171 #interrupt-cells = <1>;
172 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
173 0x81000000 0 0 0x81000000 0x4 0 1 0>;
174 interrupt-map-mask = <0 0 0 0>;
175 interrupt-map = <0 0 0 0 &mpic 61>;
176 marvell,pcie-port = <0>;
177 marvell,pcie-lane = <3>;
178 clocks = <&gateclk 8>;
179 status = "disabled";
180 };
181
182 pcie@5,0 {
183 device_type = "pci";
184 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
185 reg = <0x2800 0 0 0 0>;
186 #address-cells = <3>;
187 #size-cells = <2>;
188 #interrupt-cells = <1>;
189 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
190 0x81000000 0 0 0x81000000 0x5 0 1 0>;
191 interrupt-map-mask = <0 0 0 0>;
192 interrupt-map = <0 0 0 0 &mpic 62>;
193 marvell,pcie-port = <1>;
194 marvell,pcie-lane = <0>;
195 clocks = <&gateclk 9>;
196 status = "disabled";
197 };
198
199 pcie@6,0 {
200 device_type = "pci";
201 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
202 reg = <0x3000 0 0 0 0>;
203 #address-cells = <3>;
204 #size-cells = <2>;
205 #interrupt-cells = <1>;
206 ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
207 0x81000000 0 0 0x81000000 0x6 0 1 0>;
208 interrupt-map-mask = <0 0 0 0>;
209 interrupt-map = <0 0 0 0 &mpic 63>;
210 marvell,pcie-port = <1>;
211 marvell,pcie-lane = <1>;
212 clocks = <&gateclk 10>;
213 status = "disabled";
214 };
215
216 pcie@7,0 {
217 device_type = "pci";
218 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
219 reg = <0x3800 0 0 0 0>;
220 #address-cells = <3>;
221 #size-cells = <2>;
222 #interrupt-cells = <1>;
223 ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
224 0x81000000 0 0 0x81000000 0x7 0 1 0>;
225 interrupt-map-mask = <0 0 0 0>;
226 interrupt-map = <0 0 0 0 &mpic 64>;
227 marvell,pcie-port = <1>;
228 marvell,pcie-lane = <2>;
229 clocks = <&gateclk 11>;
230 status = "disabled";
231 };
232
233 pcie@8,0 {
234 device_type = "pci";
235 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
236 reg = <0x4000 0 0 0 0>;
237 #address-cells = <3>;
238 #size-cells = <2>;
239 #interrupt-cells = <1>;
240 ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
241 0x81000000 0 0 0x81000000 0x8 0 1 0>;
242 interrupt-map-mask = <0 0 0 0>;
243 interrupt-map = <0 0 0 0 &mpic 65>;
244 marvell,pcie-port = <1>;
245 marvell,pcie-lane = <3>;
246 clocks = <&gateclk 12>;
247 status = "disabled";
248 };
249
250 pcie@9,0 {
251 device_type = "pci";
252 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
253 reg = <0x4800 0 0 0 0>;
254 #address-cells = <3>;
255 #size-cells = <2>;
256 #interrupt-cells = <1>;
257 ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
258 0x81000000 0 0 0x81000000 0x9 0 1 0>;
259 interrupt-map-mask = <0 0 0 0>;
260 interrupt-map = <0 0 0 0 &mpic 99>;
261 marvell,pcie-port = <2>;
262 marvell,pcie-lane = <0>;
263 clocks = <&gateclk 26>;
264 status = "disabled";
265 };
266
267 pcie@10,0 {
268 device_type = "pci";
269 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
270 reg = <0x5000 0 0 0 0>;
271 #address-cells = <3>;
272 #size-cells = <2>;
273 #interrupt-cells = <1>;
274 ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
275 0x81000000 0 0 0x81000000 0xa 0 1 0>;
276 interrupt-map-mask = <0 0 0 0>;
277 interrupt-map = <0 0 0 0 &mpic 103>;
278 marvell,pcie-port = <3>;
279 marvell,pcie-lane = <0>;
280 clocks = <&gateclk 27>;
281 status = "disabled";
282 };
283 };
284
64 internal-regs { 285 internal-regs {
65 pinctrl { 286 pinctrl {
66 compatible = "marvell,mv78460-pinctrl"; 287 compatible = "marvell,mv78460-pinctrl";
@@ -80,7 +301,7 @@
80 gpio-controller; 301 gpio-controller;
81 #gpio-cells = <2>; 302 #gpio-cells = <2>;
82 interrupt-controller; 303 interrupt-controller;
83 #interrupts-cells = <2>; 304 #interrupt-cells = <2>;
84 interrupts = <82>, <83>, <84>, <85>; 305 interrupts = <82>, <83>, <84>, <85>;
85 }; 306 };
86 307
@@ -91,7 +312,7 @@
91 gpio-controller; 312 gpio-controller;
92 #gpio-cells = <2>; 313 #gpio-cells = <2>;
93 interrupt-controller; 314 interrupt-controller;
94 #interrupts-cells = <2>; 315 #interrupt-cells = <2>;
95 interrupts = <87>, <88>, <89>, <90>; 316 interrupts = <87>, <88>, <89>, <90>;
96 }; 317 };
97 318
@@ -102,7 +323,7 @@
102 gpio-controller; 323 gpio-controller;
103 #gpio-cells = <2>; 324 #gpio-cells = <2>;
104 interrupt-controller; 325 interrupt-controller;
105 #interrupts-cells = <2>; 326 #interrupt-cells = <2>;
106 interrupts = <91>; 327 interrupts = <91>;
107 }; 328 };
108 329
@@ -113,194 +334,6 @@
113 clocks = <&gateclk 1>; 334 clocks = <&gateclk 1>;
114 status = "disabled"; 335 status = "disabled";
115 }; 336 };
116
117 /*
118 * MV78460 has 4 PCIe units Gen2.0: Two units can be
119 * configured as x4 or quad x1 lanes. Two units are
120 * x4/x1.
121 */
122 pcie-controller {
123 compatible = "marvell,armada-xp-pcie";
124 status = "disabled";
125 device_type = "pci";
126
127 #address-cells = <3>;
128 #size-cells = <2>;
129
130 bus-range = <0x00 0xff>;
131
132 ranges = <0x82000000 0 0x40000 0x40000 0 0x00002000 /* Port 0.0 registers */
133 0x82000000 0 0x42000 0x42000 0 0x00002000 /* Port 2.0 registers */
134 0x82000000 0 0x44000 0x44000 0 0x00002000 /* Port 0.1 registers */
135 0x82000000 0 0x48000 0x48000 0 0x00002000 /* Port 0.2 registers */
136 0x82000000 0 0x4c000 0x4c000 0 0x00002000 /* Port 0.3 registers */
137 0x82000000 0 0x80000 0x80000 0 0x00002000 /* Port 1.0 registers */
138 0x82000000 0 0x82000 0x82000 0 0x00002000 /* Port 3.0 registers */
139 0x82000000 0 0x84000 0x84000 0 0x00002000 /* Port 1.1 registers */
140 0x82000000 0 0x88000 0x88000 0 0x00002000 /* Port 1.2 registers */
141 0x82000000 0 0x8c000 0x8c000 0 0x00002000 /* Port 1.3 registers */
142 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
143 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
144
145 pcie@1,0 {
146 device_type = "pci";
147 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
148 reg = <0x0800 0 0 0 0>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 #interrupt-cells = <1>;
152 ranges;
153 interrupt-map-mask = <0 0 0 0>;
154 interrupt-map = <0 0 0 0 &mpic 58>;
155 marvell,pcie-port = <0>;
156 marvell,pcie-lane = <0>;
157 clocks = <&gateclk 5>;
158 status = "disabled";
159 };
160
161 pcie@2,0 {
162 device_type = "pci";
163 assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
164 reg = <0x1000 0 0 0 0>;
165 #address-cells = <3>;
166 #size-cells = <2>;
167 #interrupt-cells = <1>;
168 ranges;
169 interrupt-map-mask = <0 0 0 0>;
170 interrupt-map = <0 0 0 0 &mpic 59>;
171 marvell,pcie-port = <0>;
172 marvell,pcie-lane = <1>;
173 clocks = <&gateclk 6>;
174 status = "disabled";
175 };
176
177 pcie@3,0 {
178 device_type = "pci";
179 assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
180 reg = <0x1800 0 0 0 0>;
181 #address-cells = <3>;
182 #size-cells = <2>;
183 #interrupt-cells = <1>;
184 ranges;
185 interrupt-map-mask = <0 0 0 0>;
186 interrupt-map = <0 0 0 0 &mpic 60>;
187 marvell,pcie-port = <0>;
188 marvell,pcie-lane = <2>;
189 clocks = <&gateclk 7>;
190 status = "disabled";
191 };
192
193 pcie@4,0 {
194 device_type = "pci";
195 assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
196 reg = <0x2000 0 0 0 0>;
197 #address-cells = <3>;
198 #size-cells = <2>;
199 #interrupt-cells = <1>;
200 ranges;
201 interrupt-map-mask = <0 0 0 0>;
202 interrupt-map = <0 0 0 0 &mpic 61>;
203 marvell,pcie-port = <0>;
204 marvell,pcie-lane = <3>;
205 clocks = <&gateclk 8>;
206 status = "disabled";
207 };
208
209 pcie@5,0 {
210 device_type = "pci";
211 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
212 reg = <0x2800 0 0 0 0>;
213 #address-cells = <3>;
214 #size-cells = <2>;
215 #interrupt-cells = <1>;
216 ranges;
217 interrupt-map-mask = <0 0 0 0>;
218 interrupt-map = <0 0 0 0 &mpic 62>;
219 marvell,pcie-port = <1>;
220 marvell,pcie-lane = <0>;
221 clocks = <&gateclk 9>;
222 status = "disabled";
223 };
224
225 pcie@6,0 {
226 device_type = "pci";
227 assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
228 reg = <0x3000 0 0 0 0>;
229 #address-cells = <3>;
230 #size-cells = <2>;
231 #interrupt-cells = <1>;
232 ranges;
233 interrupt-map-mask = <0 0 0 0>;
234 interrupt-map = <0 0 0 0 &mpic 63>;
235 marvell,pcie-port = <1>;
236 marvell,pcie-lane = <1>;
237 clocks = <&gateclk 10>;
238 status = "disabled";
239 };
240
241 pcie@7,0 {
242 device_type = "pci";
243 assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
244 reg = <0x3800 0 0 0 0>;
245 #address-cells = <3>;
246 #size-cells = <2>;
247 #interrupt-cells = <1>;
248 ranges;
249 interrupt-map-mask = <0 0 0 0>;
250 interrupt-map = <0 0 0 0 &mpic 64>;
251 marvell,pcie-port = <1>;
252 marvell,pcie-lane = <2>;
253 clocks = <&gateclk 11>;
254 status = "disabled";
255 };
256
257 pcie@8,0 {
258 device_type = "pci";
259 assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
260 reg = <0x4000 0 0 0 0>;
261 #address-cells = <3>;
262 #size-cells = <2>;
263 #interrupt-cells = <1>;
264 ranges;
265 interrupt-map-mask = <0 0 0 0>;
266 interrupt-map = <0 0 0 0 &mpic 65>;
267 marvell,pcie-port = <1>;
268 marvell,pcie-lane = <3>;
269 clocks = <&gateclk 12>;
270 status = "disabled";
271 };
272 pcie@9,0 {
273 device_type = "pci";
274 assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
275 reg = <0x4800 0 0 0 0>;
276 #address-cells = <3>;
277 #size-cells = <2>;
278 #interrupt-cells = <1>;
279 ranges;
280 interrupt-map-mask = <0 0 0 0>;
281 interrupt-map = <0 0 0 0 &mpic 99>;
282 marvell,pcie-port = <2>;
283 marvell,pcie-lane = <0>;
284 clocks = <&gateclk 26>;
285 status = "disabled";
286 };
287
288 pcie@10,0 {
289 device_type = "pci";
290 assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
291 reg = <0x5000 0 0 0 0>;
292 #address-cells = <3>;
293 #size-cells = <2>;
294 #interrupt-cells = <1>;
295 ranges;
296 interrupt-map-mask = <0 0 0 0>;
297 interrupt-map = <0 0 0 0 &mpic 103>;
298 marvell,pcie-port = <3>;
299 marvell,pcie-lane = <0>;
300 clocks = <&gateclk 27>;
301 status = "disabled";
302 };
303 };
304 }; 337 };
305 }; 338 };
306}; 339};
diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index 8f510458ea86..5695afcc04bf 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -11,7 +11,7 @@
11 */ 11 */
12 12
13/dts-v1/; 13/dts-v1/;
14/include/ "armada-xp-mv78260.dtsi" 14#include "armada-xp-mv78260.dtsi"
15 15
16/ { 16/ {
17 model = "PlatHome OpenBlocks AX3-4 board"; 17 model = "PlatHome OpenBlocks AX3-4 board";
@@ -27,9 +27,46 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 ranges = <0 0 0xd0000000 0x100000 /* Internal registers 1MiB */ 30 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
31 0xe0000000 0 0xe0000000 0x8100000 /* PCIe */ 31 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
32 0xf0000000 0 0xf0000000 0x8000000 /* Device Bus, NOR 128MiB */>; 32 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
33
34 devbus-bootcs {
35 status = "okay";
36
37 /* Device Bus parameters are required */
38
39 /* Read parameters */
40 devbus,bus-width = <8>;
41 devbus,turn-off-ps = <60000>;
42 devbus,badr-skew-ps = <0>;
43 devbus,acc-first-ps = <124000>;
44 devbus,acc-next-ps = <248000>;
45 devbus,rd-setup-ps = <0>;
46 devbus,rd-hold-ps = <0>;
47
48 /* Write parameters */
49 devbus,sync-enable = <0>;
50 devbus,wr-high-ps = <60000>;
51 devbus,wr-low-ps = <60000>;
52 devbus,ale-wr-ps = <60000>;
53
54 /* NOR 128 MiB */
55 nor@0 {
56 compatible = "cfi-flash";
57 reg = <0 0x8000000>;
58 bank-width = <2>;
59 };
60 };
61
62 pcie-controller {
63 status = "okay";
64 /* Internal mini-PCIe connector */
65 pcie@1,0 {
66 /* Port 0, Lane 0 */
67 status = "okay";
68 };
69 };
33 70
34 internal-regs { 71 internal-regs {
35 serial@12000 { 72 serial@12000 {
@@ -148,49 +185,6 @@
148 usb@51000 { 185 usb@51000 {
149 status = "okay"; 186 status = "okay";
150 }; 187 };
151
152 /* USB interface in the mini-PCIe connector */
153 usb@52000 {
154 status = "okay";
155 };
156
157 devbus-bootcs@10400 {
158 status = "okay";
159 ranges = <0 0xf0000000 0x8000000>; /* @addr 0xf000000, size 0x8000000 */
160
161 /* Device Bus parameters are required */
162
163 /* Read parameters */
164 devbus,bus-width = <8>;
165 devbus,turn-off-ps = <60000>;
166 devbus,badr-skew-ps = <0>;
167 devbus,acc-first-ps = <124000>;
168 devbus,acc-next-ps = <248000>;
169 devbus,rd-setup-ps = <0>;
170 devbus,rd-hold-ps = <0>;
171
172 /* Write parameters */
173 devbus,sync-enable = <0>;
174 devbus,wr-high-ps = <60000>;
175 devbus,wr-low-ps = <60000>;
176 devbus,ale-wr-ps = <60000>;
177
178 /* NOR 128 MiB */
179 nor@0 {
180 compatible = "cfi-flash";
181 reg = <0 0x8000000>;
182 bank-width = <2>;
183 };
184 };
185
186 pcie-controller {
187 status = "okay";
188 /* Internal mini-PCIe connector */
189 pcie@1,0 {
190 /* Port 0, Lane 0 */
191 status = "okay";
192 };
193 };
194 }; 188 };
195 }; 189 };
196}; 190};
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 416eb9481844..def125c0eeaa 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -16,7 +16,7 @@
16 * common to all Armada SoCs. 16 * common to all Armada SoCs.
17 */ 17 */
18 18
19/include/ "armada-370-xp.dtsi" 19#include "armada-370-xp.dtsi"
20 20
21/ { 21/ {
22 model = "Marvell Armada XP family SoC"; 22 model = "Marvell Armada XP family SoC";
@@ -27,6 +27,13 @@
27 }; 27 };
28 28
29 soc { 29 soc {
30 compatible = "marvell,armadaxp-mbus", "simple-bus";
31
32 bootrom {
33 compatible = "marvell,bootrom";
34 reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
35 };
36
30 internal-regs { 37 internal-regs {
31 L2: l2-cache { 38 L2: l2-cache {
32 compatible = "marvell,aurora-system-cache"; 39 compatible = "marvell,aurora-system-cache";
@@ -62,7 +69,7 @@
62 }; 69 };
63 70
64 timer@20300 { 71 timer@20300 {
65 marvell,timer-25Mhz; 72 compatible = "marvell,armada-xp-timer";
66 }; 73 };
67 74
68 coreclk: mvebu-sar@18230 { 75 coreclk: mvebu-sar@18230 {
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index 92b9e21389db..f77065506f1e 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -120,6 +120,7 @@
120 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 120 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
121 #address-cells = <1>; 121 #address-cells = <1>;
122 #size-cells = <0>; 122 #size-cells = <0>;
123 pinctrl-names = "default";
123 status = "disabled"; 124 status = "disabled";
124 }; 125 };
125 126
diff --git a/arch/arm/boot/dts/at91rm9200_pqfp.dtsi b/arch/arm/boot/dts/at91rm9200_pqfp.dtsi
new file mode 100644
index 000000000000..93ca66f80360
--- /dev/null
+++ b/arch/arm/boot/dts/at91rm9200_pqfp.dtsi
@@ -0,0 +1,17 @@
1/*
2 * at91rm9200_pqfp.dtsi - Device Tree Include file for AT91RM9200 PQFP family SoC
3 *
4 * Copyright (C) 2013 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#include "at91rm9200.dtsi"
10
11/ {
12 compatible = "atmel,at91rm9200-pqfp", "atmel,at91rm9200";
13};
14
15&pioD {
16 status = "disabled";
17};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index c7ccbcbffb3e..56ee8282a7a8 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -572,6 +572,7 @@
572 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>; 572 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
573 #address-cells = <1>; 573 #address-cells = <1>;
574 #size-cells = <0>; 574 #size-cells = <0>;
575 pinctrl-names = "default";
575 status = "disabled"; 576 status = "disabled";
576 }; 577 };
577 578
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index bb7f564b3a55..9fb7ffd32af2 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -291,6 +291,22 @@
291 }; 291 };
292 }; 292 };
293 293
294 i2c0 {
295 pinctrl_i2c0: i2c0-0 {
296 atmel,pins =
297 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
298 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
299 };
300 };
301
302 i2c1 {
303 pinctrl_i2c1: i2c1-0 {
304 atmel,pins =
305 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE
306 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;
307 };
308 };
309
294 tcb0 { 310 tcb0 {
295 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 311 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
296 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; 312 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;
@@ -471,6 +487,8 @@
471 dma-names = "tx", "rx"; 487 dma-names = "tx", "rx";
472 #address-cells = <1>; 488 #address-cells = <1>;
473 #size-cells = <0>; 489 #size-cells = <0>;
490 pinctrl-names = "default";
491 pinctrl-0 = <&pinctrl_i2c0>;
474 status = "disabled"; 492 status = "disabled";
475 }; 493 };
476 494
@@ -483,6 +501,8 @@
483 dma-names = "tx", "rx"; 501 dma-names = "tx", "rx";
484 #address-cells = <1>; 502 #address-cells = <1>;
485 #size-cells = <0>; 503 #size-cells = <0>;
504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_i2c1>;
486 status = "disabled"; 506 status = "disabled";
487 }; 507 };
488 508
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 3d77dbe406f4..27a9352b9d7a 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -40,6 +40,15 @@
40 40
41 i2c0: i2c@f8010000 { 41 i2c0: i2c@f8010000 {
42 status = "okay"; 42 status = "okay";
43
44 qt1070: keyboard@1b {
45 compatible = "qt1070";
46 reg = <0x1b>;
47 interrupt-parent = <&pioA>;
48 interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_qt1070_irq>;
51 };
43 }; 52 };
44 53
45 i2c1: i2c@f8014000 { 54 i2c1: i2c@f8014000 {
@@ -66,6 +75,13 @@
66 <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */ 75 <AT91_PIOA 7 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PA7 gpio CD pin pull up and deglitch */
67 }; 76 };
68 }; 77 };
78
79 qt1070 {
80 pinctrl_qt1070_irq: qt1070_irq {
81 atmel,pins =
82 <AT91_PIOA 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
83 };
84 };
69 }; 85 };
70 86
71 spi0: spi@f0000000 { 87 spi0: spi@f0000000 {
@@ -121,7 +137,7 @@
121 137
122 enter { 138 enter {
123 label = "Enter"; 139 label = "Enter";
124 gpios = <&pioB 4 GPIO_ACTIVE_LOW>; 140 gpios = <&pioB 3 GPIO_ACTIVE_LOW>;
125 linux,code = <28>; 141 linux,code = <28>;
126 gpio-key,wakeup; 142 gpio-key,wakeup;
127 }; 143 };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 57d45f5bea09..cf78ac0b04b1 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -542,6 +542,9 @@
542 compatible = "atmel,at91sam9g45-ssc"; 542 compatible = "atmel,at91sam9g45-ssc";
543 reg = <0xf0010000 0x4000>; 543 reg = <0xf0010000 0x4000>;
544 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 544 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
545 dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(13)>,
546 <&dma0 1 AT91_DMA_CFG_PER_ID(14)>;
547 dma-names = "tx", "rx";
545 pinctrl-names = "default"; 548 pinctrl-names = "default";
546 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 549 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
547 status = "disabled"; 550 status = "disabled";
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 49e3c45818c2..3a9f6fa4a36a 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -59,6 +59,11 @@
59 59
60 i2c0: i2c@f8010000 { 60 i2c0: i2c@f8010000 {
61 status = "okay"; 61 status = "okay";
62
63 wm8731: wm8731@1a {
64 compatible = "wm8731";
65 reg = <0x1a>;
66 };
62 }; 67 };
63 68
64 pinctrl@fffff400 { 69 pinctrl@fffff400 {
@@ -90,6 +95,10 @@
90 watchdog@fffffe40 { 95 watchdog@fffffe40 {
91 status = "okay"; 96 status = "okay";
92 }; 97 };
98
99 ssc0: ssc@f0010000 {
100 status = "okay";
101 };
93 }; 102 };
94 103
95 usb0: ohci@00600000 { 104 usb0: ohci@00600000 {
@@ -105,4 +114,19 @@
105 status = "okay"; 114 status = "okay";
106 }; 115 };
107 }; 116 };
117
118 sound {
119 compatible = "atmel,sam9x5-wm8731-audio";
120
121 atmel,model = "wm8731 @ AT91SAM9X5EK";
122
123 atmel,audio-routing =
124 "Headphone Jack", "RHPOUT",
125 "Headphone Jack", "LHPOUT",
126 "LLINEIN", "Line In Jack",
127 "RLINEIN", "Line In Jack";
128
129 atmel,ssc-controller = <&ssc0>;
130 atmel,audio-codec = <&wm8731>;
131 };
108}; 132};
diff --git a/arch/arm/boot/dts/bcm11351-brt.dts b/arch/arm/boot/dts/bcm11351-brt.dts
index 67ec524098b5..9d36eb4e3c41 100644
--- a/arch/arm/boot/dts/bcm11351-brt.dts
+++ b/arch/arm/boot/dts/bcm11351-brt.dts
@@ -17,7 +17,7 @@
17 17
18/ { 18/ {
19 model = "BCM11351 BRT board"; 19 model = "BCM11351 BRT board";
20 compatible = "bcm,bcm11351-brt", "bcm,bcm11351"; 20 compatible = "brcm,bcm11351-brt", "brcm,bcm11351";
21 21
22 memory { 22 memory {
23 reg = <0x80000000 0x40000000>; /* 1 GB */ 23 reg = <0x80000000 0x40000000>; /* 1 GB */
@@ -27,18 +27,18 @@
27 status = "okay"; 27 status = "okay";
28 }; 28 };
29 29
30 sdio0: sdio@0x3f180000 { 30 sdio1: sdio@3f180000 {
31 max-frequency = <48000000>; 31 max-frequency = <48000000>;
32 status = "okay"; 32 status = "okay";
33 }; 33 };
34 34
35 sdio1: sdio@0x3f190000 { 35 sdio2: sdio@3f190000 {
36 non-removable; 36 non-removable;
37 max-frequency = <48000000>; 37 max-frequency = <48000000>;
38 status = "okay"; 38 status = "okay";
39 }; 39 };
40 40
41 sdio3: sdio@0x3f1b0000 { 41 sdio4: sdio@3f1b0000 {
42 max-frequency = <48000000>; 42 max-frequency = <48000000>;
43 status = "okay"; 43 status = "okay";
44 }; 44 };
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index c0cdf66f8964..05a5aabe3b2c 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2012 Broadcom Corporation 2 * Copyright (C) 2012-2013 Broadcom Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as 5 * modify it under the terms of the GNU General Public License as
@@ -18,7 +18,7 @@
18 18
19/ { 19/ {
20 model = "BCM11351 SoC"; 20 model = "BCM11351 SoC";
21 compatible = "bcm,bcm11351"; 21 compatible = "brcm,bcm11351";
22 interrupt-parent = <&gic>; 22 interrupt-parent = <&gic>;
23 23
24 chosen { 24 chosen {
@@ -35,12 +35,12 @@
35 }; 35 };
36 36
37 smc@0x3404c000 { 37 smc@0x3404c000 {
38 compatible = "bcm,bcm11351-smc", "bcm,kona-smc"; 38 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
39 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ 39 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
40 }; 40 };
41 41
42 uart@3e000000 { 42 uart@3e000000 {
43 compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; 43 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
44 status = "disabled"; 44 status = "disabled";
45 reg = <0x3e000000 0x1000>; 45 reg = <0x3e000000 0x1000>;
46 clock-frequency = <13000000>; 46 clock-frequency = <13000000>;
@@ -50,42 +50,47 @@
50 }; 50 };
51 51
52 L2: l2-cache { 52 L2: l2-cache {
53 compatible = "bcm,bcm11351-a2-pl310-cache"; 53 compatible = "brcm,bcm11351-a2-pl310-cache";
54 reg = <0x3ff20000 0x1000>; 54 reg = <0x3ff20000 0x1000>;
55 cache-unified; 55 cache-unified;
56 cache-level = <2>; 56 cache-level = <2>;
57 }; 57 };
58 58
59 watchdog@35002f40 {
60 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
61 reg = <0x35002f40 0x6c>;
62 };
63
59 timer@35006000 { 64 timer@35006000 {
60 compatible = "bcm,kona-timer"; 65 compatible = "brcm,kona-timer";
61 reg = <0x35006000 0x1000>; 66 reg = <0x35006000 0x1000>;
62 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 67 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
63 clock-frequency = <32768>; 68 clock-frequency = <32768>;
64 }; 69 };
65 70
66 sdio0: sdio@0x3f180000 { 71 sdio1: sdio@3f180000 {
67 compatible = "bcm,kona-sdhci"; 72 compatible = "brcm,kona-sdhci";
68 reg = <0x3f180000 0x10000>; 73 reg = <0x3f180000 0x10000>;
69 interrupts = <0x0 77 0x4>; 74 interrupts = <0x0 77 0x4>;
70 status = "disabled"; 75 status = "disabled";
71 }; 76 };
72 77
73 sdio1: sdio@0x3f190000 { 78 sdio2: sdio@3f190000 {
74 compatible = "bcm,kona-sdhci"; 79 compatible = "brcm,kona-sdhci";
75 reg = <0x3f190000 0x10000>; 80 reg = <0x3f190000 0x10000>;
76 interrupts = <0x0 76 0x4>; 81 interrupts = <0x0 76 0x4>;
77 status = "disabled"; 82 status = "disabled";
78 }; 83 };
79 84
80 sdio2: sdio@0x3f1a0000 { 85 sdio3: sdio@3f1a0000 {
81 compatible = "bcm,kona-sdhci"; 86 compatible = "brcm,kona-sdhci";
82 reg = <0x3f1a0000 0x10000>; 87 reg = <0x3f1a0000 0x10000>;
83 interrupts = <0x0 74 0x4>; 88 interrupts = <0x0 74 0x4>;
84 status = "disabled"; 89 status = "disabled";
85 }; 90 };
86 91
87 sdio3: sdio@0x3f1b0000 { 92 sdio4: sdio@3f1b0000 {
88 compatible = "bcm,kona-sdhci"; 93 compatible = "brcm,kona-sdhci";
89 reg = <0x3f1b0000 0x10000>; 94 reg = <0x3f1b0000 0x10000>;
90 interrupts = <0x0 73 0x4>; 95 interrupts = <0x0 73 0x4>;
91 status = "disabled"; 96 status = "disabled";
diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts
new file mode 100644
index 000000000000..96ae67a2f0d3
--- /dev/null
+++ b/arch/arm/boot/dts/bcm28155-ap.dts
@@ -0,0 +1,45 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14/dts-v1/;
15
16#include "bcm11351.dtsi"
17
18/ {
19 model = "BCM28155 AP board";
20 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
21
22 memory {
23 reg = <0x80000000 0x40000000>; /* 1 GB */
24 };
25
26 uart@3e000000 {
27 status = "okay";
28 };
29
30 sdio1: sdio@3f180000 {
31 max-frequency = <48000000>;
32 status = "okay";
33 };
34
35 sdio2: sdio@3f190000 {
36 non-removable;
37 max-frequency = <48000000>;
38 status = "okay";
39 };
40
41 sdio4: sdio@3f1b0000 {
42 max-frequency = <48000000>;
43 status = "okay";
44 };
45};
diff --git a/arch/arm/boot/dts/ccu8540.dts b/arch/arm/boot/dts/ccu8540.dts
deleted file mode 100644
index 48ff03441f5a..000000000000
--- a/arch/arm/boot/dts/ccu8540.dts
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * Copyright 2013 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson U8540 platform with Device Tree";
17 compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
18
19 memory@0 {
20 reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
21 };
22
23 soc {
24 prcmu@80157000 {
25 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
26 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
27 };
28
29 uart@80120000 {
30 status = "okay";
31 };
32
33 uart@80121000 {
34 status = "okay";
35 };
36
37 uart@80007000 {
38 status = "okay";
39 };
40 };
41};
diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts
index 5bce7cc55cf3..588ce58a2959 100644
--- a/arch/arm/boot/dts/da850-evm.dts
+++ b/arch/arm/boot/dts/da850-evm.dts
@@ -90,6 +90,17 @@
90 }; 90 };
91 }; 91 };
92 }; 92 };
93 mdio: mdio@1e24000 {
94 status = "okay";
95 pinctrl-names = "default";
96 pinctrl-0 = <&mdio_pins>;
97 bus_freq = <2200000>;
98 };
99 eth0: ethernet@1e20000 {
100 status = "okay";
101 pinctrl-names = "default";
102 pinctrl-0 = <&mii_pins>;
103 };
93 }; 104 };
94 nand_cs3@62000000 { 105 nand_cs3@62000000 {
95 status = "okay"; 106 status = "okay";
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index d70ba5504481..8d17346f9702 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -125,11 +125,33 @@
125 0x14 0x00000010 0x000000f0 125 0x14 0x00000010 0x000000f0
126 >; 126 >;
127 }; 127 };
128 mdio_pins: pinmux_mdio_pins {
129 pinctrl-single,bits = <
130 /* MDIO_CLK, MDIO_D */
131 0x10 0x00000088 0x000000ff
132 >;
133 };
134 mii_pins: pinmux_mii_pins {
135 pinctrl-single,bits = <
136 /*
137 * MII_TXEN, MII_TXCLK, MII_COL
138 * MII_TXD_3, MII_TXD_2, MII_TXD_1
139 * MII_TXD_0
140 */
141 0x8 0x88888880 0xfffffff0
142 /*
143 * MII_RXER, MII_CRS, MII_RXCLK
144 * MII_RXDV, MII_RXD_3, MII_RXD_2
145 * MII_RXD_1, MII_RXD_0
146 */
147 0xc 0x88888888 0xffffffff
148 >;
149 };
150
128 }; 151 };
129 serial0: serial@1c42000 { 152 serial0: serial@1c42000 {
130 compatible = "ns16550a"; 153 compatible = "ns16550a";
131 reg = <0x42000 0x100>; 154 reg = <0x42000 0x100>;
132 clock-frequency = <150000000>;
133 reg-shift = <2>; 155 reg-shift = <2>;
134 interrupts = <25>; 156 interrupts = <25>;
135 status = "disabled"; 157 status = "disabled";
@@ -137,7 +159,6 @@
137 serial1: serial@1d0c000 { 159 serial1: serial@1d0c000 {
138 compatible = "ns16550a"; 160 compatible = "ns16550a";
139 reg = <0x10c000 0x100>; 161 reg = <0x10c000 0x100>;
140 clock-frequency = <150000000>;
141 reg-shift = <2>; 162 reg-shift = <2>;
142 interrupts = <53>; 163 interrupts = <53>;
143 status = "disabled"; 164 status = "disabled";
@@ -145,7 +166,6 @@
145 serial2: serial@1d0d000 { 166 serial2: serial@1d0d000 {
146 compatible = "ns16550a"; 167 compatible = "ns16550a";
147 reg = <0x10d000 0x100>; 168 reg = <0x10d000 0x100>;
148 clock-frequency = <150000000>;
149 reg-shift = <2>; 169 reg-shift = <2>;
150 interrupts = <61>; 170 interrupts = <61>;
151 status = "disabled"; 171 status = "disabled";
@@ -216,6 +236,26 @@
216 interrupts = <56>; 236 interrupts = <56>;
217 status = "disabled"; 237 status = "disabled";
218 }; 238 };
239 mdio: mdio@1e24000 {
240 compatible = "ti,davinci_mdio";
241 #address-cells = <1>;
242 #size-cells = <0>;
243 reg = <0x224000 0x1000>;
244 };
245 eth0: ethernet@1e20000 {
246 compatible = "ti,davinci-dm6467-emac";
247 reg = <0x220000 0x4000>;
248 ti,davinci-ctrl-reg-offset = <0x3000>;
249 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
250 ti,davinci-ctrl-ram-offset = <0>;
251 ti,davinci-ctrl-ram-size = <0x2000>;
252 local-mac-address = [ 00 00 00 00 00 00 ];
253 interrupts = <33
254 34
255 35
256 36
257 >;
258 };
219 }; 259 };
220 nand_cs3@62000000 { 260 nand_cs3@62000000 {
221 compatible = "ti,davinci-nand"; 261 compatible = "ti,davinci-nand";
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 5cae2ab69762..022646ef4b38 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -42,6 +42,8 @@
42 regulator-always-on; 42 regulator-always-on;
43 regulator-boot-on; 43 regulator-boot-on;
44 gpio = <&gpio0 1 0>; 44 gpio = <&gpio0 1 0>;
45 pinctrl-0 = <&pmx_gpio_1>;
46 pinctrl-names = "default";
45 }; 47 };
46 }; 48 };
47 49
@@ -53,10 +55,24 @@
53 clock-frequency = <25000000>; 55 clock-frequency = <25000000>;
54 }; 56 };
55 }; 57 };
58
59 ir_recv: ir-receiver {
60 compatible = "gpio-ir-receiver";
61 gpios = <&gpio0 19 1>;
62 pinctrl-0 = <&pmx_gpio_19>;
63 pinctrl-names = "default";
64 };
56}; 65};
57 66
58&uart0 { status = "okay"; }; 67&uart0 { status = "okay"; };
59&sata0 { status = "okay"; }; 68&sata0 { status = "okay"; };
69&mdio { status = "okay"; };
70&eth { status = "okay"; };
71
72&ethphy {
73 compatible = "marvell,88e1310";
74 reg = <1>;
75};
60 76
61&i2c0 { 77&i2c0 {
62 status = "okay"; 78 status = "okay";
@@ -103,6 +119,7 @@
103 status = "okay"; 119 status = "okay";
104 /* sdio0 card detect is connected to wrong pin on CuBox */ 120 /* sdio0 card detect is connected to wrong pin on CuBox */
105 cd-gpios = <&gpio0 12 1>; 121 cd-gpios = <&gpio0 12 1>;
122 pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>;
106}; 123};
107 124
108&spi0 { 125&spi0 {
@@ -115,23 +132,3 @@
115 reg = <0>; 132 reg = <0>;
116 }; 133 };
117}; 134};
118
119&pinctrl {
120 pinctrl-0 = <&pmx_gpio_1 &pmx_gpio_12>;
121 pinctrl-names = "default";
122
123 pmx_gpio_1: pmx-gpio-1 {
124 marvell,pins = "mpp1";
125 marvell,function = "gpio";
126 };
127
128 pmx_gpio_12: pmx-gpio-12 {
129 marvell,pins = "mpp12";
130 marvell,function = "gpio";
131 };
132
133 pmx_gpio_18: pmx-gpio-18 {
134 marvell,pins = "mpp18";
135 marvell,function = "gpio";
136 };
137};
diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts
new file mode 100644
index 000000000000..e2222ce94f2f
--- /dev/null
+++ b/arch/arm/boot/dts/dove-d2plug.dts
@@ -0,0 +1,69 @@
1/dts-v1/;
2
3/include/ "dove.dtsi"
4
5/ {
6 model = "Globalscale D2Plug";
7 compatible = "globalscale,d2plug", "marvell,dove";
8
9 memory {
10 device_type = "memory";
11 reg = <0x00000000 0x40000000>;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200n8 earlyprintk";
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>;
21 pinctrl-names = "default";
22
23 wlan-ap {
24 label = "wlan-ap";
25 gpios = <&gpio0 0 1>;
26 };
27
28 wlan-act {
29 label = "wlan-act";
30 gpios = <&gpio0 1 1>;
31 };
32
33 bluetooth-act {
34 label = "bt-act";
35 gpios = <&gpio0 2 1>;
36 };
37 };
38};
39
40&uart0 { status = "okay"; };
41&sata0 { status = "okay"; };
42&i2c0 { status = "okay"; };
43&mdio { status = "okay"; };
44&eth { status = "okay"; };
45
46/* Samsung M8G2F eMMC */
47&sdio0 {
48 status = "okay";
49 non-removable;
50 bus-width = <4>;
51};
52
53/* Marvell SD8787 WLAN/BT */
54&sdio1 {
55 status = "okay";
56 non-removable;
57 bus-width = <4>;
58};
59
60&spi0 {
61 status = "okay";
62
63 /* spi0.0: 4M Flash Macronix MX25L3205D */
64 spi-flash@0 {
65 compatible = "st,m25l3205d";
66 spi-max-frequency = <20000000>;
67 reg = <0>;
68 };
69};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 6cab46849cdb..cc279166646f 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -10,6 +10,23 @@
10 gpio2 = &gpio2; 10 gpio2 = &gpio2;
11 }; 11 };
12 12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu0: cpu@0 {
18 compatible = "marvell,pj4a", "marvell,sheeva-v7";
19 device_type = "cpu";
20 next-level-cache = <&l2>;
21 reg = <0>;
22 };
23 };
24
25 l2: l2-cache {
26 compatible = "marvell,tauros2-cache";
27 marvell,tauros2-cache-features = <0>;
28 };
29
13 soc@f1000000 { 30 soc@f1000000 {
14 compatible = "simple-bus"; 31 compatible = "simple-bus";
15 #address-cells = <1>; 32 #address-cells = <1>;
@@ -25,16 +42,28 @@
25 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */ 42 0xf2100000 0xf2100000 0x0100000 /* PCIe0 I/O 1M */
26 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */ 43 0xf8000000 0xf8000000 0x8000000>; /* BootROM 128M */
27 44
28 l2: l2-cache { 45 timer: timer@20300 {
29 compatible = "marvell,tauros2-cache"; 46 compatible = "marvell,orion-timer";
30 marvell,tauros2-cache-features = <0>; 47 reg = <0x20300 0x20>;
48 interrupt-parent = <&bridge_intc>;
49 interrupts = <1>, <2>;
50 clocks = <&core_clk 0>;
31 }; 51 };
32 52
33 intc: interrupt-controller { 53 intc: main-interrupt-ctrl@20200 {
34 compatible = "marvell,orion-intc"; 54 compatible = "marvell,orion-intc";
35 interrupt-controller; 55 interrupt-controller;
36 #interrupt-cells = <1>; 56 #interrupt-cells = <1>;
37 reg = <0x20204 0x04>, <0x20214 0x04>; 57 reg = <0x20200 0x10>, <0x20210 0x10>;
58 };
59
60 bridge_intc: bridge-interrupt-ctrl@20110 {
61 compatible = "marvell,orion-bridge-intc";
62 interrupt-controller;
63 #interrupt-cells = <1>;
64 reg = <0x20110 0x8>;
65 interrupts = <0>;
66 marvell,#interrupts = <5>;
38 }; 67 };
39 68
40 core_clk: core-clocks@d0214 { 69 core_clk: core-clocks@d0214 {
@@ -43,14 +72,14 @@
43 #clock-cells = <1>; 72 #clock-cells = <1>;
44 }; 73 };
45 74
46 gate_clk: clock-gating-control@d0038 { 75 gate_clk: clock-gating-ctrl@d0038 {
47 compatible = "marvell,dove-gating-clock"; 76 compatible = "marvell,dove-gating-clock";
48 reg = <0xd0038 0x4>; 77 reg = <0xd0038 0x4>;
49 clocks = <&core_clk 0>; 78 clocks = <&core_clk 0>;
50 #clock-cells = <1>; 79 #clock-cells = <1>;
51 }; 80 };
52 81
53 thermal: thermal@d001c { 82 thermal: thermal-diode@d001c {
54 compatible = "marvell,dove-thermal"; 83 compatible = "marvell,dove-thermal";
55 reg = <0xd001c 0x0c>, <0xd005c 0x08>; 84 reg = <0xd001c 0x0c>, <0xd005c 0x08>;
56 }; 85 };
@@ -70,6 +99,8 @@
70 reg-shift = <2>; 99 reg-shift = <2>;
71 interrupts = <8>; 100 interrupts = <8>;
72 clocks = <&core_clk 0>; 101 clocks = <&core_clk 0>;
102 pinctrl-0 = <&pmx_uart1>;
103 pinctrl-names = "default";
73 status = "disabled"; 104 status = "disabled";
74 }; 105 };
75 106
@@ -91,7 +122,7 @@
91 status = "disabled"; 122 status = "disabled";
92 }; 123 };
93 124
94 gpio0: gpio@d0400 { 125 gpio0: gpio-ctrl@d0400 {
95 compatible = "marvell,orion-gpio"; 126 compatible = "marvell,orion-gpio";
96 #gpio-cells = <2>; 127 #gpio-cells = <2>;
97 gpio-controller; 128 gpio-controller;
@@ -102,7 +133,7 @@
102 interrupts = <12>, <13>, <14>, <60>; 133 interrupts = <12>, <13>, <14>, <60>;
103 }; 134 };
104 135
105 gpio1: gpio@d0420 { 136 gpio1: gpio-ctrl@d0420 {
106 compatible = "marvell,orion-gpio"; 137 compatible = "marvell,orion-gpio";
107 #gpio-cells = <2>; 138 #gpio-cells = <2>;
108 gpio-controller; 139 gpio-controller;
@@ -113,7 +144,7 @@
113 interrupts = <61>; 144 interrupts = <61>;
114 }; 145 };
115 146
116 gpio2: gpio@e8400 { 147 gpio2: gpio-ctrl@e8400 {
117 compatible = "marvell,orion-gpio"; 148 compatible = "marvell,orion-gpio";
118 #gpio-cells = <2>; 149 #gpio-cells = <2>;
119 gpio-controller; 150 gpio-controller;
@@ -121,13 +152,188 @@
121 ngpios = <8>; 152 ngpios = <8>;
122 }; 153 };
123 154
124 pinctrl: pinctrl@d0200 { 155 pinctrl: pin-ctrl@d0200 {
125 compatible = "marvell,dove-pinctrl"; 156 compatible = "marvell,dove-pinctrl";
126 reg = <0xd0200 0x10>; 157 reg = <0xd0200 0x10>;
127 clocks = <&gate_clk 22>; 158 clocks = <&gate_clk 22>;
159
160 pmx_gpio_0: pmx-gpio-0 {
161 marvell,pins = "mpp0";
162 marvell,function = "gpio";
163 };
164
165 pmx_gpio_1: pmx-gpio-1 {
166 marvell,pins = "mpp1";
167 marvell,function = "gpio";
168 };
169
170 pmx_gpio_2: pmx-gpio-2 {
171 marvell,pins = "mpp2";
172 marvell,function = "gpio";
173 };
174
175 pmx_gpio_3: pmx-gpio-3 {
176 marvell,pins = "mpp3";
177 marvell,function = "gpio";
178 };
179
180 pmx_gpio_4: pmx-gpio-4 {
181 marvell,pins = "mpp4";
182 marvell,function = "gpio";
183 };
184
185 pmx_gpio_5: pmx-gpio-5 {
186 marvell,pins = "mpp5";
187 marvell,function = "gpio";
188 };
189
190 pmx_gpio_6: pmx-gpio-6 {
191 marvell,pins = "mpp6";
192 marvell,function = "gpio";
193 };
194
195 pmx_gpio_7: pmx-gpio-7 {
196 marvell,pins = "mpp7";
197 marvell,function = "gpio";
198 };
199
200 pmx_gpio_8: pmx-gpio-8 {
201 marvell,pins = "mpp8";
202 marvell,function = "gpio";
203 };
204
205 pmx_gpio_9: pmx-gpio-9 {
206 marvell,pins = "mpp9";
207 marvell,function = "gpio";
208 };
209
210 pmx_gpio_10: pmx-gpio-10 {
211 marvell,pins = "mpp10";
212 marvell,function = "gpio";
213 };
214
215 pmx_gpio_11: pmx-gpio-11 {
216 marvell,pins = "mpp11";
217 marvell,function = "gpio";
218 };
219
220 pmx_gpio_12: pmx-gpio-12 {
221 marvell,pins = "mpp12";
222 marvell,function = "gpio";
223 };
224
225 pmx_gpio_13: pmx-gpio-13 {
226 marvell,pins = "mpp13";
227 marvell,function = "gpio";
228 };
229
230 pmx_gpio_14: pmx-gpio-14 {
231 marvell,pins = "mpp14";
232 marvell,function = "gpio";
233 };
234
235 pmx_gpio_15: pmx-gpio-15 {
236 marvell,pins = "mpp15";
237 marvell,function = "gpio";
238 };
239
240 pmx_gpio_16: pmx-gpio-16 {
241 marvell,pins = "mpp16";
242 marvell,function = "gpio";
243 };
244
245 pmx_gpio_17: pmx-gpio-17 {
246 marvell,pins = "mpp17";
247 marvell,function = "gpio";
248 };
249
250 pmx_gpio_18: pmx-gpio-18 {
251 marvell,pins = "mpp18";
252 marvell,function = "gpio";
253 };
254
255 pmx_gpio_19: pmx-gpio-19 {
256 marvell,pins = "mpp19";
257 marvell,function = "gpio";
258 };
259
260 pmx_gpio_20: pmx-gpio-20 {
261 marvell,pins = "mpp20";
262 marvell,function = "gpio";
263 };
264
265 pmx_gpio_21: pmx-gpio-21 {
266 marvell,pins = "mpp21";
267 marvell,function = "gpio";
268 };
269
270 pmx_camera: pmx-camera {
271 marvell,pins = "mpp_camera";
272 marvell,function = "camera";
273 };
274
275 pmx_camera_gpio: pmx-camera-gpio {
276 marvell,pins = "mpp_camera";
277 marvell,function = "gpio";
278 };
279
280 pmx_sdio0: pmx-sdio0 {
281 marvell,pins = "mpp_sdio0";
282 marvell,function = "sdio0";
283 };
284
285 pmx_sdio0_gpio: pmx-sdio0-gpio {
286 marvell,pins = "mpp_sdio0";
287 marvell,function = "gpio";
288 };
289
290 pmx_sdio1: pmx-sdio1 {
291 marvell,pins = "mpp_sdio1";
292 marvell,function = "sdio1";
293 };
294
295 pmx_sdio1_gpio: pmx-sdio1-gpio {
296 marvell,pins = "mpp_sdio1";
297 marvell,function = "gpio";
298 };
299
300 pmx_audio1_gpio: pmx-audio1-gpio {
301 marvell,pins = "mpp_audio1";
302 marvell,function = "gpio";
303 };
304
305 pmx_spi0: pmx-spi0 {
306 marvell,pins = "mpp_spi0";
307 marvell,function = "spi0";
308 };
309
310 pmx_spi0_gpio: pmx-spi0-gpio {
311 marvell,pins = "mpp_spi0";
312 marvell,function = "gpio";
313 };
314
315 pmx_uart1: pmx-uart1 {
316 marvell,pins = "mpp_uart1";
317 marvell,function = "uart1";
318 };
319
320 pmx_uart1_gpio: pmx-uart1-gpio {
321 marvell,pins = "mpp_uart1";
322 marvell,function = "gpio";
323 };
324
325 pmx_nand: pmx-nand {
326 marvell,pins = "mpp_nand";
327 marvell,function = "nand";
328 };
329
330 pmx_nand_gpo: pmx-nand-gpo {
331 marvell,pins = "mpp_nand";
332 marvell,function = "gpo";
333 };
128 }; 334 };
129 335
130 spi0: spi@10600 { 336 spi0: spi-ctrl@10600 {
131 compatible = "marvell,orion-spi"; 337 compatible = "marvell,orion-spi";
132 #address-cells = <1>; 338 #address-cells = <1>;
133 #size-cells = <0>; 339 #size-cells = <0>;
@@ -135,10 +341,12 @@
135 interrupts = <6>; 341 interrupts = <6>;
136 reg = <0x10600 0x28>; 342 reg = <0x10600 0x28>;
137 clocks = <&core_clk 0>; 343 clocks = <&core_clk 0>;
344 pinctrl-0 = <&pmx_spi0>;
345 pinctrl-names = "default";
138 status = "disabled"; 346 status = "disabled";
139 }; 347 };
140 348
141 spi1: spi@14600 { 349 spi1: spi-ctrl@14600 {
142 compatible = "marvell,orion-spi"; 350 compatible = "marvell,orion-spi";
143 #address-cells = <1>; 351 #address-cells = <1>;
144 #size-cells = <0>; 352 #size-cells = <0>;
@@ -149,7 +357,7 @@
149 status = "disabled"; 357 status = "disabled";
150 }; 358 };
151 359
152 i2c0: i2c@11000 { 360 i2c0: i2c-ctrl@11000 {
153 compatible = "marvell,mv64xxx-i2c"; 361 compatible = "marvell,mv64xxx-i2c";
154 reg = <0x11000 0x20>; 362 reg = <0x11000 0x20>;
155 #address-cells = <1>; 363 #address-cells = <1>;
@@ -177,23 +385,27 @@
177 status = "okay"; 385 status = "okay";
178 }; 386 };
179 387
180 sdio0: sdio@92000 { 388 sdio0: sdio-host@92000 {
181 compatible = "marvell,dove-sdhci"; 389 compatible = "marvell,dove-sdhci";
182 reg = <0x92000 0x100>; 390 reg = <0x92000 0x100>;
183 interrupts = <35>, <37>; 391 interrupts = <35>, <37>;
184 clocks = <&gate_clk 8>; 392 clocks = <&gate_clk 8>;
393 pinctrl-0 = <&pmx_sdio0>;
394 pinctrl-names = "default";
185 status = "disabled"; 395 status = "disabled";
186 }; 396 };
187 397
188 sdio1: sdio@90000 { 398 sdio1: sdio-host@90000 {
189 compatible = "marvell,dove-sdhci"; 399 compatible = "marvell,dove-sdhci";
190 reg = <0x90000 0x100>; 400 reg = <0x90000 0x100>;
191 interrupts = <36>, <38>; 401 interrupts = <36>, <38>;
192 clocks = <&gate_clk 9>; 402 clocks = <&gate_clk 9>;
403 pinctrl-0 = <&pmx_sdio1>;
404 pinctrl-names = "default";
193 status = "disabled"; 405 status = "disabled";
194 }; 406 };
195 407
196 sata0: sata@a0000 { 408 sata0: sata-host@a0000 {
197 compatible = "marvell,orion-sata"; 409 compatible = "marvell,orion-sata";
198 reg = <0xa0000 0x2400>; 410 reg = <0xa0000 0x2400>;
199 interrupts = <62>; 411 interrupts = <62>;
@@ -202,12 +414,12 @@
202 status = "disabled"; 414 status = "disabled";
203 }; 415 };
204 416
205 rtc@d8500 { 417 rtc: real-time-clock@d8500 {
206 compatible = "marvell,orion-rtc"; 418 compatible = "marvell,orion-rtc";
207 reg = <0xd8500 0x20>; 419 reg = <0xd8500 0x20>;
208 }; 420 };
209 421
210 crypto: crypto@30000 { 422 crypto: crypto-engine@30000 {
211 compatible = "marvell,orion-crypto"; 423 compatible = "marvell,orion-crypto";
212 reg = <0x30000 0x10000>, 424 reg = <0x30000 0x10000>,
213 <0xc8000000 0x800>; 425 <0xc8000000 0x800>;
@@ -258,5 +470,40 @@
258 dmacap,xor; 470 dmacap,xor;
259 }; 471 };
260 }; 472 };
473
474 mdio: mdio-bus@72004 {
475 compatible = "marvell,orion-mdio";
476 #address-cells = <1>;
477 #size-cells = <0>;
478 reg = <0x72004 0x84>;
479 interrupts = <30>;
480 clocks = <&gate_clk 2>;
481 status = "disabled";
482
483 ethphy: ethernet-phy {
484 device-type = "ethernet-phy";
485 /* set phy address in board file */
486 };
487 };
488
489 eth: ethernet-controller@72000 {
490 compatible = "marvell,orion-eth";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 reg = <0x72000 0x4000>;
494 clocks = <&gate_clk 2>;
495 marvell,tx-checksum-limit = <1600>;
496 status = "disabled";
497
498 ethernet-port@0 {
499 device_type = "network";
500 compatible = "marvell,orion-eth-port";
501 reg = <0>;
502 interrupts = <29>;
503 /* overwrite MAC address in bootloader */
504 local-mac-address = [00 00 00 00 00 00];
505 phy-handle = <&ethphy>;
506 };
507 };
261 }; 508 };
262}; 509};
diff --git a/arch/arm/boot/dts/emev2-kzm9d-reference.dts b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
new file mode 100644
index 000000000000..cceefda268b6
--- /dev/null
+++ b/arch/arm/boot/dts/emev2-kzm9d-reference.dts
@@ -0,0 +1,57 @@
1/*
2 * Device Tree Source for the KZM9D board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10/dts-v1/;
11
12/include/ "emev2.dtsi"
13
14/ {
15 model = "EMEV2 KZM9D Board";
16 compatible = "renesas,kzm9d-reference", "renesas,emev2";
17
18 memory {
19 device_type = "memory";
20 reg = <0x40000000 0x8000000>;
21 };
22
23 chosen {
24 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
25 };
26
27 reg_1p8v: regulator@0 {
28 compatible = "regulator-fixed";
29 regulator-name = "fixed-1.8V";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <1800000>;
32 regulator-always-on;
33 regulator-boot-on;
34 };
35
36 reg_3p3v: regulator@1 {
37 compatible = "regulator-fixed";
38 regulator-name = "fixed-3.3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 regulator-always-on;
42 regulator-boot-on;
43 };
44
45 lan9220@20000000 {
46 compatible = "smsc,lan9220", "smsc,lan9115";
47 reg = <0x20000000 0x10000>;
48 phy-mode = "mii";
49 interrupt-parent = <&gpio0>;
50 interrupts = <1 1>; /* active high */
51 reg-io-width = <4>;
52 smsc,irq-active-high;
53 smsc,irq-push-pull;
54 vddvario-supply = <&reg_1p8v>;
55 vdd33a-supply = <&reg_3p3v>;
56 };
57};
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index b9b3241f173b..f92e812fdd9f 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -21,6 +21,6 @@
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 bootargs = "console=tty0 console=ttyS1,115200n81 earlyprintk=serial8250-em.1,115200n81 mem=128M@0x40000000 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096"; 24 bootargs = "console=ttyS1,115200n81 ignore_loglevel root=/dev/nfs ip=dhcp";
25 }; 25 };
26}; 26};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index c8a8c08b48dd..9063a4434d6a 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -14,6 +14,14 @@
14 compatible = "renesas,emev2"; 14 compatible = "renesas,emev2";
15 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
16 16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 gpio3 = &gpio3;
22 gpio4 = &gpio4;
23 };
24
17 cpus { 25 cpus {
18 #address-cells = <1>; 26 #address-cells = <1>;
19 #size-cells = <0>; 27 #size-cells = <0>;
@@ -38,6 +46,12 @@
38 <0xe0020000 0x0100>; 46 <0xe0020000 0x0100>;
39 }; 47 };
40 48
49 pmu {
50 compatible = "arm,cortex-a9-pmu";
51 interrupts = <0 120 4>,
52 <0 121 4>;
53 };
54
41 sti@e0180000 { 55 sti@e0180000 {
42 compatible = "renesas,em-sti"; 56 compatible = "renesas,em-sti";
43 reg = <0xe0180000 0x54>; 57 reg = <0xe0180000 0x54>;
@@ -67,4 +81,55 @@
67 reg = <0xe1050000 0x38>; 81 reg = <0xe1050000 0x38>;
68 interrupts = <0 11 0>; 82 interrupts = <0 11 0>;
69 }; 83 };
84
85 gpio0: gpio@e0050000 {
86 compatible = "renesas,em-gio";
87 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
88 interrupts = <0 67 0>, <0 68 0>;
89 gpio-controller;
90 #gpio-cells = <2>;
91 ngpios = <32>;
92 interrupt-controller;
93 #interrupt-cells = <2>;
94 };
95 gpio1: gpio@e0050080 {
96 compatible = "renesas,em-gio";
97 reg = <0xe0050080 0x2c>, <0xe00500c0 0x20>;
98 interrupts = <0 69 0>, <0 70 0>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 ngpios = <32>;
102 interrupt-controller;
103 #interrupt-cells = <2>;
104 };
105 gpio2: gpio@e0050100 {
106 compatible = "renesas,em-gio";
107 reg = <0xe0050100 0x2c>, <0xe0050140 0x20>;
108 interrupts = <0 71 0>, <0 72 0>;
109 gpio-controller;
110 #gpio-cells = <2>;
111 ngpios = <32>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 };
115 gpio3: gpio@e0050180 {
116 compatible = "renesas,em-gio";
117 reg = <0xe0050180 0x2c>, <0xe00501c0 0x20>;
118 interrupts = <0 73 0>, <0 74 0>;
119 gpio-controller;
120 #gpio-cells = <2>;
121 ngpios = <32>;
122 interrupt-controller;
123 #interrupt-cells = <2>;
124 };
125 gpio4: gpio@e0050200 {
126 compatible = "renesas,em-gio";
127 reg = <0xe0050200 0x2c>, <0xe0050240 0x20>;
128 interrupts = <0 75 0>, <0 76 0>;
129 gpio-controller;
130 #gpio-cells = <2>;
131 ngpios = <31>;
132 interrupt-controller;
133 #interrupt-cells = <2>;
134 };
70}; 135};
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index 3f94fe8e3706..caadc0257342 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -36,6 +36,12 @@
36 i2c5 = &i2c_5; 36 i2c5 = &i2c_5;
37 i2c6 = &i2c_6; 37 i2c6 = &i2c_6;
38 i2c7 = &i2c_7; 38 i2c7 = &i2c_7;
39 csis0 = &csis_0;
40 csis1 = &csis_1;
41 fimc0 = &fimc_0;
42 fimc1 = &fimc_1;
43 fimc2 = &fimc_2;
44 fimc3 = &fimc_3;
39 }; 45 };
40 46
41 chipid@10000000 { 47 chipid@10000000 {
@@ -92,6 +98,88 @@
92 reg = <0x10010000 0x400>; 98 reg = <0x10010000 0x400>;
93 }; 99 };
94 100
101 camera {
102 compatible = "samsung,fimc", "simple-bus";
103 status = "disabled";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107
108 clock_cam: clock-controller {
109 #clock-cells = <1>;
110 };
111
112 fimc_0: fimc@11800000 {
113 compatible = "samsung,exynos4210-fimc";
114 reg = <0x11800000 0x1000>;
115 interrupts = <0 84 0>;
116 clocks = <&clock 256>, <&clock 128>;
117 clock-names = "fimc", "sclk_fimc";
118 samsung,power-domain = <&pd_cam>;
119 samsung,sysreg = <&sys_reg>;
120 status = "disabled";
121 };
122
123 fimc_1: fimc@11810000 {
124 compatible = "samsung,exynos4210-fimc";
125 reg = <0x11810000 0x1000>;
126 interrupts = <0 85 0>;
127 clocks = <&clock 257>, <&clock 129>;
128 clock-names = "fimc", "sclk_fimc";
129 samsung,power-domain = <&pd_cam>;
130 samsung,sysreg = <&sys_reg>;
131 status = "disabled";
132 };
133
134 fimc_2: fimc@11820000 {
135 compatible = "samsung,exynos4210-fimc";
136 reg = <0x11820000 0x1000>;
137 interrupts = <0 86 0>;
138 clocks = <&clock 258>, <&clock 130>;
139 clock-names = "fimc", "sclk_fimc";
140 samsung,power-domain = <&pd_cam>;
141 samsung,sysreg = <&sys_reg>;
142 status = "disabled";
143 };
144
145 fimc_3: fimc@11830000 {
146 compatible = "samsung,exynos4210-fimc";
147 reg = <0x11830000 0x1000>;
148 interrupts = <0 87 0>;
149 clocks = <&clock 259>, <&clock 131>;
150 clock-names = "fimc", "sclk_fimc";
151 samsung,power-domain = <&pd_cam>;
152 samsung,sysreg = <&sys_reg>;
153 status = "disabled";
154 };
155
156 csis_0: csis@11880000 {
157 compatible = "samsung,exynos4210-csis";
158 reg = <0x11880000 0x4000>;
159 interrupts = <0 78 0>;
160 clocks = <&clock 260>, <&clock 134>;
161 clock-names = "csis", "sclk_csis";
162 bus-width = <4>;
163 samsung,power-domain = <&pd_cam>;
164 status = "disabled";
165 #address-cells = <1>;
166 #size-cells = <0>;
167 };
168
169 csis_1: csis@11890000 {
170 compatible = "samsung,exynos4210-csis";
171 reg = <0x11890000 0x4000>;
172 interrupts = <0 80 0>;
173 clocks = <&clock 261>, <&clock 135>;
174 clock-names = "csis", "sclk_csis";
175 bus-width = <2>;
176 samsung,power-domain = <&pd_cam>;
177 status = "disabled";
178 #address-cells = <1>;
179 #size-cells = <0>;
180 };
181 };
182
95 watchdog@10060000 { 183 watchdog@10060000 {
96 compatible = "samsung,s3c2410-wdt"; 184 compatible = "samsung,s3c2410-wdt";
97 reg = <0x10060000 0x100>; 185 reg = <0x10060000 0x100>;
@@ -155,13 +243,31 @@
155 status = "disabled"; 243 status = "disabled";
156 }; 244 };
157 245
246 ehci@12580000 {
247 compatible = "samsung,exynos4210-ehci";
248 reg = <0x12580000 0x100>;
249 interrupts = <0 70 0>;
250 clocks = <&clock 304>;
251 clock-names = "usbhost";
252 status = "disabled";
253 };
254
255 ohci@12590000 {
256 compatible = "samsung,exynos4210-ohci";
257 reg = <0x12590000 0x100>;
258 interrupts = <0 70 0>;
259 clocks = <&clock 304>;
260 clock-names = "usbhost";
261 status = "disabled";
262 };
263
158 mfc: codec@13400000 { 264 mfc: codec@13400000 {
159 compatible = "samsung,mfc-v5"; 265 compatible = "samsung,mfc-v5";
160 reg = <0x13400000 0x10000>; 266 reg = <0x13400000 0x10000>;
161 interrupts = <0 94 0>; 267 interrupts = <0 94 0>;
162 samsung,power-domain = <&pd_mfc>; 268 samsung,power-domain = <&pd_mfc>;
163 clocks = <&clock 170>, <&clock 273>; 269 clocks = <&clock 273>;
164 clock-names = "sclk_mfc", "mfc"; 270 clock-names = "mfc";
165 status = "disabled"; 271 status = "disabled";
166 }; 272 };
167 273
@@ -297,8 +403,8 @@
297 compatible = "samsung,exynos4210-spi"; 403 compatible = "samsung,exynos4210-spi";
298 reg = <0x13920000 0x100>; 404 reg = <0x13920000 0x100>;
299 interrupts = <0 66 0>; 405 interrupts = <0 66 0>;
300 tx-dma-channel = <&pdma0 7>; /* preliminary */ 406 dmas = <&pdma0 7>, <&pdma0 6>;
301 rx-dma-channel = <&pdma0 6>; /* preliminary */ 407 dma-names = "tx", "rx";
302 #address-cells = <1>; 408 #address-cells = <1>;
303 #size-cells = <0>; 409 #size-cells = <0>;
304 clocks = <&clock 327>, <&clock 159>; 410 clocks = <&clock 327>, <&clock 159>;
@@ -312,8 +418,8 @@
312 compatible = "samsung,exynos4210-spi"; 418 compatible = "samsung,exynos4210-spi";
313 reg = <0x13930000 0x100>; 419 reg = <0x13930000 0x100>;
314 interrupts = <0 67 0>; 420 interrupts = <0 67 0>;
315 tx-dma-channel = <&pdma1 7>; /* preliminary */ 421 dmas = <&pdma1 7>, <&pdma1 6>;
316 rx-dma-channel = <&pdma1 6>; /* preliminary */ 422 dma-names = "tx", "rx";
317 #address-cells = <1>; 423 #address-cells = <1>;
318 #size-cells = <0>; 424 #size-cells = <0>;
319 clocks = <&clock 328>, <&clock 160>; 425 clocks = <&clock 328>, <&clock 160>;
@@ -327,8 +433,8 @@
327 compatible = "samsung,exynos4210-spi"; 433 compatible = "samsung,exynos4210-spi";
328 reg = <0x13940000 0x100>; 434 reg = <0x13940000 0x100>;
329 interrupts = <0 68 0>; 435 interrupts = <0 68 0>;
330 tx-dma-channel = <&pdma0 9>; /* preliminary */ 436 dmas = <&pdma0 9>, <&pdma0 8>;
331 rx-dma-channel = <&pdma0 8>; /* preliminary */ 437 dma-names = "tx", "rx";
332 #address-cells = <1>; 438 #address-cells = <1>;
333 #size-cells = <0>; 439 #size-cells = <0>;
334 clocks = <&clock 329>, <&clock 161>; 440 clocks = <&clock 329>, <&clock 161>;
@@ -342,6 +448,8 @@
342 compatible = "samsung,exynos4210-pwm"; 448 compatible = "samsung,exynos4210-pwm";
343 reg = <0x139D0000 0x1000>; 449 reg = <0x139D0000 0x1000>;
344 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>; 450 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>, <0 41 0>;
451 clocks = <&clock 336>;
452 clock-names = "timers";
345 #pwm-cells = <2>; 453 #pwm-cells = <2>;
346 status = "disabled"; 454 status = "disabled";
347 }; 455 };
diff --git a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
index 553bceae8967..a7c212891674 100644
--- a/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4210-pinctrl.dtsi
@@ -797,6 +797,29 @@
797 samsung,pin-pud = <0>; 797 samsung,pin-pud = <0>;
798 samsung,pin-drv = <0>; 798 samsung,pin-drv = <0>;
799 }; 799 };
800
801 cam_port_a_io: cam-port-a-io {
802 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
803 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
804 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
805 samsung,pin-function = <2>;
806 samsung,pin-pud = <0>;
807 samsung,pin-drv = <0>;
808 };
809
810 cam_port_a_clk_active: cam-port-a-clk-active {
811 samsung,pins = "gpj1-3";
812 samsung,pin-function = <2>;
813 samsung,pin-pud = <0>;
814 samsung,pin-drv = <3>;
815 };
816
817 cam_port_a_clk_idle: cam-port-a-clk-idle {
818 samsung,pins = "gpj1-3";
819 samsung,pin-function = <0>;
820 samsung,pin-pud = <1>;
821 samsung,pin-drv = <0>;
822 };
800 }; 823 };
801 824
802 pinctrl@03860000 { 825 pinctrl@03860000 {
diff --git a/arch/arm/boot/dts/exynos4210-trats.dts b/arch/arm/boot/dts/exynos4210-trats.dts
index 94eebffe3044..1c164f234bcc 100644
--- a/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/arch/arm/boot/dts/exynos4210-trats.dts
@@ -30,13 +30,62 @@
30 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5"; 30 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
31 }; 31 };
32 32
33 vemmc_reg: voltage-regulator@0 { 33 regulators {
34 compatible = "regulator-fixed"; 34 compatible = "simple-bus";
35 regulator-name = "VMEM_VDD_2.8V"; 35
36 regulator-min-microvolt = <2800000>; 36 vemmc_reg: regulator-0 {
37 regulator-max-microvolt = <2800000>; 37 compatible = "regulator-fixed";
38 gpio = <&gpk0 2 0>; 38 regulator-name = "VMEM_VDD_2.8V";
39 enable-active-high; 39 regulator-min-microvolt = <2800000>;
40 regulator-max-microvolt = <2800000>;
41 gpio = <&gpk0 2 0>;
42 enable-active-high;
43 };
44
45 tsp_reg: regulator-1 {
46 compatible = "regulator-fixed";
47 regulator-name = "TSP_FIXED_VOLTAGES";
48 regulator-min-microvolt = <2800000>;
49 regulator-max-microvolt = <2800000>;
50 gpio = <&gpl0 3 0>;
51 enable-active-high;
52 };
53
54 cam_af_28v_reg: regulator-2 {
55 compatible = "regulator-fixed";
56 regulator-name = "8M_AF_2.8V_EN";
57 regulator-min-microvolt = <2800000>;
58 regulator-max-microvolt = <2800000>;
59 gpio = <&gpk1 1 0>;
60 enable-active-high;
61 };
62
63 cam_io_en_reg: regulator-3 {
64 compatible = "regulator-fixed";
65 regulator-name = "CAM_IO_EN";
66 regulator-min-microvolt = <2800000>;
67 regulator-max-microvolt = <2800000>;
68 gpio = <&gpe2 1 0>;
69 enable-active-high;
70 };
71
72 cam_io_12v_reg: regulator-4 {
73 compatible = "regulator-fixed";
74 regulator-name = "8M_1.2V_EN";
75 regulator-min-microvolt = <1200000>;
76 regulator-max-microvolt = <1200000>;
77 gpio = <&gpe2 5 0>;
78 enable-active-high;
79 };
80
81 vt_core_15v_reg: regulator-5 {
82 compatible = "regulator-fixed";
83 regulator-name = "VT_CORE_1.5V";
84 regulator-min-microvolt = <1500000>;
85 regulator-max-microvolt = <1500000>;
86 gpio = <&gpe2 2 0>;
87 enable-active-high;
88 };
40 }; 89 };
41 90
42 sdhci_emmc: sdhci@12510000 { 91 sdhci_emmc: sdhci@12510000 {
@@ -97,15 +146,6 @@
97 }; 146 };
98 }; 147 };
99 148
100 tsp_reg: voltage-regulator {
101 compatible = "regulator-fixed";
102 regulator-name = "TSP_FIXED_VOLTAGES";
103 regulator-min-microvolt = <2800000>;
104 regulator-max-microvolt = <2800000>;
105 gpio = <&gpl0 3 0>;
106 enable-active-high;
107 };
108
109 i2c@13890000 { 149 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>; 150 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>; 151 samsung,i2c-slave-addr = <0x10>;
@@ -218,6 +258,12 @@
218 regulator-always-on; 258 regulator-always-on;
219 }; 259 };
220 260
261 vtcam_reg: LDO12 {
262 regulator-name = "VT_CAM_1.8V";
263 regulator-min-microvolt = <1800000>;
264 regulator-max-microvolt = <1800000>;
265 };
266
221 vcclcd_reg: LDO13 { 267 vcclcd_reg: LDO13 {
222 regulator-name = "VCC_3.3V_LCD"; 268 regulator-name = "VCC_3.3V_LCD";
223 regulator-min-microvolt = <3300000>; 269 regulator-min-microvolt = <3300000>;
@@ -301,4 +347,26 @@
301 clock-frequency = <24000000>; 347 clock-frequency = <24000000>;
302 }; 348 };
303 }; 349 };
350
351 camera {
352 pinctrl-names = "default";
353 pinctrl-0 = <>;
354 status = "okay";
355
356 fimc_0: fimc@11800000 {
357 status = "okay";
358 };
359
360 fimc_1: fimc@11810000 {
361 status = "okay";
362 };
363
364 fimc_2: fimc@11820000 {
365 status = "okay";
366 };
367
368 fimc_3: fimc@11830000 {
369 status = "okay";
370 };
371 };
304}; 372};
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index b7f358a93bcb..057d6829d319 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -72,7 +72,7 @@
72 }; 72 };
73 }; 73 };
74 74
75 clock: clock-controller@0x10030000 { 75 clock: clock-controller@10030000 {
76 compatible = "samsung,exynos4210-clock"; 76 compatible = "samsung,exynos4210-clock";
77 reg = <0x10030000 0x20000>; 77 reg = <0x10030000 0x20000>;
78 #clock-cells = <1>; 78 #clock-cells = <1>;
@@ -125,4 +125,34 @@
125 clock-names = "sclk_fimg2d", "fimg2d"; 125 clock-names = "sclk_fimg2d", "fimg2d";
126 status = "disabled"; 126 status = "disabled";
127 }; 127 };
128
129 camera {
130 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
131 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
132
133 fimc_0: fimc@11800000 {
134 samsung,pix-limits = <4224 8192 1920 4224>;
135 samsung,mainscaler-ext;
136 samsung,cam-if;
137 };
138
139 fimc_1: fimc@11810000 {
140 samsung,pix-limits = <4224 8192 1920 4224>;
141 samsung,mainscaler-ext;
142 samsung,cam-if;
143 };
144
145 fimc_2: fimc@11820000 {
146 samsung,pix-limits = <4224 8192 1920 4224>;
147 samsung,mainscaler-ext;
148 samsung,lcd-wb;
149 };
150
151 fimc_3: fimc@11830000 {
152 samsung,pix-limits = <1920 8192 1366 1920>;
153 samsung,rotators = <0>;
154 samsung,mainscaler-ext;
155 samsung,lcd-wb;
156 };
157 };
128}; 158};
diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts
index 7993641cb32a..8768b03702e5 100644
--- a/arch/arm/boot/dts/exynos4412-origen.dts
+++ b/arch/arm/boot/dts/exynos4412-origen.dts
@@ -27,6 +27,11 @@
27 bootargs ="console=ttySAC2,115200"; 27 bootargs ="console=ttySAC2,115200";
28 }; 28 };
29 29
30 firmware@0203F000 {
31 compatible = "samsung,secure-firmware";
32 reg = <0x0203F000 0x1000>;
33 };
34
30 mmc_reg: voltage-regulator { 35 mmc_reg: voltage-regulator {
31 compatible = "regulator-fixed"; 36 compatible = "regulator-fixed";
32 regulator-name = "VMEM_VDD_2.8V"; 37 regulator-name = "VMEM_VDD_2.8V";
diff --git a/arch/arm/boot/dts/exynos4412-trats2.dts b/arch/arm/boot/dts/exynos4412-trats2.dts
new file mode 100644
index 000000000000..fb7b9ae5f399
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-trats2.dts
@@ -0,0 +1,579 @@
1/*
2 * Samsung's Exynos4412 based Trats 2 board device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * Device tree source file for Samsung's Trats 2 board which is based on
8 * Samsung's Exynos4412 SoC.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15/dts-v1/;
16#include "exynos4412.dtsi"
17
18/ {
19 model = "Samsung Trats 2 based on Exynos4412";
20 compatible = "samsung,trats2", "samsung,exynos4412";
21
22 aliases {
23 i2c8 = &i2c_ak8975;
24 };
25
26 memory {
27 reg = <0x40000000 0x40000000>;
28 };
29
30 chosen {
31 bootargs = "console=ttySAC2,115200N8 root=/dev/mmcblk0p5 rootwait earlyprintk panic=5";
32 };
33
34 firmware@0204F000 {
35 compatible = "samsung,secure-firmware";
36 reg = <0x0204F000 0x1000>;
37 };
38
39 fixed-rate-clocks {
40 xxti {
41 compatible = "samsung,clock-xxti", "fixed-clock";
42 clock-frequency = <0>;
43 };
44
45 xusbxti {
46 compatible = "samsung,clock-xusbxti", "fixed-clock";
47 clock-frequency = <24000000>;
48 };
49 };
50
51 regulators {
52 compatible = "simple-bus";
53 #address-cells = <1>;
54 #size-cells = <0>;
55
56 vemmc_reg: regulator-0 {
57 compatible = "regulator-fixed";
58 regulator-name = "VMEM_VDD_2.8V";
59 regulator-min-microvolt = <2800000>;
60 regulator-max-microvolt = <2800000>;
61 gpio = <&gpk0 2 0>;
62 enable-active-high;
63 };
64
65 cam_io_reg: voltage-regulator-1 {
66 compatible = "regulator-fixed";
67 regulator-name = "CAM_SENSOR_A";
68 regulator-min-microvolt = <2800000>;
69 regulator-max-microvolt = <2800000>;
70 gpio = <&gpm0 2 0>;
71 enable-active-high;
72 };
73
74 /* More to come */
75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79
80 key-down {
81 interrupt-parent = <&gpj1>;
82 interrupts = <2 0>;
83 gpios = <&gpj1 2 1>;
84 linux,code = <114>;
85 label = "volume down";
86 debounce-interval = <10>;
87 };
88
89 key-up {
90 interrupt-parent = <&gpj1>;
91 interrupts = <1 0>;
92 gpios = <&gpj1 1 1>;
93 linux,code = <115>;
94 label = "volume up";
95 debounce-interval = <10>;
96 };
97
98 key-power {
99 interrupt-parent = <&gpx2>;
100 interrupts = <7 0>;
101 gpios = <&gpx2 7 1>;
102 linux,code = <116>;
103 label = "power";
104 debounce-interval = <10>;
105 gpio-key,wakeup;
106 };
107 };
108
109 i2c@13890000 {
110 samsung,i2c-sda-delay = <100>;
111 samsung,i2c-slave-addr = <0x10>;
112 samsung,i2c-max-bus-freq = <400000>;
113 pinctrl-0 = <&i2c3_bus>;
114 pinctrl-names = "default";
115 status = "okay";
116
117 mms114-touchscreen@48 {
118 compatible = "melfas,mms114";
119 reg = <0x48>;
120 interrupt-parent = <&gpm2>;
121 interrupts = <3 2>;
122 x-size = <720>;
123 y-size = <1280>;
124 avdd-supply = <&ldo23_reg>;
125 vdd-supply = <&ldo24_reg>;
126 };
127 };
128
129 i2c@138D0000 {
130 samsung,i2c-sda-delay = <100>;
131 samsung,i2c-slave-addr = <0x10>;
132 samsung,i2c-max-bus-freq = <100000>;
133 pinctrl-0 = <&i2c7_bus>;
134 pinctrl-names = "default";
135 status = "okay";
136
137 max77686_pmic@09 {
138 compatible = "maxim,max77686";
139 interrupt-parent = <&gpx0>;
140 interrupts = <7 0>;
141 reg = <0x09>;
142
143 voltage-regulators {
144 ldo1_reg: ldo1 {
145 regulator-compatible = "LDO1";
146 regulator-name = "VALIVE_1.0V_AP";
147 regulator-min-microvolt = <1000000>;
148 regulator-max-microvolt = <1000000>;
149 regulator-always-on;
150 regulator-mem-on;
151 };
152
153 ldo2_reg: ldo2 {
154 regulator-compatible = "LDO2";
155 regulator-name = "VM1M2_1.2V_AP";
156 regulator-min-microvolt = <1200000>;
157 regulator-max-microvolt = <1200000>;
158 regulator-always-on;
159 regulator-mem-on;
160 };
161
162 ldo3_reg: ldo3 {
163 regulator-compatible = "LDO3";
164 regulator-name = "VCC_1.8V_AP";
165 regulator-min-microvolt = <1800000>;
166 regulator-max-microvolt = <1800000>;
167 regulator-always-on;
168 regulator-mem-on;
169 };
170
171 ldo4_reg: ldo4 {
172 regulator-compatible = "LDO4";
173 regulator-name = "VCC_2.8V_AP";
174 regulator-min-microvolt = <2800000>;
175 regulator-max-microvolt = <2800000>;
176 regulator-always-on;
177 regulator-mem-on;
178 };
179
180 ldo5_reg: ldo5 {
181 regulator-compatible = "LDO5";
182 regulator-name = "VCC_1.8V_IO";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 regulator-always-on;
186 regulator-mem-on;
187 };
188
189 ldo6_reg: ldo6 {
190 regulator-compatible = "LDO6";
191 regulator-name = "VMPLL_1.0V_AP";
192 regulator-min-microvolt = <1000000>;
193 regulator-max-microvolt = <1000000>;
194 regulator-always-on;
195 regulator-mem-on;
196 };
197
198 ldo7_reg: ldo7 {
199 regulator-compatible = "LDO7";
200 regulator-name = "VPLL_1.0V_AP";
201 regulator-min-microvolt = <1000000>;
202 regulator-max-microvolt = <1000000>;
203 regulator-always-on;
204 regulator-mem-on;
205 };
206
207 ldo8_reg: ldo8 {
208 regulator-compatible = "LDO8";
209 regulator-name = "VMIPI_1.0V";
210 regulator-min-microvolt = <1000000>;
211 regulator-max-microvolt = <1000000>;
212 regulator-mem-off;
213 };
214
215 ldo9_reg: ldo9 {
216 regulator-compatible = "LDO9";
217 regulator-name = "CAM_ISP_MIPI_1.2V";
218 regulator-min-microvolt = <1200000>;
219 regulator-max-microvolt = <1200000>;
220 regulator-mem-idle;
221 };
222
223 ldo10_reg: ldo10 {
224 regulator-compatible = "LDO10";
225 regulator-name = "VMIPI_1.8V";
226 regulator-min-microvolt = <1800000>;
227 regulator-max-microvolt = <1800000>;
228 regulator-mem-off;
229 };
230
231 ldo11_reg: ldo11 {
232 regulator-compatible = "LDO11";
233 regulator-name = "VABB1_1.95V";
234 regulator-min-microvolt = <1950000>;
235 regulator-max-microvolt = <1950000>;
236 regulator-always-on;
237 regulator-mem-off;
238 };
239
240 ldo12_reg: ldo12 {
241 regulator-compatible = "LDO12";
242 regulator-name = "VUOTG_3.0V";
243 regulator-min-microvolt = <3000000>;
244 regulator-max-microvolt = <3000000>;
245 regulator-mem-off;
246 };
247
248 ldo13_reg: ldo13 {
249 regulator-compatible = "LDO13";
250 regulator-name = "NFC_AVDD_1.8V";
251 regulator-min-microvolt = <1800000>;
252 regulator-max-microvolt = <1800000>;
253 regulator-mem-idle;
254 };
255
256 ldo14_reg: ldo14 {
257 regulator-compatible = "LDO14";
258 regulator-name = "VABB2_1.95V";
259 regulator-min-microvolt = <1950000>;
260 regulator-max-microvolt = <1950000>;
261 regulator-always-on;
262 regulator-mem-off;
263 };
264
265 ldo15_reg: ldo15 {
266 regulator-compatible = "LDO15";
267 regulator-name = "VHSIC_1.0V";
268 regulator-min-microvolt = <1000000>;
269 regulator-max-microvolt = <1000000>;
270 regulator-mem-off;
271 };
272
273 ldo16_reg: ldo16 {
274 regulator-compatible = "LDO16";
275 regulator-name = "VHSIC_1.8V";
276 regulator-min-microvolt = <1800000>;
277 regulator-max-microvolt = <1800000>;
278 regulator-mem-off;
279 };
280
281 ldo17_reg: ldo17 {
282 regulator-compatible = "LDO17";
283 regulator-name = "CAM_SENSOR_CORE_1.2V";
284 regulator-min-microvolt = <1200000>;
285 regulator-max-microvolt = <1200000>;
286 regulator-mem-idle;
287 };
288
289 ldo18_reg: ldo18 {
290 regulator-compatible = "LDO18";
291 regulator-name = "CAM_ISP_SEN_IO_1.8V";
292 regulator-min-microvolt = <1800000>;
293 regulator-max-microvolt = <1800000>;
294 regulator-mem-idle;
295 };
296
297 ldo19_reg: ldo19 {
298 regulator-compatible = "LDO19";
299 regulator-name = "VT_CAM_1.8V";
300 regulator-min-microvolt = <1800000>;
301 regulator-max-microvolt = <1800000>;
302 regulator-mem-idle;
303 };
304
305 ldo20_reg: ldo20 {
306 regulator-compatible = "LDO20";
307 regulator-name = "VDDQ_PRE_1.8V";
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <1800000>;
310 regulator-mem-idle;
311 };
312
313 ldo21_reg: ldo21 {
314 regulator-compatible = "LDO21";
315 regulator-name = "VTF_2.8V";
316 regulator-min-microvolt = <2800000>;
317 regulator-max-microvolt = <2800000>;
318 regulator-mem-idle;
319 };
320
321 ldo22_reg: ldo22 {
322 regulator-compatible = "LDO22";
323 regulator-name = "VMEM_VDD_2.8V";
324 regulator-min-microvolt = <2800000>;
325 regulator-max-microvolt = <2800000>;
326 regulator-always-on;
327 regulator-mem-off;
328 };
329
330 ldo23_reg: ldo23 {
331 regulator-compatible = "LDO23";
332 regulator-name = "TSP_AVDD_3.3V";
333 regulator-min-microvolt = <3300000>;
334 regulator-max-microvolt = <3300000>;
335 regulator-mem-idle;
336 };
337
338 ldo24_reg: ldo24 {
339 regulator-compatible = "LDO24";
340 regulator-name = "TSP_VDD_1.8V";
341 regulator-min-microvolt = <1800000>;
342 regulator-max-microvolt = <1800000>;
343 regulator-mem-idle;
344 };
345
346 ldo25_reg: ldo25 {
347 regulator-compatible = "LDO25";
348 regulator-name = "LCD_VCC_3.3V";
349 regulator-min-microvolt = <2800000>;
350 regulator-max-microvolt = <2800000>;
351 regulator-mem-idle;
352 };
353
354 ldo26_reg: ldo26 {
355 regulator-compatible = "LDO26";
356 regulator-name = "MOTOR_VCC_3.0V";
357 regulator-min-microvolt = <3000000>;
358 regulator-max-microvolt = <3000000>;
359 regulator-mem-idle;
360 };
361
362 buck1_reg: buck1 {
363 regulator-compatible = "BUCK1";
364 regulator-name = "vdd_mif";
365 regulator-min-microvolt = <850000>;
366 regulator-max-microvolt = <1100000>;
367 regulator-always-on;
368 regulator-boot-on;
369 regulator-mem-off;
370 };
371
372 buck2_reg: buck2 {
373 regulator-compatible = "BUCK2";
374 regulator-name = "vdd_arm";
375 regulator-min-microvolt = <850000>;
376 regulator-max-microvolt = <1500000>;
377 regulator-always-on;
378 regulator-boot-on;
379 regulator-mem-off;
380 };
381
382 buck3_reg: buck3 {
383 regulator-compatible = "BUCK3";
384 regulator-name = "vdd_int";
385 regulator-min-microvolt = <850000>;
386 regulator-max-microvolt = <1150000>;
387 regulator-always-on;
388 regulator-boot-on;
389 regulator-mem-off;
390 };
391
392 buck4_reg: buck4 {
393 regulator-compatible = "BUCK4";
394 regulator-name = "vdd_g3d";
395 regulator-min-microvolt = <850000>;
396 regulator-max-microvolt = <1150000>;
397 regulator-boot-on;
398 regulator-mem-off;
399 };
400
401 buck5_reg: buck5 {
402 regulator-compatible = "BUCK5";
403 regulator-name = "VMEM_1.2V_AP";
404 regulator-min-microvolt = <1200000>;
405 regulator-max-microvolt = <1200000>;
406 regulator-always-on;
407 };
408
409 buck6_reg: buck6 {
410 regulator-compatible = "BUCK6";
411 regulator-name = "VCC_SUB_1.35V";
412 regulator-min-microvolt = <1350000>;
413 regulator-max-microvolt = <1350000>;
414 regulator-always-on;
415 };
416
417 buck7_reg: buck7 {
418 regulator-compatible = "BUCK7";
419 regulator-name = "VCC_SUB_2.0V";
420 regulator-min-microvolt = <2000000>;
421 regulator-max-microvolt = <2000000>;
422 regulator-always-on;
423 };
424
425 buck8_reg: buck8 {
426 regulator-compatible = "BUCK8";
427 regulator-name = "VMEM_VDDF_3.0V";
428 regulator-min-microvolt = <2850000>;
429 regulator-max-microvolt = <2850000>;
430 regulator-always-on;
431 regulator-mem-off;
432 };
433
434 buck9_reg: buck9 {
435 regulator-compatible = "BUCK9";
436 regulator-name = "CAM_ISP_CORE_1.2V";
437 regulator-min-microvolt = <1000000>;
438 regulator-max-microvolt = <1200000>;
439 regulator-mem-off;
440 };
441 };
442 };
443 };
444
445 sdhci@12510000 {
446 bus-width = <8>;
447 non-removable;
448 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus8>;
449 pinctrl-names = "default";
450 vmmc-supply = <&vemmc_reg>;
451 status = "okay";
452 };
453
454 serial@13800000 {
455 status = "okay";
456 };
457
458 serial@13810000 {
459 status = "okay";
460 };
461
462 serial@13820000 {
463 status = "okay";
464 };
465
466 serial@13830000 {
467 status = "okay";
468 };
469
470 i2c_ak8975: i2c-gpio-0 {
471 compatible = "i2c-gpio";
472 gpios = <&gpy2 4 0>, <&gpy2 5 0>;
473 i2c-gpio,delay-us = <2>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 status = "okay";
477
478 ak8975@0c {
479 compatible = "ak,ak8975";
480 reg = <0x0c>;
481 gpios = <&gpj0 7 0>;
482 };
483 };
484
485 spi_1: spi@13930000 {
486 pinctrl-names = "default";
487 pinctrl-0 = <&spi1_bus>;
488 status = "okay";
489
490 s5c73m3_spi: s5c73m3 {
491 compatible = "samsung,s5c73m3";
492 spi-max-frequency = <50000000>;
493 reg = <0>;
494 controller-data {
495 cs-gpio = <&gpb 5 0>;
496 samsung,spi-feedback-delay = <2>;
497 };
498 };
499 };
500
501 camera {
502 pinctrl-0 = <&cam_port_b_clk_active>;
503 pinctrl-names = "default";
504 status = "okay";
505
506 fimc_0: fimc@11800000 {
507 status = "okay";
508 };
509
510 fimc_1: fimc@11810000 {
511 status = "okay";
512 };
513
514 fimc_2: fimc@11820000 {
515 status = "okay";
516 };
517
518 fimc_3: fimc@11830000 {
519 status = "okay";
520 };
521
522 csis_1: csis@11890000 {
523 vddcore-supply = <&ldo8_reg>;
524 vddio-supply = <&ldo10_reg>;
525 clock-frequency = <160000000>;
526 status = "okay";
527
528 /* Camera D (4) MIPI CSI-2 (CSIS1) */
529 port@4 {
530 reg = <4>;
531 csis1_ep: endpoint {
532 remote-endpoint = <&is_s5k6a3_ep>;
533 data-lanes = <1>;
534 samsung,csis-hs-settle = <18>;
535 samsung,csis-wclk;
536 };
537 };
538 };
539
540 fimc_lite_0: fimc-lite@12390000 {
541 status = "okay";
542 };
543
544 fimc_lite_1: fimc-lite@123A0000 {
545 status = "okay";
546 };
547
548 fimc-is@12000000 {
549 pinctrl-0 = <&fimc_is_uart>;
550 pinctrl-names = "default";
551 status = "okay";
552
553 i2c1_isp: i2c-isp@12140000 {
554 pinctrl-0 = <&fimc_is_i2c1>;
555 pinctrl-names = "default";
556
557 s5k6a3@10 {
558 compatible = "samsung,s5k6a3";
559 reg = <0x10>;
560 svdda-supply = <&cam_io_reg>;
561 svddio-supply = <&ldo19_reg>;
562 clock-frequency = <24000000>;
563 /* CAM_B_CLKOUT */
564 clocks = <&clock_cam 1>;
565 clock-names = "mclk";
566 samsung,camclk-out = <1>;
567 gpios = <&gpm1 6 0>;
568
569 port {
570 is_s5k6a3_ep: endpoint {
571 remote-endpoint = <&csis1_ep>;
572 data-lanes = <1>;
573 };
574 };
575 };
576 };
577 };
578 };
579};
diff --git a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
index 704290f7c5c0..99b26df8dbc7 100644
--- a/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi
@@ -401,13 +401,26 @@
401 samsung,pin-drv = <0>; 401 samsung,pin-drv = <0>;
402 }; 402 };
403 403
404 cam_port_a: cam-port-a { 404 cam_port_a_io: cam-port-a-io {
405 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3", 405 samsung,pins = "gpj0-0", "gpj0-1", "gpj0-2", "gpj0-3",
406 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7", 406 "gpj0-4", "gpj0-5", "gpj0-6", "gpj0-7",
407 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-3", 407 "gpj1-0", "gpj1-1", "gpj1-2", "gpj1-4";
408 "gpj1-4";
409 samsung,pin-function = <2>; 408 samsung,pin-function = <2>;
410 samsung,pin-pud = <3>; 409 samsung,pin-pud = <0>;
410 samsung,pin-drv = <0>;
411 };
412
413 cam_port_a_clk_active: cam-port-a-clk-active {
414 samsung,pins = "gpj1-3";
415 samsung,pin-function = <2>;
416 samsung,pin-pud = <0>;
417 samsung,pin-drv = <3>;
418 };
419
420 cam_port_a_clk_idle: cam-port-a-clk-idle {
421 samsung,pins = "gpj1-3";
422 samsung,pin-function = <0>;
423 samsung,pin-pud = <1>;
411 samsung,pin-drv = <0>; 424 samsung,pin-drv = <0>;
412 }; 425 };
413 }; 426 };
@@ -778,16 +791,29 @@
778 samsung,pin-drv = <3>; 791 samsung,pin-drv = <3>;
779 }; 792 };
780 793
781 cam_port_b: cam-port-b { 794 cam_port_b_io: cam-port-b-io {
782 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3", 795 samsung,pins = "gpm0-0", "gpm0-1", "gpm0-2", "gpm0-3",
783 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7", 796 "gpm0-4", "gpm0-5", "gpm0-6", "gpm0-7",
784 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1", 797 "gpm1-0", "gpm1-1", "gpm2-0", "gpm2-1";
785 "gpm2-2";
786 samsung,pin-function = <3>; 798 samsung,pin-function = <3>;
787 samsung,pin-pud = <3>; 799 samsung,pin-pud = <3>;
788 samsung,pin-drv = <0>; 800 samsung,pin-drv = <0>;
789 }; 801 };
790 802
803 cam_port_b_clk_active: cam-port-b-clk-active {
804 samsung,pins = "gpm2-2";
805 samsung,pin-function = <3>;
806 samsung,pin-pud = <0>;
807 samsung,pin-drv = <3>;
808 };
809
810 cam_port_b_clk_idle: cam-port-b-clk-idle {
811 samsung,pins = "gpm2-2";
812 samsung,pin-function = <0>;
813 samsung,pin-pud = <1>;
814 samsung,pin-drv = <0>;
815 };
816
791 eint0: ext-int0 { 817 eint0: ext-int0 {
792 samsung,pins = "gpx0-0"; 818 samsung,pins = "gpx0-0";
793 samsung,pin-function = <0xf>; 819 samsung,pin-function = <0xf>;
@@ -822,6 +848,27 @@
822 samsung,pin-pud = <0>; 848 samsung,pin-pud = <0>;
823 samsung,pin-drv = <0>; 849 samsung,pin-drv = <0>;
824 }; 850 };
851
852 fimc_is_i2c0: fimc-is-i2c0 {
853 samsung,pins = "gpm4-0", "gpm4-1";
854 samsung,pin-function = <2>;
855 samsung,pin-pud = <0>;
856 samsung,pin-drv = <0>;
857 };
858
859 fimc_is_i2c1: fimc-is-i2c1 {
860 samsung,pins = "gpm4-2", "gpm4-3";
861 samsung,pin-function = <2>;
862 samsung,pin-pud = <0>;
863 samsung,pin-drv = <0>;
864 };
865
866 fimc_is_uart: fimc-is-uart {
867 samsung,pins = "gpm3-5", "gpm3-7";
868 samsung,pin-function = <3>;
869 samsung,pin-pud = <0>;
870 samsung,pin-drv = <0>;
871 };
825 }; 872 };
826 873
827 pinctrl@03860000 { 874 pinctrl@03860000 {
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index 01da194ba329..ad531fe6ab95 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -26,9 +26,16 @@
26 pinctrl1 = &pinctrl_1; 26 pinctrl1 = &pinctrl_1;
27 pinctrl2 = &pinctrl_2; 27 pinctrl2 = &pinctrl_2;
28 pinctrl3 = &pinctrl_3; 28 pinctrl3 = &pinctrl_3;
29 fimc-lite0 = &fimc_lite_0;
30 fimc-lite1 = &fimc_lite_1;
29 }; 31 };
30 32
31 clock: clock-controller@0x10030000 { 33 pd_isp: isp-power-domain@10023CA0 {
34 compatible = "samsung,exynos4210-pd";
35 reg = <0x10023CA0 0x20>;
36 };
37
38 clock: clock-controller@10030000 {
32 compatible = "samsung,exynos4412-clock"; 39 compatible = "samsung,exynos4412-clock";
33 reg = <0x10030000 0x20000>; 40 reg = <0x10030000 0x20000>;
34 #clock-cells = <1>; 41 #clock-cells = <1>;
@@ -73,4 +80,100 @@
73 clock-names = "sclk_fimg2d", "fimg2d"; 80 clock-names = "sclk_fimg2d", "fimg2d";
74 status = "disabled"; 81 status = "disabled";
75 }; 82 };
83
84 camera {
85 clocks = <&clock 132>, <&clock 133>, <&clock 351>, <&clock 352>;
86 clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
87
88 fimc_0: fimc@11800000 {
89 compatible = "samsung,exynos4212-fimc";
90 samsung,pix-limits = <4224 8192 1920 4224>;
91 samsung,mainscaler-ext;
92 samsung,isp-wb;
93 samsung,cam-if;
94 };
95
96 fimc_1: fimc@11810000 {
97 compatible = "samsung,exynos4212-fimc";
98 samsung,pix-limits = <4224 8192 1920 4224>;
99 samsung,mainscaler-ext;
100 samsung,isp-wb;
101 samsung,cam-if;
102 };
103
104 fimc_2: fimc@11820000 {
105 compatible = "samsung,exynos4212-fimc";
106 samsung,pix-limits = <4224 8192 1920 4224>;
107 samsung,mainscaler-ext;
108 samsung,isp-wb;
109 samsung,lcd-wb;
110 samsung,cam-if;
111 };
112
113 fimc_3: fimc@11830000 {
114 compatible = "samsung,exynos4212-fimc";
115 samsung,pix-limits = <1920 8192 1366 1920>;
116 samsung,rotators = <0>;
117 samsung,mainscaler-ext;
118 samsung,isp-wb;
119 samsung,lcd-wb;
120 };
121
122 fimc_lite_0: fimc-lite@12390000 {
123 compatible = "samsung,exynos4212-fimc-lite";
124 reg = <0x12390000 0x1000>;
125 interrupts = <0 105 0>;
126 samsung,power-domain = <&pd_isp>;
127 clocks = <&clock 353>;
128 clock-names = "flite";
129 status = "disabled";
130 };
131
132 fimc_lite_1: fimc-lite@123A0000 {
133 compatible = "samsung,exynos4212-fimc-lite";
134 reg = <0x123A0000 0x1000>;
135 interrupts = <0 106 0>;
136 samsung,power-domain = <&pd_isp>;
137 clocks = <&clock 354>;
138 clock-names = "flite";
139 status = "disabled";
140 };
141
142 fimc_is: fimc-is@12000000 {
143 compatible = "samsung,exynos4212-fimc-is", "simple-bus";
144 reg = <0x12000000 0x260000>;
145 interrupts = <0 90 0>, <0 95 0>;
146 samsung,power-domain = <&pd_isp>;
147 clocks = <&clock 353>, <&clock 354>, <&clock 355>,
148 <&clock 356>, <&clock 17>, <&clock 357>,
149 <&clock 358>, <&clock 359>, <&clock 360>,
150 <&clock 450>,<&clock 451>, <&clock 452>,
151 <&clock 453>, <&clock 176>, <&clock 13>,
152 <&clock 454>, <&clock 395>, <&clock 455>;
153 clock-names = "lite0", "lite1", "ppmuispx",
154 "ppmuispmx", "mpll", "isp",
155 "drc", "fd", "mcuisp",
156 "ispdiv0", "ispdiv1", "mcuispdiv0",
157 "mcuispdiv1", "uart", "aclk200",
158 "div_aclk200", "aclk400mcuisp",
159 "div_aclk400mcuisp";
160 #address-cells = <1>;
161 #size-cells = <1>;
162 ranges;
163 status = "disabled";
164
165 pmu {
166 reg = <0x10020000 0x3000>;
167 };
168
169 i2c1_isp: i2c-isp@12140000 {
170 compatible = "samsung,exynos4212-i2c-isp";
171 reg = <0x12140000 0x100>;
172 clocks = <&clock 370>;
173 clock-names = "i2c_isp";
174 #address-cells = <1>;
175 #size-cells = <0>;
176 };
177 };
178 };
76}; 179};
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index f65e124c04a6..074739d39e2d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
95 interrupts = <0 54 0>; 95 interrupts = <0 54 0>;
96 }; 96 };
97 97
98 rtc { 98 rtc@101E0000 {
99 compatible = "samsung,s3c6410-rtc"; 99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>; 100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>; 101 interrupts = <0 43 0>, <0 44 0>;
@@ -108,4 +108,23 @@
108 interrupts = <0 42 0>; 108 interrupts = <0 42 0>;
109 status = "disabled"; 109 status = "disabled";
110 }; 110 };
111
112 fimd@14400000 {
113 compatible = "samsung,exynos5250-fimd";
114 interrupt-parent = <&combiner>;
115 reg = <0x14400000 0x40000>;
116 interrupt-names = "fifo", "vsync", "lcd_sys";
117 interrupts = <18 4>, <18 5>, <18 6>;
118 status = "disabled";
119 };
120
121 dp-controller@145B0000 {
122 compatible = "samsung,exynos5-dp";
123 reg = <0x145B0000 0x1000>;
124 interrupts = <10 3>;
125 interrupt-parent = <&combiner>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128 status = "disabled";
129 };
111}; 130};
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index abc7272c7afd..cee55fa33731 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -11,6 +11,7 @@
11 11
12/dts-v1/; 12/dts-v1/;
13#include "exynos5250.dtsi" 13#include "exynos5250.dtsi"
14#include <dt-bindings/interrupt-controller/irq.h>
14 15
15/ { 16/ {
16 model = "Insignal Arndale evaluation board based on EXYNOS5250"; 17 model = "Insignal Arndale evaluation board based on EXYNOS5250";
@@ -37,6 +38,28 @@
37 s5m8767_pmic@66 { 38 s5m8767_pmic@66 {
38 compatible = "samsung,s5m8767-pmic"; 39 compatible = "samsung,s5m8767-pmic";
39 reg = <0x66>; 40 reg = <0x66>;
41 interrupt-parent = <&gpx3>;
42 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
43
44 vinb1-supply = <&main_dc_reg>;
45 vinb2-supply = <&main_dc_reg>;
46 vinb3-supply = <&main_dc_reg>;
47 vinb4-supply = <&main_dc_reg>;
48 vinb5-supply = <&main_dc_reg>;
49 vinb6-supply = <&main_dc_reg>;
50 vinb7-supply = <&main_dc_reg>;
51 vinb8-supply = <&main_dc_reg>;
52 vinb9-supply = <&main_dc_reg>;
53
54 vinl1-supply = <&buck7_reg>;
55 vinl2-supply = <&buck7_reg>;
56 vinl3-supply = <&buck7_reg>;
57 vinl4-supply = <&main_dc_reg>;
58 vinl5-supply = <&main_dc_reg>;
59 vinl6-supply = <&main_dc_reg>;
60 vinl7-supply = <&main_dc_reg>;
61 vinl8-supply = <&buck8_reg>;
62 vinl9-supply = <&buck8_reg>;
40 63
41 s5m8767,pmic-buck2-dvs-voltage = <1300000>; 64 s5m8767,pmic-buck2-dvs-voltage = <1300000>;
42 s5m8767,pmic-buck3-dvs-voltage = <1100000>; 65 s5m8767,pmic-buck3-dvs-voltage = <1100000>;
@@ -276,6 +299,16 @@
276 op_mode = <1>; 299 op_mode = <1>;
277 }; 300 };
278 301
302 buck7_reg: BUCK7 {
303 regulator-name = "PVDD_BUCK7";
304 regulator-always-on;
305 };
306
307 buck8_reg: BUCK8 {
308 regulator-name = "PVDD_BUCK8";
309 regulator-always-on;
310 };
311
279 buck9_reg: BUCK9 { 312 buck9_reg: BUCK9 {
280 regulator-name = "VDD_33_OFF_EXT1"; 313 regulator-name = "VDD_33_OFF_EXT1";
281 regulator-min-microvolt = <750000>; 314 regulator-min-microvolt = <750000>;
@@ -295,7 +328,22 @@
295 }; 328 };
296 329
297 i2c@12C90000 { 330 i2c@12C90000 {
298 status = "disabled"; 331 wm1811a@1a {
332 compatible = "wlf,wm1811";
333 reg = <0x1a>;
334
335 AVDD2-supply = <&main_dc_reg>;
336 CPVDD-supply = <&main_dc_reg>;
337 DBVDD1-supply = <&main_dc_reg>;
338 DBVDD2-supply = <&main_dc_reg>;
339 DBVDD3-supply = <&main_dc_reg>;
340 LDO1VDD-supply = <&main_dc_reg>;
341 SPKVDD1-supply = <&main_dc_reg>;
342 SPKVDD2-supply = <&main_dc_reg>;
343
344 wlf,ldo1ena = <&gpb0 0 0>;
345 wlf,ldo2ena = <&gpb0 1 0>;
346 };
299 }; 347 };
300 348
301 i2c@12CA0000 { 349 i2c@12CA0000 {
@@ -429,18 +477,29 @@
429 vdd-supply = <&ldo8_reg>; 477 vdd-supply = <&ldo8_reg>;
430 }; 478 };
431 479
432 mmc_reg: voltage-regulator { 480 regulators {
433 compatible = "regulator-fixed"; 481 compatible = "simple-bus";
434 regulator-name = "VDD_33ON_2.8V"; 482 #address-cells = <1>;
435 regulator-min-microvolt = <2800000>; 483 #size-cells = <0>;
436 regulator-max-microvolt = <2800000>; 484
437 gpio = <&gpx1 1 1>; 485 main_dc_reg: fixedregulator@1 {
438 enable-active-high; 486 compatible = "regulator-fixed";
439 }; 487 regulator-name = "MAIN_DC";
488 };
440 489
441 reg_hdmi_en: fixedregulator@0 { 490 mmc_reg: voltage-regulator {
442 compatible = "regulator-fixed"; 491 compatible = "regulator-fixed";
443 regulator-name = "hdmi-en"; 492 regulator-name = "VDD_33ON_2.8V";
493 regulator-min-microvolt = <2800000>;
494 regulator-max-microvolt = <2800000>;
495 gpio = <&gpx1 1 1>;
496 enable-active-high;
497 };
498
499 reg_hdmi_en: fixedregulator@0 {
500 compatible = "regulator-fixed";
501 regulator-name = "hdmi-en";
502 };
444 }; 503 };
445 504
446 fixed-rate-clocks { 505 fixed-rate-clocks {
@@ -450,16 +509,18 @@
450 }; 509 };
451 }; 510 };
452 511
453 dp-controller { 512 dp-controller@145B0000 {
454 samsung,color-space = <0>; 513 samsung,color-space = <0>;
455 samsung,dynamic-range = <0>; 514 samsung,dynamic-range = <0>;
456 samsung,ycbcr-coeff = <0>; 515 samsung,ycbcr-coeff = <0>;
457 samsung,color-depth = <1>; 516 samsung,color-depth = <1>;
458 samsung,link-rate = <0x0a>; 517 samsung,link-rate = <0x0a>;
459 samsung,lane-count = <4>; 518 samsung,lane-count = <4>;
519 status = "okay";
460 }; 520 };
461 521
462 fimd: fimd@14400000 { 522 fimd: fimd@14400000 {
523 status = "okay";
463 display-timings { 524 display-timings {
464 native-mode = <&timing0>; 525 native-mode = <&timing0>;
465 timing0: timing@0 { 526 timing0: timing@0 {
@@ -477,7 +538,21 @@
477 }; 538 };
478 }; 539 };
479 540
480 rtc { 541 usb_hub_bus {
481 status = "okay"; 542 compatible = "simple-bus";
543 #address-cells = <1>;
544 #size-cells = <0>;
545
546 // SMSC USB3503 connected in hardware only mode as a PHY
547 usb_hub: usb_hub {
548 compatible = "smsc,usb3503a";
549
550 reset-gpios = <&gpx3 5 1>;
551 connect-gpios = <&gpd1 7 1>;
552 };
553 };
554
555 usb@12110000 {
556 usb-phy = <&usb2_phy>;
482 }; 557 };
483}; 558};
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49f18c24a576..2538b329f2ce 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -250,7 +250,7 @@
250 samsung,vbus-gpio = <&gpx2 6 0>; 250 samsung,vbus-gpio = <&gpx2 6 0>;
251 }; 251 };
252 252
253 dp-controller { 253 dp-controller@145B0000 {
254 samsung,color-space = <0>; 254 samsung,color-space = <0>;
255 samsung,dynamic-range = <0>; 255 samsung,dynamic-range = <0>;
256 samsung,ycbcr-coeff = <0>; 256 samsung,ycbcr-coeff = <0>;
@@ -260,21 +260,25 @@
260 260
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&dp_hpd>; 262 pinctrl-0 = <&dp_hpd>;
263 status = "okay";
263 }; 264 };
264 265
265 display-timings { 266 fimd@14400000 {
266 native-mode = <&timing0>; 267 status = "okay";
267 timing0: timing@0 { 268 display-timings {
268 /* 1280x800 */ 269 native-mode = <&timing0>;
269 clock-frequency = <50000>; 270 timing0: timing@0 {
270 hactive = <1280>; 271 /* 1280x800 */
271 vactive = <800>; 272 clock-frequency = <50000>;
272 hfront-porch = <4>; 273 hactive = <1280>;
273 hback-porch = <4>; 274 vactive = <800>;
274 hsync-len = <4>; 275 hfront-porch = <4>;
275 vback-porch = <4>; 276 hback-porch = <4>;
276 vfront-porch = <4>; 277 hsync-len = <4>;
277 vsync-len = <4>; 278 vback-porch = <4>;
279 vfront-porch = <4>;
280 vsync-len = <4>;
281 };
278 }; 282 };
279 }; 283 };
280 284
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index e79331dba12d..fd711e245e8d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,10 +171,6 @@
171 }; 171 };
172 }; 172 };
173 173
174 rtc {
175 status = "okay";
176 };
177
178 /* 174 /*
179 * On Snow we've got SIP WiFi and so can keep drive strengths low to 175 * On Snow we've got SIP WiFi and so can keep drive strengths low to
180 * reduce EMI. 176 * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 376090f07231..7d7cc777ff7b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -68,17 +68,17 @@
68 }; 68 };
69 }; 69 };
70 70
71 pd_gsc: gsc-power-domain@0x10044000 { 71 pd_gsc: gsc-power-domain@10044000 {
72 compatible = "samsung,exynos4210-pd"; 72 compatible = "samsung,exynos4210-pd";
73 reg = <0x10044000 0x20>; 73 reg = <0x10044000 0x20>;
74 }; 74 };
75 75
76 pd_mfc: mfc-power-domain@0x10044040 { 76 pd_mfc: mfc-power-domain@10044040 {
77 compatible = "samsung,exynos4210-pd"; 77 compatible = "samsung,exynos4210-pd";
78 reg = <0x10044040 0x20>; 78 reg = <0x10044040 0x20>;
79 }; 79 };
80 80
81 clock: clock-controller@0x10010000 { 81 clock: clock-controller@10010000 {
82 compatible = "samsung,exynos5250-clock"; 82 compatible = "samsung,exynos5250-clock";
83 reg = <0x10010000 0x30000>; 83 reg = <0x10010000 0x30000>;
84 #clock-cells = <1>; 84 #clock-cells = <1>;
@@ -163,16 +163,27 @@
163 clock-names = "watchdog"; 163 clock-names = "watchdog";
164 }; 164 };
165 165
166 g2d@10850000 {
167 compatible = "samsung,exynos5250-g2d";
168 reg = <0x10850000 0x1000>;
169 interrupts = <0 91 0>;
170 clocks = <&clock 345>;
171 clock-names = "fimg2d";
172 };
173
166 codec@11000000 { 174 codec@11000000 {
167 compatible = "samsung,mfc-v6"; 175 compatible = "samsung,mfc-v6";
168 reg = <0x11000000 0x10000>; 176 reg = <0x11000000 0x10000>;
169 interrupts = <0 96 0>; 177 interrupts = <0 96 0>;
170 samsung,power-domain = <&pd_mfc>; 178 samsung,power-domain = <&pd_mfc>;
179 clocks = <&clock 266>;
180 clock-names = "mfc";
171 }; 181 };
172 182
173 rtc { 183 rtc@101E0000 {
174 clocks = <&clock 337>; 184 clocks = <&clock 337>;
175 clock-names = "rtc"; 185 clock-names = "rtc";
186 status = "okay";
176 }; 187 };
177 188
178 tmu@10060000 { 189 tmu@10060000 {
@@ -559,7 +570,7 @@
559 }; 570 };
560 }; 571 };
561 572
562 gsc_0: gsc@0x13e00000 { 573 gsc_0: gsc@13e00000 {
563 compatible = "samsung,exynos5-gsc"; 574 compatible = "samsung,exynos5-gsc";
564 reg = <0x13e00000 0x1000>; 575 reg = <0x13e00000 0x1000>;
565 interrupts = <0 85 0>; 576 interrupts = <0 85 0>;
@@ -568,7 +579,7 @@
568 clock-names = "gscl"; 579 clock-names = "gscl";
569 }; 580 };
570 581
571 gsc_1: gsc@0x13e10000 { 582 gsc_1: gsc@13e10000 {
572 compatible = "samsung,exynos5-gsc"; 583 compatible = "samsung,exynos5-gsc";
573 reg = <0x13e10000 0x1000>; 584 reg = <0x13e10000 0x1000>;
574 interrupts = <0 86 0>; 585 interrupts = <0 86 0>;
@@ -577,7 +588,7 @@
577 clock-names = "gscl"; 588 clock-names = "gscl";
578 }; 589 };
579 590
580 gsc_2: gsc@0x13e20000 { 591 gsc_2: gsc@13e20000 {
581 compatible = "samsung,exynos5-gsc"; 592 compatible = "samsung,exynos5-gsc";
582 reg = <0x13e20000 0x1000>; 593 reg = <0x13e20000 0x1000>;
583 interrupts = <0 87 0>; 594 interrupts = <0 87 0>;
@@ -586,7 +597,7 @@
586 clock-names = "gscl"; 597 clock-names = "gscl";
587 }; 598 };
588 599
589 gsc_3: gsc@0x13e30000 { 600 gsc_3: gsc@13e30000 {
590 compatible = "samsung,exynos5-gsc"; 601 compatible = "samsung,exynos5-gsc";
591 reg = <0x13e30000 0x1000>; 602 reg = <0x13e30000 0x1000>;
592 interrupts = <0 88 0>; 603 interrupts = <0 88 0>;
@@ -611,29 +622,32 @@
611 interrupts = <0 94 0>; 622 interrupts = <0 94 0>;
612 }; 623 };
613 624
614 dp-controller { 625 dp_phy: video-phy@10040720 {
615 compatible = "samsung,exynos5-dp"; 626 compatible = "samsung,exynos5250-dp-video-phy";
616 reg = <0x145b0000 0x1000>; 627 reg = <0x10040720 4>;
617 interrupts = <10 3>; 628 #phy-cells = <0>;
618 interrupt-parent = <&combiner>; 629 };
630
631 dp-controller@145B0000 {
619 clocks = <&clock 342>; 632 clocks = <&clock 342>;
620 clock-names = "dp"; 633 clock-names = "dp";
621 #address-cells = <1>; 634 phys = <&dp_phy>;
622 #size-cells = <0>; 635 phy-names = "dp";
623
624 dptx-phy {
625 reg = <0x10040720>;
626 samsung,enable-mask = <1>;
627 };
628 }; 636 };
629 637
630 fimd { 638 fimd@14400000 {
631 compatible = "samsung,exynos5250-fimd";
632 interrupt-parent = <&combiner>;
633 reg = <0x14400000 0x40000>;
634 interrupt-names = "fifo", "vsync", "lcd_sys";
635 interrupts = <18 4>, <18 5>, <18 6>;
636 clocks = <&clock 133>, <&clock 339>; 639 clocks = <&clock 133>, <&clock 339>;
637 clock-names = "sclk_fimd", "fimd"; 640 clock-names = "sclk_fimd", "fimd";
638 }; 641 };
642
643 adc: adc@12D10000 {
644 compatible = "samsung,exynos-adc-v1";
645 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
646 interrupts = <0 106 0>;
647 clocks = <&clock 303>;
648 clock-names = "adc";
649 #io-channel-cells = <1>;
650 io-channel-ranges;
651 status = "disabled";
652 };
639}; 653};
diff --git a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
index 5848c425ae4d..e695aba5f73c 100644
--- a/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
+++ b/arch/arm/boot/dts/exynos5420-pinctrl.dtsi
@@ -59,6 +59,13 @@
59 interrupt-controller; 59 interrupt-controller;
60 #interrupt-cells = <2>; 60 #interrupt-cells = <2>;
61 }; 61 };
62
63 dp_hpd: dp_hpd {
64 samsung,pins = "gpx0-7";
65 samsung,pin-function = <3>;
66 samsung,pin-pud = <0>;
67 samaung,pin-drv = <0>;
68 };
62 }; 69 };
63 70
64 pinctrl@13410000 { 71 pinctrl@13410000 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index 08607df6a180..bafba25ba7c2 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -30,4 +30,35 @@
30 clock-frequency = <24000000>; 30 clock-frequency = <24000000>;
31 }; 31 };
32 }; 32 };
33
34 dp-controller@145B0000 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&dp_hpd>;
37 samsung,color-space = <0>;
38 samsung,dynamic-range = <0>;
39 samsung,ycbcr-coeff = <0>;
40 samsung,color-depth = <1>;
41 samsung,link-rate = <0x0a>;
42 samsung,lane-count = <4>;
43 status = "okay";
44 };
45
46 fimd@14400000 {
47 status = "okay";
48 display-timings {
49 native-mode = <&timing0>;
50 timing0: timing@0 {
51 clock-frequency = <50000>;
52 hactive = <2560>;
53 vactive = <1600>;
54 hfront-porch = <48>;
55 hback-porch = <80>;
56 hsync-len = <32>;
57 vback-porch = <16>;
58 vfront-porch = <8>;
59 vsync-len = <6>;
60 };
61 };
62 };
63
33}; 64};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 8c54c4b74f0e..d537cd704e19 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -14,7 +14,10 @@
14 */ 14 */
15 15
16#include "exynos5.dtsi" 16#include "exynos5.dtsi"
17/include/ "exynos5420-pinctrl.dtsi" 17#include "exynos5420-pinctrl.dtsi"
18
19#include <dt-bindings/clk/exynos-audss-clk.h>
20
18/ { 21/ {
19 compatible = "samsung,exynos5420"; 22 compatible = "samsung,exynos5420";
20 23
@@ -59,12 +62,28 @@
59 }; 62 };
60 }; 63 };
61 64
62 clock: clock-controller@0x10010000 { 65 clock: clock-controller@10010000 {
63 compatible = "samsung,exynos5420-clock"; 66 compatible = "samsung,exynos5420-clock";
64 reg = <0x10010000 0x30000>; 67 reg = <0x10010000 0x30000>;
65 #clock-cells = <1>; 68 #clock-cells = <1>;
66 }; 69 };
67 70
71 clock_audss: audss-clock-controller@3810000 {
72 compatible = "samsung,exynos5420-audss-clock";
73 reg = <0x03810000 0x0C>;
74 #clock-cells = <1>;
75 clocks = <&clock 148>;
76 clock-names = "sclk_audio";
77 };
78
79 codec@11000000 {
80 compatible = "samsung,mfc-v7";
81 reg = <0x11000000 0x10000>;
82 interrupts = <0 96 0>;
83 clocks = <&clock 401>;
84 clock-names = "mfc";
85 };
86
68 mct@101C0000 { 87 mct@101C0000 {
69 compatible = "samsung,exynos4210-mct"; 88 compatible = "samsung,exynos4210-mct";
70 reg = <0x101C0000 0x800>; 89 reg = <0x101C0000 0x800>;
@@ -90,6 +109,41 @@
90 }; 109 };
91 }; 110 };
92 111
112 gsc_pd: power-domain@10044000 {
113 compatible = "samsung,exynos4210-pd";
114 reg = <0x10044000 0x20>;
115 };
116
117 isp_pd: power-domain@10044020 {
118 compatible = "samsung,exynos4210-pd";
119 reg = <0x10044020 0x20>;
120 };
121
122 mfc_pd: power-domain@10044060 {
123 compatible = "samsung,exynos4210-pd";
124 reg = <0x10044060 0x20>;
125 };
126
127 disp_pd: power-domain@100440C0 {
128 compatible = "samsung,exynos4210-pd";
129 reg = <0x100440C0 0x20>;
130 };
131
132 mau_pd: power-domain@100440E0 {
133 compatible = "samsung,exynos4210-pd";
134 reg = <0x100440E0 0x20>;
135 };
136
137 g2d_pd: power-domain@10044100 {
138 compatible = "samsung,exynos4210-pd";
139 reg = <0x10044100 0x20>;
140 };
141
142 msc_pd: power-domain@10044120 {
143 compatible = "samsung,exynos4210-pd";
144 reg = <0x10044120 0x20>;
145 };
146
93 pinctrl_0: pinctrl@13400000 { 147 pinctrl_0: pinctrl@13400000 {
94 compatible = "samsung,exynos5420-pinctrl"; 148 compatible = "samsung,exynos5420-pinctrl";
95 reg = <0x13400000 0x1000>; 149 reg = <0x13400000 0x1000>;
@@ -126,6 +180,12 @@
126 interrupts = <0 47 0>; 180 interrupts = <0 47 0>;
127 }; 181 };
128 182
183 rtc@101E0000 {
184 clocks = <&clock 317>;
185 clock-names = "rtc";
186 status = "okay";
187 };
188
129 serial@12C00000 { 189 serial@12C00000 {
130 clocks = <&clock 257>, <&clock 128>; 190 clocks = <&clock 257>, <&clock 128>;
131 clock-names = "uart", "clk_uart_baud0"; 191 clock-names = "uart", "clk_uart_baud0";
@@ -145,4 +205,34 @@
145 clocks = <&clock 260>, <&clock 131>; 205 clocks = <&clock 260>, <&clock 131>;
146 clock-names = "uart", "clk_uart_baud0"; 206 clock-names = "uart", "clk_uart_baud0";
147 }; 207 };
208
209 dp_phy: video-phy@10040728 {
210 compatible = "samsung,exynos5250-dp-video-phy";
211 reg = <0x10040728 4>;
212 #phy-cells = <0>;
213 };
214
215 dp-controller@145B0000 {
216 clocks = <&clock 412>;
217 clock-names = "dp";
218 phys = <&dp_phy>;
219 phy-names = "dp";
220 };
221
222 fimd@14400000 {
223 samsung,power-domain = <&disp_pd>;
224 clocks = <&clock 147>, <&clock 421>;
225 clock-names = "sclk_fimd", "fimd";
226 };
227
228 adc: adc@12D10000 {
229 compatible = "samsung,exynos-adc-v2";
230 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
231 interrupts = <0 106 0>;
232 clocks = <&clock 270>;
233 clock-names = "adc";
234 #io-channel-cells = <1>;
235 io-channel-ranges;
236 status = "disabled";
237 };
148}; 238};
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 586134e2a382..5d6cf4965d6e 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -18,9 +18,12 @@
18 18
19 aliases { 19 aliases {
20 spi0 = &spi_0; 20 spi0 = &spi_0;
21 tmuctrl0 = &tmuctrl_0;
22 tmuctrl1 = &tmuctrl_1;
23 tmuctrl2 = &tmuctrl_2;
21 }; 24 };
22 25
23 clock: clock-controller@0x160000 { 26 clock: clock-controller@160000 {
24 compatible = "samsung,exynos5440-clock"; 27 compatible = "samsung,exynos5440-clock";
25 reg = <0x160000 0x1000>; 28 reg = <0x160000 0x1000>;
26 #clock-cells = <1>; 29 #clock-cells = <1>;
@@ -207,6 +210,30 @@
207 clock-names = "rtc"; 210 clock-names = "rtc";
208 }; 211 };
209 212
213 tmuctrl_0: tmuctrl@160118 {
214 compatible = "samsung,exynos5440-tmu";
215 reg = <0x160118 0x230>, <0x160368 0x10>;
216 interrupts = <0 58 0>;
217 clocks = <&clock 21>;
218 clock-names = "tmu_apbif";
219 };
220
221 tmuctrl_1: tmuctrl@16011C {
222 compatible = "samsung,exynos5440-tmu";
223 reg = <0x16011C 0x230>, <0x160368 0x10>;
224 interrupts = <0 58 0>;
225 clocks = <&clock 21>;
226 clock-names = "tmu_apbif";
227 };
228
229 tmuctrl_2: tmuctrl@160120 {
230 compatible = "samsung,exynos5440-tmu";
231 reg = <0x160120 0x230>, <0x160368 0x10>;
232 interrupts = <0 58 0>;
233 clocks = <&clock 21>;
234 clock-names = "tmu_apbif";
235 };
236
210 sata@210000 { 237 sata@210000 {
211 compatible = "snps,exynos5440-ahci"; 238 compatible = "snps,exynos5440-ahci";
212 reg = <0x210000 0x10000>; 239 reg = <0x210000 0x10000>;
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index da0588a04131..185c7c01102a 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -90,6 +90,11 @@
90 }; 90 };
91 91
92 apbx@80040000 { 92 apbx@80040000 {
93 lradc@80050000 {
94 status = "okay";
95 fsl,lradc-touchscreen-wires = <4>;
96 };
97
93 pwm: pwm@80064000 { 98 pwm: pwm@80064000 {
94 pinctrl-names = "default"; 99 pinctrl-names = "default";
95 pinctrl-0 = <&pwm2_pins_a>; 100 pinctrl-0 = <&pwm2_pins_a>;
@@ -107,6 +112,16 @@
107 pinctrl-0 = <&duart_pins_a>; 112 pinctrl-0 = <&duart_pins_a>;
108 status = "okay"; 113 status = "okay";
109 }; 114 };
115
116 usbphy0: usbphy@8007c000 {
117 status = "okay";
118 };
119 };
120 };
121
122 ahb@80080000 {
123 usb0: usb@80080000 {
124 status = "okay";
110 }; 125 };
111 }; 126 };
112 127
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
index d107c4af321f..fc766ae12e24 100644
--- a/arch/arm/boot/dts/imx23-olinuxino.dts
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -69,6 +69,10 @@
69 }; 69 };
70 70
71 apbx@80040000 { 71 apbx@80040000 {
72 lradc@80050000 {
73 status = "okay";
74 };
75
72 duart: serial@80070000 { 76 duart: serial@80070000 {
73 pinctrl-names = "default"; 77 pinctrl-names = "default";
74 pinctrl-0 = <&duart_pins_a>; 78 pinctrl-0 = <&duart_pins_a>;
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 587ceef81e45..28b5ce289662 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -20,6 +20,8 @@
20 gpio2 = &gpio2; 20 gpio2 = &gpio2;
21 serial0 = &auart0; 21 serial0 = &auart0;
22 serial1 = &auart1; 22 serial1 = &auart1;
23 spi0 = &ssp0;
24 spi1 = &ssp1;
23 }; 25 };
24 26
25 cpus { 27 cpus {
@@ -76,23 +78,21 @@
76 #size-cells = <1>; 78 #size-cells = <1>;
77 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; 79 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
78 reg-names = "gpmi-nand", "bch"; 80 reg-names = "gpmi-nand", "bch";
79 interrupts = <13>, <56>; 81 interrupts = <56>;
80 interrupt-names = "gpmi-dma", "bch"; 82 interrupt-names = "bch";
81 clocks = <&clks 34>; 83 clocks = <&clks 34>;
82 clock-names = "gpmi_io"; 84 clock-names = "gpmi_io";
83 dmas = <&dma_apbh 4>; 85 dmas = <&dma_apbh 4>;
84 dma-names = "rx-tx"; 86 dma-names = "rx-tx";
85 fsl,gpmi-dma-channel = <4>;
86 status = "disabled"; 87 status = "disabled";
87 }; 88 };
88 89
89 ssp0: ssp@80010000 { 90 ssp0: ssp@80010000 {
90 reg = <0x80010000 0x2000>; 91 reg = <0x80010000 0x2000>;
91 interrupts = <15 14>; 92 interrupts = <15>;
92 clocks = <&clks 33>; 93 clocks = <&clks 33>;
93 dmas = <&dma_apbh 1>; 94 dmas = <&dma_apbh 1>;
94 dma-names = "rx-tx"; 95 dma-names = "rx-tx";
95 fsl,ssp-dma-channel = <1>;
96 status = "disabled"; 96 status = "disabled";
97 }; 97 };
98 98
@@ -366,11 +366,10 @@
366 366
367 ssp1: ssp@80034000 { 367 ssp1: ssp@80034000 {
368 reg = <0x80034000 0x2000>; 368 reg = <0x80034000 0x2000>;
369 interrupts = <2 20>; 369 interrupts = <2>;
370 clocks = <&clks 33>; 370 clocks = <&clks 33>;
371 dmas = <&dma_apbh 2>; 371 dmas = <&dma_apbh 2>;
372 dma-names = "rx-tx"; 372 dma-names = "rx-tx";
373 fsl,ssp-dma-channel = <2>;
374 status = "disabled"; 373 status = "disabled";
375 }; 374 };
376 375
@@ -472,7 +471,7 @@
472 auart0: serial@8006c000 { 471 auart0: serial@8006c000 {
473 compatible = "fsl,imx23-auart"; 472 compatible = "fsl,imx23-auart";
474 reg = <0x8006c000 0x2000>; 473 reg = <0x8006c000 0x2000>;
475 interrupts = <24 25 23>; 474 interrupts = <24>;
476 clocks = <&clks 32>; 475 clocks = <&clks 32>;
477 dmas = <&dma_apbx 6>, <&dma_apbx 7>; 476 dmas = <&dma_apbx 6>, <&dma_apbx 7>;
478 dma-names = "rx", "tx"; 477 dma-names = "rx", "tx";
@@ -482,7 +481,7 @@
482 auart1: serial@8006e000 { 481 auart1: serial@8006e000 {
483 compatible = "fsl,imx23-auart"; 482 compatible = "fsl,imx23-auart";
484 reg = <0x8006e000 0x2000>; 483 reg = <0x8006e000 0x2000>;
485 interrupts = <59 60 58>; 484 interrupts = <59>;
486 clocks = <&clks 32>; 485 clocks = <&clks 32>;
487 dmas = <&dma_apbx 8>, <&dma_apbx 9>; 486 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
488 dma-names = "rx", "tx"; 487 dma-names = "rx", "tx";
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 701153992c69..737ed5da8f71 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -13,19 +13,35 @@
13 13
14/ { 14/ {
15 aliases { 15 aliases {
16 gpio0 = &gpio1;
17 gpio1 = &gpio2;
18 gpio2 = &gpio3;
19 gpio3 = &gpio4;
20 i2c0 = &i2c1;
21 i2c1 = &i2c2;
22 i2c2 = &i2c3;
16 serial0 = &uart1; 23 serial0 = &uart1;
17 serial1 = &uart2; 24 serial1 = &uart2;
18 serial2 = &uart3; 25 serial2 = &uart3;
19 serial3 = &uart4; 26 serial3 = &uart4;
20 serial4 = &uart5; 27 serial4 = &uart5;
21 gpio0 = &gpio1; 28 spi0 = &spi1;
22 gpio1 = &gpio2; 29 spi1 = &spi2;
23 gpio2 = &gpio3; 30 spi2 = &spi3;
24 gpio3 = &gpio4;
25 usb0 = &usbotg; 31 usb0 = &usbotg;
26 usb1 = &usbhost1; 32 usb1 = &usbhost1;
27 }; 33 };
28 34
35 cpus {
36 #address-cells = <0>;
37 #size-cells = <0>;
38
39 cpu {
40 compatible = "arm,arm926ej-s";
41 device_type = "cpu";
42 };
43 };
44
29 asic: asic-interrupt-controller@68000000 { 45 asic: asic-interrupt-controller@68000000 {
30 compatible = "fsl,imx25-asic", "fsl,avic"; 46 compatible = "fsl,imx25-asic", "fsl,avic";
31 interrupt-controller; 47 interrupt-controller;
@@ -377,7 +393,8 @@
377 status = "disabled"; 393 status = "disabled";
378 }; 394 };
379 395
380 lcdc@53fbc000 { 396 lcdc: lcdc@53fbc000 {
397 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
381 reg = <0x53fbc000 0x4000>; 398 reg = <0x53fbc000 0x4000>;
382 interrupts = <39>; 399 interrupts = <39>;
383 clocks = <&clks 103>, <&clks 66>, <&clks 49>; 400 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
@@ -424,6 +441,7 @@
424 reg = <0x53fd4000 0x4000>; 441 reg = <0x53fd4000 0x4000>;
425 clocks = <&clks 112>, <&clks 68>; 442 clocks = <&clks 112>, <&clks 68>;
426 clock-names = "ipg", "ahb"; 443 clock-names = "ipg", "ahb";
444 #dma-cells = <3>;
427 interrupts = <34>; 445 interrupts = <34>;
428 }; 446 };
429 447
@@ -444,6 +462,13 @@
444 interrupts = <26>; 462 interrupts = <26>;
445 }; 463 };
446 464
465 iim: iim@53ff0000 {
466 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
467 reg = <0x53ff0000 0x4000>;
468 interrupts = <19>;
469 clocks = <&clks 99>;
470 };
471
447 usbphy1: usbphy@1 { 472 usbphy1: usbphy@1 {
448 compatible = "nop-usbphy"; 473 compatible = "nop-usbphy";
449 status = "disabled"; 474 status = "disabled";
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index 66b8e1c1b0be..2a377ca1881a 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -53,6 +53,11 @@
53&i2c1 { 53&i2c1 {
54 clock-frequency = <400000>; 54 clock-frequency = <400000>;
55 status = "okay"; 55 status = "okay";
56
57 rtc@68 {
58 compatible = "dallas,ds1374";
59 reg = <0x68>;
60 };
56}; 61};
57 62
58&i2c2 { 63&i2c2 {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
new file mode 100644
index 000000000000..5a31c776513f
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -0,0 +1,93 @@
1/*
2 * Copyright 2012 Markus Pargmann, Pengutronix
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx27-phytec-phycard-s-som.dts"
13
14/ {
15 model = "Phytec pca100 rapid development kit";
16 compatible = "phytec,imx27-pca100-rdk", "phytec,imx27-pca100", "fsl,imx27";
17
18 display: display {
19 model = "Primeview-PD050VL1";
20 native-mode = <&timing0>;
21 bits-per-pixel = <16>; /* non-standard but required */
22 fsl,pcr = <0xf0c88080>; /* non-standard but required */
23 display-timings {
24 timing0: 640x480 {
25 hactive = <640>;
26 vactive = <480>;
27 hback-porch = <112>;
28 hfront-porch = <36>;
29 hsync-len = <32>;
30 vback-porch = <33>;
31 vfront-porch = <33>;
32 vsync-len = <2>;
33 clock-frequency = <25000000>;
34 };
35 };
36 };
37
38 regulators {
39 compatible = "simple-bus";
40
41 reg_3v3: 3v3 {
42 compatible = "regulator-fixed";
43 regulator-name = "3V3";
44 regulator-min-microvolt = <3300000>;
45 regulator-max-microvolt = <3300000>;
46 regulator-always-on;
47 };
48 };
49};
50
51&fb {
52 display = <&display>;
53 status = "okay";
54};
55
56&i2c1 {
57 status = "okay";
58
59 rtc@51 {
60 compatible = "nxp,pcf8563";
61 reg = <0x51>;
62 };
63
64 adc@64 {
65 compatible = "maxim,max1037";
66 vcc-supply = <&reg_3v3>;
67 reg = <0x64>;
68 };
69};
70
71&owire {
72 status = "okay";
73};
74
75&sdhci2 {
76 cd-gpios = <&gpio3 29 0>;
77 status = "okay";
78};
79
80&uart1 {
81 fsl,uart-has-rtscts;
82 status = "okay";
83};
84
85&uart2 {
86 fsl,uart-has-rtscts;
87 status = "okay";
88};
89
90&uart3 {
91 fsl,uart-has-rtscts;
92 status = "okay";
93};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
new file mode 100644
index 000000000000..c8d57d1d0743
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dts
@@ -0,0 +1,44 @@
1/*
2 * Copyright 2012 Sascha Hauer, Uwe Kleine-König, Steffen Trumtrar
3 * and Markus Pargmann, Pengutronix
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14#include "imx27.dtsi"
15
16/ {
17 model = "Phytec pca100";
18 compatible = "phytec,imx27-pca100", "fsl,imx27";
19
20 memory {
21 reg = <0xa0000000 0x08000000>; /* 128MB */
22 };
23};
24
25&cspi1 {
26 fsl,spi-num-chipselects = <2>;
27 cs-gpios = <&gpio4 28 0>,
28 <&gpio4 27 0>;
29 status = "okay";
30};
31
32&fec {
33 status = "okay";
34};
35
36&i2c2 {
37 status = "okay";
38
39 at24@52 {
40 compatible = "at,24c32";
41 pagesize = <32>;
42 reg = <0x52>;
43 };
44};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index e7ed9786920a..0fc6551786c6 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -35,3 +35,16 @@
35 fsl,uart-has-rtscts; 35 fsl,uart-has-rtscts;
36 status = "okay"; 36 status = "okay";
37}; 37};
38
39&weim {
40 can@d4000000 {
41 compatible = "nxp,sja1000";
42 reg = <4 0x00000000 0x00000100>;
43 interrupt-parent = <&gpio5>;
44 interrupts = <19 0x2>;
45 nxp,external-clock-frequency = <16000000>;
46 nxp,tx-output-config = <0x16>;
47 nxp,no-comparator-bypass;
48 fsl,weim-cs-timing = <0x0000dcf6 0x444a0301 0x44443302>;
49 };
50};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
index f0105651869d..4ec402c38945 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dts
@@ -17,49 +17,22 @@
17 compatible = "phytec,imx27-pcm038", "fsl,imx27"; 17 compatible = "phytec,imx27-pcm038", "fsl,imx27";
18 18
19 memory { 19 memory {
20 reg = <0x0 0x0>; 20 reg = <0xa0000000 0x08000000>;
21 }; 21 };
22};
22 23
23 soc { 24&audmux {
24 aipi@10000000 { /* aipi1 */ 25 status = "okay";
25 serial@1000a000 {
26 status = "okay";
27 };
28
29 i2c@1001d000 {
30 clock-frequency = <400000>;
31 status = "okay";
32 at24@52 {
33 compatible = "at,24c32";
34 pagesize = <32>;
35 reg = <0x52>;
36 };
37 pcf8563@51 {
38 compatible = "nxp,pcf8563";
39 reg = <0x51>;
40 };
41 lm75@4a {
42 compatible = "national,lm75";
43 reg = <0x4a>;
44 };
45 };
46 };
47 26
48 aipi@10020000 { /* aipi2 */ 27 /* SSI0 <=> PINS_4 (MC13783 Audio) */
49 ethernet@1002b000 { 28 ssi0 {
50 phy-reset-gpios = <&gpio3 30 0>; 29 fsl,audmux-port = <0>;
51 status = "okay"; 30 fsl,port-config = <0xcb205000>;
52 };
53 };
54 }; 31 };
55 32
56 nor_flash@c0000000 { 33 pins4 {
57 compatible = "cfi-flash"; 34 fsl,audmux-port = <2>;
58 bank-width = <2>; 35 fsl,port-config = <0x00001000>;
59 reg = <0xc0000000 0x02000000>;
60 linux,mtd-name = "physmap-flash.0";
61 #address-cells = <1>;
62 #size-cells = <1>;
63 }; 36 };
64}; 37};
65 38
@@ -80,28 +53,16 @@
80 fsl,mc13xxx-uses-rtc; 53 fsl,mc13xxx-uses-rtc;
81 54
82 regulators { 55 regulators {
83 sw1a_reg: sw1a { 56 /* SW1A and SW1B joined operation */
57 sw1_reg: sw1a {
84 regulator-min-microvolt = <1200000>; 58 regulator-min-microvolt = <1200000>;
85 regulator-max-microvolt = <1200000>; 59 regulator-max-microvolt = <1520000>;
86 regulator-always-on; 60 regulator-always-on;
87 regulator-boot-on; 61 regulator-boot-on;
88 }; 62 };
89 63
90 sw1b_reg: sw1b { 64 /* SW2A and SW2B joined operation */
91 regulator-min-microvolt = <1200000>; 65 sw2_reg: sw2a {
92 regulator-max-microvolt = <1200000>;
93 regulator-always-on;
94 regulator-boot-on;
95 };
96
97 sw2a_reg: sw2a {
98 regulator-min-microvolt = <1800000>;
99 regulator-max-microvolt = <1800000>;
100 regulator-always-on;
101 regulator-boot-on;
102 };
103
104 sw2b_reg: sw2b {
105 regulator-min-microvolt = <1800000>; 66 regulator-min-microvolt = <1800000>;
106 regulator-max-microvolt = <1800000>; 67 regulator-max-microvolt = <1800000>;
107 regulator-always-on; 68 regulator-always-on;
@@ -172,8 +133,62 @@
172 }; 133 };
173}; 134};
174 135
136&fec {
137 phy-reset-gpios = <&gpio3 30 0>;
138 status = "okay";
139};
140
141&i2c2 {
142 clock-frequency = <400000>;
143 status = "okay";
144
145 at24@52 {
146 compatible = "at,24c32";
147 pagesize = <32>;
148 reg = <0x52>;
149 };
150
151 pcf8563@51 {
152 compatible = "nxp,pcf8563";
153 reg = <0x51>;
154 };
155
156 lm75@4a {
157 compatible = "national,lm75";
158 reg = <0x4a>;
159 };
160};
161
175&nfc { 162&nfc {
176 nand-bus-width = <8>; 163 nand-bus-width = <8>;
177 nand-ecc-mode = "hw"; 164 nand-ecc-mode = "hw";
178 status = "okay"; 165 status = "okay";
179}; 166};
167
168&uart1 {
169 status = "okay";
170};
171
172&weim {
173 status = "okay";
174
175 nor: nor@c0000000 {
176 compatible = "cfi-flash";
177 reg = <0 0x00000000 0x02000000>;
178 bank-width = <2>;
179 linux,mtd-name = "physmap-flash.0";
180 fsl,weim-cs-timing = <0x22c2cf00 0x75000d01 0x00000900>;
181 #address-cells = <1>;
182 #size-cells = <1>;
183 };
184
185 sram: sram@c8000000 {
186 compatible = "mtd-ram";
187 reg = <1 0x00000000 0x00800000>;
188 bank-width = <2>;
189 linux,mtd-name = "mtd-ram.0";
190 fsl,weim-cs-timing = <0x0000d843 0x22252521 0x22220a00>;
191 #address-cells = <1>;
192 #size-cells = <1>;
193 };
194};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 0695264ddf1b..c037c223619a 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -13,25 +13,27 @@
13 13
14/ { 14/ {
15 aliases { 15 aliases {
16 serial0 = &uart1;
17 serial1 = &uart2;
18 serial2 = &uart3;
19 serial3 = &uart4;
20 serial4 = &uart5;
21 serial5 = &uart6;
22 gpio0 = &gpio1; 16 gpio0 = &gpio1;
23 gpio1 = &gpio2; 17 gpio1 = &gpio2;
24 gpio2 = &gpio3; 18 gpio2 = &gpio3;
25 gpio3 = &gpio4; 19 gpio3 = &gpio4;
26 gpio4 = &gpio5; 20 gpio4 = &gpio5;
27 gpio5 = &gpio6; 21 gpio5 = &gpio6;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
28 spi0 = &cspi1; 30 spi0 = &cspi1;
29 spi1 = &cspi2; 31 spi1 = &cspi2;
30 spi2 = &cspi3; 32 spi2 = &cspi3;
31 }; 33 };
32 34
33 avic: avic-interrupt-controller@e0000000 { 35 aitc: aitc-interrupt-controller@e0000000 {
34 compatible = "fsl,imx27-avic", "fsl,avic"; 36 compatible = "fsl,imx27-aitc", "fsl,avic";
35 interrupt-controller; 37 interrupt-controller;
36 #interrupt-cells = <1>; 38 #interrupt-cells = <1>;
37 reg = <0x10040000 0x1000>; 39 reg = <0x10040000 0x1000>;
@@ -47,11 +49,29 @@
47 }; 49 };
48 }; 50 };
49 51
52 cpus {
53 #size-cells = <0>;
54 #address-cells = <1>;
55
56 cpu: cpu@0 {
57 device_type = "cpu";
58 compatible = "arm,arm926ej-s";
59 operating-points = <
60 /* kHz uV */
61 266000 1300000
62 399000 1450000
63 >;
64 clock-latency = <62500>;
65 clocks = <&clks 18>;
66 voltage-tolerance = <5>;
67 };
68 };
69
50 soc { 70 soc {
51 #address-cells = <1>; 71 #address-cells = <1>;
52 #size-cells = <1>; 72 #size-cells = <1>;
53 compatible = "simple-bus"; 73 compatible = "simple-bus";
54 interrupt-parent = <&avic>; 74 interrupt-parent = <&aitc>;
55 ranges; 75 ranges;
56 76
57 aipi@10000000 { /* AIPI1 */ 77 aipi@10000000 { /* AIPI1 */
@@ -75,7 +95,7 @@
75 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 95 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
76 reg = <0x10002000 0x1000>; 96 reg = <0x10002000 0x1000>;
77 interrupts = <27>; 97 interrupts = <27>;
78 clocks = <&clks 0>; 98 clocks = <&clks 74>;
79 }; 99 };
80 100
81 gpt1: timer@10003000 { 101 gpt1: timer@10003000 {
@@ -102,7 +122,7 @@
102 clock-names = "ipg", "per"; 122 clock-names = "ipg", "per";
103 }; 123 };
104 124
105 pwm0: pwm@10006000 { 125 pwm: pwm@10006000 {
106 compatible = "fsl,imx27-pwm"; 126 compatible = "fsl,imx27-pwm";
107 reg = <0x10006000 0x1000>; 127 reg = <0x10006000 0x1000>;
108 interrupts = <23>; 128 interrupts = <23>;
@@ -110,6 +130,21 @@
110 clock-names = "ipg", "per"; 130 clock-names = "ipg", "per";
111 }; 131 };
112 132
133 kpp: kpp@10008000 {
134 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
135 reg = <0x10008000 0x1000>;
136 interrupts = <21>;
137 clocks = <&clks 37>;
138 status = "disabled";
139 };
140
141 owire: owire@10009000 {
142 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
143 reg = <0x10009000 0x1000>;
144 clocks = <&clks 35>;
145 status = "disabled";
146 };
147
113 uart1: serial@1000a000 { 148 uart1: serial@1000a000 {
114 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 149 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
115 reg = <0x1000a000 0x1000>; 150 reg = <0x1000a000 0x1000>;
@@ -260,6 +295,14 @@
260 #interrupt-cells = <2>; 295 #interrupt-cells = <2>;
261 }; 296 };
262 297
298 audmux: audmux@10016000 {
299 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
300 reg = <0x10016000 0x1000>;
301 clocks = <&clks 0>;
302 clock-names = "audmux";
303 status = "disabled";
304 };
305
263 cspi3: cspi@10017000 { 306 cspi3: cspi@10017000 {
264 #address-cells = <1>; 307 #address-cells = <1>;
265 #size-cells = <0>; 308 #size-cells = <0>;
@@ -342,6 +385,15 @@
342 reg = <0x10020000 0x20000>; 385 reg = <0x10020000 0x20000>;
343 ranges; 386 ranges;
344 387
388 fb: fb@10021000 {
389 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
390 interrupts = <61>;
391 reg = <0x10021000 0x1000>;
392 clocks = <&clks 36>, <&clks 65>, <&clks 59>;
393 clock-names = "ipg", "ahb", "per";
394 status = "disabled";
395 };
396
345 coda: coda@10023000 { 397 coda: coda@10023000 {
346 compatible = "fsl,imx27-vpu"; 398 compatible = "fsl,imx27-vpu";
347 reg = <0x10023000 0x0200>; 399 reg = <0x10023000 0x0200>;
@@ -351,27 +403,37 @@
351 iram = <&iram>; 403 iram = <&iram>;
352 }; 404 };
353 405
406 sahara2: sahara@10025000 {
407 compatible = "fsl,imx27-sahara";
408 reg = <0x10025000 0x1000>;
409 interrupts = <59>;
410 clocks = <&clks 32>, <&clks 64>;
411 clock-names = "ipg", "ahb";
412 };
413
354 clks: ccm@10027000{ 414 clks: ccm@10027000{
355 compatible = "fsl,imx27-ccm"; 415 compatible = "fsl,imx27-ccm";
356 reg = <0x10027000 0x1000>; 416 reg = <0x10027000 0x1000>;
357 #clock-cells = <1>; 417 #clock-cells = <1>;
358 }; 418 };
359 419
420 iim: iim@10028000 {
421 compatible = "fsl,imx27-iim";
422 reg = <0x10028000 0x1000>;
423 interrupts = <62>;
424 clocks = <&clks 38>;
425 };
426
360 fec: ethernet@1002b000 { 427 fec: ethernet@1002b000 {
361 compatible = "fsl,imx27-fec"; 428 compatible = "fsl,imx27-fec";
362 reg = <0x1002b000 0x4000>; 429 reg = <0x1002b000 0x4000>;
363 interrupts = <50>; 430 interrupts = <50>;
364 clocks = <&clks 48>, <&clks 67>, <&clks 0>; 431 clocks = <&clks 48>, <&clks 67>;
365 clock-names = "ipg", "ahb", "ptp"; 432 clock-names = "ipg", "ahb";
366 status = "disabled"; 433 status = "disabled";
367 }; 434 };
368 }; 435 };
369 436
370 iram: iram@ffff4c00 {
371 compatible = "mmio-sram";
372 reg = <0xffff4c00 0xb400>;
373 };
374
375 nfc: nand@d8000000 { 437 nfc: nand@d8000000 {
376 #address-cells = <1>; 438 #address-cells = <1>;
377 #size-cells = <1>; 439 #size-cells = <1>;
@@ -381,5 +443,27 @@
381 clocks = <&clks 54>; 443 clocks = <&clks 54>;
382 status = "disabled"; 444 status = "disabled";
383 }; 445 };
446
447 weim: weim@d8002000 {
448 #address-cells = <2>;
449 #size-cells = <1>;
450 compatible = "fsl,imx27-weim";
451 reg = <0xd8002000 0x1000>;
452 clocks = <&clks 0>;
453 ranges = <
454 0 0 0xc0000000 0x08000000
455 1 0 0xc8000000 0x08000000
456 2 0 0xd0000000 0x02000000
457 3 0 0xd2000000 0x02000000
458 4 0 0xd4000000 0x02000000
459 5 0 0xd6000000 0x02000000
460 >;
461 status = "disabled";
462 };
463
464 iram: iram@ffff4c00 {
465 compatible = "mmio-sram";
466 reg = <0xffff4c00 0xb400>;
467 };
384 }; 468 };
385}; 469};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index 94c4476972c3..1ec8c94bbac9 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -23,10 +23,7 @@
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 pinctrl@80018000 { 25 pinctrl@80018000 {
26 pinctrl-names = "default"; 26 ssd1306_cfa10036: ssd1306-10036@0 {
27 pinctrl-0 = <&hog_pins_cfa10036>;
28
29 hog_pins_cfa10036: hog-10036@0 {
30 reg = <0>; 27 reg = <0>;
31 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
32 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */ 29 0x2073 /* MX28_PAD_SSP0_D7__GPIO_2_7 */
@@ -83,6 +80,8 @@
83 80
84 ssd1306: oled@3c { 81 ssd1306: oled@3c {
85 compatible = "solomon,ssd1306fb-i2c"; 82 compatible = "solomon,ssd1306fb-i2c";
83 pinctrl-names = "default";
84 pinctrl-0 = <&ssd1306_cfa10036>;
86 reg = <0x3c>; 85 reg = <0x3c>;
87 reset-gpios = <&gpio2 7 0>; 86 reset-gpios = <&gpio2 7 0>;
88 solomon,height = <32>; 87 solomon,height = <32>;
diff --git a/arch/arm/boot/dts/imx28-cfa10037.dts b/arch/arm/boot/dts/imx28-cfa10037.dts
index c2ef3a3d655e..182b99fe35f3 100644
--- a/arch/arm/boot/dts/imx28-cfa10037.dts
+++ b/arch/arm/boot/dts/imx28-cfa10037.dts
@@ -22,13 +22,19 @@
22 apb@80000000 { 22 apb@80000000 {
23 apbh@80000000 { 23 apbh@80000000 {
24 pinctrl@80018000 { 24 pinctrl@80018000 {
25 pinctrl-names = "default", "default"; 25 usb_pins_cfa10037: usb-10037@0 {
26 pinctrl-1 = <&hog_pins_cfa10037>;
27
28 hog_pins_cfa10037: hog-10037@0 {
29 reg = <0>; 26 reg = <0>;
30 fsl,pinmux-ids = < 27 fsl,pinmux-ids = <
31 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 28 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
29 >;
30 fsl,drive-strength = <0>;
31 fsl,voltage = <1>;
32 fsl,pull-up = <0>;
33 };
34
35 mac0_pins_cfa10037: mac0-10037@0 {
36 reg = <0>;
37 fsl,pinmux-ids = <
32 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ 38 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
33 >; 39 >;
34 fsl,drive-strength = <0>; 40 fsl,drive-strength = <0>;
@@ -56,7 +62,8 @@
56 mac0: ethernet@800f0000 { 62 mac0: ethernet@800f0000 {
57 phy-mode = "rmii"; 63 phy-mode = "rmii";
58 pinctrl-names = "default"; 64 pinctrl-names = "default";
59 pinctrl-0 = <&mac0_pins_a>; 65 pinctrl-0 = <&mac0_pins_a
66 &mac0_pins_cfa10037>;
60 phy-reset-gpios = <&gpio2 21 0>; 67 phy-reset-gpios = <&gpio2 21 0>;
61 phy-reset-duration = <100>; 68 phy-reset-duration = <100>;
62 status = "okay"; 69 status = "okay";
@@ -68,6 +75,8 @@
68 75
69 reg_usb1_vbus: usb1_vbus { 76 reg_usb1_vbus: usb1_vbus {
70 compatible = "regulator-fixed"; 77 compatible = "regulator-fixed";
78 pinctrl-names = "default";
79 pinctrl-0 = <&usb_pins_cfa10037>;
71 regulator-name = "usb1_vbus"; 80 regulator-name = "usb1_vbus";
72 regulator-min-microvolt = <5000000>; 81 regulator-min-microvolt = <5000000>;
73 regulator-max-microvolt = <5000000>; 82 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-cfa10049.dts b/arch/arm/boot/dts/imx28-cfa10049.dts
index 04b2f769ffbd..06e4cfaf7dd2 100644
--- a/arch/arm/boot/dts/imx28-cfa10049.dts
+++ b/arch/arm/boot/dts/imx28-cfa10049.dts
@@ -22,32 +22,62 @@
22 apb@80000000 { 22 apb@80000000 {
23 apbh@80000000 { 23 apbh@80000000 {
24 pinctrl@80018000 { 24 pinctrl@80018000 {
25 pinctrl-names = "default", "default"; 25 usb_pins_cfa10049: usb-10049@0 {
26 pinctrl-1 = <&hog_pins_cfa10049
27 &hog_pins_cfa10049_pullup>;
28
29 hog_pins_cfa10049: hog-10049@0 {
30 reg = <0>; 26 reg = <0>;
31 fsl,pinmux-ids = < 27 fsl,pinmux-ids = <
32 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 28 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
29 >;
30 fsl,drive-strength = <0>;
31 fsl,voltage = <1>;
32 fsl,pull-up = <0>;
33 };
34
35 i2cmux_pins_cfa10049: i2cmux-10049@0 {
36 reg = <0>;
37 fsl,pinmux-ids = <
33 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */ 38 0x1163 /* MX28_PAD_LCD_D22__GPIO_1_22 */
34 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */ 39 0x1173 /* MX28_PAD_LCD_D22__GPIO_1_23 */
40 >;
41 fsl,drive-strength = <0>;
42 fsl,voltage = <1>;
43 fsl,pull-up = <0>;
44 };
45
46 mac0_pins_cfa10049: mac0-10049@0 {
47 reg = <0>;
48 fsl,pinmux-ids = <
35 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */ 49 0x2153 /* MX28_PAD_SSP2_D5__GPIO_2_21 */
36 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
37 >; 50 >;
38 fsl,drive-strength = <0>; 51 fsl,drive-strength = <0>;
39 fsl,voltage = <1>; 52 fsl,voltage = <1>;
40 fsl,pull-up = <0>; 53 fsl,pull-up = <0>;
41 }; 54 };
42 55
43 hog_pins_cfa10049_pullup: hog-10049-pullup@0 { 56 pca_pins_cfa10049: pca-10049@0 {
44 reg = <0>; 57 reg = <0>;
45 fsl,pinmux-ids = < 58 fsl,pinmux-ids = <
46 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */ 59 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
60 >;
61 fsl,drive-strength = <0>;
62 fsl,voltage = <1>;
63 fsl,pull-up = <1>;
64 };
65
66 rotary_pins_cfa10049: rotary-10049@0 {
67 reg = <0>;
68 fsl,pinmux-ids = <
47 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */ 69 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
48 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */ 70 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
71 >;
72 fsl,drive-strength = <0>;
73 fsl,voltage = <1>;
74 fsl,pull-up = <1>;
75 };
76
77 rotary_btn_pins_cfa10049: rotary-btn-10049@0 {
78 reg = <0>;
79 fsl,pinmux-ids = <
49 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */ 80 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
50 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
51 >; 81 >;
52 fsl,drive-strength = <0>; 82 fsl,drive-strength = <0>;
53 fsl,voltage = <1>; 83 fsl,voltage = <1>;
@@ -60,6 +90,7 @@
60 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 90 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
61 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 91 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
62 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ 92 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
93 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
63 >; 94 >;
64 fsl,drive-strength = <1>; 95 fsl,drive-strength = <1>;
65 fsl,voltage = <1>; 96 fsl,voltage = <1>;
@@ -120,6 +151,16 @@
120 fsl,pull-up = <0>; 151 fsl,pull-up = <0>;
121 }; 152 };
122 153
154 lcdif_pins_cfa10049_pullup: lcdif-10049-pullup@0 {
155 reg = <0>;
156 fsl,pinmux-ids = <
157 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
158 >;
159 fsl,drive-strength = <0>;
160 fsl,voltage = <1>;
161 fsl,pull-up = <1>;
162 };
163
123 w1_gpio_pins: w1-gpio@0 { 164 w1_gpio_pins: w1-gpio@0 {
124 reg = <0>; 165 reg = <0>;
125 fsl,pinmux-ids = < 166 fsl,pinmux-ids = <
@@ -134,7 +175,8 @@
134 lcdif@80030000 { 175 lcdif@80030000 {
135 pinctrl-names = "default"; 176 pinctrl-names = "default";
136 pinctrl-0 = <&lcdif_18bit_pins_cfa10049 177 pinctrl-0 = <&lcdif_18bit_pins_cfa10049
137 &lcdif_pins_cfa10049>; 178 &lcdif_pins_cfa10049
179 &lcdif_pins_cfa10049_pullup>;
138 display = <&display>; 180 display = <&display>;
139 status = "okay"; 181 status = "okay";
140 182
@@ -181,6 +223,8 @@
181 compatible = "i2c-mux-gpio"; 223 compatible = "i2c-mux-gpio";
182 #address-cells = <1>; 224 #address-cells = <1>;
183 #size-cells = <0>; 225 #size-cells = <0>;
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2cmux_pins_cfa10049>;
184 mux-gpios = <&gpio1 22 0 &gpio1 23 0>; 228 mux-gpios = <&gpio1 22 0 &gpio1 23 0>;
185 i2c-parent = <&i2c1>; 229 i2c-parent = <&i2c1>;
186 230
@@ -203,6 +247,8 @@
203 247
204 pca9555: pca9555@20 { 248 pca9555: pca9555@20 {
205 compatible = "nxp,pca9555"; 249 compatible = "nxp,pca9555";
250 pinctrl-names = "default";
251 pinctrl-0 = <&pca_pins_cfa10049>;
206 interrupt-parent = <&gpio2>; 252 interrupt-parent = <&gpio2>;
207 interrupts = <19 0x2>; 253 interrupts = <19 0x2>;
208 gpio-controller; 254 gpio-controller;
@@ -239,6 +285,8 @@
239 285
240 reg_usb1_vbus: usb1_vbus { 286 reg_usb1_vbus: usb1_vbus {
241 compatible = "regulator-fixed"; 287 compatible = "regulator-fixed";
288 pinctrl-names = "default";
289 pinctrl-0 = <&usb_pins_cfa10049>;
242 regulator-name = "usb1_vbus"; 290 regulator-name = "usb1_vbus";
243 regulator-min-microvolt = <5000000>; 291 regulator-min-microvolt = <5000000>;
244 regulator-max-microvolt = <5000000>; 292 regulator-max-microvolt = <5000000>;
@@ -250,7 +298,8 @@
250 mac0: ethernet@800f0000 { 298 mac0: ethernet@800f0000 {
251 phy-mode = "rmii"; 299 phy-mode = "rmii";
252 pinctrl-names = "default"; 300 pinctrl-names = "default";
253 pinctrl-0 = <&mac0_pins_a>; 301 pinctrl-0 = <&mac0_pins_a
302 &mac0_pins_cfa10049>;
254 phy-reset-gpios = <&gpio2 21 0>; 303 phy-reset-gpios = <&gpio2 21 0>;
255 phy-reset-duration = <100>; 304 phy-reset-duration = <100>;
256 status = "okay"; 305 status = "okay";
@@ -320,6 +369,8 @@
320 369
321 gpio_keys { 370 gpio_keys {
322 compatible = "gpio-keys"; 371 compatible = "gpio-keys";
372 pinctrl-names = "default";
373 pinctrl-0 = <&rotary_btn_pins_cfa10049>;
323 #address-cells = <1>; 374 #address-cells = <1>;
324 #size-cells = <0>; 375 #size-cells = <0>;
325 376
@@ -333,6 +384,8 @@
333 384
334 rotary { 385 rotary {
335 compatible = "rotary-encoder"; 386 compatible = "rotary-encoder";
387 pinctrl-names = "default";
388 pinctrl-0 = <&rotary_pins_cfa10049>;
336 gpios = <&gpio3 24 1>, <&gpio3 25 1>; 389 gpios = <&gpio3 24 1>, <&gpio3 25 1>;
337 linux,axis = <1>; /* REL_Y */ 390 linux,axis = <1>; /* REL_Y */
338 rotary-encoder,relative-axis; 391 rotary-encoder,relative-axis;
diff --git a/arch/arm/boot/dts/imx28-cfa10055.dts b/arch/arm/boot/dts/imx28-cfa10055.dts
index 158111244122..171bcbe1ec4b 100644
--- a/arch/arm/boot/dts/imx28-cfa10055.dts
+++ b/arch/arm/boot/dts/imx28-cfa10055.dts
@@ -23,36 +23,13 @@
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 pinctrl@80018000 { 25 pinctrl@80018000 {
26 pinctrl-names = "default", "default";
27 pinctrl-1 = <&hog_pins_cfa10055
28 &hog_pins_cfa10055_pullup>;
29
30 hog_pins_cfa10055: hog-10055@0 {
31 reg = <0>;
32 fsl,pinmux-ids = <
33 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
34 >;
35 fsl,drive-strength = <0>;
36 fsl,voltage = <1>;
37 fsl,pull-up = <0>;
38 };
39
40 hog_pins_cfa10055_pullup: hog-10055-pullup@0 {
41 reg = <0>;
42 fsl,pinmux-ids = <
43 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
44 >;
45 fsl,drive-strength = <0>;
46 fsl,voltage = <1>;
47 fsl,pull-up = <1>;
48 };
49
50 spi2_pins_cfa10055: spi2-cfa10055@0 { 26 spi2_pins_cfa10055: spi2-cfa10055@0 {
51 reg = <0>; 27 reg = <0>;
52 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
53 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */ 29 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
54 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */ 30 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
55 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */ 31 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
32 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
56 >; 33 >;
57 fsl,drive-strength = <1>; 34 fsl,drive-strength = <1>;
58 fsl,voltage = <1>; 35 fsl,voltage = <1>;
@@ -98,12 +75,23 @@
98 fsl,voltage = <1>; 75 fsl,voltage = <1>;
99 fsl,pull-up = <0>; 76 fsl,pull-up = <0>;
100 }; 77 };
78
79 lcdif_pins_cfa10055_pullup: lcdif-10055-pullup@0 {
80 reg = <0>;
81 fsl,pinmux-ids = <
82 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
83 >;
84 fsl,drive-strength = <0>;
85 fsl,voltage = <1>;
86 fsl,pull-up = <1>;
87 };
101 }; 88 };
102 89
103 lcdif@80030000 { 90 lcdif@80030000 {
104 pinctrl-names = "default"; 91 pinctrl-names = "default";
105 pinctrl-0 = <&lcdif_18bit_pins_cfa10055 92 pinctrl-0 = <&lcdif_18bit_pins_cfa10055
106 &lcdif_pins_cfa10055>; 93 &lcdif_pins_cfa10055
94 &lcdif_pins_cfa10055_pullup>;
107 display = <&display>; 95 display = <&display>;
108 status = "okay"; 96 status = "okay";
109 97
diff --git a/arch/arm/boot/dts/imx28-cfa10056.dts b/arch/arm/boot/dts/imx28-cfa10056.dts
new file mode 100644
index 000000000000..b45dd0e4ee57
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10056.dts
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2013 Free Electrons
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/*
13 * The CFA-10055 is an expansion board for the CFA-10036 module and
14 * CFA-10037, thus we need to include the CFA-10037 DTS.
15 */
16/include/ "imx28-cfa10037.dts"
17
18/ {
19 model = "Crystalfontz CFA-10056 Board";
20 compatible = "crystalfontz,cfa10056", "crystalfontz,cfa10037", "crystalfontz,cfa10036", "fsl,imx28";
21
22 apb@80000000 {
23 apbh@80000000 {
24 pinctrl@80018000 {
25 spi2_pins_cfa10056: spi2-cfa10056@0 {
26 reg = <0>;
27 fsl,pinmux-ids = <
28 0x2103 /* MX28_PAD_SSP2_SCK__GPIO_2_16 */
29 0x2113 /* MX28_PAD_SSP2_CMD__GPIO_2_17 */
30 0x2123 /* MX28_PAD_SSP2_D0__GPIO_2_18 */
31 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
32 >;
33 fsl,drive-strength = <1>;
34 fsl,voltage = <1>;
35 fsl,pull-up = <1>;
36 };
37
38 lcdif_pins_cfa10056: lcdif-10056@0 {
39 reg = <0>;
40 fsl,pinmux-ids = <
41 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
42 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
43 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
44 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
45 >;
46 fsl,drive-strength = <0>;
47 fsl,voltage = <1>;
48 fsl,pull-up = <0>;
49 };
50
51 lcdif_pins_cfa10056_pullup: lcdif-10056-pullup@0 {
52 reg = <0>;
53 fsl,pinmux-ids = <
54 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
55 >;
56 fsl,drive-strength = <0>;
57 fsl,voltage = <1>;
58 fsl,pull-up = <1>;
59 };
60 };
61
62 lcdif@80030000 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&lcdif_24bit_pins_a
65 &lcdif_pins_cfa10056
66 &lcdif_pins_cfa10056_pullup >;
67 display = <&display>;
68 status = "okay";
69
70 display: display {
71 bits-per-pixel = <32>;
72 bus-width = <24>;
73
74 display-timings {
75 native-mode = <&timing0>;
76 timing0: timing0 {
77 clock-frequency = <32000000>;
78 hactive = <480>;
79 vactive = <800>;
80 hback-porch = <2>;
81 hfront-porch = <2>;
82 vback-porch = <2>;
83 vfront-porch = <2>;
84 hsync-len = <5>;
85 vsync-len = <5>;
86 hsync-active = <0>;
87 vsync-active = <0>;
88 de-active = <1>;
89 pixelclk-active = <1>;
90 };
91 };
92 };
93 };
94 };
95 };
96
97 spi2 {
98 compatible = "spi-gpio";
99 pinctrl-names = "default";
100 pinctrl-0 = <&spi2_pins_cfa10056>;
101 status = "okay";
102 gpio-sck = <&gpio2 16 0>;
103 gpio-mosi = <&gpio2 17 0>;
104 gpio-miso = <&gpio2 18 0>;
105 cs-gpios = <&gpio3 5 0>;
106 num-chipselects = <1>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109
110 hx8369: hx8369@0 {
111 compatible = "himax,hx8369a", "himax,hx8369";
112 reg = <0>;
113 spi-max-frequency = <100000>;
114 spi-cpol;
115 spi-cpha;
116 gpios-reset = <&gpio3 30 0>;
117 };
118 };
119};
diff --git a/arch/arm/boot/dts/imx28-cfa10057.dts b/arch/arm/boot/dts/imx28-cfa10057.dts
index 2da713cdb42a..0333c0532f28 100644
--- a/arch/arm/boot/dts/imx28-cfa10057.dts
+++ b/arch/arm/boot/dts/imx28-cfa10057.dts
@@ -23,35 +23,16 @@
23 apb@80000000 { 23 apb@80000000 {
24 apbh@80000000 { 24 apbh@80000000 {
25 pinctrl@80018000 { 25 pinctrl@80018000 {
26 pinctrl-names = "default", "default"; 26 usb_pins_cfa10057: usb-10057@0 {
27 pinctrl-1 = <&hog_pins_cfa10057
28 &hog_pins_cfa10057_pullup>;
29
30 hog_pins_cfa10057: hog-10057@0 {
31 reg = <0>; 27 reg = <0>;
32 fsl,pinmux-ids = < 28 fsl,pinmux-ids = <
33 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */ 29 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
34 0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
35 >; 30 >;
36 fsl,drive-strength = <0>; 31 fsl,drive-strength = <0>;
37 fsl,voltage = <1>; 32 fsl,voltage = <1>;
38 fsl,pull-up = <0>; 33 fsl,pull-up = <0>;
39 }; 34 };
40 35
41 hog_pins_cfa10057_pullup: hog-10057-pullup@0 {
42 reg = <0>;
43 fsl,pinmux-ids = <
44 0x2133 /* MX28_PAD_SSP2_D3__GPIO_2_19 */
45 0x3183 /* MX28_PAD_I2C0_SCL__GPIO_3_24 */
46 0x3193 /* MX28_PAD_I2C0_SDA__GPIO_3_25 */
47 0x31a3 /* MX28_PAD_SAIF_SDATA0__GPIO_3_26 */
48 0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
49 >;
50 fsl,drive-strength = <0>;
51 fsl,voltage = <1>;
52 fsl,pull-up = <1>;
53 };
54
55 lcdif_18bit_pins_cfa10057: lcdif-18bit@0 { 36 lcdif_18bit_pins_cfa10057: lcdif-18bit@0 {
56 reg = <0>; 37 reg = <0>;
57 fsl,pinmux-ids = < 38 fsl,pinmux-ids = <
@@ -164,6 +145,8 @@
164 145
165 reg_usb1_vbus: usb1_vbus { 146 reg_usb1_vbus: usb1_vbus {
166 compatible = "regulator-fixed"; 147 compatible = "regulator-fixed";
148 pinctrl-names = "default";
149 pinctrl-0 = <&usb_pins_cfa10057>;
167 regulator-name = "usb1_vbus"; 150 regulator-name = "usb1_vbus";
168 regulator-min-microvolt = <5000000>; 151 regulator-min-microvolt = <5000000>;
169 regulator-max-microvolt = <5000000>; 152 regulator-max-microvolt = <5000000>;
diff --git a/arch/arm/boot/dts/imx28-cfa10058.dts b/arch/arm/boot/dts/imx28-cfa10058.dts
new file mode 100644
index 000000000000..64c64c55a82a
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10058.dts
@@ -0,0 +1,141 @@
1/*
2 * Copyright 2013 Crystalfontz America, Inc.
3 * Copyright 2013 Free Electrons
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/*
14 * The CFA-10058 is an expansion board for the CFA-10036 module, thus we
15 * need to include the CFA-10036 DTS.
16 */
17/include/ "imx28-cfa10036.dts"
18
19/ {
20 model = "Crystalfontz CFA-10058 Board";
21 compatible = "crystalfontz,cfa10058", "crystalfontz,cfa10036", "fsl,imx28";
22
23 apb@80000000 {
24 apbh@80000000 {
25 pinctrl@80018000 {
26 usb_pins_cfa10058: usb-10058@0 {
27 reg = <0>;
28 fsl,pinmux-ids = <
29 0x0073 /* MX28_PAD_GPMI_D7__GPIO_0_7 */
30 >;
31 fsl,drive-strength = <0>;
32 fsl,voltage = <1>;
33 fsl,pull-up = <0>;
34 };
35
36 lcdif_pins_cfa10058: lcdif-10058@0 {
37 reg = <0>;
38 fsl,pinmux-ids = <
39 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
40 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
41 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
42 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
43 >;
44 fsl,drive-strength = <0>;
45 fsl,voltage = <1>;
46 fsl,pull-up = <0>;
47 };
48 };
49
50 lcdif@80030000 {
51 pinctrl-names = "default";
52 pinctrl-0 = <&lcdif_24bit_pins_a
53 &lcdif_pins_cfa10058>;
54 display = <&display>;
55 status = "okay";
56
57 display: display {
58 bits-per-pixel = <32>;
59 bus-width = <24>;
60
61 display-timings {
62 native-mode = <&timing0>;
63 timing0: timing0 {
64 clock-frequency = <30000000>;
65 hactive = <800>;
66 vactive = <480>;
67 hback-porch = <40>;
68 hfront-porch = <40>;
69 vback-porch = <13>;
70 vfront-porch = <29>;
71 hsync-len = <8>;
72 vsync-len = <8>;
73 hsync-active = <0>;
74 vsync-active = <0>;
75 de-active = <1>;
76 pixelclk-active = <1>;
77 };
78 };
79 };
80 };
81 };
82
83 apbx@80040000 {
84 lradc@80050000 {
85 fsl,lradc-touchscreen-wires = <4>;
86 status = "okay";
87 };
88
89 pwm: pwm@80064000 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pwm3_pins_b>;
92 status = "okay";
93 };
94
95 usbphy1: usbphy@8007e000 {
96 status = "okay";
97 };
98 };
99 };
100
101 ahb@80080000 {
102 usb1: usb@80090000 {
103 vbus-supply = <&reg_usb1_vbus>;
104 pinctrl-0 = <&usbphy1_pins_a>;
105 pinctrl-names = "default";
106 status = "okay";
107 };
108 };
109
110 regulators {
111 compatible = "simple-bus";
112
113 reg_usb1_vbus: usb1_vbus {
114 pinctrl-names = "default";
115 pinctrl-0 = <&usb_pins_cfa10058>;
116 compatible = "regulator-fixed";
117 regulator-name = "usb1_vbus";
118 regulator-min-microvolt = <5000000>;
119 regulator-max-microvolt = <5000000>;
120 gpio = <&gpio0 7 1>;
121 };
122 };
123
124 ahb@80080000 {
125 mac0: ethernet@800f0000 {
126 phy-mode = "rmii";
127 pinctrl-names = "default";
128 pinctrl-0 = <&mac0_pins_a>;
129 phy-reset-gpios = <&gpio2 21 0>;
130 phy-reset-duration = <100>;
131 status = "okay";
132 };
133 };
134
135 backlight {
136 compatible = "pwm-backlight";
137 pwms = <&pwm 3 5000000>;
138 brightness-levels = <0 4 8 16 32 64 128 255>;
139 default-brightness-level = <6>;
140 };
141};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index 44d9da57736e..0d322a2bebaf 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -235,6 +235,12 @@
235 pinctrl-0 = <&auart2_2pins_b>; 235 pinctrl-0 = <&auart2_2pins_b>;
236 status = "okay"; 236 status = "okay";
237 }; 237 };
238
239 pwm: pwm@80064000 {
240 pinctrl-names = "default";
241 pinctrl-0 = <&pwm4_pins_a>;
242 status = "okay";
243 };
238 }; 244 };
239 }; 245 };
240 246
@@ -270,6 +276,13 @@
270 }; 276 };
271 }; 277 };
272 278
279 backlight {
280 compatible = "pwm-backlight";
281 pwms = <&pwm 4 5000000>;
282 brightness-levels = <0 4 8 16 32 64 128 255>;
283 default-brightness-level = <6>;
284 };
285
273 regulators { 286 regulators {
274 compatible = "simple-bus"; 287 compatible = "simple-bus";
275 288
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 9524a0571281..7363fded95ee 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -15,6 +15,8 @@
15 interrupt-parent = <&icoll>; 15 interrupt-parent = <&icoll>;
16 16
17 aliases { 17 aliases {
18 ethernet0 = &mac0;
19 ethernet1 = &mac1;
18 gpio0 = &gpio0; 20 gpio0 = &gpio0;
19 gpio1 = &gpio1; 21 gpio1 = &gpio1;
20 gpio2 = &gpio2; 22 gpio2 = &gpio2;
@@ -27,8 +29,8 @@
27 serial2 = &auart2; 29 serial2 = &auart2;
28 serial3 = &auart3; 30 serial3 = &auart3;
29 serial4 = &auart4; 31 serial4 = &auart4;
30 ethernet0 = &mac0; 32 spi0 = &ssp1;
31 ethernet1 = &mac1; 33 spi1 = &ssp2;
32 }; 34 };
33 35
34 cpus { 36 cpus {
@@ -62,9 +64,9 @@
62 reg = <0x80000000 0x2000>; 64 reg = <0x80000000 0x2000>;
63 }; 65 };
64 66
65 hsadc@80002000 { 67 hsadc: hsadc@80002000 {
66 reg = <0x80002000 0x2000>; 68 reg = <0x80002000 0x2000>;
67 interrupts = <13 87>; 69 interrupts = <13>;
68 dmas = <&dma_apbh 12>; 70 dmas = <&dma_apbh 12>;
69 dma-names = "rx"; 71 dma-names = "rx";
70 status = "disabled"; 72 status = "disabled";
@@ -86,25 +88,24 @@
86 clocks = <&clks 25>; 88 clocks = <&clks 25>;
87 }; 89 };
88 90
89 perfmon@80006000 { 91 perfmon: perfmon@80006000 {
90 reg = <0x80006000 0x800>; 92 reg = <0x80006000 0x800>;
91 interrupts = <27>; 93 interrupts = <27>;
92 status = "disabled"; 94 status = "disabled";
93 }; 95 };
94 96
95 gpmi-nand@8000c000 { 97 gpmi: gpmi-nand@8000c000 {
96 compatible = "fsl,imx28-gpmi-nand"; 98 compatible = "fsl,imx28-gpmi-nand";
97 #address-cells = <1>; 99 #address-cells = <1>;
98 #size-cells = <1>; 100 #size-cells = <1>;
99 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; 101 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
100 reg-names = "gpmi-nand", "bch"; 102 reg-names = "gpmi-nand", "bch";
101 interrupts = <88>, <41>; 103 interrupts = <41>;
102 interrupt-names = "gpmi-dma", "bch"; 104 interrupt-names = "bch";
103 clocks = <&clks 50>; 105 clocks = <&clks 50>;
104 clock-names = "gpmi_io"; 106 clock-names = "gpmi_io";
105 dmas = <&dma_apbh 4>; 107 dmas = <&dma_apbh 4>;
106 dma-names = "rx-tx"; 108 dma-names = "rx-tx";
107 fsl,gpmi-dma-channel = <4>;
108 status = "disabled"; 109 status = "disabled";
109 }; 110 };
110 111
@@ -112,11 +113,10 @@
112 #address-cells = <1>; 113 #address-cells = <1>;
113 #size-cells = <0>; 114 #size-cells = <0>;
114 reg = <0x80010000 0x2000>; 115 reg = <0x80010000 0x2000>;
115 interrupts = <96 82>; 116 interrupts = <96>;
116 clocks = <&clks 46>; 117 clocks = <&clks 46>;
117 dmas = <&dma_apbh 0>; 118 dmas = <&dma_apbh 0>;
118 dma-names = "rx-tx"; 119 dma-names = "rx-tx";
119 fsl,ssp-dma-channel = <0>;
120 status = "disabled"; 120 status = "disabled";
121 }; 121 };
122 122
@@ -124,11 +124,10 @@
124 #address-cells = <1>; 124 #address-cells = <1>;
125 #size-cells = <0>; 125 #size-cells = <0>;
126 reg = <0x80012000 0x2000>; 126 reg = <0x80012000 0x2000>;
127 interrupts = <97 83>; 127 interrupts = <97>;
128 clocks = <&clks 47>; 128 clocks = <&clks 47>;
129 dmas = <&dma_apbh 1>; 129 dmas = <&dma_apbh 1>;
130 dma-names = "rx-tx"; 130 dma-names = "rx-tx";
131 fsl,ssp-dma-channel = <1>;
132 status = "disabled"; 131 status = "disabled";
133 }; 132 };
134 133
@@ -136,11 +135,10 @@
136 #address-cells = <1>; 135 #address-cells = <1>;
137 #size-cells = <0>; 136 #size-cells = <0>;
138 reg = <0x80014000 0x2000>; 137 reg = <0x80014000 0x2000>;
139 interrupts = <98 84>; 138 interrupts = <98>;
140 clocks = <&clks 48>; 139 clocks = <&clks 48>;
141 dmas = <&dma_apbh 2>; 140 dmas = <&dma_apbh 2>;
142 dma-names = "rx-tx"; 141 dma-names = "rx-tx";
143 fsl,ssp-dma-channel = <2>;
144 status = "disabled"; 142 status = "disabled";
145 }; 143 };
146 144
@@ -148,15 +146,14 @@
148 #address-cells = <1>; 146 #address-cells = <1>;
149 #size-cells = <0>; 147 #size-cells = <0>;
150 reg = <0x80016000 0x2000>; 148 reg = <0x80016000 0x2000>;
151 interrupts = <99 85>; 149 interrupts = <99>;
152 clocks = <&clks 49>; 150 clocks = <&clks 49>;
153 dmas = <&dma_apbh 3>; 151 dmas = <&dma_apbh 3>;
154 dma-names = "rx-tx"; 152 dma-names = "rx-tx";
155 fsl,ssp-dma-channel = <3>;
156 status = "disabled"; 153 status = "disabled";
157 }; 154 };
158 155
159 pinctrl@80018000 { 156 pinctrl: pinctrl@80018000 {
160 #address-cells = <1>; 157 #address-cells = <1>;
161 #size-cells = <0>; 158 #size-cells = <0>;
162 compatible = "fsl,imx28-pinctrl", "simple-bus"; 159 compatible = "fsl,imx28-pinctrl", "simple-bus";
@@ -521,6 +518,18 @@
521 fsl,pull-up = <1>; 518 fsl,pull-up = <1>;
522 }; 519 };
523 520
521 saif0_pins_b: saif0@1 {
522 reg = <1>;
523 fsl,pinmux-ids = <
524 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
525 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
526 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
527 >;
528 fsl,drive-strength = <2>;
529 fsl,voltage = <1>;
530 fsl,pull-up = <1>;
531 };
532
524 saif1_pins_a: saif1@0 { 533 saif1_pins_a: saif1@0 {
525 reg = <0>; 534 reg = <0>;
526 fsl,pinmux-ids = < 535 fsl,pinmux-ids = <
@@ -639,6 +648,19 @@
639 fsl,pull-up = <0>; 648 fsl,pull-up = <0>;
640 }; 649 };
641 650
651 lcdif_sync_pins_a: lcdif-sync@0 {
652 reg = <0>;
653 fsl,pinmux-ids = <
654 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
655 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
656 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
657 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
658 >;
659 fsl,drive-strength = <0>;
660 fsl,voltage = <1>;
661 fsl,pull-up = <0>;
662 };
663
642 can0_pins_a: can0@0 { 664 can0_pins_a: can0@0 {
643 reg = <0>; 665 reg = <0>;
644 fsl,pinmux-ids = < 666 fsl,pinmux-ids = <
@@ -674,6 +696,21 @@
674 fsl,pull-up = <1>; 696 fsl,pull-up = <1>;
675 }; 697 };
676 698
699 spi3_pins_a: spi3@0 {
700 reg = <0>;
701 fsl,pinmux-ids = <
702 0x3082 /* MX28_PAD_AUART2_RX__SSP3_D4 */
703 0x3092 /* MX28_PAD_AUART2_TX__SSP3_D5 */
704 0x2180 /* MX28_PAD_SSP3_SCK__SSP3_SCK */
705 0x2190 /* MX28_PAD_SSP3_MOSI__SSP3_CMD */
706 0x21A0 /* MX28_PAD_SSP3_MISO__SSP3_D0 */
707 0x21B0 /* MX28_PAD_SSP3_SS0__SSP3_D3 */
708 >;
709 fsl,drive-strength = <1>;
710 fsl,voltage = <1>;
711 fsl,pull-up = <0>;
712 };
713
677 usbphy0_pins_a: usbphy0@0 { 714 usbphy0_pins_a: usbphy0@0 {
678 reg = <0>; 715 reg = <0>;
679 fsl,pinmux-ids = < 716 fsl,pinmux-ids = <
@@ -705,14 +742,14 @@
705 }; 742 };
706 }; 743 };
707 744
708 digctl@8001c000 { 745 digctl: digctl@8001c000 {
709 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl"; 746 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
710 reg = <0x8001c000 0x2000>; 747 reg = <0x8001c000 0x2000>;
711 interrupts = <89>; 748 interrupts = <89>;
712 status = "disabled"; 749 status = "disabled";
713 }; 750 };
714 751
715 etm@80022000 { 752 etm: etm@80022000 {
716 reg = <0x80022000 0x2000>; 753 reg = <0x80022000 0x2000>;
717 status = "disabled"; 754 status = "disabled";
718 }; 755 };
@@ -733,19 +770,19 @@
733 clocks = <&clks 26>; 770 clocks = <&clks 26>;
734 }; 771 };
735 772
736 dcp@80028000 { 773 dcp: dcp@80028000 {
737 reg = <0x80028000 0x2000>; 774 reg = <0x80028000 0x2000>;
738 interrupts = <52 53 54>; 775 interrupts = <52 53 54>;
739 compatible = "fsl-dcp"; 776 compatible = "fsl-dcp";
740 }; 777 };
741 778
742 pxp@8002a000 { 779 pxp: pxp@8002a000 {
743 reg = <0x8002a000 0x2000>; 780 reg = <0x8002a000 0x2000>;
744 interrupts = <39>; 781 interrupts = <39>;
745 status = "disabled"; 782 status = "disabled";
746 }; 783 };
747 784
748 ocotp@8002c000 { 785 ocotp: ocotp@8002c000 {
749 compatible = "fsl,ocotp"; 786 compatible = "fsl,ocotp";
750 reg = <0x8002c000 0x2000>; 787 reg = <0x8002c000 0x2000>;
751 status = "disabled"; 788 status = "disabled";
@@ -756,10 +793,10 @@
756 status = "disabled"; 793 status = "disabled";
757 }; 794 };
758 795
759 lcdif@80030000 { 796 lcdif: lcdif@80030000 {
760 compatible = "fsl,imx28-lcdif"; 797 compatible = "fsl,imx28-lcdif";
761 reg = <0x80030000 0x2000>; 798 reg = <0x80030000 0x2000>;
762 interrupts = <38 86>; 799 interrupts = <38>;
763 clocks = <&clks 55>; 800 clocks = <&clks 55>;
764 dmas = <&dma_apbh 13>; 801 dmas = <&dma_apbh 13>;
765 dma-names = "rx"; 802 dma-names = "rx";
@@ -784,41 +821,41 @@
784 status = "disabled"; 821 status = "disabled";
785 }; 822 };
786 823
787 simdbg@8003c000 { 824 simdbg: simdbg@8003c000 {
788 reg = <0x8003c000 0x200>; 825 reg = <0x8003c000 0x200>;
789 status = "disabled"; 826 status = "disabled";
790 }; 827 };
791 828
792 simgpmisel@8003c200 { 829 simgpmisel: simgpmisel@8003c200 {
793 reg = <0x8003c200 0x100>; 830 reg = <0x8003c200 0x100>;
794 status = "disabled"; 831 status = "disabled";
795 }; 832 };
796 833
797 simsspsel@8003c300 { 834 simsspsel: simsspsel@8003c300 {
798 reg = <0x8003c300 0x100>; 835 reg = <0x8003c300 0x100>;
799 status = "disabled"; 836 status = "disabled";
800 }; 837 };
801 838
802 simmemsel@8003c400 { 839 simmemsel: simmemsel@8003c400 {
803 reg = <0x8003c400 0x100>; 840 reg = <0x8003c400 0x100>;
804 status = "disabled"; 841 status = "disabled";
805 }; 842 };
806 843
807 gpiomon@8003c500 { 844 gpiomon: gpiomon@8003c500 {
808 reg = <0x8003c500 0x100>; 845 reg = <0x8003c500 0x100>;
809 status = "disabled"; 846 status = "disabled";
810 }; 847 };
811 848
812 simenet@8003c700 { 849 simenet: simenet@8003c700 {
813 reg = <0x8003c700 0x100>; 850 reg = <0x8003c700 0x100>;
814 status = "disabled"; 851 status = "disabled";
815 }; 852 };
816 853
817 armjtag@8003c800 { 854 armjtag: armjtag@8003c800 {
818 reg = <0x8003c800 0x100>; 855 reg = <0x8003c800 0x100>;
819 status = "disabled"; 856 status = "disabled";
820 }; 857 };
821 }; 858 };
822 859
823 apbx@80040000 { 860 apbx@80040000 {
824 compatible = "simple-bus"; 861 compatible = "simple-bus";
@@ -836,16 +873,15 @@
836 saif0: saif@80042000 { 873 saif0: saif@80042000 {
837 compatible = "fsl,imx28-saif"; 874 compatible = "fsl,imx28-saif";
838 reg = <0x80042000 0x2000>; 875 reg = <0x80042000 0x2000>;
839 interrupts = <59 80>; 876 interrupts = <59>;
840 #clock-cells = <0>; 877 #clock-cells = <0>;
841 clocks = <&clks 53>; 878 clocks = <&clks 53>;
842 dmas = <&dma_apbx 4>; 879 dmas = <&dma_apbx 4>;
843 dma-names = "rx-tx"; 880 dma-names = "rx-tx";
844 fsl,saif-dma-channel = <4>;
845 status = "disabled"; 881 status = "disabled";
846 }; 882 };
847 883
848 power@80044000 { 884 power: power@80044000 {
849 reg = <0x80044000 0x2000>; 885 reg = <0x80044000 0x2000>;
850 status = "disabled"; 886 status = "disabled";
851 }; 887 };
@@ -853,15 +889,14 @@
853 saif1: saif@80046000 { 889 saif1: saif@80046000 {
854 compatible = "fsl,imx28-saif"; 890 compatible = "fsl,imx28-saif";
855 reg = <0x80046000 0x2000>; 891 reg = <0x80046000 0x2000>;
856 interrupts = <58 81>; 892 interrupts = <58>;
857 clocks = <&clks 54>; 893 clocks = <&clks 54>;
858 dmas = <&dma_apbx 5>; 894 dmas = <&dma_apbx 5>;
859 dma-names = "rx-tx"; 895 dma-names = "rx-tx";
860 fsl,saif-dma-channel = <5>;
861 status = "disabled"; 896 status = "disabled";
862 }; 897 };
863 898
864 lradc@80050000 { 899 lradc: lradc@80050000 {
865 compatible = "fsl,imx28-lradc"; 900 compatible = "fsl,imx28-lradc";
866 reg = <0x80050000 0x2000>; 901 reg = <0x80050000 0x2000>;
867 interrupts = <10 14 15 16 17 18 19 902 interrupts = <10 14 15 16 17 18 19
@@ -869,15 +904,15 @@
869 status = "disabled"; 904 status = "disabled";
870 }; 905 };
871 906
872 spdif@80054000 { 907 spdif: spdif@80054000 {
873 reg = <0x80054000 0x2000>; 908 reg = <0x80054000 0x2000>;
874 interrupts = <45 66>; 909 interrupts = <45>;
875 dmas = <&dma_apbx 2>; 910 dmas = <&dma_apbx 2>;
876 dma-names = "tx"; 911 dma-names = "tx";
877 status = "disabled"; 912 status = "disabled";
878 }; 913 };
879 914
880 rtc@80056000 { 915 mxs_rtc: rtc@80056000 {
881 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; 916 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
882 reg = <0x80056000 0x2000>; 917 reg = <0x80056000 0x2000>;
883 interrupts = <29>; 918 interrupts = <29>;
@@ -888,11 +923,10 @@
888 #size-cells = <0>; 923 #size-cells = <0>;
889 compatible = "fsl,imx28-i2c"; 924 compatible = "fsl,imx28-i2c";
890 reg = <0x80058000 0x2000>; 925 reg = <0x80058000 0x2000>;
891 interrupts = <111 68>; 926 interrupts = <111>;
892 clock-frequency = <100000>; 927 clock-frequency = <100000>;
893 dmas = <&dma_apbx 6>; 928 dmas = <&dma_apbx 6>;
894 dma-names = "rx-tx"; 929 dma-names = "rx-tx";
895 fsl,i2c-dma-channel = <6>;
896 status = "disabled"; 930 status = "disabled";
897 }; 931 };
898 932
@@ -901,11 +935,10 @@
901 #size-cells = <0>; 935 #size-cells = <0>;
902 compatible = "fsl,imx28-i2c"; 936 compatible = "fsl,imx28-i2c";
903 reg = <0x8005a000 0x2000>; 937 reg = <0x8005a000 0x2000>;
904 interrupts = <110 69>; 938 interrupts = <110>;
905 clock-frequency = <100000>; 939 clock-frequency = <100000>;
906 dmas = <&dma_apbx 7>; 940 dmas = <&dma_apbx 7>;
907 dma-names = "rx-tx"; 941 dma-names = "rx-tx";
908 fsl,i2c-dma-channel = <7>;
909 status = "disabled"; 942 status = "disabled";
910 }; 943 };
911 944
@@ -918,7 +951,7 @@
918 status = "disabled"; 951 status = "disabled";
919 }; 952 };
920 953
921 timrot@80068000 { 954 timer: timrot@80068000 {
922 compatible = "fsl,imx28-timrot", "fsl,timrot"; 955 compatible = "fsl,imx28-timrot", "fsl,timrot";
923 reg = <0x80068000 0x2000>; 956 reg = <0x80068000 0x2000>;
924 interrupts = <48 49 50 51>; 957 interrupts = <48 49 50 51>;
@@ -928,10 +961,9 @@
928 auart0: serial@8006a000 { 961 auart0: serial@8006a000 {
929 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 962 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
930 reg = <0x8006a000 0x2000>; 963 reg = <0x8006a000 0x2000>;
931 interrupts = <112 70 71>; 964 interrupts = <112>;
932 dmas = <&dma_apbx 8>, <&dma_apbx 9>; 965 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
933 dma-names = "rx", "tx"; 966 dma-names = "rx", "tx";
934 fsl,auart-dma-channel = <8 9>;
935 clocks = <&clks 45>; 967 clocks = <&clks 45>;
936 status = "disabled"; 968 status = "disabled";
937 }; 969 };
@@ -939,7 +971,7 @@
939 auart1: serial@8006c000 { 971 auart1: serial@8006c000 {
940 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 972 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
941 reg = <0x8006c000 0x2000>; 973 reg = <0x8006c000 0x2000>;
942 interrupts = <113 72 73>; 974 interrupts = <113>;
943 dmas = <&dma_apbx 10>, <&dma_apbx 11>; 975 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
944 dma-names = "rx", "tx"; 976 dma-names = "rx", "tx";
945 clocks = <&clks 45>; 977 clocks = <&clks 45>;
@@ -949,7 +981,7 @@
949 auart2: serial@8006e000 { 981 auart2: serial@8006e000 {
950 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 982 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
951 reg = <0x8006e000 0x2000>; 983 reg = <0x8006e000 0x2000>;
952 interrupts = <114 74 75>; 984 interrupts = <114>;
953 dmas = <&dma_apbx 12>, <&dma_apbx 13>; 985 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
954 dma-names = "rx", "tx"; 986 dma-names = "rx", "tx";
955 clocks = <&clks 45>; 987 clocks = <&clks 45>;
@@ -959,7 +991,7 @@
959 auart3: serial@80070000 { 991 auart3: serial@80070000 {
960 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 992 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
961 reg = <0x80070000 0x2000>; 993 reg = <0x80070000 0x2000>;
962 interrupts = <115 76 77>; 994 interrupts = <115>;
963 dmas = <&dma_apbx 14>, <&dma_apbx 15>; 995 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
964 dma-names = "rx", "tx"; 996 dma-names = "rx", "tx";
965 clocks = <&clks 45>; 997 clocks = <&clks 45>;
@@ -969,7 +1001,7 @@
969 auart4: serial@80072000 { 1001 auart4: serial@80072000 {
970 compatible = "fsl,imx28-auart", "fsl,imx23-auart"; 1002 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
971 reg = <0x80072000 0x2000>; 1003 reg = <0x80072000 0x2000>;
972 interrupts = <116 78 79>; 1004 interrupts = <116>;
973 dmas = <&dma_apbx 0>, <&dma_apbx 1>; 1005 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
974 dma-names = "rx", "tx"; 1006 dma-names = "rx", "tx";
975 clocks = <&clks 45>; 1007 clocks = <&clks 45>;
@@ -1026,7 +1058,7 @@
1026 status = "disabled"; 1058 status = "disabled";
1027 }; 1059 };
1028 1060
1029 dflpt@800c0000 { 1061 dflpt: dflpt@800c0000 {
1030 reg = <0x800c0000 0x10000>; 1062 reg = <0x800c0000 0x10000>;
1031 status = "disabled"; 1063 status = "disabled";
1032 }; 1064 };
@@ -1049,10 +1081,9 @@
1049 status = "disabled"; 1081 status = "disabled";
1050 }; 1082 };
1051 1083
1052 switch@800f8000 { 1084 etn_switch: switch@800f8000 {
1053 reg = <0x800f8000 0x8000>; 1085 reg = <0x800f8000 0x8000>;
1054 status = "disabled"; 1086 status = "disabled";
1055 }; 1087 };
1056
1057 }; 1088 };
1058}; 1089};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index c5449257ad9a..c34f82581248 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -20,6 +20,16 @@
20 serial4 = &uart5; 20 serial4 = &uart5;
21 }; 21 };
22 22
23 cpus {
24 #address-cells = <0>;
25 #size-cells = <0>;
26
27 cpu {
28 compatible = "arm,arm1136";
29 device_type = "cpu";
30 };
31 };
32
23 avic: avic-interrupt-controller@60000000 { 33 avic: avic-interrupt-controller@60000000 {
24 compatible = "fsl,imx31-avic", "fsl,avic"; 34 compatible = "fsl,imx31-avic", "fsl,avic";
25 interrupt-controller; 35 interrupt-controller;
@@ -94,6 +104,13 @@
94 status = "disabled"; 104 status = "disabled";
95 }; 105 };
96 106
107 iim: iim@5001c000 {
108 compatible = "fsl,imx31-iim", "fsl,imx27-iim";
109 reg = <0x5001c000 0x1000>;
110 interrupts = <19>;
111 clocks = <&clks 25>;
112 };
113
97 clks: ccm@53f80000{ 114 clks: ccm@53f80000{
98 compatible = "fsl,imx31-ccm"; 115 compatible = "fsl,imx31-ccm";
99 reg = <0x53f80000 0x4000>; 116 reg = <0x53f80000 0x4000>;
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index 8f7f9ac0b989..b3606993f2e8 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -26,10 +26,6 @@
26 }; 26 };
27 27
28 clocks { 28 clocks {
29 ckih1 {
30 clock-frequency = <0>;
31 };
32
33 osc { 29 osc {
34 clock-frequency = <33554432>; 30 clock-frequency = <33554432>;
35 }; 31 };
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index ad3471ca17c7..1d337d99ecd5 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -63,6 +63,10 @@
63 }; 63 };
64 64
65 clocks { 65 clocks {
66 ckih1 {
67 clock-frequency = <22579200>;
68 };
69
66 clk_26M: codec_clock { 70 clk_26M: codec_clock {
67 compatible = "fixed-clock"; 71 compatible = "fixed-clock";
68 reg=<0>; 72 reg=<0>;
@@ -108,6 +112,7 @@
108 #size-cells = <0>; 112 #size-cells = <0>;
109 compatible = "fsl,mc13892"; 113 compatible = "fsl,mc13892";
110 spi-max-frequency = <6000000>; 114 spi-max-frequency = <6000000>;
115 spi-cs-high;
111 reg = <0>; 116 reg = <0>;
112 interrupt-parent = <&gpio1>; 117 interrupt-parent = <&gpio1>;
113 interrupts = <8 0x4>; 118 interrupts = <8 0x4>;
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 25764b505a61..a85abb424c34 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -15,13 +15,18 @@
15 15
16/ { 16/ {
17 aliases { 17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 gpio0 = &gpio1; 18 gpio0 = &gpio1;
22 gpio1 = &gpio2; 19 gpio1 = &gpio2;
23 gpio2 = &gpio3; 20 gpio2 = &gpio3;
24 gpio3 = &gpio4; 21 gpio3 = &gpio4;
22 i2c0 = &i2c1;
23 i2c1 = &i2c2;
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 spi0 = &ecspi1;
28 spi1 = &ecspi2;
29 spi2 = &cspi;
25 }; 30 };
26 31
27 tzic: tz-interrupt-controller@e0000000 { 32 tzic: tz-interrupt-controller@e0000000 {
@@ -42,7 +47,7 @@
42 47
43 ckih1 { 48 ckih1 {
44 compatible = "fsl,imx-ckih1", "fixed-clock"; 49 compatible = "fsl,imx-ckih1", "fixed-clock";
45 clock-frequency = <22579200>; 50 clock-frequency = <0>;
46 }; 51 };
47 52
48 ckih2 { 53 ckih2 {
@@ -149,6 +154,9 @@
149 reg = <0x70014000 0x4000>; 154 reg = <0x70014000 0x4000>;
150 interrupts = <30>; 155 interrupts = <30>;
151 clocks = <&clks 49>; 156 clocks = <&clks 49>;
157 dmas = <&sdma 24 1 0>,
158 <&sdma 25 1 0>;
159 dma-names = "rx", "tx";
152 fsl,fifo-depth = <15>; 160 fsl,fifo-depth = <15>;
153 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 161 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
154 status = "disabled"; 162 status = "disabled";
@@ -300,275 +308,6 @@
300 iomuxc: iomuxc@73fa8000 { 308 iomuxc: iomuxc@73fa8000 {
301 compatible = "fsl,imx51-iomuxc"; 309 compatible = "fsl,imx51-iomuxc";
302 reg = <0x73fa8000 0x4000>; 310 reg = <0x73fa8000 0x4000>;
303
304 audmux {
305 pinctrl_audmux_1: audmuxgrp-1 {
306 fsl,pins = <
307 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
308 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
309 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
310 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
311 >;
312 };
313 };
314
315 fec {
316 pinctrl_fec_1: fecgrp-1 {
317 fsl,pins = <
318 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
319 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
320 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
321 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
322 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
323 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
324 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
325 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
326 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
327 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
328 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
329 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
330 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
331 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
332 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
333 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
334 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
335 >;
336 };
337
338 pinctrl_fec_2: fecgrp-2 {
339 fsl,pins = <
340 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
341 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
342 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
343 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
344 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
345 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
346 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
347 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
348 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
349 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
350 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
351 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
352 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
353 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
354 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
355 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
356 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
357 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
358 >;
359 };
360 };
361
362 ecspi1 {
363 pinctrl_ecspi1_1: ecspi1grp-1 {
364 fsl,pins = <
365 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
366 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
367 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
368 >;
369 };
370 };
371
372 ecspi2 {
373 pinctrl_ecspi2_1: ecspi2grp-1 {
374 fsl,pins = <
375 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
376 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
377 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
378 >;
379 };
380 };
381
382 esdhc1 {
383 pinctrl_esdhc1_1: esdhc1grp-1 {
384 fsl,pins = <
385 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
386 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
387 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
388 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
389 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
390 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
391 >;
392 };
393 };
394
395 esdhc2 {
396 pinctrl_esdhc2_1: esdhc2grp-1 {
397 fsl,pins = <
398 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
399 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
400 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
401 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
402 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
403 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
404 >;
405 };
406 };
407
408 i2c2 {
409 pinctrl_i2c2_1: i2c2grp-1 {
410 fsl,pins = <
411 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
412 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
413 >;
414 };
415
416 pinctrl_i2c2_2: i2c2grp-2 {
417 fsl,pins = <
418 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
419 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
420 >;
421 };
422 };
423
424 ipu_disp1 {
425 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
426 fsl,pins = <
427 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
428 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
429 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
430 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
431 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
432 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
433 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
434 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
435 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
436 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
437 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
438 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
439 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
440 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
441 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
442 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
443 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
444 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
445 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
446 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
447 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
448 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
449 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
450 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
451 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
452 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
453 >;
454 };
455 };
456
457 ipu_disp2 {
458 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
459 fsl,pins = <
460 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
461 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
462 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
463 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
464 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
465 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
466 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
467 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
468 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
469 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
470 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
471 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
472 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
473 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
474 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
475 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
476 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
477 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
478 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
479 MX51_PAD_DI_GP4__DI2_PIN15 0x5
480 >;
481 };
482 };
483
484 pata {
485 pinctrl_pata_1: patagrp-1 {
486 fsl,pins = <
487 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
488 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
489 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
490 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
491 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
492 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
493 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
494 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
495 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
496 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
497 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
498 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
499 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
500 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
501 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
502 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
503 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
504 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
505 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
506 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
507 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
508 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
509 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
510 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
511 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
512 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
513 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
514 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
515 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
516 >;
517 };
518 };
519
520 uart1 {
521 pinctrl_uart1_1: uart1grp-1 {
522 fsl,pins = <
523 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
524 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
525 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
526 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
527 >;
528 };
529 };
530
531 uart2 {
532 pinctrl_uart2_1: uart2grp-1 {
533 fsl,pins = <
534 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
535 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
536 >;
537 };
538 };
539
540 uart3 {
541 pinctrl_uart3_1: uart3grp-1 {
542 fsl,pins = <
543 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
544 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
545 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
546 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
547 >;
548 };
549
550 pinctrl_uart3_2: uart3grp-2 {
551 fsl,pins = <
552 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
553 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
554 >;
555 };
556 };
557
558 kpp {
559 pinctrl_kpp_1: kppgrp-1 {
560 fsl,pins = <
561 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
562 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
563 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
564 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
565 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
566 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
567 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
568 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
569 >;
570 };
571 };
572 }; 311 };
573 312
574 pwm1: pwm@73fb4000 { 313 pwm1: pwm@73fb4000 {
@@ -628,6 +367,13 @@
628 reg = <0x80000000 0x10000000>; 367 reg = <0x80000000 0x10000000>;
629 ranges; 368 ranges;
630 369
370 iim: iim@83f98000 {
371 compatible = "fsl,imx51-iim", "fsl,imx27-iim";
372 reg = <0x83f98000 0x4000>;
373 interrupts = <69>;
374 clocks = <&clks 107>;
375 };
376
631 ecspi2: ecspi@83fac000 { 377 ecspi2: ecspi@83fac000 {
632 #address-cells = <1>; 378 #address-cells = <1>;
633 #size-cells = <0>; 379 #size-cells = <0>;
@@ -645,6 +391,7 @@
645 interrupts = <6>; 391 interrupts = <6>;
646 clocks = <&clks 56>, <&clks 56>; 392 clocks = <&clks 56>, <&clks 56>;
647 clock-names = "ipg", "ahb"; 393 clock-names = "ipg", "ahb";
394 #dma-cells = <3>;
648 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 395 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
649 }; 396 };
650 397
@@ -684,6 +431,9 @@
684 reg = <0x83fcc000 0x4000>; 431 reg = <0x83fcc000 0x4000>;
685 interrupts = <29>; 432 interrupts = <29>;
686 clocks = <&clks 48>; 433 clocks = <&clks 48>;
434 dmas = <&sdma 28 0 0>,
435 <&sdma 29 0 0>;
436 dma-names = "rx", "tx";
687 fsl,fifo-depth = <15>; 437 fsl,fifo-depth = <15>;
688 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 438 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
689 status = "disabled"; 439 status = "disabled";
@@ -695,6 +445,23 @@
695 status = "disabled"; 445 status = "disabled";
696 }; 446 };
697 447
448 weim: weim@83fda000 {
449 #address-cells = <2>;
450 #size-cells = <1>;
451 compatible = "fsl,imx51-weim";
452 reg = <0x83fda000 0x1000>;
453 clocks = <&clks 57>;
454 ranges = <
455 0 0 0xb0000000 0x08000000
456 1 0 0xb8000000 0x08000000
457 2 0 0xc0000000 0x08000000
458 3 0 0xc8000000 0x04000000
459 4 0 0xcc000000 0x02000000
460 5 0 0xce000000 0x02000000
461 >;
462 status = "disabled";
463 };
464
698 nfc: nand@83fdb000 { 465 nfc: nand@83fdb000 {
699 compatible = "fsl,imx51-nand"; 466 compatible = "fsl,imx51-nand";
700 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 467 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
@@ -716,6 +483,9 @@
716 reg = <0x83fe8000 0x4000>; 483 reg = <0x83fe8000 0x4000>;
717 interrupts = <96>; 484 interrupts = <96>;
718 clocks = <&clks 50>; 485 clocks = <&clks 50>;
486 dmas = <&sdma 46 0 0>,
487 <&sdma 47 0 0>;
488 dma-names = "rx", "tx";
719 fsl,fifo-depth = <15>; 489 fsl,fifo-depth = <15>;
720 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ 490 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
721 status = "disabled"; 491 status = "disabled";
@@ -732,3 +502,319 @@
732 }; 502 };
733 }; 503 };
734}; 504};
505
506&iomuxc {
507 audmux {
508 pinctrl_audmux_1: audmuxgrp-1 {
509 fsl,pins = <
510 MX51_PAD_AUD3_BB_TXD__AUD3_TXD 0x80000000
511 MX51_PAD_AUD3_BB_RXD__AUD3_RXD 0x80000000
512 MX51_PAD_AUD3_BB_CK__AUD3_TXC 0x80000000
513 MX51_PAD_AUD3_BB_FS__AUD3_TXFS 0x80000000
514 >;
515 };
516 };
517
518 fec {
519 pinctrl_fec_1: fecgrp-1 {
520 fsl,pins = <
521 MX51_PAD_EIM_EB2__FEC_MDIO 0x80000000
522 MX51_PAD_EIM_EB3__FEC_RDATA1 0x80000000
523 MX51_PAD_EIM_CS2__FEC_RDATA2 0x80000000
524 MX51_PAD_EIM_CS3__FEC_RDATA3 0x80000000
525 MX51_PAD_EIM_CS4__FEC_RX_ER 0x80000000
526 MX51_PAD_EIM_CS5__FEC_CRS 0x80000000
527 MX51_PAD_NANDF_RB2__FEC_COL 0x80000000
528 MX51_PAD_NANDF_RB3__FEC_RX_CLK 0x80000000
529 MX51_PAD_NANDF_D9__FEC_RDATA0 0x80000000
530 MX51_PAD_NANDF_D8__FEC_TDATA0 0x80000000
531 MX51_PAD_NANDF_CS2__FEC_TX_ER 0x80000000
532 MX51_PAD_NANDF_CS3__FEC_MDC 0x80000000
533 MX51_PAD_NANDF_CS4__FEC_TDATA1 0x80000000
534 MX51_PAD_NANDF_CS5__FEC_TDATA2 0x80000000
535 MX51_PAD_NANDF_CS6__FEC_TDATA3 0x80000000
536 MX51_PAD_NANDF_CS7__FEC_TX_EN 0x80000000
537 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK 0x80000000
538 >;
539 };
540
541 pinctrl_fec_2: fecgrp-2 {
542 fsl,pins = <
543 MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
544 MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
545 MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
546 MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
547 MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
548 MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
549 MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
550 MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
551 MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
552 MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
553 MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
554 MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
555 MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
556 MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
557 MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
558 MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
559 MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
560 MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
561 >;
562 };
563 };
564
565 ecspi1 {
566 pinctrl_ecspi1_1: ecspi1grp-1 {
567 fsl,pins = <
568 MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
569 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
570 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
571 >;
572 };
573 };
574
575 ecspi2 {
576 pinctrl_ecspi2_1: ecspi2grp-1 {
577 fsl,pins = <
578 MX51_PAD_NANDF_RB3__ECSPI2_MISO 0x185
579 MX51_PAD_NANDF_D15__ECSPI2_MOSI 0x185
580 MX51_PAD_NANDF_RB2__ECSPI2_SCLK 0x185
581 >;
582 };
583 };
584
585 esdhc1 {
586 pinctrl_esdhc1_1: esdhc1grp-1 {
587 fsl,pins = <
588 MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
589 MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
590 MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
591 MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
592 MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
593 MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
594 >;
595 };
596 };
597
598 esdhc2 {
599 pinctrl_esdhc2_1: esdhc2grp-1 {
600 fsl,pins = <
601 MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
602 MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
603 MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
604 MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
605 MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
606 MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
607 >;
608 };
609 };
610
611 i2c2 {
612 pinctrl_i2c2_1: i2c2grp-1 {
613 fsl,pins = <
614 MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
615 MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
616 >;
617 };
618
619 pinctrl_i2c2_2: i2c2grp-2 {
620 fsl,pins = <
621 MX51_PAD_EIM_D27__I2C2_SCL 0x400001ed
622 MX51_PAD_EIM_D24__I2C2_SDA 0x400001ed
623 >;
624 };
625
626 pinctrl_i2c2_3: i2c2grp-3 {
627 fsl,pins = <
628 MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
629 MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
630 >;
631 };
632 };
633
634 ipu_disp1 {
635 pinctrl_ipu_disp1_1: ipudisp1grp-1 {
636 fsl,pins = <
637 MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
638 MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
639 MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
640 MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
641 MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
642 MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
643 MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
644 MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
645 MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
646 MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
647 MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
648 MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
649 MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
650 MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
651 MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
652 MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
653 MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
654 MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
655 MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
656 MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
657 MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
658 MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
659 MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
660 MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
661 MX51_PAD_DI1_PIN2__DI1_PIN2 0x5 /* hsync */
662 MX51_PAD_DI1_PIN3__DI1_PIN3 0x5 /* vsync */
663 >;
664 };
665 };
666
667 ipu_disp2 {
668 pinctrl_ipu_disp2_1: ipudisp2grp-1 {
669 fsl,pins = <
670 MX51_PAD_DISP2_DAT0__DISP2_DAT0 0x5
671 MX51_PAD_DISP2_DAT1__DISP2_DAT1 0x5
672 MX51_PAD_DISP2_DAT2__DISP2_DAT2 0x5
673 MX51_PAD_DISP2_DAT3__DISP2_DAT3 0x5
674 MX51_PAD_DISP2_DAT4__DISP2_DAT4 0x5
675 MX51_PAD_DISP2_DAT5__DISP2_DAT5 0x5
676 MX51_PAD_DISP2_DAT6__DISP2_DAT6 0x5
677 MX51_PAD_DISP2_DAT7__DISP2_DAT7 0x5
678 MX51_PAD_DISP2_DAT8__DISP2_DAT8 0x5
679 MX51_PAD_DISP2_DAT9__DISP2_DAT9 0x5
680 MX51_PAD_DISP2_DAT10__DISP2_DAT10 0x5
681 MX51_PAD_DISP2_DAT11__DISP2_DAT11 0x5
682 MX51_PAD_DISP2_DAT12__DISP2_DAT12 0x5
683 MX51_PAD_DISP2_DAT13__DISP2_DAT13 0x5
684 MX51_PAD_DISP2_DAT14__DISP2_DAT14 0x5
685 MX51_PAD_DISP2_DAT15__DISP2_DAT15 0x5
686 MX51_PAD_DI2_PIN2__DI2_PIN2 0x5 /* hsync */
687 MX51_PAD_DI2_PIN3__DI2_PIN3 0x5 /* vsync */
688 MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5 /* CLK */
689 MX51_PAD_DI_GP4__DI2_PIN15 0x5 /* DE */
690 >;
691 };
692 };
693
694 kpp {
695 pinctrl_kpp_1: kppgrp-1 {
696 fsl,pins = <
697 MX51_PAD_KEY_ROW0__KEY_ROW0 0xe0
698 MX51_PAD_KEY_ROW1__KEY_ROW1 0xe0
699 MX51_PAD_KEY_ROW2__KEY_ROW2 0xe0
700 MX51_PAD_KEY_ROW3__KEY_ROW3 0xe0
701 MX51_PAD_KEY_COL0__KEY_COL0 0xe8
702 MX51_PAD_KEY_COL1__KEY_COL1 0xe8
703 MX51_PAD_KEY_COL2__KEY_COL2 0xe8
704 MX51_PAD_KEY_COL3__KEY_COL3 0xe8
705 >;
706 };
707 };
708
709 pata {
710 pinctrl_pata_1: patagrp-1 {
711 fsl,pins = <
712 MX51_PAD_NANDF_WE_B__PATA_DIOW 0x2004
713 MX51_PAD_NANDF_RE_B__PATA_DIOR 0x2004
714 MX51_PAD_NANDF_ALE__PATA_BUFFER_EN 0x2004
715 MX51_PAD_NANDF_CLE__PATA_RESET_B 0x2004
716 MX51_PAD_NANDF_WP_B__PATA_DMACK 0x2004
717 MX51_PAD_NANDF_RB0__PATA_DMARQ 0x2004
718 MX51_PAD_NANDF_RB1__PATA_IORDY 0x2004
719 MX51_PAD_GPIO_NAND__PATA_INTRQ 0x2004
720 MX51_PAD_NANDF_CS2__PATA_CS_0 0x2004
721 MX51_PAD_NANDF_CS3__PATA_CS_1 0x2004
722 MX51_PAD_NANDF_CS4__PATA_DA_0 0x2004
723 MX51_PAD_NANDF_CS5__PATA_DA_1 0x2004
724 MX51_PAD_NANDF_CS6__PATA_DA_2 0x2004
725 MX51_PAD_NANDF_D15__PATA_DATA15 0x2004
726 MX51_PAD_NANDF_D14__PATA_DATA14 0x2004
727 MX51_PAD_NANDF_D13__PATA_DATA13 0x2004
728 MX51_PAD_NANDF_D12__PATA_DATA12 0x2004
729 MX51_PAD_NANDF_D11__PATA_DATA11 0x2004
730 MX51_PAD_NANDF_D10__PATA_DATA10 0x2004
731 MX51_PAD_NANDF_D9__PATA_DATA9 0x2004
732 MX51_PAD_NANDF_D8__PATA_DATA8 0x2004
733 MX51_PAD_NANDF_D7__PATA_DATA7 0x2004
734 MX51_PAD_NANDF_D6__PATA_DATA6 0x2004
735 MX51_PAD_NANDF_D5__PATA_DATA5 0x2004
736 MX51_PAD_NANDF_D4__PATA_DATA4 0x2004
737 MX51_PAD_NANDF_D3__PATA_DATA3 0x2004
738 MX51_PAD_NANDF_D2__PATA_DATA2 0x2004
739 MX51_PAD_NANDF_D1__PATA_DATA1 0x2004
740 MX51_PAD_NANDF_D0__PATA_DATA0 0x2004
741 >;
742 };
743 };
744
745 uart1 {
746 pinctrl_uart1_1: uart1grp-1 {
747 fsl,pins = <
748 MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
749 MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
750 MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
751 MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
752 >;
753 };
754 };
755
756 uart2 {
757 pinctrl_uart2_1: uart2grp-1 {
758 fsl,pins = <
759 MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
760 MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
761 >;
762 };
763 };
764
765 uart3 {
766 pinctrl_uart3_1: uart3grp-1 {
767 fsl,pins = <
768 MX51_PAD_EIM_D25__UART3_RXD 0x1c5
769 MX51_PAD_EIM_D26__UART3_TXD 0x1c5
770 MX51_PAD_EIM_D27__UART3_RTS 0x1c5
771 MX51_PAD_EIM_D24__UART3_CTS 0x1c5
772 >;
773 };
774
775 pinctrl_uart3_2: uart3grp-2 {
776 fsl,pins = <
777 MX51_PAD_UART3_RXD__UART3_RXD 0x1c5
778 MX51_PAD_UART3_TXD__UART3_TXD 0x1c5
779 >;
780 };
781 };
782
783 usbh1 {
784 pinctrl_usbh1_1: usbh1grp-1 {
785 fsl,pins = <
786 MX51_PAD_USBH1_DATA0__USBH1_DATA0 0x1e5
787 MX51_PAD_USBH1_DATA1__USBH1_DATA1 0x1e5
788 MX51_PAD_USBH1_DATA2__USBH1_DATA2 0x1e5
789 MX51_PAD_USBH1_DATA3__USBH1_DATA3 0x1e5
790 MX51_PAD_USBH1_DATA4__USBH1_DATA4 0x1e5
791 MX51_PAD_USBH1_DATA5__USBH1_DATA5 0x1e5
792 MX51_PAD_USBH1_DATA6__USBH1_DATA6 0x1e5
793 MX51_PAD_USBH1_DATA7__USBH1_DATA7 0x1e5
794 MX51_PAD_USBH1_CLK__USBH1_CLK 0x1e5
795 MX51_PAD_USBH1_DIR__USBH1_DIR 0x1e5
796 MX51_PAD_USBH1_NXT__USBH1_NXT 0x1e5
797 MX51_PAD_USBH1_STP__USBH1_STP 0x1e5
798 >;
799 };
800 };
801
802 usbh2 {
803 pinctrl_usbh2_1: usbh2grp-1 {
804 fsl,pins = <
805 MX51_PAD_EIM_D16__USBH2_DATA0 0x1e5
806 MX51_PAD_EIM_D17__USBH2_DATA1 0x1e5
807 MX51_PAD_EIM_D18__USBH2_DATA2 0x1e5
808 MX51_PAD_EIM_D19__USBH2_DATA3 0x1e5
809 MX51_PAD_EIM_D20__USBH2_DATA4 0x1e5
810 MX51_PAD_EIM_D21__USBH2_DATA5 0x1e5
811 MX51_PAD_EIM_D22__USBH2_DATA6 0x1e5
812 MX51_PAD_EIM_D23__USBH2_DATA7 0x1e5
813 MX51_PAD_EIM_A24__USBH2_CLK 0x1e5
814 MX51_PAD_EIM_A25__USBH2_DIR 0x1e5
815 MX51_PAD_EIM_A27__USBH2_NXT 0x1e5
816 MX51_PAD_EIM_A26__USBH2_STP 0x1e5
817 >;
818 };
819 };
820};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 512a1f608253..e97ddae09d74 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -93,6 +93,15 @@
93 regulator-max-microvolt = <3200000>; 93 regulator-max-microvolt = <3200000>;
94 regulator-always-on; 94 regulator-always-on;
95 }; 95 };
96
97 reg_usb_vbus: usb_vbus {
98 compatible = "regulator-fixed";
99 regulator-name = "usb_vbus";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 gpio = <&gpio7 8 0>;
103 enable-active-high;
104 };
96 }; 105 };
97 106
98 sound { 107 sound {
@@ -145,6 +154,7 @@
145 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000 154 MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
146 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000 155 MX53_PAD_EIM_DA13__GPIO3_13 0x80000000
147 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000 156 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
157 MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
148 MX53_PAD_GPIO_16__GPIO7_11 0x80000000 158 MX53_PAD_GPIO_16__GPIO7_11 0x80000000
149 >; 159 >;
150 }; 160 };
@@ -297,8 +307,14 @@
297 status = "okay"; 307 status = "okay";
298}; 308};
299 309
310&vpu {
311 status = "okay";
312};
313
300&usbh1 { 314&usbh1 {
301 status = "okay"; 315 vbus-supply = <&reg_usb_vbus>;
316 phy_type = "utmi";
317 status = "okay";
302}; 318};
303 319
304&usbotg { 320&usbotg {
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 569aa9f2c4ed..4307e80b2d2e 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -15,11 +15,6 @@
15 15
16/ { 16/ {
17 aliases { 17 aliases {
18 serial0 = &uart1;
19 serial1 = &uart2;
20 serial2 = &uart3;
21 serial3 = &uart4;
22 serial4 = &uart5;
23 gpio0 = &gpio1; 18 gpio0 = &gpio1;
24 gpio1 = &gpio2; 19 gpio1 = &gpio2;
25 gpio2 = &gpio3; 20 gpio2 = &gpio3;
@@ -30,6 +25,24 @@
30 i2c0 = &i2c1; 25 i2c0 = &i2c1;
31 i2c1 = &i2c2; 26 i2c1 = &i2c2;
32 i2c2 = &i2c3; 27 i2c2 = &i2c3;
28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 spi0 = &ecspi1;
34 spi1 = &ecspi2;
35 spi2 = &cspi;
36 };
37
38 cpus {
39 #address-cells = <1>;
40 #size-cells = <0>;
41 cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a8";
44 reg = <0x0>;
45 };
33 }; 46 };
34 47
35 tzic: tz-interrupt-controller@0fffc000 { 48 tzic: tz-interrupt-controller@0fffc000 {
@@ -140,6 +153,9 @@
140 reg = <0x50014000 0x4000>; 153 reg = <0x50014000 0x4000>;
141 interrupts = <30>; 154 interrupts = <30>;
142 clocks = <&clks 49>; 155 clocks = <&clks 49>;
156 dmas = <&sdma 24 1 0>,
157 <&sdma 25 1 0>;
158 dma-names = "rx", "tx";
143 fsl,fifo-depth = <15>; 159 fsl,fifo-depth = <15>;
144 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ 160 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
145 status = "disabled"; 161 status = "disabled";
@@ -957,6 +973,13 @@
957 reg = <0x60000000 0x10000000>; 973 reg = <0x60000000 0x10000000>;
958 ranges; 974 ranges;
959 975
976 iim: iim@63f98000 {
977 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
978 reg = <0x63f98000 0x4000>;
979 interrupts = <69>;
980 clocks = <&clks 107>;
981 };
982
960 uart5: serial@63f90000 { 983 uart5: serial@63f90000 {
961 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 984 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
962 reg = <0x63f90000 0x4000>; 985 reg = <0x63f90000 0x4000>;
@@ -990,6 +1013,7 @@
990 interrupts = <6>; 1013 interrupts = <6>;
991 clocks = <&clks 56>, <&clks 56>; 1014 clocks = <&clks 56>, <&clks 56>;
992 clock-names = "ipg", "ahb"; 1015 clock-names = "ipg", "ahb";
1016 #dma-cells = <3>;
993 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 1017 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
994 }; 1018 };
995 1019
@@ -1029,6 +1053,9 @@
1029 reg = <0x63fcc000 0x4000>; 1053 reg = <0x63fcc000 0x4000>;
1030 interrupts = <29>; 1054 interrupts = <29>;
1031 clocks = <&clks 48>; 1055 clocks = <&clks 48>;
1056 dmas = <&sdma 28 0 0>,
1057 <&sdma 29 0 0>;
1058 dma-names = "rx", "tx";
1032 fsl,fifo-depth = <15>; 1059 fsl,fifo-depth = <15>;
1033 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ 1060 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
1034 status = "disabled"; 1061 status = "disabled";
@@ -1053,6 +1080,9 @@
1053 reg = <0x63fe8000 0x4000>; 1080 reg = <0x63fe8000 0x4000>;
1054 interrupts = <96>; 1081 interrupts = <96>;
1055 clocks = <&clks 50>; 1082 clocks = <&clks 50>;
1083 dmas = <&sdma 46 0 0>,
1084 <&sdma 47 0 0>;
1085 dma-names = "rx", "tx";
1056 fsl,fifo-depth = <15>; 1086 fsl,fifo-depth = <15>;
1057 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */ 1087 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
1058 status = "disabled"; 1088 status = "disabled";
@@ -1076,6 +1106,22 @@
1076 crtcs = <&ipu 1>; 1106 crtcs = <&ipu 1>;
1077 status = "disabled"; 1107 status = "disabled";
1078 }; 1108 };
1109
1110 vpu: vpu@63ff4000 {
1111 compatible = "fsl,imx53-vpu";
1112 reg = <0x63ff4000 0x1000>;
1113 interrupts = <9>;
1114 clocks = <&clks 63>, <&clks 63>;
1115 clock-names = "per", "ahb";
1116 iram = <&ocram>;
1117 status = "disabled";
1118 };
1119 };
1120
1121 ocram: sram@f8000000 {
1122 compatible = "mmio-sram";
1123 reg = <0xf8000000 0x20000>;
1124 clocks = <&clks 186>;
1079 }; 1125 };
1080 }; 1126 };
1081}; 1127};
diff --git a/arch/arm/boot/dts/imx6dl-pinfunc.h b/arch/arm/boot/dts/imx6dl-pinfunc.h
index 9aab950ec269..b81a7a4ebab6 100644
--- a/arch/arm/boot/dts/imx6dl-pinfunc.h
+++ b/arch/arm/boot/dts/imx6dl-pinfunc.h
@@ -14,1072 +14,1076 @@
14 * The pin function ID is a tuple of 14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val> 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */ 16 */
17#define MX6DL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0 17#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x04c 0x360 0x000 0x0 0x0
18#define MX6DL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0 18#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x04c 0x360 0x000 0x1 0x0
19#define MX6DL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0 19#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x04c 0x360 0x7f8 0x2 0x0
20#define MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0 20#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x04c 0x360 0x000 0x3 0x0
21#define MX6DL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0 21#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x04c 0x360 0x8fc 0x3 0x0
22#define MX6DL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0 22#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x04c 0x360 0x000 0x5 0x0
23#define MX6DL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0 23#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x04c 0x360 0x000 0x7 0x0
24#define MX6DL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0 24#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x050 0x364 0x000 0x0 0x0
25#define MX6DL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0 25#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x050 0x364 0x000 0x1 0x0
26#define MX6DL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0 26#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x050 0x364 0x800 0x2 0x0
27#define MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1 27#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x050 0x364 0x8fc 0x3 0x1
28#define MX6DL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0 28#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x050 0x364 0x000 0x3 0x0
29#define MX6DL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0 29#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x050 0x364 0x000 0x5 0x0
30#define MX6DL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0 30#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x050 0x364 0x000 0x7 0x0
31#define MX6DL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0 31#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x054 0x368 0x000 0x0 0x0
32#define MX6DL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0 32#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x054 0x368 0x000 0x1 0x0
33#define MX6DL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0 33#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x054 0x368 0x000 0x3 0x0
34#define MX6DL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0 34#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x054 0x368 0x914 0x3 0x0
35#define MX6DL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0 35#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x054 0x368 0x000 0x5 0x0
36#define MX6DL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0 36#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x054 0x368 0x000 0x7 0x0
37#define MX6DL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0 37#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x058 0x36c 0x000 0x0 0x0
38#define MX6DL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0 38#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x058 0x36c 0x000 0x1 0x0
39#define MX6DL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1 39#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x058 0x36c 0x914 0x3 0x1
40#define MX6DL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0 40#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x058 0x36c 0x000 0x3 0x0
41#define MX6DL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0 41#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x058 0x36c 0x000 0x5 0x0
42#define MX6DL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0 42#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x058 0x36c 0x000 0x7 0x0
43#define MX6DL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0 43#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x05c 0x370 0x000 0x0 0x0
44#define MX6DL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0 44#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x05c 0x370 0x000 0x1 0x0
45#define MX6DL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0 45#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x05c 0x370 0x000 0x3 0x0
46#define MX6DL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0 46#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x05c 0x370 0x91c 0x3 0x0
47#define MX6DL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0 47#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x05c 0x370 0x000 0x5 0x0
48#define MX6DL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0 48#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x05c 0x370 0x000 0x7 0x0
49#define MX6DL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0 49#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x060 0x374 0x000 0x0 0x0
50#define MX6DL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0 50#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x060 0x374 0x000 0x1 0x0
51#define MX6DL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1 51#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x060 0x374 0x91c 0x3 0x1
52#define MX6DL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0 52#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x060 0x374 0x000 0x3 0x0
53#define MX6DL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0 53#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x060 0x374 0x000 0x5 0x0
54#define MX6DL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0 54#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x060 0x374 0x000 0x7 0x0
55#define MX6DL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0 55#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x064 0x378 0x000 0x0 0x0
56#define MX6DL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0 56#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x064 0x378 0x000 0x1 0x0
57#define MX6DL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0 57#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x064 0x378 0x910 0x3 0x0
58#define MX6DL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0 58#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x064 0x378 0x000 0x3 0x0
59#define MX6DL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0 59#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x064 0x378 0x000 0x5 0x0
60#define MX6DL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0 60#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x064 0x378 0x000 0x7 0x0
61#define MX6DL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0 61#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x068 0x37c 0x000 0x0 0x0
62#define MX6DL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0 62#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x068 0x37c 0x000 0x1 0x0
63#define MX6DL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0 63#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x068 0x37c 0x000 0x3 0x0
64#define MX6DL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1 64#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x068 0x37c 0x910 0x3 0x1
65#define MX6DL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0 65#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x068 0x37c 0x000 0x5 0x0
66#define MX6DL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0 66#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x068 0x37c 0x000 0x7 0x0
67#define MX6DL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0 67#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x06c 0x380 0x000 0x0 0x0
68#define MX6DL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0 68#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x06c 0x380 0x000 0x1 0x0
69#define MX6DL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0 69#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x06c 0x380 0x918 0x3 0x0
70#define MX6DL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0 70#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x06c 0x380 0x000 0x3 0x0
71#define MX6DL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0 71#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x06c 0x380 0x000 0x5 0x0
72#define MX6DL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0 72#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x06c 0x380 0x000 0x7 0x0
73#define MX6DL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0 73#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x070 0x384 0x000 0x0 0x0
74#define MX6DL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0 74#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x070 0x384 0x000 0x1 0x0
75#define MX6DL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0 75#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x070 0x384 0x000 0x3 0x0
76#define MX6DL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1 76#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x070 0x384 0x918 0x3 0x1
77#define MX6DL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0 77#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x070 0x384 0x000 0x5 0x0
78#define MX6DL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0 78#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x074 0x388 0x000 0x0 0x0
79#define MX6DL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0 79#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x074 0x388 0x000 0x1 0x0
80#define MX6DL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0 80#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x074 0x388 0x7d8 0x2 0x0
81#define MX6DL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0 81#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x074 0x388 0x8c0 0x3 0x0
82#define MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0 82#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x074 0x388 0x000 0x4 0x0
83#define MX6DL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0 83#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x074 0x388 0x000 0x5 0x0
84#define MX6DL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0 84#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x074 0x388 0x000 0x7 0x0
85#define MX6DL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0 85#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x078 0x38c 0x000 0x0 0x0
86#define MX6DL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0 86#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x078 0x38c 0x000 0x1 0x0
87#define MX6DL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0 87#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x078 0x38c 0x7e0 0x2 0x0
88#define MX6DL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0 88#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x078 0x38c 0x8cc 0x3 0x0
89#define MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0 89#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x078 0x38c 0x000 0x4 0x0
90#define MX6DL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0 90#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x078 0x38c 0x000 0x5 0x0
91#define MX6DL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0 91#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x078 0x38c 0x000 0x7 0x0
92#define MX6DL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0 92#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x07c 0x390 0x000 0x0 0x0
93#define MX6DL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0 93#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x07c 0x390 0x000 0x1 0x0
94#define MX6DL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0 94#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x07c 0x390 0x7dc 0x2 0x0
95#define MX6DL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0 95#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x07c 0x390 0x8c4 0x3 0x0
96#define MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0 96#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x07c 0x390 0x000 0x4 0x0
97#define MX6DL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0 97#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x07c 0x390 0x000 0x5 0x0
98#define MX6DL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0 98#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x07c 0x390 0x000 0x7 0x0
99#define MX6DL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0 99#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x080 0x394 0x000 0x0 0x0
100#define MX6DL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0 100#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x080 0x394 0x000 0x1 0x0
101#define MX6DL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0 101#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x080 0x394 0x7e4 0x2 0x0
102#define MX6DL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0 102#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x080 0x394 0x8d0 0x3 0x0
103#define MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0 103#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x080 0x394 0x000 0x4 0x0
104#define MX6DL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0 104#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x080 0x394 0x000 0x5 0x0
105#define MX6DL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0 105#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x080 0x394 0x000 0x7 0x0
106#define MX6DL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0 106#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x084 0x398 0x000 0x0 0x0
107#define MX6DL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0 107#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x084 0x398 0x000 0x1 0x0
108#define MX6DL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0 108#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x084 0x398 0x7f4 0x2 0x0
109#define MX6DL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0 109#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x084 0x398 0x8c8 0x3 0x0
110#define MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0 110#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x084 0x398 0x86c 0x4 0x0
111#define MX6DL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0 111#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x084 0x398 0x000 0x5 0x0
112#define MX6DL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0 112#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x084 0x398 0x000 0x7 0x0
113#define MX6DL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0 113#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x088 0x39c 0x000 0x0 0x0
114#define MX6DL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0 114#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x088 0x39c 0x000 0x1 0x0
115#define MX6DL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0 115#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x088 0x39c 0x7fc 0x2 0x0
116#define MX6DL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0 116#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x088 0x39c 0x8d4 0x3 0x0
117#define MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0 117#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x088 0x39c 0x868 0x4 0x0
118#define MX6DL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0 118#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x088 0x39c 0x000 0x5 0x0
119#define MX6DL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0 119#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x088 0x39c 0x000 0x7 0x0
120#define MX6DL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0 120#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x08c 0x3a0 0x000 0x0 0x0
121#define MX6DL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0 121#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x08c 0x3a0 0x000 0x1 0x0
122#define MX6DL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0 122#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x08c 0x3a0 0x000 0x5 0x0
123#define MX6DL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0 123#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x08c 0x3a0 0x000 0x7 0x0
124#define MX6DL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0 124#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x090 0x3a4 0x000 0x0 0x0
125#define MX6DL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0 125#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x090 0x3a4 0x000 0x3 0x0
126#define MX6DL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0 126#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x090 0x3a4 0x000 0x5 0x0
127#define MX6DL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0 127#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x090 0x3a4 0x000 0x7 0x0
128#define MX6DL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0 128#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x094 0x3a8 0x000 0x0 0x0
129#define MX6DL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0 129#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x094 0x3a8 0x000 0x5 0x0
130#define MX6DL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0 130#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x094 0x3a8 0x000 0x7 0x0
131#define MX6DL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0 131#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x098 0x3ac 0x000 0x0 0x0
132#define MX6DL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0 132#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x098 0x3ac 0x000 0x1 0x0
133#define MX6DL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0 133#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x098 0x3ac 0x000 0x5 0x0
134#define MX6DL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0 134#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x098 0x3ac 0x000 0x7 0x0
135#define MX6DL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0 135#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x09c 0x3b0 0x000 0x0 0x0
136#define MX6DL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0 136#define MX6QDL_PAD_DI0_DISP_CLK__LCD_CLK 0x09c 0x3b0 0x000 0x1 0x0
137#define MX6DL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0 137#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x09c 0x3b0 0x000 0x5 0x0
138#define MX6DL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0 138#define MX6QDL_PAD_DI0_DISP_CLK__LCD_WR_RWN 0x09c 0x3b0 0x000 0x8 0x0
139#define MX6DL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0 139#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x0a0 0x3b4 0x000 0x0 0x0
140#define MX6DL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0 140#define MX6QDL_PAD_DI0_PIN15__LCD_ENABLE 0x0a0 0x3b4 0x000 0x1 0x0
141#define MX6DL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0 141#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x0a0 0x3b4 0x000 0x2 0x0
142#define MX6DL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0 142#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x0a0 0x3b4 0x000 0x5 0x0
143#define MX6DL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0 143#define MX6QDL_PAD_DI0_PIN15__LCD_RD_E 0x0a0 0x3b4 0x000 0x8 0x0
144#define MX6DL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0 144#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x0a4 0x3b8 0x000 0x0 0x0
145#define MX6DL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0 145#define MX6QDL_PAD_DI0_PIN2__LCD_HSYNC 0x0a4 0x3b8 0x8d8 0x1 0x0
146#define MX6DL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0 146#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x0a4 0x3b8 0x000 0x2 0x0
147#define MX6DL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0 147#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x0a4 0x3b8 0x000 0x5 0x0
148#define MX6DL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0 148#define MX6QDL_PAD_DI0_PIN2__LCD_RS 0x0a4 0x3b8 0x000 0x8 0x0
149#define MX6DL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0 149#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x0a8 0x3bc 0x000 0x0 0x0
150#define MX6DL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0 150#define MX6QDL_PAD_DI0_PIN3__LCD_VSYNC 0x0a8 0x3bc 0x000 0x1 0x0
151#define MX6DL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0 151#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x0a8 0x3bc 0x000 0x2 0x0
152#define MX6DL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0 152#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x0a8 0x3bc 0x000 0x5 0x0
153#define MX6DL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0 153#define MX6QDL_PAD_DI0_PIN3__LCD_CS 0x0a8 0x3bc 0x000 0x8 0x0
154#define MX6DL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0 154#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x0ac 0x3c0 0x000 0x0 0x0
155#define MX6DL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1 155#define MX6QDL_PAD_DI0_PIN4__LCD_BUSY 0x0ac 0x3c0 0x8d8 0x1 0x1
156#define MX6DL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0 156#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x0ac 0x3c0 0x000 0x2 0x0
157#define MX6DL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0 157#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x0ac 0x3c0 0x92c 0x3 0x0
158#define MX6DL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0 158#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0ac 0x3c0 0x000 0x5 0x0
159#define MX6DL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0 159#define MX6QDL_PAD_DI0_PIN4__LCD_RESET 0x0ac 0x3c0 0x000 0x8 0x0
160#define MX6DL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0 160#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x0b0 0x3c4 0x000 0x0 0x0
161#define MX6DL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0 161#define MX6QDL_PAD_DISP0_DAT0__LCD_DATA00 0x0b0 0x3c4 0x000 0x1 0x0
162#define MX6DL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0 162#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x0b0 0x3c4 0x000 0x2 0x0
163#define MX6DL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0 163#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x0b0 0x3c4 0x000 0x5 0x0
164#define MX6DL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0 164#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x0b4 0x3c8 0x000 0x0 0x0
165#define MX6DL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0 165#define MX6QDL_PAD_DISP0_DAT1__LCD_DATA01 0x0b4 0x3c8 0x000 0x1 0x0
166#define MX6DL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0 166#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x0b4 0x3c8 0x000 0x2 0x0
167#define MX6DL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0 167#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x0b4 0x3c8 0x000 0x5 0x0
168#define MX6DL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0 168#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x0b8 0x3cc 0x000 0x0 0x0
169#define MX6DL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0 169#define MX6QDL_PAD_DISP0_DAT10__LCD_DATA10 0x0b8 0x3cc 0x000 0x1 0x0
170#define MX6DL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0 170#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x0b8 0x3cc 0x000 0x5 0x0
171#define MX6DL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0 171#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x0bc 0x3d0 0x000 0x0 0x0
172#define MX6DL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0 172#define MX6QDL_PAD_DISP0_DAT11__LCD_DATA11 0x0bc 0x3d0 0x000 0x1 0x0
173#define MX6DL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0 173#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x0bc 0x3d0 0x000 0x5 0x0
174#define MX6DL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0 174#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x0c0 0x3d4 0x000 0x0 0x0
175#define MX6DL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0 175#define MX6QDL_PAD_DISP0_DAT12__LCD_DATA12 0x0c0 0x3d4 0x000 0x1 0x0
176#define MX6DL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0 176#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x0c0 0x3d4 0x000 0x5 0x0
177#define MX6DL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0 177#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x0c4 0x3d8 0x000 0x0 0x0
178#define MX6DL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0 178#define MX6QDL_PAD_DISP0_DAT13__LCD_DATA13 0x0c4 0x3d8 0x000 0x1 0x0
179#define MX6DL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0 179#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x0c4 0x3d8 0x7bc 0x3 0x0
180#define MX6DL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0 180#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x0c4 0x3d8 0x000 0x5 0x0
181#define MX6DL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0 181#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x0c8 0x3dc 0x000 0x0 0x0
182#define MX6DL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0 182#define MX6QDL_PAD_DISP0_DAT14__LCD_DATA14 0x0c8 0x3dc 0x000 0x1 0x0
183#define MX6DL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0 183#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x0c8 0x3dc 0x7b8 0x3 0x0
184#define MX6DL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0 184#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x0c8 0x3dc 0x000 0x5 0x0
185#define MX6DL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0 185#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x0cc 0x3e0 0x000 0x0 0x0
186#define MX6DL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0 186#define MX6QDL_PAD_DISP0_DAT15__LCD_DATA15 0x0cc 0x3e0 0x000 0x1 0x0
187#define MX6DL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0 187#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x0cc 0x3e0 0x7e8 0x2 0x0
188#define MX6DL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0 188#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x0cc 0x3e0 0x804 0x3 0x0
189#define MX6DL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0 189#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x0cc 0x3e0 0x000 0x5 0x0
190#define MX6DL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0 190#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x0d0 0x3e4 0x000 0x0 0x0
191#define MX6DL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0 191#define MX6QDL_PAD_DISP0_DAT16__LCD_DATA16 0x0d0 0x3e4 0x000 0x1 0x0
192#define MX6DL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1 192#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x0d0 0x3e4 0x7fc 0x2 0x1
193#define MX6DL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0 193#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x0d0 0x3e4 0x7c0 0x3 0x0
194#define MX6DL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0 194#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x0d0 0x3e4 0x8e8 0x4 0x0
195#define MX6DL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0 195#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x0d0 0x3e4 0x000 0x5 0x0
196#define MX6DL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0 196#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x0d4 0x3e8 0x000 0x0 0x0
197#define MX6DL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0 197#define MX6QDL_PAD_DISP0_DAT17__LCD_DATA17 0x0d4 0x3e8 0x000 0x1 0x0
198#define MX6DL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1 198#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x0d4 0x3e8 0x7f8 0x2 0x1
199#define MX6DL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0 199#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x0d4 0x3e8 0x7b4 0x3 0x0
200#define MX6DL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0 200#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x0d4 0x3e8 0x8ec 0x4 0x0
201#define MX6DL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0 201#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0d4 0x3e8 0x000 0x5 0x0
202#define MX6DL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0 202#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x0d8 0x3ec 0x000 0x0 0x0
203#define MX6DL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 203#define MX6QDL_PAD_DISP0_DAT18__LCD_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
204#define MX6DL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1 204#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x0d8 0x3ec 0x800 0x2 0x1
205#define MX6DL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0 205#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x0d8 0x3ec 0x7c4 0x3 0x0
206#define MX6DL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0 206#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x0d8 0x3ec 0x7a4 0x4 0x0
207#define MX6DL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0 207#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x0d8 0x3ec 0x000 0x5 0x0
208#define MX6DL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0 208#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x0d8 0x3ec 0x000 0x7 0x0
209#define MX6DL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0 209#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x0dc 0x3f0 0x000 0x0 0x0
210#define MX6DL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0 210#define MX6QDL_PAD_DISP0_DAT19__LCD_DATA19 0x0dc 0x3f0 0x000 0x1 0x0
211#define MX6DL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1 211#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x0dc 0x3f0 0x7f4 0x2 0x1
212#define MX6DL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0 212#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x0dc 0x3f0 0x7b0 0x3 0x0
213#define MX6DL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0 213#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x0dc 0x3f0 0x7a0 0x4 0x0
214#define MX6DL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0 214#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x0dc 0x3f0 0x000 0x5 0x0
215#define MX6DL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0 215#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x0dc 0x3f0 0x000 0x7 0x0
216#define MX6DL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0 216#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x0e0 0x3f4 0x000 0x0 0x0
217#define MX6DL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0 217#define MX6QDL_PAD_DISP0_DAT2__LCD_DATA02 0x0e0 0x3f4 0x000 0x1 0x0
218#define MX6DL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0 218#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x0e0 0x3f4 0x000 0x2 0x0
219#define MX6DL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0 219#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x0e0 0x3f4 0x000 0x5 0x0
220#define MX6DL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0 220#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x0e4 0x3f8 0x000 0x0 0x0
221#define MX6DL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0 221#define MX6QDL_PAD_DISP0_DAT20__LCD_DATA20 0x0e4 0x3f8 0x000 0x1 0x0
222#define MX6DL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1 222#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x0e4 0x3f8 0x7d8 0x2 0x1
223#define MX6DL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0 223#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x0e4 0x3f8 0x7a8 0x3 0x0
224#define MX6DL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0 224#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x0e4 0x3f8 0x000 0x5 0x0
225#define MX6DL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0 225#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x0e8 0x3fc 0x000 0x0 0x0
226#define MX6DL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0 226#define MX6QDL_PAD_DISP0_DAT21__LCD_DATA21 0x0e8 0x3fc 0x000 0x1 0x0
227#define MX6DL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1 227#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x0e8 0x3fc 0x7e0 0x2 0x1
228#define MX6DL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0 228#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x0e8 0x3fc 0x79c 0x3 0x0
229#define MX6DL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0 229#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x0e8 0x3fc 0x000 0x5 0x0
230#define MX6DL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0 230#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x0ec 0x400 0x000 0x0 0x0
231#define MX6DL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0 231#define MX6QDL_PAD_DISP0_DAT22__LCD_DATA22 0x0ec 0x400 0x000 0x1 0x0
232#define MX6DL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1 232#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x0ec 0x400 0x7dc 0x2 0x1
233#define MX6DL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0 233#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x0ec 0x400 0x7ac 0x3 0x0
234#define MX6DL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0 234#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x0ec 0x400 0x000 0x5 0x0
235#define MX6DL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0 235#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x0f0 0x404 0x000 0x0 0x0
236#define MX6DL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0 236#define MX6QDL_PAD_DISP0_DAT23__LCD_DATA23 0x0f0 0x404 0x000 0x1 0x0
237#define MX6DL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1 237#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x0f0 0x404 0x7e4 0x2 0x1
238#define MX6DL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0 238#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x0f0 0x404 0x798 0x3 0x0
239#define MX6DL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0 239#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x0f0 0x404 0x000 0x5 0x0
240#define MX6DL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0 240#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x0f4 0x408 0x000 0x0 0x0
241#define MX6DL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0 241#define MX6QDL_PAD_DISP0_DAT3__LCD_DATA03 0x0f4 0x408 0x000 0x1 0x0
242#define MX6DL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0 242#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x0f4 0x408 0x000 0x2 0x0
243#define MX6DL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0 243#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x0f4 0x408 0x000 0x5 0x0
244#define MX6DL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0 244#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x0f8 0x40c 0x000 0x0 0x0
245#define MX6DL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0 245#define MX6QDL_PAD_DISP0_DAT4__LCD_DATA04 0x0f8 0x40c 0x000 0x1 0x0
246#define MX6DL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0 246#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x0f8 0x40c 0x000 0x2 0x0
247#define MX6DL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0 247#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x0f8 0x40c 0x000 0x5 0x0
248#define MX6DL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0 248#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x0fc 0x410 0x000 0x0 0x0
249#define MX6DL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0 249#define MX6QDL_PAD_DISP0_DAT5__LCD_DATA05 0x0fc 0x410 0x000 0x1 0x0
250#define MX6DL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0 250#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x0fc 0x410 0x000 0x2 0x0
251#define MX6DL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0 251#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x0fc 0x410 0x000 0x3 0x0
252#define MX6DL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0 252#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x0fc 0x410 0x000 0x5 0x0
253#define MX6DL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0 253#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x100 0x414 0x000 0x0 0x0
254#define MX6DL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0 254#define MX6QDL_PAD_DISP0_DAT6__LCD_DATA06 0x100 0x414 0x000 0x1 0x0
255#define MX6DL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0 255#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x100 0x414 0x000 0x2 0x0
256#define MX6DL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0 256#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x100 0x414 0x000 0x3 0x0
257#define MX6DL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0 257#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x100 0x414 0x000 0x5 0x0
258#define MX6DL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0 258#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x104 0x418 0x000 0x0 0x0
259#define MX6DL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0 259#define MX6QDL_PAD_DISP0_DAT7__LCD_DATA07 0x104 0x418 0x000 0x1 0x0
260#define MX6DL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0 260#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x104 0x418 0x000 0x2 0x0
261#define MX6DL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0 261#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x104 0x418 0x000 0x5 0x0
262#define MX6DL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0 262#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x108 0x41c 0x000 0x0 0x0
263#define MX6DL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0 263#define MX6QDL_PAD_DISP0_DAT8__LCD_DATA08 0x108 0x41c 0x000 0x1 0x0
264#define MX6DL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0 264#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x108 0x41c 0x000 0x2 0x0
265#define MX6DL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0 265#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x108 0x41c 0x000 0x3 0x0
266#define MX6DL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0 266#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x108 0x41c 0x000 0x5 0x0
267#define MX6DL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0 267#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10c 0x420 0x000 0x0 0x0
268#define MX6DL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0 268#define MX6QDL_PAD_DISP0_DAT9__LCD_DATA09 0x10c 0x420 0x000 0x1 0x0
269#define MX6DL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0 269#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x10c 0x420 0x000 0x2 0x0
270#define MX6DL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0 270#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x10c 0x420 0x000 0x3 0x0
271#define MX6DL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0 271#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x10c 0x420 0x000 0x5 0x0
272#define MX6DL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0 272#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x110 0x4e0 0x000 0x0 0x0
273#define MX6DL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0 273#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x110 0x4e0 0x000 0x1 0x0
274#define MX6DL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0 274#define MX6QDL_PAD_EIM_A16__IPU1_CSI1_PIXCLK 0x110 0x4e0 0x8b8 0x2 0x0
275#define MX6DL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0 275#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x110 0x4e0 0x000 0x5 0x0
276#define MX6DL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0 276#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x110 0x4e0 0x000 0x7 0x0
277#define MX6DL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0 277#define MX6QDL_PAD_EIM_A16__EPDC_DATA00 0x110 0x4e0 0x000 0x8 0x0
278#define MX6DL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0 278#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x114 0x4e4 0x000 0x0 0x0
279#define MX6DL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0 279#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x114 0x4e4 0x000 0x1 0x0
280#define MX6DL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0 280#define MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x114 0x4e4 0x890 0x2 0x0
281#define MX6DL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0 281#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x114 0x4e4 0x000 0x5 0x0
282#define MX6DL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0 282#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x114 0x4e4 0x000 0x7 0x0
283#define MX6DL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0 283#define MX6QDL_PAD_EIM_A17__EPDC_PWR_STAT 0x114 0x4e4 0x000 0x8 0x0
284#define MX6DL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0 284#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x118 0x4e8 0x000 0x0 0x0
285#define MX6DL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0 285#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x118 0x4e8 0x000 0x1 0x0
286#define MX6DL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0 286#define MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0x118 0x4e8 0x894 0x2 0x0
287#define MX6DL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0 287#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x118 0x4e8 0x000 0x5 0x0
288#define MX6DL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0 288#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x118 0x4e8 0x000 0x7 0x0
289#define MX6DL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0 289#define MX6QDL_PAD_EIM_A18__EPDC_PWR_CTRL0 0x118 0x4e8 0x000 0x8 0x0
290#define MX6DL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0 290#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x11c 0x4ec 0x000 0x0 0x0
291#define MX6DL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0 291#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x11c 0x4ec 0x000 0x1 0x0
292#define MX6DL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0 292#define MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0x11c 0x4ec 0x898 0x2 0x0
293#define MX6DL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0 293#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x11c 0x4ec 0x000 0x5 0x0
294#define MX6DL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0 294#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x11c 0x4ec 0x000 0x7 0x0
295#define MX6DL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0 295#define MX6QDL_PAD_EIM_A19__EPDC_PWR_CTRL1 0x11c 0x4ec 0x000 0x8 0x0
296#define MX6DL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0 296#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x120 0x4f0 0x000 0x0 0x0
297#define MX6DL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0 297#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x120 0x4f0 0x000 0x1 0x0
298#define MX6DL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0 298#define MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0x120 0x4f0 0x89c 0x2 0x0
299#define MX6DL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0 299#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x120 0x4f0 0x000 0x5 0x0
300#define MX6DL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0 300#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x120 0x4f0 0x000 0x7 0x0
301#define MX6DL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0 301#define MX6QDL_PAD_EIM_A20__EPDC_PWR_CTRL2 0x120 0x4f0 0x000 0x8 0x0
302#define MX6DL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0 302#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x124 0x4f4 0x000 0x0 0x0
303#define MX6DL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0 303#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x124 0x4f4 0x000 0x1 0x0
304#define MX6DL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0 304#define MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0x124 0x4f4 0x8a0 0x2 0x0
305#define MX6DL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0 305#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x124 0x4f4 0x000 0x5 0x0
306#define MX6DL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0 306#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x124 0x4f4 0x000 0x7 0x0
307#define MX6DL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0 307#define MX6QDL_PAD_EIM_A21__EPDC_GDCLK 0x124 0x4f4 0x000 0x8 0x0
308#define MX6DL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0 308#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x128 0x4f8 0x000 0x0 0x0
309#define MX6DL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0 309#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x128 0x4f8 0x000 0x1 0x0
310#define MX6DL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0 310#define MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0x128 0x4f8 0x8a4 0x2 0x0
311#define MX6DL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0 311#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x128 0x4f8 0x000 0x5 0x0
312#define MX6DL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0 312#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x128 0x4f8 0x000 0x7 0x0
313#define MX6DL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0 313#define MX6QDL_PAD_EIM_A22__EPDC_GDSP 0x128 0x4f8 0x000 0x8 0x0
314#define MX6DL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0 314#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x12c 0x4fc 0x000 0x0 0x0
315#define MX6DL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0 315#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x12c 0x4fc 0x000 0x1 0x0
316#define MX6DL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0 316#define MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0x12c 0x4fc 0x8a8 0x2 0x0
317#define MX6DL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0 317#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x12c 0x4fc 0x000 0x4 0x0
318#define MX6DL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0 318#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x12c 0x4fc 0x000 0x5 0x0
319#define MX6DL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0 319#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x12c 0x4fc 0x000 0x7 0x0
320#define MX6DL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0 320#define MX6QDL_PAD_EIM_A23__EPDC_GDOE 0x12c 0x4fc 0x000 0x8 0x0
321#define MX6DL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0 321#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x130 0x500 0x000 0x0 0x0
322#define MX6DL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0 322#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x130 0x500 0x000 0x1 0x0
323#define MX6DL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0 323#define MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0x130 0x500 0x8ac 0x2 0x0
324#define MX6DL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0 324#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x130 0x500 0x000 0x4 0x0
325#define MX6DL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0 325#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x130 0x500 0x000 0x5 0x0
326#define MX6DL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0 326#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x130 0x500 0x000 0x7 0x0
327#define MX6DL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0 327#define MX6QDL_PAD_EIM_A24__EPDC_GDRL 0x130 0x500 0x000 0x8 0x0
328#define MX6DL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0 328#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x134 0x504 0x000 0x0 0x0
329#define MX6DL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0 329#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x134 0x504 0x000 0x1 0x0
330#define MX6DL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0 330#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x134 0x504 0x000 0x2 0x0
331#define MX6DL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0 331#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x134 0x504 0x000 0x3 0x0
332#define MX6DL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0 332#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x134 0x504 0x000 0x4 0x0
333#define MX6DL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0 333#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x134 0x504 0x000 0x5 0x0
334#define MX6DL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0 334#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x134 0x504 0x85c 0x6 0x0
335#define MX6DL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0 335#define MX6QDL_PAD_EIM_A25__EPDC_DATA15 0x134 0x504 0x000 0x8 0x0
336#define MX6DL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0 336#define MX6QDL_PAD_EIM_A25__EIM_ACLK_FREERUN 0x134 0x504 0x000 0x9 0x0
337#define MX6DL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0 337#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x138 0x508 0x000 0x0 0x0
338#define MX6DL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0 338#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x138 0x508 0x000 0x1 0x0
339#define MX6DL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0 339#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x138 0x508 0x000 0x5 0x0
340#define MX6DL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0 340#define MX6QDL_PAD_EIM_BCLK__EPDC_SDCE9 0x138 0x508 0x000 0x8 0x0
341#define MX6DL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0 341#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x13c 0x50c 0x000 0x0 0x0
342#define MX6DL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0 342#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x13c 0x50c 0x000 0x1 0x0
343#define MX6DL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2 343#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x13c 0x50c 0x7f4 0x2 0x2
344#define MX6DL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0 344#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x13c 0x50c 0x000 0x5 0x0
345#define MX6DL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0 345#define MX6QDL_PAD_EIM_CS0__EPDC_DATA06 0x13c 0x50c 0x000 0x8 0x0
346#define MX6DL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0 346#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x140 0x510 0x000 0x0 0x0
347#define MX6DL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0 347#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x140 0x510 0x000 0x1 0x0
348#define MX6DL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2 348#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x140 0x510 0x7fc 0x2 0x2
349#define MX6DL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0 349#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x140 0x510 0x000 0x5 0x0
350#define MX6DL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0 350#define MX6QDL_PAD_EIM_CS1__EPDC_DATA08 0x140 0x510 0x000 0x8 0x0
351#define MX6DL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0 351#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x144 0x514 0x000 0x0 0x0
352#define MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2 352#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x144 0x514 0x7d8 0x1 0x2
353#define MX6DL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0 353#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x144 0x514 0x000 0x2 0x0
354#define MX6DL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1 354#define MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x144 0x514 0x8a8 0x3 0x1
355#define MX6DL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0 355#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x144 0x514 0x864 0x4 0x0
356#define MX6DL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0 356#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x144 0x514 0x000 0x5 0x0
357#define MX6DL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0 357#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x144 0x514 0x874 0x6 0x0
358#define MX6DL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0 358#define MX6QDL_PAD_EIM_D16__EPDC_DATA10 0x144 0x514 0x000 0x8 0x0
359#define MX6DL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0 359#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x148 0x518 0x000 0x0 0x0
360#define MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2 360#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x148 0x518 0x7dc 0x1 0x2
361#define MX6DL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0 361#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x148 0x518 0x000 0x2 0x0
362#define MX6DL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1 362#define MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x148 0x518 0x8b8 0x3 0x1
363#define MX6DL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0 363#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x148 0x518 0x000 0x4 0x0
364#define MX6DL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0 364#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x148 0x518 0x000 0x5 0x0
365#define MX6DL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0 365#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x148 0x518 0x878 0x6 0x0
366#define MX6DL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0 366#define MX6QDL_PAD_EIM_D17__EPDC_VCOM0 0x148 0x518 0x000 0x8 0x0
367#define MX6DL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0 367#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x14c 0x51c 0x000 0x0 0x0
368#define MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2 368#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x14c 0x51c 0x7e0 0x1 0x2
369#define MX6DL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0 369#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x14c 0x51c 0x000 0x2 0x0
370#define MX6DL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1 370#define MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x14c 0x51c 0x8a4 0x3 0x1
371#define MX6DL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0 371#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x14c 0x51c 0x000 0x4 0x0
372#define MX6DL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0 372#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x14c 0x51c 0x000 0x5 0x0
373#define MX6DL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0 373#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x14c 0x51c 0x87c 0x6 0x0
374#define MX6DL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0 374#define MX6QDL_PAD_EIM_D18__EPDC_VCOM1 0x14c 0x51c 0x000 0x8 0x0
375#define MX6DL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0 375#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x150 0x520 0x000 0x0 0x0
376#define MX6DL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1 376#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x150 0x520 0x7e8 0x1 0x1
377#define MX6DL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0 377#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x150 0x520 0x000 0x2 0x0
378#define MX6DL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1 378#define MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x150 0x520 0x8a0 0x3 0x1
379#define MX6DL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0 379#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x150 0x520 0x000 0x4 0x0
380#define MX6DL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0 380#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x150 0x520 0x8f8 0x4 0x0
381#define MX6DL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0 381#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x150 0x520 0x000 0x5 0x0
382#define MX6DL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0 382#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x150 0x520 0x000 0x6 0x0
383#define MX6DL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0 383#define MX6QDL_PAD_EIM_D19__EPDC_DATA12 0x150 0x520 0x000 0x8 0x0
384#define MX6DL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0 384#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x154 0x524 0x000 0x0 0x0
385#define MX6DL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0 385#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x154 0x524 0x808 0x1 0x0
386#define MX6DL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0 386#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x154 0x524 0x000 0x2 0x0
387#define MX6DL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1 387#define MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x154 0x524 0x89c 0x3 0x1
388#define MX6DL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1 388#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x154 0x524 0x8f8 0x4 0x1
389#define MX6DL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0 389#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x154 0x524 0x000 0x4 0x0
390#define MX6DL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0 390#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x154 0x524 0x000 0x5 0x0
391#define MX6DL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0 391#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x154 0x524 0x000 0x6 0x0
392#define MX6DL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0 392#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x158 0x528 0x000 0x0 0x0
393#define MX6DL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0 393#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x158 0x528 0x000 0x1 0x0
394#define MX6DL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0 394#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x158 0x528 0x000 0x2 0x0
395#define MX6DL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0 395#define MX6QDL_PAD_EIM_D21__IPU1_CSI1_DATA11 0x158 0x528 0x88c 0x3 0x0
396#define MX6DL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0 396#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x158 0x528 0x920 0x4 0x0
397#define MX6DL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0 397#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x158 0x528 0x000 0x5 0x0
398#define MX6DL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1 398#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x158 0x528 0x868 0x6 0x1
399#define MX6DL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0 399#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x158 0x528 0x8f0 0x7 0x0
400#define MX6DL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0 400#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x15c 0x52c 0x000 0x0 0x0
401#define MX6DL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0 401#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x15c 0x52c 0x000 0x1 0x0
402#define MX6DL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0 402#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x15c 0x52c 0x000 0x2 0x0
403#define MX6DL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0 403#define MX6QDL_PAD_EIM_D22__IPU1_CSI1_DATA10 0x15c 0x52c 0x888 0x3 0x0
404#define MX6DL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0 404#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x15c 0x52c 0x000 0x4 0x0
405#define MX6DL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0 405#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x15c 0x52c 0x000 0x5 0x0
406#define MX6DL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0 406#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x15c 0x52c 0x000 0x6 0x0
407#define MX6DL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0 407#define MX6QDL_PAD_EIM_D22__EPDC_SDCE6 0x15c 0x52c 0x000 0x8 0x0
408#define MX6DL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0 408#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x160 0x530 0x000 0x0 0x0
409#define MX6DL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0 409#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x160 0x530 0x000 0x1 0x0
410#define MX6DL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0 410#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x160 0x530 0x000 0x2 0x0
411#define MX6DL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0 411#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x160 0x530 0x908 0x2 0x0
412#define MX6DL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0 412#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x160 0x530 0x000 0x3 0x0
413#define MX6DL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0 413#define MX6QDL_PAD_EIM_D23__IPU1_CSI1_DATA_EN 0x160 0x530 0x8b0 0x4 0x0
414#define MX6DL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0 414#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x160 0x530 0x000 0x5 0x0
415#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0 415#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x160 0x530 0x000 0x6 0x0
416#define MX6DL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0 416#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x160 0x530 0x000 0x7 0x0
417#define MX6DL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0 417#define MX6QDL_PAD_EIM_D23__EPDC_DATA11 0x160 0x530 0x000 0x8 0x0
418#define MX6DL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0 418#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x164 0x534 0x000 0x0 0x0
419#define MX6DL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0 419#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x164 0x534 0x000 0x1 0x0
420#define MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0 420#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x164 0x534 0x000 0x2 0x0
421#define MX6DL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0 421#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x164 0x534 0x90c 0x2 0x0
422#define MX6DL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0 422#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x164 0x534 0x7ec 0x3 0x0
423#define MX6DL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0 423#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x164 0x534 0x000 0x4 0x0
424#define MX6DL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0 424#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x164 0x534 0x000 0x5 0x0
425#define MX6DL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1 425#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x164 0x534 0x7bc 0x6 0x1
426#define MX6DL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0 426#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x164 0x534 0x000 0x7 0x0
427#define MX6DL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0 427#define MX6QDL_PAD_EIM_D24__EPDC_SDCE7 0x164 0x534 0x000 0x8 0x0
428#define MX6DL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0 428#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x168 0x538 0x000 0x0 0x0
429#define MX6DL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0 429#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x168 0x538 0x000 0x1 0x0
430#define MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1 430#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x168 0x538 0x90c 0x2 0x1
431#define MX6DL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0 431#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x168 0x538 0x000 0x2 0x0
432#define MX6DL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0 432#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x168 0x538 0x7f0 0x3 0x0
433#define MX6DL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0 433#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x168 0x538 0x000 0x4 0x0
434#define MX6DL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0 434#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x168 0x538 0x000 0x5 0x0
435#define MX6DL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1 435#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x168 0x538 0x7b8 0x6 0x1
436#define MX6DL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0 436#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x168 0x538 0x000 0x7 0x0
437#define MX6DL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0 437#define MX6QDL_PAD_EIM_D25__EPDC_SDCE8 0x168 0x538 0x000 0x8 0x0
438#define MX6DL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0 438#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x16c 0x53c 0x000 0x0 0x0
439#define MX6DL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0 439#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x16c 0x53c 0x000 0x1 0x0
440#define MX6DL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0 440#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x16c 0x53c 0x000 0x2 0x0
441#define MX6DL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1 441#define MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x16c 0x53c 0x898 0x3 0x1
442#define MX6DL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0 442#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x16c 0x53c 0x000 0x4 0x0
443#define MX6DL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0 443#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x16c 0x53c 0x904 0x4 0x0
444#define MX6DL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0 444#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x16c 0x53c 0x000 0x5 0x0
445#define MX6DL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0 445#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x16c 0x53c 0x000 0x6 0x0
446#define MX6DL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0 446#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x16c 0x53c 0x000 0x7 0x0
447#define MX6DL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0 447#define MX6QDL_PAD_EIM_D26__EPDC_SDOED 0x16c 0x53c 0x000 0x8 0x0
448#define MX6DL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0 448#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x170 0x540 0x000 0x0 0x0
449#define MX6DL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0 449#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x170 0x540 0x000 0x1 0x0
450#define MX6DL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0 450#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x170 0x540 0x000 0x2 0x0
451#define MX6DL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1 451#define MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x170 0x540 0x894 0x3 0x1
452#define MX6DL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1 452#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x170 0x540 0x904 0x4 0x1
453#define MX6DL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0 453#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x170 0x540 0x000 0x4 0x0
454#define MX6DL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0 454#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x170 0x540 0x000 0x5 0x0
455#define MX6DL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0 455#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x170 0x540 0x000 0x6 0x0
456#define MX6DL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0 456#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x170 0x540 0x000 0x7 0x0
457#define MX6DL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0 457#define MX6QDL_PAD_EIM_D27__EPDC_SDOE 0x170 0x540 0x000 0x8 0x0
458#define MX6DL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0 458#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x174 0x544 0x000 0x0 0x0
459#define MX6DL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1 459#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x174 0x544 0x86c 0x1 0x1
460#define MX6DL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0 460#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x174 0x544 0x000 0x2 0x0
461#define MX6DL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1 461#define MX6QDL_PAD_EIM_D28__IPU1_CSI1_DATA12 0x174 0x544 0x890 0x3 0x1
462#define MX6DL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0 462#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x174 0x544 0x000 0x4 0x0
463#define MX6DL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0 463#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x174 0x544 0x900 0x4 0x0
464#define MX6DL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0 464#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x174 0x544 0x900 0x4 0x0
465#define MX6DL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0 465#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x174 0x544 0x000 0x4 0x0
466#define MX6DL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0 466#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x174 0x544 0x000 0x5 0x0
467#define MX6DL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0 467#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x174 0x544 0x000 0x6 0x0
468#define MX6DL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0 468#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x174 0x544 0x000 0x7 0x0
469#define MX6DL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0 469#define MX6QDL_PAD_EIM_D28__EPDC_PWR_CTRL3 0x174 0x544 0x000 0x8 0x0
470#define MX6DL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1 470#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x178 0x548 0x000 0x0 0x0
471#define MX6DL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1 471#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x178 0x548 0x000 0x1 0x0
472#define MX6DL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0 472#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x178 0x548 0x808 0x2 0x1
473#define MX6DL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0 473#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x178 0x548 0x900 0x4 0x1
474#define MX6DL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0 474#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x178 0x548 0x000 0x4 0x0
475#define MX6DL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0 475#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x178 0x548 0x000 0x4 0x0
476#define MX6DL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0 476#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x178 0x548 0x900 0x4 0x1
477#define MX6DL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0 477#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x178 0x548 0x000 0x5 0x0
478#define MX6DL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0 478#define MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x178 0x548 0x8bc 0x6 0x0
479#define MX6DL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0 479#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x178 0x548 0x000 0x7 0x0
480#define MX6DL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0 480#define MX6QDL_PAD_EIM_D29__EPDC_PWR_WAKE 0x178 0x548 0x000 0x8 0x0
481#define MX6DL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0 481#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x17c 0x54c 0x000 0x0 0x0
482#define MX6DL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1 482#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x17c 0x54c 0x000 0x1 0x0
483#define MX6DL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0 483#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x17c 0x54c 0x000 0x2 0x0
484#define MX6DL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0 484#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x17c 0x54c 0x000 0x3 0x0
485#define MX6DL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0 485#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x17c 0x54c 0x000 0x4 0x0
486#define MX6DL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0 486#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x17c 0x54c 0x908 0x4 0x1
487#define MX6DL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0 487#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x17c 0x54c 0x000 0x5 0x0
488#define MX6DL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0 488#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x17c 0x54c 0x924 0x6 0x0
489#define MX6DL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0 489#define MX6QDL_PAD_EIM_D30__EPDC_SDOEZ 0x17c 0x54c 0x000 0x8 0x0
490#define MX6DL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2 490#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x180 0x550 0x000 0x0 0x0
491#define MX6DL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0 491#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x180 0x550 0x000 0x1 0x0
492#define MX6DL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0 492#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x180 0x550 0x000 0x2 0x0
493#define MX6DL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0 493#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x180 0x550 0x000 0x3 0x0
494#define MX6DL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0 494#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x180 0x550 0x908 0x4 0x2
495#define MX6DL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0 495#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x180 0x550 0x000 0x4 0x0
496#define MX6DL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0 496#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x180 0x550 0x000 0x5 0x0
497#define MX6DL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0 497#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x180 0x550 0x000 0x6 0x0
498#define MX6DL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0 498#define MX6QDL_PAD_EIM_D31__EPDC_SDCLK_P 0x180 0x550 0x000 0x8 0x0
499#define MX6DL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0 499#define MX6QDL_PAD_EIM_D31__EIM_ACLK_FREERUN 0x180 0x550 0x000 0x9 0x0
500#define MX6DL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0 500#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x184 0x554 0x000 0x0 0x0
501#define MX6DL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0 501#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x184 0x554 0x000 0x1 0x0
502#define MX6DL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0 502#define MX6QDL_PAD_EIM_DA0__IPU1_CSI1_DATA09 0x184 0x554 0x000 0x2 0x0
503#define MX6DL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0 503#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x184 0x554 0x000 0x5 0x0
504#define MX6DL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0 504#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x184 0x554 0x000 0x7 0x0
505#define MX6DL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0 505#define MX6QDL_PAD_EIM_DA0__EPDC_SDCLK_N 0x184 0x554 0x000 0x8 0x0
506#define MX6DL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0 506#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x188 0x558 0x000 0x0 0x0
507#define MX6DL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0 507#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x188 0x558 0x000 0x1 0x0
508#define MX6DL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0 508#define MX6QDL_PAD_EIM_DA1__IPU1_CSI1_DATA08 0x188 0x558 0x000 0x2 0x0
509#define MX6DL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0 509#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x188 0x558 0x000 0x5 0x0
510#define MX6DL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1 510#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x188 0x558 0x000 0x7 0x0
511#define MX6DL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0 511#define MX6QDL_PAD_EIM_DA1__EPDC_SDLE 0x188 0x558 0x000 0x8 0x0
512#define MX6DL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0 512#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x18c 0x55c 0x000 0x0 0x0
513#define MX6DL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0 513#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x18c 0x55c 0x000 0x1 0x0
514#define MX6DL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0 514#define MX6QDL_PAD_EIM_DA10__IPU1_CSI1_DATA_EN 0x18c 0x55c 0x8b0 0x2 0x1
515#define MX6DL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0 515#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x18c 0x55c 0x000 0x5 0x0
516#define MX6DL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0 516#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x18c 0x55c 0x000 0x7 0x0
517#define MX6DL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0 517#define MX6QDL_PAD_EIM_DA10__EPDC_DATA01 0x18c 0x55c 0x000 0x8 0x0
518#define MX6DL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0 518#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x190 0x560 0x000 0x0 0x0
519#define MX6DL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0 519#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x190 0x560 0x000 0x1 0x0
520#define MX6DL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0 520#define MX6QDL_PAD_EIM_DA11__IPU1_CSI1_HSYNC 0x190 0x560 0x8b4 0x2 0x0
521#define MX6DL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0 521#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x190 0x560 0x000 0x5 0x0
522#define MX6DL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1 522#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x190 0x560 0x000 0x7 0x0
523#define MX6DL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0 523#define MX6QDL_PAD_EIM_DA11__EPDC_DATA03 0x190 0x560 0x000 0x8 0x0
524#define MX6DL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0 524#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x194 0x564 0x000 0x0 0x0
525#define MX6DL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0 525#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x194 0x564 0x000 0x1 0x0
526#define MX6DL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0 526#define MX6QDL_PAD_EIM_DA12__IPU1_CSI1_VSYNC 0x194 0x564 0x8bc 0x2 0x1
527#define MX6DL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0 527#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x194 0x564 0x000 0x5 0x0
528#define MX6DL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0 528#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x194 0x564 0x000 0x7 0x0
529#define MX6DL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0 529#define MX6QDL_PAD_EIM_DA12__EPDC_DATA02 0x194 0x564 0x000 0x8 0x0
530#define MX6DL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0 530#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x198 0x568 0x000 0x0 0x0
531#define MX6DL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0 531#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x198 0x568 0x000 0x1 0x0
532#define MX6DL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0 532#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x198 0x568 0x000 0x5 0x0
533#define MX6DL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0 533#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x198 0x568 0x000 0x7 0x0
534#define MX6DL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0 534#define MX6QDL_PAD_EIM_DA13__EPDC_DATA13 0x198 0x568 0x000 0x8 0x0
535#define MX6DL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0 535#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x19c 0x56c 0x000 0x0 0x0
536#define MX6DL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0 536#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x19c 0x56c 0x000 0x1 0x0
537#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0 537#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x19c 0x56c 0x000 0x5 0x0
538#define MX6DL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0 538#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x19c 0x56c 0x000 0x7 0x0
539#define MX6DL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0 539#define MX6QDL_PAD_EIM_DA14__EPDC_DATA14 0x19c 0x56c 0x000 0x8 0x0
540#define MX6DL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0 540#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x1a0 0x570 0x000 0x0 0x0
541#define MX6DL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0 541#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x1a0 0x570 0x000 0x1 0x0
542#define MX6DL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0 542#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x1a0 0x570 0x000 0x2 0x0
543#define MX6DL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0 543#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1a0 0x570 0x000 0x5 0x0
544#define MX6DL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0 544#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x1a0 0x570 0x000 0x7 0x0
545#define MX6DL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0 545#define MX6QDL_PAD_EIM_DA15__EPDC_DATA09 0x1a0 0x570 0x000 0x8 0x0
546#define MX6DL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0 546#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x1a4 0x574 0x000 0x0 0x0
547#define MX6DL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0 547#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x1a4 0x574 0x000 0x1 0x0
548#define MX6DL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0 548#define MX6QDL_PAD_EIM_DA2__IPU1_CSI1_DATA07 0x1a4 0x574 0x000 0x2 0x0
549#define MX6DL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0 549#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1a4 0x574 0x000 0x5 0x0
550#define MX6DL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0 550#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x1a4 0x574 0x000 0x7 0x0
551#define MX6DL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0 551#define MX6QDL_PAD_EIM_DA2__EPDC_BDR0 0x1a4 0x574 0x000 0x8 0x0
552#define MX6DL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0 552#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x1a8 0x578 0x000 0x0 0x0
553#define MX6DL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0 553#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x1a8 0x578 0x000 0x1 0x0
554#define MX6DL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0 554#define MX6QDL_PAD_EIM_DA3__IPU1_CSI1_DATA06 0x1a8 0x578 0x000 0x2 0x0
555#define MX6DL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0 555#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x1a8 0x578 0x000 0x5 0x0
556#define MX6DL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0 556#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x1a8 0x578 0x000 0x7 0x0
557#define MX6DL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0 557#define MX6QDL_PAD_EIM_DA3__EPDC_BDR1 0x1a8 0x578 0x000 0x8 0x0
558#define MX6DL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0 558#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x1ac 0x57c 0x000 0x0 0x0
559#define MX6DL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0 559#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x1ac 0x57c 0x000 0x1 0x0
560#define MX6DL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0 560#define MX6QDL_PAD_EIM_DA4__IPU1_CSI1_DATA05 0x1ac 0x57c 0x000 0x2 0x0
561#define MX6DL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0 561#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x1ac 0x57c 0x000 0x5 0x0
562#define MX6DL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0 562#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x1ac 0x57c 0x000 0x7 0x0
563#define MX6DL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0 563#define MX6QDL_PAD_EIM_DA4__EPDC_SDCE0 0x1ac 0x57c 0x000 0x8 0x0
564#define MX6DL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0 564#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x1b0 0x580 0x000 0x0 0x0
565#define MX6DL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0 565#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x1b0 0x580 0x000 0x1 0x0
566#define MX6DL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0 566#define MX6QDL_PAD_EIM_DA5__IPU1_CSI1_DATA04 0x1b0 0x580 0x000 0x2 0x0
567#define MX6DL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0 567#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x1b0 0x580 0x000 0x5 0x0
568#define MX6DL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0 568#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x1b0 0x580 0x000 0x7 0x0
569#define MX6DL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0 569#define MX6QDL_PAD_EIM_DA5__EPDC_SDCE1 0x1b0 0x580 0x000 0x8 0x0
570#define MX6DL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0 570#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x1b4 0x584 0x000 0x0 0x0
571#define MX6DL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0 571#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x1b4 0x584 0x000 0x1 0x0
572#define MX6DL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0 572#define MX6QDL_PAD_EIM_DA6__IPU1_CSI1_DATA03 0x1b4 0x584 0x000 0x2 0x0
573#define MX6DL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0 573#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x1b4 0x584 0x000 0x5 0x0
574#define MX6DL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0 574#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x1b4 0x584 0x000 0x7 0x0
575#define MX6DL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0 575#define MX6QDL_PAD_EIM_DA6__EPDC_SDCE2 0x1b4 0x584 0x000 0x8 0x0
576#define MX6DL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0 576#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x1b8 0x588 0x000 0x0 0x0
577#define MX6DL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0 577#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x1b8 0x588 0x000 0x1 0x0
578#define MX6DL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0 578#define MX6QDL_PAD_EIM_DA7__IPU1_CSI1_DATA02 0x1b8 0x588 0x000 0x2 0x0
579#define MX6DL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0 579#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x1b8 0x588 0x000 0x5 0x0
580#define MX6DL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0 580#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x1b8 0x588 0x000 0x7 0x0
581#define MX6DL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0 581#define MX6QDL_PAD_EIM_DA7__EPDC_SDCE3 0x1b8 0x588 0x000 0x8 0x0
582#define MX6DL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0 582#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x1bc 0x58c 0x000 0x0 0x0
583#define MX6DL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0 583#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x1bc 0x58c 0x000 0x1 0x0
584#define MX6DL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0 584#define MX6QDL_PAD_EIM_DA8__IPU1_CSI1_DATA01 0x1bc 0x58c 0x000 0x2 0x0
585#define MX6DL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0 585#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x1bc 0x58c 0x000 0x5 0x0
586#define MX6DL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0 586#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x1bc 0x58c 0x000 0x7 0x0
587#define MX6DL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0 587#define MX6QDL_PAD_EIM_DA8__EPDC_SDCE4 0x1bc 0x58c 0x000 0x8 0x0
588#define MX6DL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0 588#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x1c0 0x590 0x000 0x0 0x0
589#define MX6DL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0 589#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x1c0 0x590 0x000 0x1 0x0
590#define MX6DL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0 590#define MX6QDL_PAD_EIM_DA9__IPU1_CSI1_DATA00 0x1c0 0x590 0x000 0x2 0x0
591#define MX6DL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0 591#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x1c0 0x590 0x000 0x5 0x0
592#define MX6DL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1 592#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x1c0 0x590 0x000 0x7 0x0
593#define MX6DL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0 593#define MX6QDL_PAD_EIM_DA9__EPDC_SDCE5 0x1c0 0x590 0x000 0x8 0x0
594#define MX6DL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0 594#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x1c4 0x594 0x000 0x0 0x0
595#define MX6DL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0 595#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x1c4 0x594 0x000 0x1 0x0
596#define MX6DL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0 596#define MX6QDL_PAD_EIM_EB0__IPU1_CSI1_DATA11 0x1c4 0x594 0x88c 0x2 0x1
597#define MX6DL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0 597#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x1c4 0x594 0x7d4 0x4 0x0
598#define MX6DL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0 598#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1c4 0x594 0x000 0x5 0x0
599#define MX6DL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1 599#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x1c4 0x594 0x000 0x7 0x0
600#define MX6DL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0 600#define MX6QDL_PAD_EIM_EB0__EPDC_PWR_COM 0x1c4 0x594 0x000 0x8 0x0
601#define MX6DL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0 601#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x1c8 0x598 0x000 0x0 0x0
602#define MX6DL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0 602#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x1c8 0x598 0x000 0x1 0x0
603#define MX6DL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0 603#define MX6QDL_PAD_EIM_EB1__IPU1_CSI1_DATA10 0x1c8 0x598 0x888 0x2 0x1
604#define MX6DL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2 604#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1c8 0x598 0x000 0x5 0x0
605#define MX6DL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1 605#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x1c8 0x598 0x000 0x7 0x0
606#define MX6DL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0 606#define MX6QDL_PAD_EIM_EB1__EPDC_SDSHR 0x1c8 0x598 0x000 0x8 0x0
607#define MX6DL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0 607#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x1cc 0x59c 0x000 0x0 0x0
608#define MX6DL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0 608#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x1cc 0x59c 0x7e4 0x1 0x2
609#define MX6DL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0 609#define MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1cc 0x59c 0x8ac 0x3 0x1
610#define MX6DL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0 610#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x1cc 0x59c 0x860 0x4 0x0
611#define MX6DL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0 611#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1cc 0x59c 0x000 0x5 0x0
612#define MX6DL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0 612#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x1cc 0x59c 0x870 0x6 0x0
613#define MX6DL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3 613#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x1cc 0x59c 0x000 0x7 0x0
614#define MX6DL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0 614#define MX6QDL_PAD_EIM_EB2__EPDC_DATA05 0x1cc 0x59c 0x000 0x8 0x0
615#define MX6DL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0 615#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x1d0 0x5a0 0x000 0x0 0x0
616#define MX6DL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1 616#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x1d0 0x5a0 0x000 0x1 0x0
617#define MX6DL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0 617#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1d0 0x5a0 0x908 0x2 0x3
618#define MX6DL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0 618#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1d0 0x5a0 0x000 0x2 0x0
619#define MX6DL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0 619#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x1d0 0x5a0 0x000 0x3 0x0
620#define MX6DL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0 620#define MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1d0 0x5a0 0x8b4 0x4 0x1
621#define MX6DL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0 621#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1d0 0x5a0 0x000 0x5 0x0
622#define MX6DL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0 622#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x1d0 0x5a0 0x000 0x6 0x0
623#define MX6DL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0 623#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x1d0 0x5a0 0x000 0x7 0x0
624#define MX6DL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1 624#define MX6QDL_PAD_EIM_EB3__EPDC_SDCE0 0x1d0 0x5a0 0x000 0x8 0x0
625#define MX6DL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0 625#define MX6QDL_PAD_EIM_EB3__EIM_ACLK_FREERUN 0x1d0 0x5a0 0x000 0x9 0x0
626#define MX6DL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0 626#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x1d4 0x5a4 0x000 0x0 0x0
627#define MX6DL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0 627#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x1d4 0x5a4 0x000 0x1 0x0
628#define MX6DL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0 628#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x1d4 0x5a4 0x804 0x2 0x1
629#define MX6DL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0 629#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x1d4 0x5a4 0x000 0x5 0x0
630#define MX6DL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2 630#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x1d4 0x5a4 0x000 0x7 0x0
631#define MX6DL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0 631#define MX6QDL_PAD_EIM_LBA__EPDC_DATA04 0x1d4 0x5a4 0x000 0x8 0x0
632#define MX6DL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0 632#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x1d8 0x5a8 0x000 0x0 0x0
633#define MX6DL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0 633#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x1d8 0x5a8 0x000 0x1 0x0
634#define MX6DL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0 634#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x1d8 0x5a8 0x7f8 0x2 0x2
635#define MX6DL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2 635#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x1d8 0x5a8 0x000 0x5 0x0
636#define MX6DL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0 636#define MX6QDL_PAD_EIM_OE__EPDC_PWR_IRQ 0x1d8 0x5a8 0x000 0x8 0x0
637#define MX6DL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0 637#define MX6QDL_PAD_EIM_RW__EIM_RW 0x1dc 0x5ac 0x000 0x0 0x0
638#define MX6DL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0 638#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x1dc 0x5ac 0x000 0x1 0x0
639#define MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0 639#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x1dc 0x5ac 0x800 0x2 0x2
640#define MX6DL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0 640#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x1dc 0x5ac 0x000 0x5 0x0
641#define MX6DL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0 641#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x1dc 0x5ac 0x000 0x7 0x0
642#define MX6DL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0 642#define MX6QDL_PAD_EIM_RW__EPDC_DATA07 0x1dc 0x5ac 0x000 0x8 0x0
643#define MX6DL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0 643#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x1e0 0x5b0 0x000 0x0 0x0
644#define MX6DL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0 644#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x1e0 0x5b0 0x000 0x1 0x0
645#define MX6DL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0 645#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x1e0 0x5b0 0x000 0x5 0x0
646#define MX6DL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0 646#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x1e0 0x5b0 0x000 0x7 0x0
647#define MX6DL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0 647#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1e4 0x5b4 0x828 0x1 0x0
648#define MX6DL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0 648#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1e4 0x5b4 0x840 0x2 0x0
649#define MX6DL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0 649#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1e4 0x5b4 0x8f4 0x3 0x0
650#define MX6DL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0 650#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1e4 0x5b4 0x000 0x5 0x0
651#define MX6DL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0 651#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1e8 0x5b8 0x8e0 0x0 0x0
652#define MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0 652#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1e8 0x5b8 0x000 0x1 0x0
653#define MX6DL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0 653#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1e8 0x5b8 0x858 0x2 0x0
654#define MX6DL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0 654#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1e8 0x5b8 0x000 0x4 0x0
655#define MX6DL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0 655#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1e8 0x5b8 0x000 0x5 0x0
656#define MX6DL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0 656#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1ec 0x5bc 0x810 0x1 0x0
657#define MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0 657#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1ec 0x5bc 0x83c 0x2 0x0
658#define MX6DL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0 658#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1ec 0x5bc 0x000 0x4 0x0
659#define MX6DL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0 659#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1ec 0x5bc 0x000 0x5 0x0
660#define MX6DL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0 660#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1ec 0x5bc 0x000 0x6 0x0
661#define MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0 661#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1f0 0x5c0 0x000 0x1 0x0
662#define MX6DL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0 662#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1f0 0x5c0 0x82c 0x2 0x0
663#define MX6DL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0 663#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1f0 0x5c0 0x000 0x5 0x0
664#define MX6DL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1 664#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1f0 0x5c0 0x000 0x6 0x0
665#define MX6DL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0 665#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1f4 0x5c4 0x790 0x0 0x0
666#define MX6DL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0 666#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1f4 0x5c4 0x000 0x1 0x0
667#define MX6DL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0 667#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1f4 0x5c4 0x834 0x2 0x0
668#define MX6DL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0 668#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1f4 0x5c4 0x8f0 0x3 0x1
669#define MX6DL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0 669#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1f4 0x5c4 0x000 0x4 0x0
670#define MX6DL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0 670#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1f4 0x5c4 0x000 0x5 0x0
671#define MX6DL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0 671#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1f8 0x5c8 0x818 0x1 0x0
672#define MX6DL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0 672#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1f8 0x5c8 0x838 0x2 0x0
673#define MX6DL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0 673#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1f8 0x5c8 0x000 0x3 0x0
674#define MX6DL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0 674#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1f8 0x5c8 0x000 0x5 0x0
675#define MX6DL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0 675#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1fc 0x5cc 0x8e4 0x0 0x0
676#define MX6DL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0 676#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1fc 0x5cc 0x81c 0x1 0x0
677#define MX6DL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0 677#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1fc 0x5cc 0x830 0x2 0x0
678#define MX6DL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0 678#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1fc 0x5cc 0x000 0x4 0x0
679#define MX6DL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0 679#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1fc 0x5cc 0x000 0x5 0x0
680#define MX6DL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0 680#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x200 0x5d0 0x000 0x1 0x0
681#define MX6DL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0 681#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x200 0x5d0 0x850 0x2 0x0
682#define MX6DL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0 682#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x200 0x5d0 0x000 0x5 0x0
683#define MX6DL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0 683#define MX6QDL_PAD_ENET_TX_EN__I2C4_SCL 0x200 0x5d0 0x880 0x9 0x0
684#define MX6DL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0 684#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x204 0x5d4 0x000 0x1 0x0
685#define MX6DL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0 685#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x204 0x5d4 0x854 0x2 0x0
686#define MX6DL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0 686#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x204 0x5d4 0x000 0x5 0x0
687#define MX6DL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0 687#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x208 0x5d8 0x8dc 0x0 0x0
688#define MX6DL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0 688#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x208 0x5d8 0x000 0x1 0x0
689#define MX6DL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0 689#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x208 0x5d8 0x84c 0x2 0x0
690#define MX6DL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1 690#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x208 0x5d8 0x000 0x4 0x0
691#define MX6DL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0 691#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x208 0x5d8 0x000 0x5 0x0
692#define MX6DL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0 692#define MX6QDL_PAD_ENET_TXD1__I2C4_SDA 0x208 0x5d8 0x884 0x9 0x0
693#define MX6DL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0 693#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x20c 0x5dc 0x000 0x0 0x0
694#define MX6DL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0 694#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x20c 0x5dc 0x8c0 0x2 0x1
695#define MX6DL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0 695#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x20c 0x5dc 0x794 0x3 0x0
696#define MX6DL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1 696#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x20c 0x5dc 0x000 0x4 0x0
697#define MX6DL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0 697#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x20c 0x5dc 0x000 0x5 0x0
698#define MX6DL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1 698#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x20c 0x5dc 0x000 0x6 0x0
699#define MX6DL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1 699#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x20c 0x5dc 0x000 0x7 0x0
700#define MX6DL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0 700#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x210 0x5e0 0x83c 0x0 0x1
701#define MX6DL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0 701#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x210 0x5e0 0x000 0x1 0x0
702#define MX6DL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0 702#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x210 0x5e0 0x8cc 0x2 0x1
703#define MX6DL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1 703#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x210 0x5e0 0x790 0x3 0x1
704#define MX6DL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0 704#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x210 0x5e0 0x000 0x4 0x0
705#define MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0 705#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x210 0x5e0 0x000 0x5 0x0
706#define MX6DL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0 706#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x210 0x5e0 0x000 0x6 0x0
707#define MX6DL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2 707#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x214 0x5e4 0x850 0x0 0x1
708#define MX6DL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0 708#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x214 0x5e4 0x000 0x1 0x0
709#define MX6DL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1 709#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x214 0x5e4 0x80c 0x2 0x0
710#define MX6DL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0 710#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x214 0x5e4 0x000 0x3 0x0
711#define MX6DL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0 711#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x214 0x5e4 0x8f0 0x4 0x2
712#define MX6DL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0 712#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x214 0x5e4 0x000 0x5 0x0
713#define MX6DL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1 713#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x214 0x5e4 0x87c 0x6 0x1
714#define MX6DL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1 714#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x214 0x5e4 0x000 0x7 0x0
715#define MX6DL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0 715#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x218 0x5e8 0x844 0x0 0x0
716#define MX6DL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0 716#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x218 0x5e8 0x000 0x1 0x0
717#define MX6DL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0 717#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x218 0x5e8 0x7d4 0x2 0x1
718#define MX6DL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0 718#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x218 0x5e8 0x8e8 0x3 0x1
719#define MX6DL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0 719#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x218 0x5e8 0x000 0x4 0x0
720#define MX6DL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1 720#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x218 0x5e8 0x000 0x5 0x0
721#define MX6DL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1 721#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x21c 0x5ec 0x848 0x0 0x0
722#define MX6DL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0 722#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x21c 0x5ec 0x814 0x1 0x0
723#define MX6DL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0 723#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x21c 0x5ec 0x000 0x2 0x0
724#define MX6DL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2 724#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x21c 0x5ec 0x8ec 0x3 0x1
725#define MX6DL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0 725#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x21c 0x5ec 0x794 0x4 0x1
726#define MX6DL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0 726#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x21c 0x5ec 0x000 0x5 0x0
727#define MX6DL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0 727#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x21c 0x5ec 0x000 0x6 0x0
728#define MX6DL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0 728#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x220 0x5f0 0x8c0 0x0 0x2
729#define MX6DL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0 729#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x220 0x5f0 0x000 0x1 0x0
730#define MX6DL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0 730#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x220 0x5f0 0x000 0x2 0x0
731#define MX6DL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1 731#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x220 0x5f0 0x000 0x3 0x0
732#define MX6DL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1 732#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x220 0x5f0 0x000 0x4 0x0
733#define MX6DL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0 733#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x220 0x5f0 0x000 0x5 0x0
734#define MX6DL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0 734#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x220 0x5f0 0x000 0x6 0x0
735#define MX6DL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1 735#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x224 0x5f4 0x830 0x0 0x1
736#define MX6DL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1 736#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x224 0x5f4 0x8d0 0x2 0x1
737#define MX6DL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1 737#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x224 0x5f4 0x000 0x5 0x0
738#define MX6DL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0 738#define MX6QDL_PAD_GPIO_2__SD2_WP 0x224 0x5f4 0x000 0x6 0x0
739#define MX6DL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0 739#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x224 0x5f4 0x8e0 0x7 0x1
740#define MX6DL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0 740#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x228 0x5f8 0x834 0x0 0x1
741#define MX6DL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1 741#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x228 0x5f8 0x878 0x2 0x1
742#define MX6DL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1 742#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x228 0x5f8 0x000 0x3 0x0
743#define MX6DL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1 743#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x228 0x5f8 0x000 0x4 0x0
744#define MX6DL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1 744#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x228 0x5f8 0x000 0x5 0x0
745#define MX6DL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0 745#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x228 0x5f8 0x924 0x6 0x1
746#define MX6DL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0 746#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x228 0x5f8 0x8dc 0x7 0x1
747#define MX6DL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1 747#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x22c 0x5fc 0x838 0x0 0x1
748#define MX6DL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1 748#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x22c 0x5fc 0x8c8 0x2 0x1
749#define MX6DL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0 749#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x22c 0x5fc 0x000 0x5 0x0
750#define MX6DL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0 750#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x22c 0x5fc 0x000 0x6 0x0
751#define MX6DL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2 751#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x230 0x600 0x84c 0x0 0x1
752#define MX6DL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0 752#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x230 0x600 0x8d4 0x2 0x1
753#define MX6DL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1 753#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x230 0x600 0x000 0x3 0x0
754#define MX6DL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2 754#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x230 0x600 0x000 0x5 0x0
755#define MX6DL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0 755#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x230 0x600 0x878 0x6 0x2
756#define MX6DL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0 756#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x230 0x600 0x000 0x7 0x0
757#define MX6DL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1 757#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x234 0x604 0x840 0x0 0x1
758#define MX6DL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1 758#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x234 0x604 0x87c 0x2 0x2
759#define MX6DL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0 759#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x234 0x604 0x000 0x5 0x0
760#define MX6DL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0 760#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x234 0x604 0x000 0x6 0x0
761#define MX6DL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0 761#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x234 0x604 0x8e4 0x7 0x1
762#define MX6DL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2 762#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x238 0x608 0x854 0x0 0x1
763#define MX6DL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0 763#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x238 0x608 0x000 0x2 0x0
764#define MX6DL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0 764#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x238 0x608 0x000 0x3 0x0
765#define MX6DL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0 765#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x238 0x608 0x000 0x4 0x0
766#define MX6DL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1 766#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x238 0x608 0x904 0x4 0x2
767#define MX6DL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1 767#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x238 0x608 0x000 0x5 0x0
768#define MX6DL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0 768#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x238 0x608 0x000 0x6 0x0
769#define MX6DL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0 769#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x238 0x608 0x000 0x7 0x0
770#define MX6DL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0 770#define MX6QDL_PAD_GPIO_7__I2C4_SCL 0x238 0x608 0x880 0x8 0x1
771#define MX6DL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3 771#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x23c 0x60c 0x858 0x0 0x1
772#define MX6DL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0 772#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x23c 0x60c 0x000 0x1 0x0
773#define MX6DL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0 773#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x23c 0x60c 0x000 0x2 0x0
774#define MX6DL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0 774#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x23c 0x60c 0x7c8 0x3 0x0
775#define MX6DL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0 775#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x23c 0x60c 0x904 0x4 0x3
776#define MX6DL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1 776#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x23c 0x60c 0x000 0x4 0x0
777#define MX6DL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1 777#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x23c 0x60c 0x000 0x5 0x0
778#define MX6DL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0 778#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x23c 0x60c 0x000 0x6 0x0
779#define MX6DL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1 779#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x23c 0x60c 0x000 0x7 0x0
780#define MX6DL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0 780#define MX6QDL_PAD_GPIO_8__I2C4_SDA 0x23c 0x60c 0x884 0x8 0x1
781#define MX6DL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0 781#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x240 0x610 0x82c 0x0 0x1
782#define MX6DL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0 782#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x240 0x610 0x000 0x1 0x0
783#define MX6DL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1 783#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x240 0x610 0x8c4 0x2 0x1
784#define MX6DL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3 784#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x240 0x610 0x000 0x3 0x0
785#define MX6DL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0 785#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x240 0x610 0x000 0x4 0x0
786#define MX6DL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1 786#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x240 0x610 0x000 0x5 0x0
787#define MX6DL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0 787#define MX6QDL_PAD_GPIO_9__SD1_WP 0x240 0x610 0x92c 0x6 0x1
788#define MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0 788#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x244 0x62c 0x7d8 0x0 0x3
789#define MX6DL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2 789#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x244 0x62c 0x824 0x1 0x0
790#define MX6DL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0 790#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x244 0x62c 0x7c0 0x2 0x1
791#define MX6DL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0 791#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x244 0x62c 0x000 0x3 0x0
792#define MX6DL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3 792#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x244 0x62c 0x000 0x4 0x0
793#define MX6DL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1 793#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x244 0x62c 0x914 0x4 0x2
794#define MX6DL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1 794#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x244 0x62c 0x000 0x5 0x0
795#define MX6DL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0 795#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x244 0x62c 0x000 0x6 0x0
796#define MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0 796#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x248 0x630 0x7dc 0x0 0x3
797#define MX6DL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2 797#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x248 0x630 0x810 0x1 0x1
798#define MX6DL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0 798#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x248 0x630 0x7c4 0x2 0x1
799#define MX6DL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0 799#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x248 0x630 0x000 0x3 0x0
800#define MX6DL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2 800#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x248 0x630 0x000 0x4 0x0
801#define MX6DL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0 801#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x248 0x630 0x91c 0x4 0x2
802#define MX6DL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0 802#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x248 0x630 0x000 0x5 0x0
803#define MX6DL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0 803#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x248 0x630 0x000 0x6 0x0
804#define MX6DL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0 804#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x24c 0x634 0x7e8 0x0 0x2
805#define MX6DL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0 805#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x24c 0x634 0x820 0x1 0x0
806#define MX6DL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0 806#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x24c 0x634 0x000 0x2 0x0
807#define MX6DL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1 807#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x24c 0x634 0x000 0x3 0x0
808#define MX6DL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0 808#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x24c 0x634 0x000 0x4 0x0
809#define MX6DL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1 809#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x24c 0x634 0x000 0x5 0x0
810#define MX6DL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0 810#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x24c 0x634 0x000 0x6 0x0
811#define MX6DL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1 811#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x250 0x638 0x7f0 0x0 0x1
812#define MX6DL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0 812#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x250 0x638 0x000 0x1 0x0
813#define MX6DL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3 813#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x250 0x638 0x860 0x2 0x1
814#define MX6DL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0 814#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x250 0x638 0x000 0x3 0x0
815#define MX6DL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0 815#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x250 0x638 0x870 0x4 0x1
816#define MX6DL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1 816#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x250 0x638 0x000 0x5 0x0
817#define MX6DL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0 817#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x250 0x638 0x8f0 0x6 0x3
818#define MX6DL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2 818#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x254 0x63c 0x000 0x0 0x0
819#define MX6DL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0 819#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x254 0x63c 0x000 0x1 0x0
820#define MX6DL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0 820#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x254 0x63c 0x920 0x2 0x1
821#define MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3 821#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x254 0x63c 0x000 0x3 0x0
822#define MX6DL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0 822#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x254 0x63c 0x918 0x4 0x2
823#define MX6DL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1 823#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x254 0x63c 0x000 0x4 0x0
824#define MX6DL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0 824#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x254 0x63c 0x000 0x5 0x0
825#define MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3 825#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x258 0x640 0x7e0 0x0 0x3
826#define MX6DL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0 826#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x258 0x640 0x000 0x1 0x0
827#define MX6DL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0 827#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x258 0x640 0x7b4 0x2 0x1
828#define MX6DL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0 828#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x258 0x640 0x000 0x3 0x0
829#define MX6DL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3 829#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x258 0x640 0x914 0x4 0x3
830#define MX6DL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0 830#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x258 0x640 0x000 0x4 0x0
831#define MX6DL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1 831#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x258 0x640 0x000 0x5 0x0
832#define MX6DL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0 832#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x258 0x640 0x000 0x6 0x0
833#define MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3 833#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x25c 0x644 0x7e4 0x0 0x3
834#define MX6DL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0 834#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x25c 0x644 0x000 0x1 0x0
835#define MX6DL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0 835#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x25c 0x644 0x7b0 0x2 0x1
836#define MX6DL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0 836#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x25c 0x644 0x000 0x3 0x0
837#define MX6DL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1 837#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x25c 0x644 0x91c 0x4 0x3
838#define MX6DL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0 838#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x25c 0x644 0x000 0x4 0x0
839#define MX6DL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1 839#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x25c 0x644 0x000 0x5 0x0
840#define MX6DL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0 840#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x25c 0x644 0x000 0x6 0x0
841#define MX6DL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0 841#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x260 0x648 0x7ec 0x0 0x1
842#define MX6DL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0 842#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x260 0x648 0x000 0x1 0x0
843#define MX6DL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1 843#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x260 0x648 0x7c8 0x2 0x1
844#define MX6DL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2 844#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x260 0x648 0x000 0x3 0x0
845#define MX6DL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1 845#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x260 0x648 0x000 0x4 0x0
846#define MX6DL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0 846#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x260 0x648 0x000 0x5 0x0
847#define MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1 847#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x260 0x648 0x85c 0x6 0x1
848#define MX6DL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0 848#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x264 0x64c 0x794 0x1 0x2
849#define MX6DL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0 849#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x264 0x64c 0x864 0x2 0x1
850#define MX6DL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0 850#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x264 0x64c 0x000 0x3 0x0
851#define MX6DL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0 851#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x264 0x64c 0x874 0x4 0x1
852#define MX6DL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0 852#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x264 0x64c 0x000 0x5 0x0
853#define MX6DL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0 853#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x264 0x64c 0x000 0x6 0x0
854#define MX6DL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0 854#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x268 0x650 0x7cc 0x0 0x0
855#define MX6DL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3 855#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x268 0x650 0x000 0x1 0x0
856#define MX6DL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0 856#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x268 0x650 0x000 0x2 0x0
857#define MX6DL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0 857#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x268 0x650 0x000 0x3 0x0
858#define MX6DL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0 858#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x268 0x650 0x000 0x4 0x0
859#define MX6DL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0 859#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x268 0x650 0x918 0x4 0x3
860#define MX6DL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0 860#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x268 0x650 0x000 0x5 0x0
861#define MX6DL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0 861#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x26c 0x654 0x000 0x0 0x0
862#define MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0 862#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x26c 0x654 0x000 0x1 0x0
863#define MX6DL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0 863#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x26c 0x654 0x000 0x5 0x0
864#define MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0 864#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x270 0x658 0x000 0x0 0x0
865#define MX6DL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0 865#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x270 0x658 0x000 0x5 0x0
866#define MX6DL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0 866#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x274 0x65c 0x000 0x0 0x0
867#define MX6DL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0 867#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x274 0x65c 0x000 0x5 0x0
868#define MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0 868#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x278 0x660 0x000 0x0 0x0
869#define MX6DL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0 869#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x278 0x660 0x000 0x1 0x0
870#define MX6DL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1 870#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x278 0x660 0x000 0x2 0x0
871#define MX6DL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0 871#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x278 0x660 0x000 0x5 0x0
872#define MX6DL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0 872#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x27c 0x664 0x000 0x0 0x0
873#define MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0 873#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x27c 0x664 0x000 0x1 0x0
874#define MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0 874#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x27c 0x664 0x844 0x2 0x1
875#define MX6DL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0 875#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x27c 0x664 0x000 0x3 0x0
876#define MX6DL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1 876#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x27c 0x664 0x000 0x4 0x0
877#define MX6DL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0 877#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x27c 0x664 0x000 0x5 0x0
878#define MX6DL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0 878#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x280 0x668 0x000 0x0 0x0
879#define MX6DL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2 879#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x280 0x668 0x000 0x1 0x0
880#define MX6DL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0 880#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x280 0x668 0x848 0x2 0x1
881#define MX6DL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0 881#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x280 0x668 0x000 0x3 0x0
882#define MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0 882#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x280 0x668 0x000 0x5 0x0
883#define MX6DL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0 883#define MX6QDL_PAD_NANDF_CS3__I2C4_SDA 0x280 0x668 0x884 0x9 0x2
884#define MX6DL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0 884#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x284 0x66c 0x000 0x0 0x0
885#define MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0 885#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x284 0x66c 0x000 0x1 0x0
886#define MX6DL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0 886#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x284 0x66c 0x000 0x5 0x0
887#define MX6DL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0 887#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x288 0x670 0x000 0x0 0x0
888#define MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0 888#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x288 0x670 0x000 0x1 0x0
889#define MX6DL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0 889#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x288 0x670 0x000 0x5 0x0
890#define MX6DL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0 890#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x28c 0x674 0x000 0x0 0x0
891#define MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0 891#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x28c 0x674 0x000 0x1 0x0
892#define MX6DL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0 892#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x28c 0x674 0x000 0x5 0x0
893#define MX6DL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0 893#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x290 0x678 0x000 0x0 0x0
894#define MX6DL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0 894#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x290 0x678 0x000 0x1 0x0
895#define MX6DL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0 895#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x290 0x678 0x000 0x5 0x0
896#define MX6DL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0 896#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x294 0x67c 0x000 0x0 0x0
897#define MX6DL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0 897#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x294 0x67c 0x000 0x1 0x0
898#define MX6DL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0 898#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x294 0x67c 0x000 0x5 0x0
899#define MX6DL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0 899#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x298 0x680 0x000 0x0 0x0
900#define MX6DL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0 900#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x298 0x680 0x000 0x1 0x0
901#define MX6DL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0 901#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x298 0x680 0x000 0x5 0x0
902#define MX6DL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0 902#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x29c 0x684 0x000 0x0 0x0
903#define MX6DL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0 903#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x29c 0x684 0x000 0x1 0x0
904#define MX6DL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0 904#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x29c 0x684 0x000 0x5 0x0
905#define MX6DL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0 905#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x2a0 0x688 0x000 0x0 0x0
906#define MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0 906#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x2a0 0x688 0x000 0x1 0x0
907#define MX6DL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0 907#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x2a0 0x688 0x000 0x5 0x0
908#define MX6DL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2 908#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2a4 0x68c 0x000 0x0 0x0
909#define MX6DL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0 909#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2a4 0x68c 0x000 0x5 0x0
910#define MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1 910#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2a8 0x690 0x000 0x0 0x0
911#define MX6DL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0 911#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2a8 0x690 0x000 0x5 0x0
912#define MX6DL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0 912#define MX6QDL_PAD_NANDF_WP_B__I2C4_SCL 0x2a8 0x690 0x880 0x9 0x2
913#define MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1 913#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x2ac 0x694 0x000 0x0 0x0
914#define MX6DL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0 914#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x2ac 0x694 0x818 0x1 0x1
915#define MX6DL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0 915#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x2ac 0x694 0x000 0x5 0x0
916#define MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1 916#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x2b0 0x698 0x000 0x0 0x0
917#define MX6DL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0 917#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x2b0 0x698 0x81c 0x1 0x1
918#define MX6DL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0 918#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x2b0 0x698 0x000 0x5 0x0
919#define MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1 919#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x2b4 0x69c 0x000 0x0 0x0
920#define MX6DL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0 920#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x2b4 0x69c 0x820 0x1 0x1
921#define MX6DL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0 921#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x2b4 0x69c 0x000 0x5 0x0
922#define MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1 922#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x2b8 0x6a0 0x000 0x0 0x0
923#define MX6DL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0 923#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x2b8 0x6a0 0x824 0x1 0x1
924#define MX6DL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0 924#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x2b8 0x6a0 0x000 0x5 0x0
925#define MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1 925#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x2bc 0x6a4 0x000 0x0 0x0
926#define MX6DL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0 926#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x2bc 0x6a4 0x828 0x1 0x1
927#define MX6DL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0 927#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x2bc 0x6a4 0x000 0x5 0x0
928#define MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0 928#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x2c0 0x6a8 0x000 0x0 0x0
929#define MX6DL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0 929#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x2c0 0x6a8 0x814 0x1 0x1
930#define MX6DL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0 930#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x2c0 0x6a8 0x000 0x5 0x0
931#define MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0 931#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x2c4 0x6ac 0x000 0x0 0x0
932#define MX6DL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0 932#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x2c4 0x6ac 0x000 0x1 0x0
933#define MX6DL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0 933#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x2c4 0x6ac 0x000 0x5 0x0
934#define MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0 934#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x2c8 0x6b0 0x000 0x0 0x0
935#define MX6DL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0 935#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x2c8 0x6b0 0x000 0x1 0x0
936#define MX6DL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0 936#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x2c8 0x6b0 0x000 0x5 0x0
937#define MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0 937#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x2cc 0x6b4 0x000 0x0 0x0
938#define MX6DL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0 938#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x2cc 0x6b4 0x000 0x1 0x0
939#define MX6DL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0 939#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x2cc 0x6b4 0x000 0x5 0x0
940#define MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0 940#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x2d0 0x6b8 0x000 0x0 0x0
941#define MX6DL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0 941#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x2d0 0x6b8 0x000 0x1 0x0
942#define MX6DL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1 942#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x2d0 0x6b8 0x000 0x5 0x0
943#define MX6DL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0 943#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x2d4 0x6bc 0x000 0x0 0x0
944#define MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0 944#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x2d4 0x6bc 0x000 0x1 0x0
945#define MX6DL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1 945#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x2d4 0x6bc 0x000 0x5 0x0
946#define MX6DL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0 946#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x2d4 0x6bc 0x80c 0x7 0x1
947#define MX6DL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0 947#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x2d8 0x6c0 0x000 0x0 0x0
948#define MX6DL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1 948#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x2d8 0x6c0 0x000 0x1 0x0
949#define MX6DL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0 949#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x2d8 0x6c0 0x8f4 0x2 0x1
950#define MX6DL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0 950#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x2d8 0x6c0 0x000 0x5 0x0
951#define MX6DL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0 951#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x2d8 0x6c0 0x000 0x7 0x0
952#define MX6DL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0 952#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x2dc 0x6c4 0x928 0x0 0x1
953#define MX6DL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0 953#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x2dc 0x6c4 0x000 0x3 0x0
954#define MX6DL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0 954#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x2dc 0x6c4 0x000 0x5 0x0
955#define MX6DL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0 955#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x2e0 0x6c8 0x000 0x0 0x0
956#define MX6DL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0 956#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x2e0 0x6c8 0x000 0x2 0x0
957#define MX6DL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0 957#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x2e0 0x6c8 0x000 0x3 0x0
958#define MX6DL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0 958#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x2e0 0x6c8 0x000 0x5 0x0
959#define MX6DL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0 959#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x2e4 0x6cc 0x000 0x0 0x0
960#define MX6DL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0 960#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x2e4 0x6cc 0x000 0x3 0x0
961#define MX6DL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0 961#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x2e4 0x6cc 0x000 0x5 0x0
962#define MX6DL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0 962#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x2e8 0x6d0 0x000 0x0 0x0
963#define MX6DL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0 963#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x2e8 0x6d0 0x000 0x2 0x0
964#define MX6DL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0 964#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x2e8 0x6d0 0x000 0x3 0x0
965#define MX6DL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0 965#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x2e8 0x6d0 0x000 0x5 0x0
966#define MX6DL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0 966#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x2ec 0x6d4 0x000 0x0 0x0
967#define MX6DL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0 967#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x2ec 0x6d4 0x000 0x2 0x0
968#define MX6DL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0 968#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x2ec 0x6d4 0x000 0x3 0x0
969#define MX6DL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0 969#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x2ec 0x6d4 0x000 0x4 0x0
970#define MX6DL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0 970#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x2ec 0x6d4 0x000 0x5 0x0
971#define MX6DL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0 971#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x2ec 0x6d4 0x000 0x6 0x0
972#define MX6DL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0 972#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x2f0 0x6d8 0x000 0x0 0x0
973#define MX6DL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0 973#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x2f0 0x6d8 0x000 0x2 0x0
974#define MX6DL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1 974#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x2f0 0x6d8 0x000 0x3 0x0
975#define MX6DL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3 975#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x2f0 0x6d8 0x000 0x4 0x0
976#define MX6DL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1 976#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x2f0 0x6d8 0x000 0x5 0x0
977#define MX6DL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0 977#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x2f0 0x6d8 0x000 0x6 0x0
978#define MX6DL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0 978#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x2f4 0x6dc 0x930 0x0 0x1
979#define MX6DL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2 979#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x2f4 0x6dc 0x8c0 0x2 0x3
980#define MX6DL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1 980#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x2f4 0x6dc 0x7a4 0x3 0x1
981#define MX6DL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0 981#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x2f4 0x6dc 0x000 0x5 0x0
982#define MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0 982#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x2f8 0x6e0 0x000 0x0 0x0
983#define MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1 983#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x2f8 0x6e0 0x8cc 0x2 0x2
984#define MX6DL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2 984#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x2f8 0x6e0 0x7a0 0x3 0x1
985#define MX6DL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0 985#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x2f8 0x6e0 0x000 0x5 0x0
986#define MX6DL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0 986#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x2fc 0x6e4 0x000 0x0 0x0
987#define MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0 987#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x2fc 0x6e4 0x798 0x3 0x1
988#define MX6DL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0 988#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x2fc 0x6e4 0x8d4 0x4 0x2
989#define MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1 989#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x2fc 0x6e4 0x000 0x5 0x0
990#define MX6DL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2 990#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x2fc 0x6e4 0x000 0x6 0x0
991#define MX6DL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0 991#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x300 0x6e8 0x000 0x0 0x0
992#define MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0 992#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x300 0x6e8 0x000 0x2 0x0
993#define MX6DL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0 993#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x300 0x6e8 0x7ac 0x3 0x1
994#define MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1 994#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x300 0x6e8 0x8c8 0x4 0x2
995#define MX6DL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2 995#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x300 0x6e8 0x000 0x5 0x0
996#define MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0 996#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x304 0x6ec 0x000 0x0 0x0
997#define MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0 997#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x304 0x6ec 0x000 0x2 0x0
998#define MX6DL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2 998#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x304 0x6ec 0x79c 0x3 0x1
999#define MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1 999#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x304 0x6ec 0x8d0 0x4 0x2
1000#define MX6DL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0 1000#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x304 0x6ec 0x000 0x5 0x0
1001#define MX6DL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1 1001#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x308 0x6f0 0x000 0x0 0x0
1002#define MX6DL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2 1002#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x308 0x6f0 0x8c4 0x2 0x2
1003#define MX6DL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0 1003#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x308 0x6f0 0x7a8 0x3 0x1
1004#define MX6DL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2 1004#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x308 0x6f0 0x000 0x5 0x0
1005#define MX6DL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0 1005#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x30c 0x6f4 0x934 0x0 0x1
1006#define MX6DL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0 1006#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x30c 0x6f4 0x900 0x1 0x2
1007#define MX6DL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0 1007#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x30c 0x6f4 0x000 0x1 0x0
1008#define MX6DL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3 1008#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x30c 0x6f4 0x7c8 0x2 0x2
1009#define MX6DL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0 1009#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x30c 0x6f4 0x000 0x5 0x0
1010#define MX6DL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0 1010#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x310 0x6f8 0x000 0x0 0x0
1011#define MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0 1011#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x310 0x6f8 0x000 0x1 0x0
1012#define MX6DL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0 1012#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x310 0x6f8 0x900 0x1 0x3
1013#define MX6DL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2 1013#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x310 0x6f8 0x000 0x2 0x0
1014#define MX6DL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0 1014#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x310 0x6f8 0x000 0x5 0x0
1015#define MX6DL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0 1015#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x314 0x6fc 0x000 0x0 0x0
1016#define MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0 1016#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x314 0x6fc 0x000 0x1 0x0
1017#define MX6DL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3 1017#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x314 0x6fc 0x8f8 0x1 0x2
1018#define MX6DL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0 1018#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x314 0x6fc 0x000 0x2 0x0
1019#define MX6DL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1 1019#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x314 0x6fc 0x000 0x5 0x0
1020#define MX6DL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0 1020#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x318 0x700 0x000 0x0 0x0
1021#define MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0 1021#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x318 0x700 0x8f8 0x1 0x3
1022#define MX6DL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0 1022#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x318 0x700 0x000 0x1 0x0
1023#define MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0 1023#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x318 0x700 0x7cc 0x2 0x1
1024#define MX6DL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0 1024#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x318 0x700 0x000 0x5 0x0
1025#define MX6DL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4 1025#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x31c 0x704 0x000 0x0 0x0
1026#define MX6DL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0 1026#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x31c 0x704 0x000 0x5 0x0
1027#define MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0 1027#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x320 0x708 0x000 0x0 0x0
1028#define MX6DL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4 1028#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x320 0x708 0x000 0x1 0x0
1029#define MX6DL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0 1029#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x320 0x708 0x908 0x1 0x4
1030#define MX6DL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0 1030#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x320 0x708 0x000 0x5 0x0
1031#define MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0 1031#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x324 0x70c 0x000 0x0 0x0
1032#define MX6DL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0 1032#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x324 0x70c 0x904 0x1 0x4
1033#define MX6DL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5 1033#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x324 0x70c 0x000 0x1 0x0
1034#define MX6DL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0 1034#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x324 0x70c 0x000 0x5 0x0
1035#define MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0 1035#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x328 0x710 0x000 0x0 0x0
1036#define MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2 1036#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x328 0x710 0x000 0x1 0x0
1037#define MX6DL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0 1037#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x328 0x710 0x904 0x1 0x5
1038#define MX6DL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0 1038#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x328 0x710 0x000 0x5 0x0
1039#define MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0 1039#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x32c 0x714 0x000 0x0 0x0
1040#define MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0 1040#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x32c 0x714 0x8fc 0x1 0x2
1041#define MX6DL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3 1041#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x32c 0x714 0x000 0x1 0x0
1042#define MX6DL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0 1042#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x32c 0x714 0x000 0x5 0x0
1043#define MX6DL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0 1043#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x330 0x718 0x000 0x0 0x0
1044#define MX6DL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5 1044#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x330 0x718 0x000 0x1 0x0
1045#define MX6DL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0 1045#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x330 0x718 0x8fc 0x1 0x3
1046#define MX6DL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0 1046#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x330 0x718 0x000 0x5 0x0
1047#define MX6DL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1 1047#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x334 0x71c 0x000 0x0 0x0
1048#define MX6DL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0 1048#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x334 0x71c 0x908 0x1 0x5
1049#define MX6DL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2 1049#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x334 0x71c 0x000 0x1 0x0
1050#define MX6DL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0 1050#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x334 0x71c 0x000 0x5 0x0
1051#define MX6DL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0 1051#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x338 0x720 0x938 0x0 0x1
1052#define MX6DL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0 1052#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x338 0x720 0x000 0x1 0x0
1053#define MX6DL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0 1053#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x338 0x720 0x90c 0x2 0x2
1054#define MX6DL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0 1054#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x338 0x720 0x000 0x2 0x0
1055#define MX6DL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3 1055#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x338 0x720 0x000 0x5 0x0
1056#define MX6DL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0 1056#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x33c 0x724 0x000 0x0 0x0
1057#define MX6DL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0 1057#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x33c 0x724 0x000 0x1 0x0
1058#define MX6DL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0 1058#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x33c 0x724 0x000 0x2 0x0
1059#define MX6DL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0 1059#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x33c 0x724 0x90c 0x2 0x3
1060#define MX6DL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0 1060#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x33c 0x724 0x000 0x5 0x0
1061#define MX6DL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0 1061#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x340 0x728 0x000 0x1 0x0
1062#define MX6DL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0 1062#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x340 0x728 0x000 0x2 0x0
1063#define MX6DL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0 1063#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x340 0x728 0x000 0x5 0x0
1064#define MX6DL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 1064#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x344 0x72c 0x000 0x1 0x0
1065#define MX6DL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0 1065#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x344 0x72c 0x000 0x2 0x0
1066#define MX6DL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0 1066#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x344 0x72c 0x000 0x5 0x0
1067#define MX6DL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0 1067#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x348 0x730 0x000 0x1 0x0
1068#define MX6DL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0 1068#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1069#define MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6 1069#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x348 0x730 0x000 0x5 0x0
1070#define MX6DL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0 1070#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x34c 0x734 0x000 0x1 0x0
1071#define MX6DL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0 1071#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x34c 0x734 0x000 0x5 0x0
1072#define MX6DL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0 1072#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x350 0x738 0x000 0x1 0x0
1073#define MX6DL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4 1073#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x350 0x738 0x904 0x2 0x6
1074#define MX6DL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0 1074#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x350 0x738 0x000 0x2 0x0
1075#define MX6DL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0 1075#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x350 0x738 0x000 0x5 0x0
1076#define MX6DL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0 1076#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x354 0x73c 0x000 0x1 0x0
1077#define MX6DL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0 1077#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x354 0x73c 0x900 0x2 0x4
1078#define MX6DL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5 1078#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x354 0x73c 0x000 0x2 0x0
1079#define MX6DL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0 1079#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x354 0x73c 0x000 0x5 0x0
1080#define MX6DL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0 1080#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x358 0x740 0x000 0x1 0x0
1081#define MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0 1081#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x358 0x740 0x000 0x2 0x0
1082#define MX6DL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7 1082#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x358 0x740 0x900 0x2 0x5
1083#define MX6DL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0 1083#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x358 0x740 0x000 0x5 0x0
1084#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x35c 0x744 0x000 0x1 0x0
1085#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x35c 0x744 0x000 0x2 0x0
1086#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x35c 0x744 0x904 0x2 0x7
1087#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x35c 0x744 0x000 0x5 0x0
1084 1088
1085#endif /* __DTS_IMX6DL_PINFUNC_H */ 1089#endif /* __DTS_IMX6DL_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts
index 95da71185a4a..a6ce7b487ad7 100644
--- a/arch/arm/boot/dts/imx6dl-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts
@@ -15,25 +15,3 @@
15 model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; 15 model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board";
16 compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; 16 compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl";
17}; 17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
27 MX6DL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
28 >;
29 };
30 };
31
32 ecspi1 {
33 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
34 fsl,pins = <
35 MX6DL_PAD_EIM_D19__GPIO3_IO19 0x80000000
36 >;
37 };
38 };
39};
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 8989df2b89e5..1e45f2f9d0b6 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,22 +15,3 @@
15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board"; 15 model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl"; 16 compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
17}; 17};
18
19&iomuxc {
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_hog>;
22
23 hog {
24 pinctrl_hog: hoggrp {
25 fsl,pins = <
26 MX6DL_PAD_GPIO_4__GPIO1_IO04 0x80000000
27 MX6DL_PAD_GPIO_5__GPIO1_IO05 0x80000000
28 MX6DL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
29 MX6DL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
30 MX6DL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
31 MX6DL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
32 MX6DL_PAD_GPIO_0__CCM_CLKO1 0x130b0
33 >;
34 };
35 };
36};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index bfc59c3566a4..e672891c1626 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -10,6 +10,7 @@
10 */ 10 */
11/dts-v1/; 11/dts-v1/;
12#include "imx6dl.dtsi" 12#include "imx6dl.dtsi"
13#include "imx6qdl-wandboard.dtsi"
13 14
14/ { 15/ {
15 model = "Wandboard i.MX6 Dual Lite Board"; 16 model = "Wandboard i.MX6 Dual Lite Board";
@@ -19,26 +20,3 @@
19 reg = <0x10000000 0x40000000>; 20 reg = <0x10000000 0x40000000>;
20 }; 21 };
21}; 22};
22
23&fec {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_enet_1>;
26 phy-mode = "rgmii";
27 status = "okay";
28};
29
30&uart1 {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_uart1_1>;
33 status = "okay";
34};
35
36&usbh1 {
37 status = "okay";
38};
39
40&usdhc3 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_usdhc3_2>;
43 status = "okay";
44};
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 2b3ecd679350..9e8ae118fdd4 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -8,8 +8,8 @@
8 * 8 *
9 */ 9 */
10 10
11#include "imx6qdl.dtsi"
12#include "imx6dl-pinfunc.h" 11#include "imx6dl-pinfunc.h"
12#include "imx6qdl.dtsi"
13 13
14/ { 14/ {
15 cpus { 15 cpus {
@@ -32,238 +32,15 @@
32 }; 32 };
33 33
34 soc { 34 soc {
35 ocram: sram@00900000 {
36 compatible = "mmio-sram";
37 reg = <0x00900000 0x20000>;
38 clocks = <&clks 142>;
39 };
40
35 aips1: aips-bus@02000000 { 41 aips1: aips-bus@02000000 {
36 iomuxc: iomuxc@020e0000 { 42 iomuxc: iomuxc@020e0000 {
37 compatible = "fsl,imx6dl-iomuxc"; 43 compatible = "fsl,imx6dl-iomuxc";
38 reg = <0x020e0000 0x4000>;
39
40 audmux {
41 pinctrl_audmux_2: audmux-2 {
42 fsl,pins = <
43 MX6DL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
44 MX6DL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
45 MX6DL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
46 MX6DL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
47 >;
48 };
49 };
50
51 ecspi1 {
52 pinctrl_ecspi1_1: ecspi1grp-1 {
53 fsl,pins = <
54 MX6DL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
55 MX6DL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
56 MX6DL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
57 >;
58 };
59 };
60
61 enet {
62 pinctrl_enet_1: enetgrp-1 {
63 fsl,pins = <
64 MX6DL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
65 MX6DL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
66 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
67 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
68 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
69 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
70 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
71 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
72 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
73 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
74 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
75 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
76 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
77 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
78 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
79 MX6DL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
80 >;
81 };
82
83 pinctrl_enet_2: enetgrp-2 {
84 fsl,pins = <
85 MX6DL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
86 MX6DL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
87 MX6DL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
88 MX6DL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
89 MX6DL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
90 MX6DL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
91 MX6DL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
92 MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
93 MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
94 MX6DL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
95 MX6DL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
96 MX6DL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
97 MX6DL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
98 MX6DL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
99 MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
100 >;
101 };
102 };
103
104 gpmi-nand {
105 pinctrl_gpmi_nand_1: gpmi-nand-1 {
106 fsl,pins = <
107 MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
108 MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
109 MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
110 MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
111 MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
112 MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
113 MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
114 MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
115 MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
116 MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
117 MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
118 MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
119 MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
120 MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
121 MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
122 MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
123 MX6DL_PAD_SD4_DAT0__NAND_DQS 0x00b1
124 >;
125 };
126 };
127
128 i2c1 {
129 pinctrl_i2c1_2: i2c1grp-2 {
130 fsl,pins = <
131 MX6DL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
132 MX6DL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
133 >;
134 };
135 };
136
137 uart1 {
138 pinctrl_uart1_1: uart1grp-1 {
139 fsl,pins = <
140 MX6DL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
141 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
142 >;
143 };
144 };
145
146 uart4 {
147 pinctrl_uart4_1: uart4grp-1 {
148 fsl,pins = <
149 MX6DL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
150 MX6DL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
151 >;
152 };
153 };
154
155 usbotg {
156 pinctrl_usbotg_2: usbotggrp-2 {
157 fsl,pins = <
158 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
159 >;
160 };
161 };
162
163 usdhc2 {
164 pinctrl_usdhc2_1: usdhc2grp-1 {
165 fsl,pins = <
166 MX6DL_PAD_SD2_CMD__SD2_CMD 0x17059
167 MX6DL_PAD_SD2_CLK__SD2_CLK 0x10059
168 MX6DL_PAD_SD2_DAT0__SD2_DATA0 0x17059
169 MX6DL_PAD_SD2_DAT1__SD2_DATA1 0x17059
170 MX6DL_PAD_SD2_DAT2__SD2_DATA2 0x17059
171 MX6DL_PAD_SD2_DAT3__SD2_DATA3 0x17059
172 MX6DL_PAD_NANDF_D4__SD2_DATA4 0x17059
173 MX6DL_PAD_NANDF_D5__SD2_DATA5 0x17059
174 MX6DL_PAD_NANDF_D6__SD2_DATA6 0x17059
175 MX6DL_PAD_NANDF_D7__SD2_DATA7 0x17059
176 >;
177 };
178 };
179
180 usdhc3 {
181 pinctrl_usdhc3_1: usdhc3grp-1 {
182 fsl,pins = <
183 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
184 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
185 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
186 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
187 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
188 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
189 MX6DL_PAD_SD3_DAT4__SD3_DATA4 0x17059
190 MX6DL_PAD_SD3_DAT5__SD3_DATA5 0x17059
191 MX6DL_PAD_SD3_DAT6__SD3_DATA6 0x17059
192 MX6DL_PAD_SD3_DAT7__SD3_DATA7 0x17059
193 >;
194 };
195
196 pinctrl_usdhc3_2: usdhc3grp_2 {
197 fsl,pins = <
198 MX6DL_PAD_SD3_CMD__SD3_CMD 0x17059
199 MX6DL_PAD_SD3_CLK__SD3_CLK 0x10059
200 MX6DL_PAD_SD3_DAT0__SD3_DATA0 0x17059
201 MX6DL_PAD_SD3_DAT1__SD3_DATA1 0x17059
202 MX6DL_PAD_SD3_DAT2__SD3_DATA2 0x17059
203 MX6DL_PAD_SD3_DAT3__SD3_DATA3 0x17059
204 >;
205 };
206 };
207
208 weim {
209 pinctrl_weim_cs0_1: weim_cs0grp-1 {
210 fsl,pins = <
211 MX6DL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
212 >;
213 };
214
215 pinctrl_weim_nor_1: weim_norgrp-1 {
216 fsl,pins = <
217 MX6DL_PAD_EIM_OE__EIM_OE_B 0xb0b1
218 MX6DL_PAD_EIM_RW__EIM_RW 0xb0b1
219 MX6DL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
220 /* data */
221 MX6DL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
222 MX6DL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
223 MX6DL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
224 MX6DL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
225 MX6DL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
226 MX6DL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
227 MX6DL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
228 MX6DL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
229 MX6DL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
230 MX6DL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
231 MX6DL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
232 MX6DL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
233 MX6DL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
234 MX6DL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
235 MX6DL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
236 MX6DL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
237 /* address */
238 MX6DL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
239 MX6DL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
240 MX6DL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
241 MX6DL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
242 MX6DL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
243 MX6DL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
244 MX6DL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
245 MX6DL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
246 MX6DL_PAD_EIM_DA15__EIM_AD15 0xb0b1
247 MX6DL_PAD_EIM_DA14__EIM_AD14 0xb0b1
248 MX6DL_PAD_EIM_DA13__EIM_AD13 0xb0b1
249 MX6DL_PAD_EIM_DA12__EIM_AD12 0xb0b1
250 MX6DL_PAD_EIM_DA11__EIM_AD11 0xb0b1
251 MX6DL_PAD_EIM_DA10__EIM_AD10 0xb0b1
252 MX6DL_PAD_EIM_DA9__EIM_AD09 0xb0b1
253 MX6DL_PAD_EIM_DA8__EIM_AD08 0xb0b1
254 MX6DL_PAD_EIM_DA7__EIM_AD07 0xb0b1
255 MX6DL_PAD_EIM_DA6__EIM_AD06 0xb0b1
256 MX6DL_PAD_EIM_DA5__EIM_AD05 0xb0b1
257 MX6DL_PAD_EIM_DA4__EIM_AD04 0xb0b1
258 MX6DL_PAD_EIM_DA3__EIM_AD03 0xb0b1
259 MX6DL_PAD_EIM_DA2__EIM_AD02 0xb0b1
260 MX6DL_PAD_EIM_DA1__EIM_AD01 0xb0b1
261 MX6DL_PAD_EIM_DA0__EIM_AD00 0xb0b1
262 >;
263 };
264
265 };
266
267 }; 44 };
268 45
269 pxp: pxp@020f0000 { 46 pxp: pxp@020f0000 {
@@ -294,3 +71,20 @@
294 }; 71 };
295 }; 72 };
296}; 73};
74
75&ldb {
76 clocks = <&clks 33>, <&clks 34>,
77 <&clks 39>, <&clks 40>,
78 <&clks 135>, <&clks 136>;
79 clock-names = "di0_pll", "di1_pll",
80 "di0_sel", "di1_sel",
81 "di0", "di1";
82
83 lvds-channel@0 {
84 crtcs = <&ipu1 0>, <&ipu1 1>;
85 };
86
87 lvds-channel@1 {
88 crtcs = <&ipu1 0>, <&ipu1 1>;
89 };
90};
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 4e54fde591bd..edf1bd967164 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -57,7 +57,7 @@
57 hog { 57 hog {
58 pinctrl_hog: hoggrp { 58 pinctrl_hog: hoggrp {
59 fsl,pins = < 59 fsl,pins = <
60 MX6Q_PAD_EIM_D25__GPIO3_IO25 0x80000000 60 MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
61 >; 61 >;
62 }; 62 };
63 }; 63 };
@@ -65,8 +65,8 @@
65 arm2 { 65 arm2 {
66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 { 66 pinctrl_usdhc3_arm2: usdhc3grp-arm2 {
67 fsl,pins = < 67 fsl,pins = <
68 MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x80000000 68 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x80000000
69 MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x80000000 69 MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x80000000
70 >; 70 >;
71 }; 71 };
72 }; 72 };
@@ -97,6 +97,14 @@
97 status = "okay"; 97 status = "okay";
98}; 98};
99 99
100&uart2 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart2_2>;
103 fsl,dte-mode;
104 fsl,uart-has-rtscts;
105 status = "okay";
106};
107
100&uart4 { 108&uart4 {
101 pinctrl-names = "default"; 109 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_uart4_1>; 110 pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
index f5e1981025ed..1a3b50d4d8fa 100644
--- a/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6q-phytec-pfla02.dtsi
@@ -20,6 +20,110 @@
20 }; 20 };
21}; 21};
22 22
23&ecspi3 {
24 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_ecspi3_1>;
26 status = "okay";
27 fsl,spi-num-chipselects = <1>;
28 cs-gpios = <&gpio4 24 0>;
29
30 flash@0 {
31 compatible = "m25p80";
32 spi-max-frequency = <20000000>;
33 reg = <0>;
34 };
35};
36
37&i2c1 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_i2c1_1>;
40 status = "okay";
41
42 eeprom@50 {
43 compatible = "atmel,24c32";
44 reg = <0x50>;
45 };
46
47 pmic@58 {
48 compatible = "dialog,da9063";
49 reg = <0x58>;
50 interrupt-parent = <&gpio4>;
51 interrupts = <17 0x8>; /* active-low GPIO4_17 */
52
53 regulators {
54 vddcore_reg: bcore1 {
55 regulator-min-microvolt = <730000>;
56 regulator-max-microvolt = <1380000>;
57 regulator-always-on;
58 };
59
60 vddsoc_reg: bcore2 {
61 regulator-min-microvolt = <730000>;
62 regulator-max-microvolt = <1380000>;
63 regulator-always-on;
64 };
65
66 vdd_ddr3_reg: bpro {
67 regulator-min-microvolt = <1500000>;
68 regulator-max-microvolt = <1500000>;
69 regulator-always-on;
70 };
71
72 vdd_3v3_reg: bperi {
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-always-on;
76 };
77
78 vdd_buckmem_reg: bmem {
79 regulator-min-microvolt = <3300000>;
80 regulator-max-microvolt = <3300000>;
81 regulator-always-on;
82 };
83
84 vdd_eth_reg: bio {
85 regulator-min-microvolt = <1200000>;
86 regulator-max-microvolt = <1200000>;
87 regulator-always-on;
88 };
89
90 vdd_eth_io_reg: ldo4 {
91 regulator-min-microvolt = <2500000>;
92 regulator-max-microvolt = <2500000>;
93 regulator-always-on;
94 };
95
96 vdd_mx6_snvs_reg: ldo5 {
97 regulator-min-microvolt = <3000000>;
98 regulator-max-microvolt = <3000000>;
99 regulator-always-on;
100 };
101
102 vdd_3v3_pmic_io_reg: ldo6 {
103 regulator-min-microvolt = <3300000>;
104 regulator-max-microvolt = <3300000>;
105 regulator-always-on;
106 };
107
108 vdd_sd0_reg: ldo9 {
109 regulator-min-microvolt = <3300000>;
110 regulator-max-microvolt = <3300000>;
111 };
112
113 vdd_sd1_reg: ldo10 {
114 regulator-min-microvolt = <3300000>;
115 regulator-max-microvolt = <3300000>;
116 };
117
118 vdd_mx6_high_reg: ldo11 {
119 regulator-min-microvolt = <3000000>;
120 regulator-max-microvolt = <3000000>;
121 regulator-always-on;
122 };
123 };
124 };
125};
126
23&iomuxc { 127&iomuxc {
24 pinctrl-names = "default"; 128 pinctrl-names = "default";
25 pinctrl-0 = <&pinctrl_hog>; 129 pinctrl-0 = <&pinctrl_hog>;
@@ -27,7 +131,9 @@
27 hog { 131 hog {
28 pinctrl_hog: hoggrp { 132 pinctrl_hog: hoggrp {
29 fsl,pins = < 133 fsl,pins = <
30 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 134 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
135 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
136 MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x80000000 /* PMIC interrupt */
31 >; 137 >;
32 }; 138 };
33 }; 139 };
@@ -35,8 +141,8 @@
35 pfla02 { 141 pfla02 {
36 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 { 142 pinctrl_usdhc3_pfla02: usdhc3grp-pfla02 {
37 fsl,pins = < 143 fsl,pins = <
38 MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 144 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
39 MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 145 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
40 >; 146 >;
41 }; 147 };
42 }; 148 };
diff --git a/arch/arm/boot/dts/imx6q-pinfunc.h b/arch/arm/boot/dts/imx6q-pinfunc.h
index faea6e1ada00..c0e38a45e4bb 100644
--- a/arch/arm/boot/dts/imx6q-pinfunc.h
+++ b/arch/arm/boot/dts/imx6q-pinfunc.h
@@ -14,1028 +14,1032 @@
14 * The pin function ID is a tuple of 14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val> 15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */ 16 */
17#define MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0 17#define MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x04c 0x360 0x000 0x0 0x0
18#define MX6Q_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0 18#define MX6QDL_PAD_SD2_DAT1__ECSPI5_SS0 0x04c 0x360 0x834 0x1 0x0
19#define MX6Q_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0 19#define MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0x04c 0x360 0x000 0x2 0x0
20#define MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0 20#define MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x04c 0x360 0x7c8 0x3 0x0
21#define MX6Q_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0 21#define MX6QDL_PAD_SD2_DAT1__KEY_COL7 0x04c 0x360 0x8f0 0x4 0x0
22#define MX6Q_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0 22#define MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x04c 0x360 0x000 0x5 0x0
23#define MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0 23#define MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x050 0x364 0x000 0x0 0x0
24#define MX6Q_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0 24#define MX6QDL_PAD_SD2_DAT2__ECSPI5_SS1 0x050 0x364 0x838 0x1 0x0
25#define MX6Q_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0 25#define MX6QDL_PAD_SD2_DAT2__EIM_CS3_B 0x050 0x364 0x000 0x2 0x0
26#define MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0 26#define MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x050 0x364 0x7b8 0x3 0x0
27#define MX6Q_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0 27#define MX6QDL_PAD_SD2_DAT2__KEY_ROW6 0x050 0x364 0x8f8 0x4 0x0
28#define MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0 28#define MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x050 0x364 0x000 0x5 0x0
29#define MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0 29#define MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x054 0x368 0x000 0x0 0x0
30#define MX6Q_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0 30#define MX6QDL_PAD_SD2_DAT0__ECSPI5_MISO 0x054 0x368 0x82c 0x1 0x0
31#define MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0 31#define MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x054 0x368 0x7b4 0x3 0x0
32#define MX6Q_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0 32#define MX6QDL_PAD_SD2_DAT0__KEY_ROW7 0x054 0x368 0x8fc 0x4 0x0
33#define MX6Q_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0 33#define MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x054 0x368 0x000 0x5 0x0
34#define MX6Q_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0 34#define MX6QDL_PAD_SD2_DAT0__DCIC2_OUT 0x054 0x368 0x000 0x6 0x0
35#define MX6Q_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0 35#define MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x058 0x36c 0x000 0x0 0x0
36#define MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0 36#define MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x058 0x36c 0x000 0x1 0x0
37#define MX6Q_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0 37#define MX6QDL_PAD_RGMII_TXC__SPDIF_EXT_CLK 0x058 0x36c 0x918 0x2 0x0
38#define MX6Q_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0 38#define MX6QDL_PAD_RGMII_TXC__GPIO6_IO19 0x058 0x36c 0x000 0x5 0x0
39#define MX6Q_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0 39#define MX6QDL_PAD_RGMII_TXC__XTALOSC_REF_CLK_24M 0x058 0x36c 0x000 0x7 0x0
40#define MX6Q_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0 40#define MX6QDL_PAD_RGMII_TD0__HSI_TX_READY 0x05c 0x370 0x000 0x0 0x0
41#define MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0 41#define MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x05c 0x370 0x000 0x1 0x0
42#define MX6Q_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0 42#define MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 0x05c 0x370 0x000 0x5 0x0
43#define MX6Q_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0 43#define MX6QDL_PAD_RGMII_TD1__HSI_RX_FLAG 0x060 0x374 0x000 0x0 0x0
44#define MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0 44#define MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x060 0x374 0x000 0x1 0x0
45#define MX6Q_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0 45#define MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 0x060 0x374 0x000 0x5 0x0
46#define MX6Q_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0 46#define MX6QDL_PAD_RGMII_TD2__HSI_RX_DATA 0x064 0x378 0x000 0x0 0x0
47#define MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0 47#define MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x064 0x378 0x000 0x1 0x0
48#define MX6Q_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0 48#define MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 0x064 0x378 0x000 0x5 0x0
49#define MX6Q_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0 49#define MX6QDL_PAD_RGMII_TD3__HSI_RX_WAKE 0x068 0x37c 0x000 0x0 0x0
50#define MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0 50#define MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x068 0x37c 0x000 0x1 0x0
51#define MX6Q_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0 51#define MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 0x068 0x37c 0x000 0x5 0x0
52#define MX6Q_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0 52#define MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x06c 0x380 0x000 0x0 0x0
53#define MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0 53#define MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x06c 0x380 0x858 0x1 0x0
54#define MX6Q_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0 54#define MX6QDL_PAD_RGMII_RX_CTL__GPIO6_IO24 0x06c 0x380 0x000 0x5 0x0
55#define MX6Q_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0 55#define MX6QDL_PAD_RGMII_RD0__HSI_RX_READY 0x070 0x384 0x000 0x0 0x0
56#define MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0 56#define MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x070 0x384 0x848 0x1 0x0
57#define MX6Q_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0 57#define MX6QDL_PAD_RGMII_RD0__GPIO6_IO25 0x070 0x384 0x000 0x5 0x0
58#define MX6Q_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0 58#define MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x074 0x388 0x000 0x0 0x0
59#define MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0 59#define MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x074 0x388 0x000 0x1 0x0
60#define MX6Q_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0 60#define MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 0x074 0x388 0x000 0x5 0x0
61#define MX6Q_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0 61#define MX6QDL_PAD_RGMII_TX_CTL__ENET_REF_CLK 0x074 0x388 0x83c 0x7 0x0
62#define MX6Q_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0 62#define MX6QDL_PAD_RGMII_RD1__HSI_TX_FLAG 0x078 0x38c 0x000 0x0 0x0
63#define MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0 63#define MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x078 0x38c 0x84c 0x1 0x0
64#define MX6Q_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0 64#define MX6QDL_PAD_RGMII_RD1__GPIO6_IO27 0x078 0x38c 0x000 0x5 0x0
65#define MX6Q_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0 65#define MX6QDL_PAD_RGMII_RD2__HSI_TX_DATA 0x07c 0x390 0x000 0x0 0x0
66#define MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0 66#define MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x07c 0x390 0x850 0x1 0x0
67#define MX6Q_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0 67#define MX6QDL_PAD_RGMII_RD2__GPIO6_IO28 0x07c 0x390 0x000 0x5 0x0
68#define MX6Q_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0 68#define MX6QDL_PAD_RGMII_RD3__HSI_TX_WAKE 0x080 0x394 0x000 0x0 0x0
69#define MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0 69#define MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x080 0x394 0x854 0x1 0x0
70#define MX6Q_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0 70#define MX6QDL_PAD_RGMII_RD3__GPIO6_IO29 0x080 0x394 0x000 0x5 0x0
71#define MX6Q_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0 71#define MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x084 0x398 0x000 0x0 0x0
72#define MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0 72#define MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x084 0x398 0x844 0x1 0x0
73#define MX6Q_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0 73#define MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 0x084 0x398 0x000 0x5 0x0
74#define MX6Q_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0 74#define MX6QDL_PAD_EIM_A25__EIM_ADDR25 0x088 0x39c 0x000 0x0 0x0
75#define MX6Q_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0 75#define MX6QDL_PAD_EIM_A25__ECSPI4_SS1 0x088 0x39c 0x000 0x1 0x0
76#define MX6Q_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0 76#define MX6QDL_PAD_EIM_A25__ECSPI2_RDY 0x088 0x39c 0x000 0x2 0x0
77#define MX6Q_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0 77#define MX6QDL_PAD_EIM_A25__IPU1_DI1_PIN12 0x088 0x39c 0x000 0x3 0x0
78#define MX6Q_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0 78#define MX6QDL_PAD_EIM_A25__IPU1_DI0_D1_CS 0x088 0x39c 0x000 0x4 0x0
79#define MX6Q_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0 79#define MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x088 0x39c 0x000 0x5 0x0
80#define MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0 80#define MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x088 0x39c 0x88c 0x6 0x0
81#define MX6Q_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0 81#define MX6QDL_PAD_EIM_EB2__EIM_EB2_B 0x08c 0x3a0 0x000 0x0 0x0
82#define MX6Q_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0 82#define MX6QDL_PAD_EIM_EB2__ECSPI1_SS0 0x08c 0x3a0 0x800 0x1 0x0
83#define MX6Q_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0 83#define MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x08c 0x3a0 0x8d4 0x3 0x0
84#define MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0 84#define MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x08c 0x3a0 0x890 0x4 0x0
85#define MX6Q_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0 85#define MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x08c 0x3a0 0x000 0x5 0x0
86#define MX6Q_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0 86#define MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x08c 0x3a0 0x8a0 0x6 0x0
87#define MX6Q_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0 87#define MX6QDL_PAD_EIM_EB2__SRC_BOOT_CFG30 0x08c 0x3a0 0x000 0x7 0x0
88#define MX6Q_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0 88#define MX6QDL_PAD_EIM_D16__EIM_DATA16 0x090 0x3a4 0x000 0x0 0x0
89#define MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0 89#define MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x090 0x3a4 0x7f4 0x1 0x0
90#define MX6Q_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0 90#define MX6QDL_PAD_EIM_D16__IPU1_DI0_PIN05 0x090 0x3a4 0x000 0x2 0x0
91#define MX6Q_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0 91#define MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x090 0x3a4 0x8d0 0x3 0x0
92#define MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0 92#define MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x090 0x3a4 0x894 0x4 0x0
93#define MX6Q_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0 93#define MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x090 0x3a4 0x000 0x5 0x0
94#define MX6Q_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0 94#define MX6QDL_PAD_EIM_D16__I2C2_SDA 0x090 0x3a4 0x8a4 0x6 0x0
95#define MX6Q_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0 95#define MX6QDL_PAD_EIM_D17__EIM_DATA17 0x094 0x3a8 0x000 0x0 0x0
96#define MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0 96#define MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x094 0x3a8 0x7f8 0x1 0x0
97#define MX6Q_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0 97#define MX6QDL_PAD_EIM_D17__IPU1_DI0_PIN06 0x094 0x3a8 0x000 0x2 0x0
98#define MX6Q_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0 98#define MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x094 0x3a8 0x8e0 0x3 0x0
99#define MX6Q_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0 99#define MX6QDL_PAD_EIM_D17__DCIC1_OUT 0x094 0x3a8 0x000 0x4 0x0
100#define MX6Q_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0 100#define MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x094 0x3a8 0x000 0x5 0x0
101#define MX6Q_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0 101#define MX6QDL_PAD_EIM_D17__I2C3_SCL 0x094 0x3a8 0x8a8 0x6 0x0
102#define MX6Q_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0 102#define MX6QDL_PAD_EIM_D18__EIM_DATA18 0x098 0x3ac 0x000 0x0 0x0
103#define MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0 103#define MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x098 0x3ac 0x7fc 0x1 0x0
104#define MX6Q_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0 104#define MX6QDL_PAD_EIM_D18__IPU1_DI0_PIN07 0x098 0x3ac 0x000 0x2 0x0
105#define MX6Q_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0 105#define MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x098 0x3ac 0x8cc 0x3 0x0
106#define MX6Q_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0 106#define MX6QDL_PAD_EIM_D18__IPU1_DI1_D0_CS 0x098 0x3ac 0x000 0x4 0x0
107#define MX6Q_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0 107#define MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x098 0x3ac 0x000 0x5 0x0
108#define MX6Q_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0 108#define MX6QDL_PAD_EIM_D18__I2C3_SDA 0x098 0x3ac 0x8ac 0x6 0x0
109#define MX6Q_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0 109#define MX6QDL_PAD_EIM_D19__EIM_DATA19 0x09c 0x3b0 0x000 0x0 0x0
110#define MX6Q_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0 110#define MX6QDL_PAD_EIM_D19__ECSPI1_SS1 0x09c 0x3b0 0x804 0x1 0x0
111#define MX6Q_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0 111#define MX6QDL_PAD_EIM_D19__IPU1_DI0_PIN08 0x09c 0x3b0 0x000 0x2 0x0
112#define MX6Q_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0 112#define MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x09c 0x3b0 0x8c8 0x3 0x0
113#define MX6Q_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0 113#define MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x09c 0x3b0 0x000 0x4 0x0
114#define MX6Q_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0 114#define MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x09c 0x3b0 0x91c 0x4 0x0
115#define MX6Q_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0 115#define MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x09c 0x3b0 0x000 0x5 0x0
116#define MX6Q_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0 116#define MX6QDL_PAD_EIM_D19__EPIT1_OUT 0x09c 0x3b0 0x000 0x6 0x0
117#define MX6Q_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0 117#define MX6QDL_PAD_EIM_D20__EIM_DATA20 0x0a0 0x3b4 0x000 0x0 0x0
118#define MX6Q_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0 118#define MX6QDL_PAD_EIM_D20__ECSPI4_SS0 0x0a0 0x3b4 0x824 0x1 0x0
119#define MX6Q_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0 119#define MX6QDL_PAD_EIM_D20__IPU1_DI0_PIN16 0x0a0 0x3b4 0x000 0x2 0x0
120#define MX6Q_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0 120#define MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x0a0 0x3b4 0x8c4 0x3 0x0
121#define MX6Q_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1 121#define MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x0a0 0x3b4 0x91c 0x4 0x1
122#define MX6Q_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0 122#define MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0a0 0x3b4 0x000 0x4 0x0
123#define MX6Q_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0 123#define MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x0a0 0x3b4 0x000 0x5 0x0
124#define MX6Q_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0 124#define MX6QDL_PAD_EIM_D20__EPIT2_OUT 0x0a0 0x3b4 0x000 0x6 0x0
125#define MX6Q_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0 125#define MX6QDL_PAD_EIM_D21__EIM_DATA21 0x0a4 0x3b8 0x000 0x0 0x0
126#define MX6Q_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0 126#define MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x0a4 0x3b8 0x000 0x1 0x0
127#define MX6Q_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0 127#define MX6QDL_PAD_EIM_D21__IPU1_DI0_PIN17 0x0a4 0x3b8 0x000 0x2 0x0
128#define MX6Q_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0 128#define MX6QDL_PAD_EIM_D21__IPU2_CSI1_DATA11 0x0a4 0x3b8 0x8b4 0x3 0x0
129#define MX6Q_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0 129#define MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x0a4 0x3b8 0x944 0x4 0x0
130#define MX6Q_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0 130#define MX6QDL_PAD_EIM_D21__GPIO3_IO21 0x0a4 0x3b8 0x000 0x5 0x0
131#define MX6Q_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0 131#define MX6QDL_PAD_EIM_D21__I2C1_SCL 0x0a4 0x3b8 0x898 0x6 0x0
132#define MX6Q_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0 132#define MX6QDL_PAD_EIM_D21__SPDIF_IN 0x0a4 0x3b8 0x914 0x7 0x0
133#define MX6Q_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0 133#define MX6QDL_PAD_EIM_D22__EIM_DATA22 0x0a8 0x3bc 0x000 0x0 0x0
134#define MX6Q_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0 134#define MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x0a8 0x3bc 0x000 0x1 0x0
135#define MX6Q_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0 135#define MX6QDL_PAD_EIM_D22__IPU1_DI0_PIN01 0x0a8 0x3bc 0x000 0x2 0x0
136#define MX6Q_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0 136#define MX6QDL_PAD_EIM_D22__IPU2_CSI1_DATA10 0x0a8 0x3bc 0x8b0 0x3 0x0
137#define MX6Q_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0 137#define MX6QDL_PAD_EIM_D22__USB_OTG_PWR 0x0a8 0x3bc 0x000 0x4 0x0
138#define MX6Q_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0 138#define MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0a8 0x3bc 0x000 0x5 0x0
139#define MX6Q_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0 139#define MX6QDL_PAD_EIM_D22__SPDIF_OUT 0x0a8 0x3bc 0x000 0x6 0x0
140#define MX6Q_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0 140#define MX6QDL_PAD_EIM_D23__EIM_DATA23 0x0ac 0x3c0 0x000 0x0 0x0
141#define MX6Q_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0 141#define MX6QDL_PAD_EIM_D23__IPU1_DI0_D0_CS 0x0ac 0x3c0 0x000 0x1 0x0
142#define MX6Q_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0 142#define MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x0ac 0x3c0 0x000 0x2 0x0
143#define MX6Q_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0 143#define MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x0ac 0x3c0 0x92c 0x2 0x0
144#define MX6Q_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0 144#define MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x0ac 0x3c0 0x000 0x3 0x0
145#define MX6Q_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0 145#define MX6QDL_PAD_EIM_D23__IPU2_CSI1_DATA_EN 0x0ac 0x3c0 0x8d8 0x4 0x0
146#define MX6Q_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0 146#define MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0ac 0x3c0 0x000 0x5 0x0
147#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0 147#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN02 0x0ac 0x3c0 0x000 0x6 0x0
148#define MX6Q_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0 148#define MX6QDL_PAD_EIM_D23__IPU1_DI1_PIN14 0x0ac 0x3c0 0x000 0x7 0x0
149#define MX6Q_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0 149#define MX6QDL_PAD_EIM_EB3__EIM_EB3_B 0x0b0 0x3c4 0x000 0x0 0x0
150#define MX6Q_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0 150#define MX6QDL_PAD_EIM_EB3__ECSPI4_RDY 0x0b0 0x3c4 0x000 0x1 0x0
151#define MX6Q_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1 151#define MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x0b0 0x3c4 0x92c 0x2 0x1
152#define MX6Q_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0 152#define MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x0b0 0x3c4 0x000 0x2 0x0
153#define MX6Q_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0 153#define MX6QDL_PAD_EIM_EB3__UART1_RI_B 0x0b0 0x3c4 0x000 0x3 0x0
154#define MX6Q_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0 154#define MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x0b0 0x3c4 0x8dc 0x4 0x0
155#define MX6Q_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0 155#define MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x0b0 0x3c4 0x000 0x5 0x0
156#define MX6Q_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0 156#define MX6QDL_PAD_EIM_EB3__IPU1_DI1_PIN03 0x0b0 0x3c4 0x000 0x6 0x0
157#define MX6Q_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0 157#define MX6QDL_PAD_EIM_EB3__SRC_BOOT_CFG31 0x0b0 0x3c4 0x000 0x7 0x0
158#define MX6Q_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0 158#define MX6QDL_PAD_EIM_D24__EIM_DATA24 0x0b4 0x3c8 0x000 0x0 0x0
159#define MX6Q_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0 159#define MX6QDL_PAD_EIM_D24__ECSPI4_SS2 0x0b4 0x3c8 0x000 0x1 0x0
160#define MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0 160#define MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x0b4 0x3c8 0x000 0x2 0x0
161#define MX6Q_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0 161#define MX6QDL_PAD_EIM_D24__UART3_RX_DATA 0x0b4 0x3c8 0x930 0x2 0x0
162#define MX6Q_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0 162#define MX6QDL_PAD_EIM_D24__ECSPI1_SS2 0x0b4 0x3c8 0x808 0x3 0x0
163#define MX6Q_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0 163#define MX6QDL_PAD_EIM_D24__ECSPI2_SS2 0x0b4 0x3c8 0x000 0x4 0x0
164#define MX6Q_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0 164#define MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0b4 0x3c8 0x000 0x5 0x0
165#define MX6Q_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0 165#define MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x0b4 0x3c8 0x7d8 0x6 0x0
166#define MX6Q_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0 166#define MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x0b4 0x3c8 0x000 0x7 0x0
167#define MX6Q_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0 167#define MX6QDL_PAD_EIM_D25__EIM_DATA25 0x0b8 0x3cc 0x000 0x0 0x0
168#define MX6Q_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0 168#define MX6QDL_PAD_EIM_D25__ECSPI4_SS3 0x0b8 0x3cc 0x000 0x1 0x0
169#define MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1 169#define MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x0b8 0x3cc 0x930 0x2 0x1
170#define MX6Q_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0 170#define MX6QDL_PAD_EIM_D25__UART3_TX_DATA 0x0b8 0x3cc 0x000 0x2 0x0
171#define MX6Q_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0 171#define MX6QDL_PAD_EIM_D25__ECSPI1_SS3 0x0b8 0x3cc 0x80c 0x3 0x0
172#define MX6Q_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0 172#define MX6QDL_PAD_EIM_D25__ECSPI2_SS3 0x0b8 0x3cc 0x000 0x4 0x0
173#define MX6Q_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0 173#define MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0b8 0x3cc 0x000 0x5 0x0
174#define MX6Q_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0 174#define MX6QDL_PAD_EIM_D25__AUD5_RXC 0x0b8 0x3cc 0x7d4 0x6 0x0
175#define MX6Q_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0 175#define MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x0b8 0x3cc 0x000 0x7 0x0
176#define MX6Q_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0 176#define MX6QDL_PAD_EIM_D26__EIM_DATA26 0x0bc 0x3d0 0x000 0x0 0x0
177#define MX6Q_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0 177#define MX6QDL_PAD_EIM_D26__IPU1_DI1_PIN11 0x0bc 0x3d0 0x000 0x1 0x0
178#define MX6Q_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0 178#define MX6QDL_PAD_EIM_D26__IPU1_CSI0_DATA01 0x0bc 0x3d0 0x000 0x2 0x0
179#define MX6Q_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0 179#define MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x0bc 0x3d0 0x8c0 0x3 0x0
180#define MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0 180#define MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x0bc 0x3d0 0x000 0x4 0x0
181#define MX6Q_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0 181#define MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0bc 0x3d0 0x928 0x4 0x0
182#define MX6Q_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0 182#define MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x0bc 0x3d0 0x000 0x5 0x0
183#define MX6Q_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0 183#define MX6QDL_PAD_EIM_D26__IPU1_SISG2 0x0bc 0x3d0 0x000 0x6 0x0
184#define MX6Q_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0 184#define MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22 0x0bc 0x3d0 0x000 0x7 0x0
185#define MX6Q_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0 185#define MX6QDL_PAD_EIM_D27__EIM_DATA27 0x0c0 0x3d4 0x000 0x0 0x0
186#define MX6Q_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0 186#define MX6QDL_PAD_EIM_D27__IPU1_DI1_PIN13 0x0c0 0x3d4 0x000 0x1 0x0
187#define MX6Q_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0 187#define MX6QDL_PAD_EIM_D27__IPU1_CSI0_DATA00 0x0c0 0x3d4 0x000 0x2 0x0
188#define MX6Q_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0 188#define MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x0c0 0x3d4 0x8bc 0x3 0x0
189#define MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1 189#define MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x0c0 0x3d4 0x928 0x4 0x1
190#define MX6Q_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0 190#define MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0c0 0x3d4 0x000 0x4 0x0
191#define MX6Q_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0 191#define MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x0c0 0x3d4 0x000 0x5 0x0
192#define MX6Q_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0 192#define MX6QDL_PAD_EIM_D27__IPU1_SISG3 0x0c0 0x3d4 0x000 0x6 0x0
193#define MX6Q_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0 193#define MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23 0x0c0 0x3d4 0x000 0x7 0x0
194#define MX6Q_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0 194#define MX6QDL_PAD_EIM_D28__EIM_DATA28 0x0c4 0x3d8 0x000 0x0 0x0
195#define MX6Q_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0 195#define MX6QDL_PAD_EIM_D28__I2C1_SDA 0x0c4 0x3d8 0x89c 0x1 0x0
196#define MX6Q_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0 196#define MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x0c4 0x3d8 0x000 0x2 0x0
197#define MX6Q_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0 197#define MX6QDL_PAD_EIM_D28__IPU2_CSI1_DATA12 0x0c4 0x3d8 0x8b8 0x3 0x0
198#define MX6Q_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0 198#define MX6QDL_PAD_EIM_D28__UART2_CTS_B 0x0c4 0x3d8 0x000 0x4 0x0
199#define MX6Q_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0 199#define MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0c4 0x3d8 0x924 0x4 0x0
200#define MX6Q_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0 200#define MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x0c4 0x3d8 0x924 0x4 0x0
201#define MX6Q_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0 201#define MX6QDL_PAD_EIM_D28__UART2_DTE_RTS_B 0x0c4 0x3d8 0x000 0x4 0x0
202#define MX6Q_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0 202#define MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0c4 0x3d8 0x000 0x5 0x0
203#define MX6Q_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0 203#define MX6QDL_PAD_EIM_D28__IPU1_EXT_TRIG 0x0c4 0x3d8 0x000 0x6 0x0
204#define MX6Q_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0 204#define MX6QDL_PAD_EIM_D28__IPU1_DI0_PIN13 0x0c4 0x3d8 0x000 0x7 0x0
205#define MX6Q_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1 205#define MX6QDL_PAD_EIM_D29__EIM_DATA29 0x0c8 0x3dc 0x000 0x0 0x0
206#define MX6Q_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1 206#define MX6QDL_PAD_EIM_D29__IPU1_DI1_PIN15 0x0c8 0x3dc 0x000 0x1 0x0
207#define MX6Q_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0 207#define MX6QDL_PAD_EIM_D29__ECSPI4_SS0 0x0c8 0x3dc 0x824 0x2 0x1
208#define MX6Q_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0 208#define MX6QDL_PAD_EIM_D29__UART2_RTS_B 0x0c8 0x3dc 0x924 0x4 0x1
209#define MX6Q_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0 209#define MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0c8 0x3dc 0x000 0x4 0x0
210#define MX6Q_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0 210#define MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x0c4 0x3dc 0x000 0x4 0x0
211#define MX6Q_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0 211#define MX6QDL_PAD_EIM_D29__UART2_DTE_CTS_B 0x0c4 0x3dc 0x924 0x4 0x1
212#define MX6Q_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0 212#define MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x0c8 0x3dc 0x000 0x5 0x0
213#define MX6Q_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0 213#define MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x0c8 0x3dc 0x8e4 0x6 0x0
214#define MX6Q_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0 214#define MX6QDL_PAD_EIM_D29__IPU1_DI0_PIN14 0x0c8 0x3dc 0x000 0x7 0x0
215#define MX6Q_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0 215#define MX6QDL_PAD_EIM_D30__EIM_DATA30 0x0cc 0x3e0 0x000 0x0 0x0
216#define MX6Q_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2 216#define MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21 0x0cc 0x3e0 0x000 0x1 0x0
217#define MX6Q_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0 217#define MX6QDL_PAD_EIM_D30__IPU1_DI0_PIN11 0x0cc 0x3e0 0x000 0x2 0x0
218#define MX6Q_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0 218#define MX6QDL_PAD_EIM_D30__IPU1_CSI0_DATA03 0x0cc 0x3e0 0x000 0x3 0x0
219#define MX6Q_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0 219#define MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x0cc 0x3e0 0x000 0x4 0x0
220#define MX6Q_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0 220#define MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x0cc 0x3e0 0x92c 0x4 0x2
221#define MX6Q_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0 221#define MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x0cc 0x3e0 0x000 0x5 0x0
222#define MX6Q_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0 222#define MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0cc 0x3e0 0x948 0x6 0x0
223#define MX6Q_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3 223#define MX6QDL_PAD_EIM_D31__EIM_DATA31 0x0d0 0x3e4 0x000 0x0 0x0
224#define MX6Q_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0 224#define MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20 0x0d0 0x3e4 0x000 0x1 0x0
225#define MX6Q_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0 225#define MX6QDL_PAD_EIM_D31__IPU1_DI0_PIN12 0x0d0 0x3e4 0x000 0x2 0x0
226#define MX6Q_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0 226#define MX6QDL_PAD_EIM_D31__IPU1_CSI0_DATA02 0x0d0 0x3e4 0x000 0x3 0x0
227#define MX6Q_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0 227#define MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x0d0 0x3e4 0x92c 0x4 0x3
228#define MX6Q_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0 228#define MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x0d0 0x3e4 0x000 0x4 0x0
229#define MX6Q_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1 229#define MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0d0 0x3e4 0x000 0x5 0x0
230#define MX6Q_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0 230#define MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x0d0 0x3e4 0x000 0x6 0x0
231#define MX6Q_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0 231#define MX6QDL_PAD_EIM_A24__EIM_ADDR24 0x0d4 0x3e8 0x000 0x0 0x0
232#define MX6Q_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0 232#define MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19 0x0d4 0x3e8 0x000 0x1 0x0
233#define MX6Q_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0 233#define MX6QDL_PAD_EIM_A24__IPU2_CSI1_DATA19 0x0d4 0x3e8 0x8d4 0x2 0x1
234#define MX6Q_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0 234#define MX6QDL_PAD_EIM_A24__IPU2_SISG2 0x0d4 0x3e8 0x000 0x3 0x0
235#define MX6Q_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0 235#define MX6QDL_PAD_EIM_A24__IPU1_SISG2 0x0d4 0x3e8 0x000 0x4 0x0
236#define MX6Q_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1 236#define MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0d4 0x3e8 0x000 0x5 0x0
237#define MX6Q_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0 237#define MX6QDL_PAD_EIM_A24__SRC_BOOT_CFG24 0x0d4 0x3e8 0x000 0x7 0x0
238#define MX6Q_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0 238#define MX6QDL_PAD_EIM_A23__EIM_ADDR23 0x0d8 0x3ec 0x000 0x0 0x0
239#define MX6Q_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0 239#define MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18 0x0d8 0x3ec 0x000 0x1 0x0
240#define MX6Q_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0 240#define MX6QDL_PAD_EIM_A23__IPU2_CSI1_DATA18 0x0d8 0x3ec 0x8d0 0x2 0x1
241#define MX6Q_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0 241#define MX6QDL_PAD_EIM_A23__IPU2_SISG3 0x0d8 0x3ec 0x000 0x3 0x0
242#define MX6Q_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0 242#define MX6QDL_PAD_EIM_A23__IPU1_SISG3 0x0d8 0x3ec 0x000 0x4 0x0
243#define MX6Q_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1 243#define MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x0d8 0x3ec 0x000 0x5 0x0
244#define MX6Q_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0 244#define MX6QDL_PAD_EIM_A23__SRC_BOOT_CFG23 0x0d8 0x3ec 0x000 0x7 0x0
245#define MX6Q_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0 245#define MX6QDL_PAD_EIM_A22__EIM_ADDR22 0x0dc 0x3f0 0x000 0x0 0x0
246#define MX6Q_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0 246#define MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17 0x0dc 0x3f0 0x000 0x1 0x0
247#define MX6Q_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0 247#define MX6QDL_PAD_EIM_A22__IPU2_CSI1_DATA17 0x0dc 0x3f0 0x8cc 0x2 0x1
248#define MX6Q_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1 248#define MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x0dc 0x3f0 0x000 0x5 0x0
249#define MX6Q_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0 249#define MX6QDL_PAD_EIM_A22__SRC_BOOT_CFG22 0x0dc 0x3f0 0x000 0x7 0x0
250#define MX6Q_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0 250#define MX6QDL_PAD_EIM_A21__EIM_ADDR21 0x0e0 0x3f4 0x000 0x0 0x0
251#define MX6Q_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0 251#define MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16 0x0e0 0x3f4 0x000 0x1 0x0
252#define MX6Q_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0 252#define MX6QDL_PAD_EIM_A21__IPU2_CSI1_DATA16 0x0e0 0x3f4 0x8c8 0x2 0x1
253#define MX6Q_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1 253#define MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x0e0 0x3f4 0x000 0x5 0x0
254#define MX6Q_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0 254#define MX6QDL_PAD_EIM_A21__SRC_BOOT_CFG21 0x0e0 0x3f4 0x000 0x7 0x0
255#define MX6Q_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0 255#define MX6QDL_PAD_EIM_A20__EIM_ADDR20 0x0e4 0x3f8 0x000 0x0 0x0
256#define MX6Q_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0 256#define MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15 0x0e4 0x3f8 0x000 0x1 0x0
257#define MX6Q_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0 257#define MX6QDL_PAD_EIM_A20__IPU2_CSI1_DATA15 0x0e4 0x3f8 0x8c4 0x2 0x1
258#define MX6Q_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1 258#define MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x0e4 0x3f8 0x000 0x5 0x0
259#define MX6Q_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0 259#define MX6QDL_PAD_EIM_A20__SRC_BOOT_CFG20 0x0e4 0x3f8 0x000 0x7 0x0
260#define MX6Q_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0 260#define MX6QDL_PAD_EIM_A19__EIM_ADDR19 0x0e8 0x3fc 0x000 0x0 0x0
261#define MX6Q_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0 261#define MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14 0x0e8 0x3fc 0x000 0x1 0x0
262#define MX6Q_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0 262#define MX6QDL_PAD_EIM_A19__IPU2_CSI1_DATA14 0x0e8 0x3fc 0x8c0 0x2 0x1
263#define MX6Q_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1 263#define MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x0e8 0x3fc 0x000 0x5 0x0
264#define MX6Q_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0 264#define MX6QDL_PAD_EIM_A19__SRC_BOOT_CFG19 0x0e8 0x3fc 0x000 0x7 0x0
265#define MX6Q_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0 265#define MX6QDL_PAD_EIM_A18__EIM_ADDR18 0x0ec 0x400 0x000 0x0 0x0
266#define MX6Q_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0 266#define MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13 0x0ec 0x400 0x000 0x1 0x0
267#define MX6Q_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0 267#define MX6QDL_PAD_EIM_A18__IPU2_CSI1_DATA13 0x0ec 0x400 0x8bc 0x2 0x1
268#define MX6Q_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1 268#define MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x0ec 0x400 0x000 0x5 0x0
269#define MX6Q_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0 269#define MX6QDL_PAD_EIM_A18__SRC_BOOT_CFG18 0x0ec 0x400 0x000 0x7 0x0
270#define MX6Q_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0 270#define MX6QDL_PAD_EIM_A17__EIM_ADDR17 0x0f0 0x404 0x000 0x0 0x0
271#define MX6Q_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0 271#define MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12 0x0f0 0x404 0x000 0x1 0x0
272#define MX6Q_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0 272#define MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x0f0 0x404 0x8b8 0x2 0x1
273#define MX6Q_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1 273#define MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x0f0 0x404 0x000 0x5 0x0
274#define MX6Q_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0 274#define MX6QDL_PAD_EIM_A17__SRC_BOOT_CFG17 0x0f0 0x404 0x000 0x7 0x0
275#define MX6Q_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0 275#define MX6QDL_PAD_EIM_A16__EIM_ADDR16 0x0f4 0x408 0x000 0x0 0x0
276#define MX6Q_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0 276#define MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK 0x0f4 0x408 0x000 0x1 0x0
277#define MX6Q_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0 277#define MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x0f4 0x408 0x8e0 0x2 0x1
278#define MX6Q_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0 278#define MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x0f4 0x408 0x000 0x5 0x0
279#define MX6Q_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0 279#define MX6QDL_PAD_EIM_A16__SRC_BOOT_CFG16 0x0f4 0x408 0x000 0x7 0x0
280#define MX6Q_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0 280#define MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0x0f8 0x40c 0x000 0x0 0x0
281#define MX6Q_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0 281#define MX6QDL_PAD_EIM_CS0__IPU1_DI1_PIN05 0x0f8 0x40c 0x000 0x1 0x0
282#define MX6Q_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0 282#define MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x0f8 0x40c 0x810 0x2 0x0
283#define MX6Q_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0 283#define MX6QDL_PAD_EIM_CS0__GPIO2_IO23 0x0f8 0x40c 0x000 0x5 0x0
284#define MX6Q_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0 284#define MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0x0fc 0x410 0x000 0x0 0x0
285#define MX6Q_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0 285#define MX6QDL_PAD_EIM_CS1__IPU1_DI1_PIN06 0x0fc 0x410 0x000 0x1 0x0
286#define MX6Q_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0 286#define MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x0fc 0x410 0x818 0x2 0x0
287#define MX6Q_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0 287#define MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x0fc 0x410 0x000 0x5 0x0
288#define MX6Q_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0 288#define MX6QDL_PAD_EIM_OE__EIM_OE_B 0x100 0x414 0x000 0x0 0x0
289#define MX6Q_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0 289#define MX6QDL_PAD_EIM_OE__IPU1_DI1_PIN07 0x100 0x414 0x000 0x1 0x0
290#define MX6Q_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0 290#define MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100 0x414 0x814 0x2 0x0
291#define MX6Q_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0 291#define MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x100 0x414 0x000 0x5 0x0
292#define MX6Q_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0 292#define MX6QDL_PAD_EIM_RW__EIM_RW 0x104 0x418 0x000 0x0 0x0
293#define MX6Q_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0 293#define MX6QDL_PAD_EIM_RW__IPU1_DI1_PIN08 0x104 0x418 0x000 0x1 0x0
294#define MX6Q_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0 294#define MX6QDL_PAD_EIM_RW__ECSPI2_SS0 0x104 0x418 0x81c 0x2 0x0
295#define MX6Q_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0 295#define MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x104 0x418 0x000 0x5 0x0
296#define MX6Q_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0 296#define MX6QDL_PAD_EIM_RW__SRC_BOOT_CFG29 0x104 0x418 0x000 0x7 0x0
297#define MX6Q_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0 297#define MX6QDL_PAD_EIM_LBA__EIM_LBA_B 0x108 0x41c 0x000 0x0 0x0
298#define MX6Q_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0 298#define MX6QDL_PAD_EIM_LBA__IPU1_DI1_PIN17 0x108 0x41c 0x000 0x1 0x0
299#define MX6Q_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0 299#define MX6QDL_PAD_EIM_LBA__ECSPI2_SS1 0x108 0x41c 0x820 0x2 0x0
300#define MX6Q_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1 300#define MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x108 0x41c 0x000 0x5 0x0
301#define MX6Q_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0 301#define MX6QDL_PAD_EIM_LBA__SRC_BOOT_CFG26 0x108 0x41c 0x000 0x7 0x0
302#define MX6Q_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0 302#define MX6QDL_PAD_EIM_EB0__EIM_EB0_B 0x10c 0x420 0x000 0x0 0x0
303#define MX6Q_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0 303#define MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11 0x10c 0x420 0x000 0x1 0x0
304#define MX6Q_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0 304#define MX6QDL_PAD_EIM_EB0__IPU2_CSI1_DATA11 0x10c 0x420 0x8b4 0x2 0x1
305#define MX6Q_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0 305#define MX6QDL_PAD_EIM_EB0__CCM_PMIC_READY 0x10c 0x420 0x7f0 0x4 0x0
306#define MX6Q_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1 306#define MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x10c 0x420 0x000 0x5 0x0
307#define MX6Q_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0 307#define MX6QDL_PAD_EIM_EB0__SRC_BOOT_CFG27 0x10c 0x420 0x000 0x7 0x0
308#define MX6Q_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0 308#define MX6QDL_PAD_EIM_EB1__EIM_EB1_B 0x110 0x424 0x000 0x0 0x0
309#define MX6Q_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0 309#define MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10 0x110 0x424 0x000 0x1 0x0
310#define MX6Q_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0 310#define MX6QDL_PAD_EIM_EB1__IPU2_CSI1_DATA10 0x110 0x424 0x8b0 0x2 0x1
311#define MX6Q_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0 311#define MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x110 0x424 0x000 0x5 0x0
312#define MX6Q_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0 312#define MX6QDL_PAD_EIM_EB1__SRC_BOOT_CFG28 0x110 0x424 0x000 0x7 0x0
313#define MX6Q_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0 313#define MX6QDL_PAD_EIM_DA0__EIM_AD00 0x114 0x428 0x000 0x0 0x0
314#define MX6Q_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0 314#define MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09 0x114 0x428 0x000 0x1 0x0
315#define MX6Q_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0 315#define MX6QDL_PAD_EIM_DA0__IPU2_CSI1_DATA09 0x114 0x428 0x000 0x2 0x0
316#define MX6Q_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0 316#define MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x114 0x428 0x000 0x5 0x0
317#define MX6Q_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0 317#define MX6QDL_PAD_EIM_DA0__SRC_BOOT_CFG00 0x114 0x428 0x000 0x7 0x0
318#define MX6Q_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0 318#define MX6QDL_PAD_EIM_DA1__EIM_AD01 0x118 0x42c 0x000 0x0 0x0
319#define MX6Q_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0 319#define MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08 0x118 0x42c 0x000 0x1 0x0
320#define MX6Q_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0 320#define MX6QDL_PAD_EIM_DA1__IPU2_CSI1_DATA08 0x118 0x42c 0x000 0x2 0x0
321#define MX6Q_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0 321#define MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x118 0x42c 0x000 0x5 0x0
322#define MX6Q_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0 322#define MX6QDL_PAD_EIM_DA1__SRC_BOOT_CFG01 0x118 0x42c 0x000 0x7 0x0
323#define MX6Q_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0 323#define MX6QDL_PAD_EIM_DA2__EIM_AD02 0x11c 0x430 0x000 0x0 0x0
324#define MX6Q_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0 324#define MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07 0x11c 0x430 0x000 0x1 0x0
325#define MX6Q_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0 325#define MX6QDL_PAD_EIM_DA2__IPU2_CSI1_DATA07 0x11c 0x430 0x000 0x2 0x0
326#define MX6Q_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0 326#define MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x11c 0x430 0x000 0x5 0x0
327#define MX6Q_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0 327#define MX6QDL_PAD_EIM_DA2__SRC_BOOT_CFG02 0x11c 0x430 0x000 0x7 0x0
328#define MX6Q_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0 328#define MX6QDL_PAD_EIM_DA3__EIM_AD03 0x120 0x434 0x000 0x0 0x0
329#define MX6Q_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0 329#define MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06 0x120 0x434 0x000 0x1 0x0
330#define MX6Q_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0 330#define MX6QDL_PAD_EIM_DA3__IPU2_CSI1_DATA06 0x120 0x434 0x000 0x2 0x0
331#define MX6Q_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0 331#define MX6QDL_PAD_EIM_DA3__GPIO3_IO03 0x120 0x434 0x000 0x5 0x0
332#define MX6Q_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0 332#define MX6QDL_PAD_EIM_DA3__SRC_BOOT_CFG03 0x120 0x434 0x000 0x7 0x0
333#define MX6Q_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0 333#define MX6QDL_PAD_EIM_DA4__EIM_AD04 0x124 0x438 0x000 0x0 0x0
334#define MX6Q_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0 334#define MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05 0x124 0x438 0x000 0x1 0x0
335#define MX6Q_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0 335#define MX6QDL_PAD_EIM_DA4__IPU2_CSI1_DATA05 0x124 0x438 0x000 0x2 0x0
336#define MX6Q_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0 336#define MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0x124 0x438 0x000 0x5 0x0
337#define MX6Q_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0 337#define MX6QDL_PAD_EIM_DA4__SRC_BOOT_CFG04 0x124 0x438 0x000 0x7 0x0
338#define MX6Q_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0 338#define MX6QDL_PAD_EIM_DA5__EIM_AD05 0x128 0x43c 0x000 0x0 0x0
339#define MX6Q_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0 339#define MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04 0x128 0x43c 0x000 0x1 0x0
340#define MX6Q_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0 340#define MX6QDL_PAD_EIM_DA5__IPU2_CSI1_DATA04 0x128 0x43c 0x000 0x2 0x0
341#define MX6Q_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0 341#define MX6QDL_PAD_EIM_DA5__GPIO3_IO05 0x128 0x43c 0x000 0x5 0x0
342#define MX6Q_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0 342#define MX6QDL_PAD_EIM_DA5__SRC_BOOT_CFG05 0x128 0x43c 0x000 0x7 0x0
343#define MX6Q_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0 343#define MX6QDL_PAD_EIM_DA6__EIM_AD06 0x12c 0x440 0x000 0x0 0x0
344#define MX6Q_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0 344#define MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03 0x12c 0x440 0x000 0x1 0x0
345#define MX6Q_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0 345#define MX6QDL_PAD_EIM_DA6__IPU2_CSI1_DATA03 0x12c 0x440 0x000 0x2 0x0
346#define MX6Q_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0 346#define MX6QDL_PAD_EIM_DA6__GPIO3_IO06 0x12c 0x440 0x000 0x5 0x0
347#define MX6Q_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0 347#define MX6QDL_PAD_EIM_DA6__SRC_BOOT_CFG06 0x12c 0x440 0x000 0x7 0x0
348#define MX6Q_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0 348#define MX6QDL_PAD_EIM_DA7__EIM_AD07 0x130 0x444 0x000 0x0 0x0
349#define MX6Q_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0 349#define MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02 0x130 0x444 0x000 0x1 0x0
350#define MX6Q_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0 350#define MX6QDL_PAD_EIM_DA7__IPU2_CSI1_DATA02 0x130 0x444 0x000 0x2 0x0
351#define MX6Q_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0 351#define MX6QDL_PAD_EIM_DA7__GPIO3_IO07 0x130 0x444 0x000 0x5 0x0
352#define MX6Q_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0 352#define MX6QDL_PAD_EIM_DA7__SRC_BOOT_CFG07 0x130 0x444 0x000 0x7 0x0
353#define MX6Q_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0 353#define MX6QDL_PAD_EIM_DA8__EIM_AD08 0x134 0x448 0x000 0x0 0x0
354#define MX6Q_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0 354#define MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01 0x134 0x448 0x000 0x1 0x0
355#define MX6Q_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0 355#define MX6QDL_PAD_EIM_DA8__IPU2_CSI1_DATA01 0x134 0x448 0x000 0x2 0x0
356#define MX6Q_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0 356#define MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x134 0x448 0x000 0x5 0x0
357#define MX6Q_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0 357#define MX6QDL_PAD_EIM_DA8__SRC_BOOT_CFG08 0x134 0x448 0x000 0x7 0x0
358#define MX6Q_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0 358#define MX6QDL_PAD_EIM_DA9__EIM_AD09 0x138 0x44c 0x000 0x0 0x0
359#define MX6Q_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0 359#define MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00 0x138 0x44c 0x000 0x1 0x0
360#define MX6Q_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0 360#define MX6QDL_PAD_EIM_DA9__IPU2_CSI1_DATA00 0x138 0x44c 0x000 0x2 0x0
361#define MX6Q_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1 361#define MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x138 0x44c 0x000 0x5 0x0
362#define MX6Q_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0 362#define MX6QDL_PAD_EIM_DA9__SRC_BOOT_CFG09 0x138 0x44c 0x000 0x7 0x0
363#define MX6Q_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0 363#define MX6QDL_PAD_EIM_DA10__EIM_AD10 0x13c 0x450 0x000 0x0 0x0
364#define MX6Q_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0 364#define MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15 0x13c 0x450 0x000 0x1 0x0
365#define MX6Q_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0 365#define MX6QDL_PAD_EIM_DA10__IPU2_CSI1_DATA_EN 0x13c 0x450 0x8d8 0x2 0x1
366#define MX6Q_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1 366#define MX6QDL_PAD_EIM_DA10__GPIO3_IO10 0x13c 0x450 0x000 0x5 0x0
367#define MX6Q_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0 367#define MX6QDL_PAD_EIM_DA10__SRC_BOOT_CFG10 0x13c 0x450 0x000 0x7 0x0
368#define MX6Q_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0 368#define MX6QDL_PAD_EIM_DA11__EIM_AD11 0x140 0x454 0x000 0x0 0x0
369#define MX6Q_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0 369#define MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02 0x140 0x454 0x000 0x1 0x0
370#define MX6Q_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0 370#define MX6QDL_PAD_EIM_DA11__IPU2_CSI1_HSYNC 0x140 0x454 0x8dc 0x2 0x1
371#define MX6Q_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1 371#define MX6QDL_PAD_EIM_DA11__GPIO3_IO11 0x140 0x454 0x000 0x5 0x0
372#define MX6Q_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0 372#define MX6QDL_PAD_EIM_DA11__SRC_BOOT_CFG11 0x140 0x454 0x000 0x7 0x0
373#define MX6Q_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0 373#define MX6QDL_PAD_EIM_DA12__EIM_AD12 0x144 0x458 0x000 0x0 0x0
374#define MX6Q_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0 374#define MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03 0x144 0x458 0x000 0x1 0x0
375#define MX6Q_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0 375#define MX6QDL_PAD_EIM_DA12__IPU2_CSI1_VSYNC 0x144 0x458 0x8e4 0x2 0x1
376#define MX6Q_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0 376#define MX6QDL_PAD_EIM_DA12__GPIO3_IO12 0x144 0x458 0x000 0x5 0x0
377#define MX6Q_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0 377#define MX6QDL_PAD_EIM_DA12__SRC_BOOT_CFG12 0x144 0x458 0x000 0x7 0x0
378#define MX6Q_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0 378#define MX6QDL_PAD_EIM_DA13__EIM_AD13 0x148 0x45c 0x000 0x0 0x0
379#define MX6Q_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0 379#define MX6QDL_PAD_EIM_DA13__IPU1_DI1_D0_CS 0x148 0x45c 0x000 0x1 0x0
380#define MX6Q_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0 380#define MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x148 0x45c 0x000 0x5 0x0
381#define MX6Q_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0 381#define MX6QDL_PAD_EIM_DA13__SRC_BOOT_CFG13 0x148 0x45c 0x000 0x7 0x0
382#define MX6Q_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0 382#define MX6QDL_PAD_EIM_DA14__EIM_AD14 0x14c 0x460 0x000 0x0 0x0
383#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0 383#define MX6QDL_PAD_EIM_DA14__IPU1_DI1_D1_CS 0x14c 0x460 0x000 0x1 0x0
384#define MX6Q_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0 384#define MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x14c 0x460 0x000 0x5 0x0
385#define MX6Q_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0 385#define MX6QDL_PAD_EIM_DA14__SRC_BOOT_CFG14 0x14c 0x460 0x000 0x7 0x0
386#define MX6Q_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0 386#define MX6QDL_PAD_EIM_DA15__EIM_AD15 0x150 0x464 0x000 0x0 0x0
387#define MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0 387#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN01 0x150 0x464 0x000 0x1 0x0
388#define MX6Q_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0 388#define MX6QDL_PAD_EIM_DA15__IPU1_DI1_PIN04 0x150 0x464 0x000 0x2 0x0
389#define MX6Q_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0 389#define MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x150 0x464 0x000 0x5 0x0
390#define MX6Q_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0 390#define MX6QDL_PAD_EIM_DA15__SRC_BOOT_CFG15 0x150 0x464 0x000 0x7 0x0
391#define MX6Q_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0 391#define MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0x154 0x468 0x000 0x0 0x0
392#define MX6Q_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0 392#define MX6QDL_PAD_EIM_WAIT__EIM_DTACK_B 0x154 0x468 0x000 0x1 0x0
393#define MX6Q_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0 393#define MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x154 0x468 0x000 0x5 0x0
394#define MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0 394#define MX6QDL_PAD_EIM_WAIT__SRC_BOOT_CFG25 0x154 0x468 0x000 0x7 0x0
395#define MX6Q_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0 395#define MX6QDL_PAD_EIM_BCLK__EIM_BCLK 0x158 0x46c 0x000 0x0 0x0
396#define MX6Q_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0 396#define MX6QDL_PAD_EIM_BCLK__IPU1_DI1_PIN16 0x158 0x46c 0x000 0x1 0x0
397#define MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0 397#define MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x158 0x46c 0x000 0x5 0x0
398#define MX6Q_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0 398#define MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x15c 0x470 0x000 0x0 0x0
399#define MX6Q_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0 399#define MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x15c 0x470 0x000 0x1 0x0
400#define MX6Q_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0 400#define MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x15c 0x470 0x000 0x5 0x0
401#define MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0 401#define MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x160 0x474 0x000 0x0 0x0
402#define MX6Q_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0 402#define MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x160 0x474 0x000 0x1 0x0
403#define MX6Q_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0 403#define MX6QDL_PAD_DI0_PIN15__AUD6_TXC 0x160 0x474 0x000 0x2 0x0
404#define MX6Q_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0 404#define MX6QDL_PAD_DI0_PIN15__GPIO4_IO17 0x160 0x474 0x000 0x5 0x0
405#define MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0 405#define MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x164 0x478 0x000 0x0 0x0
406#define MX6Q_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0 406#define MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x164 0x478 0x000 0x1 0x0
407#define MX6Q_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0 407#define MX6QDL_PAD_DI0_PIN2__AUD6_TXD 0x164 0x478 0x000 0x2 0x0
408#define MX6Q_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0 408#define MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x164 0x478 0x000 0x5 0x0
409#define MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0 409#define MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x168 0x47c 0x000 0x0 0x0
410#define MX6Q_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0 410#define MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x168 0x47c 0x000 0x1 0x0
411#define MX6Q_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0 411#define MX6QDL_PAD_DI0_PIN3__AUD6_TXFS 0x168 0x47c 0x000 0x2 0x0
412#define MX6Q_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0 412#define MX6QDL_PAD_DI0_PIN3__GPIO4_IO19 0x168 0x47c 0x000 0x5 0x0
413#define MX6Q_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0 413#define MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x16c 0x480 0x000 0x0 0x0
414#define MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0 414#define MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x16c 0x480 0x000 0x1 0x0
415#define MX6Q_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0 415#define MX6QDL_PAD_DI0_PIN4__AUD6_RXD 0x16c 0x480 0x000 0x2 0x0
416#define MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0 416#define MX6QDL_PAD_DI0_PIN4__SD1_WP 0x16c 0x480 0x94c 0x3 0x0
417#define MX6Q_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0 417#define MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x16c 0x480 0x000 0x5 0x0
418#define MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0 418#define MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x170 0x484 0x000 0x0 0x0
419#define MX6Q_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0 419#define MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x170 0x484 0x000 0x1 0x0
420#define MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0 420#define MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x170 0x484 0x000 0x2 0x0
421#define MX6Q_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0 421#define MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x170 0x484 0x000 0x5 0x0
422#define MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0 422#define MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x174 0x488 0x000 0x0 0x0
423#define MX6Q_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0 423#define MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x174 0x488 0x000 0x1 0x0
424#define MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0 424#define MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x174 0x488 0x000 0x2 0x0
425#define MX6Q_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0 425#define MX6QDL_PAD_DISP0_DAT1__GPIO4_IO22 0x174 0x488 0x000 0x5 0x0
426#define MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0 426#define MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x178 0x48c 0x000 0x0 0x0
427#define MX6Q_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0 427#define MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x178 0x48c 0x000 0x1 0x0
428#define MX6Q_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0 428#define MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x178 0x48c 0x000 0x2 0x0
429#define MX6Q_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0 429#define MX6QDL_PAD_DISP0_DAT2__GPIO4_IO23 0x178 0x48c 0x000 0x5 0x0
430#define MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0 430#define MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x17c 0x490 0x000 0x0 0x0
431#define MX6Q_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0 431#define MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x17c 0x490 0x000 0x1 0x0
432#define MX6Q_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0 432#define MX6QDL_PAD_DISP0_DAT3__ECSPI3_SS0 0x17c 0x490 0x000 0x2 0x0
433#define MX6Q_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0 433#define MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x17c 0x490 0x000 0x5 0x0
434#define MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0 434#define MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x180 0x494 0x000 0x0 0x0
435#define MX6Q_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0 435#define MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x180 0x494 0x000 0x1 0x0
436#define MX6Q_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0 436#define MX6QDL_PAD_DISP0_DAT4__ECSPI3_SS1 0x180 0x494 0x000 0x2 0x0
437#define MX6Q_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0 437#define MX6QDL_PAD_DISP0_DAT4__GPIO4_IO25 0x180 0x494 0x000 0x5 0x0
438#define MX6Q_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0 438#define MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x184 0x498 0x000 0x0 0x0
439#define MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0 439#define MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x184 0x498 0x000 0x1 0x0
440#define MX6Q_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0 440#define MX6QDL_PAD_DISP0_DAT5__ECSPI3_SS2 0x184 0x498 0x000 0x2 0x0
441#define MX6Q_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0 441#define MX6QDL_PAD_DISP0_DAT5__AUD6_RXFS 0x184 0x498 0x000 0x3 0x0
442#define MX6Q_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0 442#define MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x184 0x498 0x000 0x5 0x0
443#define MX6Q_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0 443#define MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x188 0x49c 0x000 0x0 0x0
444#define MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0 444#define MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x188 0x49c 0x000 0x1 0x0
445#define MX6Q_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0 445#define MX6QDL_PAD_DISP0_DAT6__ECSPI3_SS3 0x188 0x49c 0x000 0x2 0x0
446#define MX6Q_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0 446#define MX6QDL_PAD_DISP0_DAT6__AUD6_RXC 0x188 0x49c 0x000 0x3 0x0
447#define MX6Q_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0 447#define MX6QDL_PAD_DISP0_DAT6__GPIO4_IO27 0x188 0x49c 0x000 0x5 0x0
448#define MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0 448#define MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x18c 0x4a0 0x000 0x0 0x0
449#define MX6Q_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0 449#define MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x18c 0x4a0 0x000 0x1 0x0
450#define MX6Q_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0 450#define MX6QDL_PAD_DISP0_DAT7__ECSPI3_RDY 0x18c 0x4a0 0x000 0x2 0x0
451#define MX6Q_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0 451#define MX6QDL_PAD_DISP0_DAT7__GPIO4_IO28 0x18c 0x4a0 0x000 0x5 0x0
452#define MX6Q_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0 452#define MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x190 0x4a4 0x000 0x0 0x0
453#define MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0 453#define MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x190 0x4a4 0x000 0x1 0x0
454#define MX6Q_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0 454#define MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x190 0x4a4 0x000 0x2 0x0
455#define MX6Q_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0 455#define MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x190 0x4a4 0x000 0x3 0x0
456#define MX6Q_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0 456#define MX6QDL_PAD_DISP0_DAT8__GPIO4_IO29 0x190 0x4a4 0x000 0x5 0x0
457#define MX6Q_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0 457#define MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x194 0x4a8 0x000 0x0 0x0
458#define MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0 458#define MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x194 0x4a8 0x000 0x1 0x0
459#define MX6Q_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0 459#define MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x194 0x4a8 0x000 0x2 0x0
460#define MX6Q_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0 460#define MX6QDL_PAD_DISP0_DAT9__WDOG2_B 0x194 0x4a8 0x000 0x3 0x0
461#define MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0 461#define MX6QDL_PAD_DISP0_DAT9__GPIO4_IO30 0x194 0x4a8 0x000 0x5 0x0
462#define MX6Q_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0 462#define MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x198 0x4ac 0x000 0x0 0x0
463#define MX6Q_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0 463#define MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x198 0x4ac 0x000 0x1 0x0
464#define MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0 464#define MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x198 0x4ac 0x000 0x5 0x0
465#define MX6Q_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0 465#define MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x19c 0x4b0 0x000 0x0 0x0
466#define MX6Q_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0 466#define MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x19c 0x4b0 0x000 0x1 0x0
467#define MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0 467#define MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x19c 0x4b0 0x000 0x5 0x0
468#define MX6Q_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0 468#define MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x1a0 0x4b4 0x000 0x0 0x0
469#define MX6Q_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1 469#define MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x1a0 0x4b4 0x000 0x1 0x0
470#define MX6Q_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0 470#define MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1a0 0x4b4 0x000 0x5 0x0
471#define MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0 471#define MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x1a4 0x4b8 0x000 0x0 0x0
472#define MX6Q_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0 472#define MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x1a4 0x4b8 0x000 0x1 0x0
473#define MX6Q_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1 473#define MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x1a4 0x4b8 0x7d8 0x3 0x1
474#define MX6Q_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0 474#define MX6QDL_PAD_DISP0_DAT13__GPIO5_IO07 0x1a4 0x4b8 0x000 0x5 0x0
475#define MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0 475#define MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x1a8 0x4bc 0x000 0x0 0x0
476#define MX6Q_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0 476#define MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x1a8 0x4bc 0x000 0x1 0x0
477#define MX6Q_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1 477#define MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x1a8 0x4bc 0x7d4 0x3 0x1
478#define MX6Q_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1 478#define MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1a8 0x4bc 0x000 0x5 0x0
479#define MX6Q_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0 479#define MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x1ac 0x4c0 0x000 0x0 0x0
480#define MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0 480#define MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x1ac 0x4c0 0x000 0x1 0x0
481#define MX6Q_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0 481#define MX6QDL_PAD_DISP0_DAT15__ECSPI1_SS1 0x1ac 0x4c0 0x804 0x2 0x1
482#define MX6Q_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1 482#define MX6QDL_PAD_DISP0_DAT15__ECSPI2_SS1 0x1ac 0x4c0 0x820 0x3 0x1
483#define MX6Q_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0 483#define MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1ac 0x4c0 0x000 0x5 0x0
484#define MX6Q_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0 484#define MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x1b0 0x4c4 0x000 0x0 0x0
485#define MX6Q_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0 485#define MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x1b0 0x4c4 0x000 0x1 0x0
486#define MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0 486#define MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x1b0 0x4c4 0x818 0x2 0x1
487#define MX6Q_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0 487#define MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x1b0 0x4c4 0x7dc 0x3 0x0
488#define MX6Q_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1 488#define MX6QDL_PAD_DISP0_DAT16__SDMA_EXT_EVENT0 0x1b0 0x4c4 0x90c 0x4 0x0
489#define MX6Q_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0 489#define MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0 0x4c4 0x000 0x5 0x0
490#define MX6Q_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0 490#define MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x1b4 0x4c8 0x000 0x0 0x0
491#define MX6Q_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0 491#define MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x1b4 0x4c8 0x000 0x1 0x0
492#define MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0 492#define MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x1b4 0x4c8 0x814 0x2 0x1
493#define MX6Q_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0 493#define MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x1b4 0x4c8 0x7d0 0x3 0x0
494#define MX6Q_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1 494#define MX6QDL_PAD_DISP0_DAT17__SDMA_EXT_EVENT1 0x1b4 0x4c8 0x910 0x4 0x0
495#define MX6Q_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0 495#define MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b4 0x4c8 0x000 0x5 0x0
496#define MX6Q_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0 496#define MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x1b8 0x4cc 0x000 0x0 0x0
497#define MX6Q_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0 497#define MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x1b8 0x4cc 0x000 0x1 0x0
498#define MX6Q_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0 498#define MX6QDL_PAD_DISP0_DAT18__ECSPI2_SS0 0x1b8 0x4cc 0x81c 0x2 0x1
499#define MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0 499#define MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x1b8 0x4cc 0x7e0 0x3 0x0
500#define MX6Q_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0 500#define MX6QDL_PAD_DISP0_DAT18__AUD4_RXFS 0x1b8 0x4cc 0x7c0 0x4 0x0
501#define MX6Q_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1 501#define MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x1b8 0x4cc 0x000 0x5 0x0
502#define MX6Q_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0 502#define MX6QDL_PAD_DISP0_DAT18__EIM_CS2_B 0x1b8 0x4cc 0x000 0x7 0x0
503#define MX6Q_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0 503#define MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x1bc 0x4d0 0x000 0x0 0x0
504#define MX6Q_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0 504#define MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x1bc 0x4d0 0x000 0x1 0x0
505#define MX6Q_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0 505#define MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x1bc 0x4d0 0x810 0x2 0x1
506#define MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0 506#define MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x1bc 0x4d0 0x7cc 0x3 0x0
507#define MX6Q_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0 507#define MX6QDL_PAD_DISP0_DAT19__AUD4_RXC 0x1bc 0x4d0 0x7bc 0x4 0x0
508#define MX6Q_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1 508#define MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 0x1bc 0x4d0 0x000 0x5 0x0
509#define MX6Q_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0 509#define MX6QDL_PAD_DISP0_DAT19__EIM_CS3_B 0x1bc 0x4d0 0x000 0x7 0x0
510#define MX6Q_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0 510#define MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x1c0 0x4d4 0x000 0x0 0x0
511#define MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0 511#define MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x1c0 0x4d4 0x000 0x1 0x0
512#define MX6Q_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0 512#define MX6QDL_PAD_DISP0_DAT20__ECSPI1_SCLK 0x1c0 0x4d4 0x7f4 0x2 0x1
513#define MX6Q_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1 513#define MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x1c0 0x4d4 0x7c4 0x3 0x0
514#define MX6Q_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1 514#define MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 0x1c0 0x4d4 0x000 0x5 0x0
515#define MX6Q_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0 515#define MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x1c4 0x4d8 0x000 0x0 0x0
516#define MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0 516#define MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x1c4 0x4d8 0x000 0x1 0x0
517#define MX6Q_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0 517#define MX6QDL_PAD_DISP0_DAT21__ECSPI1_MOSI 0x1c4 0x4d8 0x7fc 0x2 0x1
518#define MX6Q_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1 518#define MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x1c4 0x4d8 0x7b8 0x3 0x1
519#define MX6Q_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1 519#define MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x1c4 0x4d8 0x000 0x5 0x0
520#define MX6Q_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0 520#define MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x1c8 0x4dc 0x000 0x0 0x0
521#define MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0 521#define MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x1c8 0x4dc 0x000 0x1 0x0
522#define MX6Q_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0 522#define MX6QDL_PAD_DISP0_DAT22__ECSPI1_MISO 0x1c8 0x4dc 0x7f8 0x2 0x1
523#define MX6Q_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1 523#define MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x1c8 0x4dc 0x7c8 0x3 0x1
524#define MX6Q_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1 524#define MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 0x1c8 0x4dc 0x000 0x5 0x0
525#define MX6Q_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0 525#define MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x1cc 0x4e0 0x000 0x0 0x0
526#define MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0 526#define MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x1cc 0x4e0 0x000 0x1 0x0
527#define MX6Q_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0 527#define MX6QDL_PAD_DISP0_DAT23__ECSPI1_SS0 0x1cc 0x4e0 0x800 0x2 0x1
528#define MX6Q_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0 528#define MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x1cc 0x4e0 0x7b4 0x3 0x1
529#define MX6Q_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0 529#define MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1cc 0x4e0 0x000 0x5 0x0
530#define MX6Q_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0 530#define MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1d0 0x4e4 0x840 0x1 0x0
531#define MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0 531#define MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1d0 0x4e4 0x86c 0x2 0x0
532#define MX6Q_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0 532#define MX6QDL_PAD_ENET_MDIO__ENET_1588_EVENT1_OUT 0x1d0 0x4e4 0x000 0x4 0x0
533#define MX6Q_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0 533#define MX6QDL_PAD_ENET_MDIO__GPIO1_IO22 0x1d0 0x4e4 0x000 0x5 0x0
534#define MX6Q_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0 534#define MX6QDL_PAD_ENET_MDIO__SPDIF_LOCK 0x1d0 0x4e4 0x000 0x6 0x0
535#define MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0 535#define MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1d4 0x4e8 0x000 0x1 0x0
536#define MX6Q_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0 536#define MX6QDL_PAD_ENET_REF_CLK__ESAI_RX_FS 0x1d4 0x4e8 0x85c 0x2 0x0
537#define MX6Q_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0 537#define MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1d4 0x4e8 0x000 0x5 0x0
538#define MX6Q_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1 538#define MX6QDL_PAD_ENET_REF_CLK__SPDIF_SR_CLK 0x1d4 0x4e8 0x000 0x6 0x0
539#define MX6Q_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0 539#define MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x1d8 0x4ec 0x000 0x0 0x0
540#define MX6Q_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0 540#define MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1d8 0x4ec 0x000 0x1 0x0
541#define MX6Q_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1 541#define MX6QDL_PAD_ENET_RX_ER__ESAI_RX_HF_CLK 0x1d8 0x4ec 0x864 0x2 0x0
542#define MX6Q_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0 542#define MX6QDL_PAD_ENET_RX_ER__SPDIF_IN 0x1d8 0x4ec 0x914 0x3 0x1
543#define MX6Q_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1 543#define MX6QDL_PAD_ENET_RX_ER__ENET_1588_EVENT2_OUT 0x1d8 0x4ec 0x000 0x4 0x0
544#define MX6Q_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0 544#define MX6QDL_PAD_ENET_RX_ER__GPIO1_IO24 0x1d8 0x4ec 0x000 0x5 0x0
545#define MX6Q_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0 545#define MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1dc 0x4f0 0x858 0x1 0x1
546#define MX6Q_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1 546#define MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1dc 0x4f0 0x870 0x2 0x0
547#define MX6Q_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0 547#define MX6QDL_PAD_ENET_CRS_DV__SPDIF_EXT_CLK 0x1dc 0x4f0 0x918 0x3 0x1
548#define MX6Q_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0 548#define MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1dc 0x4f0 0x000 0x5 0x0
549#define MX6Q_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0 549#define MX6QDL_PAD_ENET_RXD1__MLB_SIG 0x1e0 0x4f4 0x908 0x0 0x0
550#define MX6Q_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1 550#define MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1e0 0x4f4 0x84c 0x1 0x1
551#define MX6Q_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0 551#define MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1e0 0x4f4 0x860 0x2 0x0
552#define MX6Q_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0 552#define MX6QDL_PAD_ENET_RXD1__ENET_1588_EVENT3_OUT 0x1e0 0x4f4 0x000 0x4 0x0
553#define MX6Q_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0 553#define MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1e0 0x4f4 0x000 0x5 0x0
554#define MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0 554#define MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1e4 0x4f8 0x848 0x1 0x1
555#define MX6Q_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0 555#define MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1e4 0x4f8 0x868 0x2 0x0
556#define MX6Q_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0 556#define MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1e4 0x4f8 0x000 0x3 0x0
557#define MX6Q_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0 557#define MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1e4 0x4f8 0x000 0x5 0x0
558#define MX6Q_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0 558#define MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1e8 0x4fc 0x000 0x1 0x0
559#define MX6Q_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0 559#define MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1e8 0x4fc 0x880 0x2 0x0
560#define MX6Q_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0 560#define MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1e8 0x4fc 0x000 0x5 0x0
561#define MX6Q_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0 561#define MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x1ec 0x500 0x900 0x0 0x0
562#define MX6Q_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0 562#define MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1ec 0x500 0x000 0x1 0x0
563#define MX6Q_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0 563#define MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1ec 0x500 0x87c 0x2 0x0
564#define MX6Q_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0 564#define MX6QDL_PAD_ENET_TXD1__ENET_1588_EVENT0_IN 0x1ec 0x500 0x000 0x4 0x0
565#define MX6Q_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0 565#define MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1ec 0x500 0x000 0x5 0x0
566#define MX6Q_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0 566#define MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1f0 0x504 0x000 0x1 0x0
567#define MX6Q_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0 567#define MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1f0 0x504 0x884 0x2 0x0
568#define MX6Q_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0 568#define MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1f0 0x504 0x000 0x5 0x0
569#define MX6Q_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0 569#define MX6QDL_PAD_ENET_MDC__MLB_DATA 0x1f4 0x508 0x904 0x0 0x0
570#define MX6Q_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2 570#define MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1f4 0x508 0x000 0x1 0x0
571#define MX6Q_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1 571#define MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1f4 0x508 0x888 0x2 0x0
572#define MX6Q_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1 572#define MX6QDL_PAD_ENET_MDC__ENET_1588_EVENT1_IN 0x1f4 0x508 0x000 0x4 0x0
573#define MX6Q_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0 573#define MX6QDL_PAD_ENET_MDC__GPIO1_IO31 0x1f4 0x508 0x000 0x5 0x0
574#define MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0 574#define MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x1f8 0x5c8 0x7f4 0x0 0x2
575#define MX6Q_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0 575#define MX6QDL_PAD_KEY_COL0__ENET_RX_DATA3 0x1f8 0x5c8 0x854 0x1 0x1
576#define MX6Q_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0 576#define MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x1f8 0x5c8 0x7dc 0x2 0x1
577#define MX6Q_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0 577#define MX6QDL_PAD_KEY_COL0__KEY_COL0 0x1f8 0x5c8 0x000 0x3 0x0
578#define MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2 578#define MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1f8 0x5c8 0x000 0x4 0x0
579#define MX6Q_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0 579#define MX6QDL_PAD_KEY_COL0__UART4_RX_DATA 0x1f8 0x5c8 0x938 0x4 0x0
580#define MX6Q_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1 580#define MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1f8 0x5c8 0x000 0x5 0x0
581#define MX6Q_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0 581#define MX6QDL_PAD_KEY_COL0__DCIC1_OUT 0x1f8 0x5c8 0x000 0x6 0x0
582#define MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1 582#define MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x1fc 0x5cc 0x7fc 0x0 0x2
583#define MX6Q_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0 583#define MX6QDL_PAD_KEY_ROW0__ENET_TX_DATA3 0x1fc 0x5cc 0x000 0x1 0x0
584#define MX6Q_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0 584#define MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x1fc 0x5cc 0x7d0 0x2 0x1
585#define MX6Q_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0 585#define MX6QDL_PAD_KEY_ROW0__KEY_ROW0 0x1fc 0x5cc 0x000 0x3 0x0
586#define MX6Q_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2 586#define MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1fc 0x5cc 0x938 0x4 0x1
587#define MX6Q_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1 587#define MX6QDL_PAD_KEY_ROW0__UART4_TX_DATA 0x1fc 0x5cc 0x000 0x4 0x0
588#define MX6Q_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1 588#define MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1fc 0x5cc 0x000 0x5 0x0
589#define MX6Q_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0 589#define MX6QDL_PAD_KEY_ROW0__DCIC2_OUT 0x1fc 0x5cc 0x000 0x6 0x0
590#define MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0 590#define MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x200 0x5d0 0x7f8 0x0 0x2
591#define MX6Q_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0 591#define MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x200 0x5d0 0x840 0x1 0x1
592#define MX6Q_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0 592#define MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x200 0x5d0 0x7e0 0x2 0x1
593#define MX6Q_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0 593#define MX6QDL_PAD_KEY_COL1__KEY_COL1 0x200 0x5d0 0x000 0x3 0x0
594#define MX6Q_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2 594#define MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x200 0x5d0 0x000 0x4 0x0
595#define MX6Q_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0 595#define MX6QDL_PAD_KEY_COL1__UART5_RX_DATA 0x200 0x5d0 0x940 0x4 0x0
596#define MX6Q_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1 596#define MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x200 0x5d0 0x000 0x5 0x0
597#define MX6Q_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0 597#define MX6QDL_PAD_KEY_COL1__SD1_VSELECT 0x200 0x5d0 0x000 0x6 0x0
598#define MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1 598#define MX6QDL_PAD_KEY_ROW1__ECSPI1_SS0 0x204 0x5d4 0x800 0x0 0x2
599#define MX6Q_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0 599#define MX6QDL_PAD_KEY_ROW1__ENET_COL 0x204 0x5d4 0x000 0x1 0x0
600#define MX6Q_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0 600#define MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x204 0x5d4 0x7cc 0x2 0x1
601#define MX6Q_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0 601#define MX6QDL_PAD_KEY_ROW1__KEY_ROW1 0x204 0x5d4 0x000 0x3 0x0
602#define MX6Q_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2 602#define MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x204 0x5d4 0x940 0x4 0x1
603#define MX6Q_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1 603#define MX6QDL_PAD_KEY_ROW1__UART5_TX_DATA 0x204 0x5d4 0x000 0x4 0x0
604#define MX6Q_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0 604#define MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x204 0x5d4 0x000 0x5 0x0
605#define MX6Q_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0 605#define MX6QDL_PAD_KEY_ROW1__SD2_VSELECT 0x204 0x5d4 0x000 0x6 0x0
606#define MX6Q_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0 606#define MX6QDL_PAD_KEY_COL2__ECSPI1_SS1 0x208 0x5d8 0x804 0x0 0x2
607#define MX6Q_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0 607#define MX6QDL_PAD_KEY_COL2__ENET_RX_DATA2 0x208 0x5d8 0x850 0x1 0x1
608#define MX6Q_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0 608#define MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x208 0x5d8 0x000 0x2 0x0
609#define MX6Q_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1 609#define MX6QDL_PAD_KEY_COL2__KEY_COL2 0x208 0x5d8 0x000 0x3 0x0
610#define MX6Q_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0 610#define MX6QDL_PAD_KEY_COL2__ENET_MDC 0x208 0x5d8 0x000 0x4 0x0
611#define MX6Q_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0 611#define MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x208 0x5d8 0x000 0x5 0x0
612#define MX6Q_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0 612#define MX6QDL_PAD_KEY_COL2__USB_H1_PWR_CTL_WAKE 0x208 0x5d8 0x000 0x6 0x0
613#define MX6Q_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0 613#define MX6QDL_PAD_KEY_ROW2__ECSPI1_SS2 0x20c 0x5dc 0x808 0x0 0x1
614#define MX6Q_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0 614#define MX6QDL_PAD_KEY_ROW2__ENET_TX_DATA2 0x20c 0x5dc 0x000 0x1 0x0
615#define MX6Q_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1 615#define MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x20c 0x5dc 0x7e4 0x2 0x0
616#define MX6Q_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1 616#define MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x20c 0x5dc 0x000 0x3 0x0
617#define MX6Q_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0 617#define MX6QDL_PAD_KEY_ROW2__SD2_VSELECT 0x20c 0x5dc 0x000 0x4 0x0
618#define MX6Q_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1 618#define MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x20c 0x5dc 0x000 0x5 0x0
619#define MX6Q_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0 619#define MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x20c 0x5dc 0x88c 0x6 0x1
620#define MX6Q_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1 620#define MX6QDL_PAD_KEY_COL3__ECSPI1_SS3 0x210 0x5e0 0x80c 0x0 0x1
621#define MX6Q_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0 621#define MX6QDL_PAD_KEY_COL3__ENET_CRS 0x210 0x5e0 0x000 0x1 0x0
622#define MX6Q_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2 622#define MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x210 0x5e0 0x890 0x2 0x1
623#define MX6Q_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0 623#define MX6QDL_PAD_KEY_COL3__KEY_COL3 0x210 0x5e0 0x000 0x3 0x0
624#define MX6Q_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1 624#define MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x210 0x5e0 0x8a0 0x4 0x1
625#define MX6Q_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0 625#define MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x210 0x5e0 0x000 0x5 0x0
626#define MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1 626#define MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x210 0x5e0 0x914 0x6 0x2
627#define MX6Q_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0 627#define MX6QDL_PAD_KEY_ROW3__ASRC_EXT_CLK 0x214 0x5e4 0x7b0 0x1 0x0
628#define MX6Q_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0 628#define MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x214 0x5e4 0x894 0x2 0x1
629#define MX6Q_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0 629#define MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x214 0x5e4 0x000 0x3 0x0
630#define MX6Q_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0 630#define MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x214 0x5e4 0x8a4 0x4 0x1
631#define MX6Q_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1 631#define MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x214 0x5e4 0x000 0x5 0x0
632#define MX6Q_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0 632#define MX6QDL_PAD_KEY_ROW3__SD1_VSELECT 0x214 0x5e4 0x000 0x6 0x0
633#define MX6Q_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0 633#define MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x218 0x5e8 0x000 0x0 0x0
634#define MX6Q_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0 634#define MX6QDL_PAD_KEY_COL4__IPU1_SISG4 0x218 0x5e8 0x000 0x1 0x0
635#define MX6Q_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0 635#define MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x218 0x5e8 0x944 0x2 0x1
636#define MX6Q_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0 636#define MX6QDL_PAD_KEY_COL4__KEY_COL4 0x218 0x5e8 0x000 0x3 0x0
637#define MX6Q_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0 637#define MX6QDL_PAD_KEY_COL4__UART5_RTS_B 0x218 0x5e8 0x93c 0x4 0x0
638#define MX6Q_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0 638#define MX6QDL_PAD_KEY_COL4__UART5_CTS_B 0x218 0x5e8 0x000 0x4 0x0
639#define MX6Q_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0 639#define MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x218 0x5e8 0x000 0x5 0x0
640#define MX6Q_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0 640#define MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x21c 0x5ec 0x7e8 0x0 0x0
641#define MX6Q_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1 641#define MX6QDL_PAD_KEY_ROW4__IPU1_SISG5 0x21c 0x5ec 0x000 0x1 0x0
642#define MX6Q_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0 642#define MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x21c 0x5ec 0x000 0x2 0x0
643#define MX6Q_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0 643#define MX6QDL_PAD_KEY_ROW4__KEY_ROW4 0x21c 0x5ec 0x000 0x3 0x0
644#define MX6Q_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0 644#define MX6QDL_PAD_KEY_ROW4__UART5_CTS_B 0x21c 0x5ec 0x000 0x4 0x0
645#define MX6Q_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1 645#define MX6QDL_PAD_KEY_ROW4__UART5_RTS_B 0x21c 0x5ec 0x93c 0x4 0x1
646#define MX6Q_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0 646#define MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x21c 0x5ec 0x000 0x5 0x0
647#define MX6Q_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0 647#define MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x220 0x5f0 0x000 0x0 0x0
648#define MX6Q_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0 648#define MX6QDL_PAD_GPIO_0__KEY_COL5 0x220 0x5f0 0x8e8 0x2 0x0
649#define MX6Q_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0 649#define MX6QDL_PAD_GPIO_0__ASRC_EXT_CLK 0x220 0x5f0 0x7b0 0x3 0x1
650#define MX6Q_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1 650#define MX6QDL_PAD_GPIO_0__EPIT1_OUT 0x220 0x5f0 0x000 0x4 0x0
651#define MX6Q_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0 651#define MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x220 0x5f0 0x000 0x5 0x0
652#define MX6Q_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0 652#define MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x220 0x5f0 0x000 0x6 0x0
653#define MX6Q_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0 653#define MX6QDL_PAD_GPIO_0__SNVS_VIO_5 0x220 0x5f0 0x000 0x7 0x0
654#define MX6Q_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0 654#define MX6QDL_PAD_GPIO_1__ESAI_RX_CLK 0x224 0x5f4 0x86c 0x0 0x1
655#define MX6Q_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0 655#define MX6QDL_PAD_GPIO_1__WDOG2_B 0x224 0x5f4 0x000 0x1 0x0
656#define MX6Q_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0 656#define MX6QDL_PAD_GPIO_1__KEY_ROW5 0x224 0x5f4 0x8f4 0x2 0x0
657#define MX6Q_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1 657#define MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x224 0x5f4 0x000 0x3 0x0
658#define MX6Q_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0 658#define MX6QDL_PAD_GPIO_1__PWM2_OUT 0x224 0x5f4 0x000 0x4 0x0
659#define MX6Q_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0 659#define MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x224 0x5f4 0x000 0x5 0x0
660#define MX6Q_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0 660#define MX6QDL_PAD_GPIO_1__SD1_CD_B 0x224 0x5f4 0x000 0x6 0x0
661#define MX6Q_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0 661#define MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x228 0x5f8 0x85c 0x0 0x1
662#define MX6Q_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0 662#define MX6QDL_PAD_GPIO_9__WDOG1_B 0x228 0x5f8 0x000 0x1 0x0
663#define MX6Q_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1 663#define MX6QDL_PAD_GPIO_9__KEY_COL6 0x228 0x5f8 0x8ec 0x2 0x0
664#define MX6Q_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1 664#define MX6QDL_PAD_GPIO_9__CCM_REF_EN_B 0x228 0x5f8 0x000 0x3 0x0
665#define MX6Q_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1 665#define MX6QDL_PAD_GPIO_9__PWM1_OUT 0x228 0x5f8 0x000 0x4 0x0
666#define MX6Q_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0 666#define MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x228 0x5f8 0x000 0x5 0x0
667#define MX6Q_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0 667#define MX6QDL_PAD_GPIO_9__SD1_WP 0x228 0x5f8 0x94c 0x6 0x1
668#define MX6Q_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0 668#define MX6QDL_PAD_GPIO_3__ESAI_RX_HF_CLK 0x22c 0x5fc 0x864 0x0 0x1
669#define MX6Q_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1 669#define MX6QDL_PAD_GPIO_3__I2C3_SCL 0x22c 0x5fc 0x8a8 0x2 0x1
670#define MX6Q_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1 670#define MX6QDL_PAD_GPIO_3__XTALOSC_REF_CLK_24M 0x22c 0x5fc 0x000 0x3 0x0
671#define MX6Q_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1 671#define MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x22c 0x5fc 0x000 0x4 0x0
672#define MX6Q_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1 672#define MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x22c 0x5fc 0x000 0x5 0x0
673#define MX6Q_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0 673#define MX6QDL_PAD_GPIO_3__USB_H1_OC 0x22c 0x5fc 0x948 0x6 0x1
674#define MX6Q_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0 674#define MX6QDL_PAD_GPIO_3__MLB_CLK 0x22c 0x5fc 0x900 0x7 0x1
675#define MX6Q_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1 675#define MX6QDL_PAD_GPIO_6__ESAI_TX_CLK 0x230 0x600 0x870 0x0 0x1
676#define MX6Q_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1 676#define MX6QDL_PAD_GPIO_6__I2C3_SDA 0x230 0x600 0x8ac 0x2 0x1
677#define MX6Q_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1 677#define MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x230 0x600 0x000 0x5 0x0
678#define MX6Q_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0 678#define MX6QDL_PAD_GPIO_6__SD2_LCTL 0x230 0x600 0x000 0x6 0x0
679#define MX6Q_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0 679#define MX6QDL_PAD_GPIO_6__MLB_SIG 0x230 0x600 0x908 0x7 0x1
680#define MX6Q_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1 680#define MX6QDL_PAD_GPIO_2__ESAI_TX_FS 0x234 0x604 0x860 0x0 0x1
681#define MX6Q_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1 681#define MX6QDL_PAD_GPIO_2__KEY_ROW6 0x234 0x604 0x8f8 0x2 0x1
682#define MX6Q_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1 682#define MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x234 0x604 0x000 0x5 0x0
683#define MX6Q_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0 683#define MX6QDL_PAD_GPIO_2__SD2_WP 0x234 0x604 0x000 0x6 0x0
684#define MX6Q_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0 684#define MX6QDL_PAD_GPIO_2__MLB_DATA 0x234 0x604 0x904 0x7 0x1
685#define MX6Q_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1 685#define MX6QDL_PAD_GPIO_4__ESAI_TX_HF_CLK 0x238 0x608 0x868 0x0 0x1
686#define MX6Q_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1 686#define MX6QDL_PAD_GPIO_4__KEY_COL7 0x238 0x608 0x8f0 0x2 0x1
687#define MX6Q_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0 687#define MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x238 0x608 0x000 0x5 0x0
688#define MX6Q_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0 688#define MX6QDL_PAD_GPIO_4__SD2_CD_B 0x238 0x608 0x000 0x6 0x0
689#define MX6Q_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2 689#define MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x23c 0x60c 0x87c 0x0 0x1
690#define MX6Q_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0 690#define MX6QDL_PAD_GPIO_5__KEY_ROW7 0x23c 0x60c 0x8fc 0x2 0x1
691#define MX6Q_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1 691#define MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x23c 0x60c 0x000 0x3 0x0
692#define MX6Q_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0 692#define MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x23c 0x60c 0x000 0x5 0x0
693#define MX6Q_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0 693#define MX6QDL_PAD_GPIO_5__I2C3_SCL 0x23c 0x60c 0x8a8 0x6 0x2
694#define MX6Q_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0 694#define MX6QDL_PAD_GPIO_5__ARM_EVENTI 0x23c 0x60c 0x000 0x7 0x0
695#define MX6Q_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0 695#define MX6QDL_PAD_GPIO_7__ESAI_TX4_RX1 0x240 0x610 0x884 0x0 0x1
696#define MX6Q_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2 696#define MX6QDL_PAD_GPIO_7__ECSPI5_RDY 0x240 0x610 0x000 0x1 0x0
697#define MX6Q_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0 697#define MX6QDL_PAD_GPIO_7__EPIT1_OUT 0x240 0x610 0x000 0x2 0x0
698#define MX6Q_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0 698#define MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x240 0x610 0x000 0x3 0x0
699#define MX6Q_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0 699#define MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x240 0x610 0x000 0x4 0x0
700#define MX6Q_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1 700#define MX6QDL_PAD_GPIO_7__UART2_RX_DATA 0x240 0x610 0x928 0x4 0x2
701#define MX6Q_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0 701#define MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x240 0x610 0x000 0x5 0x0
702#define MX6Q_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0 702#define MX6QDL_PAD_GPIO_7__SPDIF_LOCK 0x240 0x610 0x000 0x6 0x0
703#define MX6Q_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1 703#define MX6QDL_PAD_GPIO_7__USB_OTG_HOST_MODE 0x240 0x610 0x000 0x7 0x0
704#define MX6Q_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3 704#define MX6QDL_PAD_GPIO_8__ESAI_TX5_RX0 0x244 0x614 0x888 0x0 0x1
705#define MX6Q_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0 705#define MX6QDL_PAD_GPIO_8__XTALOSC_REF_CLK_32K 0x244 0x614 0x000 0x1 0x0
706#define MX6Q_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0 706#define MX6QDL_PAD_GPIO_8__EPIT2_OUT 0x244 0x614 0x000 0x2 0x0
707#define MX6Q_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0 707#define MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x244 0x614 0x7e4 0x3 0x1
708#define MX6Q_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0 708#define MX6QDL_PAD_GPIO_8__UART2_RX_DATA 0x244 0x614 0x928 0x4 0x3
709#define MX6Q_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1 709#define MX6QDL_PAD_GPIO_8__UART2_TX_DATA 0x244 0x614 0x000 0x4 0x0
710#define MX6Q_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0 710#define MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x244 0x614 0x000 0x5 0x0
711#define MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1 711#define MX6QDL_PAD_GPIO_8__SPDIF_SR_CLK 0x244 0x614 0x000 0x6 0x0
712#define MX6Q_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0 712#define MX6QDL_PAD_GPIO_8__USB_OTG_PWR_CTL_WAKE 0x244 0x614 0x000 0x7 0x0
713#define MX6Q_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3 713#define MX6QDL_PAD_GPIO_16__ESAI_TX3_RX2 0x248 0x618 0x880 0x0 0x1
714#define MX6Q_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0 714#define MX6QDL_PAD_GPIO_16__ENET_1588_EVENT2_IN 0x248 0x618 0x000 0x1 0x0
715#define MX6Q_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2 715#define MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x248 0x618 0x83c 0x2 0x1
716#define MX6Q_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0 716#define MX6QDL_PAD_GPIO_16__SD1_LCTL 0x248 0x618 0x000 0x3 0x0
717#define MX6Q_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0 717#define MX6QDL_PAD_GPIO_16__SPDIF_IN 0x248 0x618 0x914 0x4 0x3
718#define MX6Q_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0 718#define MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x248 0x618 0x000 0x5 0x0
719#define MX6Q_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1 719#define MX6QDL_PAD_GPIO_16__I2C3_SDA 0x248 0x618 0x8ac 0x6 0x2
720#define MX6Q_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1 720#define MX6QDL_PAD_GPIO_16__JTAG_DE_B 0x248 0x618 0x000 0x7 0x0
721#define MX6Q_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0 721#define MX6QDL_PAD_GPIO_17__ESAI_TX0 0x24c 0x61c 0x874 0x0 0x0
722#define MX6Q_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0 722#define MX6QDL_PAD_GPIO_17__ENET_1588_EVENT3_IN 0x24c 0x61c 0x000 0x1 0x0
723#define MX6Q_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0 723#define MX6QDL_PAD_GPIO_17__CCM_PMIC_READY 0x24c 0x61c 0x7f0 0x2 0x1
724#define MX6Q_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1 724#define MX6QDL_PAD_GPIO_17__SDMA_EXT_EVENT0 0x24c 0x61c 0x90c 0x3 0x1
725#define MX6Q_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0 725#define MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x24c 0x61c 0x000 0x4 0x0
726#define MX6Q_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1 726#define MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x24c 0x61c 0x000 0x5 0x0
727#define MX6Q_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2 727#define MX6QDL_PAD_GPIO_18__ESAI_TX1 0x250 0x620 0x878 0x0 0x0
728#define MX6Q_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0 728#define MX6QDL_PAD_GPIO_18__ENET_RX_CLK 0x250 0x620 0x844 0x1 0x1
729#define MX6Q_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0 729#define MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x250 0x620 0x000 0x2 0x0
730#define MX6Q_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1 730#define MX6QDL_PAD_GPIO_18__SDMA_EXT_EVENT1 0x250 0x620 0x910 0x3 0x1
731#define MX6Q_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0 731#define MX6QDL_PAD_GPIO_18__ASRC_EXT_CLK 0x250 0x620 0x7b0 0x4 0x2
732#define MX6Q_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0 732#define MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x250 0x620 0x000 0x5 0x0
733#define MX6Q_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0 733#define MX6QDL_PAD_GPIO_18__SNVS_VIO_5_CTL 0x250 0x620 0x000 0x6 0x0
734#define MX6Q_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0 734#define MX6QDL_PAD_GPIO_19__KEY_COL5 0x254 0x624 0x8e8 0x0 0x1
735#define MX6Q_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0 735#define MX6QDL_PAD_GPIO_19__ENET_1588_EVENT0_OUT 0x254 0x624 0x000 0x1 0x0
736#define MX6Q_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0 736#define MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x254 0x624 0x000 0x2 0x0
737#define MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0 737#define MX6QDL_PAD_GPIO_19__CCM_CLKO1 0x254 0x624 0x000 0x3 0x0
738#define MX6Q_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0 738#define MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x254 0x624 0x000 0x4 0x0
739#define MX6Q_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0 739#define MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x254 0x624 0x000 0x5 0x0
740#define MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0 740#define MX6QDL_PAD_GPIO_19__ENET_TX_ER 0x254 0x624 0x000 0x6 0x0
741#define MX6Q_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0 741#define MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x258 0x628 0x000 0x0 0x0
742#define MX6Q_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0 742#define MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0x258 0x628 0x000 0x5 0x0
743#define MX6Q_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0 743#define MX6QDL_PAD_CSI0_PIXCLK__ARM_EVENTO 0x258 0x628 0x000 0x7 0x0
744#define MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0 744#define MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x25c 0x62c 0x000 0x0 0x0
745#define MX6Q_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0 745#define MX6QDL_PAD_CSI0_MCLK__CCM_CLKO1 0x25c 0x62c 0x000 0x3 0x0
746#define MX6Q_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0 746#define MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0x25c 0x62c 0x000 0x5 0x0
747#define MX6Q_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0 747#define MX6QDL_PAD_CSI0_MCLK__ARM_TRACE_CTL 0x25c 0x62c 0x000 0x7 0x0
748#define MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0 748#define MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x260 0x630 0x000 0x0 0x0
749#define MX6Q_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0 749#define MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x260 0x630 0x000 0x1 0x0
750#define MX6Q_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0 750#define MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x260 0x630 0x000 0x5 0x0
751#define MX6Q_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0 751#define MX6QDL_PAD_CSI0_DATA_EN__ARM_TRACE_CLK 0x260 0x630 0x000 0x7 0x0
752#define MX6Q_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0 752#define MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x264 0x634 0x000 0x0 0x0
753#define MX6Q_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0 753#define MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x264 0x634 0x000 0x1 0x0
754#define MX6Q_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3 754#define MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x264 0x634 0x000 0x5 0x0
755#define MX6Q_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2 755#define MX6QDL_PAD_CSI0_VSYNC__ARM_TRACE00 0x264 0x634 0x000 0x7 0x0
756#define MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0 756#define MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x268 0x638 0x000 0x0 0x0
757#define MX6Q_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0 757#define MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x268 0x638 0x000 0x1 0x0
758#define MX6Q_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0 758#define MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x268 0x638 0x7f4 0x2 0x3
759#define MX6Q_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0 759#define MX6QDL_PAD_CSI0_DAT4__KEY_COL5 0x268 0x638 0x8e8 0x3 0x2
760#define MX6Q_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0 760#define MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x268 0x638 0x000 0x4 0x0
761#define MX6Q_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3 761#define MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x268 0x638 0x000 0x5 0x0
762#define MX6Q_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1 762#define MX6QDL_PAD_CSI0_DAT4__ARM_TRACE01 0x268 0x638 0x000 0x7 0x0
763#define MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0 763#define MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x26c 0x63c 0x000 0x0 0x0
764#define MX6Q_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0 764#define MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x26c 0x63c 0x000 0x1 0x0
765#define MX6Q_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0 765#define MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x26c 0x63c 0x7fc 0x2 0x3
766#define MX6Q_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0 766#define MX6QDL_PAD_CSI0_DAT5__KEY_ROW5 0x26c 0x63c 0x8f4 0x3 0x1
767#define MX6Q_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0 767#define MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x26c 0x63c 0x000 0x4 0x0
768#define MX6Q_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3 768#define MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x26c 0x63c 0x000 0x5 0x0
769#define MX6Q_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1 769#define MX6QDL_PAD_CSI0_DAT5__ARM_TRACE02 0x26c 0x63c 0x000 0x7 0x0
770#define MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0 770#define MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x270 0x640 0x000 0x0 0x0
771#define MX6Q_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0 771#define MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x270 0x640 0x000 0x1 0x0
772#define MX6Q_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0 772#define MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x270 0x640 0x7f8 0x2 0x3
773#define MX6Q_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0 773#define MX6QDL_PAD_CSI0_DAT6__KEY_COL6 0x270 0x640 0x8ec 0x3 0x1
774#define MX6Q_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0 774#define MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x270 0x640 0x000 0x4 0x0
775#define MX6Q_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3 775#define MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x270 0x640 0x000 0x5 0x0
776#define MX6Q_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2 776#define MX6QDL_PAD_CSI0_DAT6__ARM_TRACE03 0x270 0x640 0x000 0x7 0x0
777#define MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0 777#define MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x274 0x644 0x000 0x0 0x0
778#define MX6Q_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0 778#define MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x274 0x644 0x000 0x1 0x0
779#define MX6Q_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0 779#define MX6QDL_PAD_CSI0_DAT7__ECSPI1_SS0 0x274 0x644 0x800 0x2 0x3
780#define MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0 780#define MX6QDL_PAD_CSI0_DAT7__KEY_ROW6 0x274 0x644 0x8f8 0x3 0x2
781#define MX6Q_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0 781#define MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x274 0x644 0x000 0x4 0x0
782#define MX6Q_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2 782#define MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x274 0x644 0x000 0x5 0x0
783#define MX6Q_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2 783#define MX6QDL_PAD_CSI0_DAT7__ARM_TRACE04 0x274 0x644 0x000 0x7 0x0
784#define MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1 784#define MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x278 0x648 0x000 0x0 0x0
785#define MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0 785#define MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x278 0x648 0x000 0x1 0x0
786#define MX6Q_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0 786#define MX6QDL_PAD_CSI0_DAT8__ECSPI2_SCLK 0x278 0x648 0x810 0x2 0x2
787#define MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0 787#define MX6QDL_PAD_CSI0_DAT8__KEY_COL7 0x278 0x648 0x8f0 0x3 0x2
788#define MX6Q_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0 788#define MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x278 0x648 0x89c 0x4 0x1
789#define MX6Q_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2 789#define MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x278 0x648 0x000 0x5 0x0
790#define MX6Q_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2 790#define MX6QDL_PAD_CSI0_DAT8__ARM_TRACE05 0x278 0x648 0x000 0x7 0x0
791#define MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1 791#define MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x27c 0x64c 0x000 0x0 0x0
792#define MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0 792#define MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x27c 0x64c 0x000 0x1 0x0
793#define MX6Q_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0 793#define MX6QDL_PAD_CSI0_DAT9__ECSPI2_MOSI 0x27c 0x64c 0x818 0x2 0x2
794#define MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0 794#define MX6QDL_PAD_CSI0_DAT9__KEY_ROW7 0x27c 0x64c 0x8fc 0x3 0x2
795#define MX6Q_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0 795#define MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x27c 0x64c 0x898 0x4 0x1
796#define MX6Q_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2 796#define MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x27c 0x64c 0x000 0x5 0x0
797#define MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0 797#define MX6QDL_PAD_CSI0_DAT9__ARM_TRACE06 0x27c 0x64c 0x000 0x7 0x0
798#define MX6Q_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0 798#define MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x280 0x650 0x000 0x0 0x0
799#define MX6Q_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0 799#define MX6QDL_PAD_CSI0_DAT10__AUD3_RXC 0x280 0x650 0x000 0x1 0x0
800#define MX6Q_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0 800#define MX6QDL_PAD_CSI0_DAT10__ECSPI2_MISO 0x280 0x650 0x814 0x2 0x2
801#define MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0 801#define MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x280 0x650 0x000 0x3 0x0
802#define MX6Q_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0 802#define MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x280 0x650 0x920 0x3 0x0
803#define MX6Q_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2 803#define MX6QDL_PAD_CSI0_DAT10__GPIO5_IO28 0x280 0x650 0x000 0x5 0x0
804#define MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1 804#define MX6QDL_PAD_CSI0_DAT10__ARM_TRACE07 0x280 0x650 0x000 0x7 0x0
805#define MX6Q_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0 805#define MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x284 0x654 0x000 0x0 0x0
806#define MX6Q_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0 806#define MX6QDL_PAD_CSI0_DAT11__AUD3_RXFS 0x284 0x654 0x000 0x1 0x0
807#define MX6Q_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0 807#define MX6QDL_PAD_CSI0_DAT11__ECSPI2_SS0 0x284 0x654 0x81c 0x2 0x2
808#define MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0 808#define MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x284 0x654 0x920 0x3 0x1
809#define MX6Q_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0 809#define MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x284 0x654 0x000 0x3 0x0
810#define MX6Q_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0 810#define MX6QDL_PAD_CSI0_DAT11__GPIO5_IO29 0x284 0x654 0x000 0x5 0x0
811#define MX6Q_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2 811#define MX6QDL_PAD_CSI0_DAT11__ARM_TRACE08 0x284 0x654 0x000 0x7 0x0
812#define MX6Q_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0 812#define MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x288 0x658 0x000 0x0 0x0
813#define MX6Q_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0 813#define MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x288 0x658 0x000 0x1 0x0
814#define MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0 814#define MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x288 0x658 0x000 0x3 0x0
815#define MX6Q_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0 815#define MX6QDL_PAD_CSI0_DAT12__UART4_RX_DATA 0x288 0x658 0x938 0x3 0x2
816#define MX6Q_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3 816#define MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x288 0x658 0x000 0x5 0x0
817#define MX6Q_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0 817#define MX6QDL_PAD_CSI0_DAT12__ARM_TRACE09 0x288 0x658 0x000 0x7 0x0
818#define MX6Q_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0 818#define MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x28c 0x65c 0x000 0x0 0x0
819#define MX6Q_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0 819#define MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x28c 0x65c 0x000 0x1 0x0
820#define MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0 820#define MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x28c 0x65c 0x938 0x3 0x3
821#define MX6Q_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0 821#define MX6QDL_PAD_CSI0_DAT13__UART4_TX_DATA 0x28c 0x65c 0x000 0x3 0x0
822#define MX6Q_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0 822#define MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x28c 0x65c 0x000 0x5 0x0
823#define MX6Q_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2 823#define MX6QDL_PAD_CSI0_DAT13__ARM_TRACE10 0x28c 0x65c 0x000 0x7 0x0
824#define MX6Q_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0 824#define MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x290 0x660 0x000 0x0 0x0
825#define MX6Q_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0 825#define MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x290 0x660 0x000 0x1 0x0
826#define MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0 826#define MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x290 0x660 0x000 0x3 0x0
827#define MX6Q_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0 827#define MX6QDL_PAD_CSI0_DAT14__UART5_RX_DATA 0x290 0x660 0x940 0x3 0x2
828#define MX6Q_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3 828#define MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x290 0x660 0x000 0x5 0x0
829#define MX6Q_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0 829#define MX6QDL_PAD_CSI0_DAT14__ARM_TRACE11 0x290 0x660 0x000 0x7 0x0
830#define MX6Q_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0 830#define MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x294 0x664 0x000 0x0 0x0
831#define MX6Q_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0 831#define MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x294 0x664 0x000 0x1 0x0
832#define MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0 832#define MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x294 0x664 0x940 0x3 0x3
833#define MX6Q_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0 833#define MX6QDL_PAD_CSI0_DAT15__UART5_TX_DATA 0x294 0x664 0x000 0x3 0x0
834#define MX6Q_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0 834#define MX6QDL_PAD_CSI0_DAT15__GPIO6_IO01 0x294 0x664 0x000 0x5 0x0
835#define MX6Q_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0 835#define MX6QDL_PAD_CSI0_DAT15__ARM_TRACE12 0x294 0x664 0x000 0x7 0x0
836#define MX6Q_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0 836#define MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x298 0x668 0x000 0x0 0x0
837#define MX6Q_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0 837#define MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x298 0x668 0x000 0x1 0x0
838#define MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0 838#define MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x298 0x668 0x934 0x3 0x0
839#define MX6Q_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0 839#define MX6QDL_PAD_CSI0_DAT16__UART4_CTS_B 0x298 0x668 0x000 0x3 0x0
840#define MX6Q_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0 840#define MX6QDL_PAD_CSI0_DAT16__GPIO6_IO02 0x298 0x668 0x000 0x5 0x0
841#define MX6Q_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1 841#define MX6QDL_PAD_CSI0_DAT16__ARM_TRACE13 0x298 0x668 0x000 0x7 0x0
842#define MX6Q_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0 842#define MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x29c 0x66c 0x000 0x0 0x0
843#define MX6Q_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0 843#define MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x29c 0x66c 0x000 0x1 0x0
844#define MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0 844#define MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x29c 0x66c 0x000 0x3 0x0
845#define MX6Q_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0 845#define MX6QDL_PAD_CSI0_DAT17__UART4_RTS_B 0x29c 0x66c 0x934 0x3 0x1
846#define MX6Q_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2 846#define MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x29c 0x66c 0x000 0x5 0x0
847#define MX6Q_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0 847#define MX6QDL_PAD_CSI0_DAT17__ARM_TRACE14 0x29c 0x66c 0x000 0x7 0x0
848#define MX6Q_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0 848#define MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x2a0 0x670 0x000 0x0 0x0
849#define MX6Q_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0 849#define MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x2a0 0x670 0x000 0x1 0x0
850#define MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0 850#define MX6QDL_PAD_CSI0_DAT18__UART5_RTS_B 0x2a0 0x670 0x93c 0x3 0x2
851#define MX6Q_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0 851#define MX6QDL_PAD_CSI0_DAT18__UART5_CTS_B 0x2a0 0x670 0x000 0x3 0x0
852#define MX6Q_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0 852#define MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04 0x2a0 0x670 0x000 0x5 0x0
853#define MX6Q_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3 853#define MX6QDL_PAD_CSI0_DAT18__ARM_TRACE15 0x2a0 0x670 0x000 0x7 0x0
854#define MX6Q_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0 854#define MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x2a4 0x674 0x000 0x0 0x0
855#define MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0 855#define MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x2a4 0x674 0x000 0x1 0x0
856#define MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0 856#define MX6QDL_PAD_CSI0_DAT19__UART5_CTS_B 0x2a4 0x674 0x000 0x3 0x0
857#define MX6Q_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2 857#define MX6QDL_PAD_CSI0_DAT19__UART5_RTS_B 0x2a4 0x674 0x93c 0x3 0x3
858#define MX6Q_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0 858#define MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x2a4 0x674 0x000 0x5 0x0
859#define MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0 859#define MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x2a8 0x690 0x000 0x0 0x0
860#define MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3 860#define MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x2a8 0x690 0x000 0x1 0x0
861#define MX6Q_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0 861#define MX6QDL_PAD_SD3_DAT7__UART1_RX_DATA 0x2a8 0x690 0x920 0x1 0x2
862#define MX6Q_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0 862#define MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x2a8 0x690 0x000 0x5 0x0
863#define MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0 863#define MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x2ac 0x694 0x000 0x0 0x0
864#define MX6Q_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0 864#define MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x2ac 0x694 0x920 0x1 0x3
865#define MX6Q_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4 865#define MX6QDL_PAD_SD3_DAT6__UART1_TX_DATA 0x2ac 0x694 0x000 0x1 0x0
866#define MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0 866#define MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x2ac 0x694 0x000 0x5 0x0
867#define MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0 867#define MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x2b0 0x698 0x000 0x0 0x0
868#define MX6Q_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5 868#define MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x2b0 0x698 0x000 0x1 0x0
869#define MX6Q_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0 869#define MX6QDL_PAD_SD3_DAT5__UART2_RX_DATA 0x2b0 0x698 0x928 0x1 0x4
870#define MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0 870#define MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x2b0 0x698 0x000 0x5 0x0
871#define MX6Q_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0 871#define MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x2b4 0x69c 0x000 0x0 0x0
872#define MX6Q_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0 872#define MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x2b4 0x69c 0x928 0x1 0x5
873#define MX6Q_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2 873#define MX6QDL_PAD_SD3_DAT4__UART2_TX_DATA 0x2b4 0x69c 0x000 0x1 0x0
874#define MX6Q_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0 874#define MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x2b4 0x69c 0x000 0x5 0x0
875#define MX6Q_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0 875#define MX6QDL_PAD_SD3_CMD__SD3_CMD 0x2b8 0x6a0 0x000 0x0 0x0
876#define MX6Q_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0 876#define MX6QDL_PAD_SD3_CMD__UART2_CTS_B 0x2b8 0x6a0 0x000 0x1 0x0
877#define MX6Q_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3 877#define MX6QDL_PAD_SD3_CMD__UART2_RTS_B 0x2b8 0x6a0 0x924 0x1 0x2
878#define MX6Q_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0 878#define MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x2b8 0x6a0 0x000 0x2 0x0
879#define MX6Q_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2 879#define MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x2b8 0x6a0 0x000 0x5 0x0
880#define MX6Q_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0 880#define MX6QDL_PAD_SD3_CLK__SD3_CLK 0x2bc 0x6a4 0x000 0x0 0x0
881#define MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0 881#define MX6QDL_PAD_SD3_CLK__UART2_RTS_B 0x2bc 0x6a4 0x924 0x1 0x3
882#define MX6Q_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0 882#define MX6QDL_PAD_SD3_CLK__UART2_CTS_B 0x2bc 0x6a4 0x000 0x1 0x0
883#define MX6Q_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2 883#define MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x2bc 0x6a4 0x7e4 0x2 0x2
884#define MX6Q_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0 884#define MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x2bc 0x6a4 0x000 0x5 0x0
885#define MX6Q_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0 885#define MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x2c0 0x6a8 0x000 0x0 0x0
886#define MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0 886#define MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x2c0 0x6a8 0x000 0x1 0x0
887#define MX6Q_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3 887#define MX6QDL_PAD_SD3_DAT0__UART1_RTS_B 0x2c0 0x6a8 0x91c 0x1 0x2
888#define MX6Q_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0 888#define MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x2c0 0x6a8 0x000 0x2 0x0
889#define MX6Q_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1 889#define MX6QDL_PAD_SD3_DAT0__GPIO7_IO04 0x2c0 0x6a8 0x000 0x5 0x0
890#define MX6Q_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0 890#define MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x2c4 0x6ac 0x000 0x0 0x0
891#define MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0 891#define MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x2c4 0x6ac 0x91c 0x1 0x3
892#define MX6Q_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0 892#define MX6QDL_PAD_SD3_DAT1__UART1_CTS_B 0x2c4 0x6ac 0x000 0x1 0x0
893#define MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0 893#define MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x2c4 0x6ac 0x7e8 0x2 0x1
894#define MX6Q_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0 894#define MX6QDL_PAD_SD3_DAT1__GPIO7_IO05 0x2c4 0x6ac 0x000 0x5 0x0
895#define MX6Q_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4 895#define MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x2c8 0x6b0 0x000 0x0 0x0
896#define MX6Q_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0 896#define MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x2c8 0x6b0 0x000 0x5 0x0
897#define MX6Q_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0 897#define MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x2cc 0x6b4 0x000 0x0 0x0
898#define MX6Q_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5 898#define MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x2cc 0x6b4 0x000 0x1 0x0
899#define MX6Q_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0 899#define MX6QDL_PAD_SD3_DAT3__UART3_RTS_B 0x2cc 0x6b4 0x92c 0x1 0x4
900#define MX6Q_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0 900#define MX6QDL_PAD_SD3_DAT3__GPIO7_IO07 0x2cc 0x6b4 0x000 0x5 0x0
901#define MX6Q_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0 901#define MX6QDL_PAD_SD3_RST__SD3_RESET 0x2d0 0x6b8 0x000 0x0 0x0
902#define MX6Q_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0 902#define MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x2d0 0x6b8 0x92c 0x1 0x5
903#define MX6Q_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0 903#define MX6QDL_PAD_SD3_RST__UART3_CTS_B 0x2d0 0x6b8 0x000 0x1 0x0
904#define MX6Q_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0 904#define MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x2d0 0x6b8 0x000 0x5 0x0
905#define MX6Q_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0 905#define MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x2d4 0x6bc 0x000 0x0 0x0
906#define MX6Q_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0 906#define MX6QDL_PAD_NANDF_CLE__IPU2_SISG4 0x2d4 0x6bc 0x000 0x1 0x0
907#define MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0 907#define MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x2d4 0x6bc 0x000 0x5 0x0
908#define MX6Q_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0 908#define MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x2d8 0x6c0 0x000 0x0 0x0
909#define MX6Q_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0 909#define MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x2d8 0x6c0 0x000 0x1 0x0
910#define MX6Q_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0 910#define MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x2d8 0x6c0 0x000 0x5 0x0
911#define MX6Q_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0 911#define MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x2dc 0x6c4 0x000 0x0 0x0
912#define MX6Q_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0 912#define MX6QDL_PAD_NANDF_WP_B__IPU2_SISG5 0x2dc 0x6c4 0x000 0x1 0x0
913#define MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0 913#define MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x2dc 0x6c4 0x000 0x5 0x0
914#define MX6Q_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0 914#define MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x2e0 0x6c8 0x000 0x0 0x0
915#define MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0 915#define MX6QDL_PAD_NANDF_RB0__IPU2_DI0_PIN01 0x2e0 0x6c8 0x000 0x1 0x0
916#define MX6Q_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0 916#define MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x2e0 0x6c8 0x000 0x5 0x0
917#define MX6Q_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0 917#define MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x2e4 0x6cc 0x000 0x0 0x0
918#define MX6Q_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0 918#define MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x2e4 0x6cc 0x000 0x5 0x0
919#define MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0 919#define MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0x2e8 0x6d0 0x000 0x0 0x0
920#define MX6Q_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0 920#define MX6QDL_PAD_NANDF_CS1__SD4_VSELECT 0x2e8 0x6d0 0x000 0x1 0x0
921#define MX6Q_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1 921#define MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x2e8 0x6d0 0x000 0x2 0x0
922#define MX6Q_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0 922#define MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x2e8 0x6d0 0x000 0x5 0x0
923#define MX6Q_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0 923#define MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0x2ec 0x6d4 0x000 0x0 0x0
924#define MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0 924#define MX6QDL_PAD_NANDF_CS2__IPU1_SISG0 0x2ec 0x6d4 0x000 0x1 0x0
925#define MX6Q_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0 925#define MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x2ec 0x6d4 0x874 0x2 0x1
926#define MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0 926#define MX6QDL_PAD_NANDF_CS2__EIM_CRE 0x2ec 0x6d4 0x000 0x3 0x0
927#define MX6Q_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0 927#define MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x2ec 0x6d4 0x000 0x4 0x0
928#define MX6Q_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1 928#define MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x2ec 0x6d4 0x000 0x5 0x0
929#define MX6Q_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0 929#define MX6QDL_PAD_NANDF_CS2__IPU2_SISG0 0x2ec 0x6d4 0x000 0x6 0x0
930#define MX6Q_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0 930#define MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0x2f0 0x6d8 0x000 0x0 0x0
931#define MX6Q_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0 931#define MX6QDL_PAD_NANDF_CS3__IPU1_SISG1 0x2f0 0x6d8 0x000 0x1 0x0
932#define MX6Q_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0 932#define MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x2f0 0x6d8 0x878 0x2 0x1
933#define MX6Q_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0 933#define MX6QDL_PAD_NANDF_CS3__EIM_ADDR26 0x2f0 0x6d8 0x000 0x3 0x0
934#define MX6Q_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0 934#define MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x2f0 0x6d8 0x000 0x5 0x0
935#define MX6Q_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2 935#define MX6QDL_PAD_NANDF_CS3__IPU2_SISG1 0x2f0 0x6d8 0x000 0x6 0x0
936#define MX6Q_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0 936#define MX6QDL_PAD_SD4_CMD__SD4_CMD 0x2f4 0x6dc 0x000 0x0 0x0
937#define MX6Q_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0 937#define MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x2f4 0x6dc 0x000 0x1 0x0
938#define MX6Q_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0 938#define MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x2f4 0x6dc 0x000 0x2 0x0
939#define MX6Q_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3 939#define MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x2f4 0x6dc 0x930 0x2 0x2
940#define MX6Q_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0 940#define MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x2f4 0x6dc 0x000 0x5 0x0
941#define MX6Q_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0 941#define MX6QDL_PAD_SD4_CLK__SD4_CLK 0x2f8 0x6e0 0x000 0x0 0x0
942#define MX6Q_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0 942#define MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x2f8 0x6e0 0x000 0x1 0x0
943#define MX6Q_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0 943#define MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x2f8 0x6e0 0x930 0x2 0x3
944#define MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0 944#define MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x2f8 0x6e0 0x000 0x2 0x0
945#define MX6Q_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0 945#define MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x2f8 0x6e0 0x000 0x5 0x0
946#define MX6Q_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0 946#define MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x2fc 0x6e4 0x000 0x0 0x0
947#define MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0 947#define MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x2fc 0x6e4 0x000 0x1 0x0
948#define MX6Q_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0 948#define MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x2fc 0x6e4 0x000 0x5 0x0
949#define MX6Q_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0 949#define MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x300 0x6e8 0x000 0x0 0x0
950#define MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0 950#define MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x300 0x6e8 0x000 0x1 0x0
951#define MX6Q_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0 951#define MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x300 0x6e8 0x000 0x5 0x0
952#define MX6Q_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0 952#define MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x304 0x6ec 0x000 0x0 0x0
953#define MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0 953#define MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x304 0x6ec 0x000 0x1 0x0
954#define MX6Q_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0 954#define MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x304 0x6ec 0x000 0x5 0x0
955#define MX6Q_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0 955#define MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x308 0x6f0 0x000 0x0 0x0
956#define MX6Q_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0 956#define MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x308 0x6f0 0x000 0x1 0x0
957#define MX6Q_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0 957#define MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x308 0x6f0 0x000 0x5 0x0
958#define MX6Q_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0 958#define MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x30c 0x6f4 0x000 0x0 0x0
959#define MX6Q_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0 959#define MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x30c 0x6f4 0x000 0x1 0x0
960#define MX6Q_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0 960#define MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x30c 0x6f4 0x000 0x5 0x0
961#define MX6Q_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0 961#define MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x310 0x6f8 0x000 0x0 0x0
962#define MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0 962#define MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x310 0x6f8 0x000 0x1 0x0
963#define MX6Q_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0 963#define MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x310 0x6f8 0x000 0x5 0x0
964#define MX6Q_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0 964#define MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x314 0x6fc 0x000 0x0 0x0
965#define MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0 965#define MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x314 0x6fc 0x000 0x1 0x0
966#define MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0 966#define MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x314 0x6fc 0x000 0x5 0x0
967#define MX6Q_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0 967#define MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x318 0x700 0x000 0x0 0x0
968#define MX6Q_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0 968#define MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x318 0x700 0x000 0x1 0x0
969#define MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0 969#define MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x318 0x700 0x000 0x5 0x0
970#define MX6Q_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0 970#define MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x31c 0x704 0x000 0x1 0x0
971#define MX6Q_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0 971#define MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x31c 0x704 0x000 0x2 0x0
972#define MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0 972#define MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x31c 0x704 0x000 0x5 0x0
973#define MX6Q_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0 973#define MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x320 0x708 0x000 0x1 0x0
974#define MX6Q_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0 974#define MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x320 0x708 0x000 0x2 0x0
975#define MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0 975#define MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x320 0x708 0x000 0x5 0x0
976#define MX6Q_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0 976#define MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x324 0x70c 0x000 0x1 0x0
977#define MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0 977#define MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x324 0x70c 0x000 0x2 0x0
978#define MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6 978#define MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x324 0x70c 0x000 0x5 0x0
979#define MX6Q_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0 979#define MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x328 0x710 0x000 0x1 0x0
980#define MX6Q_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0 980#define MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x328 0x710 0x000 0x5 0x0
981#define MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0 981#define MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x32c 0x714 0x000 0x1 0x0
982#define MX6Q_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4 982#define MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x32c 0x714 0x928 0x2 0x6
983#define MX6Q_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0 983#define MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x32c 0x714 0x000 0x2 0x0
984#define MX6Q_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0 984#define MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x32c 0x714 0x000 0x5 0x0
985#define MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0 985#define MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x330 0x718 0x000 0x1 0x0
986#define MX6Q_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0 986#define MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x330 0x718 0x924 0x2 0x4
987#define MX6Q_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5 987#define MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x330 0x718 0x000 0x2 0x0
988#define MX6Q_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0 988#define MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x330 0x718 0x000 0x5 0x0
989#define MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0 989#define MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x334 0x71c 0x000 0x1 0x0
990#define MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0 990#define MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x334 0x71c 0x000 0x2 0x0
991#define MX6Q_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7 991#define MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x334 0x71c 0x924 0x2 0x5
992#define MX6Q_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0 992#define MX6QDL_PAD_SD4_DAT6__GPIO2_IO14 0x334 0x71c 0x000 0x5 0x0
993#define MX6Q_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0 993#define MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x338 0x720 0x000 0x1 0x0
994#define MX6Q_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1 994#define MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x338 0x720 0x000 0x2 0x0
995#define MX6Q_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0 995#define MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x338 0x720 0x928 0x2 0x7
996#define MX6Q_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0 996#define MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x338 0x720 0x000 0x5 0x0
997#define MX6Q_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0 997#define MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x33c 0x724 0x000 0x0 0x0
998#define MX6Q_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0 998#define MX6QDL_PAD_SD1_DAT1__ECSPI5_SS0 0x33c 0x724 0x834 0x1 0x1
999#define MX6Q_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1 999#define MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x33c 0x724 0x000 0x2 0x0
1000#define MX6Q_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0 1000#define MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x33c 0x724 0x000 0x3 0x0
1001#define MX6Q_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0 1001#define MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x33c 0x724 0x000 0x5 0x0
1002#define MX6Q_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0 1002#define MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x340 0x728 0x000 0x0 0x0
1003#define MX6Q_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0 1003#define MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x340 0x728 0x82c 0x1 0x1
1004#define MX6Q_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0 1004#define MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x340 0x728 0x000 0x3 0x0
1005#define MX6Q_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0 1005#define MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x340 0x728 0x000 0x5 0x0
1006#define MX6Q_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0 1006#define MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x344 0x72c 0x000 0x0 0x0
1007#define MX6Q_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0 1007#define MX6QDL_PAD_SD1_DAT3__ECSPI5_SS2 0x344 0x72c 0x000 0x1 0x0
1008#define MX6Q_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0 1008#define MX6QDL_PAD_SD1_DAT3__GPT_COMPARE3 0x344 0x72c 0x000 0x2 0x0
1009#define MX6Q_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0 1009#define MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x344 0x72c 0x000 0x3 0x0
1010#define MX6Q_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0 1010#define MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x344 0x72c 0x000 0x4 0x0
1011#define MX6Q_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0 1011#define MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x344 0x72c 0x000 0x5 0x0
1012#define MX6Q_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0 1012#define MX6QDL_PAD_SD1_DAT3__WDOG2_RESET_B_DEB 0x344 0x72c 0x000 0x6 0x0
1013#define MX6Q_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0 1013#define MX6QDL_PAD_SD1_CMD__SD1_CMD 0x348 0x730 0x000 0x0 0x0
1014#define MX6Q_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0 1014#define MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI 0x348 0x730 0x830 0x1 0x0
1015#define MX6Q_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1 1015#define MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x348 0x730 0x000 0x2 0x0
1016#define MX6Q_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0 1016#define MX6QDL_PAD_SD1_CMD__GPT_COMPARE1 0x348 0x730 0x000 0x3 0x0
1017#define MX6Q_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0 1017#define MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x348 0x730 0x000 0x5 0x0
1018#define MX6Q_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0 1018#define MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x34c 0x734 0x000 0x0 0x0
1019#define MX6Q_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0 1019#define MX6QDL_PAD_SD1_DAT2__ECSPI5_SS1 0x34c 0x734 0x838 0x1 0x1
1020#define MX6Q_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0 1020#define MX6QDL_PAD_SD1_DAT2__GPT_COMPARE2 0x34c 0x734 0x000 0x2 0x0
1021#define MX6Q_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0 1021#define MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x34c 0x734 0x000 0x3 0x0
1022#define MX6Q_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0 1022#define MX6QDL_PAD_SD1_DAT2__WDOG1_B 0x34c 0x734 0x000 0x4 0x0
1023#define MX6Q_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0 1023#define MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x34c 0x734 0x000 0x5 0x0
1024#define MX6Q_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0 1024#define MX6QDL_PAD_SD1_DAT2__WDOG1_RESET_B_DEB 0x34c 0x734 0x000 0x6 0x0
1025#define MX6Q_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0 1025#define MX6QDL_PAD_SD1_CLK__SD1_CLK 0x350 0x738 0x000 0x0 0x0
1026#define MX6Q_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1 1026#define MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK 0x350 0x738 0x828 0x1 0x0
1027#define MX6Q_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3 1027#define MX6QDL_PAD_SD1_CLK__GPT_CLKIN 0x350 0x738 0x000 0x3 0x0
1028#define MX6Q_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1 1028#define MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x350 0x738 0x000 0x5 0x0
1029#define MX6Q_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0 1029#define MX6QDL_PAD_SD2_CLK__SD2_CLK 0x354 0x73c 0x000 0x0 0x0
1030#define MX6Q_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0 1030#define MX6QDL_PAD_SD2_CLK__ECSPI5_SCLK 0x354 0x73c 0x828 0x1 0x1
1031#define MX6Q_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1 1031#define MX6QDL_PAD_SD2_CLK__KEY_COL5 0x354 0x73c 0x8e8 0x2 0x3
1032#define MX6Q_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2 1032#define MX6QDL_PAD_SD2_CLK__AUD4_RXFS 0x354 0x73c 0x7c0 0x3 0x1
1033#define MX6Q_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1 1033#define MX6QDL_PAD_SD2_CLK__GPIO1_IO10 0x354 0x73c 0x000 0x5 0x0
1034#define MX6Q_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0 1034#define MX6QDL_PAD_SD2_CMD__SD2_CMD 0x358 0x740 0x000 0x0 0x0
1035#define MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0 1035#define MX6QDL_PAD_SD2_CMD__ECSPI5_MOSI 0x358 0x740 0x830 0x1 0x1
1036#define MX6Q_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0 1036#define MX6QDL_PAD_SD2_CMD__KEY_ROW5 0x358 0x740 0x8f4 0x2 0x2
1037#define MX6Q_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2 1037#define MX6QDL_PAD_SD2_CMD__AUD4_RXC 0x358 0x740 0x7bc 0x3 0x1
1038#define MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1 1038#define MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x358 0x740 0x000 0x5 0x0
1039#define MX6Q_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0 1039#define MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x35c 0x744 0x000 0x0 0x0
1040#define MX6QDL_PAD_SD2_DAT3__ECSPI5_SS3 0x35c 0x744 0x000 0x1 0x0
1041#define MX6QDL_PAD_SD2_DAT3__KEY_COL6 0x35c 0x744 0x8ec 0x2 0x2
1042#define MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x35c 0x744 0x7c4 0x3 0x1
1043#define MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x35c 0x744 0x000 0x5 0x0
1040 1044
1041#endif /* __DTS_IMX6Q_PINFUNC_H */ 1045#endif /* __DTS_IMX6Q_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6q-sabreauto.dts b/arch/arm/boot/dts/imx6q-sabreauto.dts
index 09a75807bc6d..334b9247e78c 100644
--- a/arch/arm/boot/dts/imx6q-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6q-sabreauto.dts
@@ -20,24 +20,6 @@
20 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
21}; 21};
22 22
23&iomuxc { 23&sata {
24 pinctrl-names = "default"; 24 status = "okay";
25 pinctrl-0 = <&pinctrl_hog>;
26
27 hog {
28 pinctrl_hog: hoggrp {
29 fsl,pins = <
30 MX6Q_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
31 MX6Q_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
32 >;
33 };
34 };
35
36 ecspi1 {
37 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
38 fsl,pins = <
39 MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000
40 >;
41 };
42 };
43}; 25};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 6a000666c147..3530280f5150 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -65,6 +65,10 @@
65 }; 65 };
66}; 66};
67 67
68&sata {
69 status = "okay";
70};
71
68&ecspi1 { 72&ecspi1 {
69 fsl,spi-num-chipselects = <1>; 73 fsl,spi-num-chipselects = <1>;
70 cs-gpios = <&gpio3 19 0>; 74 cs-gpios = <&gpio3 19 0>;
@@ -91,14 +95,14 @@
91 hog { 95 hog {
92 pinctrl_hog: hoggrp { 96 pinctrl_hog: hoggrp {
93 fsl,pins = < 97 fsl,pins = <
94 MX6Q_PAD_NANDF_D6__GPIO2_IO06 0x80000000 98 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x80000000
95 MX6Q_PAD_NANDF_D7__GPIO2_IO07 0x80000000 99 MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x80000000
96 MX6Q_PAD_EIM_D19__GPIO3_IO19 0x80000000 100 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
97 MX6Q_PAD_EIM_D22__GPIO3_IO22 0x80000000 101 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
98 MX6Q_PAD_EIM_D23__GPIO3_IO23 0x80000000 102 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
99 MX6Q_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 103 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000
100 MX6Q_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 104 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0
101 MX6Q_PAD_GPIO_0__CCM_CLKO1 0x80000000 105 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x80000000
102 >; 106 >;
103 }; 107 };
104 }; 108 };
@@ -163,7 +167,7 @@
163 codec: sgtl5000@0a { 167 codec: sgtl5000@0a {
164 compatible = "fsl,sgtl5000"; 168 compatible = "fsl,sgtl5000";
165 reg = <0x0a>; 169 reg = <0x0a>;
166 clocks = <&clks 169>; 170 clocks = <&clks 201>;
167 VDDA-supply = <&reg_2p5v>; 171 VDDA-supply = <&reg_2p5v>;
168 VDDIO-supply = <&reg_3p3v>; 172 VDDIO-supply = <&reg_3p3v>;
169 }; 173 };
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 0038228c508c..9cbdfe7a0931 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,21 +20,6 @@
20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q"; 20 compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
21}; 21};
22 22
23&iomuxc { 23&sata {
24 pinctrl-names = "default"; 24 status = "okay";
25 pinctrl-0 = <&pinctrl_hog>;
26
27 hog {
28 pinctrl_hog: hoggrp {
29 fsl,pins = <
30 MX6Q_PAD_GPIO_4__GPIO1_IO04 0x80000000
31 MX6Q_PAD_GPIO_5__GPIO1_IO05 0x80000000
32 MX6Q_PAD_NANDF_D0__GPIO2_IO00 0x80000000
33 MX6Q_PAD_NANDF_D1__GPIO2_IO01 0x80000000
34 MX6Q_PAD_NANDF_D2__GPIO2_IO02 0x80000000
35 MX6Q_PAD_NANDF_D3__GPIO2_IO03 0x80000000
36 MX6Q_PAD_GPIO_0__CCM_CLKO1 0x130b0
37 >;
38 };
39 };
40}; 25};
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
new file mode 100644
index 000000000000..36be17f207b1
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6q.dtsi"
13#include "imx6qdl-wandboard.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Quad Board";
17 compatible = "wand,imx6q-wandboard", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ba09dc32324e..f024ef28b34b 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -8,8 +8,8 @@
8 * 8 *
9 */ 9 */
10 10
11#include "imx6qdl.dtsi"
12#include "imx6q-pinfunc.h" 11#include "imx6q-pinfunc.h"
12#include "imx6qdl.dtsi"
13 13
14/ { 14/ {
15 cpus { 15 cpus {
@@ -61,6 +61,12 @@
61 }; 61 };
62 62
63 soc { 63 soc {
64 ocram: sram@00900000 {
65 compatible = "mmio-sram";
66 reg = <0x00900000 0x40000>;
67 clocks = <&clks 142>;
68 };
69
64 aips-bus@02000000 { /* AIPS1 */ 70 aips-bus@02000000 { /* AIPS1 */
65 spba-bus@02000000 { 71 spba-bus@02000000 {
66 ecspi5: ecspi@02018000 { 72 ecspi5: ecspi@02018000 {
@@ -77,357 +83,54 @@
77 83
78 iomuxc: iomuxc@020e0000 { 84 iomuxc: iomuxc@020e0000 {
79 compatible = "fsl,imx6q-iomuxc"; 85 compatible = "fsl,imx6q-iomuxc";
80 reg = <0x020e0000 0x4000>;
81
82 /* shared pinctrl settings */
83 audmux {
84 pinctrl_audmux_1: audmux-1 {
85 fsl,pins = <
86 MX6Q_PAD_SD2_DAT0__AUD4_RXD 0x80000000
87 MX6Q_PAD_SD2_DAT3__AUD4_TXC 0x80000000
88 MX6Q_PAD_SD2_DAT2__AUD4_TXD 0x80000000
89 MX6Q_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
90 >;
91 };
92
93 pinctrl_audmux_2: audmux-2 {
94 fsl,pins = <
95 MX6Q_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
96 MX6Q_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
97 MX6Q_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
98 MX6Q_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
99 >;
100 };
101 };
102
103 ecspi1 {
104 pinctrl_ecspi1_1: ecspi1grp-1 {
105 fsl,pins = <
106 MX6Q_PAD_EIM_D17__ECSPI1_MISO 0x100b1
107 MX6Q_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
108 MX6Q_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
109 >;
110 };
111 };
112
113 ecspi3 {
114 pinctrl_ecspi3_1: ecspi3grp-1 {
115 fsl,pins = <
116 MX6Q_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
117 MX6Q_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
118 MX6Q_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
119 >;
120 };
121 };
122
123 enet {
124 pinctrl_enet_1: enetgrp-1 {
125 fsl,pins = <
126 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
127 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
128 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
129 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
130 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
131 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
132 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
133 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
134 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
135 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
136 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
137 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
138 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
139 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
140 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
141 MX6Q_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
142 >;
143 };
144
145 pinctrl_enet_2: enetgrp-2 {
146 fsl,pins = <
147 MX6Q_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
148 MX6Q_PAD_KEY_COL2__ENET_MDC 0x1b0b0
149 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
150 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
151 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
152 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
153 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
154 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
155 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
156 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
157 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
158 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
159 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
160 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
161 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
162 >;
163 };
164
165 pinctrl_enet_3: enetgrp-3 {
166 fsl,pins = <
167 MX6Q_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
168 MX6Q_PAD_ENET_MDC__ENET_MDC 0x1b0b0
169 MX6Q_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
170 MX6Q_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
171 MX6Q_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
172 MX6Q_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
173 MX6Q_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
174 MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
175 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
176 MX6Q_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
177 MX6Q_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
178 MX6Q_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
179 MX6Q_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
180 MX6Q_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
181 MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
182 MX6Q_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
183 >;
184 };
185 };
186
187 gpmi-nand {
188 pinctrl_gpmi_nand_1: gpmi-nand-1 {
189 fsl,pins = <
190 MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
191 MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
192 MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
193 MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
194 MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
195 MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
196 MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
197 MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
198 MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
199 MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
200 MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
201 MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
202 MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
203 MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
204 MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
205 MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
206 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
207 >;
208 };
209 };
210
211 i2c1 {
212 pinctrl_i2c1_1: i2c1grp-1 {
213 fsl,pins = <
214 MX6Q_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
215 MX6Q_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
216 >;
217 };
218 86
219 pinctrl_i2c1_2: i2c1grp-2 { 87 ipu2 {
220 fsl,pins = < 88 pinctrl_ipu2_1: ipu2grp-1 {
221 MX6Q_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 89 fsl,pins = <
222 MX6Q_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 90 MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
223 >; 91 MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15 0x10
224 }; 92 MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02 0x10
225 }; 93 MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03 0x10
226 94 MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04 0x80000000
227 i2c2 { 95 MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00 0x10
228 pinctrl_i2c2_1: i2c2grp-1 { 96 MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01 0x10
229 fsl,pins = < 97 MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02 0x10
230 MX6Q_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 98 MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03 0x10
231 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 99 MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04 0x10
100 MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05 0x10
101 MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06 0x10
102 MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07 0x10
103 MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08 0x10
104 MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09 0x10
105 MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10 0x10
106 MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11 0x10
107 MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12 0x10
108 MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13 0x10
109 MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14 0x10
110 MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15 0x10
111 MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16 0x10
112 MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17 0x10
113 MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18 0x10
114 MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19 0x10
115 MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20 0x10
116 MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21 0x10
117 MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22 0x10
118 MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23 0x10
232 >; 119 >;
233 }; 120 };
234 }; 121 };
235
236 i2c3 {
237 pinctrl_i2c3_1: i2c3grp-1 {
238 fsl,pins = <
239 MX6Q_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
240 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
241 >;
242 };
243 };
244
245 uart1 {
246 pinctrl_uart1_1: uart1grp-1 {
247 fsl,pins = <
248 MX6Q_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
249 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
250 >;
251 };
252 };
253
254 uart2 {
255 pinctrl_uart2_1: uart2grp-1 {
256 fsl,pins = <
257 MX6Q_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
258 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
259 >;
260 };
261 };
262
263 uart4 {
264 pinctrl_uart4_1: uart4grp-1 {
265 fsl,pins = <
266 MX6Q_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
267 MX6Q_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
268 >;
269 };
270 };
271
272 usbotg {
273 pinctrl_usbotg_1: usbotggrp-1 {
274 fsl,pins = <
275 MX6Q_PAD_GPIO_1__USB_OTG_ID 0x17059
276 >;
277 };
278
279 pinctrl_usbotg_2: usbotggrp-2 {
280 fsl,pins = <
281 MX6Q_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
282 >;
283 };
284 };
285
286 usdhc2 {
287 pinctrl_usdhc2_1: usdhc2grp-1 {
288 fsl,pins = <
289 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
290 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
291 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
292 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
293 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
294 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
295 MX6Q_PAD_NANDF_D4__SD2_DATA4 0x17059
296 MX6Q_PAD_NANDF_D5__SD2_DATA5 0x17059
297 MX6Q_PAD_NANDF_D6__SD2_DATA6 0x17059
298 MX6Q_PAD_NANDF_D7__SD2_DATA7 0x17059
299 >;
300 };
301
302 pinctrl_usdhc2_2: usdhc2grp-2 {
303 fsl,pins = <
304 MX6Q_PAD_SD2_CMD__SD2_CMD 0x17059
305 MX6Q_PAD_SD2_CLK__SD2_CLK 0x10059
306 MX6Q_PAD_SD2_DAT0__SD2_DATA0 0x17059
307 MX6Q_PAD_SD2_DAT1__SD2_DATA1 0x17059
308 MX6Q_PAD_SD2_DAT2__SD2_DATA2 0x17059
309 MX6Q_PAD_SD2_DAT3__SD2_DATA3 0x17059
310 >;
311 };
312 };
313
314 usdhc3 {
315 pinctrl_usdhc3_1: usdhc3grp-1 {
316 fsl,pins = <
317 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
318 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
319 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
320 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
321 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
322 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
323 MX6Q_PAD_SD3_DAT4__SD3_DATA4 0x17059
324 MX6Q_PAD_SD3_DAT5__SD3_DATA5 0x17059
325 MX6Q_PAD_SD3_DAT6__SD3_DATA6 0x17059
326 MX6Q_PAD_SD3_DAT7__SD3_DATA7 0x17059
327 >;
328 };
329
330 pinctrl_usdhc3_2: usdhc3grp-2 {
331 fsl,pins = <
332 MX6Q_PAD_SD3_CMD__SD3_CMD 0x17059
333 MX6Q_PAD_SD3_CLK__SD3_CLK 0x10059
334 MX6Q_PAD_SD3_DAT0__SD3_DATA0 0x17059
335 MX6Q_PAD_SD3_DAT1__SD3_DATA1 0x17059
336 MX6Q_PAD_SD3_DAT2__SD3_DATA2 0x17059
337 MX6Q_PAD_SD3_DAT3__SD3_DATA3 0x17059
338 >;
339 };
340 };
341
342 usdhc4 {
343 pinctrl_usdhc4_1: usdhc4grp-1 {
344 fsl,pins = <
345 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
346 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
347 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
348 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
349 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
350 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
351 MX6Q_PAD_SD4_DAT4__SD4_DATA4 0x17059
352 MX6Q_PAD_SD4_DAT5__SD4_DATA5 0x17059
353 MX6Q_PAD_SD4_DAT6__SD4_DATA6 0x17059
354 MX6Q_PAD_SD4_DAT7__SD4_DATA7 0x17059
355 >;
356 };
357
358 pinctrl_usdhc4_2: usdhc4grp-2 {
359 fsl,pins = <
360 MX6Q_PAD_SD4_CMD__SD4_CMD 0x17059
361 MX6Q_PAD_SD4_CLK__SD4_CLK 0x10059
362 MX6Q_PAD_SD4_DAT0__SD4_DATA0 0x17059
363 MX6Q_PAD_SD4_DAT1__SD4_DATA1 0x17059
364 MX6Q_PAD_SD4_DAT2__SD4_DATA2 0x17059
365 MX6Q_PAD_SD4_DAT3__SD4_DATA3 0x17059
366 >;
367 };
368 };
369
370 weim {
371 pinctrl_weim_cs0_1: weim_cs0grp-1 {
372 fsl,pins = <
373 MX6Q_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
374 >;
375 };
376
377 pinctrl_weim_nor_1: weimnorgrp-1 {
378 fsl,pins = <
379 MX6Q_PAD_EIM_OE__EIM_OE_B 0xb0b1
380 MX6Q_PAD_EIM_RW__EIM_RW 0xb0b1
381 MX6Q_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
382 /* data */
383 MX6Q_PAD_EIM_D16__EIM_DATA16 0x1b0b0
384 MX6Q_PAD_EIM_D17__EIM_DATA17 0x1b0b0
385 MX6Q_PAD_EIM_D18__EIM_DATA18 0x1b0b0
386 MX6Q_PAD_EIM_D19__EIM_DATA19 0x1b0b0
387 MX6Q_PAD_EIM_D20__EIM_DATA20 0x1b0b0
388 MX6Q_PAD_EIM_D21__EIM_DATA21 0x1b0b0
389 MX6Q_PAD_EIM_D22__EIM_DATA22 0x1b0b0
390 MX6Q_PAD_EIM_D23__EIM_DATA23 0x1b0b0
391 MX6Q_PAD_EIM_D24__EIM_DATA24 0x1b0b0
392 MX6Q_PAD_EIM_D25__EIM_DATA25 0x1b0b0
393 MX6Q_PAD_EIM_D26__EIM_DATA26 0x1b0b0
394 MX6Q_PAD_EIM_D27__EIM_DATA27 0x1b0b0
395 MX6Q_PAD_EIM_D28__EIM_DATA28 0x1b0b0
396 MX6Q_PAD_EIM_D29__EIM_DATA29 0x1b0b0
397 MX6Q_PAD_EIM_D30__EIM_DATA30 0x1b0b0
398 MX6Q_PAD_EIM_D31__EIM_DATA31 0x1b0b0
399 /* address */
400 MX6Q_PAD_EIM_A23__EIM_ADDR23 0xb0b1
401 MX6Q_PAD_EIM_A22__EIM_ADDR22 0xb0b1
402 MX6Q_PAD_EIM_A21__EIM_ADDR21 0xb0b1
403 MX6Q_PAD_EIM_A20__EIM_ADDR20 0xb0b1
404 MX6Q_PAD_EIM_A19__EIM_ADDR19 0xb0b1
405 MX6Q_PAD_EIM_A18__EIM_ADDR18 0xb0b1
406 MX6Q_PAD_EIM_A17__EIM_ADDR17 0xb0b1
407 MX6Q_PAD_EIM_A16__EIM_ADDR16 0xb0b1
408 MX6Q_PAD_EIM_DA15__EIM_AD15 0xb0b1
409 MX6Q_PAD_EIM_DA14__EIM_AD14 0xb0b1
410 MX6Q_PAD_EIM_DA13__EIM_AD13 0xb0b1
411 MX6Q_PAD_EIM_DA12__EIM_AD12 0xb0b1
412 MX6Q_PAD_EIM_DA11__EIM_AD11 0xb0b1
413 MX6Q_PAD_EIM_DA10__EIM_AD10 0xb0b1
414 MX6Q_PAD_EIM_DA9__EIM_AD09 0xb0b1
415 MX6Q_PAD_EIM_DA8__EIM_AD08 0xb0b1
416 MX6Q_PAD_EIM_DA7__EIM_AD07 0xb0b1
417 MX6Q_PAD_EIM_DA6__EIM_AD06 0xb0b1
418 MX6Q_PAD_EIM_DA5__EIM_AD05 0xb0b1
419 MX6Q_PAD_EIM_DA4__EIM_AD04 0xb0b1
420 MX6Q_PAD_EIM_DA3__EIM_AD03 0xb0b1
421 MX6Q_PAD_EIM_DA2__EIM_AD02 0xb0b1
422 MX6Q_PAD_EIM_DA1__EIM_AD01 0xb0b1
423 MX6Q_PAD_EIM_DA0__EIM_AD00 0xb0b1
424 >;
425 };
426
427 };
428 }; 122 };
429 }; 123 };
430 124
125 sata: sata@02200000 {
126 compatible = "fsl,imx6q-ahci";
127 reg = <0x02200000 0x4000>;
128 interrupts = <0 39 0x04>;
129 clocks = <&clks 154>, <&clks 187>, <&clks 105>;
130 clock-names = "sata", "sata_ref", "ahb";
131 status = "disabled";
132 };
133
431 ipu2: ipu@02800000 { 134 ipu2: ipu@02800000 {
432 #crtc-cells = <1>; 135 #crtc-cells = <1>;
433 compatible = "fsl,imx6q-ipu"; 136 compatible = "fsl,imx6q-ipu";
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e994011220e7..1cbbc5160d27 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -45,6 +45,28 @@
45 status = "okay"; 45 status = "okay";
46}; 46};
47 47
48&iomuxc {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_hog>;
51
52 hog {
53 pinctrl_hog: hoggrp {
54 fsl,pins = <
55 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
56 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
57 >;
58 };
59 };
60
61 ecspi1 {
62 pinctrl_ecspi1_sabreauto: ecspi1-sabreauto {
63 fsl,pins = <
64 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
65 >;
66 };
67 };
68};
69
48&uart4 { 70&uart4 {
49 pinctrl-names = "default"; 71 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_uart4_1>; 72 pinctrl-0 = <&pinctrl_uart4_1>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 6e5dfdb32416..39eafc222a2e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -27,6 +27,15 @@
27 enable-active-high; 27 enable-active-high;
28 }; 28 };
29 29
30 reg_usb_h1_vbus: usb_h1_vbus {
31 compatible = "regulator-fixed";
32 regulator-name = "usb_h1_vbus";
33 regulator-min-microvolt = <5000000>;
34 regulator-max-microvolt = <5000000>;
35 gpio = <&gpio1 29 0>;
36 enable-active-high;
37 };
38
30 reg_audio: wm8962_supply { 39 reg_audio: wm8962_supply {
31 compatible = "regulator-fixed"; 40 compatible = "regulator-fixed";
32 regulator-name = "wm8962-supply"; 41 regulator-name = "wm8962-supply";
@@ -41,12 +50,14 @@
41 volume-up { 50 volume-up {
42 label = "Volume Up"; 51 label = "Volume Up";
43 gpios = <&gpio1 4 0>; 52 gpios = <&gpio1 4 0>;
53 gpio-key,wakeup;
44 linux,code = <115>; /* KEY_VOLUMEUP */ 54 linux,code = <115>; /* KEY_VOLUMEUP */
45 }; 55 };
46 56
47 volume-down { 57 volume-down {
48 label = "Volume Down"; 58 label = "Volume Down";
49 gpios = <&gpio1 5 0>; 59 gpios = <&gpio1 5 0>;
60 gpio-key,wakeup;
50 linux,code = <114>; /* KEY_VOLUMEDOWN */ 61 linux,code = <114>; /* KEY_VOLUMEDOWN */
51 }; 62 };
52 }; 63 };
@@ -77,6 +88,22 @@
77 status = "okay"; 88 status = "okay";
78}; 89};
79 90
91&ecspi1 {
92 fsl,spi-num-chipselects = <1>;
93 cs-gpios = <&gpio4 9 0>;
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi1_2>;
96 status = "okay";
97
98 flash: m25p80@0 {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "st,m25p32";
102 spi-max-frequency = <20000000>;
103 reg = <0>;
104 };
105};
106
80&fec { 107&fec {
81 pinctrl-names = "default"; 108 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_enet_1>; 109 pinctrl-0 = <&pinctrl_enet_1>;
@@ -93,7 +120,7 @@
93 codec: wm8962@1a { 120 codec: wm8962@1a {
94 compatible = "wlf,wm8962"; 121 compatible = "wlf,wm8962";
95 reg = <0x1a>; 122 reg = <0x1a>;
96 clocks = <&clks 169>; 123 clocks = <&clks 201>;
97 DCVDD-supply = <&reg_audio>; 124 DCVDD-supply = <&reg_audio>;
98 DBVDD-supply = <&reg_audio>; 125 DBVDD-supply = <&reg_audio>;
99 AVDD-supply = <&reg_audio>; 126 AVDD-supply = <&reg_audio>;
@@ -113,6 +140,68 @@
113 }; 140 };
114}; 141};
115 142
143&i2c3 {
144 clock-frequency = <100000>;
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_i2c3_2>;
147 status = "okay";
148
149 egalax_ts@04 {
150 compatible = "eeti,egalax_ts";
151 reg = <0x04>;
152 interrupt-parent = <&gpio6>;
153 interrupts = <7 2>;
154 wakeup-gpios = <&gpio6 7 0>;
155 };
156};
157
158&iomuxc {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_hog>;
161
162 hog {
163 pinctrl_hog: hoggrp {
164 fsl,pins = <
165 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000
166 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000
167 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x80000000
168 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x80000000
169 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x80000000
170 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x80000000
171 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
172 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x80000000
173 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
174 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000
175 >;
176 };
177 };
178};
179
180&ldb {
181 status = "okay";
182
183 lvds-channel@1 {
184 fsl,data-mapping = "spwg";
185 fsl,data-width = <18>;
186 status = "okay";
187
188 display-timings {
189 native-mode = <&timing0>;
190 timing0: hsd100pxn1 {
191 clock-frequency = <65000000>;
192 hactive = <1024>;
193 vactive = <768>;
194 hback-porch = <220>;
195 hfront-porch = <40>;
196 vback-porch = <21>;
197 vfront-porch = <7>;
198 hsync-len = <60>;
199 vsync-len = <10>;
200 };
201 };
202 };
203};
204
116&ssi2 { 205&ssi2 {
117 fsl,mode = "i2s-slave"; 206 fsl,mode = "i2s-slave";
118 status = "okay"; 207 status = "okay";
@@ -125,6 +214,7 @@
125}; 214};
126 215
127&usbh1 { 216&usbh1 {
217 vbus-supply = <&reg_usb_h1_vbus>;
128 status = "okay"; 218 status = "okay";
129}; 219};
130 220
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
new file mode 100644
index 000000000000..a55113e65bcb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -0,0 +1,137 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/ {
13 regulators {
14 compatible = "simple-bus";
15
16 reg_2p5v: 2p5v {
17 compatible = "regulator-fixed";
18 regulator-name = "2P5V";
19 regulator-min-microvolt = <2500000>;
20 regulator-max-microvolt = <2500000>;
21 regulator-always-on;
22 };
23
24 reg_3p3v: 3p3v {
25 compatible = "regulator-fixed";
26 regulator-name = "3P3V";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 regulator-always-on;
30 };
31 };
32
33 sound {
34 compatible = "fsl,imx6-wandboard-sgtl5000",
35 "fsl,imx-audio-sgtl5000";
36 model = "imx6-wandboard-sgtl5000";
37 ssi-controller = <&ssi1>;
38 audio-codec = <&codec>;
39 audio-routing =
40 "MIC_IN", "Mic Jack",
41 "Mic Jack", "Mic Bias",
42 "Headphone Jack", "HP_OUT";
43 mux-int-port = <1>;
44 mux-ext-port = <3>;
45 };
46};
47
48&audmux {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_audmux_2>;
51 status = "okay";
52};
53
54&i2c2 {
55 clock-frequency = <100000>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_i2c2_2>;
58 status = "okay";
59
60 codec: sgtl5000@0a {
61 compatible = "fsl,sgtl5000";
62 reg = <0x0a>;
63 clocks = <&clks 201>;
64 VDDA-supply = <&reg_2p5v>;
65 VDDIO-supply = <&reg_3p3v>;
66 };
67};
68
69&iomuxc {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_hog>;
72
73 hog {
74 pinctrl_hog: hoggrp {
75 fsl,pins = <
76 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
77 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
78 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
79 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
80 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
81 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
82 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
83 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
84 >;
85 };
86 };
87};
88
89&fec {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_enet_1>;
92 phy-mode = "rgmii";
93 status = "okay";
94};
95
96&ssi1 {
97 fsl,mode = "i2s-slave";
98 status = "okay";
99};
100
101&uart1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_uart1_1>;
104 status = "okay";
105};
106
107&uart3 {
108 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_uart3_2>;
110 fsl,uart-has-rtscts;
111 status = "okay";
112};
113
114&usbh1 {
115 status = "okay";
116};
117
118&usdhc1 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_usdhc1_2>;
121 cd-gpios = <&gpio1 2 0>;
122 status = "okay";
123};
124
125&usdhc2 {
126 pinctrl-names = "default";
127 pinctrl-0 = <&pinctrl_usdhc2_2>;
128 non-removable;
129 status = "okay";
130};
131
132&usdhc3 {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_usdhc3_2>;
135 cd-gpios = <&gpio3 9 0>;
136 status = "okay";
137};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index f21d259080fd..ccd55c2fdb67 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -14,11 +14,6 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
22 gpio0 = &gpio1; 17 gpio0 = &gpio1;
23 gpio1 = &gpio2; 18 gpio1 = &gpio2;
24 gpio2 = &gpio3; 19 gpio2 = &gpio3;
@@ -26,6 +21,18 @@
26 gpio4 = &gpio5; 21 gpio4 = &gpio5;
27 gpio5 = &gpio6; 22 gpio5 = &gpio6;
28 gpio6 = &gpio7; 23 gpio6 = &gpio7;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
29 }; 36 };
30 37
31 intc: interrupt-controller@00a01000 { 38 intc: interrupt-controller@00a01000 {
@@ -81,15 +88,14 @@
81 #size-cells = <1>; 88 #size-cells = <1>;
82 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
83 reg-names = "gpmi-nand", "bch"; 90 reg-names = "gpmi-nand", "bch";
84 interrupts = <0 13 0x04>, <0 15 0x04>; 91 interrupts = <0 15 0x04>;
85 interrupt-names = "gpmi-dma", "bch"; 92 interrupt-names = "bch";
86 clocks = <&clks 152>, <&clks 153>, <&clks 151>, 93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
87 <&clks 150>, <&clks 149>; 94 <&clks 150>, <&clks 149>;
88 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
89 "gpmi_bch_apb", "per1_bch"; 96 "gpmi_bch_apb", "per1_bch";
90 dmas = <&dma_apbh 0>; 97 dmas = <&dma_apbh 0>;
91 dma-names = "rx-tx"; 98 dma-names = "rx-tx";
92 fsl,gpmi-dma-channel = <0>;
93 status = "disabled"; 99 status = "disabled";
94 }; 100 };
95 101
@@ -184,6 +190,8 @@
184 interrupts = <0 26 0x04>; 190 interrupts = <0 26 0x04>;
185 clocks = <&clks 160>, <&clks 161>; 191 clocks = <&clks 160>, <&clks 161>;
186 clock-names = "ipg", "per"; 192 clock-names = "ipg", "per";
193 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
194 dma-names = "rx", "tx";
187 status = "disabled"; 195 status = "disabled";
188 }; 196 };
189 197
@@ -197,6 +205,9 @@
197 reg = <0x02028000 0x4000>; 205 reg = <0x02028000 0x4000>;
198 interrupts = <0 46 0x04>; 206 interrupts = <0 46 0x04>;
199 clocks = <&clks 178>; 207 clocks = <&clks 178>;
208 dmas = <&sdma 37 1 0>,
209 <&sdma 38 1 0>;
210 dma-names = "rx", "tx";
200 fsl,fifo-depth = <15>; 211 fsl,fifo-depth = <15>;
201 fsl,ssi-dma-events = <38 37>; 212 fsl,ssi-dma-events = <38 37>;
202 status = "disabled"; 213 status = "disabled";
@@ -207,6 +218,9 @@
207 reg = <0x0202c000 0x4000>; 218 reg = <0x0202c000 0x4000>;
208 interrupts = <0 47 0x04>; 219 interrupts = <0 47 0x04>;
209 clocks = <&clks 179>; 220 clocks = <&clks 179>;
221 dmas = <&sdma 41 1 0>,
222 <&sdma 42 1 0>;
223 dma-names = "rx", "tx";
210 fsl,fifo-depth = <15>; 224 fsl,fifo-depth = <15>;
211 fsl,ssi-dma-events = <42 41>; 225 fsl,ssi-dma-events = <42 41>;
212 status = "disabled"; 226 status = "disabled";
@@ -217,6 +231,9 @@
217 reg = <0x02030000 0x4000>; 231 reg = <0x02030000 0x4000>;
218 interrupts = <0 48 0x04>; 232 interrupts = <0 48 0x04>;
219 clocks = <&clks 180>; 233 clocks = <&clks 180>;
234 dmas = <&sdma 45 1 0>,
235 <&sdma 46 1 0>;
236 dma-names = "rx", "tx";
220 fsl,fifo-depth = <15>; 237 fsl,fifo-depth = <15>;
221 fsl,ssi-dma-events = <46 45>; 238 fsl,ssi-dma-events = <46 45>;
222 status = "disabled"; 239 status = "disabled";
@@ -278,17 +295,23 @@
278 }; 295 };
279 296
280 can1: flexcan@02090000 { 297 can1: flexcan@02090000 {
298 compatible = "fsl,imx6q-flexcan";
281 reg = <0x02090000 0x4000>; 299 reg = <0x02090000 0x4000>;
282 interrupts = <0 110 0x04>; 300 interrupts = <0 110 0x04>;
301 clocks = <&clks 108>, <&clks 109>;
302 clock-names = "ipg", "per";
283 }; 303 };
284 304
285 can2: flexcan@02094000 { 305 can2: flexcan@02094000 {
306 compatible = "fsl,imx6q-flexcan";
286 reg = <0x02094000 0x4000>; 307 reg = <0x02094000 0x4000>;
287 interrupts = <0 111 0x04>; 308 interrupts = <0 111 0x04>;
309 clocks = <&clks 110>, <&clks 111>;
310 clock-names = "ipg", "per";
288 }; 311 };
289 312
290 gpt: gpt@02098000 { 313 gpt: gpt@02098000 {
291 compatible = "fsl,imx6q-gpt"; 314 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
292 reg = <0x02098000 0x4000>; 315 reg = <0x02098000 0x4000>;
293 interrupts = <0 55 0x04>; 316 interrupts = <0 55 0x04>;
294 clocks = <&clks 119>, <&clks 120>; 317 clocks = <&clks 119>, <&clks 120>;
@@ -491,6 +514,13 @@
491 }; 514 };
492 }; 515 };
493 516
517 tempmon: tempmon {
518 compatible = "fsl,imx6q-tempmon";
519 interrupts = <0 49 0x04>;
520 fsl,tempmon = <&anatop>;
521 fsl,tempmon-data = <&ocotp>;
522 };
523
494 usbphy1: usbphy@020c9000 { 524 usbphy1: usbphy@020c9000 {
495 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
496 reg = <0x020c9000 0x1000>; 526 reg = <0x020c9000 0x1000>;
@@ -546,6 +576,713 @@
546 reg = <0x020e0000 0x38>; 576 reg = <0x020e0000 0x38>;
547 }; 577 };
548 578
579 iomuxc: iomuxc@020e0000 {
580 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
581 reg = <0x020e0000 0x4000>;
582
583 audmux {
584 pinctrl_audmux_1: audmux-1 {
585 fsl,pins = <
586 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
587 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
588 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
589 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
590 >;
591 };
592
593 pinctrl_audmux_2: audmux-2 {
594 fsl,pins = <
595 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
596 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
597 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
598 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
599 >;
600 };
601
602 pinctrl_audmux_3: audmux-3 {
603 fsl,pins = <
604 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
605 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
606 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
607 >;
608 };
609 };
610
611 ecspi1 {
612 pinctrl_ecspi1_1: ecspi1grp-1 {
613 fsl,pins = <
614 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
615 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
616 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
617 >;
618 };
619
620 pinctrl_ecspi1_2: ecspi1grp-2 {
621 fsl,pins = <
622 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
623 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
624 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
625 >;
626 };
627 };
628
629 ecspi3 {
630 pinctrl_ecspi3_1: ecspi3grp-1 {
631 fsl,pins = <
632 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
633 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
634 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
635 >;
636 };
637 };
638
639 enet {
640 pinctrl_enet_1: enetgrp-1 {
641 fsl,pins = <
642 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
643 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
644 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
645 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
646 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
647 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
648 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
649 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
650 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
651 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
652 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
653 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
654 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
655 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
656 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
657 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
658 >;
659 };
660
661 pinctrl_enet_2: enetgrp-2 {
662 fsl,pins = <
663 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
664 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
665 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
666 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
667 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
668 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
669 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
670 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
671 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
672 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
673 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
674 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
675 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
676 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
677 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
678 >;
679 };
680
681 pinctrl_enet_3: enetgrp-3 {
682 fsl,pins = <
683 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
684 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
685 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
686 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
687 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
688 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
689 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
690 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
691 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
692 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
693 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
694 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
695 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
696 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
697 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
698 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
699 >;
700 };
701 };
702
703 esai {
704 pinctrl_esai_1: esaigrp-1 {
705 fsl,pins = <
706 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
707 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
708 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
709 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
710 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
711 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
712 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
713 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
714 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
715 >;
716 };
717
718 pinctrl_esai_2: esaigrp-2 {
719 fsl,pins = <
720 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
721 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
722 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
723 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
724 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
725 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
726 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
727 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
728 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
729 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
730 >;
731 };
732 };
733
734 flexcan1 {
735 pinctrl_flexcan1_1: flexcan1grp-1 {
736 fsl,pins = <
737 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
738 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
739 >;
740 };
741
742 pinctrl_flexcan1_2: flexcan1grp-2 {
743 fsl,pins = <
744 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
745 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
746 >;
747 };
748 };
749
750 flexcan2 {
751 pinctrl_flexcan2_1: flexcan2grp-1 {
752 fsl,pins = <
753 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
754 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
755 >;
756 };
757 };
758
759 gpmi-nand {
760 pinctrl_gpmi_nand_1: gpmi-nand-1 {
761 fsl,pins = <
762 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
763 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
764 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
765 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
766 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
767 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
768 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
769 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
770 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
771 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
772 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
773 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
774 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
775 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
776 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
777 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
778 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
779 >;
780 };
781 };
782
783 hdmi_hdcp {
784 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
785 fsl,pins = <
786 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
787 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
788 >;
789 };
790
791 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
792 fsl,pins = <
793 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
794 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
795 >;
796 };
797
798 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
799 fsl,pins = <
800 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
801 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
802 >;
803 };
804 };
805
806 hdmi_cec {
807 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
808 fsl,pins = <
809 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
810 >;
811 };
812
813 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
814 fsl,pins = <
815 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
816 >;
817 };
818 };
819
820 i2c1 {
821 pinctrl_i2c1_1: i2c1grp-1 {
822 fsl,pins = <
823 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
824 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
825 >;
826 };
827
828 pinctrl_i2c1_2: i2c1grp-2 {
829 fsl,pins = <
830 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
831 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
832 >;
833 };
834 };
835
836 i2c2 {
837 pinctrl_i2c2_1: i2c2grp-1 {
838 fsl,pins = <
839 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
840 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
841 >;
842 };
843
844 pinctrl_i2c2_2: i2c2grp-2 {
845 fsl,pins = <
846 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
847 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
848 >;
849 };
850
851 pinctrl_i2c2_3: i2c2grp-3 {
852 fsl,pins = <
853 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
854 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
855 >;
856 };
857 };
858
859 i2c3 {
860 pinctrl_i2c3_1: i2c3grp-1 {
861 fsl,pins = <
862 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
863 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
864 >;
865 };
866
867 pinctrl_i2c3_2: i2c3grp-2 {
868 fsl,pins = <
869 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
870 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
871 >;
872 };
873
874 pinctrl_i2c3_3: i2c3grp-3 {
875 fsl,pins = <
876 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
877 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
878 >;
879 };
880
881 pinctrl_i2c3_4: i2c3grp-4 {
882 fsl,pins = <
883 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
884 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
885 >;
886 };
887 };
888
889 ipu1 {
890 pinctrl_ipu1_1: ipu1grp-1 {
891 fsl,pins = <
892 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
893 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
894 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
895 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
896 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
897 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
898 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
899 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
900 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
901 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
902 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
903 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
904 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
905 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
906 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
907 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
908 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
909 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
910 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
911 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
912 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
913 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
914 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
915 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
916 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
917 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
918 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
919 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
920 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
921 >;
922 };
923
924 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
925 fsl,pins = <
926 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
927 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
928 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
929 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
930 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
931 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
932 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
933 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
934 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
935 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
936 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
937 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
938 >;
939 };
940
941 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
942 fsl,pins = <
943 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
944 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
945 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
946 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
947 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
948 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
949 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
950 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
951 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
952 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
953 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
954 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
955 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
956 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
957 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
958 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
959 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
960 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
961 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
962 >;
963 };
964 };
965
966 mlb {
967 pinctrl_mlb_1: mlbgrp-1 {
968 fsl,pins = <
969 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
970 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
971 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
972 >;
973 };
974
975 pinctrl_mlb_2: mlbgrp-2 {
976 fsl,pins = <
977 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
978 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
979 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
980 >;
981 };
982 };
983
984 pwm0 {
985 pinctrl_pwm0_1: pwm0grp-1 {
986 fsl,pins = <
987 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
988 >;
989 };
990 };
991
992 pwm3 {
993 pinctrl_pwm3_1: pwm3grp-1 {
994 fsl,pins = <
995 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
996 >;
997 };
998 };
999
1000 spdif {
1001 pinctrl_spdif_1: spdifgrp-1 {
1002 fsl,pins = <
1003 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
1004 >;
1005 };
1006
1007 pinctrl_spdif_2: spdifgrp-2 {
1008 fsl,pins = <
1009 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1010 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1011 >;
1012 };
1013 };
1014
1015 uart1 {
1016 pinctrl_uart1_1: uart1grp-1 {
1017 fsl,pins = <
1018 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1019 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1020 >;
1021 };
1022 };
1023
1024 uart2 {
1025 pinctrl_uart2_1: uart2grp-1 {
1026 fsl,pins = <
1027 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1028 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1029 >;
1030 };
1031
1032 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1033 fsl,pins = <
1034 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1035 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1036 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1037 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1038 >;
1039 };
1040 };
1041
1042 uart3 {
1043 pinctrl_uart3_1: uart3grp-1 {
1044 fsl,pins = <
1045 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1046 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1047 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1048 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1049 >;
1050 };
1051
1052 pinctrl_uart3_2: uart3grp-2 {
1053 fsl,pins = <
1054 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1055 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1056 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1057 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1058 >;
1059 };
1060 };
1061
1062 uart4 {
1063 pinctrl_uart4_1: uart4grp-1 {
1064 fsl,pins = <
1065 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1066 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1067 >;
1068 };
1069 };
1070
1071 usbotg {
1072 pinctrl_usbotg_1: usbotggrp-1 {
1073 fsl,pins = <
1074 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1075 >;
1076 };
1077
1078 pinctrl_usbotg_2: usbotggrp-2 {
1079 fsl,pins = <
1080 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1081 >;
1082 };
1083 };
1084
1085 usbh2 {
1086 pinctrl_usbh2_1: usbh2grp-1 {
1087 fsl,pins = <
1088 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1089 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1090 >;
1091 };
1092
1093 pinctrl_usbh2_2: usbh2grp-2 {
1094 fsl,pins = <
1095 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1096 >;
1097 };
1098 };
1099
1100 usbh3 {
1101 pinctrl_usbh3_1: usbh3grp-1 {
1102 fsl,pins = <
1103 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1104 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1105 >;
1106 };
1107
1108 pinctrl_usbh3_2: usbh3grp-2 {
1109 fsl,pins = <
1110 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1111 >;
1112 };
1113 };
1114
1115 usdhc1 {
1116 pinctrl_usdhc1_1: usdhc1grp-1 {
1117 fsl,pins = <
1118 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1119 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1120 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1121 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1122 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1123 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1124 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1125 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1126 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1127 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1128 >;
1129 };
1130
1131 pinctrl_usdhc1_2: usdhc1grp-2 {
1132 fsl,pins = <
1133 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1134 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1135 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1136 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1137 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1138 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1139 >;
1140 };
1141 };
1142
1143 usdhc2 {
1144 pinctrl_usdhc2_1: usdhc2grp-1 {
1145 fsl,pins = <
1146 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1147 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1148 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1149 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1150 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1151 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1152 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1153 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1154 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1155 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1156 >;
1157 };
1158
1159 pinctrl_usdhc2_2: usdhc2grp-2 {
1160 fsl,pins = <
1161 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1162 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1163 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1164 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1165 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1166 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1167 >;
1168 };
1169 };
1170
1171 usdhc3 {
1172 pinctrl_usdhc3_1: usdhc3grp-1 {
1173 fsl,pins = <
1174 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1175 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1176 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1177 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1178 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1179 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1180 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1181 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1182 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1183 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1184 >;
1185 };
1186
1187 pinctrl_usdhc3_2: usdhc3grp-2 {
1188 fsl,pins = <
1189 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1190 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1191 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1192 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1193 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1194 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1195 >;
1196 };
1197 };
1198
1199 usdhc4 {
1200 pinctrl_usdhc4_1: usdhc4grp-1 {
1201 fsl,pins = <
1202 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1203 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1204 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1205 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1206 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1207 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1208 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1209 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1210 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1211 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1212 >;
1213 };
1214
1215 pinctrl_usdhc4_2: usdhc4grp-2 {
1216 fsl,pins = <
1217 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1218 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1219 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1220 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1221 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1222 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1223 >;
1224 };
1225 };
1226
1227 weim {
1228 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1229 fsl,pins = <
1230 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1231 >;
1232 };
1233
1234 pinctrl_weim_nor_1: weim_norgrp-1 {
1235 fsl,pins = <
1236 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1237 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1238 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1239 /* data */
1240 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1241 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1242 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1243 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1244 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1245 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1246 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1247 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1248 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1249 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1250 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1251 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1252 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1253 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1254 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1255 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1256 /* address */
1257 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1258 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1259 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1260 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1261 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1262 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1263 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1264 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1265 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1266 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1267 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1268 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1269 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1270 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1271 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1272 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1273 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1274 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1275 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1276 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1277 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1278 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1279 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1280 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1281 >;
1282 };
1283 };
1284 };
1285
549 ldb: ldb@020e0008 { 1286 ldb: ldb@020e0008 {
550 #address-cells = <1>; 1287 #address-cells = <1>;
551 #size-cells = <0>; 1288 #size-cells = <0>;
@@ -555,13 +1292,11 @@
555 1292
556 lvds-channel@0 { 1293 lvds-channel@0 {
557 reg = <0>; 1294 reg = <0>;
558 crtcs = <&ipu1 0>;
559 status = "disabled"; 1295 status = "disabled";
560 }; 1296 };
561 1297
562 lvds-channel@1 { 1298 lvds-channel@1 {
563 reg = <1>; 1299 reg = <1>;
564 crtcs = <&ipu1 1>;
565 status = "disabled"; 1300 status = "disabled";
566 }; 1301 };
567 }; 1302 };
@@ -582,6 +1317,7 @@
582 interrupts = <0 2 0x04>; 1317 interrupts = <0 2 0x04>;
583 clocks = <&clks 155>, <&clks 155>; 1318 clocks = <&clks 155>, <&clks 155>;
584 clock-names = "ipg", "ahb"; 1319 clock-names = "ipg", "ahb";
1320 #dma-cells = <3>;
585 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 1321 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
586 }; 1322 };
587 }; 1323 };
@@ -751,8 +1487,8 @@
751 clocks = <&clks 196>; 1487 clocks = <&clks 196>;
752 }; 1488 };
753 1489
754 ocotp@021bc000 { 1490 ocotp: ocotp@021bc000 {
755 compatible = "fsl,imx6q-ocotp"; 1491 compatible = "fsl,imx6q-ocotp", "syscon";
756 reg = <0x021bc000 0x4000>; 1492 reg = <0x021bc000 0x4000>;
757 }; 1493 };
758 1494
@@ -791,6 +1527,8 @@
791 interrupts = <0 27 0x04>; 1527 interrupts = <0 27 0x04>;
792 clocks = <&clks 160>, <&clks 161>; 1528 clocks = <&clks 160>, <&clks 161>;
793 clock-names = "ipg", "per"; 1529 clock-names = "ipg", "per";
1530 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1531 dma-names = "rx", "tx";
794 status = "disabled"; 1532 status = "disabled";
795 }; 1533 };
796 1534
@@ -800,6 +1538,8 @@
800 interrupts = <0 28 0x04>; 1538 interrupts = <0 28 0x04>;
801 clocks = <&clks 160>, <&clks 161>; 1539 clocks = <&clks 160>, <&clks 161>;
802 clock-names = "ipg", "per"; 1540 clock-names = "ipg", "per";
1541 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1542 dma-names = "rx", "tx";
803 status = "disabled"; 1543 status = "disabled";
804 }; 1544 };
805 1545
@@ -809,6 +1549,8 @@
809 interrupts = <0 29 0x04>; 1549 interrupts = <0 29 0x04>;
810 clocks = <&clks 160>, <&clks 161>; 1550 clocks = <&clks 160>, <&clks 161>;
811 clock-names = "ipg", "per"; 1551 clock-names = "ipg", "per";
1552 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1553 dma-names = "rx", "tx";
812 status = "disabled"; 1554 status = "disabled";
813 }; 1555 };
814 1556
@@ -818,6 +1560,8 @@
818 interrupts = <0 30 0x04>; 1560 interrupts = <0 30 0x04>;
819 clocks = <&clks 160>, <&clks 161>; 1561 clocks = <&clks 160>, <&clks 161>;
820 clock-names = "ipg", "per"; 1562 clock-names = "ipg", "per";
1563 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1564 dma-names = "rx", "tx";
821 status = "disabled"; 1565 status = "disabled";
822 }; 1566 };
823 }; 1567 };
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index c5e5da02d7e3..c46651e4d966 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -152,32 +152,41 @@
152 }; 152 };
153 153
154 uart5: serial@02018000 { 154 uart5: serial@02018000 {
155 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 155 compatible = "fsl,imx6sl-uart",
156 "fsl,imx6q-uart", "fsl,imx21-uart";
156 reg = <0x02018000 0x4000>; 157 reg = <0x02018000 0x4000>;
157 interrupts = <0 30 0x04>; 158 interrupts = <0 30 0x04>;
158 clocks = <&clks IMX6SL_CLK_UART>, 159 clocks = <&clks IMX6SL_CLK_UART>,
159 <&clks IMX6SL_CLK_UART_SERIAL>; 160 <&clks IMX6SL_CLK_UART_SERIAL>;
160 clock-names = "ipg", "per"; 161 clock-names = "ipg", "per";
162 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
163 dma-names = "rx", "tx";
161 status = "disabled"; 164 status = "disabled";
162 }; 165 };
163 166
164 uart1: serial@02020000 { 167 uart1: serial@02020000 {
165 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 168 compatible = "fsl,imx6sl-uart",
169 "fsl,imx6q-uart", "fsl,imx21-uart";
166 reg = <0x02020000 0x4000>; 170 reg = <0x02020000 0x4000>;
167 interrupts = <0 26 0x04>; 171 interrupts = <0 26 0x04>;
168 clocks = <&clks IMX6SL_CLK_UART>, 172 clocks = <&clks IMX6SL_CLK_UART>,
169 <&clks IMX6SL_CLK_UART_SERIAL>; 173 <&clks IMX6SL_CLK_UART_SERIAL>;
170 clock-names = "ipg", "per"; 174 clock-names = "ipg", "per";
175 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
176 dma-names = "rx", "tx";
171 status = "disabled"; 177 status = "disabled";
172 }; 178 };
173 179
174 uart2: serial@02024000 { 180 uart2: serial@02024000 {
175 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 181 compatible = "fsl,imx6sl-uart",
182 "fsl,imx6q-uart", "fsl,imx21-uart";
176 reg = <0x02024000 0x4000>; 183 reg = <0x02024000 0x4000>;
177 interrupts = <0 27 0x04>; 184 interrupts = <0 27 0x04>;
178 clocks = <&clks IMX6SL_CLK_UART>, 185 clocks = <&clks IMX6SL_CLK_UART>,
179 <&clks IMX6SL_CLK_UART_SERIAL>; 186 <&clks IMX6SL_CLK_UART_SERIAL>;
180 clock-names = "ipg", "per"; 187 clock-names = "ipg", "per";
188 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
189 dma-names = "rx", "tx";
181 status = "disabled"; 190 status = "disabled";
182 }; 191 };
183 192
@@ -186,6 +195,9 @@
186 reg = <0x02028000 0x4000>; 195 reg = <0x02028000 0x4000>;
187 interrupts = <0 46 0x04>; 196 interrupts = <0 46 0x04>;
188 clocks = <&clks IMX6SL_CLK_SSI1>; 197 clocks = <&clks IMX6SL_CLK_SSI1>;
198 dmas = <&sdma 37 1 0>,
199 <&sdma 38 1 0>;
200 dma-names = "rx", "tx";
189 fsl,fifo-depth = <15>; 201 fsl,fifo-depth = <15>;
190 status = "disabled"; 202 status = "disabled";
191 }; 203 };
@@ -195,6 +207,9 @@
195 reg = <0x0202c000 0x4000>; 207 reg = <0x0202c000 0x4000>;
196 interrupts = <0 47 0x04>; 208 interrupts = <0 47 0x04>;
197 clocks = <&clks IMX6SL_CLK_SSI2>; 209 clocks = <&clks IMX6SL_CLK_SSI2>;
210 dmas = <&sdma 41 1 0>,
211 <&sdma 42 1 0>;
212 dma-names = "rx", "tx";
198 fsl,fifo-depth = <15>; 213 fsl,fifo-depth = <15>;
199 status = "disabled"; 214 status = "disabled";
200 }; 215 };
@@ -204,27 +219,36 @@
204 reg = <0x02030000 0x4000>; 219 reg = <0x02030000 0x4000>;
205 interrupts = <0 48 0x04>; 220 interrupts = <0 48 0x04>;
206 clocks = <&clks IMX6SL_CLK_SSI3>; 221 clocks = <&clks IMX6SL_CLK_SSI3>;
222 dmas = <&sdma 45 1 0>,
223 <&sdma 46 1 0>;
224 dma-names = "rx", "tx";
207 fsl,fifo-depth = <15>; 225 fsl,fifo-depth = <15>;
208 status = "disabled"; 226 status = "disabled";
209 }; 227 };
210 228
211 uart3: serial@02034000 { 229 uart3: serial@02034000 {
212 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 230 compatible = "fsl,imx6sl-uart",
231 "fsl,imx6q-uart", "fsl,imx21-uart";
213 reg = <0x02034000 0x4000>; 232 reg = <0x02034000 0x4000>;
214 interrupts = <0 28 0x04>; 233 interrupts = <0 28 0x04>;
215 clocks = <&clks IMX6SL_CLK_UART>, 234 clocks = <&clks IMX6SL_CLK_UART>,
216 <&clks IMX6SL_CLK_UART_SERIAL>; 235 <&clks IMX6SL_CLK_UART_SERIAL>;
217 clock-names = "ipg", "per"; 236 clock-names = "ipg", "per";
237 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
238 dma-names = "rx", "tx";
218 status = "disabled"; 239 status = "disabled";
219 }; 240 };
220 241
221 uart4: serial@02038000 { 242 uart4: serial@02038000 {
222 compatible = "fsl,imx6sl-uart", "fsl,imx21-uart"; 243 compatible = "fsl,imx6sl-uart",
244 "fsl,imx6q-uart", "fsl,imx21-uart";
223 reg = <0x02038000 0x4000>; 245 reg = <0x02038000 0x4000>;
224 interrupts = <0 29 0x04>; 246 interrupts = <0 29 0x04>;
225 clocks = <&clks IMX6SL_CLK_UART>, 247 clocks = <&clks IMX6SL_CLK_UART>,
226 <&clks IMX6SL_CLK_UART_SERIAL>; 248 <&clks IMX6SL_CLK_UART_SERIAL>;
227 clock-names = "ipg", "per"; 249 clock-names = "ipg", "per";
250 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
251 dma-names = "rx", "tx";
228 status = "disabled"; 252 status = "disabled";
229 }; 253 };
230 }; 254 };
@@ -594,6 +618,7 @@
594 clocks = <&clks IMX6SL_CLK_SDMA>, 618 clocks = <&clks IMX6SL_CLK_SDMA>,
595 <&clks IMX6SL_CLK_SDMA>; 619 <&clks IMX6SL_CLK_SDMA>;
596 clock-names = "ipg", "ahb"; 620 clock-names = "ipg", "ahb";
621 #dma-cells = <3>;
597 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin"; 622 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sl.bin";
598 }; 623 };
599 624
diff --git a/arch/arm/boot/dts/keystone.dts b/arch/arm/boot/dts/keystone.dts
index 1334b42c6b77..a68e34bbecb2 100644
--- a/arch/arm/boot/dts/keystone.dts
+++ b/arch/arm/boot/dts/keystone.dts
@@ -7,7 +7,9 @@
7 */ 7 */
8 8
9/dts-v1/; 9/dts-v1/;
10/include/ "skeleton.dtsi" 10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12#include "skeleton.dtsi"
11 13
12/ { 14/ {
13 model = "Texas Instruments Keystone 2 SoC"; 15 model = "Texas Instruments Keystone 2 SoC";
@@ -67,18 +69,23 @@
67 69
68 timer { 70 timer {
69 compatible = "arm,armv7-timer"; 71 compatible = "arm,armv7-timer";
70 interrupts = <1 13 0xf08>, 72 interrupts =
71 <1 14 0xf08>, 73 <GIC_PPI 13
72 <1 11 0xf08>, 74 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
73 <1 10 0x308>; 75 <GIC_PPI 14
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 11
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 10
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
74 }; 81 };
75 82
76 pmu { 83 pmu {
77 compatible = "arm,cortex-a15-pmu"; 84 compatible = "arm,cortex-a15-pmu";
78 interrupts = <0 20 0xf01>, 85 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>,
79 <0 21 0xf01>, 86 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
80 <0 22 0xf01>, 87 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>,
81 <0 23 0xf01>; 88 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>;
82 }; 89 };
83 90
84 soc { 91 soc {
@@ -100,7 +107,7 @@
100 reg-io-width = <4>; 107 reg-io-width = <4>;
101 reg = <0x02530c00 0x100>; 108 reg = <0x02530c00 0x100>;
102 clock-frequency = <133120000>; 109 clock-frequency = <133120000>;
103 interrupts = <0 277 0xf01>; 110 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
104 }; 111 };
105 112
106 uart1: serial@02531000 { 113 uart1: serial@02531000 {
@@ -110,7 +117,7 @@
110 reg-io-width = <4>; 117 reg-io-width = <4>;
111 reg = <0x02531000 0x100>; 118 reg = <0x02531000 0x100>;
112 clock-frequency = <133120000>; 119 clock-frequency = <133120000>;
113 interrupts = <0 280 0xf01>; 120 interrupts = <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>;
114 }; 121 };
115 122
116 }; 123 };
diff --git a/arch/arm/boot/dts/kirkwood-6281.dtsi b/arch/arm/boot/dts/kirkwood-6281.dtsi
index 1e5bef0bead7..650ef30e1856 100644
--- a/arch/arm/boot/dts/kirkwood-6281.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6281.dtsi
@@ -1,4 +1,39 @@
1/ { 1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
17
18 pcie@1,0 {
19 device_type = "pci";
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
22 #address-cells = <3>;
23 #size-cells = <2>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &intc 9>;
29 marvell,pcie-port = <0>;
30 marvell,pcie-lane = <0>;
31 clocks = <&gate_clk 2>;
32 status = "disabled";
33 };
34 };
35 };
36
2 ocp@f1000000 { 37 ocp@f1000000 {
3 pinctrl: pinctrl@10000 { 38 pinctrl: pinctrl@10000 {
4 compatible = "marvell,88f6281-pinctrl"; 39 compatible = "marvell,88f6281-pinctrl";
@@ -41,37 +76,6 @@
41 }; 76 };
42 }; 77 };
43 78
44 pcie-controller {
45 compatible = "marvell,kirkwood-pcie";
46 status = "disabled";
47 device_type = "pci";
48
49 #address-cells = <3>;
50 #size-cells = <2>;
51
52 bus-range = <0x00 0xff>;
53
54 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
55 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
56 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
57
58 pcie@1,0 {
59 device_type = "pci";
60 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
61 reg = <0x0800 0 0 0 0>;
62 #address-cells = <3>;
63 #size-cells = <2>;
64 #interrupt-cells = <1>;
65 ranges;
66 interrupt-map-mask = <0 0 0 0>;
67 interrupt-map = <0 0 0 0 &intc 9>;
68 marvell,pcie-port = <0>;
69 marvell,pcie-lane = <0>;
70 clocks = <&gate_clk 2>;
71 status = "disabled";
72 };
73 };
74
75 rtc@10300 { 79 rtc@10300 {
76 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; 80 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
77 reg = <0x10300 0x20>; 81 reg = <0x10300 0x20>;
diff --git a/arch/arm/boot/dts/kirkwood-6282.dtsi b/arch/arm/boot/dts/kirkwood-6282.dtsi
index a63a11137262..3933a331ddc2 100644
--- a/arch/arm/boot/dts/kirkwood-6282.dtsi
+++ b/arch/arm/boot/dts/kirkwood-6282.dtsi
@@ -1,4 +1,59 @@
1/ { 1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
16 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
17 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
18 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
19 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1.0 MEM */
20 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1.0 IO */>;
21
22 pcie@1,0 {
23 device_type = "pci";
24 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
25 reg = <0x0800 0 0 0 0>;
26 #address-cells = <3>;
27 #size-cells = <2>;
28 #interrupt-cells = <1>;
29 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
30 0x81000000 0 0 0x81000000 0x1 0 1 0>;
31 interrupt-map-mask = <0 0 0 0>;
32 interrupt-map = <0 0 0 0 &intc 9>;
33 marvell,pcie-port = <0>;
34 marvell,pcie-lane = <0>;
35 clocks = <&gate_clk 2>;
36 status = "disabled";
37 };
38
39 pcie@2,0 {
40 device_type = "pci";
41 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
42 reg = <0x1000 0 0 0 0>;
43 #address-cells = <3>;
44 #size-cells = <2>;
45 #interrupt-cells = <1>;
46 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
47 0x81000000 0 0 0x81000000 0x2 0 1 0>;
48 interrupt-map-mask = <0 0 0 0>;
49 interrupt-map = <0 0 0 0 &intc 10>;
50 marvell,pcie-port = <1>;
51 marvell,pcie-lane = <0>;
52 clocks = <&gate_clk 18>;
53 status = "disabled";
54 };
55 };
56 };
2 ocp@f1000000 { 57 ocp@f1000000 {
3 58
4 pinctrl: pinctrl@10000 { 59 pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@
94 status = "disabled"; 149 status = "disabled";
95 }; 150 };
96 151
97 pcie-controller {
98 compatible = "marvell,kirkwood-pcie";
99 status = "disabled";
100 device_type = "pci";
101
102 #address-cells = <3>;
103 #size-cells = <2>;
104
105 bus-range = <0x00 0xff>;
106
107 ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000 /* Port 0.0 registers */
108 0x82000000 0 0x00044000 0x00044000 0 0x00002000 /* Port 1.0 registers */
109 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000 /* non-prefetchable memory */
110 0x81000000 0 0 0xe8000000 0 0x00100000>; /* downstream I/O */
111
112 pcie@1,0 {
113 device_type = "pci";
114 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
115 reg = <0x0800 0 0 0 0>;
116 #address-cells = <3>;
117 #size-cells = <2>;
118 #interrupt-cells = <1>;
119 ranges;
120 interrupt-map-mask = <0 0 0 0>;
121 interrupt-map = <0 0 0 0 &intc 9>;
122 marvell,pcie-port = <0>;
123 marvell,pcie-lane = <0>;
124 clocks = <&gate_clk 2>;
125 status = "disabled";
126 };
127
128 pcie@2,0 {
129 device_type = "pci";
130 assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;
131 reg = <0x1000 0 0 0 0>;
132 #address-cells = <3>;
133 #size-cells = <2>;
134 #interrupt-cells = <1>;
135 ranges;
136 interrupt-map-mask = <0 0 0 0>;
137 interrupt-map = <0 0 0 0 &intc 10>;
138 marvell,pcie-port = <1>;
139 marvell,pcie-lane = <0>;
140 clocks = <&gate_clk 18>;
141 status = "disabled";
142 };
143 };
144 }; 152 };
145}; 153};
diff --git a/arch/arm/boot/dts/kirkwood-cloudbox.dts b/arch/arm/boot/dts/kirkwood-cloudbox.dts
index 00c48d26de68..142b9cd3b454 100644
--- a/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ b/arch/arm/boot/dts/kirkwood-cloudbox.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "LaCie CloudBox"; 7 model = "LaCie CloudBox";
@@ -89,3 +89,19 @@
89 gpios = <&gpio0 17 0>; 89 gpios = <&gpio0 17 0>;
90 }; 90 };
91}; 91};
92
93&mdio {
94 status = "okay";
95
96 ethphy0: ethernet-phy@0 {
97 device_type = "ethernet-phy";
98 reg = <0>;
99 };
100};
101
102&eth0 {
103 status = "okay";
104 ethernet0-port@0 {
105 phy-handle = <&ethphy0>;
106 };
107};
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6281.dts b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
index 9d777edd1f36..72c4b0a0366f 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6281.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6281.dts
@@ -11,14 +11,15 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "kirkwood-db.dtsi" 14#include "kirkwood-db.dtsi"
15/include/ "kirkwood-6281.dtsi" 15#include "kirkwood-6281.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell DB-88F6281-BP Development Board"; 18 model = "Marvell DB-88F6281-BP Development Board";
19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";
20 20
21 ocp@f1000000 { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
22 pcie-controller { 23 pcie-controller {
23 status = "okay"; 24 status = "okay";
24 25
diff --git a/arch/arm/boot/dts/kirkwood-db-88f6282.dts b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
index f4c852886d23..36c411d34926 100644
--- a/arch/arm/boot/dts/kirkwood-db-88f6282.dts
+++ b/arch/arm/boot/dts/kirkwood-db-88f6282.dts
@@ -11,14 +11,15 @@
11 11
12/dts-v1/; 12/dts-v1/;
13 13
14/include/ "kirkwood-db.dtsi" 14#include "kirkwood-db.dtsi"
15/include/ "kirkwood-6282.dtsi" 15#include "kirkwood-6282.dtsi"
16 16
17/ { 17/ {
18 model = "Marvell DB-88F6282-BP Development Board"; 18 model = "Marvell DB-88F6282-BP Development Board";
19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood"; 19 compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";
20 20
21 ocp@f1000000 { 21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
22 pcie-controller { 23 pcie-controller {
23 status = "okay"; 24 status = "okay";
24 25
diff --git a/arch/arm/boot/dts/kirkwood-db.dtsi b/arch/arm/boot/dts/kirkwood-db.dtsi
index c87cfb816120..c0e2a5879174 100644
--- a/arch/arm/boot/dts/kirkwood-db.dtsi
+++ b/arch/arm/boot/dts/kirkwood-db.dtsi
@@ -12,7 +12,7 @@
12 * and 6282 variants of the Marvell Kirkwood Development Board. 12 * and 6282 variants of the Marvell Kirkwood Development Board.
13 */ 13 */
14 14
15/include/ "kirkwood.dtsi" 15#include "kirkwood.dtsi"
16 16
17/ { 17/ {
18 memory { 18 memory {
@@ -77,13 +77,21 @@
77 cd-gpios = <&gpio1 6 0>; 77 cd-gpios = <&gpio1 6 0>;
78 status = "okay"; 78 status = "okay";
79 }; 79 };
80 };
81};
80 82
81 pcie-controller { 83&mdio {
82 status = "okay"; 84 status = "okay";
83 85
84 pcie@1,0 { 86 ethphy0: ethernet-phy@8 {
85 status = "okay"; 87 device_type = "ethernet-phy";
86 }; 88 reg = <8>;
87 }; 89 };
90};
91
92&eth0 {
93 status = "okay";
94 ethernet0-port@0 {
95 phy-handle = <&ethphy0>;
88 }; 96 };
89}; 97};
diff --git a/arch/arm/boot/dts/kirkwood-dns320.dts b/arch/arm/boot/dts/kirkwood-dns320.dts
index 14d4ceea3057..e112ca62d978 100644
--- a/arch/arm/boot/dts/kirkwood-dns320.dts
+++ b/arch/arm/boot/dts/kirkwood-dns320.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-dnskw.dtsi" 3#include "kirkwood-dnskw.dtsi"
4 4
5/ { 5/ {
6 model = "D-Link DNS-320 NAS (Rev A1)"; 6 model = "D-Link DNS-320 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dns325.dts b/arch/arm/boot/dts/kirkwood-dns325.dts
index 63872570e6ce..5119fb8a8eb6 100644
--- a/arch/arm/boot/dts/kirkwood-dns325.dts
+++ b/arch/arm/boot/dts/kirkwood-dns325.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-dnskw.dtsi" 3#include "kirkwood-dnskw.dtsi"
4 4
5/ { 5/ {
6 model = "D-Link DNS-325 NAS (Rev A1)"; 6 model = "D-Link DNS-325 NAS (Rev A1)";
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 0afe1d07c803..d544f77a4ca4 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 model = "D-Link DNS NASes (kirkwood-based)"; 5 model = "D-Link DNS NASes (kirkwood-based)";
@@ -219,3 +219,19 @@
219 }; 219 };
220 }; 220 };
221}; 221};
222
223&mdio {
224 status = "okay";
225
226 ethphy0: ethernet-phy@8 {
227 device_type = "ethernet-phy";
228 reg = <8>;
229 };
230};
231
232&eth0 {
233 status = "okay";
234 ethernet0-port@0 {
235 phy-handle = <&ethphy0>;
236 };
237};
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
index 7714742bb8d8..59a2117c35a7 100644
--- a/arch/arm/boot/dts/kirkwood-dockstar.dts
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Seagate FreeAgent Dockstar"; 7 model = "Seagate FreeAgent Dockstar";
@@ -90,3 +90,20 @@
90 }; 90 };
91 }; 91 };
92}; 92};
93
94&mdio {
95 status = "okay";
96
97 ethphy0: ethernet-phy@0 {
98 device_type = "ethernet-phy";
99 compatible = "marvell,88e1116";
100 reg = <0>;
101 };
102};
103
104&eth0 {
105 status = "okay";
106 ethernet0-port@0 {
107 phy-handle = <&ethphy0>;
108 };
109};
diff --git a/arch/arm/boot/dts/kirkwood-dreamplug.dts b/arch/arm/boot/dts/kirkwood-dreamplug.dts
index 36c7ba38d500..6f62af99c9cb 100644
--- a/arch/arm/boot/dts/kirkwood-dreamplug.dts
+++ b/arch/arm/boot/dts/kirkwood-dreamplug.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Globalscale Technologies Dreamplug"; 7 model = "Globalscale Technologies Dreamplug";
@@ -99,3 +99,31 @@
99 }; 99 };
100 }; 100 };
101}; 101};
102
103&mdio {
104 status = "okay";
105
106 ethphy0: ethernet-phy@0 {
107 device_type = "ethernet-phy";
108 reg = <0>;
109 };
110
111 ethphy1: ethernet-phy@1 {
112 device_type = "ethernet-phy";
113 reg = <1>;
114 };
115};
116
117&eth0 {
118 status = "okay";
119 ethernet0-port@0 {
120 phy-handle = <&ethphy0>;
121 };
122};
123
124&eth1 {
125 status = "okay";
126 ethernet1-port@0 {
127 phy-handle = <&ethphy1>;
128 };
129};
diff --git a/arch/arm/boot/dts/kirkwood-goflexnet.dts b/arch/arm/boot/dts/kirkwood-goflexnet.dts
index 31caa6405065..6f7c7d7ecf2a 100644
--- a/arch/arm/boot/dts/kirkwood-goflexnet.dts
+++ b/arch/arm/boot/dts/kirkwood-goflexnet.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Seagate GoFlex Net"; 7 model = "Seagate GoFlex Net";
@@ -170,3 +170,19 @@
170 }; 170 };
171 }; 171 };
172}; 172};
173
174&mdio {
175 status = "okay";
176
177 ethphy0: ethernet-phy@0 {
178 device_type = "ethernet-phy";
179 reg = <0>;
180 };
181};
182
183&eth0 {
184 status = "okay";
185 ethernet0-port@0 {
186 phy-handle = <&ethphy0>;
187 };
188};
diff --git a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
index 1e642f39b154..6548b9dc6855 100644
--- a/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
+++ b/arch/arm/boot/dts/kirkwood-guruplug-server-plus.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Globalscale Technologies Guruplug Server Plus"; 7 model = "Globalscale Technologies Guruplug Server Plus";
@@ -96,3 +96,33 @@
96 }; 96 };
97 }; 97 };
98}; 98};
99
100&mdio {
101 status = "okay";
102
103 ethphy0: ethernet-phy@0 {
104 device_type = "ethernet-phy";
105 compatible = "marvell,88e1121";
106 reg = <0>;
107 };
108
109 ethphy1: ethernet-phy@1 {
110 device_type = "ethernet-phy";
111 compatible = "marvell,88e1121";
112 reg = <1>;
113 };
114};
115
116&eth0 {
117 status = "okay";
118 ethernet0-port@0 {
119 phy-handle = <&ethphy0>;
120 };
121};
122
123&eth1 {
124 status = "okay";
125 ethernet1-port@0 {
126 phy-handle = <&ethphy1>;
127 };
128};
diff --git a/arch/arm/boot/dts/kirkwood-ib62x0.dts b/arch/arm/boot/dts/kirkwood-ib62x0.dts
index 20c4b081f420..cb711a3bd983 100644
--- a/arch/arm/boot/dts/kirkwood-ib62x0.dts
+++ b/arch/arm/boot/dts/kirkwood-ib62x0.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)"; 7 model = "RaidSonic ICY BOX IB-NAS62x0 (Rev B)";
@@ -122,3 +122,19 @@
122 122
123 123
124}; 124};
125
126&mdio {
127 status = "okay";
128
129 ethphy0: ethernet-phy@8 {
130 device_type = "ethernet-phy";
131 reg = <8>;
132 };
133};
134
135&eth0 {
136 status = "okay";
137 ethernet0-port@0 {
138 phy-handle = <&ethphy0>;
139 };
140};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index 441204e8abc6..0323f017eeed 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Iomega Iconnect"; 7 model = "Iomega Iconnect";
@@ -18,6 +18,17 @@
18 linux,initrd-end = <0x4800000>; 18 linux,initrd-end = <0x4800000>;
19 }; 19 };
20 20
21 mbus {
22 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
23 pcie-controller {
24 status = "okay";
25
26 pcie@1,0 {
27 status = "okay";
28 };
29 };
30 };
31
21 ocp@f1000000 { 32 ocp@f1000000 {
22 pinctrl: pinctrl@10000 { 33 pinctrl: pinctrl@10000 {
23 pmx_button_reset: pmx-button-reset { 34 pmx_button_reset: pmx-button-reset {
@@ -101,14 +112,6 @@
101 reg = <0x980000 0x1f400000>; 112 reg = <0x980000 0x1f400000>;
102 }; 113 };
103 }; 114 };
104
105 pcie-controller {
106 status = "okay";
107
108 pcie@1,0 {
109 status = "okay";
110 };
111 };
112 }; 115 };
113 116
114 gpio-leds { 117 gpio-leds {
@@ -176,3 +179,19 @@
176 }; 179 };
177 }; 180 };
178}; 181};
182
183&mdio {
184 status = "okay";
185
186 ethphy0: ethernet-phy@11 {
187 device_type = "ethernet-phy";
188 reg = <11>;
189 };
190};
191
192&eth0 {
193 status = "okay";
194 ethernet0-port@0 {
195 phy-handle = <&ethphy0>;
196 };
197};
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
index 00a7bfe5e83b..df8447442b37 100644
--- a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "Iomega StorCenter ix2-200"; 7 model = "Iomega StorCenter ix2-200";
@@ -194,3 +194,27 @@
194 }; 194 };
195 }; 195 };
196}; 196};
197
198&mdio {
199 status = "okay";
200
201 ethphy1: ethernet-phy@11 {
202 device_type = "ethernet-phy";
203 reg = <11>;
204 };
205};
206
207&eth0 {
208 status = "okay";
209 ethernet0-port@0 {
210 speed = <1000>;
211 duplex = <1>;
212 };
213};
214
215&eth1 {
216 status = "okay";
217 ethernet1-port@0 {
218 phy-handle = <&ethphy1>;
219 };
220};
diff --git a/arch/arm/boot/dts/kirkwood-is2.dts b/arch/arm/boot/dts/kirkwood-is2.dts
index c3f036b86cca..da674bbd49a8 100644
--- a/arch/arm/boot/dts/kirkwood-is2.dts
+++ b/arch/arm/boot/dts/kirkwood-is2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Internet Space v2"; 6 model = "LaCie Internet Space v2";
@@ -30,3 +30,5 @@
30 }; 30 };
31 }; 31 };
32}; 32};
33
34&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
index 5d9f5ea78700..6899408482d2 100644
--- a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-98dx4122.dtsi" 4#include "kirkwood-98dx4122.dtsi"
5 5
6/ { 6/ {
7 model = "Keymile Kirkwood Reference Design"; 7 model = "Keymile Kirkwood Reference Design";
@@ -50,3 +50,19 @@
50 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 50 i2c-gpio,delay-us = <2>; /* ~100 kHz */
51 }; 51 };
52}; 52};
53
54&mdio {
55 status = "okay";
56
57 ethphy0: ethernet-phy@0 {
58 device_type = "ethernet-phy";
59 reg = <0>;
60 };
61};
62
63&eth0 {
64 status = "okay";
65 ethernet0-port@0 {
66 phy-handle = <&ethphy0>;
67 };
68};
diff --git a/arch/arm/boot/dts/kirkwood-lschlv2.dts b/arch/arm/boot/dts/kirkwood-lschlv2.dts
index 9f55d95f35f5..e2fa368aef25 100644
--- a/arch/arm/boot/dts/kirkwood-lschlv2.dts
+++ b/arch/arm/boot/dts/kirkwood-lschlv2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-lsxl.dtsi" 3#include "kirkwood-lsxl.dtsi"
4 4
5/ { 5/ {
6 model = "Buffalo Linkstation LS-CHLv2"; 6 model = "Buffalo Linkstation LS-CHLv2";
diff --git a/arch/arm/boot/dts/kirkwood-lsxhl.dts b/arch/arm/boot/dts/kirkwood-lsxhl.dts
index 5c84c118ed8d..8d89cdf8d6bf 100644
--- a/arch/arm/boot/dts/kirkwood-lsxhl.dts
+++ b/arch/arm/boot/dts/kirkwood-lsxhl.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-lsxl.dtsi" 3#include "kirkwood-lsxl.dtsi"
4 4
5/ { 5/ {
6 model = "Buffalo Linkstation LS-XHL"; 6 model = "Buffalo Linkstation LS-XHL";
diff --git a/arch/arm/boot/dts/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
index 31b17f5b9d28..4e8f9e42c592 100644
--- a/arch/arm/boot/dts/kirkwood-lsxl.dtsi
+++ b/arch/arm/boot/dts/kirkwood-lsxl.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 chosen { 5 chosen {
@@ -207,3 +207,31 @@
207 }; 207 };
208 }; 208 };
209}; 209};
210
211&mdio {
212 status = "okay";
213
214 ethphy0: ethernet-phy@0 {
215 device_type = "ethernet-phy";
216 reg = <0>;
217 };
218
219 ethphy1: ethernet-phy@8 {
220 device_type = "ethernet-phy";
221 reg = <8>;
222 };
223};
224
225&eth0 {
226 status = "okay";
227 ethernet0-port@0 {
228 phy-handle = <&ethphy0>;
229 };
230};
231
232&eth1 {
233 status = "okay";
234 ethernet1-port@0 {
235 phy-handle = <&ethphy1>;
236 };
237};
diff --git a/arch/arm/boot/dts/kirkwood-mplcec4.dts b/arch/arm/boot/dts/kirkwood-mplcec4.dts
index 6179333fd71f..ce2b94b513db 100644
--- a/arch/arm/boot/dts/kirkwood-mplcec4.dts
+++ b/arch/arm/boot/dts/kirkwood-mplcec4.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5 5
6/ { 6/ {
7 model = "MPL CEC4"; 7 model = "MPL CEC4";
@@ -16,6 +16,17 @@
16 bootargs = "console=ttyS0,115200n8 earlyprintk"; 16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 }; 17 };
18 18
19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller {
22 status = "okay";
23
24 pcie@1,0 {
25 status = "okay";
26 };
27 };
28 };
29
19 ocp@f1000000 { 30 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 31 pinctrl: pinctrl@10000 {
21 pmx_led_health: pmx-led-health { 32 pmx_led_health: pmx-led-health {
@@ -134,14 +145,6 @@
134 cd-gpios = <&gpio1 15 1>; 145 cd-gpios = <&gpio1 15 1>;
135 /* No WP GPIO */ 146 /* No WP GPIO */
136 }; 147 };
137
138 pcie-controller {
139 status = "okay";
140
141 pcie@1,0 {
142 status = "okay";
143 };
144 };
145 }; 148 };
146 149
147 gpio-leds { 150 gpio-leds {
@@ -191,3 +194,30 @@
191 }; 194 };
192}; 195};
193 196
197&mdio {
198 status = "okay";
199
200 ethphy0: ethernet-phy@1 {
201 device_type = "ethernet-phy";
202 reg = <1>;
203 };
204
205 ethphy1: ethernet-phy@2 {
206 device_type = "ethernet-phy";
207 reg = <2>;
208 };
209};
210
211&eth0 {
212 status = "okay";
213 ethernet0-port@0 {
214 phy-handle = <&ethphy0>;
215 };
216};
217
218&eth1 {
219 status = "okay";
220 ethernet1-port@0 {
221 phy-handle = <&ethphy1>;
222 };
223};
diff --git a/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
new file mode 100644
index 000000000000..6317e1d088b3
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-mv88f6281gtw-ge.dts
@@ -0,0 +1,125 @@
1/*
2 * Marvell 88F6281 GTW GE Board
3 *
4 * Lennert Buytenhek <buytenh@marvell.com>
5 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 *
11 * This file contains the definitions that are common between the 6281
12 * and 6282 variants of the Marvell Kirkwood Development Board.
13 */
14
15/dts-v1/;
16
17#include "kirkwood.dtsi"
18#include "kirkwood-6281.dtsi"
19
20/ {
21 model = "Marvell 88F6281 GTW GE Board";
22 compatible = "marvell,mv88f6281gtw-ge", "marvell,kirkwood-88f6281", "marvell,kirkwood";
23
24 memory {
25 device_type = "memory";
26 reg = <0x00000000 0x20000000>; /* 512 MB */
27 };
28
29 chosen {
30 bootargs = "console=ttyS0,115200n8 earlyprintk";
31 };
32
33 ocp@f1000000 {
34 pinctrl@10000 {
35 pmx_usb_led: pmx-usb-led {
36 marvell,pins = "mpp12";
37 marvell,function = "gpo";
38 };
39
40 pmx_leds: pmx-leds {
41 marvell,pins = "mpp20", "mpp21";
42 marvell,function = "gpio";
43 };
44
45 pmx_keys: pmx-keys {
46 marvell,pins = "mpp46", "mpp47";
47 marvell,function = "gpio";
48 };
49 };
50
51 spi@10600 {
52 pinctrl-0 = <&pmx_spi>;
53 pinctrl-names = "default";
54 status = "okay";
55
56 flash@0 {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "mx25l12805d";
60 reg = <0>;
61 spi-max-frequency = <50000000>;
62 mode = <0>;
63 };
64 };
65
66 serial@12000 {
67 pinctrl-0 = <&pmx_uart0>;
68 pinctrl-names = "default";
69 clock-frequency = <200000000>;
70 status = "ok";
71 };
72
73 ehci@50000 {
74 status = "okay";
75 };
76
77 pcie-controller {
78 status = "okay";
79
80 pcie@1,0 {
81 status = "okay";
82 };
83 };
84 };
85
86 gpio-leds {
87 compatible = "gpio-leds";
88 pinctrl-0 = <&pmx_leds &pmx_usb_led>;
89 pinctrl-names = "default";
90
91 green-status {
92 label = "gtw:green:Status";
93 gpios = <&gpio0 20 0>;
94 };
95
96 red-status {
97 label = "gtw:red:Status";
98 gpios = <&gpio0 21 0>;
99 };
100
101 green-usb {
102 label = "gtw:green:USB";
103 gpios = <&gpio0 12 0>;
104 };
105 };
106
107 gpio_keys {
108 compatible = "gpio-keys";
109 #address-cells = <1>;
110 #size-cells = <0>;
111 pinctrl-0 = <&pmx_keys>;
112 pinctrl-names = "default";
113
114 button@1 {
115 label = "SWR Button";
116 linux,code = <0x198>; /* KEY_RESTART */
117 gpios = <&gpio1 15 1>;
118 };
119 button@2 {
120 label = "WPS Button";
121 linux,code = <0x211>; /* KEY_WPS_BUTTON */
122 gpios = <&gpio1 14 1>;
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
index ad6ade7d9191..874857ea9cb8 100644
--- a/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ b/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "NETGEAR ReadyNAS Duo v2"; 7 model = "NETGEAR ReadyNAS Duo v2";
@@ -16,6 +16,17 @@
16 bootargs = "console=ttyS0,115200n8 earlyprintk"; 16 bootargs = "console=ttyS0,115200n8 earlyprintk";
17 }; 17 };
18 18
19 mbus {
20 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
21 pcie-controller {
22 status = "okay";
23
24 pcie@1,0 {
25 status = "okay";
26 };
27 };
28 };
29
19 ocp@f1000000 { 30 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 31 pinctrl: pinctrl@10000 {
21 pmx_button_power: pmx-button-power { 32 pmx_button_power: pmx-button-power {
@@ -52,6 +63,17 @@
52 }; 63 };
53 }; 64 };
54 65
66 clocks {
67 #address-cells = <1>;
68 #size-cells = <0>;
69
70 g762_clk: fixedclk {
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <8192>;
74 };
75 };
76
55 i2c@11000 { 77 i2c@11000 {
56 status = "okay"; 78 status = "okay";
57 79
@@ -59,6 +81,15 @@
59 compatible = "ricoh,rs5c372a"; 81 compatible = "ricoh,rs5c372a";
60 reg = <0x32>; 82 reg = <0x32>;
61 }; 83 };
84
85 g762: g762@3e {
86 compatible = "gmt,g762";
87 reg = <0x3e>;
88 clocks = <&g762_clk>; /* input clock */
89 fan_gear_mode = <0>;
90 fan_startv = <1>;
91 pwm_polarity = <0>;
92 };
62 }; 93 };
63 94
64 serial@12000 { 95 serial@12000 {
@@ -101,14 +132,6 @@
101 status = "okay"; 132 status = "okay";
102 nr-ports = <2>; 133 nr-ports = <2>;
103 }; 134 };
104
105 pcie-controller {
106 status = "okay";
107
108 pcie@1,0 {
109 status = "okay";
110 };
111 };
112 }; 135 };
113 136
114 gpio-leds { 137 gpio-leds {
@@ -184,3 +207,19 @@
184 }; 207 };
185 }; 208 };
186}; 209};
210
211&mdio {
212 status = "okay";
213
214 ethphy0: ethernet-phy@0 {
215 device_type = "ethernet-phy";
216 reg = <0>;
217 };
218};
219
220&eth0 {
221 status = "okay";
222 ethernet0-port@0 {
223 phy-handle = <&ethphy0>;
224 };
225};
diff --git a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
index 2afac0405816..2fcb82e20828 100644
--- a/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ns2-common.dtsi
@@ -1,5 +1,5 @@
1/include/ "kirkwood.dtsi" 1#include "kirkwood.dtsi"
2/include/ "kirkwood-6281.dtsi" 2#include "kirkwood-6281.dtsi"
3 3
4/ { 4/ {
5 chosen { 5 chosen {
@@ -84,3 +84,19 @@
84 }; 84 };
85 85
86}; 86};
87
88&mdio {
89 status = "okay";
90
91 ethphy0: ethernet-phy {
92 device_type = "ethernet-phy";
93 /* overwrite reg property in board file */
94 };
95};
96
97&eth0 {
98 status = "okay";
99 ethernet0-port@0 {
100 phy-handle = <&ethphy0>;
101 };
102};
diff --git a/arch/arm/boot/dts/kirkwood-ns2.dts b/arch/arm/boot/dts/kirkwood-ns2.dts
index b50e93d7796c..53368d1022cc 100644
--- a/arch/arm/boot/dts/kirkwood-ns2.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space v2"; 6 model = "LaCie Network Space v2";
@@ -30,3 +30,5 @@
30 }; 30 };
31 }; 31 };
32}; 32};
33
34&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2lite.dts b/arch/arm/boot/dts/kirkwood-ns2lite.dts
index af8259fe8955..279607093cdb 100644
--- a/arch/arm/boot/dts/kirkwood-ns2lite.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2lite.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space Lite v2"; 6 model = "LaCie Network Space Lite v2";
@@ -30,3 +30,5 @@
30 }; 30 };
31 }; 31 };
32}; 32};
33
34&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2max.dts b/arch/arm/boot/dts/kirkwood-ns2max.dts
index 85f24d227e17..defdc77fb550 100644
--- a/arch/arm/boot/dts/kirkwood-ns2max.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2max.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 model = "LaCie Network Space Max v2"; 6 model = "LaCie Network Space Max v2";
@@ -49,3 +49,5 @@
49 }; 49 };
50 }; 50 };
51}; 51};
52
53&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ns2mini.dts b/arch/arm/boot/dts/kirkwood-ns2mini.dts
index 329e530bffe7..adbafdd90991 100644
--- a/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -1,6 +1,6 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood-ns2-common.dtsi" 3#include "kirkwood-ns2-common.dtsi"
4 4
5/ { 5/ {
6 /* This machine is embedded in the first LaCie CloudBox product. */ 6 /* This machine is embedded in the first LaCie CloudBox product. */
@@ -50,3 +50,5 @@
50 }; 50 };
51 }; 51 };
52}; 52};
53
54&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
new file mode 100644
index 000000000000..06267a91de38
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310-common.dtsi
@@ -0,0 +1,107 @@
1#include "kirkwood.dtsi"
2#include "kirkwood-6281.dtsi"
3
4/ {
5 model = "ZyXEL NSA310";
6
7 ocp@f1000000 {
8 pinctrl: pinctrl@10000 {
9
10 pmx_usb_power_off: pmx-usb-power-off {
11 marvell,pins = "mpp21";
12 marvell,function = "gpio";
13 };
14 pmx_pwr_off: pmx-pwr-off {
15 marvell,pins = "mpp48";
16 marvell,function = "gpio";
17 };
18
19 };
20
21 serial@12000 {
22 status = "ok";
23 };
24
25 sata@80000 {
26 status = "okay";
27 nr-ports = <2>;
28 };
29
30 nand@3000000 {
31 status = "okay";
32 chip-delay = <35>;
33
34 partition@0 {
35 label = "uboot";
36 reg = <0x0000000 0x0100000>;
37 read-only;
38 };
39 partition@100000 {
40 label = "uboot_env";
41 reg = <0x0100000 0x0080000>;
42 };
43 partition@180000 {
44 label = "key_store";
45 reg = <0x0180000 0x0080000>;
46 };
47 partition@200000 {
48 label = "info";
49 reg = <0x0200000 0x0080000>;
50 };
51 partition@280000 {
52 label = "etc";
53 reg = <0x0280000 0x0a00000>;
54 };
55 partition@c80000 {
56 label = "kernel_1";
57 reg = <0x0c80000 0x0a00000>;
58 };
59 partition@1680000 {
60 label = "rootfs1";
61 reg = <0x1680000 0x2fc0000>;
62 };
63 partition@4640000 {
64 label = "kernel_2";
65 reg = <0x4640000 0x0a00000>;
66 };
67 partition@5040000 {
68 label = "rootfs2";
69 reg = <0x5040000 0x2fc0000>;
70 };
71 };
72
73 pcie-controller {
74 status = "okay";
75
76 pcie@1,0 {
77 status = "okay";
78 };
79 };
80 };
81
82 gpio_poweroff {
83 compatible = "gpio-poweroff";
84 pinctrl-0 = <&pmx_pwr_off>;
85 pinctrl-names = "default";
86 gpios = <&gpio1 16 0>;
87 };
88
89 regulators {
90 compatible = "simple-bus";
91 #address-cells = <1>;
92 #size-cells = <0>;
93 pinctrl-0 = <&pmx_usb_power_off>;
94 pinctrl-names = "default";
95
96 usb0_power_off: regulator@1 {
97 compatible = "regulator-fixed";
98 reg = <1>;
99 regulator-name = "USB Power Off";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
103 regulator-boot-on;
104 gpio = <&gpio0 21 0>;
105 };
106 };
107};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310.dts b/arch/arm/boot/dts/kirkwood-nsa310.dts
index 69003598f5fa..7aeae0c2c1f4 100644
--- a/arch/arm/boot/dts/kirkwood-nsa310.dts
+++ b/arch/arm/boot/dts/kirkwood-nsa310.dts
@@ -1,10 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood-nsa310-common.dtsi"
4/include/ "kirkwood-6281.dtsi"
5 4
6/ { 5/ {
7 model = "ZyXEL NSA310";
8 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood"; 6 compatible = "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
9 7
10 memory { 8 memory {
@@ -16,6 +14,17 @@
16 bootargs = "console=ttyS0,115200"; 14 bootargs = "console=ttyS0,115200";
17 }; 15 };
18 16
17 mbus {
18 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
19 pcie-controller {
20 status = "okay";
21
22 pcie@1,0 {
23 status = "okay";
24 };
25 };
26 };
27
19 ocp@f1000000 { 28 ocp@f1000000 {
20 pinctrl: pinctrl@10000 { 29 pinctrl: pinctrl@10000 {
21 pinctrl-0 = <&pmx_unknown>; 30 pinctrl-0 = <&pmx_unknown>;
@@ -41,11 +50,6 @@
41 marvell,function = "gpio"; 50 marvell,function = "gpio";
42 }; 51 };
43 52
44 pmx_usb_power_off: pmx-usb-power-off {
45 marvell,pins = "mpp21";
46 marvell,function = "gpio";
47 };
48
49 pmx_led_sys_green: pmx-led-sys-green { 53 pmx_led_sys_green: pmx-led-sys-green {
50 marvell,pins = "mpp28"; 54 marvell,pins = "mpp28";
51 marvell,function = "gpio"; 55 marvell,function = "gpio";
@@ -95,20 +99,6 @@
95 marvell,pins = "mpp46"; 99 marvell,pins = "mpp46";
96 marvell,function = "gpio"; 100 marvell,function = "gpio";
97 }; 101 };
98
99 pmx_pwr_off: pmx-pwr-off {
100 marvell,pins = "mpp48";
101 marvell,function = "gpio";
102 };
103 };
104
105 serial@12000 {
106 status = "ok";
107 };
108
109 sata@80000 {
110 status = "okay";
111 nr-ports = <2>;
112 }; 102 };
113 103
114 i2c@11000 { 104 i2c@11000 {
@@ -119,57 +109,6 @@
119 reg = <0x2e>; 109 reg = <0x2e>;
120 }; 110 };
121 }; 111 };
122
123 nand@3000000 {
124 status = "okay";
125 chip-delay = <35>;
126
127 partition@0 {
128 label = "uboot";
129 reg = <0x0000000 0x0100000>;
130 read-only;
131 };
132 partition@100000 {
133 label = "uboot_env";
134 reg = <0x0100000 0x0080000>;
135 };
136 partition@180000 {
137 label = "key_store";
138 reg = <0x0180000 0x0080000>;
139 };
140 partition@200000 {
141 label = "info";
142 reg = <0x0200000 0x0080000>;
143 };
144 partition@280000 {
145 label = "etc";
146 reg = <0x0280000 0x0a00000>;
147 };
148 partition@c80000 {
149 label = "kernel_1";
150 reg = <0x0c80000 0x0a00000>;
151 };
152 partition@1680000 {
153 label = "rootfs1";
154 reg = <0x1680000 0x2fc0000>;
155 };
156 partition@4640000 {
157 label = "kernel_2";
158 reg = <0x4640000 0x0a00000>;
159 };
160 partition@5040000 {
161 label = "rootfs2";
162 reg = <0x5040000 0x2fc0000>;
163 };
164 };
165
166 pcie-controller {
167 status = "okay";
168
169 pcie@1,0 {
170 status = "okay";
171 };
172 };
173 }; 112 };
174 113
175 gpio_keys { 114 gpio_keys {
@@ -246,30 +185,4 @@
246 gpios = <&gpio1 8 0>; 185 gpios = <&gpio1 8 0>;
247 }; 186 };
248 }; 187 };
249
250 gpio_poweroff {
251 compatible = "gpio-poweroff";
252 pinctrl-0 = <&pmx_pwr_off>;
253 pinctrl-names = "default";
254 gpios = <&gpio1 16 0>;
255 };
256
257 regulators {
258 compatible = "simple-bus";
259 #address-cells = <1>;
260 #size-cells = <0>;
261 pinctrl-0 = <&pmx_usb_power_off>;
262 pinctrl-names = "default";
263
264 usb0_power_off: regulator@1 {
265 compatible = "regulator-fixed";
266 reg = <1>;
267 regulator-name = "USB Power Off";
268 regulator-min-microvolt = <5000000>;
269 regulator-max-microvolt = <5000000>;
270 regulator-always-on;
271 regulator-boot-on;
272 gpio = <&gpio0 21 0>;
273 };
274 };
275}; 188};
diff --git a/arch/arm/boot/dts/kirkwood-nsa310a.dts b/arch/arm/boot/dts/kirkwood-nsa310a.dts
new file mode 100644
index 000000000000..ab0212b0e6f5
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-nsa310a.dts
@@ -0,0 +1,165 @@
1/dts-v1/;
2
3#include "kirkwood-nsa310-common.dtsi"
4
5/*
6 * There are at least two different NSA310 designs. This variant does
7 * not have the red USB Led.
8 */
9
10/ {
11 compatible = "zyxel,nsa310a", "zyxel,nsa310", "marvell,kirkwood-88f6281", "marvell,kirkwood";
12
13 memory {
14 device_type = "memory";
15 reg = <0x00000000 0x10000000>;
16 };
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 };
21
22 ocp@f1000000 {
23 pinctrl: pinctrl@10000 {
24 pinctrl-names = "default";
25
26 pmx_led_esata_green: pmx-led-esata-green {
27 marvell,pins = "mpp12";
28 marvell,function = "gpio";
29 };
30
31 pmx_led_esata_red: pmx-led-esata-red {
32 marvell,pins = "mpp13";
33 marvell,function = "gpio";
34 };
35
36 pmx_led_usb_green: pmx-led-usb-green {
37 marvell,pins = "mpp15";
38 marvell,function = "gpio";
39 };
40
41 pmx_usb_power_off: pmx-usb-power-off {
42 marvell,pins = "mpp21";
43 marvell,function = "gpio";
44 };
45
46 pmx_led_sys_green: pmx-led-sys-green {
47 marvell,pins = "mpp28";
48 marvell,function = "gpio";
49 };
50
51 pmx_led_sys_red: pmx-led-sys-red {
52 marvell,pins = "mpp29";
53 marvell,function = "gpio";
54 };
55
56 pmx_btn_reset: pmx-btn-reset {
57 marvell,pins = "mpp36";
58 marvell,function = "gpio";
59 };
60
61 pmx_btn_copy: pmx-btn-copy {
62 marvell,pins = "mpp37";
63 marvell,function = "gpio";
64 };
65
66 pmx_led_copy_green: pmx-led-copy-green {
67 marvell,pins = "mpp39";
68 marvell,function = "gpio";
69 };
70
71 pmx_led_copy_red: pmx-led-copy-red {
72 marvell,pins = "mpp40";
73 marvell,function = "gpio";
74 };
75
76 pmx_led_hdd_green: pmx-led-hdd-green {
77 marvell,pins = "mpp41";
78 marvell,function = "gpio";
79 };
80
81 pmx_led_hdd_red: pmx-led-hdd-red {
82 marvell,pins = "mpp42";
83 marvell,function = "gpio";
84 };
85
86 pmx_btn_power: pmx-btn-power {
87 marvell,pins = "mpp46";
88 marvell,function = "gpio";
89 };
90
91 };
92
93 i2c@11000 {
94 status = "okay";
95
96 lm85: lm85@2e {
97 compatible = "lm85";
98 reg = <0x2e>;
99 };
100 };
101 };
102
103 gpio_keys {
104 compatible = "gpio-keys";
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 button@1 {
109 label = "Power Button";
110 linux,code = <116>;
111 gpios = <&gpio1 14 0>;
112 };
113 button@2 {
114 label = "Copy Button";
115 linux,code = <133>;
116 gpios = <&gpio1 5 1>;
117 };
118 button@3 {
119 label = "Reset Button";
120 linux,code = <0x198>;
121 gpios = <&gpio1 4 1>;
122 };
123 };
124
125 gpio-leds {
126 compatible = "gpio-leds";
127
128 green-sys {
129 label = "nsa310:green:sys";
130 gpios = <&gpio0 28 0>;
131 };
132 red-sys {
133 label = "nsa310:red:sys";
134 gpios = <&gpio0 29 0>;
135 };
136 green-hdd {
137 label = "nsa310:green:hdd";
138 gpios = <&gpio1 9 0>;
139 };
140 red-hdd {
141 label = "nsa310:red:hdd";
142 gpios = <&gpio1 10 0>;
143 };
144 green-esata {
145 label = "nsa310:green:esata";
146 gpios = <&gpio0 12 0>;
147 };
148 red-esata {
149 label = "nsa310:red:esata";
150 gpios = <&gpio0 13 0>;
151 };
152 green-usb {
153 label = "nsa310:green:usb";
154 gpios = <&gpio0 15 0>;
155 };
156 green-copy {
157 label = "nsa310:green:copy";
158 gpios = <&gpio1 7 0>;
159 };
160 red-copy {
161 label = "nsa310:red:copy";
162 gpios = <&gpio1 8 0>;
163 };
164 };
165};
diff --git a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
index 38dc8517d777..85ccf8d8abb1 100644
--- a/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
+++ b/arch/arm/boot/dts/kirkwood-openblocks_a6.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "Plat'Home OpenBlocksA6"; 7 model = "Plat'Home OpenBlocksA6";
@@ -166,3 +166,19 @@
166 }; 166 };
167 }; 167 };
168}; 168};
169
170&mdio {
171 status = "okay";
172
173 ethphy0: ethernet-phy@0 {
174 device_type = "ethernet-phy";
175 reg = <0>;
176 };
177};
178
179&eth0 {
180 status = "okay";
181 ethernet0-port@0 {
182 phy-handle = <&ethphy0>;
183 };
184};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
index f7143f128504..5696b630b70b 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-common.dtsi
@@ -6,8 +6,8 @@
6 * Licensed under GPLv2 6 * Licensed under GPLv2
7 */ 7 */
8 8
9/include/ "kirkwood.dtsi" 9#include "kirkwood.dtsi"
10/include/ "kirkwood-6281.dtsi" 10#include "kirkwood-6281.dtsi"
11 11
12/ { 12/ {
13 memory { 13 memory {
@@ -91,3 +91,19 @@
91 }; 91 };
92 }; 92 };
93}; 93};
94
95&mdio {
96 status = "okay";
97
98 ethphy0: ethernet-phy@0 {
99 device_type = "ethernet-phy";
100 reg = <0>;
101 };
102};
103
104&eth0 {
105 status = "okay";
106 ethernet0-port@0 {
107 phy-handle = <&ethphy0>;
108 };
109};
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
index f620ce48de97..eac6a21f3b1f 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug-esata.dts
@@ -8,7 +8,7 @@
8 8
9/dts-v1/; 9/dts-v1/;
10 10
11/include/ "kirkwood-sheevaplug-common.dtsi" 11#include "kirkwood-sheevaplug-common.dtsi"
12 12
13/ { 13/ {
14 model = "Globalscale Technologies eSATA SheevaPlug"; 14 model = "Globalscale Technologies eSATA SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
index bf1dff251432..bb61918313db 100644
--- a/arch/arm/boot/dts/kirkwood-sheevaplug.dts
+++ b/arch/arm/boot/dts/kirkwood-sheevaplug.dts
@@ -8,7 +8,7 @@
8 8
9/dts-v1/; 9/dts-v1/;
10 10
11/include/ "kirkwood-sheevaplug-common.dtsi" 11#include "kirkwood-sheevaplug-common.dtsi"
12 12
13/ { 13/ {
14 model = "Globalscale Technologies SheevaPlug"; 14 model = "Globalscale Technologies SheevaPlug";
diff --git a/arch/arm/boot/dts/kirkwood-topkick.dts b/arch/arm/boot/dts/kirkwood-topkick.dts
index f2052d7bc10f..30842b4ff293 100644
--- a/arch/arm/boot/dts/kirkwood-topkick.dts
+++ b/arch/arm/boot/dts/kirkwood-topkick.dts
@@ -1,7 +1,7 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5 5
6/ { 6/ {
7 model = "Univeral Scientific Industrial Co. Topkick-1281P2"; 7 model = "Univeral Scientific Industrial Co. Topkick-1281P2";
@@ -203,3 +203,19 @@
203 }; 203 };
204 }; 204 };
205}; 205};
206
207&mdio {
208 status = "okay";
209
210 ethphy0: ethernet-phy@0 {
211 device_type = "ethernet-phy";
212 reg = <0>;
213 };
214};
215
216&eth0 {
217 status = "okay";
218 ethernet0-port@0 {
219 phy-handle = <&ethphy0>;
220 };
221};
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
index 6dd1038e4de4..f755bc1dc604 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6281.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6281.dts
@@ -1,8 +1,8 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6281.dtsi" 4#include "kirkwood-6281.dtsi"
5/include/ "kirkwood-ts219.dtsi" 5#include "kirkwood-ts219.dtsi"
6 6
7/ { 7/ {
8 ocp@f1000000 { 8 ocp@f1000000 {
@@ -50,4 +50,6 @@
50 gpios = <&gpio0 16 1>; 50 gpios = <&gpio0 16 1>;
51 }; 51 };
52 }; 52 };
53}; \ No newline at end of file 53};
54
55&ethphy0 { reg = <8>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
index 6fdc5ffcaae5..9efcd2dc79d3 100644
--- a/arch/arm/boot/dts/kirkwood-ts219-6282.dts
+++ b/arch/arm/boot/dts/kirkwood-ts219-6282.dts
@@ -1,10 +1,21 @@
1/dts-v1/; 1/dts-v1/;
2 2
3/include/ "kirkwood.dtsi" 3#include "kirkwood.dtsi"
4/include/ "kirkwood-6282.dtsi" 4#include "kirkwood-6282.dtsi"
5/include/ "kirkwood-ts219.dtsi" 5#include "kirkwood-ts219.dtsi"
6 6
7/ { 7/ {
8 mbus {
9 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;
10 pcie-controller {
11 status = "okay";
12
13 pcie@2,0 {
14 status = "okay";
15 };
16 };
17 };
18
8 ocp@f1000000 { 19 ocp@f1000000 {
9 pinctrl: pinctrl@10000 { 20 pinctrl: pinctrl@10000 {
10 21
@@ -30,14 +41,6 @@
30 marvell,function = "gpio"; 41 marvell,function = "gpio";
31 }; 42 };
32 }; 43 };
33 pcie-controller {
34 status = "okay";
35
36 pcie@2,0 {
37 status = "okay";
38 };
39 };
40
41 }; 44 };
42 45
43 gpio_keys { 46 gpio_keys {
@@ -58,4 +61,6 @@
58 gpios = <&gpio1 5 1>; 61 gpios = <&gpio1 5 1>;
59 }; 62 };
60 }; 63 };
61}; \ No newline at end of file 64};
65
66&ethphy0 { reg = <0>; };
diff --git a/arch/arm/boot/dts/kirkwood-ts219.dtsi b/arch/arm/boot/dts/kirkwood-ts219.dtsi
index 0c9a94cd666c..39158cf16258 100644
--- a/arch/arm/boot/dts/kirkwood-ts219.dtsi
+++ b/arch/arm/boot/dts/kirkwood-ts219.dtsi
@@ -11,6 +11,16 @@
11 bootargs = "console=ttyS0,115200n8"; 11 bootargs = "console=ttyS0,115200n8";
12 }; 12 };
13 13
14 mbus {
15 pcie-controller {
16 status = "okay";
17
18 pcie@1,0 {
19 status = "okay";
20 };
21 };
22 };
23
14 ocp@f1000000 { 24 ocp@f1000000 {
15 i2c@11000 { 25 i2c@11000 {
16 status = "okay"; 26 status = "okay";
@@ -87,12 +97,21 @@
87 status = "okay"; 97 status = "okay";
88 nr-ports = <2>; 98 nr-ports = <2>;
89 }; 99 };
90 pcie-controller { 100 };
91 status = "okay"; 101};
92 102
93 pcie@1,0 { 103&mdio {
94 status = "okay"; 104 status = "okay";
95 }; 105
96 }; 106 ethphy0: ethernet-phy {
107 device_type = "ethernet-phy";
108 /* overwrite reg property in board file */
109 };
110};
111
112&eth0 {
113 status = "okay";
114 ethernet0-port@0 {
115 phy-handle = <&ethphy0>;
97 }; 116 };
98}; 117};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index 9809fc1f105c..cf7aeaf89e9c 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -1,5 +1,7 @@
1/include/ "skeleton.dtsi" 1/include/ "skeleton.dtsi"
2 2
3#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
4
3/ { 5/ {
4 compatible = "marvell,kirkwood"; 6 compatible = "marvell,kirkwood";
5 interrupt-parent = <&intc>; 7 interrupt-parent = <&intc>;
@@ -20,23 +22,53 @@
20 gpio0 = &gpio0; 22 gpio0 = &gpio0;
21 gpio1 = &gpio1; 23 gpio1 = &gpio1;
22 }; 24 };
23 intc: interrupt-controller { 25
24 compatible = "marvell,orion-intc", "marvell,intc"; 26 mbus {
25 interrupt-controller; 27 compatible = "marvell,kirkwood-mbus", "simple-bus";
26 #interrupt-cells = <1>; 28 #address-cells = <2>;
27 reg = <0xf1020204 0x04>, 29 #size-cells = <1>;
28 <0xf1020214 0x04>; 30 controller = <&mbusc>;
31 pcie-mem-aperture = <0xe0000000 0x10000000>; /* 256 MiB memory space */
32 pcie-io-aperture = <0xf2000000 0x100000>; /* 1 MiB I/O space */
29 }; 33 };
30 34
31 ocp@f1000000 { 35 ocp@f1000000 {
32 compatible = "simple-bus"; 36 compatible = "simple-bus";
33 ranges = <0x00000000 0xf1000000 0x0100000 37 ranges = <0x00000000 0xf1000000 0x0100000
34 0xe0000000 0xe0000000 0x8100000 /* PCIE */
35 0xf4000000 0xf4000000 0x0000400 38 0xf4000000 0xf4000000 0x0000400
36 0xf5000000 0xf5000000 0x0000400>; 39 0xf5000000 0xf5000000 0x0000400>;
37 #address-cells = <1>; 40 #address-cells = <1>;
38 #size-cells = <1>; 41 #size-cells = <1>;
39 42
43 mbusc: mbus-controller@20000 {
44 compatible = "marvell,mbus-controller";
45 reg = <0x20000 0x80>, <0x1500 0x20>;
46 };
47
48 timer: timer@20300 {
49 compatible = "marvell,orion-timer";
50 reg = <0x20300 0x20>;
51 interrupt-parent = <&bridge_intc>;
52 interrupts = <1>, <2>;
53 clocks = <&core_clk 0>;
54 };
55
56 intc: main-interrupt-ctrl@20200 {
57 compatible = "marvell,orion-intc";
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 reg = <0x20200 0x10>, <0x20210 0x10>;
61 };
62
63 bridge_intc: bridge-interrupt-ctrl@20110 {
64 compatible = "marvell,orion-bridge-intc";
65 interrupt-controller;
66 #interrupt-cells = <1>;
67 reg = <0x20110 0x8>;
68 interrupts = <1>;
69 marvell,#interrupts = <6>;
70 };
71
40 core_clk: core-clocks@10030 { 72 core_clk: core-clocks@10030 {
41 compatible = "marvell,kirkwood-core-clock"; 73 compatible = "marvell,kirkwood-core-clock";
42 reg = <0x10030 0x4>; 74 reg = <0x10030 0x4>;
@@ -103,9 +135,11 @@
103 #clock-cells = <1>; 135 #clock-cells = <1>;
104 }; 136 };
105 137
106 wdt@20300 { 138 wdt: watchdog-timer@20300 {
107 compatible = "marvell,orion-wdt"; 139 compatible = "marvell,orion-wdt";
108 reg = <0x20300 0x28>; 140 reg = <0x20300 0x28>;
141 interrupt-parent = <&bridge_intc>;
142 interrupts = <3>;
109 clocks = <&gate_clk 7>; 143 clocks = <&gate_clk 7>;
110 status = "okay"; 144 status = "okay";
111 }; 145 };
@@ -192,5 +226,57 @@
192 clocks = <&gate_clk 17>; 226 clocks = <&gate_clk 17>;
193 status = "okay"; 227 status = "okay";
194 }; 228 };
229
230 mdio: mdio-bus@72004 {
231 compatible = "marvell,orion-mdio";
232 #address-cells = <1>;
233 #size-cells = <0>;
234 reg = <0x72004 0x84>;
235 interrupts = <46>;
236 clocks = <&gate_clk 0>;
237 status = "disabled";
238
239 /* add phy nodes in board file */
240 };
241
242 eth0: ethernet-controller@72000 {
243 compatible = "marvell,kirkwood-eth";
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg = <0x72000 0x4000>;
247 clocks = <&gate_clk 0>;
248 marvell,tx-checksum-limit = <1600>;
249 status = "disabled";
250
251 ethernet0-port@0 {
252 device_type = "network";
253 compatible = "marvell,kirkwood-eth-port";
254 reg = <0>;
255 interrupts = <11>;
256 /* overwrite MAC address in bootloader */
257 local-mac-address = [00 00 00 00 00 00];
258 /* set phy-handle property in board file */
259 };
260 };
261
262 eth1: ethernet-controller@76000 {
263 compatible = "marvell,kirkwood-eth";
264 #address-cells = <1>;
265 #size-cells = <0>;
266 reg = <0x76000 0x4000>;
267 clocks = <&gate_clk 19>;
268 marvell,tx-checksum-limit = <1600>;
269 status = "disabled";
270
271 ethernet1-port@0 {
272 device_type = "network";
273 compatible = "marvell,kirkwood-eth-port";
274 reg = <0>;
275 interrupts = <15>;
276 /* overwrite MAC address in bootloader */
277 local-mac-address = [00 00 00 00 00 00];
278 /* set phy-handle property in board file */
279 };
280 };
195 }; 281 };
196}; 282};
diff --git a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
index 0077fc8510b7..aed83deaa991 100644
--- a/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
+++ b/arch/arm/boot/dts/orion5x-lacie-ethernet-disk-mini-v2.dts
@@ -53,3 +53,20 @@
53 }; 53 };
54 }; 54 };
55}; 55};
56
57&mdio {
58 status = "okay";
59
60 ethphy: ethernet-phy {
61 device-type = "ethernet-phy";
62 reg = <8>;
63 };
64};
65
66&eth {
67 status = "okay";
68
69 ethernet-port@0 {
70 phy-handle = <&ethphy>;
71 };
72};
diff --git a/arch/arm/boot/dts/orion5x.dtsi b/arch/arm/boot/dts/orion5x.dtsi
index 892c64e3f1e1..e06c37e91ac6 100644
--- a/arch/arm/boot/dts/orion5x.dtsi
+++ b/arch/arm/boot/dts/orion5x.dtsi
@@ -16,11 +16,12 @@
16 aliases { 16 aliases {
17 gpio0 = &gpio0; 17 gpio0 = &gpio0;
18 }; 18 };
19
19 intc: interrupt-controller { 20 intc: interrupt-controller {
20 compatible = "marvell,orion-intc", "marvell,intc"; 21 compatible = "marvell,orion-intc";
21 interrupt-controller; 22 interrupt-controller;
22 #interrupt-cells = <1>; 23 #interrupt-cells = <1>;
23 reg = <0xf1020204 0x04>; 24 reg = <0xf1020200 0x08>;
24 }; 25 };
25 26
26 ocp@f1000000 { 27 ocp@f1000000 {
@@ -132,5 +133,34 @@
132 interrupts = <28>; 133 interrupts = <28>;
133 status = "okay"; 134 status = "okay";
134 }; 135 };
136
137 mdio: mdio-bus@72004 {
138 compatible = "marvell,orion-mdio";
139 #address-cells = <1>;
140 #size-cells = <0>;
141 reg = <0x72004 0x84>;
142 interrupts = <22>;
143 status = "disabled";
144
145 /* add phy nodes in board file */
146 };
147
148 eth: ethernet-controller@72000 {
149 compatible = "marvell,orion-eth";
150 #address-cells = <1>;
151 #size-cells = <0>;
152 reg = <0x72000 0x4000>;
153 marvell,tx-checksum-limit = <1600>;
154 status = "disabled";
155
156 ethernet-port@0 {
157 device_type = "network";
158 compatible = "marvell,orion-eth-port";
159 reg = <0>;
160 /* overwrite MAC address in bootloader */
161 local-mac-address = [00 00 00 00 00 00];
162 /* set phy-handle property in board file */
163 };
164 };
135 }; 165 };
136}; 166};
diff --git a/arch/arm/boot/dts/pxa3xx.dtsi b/arch/arm/boot/dts/pxa3xx.dtsi
index f9d92da86783..83bb0eff697b 100644
--- a/arch/arm/boot/dts/pxa3xx.dtsi
+++ b/arch/arm/boot/dts/pxa3xx.dtsi
@@ -28,5 +28,16 @@
28 marvell,intc-priority; 28 marvell,intc-priority;
29 marvell,intc-nr-irqs = <56>; 29 marvell,intc-nr-irqs = <56>;
30 }; 30 };
31
32 gpio: gpio@40e00000 {
33 compatible = "intel,pxa3xx-gpio";
34 reg = <0x40e00000 0x10000>;
35 interrupt-names = "gpio0", "gpio1", "gpio_mux";
36 interrupts = <8 9 10>;
37 gpio-controller;
38 #gpio-cells = <0x2>;
39 interrupt-controller;
40 #interrupt-cells = <0x2>;
41 };
31 }; 42 };
32}; 43};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
new file mode 100644
index 000000000000..f444624eb097
--- /dev/null
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -0,0 +1,65 @@
1/*
2 * Device Tree Source for the APE6EVM board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "r8a73a4.dtsi"
13
14/ {
15 model = "APE6EVM";
16 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
17
18 chosen {
19 bootargs = "console=ttySC0,115200 ignore_loglevel rw";
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0 0x40000000 0 0x40000000>;
25 };
26
27 lbsc {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <1>;
31 ranges = <0 0 0 0x80000000>;
32 };
33};
34
35&i2c5 {
36 vdd_dvfs: max8973@1b {
37 compatible = "maxim,max8973";
38 reg = <0x1b>;
39
40 regulator-min-microvolt = <935000>;
41 regulator-max-microvolt = <1200000>;
42 regulator-boot-on;
43 regulator-always-on;
44 };
45};
46
47&cpu0 {
48 cpu0-supply = <&vdd_dvfs>;
49 operating-points = <
50 /* kHz uV */
51 1950000 1115000
52 1462500 995000
53 >;
54 voltage-tolerance = <1>; /* 1% */
55};
56
57&pfc {
58 pinctrl-0 = <&scifa0_pins>;
59 pinctrl-names = "default";
60
61 scifa0_pins: scifa0 {
62 renesas,groups = "scifa0_data";
63 renesas,function = "scifa0";
64 };
65};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm.dts b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
index f603c6946c29..72f867e65791 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm.dts
@@ -16,7 +16,7 @@
16 compatible = "renesas,ape6evm", "renesas,r8a73a4"; 16 compatible = "renesas,ape6evm", "renesas,r8a73a4";
17 17
18 chosen { 18 chosen {
19 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp"; 19 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
20 }; 20 };
21 21
22 memory@40000000 { 22 memory@40000000 {
@@ -50,3 +50,25 @@
50 }; 50 };
51 }; 51 };
52}; 52};
53
54&i2c5 {
55 vdd_dvfs: max8973@1b {
56 compatible = "maxim,max8973";
57 reg = <0x1b>;
58
59 regulator-min-microvolt = <935000>;
60 regulator-max-microvolt = <1200000>;
61 regulator-boot-on;
62 regulator-always-on;
63 };
64};
65
66&cpu0 {
67 cpu0-supply = <&vdd_dvfs>;
68 operating-points = <
69 /* kHz uV */
70 1950000 1115000
71 1462500 995000
72 >;
73 voltage-tolerance = <1>; /* 1% */
74};
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 4ff2019c0e30..6c26caa880f2 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -85,4 +85,137 @@
85 interrupt-parent = <&gic>; 85 interrupt-parent = <&gic>;
86 interrupts = <0 69 4>; 86 interrupts = <0 69 4>;
87 }; 87 };
88
89 i2c0: i2c@e6500000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "renesas,rmobile-iic";
93 reg = <0 0xe6500000 0 0x428>;
94 interrupt-parent = <&gic>;
95 interrupts = <0 174 0x4>;
96 };
97
98 i2c1: i2c@e6510000 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 compatible = "renesas,rmobile-iic";
102 reg = <0 0xe6510000 0 0x428>;
103 interrupt-parent = <&gic>;
104 interrupts = <0 175 0x4>;
105 };
106
107 i2c2: i2c@e6520000 {
108 #address-cells = <1>;
109 #size-cells = <0>;
110 compatible = "renesas,rmobile-iic";
111 reg = <0 0xe6520000 0 0x428>;
112 interrupt-parent = <&gic>;
113 interrupts = <0 176 0x4>;
114 };
115
116 i2c3: i2c@e6530000 {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 compatible = "renesas,rmobile-iic";
120 reg = <0 0xe6530000 0 0x428>;
121 interrupt-parent = <&gic>;
122 interrupts = <0 177 0x4>;
123 };
124
125 i2c4: i2c@e6540000 {
126 #address-cells = <1>;
127 #size-cells = <0>;
128 compatible = "renesas,rmobile-iic";
129 reg = <0 0xe6540000 0 0x428>;
130 interrupt-parent = <&gic>;
131 interrupts = <0 178 0x4>;
132 };
133
134 i2c5: i2c@e60b0000 {
135 #address-cells = <1>;
136 #size-cells = <0>;
137 compatible = "renesas,rmobile-iic";
138 reg = <0 0xe60b0000 0 0x428>;
139 interrupt-parent = <&gic>;
140 interrupts = <0 179 0x4>;
141 };
142
143 i2c6: i2c@e6550000 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 compatible = "renesas,rmobile-iic";
147 reg = <0 0xe6550000 0 0x428>;
148 interrupt-parent = <&gic>;
149 interrupts = <0 184 0x4>;
150 };
151
152 i2c7: i2c@e6560000 {
153 #address-cells = <1>;
154 #size-cells = <0>;
155 compatible = "renesas,rmobile-iic";
156 reg = <0 0xe6560000 0 0x428>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 185 0x4>;
159 };
160
161 i2c8: i2c@e6570000 {
162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "renesas,rmobile-iic";
165 reg = <0 0xe6570000 0 0x428>;
166 interrupt-parent = <&gic>;
167 interrupts = <0 173 0x4>;
168 };
169
170 mmcif0: mmcif@ee200000 {
171 compatible = "renesas,sh-mmcif";
172 reg = <0 0xee200000 0 0x80>;
173 interrupt-parent = <&gic>;
174 interrupts = <0 169 0x4>;
175 reg-io-width = <4>;
176 status = "disabled";
177 };
178
179 mmcif1: mmcif@ee220000 {
180 compatible = "renesas,sh-mmcif";
181 reg = <0 0xee220000 0 0x80>;
182 interrupt-parent = <&gic>;
183 interrupts = <0 170 0x4>;
184 reg-io-width = <4>;
185 status = "disabled";
186 };
187
188 pfc: pfc@e6050000 {
189 compatible = "renesas,pfc-r8a73a4";
190 reg = <0 0xe6050000 0 0x9000>;
191 gpio-controller;
192 #gpio-cells = <2>;
193 };
194
195 sdhi0: sdhi@ee100000 {
196 compatible = "renesas,r8a73a4-sdhi";
197 reg = <0 0xee100000 0 0x100>;
198 interrupt-parent = <&gic>;
199 interrupts = <0 165 4>;
200 cap-sd-highspeed;
201 status = "disabled";
202 };
203
204 sdhi1: sdhi@ee120000 {
205 compatible = "renesas,r8a73a4-sdhi";
206 reg = <0 0xee120000 0 0x100>;
207 interrupt-parent = <&gic>;
208 interrupts = <0 166 4>;
209 cap-sd-highspeed;
210 status = "disabled";
211 };
212
213 sdhi2: sdhi@ee140000 {
214 compatible = "renesas,r8a73a4-sdhi";
215 reg = <0 0xee140000 0 0x100>;
216 interrupt-parent = <&gic>;
217 interrupts = <0 167 4>;
218 cap-sd-highspeed;
219 status = "disabled";
220 };
88}; 221};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 09ea22c26359..c638e4ab91b8 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -10,13 +10,14 @@
10 10
11/dts-v1/; 11/dts-v1/;
12/include/ "r8a7740.dtsi" 12/include/ "r8a7740.dtsi"
13#include <dt-bindings/gpio/gpio.h>
13 14
14/ { 15/ {
15 model = "armadillo 800 eva reference"; 16 model = "armadillo 800 eva reference";
16 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; 17 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
17 18
18 chosen { 19 chosen {
19 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; 20 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
20 }; 21 };
21 22
22 memory { 23 memory {
@@ -33,6 +34,21 @@
33 regulator-boot-on; 34 regulator-boot-on;
34 }; 35 };
35 36
37 leds {
38 compatible = "gpio-leds";
39 led1 {
40 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
41 };
42 led2 {
43 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
44 };
45 led3 {
46 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
47 };
48 led4 {
49 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
50 };
51 };
36}; 52};
37 53
38&i2c0 { 54&i2c0 {
@@ -41,5 +57,23 @@
41 reg = <0x55>; 57 reg = <0x55>;
42 interrupt-parent = <&irqpin1>; 58 interrupt-parent = <&irqpin1>;
43 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */ 59 interrupts = <2 0>; /* IRQ10: hwirq 2 on irqpin1 */
60 pinctrl-0 = <&st1232_pins>;
61 pinctrl-names = "default";
62 gpios = <&pfc 166 GPIO_ACTIVE_LOW>;
63 };
64};
65
66&pfc {
67 pinctrl-0 = <&scifa1_pins>;
68 pinctrl-names = "default";
69
70 scifa1_pins: scifa1 {
71 renesas,groups = "scifa1_data";
72 renesas,function = "scifa1";
73 };
74
75 st1232_pins: st1232 {
76 renesas,groups = "intc_irq10";
77 renesas,function = "intc";
44 }; 78 };
45}; 79};
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
index 93da655b2598..426cd9c3e1c4 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva.dts
@@ -16,7 +16,7 @@
16 compatible = "renesas,armadillo800eva"; 16 compatible = "renesas,armadillo800eva";
17 17
18 chosen { 18 chosen {
19 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp nfsroot=,rsize=4096,wsize=4096 rw"; 19 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
20 }; 20 };
21 21
22 memory { 22 memory {
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 24e930643821..44d3d520e01f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -32,6 +32,11 @@
32 <0xc2000000 0x1000>; 32 <0xc2000000 0x1000>;
33 }; 33 };
34 34
35 pmu {
36 compatible = "arm,cortex-a9-pmu";
37 interrupts = <0 83 4>;
38 };
39
35 /* irqpin0: IRQ0 - IRQ7 */ 40 /* irqpin0: IRQ0 - IRQ7 */
36 irqpin0: irqpin@e6900000 { 41 irqpin0: irqpin@e6900000 {
37 compatible = "renesas,intc-irqpin"; 42 compatible = "renesas,intc-irqpin";
@@ -139,4 +144,19 @@
139 0 72 0x4 144 0 72 0x4
140 0 73 0x4>; 145 0 73 0x4>;
141 }; 146 };
147
148 pfc: pfc@e6050000 {
149 compatible = "renesas,pfc-r8a7740";
150 reg = <0xe6050000 0x8000>,
151 <0xe605800c 0x20>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 };
155
156 tpu: pwm@e6600000 {
157 compatible = "renesas,tpu-r8a7740", "renesas,tpu";
158 reg = <0xe6600000 0x100>;
159 status = "disabled";
160 #pwm-cells = <3>;
161 };
142}; 162};
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
new file mode 100644
index 000000000000..9bb903a3230d
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -0,0 +1,32 @@
1/*
2 * Reference Device Tree Source for the Bock-W board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on r8a7779
8 *
9 * Copyright (C) 2013 Renesas Solutions Corp.
10 * Copyright (C) 2013 Simon Horman
11 *
12 * This file is licensed under the terms of the GNU General Public License
13 * version 2. This program is licensed "as is" without any warranty of any
14 * kind, whether express or implied.
15 */
16
17/dts-v1/;
18/include/ "r8a7778.dtsi"
19
20/ {
21 model = "bockw";
22 compatible = "renesas,bockw-reference", "renesas,r8a7778";
23
24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel rw";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x60000000 0x10000000>;
31 };
32};
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 0076b1e8a0fb..12bbebc9c955 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -22,7 +22,7 @@
22 compatible = "renesas,bockw", "renesas,r8a7778"; 22 compatible = "renesas,bockw", "renesas,r8a7778";
23 23
24 chosen { 24 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs"; 25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
26 }; 26 };
27 27
28 memory { 28 memory {
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 474373559bdc..45ac404ab6d8 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -32,4 +32,70 @@
32 reg = <0xfe438000 0x1000>, 32 reg = <0xfe438000 0x1000>,
33 <0xfe430000 0x100>; 33 <0xfe430000 0x100>;
34 }; 34 };
35
36 gpio0: gpio@ffc40000 {
37 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
38 reg = <0xffc40000 0x2c>;
39 interrupt-parent = <&gic>;
40 interrupts = <0 103 0x4>;
41 #gpio-cells = <2>;
42 gpio-controller;
43 gpio-ranges = <&pfc 0 0 32>;
44 #interrupt-cells = <2>;
45 interrupt-controller;
46 };
47
48 gpio1: gpio@ffc41000 {
49 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
50 reg = <0xffc41000 0x2c>;
51 interrupt-parent = <&gic>;
52 interrupts = <0 103 0x4>;
53 #gpio-cells = <2>;
54 gpio-controller;
55 gpio-ranges = <&pfc 0 32 32>;
56 #interrupt-cells = <2>;
57 interrupt-controller;
58 };
59
60 gpio2: gpio@ffc42000 {
61 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
62 reg = <0xffc42000 0x2c>;
63 interrupt-parent = <&gic>;
64 interrupts = <0 103 0x4>;
65 #gpio-cells = <2>;
66 gpio-controller;
67 gpio-ranges = <&pfc 0 64 32>;
68 #interrupt-cells = <2>;
69 interrupt-controller;
70 };
71
72 gpio3: gpio@ffc43000 {
73 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
74 reg = <0xffc43000 0x2c>;
75 interrupt-parent = <&gic>;
76 interrupts = <0 103 0x4>;
77 #gpio-cells = <2>;
78 gpio-controller;
79 gpio-ranges = <&pfc 0 96 32>;
80 #interrupt-cells = <2>;
81 interrupt-controller;
82 };
83
84 gpio4: gpio@ffc44000 {
85 compatible = "renesas,gpio-r8a7778", "renesas,gpio-rcar";
86 reg = <0xffc44000 0x2c>;
87 interrupt-parent = <&gic>;
88 interrupts = <0 103 0x4>;
89 #gpio-cells = <2>;
90 gpio-controller;
91 gpio-ranges = <&pfc 0 128 27>;
92 #interrupt-cells = <2>;
93 interrupt-controller;
94 };
95
96 pfc: pfc@fffc0000 {
97 compatible = "renesas,pfc-r8a7778";
98 reg = <0xfffc000 0x118>;
99 #gpio-range-cells = <3>;
100 };
35}; 101};
diff --git a/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
index 72be4c87cfb5..6d5508392252 100644
--- a/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ b/arch/arm/boot/dts/r8a7779-marzen-reference.dts
@@ -11,13 +11,14 @@
11 11
12/dts-v1/; 12/dts-v1/;
13/include/ "r8a7779.dtsi" 13/include/ "r8a7779.dtsi"
14#include <dt-bindings/gpio/gpio.h>
14 15
15/ { 16/ {
16 model = "marzen"; 17 model = "marzen";
17 compatible = "renesas,marzen-reference", "renesas,r8a7779"; 18 compatible = "renesas,marzen-reference", "renesas,r8a7779";
18 19
19 chosen { 20 chosen {
20 bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"; 21 bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on rw";
21 }; 22 };
22 23
23 memory { 24 memory {
@@ -37,6 +38,9 @@
37 lan0@18000000 { 38 lan0@18000000 {
38 compatible = "smsc,lan9220", "smsc,lan9115"; 39 compatible = "smsc,lan9220", "smsc,lan9115";
39 reg = <0x18000000 0x100>; 40 reg = <0x18000000 0x100>;
41 pinctrl-0 = <&lan0_pins>;
42 pinctrl-names = "default";
43
40 phy-mode = "mii"; 44 phy-mode = "mii";
41 interrupt-parent = <&gic>; 45 interrupt-parent = <&gic>;
42 interrupts = <0 28 0x4>; 46 interrupts = <0 28 0x4>;
@@ -44,4 +48,49 @@
44 vddvario-supply = <&fixedregulator3v3>; 48 vddvario-supply = <&fixedregulator3v3>;
45 vdd33a-supply = <&fixedregulator3v3>; 49 vdd33a-supply = <&fixedregulator3v3>;
46 }; 50 };
51
52 leds {
53 compatible = "gpio-leds";
54 led2 {
55 gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
56 };
57 led3 {
58 gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
59 };
60 led4 {
61 gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
62 };
63 };
64};
65
66&pfc {
67 pinctrl-0 = <&scif2_pins &scif4_pins &sdhi0_pins>;
68 pinctrl-names = "default";
69
70 lan0_pins: lan0 {
71 intc {
72 renesas,groups = "intc_irq1_b";
73 renesas,function = "intc";
74 };
75 lbsc {
76 renesas,groups = "lbsc_ex_cs0";
77 renesas,function = "lbsc";
78 };
79 };
80
81 scif2_pins: scif2 {
82 renesas,groups = "scif2_data_c";
83 renesas,function = "scif2";
84 };
85
86 scif4_pins: scif4 {
87 renesas,groups = "scif4_data";
88 renesas,function = "scif4";
89 };
90
91 sdhi0_pins: sdhi0 {
92 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd",
93 "sdhi0_wp";
94 renesas,function = "sdhi0";
95 };
47}; 96};
diff --git a/arch/arm/boot/dts/r8a7779-marzen.dts b/arch/arm/boot/dts/r8a7779-marzen.dts
new file mode 100644
index 000000000000..f3f7f7999736
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7779-marzen.dts
@@ -0,0 +1,27 @@
1/*
2 * Device Tree Source for the Marzen board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
12/dts-v1/;
13/include/ "r8a7779.dtsi"
14
15/ {
16 model = "marzen";
17 compatible = "renesas,marzen", "renesas,r8a7779";
18
19 chosen {
20 bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x60000000 0x40000000>;
26 };
27};
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 7f146c6bf756..23a62447359c 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -48,6 +48,90 @@
48 <0xf0000100 0x100>; 48 <0xf0000100 0x100>;
49 }; 49 };
50 50
51 gpio0: gpio@ffc40000 {
52 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
53 reg = <0xffc40000 0x2c>;
54 interrupt-parent = <&gic>;
55 interrupts = <0 141 0x4>;
56 #gpio-cells = <2>;
57 gpio-controller;
58 gpio-ranges = <&pfc 0 0 32>;
59 #interrupt-cells = <2>;
60 interrupt-controller;
61 };
62
63 gpio1: gpio@ffc41000 {
64 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
65 reg = <0xffc41000 0x2c>;
66 interrupt-parent = <&gic>;
67 interrupts = <0 142 0x4>;
68 #gpio-cells = <2>;
69 gpio-controller;
70 gpio-ranges = <&pfc 0 32 32>;
71 #interrupt-cells = <2>;
72 interrupt-controller;
73 };
74
75 gpio2: gpio@ffc42000 {
76 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
77 reg = <0xffc42000 0x2c>;
78 interrupt-parent = <&gic>;
79 interrupts = <0 143 0x4>;
80 #gpio-cells = <2>;
81 gpio-controller;
82 gpio-ranges = <&pfc 0 64 32>;
83 #interrupt-cells = <2>;
84 interrupt-controller;
85 };
86
87 gpio3: gpio@ffc43000 {
88 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
89 reg = <0xffc43000 0x2c>;
90 interrupt-parent = <&gic>;
91 interrupts = <0 144 0x4>;
92 #gpio-cells = <2>;
93 gpio-controller;
94 gpio-ranges = <&pfc 0 96 32>;
95 #interrupt-cells = <2>;
96 interrupt-controller;
97 };
98
99 gpio4: gpio@ffc44000 {
100 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
101 reg = <0xffc44000 0x2c>;
102 interrupt-parent = <&gic>;
103 interrupts = <0 145 0x4>;
104 #gpio-cells = <2>;
105 gpio-controller;
106 gpio-ranges = <&pfc 0 128 32>;
107 #interrupt-cells = <2>;
108 interrupt-controller;
109 };
110
111 gpio5: gpio@ffc45000 {
112 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
113 reg = <0xffc45000 0x2c>;
114 interrupt-parent = <&gic>;
115 interrupts = <0 146 0x4>;
116 #gpio-cells = <2>;
117 gpio-controller;
118 gpio-ranges = <&pfc 0 160 32>;
119 #interrupt-cells = <2>;
120 interrupt-controller;
121 };
122
123 gpio6: gpio@ffc46000 {
124 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
125 reg = <0xffc46000 0x2c>;
126 interrupt-parent = <&gic>;
127 interrupts = <0 147 0x4>;
128 #gpio-cells = <2>;
129 gpio-controller;
130 gpio-ranges = <&pfc 0 192 9>;
131 #interrupt-cells = <2>;
132 interrupt-controller;
133 };
134
51 irqpin0: irqpin@fe780010 { 135 irqpin0: irqpin@fe780010 {
52 compatible = "renesas,intc-irqpin"; 136 compatible = "renesas,intc-irqpin";
53 #interrupt-cells = <2>; 137 #interrupt-cells = <2>;
@@ -65,7 +149,7 @@
65 sense-bitfield-width = <2>; 149 sense-bitfield-width = <2>;
66 }; 150 };
67 151
68 i2c0: i2c@0xffc70000 { 152 i2c0: i2c@ffc70000 {
69 #address-cells = <1>; 153 #address-cells = <1>;
70 #size-cells = <0>; 154 #size-cells = <0>;
71 compatible = "renesas,rmobile-iic"; 155 compatible = "renesas,rmobile-iic";
@@ -74,7 +158,7 @@
74 interrupts = <0 79 0x4>; 158 interrupts = <0 79 0x4>;
75 }; 159 };
76 160
77 i2c1: i2c@0xffc71000 { 161 i2c1: i2c@ffc71000 {
78 #address-cells = <1>; 162 #address-cells = <1>;
79 #size-cells = <0>; 163 #size-cells = <0>;
80 compatible = "renesas,rmobile-iic"; 164 compatible = "renesas,rmobile-iic";
@@ -83,7 +167,7 @@
83 interrupts = <0 82 0x4>; 167 interrupts = <0 82 0x4>;
84 }; 168 };
85 169
86 i2c2: i2c@0xffc72000 { 170 i2c2: i2c@ffc72000 {
87 #address-cells = <1>; 171 #address-cells = <1>;
88 #size-cells = <0>; 172 #size-cells = <0>;
89 compatible = "renesas,rmobile-iic"; 173 compatible = "renesas,rmobile-iic";
@@ -92,7 +176,7 @@
92 interrupts = <0 80 0x4>; 176 interrupts = <0 80 0x4>;
93 }; 177 };
94 178
95 i2c3: i2c@0xffc73000 { 179 i2c3: i2c@ffc73000 {
96 #address-cells = <1>; 180 #address-cells = <1>;
97 #size-cells = <0>; 181 #size-cells = <0>;
98 compatible = "renesas,rmobile-iic"; 182 compatible = "renesas,rmobile-iic";
@@ -101,6 +185,12 @@
101 interrupts = <0 81 0x4>; 185 interrupts = <0 81 0x4>;
102 }; 186 };
103 187
188 pfc: pfc@fffc0000 {
189 compatible = "renesas,pfc-r8a7779";
190 reg = <0xfffc0000 0x23c>;
191 #gpio-range-cells = <3>;
192 };
193
104 thermal@ffc48000 { 194 thermal@ffc48000 {
105 compatible = "renesas,rcar-thermal"; 195 compatible = "renesas,rcar-thermal";
106 reg = <0xffc48000 0x38>; 196 reg = <0xffc48000 0x38>;
diff --git a/arch/arm/boot/dts/r8a7790-lager-reference.dts b/arch/arm/boot/dts/r8a7790-lager-reference.dts
new file mode 100644
index 000000000000..c462ef138922
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7790-lager-reference.dts
@@ -0,0 +1,45 @@
1/*
2 * Device Tree Source for the Lager board
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12/include/ "r8a7790.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14
15/ {
16 model = "Lager";
17 compatible = "renesas,lager-reference", "renesas,r8a7790";
18
19 chosen {
20 bootargs = "console=ttySC6,115200 ignore_loglevel rw";
21 };
22
23 memory@40000000 {
24 device_type = "memory";
25 reg = <0 0x40000000 0 0x80000000>;
26 };
27
28 lbsc {
29 #address-cells = <1>;
30 #size-cells = <1>;
31 };
32
33 leds {
34 compatible = "gpio-leds";
35 led6 {
36 gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
37 };
38 led7 {
39 gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
40 };
41 led8 {
42 gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
43 };
44 };
45};
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 09a84fce89d6..203bd089af29 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -16,7 +16,7 @@
16 compatible = "renesas,lager", "renesas,r8a7790"; 16 compatible = "renesas,lager", "renesas,r8a7790";
17 17
18 chosen { 18 chosen {
19 bootargs = "console=ttySC6,115200 ignore_loglevel"; 19 bootargs = "console=ttySC6,115200 ignore_loglevel rw root=/dev/nfs ip=dhcp";
20 }; 20 };
21 21
22 memory@40000000 { 22 memory@40000000 {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 339d9b11721c..3b879e7c697c 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -38,6 +38,78 @@
38 interrupts = <1 9 0xf04>; 38 interrupts = <1 9 0xf04>;
39 }; 39 };
40 40
41 gpio0: gpio@ffc40000 {
42 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
43 reg = <0 0xffc40000 0 0x2c>;
44 interrupt-parent = <&gic>;
45 interrupts = <0 4 0x4>;
46 #gpio-cells = <2>;
47 gpio-controller;
48 gpio-ranges = <&pfc 0 0 32>;
49 #interrupt-cells = <2>;
50 interrupt-controller;
51 };
52
53 gpio1: gpio@ffc41000 {
54 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
55 reg = <0 0xffc41000 0 0x2c>;
56 interrupt-parent = <&gic>;
57 interrupts = <0 5 0x4>;
58 #gpio-cells = <2>;
59 gpio-controller;
60 gpio-ranges = <&pfc 0 32 32>;
61 #interrupt-cells = <2>;
62 interrupt-controller;
63 };
64
65 gpio2: gpio@ffc42000 {
66 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
67 reg = <0 0xffc42000 0 0x2c>;
68 interrupt-parent = <&gic>;
69 interrupts = <0 6 0x4>;
70 #gpio-cells = <2>;
71 gpio-controller;
72 gpio-ranges = <&pfc 0 64 32>;
73 #interrupt-cells = <2>;
74 interrupt-controller;
75 };
76
77 gpio3: gpio@ffc43000 {
78 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
79 reg = <0 0xffc43000 0 0x2c>;
80 interrupt-parent = <&gic>;
81 interrupts = <0 7 0x4>;
82 #gpio-cells = <2>;
83 gpio-controller;
84 gpio-ranges = <&pfc 0 96 32>;
85 #interrupt-cells = <2>;
86 interrupt-controller;
87 };
88
89 gpio4: gpio@ffc44000 {
90 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
91 reg = <0 0xffc44000 0 0x2c>;
92 interrupt-parent = <&gic>;
93 interrupts = <0 8 0x4>;
94 #gpio-cells = <2>;
95 gpio-controller;
96 gpio-ranges = <&pfc 0 128 32>;
97 #interrupt-cells = <2>;
98 interrupt-controller;
99 };
100
101 gpio5: gpio@ffc45000 {
102 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
103 reg = <0 0xffc45000 0 0x2c>;
104 interrupt-parent = <&gic>;
105 interrupts = <0 9 0x4>;
106 #gpio-cells = <2>;
107 gpio-controller;
108 gpio-ranges = <&pfc 0 160 32>;
109 #interrupt-cells = <2>;
110 interrupt-controller;
111 };
112
41 timer { 113 timer {
42 compatible = "arm,armv7-timer"; 114 compatible = "arm,armv7-timer";
43 interrupts = <1 13 0xf08>, 115 interrupts = <1 13 0xf08>,
@@ -54,4 +126,64 @@
54 interrupt-parent = <&gic>; 126 interrupt-parent = <&gic>;
55 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; 127 interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>;
56 }; 128 };
129
130 mmcif0: mmcif@ee200000 {
131 compatible = "renesas,sh-mmcif";
132 reg = <0 0xee200000 0 0x80>;
133 interrupt-parent = <&gic>;
134 interrupts = <0 169 0x4>;
135 reg-io-width = <4>;
136 status = "disabled";
137 };
138
139 mmcif1: mmcif@ee220000 {
140 compatible = "renesas,sh-mmcif";
141 reg = <0 0xee220000 0 0x80>;
142 interrupt-parent = <&gic>;
143 interrupts = <0 170 0x4>;
144 reg-io-width = <4>;
145 status = "disabled";
146 };
147
148 pfc: pfc@e6060000 {
149 compatible = "renesas,pfc-r8a7790";
150 reg = <0 0xe6060000 0 0x250>;
151 #gpio-range-cells = <3>;
152 };
153
154 sdhi0: sdhi@ee100000 {
155 compatible = "renesas,r8a7790-sdhi";
156 reg = <0 0xee100000 0 0x100>;
157 interrupt-parent = <&gic>;
158 interrupts = <0 165 4>;
159 cap-sd-highspeed;
160 status = "disabled";
161 };
162
163 sdhi1: sdhi@ee120000 {
164 compatible = "renesas,r8a7790-sdhi";
165 reg = <0 0xee120000 0 0x100>;
166 interrupt-parent = <&gic>;
167 interrupts = <0 166 4>;
168 cap-sd-highspeed;
169 status = "disabled";
170 };
171
172 sdhi2: sdhi@ee140000 {
173 compatible = "renesas,r8a7790-sdhi";
174 reg = <0 0xee140000 0 0x100>;
175 interrupt-parent = <&gic>;
176 interrupts = <0 167 4>;
177 cap-sd-highspeed;
178 status = "disabled";
179 };
180
181 sdhi3: sdhi@ee160000 {
182 compatible = "renesas,r8a7790-sdhi";
183 reg = <0 0xee160000 0 0x100>;
184 interrupt-parent = <&gic>;
185 interrupts = <0 168 4>;
186 cap-sd-highspeed;
187 status = "disabled";
188 };
57}; 189};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index a1d5e25a6698..b7f49615120d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -48,6 +48,11 @@
48 }; 48 };
49 }; 49 };
50 50
51 pmu {
52 compatible = "arm,cortex-a5-pmu";
53 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
54 };
55
51 memory { 56 memory {
52 reg = <0x20000000 0x8000000>; 57 reg = <0x20000000 0x8000000>;
53 }; 58 };
@@ -1029,21 +1034,30 @@
1029 compatible = "atmel,at91rm9200-nand"; 1034 compatible = "atmel,at91rm9200-nand";
1030 #address-cells = <1>; 1035 #address-cells = <1>;
1031 #size-cells = <1>; 1036 #size-cells = <1>;
1037 ranges;
1032 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1038 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1033 0xffffc070 0x00000490 /* SMC PMECC regs */ 1039 0xffffc070 0x00000490 /* SMC PMECC regs */
1034 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1040 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1035 0x00100000 0x00100000 /* ROM code */ 1041 0x00110000 0x00018000 /* ROM code */
1036 0x70000000 0x10000000 /* NFC Command Registers */
1037 0xffffc000 0x00000070 /* NFC HSMC regs */
1038 0x00200000 0x00100000 /* NFC SRAM banks */
1039 >; 1042 >;
1040 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1043 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1041 atmel,nand-addr-offset = <21>; 1044 atmel,nand-addr-offset = <21>;
1042 atmel,nand-cmd-offset = <22>; 1045 atmel,nand-cmd-offset = <22>;
1043 pinctrl-names = "default"; 1046 pinctrl-names = "default";
1044 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1047 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1045 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; 1048 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1046 status = "disabled"; 1049 status = "disabled";
1050
1051 nfc@70000000 {
1052 compatible = "atmel,sama5d3-nfc";
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1055 reg = <
1056 0x70000000 0x10000000 /* NFC Command Registers */
1057 0xffffc000 0x00000070 /* NFC HSMC regs */
1058 0x00200000 0x00100000 /* NFC SRAM banks */
1059 >;
1060 };
1047 }; 1061 };
1048 }; 1062 };
1049}; 1063};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8050813a54..31ed9e3bb649 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -47,8 +47,6 @@
47 atmel,has-pmecc; 47 atmel,has-pmecc;
48 atmel,pmecc-cap = <4>; 48 atmel,pmecc-cap = <4>;
49 atmel,pmecc-sector-size = <512>; 49 atmel,pmecc-sector-size = <512>;
50 atmel,has-nfc;
51 atmel,use-nfc-sram;
52 nand-on-flash-bbt; 50 nand-on-flash-bbt;
53 status = "okay"; 51 status = "okay";
54 52
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
index 7bf020ecadf5..249f65be2a50 100644
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ b/arch/arm/boot/dts/sh7372.dtsi
@@ -23,4 +23,12 @@
23 reg = <0x0>; 23 reg = <0x0>;
24 }; 24 };
25 }; 25 };
26
27 pfc: pfc@e6050000 {
28 compatible = "renesas,pfc-sh7372";
29 reg = <0xe6050000 0x8000>,
30 <0xe605801c 0x1c>;
31 gpio-controller;
32 #gpio-cells = <2>;
33 };
26}; 34};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index b6f759e830ed..212230629f27 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -13,6 +13,7 @@
13 13
14/dts-v1/; 14/dts-v1/;
15/include/ "sh73a0.dtsi" 15/include/ "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h>
16 17
17/ { 18/ {
18 model = "KZM-A9-GT"; 19 model = "KZM-A9-GT";
@@ -32,7 +33,7 @@
32 }; 33 };
33 34
34 chosen { 35 chosen {
35 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; 36 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw";
36 }; 37 };
37 38
38 memory { 39 memory {
@@ -58,6 +59,24 @@
58 regulator-boot-on; 59 regulator-boot-on;
59 }; 60 };
60 61
62 vmmc_sdhi0: regulator@2 {
63 compatible = "regulator-fixed";
64 regulator-name = "SDHI0 Vcc";
65 regulator-min-microvolt = <3300000>;
66 regulator-max-microvolt = <3300000>;
67 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
68 enable-active-high;
69 };
70
71 vmmc_sdhi2: regulator@3 {
72 compatible = "regulator-fixed";
73 regulator-name = "SDHI2 Vcc";
74 regulator-min-microvolt = <3300000>;
75 regulator-max-microvolt = <3300000>;
76 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 };
79
61 lan9220@10000000 { 80 lan9220@10000000 {
62 compatible = "smsc,lan9220", "smsc,lan9115"; 81 compatible = "smsc,lan9220", "smsc,lan9115";
63 reg = <0x10000000 0x100>; 82 reg = <0x10000000 0x100>;
@@ -70,6 +89,22 @@
70 vddvario-supply = <&reg_1p8v>; 89 vddvario-supply = <&reg_1p8v>;
71 vdd33a-supply = <&reg_3p3v>; 90 vdd33a-supply = <&reg_3p3v>;
72 }; 91 };
92
93 leds {
94 compatible = "gpio-leds";
95 led1 {
96 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
97 };
98 led2 {
99 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
100 };
101 led3 {
102 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
103 };
104 led4 {
105 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
106 };
107 };
73}; 108};
74 109
75&i2c0 { 110&i2c0 {
@@ -145,20 +180,71 @@
145 }; 180 };
146}; 181};
147 182
183&i2c3 {
184 pinctrl-0 = <&i2c3_pins>;
185 pinctrl-names = "default";
186};
187
148&mmcif { 188&mmcif {
189 pinctrl-0 = <&mmcif_pins>;
190 pinctrl-names = "default";
191
149 bus-width = <8>; 192 bus-width = <8>;
150 vmmc-supply = <&reg_1p8v>; 193 vmmc-supply = <&reg_1p8v>;
151 status = "okay"; 194 status = "okay";
152}; 195};
153 196
197&pfc {
198 pinctrl-0 = <&scifa4_pins>;
199 pinctrl-names = "default";
200
201 i2c3_pins: i2c3 {
202 renesas,groups = "i2c3_1";
203 renesas,function = "i2c3";
204 };
205
206 mmcif_pins: mmcif {
207 mux {
208 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
209 renesas,function = "mmc0";
210 };
211 cfg {
212 renesas,groups = "mmc0_data8_0";
213 renesas,pins = "PORT279";
214 bias-pull-up;
215 };
216 };
217
218 scifa4_pins: scifa4 {
219 renesas,groups = "scifa4_data", "scifa4_ctrl";
220 renesas,function = "scifa4";
221 };
222
223 sdhi0_pins: sdhi0 {
224 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
225 renesas,function = "sdhi0";
226 };
227
228 sdhi2_pins: sdhi2 {
229 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
230 renesas,function = "sdhi2";
231 };
232};
233
154&sdhi0 { 234&sdhi0 {
155 vmmc-supply = <&reg_3p3v>; 235 pinctrl-0 = <&sdhi0_pins>;
236 pinctrl-names = "default";
237
238 vmmc-supply = <&vmmc_sdhi0>;
156 bus-width = <4>; 239 bus-width = <4>;
157 status = "okay"; 240 status = "okay";
158}; 241};
159 242
160&sdhi2 { 243&sdhi2 {
161 vmmc-supply = <&reg_3p3v>; 244 pinctrl-0 = <&sdhi2_pins>;
245 pinctrl-names = "default";
246
247 vmmc-supply = <&vmmc_sdhi2>;
162 bus-width = <4>; 248 bus-width = <4>;
163 broken-cd; 249 broken-cd;
164 status = "okay"; 250 status = "okay";
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 7c4071e7790c..0f1ca7792c46 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -16,7 +16,7 @@
16 compatible = "renesas,kzm9g", "renesas,sh73a0"; 16 compatible = "renesas,kzm9g", "renesas,sh73a0";
17 17
18 chosen { 18 chosen {
19 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200"; 19 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw";
20 }; 20 };
21 21
22 memory { 22 memory {
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index b97750256003..ba59a5875a10 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -38,6 +38,12 @@
38 <0xf0000100 0x100>; 38 <0xf0000100 0x100>;
39 }; 39 };
40 40
41 pmu {
42 compatible = "arm,cortex-a9-pmu";
43 interrupts = <0 55 4>,
44 <0 56 4>;
45 };
46
41 irqpin0: irqpin@e6900000 { 47 irqpin0: irqpin@e6900000 {
42 compatible = "renesas,intc-irqpin"; 48 compatible = "renesas,intc-irqpin";
43 #interrupt-cells = <2>; 49 #interrupt-cells = <2>;
@@ -222,4 +228,12 @@
222 cap-sd-highspeed; 228 cap-sd-highspeed;
223 status = "disabled"; 229 status = "disabled";
224 }; 230 };
231
232 pfc: pfc@e6050000 {
233 compatible = "renesas,pfc-sh73a0";
234 reg = <0xe6050000 0x8000>,
235 <0xe605801c 0x1c>;
236 gpio-controller;
237 #gpio-cells = <2>;
238 };
225}; 239};
diff --git a/arch/arm/boot/dts/skeleton64.dtsi b/arch/arm/boot/dts/skeleton64.dtsi
index 15994158a998..b5d7f36f33de 100644
--- a/arch/arm/boot/dts/skeleton64.dtsi
+++ b/arch/arm/boot/dts/skeleton64.dtsi
@@ -9,5 +9,5 @@
9 #size-cells = <2>; 9 #size-cells = <2>;
10 chosen { }; 10 chosen { };
11 aliases { }; 11 aliases { };
12 memory { device_type = "memory"; reg = <0 0>; }; 12 memory { device_type = "memory"; reg = <0 0 0 0>; };
13}; 13};
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index bee62a2cf6d6..e273fa993b8c 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -476,25 +476,25 @@
476 }; 476 };
477 477
478 timer0: timer0@ffc08000 { 478 timer0: timer0@ffc08000 {
479 compatible = "snps,dw-apb-timer-sp"; 479 compatible = "snps,dw-apb-timer";
480 interrupts = <0 167 4>; 480 interrupts = <0 167 4>;
481 reg = <0xffc08000 0x1000>; 481 reg = <0xffc08000 0x1000>;
482 }; 482 };
483 483
484 timer1: timer1@ffc09000 { 484 timer1: timer1@ffc09000 {
485 compatible = "snps,dw-apb-timer-sp"; 485 compatible = "snps,dw-apb-timer";
486 interrupts = <0 168 4>; 486 interrupts = <0 168 4>;
487 reg = <0xffc09000 0x1000>; 487 reg = <0xffc09000 0x1000>;
488 }; 488 };
489 489
490 timer2: timer2@ffd00000 { 490 timer2: timer2@ffd00000 {
491 compatible = "snps,dw-apb-timer-osc"; 491 compatible = "snps,dw-apb-timer";
492 interrupts = <0 169 4>; 492 interrupts = <0 169 4>;
493 reg = <0xffd00000 0x1000>; 493 reg = <0xffd00000 0x1000>;
494 }; 494 };
495 495
496 timer3: timer3@ffd01000 { 496 timer3: timer3@ffd01000 {
497 compatible = "snps,dw-apb-timer-osc"; 497 compatible = "snps,dw-apb-timer";
498 interrupts = <0 170 4>; 498 interrupts = <0 170 4>;
499 reg = <0xffd01000 0x1000>; 499 reg = <0xffd01000 0x1000>;
500 }; 500 };
diff --git a/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
new file mode 100644
index 000000000000..e0799966bc25
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
@@ -0,0 +1,196 @@
1/*
2 * Copyright 2012 ST-Ericsson
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include "ste-nomadik-pinctrl.dtsi"
12
13/ {
14 soc {
15 pinctrl {
16 uart0 {
17 uart0_default_mux: uart0_mux {
18 default_mux {
19 ste,function = "u0";
20 ste,pins = "u0_a_1";
21 };
22 };
23
24 uart0_default_mode: uart0_default {
25 default_cfg1 {
26 ste,pins = "GPIO0", "GPIO2";
27 ste,config = <&in_pu>;
28 };
29
30 default_cfg2 {
31 ste,pins = "GPIO1", "GPIO3";
32 ste,config = <&out_hi>;
33 };
34 };
35
36 uart0_sleep_mode: uart0_sleep {
37 sleep_cfg1 {
38 ste,pins = "GPIO0", "GPIO2";
39 ste,config = <&slpm_in_pu>;
40 };
41
42 sleep_cfg2 {
43 ste,pins = "GPIO1", "GPIO3";
44 ste,config = <&slpm_out_hi>;
45 };
46 };
47 };
48
49 uart2 {
50 uart2_default_mode: uart2_default {
51 default_mux {
52 ste,function = "u2";
53 ste,pins = "u2txrx_a_1";
54 };
55
56 default_cfg1 {
57 ste,pins = "GPIO120";
58 ste,config = <&in_pu>;
59 };
60
61 default_cfg2 {
62 ste,pins = "GPIO121";
63 ste,config = <&out_hi>;
64 };
65 };
66
67 uart2_sleep_mode: uart2_sleep {
68 sleep_cfg1 {
69 ste,pins = "GPIO120";
70 ste,config = <&slpm_in_pu>;
71 };
72
73 sleep_cfg2 {
74 ste,pins = "GPIO121";
75 ste,config = <&slpm_out_hi>;
76 };
77 };
78 };
79
80 i2c0 {
81 i2c0_default_mux: i2c_mux {
82 default_mux {
83 ste,function = "i2c0";
84 ste,pins = "i2c0_a_1";
85 };
86 };
87
88 i2c0_default_mode: i2c_default {
89 default_cfg1 {
90 ste,pins = "GPIO147", "GPIO148";
91 ste,config = <&in_pu>;
92 };
93 };
94
95 i2c0_sleep_mode: i2c_sleep {
96 sleep_cfg1 {
97 ste,pins = "GPIO147", "GPIO148";
98 ste,config = <&slpm_in_pu>;
99 };
100 };
101 };
102
103 i2c1 {
104 i2c1_default_mux: i2c_mux {
105 default_mux {
106 ste,function = "i2c1";
107 ste,pins = "i2c1_b_2";
108 };
109 };
110
111 i2c1_default_mode: i2c_default {
112 default_cfg1 {
113 ste,pins = "GPIO16", "GPIO17";
114 ste,config = <&in_pu>;
115 };
116 };
117
118 i2c1_sleep_mode: i2c_sleep {
119 sleep_cfg1 {
120 ste,pins = "GPIO16", "GPIO17";
121 ste,config = <&slpm_in_pu>;
122 };
123 };
124 };
125
126 i2c2 {
127 i2c2_default_mux: i2c_mux {
128 default_mux {
129 ste,function = "i2c2";
130 ste,pins = "i2c2_b_2";
131 };
132 };
133
134 i2c2_default_mode: i2c_default {
135 default_cfg1 {
136 ste,pins = "GPIO10", "GPIO11";
137 ste,config = <&in_pu>;
138 };
139 };
140
141 i2c2_sleep_mode: i2c_sleep {
142 sleep_cfg1 {
143 ste,pins = "GPIO11", "GPIO11";
144 ste,config = <&slpm_in_pu>;
145 };
146 };
147 };
148
149 i2c4 {
150 i2c4_default_mux: i2c_mux {
151 default_mux {
152 ste,function = "i2c4";
153 ste,pins = "i2c4_b_2";
154 };
155 };
156
157 i2c4_default_mode: i2c_default {
158 default_cfg1 {
159 ste,pins = "GPIO122", "GPIO123";
160 ste,config = <&in_pu>;
161 };
162 };
163
164 i2c4_sleep_mode: i2c_sleep {
165 sleep_cfg1 {
166 ste,pins = "GPIO122", "GPIO123";
167 ste,config = <&slpm_in_pu>;
168 };
169 };
170 };
171
172 i2c5 {
173 i2c5_default_mux: i2c_mux {
174 default_mux {
175 ste,function = "i2c5";
176 ste,pins = "i2c5_c_2";
177 };
178 };
179
180 i2c5_default_mode: i2c_default {
181 default_cfg1 {
182 ste,pins = "GPIO118", "GPIO119";
183 ste,config = <&in_pu>;
184 };
185 };
186
187 i2c5_sleep_mode: i2c_sleep {
188 sleep_cfg1 {
189 ste,pins = "GPIO118", "GPIO119";
190 ste,config = <&slpm_in_pu>;
191 };
192 };
193 };
194 };
195 };
196};
diff --git a/arch/arm/boot/dts/ste-ccu8540.dts b/arch/arm/boot/dts/ste-ccu8540.dts
new file mode 100644
index 000000000000..7f3baf51a3a9
--- /dev/null
+++ b/arch/arm/boot/dts/ste-ccu8540.dts
@@ -0,0 +1,86 @@
1/*
2 * Copyright 2013 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "ste-dbx5x0.dtsi"
14#include "ste-ccu8540-pinctrl.dtsi"
15
16/ {
17 model = "ST-Ericsson U8540 platform with Device Tree";
18 compatible = "st-ericsson,ccu8540", "st-ericsson,u8540";
19
20 memory@0 {
21 reg = <0x20000000 0x1f000000>, <0xc0000000 0x3f000000>;
22 };
23
24 soc {
25 pinctrl {
26 compatible = "stericsson,db8540-pinctrl";
27 };
28
29 prcmu@80157000 {
30 reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x3000>;
31 reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
32 };
33
34 uart@80120000 {
35 pinctrl-names = "default", "sleep";
36 pinctrl-0 = <&uart0_default_mux>, <&uart0_default_mode>;
37 pinctrl-1 = <&uart0_sleep_mode>;
38 status = "okay";
39 };
40
41 uart@80121000 {
42 status = "okay";
43 };
44
45 uart@80007000 {
46 pinctrl-names = "default", "sleep";
47 pinctrl-0 = <&uart2_default_mode>;
48 pinctrl-1 = <&uart2_sleep_mode>;
49 status = "okay";
50 };
51
52 i2c0: i2c@80004000 {
53 pinctrl-names = "default","sleep";
54 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
55 pinctrl-1 = <&i2c0_sleep_mode>;
56 };
57
58 i2c1: i2c@80122000 {
59 pinctrl-names = "default","sleep";
60 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
61 pinctrl-1 = <&i2c1_sleep_mode>;
62 };
63
64 i2c2: i2c@80128000 {
65 pinctrl-names = "default","sleep";
66 pinctrl-0 = <&i2c2_default_mux>, <&i2c2_default_mode>;
67 pinctrl-1 = <&i2c2_sleep_mode>;
68 };
69
70 i2c3: i2c@80110000 {
71 status = "disabled";
72 };
73
74 i2c4: i2c@8012a000 {
75 pinctrl-names = "default","sleep";
76 pinctrl-0 = <&i2c4_default_mux>, <&i2c4_default_mode>;
77 pinctrl-1 = <&i2c4_sleep_mode>;
78 };
79
80 i2c5: i2c@80001000 {
81 pinctrl-names = "default","sleep";
82 pinctrl-0 = <&i2c5_default_mux>, <&i2c5_default_mode>;
83 pinctrl-1 = <&i2c5_sleep_mode>;
84 };
85 };
86};
diff --git a/arch/arm/boot/dts/ccu9540.dts b/arch/arm/boot/dts/ste-ccu9540.dts
index ed29ec7288e4..229508750890 100644
--- a/arch/arm/boot/dts/ccu9540.dts
+++ b/arch/arm/boot/dts/ste-ccu9540.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14 14
15/ { 15/ {
16 model = "ST-Ericsson CCU9540 platform with Device Tree"; 16 model = "ST-Ericsson CCU9540 platform with Device Tree";
diff --git a/arch/arm/boot/dts/dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index a1529455f081..1c1091eedade 100644
--- a/arch/arm/boot/dts/dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -245,7 +245,7 @@
245 <22 IRQ_TYPE_LEVEL_HIGH>; 245 <22 IRQ_TYPE_LEVEL_HIGH>;
246 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH"; 246 interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
247 status = "disabled"; 247 status = "disabled";
248 }; 248 };
249 249
250 db8500-prcmu-regulators { 250 db8500-prcmu-regulators {
251 compatible = "stericsson,db8500-prcmu-regulator"; 251 compatible = "stericsson,db8500-prcmu-regulator";
@@ -457,8 +457,36 @@
457 stericsson,earpeice-cmv = <950>; /* Units in mV. */ 457 stericsson,earpeice-cmv = <950>; /* Units in mV. */
458 }; 458 };
459 459
460 ext_regulators: ab8500-ext-regulators {
461 compatible = "stericsson,ab8500-ext-regulator";
462
463 ab8500_ext1_reg: ab8500_ext1 {
464 regulator-compatible = "ab8500_ext1";
465 regulator-min-microvolt = <1800000>;
466 regulator-max-microvolt = <1800000>;
467 regulator-boot-on;
468 regulator-always-on;
469 };
470
471 ab8500_ext2_reg: ab8500_ext2 {
472 regulator-compatible = "ab8500_ext2";
473 regulator-min-microvolt = <1360000>;
474 regulator-max-microvolt = <1360000>;
475 regulator-boot-on;
476 regulator-always-on;
477 };
478
479 ab8500_ext3_reg: ab8500_ext3 {
480 regulator-compatible = "ab8500_ext3";
481 regulator-min-microvolt = <3400000>;
482 regulator-max-microvolt = <3400000>;
483 regulator-boot-on;
484 };
485 };
486
460 ab8500-regulators { 487 ab8500-regulators {
461 compatible = "stericsson,ab8500-regulator"; 488 compatible = "stericsson,ab8500-regulator";
489 vin-supply = <&ab8500_ext3_reg>;
462 490
463 // supplies to the display/camera 491 // supplies to the display/camera
464 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 492 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
diff --git a/arch/arm/boot/dts/href.dtsi b/arch/arm/boot/dts/ste-href.dtsi
index 9db41b9d8358..370e03f5e7b2 100644
--- a/arch/arm/boot/dts/href.dtsi
+++ b/arch/arm/boot/dts/ste-href.dtsi
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/irq.h>
13#include "dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14 14
15/ { 15/ {
16 memory { 16 memory {
diff --git a/arch/arm/boot/dts/hrefprev60.dts b/arch/arm/boot/dts/ste-hrefprev60.dts
index c6bb07df2d1d..d8d3b99ab007 100644
--- a/arch/arm/boot/dts/hrefprev60.dts
+++ b/arch/arm/boot/dts/ste-hrefprev60.dts
@@ -10,9 +10,9 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14#include "href.dtsi" 14#include "ste-href.dtsi"
15#include "stuib.dtsi" 15#include "ste-stuib.dtsi"
16 16
17/ { 17/ {
18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree"; 18 model = "ST-Ericsson HREF (pre-v60) platform with Device Tree";
diff --git a/arch/arm/boot/dts/hrefv60plus.dts b/arch/arm/boot/dts/ste-hrefv60plus.dts
index 3d580d6447f9..6e52ebbf113f 100644
--- a/arch/arm/boot/dts/hrefv60plus.dts
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dts
@@ -10,9 +10,9 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14#include "href.dtsi" 14#include "ste-href.dtsi"
15#include "stuib.dtsi" 15#include "ste-stuib.dtsi"
16 16
17/ { 17/ {
18 model = "ST-Ericsson HREF (v60+) platform with Device Tree"; 18 model = "ST-Ericsson HREF (v60+) platform with Device Tree";
diff --git a/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
new file mode 100644
index 000000000000..efddee9403c4
--- /dev/null
+++ b/arch/arm/boot/dts/ste-nomadik-pinctrl.dtsi
@@ -0,0 +1,95 @@
1/*
2 * Copyright 2012 ST-Ericsson
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11#include <dt-bindings/pinctrl/nomadik.h>
12
13/ {
14 in_nopull: in_nopull {
15 ste,input = <INPUT_NOPULL>;
16 };
17
18 in_pu: input_pull_up {
19 ste,input = <INPUT_PULLUP>;
20 };
21
22 in_pd: input_pull_down {
23 ste,input = <INPUT_PULLDOWN>;
24 };
25
26 out_hi: output_high {
27 ste,output = <OUTPUT_HIGH>;
28 };
29
30 out_lo: output_low {
31 ste,output = <OUTPUT_LOW>;
32 };
33
34 gpio_out_lo: gpio_output_low {
35 ste,gpio = <GPIOMODE_ENABLED>;
36 ste,output = <OUTPUT_LOW>;
37 };
38
39 slpm_in_pu: slpm_in_pu {
40 ste,sleep = <SLPM_ENABLED>;
41 ste,sleep-input = <SLPM_INPUT_PULLUP>;
42 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
43 };
44
45 slpm_in_wkup_pdis: slpm_in_wkup_pdis {
46 ste,sleep = <SLPM_ENABLED>;
47 ste,sleep-input = <SLPM_DIR_INPUT>;
48 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
49 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
50 };
51
52 slpm_out_lo: slpm_out_lo {
53 ste,sleep = <SLPM_ENABLED>;
54 ste,sleep-output = <SLPM_OUTPUT_LOW>;
55 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
56 };
57
58 slpm_out_hi: slpm_out_hi {
59 ste,sleep = <SLPM_ENABLED>;
60 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
61 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
62 };
63
64 slpm_out_hi_wkup_pdis: slpm_out_hi_wkup_pdis {
65 ste,sleep = <SLPM_ENABLED>;
66 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
67 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
68 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
69 };
70
71 slpm_out_wkup_pdis: slpm_out_wkup_pdis {
72 ste,sleep = <SLPM_ENABLED>;
73 ste,sleep-output = <SLPM_DIR_OUTPUT>;
74 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
75 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
76 };
77
78 in_wkup_pdis: in_wkup_pdis {
79 ste,sleep-input = <SLPM_DIR_INPUT>;
80 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
81 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
82 };
83
84 out_hi_wkup_pdis: out_hi_wkup_pdis {
85 ste,sleep-output = <SLPM_OUTPUT_HIGH>;
86 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
87 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
88 };
89
90 out_wkup_pdis: out_wkup_pdis {
91 ste,sleep-output = <SLPM_DIR_OUTPUT>;
92 ste,sleep-wakeup = <SLPM_WAKEUP_ENABLE>;
93 ste,sleep-pull-disable = <SLPM_PDIS_DISABLED>;
94 };
95};
diff --git a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
index a3acfa7b3dc9..9169d3025f39 100644
--- a/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
+++ b/arch/arm/boot/dts/ste-nomadik-stn8815.dtsi
@@ -140,18 +140,30 @@
140 }; 140 };
141 }; 141 };
142 i2c0 { 142 i2c0 {
143 i2c0_default_mux: i2c0_mux {
144 i2c0_default_mux {
145 ste,function = "i2c0";
146 ste,pins = "i2c0_a_1";
147 };
148 };
143 i2c0_default_mode: i2c0_default { 149 i2c0_default_mode: i2c0_default {
144 i2c0_default_cfg { 150 i2c0_default_cfg {
145 ste,pins = "GPIO62_D3", "GPIO63_D2"; 151 ste,pins = "GPIO62_D3", "GPIO63_D2";
146 ste,input = <1>; 152 ste,input = <0>;
147 }; 153 };
148 }; 154 };
149 }; 155 };
150 i2c1 { 156 i2c1 {
157 i2c1_default_mux: i2c1_mux {
158 i2c1_default_mux {
159 ste,function = "i2c1";
160 ste,pins = "i2c1_a_1";
161 };
162 };
151 i2c1_default_mode: i2c1_default { 163 i2c1_default_mode: i2c1_default {
152 i2c1_default_cfg { 164 i2c1_default_cfg {
153 ste,pins = "GPIO53_L4", "GPIO54_L3"; 165 ste,pins = "GPIO53_L4", "GPIO54_L3";
154 ste,input = <1>; 166 ste,input = <0>;
155 }; 167 };
156 }; 168 };
157 }; 169 };
@@ -159,7 +171,7 @@
159 i2c2_default_mode: i2c2_default { 171 i2c2_default_mode: i2c2_default {
160 i2c2_default_cfg { 172 i2c2_default_cfg {
161 ste,pins = "GPIO73_C21", "GPIO74_C20"; 173 ste,pins = "GPIO73_C21", "GPIO74_C20";
162 ste,input = <1>; 174 ste,input = <0>;
163 }; 175 };
164 }; 176 };
165 }; 177 };
@@ -682,13 +694,17 @@
682 694
683 /* I2C0 connected to the STw4811 power management chip */ 695 /* I2C0 connected to the STw4811 power management chip */
684 i2c0 { 696 i2c0 {
685 compatible = "i2c-gpio"; 697 compatible = "st,nomadik-i2c", "arm,primecell";
686 gpios = <&gpio1 31 0>, /* sda */ 698 reg = <0x101f8000 0x1000>;
687 <&gpio1 30 0>; /* scl */ 699 interrupt-parent = <&vica>;
700 interrupts = <20>;
701 clock-frequency = <100000>;
688 #address-cells = <1>; 702 #address-cells = <1>;
689 #size-cells = <0>; 703 #size-cells = <0>;
704 clocks = <&i2c0clk>, <&pclki2c0>;
705 clock-names = "mclk", "apb_pclk";
690 pinctrl-names = "default"; 706 pinctrl-names = "default";
691 pinctrl-0 = <&i2c0_default_mode>; 707 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>;
692 708
693 stw4811@2d { 709 stw4811@2d {
694 compatible = "st,stw4811"; 710 compatible = "st,stw4811";
@@ -698,13 +714,17 @@
698 714
699 /* I2C1 connected to various sensors */ 715 /* I2C1 connected to various sensors */
700 i2c1 { 716 i2c1 {
701 compatible = "i2c-gpio"; 717 compatible = "st,nomadik-i2c", "arm,primecell";
702 gpios = <&gpio1 22 0>, /* sda */ 718 reg = <0x101f7000 0x1000>;
703 <&gpio1 21 0>; /* scl */ 719 interrupt-parent = <&vica>;
720 interrupts = <21>;
721 clock-frequency = <100000>;
704 #address-cells = <1>; 722 #address-cells = <1>;
705 #size-cells = <0>; 723 #size-cells = <0>;
724 clocks = <&i2c1clk>, <&pclki2c1>;
725 clock-names = "mclk", "apb_pclk";
706 pinctrl-names = "default"; 726 pinctrl-names = "default";
707 pinctrl-0 = <&i2c1_default_mode>; 727 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>;
708 728
709 camera@2d { 729 camera@2d {
710 compatible = "st,camera"; 730 compatible = "st,camera";
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 49824be66845..f1fc128e249d 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "dbx5x0.dtsi" 13#include "ste-dbx5x0.dtsi"
14 14
15/ { 15/ {
16 model = "Calao Systems Snowball platform with device tree"; 16 model = "Calao Systems Snowball platform with device tree";
@@ -165,34 +165,6 @@
165 status = "okay"; 165 status = "okay";
166 }; 166 };
167 167
168 i2c@80004000 {
169 tc3589x@42 {
170 //compatible = "tc3589x";
171 reg = <0x42>;
172 gpios = <&gpio6 25 0x4>;
173 interrupt-parent = <&gpio6>;
174 };
175 tps61052@33 {
176 //compatible = "tps61052";
177 reg = <0x33>;
178 };
179 };
180
181 i2c@80128000 {
182 lp5521@33 {
183 // compatible = "lp5521";
184 reg = <0x33>;
185 };
186 lp5521@34 {
187 // compatible = "lp5521";
188 reg = <0x34>;
189 };
190 bh1780@29 {
191 // compatible = "rohm,bh1780gli";
192 reg = <0x33>;
193 };
194 };
195
196 cpufreq-cooling { 168 cpufreq-cooling {
197 status = "okay"; 169 status = "okay";
198 }; 170 };
@@ -310,6 +282,20 @@
310 compatible = "stericsson,ab8500-gpio"; 282 compatible = "stericsson,ab8500-gpio";
311 }; 283 };
312 284
285 ext_regulators: ab8500-ext-regulators {
286 ab8500_ext1_reg: ab8500_ext1 {
287 regulator-name = "ab8500-ext-supply1";
288 };
289
290 ab8500_ext2_reg_reg: ab8500_ext2 {
291 regulator-name = "ab8500-ext-supply2";
292 };
293
294 ab8500_ext3_reg_reg: ab8500_ext3 {
295 regulator-name = "ab8500-ext-supply3";
296 };
297 };
298
313 ab8500-regulators { 299 ab8500-regulators {
314 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 { 300 ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
315 regulator-name = "V-DISPLAY"; 301 regulator-name = "V-DISPLAY";
diff --git a/arch/arm/boot/dts/stuib.dtsi b/arch/arm/boot/dts/ste-stuib.dtsi
index 524e33240ad4..524e33240ad4 100644
--- a/arch/arm/boot/dts/stuib.dtsi
+++ b/arch/arm/boot/dts/ste-stuib.dtsi
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
new file mode 100644
index 000000000000..eb4d73b6a090
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun4i-a10.dtsi"
16
17/ {
18 model = "Mele A1000";
19 compatible = "mele,a1000", "allwinner,sun4i-a10";
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 soc@01c00000 {
26 emac: ethernet@01c0b000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&emac_pins_a>;
29 phy = <&phy1>;
30 status = "okay";
31 };
32
33 mdio@01c0b080 {
34 phy-supply = <&reg_emac_3v3>;
35 status = "okay";
36
37 phy1: ethernet-phy@1 {
38 reg = <1>;
39 };
40 };
41
42 pinctrl@01c20800 {
43 emac_power_pin_a1000: emac_power_pin@0 {
44 allwinner,pins = "PH15";
45 allwinner,function = "gpio_out";
46 allwinner,drive = <0>;
47 allwinner,pull = <0>;
48 };
49
50 led_pins_a1000: led_pins@0 {
51 allwinner,pins = "PH10", "PH20";
52 allwinner,function = "gpio_out";
53 allwinner,drive = <0>;
54 allwinner,pull = <0>;
55 };
56 };
57
58 uart0: serial@01c28000 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&uart0_pins_a>;
61 status = "okay";
62 };
63
64 i2c0: i2c@01c2ac00 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins_a>;
67 status = "okay";
68 };
69 };
70
71 leds {
72 compatible = "gpio-leds";
73 pinctrl-names = "default";
74 pinctrl-0 = <&led_pins_a1000>;
75
76 red {
77 label = "a1000:red:usr";
78 gpios = <&pio 7 10 0>;
79 };
80
81 blue {
82 label = "a1000:blue:usr";
83 gpios = <&pio 7 20 0>;
84 };
85 };
86
87 regulators {
88 compatible = "simple-bus";
89
90 reg_emac_3v3: emac-3v3 {
91 compatible = "regulator-fixed";
92 pinctrl-names = "default";
93 pinctrl-0 = <&emac_power_pin_a1000>;
94 regulator-name = "emac-3v3";
95 regulator-min-microvolt = <3300000>;
96 regulator-max-microvolt = <3300000>;
97 enable-active-high;
98 gpio = <&pio 7 15 0>;
99 };
100 };
101};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index 757c4cd900ee..425a7db898c5 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -26,7 +26,7 @@
26 bootargs = "earlyprintk console=ttyS0,115200"; 26 bootargs = "earlyprintk console=ttyS0,115200";
27 }; 27 };
28 28
29 soc@01c20000 { 29 soc@01c00000 {
30 emac: ethernet@01c0b000 { 30 emac: ethernet@01c0b000 {
31 pinctrl-names = "default"; 31 pinctrl-names = "default";
32 pinctrl-0 = <&emac_pins_a>; 32 pinctrl-0 = <&emac_pins_a>;
@@ -76,12 +76,12 @@
76 pinctrl-0 = <&led_pins_cubieboard>; 76 pinctrl-0 = <&led_pins_cubieboard>;
77 77
78 blue { 78 blue {
79 label = "cubieboard::blue"; 79 label = "cubieboard:blue:usr";
80 gpios = <&pio 7 21 0>; /* LED1 */ 80 gpios = <&pio 7 21 0>; /* LED1 */
81 }; 81 };
82 82
83 green { 83 green {
84 label = "cubieboard::green"; 84 label = "cubieboard:green:usr";
85 gpios = <&pio 7 20 0>; /* LED2 */ 85 gpios = <&pio 7 20 0>; /* LED2 */
86 linux,default-trigger = "heartbeat"; 86 linux,default-trigger = "heartbeat";
87 }; 87 };
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 3514b37d66bc..b3ae51fa9372 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 emac: ethernet@01c0b000 { 26 emac: ethernet@01c0b000 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&emac_pins_a>; 28 pinctrl-0 = <&emac_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index 078ed7f618d7..0c1447c68059 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 uart0: serial@01c28000 { 26 uart0: serial@01c28000 {
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>; 28 pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b2bd6e124250..c32770a28acf 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -160,11 +160,10 @@
160 }; 160 };
161 }; 161 };
162 162
163 soc@01c20000 { 163 soc@01c00000 {
164 compatible = "simple-bus"; 164 compatible = "simple-bus";
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <1>; 166 #size-cells = <1>;
167 reg = <0x01c20000 0x300000>;
168 ranges; 167 ranges;
169 168
170 emac: ethernet@01c0b000 { 169 emac: ethernet@01c0b000 {
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 64dc0c42c43a..3c9f8b3cd3e3 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -18,7 +18,7 @@
18 model = "Olimex A10s-Olinuxino Micro"; 18 model = "Olimex A10s-Olinuxino Micro";
19 compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s"; 19 compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
20 20
21 soc@01c20000 { 21 soc@01c00000 {
22 emac: ethernet@01c0b000 { 22 emac: ethernet@01c0b000 {
23 pinctrl-names = "default"; 23 pinctrl-names = "default";
24 pinctrl-0 = <&emac_pins_a>; 24 pinctrl-0 = <&emac_pins_a>;
@@ -60,6 +60,31 @@
60 pinctrl-0 = <&uart3_pins_a>; 60 pinctrl-0 = <&uart3_pins_a>;
61 status = "okay"; 61 status = "okay";
62 }; 62 };
63
64 i2c0: i2c@01c2ac00 {
65 pinctrl-names = "default";
66 pinctrl-0 = <&i2c0_pins_a>;
67 status = "okay";
68 };
69
70 i2c1: i2c@01c2b000 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&i2c1_pins_a>;
73 status = "okay";
74
75 at24@50 {
76 compatible = "at,24c16";
77 pagesize = <16>;
78 reg = <0x50>;
79 read-only;
80 };
81 };
82
83 i2c2: i2c@01c2b400 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&i2c2_pins_a>;
86 status = "okay";
87 };
63 }; 88 };
64 89
65 leds { 90 leds {
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 2307ce827ae0..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
95 95
96 ahb_gates: ahb_gates@01c20060 { 96 ahb_gates: ahb_gates@01c20060 {
97 #clock-cells = <1>; 97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-ahb-gates-clk"; 98 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
99 reg = <0x01c20060 0x8>; 99 reg = <0x01c20060 0x8>;
100 clocks = <&ahb>; 100 clocks = <&ahb>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0", 101 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", 102 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", 103 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", 104 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", 105 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", 106 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", 107 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
112 }; 108 };
113 109
114 apb0: apb0@01c20054 { 110 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
120 116
121 apb0_gates: apb0_gates@01c20068 { 117 apb0_gates: apb0_gates@01c20068 {
122 #clock-cells = <1>; 118 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-apb0-gates-clk"; 119 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
124 reg = <0x01c20068 0x4>; 120 reg = <0x01c20068 0x4>;
125 clocks = <&apb0>; 121 clocks = <&apb0>;
126 clock-output-names = "apb0_codec", "apb0_spdif", 122 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", 123 "apb0_ir", "apb0_keypad";
128 "apb0_ir1", "apb0_keypad";
129 }; 124 };
130 125
131 /* dummy is pll62 */ 126 /* dummy is pll62 */
@@ -145,23 +140,19 @@
145 140
146 apb1_gates: apb1_gates@01c2006c { 141 apb1_gates: apb1_gates@01c2006c {
147 #clock-cells = <1>; 142 #clock-cells = <1>;
148 compatible = "allwinner,sun4i-apb1-gates-clk"; 143 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>; 144 reg = <0x01c2006c 0x4>;
150 clocks = <&apb1>; 145 clocks = <&apb1>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1", 146 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr", 147 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0", 148 "apb1_uart2", "apb1_uart3";
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
156 "apb1_uart7";
157 }; 149 };
158 }; 150 };
159 151
160 soc@01c20000 { 152 soc@01c00000 {
161 compatible = "simple-bus"; 153 compatible = "simple-bus";
162 #address-cells = <1>; 154 #address-cells = <1>;
163 #size-cells = <1>; 155 #size-cells = <1>;
164 reg = <0x01c20000 0x300000>;
165 ranges; 156 ranges;
166 157
167 emac: ethernet@01c0b000 { 158 emac: ethernet@01c0b000 {
@@ -229,6 +220,27 @@
229 allwinner,drive = <0>; 220 allwinner,drive = <0>;
230 allwinner,pull = <0>; 221 allwinner,pull = <0>;
231 }; 222 };
223
224 i2c0_pins_a: i2c0@0 {
225 allwinner,pins = "PB0", "PB1";
226 allwinner,function = "i2c0";
227 allwinner,drive = <0>;
228 allwinner,pull = <0>;
229 };
230
231 i2c1_pins_a: i2c1@0 {
232 allwinner,pins = "PB15", "PB16";
233 allwinner,function = "i2c1";
234 allwinner,drive = <0>;
235 allwinner,pull = <0>;
236 };
237
238 i2c2_pins_a: i2c2@0 {
239 allwinner,pins = "PB17", "PB18";
240 allwinner,function = "i2c2";
241 allwinner,drive = <0>;
242 allwinner,pull = <0>;
243 };
232 }; 244 };
233 245
234 timer@01c20c00 { 246 timer@01c20c00 {
@@ -282,5 +294,38 @@
282 clocks = <&apb1_gates 19>; 294 clocks = <&apb1_gates 19>;
283 status = "disabled"; 295 status = "disabled";
284 }; 296 };
297
298 i2c0: i2c@01c2ac00 {
299 #address-cells = <1>;
300 #size-cells = <0>;
301 compatible = "allwinner,sun4i-i2c";
302 reg = <0x01c2ac00 0x400>;
303 interrupts = <7>;
304 clocks = <&apb1_gates 0>;
305 clock-frequency = <100000>;
306 status = "disabled";
307 };
308
309 i2c1: i2c@01c2b000 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "allwinner,sun4i-i2c";
313 reg = <0x01c2b000 0x400>;
314 interrupts = <8>;
315 clocks = <&apb1_gates 1>;
316 clock-frequency = <100000>;
317 status = "disabled";
318 };
319
320 i2c2: i2c@01c2b400 {
321 #address-cells = <1>;
322 #size-cells = <0>;
323 compatible = "allwinner,sun4i-i2c";
324 reg = <0x01c2b400 0x400>;
325 interrupts = <9>;
326 clocks = <&apb1_gates 2>;
327 clock-frequency = <100000>;
328 status = "disabled";
329 };
285 }; 330 };
286}; 331};
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index 80497e376706..9e508dcc4245 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -22,7 +22,7 @@
22 bootargs = "earlyprintk console=ttyS0,115200"; 22 bootargs = "earlyprintk console=ttyS0,115200";
23 }; 23 };
24 24
25 soc@01c20000 { 25 soc@01c00000 {
26 pinctrl@01c20800 { 26 pinctrl@01c20800 {
27 led_pins_olinuxino: led_pins@0 { 27 led_pins_olinuxino: led_pins@0 {
28 allwinner,pins = "PG9"; 28 allwinner,pins = "PG9";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 7363211daf84..f6091dc0936c 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -150,11 +150,10 @@
150 }; 150 };
151 }; 151 };
152 152
153 soc@01c20000 { 153 soc@01c00000 {
154 compatible = "simple-bus"; 154 compatible = "simple-bus";
155 #address-cells = <1>; 155 #address-cells = <1>;
156 #size-cells = <1>; 156 #size-cells = <1>;
157 reg = <0x01c20000 0x300000>;
158 ranges; 157 ranges;
159 158
160 intc: interrupt-controller@01c20400 { 159 intc: interrupt-controller@01c20400 {
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
new file mode 100644
index 000000000000..e5adae30899b
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun6i-a31.dtsi"
16
17/ {
18 model = "WITS A31 Colombus Evaluation Board";
19 compatible = "wits,colombus", "allwinner,sun6i-a31";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 {
26 uart0: serial@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
29 status = "okay";
30 };
31 };
32};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
new file mode 100644
index 000000000000..f244f5f02365
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -0,0 +1,299 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <1>;
33 };
34
35 cpu@2 {
36 compatible = "arm,cortex-a7";
37 device_type = "cpu";
38 reg = <2>;
39 };
40
41 cpu@3 {
42 compatible = "arm,cortex-a7";
43 device_type = "cpu";
44 reg = <3>;
45 };
46 };
47
48 memory {
49 reg = <0x40000000 0x80000000>;
50 };
51
52 clocks {
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 osc24M: osc24M {
58 #clock-cells = <0>;
59 compatible = "fixed-clock";
60 clock-frequency = <24000000>;
61 };
62
63 osc32k: osc32k {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 pll1: pll1@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
88 cpu: cpu@01c20050 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
92
93 /*
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
97 * Allwinner.
98 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
100 };
101
102 axi: axi@01c20050 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>;
107 };
108
109 ahb1_mux: ahb1_mux@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
114 };
115
116 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
121 };
122
123 ahb1_gates: ahb1_gates@01c20060 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
127 clocks = <&ahb1>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
142 };
143
144 apb1: apb1@01c20054 {
145 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>;
149 };
150
151 apb1_gates: apb1_gates@01c20060 {
152 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
155 clocks = <&apb1>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
158 "apb1_daudio1";
159 };
160
161 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166 };
167
168 apb2: apb2@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
173 };
174
175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x8>;
179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
184 };
185 };
186
187 soc@01c00000 {
188 compatible = "simple-bus";
189 #address-cells = <1>;
190 #size-cells = <1>;
191 ranges;
192
193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
197 clocks = <&apb1_gates 5>;
198 gpio-controller;
199 interrupt-controller;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #gpio-cells = <3>;
203
204 uart0_pins_a: uart0@0 {
205 allwinner,pins = "PH20", "PH21";
206 allwinner,function = "uart0";
207 allwinner,drive = <0>;
208 allwinner,pull = <0>;
209 };
210 };
211
212 timer@01c20c00 {
213 compatible = "allwinner,sun4i-timer";
214 reg = <0x01c20c00 0xa0>;
215 interrupts = <0 18 1>,
216 <0 19 1>,
217 <0 20 1>,
218 <0 21 1>,
219 <0 22 1>;
220 clocks = <&osc24M>;
221 };
222
223 wdt1: watchdog@01c20ca0 {
224 compatible = "allwinner,sun6i-wdt";
225 reg = <0x01c20ca0 0x20>;
226 };
227
228 uart0: serial@01c28000 {
229 compatible = "snps,dw-apb-uart";
230 reg = <0x01c28000 0x400>;
231 interrupts = <0 0 1>;
232 reg-shift = <2>;
233 reg-io-width = <4>;
234 clocks = <&apb2_gates 16>;
235 status = "disabled";
236 };
237
238 uart1: serial@01c28400 {
239 compatible = "snps,dw-apb-uart";
240 reg = <0x01c28400 0x400>;
241 interrupts = <0 1 1>;
242 reg-shift = <2>;
243 reg-io-width = <4>;
244 clocks = <&apb2_gates 17>;
245 status = "disabled";
246 };
247
248 uart2: serial@01c28800 {
249 compatible = "snps,dw-apb-uart";
250 reg = <0x01c28800 0x400>;
251 interrupts = <0 2 1>;
252 reg-shift = <2>;
253 reg-io-width = <4>;
254 clocks = <&apb2_gates 18>;
255 status = "disabled";
256 };
257
258 uart3: serial@01c28c00 {
259 compatible = "snps,dw-apb-uart";
260 reg = <0x01c28c00 0x400>;
261 interrupts = <0 3 1>;
262 reg-shift = <2>;
263 reg-io-width = <4>;
264 clocks = <&apb2_gates 19>;
265 status = "disabled";
266 };
267
268 uart4: serial@01c29000 {
269 compatible = "snps,dw-apb-uart";
270 reg = <0x01c29000 0x400>;
271 interrupts = <0 4 1>;
272 reg-shift = <2>;
273 reg-io-width = <4>;
274 clocks = <&apb2_gates 20>;
275 status = "disabled";
276 };
277
278 uart5: serial@01c29400 {
279 compatible = "snps,dw-apb-uart";
280 reg = <0x01c29400 0x400>;
281 interrupts = <0 5 1>;
282 reg-shift = <2>;
283 reg-io-width = <4>;
284 clocks = <&apb2_gates 21>;
285 status = "disabled";
286 };
287
288 gic: interrupt-controller@01c81000 {
289 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
290 reg = <0x01c81000 0x1000>,
291 <0x01c82000 0x1000>,
292 <0x01c84000 0x2000>,
293 <0x01c86000 0x2000>;
294 interrupt-controller;
295 #interrupt-cells = <3>;
296 interrupts = <1 9 0xf04>;
297 };
298 };
299};
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Cubietech Cubieboard2";
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_cubieboard2: led_pins@0 {
24 allwinner,pins = "PH20", "PH21";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <0>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&led_pins_cubieboard2>;
42
43 blue {
44 label = "cubieboard2:blue:usr";
45 gpios = <&pio 7 21 0>;
46 };
47
48 green {
49 label = "cubieboard2:green:usr";
50 gpios = <&pio 7 20 0>;
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
new file mode 100644
index 000000000000..34a6c02a7c72
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -0,0 +1,61 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Olimex A20-Olinuxino Micro";
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_olinuxino: led_pins@0 {
24 allwinner,pins = "PH2";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <1>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36
37 uart6: serial@01c29800 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&uart6_pins_a>;
40 status = "okay";
41 };
42
43 uart7: serial@01c29c00 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&uart7_pins_a>;
46 status = "okay";
47 };
48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&led_pins_olinuxino>;
54
55 green {
56 label = "a20-olinuxino-micro:green:usr";
57 gpios = <&pio 7 2 0>;
58 default-state = "on";
59 };
60 };
61};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
new file mode 100644
index 000000000000..999ff45cb77e
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -0,0 +1,311 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "arm,cortex-a7";
25 device_type = "cpu";
26 reg = <0>;
27 };
28
29 cpu@1 {
30 compatible = "arm,cortex-a7";
31 device_type = "cpu";
32 reg = <1>;
33 };
34 };
35
36 memory {
37 reg = <0x40000000 0x80000000>;
38 };
39
40 clocks {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 osc24M: osc24M@01c20050 {
46 #clock-cells = <0>;
47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
49 clock-frequency = <24000000>;
50 };
51
52 osc32k: osc32k {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <32768>;
56 };
57
58 pll1: pll1@01c20000 {
59 #clock-cells = <0>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
62 clocks = <&osc24M>;
63 };
64
65 /*
66 * This is a dummy clock, to be used as placeholder on
67 * other mux clocks when a specific parent clock is not
68 * yet implemented. It should be dropped when the driver
69 * is complete.
70 */
71 pll6: pll6 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 cpu: cpu@01c20054 {
78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-cpu-clk";
80 reg = <0x01c20054 0x4>;
81 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
82 };
83
84 axi: axi@01c20054 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-axi-clk";
87 reg = <0x01c20054 0x4>;
88 clocks = <&cpu>;
89 };
90
91 ahb: ahb@01c20054 {
92 #clock-cells = <0>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
95 clocks = <&axi>;
96 };
97
98 ahb_gates: ahb_gates@01c20060 {
99 #clock-cells = <1>;
100 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
101 reg = <0x01c20060 0x8>;
102 clocks = <&ahb>;
103 clock-output-names = "ahb_usb0", "ahb_ehci0",
104 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
105 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
106 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
107 "ahb_nand", "ahb_sdram", "ahb_ace",
108 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
109 "ahb_spi2", "ahb_spi3", "ahb_sata",
110 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
111 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
112 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
115 "ahb_mali";
116 };
117
118 apb0: apb0@01c20054 {
119 #clock-cells = <0>;
120 compatible = "allwinner,sun4i-apb0-clk";
121 reg = <0x01c20054 0x4>;
122 clocks = <&ahb>;
123 };
124
125 apb0_gates: apb0_gates@01c20068 {
126 #clock-cells = <1>;
127 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128 reg = <0x01c20068 0x4>;
129 clocks = <&apb0>;
130 clock-output-names = "apb0_codec", "apb0_spdif",
131 "apb0_ac97", "apb0_iis0", "apb0_iis1",
132 "apb0_pio", "apb0_ir0", "apb0_ir1",
133 "apb0_iis2", "apb0_keypad";
134 };
135
136 apb1_mux: apb1_mux@01c20058 {
137 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&pll6>, <&osc32k>;
141 };
142
143 apb1: apb1@01c20058 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-apb1-clk";
146 reg = <0x01c20058 0x4>;
147 clocks = <&apb1_mux>;
148 };
149
150 apb1_gates: apb1_gates@01c2006c {
151 #clock-cells = <1>;
152 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153 reg = <0x01c2006c 0x4>;
154 clocks = <&apb1>;
155 clock-output-names = "apb1_i2c0", "apb1_i2c1",
156 "apb1_i2c2", "apb1_i2c3", "apb1_can",
157 "apb1_scr", "apb1_ps20", "apb1_ps21",
158 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
159 "apb1_uart2", "apb1_uart3", "apb1_uart4",
160 "apb1_uart5", "apb1_uart6", "apb1_uart7";
161 };
162 };
163
164 soc@01c00000 {
165 compatible = "simple-bus";
166 #address-cells = <1>;
167 #size-cells = <1>;
168 ranges;
169
170 pio: pinctrl@01c20800 {
171 compatible = "allwinner,sun7i-a20-pinctrl";
172 reg = <0x01c20800 0x400>;
173 interrupts = <0 28 1>;
174 clocks = <&apb0_gates 5>;
175 gpio-controller;
176 interrupt-controller;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 #gpio-cells = <3>;
180
181 uart0_pins_a: uart0@0 {
182 allwinner,pins = "PB22", "PB23";
183 allwinner,function = "uart0";
184 allwinner,drive = <0>;
185 allwinner,pull = <0>;
186 };
187
188 uart6_pins_a: uart6@0 {
189 allwinner,pins = "PI12", "PI13";
190 allwinner,function = "uart6";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
193 };
194
195 uart7_pins_a: uart7@0 {
196 allwinner,pins = "PI20", "PI21";
197 allwinner,function = "uart7";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
200 };
201 };
202
203 timer@01c20c00 {
204 compatible = "allwinner,sun4i-timer";
205 reg = <0x01c20c00 0x90>;
206 interrupts = <0 22 1>,
207 <0 23 1>,
208 <0 24 1>,
209 <0 25 1>,
210 <0 67 1>,
211 <0 68 1>;
212 clocks = <&osc24M>;
213 };
214
215 wdt: watchdog@01c20c90 {
216 compatible = "allwinner,sun4i-wdt";
217 reg = <0x01c20c90 0x10>;
218 };
219
220 uart0: serial@01c28000 {
221 compatible = "snps,dw-apb-uart";
222 reg = <0x01c28000 0x400>;
223 interrupts = <0 1 1>;
224 reg-shift = <2>;
225 reg-io-width = <4>;
226 clocks = <&apb1_gates 16>;
227 status = "disabled";
228 };
229
230 uart1: serial@01c28400 {
231 compatible = "snps,dw-apb-uart";
232 reg = <0x01c28400 0x400>;
233 interrupts = <0 2 1>;
234 reg-shift = <2>;
235 reg-io-width = <4>;
236 clocks = <&apb1_gates 17>;
237 status = "disabled";
238 };
239
240 uart2: serial@01c28800 {
241 compatible = "snps,dw-apb-uart";
242 reg = <0x01c28800 0x400>;
243 interrupts = <0 3 1>;
244 reg-shift = <2>;
245 reg-io-width = <4>;
246 clocks = <&apb1_gates 18>;
247 status = "disabled";
248 };
249
250 uart3: serial@01c28c00 {
251 compatible = "snps,dw-apb-uart";
252 reg = <0x01c28c00 0x400>;
253 interrupts = <0 4 1>;
254 reg-shift = <2>;
255 reg-io-width = <4>;
256 clocks = <&apb1_gates 19>;
257 status = "disabled";
258 };
259
260 uart4: serial@01c29000 {
261 compatible = "snps,dw-apb-uart";
262 reg = <0x01c29000 0x400>;
263 interrupts = <0 17 1>;
264 reg-shift = <2>;
265 reg-io-width = <4>;
266 clocks = <&apb1_gates 20>;
267 status = "disabled";
268 };
269
270 uart5: serial@01c29400 {
271 compatible = "snps,dw-apb-uart";
272 reg = <0x01c29400 0x400>;
273 interrupts = <0 18 1>;
274 reg-shift = <2>;
275 reg-io-width = <4>;
276 clocks = <&apb1_gates 21>;
277 status = "disabled";
278 };
279
280 uart6: serial@01c29800 {
281 compatible = "snps,dw-apb-uart";
282 reg = <0x01c29800 0x400>;
283 interrupts = <0 19 1>;
284 reg-shift = <2>;
285 reg-io-width = <4>;
286 clocks = <&apb1_gates 22>;
287 status = "disabled";
288 };
289
290 uart7: serial@01c29c00 {
291 compatible = "snps,dw-apb-uart";
292 reg = <0x01c29c00 0x400>;
293 interrupts = <0 20 1>;
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 clocks = <&apb1_gates 23>;
297 status = "disabled";
298 };
299
300 gic: interrupt-controller@01c81000 {
301 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
302 reg = <0x01c81000 0x1000>,
303 <0x01c82000 0x1000>,
304 <0x01c84000 0x2000>,
305 <0x01c86000 0x2000>;
306 interrupt-controller;
307 #interrupt-cells = <3>;
308 interrupts = <1 9 0xf04>;
309 };
310 };
311};
diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts
index cb640eb6c932..60230288884b 100644
--- a/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -791,7 +791,7 @@
791 regulator-boot-on; 791 regulator-boot-on;
792 }; 792 };
793 793
794 dcdc3 { 794 tps65090_dcdc3_reg: dcdc3 {
795 regulator-name = "vdd-ao"; 795 regulator-name = "vdd-ao";
796 regulator-always-on; 796 regulator-always-on;
797 regulator-boot-on; 797 regulator-boot-on;
@@ -836,6 +836,182 @@
836 }; 836 };
837 }; 837 };
838 }; 838 };
839
840 palmas: tps65913 {
841 compatible = "ti,palmas";
842 reg = <0x58>;
843 interrupts = <0 86 IRQ_TYPE_LEVEL_LOW>;
844
845 #interrupt-cells = <2>;
846 interrupt-controller;
847
848 ti,system-power-controller;
849
850 palmas_gpio: gpio {
851 compatible = "ti,palmas-gpio";
852 gpio-controller;
853 #gpio-cells = <2>;
854 };
855
856 pmic {
857 compatible = "ti,tps65913-pmic", "ti,palmas-pmic";
858 smps1-in-supply = <&tps65090_dcdc3_reg>;
859 smps3-in-supply = <&tps65090_dcdc3_reg>;
860 smps4-in-supply = <&tps65090_dcdc2_reg>;
861 smps7-in-supply = <&tps65090_dcdc2_reg>;
862 smps8-in-supply = <&tps65090_dcdc2_reg>;
863 smps9-in-supply = <&tps65090_dcdc2_reg>;
864 ldo1-in-supply = <&tps65090_dcdc2_reg>;
865 ldo2-in-supply = <&tps65090_dcdc2_reg>;
866 ldo3-in-supply = <&palmas_smps3_reg>;
867 ldo4-in-supply = <&tps65090_dcdc2_reg>;
868 ldo5-in-supply = <&vdd_ac_bat_reg>;
869 ldo6-in-supply = <&tps65090_dcdc2_reg>;
870 ldo7-in-supply = <&tps65090_dcdc2_reg>;
871 ldo8-in-supply = <&tps65090_dcdc3_reg>;
872 ldo9-in-supply = <&palmas_smps9_reg>;
873 ldoln-in-supply = <&tps65090_dcdc1_reg>;
874 ldousb-in-supply = <&tps65090_dcdc1_reg>;
875
876 regulators {
877 smps12 {
878 regulator-name = "vddio-ddr";
879 regulator-min-microvolt = <1350000>;
880 regulator-max-microvolt = <1350000>;
881 regulator-always-on;
882 regulator-boot-on;
883 };
884
885 palmas_smps3_reg: smps3 {
886 regulator-name = "vddio-1v8";
887 regulator-min-microvolt = <1800000>;
888 regulator-max-microvolt = <1800000>;
889 regulator-always-on;
890 regulator-boot-on;
891 };
892
893 smps45 {
894 regulator-name = "vdd-core";
895 regulator-min-microvolt = <900000>;
896 regulator-max-microvolt = <1400000>;
897 regulator-always-on;
898 regulator-boot-on;
899 };
900
901 smps457 {
902 regulator-name = "vdd-core";
903 regulator-min-microvolt = <900000>;
904 regulator-max-microvolt = <1400000>;
905 regulator-always-on;
906 regulator-boot-on;
907 };
908
909 smps8 {
910 regulator-name = "avdd-pll";
911 regulator-min-microvolt = <1050000>;
912 regulator-max-microvolt = <1050000>;
913 regulator-always-on;
914 regulator-boot-on;
915 };
916
917 palmas_smps9_reg: smps9 {
918 regulator-name = "sdhci-vdd-sd-slot";
919 regulator-min-microvolt = <2800000>;
920 regulator-max-microvolt = <2800000>;
921 regulator-always-on;
922 };
923
924 ldo1 {
925 regulator-name = "avdd-cam1";
926 regulator-min-microvolt = <2800000>;
927 regulator-max-microvolt = <2800000>;
928 };
929
930 ldo2 {
931 regulator-name = "avdd-cam2";
932 regulator-min-microvolt = <2800000>;
933 regulator-max-microvolt = <2800000>;
934 };
935
936 ldo3 {
937 regulator-name = "avdd-dsi-csi";
938 regulator-min-microvolt = <1200000>;
939 regulator-max-microvolt = <1200000>;
940 regulator-always-on;
941 regulator-boot-on;
942 };
943
944 ldo4 {
945 regulator-name = "vpp-fuse";
946 regulator-min-microvolt = <1800000>;
947 regulator-max-microvolt = <1800000>;
948 };
949
950 ldo6 {
951 regulator-name = "vdd-sensor-2v85";
952 regulator-min-microvolt = <2850000>;
953 regulator-max-microvolt = <2850000>;
954 };
955
956 ldo7 {
957 regulator-name = "vdd-af-cam1";
958 regulator-min-microvolt = <2800000>;
959 regulator-max-microvolt = <2800000>;
960 };
961
962 ldo8 {
963 regulator-name = "vdd-rtc";
964 regulator-min-microvolt = <900000>;
965 regulator-max-microvolt = <900000>;
966 regulator-always-on;
967 regulator-boot-on;
968 ti,enable-ldo8-tracking;
969 };
970
971 ldo9 {
972 regulator-name = "vddio-sdmmc-2";
973 regulator-min-microvolt = <1800000>;
974 regulator-max-microvolt = <3300000>;
975 regulator-always-on;
976 regulator-boot-on;
977 };
978
979 ldoln {
980 regulator-name = "hvdd-usb";
981 regulator-min-microvolt = <3300000>;
982 regulator-max-microvolt = <3300000>;
983 };
984
985 ldousb {
986 regulator-name = "avdd-usb";
987 regulator-min-microvolt = <3300000>;
988 regulator-max-microvolt = <3300000>;
989 regulator-always-on;
990 regulator-boot-on;
991 };
992
993 regen1 {
994 regulator-name = "rail-3v3";
995 regulator-max-microvolt = <3300000>;
996 regulator-always-on;
997 regulator-boot-on;
998 };
999
1000 regen2 {
1001 regulator-name = "rail-5v0";
1002 regulator-max-microvolt = <5000000>;
1003 regulator-always-on;
1004 regulator-boot-on;
1005 };
1006 };
1007 };
1008
1009 rtc {
1010 compatible = "ti,palmas-rtc";
1011 interrupt-parent = <&palmas>;
1012 interrupts = <8 0>;
1013 };
1014 };
839 }; 1015 };
840 1016
841 spi@7000da00 { 1017 spi@7000da00 {
@@ -850,6 +1026,13 @@
850 1026
851 pmc { 1027 pmc {
852 nvidia,invert-interrupt; 1028 nvidia,invert-interrupt;
1029 nvidia,suspend-mode = <1>;
1030 nvidia,cpu-pwr-good-time = <500>;
1031 nvidia,cpu-pwr-off-time = <300>;
1032 nvidia,core-pwr-good-time = <641 3845>;
1033 nvidia,core-pwr-off-time = <61036>;
1034 nvidia,core-power-req-active-high;
1035 nvidia,sys-clock-req-active-high;
853 }; 1036 };
854 1037
855 ahub { 1038 ahub {
@@ -870,6 +1053,15 @@
870 non-removable; 1053 non-removable;
871 }; 1054 };
872 1055
1056 usb@7d008000 {
1057 status = "okay";
1058 };
1059
1060 usb-phy@7d008000 {
1061 status = "okay";
1062 vbus-supply = <&usb3_vbus_reg>;
1063 };
1064
873 clocks { 1065 clocks {
874 compatible = "simple-bus"; 1066 compatible = "simple-bus";
875 #address-cells = <1>; 1067 #address-cells = <1>;
@@ -883,6 +1075,35 @@
883 }; 1075 };
884 }; 1076 };
885 1077
1078 gpio-keys {
1079 compatible = "gpio-keys";
1080
1081 home {
1082 label = "Home";
1083 gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
1084 linux,code = <102>; /* KEY_HOME */
1085 };
1086
1087 power {
1088 label = "Power";
1089 gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>;
1090 linux,code = <116>; /* KEY_POWER */
1091 gpio-key,wakeup;
1092 };
1093
1094 volume_down {
1095 label = "Volume Down";
1096 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
1097 linux,code = <114>; /* KEY_VOLUMEDOWN */
1098 };
1099
1100 volume_up {
1101 label = "Volume Up";
1102 gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>;
1103 linux,code = <115>; /* KEY_VOLUMEUP */
1104 };
1105 };
1106
886 regulators { 1107 regulators {
887 compatible = "simple-bus"; 1108 compatible = "simple-bus";
888 #address-cells = <1>; 1109 #address-cells = <1>;
@@ -951,6 +1172,16 @@
951 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; 1172 gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>;
952 vin-supply = <&tps65090_dcdc1_reg>; 1173 vin-supply = <&tps65090_dcdc1_reg>;
953 }; 1174 };
1175
1176 vdd_cam_1v8_reg: regulator@6 {
1177 compatible = "regulator-fixed";
1178 reg = <6>;
1179 regulator-name = "vdd_cam_1v8_reg";
1180 regulator-min-microvolt = <1800000>;
1181 regulator-max-microvolt = <1800000>;
1182 enable-active-high;
1183 gpio = <&palmas_gpio 6 0>;
1184 };
954 }; 1185 };
955 1186
956 sound { 1187 sound {
@@ -964,7 +1195,9 @@
964 "Speakers", "SPORP", 1195 "Speakers", "SPORP",
965 "Speakers", "SPORN", 1196 "Speakers", "SPORN",
966 "Speakers", "SPOLP", 1197 "Speakers", "SPOLP",
967 "Speakers", "SPOLN"; 1198 "Speakers", "SPOLN",
1199 "Mic Jack", "MICBIAS1",
1200 "IN2P", "Mic Jack";
968 1201
969 nvidia,i2s-controller = <&tegra_i2s1>; 1202 nvidia,i2s-controller = <&tegra_i2s1>;
970 nvidia,audio-codec = <&rt5640>; 1203 nvidia,audio-codec = <&rt5640>;
diff --git a/arch/arm/boot/dts/tegra114-pluto.dts b/arch/arm/boot/dts/tegra114-pluto.dts
deleted file mode 100644
index d5f8d3e0bde2..000000000000
--- a/arch/arm/boot/dts/tegra114-pluto.dts
+++ /dev/null
@@ -1,33 +0,0 @@
1/dts-v1/;
2
3#include "tegra114.dtsi"
4
5/ {
6 model = "NVIDIA Tegra114 Pluto evaluation board";
7 compatible = "nvidia,pluto", "nvidia,tegra114";
8
9 memory {
10 reg = <0x80000000 0x40000000>;
11 };
12
13 serial@70006300 {
14 status = "okay";
15 };
16
17 pmc {
18 nvidia,invert-interrupt;
19 };
20
21 clocks {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 clk32k_in: clock {
27 compatible = "fixed-clock";
28 reg=<0>;
29 #clock-cells = <0>;
30 clock-frequency = <32768>;
31 };
32 };
33};
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index abf6c40d28c6..2905145d8e59 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -430,6 +430,68 @@
430 status = "disable"; 430 status = "disable";
431 }; 431 };
432 432
433 usb@7d000000 {
434 compatible = "nvidia,tegra30-ehci", "usb-ehci";
435 reg = <0x7d000000 0x4000>;
436 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
437 phy_type = "utmi";
438 clocks = <&tegra_car TEGRA114_CLK_USBD>;
439 nvidia,phy = <&phy1>;
440 status = "disabled";
441 };
442
443 phy1: usb-phy@7d000000 {
444 compatible = "nvidia,tegra30-usb-phy";
445 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
446 phy_type = "utmi";
447 clocks = <&tegra_car TEGRA114_CLK_USBD>,
448 <&tegra_car TEGRA114_CLK_PLL_U>,
449 <&tegra_car TEGRA114_CLK_USBD>;
450 clock-names = "reg", "pll_u", "utmi-pads";
451 nvidia,hssync-start-delay = <0>;
452 nvidia,idle-wait-delay = <17>;
453 nvidia,elastic-limit = <16>;
454 nvidia,term-range-adj = <6>;
455 nvidia,xcvr-setup = <9>;
456 nvidia,xcvr-lsfslew = <0>;
457 nvidia,xcvr-lsrslew = <3>;
458 nvidia,hssquelch-level = <2>;
459 nvidia,hsdiscon-level = <5>;
460 nvidia,xcvr-hsslew = <12>;
461 status = "disabled";
462 };
463
464 usb@7d008000 {
465 compatible = "nvidia,tegra30-ehci", "usb-ehci";
466 reg = <0x7d008000 0x4000>;
467 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
468 phy_type = "utmi";
469 clocks = <&tegra_car TEGRA114_CLK_USB3>;
470 nvidia,phy = <&phy3>;
471 status = "disabled";
472 };
473
474 phy3: usb-phy@7d008000 {
475 compatible = "nvidia,tegra30-usb-phy";
476 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
477 phy_type = "utmi";
478 clocks = <&tegra_car TEGRA114_CLK_USB3>,
479 <&tegra_car TEGRA114_CLK_PLL_U>,
480 <&tegra_car TEGRA114_CLK_USBD>;
481 clock-names = "reg", "pll_u", "utmi-pads";
482 nvidia,hssync-start-delay = <0>;
483 nvidia,idle-wait-delay = <17>;
484 nvidia,elastic-limit = <16>;
485 nvidia,term-range-adj = <6>;
486 nvidia,xcvr-setup = <9>;
487 nvidia,xcvr-lsfslew = <0>;
488 nvidia,xcvr-lsrslew = <3>;
489 nvidia,hssquelch-level = <2>;
490 nvidia,hsdiscon-level = <5>;
491 nvidia,xcvr-hsslew = <12>;
492 status = "disabled";
493 };
494
433 cpus { 495 cpus {
434 #address-cells = <1>; 496 #address-cells = <1>;
435 #size-cells = <0>; 497 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/tegra20-colibri-512.dtsi b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
index 5592be6f2f7a..d5c9bca01232 100644
--- a/arch/arm/boot/dts/tegra20-colibri-512.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri-512.dtsi
@@ -363,7 +363,7 @@
363 }; 363 };
364 364
365 pmc { 365 pmc {
366 nvidia,suspend-mode = <2>; 366 nvidia,suspend-mode = <1>;
367 nvidia,cpu-pwr-good-time = <5000>; 367 nvidia,cpu-pwr-good-time = <5000>;
368 nvidia,cpu-pwr-off-time = <5000>; 368 nvidia,cpu-pwr-off-time = <5000>;
369 nvidia,core-pwr-good-time = <3845 3845>; 369 nvidia,core-pwr-good-time = <3845 3845>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index d9f89cd879a7..e156ab30e763 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -335,7 +335,7 @@
335 regulator-always-on; 335 regulator-always-on;
336 }; 336 };
337 337
338 ldo0 { 338 pci_clk_reg: ldo0 {
339 regulator-name = "vdd_ldo0,vddio_pex_clk"; 339 regulator-name = "vdd_ldo0,vddio_pex_clk";
340 regulator-min-microvolt = <3300000>; 340 regulator-min-microvolt = <3300000>;
341 regulator-max-microvolt = <3300000>; 341 regulator-max-microvolt = <3300000>;
@@ -417,7 +417,7 @@
417 417
418 pmc { 418 pmc {
419 nvidia,invert-interrupt; 419 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <2>; 420 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <5000>; 421 nvidia,cpu-pwr-good-time = <5000>;
422 nvidia,cpu-pwr-off-time = <5000>; 422 nvidia,cpu-pwr-off-time = <5000>;
423 nvidia,core-pwr-good-time = <3845 3845>; 423 nvidia,core-pwr-good-time = <3845 3845>;
@@ -425,6 +425,20 @@
425 nvidia,sys-clock-req-active-high; 425 nvidia,sys-clock-req-active-high;
426 }; 426 };
427 427
428 pcie-controller {
429 pex-clk-supply = <&pci_clk_reg>;
430 vdd-supply = <&pci_vdd_reg>;
431 status = "okay";
432
433 pci@1,0 {
434 status = "okay";
435 };
436
437 pci@2,0 {
438 status = "okay";
439 };
440 };
441
428 usb@c5000000 { 442 usb@c5000000 {
429 status = "okay"; 443 status = "okay";
430 }; 444 };
@@ -643,7 +657,7 @@
643 enable-active-high; 657 enable-active-high;
644 }; 658 };
645 659
646 regulator@3 { 660 pci_vdd_reg: regulator@3 {
647 compatible = "regulator-fixed"; 661 compatible = "regulator-fixed";
648 reg = <3>; 662 reg = <3>;
649 regulator-name = "vdd_1v05"; 663 regulator-name = "vdd_1v05";
@@ -651,8 +665,6 @@
651 regulator-max-microvolt = <1050000>; 665 regulator-max-microvolt = <1050000>;
652 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; 666 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
653 enable-active-high; 667 enable-active-high;
654 /* Hack until board-harmony-pcie.c is removed */
655 status = "disabled";
656 }; 668 };
657 669
658 regulator@4 { 670 regulator@4 {
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index cfd12763b1b2..8d71fc9d8a2f 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -417,7 +417,7 @@
417 417
418 pmc { 418 pmc {
419 nvidia,invert-interrupt; 419 nvidia,invert-interrupt;
420 nvidia,suspend-mode = <2>; 420 nvidia,suspend-mode = <1>;
421 nvidia,cpu-pwr-good-time = <2000>; 421 nvidia,cpu-pwr-good-time = <2000>;
422 nvidia,cpu-pwr-off-time = <0>; 422 nvidia,cpu-pwr-off-time = <0>;
423 nvidia,core-pwr-good-time = <3845 3845>; 423 nvidia,core-pwr-good-time = <3845 3845>;
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index c8242533268f..315aae26c3cd 100644
--- a/arch/arm/boot/dts/tegra20-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -518,7 +518,7 @@
518 518
519 pmc { 519 pmc {
520 nvidia,invert-interrupt; 520 nvidia,invert-interrupt;
521 nvidia,suspend-mode = <2>; 521 nvidia,suspend-mode = <1>;
522 nvidia,cpu-pwr-good-time = <5000>; 522 nvidia,cpu-pwr-good-time = <5000>;
523 nvidia,cpu-pwr-off-time = <5000>; 523 nvidia,cpu-pwr-off-time = <5000>;
524 nvidia,core-pwr-good-time = <3845 3845>; 524 nvidia,core-pwr-good-time = <3845 3845>;
@@ -828,7 +828,7 @@
828 regulator-min-microvolt = <5000000>; 828 regulator-min-microvolt = <5000000>;
829 regulator-max-microvolt = <5000000>; 829 regulator-max-microvolt = <5000000>;
830 enable-active-high; 830 enable-active-high;
831 gpio = <&gpio 24 0>; /* PD0 */ 831 gpio = <&gpio TEGRA_GPIO(D, 0) 0>;
832 regulator-always-on; 832 regulator-always-on;
833 regulator-boot-on; 833 regulator-boot-on;
834 }; 834 };
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index c54faae7cfb3..7726dab3d08d 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -366,7 +366,7 @@
366 regulator-always-on; 366 regulator-always-on;
367 }; 367 };
368 368
369 ldo0 { 369 pci_clk_reg: ldo0 {
370 regulator-name = "vdd_ldo0,vddio_pex_clk"; 370 regulator-name = "vdd_ldo0,vddio_pex_clk";
371 regulator-min-microvolt = <3300000>; 371 regulator-min-microvolt = <3300000>;
372 regulator-max-microvolt = <3300000>; 372 regulator-max-microvolt = <3300000>;
@@ -459,7 +459,7 @@
459 459
460 pmc { 460 pmc {
461 nvidia,invert-interrupt; 461 nvidia,invert-interrupt;
462 nvidia,suspend-mode = <2>; 462 nvidia,suspend-mode = <1>;
463 nvidia,cpu-pwr-good-time = <5000>; 463 nvidia,cpu-pwr-good-time = <5000>;
464 nvidia,cpu-pwr-off-time = <5000>; 464 nvidia,cpu-pwr-off-time = <5000>;
465 nvidia,core-pwr-good-time = <3845 3845>; 465 nvidia,core-pwr-good-time = <3845 3845>;
@@ -467,6 +467,11 @@
467 nvidia,sys-clock-req-active-high; 467 nvidia,sys-clock-req-active-high;
468 }; 468 };
469 469
470 pcie-controller {
471 pex-clk-supply = <&pci_clk_reg>;
472 vdd-supply = <&pci_vdd_reg>;
473 };
474
470 usb@c5008000 { 475 usb@c5008000 {
471 status = "okay"; 476 status = "okay";
472 }; 477 };
@@ -509,5 +514,15 @@
509 regulator-max-microvolt = <5000000>; 514 regulator-max-microvolt = <5000000>;
510 regulator-always-on; 515 regulator-always-on;
511 }; 516 };
517
518 pci_vdd_reg: regulator@1 {
519 compatible = "regulator-fixed";
520 reg = <1>;
521 regulator-name = "vdd_1v05";
522 regulator-min-microvolt = <1050000>;
523 regulator-max-microvolt = <1050000>;
524 gpio = <&pmic 2 0>;
525 enable-active-high;
526 };
512 }; 527 };
513}; 528};
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index c572c43751b1..3ada3cb67f07 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -32,6 +32,14 @@
32 }; 32 };
33 }; 33 };
34 34
35 pcie-controller {
36 status = "okay";
37
38 pci@1,0 {
39 status = "okay";
40 };
41 };
42
35 sound { 43 sound {
36 compatible = "ad,tegra-audio-wm8903-tec", 44 compatible = "ad,tegra-audio-wm8903-tec",
37 "nvidia,tegra-audio-wm8903"; 45 "nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 1e9d33adb925..78deea5c0d21 100644
--- a/arch/arm/boot/dts/tegra20-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
@@ -302,7 +302,7 @@
302 }; 302 };
303 303
304 pmc { 304 pmc {
305 nvidia,suspend-mode = <2>; 305 nvidia,suspend-mode = <1>;
306 nvidia,cpu-pwr-good-time = <5000>; 306 nvidia,cpu-pwr-good-time = <5000>;
307 nvidia,cpu-pwr-off-time = <5000>; 307 nvidia,cpu-pwr-off-time = <5000>;
308 nvidia,core-pwr-good-time = <3845 3845>; 308 nvidia,core-pwr-good-time = <3845 3845>;
@@ -310,6 +310,16 @@
310 nvidia,sys-clock-req-active-high; 310 nvidia,sys-clock-req-active-high;
311 }; 311 };
312 312
313 pcie-controller {
314 status = "okay";
315 pex-clk-supply = <&pci_clk_reg>;
316 vdd-supply = <&pci_vdd_reg>;
317
318 pci@1,0 {
319 status = "okay";
320 };
321 };
322
313 usb@c5000000 { 323 usb@c5000000 {
314 status = "okay"; 324 status = "okay";
315 }; 325 };
@@ -410,10 +420,28 @@
410 regulator-min-microvolt = <5000000>; 420 regulator-min-microvolt = <5000000>;
411 regulator-max-microvolt = <5000000>; 421 regulator-max-microvolt = <5000000>;
412 enable-active-high; 422 enable-active-high;
413 gpio = <&gpio 170 0>; /* PV2 */ 423 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
414 regulator-always-on; 424 regulator-always-on;
415 regulator-boot-on; 425 regulator-boot-on;
416 }; 426 };
427
428 pci_clk_reg: regulator@3 {
429 compatible = "regulator-fixed";
430 reg = <3>;
431 regulator-name = "pci_clk";
432 regulator-min-microvolt = <3300000>;
433 regulator-max-microvolt = <3300000>;
434 regulator-always-on;
435 };
436
437 pci_vdd_reg: regulator@4 {
438 compatible = "regulator-fixed";
439 reg = <4>;
440 regulator-name = "pci_vdd";
441 regulator-min-microvolt = <1050000>;
442 regulator-max-microvolt = <1050000>;
443 regulator-always-on;
444 };
417 }; 445 };
418 446
419 sound { 447 sound {
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 7f8c28d1121f..aab872cd0530 100644
--- a/arch/arm/boot/dts/tegra20-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -494,7 +494,7 @@
494 494
495 pmc { 495 pmc {
496 nvidia,invert-interrupt; 496 nvidia,invert-interrupt;
497 nvidia,suspend-mode = <2>; 497 nvidia,suspend-mode = <1>;
498 nvidia,cpu-pwr-good-time = <2000>; 498 nvidia,cpu-pwr-good-time = <2000>;
499 nvidia,cpu-pwr-off-time = <100>; 499 nvidia,cpu-pwr-off-time = <100>;
500 nvidia,core-pwr-good-time = <3845 3845>; 500 nvidia,core-pwr-good-time = <3845 3845>;
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
index c703197dca6e..d33a73cf167c 100644
--- a/arch/arm/boot/dts/tegra20-whistler.dts
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -497,7 +497,7 @@
497 497
498 pmc { 498 pmc {
499 nvidia,invert-interrupt; 499 nvidia,invert-interrupt;
500 nvidia,suspend-mode = <2>; 500 nvidia,suspend-mode = <1>;
501 nvidia,cpu-pwr-good-time = <2000>; 501 nvidia,cpu-pwr-good-time = <2000>;
502 nvidia,cpu-pwr-off-time = <1000>; 502 nvidia,cpu-pwr-off-time = <1000>;
503 nvidia,core-pwr-good-time = <0 3845>; 503 nvidia,core-pwr-good-time = <0 3845>;
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index e4570834512e..df40b54fd8bc 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -455,6 +455,61 @@
455 #size-cells = <0>; 455 #size-cells = <0>;
456 }; 456 };
457 457
458 pcie-controller {
459 compatible = "nvidia,tegra20-pcie";
460 device_type = "pci";
461 reg = <0x80003000 0x00000800 /* PADS registers */
462 0x80003800 0x00000200 /* AFI registers */
463 0x90000000 0x10000000>; /* configuration space */
464 reg-names = "pads", "afi", "cs";
465 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
466 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
467 interrupt-names = "intr", "msi";
468
469 bus-range = <0x00 0xff>;
470 #address-cells = <3>;
471 #size-cells = <2>;
472
473 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
474 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
475 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
476 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
477 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
478
479 clocks = <&tegra_car TEGRA20_CLK_PEX>,
480 <&tegra_car TEGRA20_CLK_AFI>,
481 <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
482 <&tegra_car TEGRA20_CLK_PLL_E>;
483 clock-names = "pex", "afi", "pcie_xclk", "pll_e";
484 status = "disabled";
485
486 pci@1,0 {
487 device_type = "pci";
488 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
489 reg = <0x000800 0 0 0 0>;
490 status = "disabled";
491
492 #address-cells = <3>;
493 #size-cells = <2>;
494 ranges;
495
496 nvidia,num-lanes = <2>;
497 };
498
499 pci@2,0 {
500 device_type = "pci";
501 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
502 reg = <0x001000 0 0 0 0>;
503 status = "disabled";
504
505 #address-cells = <3>;
506 #size-cells = <2>;
507 ranges;
508
509 nvidia,num-lanes = <2>;
510 };
511 };
512
458 usb@c5000000 { 513 usb@c5000000 {
459 compatible = "nvidia,tegra20-ehci", "usb-ehci"; 514 compatible = "nvidia,tegra20-ehci", "usb-ehci";
460 reg = <0xc5000000 0x4000>; 515 reg = <0xc5000000 0x4000>;
diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index 87c5f7b7c271..08cad696e89f 100644
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -10,6 +10,40 @@
10 reg = <0x80000000 0x7ff00000>; 10 reg = <0x80000000 0x7ff00000>;
11 }; 11 };
12 12
13 pcie-controller {
14 status = "okay";
15 pex-clk-supply = <&sys_3v3_pexs_reg>;
16 vdd-supply = <&ldo1_reg>;
17 avdd-supply = <&ldo2_reg>;
18
19 pci@1,0 {
20 status = "okay";
21 nvidia,num-lanes = <2>;
22 };
23
24 pci@2,0 {
25 nvidia,num-lanes = <2>;
26 };
27
28 pci@3,0 {
29 status = "okay";
30 nvidia,num-lanes = <2>;
31 };
32 };
33
34 host1x {
35 hdmi {
36 status = "okay";
37
38 vdd-supply = <&sys_3v3_reg>;
39 pll-supply = <&vio_reg>;
40
41 nvidia,hpd-gpio =
42 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
43 nvidia,ddc-i2c-bus = <&hdmiddc>;
44 };
45 };
46
13 pinmux { 47 pinmux {
14 pinctrl-names = "default"; 48 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>; 49 pinctrl-0 = <&state_default>;
@@ -76,6 +110,11 @@
76 nvidia,pull = <0>; 110 nvidia,pull = <0>;
77 nvidia,tristate = <0>; 111 nvidia,tristate = <0>;
78 }; 112 };
113 pex_l1_prsnt_n_pdd4 {
114 nvidia,pins = "pex_l1_prsnt_n_pdd4",
115 "pex_l1_clkreq_n_pdd6";
116 nvidia,pull = <2>;
117 };
79 sdio3 { 118 sdio3 {
80 nvidia,pins = "drive_sdio3"; 119 nvidia,pins = "drive_sdio3";
81 nvidia,high-speed-mode = <0>; 120 nvidia,high-speed-mode = <0>;
@@ -85,6 +124,10 @@
85 nvidia,slew-rate-rising = <1>; 124 nvidia,slew-rate-rising = <1>;
86 nvidia,slew-rate-falling = <1>; 125 nvidia,slew-rate-falling = <1>;
87 }; 126 };
127 gpv {
128 nvidia,pins = "drive_gpv";
129 nvidia,pull-up-strength = <16>;
130 };
88 }; 131 };
89 }; 132 };
90 133
@@ -107,7 +150,7 @@
107 clock-frequency = <100000>; 150 clock-frequency = <100000>;
108 }; 151 };
109 152
110 i2c@7000c700 { 153 hdmiddc: i2c@7000c700 {
111 status = "okay"; 154 status = "okay";
112 clock-frequency = <100000>; 155 clock-frequency = <100000>;
113 }; 156 };
@@ -262,7 +305,7 @@
262 pmc { 305 pmc {
263 status = "okay"; 306 status = "okay";
264 nvidia,invert-interrupt; 307 nvidia,invert-interrupt;
265 nvidia,suspend-mode = <2>; 308 nvidia,suspend-mode = <1>;
266 nvidia,cpu-pwr-good-time = <2000>; 309 nvidia,cpu-pwr-good-time = <2000>;
267 nvidia,cpu-pwr-off-time = <200>; 310 nvidia,cpu-pwr-off-time = <200>;
268 nvidia,core-pwr-good-time = <3845 3845>; 311 nvidia,core-pwr-good-time = <3845 3845>;
@@ -285,6 +328,15 @@
285 non-removable; 328 non-removable;
286 }; 329 };
287 330
331 usb@7d008000 {
332 status = "okay";
333 };
334
335 usb-phy@7d008000 {
336 vbus-supply = <&usb3_vbus_reg>;
337 status = "okay";
338 };
339
288 clocks { 340 clocks {
289 compatible = "simple-bus"; 341 compatible = "simple-bus";
290 #address-cells = <1>; 342 #address-cells = <1>;
@@ -357,7 +409,7 @@
357 regulator-min-microvolt = <5000000>; 409 regulator-min-microvolt = <5000000>;
358 regulator-max-microvolt = <5000000>; 410 regulator-max-microvolt = <5000000>;
359 enable-active-high; 411 enable-active-high;
360 gpio = <&gpio TEGRA_GPIO(I, 4) GPIO_ACTIVE_HIGH>; 412 gpio = <&gpio TEGRA_GPIO(DD, 6) GPIO_ACTIVE_HIGH>;
361 gpio-open-drain; 413 gpio-open-drain;
362 vin-supply = <&vdd_5v_in_reg>; 414 vin-supply = <&vdd_5v_in_reg>;
363 }; 415 };
@@ -369,7 +421,7 @@
369 regulator-min-microvolt = <5000000>; 421 regulator-min-microvolt = <5000000>;
370 regulator-max-microvolt = <5000000>; 422 regulator-max-microvolt = <5000000>;
371 enable-active-high; 423 enable-active-high;
372 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; 424 gpio = <&gpio TEGRA_GPIO(DD, 4) GPIO_ACTIVE_HIGH>;
373 gpio-open-drain; 425 gpio-open-drain;
374 vin-supply = <&vdd_5v_in_reg>; 426 vin-supply = <&vdd_5v_in_reg>;
375 }; 427 };
@@ -421,7 +473,9 @@
421 473
422 nvidia,audio-routing = 474 nvidia,audio-routing =
423 "Headphones", "HPOR", 475 "Headphones", "HPOR",
424 "Headphones", "HPOL"; 476 "Headphones", "HPOL",
477 "Mic Jack", "MICBIAS1",
478 "IN2P", "Mic Jack";
425 479
426 nvidia,i2s-controller = <&tegra_i2s1>; 480 nvidia,i2s-controller = <&tegra_i2s1>;
427 nvidia,audio-codec = <&rt5640>; 481 nvidia,audio-codec = <&rt5640>;
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi
index f65b53d32416..e19dbf238e5c 100644
--- a/arch/arm/boot/dts/tegra30-cardhu.dtsi
+++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi
@@ -31,6 +31,26 @@
31 reg = <0x80000000 0x40000000>; 31 reg = <0x80000000 0x40000000>;
32 }; 32 };
33 33
34 pcie-controller {
35 status = "okay";
36 pex-clk-supply = <&pex_hvdd_3v3_reg>;
37 vdd-supply = <&ldo1_reg>;
38 avdd-supply = <&ldo2_reg>;
39
40 pci@1,0 {
41 nvidia,num-lanes = <4>;
42 };
43
44 pci@2,0 {
45 nvidia,num-lanes = <1>;
46 };
47
48 pci@3,0 {
49 status = "okay";
50 nvidia,num-lanes = <1>;
51 };
52 };
53
34 pinmux { 54 pinmux {
35 pinctrl-names = "default"; 55 pinctrl-names = "default";
36 pinctrl-0 = <&state_default>; 56 pinctrl-0 = <&state_default>;
@@ -173,19 +193,6 @@
173 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; 193 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
174 }; 194 };
175 195
176 tps62361 {
177 compatible = "ti,tps62361";
178 reg = <0x60>;
179
180 regulator-name = "tps62361-vout";
181 regulator-min-microvolt = <500000>;
182 regulator-max-microvolt = <1500000>;
183 regulator-boot-on;
184 regulator-always-on;
185 ti,vsel0-state-high;
186 ti,vsel1-state-high;
187 };
188
189 pmic: tps65911@2d { 196 pmic: tps65911@2d {
190 compatible = "ti,tps65911"; 197 compatible = "ti,tps65911";
191 reg = <0x2d>; 198 reg = <0x2d>;
@@ -286,6 +293,26 @@
286 }; 293 };
287 }; 294 };
288 }; 295 };
296
297 nct1008 {
298 compatible = "onnn,nct1008";
299 reg = <0x4c>;
300 interrupt-parent = <&gpio>;
301 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
302 };
303
304 tps62361 {
305 compatible = "ti,tps62361";
306 reg = <0x60>;
307
308 regulator-name = "tps62361-vout";
309 regulator-min-microvolt = <500000>;
310 regulator-max-microvolt = <1500000>;
311 regulator-boot-on;
312 regulator-always-on;
313 ti,vsel0-state-high;
314 ti,vsel1-state-high;
315 };
289 }; 316 };
290 317
291 spi@7000da00 { 318 spi@7000da00 {
@@ -307,7 +334,7 @@
307 pmc { 334 pmc {
308 status = "okay"; 335 status = "okay";
309 nvidia,invert-interrupt; 336 nvidia,invert-interrupt;
310 nvidia,suspend-mode = <2>; 337 nvidia,suspend-mode = <1>;
311 nvidia,cpu-pwr-good-time = <2000>; 338 nvidia,cpu-pwr-good-time = <2000>;
312 nvidia,cpu-pwr-off-time = <200>; 339 nvidia,cpu-pwr-off-time = <200>;
313 nvidia,core-pwr-good-time = <3845 3845>; 340 nvidia,core-pwr-good-time = <3845 3845>;
@@ -330,6 +357,15 @@
330 non-removable; 357 non-removable;
331 }; 358 };
332 359
360 usb@7d008000 {
361 status = "okay";
362 };
363
364 usb-phy@7d008000 {
365 vbus-supply = <&usb3_vbus_reg>;
366 status = "okay";
367 };
368
333 clocks { 369 clocks {
334 compatible = "simple-bus"; 370 compatible = "simple-bus";
335 #address-cells = <1>; 371 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index d8783f0fae63..0022c127e1d9 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -16,6 +16,76 @@
16 serial4 = &uarte; 16 serial4 = &uarte;
17 }; 17 };
18 18
19 pcie-controller {
20 compatible = "nvidia,tegra30-pcie";
21 device_type = "pci";
22 reg = <0x00003000 0x00000800 /* PADS registers */
23 0x00003800 0x00000200 /* AFI registers */
24 0x10000000 0x10000000>; /* configuration space */
25 reg-names = "pads", "afi", "cs";
26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
27 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
28 interrupt-names = "intr", "msi";
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
36 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
37 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
38 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
39 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
40
41 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
42 <&tegra_car TEGRA30_CLK_AFI>,
43 <&tegra_car TEGRA30_CLK_PCIEX>,
44 <&tegra_car TEGRA30_CLK_PLL_E>,
45 <&tegra_car TEGRA30_CLK_CML0>;
46 clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
47 status = "disabled";
48
49 pci@1,0 {
50 device_type = "pci";
51 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
52 reg = <0x000800 0 0 0 0>;
53 status = "disabled";
54
55 #address-cells = <3>;
56 #size-cells = <2>;
57 ranges;
58
59 nvidia,num-lanes = <2>;
60 };
61
62 pci@2,0 {
63 device_type = "pci";
64 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
65 reg = <0x001000 0 0 0 0>;
66 status = "disabled";
67
68 #address-cells = <3>;
69 #size-cells = <2>;
70 ranges;
71
72 nvidia,num-lanes = <2>;
73 };
74
75 pci@3,0 {
76 device_type = "pci";
77 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
78 reg = <0x001800 0 0 0 0>;
79 status = "disabled";
80
81 #address-cells = <3>;
82 #size-cells = <2>;
83 ranges;
84
85 nvidia,num-lanes = <2>;
86 };
87 };
88
19 host1x { 89 host1x {
20 compatible = "nvidia,tegra30-host1x", "simple-bus"; 90 compatible = "nvidia,tegra30-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>; 91 reg = <0x50000000 0x00024000>;
@@ -561,6 +631,92 @@
561 status = "disabled"; 631 status = "disabled";
562 }; 632 };
563 633
634 usb@7d000000 {
635 compatible = "nvidia,tegra30-ehci", "usb-ehci";
636 reg = <0x7d000000 0x4000>;
637 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
638 phy_type = "utmi";
639 clocks = <&tegra_car TEGRA30_CLK_USBD>;
640 nvidia,needs-double-reset;
641 nvidia,phy = <&phy1>;
642 status = "disabled";
643 };
644
645 phy1: usb-phy@7d000000 {
646 compatible = "nvidia,tegra30-usb-phy";
647 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
648 phy_type = "utmi";
649 clocks = <&tegra_car TEGRA30_CLK_USBD>,
650 <&tegra_car TEGRA30_CLK_PLL_U>,
651 <&tegra_car TEGRA30_CLK_USBD>;
652 clock-names = "reg", "pll_u", "utmi-pads";
653 nvidia,hssync-start-delay = <9>;
654 nvidia,idle-wait-delay = <17>;
655 nvidia,elastic-limit = <16>;
656 nvidia,term-range-adj = <6>;
657 nvidia,xcvr-setup = <51>;
658 nvidia.xcvr-setup-use-fuses;
659 nvidia,xcvr-lsfslew = <1>;
660 nvidia,xcvr-lsrslew = <1>;
661 nvidia,xcvr-hsslew = <32>;
662 nvidia,hssquelch-level = <2>;
663 nvidia,hsdiscon-level = <5>;
664 status = "disabled";
665 };
666
667 usb@7d004000 {
668 compatible = "nvidia,tegra30-ehci", "usb-ehci";
669 reg = <0x7d004000 0x4000>;
670 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
671 phy_type = "ulpi";
672 clocks = <&tegra_car TEGRA30_CLK_USB2>;
673 nvidia,phy = <&phy2>;
674 status = "disabled";
675 };
676
677 phy2: usb-phy@7d004000 {
678 compatible = "nvidia,tegra30-usb-phy";
679 reg = <0x7d004000 0x4000>;
680 phy_type = "ulpi";
681 clocks = <&tegra_car TEGRA30_CLK_USB2>,
682 <&tegra_car TEGRA30_CLK_PLL_U>,
683 <&tegra_car TEGRA30_CLK_CDEV2>;
684 clock-names = "reg", "pll_u", "ulpi-link";
685 status = "disabled";
686 };
687
688 usb@7d008000 {
689 compatible = "nvidia,tegra30-ehci", "usb-ehci";
690 reg = <0x7d008000 0x4000>;
691 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
692 phy_type = "utmi";
693 clocks = <&tegra_car TEGRA30_CLK_USB3>;
694 nvidia,phy = <&phy3>;
695 status = "disabled";
696 };
697
698 phy3: usb-phy@7d008000 {
699 compatible = "nvidia,tegra30-usb-phy";
700 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
701 phy_type = "utmi";
702 clocks = <&tegra_car TEGRA30_CLK_USB3>,
703 <&tegra_car TEGRA30_CLK_PLL_U>,
704 <&tegra_car TEGRA30_CLK_USBD>;
705 clock-names = "reg", "pll_u", "utmi-pads";
706 nvidia,hssync-start-delay = <0>;
707 nvidia,idle-wait-delay = <17>;
708 nvidia,elastic-limit = <16>;
709 nvidia,term-range-adj = <6>;
710 nvidia,xcvr-setup = <51>;
711 nvidia.xcvr-setup-use-fuses;
712 nvidia,xcvr-lsfslew = <2>;
713 nvidia,xcvr-lsrslew = <2>;
714 nvidia,xcvr-hsslew = <32>;
715 nvidia,hssquelch-level = <2>;
716 nvidia,hsdiscon-level = <5>;
717 status = "disabled";
718 };
719
564 cpus { 720 cpus {
565 #address-cells = <1>; 721 #address-cells = <1>;
566 #size-cells = <0>; 722 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/u9540.dts b/arch/arm/boot/dts/u9540.dts
deleted file mode 100644
index 95892ec6c342..000000000000
--- a/arch/arm/boot/dts/u9540.dts
+++ /dev/null
@@ -1,72 +0,0 @@
1/*
2 * Copyright 2012 ST-Ericsson AB
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "dbx5x0.dtsi"
14
15/ {
16 model = "ST-Ericsson U9540 platform with Device Tree";
17 compatible = "st-ericsson,u9540";
18
19 memory {
20 reg = <0x00000000 0x20000000>;
21 };
22
23 soc-u9500 {
24 uart@80120000 {
25 status = "okay";
26 };
27
28 uart@80121000 {
29 status = "okay";
30 };
31
32 uart@80007000 {
33 status = "okay";
34 };
35
36 // External Micro SD slot
37 sdi0_per1@80126000 {
38 arm,primecell-periphid = <0x10480180>;
39 max-frequency = <100000000>;
40 bus-width = <4>;
41 mmc-cap-sd-highspeed;
42 mmc-cap-mmc-highspeed;
43 vmmc-supply = <&ab8500_ldo_aux3_reg>;
44
45 cd-gpios = <&gpio7 6 0x4>; // 230
46 cd-inverted;
47
48 status = "okay";
49 };
50
51
52 // WLAN SDIO channel
53 sdi1_per2@80118000 {
54 arm,primecell-periphid = <0x10480180>;
55 max-frequency = <50000000>;
56 bus-width = <4>;
57
58 status = "okay";
59 };
60
61 // On-board eMMC
62 sdi4_per2@80114000 {
63 arm,primecell-periphid = <0x10480180>;
64 max-frequency = <100000000>;
65 bus-width = <8>;
66 mmc-cap-mmc-highspeed;
67 vmmc-supply = <&ab8500_ldo_aux2_reg>;
68
69 status = "okay";
70 };
71 };
72};
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index d2803be4e1a8..15f98cbcb75a 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
37 device_type = "cpu"; 37 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 reg = <0>; 39 reg = <0>;
40 cci-control-port = <&cci_control1>;
40 }; 41 };
41 42
42 cpu1: cpu@1 { 43 cpu1: cpu@1 {
43 device_type = "cpu"; 44 device_type = "cpu";
44 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
45 reg = <1>; 46 reg = <1>;
47 cci-control-port = <&cci_control1>;
46 }; 48 };
47 49
48 cpu2: cpu@2 { 50 cpu2: cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
50 compatible = "arm,cortex-a7"; 52 compatible = "arm,cortex-a7";
51 reg = <0x100>; 53 reg = <0x100>;
54 cci-control-port = <&cci_control2>;
52 }; 55 };
53 56
54 cpu3: cpu@3 { 57 cpu3: cpu@3 {
55 device_type = "cpu"; 58 device_type = "cpu";
56 compatible = "arm,cortex-a7"; 59 compatible = "arm,cortex-a7";
57 reg = <0x101>; 60 reg = <0x101>;
61 cci-control-port = <&cci_control2>;
58 }; 62 };
59 63
60 cpu4: cpu@4 { 64 cpu4: cpu@4 {
61 device_type = "cpu"; 65 device_type = "cpu";
62 compatible = "arm,cortex-a7"; 66 compatible = "arm,cortex-a7";
63 reg = <0x102>; 67 reg = <0x102>;
68 cci-control-port = <&cci_control2>;
64 }; 69 };
65 }; 70 };
66 71
@@ -104,6 +109,26 @@
104 interrupts = <1 9 0xf04>; 109 interrupts = <1 9 0xf04>;
105 }; 110 };
106 111
112 cci@2c090000 {
113 compatible = "arm,cci-400";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0 0x2c090000 0 0x1000>;
117 ranges = <0x0 0x0 0x2c090000 0x10000>;
118
119 cci_control1: slave-if@4000 {
120 compatible = "arm,cci-400-ctrl-if";
121 interface-type = "ace";
122 reg = <0x4000 0x1000>;
123 };
124
125 cci_control2: slave-if@5000 {
126 compatible = "arm,cci-400-ctrl-if";
127 interface-type = "ace";
128 reg = <0x5000 0x1000>;
129 };
130 };
131
107 memory-controller@7ffd0000 { 132 memory-controller@7ffd0000 {
108 compatible = "arm,pl354", "arm,primecell"; 133 compatible = "arm,pl354", "arm,primecell";
109 reg = <0 0x7ffd0000 0 0x1000>; 134 reg = <0 0x7ffd0000 0 0x1000>;
@@ -125,6 +150,12 @@
125 clock-names = "apb_pclk"; 150 clock-names = "apb_pclk";
126 }; 151 };
127 152
153 scc@7fff0000 {
154 compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
155 reg = <0 0x7fff0000 0 0x1000>;
156 interrupts = <0 95 4>;
157 };
158
128 timer { 159 timer {
129 compatible = "arm,armv7-timer"; 160 compatible = "arm,armv7-timer";
130 interrupts = <1 13 0xf08>, 161 interrupts = <1 13 0xf08>,
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index b3905f5bcaf9..1a58678b93fa 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -50,6 +50,13 @@
50 status = "okay"; 50 status = "okay";
51}; 51};
52 52
53&i2c0 {
54 clock-frequency = <100000>;
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_i2c0_1>;
57 status = "okay";
58};
59
53&uart1 { 60&uart1 {
54 pinctrl-names = "default"; 61 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_uart1_1>; 62 pinctrl-0 = <&pinctrl_uart1_1>;
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 6f54a64850eb..e32b92b949d2 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -41,8 +41,8 @@
41 L2: cache-controller { 41 L2: cache-controller {
42 compatible = "arm,pl310-cache"; 42 compatible = "arm,pl310-cache";
43 reg = <0xF8F02000 0x1000>; 43 reg = <0xF8F02000 0x1000>;
44 arm,data-latency = <2 3 2>; 44 arm,data-latency = <3 2 2>;
45 arm,tag-latency = <2 3 2>; 45 arm,tag-latency = <2 2 2>;
46 cache-unified; 46 cache-unified;
47 cache-level = <2>; 47 cache-level = <2>;
48 }; 48 };
diff --git a/arch/arm/common/edma.c b/arch/arm/common/edma.c
index 39ad030ac0c7..117f955a2a06 100644
--- a/arch/arm/common/edma.c
+++ b/arch/arm/common/edma.c
@@ -1235,6 +1235,23 @@ void edma_resume(unsigned channel)
1235} 1235}
1236EXPORT_SYMBOL(edma_resume); 1236EXPORT_SYMBOL(edma_resume);
1237 1237
1238int edma_trigger_channel(unsigned channel)
1239{
1240 unsigned ctlr;
1241 unsigned int mask;
1242
1243 ctlr = EDMA_CTLR(channel);
1244 channel = EDMA_CHAN_SLOT(channel);
1245 mask = BIT(channel & 0x1f);
1246
1247 edma_shadow0_write_array(ctlr, SH_ESR, (channel >> 5), mask);
1248
1249 pr_debug("EDMA: ESR%d %08x\n", (channel >> 5),
1250 edma_shadow0_read_array(ctlr, SH_ESR, (channel >> 5)));
1251 return 0;
1252}
1253EXPORT_SYMBOL(edma_trigger_channel);
1254
1238/** 1255/**
1239 * edma_start - start dma on a channel 1256 * edma_start - start dma on a channel
1240 * @channel: channel being activated 1257 * @channel: channel being activated
diff --git a/arch/arm/configs/ag5evm_defconfig b/arch/arm/configs/ag5evm_defconfig
deleted file mode 100644
index 212ead354a6b..000000000000
--- a/arch/arm/configs/ag5evm_defconfig
+++ /dev/null
@@ -1,83 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_NAMESPACES=y
7# CONFIG_UTS_NS is not set
8# CONFIG_IPC_NS is not set
9# CONFIG_USER_NS is not set
10# CONFIG_PID_NS is not set
11CONFIG_BLK_DEV_INITRD=y
12CONFIG_INITRAMFS_SOURCE=""
13CONFIG_EXPERT=y
14CONFIG_SLAB=y
15# CONFIG_BLK_DEV_BSG is not set
16# CONFIG_IOSCHED_DEADLINE is not set
17# CONFIG_IOSCHED_CFQ is not set
18CONFIG_ARCH_SHMOBILE=y
19CONFIG_ARCH_SH73A0=y
20CONFIG_MACH_AG5EVM=y
21CONFIG_MEMORY_SIZE=0x10000000
22CONFIG_CPU_BPREDICT_DISABLE=y
23CONFIG_ARM_ERRATA_430973=y
24CONFIG_ARM_ERRATA_458693=y
25CONFIG_NO_HZ=y
26CONFIG_AEABI=y
27# CONFIG_OABI_COMPAT is not set
28CONFIG_HIGHMEM=y
29CONFIG_ZBOOT_ROM_TEXT=0x0
30CONFIG_ZBOOT_ROM_BSS=0x0
31CONFIG_CMDLINE="console=tty0 console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel"
32CONFIG_CMDLINE_FORCE=y
33CONFIG_KEXEC=y
34# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
35CONFIG_PM=y
36# CONFIG_SUSPEND is not set
37CONFIG_PM_RUNTIME=y
38CONFIG_NET=y
39CONFIG_PACKET=y
40CONFIG_UNIX=y
41CONFIG_INET=y
42# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
43# CONFIG_INET_XFRM_MODE_TUNNEL is not set
44# CONFIG_INET_XFRM_MODE_BEET is not set
45# CONFIG_INET_LRO is not set
46# CONFIG_INET_DIAG is not set
47# CONFIG_IPV6 is not set
48# CONFIG_WIRELESS is not set
49CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
50# CONFIG_BLK_DEV is not set
51CONFIG_NETDEVICES=y
52CONFIG_NET_ETHERNET=y
53CONFIG_SMSC911X=y
54# CONFIG_NETDEV_1000 is not set
55# CONFIG_NETDEV_10000 is not set
56# CONFIG_WLAN is not set
57CONFIG_INPUT_SPARSEKMAP=y
58# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
59CONFIG_INPUT_EVDEV=y
60# CONFIG_INPUT_KEYBOARD is not set
61# CONFIG_INPUT_MOUSE is not set
62CONFIG_SERIAL_SH_SCI=y
63CONFIG_SERIAL_SH_SCI_NR_UARTS=9
64CONFIG_SERIAL_SH_SCI_CONSOLE=y
65# CONFIG_LEGACY_PTYS is not set
66# CONFIG_HW_RANDOM is not set
67CONFIG_I2C=y
68CONFIG_I2C_SH_MOBILE=y
69# CONFIG_HWMON is not set
70# CONFIG_MFD_SUPPORT is not set
71CONFIG_FB=y
72CONFIG_FB_SH_MOBILE_LCDC=y
73CONFIG_FRAMEBUFFER_CONSOLE=y
74CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
75# CONFIG_HID_SUPPORT is not set
76# CONFIG_USB_SUPPORT is not set
77# CONFIG_DNOTIFY is not set
78# CONFIG_INOTIFY_USER is not set
79CONFIG_TMPFS=y
80# CONFIG_MISC_FILESYSTEMS is not set
81CONFIG_MAGIC_SYSRQ=y
82CONFIG_DEBUG_KERNEL=y
83# CONFIG_FTRACE is not set
diff --git a/arch/arm/configs/ape6evm_defconfig b/arch/arm/configs/ape6evm_defconfig
index dab5a7dfadc6..1ce39940795d 100644
--- a/arch/arm/configs/ape6evm_defconfig
+++ b/arch/arm/configs/ape6evm_defconfig
@@ -54,7 +54,8 @@ CONFIG_NETDEVICES=y
54CONFIG_SMC91X=y 54CONFIG_SMC91X=y
55CONFIG_SMSC911X=y 55CONFIG_SMSC911X=y
56# CONFIG_INPUT_MOUSEDEV is not set 56# CONFIG_INPUT_MOUSEDEV is not set
57# CONFIG_INPUT_KEYBOARD is not set 57CONFIG_INPUT_EVDEV=y
58CONFIG_KEYBOARD_GPIO=y
58# CONFIG_INPUT_MOUSE is not set 59# CONFIG_INPUT_MOUSE is not set
59# CONFIG_SERIO is not set 60# CONFIG_SERIO is not set
60CONFIG_SERIAL_NONSTANDARD=y 61CONFIG_SERIAL_NONSTANDARD=y
@@ -71,6 +72,9 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
71CONFIG_REGULATOR_GPIO=y 72CONFIG_REGULATOR_GPIO=y
72# CONFIG_HID is not set 73# CONFIG_HID is not set
73# CONFIG_USB_SUPPORT is not set 74# CONFIG_USB_SUPPORT is not set
75CONFIG_NEW_LEDS=y
76CONFIG_LEDS_CLASS=y
77CONFIG_LEDS_GPIO=y
74# CONFIG_IOMMU_SUPPORT is not set 78# CONFIG_IOMMU_SUPPORT is not set
75# CONFIG_DNOTIFY is not set 79# CONFIG_DNOTIFY is not set
76CONFIG_TMPFS=y 80CONFIG_TMPFS=y
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 75fd842d4071..690e89273230 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -14,11 +14,13 @@ CONFIG_MODULE_UNLOAD=y
14# CONFIG_IOSCHED_DEADLINE is not set 14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_AT91=y 16CONFIG_ARCH_AT91=y
17CONFIG_SOC_AT91RM9200=y
17CONFIG_SOC_AT91SAM9260=y 18CONFIG_SOC_AT91SAM9260=y
18CONFIG_SOC_AT91SAM9263=y 19CONFIG_SOC_AT91SAM9263=y
19CONFIG_SOC_AT91SAM9G45=y 20CONFIG_SOC_AT91SAM9G45=y
20CONFIG_SOC_AT91SAM9X5=y 21CONFIG_SOC_AT91SAM9X5=y
21CONFIG_SOC_AT91SAM9N12=y 22CONFIG_SOC_AT91SAM9N12=y
23CONFIG_MACH_AT91RM9200_DT=y
22CONFIG_MACH_AT91SAM9_DT=y 24CONFIG_MACH_AT91SAM9_DT=y
23CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 25CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
24CONFIG_AT91_TIMER_HZ=128 26CONFIG_AT91_TIMER_HZ=128
@@ -62,6 +64,7 @@ CONFIG_MTD=y
62CONFIG_MTD_CMDLINE_PARTS=y 64CONFIG_MTD_CMDLINE_PARTS=y
63CONFIG_MTD_CHAR=y 65CONFIG_MTD_CHAR=y
64CONFIG_MTD_BLOCK=y 66CONFIG_MTD_BLOCK=y
67CONFIG_MTD_DATAFLASH=y
65CONFIG_MTD_NAND=y 68CONFIG_MTD_NAND=y
66CONFIG_MTD_NAND_ATMEL=y 69CONFIG_MTD_NAND_ATMEL=y
67CONFIG_MTD_UBI=y 70CONFIG_MTD_UBI=y
@@ -78,7 +81,6 @@ CONFIG_BLK_DEV_SD=y
78CONFIG_SCSI_MULTI_LUN=y 81CONFIG_SCSI_MULTI_LUN=y
79# CONFIG_SCSI_LOWLEVEL is not set 82# CONFIG_SCSI_LOWLEVEL is not set
80CONFIG_NETDEVICES=y 83CONFIG_NETDEVICES=y
81CONFIG_MII=y
82CONFIG_MACB=y 84CONFIG_MACB=y
83# CONFIG_NET_VENDOR_BROADCOM is not set 85# CONFIG_NET_VENDOR_BROADCOM is not set
84# CONFIG_NET_VENDOR_FARADAY is not set 86# CONFIG_NET_VENDOR_FARADAY is not set
diff --git a/arch/arm/configs/bcm_defconfig b/arch/arm/configs/bcm_defconfig
index 65edf6d47215..6e4931097dd4 100644
--- a/arch/arm/configs/bcm_defconfig
+++ b/arch/arm/configs/bcm_defconfig
@@ -42,6 +42,18 @@ CONFIG_VFP=y
42CONFIG_NEON=y 42CONFIG_NEON=y
43# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 43# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
44CONFIG_PM_RUNTIME=y 44CONFIG_PM_RUNTIME=y
45CONFIG_NET=y
46CONFIG_PACKET=y
47CONFIG_PACKET_DIAG=y
48CONFIG_UNIX=y
49CONFIG_UNIX_DIAG=y
50CONFIG_NET_KEY=y
51CONFIG_INET=y
52CONFIG_IP_MULTICAST=y
53CONFIG_ARPD=y
54CONFIG_SYN_COOKIES=y
55CONFIG_TCP_MD5SIG=y
56CONFIG_IPV6=y
45CONFIG_DEVTMPFS=y 57CONFIG_DEVTMPFS=y
46CONFIG_DEVTMPFS_MOUNT=y 58CONFIG_DEVTMPFS_MOUNT=y
47CONFIG_PROC_DEVICETREE=y 59CONFIG_PROC_DEVICETREE=y
@@ -112,7 +124,6 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=110
112CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y 124CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
113CONFIG_DEBUG_INFO=y 125CONFIG_DEBUG_INFO=y
114# CONFIG_FTRACE is not set 126# CONFIG_FTRACE is not set
115CONFIG_DEBUG_LL=y
116CONFIG_CRC_CCITT=y 127CONFIG_CRC_CCITT=y
117CONFIG_CRC_T10DIF=y 128CONFIG_CRC_T10DIF=y
118CONFIG_CRC_ITU_T=y 129CONFIG_CRC_ITU_T=y
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 4364eff5b01e..110105476848 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -13,6 +13,9 @@ CONFIG_ARCH_DOVE=y
13CONFIG_MACH_DOVE_DB=y 13CONFIG_MACH_DOVE_DB=y
14CONFIG_MACH_CM_A510=y 14CONFIG_MACH_CM_A510=y
15CONFIG_MACH_DOVE_DT=y 15CONFIG_MACH_DOVE_DT=y
16CONFIG_PCI=y
17CONFIG_PCI_MSI=y
18CONFIG_PCI_MVEBU=y
16CONFIG_AEABI=y 19CONFIG_AEABI=y
17CONFIG_HIGHMEM=y 20CONFIG_HIGHMEM=y
18CONFIG_ZBOOT_ROM_TEXT=0x0 21CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -78,6 +81,7 @@ CONFIG_SPI_ORION=y
78CONFIG_THERMAL=y 81CONFIG_THERMAL=y
79CONFIG_DOVE_THERMAL=y 82CONFIG_DOVE_THERMAL=y
80CONFIG_USB=y 83CONFIG_USB=y
84CONFIG_USB_XHCI_HCD=y
81CONFIG_USB_EHCI_HCD=y 85CONFIG_USB_EHCI_HCD=y
82CONFIG_USB_EHCI_ROOT_HUB_TT=y 86CONFIG_USB_EHCI_ROOT_HUB_TT=y
83CONFIG_USB_STORAGE=y 87CONFIG_USB_STORAGE=y
diff --git a/arch/arm/configs/exynos4_defconfig b/arch/arm/configs/exynos4_defconfig
deleted file mode 100644
index bffe68e190a3..000000000000
--- a/arch/arm/configs/exynos4_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_BLK_DEV_INITRD=y
3CONFIG_KALLSYMS_ALL=y
4CONFIG_MODULES=y
5CONFIG_MODULE_UNLOAD=y
6# CONFIG_BLK_DEV_BSG is not set
7CONFIG_ARCH_EXYNOS=y
8CONFIG_S3C_LOWLEVEL_UART_PORT=1
9CONFIG_MACH_SMDKC210=y
10CONFIG_MACH_ARMLEX4210=y
11CONFIG_MACH_UNIVERSAL_C210=y
12CONFIG_MACH_NURI=y
13CONFIG_MACH_ORIGEN=y
14CONFIG_MACH_SMDK4412=y
15CONFIG_NO_HZ=y
16CONFIG_HIGH_RES_TIMERS=y
17CONFIG_SMP=y
18CONFIG_NR_CPUS=2
19CONFIG_PREEMPT=y
20CONFIG_AEABI=y
21CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
22CONFIG_VFP=y
23CONFIG_NEON=y
24CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
25CONFIG_BLK_DEV_LOOP=y
26CONFIG_BLK_DEV_RAM=y
27CONFIG_BLK_DEV_RAM_SIZE=8192
28CONFIG_SCSI=y
29CONFIG_BLK_DEV_SD=y
30CONFIG_CHR_DEV_SG=y
31CONFIG_INPUT_EVDEV=y
32# CONFIG_INPUT_KEYBOARD is not set
33# CONFIG_INPUT_MOUSE is not set
34CONFIG_INPUT_TOUCHSCREEN=y
35CONFIG_SERIAL_8250=y
36CONFIG_SERIAL_SAMSUNG=y
37CONFIG_SERIAL_SAMSUNG_CONSOLE=y
38CONFIG_HW_RANDOM=y
39CONFIG_I2C=y
40# CONFIG_HWMON is not set
41# CONFIG_MFD_SUPPORT is not set
42# CONFIG_HID_SUPPORT is not set
43# CONFIG_USB_SUPPORT is not set
44CONFIG_EXT2_FS=y
45CONFIG_MSDOS_FS=y
46CONFIG_VFAT_FS=y
47CONFIG_TMPFS=y
48CONFIG_TMPFS_POSIX_ACL=y
49CONFIG_CRAMFS=y
50CONFIG_ROMFS_FS=y
51CONFIG_PARTITION_ADVANCED=y
52CONFIG_BSD_DISKLABEL=y
53CONFIG_SOLARIS_X86_PARTITION=y
54CONFIG_NLS_CODEPAGE_437=y
55CONFIG_NLS_ASCII=y
56CONFIG_NLS_ISO8859_1=y
57CONFIG_MAGIC_SYSRQ=y
58CONFIG_DEBUG_KERNEL=y
59CONFIG_DETECT_HUNG_TASK=y
60CONFIG_DEBUG_RT_MUTEXES=y
61CONFIG_DEBUG_SPINLOCK=y
62CONFIG_DEBUG_MUTEXES=y
63CONFIG_DEBUG_INFO=y
64CONFIG_SYSCTL_SYSCALL_CHECK=y
65CONFIG_DEBUG_USER=y
66CONFIG_DEBUG_LL=y
67CONFIG_EARLY_PRINTK=y
68CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index f07a847b00c9..e958ebe79779 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -1,4 +1,3 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_SWAP is not set 1# CONFIG_SWAP is not set
3CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
4CONFIG_POSIX_MQUEUE=y 3CONFIG_POSIX_MQUEUE=y
@@ -17,16 +16,18 @@ CONFIG_MODULE_UNLOAD=y
17# CONFIG_BLK_DEV_BSG is not set 16# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set 17# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set 18# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_MXC=y
21CONFIG_ARCH_MULTI_V4T=y 19CONFIG_ARCH_MULTI_V4T=y
22CONFIG_ARCH_MULTI_V5=y 20CONFIG_ARCH_MULTI_V5=y
23# CONFIG_ARCH_MULTI_V7 is not set 21# CONFIG_ARCH_MULTI_V7 is not set
22CONFIG_ARCH_MXC=y
23CONFIG_MXC_IRQ_PRIOR=y
24CONFIG_ARCH_MX1ADS=y 24CONFIG_ARCH_MX1ADS=y
25CONFIG_MACH_SCB9328=y 25CONFIG_MACH_SCB9328=y
26CONFIG_MACH_APF9328=y 26CONFIG_MACH_APF9328=y
27CONFIG_MACH_MX21ADS=y 27CONFIG_MACH_MX21ADS=y
28CONFIG_MACH_MX25_3DS=y 28CONFIG_MACH_MX25_3DS=y
29CONFIG_MACH_EUKREA_CPUIMX25SD=y 29CONFIG_MACH_EUKREA_CPUIMX25SD=y
30CONFIG_MACH_IMX25_DT=y
30CONFIG_MACH_MX27ADS=y 31CONFIG_MACH_MX27ADS=y
31CONFIG_MACH_PCM038=y 32CONFIG_MACH_PCM038=y
32CONFIG_MACH_CPUIMX27=y 33CONFIG_MACH_CPUIMX27=y
@@ -39,8 +40,6 @@ CONFIG_MACH_PCA100=y
39CONFIG_MACH_MXT_TD60=y 40CONFIG_MACH_MXT_TD60=y
40CONFIG_MACH_IMX27IPCAM=y 41CONFIG_MACH_IMX27IPCAM=y
41CONFIG_MACH_IMX27_DT=y 42CONFIG_MACH_IMX27_DT=y
42CONFIG_MXC_IRQ_PRIOR=y
43CONFIG_MXC_PWM=y
44CONFIG_PREEMPT=y 43CONFIG_PREEMPT=y
45CONFIG_AEABI=y 44CONFIG_AEABI=y
46CONFIG_ZBOOT_ROM_TEXT=0x0 45CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -67,7 +66,6 @@ CONFIG_DEVTMPFS=y
67CONFIG_DEVTMPFS_MOUNT=y 66CONFIG_DEVTMPFS_MOUNT=y
68CONFIG_MTD=y 67CONFIG_MTD=y
69CONFIG_MTD_CMDLINE_PARTS=y 68CONFIG_MTD_CMDLINE_PARTS=y
70CONFIG_MTD_CHAR=y
71CONFIG_MTD_BLOCK=y 69CONFIG_MTD_BLOCK=y
72CONFIG_MTD_CFI=y 70CONFIG_MTD_CFI=y
73CONFIG_MTD_CFI_ADV_OPTIONS=y 71CONFIG_MTD_CFI_ADV_OPTIONS=y
@@ -123,24 +121,20 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
123CONFIG_REGULATOR_MC13783=y 121CONFIG_REGULATOR_MC13783=y
124CONFIG_REGULATOR_MC13892=y 122CONFIG_REGULATOR_MC13892=y
125CONFIG_MEDIA_SUPPORT=y 123CONFIG_MEDIA_SUPPORT=y
126CONFIG_VIDEO_DEV=y
127CONFIG_V4L_PLATFORM_DRIVERS=y
128CONFIG_MEDIA_CAMERA_SUPPORT=y 124CONFIG_MEDIA_CAMERA_SUPPORT=y
125CONFIG_V4L_PLATFORM_DRIVERS=y
129CONFIG_SOC_CAMERA=y 126CONFIG_SOC_CAMERA=y
130CONFIG_SOC_CAMERA_OV2640=y
131CONFIG_VIDEO_MX2=y 127CONFIG_VIDEO_MX2=y
132CONFIG_V4L_MEM2MEM_DRIVERS=y 128CONFIG_V4L_MEM2MEM_DRIVERS=y
133CONFIG_VIDEO_CODA=y 129CONFIG_VIDEO_CODA=y
130CONFIG_SOC_CAMERA_OV2640=y
134CONFIG_FB=y 131CONFIG_FB=y
135CONFIG_FB_IMX=y 132CONFIG_FB_IMX=y
136CONFIG_BACKLIGHT_LCD_SUPPORT=y 133CONFIG_BACKLIGHT_LCD_SUPPORT=y
137CONFIG_LCD_CLASS_DEVICE=y 134CONFIG_LCD_CLASS_DEVICE=y
138CONFIG_LCD_L4F00242T03=y 135CONFIG_LCD_L4F00242T03=y
139CONFIG_BACKLIGHT_CLASS_DEVICE=y 136CONFIG_BACKLIGHT_CLASS_DEVICE=y
140CONFIG_BACKLIGHT_PWM=y
141CONFIG_FRAMEBUFFER_CONSOLE=y 137CONFIG_FRAMEBUFFER_CONSOLE=y
142CONFIG_FONTS=y
143CONFIG_FONT_8x8=y
144CONFIG_LOGO=y 138CONFIG_LOGO=y
145CONFIG_SOUND=y 139CONFIG_SOUND=y
146CONFIG_SND=y 140CONFIG_SND=y
@@ -157,7 +151,6 @@ CONFIG_USB_HID=m
157CONFIG_USB=y 151CONFIG_USB=y
158CONFIG_USB_EHCI_HCD=y 152CONFIG_USB_EHCI_HCD=y
159CONFIG_USB_EHCI_MXC=y 153CONFIG_USB_EHCI_MXC=y
160CONFIG_USB_ULPI=y
161CONFIG_MMC=y 154CONFIG_MMC=y
162CONFIG_MMC_SDHCI=y 155CONFIG_MMC_SDHCI=y
163CONFIG_MMC_SDHCI_PLTFM=y 156CONFIG_MMC_SDHCI_PLTFM=y
@@ -198,3 +191,5 @@ CONFIG_NLS_CODEPAGE_850=m
198CONFIG_NLS_ISO8859_1=y 191CONFIG_NLS_ISO8859_1=y
199CONFIG_NLS_ISO8859_15=m 192CONFIG_NLS_ISO8859_15=m
200# CONFIG_CRYPTO_ANSI_CPRNG is not set 193# CONFIG_CRYPTO_ANSI_CPRNG is not set
194CONFIG_FONTS=y
195CONFIG_FONT_8x8=y
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 06686e7303a9..5d488c24b132 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -1,4 +1,3 @@
1CONFIG_EXPERIMENTAL=y
2# CONFIG_LOCALVERSION_AUTO is not set 1# CONFIG_LOCALVERSION_AUTO is not set
3CONFIG_KERNEL_LZO=y 2CONFIG_KERNEL_LZO=y
4CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
@@ -17,10 +16,8 @@ CONFIG_MODULE_UNLOAD=y
17CONFIG_MODVERSIONS=y 16CONFIG_MODVERSIONS=y
18CONFIG_MODULE_SRCVERSION_ALL=y 17CONFIG_MODULE_SRCVERSION_ALL=y
19# CONFIG_BLK_DEV_BSG is not set 18# CONFIG_BLK_DEV_BSG is not set
20CONFIG_ARCH_MXC=y
21CONFIG_ARCH_MULTI_V6=y 19CONFIG_ARCH_MULTI_V6=y
22CONFIG_ARCH_MULTI_V7=y 20CONFIG_ARCH_MXC=y
23CONFIG_MACH_IMX31_DT=y
24CONFIG_MACH_MX31LILLY=y 21CONFIG_MACH_MX31LILLY=y
25CONFIG_MACH_MX31LITE=y 22CONFIG_MACH_MX31LITE=y
26CONFIG_MACH_PCM037=y 23CONFIG_MACH_PCM037=y
@@ -30,6 +27,7 @@ CONFIG_MACH_MX31MOBOARD=y
30CONFIG_MACH_QONG=y 27CONFIG_MACH_QONG=y
31CONFIG_MACH_ARMADILLO5X0=y 28CONFIG_MACH_ARMADILLO5X0=y
32CONFIG_MACH_KZM_ARM11_01=y 29CONFIG_MACH_KZM_ARM11_01=y
30CONFIG_MACH_IMX31_DT=y
33CONFIG_MACH_PCM043=y 31CONFIG_MACH_PCM043=y
34CONFIG_MACH_MX35_3DS=y 32CONFIG_MACH_MX35_3DS=y
35CONFIG_MACH_VPR200=y 33CONFIG_MACH_VPR200=y
@@ -39,7 +37,6 @@ CONFIG_SOC_IMX53=y
39CONFIG_SOC_IMX6Q=y 37CONFIG_SOC_IMX6Q=y
40CONFIG_SOC_IMX6SL=y 38CONFIG_SOC_IMX6SL=y
41CONFIG_SOC_VF610=y 39CONFIG_SOC_VF610=y
42CONFIG_MXC_PWM=y
43CONFIG_SMP=y 40CONFIG_SMP=y
44CONFIG_VMSPLIT_2G=y 41CONFIG_VMSPLIT_2G=y
45CONFIG_PREEMPT_VOLUNTARY=y 42CONFIG_PREEMPT_VOLUNTARY=y
@@ -64,20 +61,24 @@ CONFIG_IP_PNP_DHCP=y
64# CONFIG_INET_LRO is not set 61# CONFIG_INET_LRO is not set
65CONFIG_IPV6=y 62CONFIG_IPV6=y
66CONFIG_NETFILTER=y 63CONFIG_NETFILTER=y
67# CONFIG_WIRELESS is not set 64CONFIG_CFG80211=y
65CONFIG_MAC80211=y
66CONFIG_RFKILL=y
67CONFIG_RFKILL_INPUT=y
68CONFIG_DEVTMPFS=y 68CONFIG_DEVTMPFS=y
69CONFIG_DEVTMPFS_MOUNT=y 69CONFIG_DEVTMPFS_MOUNT=y
70# CONFIG_STANDALONE is not set 70# CONFIG_STANDALONE is not set
71CONFIG_IMX_WEIM=y
71CONFIG_CONNECTOR=y 72CONFIG_CONNECTOR=y
72CONFIG_MTD=y 73CONFIG_MTD=y
73CONFIG_MTD_CMDLINE_PARTS=y 74CONFIG_MTD_CMDLINE_PARTS=y
74CONFIG_MTD_CHAR=y
75CONFIG_MTD_BLOCK=y 75CONFIG_MTD_BLOCK=y
76CONFIG_MTD_CFI=y 76CONFIG_MTD_CFI=y
77CONFIG_MTD_JEDECPROBE=y 77CONFIG_MTD_JEDECPROBE=y
78CONFIG_MTD_CFI_INTELEXT=y 78CONFIG_MTD_CFI_INTELEXT=y
79CONFIG_MTD_CFI_AMDSTD=y 79CONFIG_MTD_CFI_AMDSTD=y
80CONFIG_MTD_CFI_STAA=y 80CONFIG_MTD_CFI_STAA=y
81CONFIG_MTD_PHYSMAP_OF=y
81CONFIG_MTD_DATAFLASH=y 82CONFIG_MTD_DATAFLASH=y
82CONFIG_MTD_M25P80=y 83CONFIG_MTD_M25P80=y
83CONFIG_MTD_SST25L=y 84CONFIG_MTD_SST25L=y
@@ -88,6 +89,7 @@ CONFIG_MTD_UBI=y
88CONFIG_BLK_DEV_LOOP=y 89CONFIG_BLK_DEV_LOOP=y
89CONFIG_BLK_DEV_RAM=y 90CONFIG_BLK_DEV_RAM=y
90CONFIG_BLK_DEV_RAM_SIZE=65536 91CONFIG_BLK_DEV_RAM_SIZE=65536
92CONFIG_SRAM=y
91CONFIG_EEPROM_AT24=y 93CONFIG_EEPROM_AT24=y
92CONFIG_EEPROM_AT25=y 94CONFIG_EEPROM_AT25=y
93# CONFIG_SCSI_PROC_FS is not set 95# CONFIG_SCSI_PROC_FS is not set
@@ -98,10 +100,11 @@ CONFIG_SCSI_LOGGING=y
98CONFIG_SCSI_SCAN_ASYNC=y 100CONFIG_SCSI_SCAN_ASYNC=y
99# CONFIG_SCSI_LOWLEVEL is not set 101# CONFIG_SCSI_LOWLEVEL is not set
100CONFIG_ATA=y 102CONFIG_ATA=y
103CONFIG_SATA_AHCI_PLATFORM=y
104CONFIG_AHCI_IMX=y
101CONFIG_PATA_IMX=y 105CONFIG_PATA_IMX=y
102CONFIG_NETDEVICES=y 106CONFIG_NETDEVICES=y
103# CONFIG_NET_VENDOR_BROADCOM is not set 107# CONFIG_NET_VENDOR_BROADCOM is not set
104# CONFIG_NET_VENDOR_CHELSIO is not set
105CONFIG_CS89x0=y 108CONFIG_CS89x0=y
106CONFIG_CS89x0_PLATFORM=y 109CONFIG_CS89x0_PLATFORM=y
107# CONFIG_NET_VENDOR_FARADAY is not set 110# CONFIG_NET_VENDOR_FARADAY is not set
@@ -115,7 +118,7 @@ CONFIG_SMC91X=y
115CONFIG_SMC911X=y 118CONFIG_SMC911X=y
116CONFIG_SMSC911X=y 119CONFIG_SMSC911X=y
117# CONFIG_NET_VENDOR_STMICRO is not set 120# CONFIG_NET_VENDOR_STMICRO is not set
118# CONFIG_WLAN is not set 121CONFIG_BRCMFMAC=m
119# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 122# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
120CONFIG_INPUT_EVDEV=y 123CONFIG_INPUT_EVDEV=y
121CONFIG_INPUT_EVBUG=m 124CONFIG_INPUT_EVBUG=m
@@ -124,6 +127,7 @@ CONFIG_KEYBOARD_IMX=y
124CONFIG_MOUSE_PS2=m 127CONFIG_MOUSE_PS2=m
125CONFIG_MOUSE_PS2_ELANTECH=y 128CONFIG_MOUSE_PS2_ELANTECH=y
126CONFIG_INPUT_TOUCHSCREEN=y 129CONFIG_INPUT_TOUCHSCREEN=y
130CONFIG_TOUCHSCREEN_EGALAX=y
127CONFIG_TOUCHSCREEN_MC13783=y 131CONFIG_TOUCHSCREEN_MC13783=y
128CONFIG_INPUT_MISC=y 132CONFIG_INPUT_MISC=y
129CONFIG_INPUT_MMA8450=y 133CONFIG_INPUT_MMA8450=y
@@ -133,13 +137,13 @@ CONFIG_VT_HW_CONSOLE_BINDING=y
133# CONFIG_DEVKMEM is not set 137# CONFIG_DEVKMEM is not set
134CONFIG_SERIAL_IMX=y 138CONFIG_SERIAL_IMX=y
135CONFIG_SERIAL_IMX_CONSOLE=y 139CONFIG_SERIAL_IMX_CONSOLE=y
140CONFIG_SERIAL_FSL_LPUART=y
141CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
136CONFIG_HW_RANDOM=y 142CONFIG_HW_RANDOM=y
137CONFIG_HW_RANDOM_MXC_RNGA=y 143CONFIG_HW_RANDOM_MXC_RNGA=y
138CONFIG_I2C=y
139# CONFIG_I2C_COMPAT is not set 144# CONFIG_I2C_COMPAT is not set
140CONFIG_I2C_CHARDEV=y 145CONFIG_I2C_CHARDEV=y
141# CONFIG_I2C_HELPER_AUTO is not set 146# CONFIG_I2C_HELPER_AUTO is not set
142CONFIG_I2C_ALGOBIT=m
143CONFIG_I2C_ALGOPCF=m 147CONFIG_I2C_ALGOPCF=m
144CONFIG_I2C_ALGOPCA=m 148CONFIG_I2C_ALGOPCA=m
145CONFIG_I2C_IMX=y 149CONFIG_I2C_IMX=y
@@ -155,30 +159,26 @@ CONFIG_MFD_MC13XXX_SPI=y
155CONFIG_MFD_MC13XXX_I2C=y 159CONFIG_MFD_MC13XXX_I2C=y
156CONFIG_REGULATOR=y 160CONFIG_REGULATOR=y
157CONFIG_REGULATOR_FIXED_VOLTAGE=y 161CONFIG_REGULATOR_FIXED_VOLTAGE=y
158CONFIG_REGULATOR_DA9052=y
159CONFIG_REGULATOR_ANATOP=y 162CONFIG_REGULATOR_ANATOP=y
163CONFIG_REGULATOR_DA9052=y
160CONFIG_REGULATOR_MC13783=y 164CONFIG_REGULATOR_MC13783=y
161CONFIG_REGULATOR_MC13892=y 165CONFIG_REGULATOR_MC13892=y
162CONFIG_MEDIA_SUPPORT=y 166CONFIG_MEDIA_SUPPORT=y
163CONFIG_VIDEO_DEV=y
164CONFIG_V4L_PLATFORM_DRIVERS=y
165CONFIG_MEDIA_CAMERA_SUPPORT=y 167CONFIG_MEDIA_CAMERA_SUPPORT=y
168CONFIG_V4L_PLATFORM_DRIVERS=y
166CONFIG_SOC_CAMERA=y 169CONFIG_SOC_CAMERA=y
170CONFIG_VIDEO_MX3=y
171CONFIG_V4L_MEM2MEM_DRIVERS=y
172CONFIG_VIDEO_CODA=y
167CONFIG_SOC_CAMERA_OV2640=y 173CONFIG_SOC_CAMERA_OV2640=y
168CONFIG_DRM=y 174CONFIG_DRM=y
169CONFIG_VIDEO_MX3=y
170CONFIG_FB=y
171CONFIG_LCD_PLATFORM=y
172CONFIG_BACKLIGHT_LCD_SUPPORT=y 175CONFIG_BACKLIGHT_LCD_SUPPORT=y
173CONFIG_LCD_CLASS_DEVICE=y 176CONFIG_LCD_CLASS_DEVICE=y
174CONFIG_LCD_L4F00242T03=y 177CONFIG_LCD_L4F00242T03=y
178CONFIG_LCD_PLATFORM=y
175CONFIG_BACKLIGHT_CLASS_DEVICE=y 179CONFIG_BACKLIGHT_CLASS_DEVICE=y
176CONFIG_BACKLIGHT_PWM=y 180CONFIG_BACKLIGHT_PWM=y
177CONFIG_FRAMEBUFFER_CONSOLE=y 181CONFIG_FRAMEBUFFER_CONSOLE=y
178CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
179CONFIG_FONTS=y
180CONFIG_FONT_8x8=y
181CONFIG_FONT_8x16=y
182CONFIG_LOGO=y 182CONFIG_LOGO=y
183CONFIG_SOUND=y 183CONFIG_SOUND=y
184CONFIG_SND=y 184CONFIG_SND=y
@@ -192,11 +192,12 @@ CONFIG_SND_SOC_IMX_MC13783=y
192CONFIG_USB=y 192CONFIG_USB=y
193CONFIG_USB_EHCI_HCD=y 193CONFIG_USB_EHCI_HCD=y
194CONFIG_USB_EHCI_MXC=y 194CONFIG_USB_EHCI_MXC=y
195CONFIG_USB_STORAGE=y
195CONFIG_USB_CHIPIDEA=y 196CONFIG_USB_CHIPIDEA=y
196CONFIG_USB_CHIPIDEA_HOST=y 197CONFIG_USB_CHIPIDEA_HOST=y
197CONFIG_USB_PHY=y 198CONFIG_USB_PHY=y
199CONFIG_NOP_USB_XCEIV=y
198CONFIG_USB_MXS_PHY=y 200CONFIG_USB_MXS_PHY=y
199CONFIG_USB_STORAGE=y
200CONFIG_MMC=y 201CONFIG_MMC=y
201CONFIG_MMC_SDHCI=y 202CONFIG_MMC_SDHCI=y
202CONFIG_MMC_SDHCI_PLTFM=y 203CONFIG_MMC_SDHCI_PLTFM=y
@@ -213,9 +214,10 @@ CONFIG_IMX_SDMA=y
213CONFIG_MXS_DMA=y 214CONFIG_MXS_DMA=y
214CONFIG_STAGING=y 215CONFIG_STAGING=y
215CONFIG_DRM_IMX=y 216CONFIG_DRM_IMX=y
216CONFIG_DRM_IMX_TVE=y
217CONFIG_DRM_IMX_FB_HELPER=y 217CONFIG_DRM_IMX_FB_HELPER=y
218CONFIG_DRM_IMX_PARALLEL_DISPLAY=y 218CONFIG_DRM_IMX_PARALLEL_DISPLAY=y
219CONFIG_DRM_IMX_TVE=y
220CONFIG_DRM_IMX_LDB=y
219CONFIG_DRM_IMX_IPUV3_CORE=y 221CONFIG_DRM_IMX_IPUV3_CORE=y
220CONFIG_DRM_IMX_IPUV3=y 222CONFIG_DRM_IMX_IPUV3=y
221CONFIG_COMMON_CLK_DEBUG=y 223CONFIG_COMMON_CLK_DEBUG=y
@@ -269,3 +271,6 @@ CONFIG_CRC_CCITT=m
269CONFIG_CRC_T10DIF=y 271CONFIG_CRC_T10DIF=y
270CONFIG_CRC7=m 272CONFIG_CRC7=m
271CONFIG_LIBCRC32C=m 273CONFIG_LIBCRC32C=m
274CONFIG_FONTS=y
275CONFIG_FONT_8x8=y
276CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 0f2aa61911a3..0ae0eaebf6b2 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -10,49 +10,18 @@ CONFIG_MODULE_UNLOAD=y
10# CONFIG_BLK_DEV_BSG is not set 10# CONFIG_BLK_DEV_BSG is not set
11CONFIG_ARCH_KIRKWOOD=y 11CONFIG_ARCH_KIRKWOOD=y
12CONFIG_MACH_D2NET_V2=y 12CONFIG_MACH_D2NET_V2=y
13CONFIG_MACH_DB88F6281_BP=y
14CONFIG_MACH_DOCKSTAR=y
15CONFIG_MACH_ESATA_SHEEVAPLUG=y
16CONFIG_MACH_GURUPLUG=y
17CONFIG_MACH_INETSPACE_V2=y
18CONFIG_MACH_MV88F6281GTW_GE=y
19CONFIG_MACH_NET2BIG_V2=y 13CONFIG_MACH_NET2BIG_V2=y
20CONFIG_MACH_NET5BIG_V2=y 14CONFIG_MACH_NET5BIG_V2=y
21CONFIG_MACH_NETSPACE_MAX_V2=y
22CONFIG_MACH_NETSPACE_V2=y
23CONFIG_MACH_OPENRD_BASE=y 15CONFIG_MACH_OPENRD_BASE=y
24CONFIG_MACH_OPENRD_CLIENT=y 16CONFIG_MACH_OPENRD_CLIENT=y
25CONFIG_MACH_OPENRD_ULTIMATE=y 17CONFIG_MACH_OPENRD_ULTIMATE=y
26CONFIG_MACH_RD88F6192_NAS=y 18CONFIG_MACH_RD88F6192_NAS=y
27CONFIG_MACH_RD88F6281=y 19CONFIG_MACH_RD88F6281=y
28CONFIG_MACH_SHEEVAPLUG=y
29CONFIG_MACH_T5325=y 20CONFIG_MACH_T5325=y
30CONFIG_MACH_TS219=y 21CONFIG_MACH_TS219=y
31CONFIG_MACH_TS41X=y 22CONFIG_MACH_TS41X=y
32CONFIG_MACH_CLOUDBOX_DT=y 23CONFIG_ARCH_KIRKWOOD_DT=y
33CONFIG_MACH_DB88F628X_BP_DT=y 24CONFIG_MACH_MV88F6281GTW_GE_DT=y
34CONFIG_MACH_DLINK_KIRKWOOD_DT=y
35CONFIG_MACH_DOCKSTAR_DT=y
36CONFIG_MACH_DREAMPLUG_DT=y
37CONFIG_MACH_GOFLEXNET_DT=y
38CONFIG_MACH_GURUPLUG_DT=y
39CONFIG_MACH_IB62X0_DT=y
40CONFIG_MACH_ICONNECT_DT=y
41CONFIG_MACH_INETSPACE_V2_DT=y
42CONFIG_MACH_IOMEGA_IX2_200_DT=y
43CONFIG_MACH_KM_KIRKWOOD_DT=y
44CONFIG_MACH_LSXL_DT=y
45CONFIG_MACH_MPLCEC4_DT=y
46CONFIG_MACH_NETSPACE_LITE_V2_DT=y
47CONFIG_MACH_NETSPACE_MAX_V2_DT=y
48CONFIG_MACH_NETSPACE_MINI_V2_DT=y
49CONFIG_MACH_NETSPACE_V2_DT=y
50CONFIG_MACH_NSA310_DT=y
51CONFIG_MACH_OPENBLOCKS_A6_DT=y
52CONFIG_MACH_READYNAS_DT=y
53CONFIG_MACH_SHEEVAPLUG_DT=y
54CONFIG_MACH_TOPKICK_DT=y
55CONFIG_MACH_TS219_DT=y
56# CONFIG_CPU_FEROCEON_OLD_ID is not set 25# CONFIG_CPU_FEROCEON_OLD_ID is not set
57CONFIG_PCI_MVEBU=y 26CONFIG_PCI_MVEBU=y
58CONFIG_PREEMPT=y 27CONFIG_PREEMPT=y
@@ -92,6 +61,7 @@ CONFIG_MTD_M25P80=y
92CONFIG_MTD_NAND=y 61CONFIG_MTD_NAND=y
93CONFIG_MTD_NAND_ORION=y 62CONFIG_MTD_NAND_ORION=y
94CONFIG_BLK_DEV_LOOP=y 63CONFIG_BLK_DEV_LOOP=y
64CONFIG_EEPROM_AT24=y
95# CONFIG_SCSI_PROC_FS is not set 65# CONFIG_SCSI_PROC_FS is not set
96CONFIG_BLK_DEV_SD=y 66CONFIG_BLK_DEV_SD=y
97CONFIG_BLK_DEV_SR=m 67CONFIG_BLK_DEV_SR=m
@@ -100,9 +70,9 @@ CONFIG_ATA=y
100CONFIG_SATA_AHCI=y 70CONFIG_SATA_AHCI=y
101CONFIG_SATA_MV=y 71CONFIG_SATA_MV=y
102CONFIG_NETDEVICES=y 72CONFIG_NETDEVICES=y
103CONFIG_MII=y
104CONFIG_NET_DSA_MV88E6123_61_65=y 73CONFIG_NET_DSA_MV88E6123_61_65=y
105CONFIG_MV643XX_ETH=y 74CONFIG_MV643XX_ETH=y
75CONFIG_R8169=y
106CONFIG_MARVELL_PHY=y 76CONFIG_MARVELL_PHY=y
107CONFIG_LIBERTAS=y 77CONFIG_LIBERTAS=y
108CONFIG_LIBERTAS_SDIO=y 78CONFIG_LIBERTAS_SDIO=y
@@ -123,9 +93,11 @@ CONFIG_I2C_MV64XXX=y
123CONFIG_SPI=y 93CONFIG_SPI=y
124CONFIG_SPI_ORION=y 94CONFIG_SPI_ORION=y
125CONFIG_GPIO_SYSFS=y 95CONFIG_GPIO_SYSFS=y
126# CONFIG_HWMON is not set 96CONFIG_SENSORS_ADT7475=y
97CONFIG_SENSORS_LM63=y
98CONFIG_SENSORS_LM75=y
99CONFIG_SENSORS_LM85=y
127CONFIG_THERMAL=y 100CONFIG_THERMAL=y
128CONFIG_KIRKWOOD_THERMAL=y
129CONFIG_WATCHDOG=y 101CONFIG_WATCHDOG=y
130CONFIG_ORION_WATCHDOG=y 102CONFIG_ORION_WATCHDOG=y
131CONFIG_HID_DRAGONRISE=y 103CONFIG_HID_DRAGONRISE=y
@@ -164,6 +136,8 @@ CONFIG_LEDS_TRIGGER_TIMER=y
164CONFIG_LEDS_TRIGGER_HEARTBEAT=y 136CONFIG_LEDS_TRIGGER_HEARTBEAT=y
165CONFIG_LEDS_TRIGGER_DEFAULT_ON=y 137CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
166CONFIG_RTC_CLASS=y 138CONFIG_RTC_CLASS=y
139CONFIG_RTC_DRV_RS5C372=y
140CONFIG_RTC_DRV_PCF8563=y
167CONFIG_RTC_DRV_S35390A=y 141CONFIG_RTC_DRV_S35390A=y
168CONFIG_RTC_DRV_MV=y 142CONFIG_RTC_DRV_MV=y
169CONFIG_DMADEVICES=y 143CONFIG_DMADEVICES=y
@@ -171,6 +145,7 @@ CONFIG_MV_XOR=y
171CONFIG_EXT2_FS=y 145CONFIG_EXT2_FS=y
172CONFIG_EXT3_FS=y 146CONFIG_EXT3_FS=y
173# CONFIG_EXT3_FS_XATTR is not set 147# CONFIG_EXT3_FS_XATTR is not set
148CONFIG_EXT4_FS=y
174CONFIG_ISO9660_FS=m 149CONFIG_ISO9660_FS=m
175CONFIG_JOLIET=y 150CONFIG_JOLIET=y
176CONFIG_UDF_FS=m 151CONFIG_UDF_FS=m
@@ -186,12 +161,12 @@ CONFIG_NLS_CODEPAGE_850=y
186CONFIG_NLS_ISO8859_1=y 161CONFIG_NLS_ISO8859_1=y
187CONFIG_NLS_ISO8859_2=y 162CONFIG_NLS_ISO8859_2=y
188CONFIG_NLS_UTF8=y 163CONFIG_NLS_UTF8=y
189CONFIG_MAGIC_SYSRQ=y 164CONFIG_DEBUG_INFO=y
190CONFIG_DEBUG_FS=y 165CONFIG_DEBUG_FS=y
166CONFIG_MAGIC_SYSRQ=y
191CONFIG_DEBUG_KERNEL=y 167CONFIG_DEBUG_KERNEL=y
192# CONFIG_SCHED_DEBUG is not set 168# CONFIG_SCHED_DEBUG is not set
193# CONFIG_DEBUG_PREEMPT is not set 169# CONFIG_DEBUG_PREEMPT is not set
194CONFIG_DEBUG_INFO=y
195# CONFIG_FTRACE is not set 170# CONFIG_FTRACE is not set
196CONFIG_DEBUG_USER=y 171CONFIG_DEBUG_USER=y
197CONFIG_DEBUG_LL=y 172CONFIG_DEBUG_LL=y
diff --git a/arch/arm/configs/kota2_defconfig b/arch/arm/configs/lager_defconfig
index 57ad3d47de70..e777ef22b801 100644
--- a/arch/arm/configs/kota2_defconfig
+++ b/arch/arm/configs/lager_defconfig
@@ -1,52 +1,38 @@
1# CONFIG_ARM_PATCH_PHYS_VIRT is not set
2CONFIG_EXPERIMENTAL=y
3CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
2CONFIG_NO_HZ=y
4CONFIG_IKCONFIG=y 3CONFIG_IKCONFIG=y
5CONFIG_IKCONFIG_PROC=y 4CONFIG_IKCONFIG_PROC=y
6CONFIG_LOG_BUF_SHIFT=16 5CONFIG_LOG_BUF_SHIFT=16
7CONFIG_CGROUPS=y 6CONFIG_CC_OPTIMIZE_FOR_SIZE=y
8CONFIG_CPUSETS=y
9CONFIG_NAMESPACES=y
10# CONFIG_UTS_NS is not set
11# CONFIG_IPC_NS is not set
12# CONFIG_USER_NS is not set
13# CONFIG_PID_NS is not set
14CONFIG_SYSCTL_SYSCALL=y 7CONFIG_SYSCTL_SYSCALL=y
15CONFIG_EMBEDDED=y 8CONFIG_EMBEDDED=y
9CONFIG_PERF_EVENTS=y
16CONFIG_SLAB=y 10CONFIG_SLAB=y
11# CONFIG_LBDAF is not set
17# CONFIG_BLK_DEV_BSG is not set 12# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set 13# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set 14# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y 15CONFIG_ARCH_SHMOBILE=y
21CONFIG_KEYBOARD_GPIO_POLLED=y 16CONFIG_ARCH_R8A7790=y
22CONFIG_ARCH_SH73A0=y 17CONFIG_MACH_LAGER=y
23CONFIG_MACH_KOTA2=y
24CONFIG_MEMORY_SIZE=0x1e000000
25# CONFIG_SH_TIMER_TMU is not set 18# CONFIG_SH_TIMER_TMU is not set
26# CONFIG_SWP_EMULATE is not set 19# CONFIG_EM_TIMER_STI is not set
27CONFIG_CPU_BPREDICT_DISABLE=y 20CONFIG_ARM_ERRATA_430973=y
21CONFIG_ARM_ERRATA_458693=y
28CONFIG_ARM_ERRATA_460075=y 22CONFIG_ARM_ERRATA_460075=y
29CONFIG_ARM_ERRATA_742230=y
30CONFIG_ARM_ERRATA_742231=y
31CONFIG_PL310_ERRATA_588369=y
32CONFIG_ARM_ERRATA_720789=y
33CONFIG_PL310_ERRATA_727915=y
34CONFIG_ARM_ERRATA_743622=y 23CONFIG_ARM_ERRATA_743622=y
35CONFIG_ARM_ERRATA_751472=y
36CONFIG_PL310_ERRATA_753970=y
37CONFIG_ARM_ERRATA_754322=y 24CONFIG_ARM_ERRATA_754322=y
38CONFIG_PL310_ERRATA_769419=y 25CONFIG_HAVE_ARM_ARCH_TIMER=y
39CONFIG_NO_HZ=y
40CONFIG_SMP=y
41CONFIG_AEABI=y 26CONFIG_AEABI=y
42# CONFIG_OABI_COMPAT is not set 27# CONFIG_OABI_COMPAT is not set
43CONFIG_HIGHMEM=y 28CONFIG_FORCE_MAX_ZONEORDER=13
44CONFIG_ZBOOT_ROM_TEXT=0x0 29CONFIG_ZBOOT_ROM_TEXT=0x0
45CONFIG_ZBOOT_ROM_BSS=0x0 30CONFIG_ZBOOT_ROM_BSS=0x0
46CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel" 31CONFIG_ARM_APPENDED_DTB=y
47CONFIG_CMDLINE_FORCE=y
48CONFIG_KEXEC=y 32CONFIG_KEXEC=y
49CONFIG_CPU_IDLE=y 33CONFIG_AUTO_ZRELADDR=y
34CONFIG_VFP=y
35CONFIG_NEON=y
50# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 36# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
51CONFIG_PM_RUNTIME=y 37CONFIG_PM_RUNTIME=y
52CONFIG_NET=y 38CONFIG_NET=y
@@ -61,47 +47,48 @@ CONFIG_IP_PNP_DHCP=y
61# CONFIG_INET_LRO is not set 47# CONFIG_INET_LRO is not set
62# CONFIG_INET_DIAG is not set 48# CONFIG_INET_DIAG is not set
63# CONFIG_IPV6 is not set 49# CONFIG_IPV6 is not set
64CONFIG_CFG80211=y 50# CONFIG_WIRELESS is not set
65CONFIG_WIRELESS_EXT_SYSFS=y
66CONFIG_MAC80211=y
67CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 51CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
68# CONFIG_BLK_DEV is not set
69CONFIG_NETDEVICES=y 52CONFIG_NETDEVICES=y
53# CONFIG_NET_CORE is not set
54# CONFIG_NET_VENDOR_ARC is not set
55# CONFIG_NET_CADENCE is not set
70# CONFIG_NET_VENDOR_BROADCOM is not set 56# CONFIG_NET_VENDOR_BROADCOM is not set
71# CONFIG_NET_VENDOR_CHELSIO is not set 57# CONFIG_NET_VENDOR_CIRRUS is not set
72# CONFIG_NET_VENDOR_FARADAY is not set 58# CONFIG_NET_VENDOR_FARADAY is not set
73# CONFIG_NET_VENDOR_INTEL is not set 59# CONFIG_NET_VENDOR_INTEL is not set
74# CONFIG_NET_VENDOR_MARVELL is not set 60# CONFIG_NET_VENDOR_MARVELL is not set
75# CONFIG_NET_VENDOR_MICREL is not set 61# CONFIG_NET_VENDOR_MICREL is not set
76# CONFIG_NET_VENDOR_NATSEMI is not set 62# CONFIG_NET_VENDOR_NATSEMI is not set
63CONFIG_SH_ETH=y
77# CONFIG_NET_VENDOR_SEEQ is not set 64# CONFIG_NET_VENDOR_SEEQ is not set
78CONFIG_SMSC911X=y 65# CONFIG_NET_VENDOR_SMSC is not set
79# CONFIG_NET_VENDOR_STMICRO is not set 66# CONFIG_NET_VENDOR_STMICRO is not set
80CONFIG_B43=y 67# CONFIG_NET_VENDOR_VIA is not set
81CONFIG_B43_PHY_N=y 68# CONFIG_NET_VENDOR_WIZNET is not set
82CONFIG_B43_DEBUG=y 69# CONFIG_WLAN is not set
83CONFIG_INPUT_SPARSEKMAP=y
84# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 70# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
85CONFIG_INPUT_EVDEV=y 71CONFIG_INPUT_EVDEV=y
86# CONFIG_KEYBOARD_ATKBD is not set 72# CONFIG_KEYBOARD_ATKBD is not set
87CONFIG_KEYBOARD_GPIO=y 73CONFIG_KEYBOARD_GPIO=y
88CONFIG_KEYBOARD_SH_KEYSC=y
89# CONFIG_INPUT_MOUSE is not set 74# CONFIG_INPUT_MOUSE is not set
75# CONFIG_SERIO is not set
90# CONFIG_LEGACY_PTYS is not set 76# CONFIG_LEGACY_PTYS is not set
91CONFIG_SERIAL_SH_SCI=y 77CONFIG_SERIAL_SH_SCI=y
92CONFIG_SERIAL_SH_SCI_NR_UARTS=9 78CONFIG_SERIAL_SH_SCI_NR_UARTS=10
93CONFIG_SERIAL_SH_SCI_CONSOLE=y 79CONFIG_SERIAL_SH_SCI_CONSOLE=y
94# CONFIG_HW_RANDOM is not set 80# CONFIG_HW_RANDOM is not set
81CONFIG_I2C=y
82CONFIG_I2C_GPIO=y
95CONFIG_I2C_SH_MOBILE=y 83CONFIG_I2C_SH_MOBILE=y
84CONFIG_GPIO_SH_PFC=y
85CONFIG_GPIOLIB=y
86CONFIG_GPIO_RCAR=y
96# CONFIG_HWMON is not set 87# CONFIG_HWMON is not set
97CONFIG_BCMA=y 88CONFIG_THERMAL=y
98CONFIG_BCMA_DEBUG=y 89CONFIG_RCAR_THERMAL=y
99CONFIG_FB=y 90CONFIG_REGULATOR=y
100CONFIG_FB_SH_MOBILE_LCDC=y 91CONFIG_REGULATOR_FIXED_VOLTAGE=y
101CONFIG_LCD_PLATFORM=y
102CONFIG_FRAMEBUFFER_CONSOLE=y
103CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
104# CONFIG_HID_SUPPORT is not set
105# CONFIG_USB_SUPPORT is not set 92# CONFIG_USB_SUPPORT is not set
106CONFIG_MMC=y 93CONFIG_MMC=y
107CONFIG_MMC_SDHI=y 94CONFIG_MMC_SDHI=y
@@ -109,13 +96,25 @@ CONFIG_MMC_SH_MMCIF=y
109CONFIG_NEW_LEDS=y 96CONFIG_NEW_LEDS=y
110CONFIG_LEDS_CLASS=y 97CONFIG_LEDS_CLASS=y
111CONFIG_LEDS_GPIO=y 98CONFIG_LEDS_GPIO=y
112CONFIG_LEDS_RENESAS_TPU=y 99CONFIG_RTC_CLASS=y
113CONFIG_LEDS_TRIGGERS=y 100CONFIG_DMADEVICES=y
101CONFIG_SH_DMAE=y
102# CONFIG_IOMMU_SUPPORT is not set
114# CONFIG_DNOTIFY is not set 103# CONFIG_DNOTIFY is not set
104CONFIG_MSDOS_FS=y
105CONFIG_VFAT_FS=y
115CONFIG_TMPFS=y 106CONFIG_TMPFS=y
107CONFIG_CONFIGFS_FS=y
116# CONFIG_MISC_FILESYSTEMS is not set 108# CONFIG_MISC_FILESYSTEMS is not set
117CONFIG_MAGIC_SYSRQ=y 109CONFIG_NFS_FS=y
118CONFIG_DEBUG_INFO=y 110CONFIG_NFS_V3_ACL=y
119CONFIG_DEBUG_INFO_REDUCED=y 111CONFIG_NFS_V4=y
120# CONFIG_FTRACE is not set 112CONFIG_NFS_V4_1=y
121CONFIG_DEBUG_USER=y 113CONFIG_ROOT_NFS=y
114CONFIG_NLS_CODEPAGE_437=y
115CONFIG_NLS_ISO8859_1=y
116# CONFIG_ENABLE_WARN_DEPRECATED is not set
117# CONFIG_ENABLE_MUST_CHECK is not set
118# CONFIG_ARM_UNWIND is not set
119# CONFIG_CRYPTO_ANSI_CPRNG is not set
120# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/marzen_defconfig b/arch/arm/configs/marzen_defconfig
index c50e52be4463..000e9205b2b9 100644
--- a/arch/arm/configs/marzen_defconfig
+++ b/arch/arm/configs/marzen_defconfig
@@ -29,6 +29,7 @@ CONFIG_AEABI=y
29CONFIG_HIGHMEM=y 29CONFIG_HIGHMEM=y
30CONFIG_ZBOOT_ROM_TEXT=0x0 30CONFIG_ZBOOT_ROM_TEXT=0x0
31CONFIG_ZBOOT_ROM_BSS=0x0 31CONFIG_ZBOOT_ROM_BSS=0x0
32CONFIG_ARM_APPENDED_DTB=y
32CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on" 33CONFIG_CMDLINE="console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on"
33CONFIG_CMDLINE_FORCE=y 34CONFIG_CMDLINE_FORCE=y
34CONFIG_KEXEC=y 35CONFIG_KEXEC=y
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 731814e2c189..594d706b641f 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -39,6 +39,8 @@ CONFIG_MVNETA=y
39CONFIG_MARVELL_PHY=y 39CONFIG_MARVELL_PHY=y
40CONFIG_MWIFIEX=y 40CONFIG_MWIFIEX=y
41CONFIG_MWIFIEX_SDIO=y 41CONFIG_MWIFIEX_SDIO=y
42CONFIG_INPUT_EVDEV=y
43CONFIG_KEYBOARD_GPIO=y
42CONFIG_SERIAL_8250=y 44CONFIG_SERIAL_8250=y
43CONFIG_SERIAL_8250_CONSOLE=y 45CONFIG_SERIAL_8250_CONSOLE=y
44CONFIG_I2C=y 46CONFIG_I2C=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 1d6d8fb7f4a1..4555c025629a 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -1,4 +1,3 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 1CONFIG_SYSVIPC=y
3CONFIG_NO_HZ=y 2CONFIG_NO_HZ=y
4CONFIG_HIGH_RES_TIMERS=y 3CONFIG_HIGH_RES_TIMERS=y
@@ -27,7 +26,6 @@ CONFIG_ARCH_MXS=y
27# CONFIG_ARM_THUMB is not set 26# CONFIG_ARM_THUMB is not set
28CONFIG_PREEMPT_VOLUNTARY=y 27CONFIG_PREEMPT_VOLUNTARY=y
29CONFIG_AEABI=y 28CONFIG_AEABI=y
30CONFIG_AUTO_ZRELADDR=y
31CONFIG_FPE_NWFPE=y 29CONFIG_FPE_NWFPE=y
32CONFIG_NET=y 30CONFIG_NET=y
33CONFIG_PACKET=y 31CONFIG_PACKET=y
@@ -43,8 +41,6 @@ CONFIG_SYN_COOKIES=y
43# CONFIG_INET_DIAG is not set 41# CONFIG_INET_DIAG is not set
44# CONFIG_IPV6 is not set 42# CONFIG_IPV6 is not set
45CONFIG_CAN=m 43CONFIG_CAN=m
46CONFIG_CAN_RAW=m
47CONFIG_CAN_BCM=m
48CONFIG_CAN_FLEXCAN=m 44CONFIG_CAN_FLEXCAN=m
49# CONFIG_WIRELESS is not set 45# CONFIG_WIRELESS is not set
50CONFIG_DEVTMPFS=y 46CONFIG_DEVTMPFS=y
@@ -52,7 +48,6 @@ CONFIG_DEVTMPFS_MOUNT=y
52# CONFIG_FIRMWARE_IN_KERNEL is not set 48# CONFIG_FIRMWARE_IN_KERNEL is not set
53CONFIG_MTD=y 49CONFIG_MTD=y
54CONFIG_MTD_CMDLINE_PARTS=y 50CONFIG_MTD_CMDLINE_PARTS=y
55CONFIG_MTD_CHAR=y
56CONFIG_MTD_BLOCK=y 51CONFIG_MTD_BLOCK=y
57CONFIG_MTD_DATAFLASH=y 52CONFIG_MTD_DATAFLASH=y
58CONFIG_MTD_M25P80=y 53CONFIG_MTD_M25P80=y
@@ -67,12 +62,12 @@ CONFIG_SCSI=y
67CONFIG_BLK_DEV_SD=y 62CONFIG_BLK_DEV_SD=y
68CONFIG_NETDEVICES=y 63CONFIG_NETDEVICES=y
69CONFIG_ENC28J60=y 64CONFIG_ENC28J60=y
70CONFIG_USB_USBNET=y
71CONFIG_USB_NET_SMSC95XX=y
72CONFIG_SMSC_PHY=y 65CONFIG_SMSC_PHY=y
73CONFIG_ICPLUS_PHY=y 66CONFIG_ICPLUS_PHY=y
74CONFIG_REALTEK_PHY=y 67CONFIG_REALTEK_PHY=y
75CONFIG_MICREL_PHY=y 68CONFIG_MICREL_PHY=y
69CONFIG_USB_USBNET=y
70CONFIG_USB_NET_SMSC95XX=y
76# CONFIG_WLAN is not set 71# CONFIG_WLAN is not set
77# CONFIG_INPUT_MOUSEDEV_PSAUX is not set 72# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
78CONFIG_INPUT_EVDEV=y 73CONFIG_INPUT_EVDEV=y
@@ -110,7 +105,6 @@ CONFIG_LCD_CLASS_DEVICE=y
110CONFIG_BACKLIGHT_CLASS_DEVICE=y 105CONFIG_BACKLIGHT_CLASS_DEVICE=y
111CONFIG_BACKLIGHT_PWM=y 106CONFIG_BACKLIGHT_PWM=y
112CONFIG_FRAMEBUFFER_CONSOLE=y 107CONFIG_FRAMEBUFFER_CONSOLE=y
113CONFIG_FONTS=y
114CONFIG_LOGO=y 108CONFIG_LOGO=y
115CONFIG_SOUND=y 109CONFIG_SOUND=y
116CONFIG_SND=y 110CONFIG_SND=y
@@ -119,9 +113,9 @@ CONFIG_SND_MXS_SOC=y
119CONFIG_SND_SOC_MXS_SGTL5000=y 113CONFIG_SND_SOC_MXS_SGTL5000=y
120CONFIG_USB=y 114CONFIG_USB=y
121CONFIG_USB_EHCI_HCD=y 115CONFIG_USB_EHCI_HCD=y
116CONFIG_USB_STORAGE=y
122CONFIG_USB_CHIPIDEA=y 117CONFIG_USB_CHIPIDEA=y
123CONFIG_USB_CHIPIDEA_HOST=y 118CONFIG_USB_CHIPIDEA_HOST=y
124CONFIG_USB_STORAGE=y
125CONFIG_USB_PHY=y 119CONFIG_USB_PHY=y
126CONFIG_USB_MXS_PHY=y 120CONFIG_USB_MXS_PHY=y
127CONFIG_MMC=y 121CONFIG_MMC=y
@@ -143,9 +137,9 @@ CONFIG_DMADEVICES=y
143CONFIG_MXS_DMA=y 137CONFIG_MXS_DMA=y
144CONFIG_STAGING=y 138CONFIG_STAGING=y
145CONFIG_MXS_LRADC=y 139CONFIG_MXS_LRADC=y
146CONFIG_IIO_SYSFS_TRIGGER=y
147CONFIG_COMMON_CLK_DEBUG=y 140CONFIG_COMMON_CLK_DEBUG=y
148CONFIG_IIO=y 141CONFIG_IIO=y
142CONFIG_IIO_SYSFS_TRIGGER=y
149CONFIG_PWM=y 143CONFIG_PWM=y
150CONFIG_PWM_MXS=y 144CONFIG_PWM_MXS=y
151CONFIG_EXT2_FS=y 145CONFIG_EXT2_FS=y
@@ -173,14 +167,14 @@ CONFIG_NLS_CODEPAGE_850=y
173CONFIG_NLS_ISO8859_1=y 167CONFIG_NLS_ISO8859_1=y
174CONFIG_NLS_ISO8859_15=y 168CONFIG_NLS_ISO8859_15=y
175CONFIG_PRINTK_TIME=y 169CONFIG_PRINTK_TIME=y
170CONFIG_DEBUG_INFO=y
176CONFIG_FRAME_WARN=2048 171CONFIG_FRAME_WARN=2048
177CONFIG_MAGIC_SYSRQ=y
178CONFIG_UNUSED_SYMBOLS=y 172CONFIG_UNUSED_SYMBOLS=y
173CONFIG_MAGIC_SYSRQ=y
179CONFIG_DEBUG_KERNEL=y 174CONFIG_DEBUG_KERNEL=y
180CONFIG_LOCKUP_DETECTOR=y 175CONFIG_LOCKUP_DETECTOR=y
181CONFIG_TIMER_STATS=y 176CONFIG_TIMER_STATS=y
182CONFIG_PROVE_LOCKING=y 177CONFIG_PROVE_LOCKING=y
183CONFIG_DEBUG_INFO=y
184CONFIG_BLK_DEV_IO_TRACE=y 178CONFIG_BLK_DEV_IO_TRACE=y
185CONFIG_STRICT_DEVMEM=y 179CONFIG_STRICT_DEVMEM=y
186CONFIG_DEBUG_USER=y 180CONFIG_DEBUG_USER=y
@@ -188,3 +182,4 @@ CONFIG_DEBUG_USER=y
188# CONFIG_CRYPTO_HW is not set 182# CONFIG_CRYPTO_HW is not set
189CONFIG_CRC_ITU_T=m 183CONFIG_CRC_ITU_T=m
190CONFIG_CRC7=m 184CONFIG_CRC7=m
185CONFIG_FONTS=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 056b27aafbe6..254cf0539439 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -305,3 +305,4 @@ CONFIG_TI_DAVINCI_MDIO=y
305CONFIG_TI_DAVINCI_CPDMA=y 305CONFIG_TI_DAVINCI_CPDMA=y
306CONFIG_TI_CPSW=y 306CONFIG_TI_CPSW=y
307CONFIG_AT803X_PHY=y 307CONFIG_AT803X_PHY=y
308CONFIG_SOC_DRA7XX=y
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 92d0a149aeb5..ea042e80e54d 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -1,3 +1,4 @@
1CONFIG_SYSVIPC=y
1CONFIG_NO_HZ=y 2CONFIG_NO_HZ=y
2CONFIG_HIGH_RES_TIMERS=y 3CONFIG_HIGH_RES_TIMERS=y
3CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
@@ -26,8 +27,11 @@ CONFIG_ARCH_TEGRA=y
26CONFIG_ARCH_TEGRA_2x_SOC=y 27CONFIG_ARCH_TEGRA_2x_SOC=y
27CONFIG_ARCH_TEGRA_3x_SOC=y 28CONFIG_ARCH_TEGRA_3x_SOC=y
28CONFIG_ARCH_TEGRA_114_SOC=y 29CONFIG_ARCH_TEGRA_114_SOC=y
29CONFIG_TEGRA_PCI=y
30CONFIG_TEGRA_EMC_SCALING_ENABLE=y 30CONFIG_TEGRA_EMC_SCALING_ENABLE=y
31CONFIG_PCI=y
32CONFIG_PCI_MSI=y
33CONFIG_PCI_TEGRA=y
34CONFIG_PCIEPORTBUS=y
31CONFIG_SMP=y 35CONFIG_SMP=y
32CONFIG_PREEMPT=y 36CONFIG_PREEMPT=y
33CONFIG_AEABI=y 37CONFIG_AEABI=y
@@ -92,6 +96,7 @@ CONFIG_ISL29003=y
92CONFIG_SCSI=y 96CONFIG_SCSI=y
93CONFIG_BLK_DEV_SD=y 97CONFIG_BLK_DEV_SD=y
94CONFIG_BLK_DEV_SR=y 98CONFIG_BLK_DEV_SR=y
99CONFIG_SCSI_MULTI_LUN=y
95# CONFIG_SCSI_LOWLEVEL is not set 100# CONFIG_SCSI_LOWLEVEL is not set
96CONFIG_NETDEVICES=y 101CONFIG_NETDEVICES=y
97CONFIG_DUMMY=y 102CONFIG_DUMMY=y
@@ -106,6 +111,7 @@ CONFIG_RT2800USB=m
106CONFIG_INPUT_EVDEV=y 111CONFIG_INPUT_EVDEV=y
107CONFIG_KEYBOARD_GPIO=y 112CONFIG_KEYBOARD_GPIO=y
108CONFIG_KEYBOARD_TEGRA=y 113CONFIG_KEYBOARD_TEGRA=y
114CONFIG_MOUSE_PS2_ELANTECH=y
109CONFIG_INPUT_MISC=y 115CONFIG_INPUT_MISC=y
110CONFIG_INPUT_MPU3050=y 116CONFIG_INPUT_MPU3050=y
111# CONFIG_LEGACY_PTYS is not set 117# CONFIG_LEGACY_PTYS is not set
@@ -178,6 +184,7 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
178CONFIG_SND_SOC_TEGRA_TRIMSLICE=y 184CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
179CONFIG_SND_SOC_TEGRA_ALC5632=y 185CONFIG_SND_SOC_TEGRA_ALC5632=y
180CONFIG_USB=y 186CONFIG_USB=y
187CONFIG_USB_XHCI_HCD=y
181CONFIG_USB_EHCI_HCD=y 188CONFIG_USB_EHCI_HCD=y
182CONFIG_USB_EHCI_TEGRA=y 189CONFIG_USB_EHCI_TEGRA=y
183CONFIG_USB_ACM=y 190CONFIG_USB_ACM=y
diff --git a/arch/arm/include/asm/dma-contiguous.h b/arch/arm/include/asm/dma-contiguous.h
index e072bb2ba1b1..4f8e9e5514b1 100644
--- a/arch/arm/include/asm/dma-contiguous.h
+++ b/arch/arm/include/asm/dma-contiguous.h
@@ -5,7 +5,6 @@
5#ifdef CONFIG_DMA_CMA 5#ifdef CONFIG_DMA_CMA
6 6
7#include <linux/types.h> 7#include <linux/types.h>
8#include <asm-generic/dma-contiguous.h>
9 8
10void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size); 9void dma_contiguous_early_fixup(phys_addr_t base, unsigned long size);
11 10
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
deleted file mode 100644
index f77ffc1eb0c2..000000000000
--- a/arch/arm/include/asm/localtimer.h
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/arm/include/asm/localtimer.h
3 *
4 * Copyright (C) 2004-2005 ARM Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_ARM_LOCALTIMER_H
11#define __ASM_ARM_LOCALTIMER_H
12
13#include <linux/errno.h>
14
15struct clock_event_device;
16
17struct local_timer_ops {
18 int (*setup)(struct clock_event_device *);
19 void (*stop)(struct clock_event_device *);
20};
21
22#ifdef CONFIG_LOCAL_TIMERS
23/*
24 * Register a local timer driver
25 */
26int local_timer_register(struct local_timer_ops *);
27#else
28static inline int local_timer_register(struct local_timer_ops *ops)
29{
30 return -ENXIO;
31}
32#endif
33
34#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 69b879ac0289..402a2bc6aa68 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -35,7 +35,7 @@ struct machine_desc {
35 unsigned int nr_irqs; /* number of IRQs */ 35 unsigned int nr_irqs; /* number of IRQs */
36 36
37#ifdef CONFIG_ZONE_DMA 37#ifdef CONFIG_ZONE_DMA
38 unsigned long dma_zone_size; /* size of DMA-able area */ 38 phys_addr_t dma_zone_size; /* size of DMA-able area */
39#endif 39#endif
40 40
41 unsigned int video_start; /* start of video RAM */ 41 unsigned int video_start; /* start of video RAM */
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index a1c90d7feb0e..454d642a4070 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -36,6 +36,8 @@ struct hw_pci {
36 resource_size_t start, 36 resource_size_t start,
37 resource_size_t size, 37 resource_size_t size,
38 resource_size_t align); 38 resource_size_t align);
39 void (*add_bus)(struct pci_bus *bus);
40 void (*remove_bus)(struct pci_bus *bus);
39}; 41};
40 42
41/* 43/*
@@ -63,6 +65,8 @@ struct pci_sys_data {
63 resource_size_t start, 65 resource_size_t start,
64 resource_size_t size, 66 resource_size_t size,
65 resource_size_t align); 67 resource_size_t align);
68 void (*add_bus)(struct pci_bus *bus);
69 void (*remove_bus)(struct pci_bus *bus);
66 void *private_data; /* platform controller private data */ 70 void *private_data; /* platform controller private data */
67}; 71};
68 72
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 12f71a190422..f94784f0e3a6 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -37,10 +37,10 @@ struct outer_cache_fns {
37 void (*resume)(void); 37 void (*resume)(void);
38}; 38};
39 39
40#ifdef CONFIG_OUTER_CACHE
41
42extern struct outer_cache_fns outer_cache; 40extern struct outer_cache_fns outer_cache;
43 41
42#ifdef CONFIG_OUTER_CACHE
43
44static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) 44static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
45{ 45{
46 if (outer_cache.inv_range) 46 if (outer_cache.inv_range)
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/include/debug/msm.S
index 0e05f88abcd5..9166e1bc470e 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/include/debug/msm.S
@@ -15,8 +15,36 @@
15 * 15 *
16 */ 16 */
17 17
18#include <mach/hardware.h> 18#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_QSD8X50)
19#include <mach/msm_iomap.h> 19#define MSM_UART1_PHYS 0xA9A00000
20#define MSM_UART2_PHYS 0xA9B00000
21#define MSM_UART3_PHYS 0xA9C00000
22#elif defined(CONFIG_ARCH_MSM7X30)
23#define MSM_UART1_PHYS 0xACA00000
24#define MSM_UART2_PHYS 0xACB00000
25#define MSM_UART3_PHYS 0xACC00000
26#endif
27
28#if defined(CONFIG_DEBUG_MSM_UART1)
29#define MSM_DEBUG_UART_BASE 0xE1000000
30#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
31#elif defined(CONFIG_DEBUG_MSM_UART2)
32#define MSM_DEBUG_UART_BASE 0xE1000000
33#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
34#elif defined(CONFIG_DEBUG_MSM_UART3)
35#define MSM_DEBUG_UART_BASE 0xE1000000
36#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
37#endif
38
39#ifdef CONFIG_DEBUG_MSM8660_UART
40#define MSM_DEBUG_UART_BASE 0xF0040000
41#define MSM_DEBUG_UART_PHYS 0x19C40000
42#endif
43
44#ifdef CONFIG_DEBUG_MSM8960_UART
45#define MSM_DEBUG_UART_BASE 0xF0040000
46#define MSM_DEBUG_UART_PHYS 0x16440000
47#endif
20 48
21 .macro addruart, rp, rv, tmp 49 .macro addruart, rp, rv, tmp
22#ifdef MSM_DEBUG_UART_PHYS 50#ifdef MSM_DEBUG_UART_PHYS
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 88e14d74b6de..317da88ae65b 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -363,6 +363,20 @@ void pcibios_fixup_bus(struct pci_bus *bus)
363} 363}
364EXPORT_SYMBOL(pcibios_fixup_bus); 364EXPORT_SYMBOL(pcibios_fixup_bus);
365 365
366void pcibios_add_bus(struct pci_bus *bus)
367{
368 struct pci_sys_data *sys = bus->sysdata;
369 if (sys->add_bus)
370 sys->add_bus(bus);
371}
372
373void pcibios_remove_bus(struct pci_bus *bus)
374{
375 struct pci_sys_data *sys = bus->sysdata;
376 if (sys->remove_bus)
377 sys->remove_bus(bus);
378}
379
366/* 380/*
367 * Swizzle the device pin each time we cross a bridge. If a platform does 381 * Swizzle the device pin each time we cross a bridge. If a platform does
368 * not provide a swizzle function, we perform the standard PCI swizzling. 382 * not provide a swizzle function, we perform the standard PCI swizzling.
@@ -464,6 +478,8 @@ static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
464 sys->swizzle = hw->swizzle; 478 sys->swizzle = hw->swizzle;
465 sys->map_irq = hw->map_irq; 479 sys->map_irq = hw->map_irq;
466 sys->align_resource = hw->align_resource; 480 sys->align_resource = hw->align_resource;
481 sys->add_bus = hw->add_bus;
482 sys->remove_bus = hw->remove_bus;
467 INIT_LIST_HEAD(&sys->resources); 483 INIT_LIST_HEAD(&sys->resources);
468 484
469 if (hw->private_data) 485 if (hw->private_data)
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 92d10e503746..72024ea8a3a6 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -41,7 +41,6 @@
41#include <asm/sections.h> 41#include <asm/sections.h>
42#include <asm/tlbflush.h> 42#include <asm/tlbflush.h>
43#include <asm/ptrace.h> 43#include <asm/ptrace.h>
44#include <asm/localtimer.h>
45#include <asm/smp_plat.h> 44#include <asm/smp_plat.h>
46#include <asm/virt.h> 45#include <asm/virt.h>
47#include <asm/mach/arch.h> 46#include <asm/mach/arch.h>
@@ -156,8 +155,6 @@ int platform_can_cpu_hotplug(void)
156} 155}
157 156
158#ifdef CONFIG_HOTPLUG_CPU 157#ifdef CONFIG_HOTPLUG_CPU
159static void percpu_timer_stop(void);
160
161static int platform_cpu_kill(unsigned int cpu) 158static int platform_cpu_kill(unsigned int cpu)
162{ 159{
163 if (smp_ops.cpu_kill) 160 if (smp_ops.cpu_kill)
@@ -201,11 +198,6 @@ int __cpu_disable(void)
201 migrate_irqs(); 198 migrate_irqs();
202 199
203 /* 200 /*
204 * Stop the local timer for this CPU.
205 */
206 percpu_timer_stop();
207
208 /*
209 * Flush user cache and TLB mappings, and then remove this CPU 201 * Flush user cache and TLB mappings, and then remove this CPU
210 * from the vm mask set of all processes. 202 * from the vm mask set of all processes.
211 * 203 *
@@ -326,8 +318,6 @@ static void smp_store_cpu_info(unsigned int cpuid)
326 store_cpu_topology(cpuid); 318 store_cpu_topology(cpuid);
327} 319}
328 320
329static void percpu_timer_setup(void);
330
331/* 321/*
332 * This is the secondary CPU boot entry. We're using this CPUs 322 * This is the secondary CPU boot entry. We're using this CPUs
333 * idle thread stack, but a set of temporary page tables. 323 * idle thread stack, but a set of temporary page tables.
@@ -382,11 +372,6 @@ asmlinkage void secondary_start_kernel(void)
382 set_cpu_online(cpu, true); 372 set_cpu_online(cpu, true);
383 complete(&cpu_running); 373 complete(&cpu_running);
384 374
385 /*
386 * Setup the percpu timer for this CPU.
387 */
388 percpu_timer_setup();
389
390 local_irq_enable(); 375 local_irq_enable();
391 local_fiq_enable(); 376 local_fiq_enable();
392 377
@@ -424,12 +409,6 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
424 max_cpus = ncores; 409 max_cpus = ncores;
425 if (ncores > 1 && max_cpus) { 410 if (ncores > 1 && max_cpus) {
426 /* 411 /*
427 * Enable the local timer or broadcast device for the
428 * boot CPU, but only if we have more than one CPU.
429 */
430 percpu_timer_setup();
431
432 /*
433 * Initialise the present map, which describes the set of CPUs 412 * Initialise the present map, which describes the set of CPUs
434 * actually populated at the present time. A platform should 413 * actually populated at the present time. A platform should
435 * re-initialize the map in the platforms smp_prepare_cpus() 414 * re-initialize the map in the platforms smp_prepare_cpus()
@@ -505,11 +484,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
505 return sum; 484 return sum;
506} 485}
507 486
508/*
509 * Timer (local or broadcast) support
510 */
511static DEFINE_PER_CPU(struct clock_event_device, percpu_clockevent);
512
513#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 487#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
514void tick_broadcast(const struct cpumask *mask) 488void tick_broadcast(const struct cpumask *mask)
515{ 489{
@@ -517,67 +491,6 @@ void tick_broadcast(const struct cpumask *mask)
517} 491}
518#endif 492#endif
519 493
520static void broadcast_timer_set_mode(enum clock_event_mode mode,
521 struct clock_event_device *evt)
522{
523}
524
525static void broadcast_timer_setup(struct clock_event_device *evt)
526{
527 evt->name = "dummy_timer";
528 evt->features = CLOCK_EVT_FEAT_ONESHOT |
529 CLOCK_EVT_FEAT_PERIODIC |
530 CLOCK_EVT_FEAT_DUMMY;
531 evt->rating = 100;
532 evt->mult = 1;
533 evt->set_mode = broadcast_timer_set_mode;
534
535 clockevents_register_device(evt);
536}
537
538static struct local_timer_ops *lt_ops;
539
540#ifdef CONFIG_LOCAL_TIMERS
541int local_timer_register(struct local_timer_ops *ops)
542{
543 if (!is_smp() || !setup_max_cpus)
544 return -ENXIO;
545
546 if (lt_ops)
547 return -EBUSY;
548
549 lt_ops = ops;
550 return 0;
551}
552#endif
553
554static void percpu_timer_setup(void)
555{
556 unsigned int cpu = smp_processor_id();
557 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
558
559 evt->cpumask = cpumask_of(cpu);
560
561 if (!lt_ops || lt_ops->setup(evt))
562 broadcast_timer_setup(evt);
563}
564
565#ifdef CONFIG_HOTPLUG_CPU
566/*
567 * The generic clock events code purposely does not stop the local timer
568 * on CPU_DEAD/CPU_DEAD_FROZEN hotplug events, so we have to do it
569 * manually here.
570 */
571static void percpu_timer_stop(void)
572{
573 unsigned int cpu = smp_processor_id();
574 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
575
576 if (lt_ops)
577 lt_ops->stop(evt);
578}
579#endif
580
581static DEFINE_RAW_SPINLOCK(stop_lock); 494static DEFINE_RAW_SPINLOCK(stop_lock);
582 495
583/* 496/*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 25956204ef23..2985c9f0905d 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/clk.h> 13#include <linux/clk.h>
14#include <linux/cpu.h>
14#include <linux/delay.h> 15#include <linux/delay.h>
15#include <linux/device.h> 16#include <linux/device.h>
16#include <linux/err.h> 17#include <linux/err.h>
@@ -24,7 +25,6 @@
24 25
25#include <asm/smp_plat.h> 26#include <asm/smp_plat.h>
26#include <asm/smp_twd.h> 27#include <asm/smp_twd.h>
27#include <asm/localtimer.h>
28 28
29/* set up by the platform code */ 29/* set up by the platform code */
30static void __iomem *twd_base; 30static void __iomem *twd_base;
@@ -33,7 +33,7 @@ static struct clk *twd_clk;
33static unsigned long twd_timer_rate; 33static unsigned long twd_timer_rate;
34static DEFINE_PER_CPU(bool, percpu_setup_called); 34static DEFINE_PER_CPU(bool, percpu_setup_called);
35 35
36static struct clock_event_device __percpu **twd_evt; 36static struct clock_event_device __percpu *twd_evt;
37static int twd_ppi; 37static int twd_ppi;
38 38
39static void twd_set_mode(enum clock_event_mode mode, 39static void twd_set_mode(enum clock_event_mode mode,
@@ -90,8 +90,10 @@ static int twd_timer_ack(void)
90 return 0; 90 return 0;
91} 91}
92 92
93static void twd_timer_stop(struct clock_event_device *clk) 93static void twd_timer_stop(void)
94{ 94{
95 struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
96
95 twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk); 97 twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
96 disable_percpu_irq(clk->irq); 98 disable_percpu_irq(clk->irq);
97} 99}
@@ -106,7 +108,7 @@ static void twd_update_frequency(void *new_rate)
106{ 108{
107 twd_timer_rate = *((unsigned long *) new_rate); 109 twd_timer_rate = *((unsigned long *) new_rate);
108 110
109 clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); 111 clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
110} 112}
111 113
112static int twd_rate_change(struct notifier_block *nb, 114static int twd_rate_change(struct notifier_block *nb,
@@ -132,7 +134,7 @@ static struct notifier_block twd_clk_nb = {
132 134
133static int twd_clk_init(void) 135static int twd_clk_init(void)
134{ 136{
135 if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) 137 if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
136 return clk_notifier_register(twd_clk, &twd_clk_nb); 138 return clk_notifier_register(twd_clk, &twd_clk_nb);
137 139
138 return 0; 140 return 0;
@@ -151,7 +153,7 @@ static void twd_update_frequency(void *data)
151{ 153{
152 twd_timer_rate = clk_get_rate(twd_clk); 154 twd_timer_rate = clk_get_rate(twd_clk);
153 155
154 clockevents_update_freq(*__this_cpu_ptr(twd_evt), twd_timer_rate); 156 clockevents_update_freq(__this_cpu_ptr(twd_evt), twd_timer_rate);
155} 157}
156 158
157static int twd_cpufreq_transition(struct notifier_block *nb, 159static int twd_cpufreq_transition(struct notifier_block *nb,
@@ -177,7 +179,7 @@ static struct notifier_block twd_cpufreq_nb = {
177 179
178static int twd_cpufreq_init(void) 180static int twd_cpufreq_init(void)
179{ 181{
180 if (twd_evt && *__this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk)) 182 if (twd_evt && __this_cpu_ptr(twd_evt) && !IS_ERR(twd_clk))
181 return cpufreq_register_notifier(&twd_cpufreq_nb, 183 return cpufreq_register_notifier(&twd_cpufreq_nb,
182 CPUFREQ_TRANSITION_NOTIFIER); 184 CPUFREQ_TRANSITION_NOTIFIER);
183 185
@@ -228,7 +230,7 @@ static void twd_calibrate_rate(void)
228 230
229static irqreturn_t twd_handler(int irq, void *dev_id) 231static irqreturn_t twd_handler(int irq, void *dev_id)
230{ 232{
231 struct clock_event_device *evt = *(struct clock_event_device **)dev_id; 233 struct clock_event_device *evt = dev_id;
232 234
233 if (twd_timer_ack()) { 235 if (twd_timer_ack()) {
234 evt->event_handler(evt); 236 evt->event_handler(evt);
@@ -265,9 +267,9 @@ static void twd_get_clock(struct device_node *np)
265/* 267/*
266 * Setup the local clock events for a CPU. 268 * Setup the local clock events for a CPU.
267 */ 269 */
268static int twd_timer_setup(struct clock_event_device *clk) 270static void twd_timer_setup(void)
269{ 271{
270 struct clock_event_device **this_cpu_clk; 272 struct clock_event_device *clk = __this_cpu_ptr(twd_evt);
271 int cpu = smp_processor_id(); 273 int cpu = smp_processor_id();
272 274
273 /* 275 /*
@@ -276,9 +278,9 @@ static int twd_timer_setup(struct clock_event_device *clk)
276 */ 278 */
277 if (per_cpu(percpu_setup_called, cpu)) { 279 if (per_cpu(percpu_setup_called, cpu)) {
278 __raw_writel(0, twd_base + TWD_TIMER_CONTROL); 280 __raw_writel(0, twd_base + TWD_TIMER_CONTROL);
279 clockevents_register_device(*__this_cpu_ptr(twd_evt)); 281 clockevents_register_device(clk);
280 enable_percpu_irq(clk->irq, 0); 282 enable_percpu_irq(clk->irq, 0);
281 return 0; 283 return;
282 } 284 }
283 per_cpu(percpu_setup_called, cpu) = true; 285 per_cpu(percpu_setup_called, cpu) = true;
284 286
@@ -297,27 +299,37 @@ static int twd_timer_setup(struct clock_event_device *clk)
297 clk->set_mode = twd_set_mode; 299 clk->set_mode = twd_set_mode;
298 clk->set_next_event = twd_set_next_event; 300 clk->set_next_event = twd_set_next_event;
299 clk->irq = twd_ppi; 301 clk->irq = twd_ppi;
300 302 clk->cpumask = cpumask_of(cpu);
301 this_cpu_clk = __this_cpu_ptr(twd_evt);
302 *this_cpu_clk = clk;
303 303
304 clockevents_config_and_register(clk, twd_timer_rate, 304 clockevents_config_and_register(clk, twd_timer_rate,
305 0xf, 0xffffffff); 305 0xf, 0xffffffff);
306 enable_percpu_irq(clk->irq, 0); 306 enable_percpu_irq(clk->irq, 0);
307}
307 308
308 return 0; 309static int twd_timer_cpu_notify(struct notifier_block *self,
310 unsigned long action, void *hcpu)
311{
312 switch (action & ~CPU_TASKS_FROZEN) {
313 case CPU_STARTING:
314 twd_timer_setup();
315 break;
316 case CPU_DYING:
317 twd_timer_stop();
318 break;
319 }
320
321 return NOTIFY_OK;
309} 322}
310 323
311static struct local_timer_ops twd_lt_ops = { 324static struct notifier_block twd_timer_cpu_nb = {
312 .setup = twd_timer_setup, 325 .notifier_call = twd_timer_cpu_notify,
313 .stop = twd_timer_stop,
314}; 326};
315 327
316static int __init twd_local_timer_common_register(struct device_node *np) 328static int __init twd_local_timer_common_register(struct device_node *np)
317{ 329{
318 int err; 330 int err;
319 331
320 twd_evt = alloc_percpu(struct clock_event_device *); 332 twd_evt = alloc_percpu(struct clock_event_device);
321 if (!twd_evt) { 333 if (!twd_evt) {
322 err = -ENOMEM; 334 err = -ENOMEM;
323 goto out_free; 335 goto out_free;
@@ -329,12 +341,22 @@ static int __init twd_local_timer_common_register(struct device_node *np)
329 goto out_free; 341 goto out_free;
330 } 342 }
331 343
332 err = local_timer_register(&twd_lt_ops); 344 err = register_cpu_notifier(&twd_timer_cpu_nb);
333 if (err) 345 if (err)
334 goto out_irq; 346 goto out_irq;
335 347
336 twd_get_clock(np); 348 twd_get_clock(np);
337 349
350 /*
351 * Immediately configure the timer on the boot CPU, unless we need
352 * jiffies to be incrementing to calibrate the rate in which case
353 * setup the timer in late_time_init.
354 */
355 if (twd_timer_rate)
356 twd_timer_setup();
357 else
358 late_time_init = twd_timer_setup;
359
338 return 0; 360 return 0;
339 361
340out_irq: 362out_irq:
diff --git a/arch/arm/mach-at91/board-dt-sama5.c b/arch/arm/mach-at91/board-dt-sama5.c
index ad95f6a23a28..bf00d15d954d 100644
--- a/arch/arm/mach-at91/board-dt-sama5.c
+++ b/arch/arm/mach-at91/board-dt-sama5.c
@@ -42,20 +42,15 @@ static int ksz9021rn_phy_fixup(struct phy_device *phy)
42{ 42{
43 int value; 43 int value;
44 44
45#define GMII_RCCPSR 260
46#define GMII_RRDPSR 261
47#define GMII_ERCR 11
48#define GMII_ERDWR 12
49
50 /* Set delay values */ 45 /* Set delay values */
51 value = GMII_RCCPSR | 0x8000; 46 value = MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW | 0x8000;
52 phy_write(phy, GMII_ERCR, value); 47 phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
53 value = 0xF2F4; 48 value = 0xF2F4;
54 phy_write(phy, GMII_ERDWR, value); 49 phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
55 value = GMII_RRDPSR | 0x8000; 50 value = MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW | 0x8000;
56 phy_write(phy, GMII_ERCR, value); 51 phy_write(phy, MICREL_KSZ9021_EXTREG_CTRL, value);
57 value = 0x2222; 52 value = 0x2222;
58 phy_write(phy, GMII_ERDWR, value); 53 phy_write(phy, MICREL_KSZ9021_EXTREG_DATA_WRITE, value);
59 54
60 return 0; 55 return 0;
61} 56}
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3aaa9784cf0e..f1d49e929ccb 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -26,7 +26,7 @@
26#include <linux/gpio.h> 26#include <linux/gpio.h>
27#include <linux/platform_device.h> 27#include <linux/platform_device.h>
28#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
29#include <linux/i2c/pca953x.h> 29#include <linux/platform_data/pca953x.h>
30 30
31#include <asm/mach-types.h> 31#include <asm/mach-types.h>
32#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a832e0707611..f17aa3150019 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -33,6 +33,7 @@
33#include <mach/at91sam9g45.h> 33#include <mach/at91sam9g45.h>
34#include <mach/at91sam9x5.h> 34#include <mach/at91sam9x5.h>
35#include <mach/at91sam9n12.h> 35#include <mach/at91sam9n12.h>
36#include <mach/sama5d3.h>
36 37
37/* 38/*
38 * On all at91 except rm9200 and x40 have the System Controller starts 39 * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 6dc81ee38048..31096a8aaf1d 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -65,6 +65,14 @@
65#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ 65#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
66 66
67/* 67/*
68 * User Peripheral physical base addresses.
69 */
70#define SAMA5D3_BASE_USART0 0xf001c000
71#define SAMA5D3_BASE_USART1 0xf0020000
72#define SAMA5D3_BASE_USART2 0xf8020000
73#define SAMA5D3_BASE_USART3 0xf8024000
74
75/*
68 * Internal Memory 76 * Internal Memory
69 */ 77 */
70#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 78#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 5659f7c72120..4bb644f8e87c 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,6 +94,15 @@ static const u32 uarts_sam9x5[] = {
94 0, 94 0,
95}; 95};
96 96
97static const u32 uarts_sama5[] = {
98 AT91_BASE_DBGU1,
99 SAMA5D3_BASE_USART0,
100 SAMA5D3_BASE_USART1,
101 SAMA5D3_BASE_USART2,
102 SAMA5D3_BASE_USART3,
103 0,
104};
105
97static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) 106static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
98{ 107{
99 u32 cidr, socid; 108 u32 cidr, socid;
@@ -121,8 +130,12 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
121 case ARCH_ID_AT91SAM9RL64: 130 case ARCH_ID_AT91SAM9RL64:
122 return uarts_sam9rl; 131 return uarts_sam9rl;
123 132
133 case ARCH_ID_AT91SAM9N12:
124 case ARCH_ID_AT91SAM9X5: 134 case ARCH_ID_AT91SAM9X5:
125 return uarts_sam9x5; 135 return uarts_sam9x5;
136
137 case ARCH_ID_SAMA5D3:
138 return uarts_sama5;
126 } 139 }
127 140
128 /* at91sam9g10 */ 141 /* at91sam9g10 */
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index f11289519c39..69d67f714a2f 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -12,6 +12,7 @@ config ARCH_BCM
12 select GPIO_BCM 12 select GPIO_BCM
13 select SPARSE_IRQ 13 select SPARSE_IRQ
14 select TICK_ONESHOT 14 select TICK_ONESHOT
15 select CACHE_L2X0
15 help 16 help
16 This enables support for system based on Broadcom SoCs. 17 This enables support for system based on Broadcom SoCs.
17 It currently supports the 'BCM281XX' family, which includes 18 It currently supports the 'BCM281XX' family, which includes
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 6adb6aecf48f..e3d03033a7e2 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -1,5 +1,5 @@
1# 1#
2# Copyright (C) 2012 Broadcom Corporation 2# Copyright (C) 2012-2013 Broadcom Corporation
3# 3#
4# This program is free software; you can redistribute it and/or 4# This program is free software; you can redistribute it and/or
5# modify it under the terms of the GNU General Public License as 5# modify it under the terms of the GNU General Public License as
@@ -10,6 +10,6 @@
10# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11# GNU General Public License for more details. 11# GNU General Public License for more details.
12 12
13obj-$(CONFIG_ARCH_BCM) := board_bcm.o bcm_kona_smc.o bcm_kona_smc_asm.o 13obj-$(CONFIG_ARCH_BCM) := board_bcm281xx.o bcm_kona_smc.o bcm_kona_smc_asm.o kona.o
14plus_sec := $(call as-instr,.arch_extension sec,+sec) 14plus_sec := $(call as-instr,.arch_extension sec,+sec)
15AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec) 15AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.c b/arch/arm/mach-bcm/bcm_kona_smc.c
index 56d9d19b2470..5e31e918f325 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.c
+++ b/arch/arm/mach-bcm/bcm_kona_smc.c
@@ -36,18 +36,20 @@ struct bcm_kona_smc_data {
36}; 36};
37 37
38static const struct of_device_id bcm_kona_smc_ids[] __initconst = { 38static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
39 {.compatible = "bcm,kona-smc"}, 39 {.compatible = "brcm,kona-smc"},
40 {.compatible = "bcm,kona-smc"}, /* deprecated name */
40 {}, 41 {},
41}; 42};
42 43
43/* Map in the bounce area */ 44/* Map in the bounce area */
44void __init bcm_kona_smc_init(void) 45int __init bcm_kona_smc_init(void)
45{ 46{
46 struct device_node *node; 47 struct device_node *node;
47 48
48 /* Read buffer addr and size from the device tree node */ 49 /* Read buffer addr and size from the device tree node */
49 node = of_find_matching_node(NULL, bcm_kona_smc_ids); 50 node = of_find_matching_node(NULL, bcm_kona_smc_ids);
50 BUG_ON(!node); 51 if (!node)
52 return -ENODEV;
51 53
52 /* Don't care about size or flags of the DT node */ 54 /* Don't care about size or flags of the DT node */
53 bridge_data.buffer_addr = 55 bridge_data.buffer_addr =
@@ -59,7 +61,9 @@ void __init bcm_kona_smc_init(void)
59 61
60 bridge_data.initialized = 1; 62 bridge_data.initialized = 1;
61 63
62 pr_info("Secure API initialized!\n"); 64 pr_info("Kona Secure API initialized\n");
65
66 return 0;
63} 67}
64 68
65/* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */ 69/* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
diff --git a/arch/arm/mach-bcm/bcm_kona_smc.h b/arch/arm/mach-bcm/bcm_kona_smc.h
index 3bedbed1c21b..d098a7e76744 100644
--- a/arch/arm/mach-bcm/bcm_kona_smc.h
+++ b/arch/arm/mach-bcm/bcm_kona_smc.h
@@ -64,7 +64,7 @@
64#define SSAPI_BRCM_START_VC_CORE 0x0E000008 64#define SSAPI_BRCM_START_VC_CORE 0x0E000008
65 65
66#ifndef __ASSEMBLY__ 66#ifndef __ASSEMBLY__
67extern void bcm_kona_smc_init(void); 67extern int __init bcm_kona_smc_init(void);
68 68
69extern unsigned bcm_kona_smc(unsigned service_id, 69extern unsigned bcm_kona_smc(unsigned service_id,
70 unsigned arg0, 70 unsigned arg0,
diff --git a/arch/arm/mach-bcm/board_bcm.c b/arch/arm/mach-bcm/board_bcm281xx.c
index 28599326d4ad..8d9f931164bb 100644
--- a/arch/arm/mach-bcm/board_bcm.c
+++ b/arch/arm/mach-bcm/board_bcm281xx.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2012 Broadcom Corporation 2 * Copyright (C) 2012-2013 Broadcom Corporation
3 * 3 *
4 * This program is free software; you can redistribute it and/or 4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as 5 * modify it under the terms of the GNU General Public License as
@@ -21,23 +21,39 @@
21#include <asm/mach/time.h> 21#include <asm/mach/time.h>
22#include <asm/hardware/cache-l2x0.h> 22#include <asm/hardware/cache-l2x0.h>
23 23
24
25#include "bcm_kona_smc.h" 24#include "bcm_kona_smc.h"
25#include "kona.h"
26 26
27static int __init kona_l2_cache_init(void) 27static int __init kona_l2_cache_init(void)
28{ 28{
29 if (!IS_ENABLED(CONFIG_CACHE_L2X0)) 29 if (!IS_ENABLED(CONFIG_CACHE_L2X0))
30 return 0; 30 return 0;
31 31
32 if (bcm_kona_smc_init() < 0) {
33 pr_info("Kona secure API not available. Skipping L2 init\n");
34 return 0;
35 }
36
32 bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0); 37 bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
33 38
34 /* 39 /*
35 * The aux_val and aux_mask have no effect since L2 cache is already 40 * The aux_val and aux_mask have no effect since L2 cache is already
36 * enabled. Pass 0s for aux_val and 1s for aux_mask for default value. 41 * enabled. Pass 0s for aux_val and 1s for aux_mask for default value.
37 */ 42 */
38 l2x0_of_init(0, ~0); 43 return l2x0_of_init(0, ~0);
44}
39 45
40 return 0; 46static void bcm_board_setup_restart(void)
47{
48 struct device_node *np;
49
50 np = of_find_compatible_node(NULL, NULL, "brcm,bcm11351");
51 if (np) {
52 if (of_device_is_available(np))
53 bcm_kona_setup_restart();
54 of_node_put(np);
55 }
56 /* Restart setup for other boards goes here */
41} 57}
42 58
43static void __init board_init(void) 59static void __init board_init(void)
@@ -45,15 +61,15 @@ static void __init board_init(void)
45 of_platform_populate(NULL, of_default_bus_match_table, NULL, 61 of_platform_populate(NULL, of_default_bus_match_table, NULL,
46 &platform_bus); 62 &platform_bus);
47 63
48 bcm_kona_smc_init(); 64 bcm_board_setup_restart();
49
50 kona_l2_cache_init(); 65 kona_l2_cache_init();
51} 66}
52 67
53static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, }; 68static const char * const bcm11351_dt_compat[] = { "brcm,bcm11351", NULL, };
54 69
55DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor") 70DT_MACHINE_START(BCM11351_DT, "Broadcom Application Processor")
56 .init_time = clocksource_of_init, 71 .init_time = clocksource_of_init,
57 .init_machine = board_init, 72 .init_machine = board_init,
73 .restart = bcm_kona_restart,
58 .dt_compat = bcm11351_dt_compat, 74 .dt_compat = bcm11351_dt_compat,
59MACHINE_END 75MACHINE_END
diff --git a/arch/arm/mach-bcm/kona.c b/arch/arm/mach-bcm/kona.c
new file mode 100644
index 000000000000..6939d9017f63
--- /dev/null
+++ b/arch/arm/mach-bcm/kona.c
@@ -0,0 +1,65 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/of_address.h>
15#include <asm/io.h>
16
17#include "kona.h"
18
19static void __iomem *watchdog_base;
20
21void bcm_kona_setup_restart(void)
22{
23 struct device_node *np_wdog;
24
25 /*
26 * The assumption is that whoever calls bcm_kona_setup_restart()
27 * also needs a Kona Watchdog Timer entry in Device Tree, i.e. we
28 * report an error if the DT entry is missing.
29 */
30 np_wdog = of_find_compatible_node(NULL, NULL, "brcm,kona-wdt");
31 if (!np_wdog) {
32 pr_err("brcm,kona-wdt not found in DT, reboot disabled\n");
33 return;
34 }
35 watchdog_base = of_iomap(np_wdog, 0);
36 WARN(!watchdog_base, "failed to map watchdog base");
37 of_node_put(np_wdog);
38}
39
40#define SECWDOG_OFFSET 0x00000000
41#define SECWDOG_RESERVED_MASK 0xE2000000
42#define SECWDOG_WD_LOAD_FLAG_MASK 0x10000000
43#define SECWDOG_EN_MASK 0x08000000
44#define SECWDOG_SRSTEN_MASK 0x04000000
45#define SECWDOG_CLKS_SHIFT 20
46#define SECWDOG_LOCK_SHIFT 0
47
48void bcm_kona_restart(enum reboot_mode mode, const char *cmd)
49{
50 uint32_t val;
51
52 if (!watchdog_base)
53 panic("Watchdog not mapped. Reboot failed.\n");
54
55 /* Enable watchdog2 with very short timeout. */
56 val = readl(watchdog_base + SECWDOG_OFFSET);
57 val &= SECWDOG_RESERVED_MASK | SECWDOG_WD_LOAD_FLAG_MASK;
58 val |= SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK |
59 (0x8 << SECWDOG_CLKS_SHIFT) |
60 (0x8 << SECWDOG_LOCK_SHIFT);
61 writel(val, watchdog_base + SECWDOG_OFFSET);
62
63 while (1)
64 ;
65}
diff --git a/arch/arm/mach-bcm/kona.h b/arch/arm/mach-bcm/kona.h
new file mode 100644
index 000000000000..291eca3e06ff
--- /dev/null
+++ b/arch/arm/mach-bcm/kona.h
@@ -0,0 +1,17 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/reboot.h>
15
16void bcm_kona_setup_restart(void);
17void bcm_kona_restart(enum reboot_mode mode, const char *cmd);
diff --git a/arch/arm/mach-clps711x/Kconfig b/arch/arm/mach-clps711x/Kconfig
index 01ad4d41e728..bea6295c8c59 100644
--- a/arch/arm/mach-clps711x/Kconfig
+++ b/arch/arm/mach-clps711x/Kconfig
@@ -33,9 +33,6 @@ config ARCH_P720T
33 Say Y here if you intend to run this kernel on the ARM Prospector 33 Say Y here if you intend to run this kernel on the ARM Prospector
34 720T. 34 720T.
35 35
36config ARCH_FORTUNET
37 bool "FORTUNET"
38
39config EP72XX_ROM_BOOT 36config EP72XX_ROM_BOOT
40 bool "EP721x/EP731x ROM boot" 37 bool "EP721x/EP731x ROM boot"
41 help 38 help
diff --git a/arch/arm/mach-clps711x/Makefile b/arch/arm/mach-clps711x/Makefile
index f30ed2b496fb..f04151efd96a 100644
--- a/arch/arm/mach-clps711x/Makefile
+++ b/arch/arm/mach-clps711x/Makefile
@@ -10,5 +10,4 @@ obj-$(CONFIG_ARCH_AUTCPU12) += board-autcpu12.o
10obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o 10obj-$(CONFIG_ARCH_CDB89712) += board-cdb89712.o
11obj-$(CONFIG_ARCH_CLEP7312) += board-clep7312.o 11obj-$(CONFIG_ARCH_CLEP7312) += board-clep7312.o
12obj-$(CONFIG_ARCH_EDB7211) += board-edb7211.o 12obj-$(CONFIG_ARCH_EDB7211) += board-edb7211.o
13obj-$(CONFIG_ARCH_FORTUNET) += board-fortunet.o
14obj-$(CONFIG_ARCH_P720T) += board-p720t.o 13obj-$(CONFIG_ARCH_P720T) += board-p720t.o
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c
index 5867aebd8d0c..f8d71a89644a 100644
--- a/arch/arm/mach-clps711x/board-autcpu12.c
+++ b/arch/arm/mach-clps711x/board-autcpu12.c
@@ -259,11 +259,7 @@ static void __init autcpu12_init(void)
259static void __init autcpu12_init_late(void) 259static void __init autcpu12_init_late(void)
260{ 260{
261 gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios)); 261 gpio_request_array(autcpu12_gpios, ARRAY_SIZE(autcpu12_gpios));
262 262 platform_device_register(&autcpu12_nand_pdev);
263 if (IS_ENABLED(MTD_NAND_GPIO) && IS_ENABLED(GPIO_GENERIC_PLATFORM)) {
264 /* We are need both drivers to handle NAND */
265 platform_device_register(&autcpu12_nand_pdev);
266 }
267} 263}
268 264
269MACHINE_START(AUTCPU12, "autronix autcpu12") 265MACHINE_START(AUTCPU12, "autronix autcpu12")
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c
index 9dfb990f0801..fe6184ead896 100644
--- a/arch/arm/mach-clps711x/board-edb7211.c
+++ b/arch/arm/mach-clps711x/board-edb7211.c
@@ -126,21 +126,6 @@ static struct gpio edb7211_gpios[] __initconst = {
126 { EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" }, 126 { EDB7211_LCDBL, GPIOF_OUT_INIT_LOW, "LCD BACKLIGHT" },
127}; 127};
128 128
129static struct map_desc edb7211_io_desc[] __initdata = {
130 { /* Memory-mapped extra keyboard row */
131 .virtual = IO_ADDRESS(EDB7211_EXTKBD_BASE),
132 .pfn = __phys_to_pfn(EDB7211_EXTKBD_BASE),
133 .length = SZ_1M,
134 .type = MT_DEVICE,
135 },
136};
137
138void __init edb7211_map_io(void)
139{
140 clps711x_map_io();
141 iotable_init(edb7211_io_desc, ARRAY_SIZE(edb7211_io_desc));
142}
143
144/* Reserve screen memory region at the start of main system memory. */ 129/* Reserve screen memory region at the start of main system memory. */
145static void __init edb7211_reserve(void) 130static void __init edb7211_reserve(void)
146{ 131{
@@ -195,7 +180,7 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
195 .nr_irqs = CLPS711X_NR_IRQS, 180 .nr_irqs = CLPS711X_NR_IRQS,
196 .fixup = fixup_edb7211, 181 .fixup = fixup_edb7211,
197 .reserve = edb7211_reserve, 182 .reserve = edb7211_reserve,
198 .map_io = edb7211_map_io, 183 .map_io = clps711x_map_io,
199 .init_early = clps711x_init_early, 184 .init_early = clps711x_init_early,
200 .init_irq = clps711x_init_irq, 185 .init_irq = clps711x_init_irq,
201 .init_time = clps711x_timer_init, 186 .init_time = clps711x_timer_init,
diff --git a/arch/arm/mach-clps711x/board-fortunet.c b/arch/arm/mach-clps711x/board-fortunet.c
deleted file mode 100644
index b1561e3d7c5c..000000000000
--- a/arch/arm/mach-clps711x/board-fortunet.c
+++ /dev/null
@@ -1,85 +0,0 @@
1/*
2 * linux/arch/arm/mach-clps711x/fortunet.c
3 *
4 * Derived from linux/arch/arm/mach-integrator/arch.c
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22#include <linux/types.h>
23#include <linux/init.h>
24#include <linux/initrd.h>
25
26#include <mach/hardware.h>
27#include <asm/setup.h>
28#include <asm/mach-types.h>
29
30#include <asm/mach/arch.h>
31
32#include <asm/memory.h>
33
34#include "common.h"
35
36struct meminfo memmap = {
37 .nr_banks = 1,
38 .bank = {
39 {
40 .start = 0xC0000000,
41 .size = 0x01000000,
42 },
43 },
44};
45
46typedef struct tag_IMAGE_PARAMS
47{
48 int ramdisk_ok;
49 int ramdisk_address;
50 int ramdisk_size;
51 int ram_size;
52 int extra_param_type;
53 int extra_param_ptr;
54 int command_line;
55} IMAGE_PARAMS;
56
57#define IMAGE_PARAMS_PHYS 0xC01F0000
58
59static void __init
60fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
61{
62 IMAGE_PARAMS *ip = phys_to_virt(IMAGE_PARAMS_PHYS);
63 *cmdline = phys_to_virt(ip->command_line);
64#ifdef CONFIG_BLK_DEV_INITRD
65 if(ip->ramdisk_ok)
66 {
67 initrd_start = __phys_to_virt(ip->ramdisk_address);
68 initrd_end = initrd_start + ip->ramdisk_size;
69 }
70#endif
71 memmap.bank[0].size = ip->ram_size;
72 *mi = memmap;
73}
74
75MACHINE_START(FORTUNET, "ARM-FortuNet")
76 /* Maintainer: FortuNet Inc. */
77 .nr_irqs = CLPS711X_NR_IRQS,
78 .fixup = fortunet_fixup,
79 .map_io = clps711x_map_io,
80 .init_early = clps711x_init_early,
81 .init_irq = clps711x_init_irq,
82 .init_time = clps711x_timer_init,
83 .handle_irq = clps711x_handle_irq,
84 .restart = clps711x_restart,
85MACHINE_END
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c
index 856b81cf2f8a..fb77d1448fec 100644
--- a/arch/arm/mach-clps711x/devices.c
+++ b/arch/arm/mach-clps711x/devices.c
@@ -57,7 +57,7 @@ static void __init clps711x_add_syscon(void)
57 unsigned i; 57 unsigned i;
58 58
59 for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++) 59 for (i = 0; i < ARRAY_SIZE(clps711x_syscon_res); i++)
60 platform_device_register_simple("clps711x-syscon", i + 1, 60 platform_device_register_simple("syscon", i + 1,
61 &clps711x_syscon_res[i], 1); 61 &clps711x_syscon_res[i], 1);
62} 62}
63 63
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 1332de8c52c9..c4bdc0a1c36e 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -185,10 +185,6 @@ static __init void da830_evm_usb_init(void)
185 __func__, ret); 185 __func__, ret);
186} 186}
187 187
188static struct davinci_uart_config da830_evm_uart_config __initdata = {
189 .enabled_uarts = 0x7,
190};
191
192static const short da830_evm_mcasp1_pins[] = { 188static const short da830_evm_mcasp1_pins[] = {
193 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, 189 DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1,
194 DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, 190 DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5,
@@ -630,7 +626,7 @@ static __init void da830_evm_init(void)
630 pr_warning("da830_evm_init: watchdog registration failed: %d\n", 626 pr_warning("da830_evm_init: watchdog registration failed: %d\n",
631 ret); 627 ret);
632 628
633 davinci_serial_init(&da830_evm_uart_config); 629 davinci_serial_init(da8xx_serial_device);
634 i2c_register_board_info(1, da830_evm_i2c_devices, 630 i2c_register_board_info(1, da830_evm_i2c_devices,
635 ARRAY_SIZE(da830_evm_i2c_devices)); 631 ARRAY_SIZE(da830_evm_i2c_devices));
636 632
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 9f09f45835f8..dd1fb24521aa 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -19,7 +19,7 @@
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/i2c/at24.h> 21#include <linux/i2c/at24.h>
22#include <linux/i2c/pca953x.h> 22#include <linux/platform_data/pca953x.h>
23#include <linux/input.h> 23#include <linux/input.h>
24#include <linux/input/tps6507x-ts.h> 24#include <linux/input/tps6507x-ts.h>
25#include <linux/mfd/tps6507x.h> 25#include <linux/mfd/tps6507x.h>
@@ -746,10 +746,6 @@ static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = {
746 .bus_delay = 0, /* usec */ 746 .bus_delay = 0, /* usec */
747}; 747};
748 748
749static struct davinci_uart_config da850_evm_uart_config __initdata = {
750 .enabled_uarts = 0x7,
751};
752
753/* davinci da850 evm audio machine driver */ 749/* davinci da850 evm audio machine driver */
754static u8 da850_iis_serializer_direction[] = { 750static u8 da850_iis_serializer_direction[] = {
755 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, 751 INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE,
@@ -1492,7 +1488,7 @@ static __init void da850_evm_init(void)
1492 __func__, ret); 1488 __func__, ret);
1493 } 1489 }
1494 1490
1495 davinci_serial_init(&da850_evm_uart_config); 1491 davinci_serial_init(da8xx_serial_device);
1496 1492
1497 i2c_register_board_info(1, da850_evm_i2c_devices, 1493 i2c_register_board_info(1, da850_evm_i2c_devices,
1498 ARRAY_SIZE(da850_evm_i2c_devices)); 1494 ARRAY_SIZE(da850_evm_i2c_devices));
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index c2a0a67d09e0..42b23a3194a0 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -314,10 +314,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
314 &davinci_nand_device, 314 &davinci_nand_device,
315}; 315};
316 316
317static struct davinci_uart_config uart_config __initdata = {
318 .enabled_uarts = (1 << 0),
319};
320
321static void __init dm355_evm_map_io(void) 317static void __init dm355_evm_map_io(void)
322{ 318{
323 dm355_init(); 319 dm355_init();
@@ -393,7 +389,7 @@ static __init void dm355_evm_init(void)
393 platform_add_devices(davinci_evm_devices, 389 platform_add_devices(davinci_evm_devices,
394 ARRAY_SIZE(davinci_evm_devices)); 390 ARRAY_SIZE(davinci_evm_devices));
395 evm_init_i2c(); 391 evm_init_i2c();
396 davinci_serial_init(&uart_config); 392 davinci_serial_init(dm355_serial_device);
397 393
398 /* NOTE: NAND flash timings set by the UBL are slower than 394 /* NOTE: NAND flash timings set by the UBL are slower than
399 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 395 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 139e42da25f0..65a984c52df6 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -173,10 +173,6 @@ static struct platform_device *davinci_leopard_devices[] __initdata = {
173 &davinci_nand_device, 173 &davinci_nand_device,
174}; 174};
175 175
176static struct davinci_uart_config uart_config __initdata = {
177 .enabled_uarts = (1 << 0),
178};
179
180static void __init dm355_leopard_map_io(void) 176static void __init dm355_leopard_map_io(void)
181{ 177{
182 dm355_init(); 178 dm355_init();
@@ -252,7 +248,7 @@ static __init void dm355_leopard_init(void)
252 platform_add_devices(davinci_leopard_devices, 248 platform_add_devices(davinci_leopard_devices,
253 ARRAY_SIZE(davinci_leopard_devices)); 249 ARRAY_SIZE(davinci_leopard_devices));
254 leopard_init_i2c(); 250 leopard_init_i2c();
255 davinci_serial_init(&uart_config); 251 davinci_serial_init(dm355_serial_device);
256 252
257 /* NOTE: NAND flash timings set by the UBL are slower than 253 /* NOTE: NAND flash timings set by the UBL are slower than
258 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 254 * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 4cdb61c54459..92b7f770615a 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -718,10 +718,6 @@ fail:
718 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ 718 /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */
719} 719}
720 720
721static struct davinci_uart_config uart_config __initdata = {
722 .enabled_uarts = (1 << 0),
723};
724
725static void __init dm365_evm_map_io(void) 721static void __init dm365_evm_map_io(void)
726{ 722{
727 dm365_init(); 723 dm365_init();
@@ -748,7 +744,7 @@ static struct spi_board_info dm365_evm_spi_info[] __initconst = {
748static __init void dm365_evm_init(void) 744static __init void dm365_evm_init(void)
749{ 745{
750 evm_init_i2c(); 746 evm_init_i2c();
751 davinci_serial_init(&uart_config); 747 davinci_serial_init(dm365_serial_device);
752 748
753 dm365evm_emac_configure(); 749 dm365evm_emac_configure();
754 dm365evm_mmc_configure(); 750 dm365evm_mmc_configure();
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index fa4bfaf952d8..40bb9b5b87e8 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -727,10 +727,6 @@ static struct platform_device *davinci_evm_devices[] __initdata = {
727 &rtc_dev, 727 &rtc_dev,
728}; 728};
729 729
730static struct davinci_uart_config uart_config __initdata = {
731 .enabled_uarts = (1 << 0),
732};
733
734static void __init 730static void __init
735davinci_evm_map_io(void) 731davinci_evm_map_io(void)
736{ 732{
@@ -792,7 +788,7 @@ static __init void davinci_evm_init(void)
792 davinci_setup_mmc(0, &dm6446evm_mmc_config); 788 davinci_setup_mmc(0, &dm6446evm_mmc_config);
793 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg); 789 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
794 790
795 davinci_serial_init(&uart_config); 791 davinci_serial_init(dm644x_serial_device);
796 dm644x_init_asp(&dm644x_evm_snd_data); 792 dm644x_init_asp(&dm644x_evm_snd_data);
797 793
798 /* irlml6401 switches over 1A, in under 8 msec */ 794 /* irlml6401 switches over 1A, in under 8 msec */
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 0c005e876cac..2bc3651d56cc 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -750,10 +750,6 @@ static void __init davinci_map_io(void)
750 cdce_clk_init(); 750 cdce_clk_init();
751} 751}
752 752
753static struct davinci_uart_config uart_config __initdata = {
754 .enabled_uarts = (1 << 0),
755};
756
757#define DM646X_EVM_PHY_ID "davinci_mdio-0:01" 753#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
758/* 754/*
759 * The following EDMA channels/slots are not being used by drivers (for 755 * The following EDMA channels/slots are not being used by drivers (for
@@ -793,7 +789,7 @@ static __init void evm_init(void)
793 struct davinci_soc_info *soc_info = &davinci_soc_info; 789 struct davinci_soc_info *soc_info = &davinci_soc_info;
794 790
795 evm_init_i2c(); 791 evm_init_i2c();
796 davinci_serial_init(&uart_config); 792 davinci_serial_init(dm646x_serial_device);
797 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]); 793 dm646x_init_mcasp0(&dm646x_evm_snd_data[0]);
798 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]); 794 dm646x_init_mcasp1(&dm646x_evm_snd_data[1]);
799 795
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 9549d53aa63f..cd0f58730c2b 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -434,10 +434,6 @@ static void __init mityomapl138_setup_nand(void)
434 ARRAY_SIZE(mityomapl138_devices)); 434 ARRAY_SIZE(mityomapl138_devices));
435} 435}
436 436
437static struct davinci_uart_config mityomapl138_uart_config __initdata = {
438 .enabled_uarts = 0x7,
439};
440
441static const short mityomap_mii_pins[] = { 437static const short mityomap_mii_pins[] = {
442 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, 438 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
443 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, 439 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
@@ -517,7 +513,7 @@ static void __init mityomapl138_init(void)
517 if (ret) 513 if (ret)
518 pr_warning("watchdog registration failed: %d\n", ret); 514 pr_warning("watchdog registration failed: %d\n", ret);
519 515
520 davinci_serial_init(&mityomapl138_uart_config); 516 davinci_serial_init(da8xx_serial_device);
521 517
522 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); 518 ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata);
523 if (ret) 519 if (ret)
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 808233b60e3d..46f336fca803 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -154,10 +154,6 @@ static struct platform_device *davinci_ntosd2_devices[] __initdata = {
154 &ntosd2_leds_dev, 154 &ntosd2_leds_dev,
155}; 155};
156 156
157static struct davinci_uart_config uart_config __initdata = {
158 .enabled_uarts = (1 << 0),
159};
160
161static void __init davinci_ntosd2_map_io(void) 157static void __init davinci_ntosd2_map_io(void)
162{ 158{
163 dm644x_init(); 159 dm644x_init();
@@ -198,7 +194,7 @@ static __init void davinci_ntosd2_init(void)
198 platform_add_devices(davinci_ntosd2_devices, 194 platform_add_devices(davinci_ntosd2_devices,
199 ARRAY_SIZE(davinci_ntosd2_devices)); 195 ARRAY_SIZE(davinci_ntosd2_devices));
200 196
201 davinci_serial_init(&uart_config); 197 davinci_serial_init(dm644x_serial_device);
202 dm644x_init_asp(&dm644x_ntosd2_snd_data); 198 dm644x_init_asp(&dm644x_ntosd2_snd_data);
203 199
204 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID; 200 soc_info->emac_pdata->phy_id = NEUROS_OSD2_PHY_ID;
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index b8c20de10ca2..ab98c75cabb4 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -286,15 +286,11 @@ usb11_setup_oc_fail:
286 gpio_free(DA850_USB1_VBUS_PIN); 286 gpio_free(DA850_USB1_VBUS_PIN);
287} 287}
288 288
289static struct davinci_uart_config omapl138_hawk_uart_config __initdata = {
290 .enabled_uarts = 0x7,
291};
292
293static __init void omapl138_hawk_init(void) 289static __init void omapl138_hawk_init(void)
294{ 290{
295 int ret; 291 int ret;
296 292
297 davinci_serial_init(&omapl138_hawk_uart_config); 293 davinci_serial_init(da8xx_serial_device);
298 294
299 omapl138_hawk_config_emac(); 295 omapl138_hawk_config_emac();
300 296
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 513eee14f77d..d84360148100 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -125,10 +125,6 @@ static struct platform_device *davinci_sffsdr_devices[] __initdata = {
125 &davinci_sffsdr_nandflash_device, 125 &davinci_sffsdr_nandflash_device,
126}; 126};
127 127
128static struct davinci_uart_config uart_config __initdata = {
129 .enabled_uarts = (1 << 0),
130};
131
132static void __init davinci_sffsdr_map_io(void) 128static void __init davinci_sffsdr_map_io(void)
133{ 129{
134 dm644x_init(); 130 dm644x_init();
@@ -141,7 +137,7 @@ static __init void davinci_sffsdr_init(void)
141 platform_add_devices(davinci_sffsdr_devices, 137 platform_add_devices(davinci_sffsdr_devices,
142 ARRAY_SIZE(davinci_sffsdr_devices)); 138 ARRAY_SIZE(davinci_sffsdr_devices));
143 sffsdr_init_i2c(); 139 sffsdr_init_i2c();
144 davinci_serial_init(&uart_config); 140 davinci_serial_init(dm644x_serial_device);
145 soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID; 141 soc_info->emac_pdata->phy_id = SFFSDR_PHY_ID;
146 davinci_setup_usb(0, 0); /* We support only peripheral mode. */ 142 davinci_setup_usb(0, 0); /* We support only peripheral mode. */
147 143
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index abbaf0270be6..d6c746e35ad9 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -395,9 +395,9 @@ static struct clk_lookup da830_clks[] = {
395 CLK(NULL, "tptc0", &tptc0_clk), 395 CLK(NULL, "tptc0", &tptc0_clk),
396 CLK(NULL, "tptc1", &tptc1_clk), 396 CLK(NULL, "tptc1", &tptc1_clk),
397 CLK("da830-mmc.0", NULL, &mmcsd_clk), 397 CLK("da830-mmc.0", NULL, &mmcsd_clk),
398 CLK(NULL, "uart0", &uart0_clk), 398 CLK("serial8250.0", NULL, &uart0_clk),
399 CLK(NULL, "uart1", &uart1_clk), 399 CLK("serial8250.1", NULL, &uart1_clk),
400 CLK(NULL, "uart2", &uart2_clk), 400 CLK("serial8250.2", NULL, &uart2_clk),
401 CLK("spi_davinci.0", NULL, &spi0_clk), 401 CLK("spi_davinci.0", NULL, &spi0_clk),
402 CLK("spi_davinci.1", NULL, &spi1_clk), 402 CLK("spi_davinci.1", NULL, &spi1_clk),
403 CLK(NULL, "ecap0", &ecap0_clk), 403 CLK(NULL, "ecap0", &ecap0_clk),
@@ -417,6 +417,7 @@ static struct clk_lookup da830_clks[] = {
417 CLK(NULL, "aintc", &aintc_clk), 417 CLK(NULL, "aintc", &aintc_clk),
418 CLK(NULL, "secu_mgr", &secu_mgr_clk), 418 CLK(NULL, "secu_mgr", &secu_mgr_clk),
419 CLK("davinci_emac.1", NULL, &emac_clk), 419 CLK("davinci_emac.1", NULL, &emac_clk),
420 CLK("davinci_mdio.0", "fck", &emac_clk),
420 CLK(NULL, "gpio", &gpio_clk), 421 CLK(NULL, "gpio", &gpio_clk),
421 CLK("i2c_davinci.2", NULL, &i2c1_clk), 422 CLK("i2c_davinci.2", NULL, &i2c1_clk),
422 CLK(NULL, "usb11", &usb11_clk), 423 CLK(NULL, "usb11", &usb11_clk),
@@ -1199,7 +1200,6 @@ static struct davinci_soc_info davinci_soc_info_da830 = {
1199 .gpio_base = DA8XX_GPIO_BASE, 1200 .gpio_base = DA8XX_GPIO_BASE,
1200 .gpio_num = 128, 1201 .gpio_num = 128,
1201 .gpio_irq = IRQ_DA8XX_GPIO0, 1202 .gpio_irq = IRQ_DA8XX_GPIO0,
1202 .serial_dev = &da8xx_serial_device,
1203 .emac_pdata = &da8xx_emac_pdata, 1203 .emac_pdata = &da8xx_emac_pdata,
1204}; 1204};
1205 1205
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index a0d4f6038b60..f56e5fbfa2fd 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -451,9 +451,9 @@ static struct clk_lookup da850_clks[] = {
451 CLK(NULL, "tpcc1", &tpcc1_clk), 451 CLK(NULL, "tpcc1", &tpcc1_clk),
452 CLK(NULL, "tptc2", &tptc2_clk), 452 CLK(NULL, "tptc2", &tptc2_clk),
453 CLK("pruss_uio", "pruss", &pruss_clk), 453 CLK("pruss_uio", "pruss", &pruss_clk),
454 CLK(NULL, "uart0", &uart0_clk), 454 CLK("serial8250.0", NULL, &uart0_clk),
455 CLK(NULL, "uart1", &uart1_clk), 455 CLK("serial8250.1", NULL, &uart1_clk),
456 CLK(NULL, "uart2", &uart2_clk), 456 CLK("serial8250.2", NULL, &uart2_clk),
457 CLK(NULL, "aintc", &aintc_clk), 457 CLK(NULL, "aintc", &aintc_clk),
458 CLK(NULL, "gpio", &gpio_clk), 458 CLK(NULL, "gpio", &gpio_clk),
459 CLK("i2c_davinci.2", NULL, &i2c1_clk), 459 CLK("i2c_davinci.2", NULL, &i2c1_clk),
@@ -461,6 +461,7 @@ static struct clk_lookup da850_clks[] = {
461 CLK(NULL, "arm", &arm_clk), 461 CLK(NULL, "arm", &arm_clk),
462 CLK(NULL, "rmii", &rmii_clk), 462 CLK(NULL, "rmii", &rmii_clk),
463 CLK("davinci_emac.1", NULL, &emac_clk), 463 CLK("davinci_emac.1", NULL, &emac_clk),
464 CLK("davinci_mdio.0", "fck", &emac_clk),
464 CLK("davinci-mcasp.0", NULL, &mcasp_clk), 465 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
465 CLK("da8xx_lcdc.0", "fck", &lcdc_clk), 466 CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
466 CLK("da830-mmc.0", NULL, &mmcsd0_clk), 467 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
@@ -1301,7 +1302,6 @@ static struct davinci_soc_info davinci_soc_info_da850 = {
1301 .gpio_base = DA8XX_GPIO_BASE, 1302 .gpio_base = DA8XX_GPIO_BASE,
1302 .gpio_num = 144, 1303 .gpio_num = 144,
1303 .gpio_irq = IRQ_DA8XX_GPIO0, 1304 .gpio_irq = IRQ_DA8XX_GPIO0,
1304 .serial_dev = &da8xx_serial_device,
1305 .emac_pdata = &da8xx_emac_pdata, 1305 .emac_pdata = &da8xx_emac_pdata,
1306 .sram_dma = DA8XX_SHARED_RAM_BASE, 1306 .sram_dma = DA8XX_SHARED_RAM_BASE,
1307 .sram_len = SZ_128K, 1307 .sram_len = SZ_128K,
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 961aea8bbad5..d2bc574ae172 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -20,13 +20,6 @@
20 20
21#define DA8XX_NUM_UARTS 3 21#define DA8XX_NUM_UARTS 3
22 22
23static void __init da8xx_uart_clk_enable(void)
24{
25 int i;
26 for (i = 0; i < DA8XX_NUM_UARTS; i++)
27 davinci_serial_setup_clk(i, NULL);
28}
29
30static struct of_device_id da8xx_irq_match[] __initdata = { 23static struct of_device_id da8xx_irq_match[] __initdata = {
31 { .compatible = "ti,cp-intc", .data = cp_intc_of_init, }, 24 { .compatible = "ti,cp-intc", .data = cp_intc_of_init, },
32 { } 25 { }
@@ -47,6 +40,12 @@ static struct of_dev_auxdata da850_auxdata_lookup[] __initdata = {
47 OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL), 40 OF_DEV_AUXDATA("ti,da850-ecap", 0x01f07000, "ecap", NULL),
48 OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL), 41 OF_DEV_AUXDATA("ti,da850-ecap", 0x01f08000, "ecap", NULL),
49 OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL), 42 OF_DEV_AUXDATA("ti,da830-spi", 0x01f0e000, "spi_davinci.1", NULL),
43 OF_DEV_AUXDATA("ns16550a", 0x01c42000, "serial8250.0", NULL),
44 OF_DEV_AUXDATA("ns16550a", 0x01d0c000, "serial8250.1", NULL),
45 OF_DEV_AUXDATA("ns16550a", 0x01d0d000, "serial8250.2", NULL),
46 OF_DEV_AUXDATA("ti,davinci_mdio", 0x01e24000, "davinci_mdio.0", NULL),
47 OF_DEV_AUXDATA("ti,davinci-dm6467-emac", 0x01e20000, "davinci_emac.1",
48 NULL),
50 {} 49 {}
51}; 50};
52 51
@@ -57,7 +56,6 @@ static void __init da850_init_machine(void)
57 of_platform_populate(NULL, of_default_bus_match_table, 56 of_platform_populate(NULL, of_default_bus_match_table,
58 da850_auxdata_lookup, NULL); 57 da850_auxdata_lookup, NULL);
59 58
60 da8xx_uart_clk_enable();
61} 59}
62 60
63static const char *da850_boards_compat[] __initdata = { 61static const char *da850_boards_compat[] __initdata = {
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index a883043d0820..2ab5d577186f 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -106,4 +106,9 @@ int dm646x_init_edma(struct edma_rsv_info *rsv);
106void dm646x_video_init(void); 106void dm646x_video_init(void);
107void dm646x_setup_vpif(struct vpif_display_config *, 107void dm646x_setup_vpif(struct vpif_display_config *,
108 struct vpif_capture_config *); 108 struct vpif_capture_config *);
109
110extern struct platform_device dm365_serial_device[];
111extern struct platform_device dm355_serial_device[];
112extern struct platform_device dm644x_serial_device[];
113extern struct platform_device dm646x_serial_device[];
109#endif /*__DAVINCI_H */ 114#endif /*__DAVINCI_H */
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index 71a46a348761..2e473fefd71e 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -68,7 +68,7 @@
68void __iomem *da8xx_syscfg0_base; 68void __iomem *da8xx_syscfg0_base;
69void __iomem *da8xx_syscfg1_base; 69void __iomem *da8xx_syscfg1_base;
70 70
71static struct plat_serial8250_port da8xx_serial_pdata[] = { 71static struct plat_serial8250_port da8xx_serial0_pdata[] = {
72 { 72 {
73 .mapbase = DA8XX_UART0_BASE, 73 .mapbase = DA8XX_UART0_BASE,
74 .irq = IRQ_DA8XX_UARTINT0, 74 .irq = IRQ_DA8XX_UARTINT0,
@@ -78,6 +78,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
78 .regshift = 2, 78 .regshift = 2,
79 }, 79 },
80 { 80 {
81 .flags = 0,
82 }
83};
84static struct plat_serial8250_port da8xx_serial1_pdata[] = {
85 {
81 .mapbase = DA8XX_UART1_BASE, 86 .mapbase = DA8XX_UART1_BASE,
82 .irq = IRQ_DA8XX_UARTINT1, 87 .irq = IRQ_DA8XX_UARTINT1,
83 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 88 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -86,6 +91,11 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
86 .regshift = 2, 91 .regshift = 2,
87 }, 92 },
88 { 93 {
94 .flags = 0,
95 }
96};
97static struct plat_serial8250_port da8xx_serial2_pdata[] = {
98 {
89 .mapbase = DA8XX_UART2_BASE, 99 .mapbase = DA8XX_UART2_BASE,
90 .irq = IRQ_DA8XX_UARTINT2, 100 .irq = IRQ_DA8XX_UARTINT2,
91 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 101 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -95,15 +105,33 @@ static struct plat_serial8250_port da8xx_serial_pdata[] = {
95 }, 105 },
96 { 106 {
97 .flags = 0, 107 .flags = 0,
98 }, 108 }
99}; 109};
100 110
101struct platform_device da8xx_serial_device = { 111struct platform_device da8xx_serial_device[] = {
102 .name = "serial8250", 112 {
103 .id = PLAT8250_DEV_PLATFORM, 113 .name = "serial8250",
104 .dev = { 114 .id = PLAT8250_DEV_PLATFORM,
105 .platform_data = da8xx_serial_pdata, 115 .dev = {
116 .platform_data = da8xx_serial0_pdata,
117 }
118 },
119 {
120 .name = "serial8250",
121 .id = PLAT8250_DEV_PLATFORM1,
122 .dev = {
123 .platform_data = da8xx_serial1_pdata,
124 }
125 },
126 {
127 .name = "serial8250",
128 .id = PLAT8250_DEV_PLATFORM2,
129 .dev = {
130 .platform_data = da8xx_serial2_pdata,
131 }
106 }, 132 },
133 {
134 }
107}; 135};
108 136
109static s8 da8xx_queue_tc_mapping[][2] = { 137static s8 da8xx_queue_tc_mapping[][2] = {
@@ -453,12 +481,8 @@ int __init da8xx_register_emac(void)
453 ret = platform_device_register(&da8xx_mdio_device); 481 ret = platform_device_register(&da8xx_mdio_device);
454 if (ret < 0) 482 if (ret < 0)
455 return ret; 483 return ret;
456 ret = platform_device_register(&da8xx_emac_device); 484
457 if (ret < 0) 485 return platform_device_register(&da8xx_emac_device);
458 return ret;
459 ret = clk_add_alias(NULL, dev_name(&da8xx_mdio_device.dev),
460 NULL, &da8xx_emac_device.dev);
461 return ret;
462} 486}
463 487
464static struct resource da830_mcasp1_resources[] = { 488static struct resource da830_mcasp1_resources[] = {
@@ -828,14 +852,7 @@ static struct platform_device da8xx_rtc_device = {
828 852
829int da8xx_register_rtc(void) 853int da8xx_register_rtc(void)
830{ 854{
831 int ret; 855 return platform_device_register(&da8xx_rtc_device);
832
833 ret = platform_device_register(&da8xx_rtc_device);
834 if (!ret)
835 /* Atleast on DA850, RTC is a wakeup source */
836 device_init_wakeup(&da8xx_rtc_device.dev, true);
837
838 return ret;
839} 856}
840 857
841static void __iomem *da8xx_ddr2_ctlr_base; 858static void __iomem *da8xx_ddr2_ctlr_base;
diff --git a/arch/arm/mach-davinci/devices-tnetv107x.c b/arch/arm/mach-davinci/devices-tnetv107x.c
index 128cb9ae80f4..01d8686e553c 100644
--- a/arch/arm/mach-davinci/devices-tnetv107x.c
+++ b/arch/arm/mach-davinci/devices-tnetv107x.c
@@ -126,7 +126,7 @@ static struct platform_device edma_device = {
126 .dev.platform_data = tnetv107x_edma_info, 126 .dev.platform_data = tnetv107x_edma_info,
127}; 127};
128 128
129static struct plat_serial8250_port serial_data[] = { 129static struct plat_serial8250_port serial0_platform_data[] = {
130 { 130 {
131 .mapbase = TNETV107X_UART0_BASE, 131 .mapbase = TNETV107X_UART0_BASE,
132 .irq = IRQ_TNETV107X_UART0, 132 .irq = IRQ_TNETV107X_UART0,
@@ -137,6 +137,11 @@ static struct plat_serial8250_port serial_data[] = {
137 .regshift = 2, 137 .regshift = 2,
138 }, 138 },
139 { 139 {
140 .flags = 0,
141 }
142};
143static struct plat_serial8250_port serial1_platform_data[] = {
144 {
140 .mapbase = TNETV107X_UART1_BASE, 145 .mapbase = TNETV107X_UART1_BASE,
141 .irq = IRQ_TNETV107X_UART1, 146 .irq = IRQ_TNETV107X_UART1,
142 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 147 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -146,6 +151,11 @@ static struct plat_serial8250_port serial_data[] = {
146 .regshift = 2, 151 .regshift = 2,
147 }, 152 },
148 { 153 {
154 .flags = 0,
155 }
156};
157static struct plat_serial8250_port serial2_platform_data[] = {
158 {
149 .mapbase = TNETV107X_UART2_BASE, 159 .mapbase = TNETV107X_UART2_BASE,
150 .irq = IRQ_TNETV107X_UART2, 160 .irq = IRQ_TNETV107X_UART2,
151 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 161 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -156,13 +166,28 @@ static struct plat_serial8250_port serial_data[] = {
156 }, 166 },
157 { 167 {
158 .flags = 0, 168 .flags = 0,
159 }, 169 }
160}; 170};
161 171
162struct platform_device tnetv107x_serial_device = { 172
163 .name = "serial8250", 173struct platform_device tnetv107x_serial_device[] = {
164 .id = PLAT8250_DEV_PLATFORM, 174 {
165 .dev.platform_data = serial_data, 175 .name = "serial8250",
176 .id = PLAT8250_DEV_PLATFORM,
177 .dev.platform_data = serial0_platform_data,
178 },
179 {
180 .name = "serial8250",
181 .id = PLAT8250_DEV_PLATFORM1,
182 .dev.platform_data = serial1_platform_data,
183 },
184 {
185 .name = "serial8250",
186 .id = PLAT8250_DEV_PLATFORM2,
187 .dev.platform_data = serial2_platform_data,
188 },
189 {
190 }
166}; 191};
167 192
168static struct resource mmc0_resources[] = { 193static struct resource mmc0_resources[] = {
@@ -385,7 +410,7 @@ void __init tnetv107x_devices_init(struct tnetv107x_device_info *info)
385 platform_device_register(&tsc_device); 410 platform_device_register(&tsc_device);
386 411
387 if (info->serial_config) 412 if (info->serial_config)
388 davinci_serial_init(info->serial_config); 413 davinci_serial_init(tnetv107x_serial_device);
389 414
390 for (i = 0; i < 2; i++) 415 for (i = 0; i < 2; i++)
391 if (info->mmc_config[i]) { 416 if (info->mmc_config[i]) {
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 86100d179694..3eaa5f6b2160 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -357,9 +357,9 @@ static struct clk_lookup dm355_clks[] = {
357 CLK(NULL, "clkout3", &clkout3_clk), 357 CLK(NULL, "clkout3", &clkout3_clk),
358 CLK(NULL, "arm", &arm_clk), 358 CLK(NULL, "arm", &arm_clk),
359 CLK(NULL, "mjcp", &mjcp_clk), 359 CLK(NULL, "mjcp", &mjcp_clk),
360 CLK(NULL, "uart0", &uart0_clk), 360 CLK("serial8250.0", NULL, &uart0_clk),
361 CLK(NULL, "uart1", &uart1_clk), 361 CLK("serial8250.1", NULL, &uart1_clk),
362 CLK(NULL, "uart2", &uart2_clk), 362 CLK("serial8250.2", NULL, &uart2_clk),
363 CLK("i2c_davinci.1", NULL, &i2c_clk), 363 CLK("i2c_davinci.1", NULL, &i2c_clk),
364 CLK("davinci-mcbsp.0", NULL, &asp0_clk), 364 CLK("davinci-mcbsp.0", NULL, &asp0_clk),
365 CLK("davinci-mcbsp.1", NULL, &asp1_clk), 365 CLK("davinci-mcbsp.1", NULL, &asp1_clk),
@@ -922,7 +922,7 @@ static struct davinci_timer_info dm355_timer_info = {
922 .clocksource_id = T0_TOP, 922 .clocksource_id = T0_TOP,
923}; 923};
924 924
925static struct plat_serial8250_port dm355_serial_platform_data[] = { 925static struct plat_serial8250_port dm355_serial0_platform_data[] = {
926 { 926 {
927 .mapbase = DAVINCI_UART0_BASE, 927 .mapbase = DAVINCI_UART0_BASE,
928 .irq = IRQ_UARTINT0, 928 .irq = IRQ_UARTINT0,
@@ -932,6 +932,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
932 .regshift = 2, 932 .regshift = 2,
933 }, 933 },
934 { 934 {
935 .flags = 0,
936 }
937};
938static struct plat_serial8250_port dm355_serial1_platform_data[] = {
939 {
935 .mapbase = DAVINCI_UART1_BASE, 940 .mapbase = DAVINCI_UART1_BASE,
936 .irq = IRQ_UARTINT1, 941 .irq = IRQ_UARTINT1,
937 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 942 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -940,6 +945,11 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
940 .regshift = 2, 945 .regshift = 2,
941 }, 946 },
942 { 947 {
948 .flags = 0,
949 }
950};
951static struct plat_serial8250_port dm355_serial2_platform_data[] = {
952 {
943 .mapbase = DM355_UART2_BASE, 953 .mapbase = DM355_UART2_BASE,
944 .irq = IRQ_DM355_UARTINT2, 954 .irq = IRQ_DM355_UARTINT2,
945 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 955 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -948,16 +958,34 @@ static struct plat_serial8250_port dm355_serial_platform_data[] = {
948 .regshift = 2, 958 .regshift = 2,
949 }, 959 },
950 { 960 {
951 .flags = 0 961 .flags = 0,
952 }, 962 }
953}; 963};
954 964
955static struct platform_device dm355_serial_device = { 965struct platform_device dm355_serial_device[] = {
956 .name = "serial8250", 966 {
957 .id = PLAT8250_DEV_PLATFORM, 967 .name = "serial8250",
958 .dev = { 968 .id = PLAT8250_DEV_PLATFORM,
959 .platform_data = dm355_serial_platform_data, 969 .dev = {
970 .platform_data = dm355_serial0_platform_data,
971 }
972 },
973 {
974 .name = "serial8250",
975 .id = PLAT8250_DEV_PLATFORM1,
976 .dev = {
977 .platform_data = dm355_serial1_platform_data,
978 }
960 }, 979 },
980 {
981 .name = "serial8250",
982 .id = PLAT8250_DEV_PLATFORM2,
983 .dev = {
984 .platform_data = dm355_serial2_platform_data,
985 }
986 },
987 {
988 }
961}; 989};
962 990
963static struct davinci_soc_info davinci_soc_info_dm355 = { 991static struct davinci_soc_info davinci_soc_info_dm355 = {
@@ -981,7 +1009,6 @@ static struct davinci_soc_info davinci_soc_info_dm355 = {
981 .gpio_base = DAVINCI_GPIO_BASE, 1009 .gpio_base = DAVINCI_GPIO_BASE,
982 .gpio_num = 104, 1010 .gpio_num = 104,
983 .gpio_irq = IRQ_DM355_GPIOBNK0, 1011 .gpio_irq = IRQ_DM355_GPIOBNK0,
984 .serial_dev = &dm355_serial_device,
985 .sram_dma = 0x00010000, 1012 .sram_dma = 0x00010000,
986 .sram_len = SZ_32K, 1013 .sram_len = SZ_32K,
987}; 1014};
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index dad28029ba9b..c29e324eb0bb 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -455,8 +455,8 @@ static struct clk_lookup dm365_clks[] = {
455 CLK("vpss", "master", &vpss_master_clk), 455 CLK("vpss", "master", &vpss_master_clk),
456 CLK("vpss", "slave", &vpss_slave_clk), 456 CLK("vpss", "slave", &vpss_slave_clk),
457 CLK(NULL, "arm", &arm_clk), 457 CLK(NULL, "arm", &arm_clk),
458 CLK(NULL, "uart0", &uart0_clk), 458 CLK("serial8250.0", NULL, &uart0_clk),
459 CLK(NULL, "uart1", &uart1_clk), 459 CLK("serial8250.1", NULL, &uart1_clk),
460 CLK("i2c_davinci.1", NULL, &i2c_clk), 460 CLK("i2c_davinci.1", NULL, &i2c_clk),
461 CLK("da830-mmc.0", NULL, &mmcsd0_clk), 461 CLK("da830-mmc.0", NULL, &mmcsd0_clk),
462 CLK("da830-mmc.1", NULL, &mmcsd1_clk), 462 CLK("da830-mmc.1", NULL, &mmcsd1_clk),
@@ -477,6 +477,7 @@ static struct clk_lookup dm365_clks[] = {
477 CLK(NULL, "timer3", &timer3_clk), 477 CLK(NULL, "timer3", &timer3_clk),
478 CLK(NULL, "usb", &usb_clk), 478 CLK(NULL, "usb", &usb_clk),
479 CLK("davinci_emac.1", NULL, &emac_clk), 479 CLK("davinci_emac.1", NULL, &emac_clk),
480 CLK("davinci_mdio.0", "fck", &emac_clk),
480 CLK("davinci_voicecodec", NULL, &voicecodec_clk), 481 CLK("davinci_voicecodec", NULL, &voicecodec_clk),
481 CLK("davinci-mcbsp", NULL, &asp0_clk), 482 CLK("davinci-mcbsp", NULL, &asp0_clk),
482 CLK(NULL, "rto", &rto_clk), 483 CLK(NULL, "rto", &rto_clk),
@@ -1041,7 +1042,7 @@ static struct davinci_timer_info dm365_timer_info = {
1041 1042
1042#define DM365_UART1_BASE (IO_PHYS + 0x106000) 1043#define DM365_UART1_BASE (IO_PHYS + 0x106000)
1043 1044
1044static struct plat_serial8250_port dm365_serial_platform_data[] = { 1045static struct plat_serial8250_port dm365_serial0_platform_data[] = {
1045 { 1046 {
1046 .mapbase = DAVINCI_UART0_BASE, 1047 .mapbase = DAVINCI_UART0_BASE,
1047 .irq = IRQ_UARTINT0, 1048 .irq = IRQ_UARTINT0,
@@ -1051,6 +1052,11 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
1051 .regshift = 2, 1052 .regshift = 2,
1052 }, 1053 },
1053 { 1054 {
1055 .flags = 0,
1056 }
1057};
1058static struct plat_serial8250_port dm365_serial1_platform_data[] = {
1059 {
1054 .mapbase = DM365_UART1_BASE, 1060 .mapbase = DM365_UART1_BASE,
1055 .irq = IRQ_UARTINT1, 1061 .irq = IRQ_UARTINT1,
1056 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 1062 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -1059,16 +1065,27 @@ static struct plat_serial8250_port dm365_serial_platform_data[] = {
1059 .regshift = 2, 1065 .regshift = 2,
1060 }, 1066 },
1061 { 1067 {
1062 .flags = 0 1068 .flags = 0,
1063 }, 1069 }
1064}; 1070};
1065 1071
1066static struct platform_device dm365_serial_device = { 1072struct platform_device dm365_serial_device[] = {
1067 .name = "serial8250", 1073 {
1068 .id = PLAT8250_DEV_PLATFORM, 1074 .name = "serial8250",
1069 .dev = { 1075 .id = PLAT8250_DEV_PLATFORM,
1070 .platform_data = dm365_serial_platform_data, 1076 .dev = {
1077 .platform_data = dm365_serial0_platform_data,
1078 }
1079 },
1080 {
1081 .name = "serial8250",
1082 .id = PLAT8250_DEV_PLATFORM1,
1083 .dev = {
1084 .platform_data = dm365_serial1_platform_data,
1085 }
1071 }, 1086 },
1087 {
1088 }
1072}; 1089};
1073 1090
1074static struct davinci_soc_info davinci_soc_info_dm365 = { 1091static struct davinci_soc_info davinci_soc_info_dm365 = {
@@ -1093,7 +1110,6 @@ static struct davinci_soc_info davinci_soc_info_dm365 = {
1093 .gpio_num = 104, 1110 .gpio_num = 104,
1094 .gpio_irq = IRQ_DM365_GPIO0, 1111 .gpio_irq = IRQ_DM365_GPIO0,
1095 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */ 1112 .gpio_unbanked = 8, /* really 16 ... skip muxed GPIOs */
1096 .serial_dev = &dm365_serial_device,
1097 .emac_pdata = &dm365_emac_pdata, 1113 .emac_pdata = &dm365_emac_pdata,
1098 .sram_dma = 0x00010000, 1114 .sram_dma = 0x00010000,
1099 .sram_len = SZ_32K, 1115 .sram_len = SZ_32K,
@@ -1407,8 +1423,6 @@ static int __init dm365_init_devices(void)
1407 1423
1408 platform_device_register(&dm365_mdio_device); 1424 platform_device_register(&dm365_mdio_device);
1409 platform_device_register(&dm365_emac_device); 1425 platform_device_register(&dm365_emac_device);
1410 clk_add_alias(NULL, dev_name(&dm365_mdio_device.dev),
1411 NULL, &dm365_emac_device.dev);
1412 1426
1413 return 0; 1427 return 0;
1414} 1428}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index a49d18246fe9..4f74682293d6 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -303,10 +303,11 @@ static struct clk_lookup dm644x_clks[] = {
303 CLK("vpss", "master", &vpss_master_clk), 303 CLK("vpss", "master", &vpss_master_clk),
304 CLK("vpss", "slave", &vpss_slave_clk), 304 CLK("vpss", "slave", &vpss_slave_clk),
305 CLK(NULL, "arm", &arm_clk), 305 CLK(NULL, "arm", &arm_clk),
306 CLK(NULL, "uart0", &uart0_clk), 306 CLK("serial8250.0", NULL, &uart0_clk),
307 CLK(NULL, "uart1", &uart1_clk), 307 CLK("serial8250.1", NULL, &uart1_clk),
308 CLK(NULL, "uart2", &uart2_clk), 308 CLK("serial8250.2", NULL, &uart2_clk),
309 CLK("davinci_emac.1", NULL, &emac_clk), 309 CLK("davinci_emac.1", NULL, &emac_clk),
310 CLK("davinci_mdio.0", "fck", &emac_clk),
310 CLK("i2c_davinci.1", NULL, &i2c_clk), 311 CLK("i2c_davinci.1", NULL, &i2c_clk),
311 CLK("palm_bk3710", NULL, &ide_clk), 312 CLK("palm_bk3710", NULL, &ide_clk),
312 CLK("davinci-mcbsp", NULL, &asp_clk), 313 CLK("davinci-mcbsp", NULL, &asp_clk),
@@ -813,7 +814,7 @@ static struct davinci_timer_info dm644x_timer_info = {
813 .clocksource_id = T0_TOP, 814 .clocksource_id = T0_TOP,
814}; 815};
815 816
816static struct plat_serial8250_port dm644x_serial_platform_data[] = { 817static struct plat_serial8250_port dm644x_serial0_platform_data[] = {
817 { 818 {
818 .mapbase = DAVINCI_UART0_BASE, 819 .mapbase = DAVINCI_UART0_BASE,
819 .irq = IRQ_UARTINT0, 820 .irq = IRQ_UARTINT0,
@@ -823,6 +824,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
823 .regshift = 2, 824 .regshift = 2,
824 }, 825 },
825 { 826 {
827 .flags = 0,
828 }
829};
830static struct plat_serial8250_port dm644x_serial1_platform_data[] = {
831 {
826 .mapbase = DAVINCI_UART1_BASE, 832 .mapbase = DAVINCI_UART1_BASE,
827 .irq = IRQ_UARTINT1, 833 .irq = IRQ_UARTINT1,
828 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 834 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -831,6 +837,11 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
831 .regshift = 2, 837 .regshift = 2,
832 }, 838 },
833 { 839 {
840 .flags = 0,
841 }
842};
843static struct plat_serial8250_port dm644x_serial2_platform_data[] = {
844 {
834 .mapbase = DAVINCI_UART2_BASE, 845 .mapbase = DAVINCI_UART2_BASE,
835 .irq = IRQ_UARTINT2, 846 .irq = IRQ_UARTINT2,
836 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 847 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -839,16 +850,34 @@ static struct plat_serial8250_port dm644x_serial_platform_data[] = {
839 .regshift = 2, 850 .regshift = 2,
840 }, 851 },
841 { 852 {
842 .flags = 0 853 .flags = 0,
843 }, 854 }
844}; 855};
845 856
846static struct platform_device dm644x_serial_device = { 857struct platform_device dm644x_serial_device[] = {
847 .name = "serial8250", 858 {
848 .id = PLAT8250_DEV_PLATFORM, 859 .name = "serial8250",
849 .dev = { 860 .id = PLAT8250_DEV_PLATFORM,
850 .platform_data = dm644x_serial_platform_data, 861 .dev = {
862 .platform_data = dm644x_serial0_platform_data,
863 }
851 }, 864 },
865 {
866 .name = "serial8250",
867 .id = PLAT8250_DEV_PLATFORM1,
868 .dev = {
869 .platform_data = dm644x_serial1_platform_data,
870 }
871 },
872 {
873 .name = "serial8250",
874 .id = PLAT8250_DEV_PLATFORM2,
875 .dev = {
876 .platform_data = dm644x_serial2_platform_data,
877 }
878 },
879 {
880 }
852}; 881};
853 882
854static struct davinci_soc_info davinci_soc_info_dm644x = { 883static struct davinci_soc_info davinci_soc_info_dm644x = {
@@ -872,7 +901,6 @@ static struct davinci_soc_info davinci_soc_info_dm644x = {
872 .gpio_base = DAVINCI_GPIO_BASE, 901 .gpio_base = DAVINCI_GPIO_BASE,
873 .gpio_num = 71, 902 .gpio_num = 71,
874 .gpio_irq = IRQ_GPIOBNK0, 903 .gpio_irq = IRQ_GPIOBNK0,
875 .serial_dev = &dm644x_serial_device,
876 .emac_pdata = &dm644x_emac_pdata, 904 .emac_pdata = &dm644x_emac_pdata,
877 .sram_dma = 0x00008000, 905 .sram_dma = 0x00008000,
878 .sram_len = SZ_16K, 906 .sram_len = SZ_16K,
@@ -923,8 +951,6 @@ static int __init dm644x_init_devices(void)
923 951
924 platform_device_register(&dm644x_mdio_device); 952 platform_device_register(&dm644x_mdio_device);
925 platform_device_register(&dm644x_emac_device); 953 platform_device_register(&dm644x_emac_device);
926 clk_add_alias(NULL, dev_name(&dm644x_mdio_device.dev),
927 NULL, &dm644x_emac_device.dev);
928 954
929 return 0; 955 return 0;
930} 956}
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index d1259e80141b..68f8d1f1aca1 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -342,15 +342,16 @@ static struct clk_lookup dm646x_clks[] = {
342 CLK(NULL, "edma_tc1", &edma_tc1_clk), 342 CLK(NULL, "edma_tc1", &edma_tc1_clk),
343 CLK(NULL, "edma_tc2", &edma_tc2_clk), 343 CLK(NULL, "edma_tc2", &edma_tc2_clk),
344 CLK(NULL, "edma_tc3", &edma_tc3_clk), 344 CLK(NULL, "edma_tc3", &edma_tc3_clk),
345 CLK(NULL, "uart0", &uart0_clk), 345 CLK("serial8250.0", NULL, &uart0_clk),
346 CLK(NULL, "uart1", &uart1_clk), 346 CLK("serial8250.1", NULL, &uart1_clk),
347 CLK(NULL, "uart2", &uart2_clk), 347 CLK("serial8250.2", NULL, &uart2_clk),
348 CLK("i2c_davinci.1", NULL, &i2c_clk), 348 CLK("i2c_davinci.1", NULL, &i2c_clk),
349 CLK(NULL, "gpio", &gpio_clk), 349 CLK(NULL, "gpio", &gpio_clk),
350 CLK("davinci-mcasp.0", NULL, &mcasp0_clk), 350 CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
351 CLK("davinci-mcasp.1", NULL, &mcasp1_clk), 351 CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
352 CLK(NULL, "aemif", &aemif_clk), 352 CLK(NULL, "aemif", &aemif_clk),
353 CLK("davinci_emac.1", NULL, &emac_clk), 353 CLK("davinci_emac.1", NULL, &emac_clk),
354 CLK("davinci_mdio.0", "fck", &emac_clk),
354 CLK(NULL, "pwm0", &pwm0_clk), 355 CLK(NULL, "pwm0", &pwm0_clk),
355 CLK(NULL, "pwm1", &pwm1_clk), 356 CLK(NULL, "pwm1", &pwm1_clk),
356 CLK(NULL, "timer0", &timer0_clk), 357 CLK(NULL, "timer0", &timer0_clk),
@@ -790,7 +791,7 @@ static struct davinci_timer_info dm646x_timer_info = {
790 .clocksource_id = T0_TOP, 791 .clocksource_id = T0_TOP,
791}; 792};
792 793
793static struct plat_serial8250_port dm646x_serial_platform_data[] = { 794static struct plat_serial8250_port dm646x_serial0_platform_data[] = {
794 { 795 {
795 .mapbase = DAVINCI_UART0_BASE, 796 .mapbase = DAVINCI_UART0_BASE,
796 .irq = IRQ_UARTINT0, 797 .irq = IRQ_UARTINT0,
@@ -800,6 +801,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
800 .regshift = 2, 801 .regshift = 2,
801 }, 802 },
802 { 803 {
804 .flags = 0,
805 }
806};
807static struct plat_serial8250_port dm646x_serial1_platform_data[] = {
808 {
803 .mapbase = DAVINCI_UART1_BASE, 809 .mapbase = DAVINCI_UART1_BASE,
804 .irq = IRQ_UARTINT1, 810 .irq = IRQ_UARTINT1,
805 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 811 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -808,6 +814,11 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
808 .regshift = 2, 814 .regshift = 2,
809 }, 815 },
810 { 816 {
817 .flags = 0,
818 }
819};
820static struct plat_serial8250_port dm646x_serial2_platform_data[] = {
821 {
811 .mapbase = DAVINCI_UART2_BASE, 822 .mapbase = DAVINCI_UART2_BASE,
812 .irq = IRQ_DM646X_UARTINT2, 823 .irq = IRQ_DM646X_UARTINT2,
813 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 824 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
@@ -816,16 +827,34 @@ static struct plat_serial8250_port dm646x_serial_platform_data[] = {
816 .regshift = 2, 827 .regshift = 2,
817 }, 828 },
818 { 829 {
819 .flags = 0 830 .flags = 0,
820 }, 831 }
821}; 832};
822 833
823static struct platform_device dm646x_serial_device = { 834struct platform_device dm646x_serial_device[] = {
824 .name = "serial8250", 835 {
825 .id = PLAT8250_DEV_PLATFORM, 836 .name = "serial8250",
826 .dev = { 837 .id = PLAT8250_DEV_PLATFORM,
827 .platform_data = dm646x_serial_platform_data, 838 .dev = {
839 .platform_data = dm646x_serial0_platform_data,
840 }
841 },
842 {
843 .name = "serial8250",
844 .id = PLAT8250_DEV_PLATFORM1,
845 .dev = {
846 .platform_data = dm646x_serial1_platform_data,
847 }
828 }, 848 },
849 {
850 .name = "serial8250",
851 .id = PLAT8250_DEV_PLATFORM2,
852 .dev = {
853 .platform_data = dm646x_serial2_platform_data,
854 }
855 },
856 {
857 }
829}; 858};
830 859
831static struct davinci_soc_info davinci_soc_info_dm646x = { 860static struct davinci_soc_info davinci_soc_info_dm646x = {
@@ -849,7 +878,6 @@ static struct davinci_soc_info davinci_soc_info_dm646x = {
849 .gpio_base = DAVINCI_GPIO_BASE, 878 .gpio_base = DAVINCI_GPIO_BASE,
850 .gpio_num = 43, /* Only 33 usable */ 879 .gpio_num = 43, /* Only 33 usable */
851 .gpio_irq = IRQ_DM646X_GPIOBNK0, 880 .gpio_irq = IRQ_DM646X_GPIOBNK0,
852 .serial_dev = &dm646x_serial_device,
853 .emac_pdata = &dm646x_emac_pdata, 881 .emac_pdata = &dm646x_emac_pdata,
854 .sram_dma = 0x10010000, 882 .sram_dma = 0x10010000,
855 .sram_len = SZ_32K, 883 .sram_len = SZ_32K,
@@ -913,8 +941,6 @@ static int __init dm646x_init_devices(void)
913 941
914 platform_device_register(&dm646x_mdio_device); 942 platform_device_register(&dm646x_mdio_device);
915 platform_device_register(&dm646x_emac_device); 943 platform_device_register(&dm646x_emac_device);
916 clk_add_alias(NULL, dev_name(&dm646x_mdio_device.dev),
917 NULL, &dm646x_emac_device.dev);
918 944
919 return 0; 945 return 0;
920} 946}
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index cce316b92c06..0b3c169758ed 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -72,7 +72,6 @@ struct davinci_soc_info {
72 unsigned gpio_unbanked; 72 unsigned gpio_unbanked;
73 struct davinci_gpio_controller *gpio_ctlrs; 73 struct davinci_gpio_controller *gpio_ctlrs;
74 int gpio_ctlrs_num; 74 int gpio_ctlrs_num;
75 struct platform_device *serial_dev;
76 struct emac_platform_data *emac_pdata; 75 struct emac_platform_data *emac_pdata;
77 dma_addr_t sram_dma; 76 dma_addr_t sram_dma;
78 unsigned sram_len; 77 unsigned sram_len;
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 7b41a5e9bc31..aae53072c0eb 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -111,7 +111,7 @@ void da8xx_restart(enum reboot_mode mode, const char *cmd);
111void da8xx_rproc_reserve_cma(void); 111void da8xx_rproc_reserve_cma(void);
112int da8xx_register_rproc(void); 112int da8xx_register_rproc(void);
113 113
114extern struct platform_device da8xx_serial_device; 114extern struct platform_device da8xx_serial_device[];
115extern struct emac_platform_data da8xx_emac_pdata; 115extern struct emac_platform_data da8xx_emac_pdata;
116extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata; 116extern struct da8xx_lcdc_platform_data sharp_lcd035q3dg01_pdata;
117extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata; 117extern struct da8xx_lcdc_platform_data sharp_lk043t1dg01_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index 62ad300440f5..52b8571b2e70 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -15,6 +15,8 @@
15 15
16#include <mach/hardware.h> 16#include <mach/hardware.h>
17 17
18#include <linux/platform_device.h>
19
18#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 20#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
19#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 21#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
20#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800) 22#define DAVINCI_UART2_BASE (IO_PHYS + 0x20800)
@@ -37,13 +39,7 @@
37#define UART_DM646X_SCR_TX_WATERMARK 0x08 39#define UART_DM646X_SCR_TX_WATERMARK 0x08
38 40
39#ifndef __ASSEMBLY__ 41#ifndef __ASSEMBLY__
40struct davinci_uart_config { 42extern int davinci_serial_init(struct platform_device *);
41 /* Bit field of UARTs present; bit 0 --> UART0 */
42 unsigned int enabled_uarts;
43};
44
45extern int davinci_serial_init(struct davinci_uart_config *);
46extern int davinci_serial_setup_clk(unsigned instance, unsigned int *rate);
47#endif 43#endif
48 44
49#endif /* __ASM_ARCH_SERIAL_H */ 45#endif /* __ASM_ARCH_SERIAL_H */
diff --git a/arch/arm/mach-davinci/include/mach/tnetv107x.h b/arch/arm/mach-davinci/include/mach/tnetv107x.h
index 16314c64f755..494fcf5ccfe1 100644
--- a/arch/arm/mach-davinci/include/mach/tnetv107x.h
+++ b/arch/arm/mach-davinci/include/mach/tnetv107x.h
@@ -42,7 +42,6 @@
42#include <mach/serial.h> 42#include <mach/serial.h>
43 43
44struct tnetv107x_device_info { 44struct tnetv107x_device_info {
45 struct davinci_uart_config *serial_config;
46 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */ 45 struct davinci_mmc_config *mmc_config[2]; /* 2 controllers */
47 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */ 46 struct davinci_nand_pdata *nand_config[4]; /* 4 chipsels */
48 struct matrix_keypad_platform_data *keypad_config; 47 struct matrix_keypad_platform_data *keypad_config;
@@ -50,7 +49,7 @@ struct tnetv107x_device_info {
50}; 49};
51 50
52extern struct platform_device tnetv107x_wdt_device; 51extern struct platform_device tnetv107x_wdt_device;
53extern struct platform_device tnetv107x_serial_device; 52extern struct platform_device tnetv107x_serial_device[];
54 53
55extern void tnetv107x_init(void); 54extern void tnetv107x_init(void);
56extern void tnetv107x_devices_init(struct tnetv107x_device_info *); 55extern void tnetv107x_devices_init(struct tnetv107x_device_info *);
diff --git a/arch/arm/mach-davinci/serial.c b/arch/arm/mach-davinci/serial.c
index f2625814c3c9..5e93a734c858 100644
--- a/arch/arm/mach-davinci/serial.c
+++ b/arch/arm/mach-davinci/serial.c
@@ -70,49 +70,36 @@ static void __init davinci_serial_reset(struct plat_serial8250_port *p)
70 UART_DM646X_SCR_TX_WATERMARK); 70 UART_DM646X_SCR_TX_WATERMARK);
71} 71}
72 72
73/* Enable UART clock and obtain its rate */ 73int __init davinci_serial_init(struct platform_device *serial_dev)
74int __init davinci_serial_setup_clk(unsigned instance, unsigned int *rate)
75{ 74{
76 char name[16]; 75 int i, ret = 0;
76 struct device *dev;
77 struct plat_serial8250_port *p;
77 struct clk *clk; 78 struct clk *clk;
78 struct davinci_soc_info *soc_info = &davinci_soc_info;
79 struct device *dev = &soc_info->serial_dev->dev;
80
81 sprintf(name, "uart%d", instance);
82 clk = clk_get(dev, name);
83 if (IS_ERR(clk)) {
84 pr_err("%s:%d: failed to get UART%d clock\n",
85 __func__, __LINE__, instance);
86 return PTR_ERR(clk);
87 }
88
89 clk_prepare_enable(clk);
90
91 if (rate)
92 *rate = clk_get_rate(clk);
93
94 return 0;
95}
96
97int __init davinci_serial_init(struct davinci_uart_config *info)
98{
99 int i, ret;
100 struct davinci_soc_info *soc_info = &davinci_soc_info;
101 struct device *dev = &soc_info->serial_dev->dev;
102 struct plat_serial8250_port *p = dev->platform_data;
103 79
104 /* 80 /*
105 * Make sure the serial ports are muxed on at this point. 81 * Make sure the serial ports are muxed on at this point.
106 * You have to mux them off in device drivers later on if not needed. 82 * You have to mux them off in device drivers later on if not needed.
107 */ 83 */
108 for (i = 0; p->flags; i++, p++) { 84 for (i = 0; serial_dev[i].dev.platform_data != NULL; i++) {
109 if (!(info->enabled_uarts & (1 << i))) 85 dev = &serial_dev[i].dev;
110 continue; 86 p = dev->platform_data;
111 87
112 ret = davinci_serial_setup_clk(i, &p->uartclk); 88 ret = platform_device_register(&serial_dev[i]);
113 if (ret) 89 if (ret)
114 continue; 90 continue;
115 91
92 clk = clk_get(dev, NULL);
93 if (IS_ERR(clk)) {
94 pr_err("%s:%d: failed to get UART%d clock\n",
95 __func__, __LINE__, i);
96 continue;
97 }
98
99 clk_prepare_enable(clk);
100
101 p->uartclk = clk_get_rate(clk);
102
116 if (!p->membase && p->mapbase) { 103 if (!p->membase && p->mapbase) {
117 p->membase = ioremap(p->mapbase, SZ_4K); 104 p->membase = ioremap(p->mapbase, SZ_4K);
118 105
@@ -125,6 +112,5 @@ int __init davinci_serial_init(struct davinci_uart_config *info)
125 if (p->membase && p->type != PORT_AR7) 112 if (p->membase && p->type != PORT_AR7)
126 davinci_serial_reset(p); 113 davinci_serial_reset(p);
127 } 114 }
128 115 return ret;
129 return platform_device_register(soc_info->serial_dev);
130} 116}
diff --git a/arch/arm/mach-davinci/tnetv107x.c b/arch/arm/mach-davinci/tnetv107x.c
index 4545667ecd3c..f4d7fbb24b3b 100644
--- a/arch/arm/mach-davinci/tnetv107x.c
+++ b/arch/arm/mach-davinci/tnetv107x.c
@@ -264,7 +264,7 @@ static struct clk_lookup clks[] = {
264 CLK(NULL, "clk_chipcfg", &clk_chipcfg), 264 CLK(NULL, "clk_chipcfg", &clk_chipcfg),
265 CLK("tnetv107x-ts.0", NULL, &clk_tsc), 265 CLK("tnetv107x-ts.0", NULL, &clk_tsc),
266 CLK(NULL, "clk_rom", &clk_rom), 266 CLK(NULL, "clk_rom", &clk_rom),
267 CLK(NULL, "uart2", &clk_uart2), 267 CLK("serial8250.2", NULL, &clk_uart2),
268 CLK(NULL, "clk_pktsec", &clk_pktsec), 268 CLK(NULL, "clk_pktsec", &clk_pktsec),
269 CLK("tnetv107x-rng.0", NULL, &clk_rng), 269 CLK("tnetv107x-rng.0", NULL, &clk_rng),
270 CLK("tnetv107x-pka.0", NULL, &clk_pka), 270 CLK("tnetv107x-pka.0", NULL, &clk_pka),
@@ -274,8 +274,8 @@ static struct clk_lookup clks[] = {
274 CLK(NULL, "clk_gpio", &clk_gpio), 274 CLK(NULL, "clk_gpio", &clk_gpio),
275 CLK(NULL, "clk_mdio", &clk_mdio), 275 CLK(NULL, "clk_mdio", &clk_mdio),
276 CLK("dm6441-mmc.0", NULL, &clk_sdio0), 276 CLK("dm6441-mmc.0", NULL, &clk_sdio0),
277 CLK(NULL, "uart0", &clk_uart0), 277 CLK("serial8250.0", NULL, &clk_uart0),
278 CLK(NULL, "uart1", &clk_uart1), 278 CLK("serial8250.1", NULL, &clk_uart1),
279 CLK(NULL, "timer0", &clk_timer0), 279 CLK(NULL, "timer0", &clk_timer0),
280 CLK(NULL, "timer1", &clk_timer1), 280 CLK(NULL, "timer1", &clk_timer1),
281 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm), 281 CLK("tnetv107x_wdt.0", NULL, &clk_wdt_arm),
@@ -757,7 +757,7 @@ static struct davinci_soc_info tnetv107x_soc_info = {
757 .gpio_type = GPIO_TYPE_TNETV107X, 757 .gpio_type = GPIO_TYPE_TNETV107X,
758 .gpio_num = TNETV107X_N_GPIO, 758 .gpio_num = TNETV107X_N_GPIO,
759 .timer_info = &timer_info, 759 .timer_info = &timer_info,
760 .serial_dev = &tnetv107x_serial_device, 760 .serial_dev = tnetv107x_serial_device,
761}; 761};
762 762
763void __init tnetv107x_init(void) 763void __init tnetv107x_init(void)
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dff7b2fd4e20..0bc7cdf8cf46 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -23,6 +23,8 @@ config MACH_CM_A510
23config MACH_DOVE_DT 23config MACH_DOVE_DT
24 bool "Marvell Dove Flattened Device Tree" 24 bool "Marvell Dove Flattened Device Tree"
25 select DOVE_CLK 25 select DOVE_CLK
26 select ORION_IRQCHIP
27 select ORION_TIMER
26 select REGULATOR 28 select REGULATOR
27 select REGULATOR_FIXED_VOLTAGE 29 select REGULATOR_FIXED_VOLTAGE
28 select USE_OF 30 select USE_OF
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index 4d9d2ffc4535..cbc5c0618788 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,5 +1,5 @@
1obj-y += common.o irq.o 1obj-y += common.o
2obj-$(CONFIG_DOVE_LEGACY) += mpp.o 2obj-$(CONFIG_DOVE_LEGACY) += irq.o mpp.o
3obj-$(CONFIG_PCI) += pcie.o 3obj-$(CONFIG_PCI) += pcie.o
4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o 4obj-$(CONFIG_MACH_DOVE_DB) += dove-db-setup.o
5obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o 5obj-$(CONFIG_MACH_DOVE_DT) += board-dt.o
diff --git a/arch/arm/mach-dove/board-dt.c b/arch/arm/mach-dove/board-dt.c
index f3755ac81148..49f72a848423 100644
--- a/arch/arm/mach-dove/board-dt.c
+++ b/arch/arm/mach-dove/board-dt.c
@@ -10,11 +10,14 @@
10 10
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/clk-provider.h> 12#include <linux/clk-provider.h>
13#include <linux/clocksource.h>
14#include <linux/irqchip.h>
13#include <linux/of.h> 15#include <linux/of.h>
14#include <linux/of_platform.h> 16#include <linux/of_platform.h>
15#include <linux/platform_data/usb-ehci-orion.h> 17#include <linux/platform_data/usb-ehci-orion.h>
16#include <asm/hardware/cache-tauros2.h> 18#include <asm/hardware/cache-tauros2.h>
17#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
20#include <mach/dove.h>
18#include <mach/pm.h> 21#include <mach/pm.h>
19#include <plat/common.h> 22#include <plat/common.h>
20#include <plat/irq.h> 23#include <plat/irq.h>
@@ -33,10 +36,6 @@ static void __init dove_legacy_clk_init(void)
33 clkspec.np = np; 36 clkspec.np = np;
34 clkspec.args_count = 1; 37 clkspec.args_count = 1;
35 38
36 clkspec.args[0] = CLOCK_GATING_BIT_GBE;
37 orion_clkdev_add(NULL, "mv643xx_eth_port.0",
38 of_clk_get_from_provider(&clkspec));
39
40 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0; 39 clkspec.args[0] = CLOCK_GATING_BIT_PCIE0;
41 orion_clkdev_add("0", "pcie", 40 orion_clkdev_add("0", "pcie",
42 of_clk_get_from_provider(&clkspec)); 41 of_clk_get_from_provider(&clkspec));
@@ -46,15 +45,18 @@ static void __init dove_legacy_clk_init(void)
46 of_clk_get_from_provider(&clkspec)); 45 of_clk_get_from_provider(&clkspec));
47} 46}
48 47
49static void __init dove_of_clk_init(void) 48static void __init dove_dt_time_init(void)
50{ 49{
51 of_clk_init(NULL); 50 of_clk_init(NULL);
52 dove_legacy_clk_init(); 51 clocksource_of_init();
53} 52}
54 53
55static struct mv643xx_eth_platform_data dove_dt_ge00_data = { 54static void __init dove_dt_init_early(void)
56 .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT, 55{
57}; 56 mvebu_mbus_init("marvell,dove-mbus",
57 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
58 DOVE_MC_WINS_BASE, DOVE_MC_WINS_SZ);
59}
58 60
59static void __init dove_dt_init(void) 61static void __init dove_dt_init(void)
60{ 62{
@@ -65,11 +67,10 @@ static void __init dove_dt_init(void)
65#endif 67#endif
66 dove_setup_cpu_wins(); 68 dove_setup_cpu_wins();
67 69
68 /* Setup root of clk tree */ 70 /* Setup clocks for legacy devices */
69 dove_of_clk_init(); 71 dove_legacy_clk_init();
70 72
71 /* Internal devices not ported to DT yet */ 73 /* Internal devices not ported to DT yet */
72 dove_ge00_init(&dove_dt_ge00_data);
73 dove_pcie_init(1, 1); 74 dove_pcie_init(1, 1);
74 75
75 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 76 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
@@ -82,9 +83,8 @@ static const char * const dove_dt_board_compat[] = {
82 83
83DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)") 84DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
84 .map_io = dove_map_io, 85 .map_io = dove_map_io,
85 .init_early = dove_init_early, 86 .init_early = dove_dt_init_early,
86 .init_irq = orion_dt_init_irq, 87 .init_time = dove_dt_time_init,
87 .init_time = dove_timer_init,
88 .init_machine = dove_dt_init, 88 .init_machine = dove_dt_init,
89 .restart = dove_restart, 89 .restart = dove_restart,
90 .dt_compat = dove_dt_board_compat, 90 .dt_compat = dove_dt_board_compat,
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 304f069ebf50..c122bcff9f7c 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -27,6 +27,22 @@
27#include <plat/time.h> 27#include <plat/time.h>
28#include "common.h" 28#include "common.h"
29 29
30/* These can go away once Dove uses the mvebu-mbus DT binding */
31#define DOVE_MBUS_PCIE0_MEM_TARGET 0x4
32#define DOVE_MBUS_PCIE0_MEM_ATTR 0xe8
33#define DOVE_MBUS_PCIE0_IO_TARGET 0x4
34#define DOVE_MBUS_PCIE0_IO_ATTR 0xe0
35#define DOVE_MBUS_PCIE1_MEM_TARGET 0x8
36#define DOVE_MBUS_PCIE1_MEM_ATTR 0xe8
37#define DOVE_MBUS_PCIE1_IO_TARGET 0x8
38#define DOVE_MBUS_PCIE1_IO_ATTR 0xe0
39#define DOVE_MBUS_CESA_TARGET 0x3
40#define DOVE_MBUS_CESA_ATTR 0x1
41#define DOVE_MBUS_BOOTROM_TARGET 0x1
42#define DOVE_MBUS_BOOTROM_ATTR 0xfd
43#define DOVE_MBUS_SCRATCHPAD_TARGET 0xd
44#define DOVE_MBUS_SCRATCHPAD_ATTR 0x0
45
30/***************************************************************************** 46/*****************************************************************************
31 * I/O Address Mapping 47 * I/O Address Mapping
32 ****************************************************************************/ 48 ****************************************************************************/
@@ -332,34 +348,40 @@ void __init dove_setup_cpu_wins(void)
332{ 348{
333 /* 349 /*
334 * The PCIe windows will no longer be statically allocated 350 * The PCIe windows will no longer be statically allocated
335 * here once Dove is migrated to the pci-mvebu driver. 351 * here once Dove is migrated to the pci-mvebu driver. The
352 * non-PCIe windows will no longer be created here once Dove
353 * fully moves to DT.
336 */ 354 */
337 mvebu_mbus_add_window_remap_flags("pcie0.0", 355 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE0_IO_TARGET,
356 DOVE_MBUS_PCIE0_IO_ATTR,
338 DOVE_PCIE0_IO_PHYS_BASE, 357 DOVE_PCIE0_IO_PHYS_BASE,
339 DOVE_PCIE0_IO_SIZE, 358 DOVE_PCIE0_IO_SIZE,
340 DOVE_PCIE0_IO_BUS_BASE, 359 DOVE_PCIE0_IO_BUS_BASE);
341 MVEBU_MBUS_PCI_IO); 360 mvebu_mbus_add_window_remap_by_id(DOVE_MBUS_PCIE1_IO_TARGET,
342 mvebu_mbus_add_window_remap_flags("pcie1.0", 361 DOVE_MBUS_PCIE1_IO_ATTR,
343 DOVE_PCIE1_IO_PHYS_BASE, 362 DOVE_PCIE1_IO_PHYS_BASE,
344 DOVE_PCIE1_IO_SIZE, 363 DOVE_PCIE1_IO_SIZE,
345 DOVE_PCIE1_IO_BUS_BASE, 364 DOVE_PCIE1_IO_BUS_BASE);
346 MVEBU_MBUS_PCI_IO); 365 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE0_MEM_TARGET,
347 mvebu_mbus_add_window_remap_flags("pcie0.0", 366 DOVE_MBUS_PCIE0_MEM_ATTR,
348 DOVE_PCIE0_MEM_PHYS_BASE, 367 DOVE_PCIE0_MEM_PHYS_BASE,
349 DOVE_PCIE0_MEM_SIZE, 368 DOVE_PCIE0_MEM_SIZE);
350 MVEBU_MBUS_NO_REMAP, 369 mvebu_mbus_add_window_by_id(DOVE_MBUS_PCIE1_MEM_TARGET,
351 MVEBU_MBUS_PCI_MEM); 370 DOVE_MBUS_PCIE1_MEM_ATTR,
352 mvebu_mbus_add_window_remap_flags("pcie1.0", 371 DOVE_PCIE1_MEM_PHYS_BASE,
353 DOVE_PCIE1_MEM_PHYS_BASE, 372 DOVE_PCIE1_MEM_SIZE);
354 DOVE_PCIE1_MEM_SIZE, 373 mvebu_mbus_add_window_by_id(DOVE_MBUS_CESA_TARGET,
355 MVEBU_MBUS_NO_REMAP, 374 DOVE_MBUS_CESA_ATTR,
356 MVEBU_MBUS_PCI_MEM); 375 DOVE_CESA_PHYS_BASE,
357 mvebu_mbus_add_window("cesa", DOVE_CESA_PHYS_BASE, 376 DOVE_CESA_SIZE);
358 DOVE_CESA_SIZE); 377 mvebu_mbus_add_window_by_id(DOVE_MBUS_BOOTROM_TARGET,
359 mvebu_mbus_add_window("bootrom", DOVE_BOOTROM_PHYS_BASE, 378 DOVE_MBUS_BOOTROM_ATTR,
360 DOVE_BOOTROM_SIZE); 379 DOVE_BOOTROM_PHYS_BASE,
361 mvebu_mbus_add_window("scratchpad", DOVE_SCRATCHPAD_PHYS_BASE, 380 DOVE_BOOTROM_SIZE);
362 DOVE_SCRATCHPAD_SIZE); 381 mvebu_mbus_add_window_by_id(DOVE_MBUS_SCRATCHPAD_TARGET,
382 DOVE_MBUS_SCRATCHPAD_ATTR,
383 DOVE_SCRATCHPAD_PHYS_BASE,
384 DOVE_SCRATCHPAD_SIZE);
363} 385}
364 386
365void __init dove_init(void) 387void __init dove_init(void)
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 60bd729a1ba5..8a433a51289c 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -47,7 +47,7 @@ static const struct dove_mpp_grp dove_mpp_grp[] = {
47 47
48/* Enable gpio for a range of pins. mode should be a combination of 48/* Enable gpio for a range of pins. mode should be a combination of
49 GPIO_OUTPUT_OK | GPIO_INPUT_OK */ 49 GPIO_OUTPUT_OK | GPIO_INPUT_OK */
50static void dove_mpp_gpio_mode(int start, int end, int gpio_mode) 50static void __init dove_mpp_gpio_mode(int start, int end, int gpio_mode)
51{ 51{
52 int i; 52 int i;
53 53
diff --git a/arch/arm/mach-ep93xx/vision_ep9307.c b/arch/arm/mach-ep93xx/vision_ep9307.c
index 605956fd07a2..6bc1c181581d 100644
--- a/arch/arm/mach-ep93xx/vision_ep9307.c
+++ b/arch/arm/mach-ep93xx/vision_ep9307.c
@@ -23,7 +23,7 @@
23#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
24#include <linux/i2c.h> 24#include <linux/i2c.h>
25#include <linux/i2c-gpio.h> 25#include <linux/i2c-gpio.h>
26#include <linux/i2c/pca953x.h> 26#include <linux/platform_data/pca953x.h>
27#include <linux/spi/spi.h> 27#include <linux/spi/spi.h>
28#include <linux/spi/flash.h> 28#include <linux/spi/flash.h>
29#include <linux/spi/mmc_spi.h> 29#include <linux/spi/mmc_spi.h>
@@ -224,62 +224,15 @@ static struct ep93xx_spi_chip_ops vision_spi_flash_hw = {
224#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0) 224#define VISION_SPI_MMC_WP EP93XX_GPIO_LINE_F(0)
225#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15 225#define VISION_SPI_MMC_CD EP93XX_GPIO_LINE_EGPIO15
226 226
227static struct gpio vision_spi_mmc_gpios[] = {
228 { VISION_SPI_MMC_WP, GPIOF_DIR_IN, "mmc_spi:wp" },
229 { VISION_SPI_MMC_CD, GPIOF_DIR_IN, "mmc_spi:cd" },
230};
231
232static int vision_spi_mmc_init(struct device *pdev,
233 irqreturn_t (*func)(int, void *), void *pdata)
234{
235 int err;
236
237 err = gpio_request_array(vision_spi_mmc_gpios,
238 ARRAY_SIZE(vision_spi_mmc_gpios));
239 if (err)
240 return err;
241
242 err = gpio_set_debounce(VISION_SPI_MMC_CD, 1);
243 if (err)
244 goto exit_err;
245
246 err = request_irq(gpio_to_irq(VISION_SPI_MMC_CD), func,
247 IRQ_TYPE_EDGE_BOTH, "mmc_spi:cd", pdata);
248 if (err)
249 goto exit_err;
250
251 return 0;
252
253exit_err:
254 gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
255 return err;
256
257}
258
259static void vision_spi_mmc_exit(struct device *pdev, void *pdata)
260{
261 free_irq(gpio_to_irq(VISION_SPI_MMC_CD), pdata);
262 gpio_free_array(vision_spi_mmc_gpios, ARRAY_SIZE(vision_spi_mmc_gpios));
263}
264
265static int vision_spi_mmc_get_ro(struct device *pdev)
266{
267 return !!gpio_get_value(VISION_SPI_MMC_WP);
268}
269
270static int vision_spi_mmc_get_cd(struct device *pdev)
271{
272 return !gpio_get_value(VISION_SPI_MMC_CD);
273}
274
275static struct mmc_spi_platform_data vision_spi_mmc_data = { 227static struct mmc_spi_platform_data vision_spi_mmc_data = {
276 .init = vision_spi_mmc_init,
277 .exit = vision_spi_mmc_exit,
278 .get_ro = vision_spi_mmc_get_ro,
279 .get_cd = vision_spi_mmc_get_cd,
280 .detect_delay = 100, 228 .detect_delay = 100,
281 .powerup_msecs = 100, 229 .powerup_msecs = 100,
282 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34, 230 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
231 .flags = MMC_SPI_USE_CD_GPIO | MMC_SPI_USE_RO_GPIO,
232 .cd_gpio = VISION_SPI_MMC_CD,
233 .cd_debounce = 1,
234 .ro_gpio = VISION_SPI_MMC_WP,
235 .caps2 = MMC_CAP2_RO_ACTIVE_HIGH,
283}; 236};
284 237
285static int vision_spi_mmc_hw_setup(struct spi_device *spi) 238static int vision_spi_mmc_hw_setup(struct spi_device *spi)
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5952e68c76c4..56fe819ee10b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -36,6 +36,7 @@ config CPU_EXYNOS4210
36 bool "SAMSUNG EXYNOS4210" 36 bool "SAMSUNG EXYNOS4210"
37 default y 37 default y
38 depends on ARCH_EXYNOS4 38 depends on ARCH_EXYNOS4
39 select ARCH_HAS_BANDGAP
39 select ARM_CPU_SUSPEND if PM 40 select ARM_CPU_SUSPEND if PM
40 select PINCTRL_EXYNOS 41 select PINCTRL_EXYNOS
41 select PM_GENERIC_DOMAINS if PM 42 select PM_GENERIC_DOMAINS if PM
@@ -49,7 +50,9 @@ config SOC_EXYNOS4212
49 bool "SAMSUNG EXYNOS4212" 50 bool "SAMSUNG EXYNOS4212"
50 default y 51 default y
51 depends on ARCH_EXYNOS4 52 depends on ARCH_EXYNOS4
53 select ARCH_HAS_BANDGAP
52 select PINCTRL_EXYNOS 54 select PINCTRL_EXYNOS
55 select PM_GENERIC_DOMAINS if PM
53 select S5P_PM if PM 56 select S5P_PM if PM
54 select S5P_SLEEP if PM 57 select S5P_SLEEP if PM
55 select SAMSUNG_DMADEV 58 select SAMSUNG_DMADEV
@@ -60,7 +63,9 @@ config SOC_EXYNOS4412
60 bool "SAMSUNG EXYNOS4412" 63 bool "SAMSUNG EXYNOS4412"
61 default y 64 default y
62 depends on ARCH_EXYNOS4 65 depends on ARCH_EXYNOS4
66 select ARCH_HAS_BANDGAP
63 select PINCTRL_EXYNOS 67 select PINCTRL_EXYNOS
68 select PM_GENERIC_DOMAINS if PM
64 select SAMSUNG_DMADEV 69 select SAMSUNG_DMADEV
65 help 70 help
66 Enable EXYNOS4412 SoC support 71 Enable EXYNOS4412 SoC support
@@ -69,6 +74,7 @@ config SOC_EXYNOS5250
69 bool "SAMSUNG EXYNOS5250" 74 bool "SAMSUNG EXYNOS5250"
70 default y 75 default y
71 depends on ARCH_EXYNOS5 76 depends on ARCH_EXYNOS5
77 select ARCH_HAS_BANDGAP
72 select PINCTRL_EXYNOS 78 select PINCTRL_EXYNOS
73 select PM_GENERIC_DOMAINS if PM 79 select PM_GENERIC_DOMAINS if PM
74 select S5P_PM if PM 80 select S5P_PM if PM
@@ -93,6 +99,7 @@ config SOC_EXYNOS5440
93 default y 99 default y
94 depends on ARCH_EXYNOS5 100 depends on ARCH_EXYNOS5
95 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 101 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
102 select ARCH_HAS_BANDGAP
96 select ARCH_HAS_OPP 103 select ARCH_HAS_OPP
97 select HAVE_ARM_ARCH_TIMER 104 select HAVE_ARM_ARCH_TIMER
98 select AUTO_ZRELADDR 105 select AUTO_ZRELADDR
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index 972490fc09d6..8646a141ae46 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -17,7 +17,6 @@
17 17
18void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); 18void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1);
19void exynos_init_time(void); 19void exynos_init_time(void);
20extern unsigned long xxti_f, xusbxti_f;
21 20
22struct map_desc; 21struct map_desc;
23void exynos_init_io(void); 22void exynos_init_io(void);
@@ -25,56 +24,14 @@ void exynos4_restart(enum reboot_mode mode, const char *cmd);
25void exynos5_restart(enum reboot_mode mode, const char *cmd); 24void exynos5_restart(enum reboot_mode mode, const char *cmd);
26void exynos_init_late(void); 25void exynos_init_late(void);
27 26
28/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
29void exynos4_clk_init(struct device_node *np, int is_exynos4210, void __iomem *reg_base, unsigned long xom);
30void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
31
32void exynos_firmware_init(void); 27void exynos_firmware_init(void);
33 28
34void exynos_set_timer_source(u8 channels);
35
36#ifdef CONFIG_PM_GENERIC_DOMAINS 29#ifdef CONFIG_PM_GENERIC_DOMAINS
37int exynos_pm_late_initcall(void); 30int exynos_pm_late_initcall(void);
38#else 31#else
39static inline int exynos_pm_late_initcall(void) { return 0; } 32static inline int exynos_pm_late_initcall(void) { return 0; }
40#endif 33#endif
41 34
42#ifdef CONFIG_ARCH_EXYNOS4
43void exynos4_register_clocks(void);
44void exynos4_setup_clocks(void);
45
46#else
47#define exynos4_register_clocks()
48#define exynos4_setup_clocks()
49#endif
50
51#ifdef CONFIG_ARCH_EXYNOS5
52void exynos5_register_clocks(void);
53void exynos5_setup_clocks(void);
54
55#else
56#define exynos5_register_clocks()
57#define exynos5_setup_clocks()
58#endif
59
60#ifdef CONFIG_CPU_EXYNOS4210
61void exynos4210_register_clocks(void);
62
63#else
64#define exynos4210_register_clocks()
65#endif
66
67#ifdef CONFIG_SOC_EXYNOS4212
68void exynos4212_register_clocks(void);
69
70#else
71#define exynos4212_register_clocks()
72#endif
73
74struct device_node;
75void combiner_init(void __iomem *combiner_base, struct device_node *np,
76 unsigned int max_nr, int irq_base);
77
78extern struct smp_operations exynos_smp_ops; 35extern struct smp_operations exynos_smp_ops;
79 36
80extern void exynos_cpu_die(unsigned int cpu); 37extern void exynos_cpu_die(unsigned int cpu);
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 225ee8431c72..ac139226d63c 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
200 if (soc_is_exynos5250()) 200 if (soc_is_exynos5250())
201 exynos5_core_down_clk(); 201 exynos5_core_down_clk();
202 202
203 if (soc_is_exynos5440())
204 exynos4_idle_driver.state_count = 1;
205
203 ret = cpuidle_register_driver(&exynos4_idle_driver); 206 ret = cpuidle_register_driver(&exynos4_idle_driver);
204 if (ret) { 207 if (ret) {
205 printk(KERN_ERR "CPUidle failed to register driver\n"); 208 printk(KERN_ERR "CPUidle failed to register driver\n");
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index cd9fcb1cd7ab..8e8437dea3ce 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,9 +1,14 @@
1config ARCH_HIGHBANK 1config ARCH_HIGHBANK
2 bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7 2 bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
3 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
3 select ARCH_HAS_CPUFREQ 4 select ARCH_HAS_CPUFREQ
5 select ARCH_HAS_HOLES_MEMORYMODEL
4 select ARCH_HAS_OPP 6 select ARCH_HAS_OPP
5 select ARCH_WANT_OPTIONAL_GPIOLIB 7 select ARCH_WANT_OPTIONAL_GPIOLIB
6 select ARM_AMBA 8 select ARM_AMBA
9 select ARM_ERRATA_764369
10 select ARM_ERRATA_775420
11 select ARM_ERRATA_798181
7 select ARM_GIC 12 select ARM_GIC
8 select ARM_TIMER_SP804 13 select ARM_TIMER_SP804
9 select CACHE_L2X0 14 select CACHE_L2X0
@@ -12,9 +17,10 @@ config ARCH_HIGHBANK
12 select CPU_V7 17 select CPU_V7
13 select GENERIC_CLOCKEVENTS 18 select GENERIC_CLOCKEVENTS
14 select HAVE_ARM_SCU 19 select HAVE_ARM_SCU
15 select HAVE_ARM_TWD if LOCAL_TIMERS 20 select HAVE_ARM_TWD if SMP
16 select HAVE_SMP 21 select HAVE_SMP
17 select MAILBOX 22 select MAILBOX
18 select PL320_MBOX 23 select PL320_MBOX
19 select SPARSE_IRQ 24 select SPARSE_IRQ
20 select USE_OF 25 select USE_OF
26 select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 88815795fe26..8e63ccdb0de3 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -18,14 +18,11 @@
18#include <linux/clocksource.h> 18#include <linux/clocksource.h>
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/irqchip.h> 21#include <linux/irqchip.h>
23#include <linux/irqdomain.h>
24#include <linux/of.h> 22#include <linux/of.h>
25#include <linux/of_irq.h> 23#include <linux/of_irq.h>
26#include <linux/of_platform.h> 24#include <linux/of_platform.h>
27#include <linux/of_address.h> 25#include <linux/of_address.h>
28#include <linux/smp.h>
29#include <linux/amba/bus.h> 26#include <linux/amba/bus.h>
30#include <linux/clk-provider.h> 27#include <linux/clk-provider.h>
31 28
@@ -35,7 +32,6 @@
35#include <asm/hardware/cache-l2x0.h> 32#include <asm/hardware/cache-l2x0.h>
36#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
37#include <asm/mach/map.h> 34#include <asm/mach/map.h>
38#include <asm/mach/time.h>
39 35
40#include "core.h" 36#include "core.h"
41#include "sysregs.h" 37#include "sysregs.h"
@@ -65,13 +61,11 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
65 HB_JUMP_TABLE_PHYS(cpu) + 15); 61 HB_JUMP_TABLE_PHYS(cpu) + 15);
66} 62}
67 63
68#ifdef CONFIG_CACHE_L2X0
69static void highbank_l2x0_disable(void) 64static void highbank_l2x0_disable(void)
70{ 65{
71 /* Disable PL310 L2 Cache controller */ 66 /* Disable PL310 L2 Cache controller */
72 highbank_smc1(0x102, 0x0); 67 highbank_smc1(0x102, 0x0);
73} 68}
74#endif
75 69
76static void __init highbank_init_irq(void) 70static void __init highbank_init_irq(void)
77{ 71{
@@ -80,12 +74,13 @@ static void __init highbank_init_irq(void)
80 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 74 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
81 highbank_scu_map_io(); 75 highbank_scu_map_io();
82 76
83#ifdef CONFIG_CACHE_L2X0
84 /* Enable PL310 L2 Cache controller */ 77 /* Enable PL310 L2 Cache controller */
85 highbank_smc1(0x102, 0x1); 78 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
86 l2x0_of_init(0, ~0UL); 79 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
87 outer_cache.disable = highbank_l2x0_disable; 80 highbank_smc1(0x102, 0x1);
88#endif 81 l2x0_of_init(0, ~0UL);
82 outer_cache.disable = highbank_l2x0_disable;
83 }
89} 84}
90 85
91static void __init highbank_timer_init(void) 86static void __init highbank_timer_init(void)
@@ -176,6 +171,9 @@ static const char *highbank_match[] __initconst = {
176}; 171};
177 172
178DT_MACHINE_START(HIGHBANK, "Highbank") 173DT_MACHINE_START(HIGHBANK, "Highbank")
174#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
175 .dma_zone_size = (4ULL * SZ_1G),
176#endif
179 .smp = smp_ops(highbank_smp_ops), 177 .smp = smp_ops(highbank_smp_ops),
180 .init_irq = highbank_init_irq, 178 .init_irq = highbank_init_irq,
181 .init_time = highbank_timer_init, 179 .init_time = highbank_timer_init,
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index f54656091a9d..29a8af6922a8 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,6 +1,7 @@
1config ARCH_MXC 1config ARCH_MXC
2 bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7 2 bool "Freescale i.MX family" if ARCH_MULTI_V4_V5 || ARCH_MULTI_V6_V7
3 select ARCH_REQUIRE_GPIOLIB 3 select ARCH_REQUIRE_GPIOLIB
4 select ARM_CPU_SUSPEND if PM
4 select ARM_PATCH_PHYS_VIRT 5 select ARM_PATCH_PHYS_VIRT
5 select AUTO_ZRELADDR if !ZBOOT_ROM 6 select AUTO_ZRELADDR if !ZBOOT_ROM
6 select CLKDEV_LOOKUP 7 select CLKDEV_LOOKUP
@@ -8,6 +9,7 @@ config ARCH_MXC
8 select GENERIC_ALLOCATOR 9 select GENERIC_ALLOCATOR
9 select GENERIC_CLOCKEVENTS 10 select GENERIC_CLOCKEVENTS
10 select GENERIC_IRQ_CHIP 11 select GENERIC_IRQ_CHIP
12 select MIGHT_HAVE_CACHE_L2X0 if ARCH_MULTI_V6_V7
11 select MULTI_IRQ_HANDLER 13 select MULTI_IRQ_HANDLER
12 select SPARSE_IRQ 14 select SPARSE_IRQ
13 select USE_OF 15 select USE_OF
@@ -785,7 +787,6 @@ config SOC_IMX6Q
785 bool "i.MX6 Quad/DualLite support" 787 bool "i.MX6 Quad/DualLite support"
786 select ARCH_HAS_CPUFREQ 788 select ARCH_HAS_CPUFREQ
787 select ARCH_HAS_OPP 789 select ARCH_HAS_OPP
788 select ARM_CPU_SUSPEND if PM
789 select ARM_ERRATA_754322 790 select ARM_ERRATA_754322
790 select ARM_ERRATA_764369 if SMP 791 select ARM_ERRATA_764369 if SMP
791 select ARM_ERRATA_775420 792 select ARM_ERRATA_775420
@@ -793,7 +794,7 @@ config SOC_IMX6Q
793 select COMMON_CLK 794 select COMMON_CLK
794 select CPU_V7 795 select CPU_V7
795 select HAVE_ARM_SCU if SMP 796 select HAVE_ARM_SCU if SMP
796 select HAVE_ARM_TWD if LOCAL_TIMERS 797 select HAVE_ARM_TWD if SMP
797 select HAVE_IMX_ANATOP 798 select HAVE_IMX_ANATOP
798 select HAVE_IMX_GPC 799 select HAVE_IMX_GPC
799 select HAVE_IMX_MMDC 800 select HAVE_IMX_MMDC
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index e20f22d58fd8..5383c589ad71 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -15,7 +15,8 @@ imx5-pm-$(CONFIG_PM) += pm-imx5.o
15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) 15obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
16 16
17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \ 17obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
18 clk-pfd.o clk-busy.o clk.o 18 clk-pfd.o clk-busy.o clk.o \
19 clk-fixup-div.o clk-fixup-mux.o
19 20
20obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 21obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
21obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 22obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 0cfa07dd9aa4..ad3b755abb78 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -66,7 +66,7 @@ void imx_anatop_post_resume(void)
66 imx_anatop_enable_weak2p5(false); 66 imx_anatop_enable_weak2p5(false);
67} 67}
68 68
69void imx_anatop_usb_chrg_detect_disable(void) 69static void imx_anatop_usb_chrg_detect_disable(void)
70{ 70{
71 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT, 71 regmap_write(anatop, ANADIG_USB1_CHRG_DETECT,
72 BM_ANADIG_USB_CHRG_DETECT_EN_B 72 BM_ANADIG_USB_CHRG_DETECT_EN_B
@@ -100,4 +100,6 @@ void __init imx_anatop_init(void)
100 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__); 100 pr_err("%s: failed to find imx6q-anatop regmap!\n", __func__);
101 return; 101 return;
102 } 102 }
103
104 imx_anatop_usb_chrg_detect_disable();
103} 105}
diff --git a/arch/arm/mach-imx/clk-fixup-div.c b/arch/arm/mach-imx/clk-fixup-div.c
new file mode 100644
index 000000000000..21db020b1f2d
--- /dev/null
+++ b/arch/arm/mach-imx/clk-fixup-div.c
@@ -0,0 +1,129 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include "clk.h"
17
18#define to_clk_div(_hw) container_of(_hw, struct clk_divider, hw)
19#define div_mask(d) ((1 << (d->width)) - 1)
20
21/**
22 * struct clk_fixup_div - imx integer fixup divider clock
23 * @divider: the parent class
24 * @ops: pointer to clk_ops of parent class
25 * @fixup: a hook to fixup the write value
26 *
27 * The imx fixup divider clock is a subclass of basic clk_divider
28 * with an addtional fixup hook.
29 */
30struct clk_fixup_div {
31 struct clk_divider divider;
32 const struct clk_ops *ops;
33 void (*fixup)(u32 *val);
34};
35
36static inline struct clk_fixup_div *to_clk_fixup_div(struct clk_hw *hw)
37{
38 struct clk_divider *divider = to_clk_div(hw);
39
40 return container_of(divider, struct clk_fixup_div, divider);
41}
42
43static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
44 unsigned long parent_rate)
45{
46 struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
47
48 return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
49}
50
51static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
52 unsigned long *prate)
53{
54 struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
55
56 return fixup_div->ops->round_rate(&fixup_div->divider.hw, rate, prate);
57}
58
59static int clk_fixup_div_set_rate(struct clk_hw *hw, unsigned long rate,
60 unsigned long parent_rate)
61{
62 struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
63 struct clk_divider *div = to_clk_div(hw);
64 unsigned int divider, value;
65 unsigned long flags = 0;
66 u32 val;
67
68 divider = parent_rate / rate;
69
70 /* Zero based divider */
71 value = divider - 1;
72
73 if (value > div_mask(div))
74 value = div_mask(div);
75
76 spin_lock_irqsave(div->lock, flags);
77
78 val = readl(div->reg);
79 val &= ~(div_mask(div) << div->shift);
80 val |= value << div->shift;
81 fixup_div->fixup(&val);
82 writel(val, div->reg);
83
84 spin_unlock_irqrestore(div->lock, flags);
85
86 return 0;
87}
88
89static const struct clk_ops clk_fixup_div_ops = {
90 .recalc_rate = clk_fixup_div_recalc_rate,
91 .round_rate = clk_fixup_div_round_rate,
92 .set_rate = clk_fixup_div_set_rate,
93};
94
95struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
96 void __iomem *reg, u8 shift, u8 width,
97 void (*fixup)(u32 *val))
98{
99 struct clk_fixup_div *fixup_div;
100 struct clk *clk;
101 struct clk_init_data init;
102
103 if (!fixup)
104 return ERR_PTR(-EINVAL);
105
106 fixup_div = kzalloc(sizeof(*fixup_div), GFP_KERNEL);
107 if (!fixup_div)
108 return ERR_PTR(-ENOMEM);
109
110 init.name = name;
111 init.ops = &clk_fixup_div_ops;
112 init.flags = CLK_SET_RATE_PARENT;
113 init.parent_names = parent ? &parent : NULL;
114 init.num_parents = parent ? 1 : 0;
115
116 fixup_div->divider.reg = reg;
117 fixup_div->divider.shift = shift;
118 fixup_div->divider.width = width;
119 fixup_div->divider.lock = &imx_ccm_lock;
120 fixup_div->divider.hw.init = &init;
121 fixup_div->ops = &clk_divider_ops;
122 fixup_div->fixup = fixup;
123
124 clk = clk_register(NULL, &fixup_div->divider.hw);
125 if (IS_ERR(clk))
126 kfree(fixup_div);
127
128 return clk;
129}
diff --git a/arch/arm/mach-imx/clk-fixup-mux.c b/arch/arm/mach-imx/clk-fixup-mux.c
new file mode 100644
index 000000000000..deb4b8093b30
--- /dev/null
+++ b/arch/arm/mach-imx/clk-fixup-mux.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright (C) 2013 Freescale Semiconductor, Inc.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <linux/clk-provider.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include "clk.h"
17
18#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
19
20/**
21 * struct clk_fixup_mux - imx integer fixup multiplexer clock
22 * @mux: the parent class
23 * @ops: pointer to clk_ops of parent class
24 * @fixup: a hook to fixup the write value
25 *
26 * The imx fixup multiplexer clock is a subclass of basic clk_mux
27 * with an addtional fixup hook.
28 */
29struct clk_fixup_mux {
30 struct clk_mux mux;
31 const struct clk_ops *ops;
32 void (*fixup)(u32 *val);
33};
34
35static inline struct clk_fixup_mux *to_clk_fixup_mux(struct clk_hw *hw)
36{
37 struct clk_mux *mux = to_clk_mux(hw);
38
39 return container_of(mux, struct clk_fixup_mux, mux);
40}
41
42static u8 clk_fixup_mux_get_parent(struct clk_hw *hw)
43{
44 struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
45
46 return fixup_mux->ops->get_parent(&fixup_mux->mux.hw);
47}
48
49static int clk_fixup_mux_set_parent(struct clk_hw *hw, u8 index)
50{
51 struct clk_fixup_mux *fixup_mux = to_clk_fixup_mux(hw);
52 struct clk_mux *mux = to_clk_mux(hw);
53 unsigned long flags = 0;
54 u32 val;
55
56 spin_lock_irqsave(mux->lock, flags);
57
58 val = readl(mux->reg);
59 val &= ~(mux->mask << mux->shift);
60 val |= index << mux->shift;
61 fixup_mux->fixup(&val);
62 writel(val, mux->reg);
63
64 spin_unlock_irqrestore(mux->lock, flags);
65
66 return 0;
67}
68
69static const struct clk_ops clk_fixup_mux_ops = {
70 .get_parent = clk_fixup_mux_get_parent,
71 .set_parent = clk_fixup_mux_set_parent,
72};
73
74struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
75 u8 shift, u8 width, const char **parents,
76 int num_parents, void (*fixup)(u32 *val))
77{
78 struct clk_fixup_mux *fixup_mux;
79 struct clk *clk;
80 struct clk_init_data init;
81
82 if (!fixup)
83 return ERR_PTR(-EINVAL);
84
85 fixup_mux = kzalloc(sizeof(*fixup_mux), GFP_KERNEL);
86 if (!fixup_mux)
87 return ERR_PTR(-ENOMEM);
88
89 init.name = name;
90 init.ops = &clk_fixup_mux_ops;
91 init.parent_names = parents;
92 init.num_parents = num_parents;
93
94 fixup_mux->mux.reg = reg;
95 fixup_mux->mux.shift = shift;
96 fixup_mux->mux.mask = BIT(width) - 1;
97 fixup_mux->mux.lock = &imx_ccm_lock;
98 fixup_mux->mux.hw.init = &init;
99 fixup_mux->ops = &clk_mux_ops;
100 fixup_mux->fixup = fixup;
101
102 clk = clk_register(NULL, &fixup_mux->mux.hw);
103 if (IS_ERR(clk))
104 kfree(fixup_mux);
105
106 return clk;
107}
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 9afac26fa1cc..1a56a3319997 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -119,7 +119,7 @@ enum imx5_clks {
119 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel, 119 srtc_gate, pata_gate, sata_gate, spdif_xtal_sel, spdif0_sel,
120 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf, 120 spdif1_sel, spdif0_pred, spdif0_podf, spdif1_pred, spdif1_podf,
121 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate, 121 spdif0_com_s, spdif1_com_sel, spdif0_gate, spdif1_gate, spdif_ipg_gate,
122 clk_max 122 ocram, clk_max
123}; 123};
124 124
125static struct clk *clk[clk_max]; 125static struct clk *clk[clk_max];
@@ -506,6 +506,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
506 mx53_can_sel, ARRAY_SIZE(mx53_can_sel)); 506 mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
507 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22); 507 clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
508 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20); 508 clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
509 clk[ocram] = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
509 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8); 510 clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
510 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6); 511 clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
511 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22); 512 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 86567d980b07..9181a241d3a8 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -206,6 +206,17 @@ static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m",
206static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", 206static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
207 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", 207 "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
208 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; 208 "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", };
209static const char *cko2_sels[] = {
210 "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
211 "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
212 "usdhc3", "dummy", "arm", "ipu1",
213 "ipu2", "vdo_axi", "osc", "gpu2d_core",
214 "gpu3d_core", "usdhc2", "ssi1", "ssi2",
215 "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
216 "ldb_di0", "ldb_di1", "esai", "eim_slow",
217 "uart_serial", "spdif", "asrc", "hsi_tx",
218};
219static const char *cko_sels[] = { "cko1", "cko2", };
209 220
210enum mx6q_clks { 221enum mx6q_clks {
211 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, 222 dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m,
@@ -239,7 +250,8 @@ enum mx6q_clks {
239 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg, 250 pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
240 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, 251 ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
241 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, 252 sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate,
242 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, clk_max 253 usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow,
254 spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max
243}; 255};
244 256
245static struct clk *clk[clk_max]; 257static struct clk *clk[clk_max];
@@ -276,6 +288,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
276 struct device_node *np; 288 struct device_node *np;
277 void __iomem *base; 289 void __iomem *base;
278 int i, irq; 290 int i, irq;
291 int ret;
279 292
280 clk[dummy] = imx_clk_fixed("dummy", 0); 293 clk[dummy] = imx_clk_fixed("dummy", 0);
281 clk[ckil] = imx_obtain_fixed_clock("ckil", 0); 294 clk[ckil] = imx_obtain_fixed_clock("ckil", 0);
@@ -384,19 +397,21 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
384 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels)); 397 clk[ipu2_di1_sel] = imx_clk_mux("ipu2_di1_sel", base + 0x38, 9, 3, ipu2_di1_sels, ARRAY_SIZE(ipu2_di1_sels));
385 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels)); 398 clk[hsi_tx_sel] = imx_clk_mux("hsi_tx_sel", base + 0x30, 28, 1, hsi_tx_sels, ARRAY_SIZE(hsi_tx_sels));
386 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels)); 399 clk[pcie_axi_sel] = imx_clk_mux("pcie_axi_sel", base + 0x18, 10, 1, pcie_axi_sels, ARRAY_SIZE(pcie_axi_sels));
387 clk[ssi1_sel] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 400 clk[ssi1_sel] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
388 clk[ssi2_sel] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 401 clk[ssi2_sel] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
389 clk[ssi3_sel] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 402 clk[ssi3_sel] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
390 clk[usdhc1_sel] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 403 clk[usdhc1_sel] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
391 clk[usdhc2_sel] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 404 clk[usdhc2_sel] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
392 clk[usdhc3_sel] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 405 clk[usdhc3_sel] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
393 clk[usdhc4_sel] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 406 clk[usdhc4_sel] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
394 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels)); 407 clk[enfc_sel] = imx_clk_mux("enfc_sel", base + 0x2c, 16, 2, enfc_sels, ARRAY_SIZE(enfc_sels));
395 clk[emi_sel] = imx_clk_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels)); 408 clk[emi_sel] = imx_clk_fixup_mux("emi_sel", base + 0x1c, 27, 2, emi_sels, ARRAY_SIZE(emi_sels), imx_cscmr1_fixup);
396 clk[emi_slow_sel] = imx_clk_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels)); 409 clk[emi_slow_sel] = imx_clk_fixup_mux("emi_slow_sel", base + 0x1c, 29, 2, emi_slow_sels, ARRAY_SIZE(emi_slow_sels), imx_cscmr1_fixup);
397 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels)); 410 clk[vdo_axi_sel] = imx_clk_mux("vdo_axi_sel", base + 0x18, 11, 1, vdo_axi_sels, ARRAY_SIZE(vdo_axi_sels));
398 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels)); 411 clk[vpu_axi_sel] = imx_clk_mux("vpu_axi_sel", base + 0x18, 14, 2, vpu_axi_sels, ARRAY_SIZE(vpu_axi_sels));
399 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels)); 412 clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
413 clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
414 clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
400 415
401 /* name reg shift width busy: reg, shift parent_names num_parents */ 416 /* name reg shift width busy: reg, shift parent_names num_parents */
402 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels)); 417 clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
@@ -406,7 +421,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
406 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3); 421 clk[periph_clk2] = imx_clk_divider("periph_clk2", "periph_clk2_sel", base + 0x14, 27, 3);
407 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3); 422 clk[periph2_clk2] = imx_clk_divider("periph2_clk2", "periph2_clk2_sel", base + 0x14, 0, 3);
408 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2); 423 clk[ipg] = imx_clk_divider("ipg", "ahb", base + 0x14, 8, 2);
409 clk[ipg_per] = imx_clk_divider("ipg_per", "ipg", base + 0x1c, 0, 6); 424 clk[ipg_per] = imx_clk_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
410 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3); 425 clk[esai_pred] = imx_clk_divider("esai_pred", "esai_sel", base + 0x28, 9, 3);
411 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3); 426 clk[esai_podf] = imx_clk_divider("esai_podf", "esai_pred", base + 0x28, 25, 3);
412 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3); 427 clk[asrc_pred] = imx_clk_divider("asrc_pred", "asrc_sel", base + 0x30, 12, 3);
@@ -442,10 +457,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
442 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3); 457 clk[usdhc4_podf] = imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3);
443 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3); 458 clk[enfc_pred] = imx_clk_divider("enfc_pred", "enfc_sel", base + 0x2c, 18, 3);
444 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6); 459 clk[enfc_podf] = imx_clk_divider("enfc_podf", "enfc_pred", base + 0x2c, 21, 6);
445 clk[emi_podf] = imx_clk_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3); 460 clk[emi_podf] = imx_clk_fixup_divider("emi_podf", "emi_sel", base + 0x1c, 20, 3, imx_cscmr1_fixup);
446 clk[emi_slow_podf] = imx_clk_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3); 461 clk[emi_slow_podf] = imx_clk_fixup_divider("emi_slow_podf", "emi_slow_sel", base + 0x1c, 23, 3, imx_cscmr1_fixup);
447 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3); 462 clk[vpu_axi_podf] = imx_clk_divider("vpu_axi_podf", "vpu_axi_sel", base + 0x24, 25, 3);
448 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3); 463 clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", base + 0x60, 4, 3);
464 clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", base + 0x60, 21, 3);
449 465
450 /* name parent_name reg shift width busy: reg, shift */ 466 /* name parent_name reg shift width busy: reg, shift */
451 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0); 467 clk[axi] = imx_clk_busy_divider("axi", "axi_sel", base + 0x14, 16, 3, base + 0x48, 0);
@@ -486,6 +502,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
486 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10); 502 clk[i2c3] = imx_clk_gate2("i2c3", "ipg_per", base + 0x70, 10);
487 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12); 503 clk[iim] = imx_clk_gate2("iim", "ipg", base + 0x70, 12);
488 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14); 504 clk[enfc] = imx_clk_gate2("enfc", "enfc_podf", base + 0x70, 14);
505 clk[vdoa] = imx_clk_gate2("vdoa", "vdo_axi", base + 0x70, 26);
489 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0); 506 clk[ipu1] = imx_clk_gate2("ipu1", "ipu1_podf", base + 0x74, 0);
490 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2); 507 clk[ipu1_di0] = imx_clk_gate2("ipu1_di0", "ipu1_di0_sel", base + 0x74, 2);
491 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4); 508 clk[ipu1_di1] = imx_clk_gate2("ipu1_di1", "ipu1_di1_sel", base + 0x74, 4);
@@ -521,6 +538,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
521 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4); 538 clk[sata] = imx_clk_gate2("sata", "ipg", base + 0x7c, 4);
522 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6); 539 clk[sdma] = imx_clk_gate2("sdma", "ahb", base + 0x7c, 6);
523 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12); 540 clk[spba] = imx_clk_gate2("spba", "ipg", base + 0x7c, 12);
541 clk[spdif] = imx_clk_gate2("spdif", "spdif_podf", base + 0x7c, 14);
524 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18); 542 clk[ssi1_ipg] = imx_clk_gate2("ssi1_ipg", "ipg", base + 0x7c, 18);
525 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20); 543 clk[ssi2_ipg] = imx_clk_gate2("ssi2_ipg", "ipg", base + 0x7c, 20);
526 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22); 544 clk[ssi3_ipg] = imx_clk_gate2("ssi3_ipg", "ipg", base + 0x7c, 22);
@@ -535,6 +553,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
535 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12); 553 clk[vdo_axi] = imx_clk_gate2("vdo_axi", "vdo_axi_sel", base + 0x80, 12);
536 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14); 554 clk[vpu_axi] = imx_clk_gate2("vpu_axi", "vpu_axi_podf", base + 0x80, 14);
537 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7); 555 clk[cko1] = imx_clk_gate("cko1", "cko1_podf", base + 0x60, 7);
556 clk[cko2] = imx_clk_gate("cko2", "cko2_podf", base + 0x60, 24);
538 557
539 for (i = 0; i < ARRAY_SIZE(clk); i++) 558 for (i = 0; i < ARRAY_SIZE(clk); i++)
540 if (IS_ERR(clk[i])) 559 if (IS_ERR(clk[i]))
@@ -554,7 +573,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
554 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); 573 clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL);
555 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); 574 clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL);
556 575
557 if (imx6q_revision() != IMX_CHIP_REVISION_1_0) { 576 if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) {
558 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); 577 clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
559 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); 578 clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
560 } 579 }
@@ -574,6 +593,16 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
574 clk_prepare_enable(clk[usbphy2_gate]); 593 clk_prepare_enable(clk[usbphy2_gate]);
575 } 594 }
576 595
596 /*
597 * Let's initially set up CLKO with OSC24M, since this configuration
598 * is widely used by imx6q board designs to clock audio codec.
599 */
600 ret = clk_set_parent(clk[cko2_sel], clk[osc]);
601 if (!ret)
602 ret = clk_set_parent(clk[cko], clk[cko2]);
603 if (ret)
604 pr_warn("failed to set up CLKO: %d\n", ret);
605
577 /* Set initial power mode */ 606 /* Set initial power mode */
578 imx6q_set_lpm(WAIT_CLOCKED); 607 imx6q_set_lpm(WAIT_CLOCKED);
579 608
diff --git a/arch/arm/mach-imx/clk-imx6sl.c b/arch/arm/mach-imx/clk-imx6sl.c
index a307ac22dffe..a5c3c5d21aee 100644
--- a/arch/arm/mach-imx/clk-imx6sl.c
+++ b/arch/arm/mach-imx/clk-imx6sl.c
@@ -138,14 +138,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
138 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels)); 138 clks[IMX6SL_CLK_PERIPH_CLK2_SEL] = imx_clk_mux("periph_clk2_sel", base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
139 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 139 clks[IMX6SL_CLK_CSI_SEL] = imx_clk_mux("csi_sel", base + 0x3c, 9, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
140 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels)); 140 clks[IMX6SL_CLK_LCDIF_AXI_SEL] = imx_clk_mux("lcdif_axi_sel", base + 0x3c, 14, 2, csi_lcdif_sels, ARRAY_SIZE(csi_lcdif_sels));
141 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 141 clks[IMX6SL_CLK_USDHC1_SEL] = imx_clk_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
142 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 142 clks[IMX6SL_CLK_USDHC2_SEL] = imx_clk_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
143 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 143 clks[IMX6SL_CLK_USDHC3_SEL] = imx_clk_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
144 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels)); 144 clks[IMX6SL_CLK_USDHC4_SEL] = imx_clk_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
145 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 145 clks[IMX6SL_CLK_SSI1_SEL] = imx_clk_fixup_mux("ssi1_sel", base + 0x1c, 10, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
146 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 146 clks[IMX6SL_CLK_SSI2_SEL] = imx_clk_fixup_mux("ssi2_sel", base + 0x1c, 12, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
147 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels)); 147 clks[IMX6SL_CLK_SSI3_SEL] = imx_clk_fixup_mux("ssi3_sel", base + 0x1c, 14, 2, ssi_sels, ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
148 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels)); 148 clks[IMX6SL_CLK_PERCLK_SEL] = imx_clk_fixup_mux("perclk_sel", base + 0x1c, 6, 1, perclk_sels, ARRAY_SIZE(perclk_sels), imx_cscmr1_fixup);
149 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 149 clks[IMX6SL_CLK_PXP_AXI_SEL] = imx_clk_mux("pxp_axi_sel", base + 0x34, 6, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
150 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels)); 150 clks[IMX6SL_CLK_EPDC_AXI_SEL] = imx_clk_mux("epdc_axi_sel", base + 0x34, 15, 3, epdc_pxp_sels, ARRAY_SIZE(epdc_pxp_sels));
151 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels)); 151 clks[IMX6SL_CLK_GPU2D_OVG_SEL] = imx_clk_mux("gpu2d_ovg_sel", base + 0x18, 4, 2, gpu2d_ovg_sels, ARRAY_SIZE(gpu2d_ovg_sels));
@@ -179,14 +179,14 @@ static void __init imx6sl_clocks_init(struct device_node *ccm_node)
179 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6); 179 clks[IMX6SL_CLK_SSI2_PODF] = imx_clk_divider("ssi2_podf", "ssi2_pred", base + 0x2c, 0, 6);
180 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3); 180 clks[IMX6SL_CLK_SSI3_PRED] = imx_clk_divider("ssi3_pred", "ssi3_sel", base + 0x28, 22, 3);
181 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6); 181 clks[IMX6SL_CLK_SSI3_PODF] = imx_clk_divider("ssi3_podf", "ssi3_pred", base + 0x28, 16, 6);
182 clks[IMX6SL_CLK_PERCLK] = imx_clk_divider("perclk", "perclk_sel", base + 0x1c, 0, 6); 182 clks[IMX6SL_CLK_PERCLK] = imx_clk_fixup_divider("perclk", "perclk_sel", base + 0x1c, 0, 6, imx_cscmr1_fixup);
183 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3); 183 clks[IMX6SL_CLK_PXP_AXI_PODF] = imx_clk_divider("pxp_axi_podf", "pxp_axi_sel", base + 0x34, 3, 3);
184 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3); 184 clks[IMX6SL_CLK_EPDC_AXI_PODF] = imx_clk_divider("epdc_axi_podf", "epdc_axi_sel", base + 0x34, 12, 3);
185 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3); 185 clks[IMX6SL_CLK_GPU2D_OVG_PODF] = imx_clk_divider("gpu2d_ovg_podf", "gpu2d_ovg_sel", base + 0x18, 26, 3);
186 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3); 186 clks[IMX6SL_CLK_GPU2D_PODF] = imx_clk_divider("gpu2d_podf", "gpu2d_sel", base + 0x18, 29, 3);
187 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3); 187 clks[IMX6SL_CLK_LCDIF_PIX_PRED] = imx_clk_divider("lcdif_pix_pred", "lcdif_pix_sel", base + 0x38, 3, 3);
188 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3); 188 clks[IMX6SL_CLK_EPDC_PIX_PRED] = imx_clk_divider("epdc_pix_pred", "epdc_pix_sel", base + 0x38, 12, 3);
189 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3); 189 clks[IMX6SL_CLK_LCDIF_PIX_PODF] = imx_clk_fixup_divider("lcdif_pix_podf", "lcdif_pix_pred", base + 0x1c, 20, 3, imx_cscmr1_fixup);
190 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3); 190 clks[IMX6SL_CLK_EPDC_PIX_PODF] = imx_clk_divider("epdc_pix_podf", "epdc_pix_pred", base + 0x18, 23, 3);
191 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3); 191 clks[IMX6SL_CLK_SPDIF0_PRED] = imx_clk_divider("spdif0_pred", "spdif0_sel", base + 0x30, 25, 3);
192 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3); 192 clks[IMX6SL_CLK_SPDIF0_PODF] = imx_clk_divider("spdif0_podf", "spdif0_pred", base + 0x30, 22, 3);
diff --git a/arch/arm/mach-imx/clk-pllv3.c b/arch/arm/mach-imx/clk-pllv3.c
index a9fad5f8d340..f6640b6a7b31 100644
--- a/arch/arm/mach-imx/clk-pllv3.c
+++ b/arch/arm/mach-imx/clk-pllv3.c
@@ -48,7 +48,7 @@ struct clk_pllv3 {
48static int clk_pllv3_prepare(struct clk_hw *hw) 48static int clk_pllv3_prepare(struct clk_hw *hw)
49{ 49{
50 struct clk_pllv3 *pll = to_clk_pllv3(hw); 50 struct clk_pllv3 *pll = to_clk_pllv3(hw);
51 unsigned long timeout = jiffies + msecs_to_jiffies(10); 51 unsigned long timeout;
52 u32 val; 52 u32 val;
53 53
54 val = readl_relaxed(pll->base); 54 val = readl_relaxed(pll->base);
@@ -59,12 +59,19 @@ static int clk_pllv3_prepare(struct clk_hw *hw)
59 val &= ~BM_PLL_POWER; 59 val &= ~BM_PLL_POWER;
60 writel_relaxed(val, pll->base); 60 writel_relaxed(val, pll->base);
61 61
62 timeout = jiffies + msecs_to_jiffies(10);
62 /* Wait for PLL to lock */ 63 /* Wait for PLL to lock */
63 while (!(readl_relaxed(pll->base) & BM_PLL_LOCK)) 64 do {
65 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
66 break;
64 if (time_after(jiffies, timeout)) 67 if (time_after(jiffies, timeout))
65 return -ETIMEDOUT; 68 break;
69 } while (1);
66 70
67 return 0; 71 if (readl_relaxed(pll->base) & BM_PLL_LOCK)
72 return 0;
73 else
74 return -ETIMEDOUT;
68} 75}
69 76
70static void clk_pllv3_unprepare(struct clk_hw *hw) 77static void clk_pllv3_unprepare(struct clk_hw *hw)
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
index 55bc80a00666..edc35df7bed4 100644
--- a/arch/arm/mach-imx/clk.c
+++ b/arch/arm/mach-imx/clk.c
@@ -37,3 +37,29 @@ struct clk * __init imx_obtain_fixed_clock(
37 clk = imx_clk_fixed(name, rate); 37 clk = imx_clk_fixed(name, rate);
38 return clk; 38 return clk;
39} 39}
40
41/*
42 * This fixups the register CCM_CSCMR1 write value.
43 * The write/read/divider values of the aclk_podf field
44 * of that register have the relationship described by
45 * the following table:
46 *
47 * write value read value divider
48 * 3b'000 3b'110 7
49 * 3b'001 3b'111 8
50 * 3b'010 3b'100 5
51 * 3b'011 3b'101 6
52 * 3b'100 3b'010 3
53 * 3b'101 3b'011 4
54 * 3b'110 3b'000 1
55 * 3b'111 3b'001 2(default)
56 *
57 * That's why we do the xor operation below.
58 */
59#define CSCMR1_FIXUP 0x00600000
60
61void imx_cscmr1_fixup(u32 *val)
62{
63 *val ^= CSCMR1_FIXUP;
64 return;
65}
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 0e4e8bb261b9..048c5ad8a80b 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -6,6 +6,8 @@
6 6
7extern spinlock_t imx_ccm_lock; 7extern spinlock_t imx_ccm_lock;
8 8
9extern void imx_cscmr1_fixup(u32 *val);
10
9struct clk *imx_clk_pllv1(const char *name, const char *parent, 11struct clk *imx_clk_pllv1(const char *name, const char *parent,
10 void __iomem *base); 12 void __iomem *base);
11 13
@@ -49,6 +51,14 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
49 u8 width, void __iomem *busy_reg, u8 busy_shift, 51 u8 width, void __iomem *busy_reg, u8 busy_shift,
50 const char **parent_names, int num_parents); 52 const char **parent_names, int num_parents);
51 53
54struct clk *imx_clk_fixup_divider(const char *name, const char *parent,
55 void __iomem *reg, u8 shift, u8 width,
56 void (*fixup)(u32 *val));
57
58struct clk *imx_clk_fixup_mux(const char *name, void __iomem *reg,
59 u8 shift, u8 width, const char **parents,
60 int num_parents, void (*fixup)(u32 *val));
61
52static inline struct clk *imx_clk_fixed(const char *name, int rate) 62static inline struct clk *imx_clk_fixed(const char *name, int rate)
53{ 63{
54 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate); 64 return clk_register_fixed_rate(NULL, name, NULL, CLK_IS_ROOT, rate);
@@ -79,7 +89,8 @@ static inline struct clk *imx_clk_gate(const char *name, const char *parent,
79static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg, 89static inline struct clk *imx_clk_mux(const char *name, void __iomem *reg,
80 u8 shift, u8 width, const char **parents, int num_parents) 90 u8 shift, u8 width, const char **parents, int num_parents)
81{ 91{
82 return clk_register_mux(NULL, name, parents, num_parents, 0, reg, shift, 92 return clk_register_mux(NULL, name, parents, num_parents,
93 CLK_SET_RATE_NO_REPARENT, reg, shift,
83 width, 0, &imx_ccm_lock); 94 width, 0, &imx_ccm_lock);
84} 95}
85 96
@@ -88,7 +99,7 @@ static inline struct clk *imx_clk_mux_flags(const char *name,
88 int num_parents, unsigned long flags) 99 int num_parents, unsigned long flags)
89{ 100{
90 return clk_register_mux(NULL, name, parents, num_parents, 101 return clk_register_mux(NULL, name, parents, num_parents,
91 flags, reg, shift, width, 0, 102 flags | CLK_SET_RATE_NO_REPARENT, reg, shift, width, 0,
92 &imx_ccm_lock); 103 &imx_ccm_lock);
93} 104}
94 105
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index cb6c838b63ed..4517fd760bfc 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -137,7 +137,6 @@ extern void imx_gpc_restore_all(void);
137extern void imx_anatop_init(void); 137extern void imx_anatop_init(void);
138extern void imx_anatop_pre_suspend(void); 138extern void imx_anatop_pre_suspend(void);
139extern void imx_anatop_post_resume(void); 139extern void imx_anatop_post_resume(void);
140extern void imx_anatop_usb_chrg_detect_disable(void);
141extern u32 imx_anatop_get_digprog(void); 140extern u32 imx_anatop_get_digprog(void);
142extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode); 141extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
143extern void imx6q_set_chicken_bit(void); 142extern void imx6q_set_chicken_bit(void);
@@ -147,12 +146,10 @@ extern int imx_cpu_kill(unsigned int cpu);
147 146
148#ifdef CONFIG_PM 147#ifdef CONFIG_PM
149extern void imx6q_pm_init(void); 148extern void imx6q_pm_init(void);
150extern void imx51_pm_init(void); 149extern void imx5_pm_init(void);
151extern void imx53_pm_init(void);
152#else 150#else
153static inline void imx6q_pm_init(void) {} 151static inline void imx6q_pm_init(void) {}
154static inline void imx51_pm_init(void) {} 152static inline void imx5_pm_init(void) {}
155static inline void imx53_pm_init(void) {}
156#endif 153#endif
157 154
158#ifdef CONFIG_NEON 155#ifdef CONFIG_NEON
@@ -161,6 +158,12 @@ extern int mx51_neon_fixup(void);
161static inline int mx51_neon_fixup(void) { return 0; } 158static inline int mx51_neon_fixup(void) { return 0; }
162#endif 159#endif
163 160
161#ifdef CONFIG_CACHE_L2X0
162extern void imx_init_l2cache(void);
163#else
164static inline void imx_init_l2cache(void) {}
165#endif
166
164extern struct smp_operations imx_smp_ops; 167extern struct smp_operations imx_smp_ops;
165 168
166#endif 169#endif
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 29ac8ee651d2..97f9c6297fcf 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -26,7 +26,7 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/mtd/physmap.h> 27#include <linux/mtd/physmap.h>
28#include <linux/i2c.h> 28#include <linux/i2c.h>
29#include <linux/i2c/pca953x.h> 29#include <linux/platform_data/pca953x.h>
30#include <linux/input.h> 30#include <linux/input.h>
31#include <linux/gpio.h> 31#include <linux/gpio.h>
32#include <linux/delay.h> 32#include <linux/delay.h>
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index a02f275a198d..85a1b51346c8 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -31,7 +31,7 @@
31#include <linux/regmap.h> 31#include <linux/regmap.h>
32#include <linux/micrel_phy.h> 32#include <linux/micrel_phy.h>
33#include <linux/mfd/syscon.h> 33#include <linux/mfd/syscon.h>
34#include <asm/hardware/cache-l2x0.h> 34#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
35#include <asm/mach/arch.h> 35#include <asm/mach/arch.h>
36#include <asm/mach/map.h> 36#include <asm/mach/map.h>
37#include <asm/system_misc.h> 37#include <asm/system_misc.h>
@@ -103,87 +103,77 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
103{ 103{
104 if (IS_BUILTIN(CONFIG_PHYLIB)) { 104 if (IS_BUILTIN(CONFIG_PHYLIB)) {
105 /* min rx data delay */ 105 /* min rx data delay */
106 phy_write(phydev, 0x0b, 0x8105); 106 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
107 phy_write(phydev, 0x0c, 0x0000); 107 0x8000 | MICREL_KSZ9021_RGMII_RX_DATA_PAD_SCEW);
108 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0x0000);
108 109
109 /* max rx/tx clock delay, min rx/tx control delay */ 110 /* max rx/tx clock delay, min rx/tx control delay */
110 phy_write(phydev, 0x0b, 0x8104); 111 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
111 phy_write(phydev, 0x0c, 0xf0f0); 112 0x8000 | MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
112 phy_write(phydev, 0x0b, 0x104); 113 phy_write(phydev, MICREL_KSZ9021_EXTREG_DATA_WRITE, 0xf0f0);
114 phy_write(phydev, MICREL_KSZ9021_EXTREG_CTRL,
115 MICREL_KSZ9021_RGMII_CLK_CTRL_PAD_SCEW);
113 } 116 }
114 117
115 return 0; 118 return 0;
116} 119}
117 120
118static void __init imx6q_sabrelite_cko1_setup(void) 121static void mmd_write_reg(struct phy_device *dev, int device, int reg, int val)
119{ 122{
120 struct clk *cko1_sel, *ahb, *cko1; 123 phy_write(dev, 0x0d, device);
121 unsigned long rate; 124 phy_write(dev, 0x0e, reg);
122 125 phy_write(dev, 0x0d, (1 << 14) | device);
123 cko1_sel = clk_get_sys(NULL, "cko1_sel"); 126 phy_write(dev, 0x0e, val);
124 ahb = clk_get_sys(NULL, "ahb");
125 cko1 = clk_get_sys(NULL, "cko1");
126 if (IS_ERR(cko1_sel) || IS_ERR(ahb) || IS_ERR(cko1)) {
127 pr_err("cko1 setup failed!\n");
128 goto put_clk;
129 }
130 clk_set_parent(cko1_sel, ahb);
131 rate = clk_round_rate(cko1, 16000000);
132 clk_set_rate(cko1, rate);
133put_clk:
134 if (!IS_ERR(cko1_sel))
135 clk_put(cko1_sel);
136 if (!IS_ERR(ahb))
137 clk_put(ahb);
138 if (!IS_ERR(cko1))
139 clk_put(cko1);
140} 127}
141 128
142static void __init imx6q_sabrelite_init(void) 129static int ksz9031rn_phy_fixup(struct phy_device *dev)
143{ 130{
144 if (IS_BUILTIN(CONFIG_PHYLIB)) 131 /*
145 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, 132 * min rx data delay, max rx/tx clock delay,
146 ksz9021rn_phy_fixup); 133 * min rx/tx control delay
147 imx6q_sabrelite_cko1_setup(); 134 */
135 mmd_write_reg(dev, 2, 4, 0);
136 mmd_write_reg(dev, 2, 5, 0);
137 mmd_write_reg(dev, 2, 8, 0x003ff);
138
139 return 0;
148} 140}
149 141
150static void __init imx6q_sabresd_cko1_setup(void) 142static int ar8031_phy_fixup(struct phy_device *dev)
151{ 143{
152 struct clk *cko1_sel, *pll4, *pll4_post, *cko1; 144 u16 val;
153 unsigned long rate; 145
154 146 /* To enable AR8031 output a 125MHz clk from CLK_25M */
155 cko1_sel = clk_get_sys(NULL, "cko1_sel"); 147 phy_write(dev, 0xd, 0x7);
156 pll4 = clk_get_sys(NULL, "pll4_audio"); 148 phy_write(dev, 0xe, 0x8016);
157 pll4_post = clk_get_sys(NULL, "pll4_post_div"); 149 phy_write(dev, 0xd, 0x4007);
158 cko1 = clk_get_sys(NULL, "cko1"); 150
159 if (IS_ERR(cko1_sel) || IS_ERR(pll4) 151 val = phy_read(dev, 0xe);
160 || IS_ERR(pll4_post) || IS_ERR(cko1)) { 152 val &= 0xffe3;
161 pr_err("cko1 setup failed!\n"); 153 val |= 0x18;
162 goto put_clk; 154 phy_write(dev, 0xe, val);
163 } 155
164 /* 156 /* introduce tx clock delay */
165 * Setting pll4 at 768MHz (24MHz * 32) 157 phy_write(dev, 0x1d, 0x5);
166 * So its child clock can get 24MHz easily 158 val = phy_read(dev, 0x1e);
167 */ 159 val |= 0x0100;
168 clk_set_rate(pll4, 768000000); 160 phy_write(dev, 0x1e, val);
169 161
170 clk_set_parent(cko1_sel, pll4_post); 162 return 0;
171 rate = clk_round_rate(cko1, 24000000);
172 clk_set_rate(cko1, rate);
173put_clk:
174 if (!IS_ERR(cko1_sel))
175 clk_put(cko1_sel);
176 if (!IS_ERR(pll4_post))
177 clk_put(pll4_post);
178 if (!IS_ERR(pll4))
179 clk_put(pll4);
180 if (!IS_ERR(cko1))
181 clk_put(cko1);
182} 163}
183 164
184static void __init imx6q_sabresd_init(void) 165#define PHY_ID_AR8031 0x004dd074
166
167static void __init imx6q_enet_phy_init(void)
185{ 168{
186 imx6q_sabresd_cko1_setup(); 169 if (IS_BUILTIN(CONFIG_PHYLIB)) {
170 phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK,
171 ksz9021rn_phy_fixup);
172 phy_register_fixup_for_uid(PHY_ID_KSZ9031, MICREL_PHY_ID_MASK,
173 ksz9031rn_phy_fixup);
174 phy_register_fixup_for_uid(PHY_ID_AR8031, 0xffffffff,
175 ar8031_phy_fixup);
176 }
187} 177}
188 178
189static void __init imx6q_1588_init(void) 179static void __init imx6q_1588_init(void)
@@ -192,29 +182,22 @@ static void __init imx6q_1588_init(void)
192 182
193 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); 183 gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
194 if (!IS_ERR(gpr)) 184 if (!IS_ERR(gpr))
195 regmap_update_bits(gpr, 0x4, 1 << 21, 1 << 21); 185 regmap_update_bits(gpr, IOMUXC_GPR1,
186 IMX6Q_GPR1_ENET_CLK_SEL_MASK,
187 IMX6Q_GPR1_ENET_CLK_SEL_ANATOP);
196 else 188 else
197 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n"); 189 pr_err("failed to find fsl,imx6q-iomux-gpr regmap\n");
198 190
199} 191}
200static void __init imx6q_usb_init(void)
201{
202 imx_anatop_usb_chrg_detect_disable();
203}
204 192
205static void __init imx6q_init_machine(void) 193static void __init imx6q_init_machine(void)
206{ 194{
207 if (of_machine_is_compatible("fsl,imx6q-sabrelite")) 195 imx6q_enet_phy_init();
208 imx6q_sabrelite_init();
209 else if (of_machine_is_compatible("fsl,imx6q-sabresd") ||
210 of_machine_is_compatible("fsl,imx6dl-sabresd"))
211 imx6q_sabresd_init();
212 196
213 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 197 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
214 198
215 imx_anatop_init(); 199 imx_anatop_init();
216 imx6q_pm_init(); 200 imx6q_pm_init();
217 imx6q_usb_init();
218 imx6q_1588_init(); 201 imx6q_1588_init();
219} 202}
220 203
@@ -296,44 +279,10 @@ static void __init imx6q_map_io(void)
296 imx_scu_map_io(); 279 imx_scu_map_io();
297} 280}
298 281
299#ifdef CONFIG_CACHE_L2X0
300static void __init imx6q_init_l2cache(void)
301{
302 void __iomem *l2x0_base;
303 struct device_node *np;
304 unsigned int val;
305
306 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
307 if (!np)
308 goto out;
309
310 l2x0_base = of_iomap(np, 0);
311 if (!l2x0_base) {
312 of_node_put(np);
313 goto out;
314 }
315
316 /* Configure the L2 PREFETCH and POWER registers */
317 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
318 val |= 0x70800000;
319 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
320 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
321 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
322
323 iounmap(l2x0_base);
324 of_node_put(np);
325
326out:
327 l2x0_of_init(0, ~0UL);
328}
329#else
330static inline void imx6q_init_l2cache(void) {}
331#endif
332
333static void __init imx6q_init_irq(void) 282static void __init imx6q_init_irq(void)
334{ 283{
335 imx6q_init_revision(); 284 imx6q_init_revision();
336 imx6q_init_l2cache(); 285 imx_init_l2cache();
337 imx_src_init(); 286 imx_src_init();
338 imx_gpc_init(); 287 imx_gpc_init();
339 irqchip_init(); 288 irqchip_init();
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index 132db2609507..0d75dc54f715 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -11,7 +11,6 @@
11#include <linux/irqchip.h> 11#include <linux/irqchip.h>
12#include <linux/of.h> 12#include <linux/of.h>
13#include <linux/of_platform.h> 13#include <linux/of_platform.h>
14#include <asm/hardware/cache-l2x0.h>
15#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
16#include <asm/mach/map.h> 15#include <asm/mach/map.h>
17 16
@@ -26,7 +25,7 @@ static void __init imx6sl_init_machine(void)
26 25
27static void __init imx6sl_init_irq(void) 26static void __init imx6sl_init_irq(void)
28{ 27{
29 l2x0_of_init(0, ~0UL); 28 imx_init_l2cache();
30 imx_src_init(); 29 imx_src_init();
31 imx_gpc_init(); 30 imx_gpc_init();
32 irqchip_init(); 31 irqchip_init();
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index a27faaba98ec..c91894003da9 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -26,7 +26,7 @@
26#include <asm/mach/time.h> 26#include <asm/mach/time.h>
27#include <asm/mach/map.h> 27#include <asm/mach/map.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/i2c/pca953x.h> 29#include <linux/platform_data/pca953x.h>
30 30
31#include "common.h" 31#include "common.h"
32#include "devices-imx27.h" 32#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index e065c117f5a6..5211f62c624e 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -61,25 +61,8 @@ void __init mx25_init_irq(void)
61 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR)); 61 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
62} 62}
63 63
64static struct sdma_script_start_addrs imx25_sdma_script __initdata = {
65 .ap_2_ap_addr = 729,
66 .uart_2_mcu_addr = 904,
67 .per_2_app_addr = 1255,
68 .mcu_2_app_addr = 834,
69 .uartsh_2_mcu_addr = 1120,
70 .per_2_shp_addr = 1329,
71 .mcu_2_shp_addr = 1048,
72 .ata_2_mcu_addr = 1560,
73 .mcu_2_ata_addr = 1479,
74 .app_2_per_addr = 1189,
75 .app_2_mcu_addr = 770,
76 .shp_2_per_addr = 1407,
77 .shp_2_mcu_addr = 979,
78};
79
80static struct sdma_platform_data imx25_sdma_pdata __initdata = { 64static struct sdma_platform_data imx25_sdma_pdata __initdata = {
81 .fw_name = "sdma-imx25.bin", 65 .fw_name = "sdma-imx25.bin",
82 .script_addrs = &imx25_sdma_script,
83}; 66};
84 67
85static const struct resource imx25_audmux_res[] __initconst = { 68static const struct resource imx25_audmux_res[] __initconst = {
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index cf193d87274a..eb3cce38c70d 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -103,22 +103,8 @@ void __init mx53_init_irq(void)
103 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR)); 103 tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
104} 104}
105 105
106static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
107 .ap_2_ap_addr = 642,
108 .uart_2_mcu_addr = 817,
109 .mcu_2_app_addr = 747,
110 .mcu_2_shp_addr = 961,
111 .ata_2_mcu_addr = 1473,
112 .mcu_2_ata_addr = 1392,
113 .app_2_per_addr = 1033,
114 .app_2_mcu_addr = 683,
115 .shp_2_per_addr = 1251,
116 .shp_2_mcu_addr = 892,
117};
118
119static struct sdma_platform_data imx51_sdma_pdata __initdata = { 106static struct sdma_platform_data imx51_sdma_pdata __initdata = {
120 .fw_name = "sdma-imx51.bin", 107 .fw_name = "sdma-imx51.bin",
121 .script_addrs = &imx51_sdma_script,
122}; 108};
123 109
124static const struct resource imx51_audmux_res[] __initconst = { 110static const struct resource imx51_audmux_res[] __initconst = {
@@ -153,10 +139,10 @@ void __init imx51_soc_init(void)
153void __init imx51_init_late(void) 139void __init imx51_init_late(void)
154{ 140{
155 mx51_neon_fixup(); 141 mx51_neon_fixup();
156 imx51_pm_init(); 142 imx5_pm_init();
157} 143}
158 144
159void __init imx53_init_late(void) 145void __init imx53_init_late(void)
160{ 146{
161 imx53_pm_init(); 147 imx5_pm_init();
162} 148}
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index 82e79c658eb2..58aeaf5baaf6 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -169,14 +169,9 @@ static int __init imx5_pm_common_init(void)
169 return imx5_cpuidle_init(); 169 return imx5_cpuidle_init();
170} 170}
171 171
172void __init imx51_pm_init(void) 172void __init imx5_pm_init(void)
173{ 173{
174 int ret = imx5_pm_common_init(); 174 int ret = imx5_pm_common_init();
175 if (!ret) 175 if (!ret)
176 suspend_set_ops(&mx5_suspend_ops); 176 suspend_set_ops(&mx5_suspend_ops);
177} 177}
178
179void __init imx53_pm_init(void)
180{
181 imx5_pm_common_init();
182}
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index 6fe81bb4d3c9..64ff37ea72b1 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -27,6 +27,7 @@
27#include <asm/system_misc.h> 27#include <asm/system_misc.h>
28#include <asm/proc-fns.h> 28#include <asm/proc-fns.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30#include <asm/hardware/cache-l2x0.h>
30 31
31#include "common.h" 32#include "common.h"
32#include "hardware.h" 33#include "hardware.h"
@@ -95,3 +96,35 @@ void __init mxc_arch_reset_init_dt(void)
95 96
96 clk_prepare(wdog_clk); 97 clk_prepare(wdog_clk);
97} 98}
99
100#ifdef CONFIG_CACHE_L2X0
101void __init imx_init_l2cache(void)
102{
103 void __iomem *l2x0_base;
104 struct device_node *np;
105 unsigned int val;
106
107 np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
108 if (!np)
109 goto out;
110
111 l2x0_base = of_iomap(np, 0);
112 if (!l2x0_base) {
113 of_node_put(np);
114 goto out;
115 }
116
117 /* Configure the L2 PREFETCH and POWER registers */
118 val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
119 val |= 0x70800000;
120 writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
121 val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
122 writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
123
124 iounmap(l2x0_base);
125 of_node_put(np);
126
127out:
128 l2x0_of_init(0, ~0UL);
129}
130#endif
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 51a50e996840..366d1a3b418d 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -7,7 +7,6 @@ config ARCH_KEYSTONE
7 select HAVE_SMP 7 select HAVE_SMP
8 select CLKSRC_MMIO 8 select CLKSRC_MMIO
9 select GENERIC_CLOCKEVENTS 9 select GENERIC_CLOCKEVENTS
10 select HAVE_SCHED_CLOCK
11 select ARCH_WANT_OPTIONAL_GPIOLIB 10 select ARCH_WANT_OPTIONAL_GPIOLIB
12 select ARM_ERRATA_798181 if SMP 11 select ARM_ERRATA_798181 if SMP
13 help 12 help
diff --git a/arch/arm/mach-keystone/platsmp.c b/arch/arm/mach-keystone/platsmp.c
index 14378e3fef16..c12296157d4a 100644
--- a/arch/arm/mach-keystone/platsmp.c
+++ b/arch/arm/mach-keystone/platsmp.c
@@ -38,6 +38,5 @@ static int keystone_smp_boot_secondary(unsigned int cpu,
38} 38}
39 39
40struct smp_operations keystone_smp_ops __initdata = { 40struct smp_operations keystone_smp_ops __initdata = {
41 .smp_init_cpus = arm_dt_init_cpu_maps,
42 .smp_boot_secondary = keystone_smp_boot_secondary, 41 .smp_boot_secondary = keystone_smp_boot_secondary,
43}; 42};
diff --git a/arch/arm/mach-keystone/smc.S b/arch/arm/mach-keystone/smc.S
index 9b9e4f7b241e..d15de8179fab 100644
--- a/arch/arm/mach-keystone/smc.S
+++ b/arch/arm/mach-keystone/smc.S
@@ -22,8 +22,7 @@
22 * Return: Non zero value on failure 22 * Return: Non zero value on failure
23 */ 23 */
24ENTRY(keystone_cpu_smc) 24ENTRY(keystone_cpu_smc)
25 stmfd sp!, {r4-r12, lr} 25 stmfd sp!, {r4-r11, lr}
26 smc #0 26 smc #0
27 dsb 27 ldmfd sp!, {r4-r11, pc}
28 ldmfd sp!, {r4-r12, pc}
29ENDPROC(keystone_cpu_smc) 28ENDPROC(keystone_cpu_smc)
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index b634f9650a7b..fe8319ad3158 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -2,67 +2,32 @@ if ARCH_KIRKWOOD
2 2
3menu "Marvell Kirkwood Implementations" 3menu "Marvell Kirkwood Implementations"
4 4
5config KIRKWOOD_LEGACY
6 bool
7
5config MACH_D2NET_V2 8config MACH_D2NET_V2
6 bool "LaCie d2 Network v2 NAS Board" 9 bool "LaCie d2 Network v2 NAS Board"
10 select KIRKWOOD_LEGACY
7 help 11 help
8 Say 'Y' here if you want your kernel to support the 12 Say 'Y' here if you want your kernel to support the
9 LaCie d2 Network v2 NAS. 13 LaCie d2 Network v2 NAS.
10 14
11config MACH_DOCKSTAR
12 bool "Seagate FreeAgent DockStar"
13 help
14 Say 'Y' here if you want your kernel to support the
15 Seagate FreeAgent DockStar.
16
17config MACH_ESATA_SHEEVAPLUG
18 bool "Marvell eSATA SheevaPlug Reference Board"
19 help
20 Say 'Y' here if you want your kernel to support the
21 Marvell eSATA SheevaPlug Reference Board.
22
23config MACH_GURUPLUG
24 bool "Marvell GuruPlug Reference Board"
25 help
26 Say 'Y' here if you want your kernel to support the
27 Marvell GuruPlug Reference Board.
28
29config MACH_INETSPACE_V2
30 bool "LaCie Internet Space v2 NAS Board"
31 help
32 Say 'Y' here if you want your kernel to support the
33 LaCie Internet Space v2 NAS.
34
35config MACH_MV88F6281GTW_GE
36 bool "Marvell 88F6281 GTW GE Board"
37 help
38 Say 'Y' here if you want your kernel to support the
39 Marvell 88F6281 GTW GE Board.
40
41config MACH_NET2BIG_V2 15config MACH_NET2BIG_V2
42 bool "LaCie 2Big Network v2 NAS Board" 16 bool "LaCie 2Big Network v2 NAS Board"
17 select KIRKWOOD_LEGACY
43 help 18 help
44 Say 'Y' here if you want your kernel to support the 19 Say 'Y' here if you want your kernel to support the
45 LaCie 2Big Network v2 NAS. 20 LaCie 2Big Network v2 NAS.
46 21
47config MACH_NET5BIG_V2 22config MACH_NET5BIG_V2
48 bool "LaCie 5Big Network v2 NAS Board" 23 bool "LaCie 5Big Network v2 NAS Board"
24 select KIRKWOOD_LEGACY
49 help 25 help
50 Say 'Y' here if you want your kernel to support the 26 Say 'Y' here if you want your kernel to support the
51 LaCie 5Big Network v2 NAS. 27 LaCie 5Big Network v2 NAS.
52 28
53config MACH_NETSPACE_MAX_V2
54 bool "LaCie Network Space Max v2 NAS Board"
55 help
56 Say 'Y' here if you want your kernel to support the
57 LaCie Network Space Max v2 NAS.
58
59config MACH_NETSPACE_V2
60 bool "LaCie Network Space v2 NAS Board"
61 help
62 Say 'Y' here if you want your kernel to support the
63 LaCie Network Space v2 NAS.
64
65config MACH_OPENRD 29config MACH_OPENRD
30 select KIRKWOOD_LEGACY
66 bool 31 bool
67 32
68config MACH_OPENRD_BASE 33config MACH_OPENRD_BASE
@@ -88,30 +53,28 @@ config MACH_OPENRD_ULTIMATE
88 53
89config MACH_RD88F6192_NAS 54config MACH_RD88F6192_NAS
90 bool "Marvell RD-88F6192-NAS Reference Board" 55 bool "Marvell RD-88F6192-NAS Reference Board"
56 select KIRKWOOD_LEGACY
91 help 57 help
92 Say 'Y' here if you want your kernel to support the 58 Say 'Y' here if you want your kernel to support the
93 Marvell RD-88F6192-NAS Reference Board. 59 Marvell RD-88F6192-NAS Reference Board.
94 60
95config MACH_RD88F6281 61config MACH_RD88F6281
96 bool "Marvell RD-88F6281 Reference Board" 62 bool "Marvell RD-88F6281 Reference Board"
63 select KIRKWOOD_LEGACY
97 help 64 help
98 Say 'Y' here if you want your kernel to support the 65 Say 'Y' here if you want your kernel to support the
99 Marvell RD-88F6281 Reference Board. 66 Marvell RD-88F6281 Reference Board.
100 67
101config MACH_SHEEVAPLUG
102 bool "Marvell SheevaPlug Reference Board"
103 help
104 Say 'Y' here if you want your kernel to support the
105 Marvell SheevaPlug Reference Board.
106
107config MACH_T5325 68config MACH_T5325
108 bool "HP t5325 Thin Client" 69 bool "HP t5325 Thin Client"
70 select KIRKWOOD_LEGACY
109 help 71 help
110 Say 'Y' here if you want your kernel to support the 72 Say 'Y' here if you want your kernel to support the
111 HP t5325 Thin Client. 73 HP t5325 Thin Client.
112 74
113config MACH_TS219 75config MACH_TS219
114 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS" 76 bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
77 select KIRKWOOD_LEGACY
115 help 78 help
116 Say 'Y' here if you want your kernel to support the 79 Say 'Y' here if you want your kernel to support the
117 QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and 80 QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
@@ -119,6 +82,7 @@ config MACH_TS219
119 82
120config MACH_TS41X 83config MACH_TS41X
121 bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS" 84 bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
85 select KIRKWOOD_LEGACY
122 help 86 help
123 Say 'Y' here if you want your kernel to support the 87 Say 'Y' here if you want your kernel to support the
124 QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo 88 QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
@@ -129,6 +93,9 @@ comment "Device tree entries"
129config ARCH_KIRKWOOD_DT 93config ARCH_KIRKWOOD_DT
130 bool "Marvell Kirkwood Flattened Device Tree" 94 bool "Marvell Kirkwood Flattened Device Tree"
131 select KIRKWOOD_CLK 95 select KIRKWOOD_CLK
96 select OF_IRQ
97 select ORION_IRQCHIP
98 select ORION_TIMER
132 select POWER_SUPPLY 99 select POWER_SUPPLY
133 select POWER_RESET 100 select POWER_RESET
134 select POWER_RESET_GPIO 101 select POWER_RESET_GPIO
@@ -139,184 +106,12 @@ config ARCH_KIRKWOOD_DT
139 Say 'Y' here if you want your kernel to support the 106 Say 'Y' here if you want your kernel to support the
140 Marvell Kirkwood using flattened device tree. 107 Marvell Kirkwood using flattened device tree.
141 108
142config MACH_CLOUDBOX_DT 109config MACH_MV88F6281GTW_GE_DT
143 bool "LaCie CloudBox NAS (Flattened Device Tree)" 110 bool "Marvell 88F6281 GTW GE Board (Flattened Device Tree)"
144 select ARCH_KIRKWOOD_DT 111 depends on ARCH_KIRKWOOD_DT
145 help
146 Say 'Y' here if you want your kernel to support the LaCie
147 CloudBox NAS, using Flattened Device Tree.
148
149config MACH_DB88F628X_BP_DT
150 bool "Marvell DB-88F628x-BP Development Board (Flattened Device Tree)"
151 help
152 Say 'Y' here if you want your kernel to support the Marvell
153 DB-88F6281-BP and DB-88F6282-BP Development Board (Flattened
154 Device Tree).
155
156config MACH_DLINK_KIRKWOOD_DT
157 bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
158 select ARCH_KIRKWOOD_DT
159 help
160 Say 'Y' here if you want your kernel to support the
161 Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
162 using Flattened Device Tree.
163
164config MACH_DOCKSTAR_DT
165 bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
166 select ARCH_KIRKWOOD_DT
167 help 112 help
168 Say 'Y' here if you want your kernel to support the 113 Say 'Y' here if you want your kernel to support the
169 Seagate FreeAgent Dockstar (Flattened Device Tree). 114 Marvell 88F6281 GTW GE Board (Flattened Device Tree).
170
171config MACH_DREAMPLUG_DT
172 bool "Marvell DreamPlug (Flattened Device Tree)"
173 select ARCH_KIRKWOOD_DT
174 help
175 Say 'Y' here if you want your kernel to support the
176 Marvell DreamPlug (Flattened Device Tree).
177
178config MACH_GOFLEXNET_DT
179 bool "Seagate GoFlex Net (Flattened Device Tree)"
180 select ARCH_KIRKWOOD_DT
181 help
182 Say 'Y' here if you want your kernel to support the
183 Seagate GoFlex Net (Flattened Device Tree).
184
185config MACH_GURUPLUG_DT
186 bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
187 select ARCH_KIRKWOOD_DT
188 help
189 Say 'Y' here if you want your kernel to support the
190 Marvell GuruPlug Reference Board (Flattened Device Tree).
191
192config MACH_IB62X0_DT
193 bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
194 select ARCH_KIRKWOOD_DT
195 help
196 Say 'Y' here if you want your kernel to support the
197 RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
198 Flattened Device Tree.
199
200config MACH_ICONNECT_DT
201 bool "Iomega Iconnect (Flattened Device Tree)"
202 select ARCH_KIRKWOOD_DT
203 help
204 Say 'Y' here to enable Iomega Iconnect support.
205
206config MACH_INETSPACE_V2_DT
207 bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
208 select ARCH_KIRKWOOD_DT
209 help
210 Say 'Y' here if you want your kernel to support the LaCie
211 Internet Space v2 NAS, using Flattened Device Tree.
212
213config MACH_IOMEGA_IX2_200_DT
214 bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
215 select ARCH_KIRKWOOD_DT
216 help
217 Say 'Y' here if you want your kernel to support the
218 Iomega StorCenter ix2-200 (Flattened Device Tree).
219
220config MACH_KM_KIRKWOOD_DT
221 bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
222 select ARCH_KIRKWOOD_DT
223 help
224 Say 'Y' here if you want your kernel to support the
225 Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
226
227config MACH_LSXL_DT
228 bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
229 select ARCH_KIRKWOOD_DT
230 select POWER_RESET_RESTART
231 help
232 Say 'Y' here if you want your kernel to support the
233 Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
234 Flattened Device Tree.
235
236config MACH_MPLCEC4_DT
237 bool "MPL CEC4 (Flattened Device Tree)"
238 select ARCH_KIRKWOOD_DT
239 help
240 Say 'Y' here if you want your kernel to support the
241 MPL CEC4 (Flattened Device Tree).
242
243config MACH_NETSPACE_LITE_V2_DT
244 bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
245 select ARCH_KIRKWOOD_DT
246 help
247 Say 'Y' here if you want your kernel to support the LaCie
248 Network Space Lite v2 NAS, using Flattened Device Tree.
249
250config MACH_NETSPACE_MAX_V2_DT
251 bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
252 select ARCH_KIRKWOOD_DT
253 help
254 Say 'Y' here if you want your kernel to support the LaCie
255 Network Space Max v2 NAS, using Flattened Device Tree.
256
257config MACH_NETSPACE_MINI_V2_DT
258 bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
259 select ARCH_KIRKWOOD_DT
260 help
261 Say 'Y' here if you want your kernel to support the LaCie
262 Network Space Mini v2 NAS using Flattened Device Tree.
263
264 This board is embedded in a product named CloudBox, which
265 provides automatic backup on a 100GB cloud storage. This
266 should not confused with a more recent LaCie NAS also named
267 CloudBox. For this last, the disk capacity is 1TB or above.
268
269config MACH_NETSPACE_V2_DT
270 bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
271 select ARCH_KIRKWOOD_DT
272 help
273 Say 'Y' here if you want your kernel to support the LaCie
274 Network Space v2 NAS, using Flattened Device Tree.
275
276config MACH_OPENBLOCKS_A6_DT
277 bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
278 select ARCH_KIRKWOOD_DT
279 help
280 Say 'Y' here if you want your kernel to support the
281 Plat'Home OpenBlocks A6 (Flattened Device Tree).
282
283config MACH_READYNAS_DT
284 bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
285 select ARCH_KIRKWOOD_DT
286 select ARM_APPENDED_DTB
287 select ARM_ATAG_DTB_COMPAT
288 help
289 Say 'Y' here if you want your kernel to support the
290 NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
291
292config MACH_SHEEVAPLUG_DT
293 bool "Marvell (eSATA) SheevaPlug (Flattened Device Tree)"
294 select ARCH_KIRKWOOD_DT
295 help
296 Say 'Y' here if you want your kernel to support the
297 Marvell (eSATA) SheevaPlug (Flattened Device Tree).
298
299config MACH_TOPKICK_DT
300 bool "USI Topkick (Flattened Device Tree)"
301 select ARCH_KIRKWOOD_DT
302 help
303 Say 'Y' here if you want your kernel to support the
304 USI Topkick, using Flattened Device Tree
305
306config MACH_TS219_DT
307 bool "Device Tree for QNAP TS-11X, TS-21X NAS"
308 select ARCH_KIRKWOOD_DT
309 select ARM_APPENDED_DTB
310 select ARM_ATAG_DTB_COMPAT
311 select POWER_RESET_QNAP
312 help
313 Say 'Y' here if you want your kernel to support the QNAP
314 TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
315 TS-219P+ Turbo NAS devices using Fattened Device Tree.
316 There are two different Device Tree descriptions, depending
317 on if the device is based on an if the board uses the MV6281
318 or MV6282. If you have the wrong one, the buttons will not
319 work.
320 115
321endmenu 116endmenu
322 117
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index ac4cd75dd499..d1f8e3d0793b 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -1,44 +1,14 @@
1obj-y += common.o irq.o pcie.o mpp.o 1obj-y += common.o pcie.o
2 2obj-$(CONFIG_KIRKWOOD_LEGACY) += irq.o mpp.o
3obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o 3obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
4obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
5obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
6obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
7obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
8obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
9obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o 4obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
10obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o 5obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
11obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o
12obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
13obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o 6obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
14obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o 7obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
15obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o 8obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
16obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
17obj-$(CONFIG_MACH_T5325) += t5325-setup.o 9obj-$(CONFIG_MACH_T5325) += t5325-setup.o
18obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o 10obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
19obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o 11obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
20 12
21obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o 13obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
22obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o 14obj-$(CONFIG_MACH_MV88F6281GTW_GE_DT) += board-mv88f6281gtw_ge.o
23obj-$(CONFIG_MACH_DB88F628X_BP_DT) += board-db88f628x-bp.o
24obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
25obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
26obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
27obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
28obj-$(CONFIG_MACH_GURUPLUG_DT) += board-guruplug.o
29obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
30obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
31obj-$(CONFIG_MACH_INETSPACE_V2_DT) += board-ns2.o
32obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
33obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
34obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
35obj-$(CONFIG_MACH_MPLCEC4_DT) += board-mplcec4.o
36obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o
37obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o
38obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o
39obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o
40obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
41obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o
42obj-$(CONFIG_MACH_SHEEVAPLUG_DT) += board-sheevaplug.o
43obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o
44obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
diff --git a/arch/arm/mach-kirkwood/board-db88f628x-bp.c b/arch/arm/mach-kirkwood/board-db88f628x-bp.c
deleted file mode 100644
index 2f574bc8ed40..000000000000
--- a/arch/arm/mach-kirkwood/board-db88f628x-bp.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Saeed Bishara <saeed@marvell.com>
3 *
4 * Marvell DB-88F628{1,2}-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/mv643xx_eth.h>
15#include "common.h"
16
17static struct mv643xx_eth_platform_data db88f628x_ge00_data = {
18 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
19};
20
21void __init db88f628x_init(void)
22{
23 kirkwood_ge00_init(&db88f628x_ge00_data);
24}
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
deleted file mode 100644
index a1aa87f09180..000000000000
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * Copyright 2012 (C), Jamie Lentin <jm@lentin.co.uk>
3 *
4 * arch/arm/mach-kirkwood/board-dnskw.c
5 *
6 * D-link DNS-320 & DNS-325 NAS Init for drivers not converted to
7 * flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/gpio.h>
19#include "common.h"
20
21static struct mv643xx_eth_platform_data dnskw_ge00_data = {
22 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
23};
24
25/* Register any GPIO for output and set the value */
26static void __init dnskw_gpio_register(unsigned gpio, char *name, int def)
27{
28 if (gpio_request(gpio, name) == 0 &&
29 gpio_direction_output(gpio, 0) == 0) {
30 gpio_set_value(gpio, def);
31 if (gpio_export(gpio, 0) != 0)
32 pr_err("dnskw: Failed to export GPIO %s\n", name);
33 } else
34 pr_err("dnskw: Failed to register %s\n", name);
35}
36
37void __init dnskw_init(void)
38{
39 kirkwood_ge00_init(&dnskw_ge00_data);
40
41 /* Set NAS to turn back on after a power failure */
42 dnskw_gpio_register(37, "dnskw:power:recover", 1);
43}
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
deleted file mode 100644
index d7196db33984..000000000000
--- a/arch/arm/mach-kirkwood/board-dockstar.c
+++ /dev/null
@@ -1,32 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/board-dockstar.c
3 *
4 * Seagate FreeAgent Dockstar Board Init for drivers not converted to
5 * flattened device tree yet.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 *
11 * Copied and modified for Seagate GoFlex Net support by
12 * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
13 * GoFlex kernel patches.
14 *
15 */
16
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/mv643xx_eth.h>
20#include "common.h"
21
22static struct mv643xx_eth_platform_data dockstar_ge00_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
24};
25
26void __init dockstar_dt_init(void)
27{
28 /*
29 * Basic setup. Needs to be called early.
30 */
31 kirkwood_ge00_init(&dockstar_ge00_data);
32}
diff --git a/arch/arm/mach-kirkwood/board-dreamplug.c b/arch/arm/mach-kirkwood/board-dreamplug.c
deleted file mode 100644
index 0903242c00dc..000000000000
--- a/arch/arm/mach-kirkwood/board-dreamplug.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
3 *
4 * arch/arm/mach-kirkwood/board-dreamplug.c
5 *
6 * Marvell DreamPlug Reference Board Init for drivers not converted to
7 * flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include "common.h"
19
20static struct mv643xx_eth_platform_data dreamplug_ge00_data = {
21 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
22};
23
24static struct mv643xx_eth_platform_data dreamplug_ge01_data = {
25 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
26};
27
28void __init dreamplug_init(void)
29{
30 /*
31 * Basic setup. Needs to be called early.
32 */
33 kirkwood_ge00_init(&dreamplug_ge00_data);
34 kirkwood_ge01_init(&dreamplug_ge01_data);
35}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 6e122ed3282f..82d3ad8e87cf 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -15,6 +15,9 @@
15#include <linux/of.h> 15#include <linux/of.h>
16#include <linux/of_platform.h> 16#include <linux/of_platform.h>
17#include <linux/clk-provider.h> 17#include <linux/clk-provider.h>
18#include <linux/clocksource.h>
19#include <linux/dma-mapping.h>
20#include <linux/irqchip.h>
18#include <linux/kexec.h> 21#include <linux/kexec.h>
19#include <asm/mach/arch.h> 22#include <asm/mach/arch.h>
20#include <asm/mach/map.h> 23#include <asm/mach/map.h>
@@ -49,10 +52,6 @@ static void __init kirkwood_legacy_clk_init(void)
49 orion_clkdev_add("1", "pcie", 52 orion_clkdev_add("1", "pcie",
50 of_clk_get_from_provider(&clkspec)); 53 of_clk_get_from_provider(&clkspec));
51 54
52 clkspec.args[0] = CGC_BIT_SDIO;
53 orion_clkdev_add(NULL, "mvsdio",
54 of_clk_get_from_provider(&clkspec));
55
56 /* 55 /*
57 * The ethernet interfaces forget the MAC address assigned by 56 * The ethernet interfaces forget the MAC address assigned by
58 * u-boot if the clocks are turned off. Until proper DT support 57 * u-boot if the clocks are turned off. Until proper DT support
@@ -60,19 +59,24 @@ static void __init kirkwood_legacy_clk_init(void)
60 */ 59 */
61 clkspec.args[0] = CGC_BIT_GE0; 60 clkspec.args[0] = CGC_BIT_GE0;
62 clk = of_clk_get_from_provider(&clkspec); 61 clk = of_clk_get_from_provider(&clkspec);
63 orion_clkdev_add(NULL, "mv643xx_eth_port.0", clk);
64 clk_prepare_enable(clk); 62 clk_prepare_enable(clk);
65 63
66 clkspec.args[0] = CGC_BIT_GE1; 64 clkspec.args[0] = CGC_BIT_GE1;
67 clk = of_clk_get_from_provider(&clkspec); 65 clk = of_clk_get_from_provider(&clkspec);
68 orion_clkdev_add(NULL, "mv643xx_eth_port.1", clk);
69 clk_prepare_enable(clk); 66 clk_prepare_enable(clk);
70} 67}
71 68
72static void __init kirkwood_of_clk_init(void) 69static void __init kirkwood_dt_time_init(void)
73{ 70{
74 of_clk_init(NULL); 71 of_clk_init(NULL);
75 kirkwood_legacy_clk_init(); 72 clocksource_of_init();
73}
74
75static void __init kirkwood_dt_init_early(void)
76{
77 mvebu_mbus_init("marvell,kirkwood-mbus",
78 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
79 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
76} 80}
77 81
78static void __init kirkwood_dt_init(void) 82static void __init kirkwood_dt_init(void)
@@ -87,14 +91,15 @@ static void __init kirkwood_dt_init(void)
87 */ 91 */
88 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); 92 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
89 93
94 BUG_ON(mvebu_mbus_dt_init());
90 kirkwood_setup_wins(); 95 kirkwood_setup_wins();
91 96
92 kirkwood_l2_init(); 97 kirkwood_l2_init();
93 98
94 kirkwood_cpufreq_init(); 99 kirkwood_cpufreq_init();
95 100
96 /* Setup root of clk tree */ 101 /* Setup clocks for legacy devices */
97 kirkwood_of_clk_init(); 102 kirkwood_legacy_clk_init();
98 103
99 kirkwood_cpuidle_init(); 104 kirkwood_cpuidle_init();
100 105
@@ -102,105 +107,22 @@ static void __init kirkwood_dt_init(void)
102 kexec_reinit = kirkwood_enable_pcie; 107 kexec_reinit = kirkwood_enable_pcie;
103#endif 108#endif
104 109
105 if (of_machine_is_compatible("globalscale,dreamplug")) 110 if (of_machine_is_compatible("marvell,mv88f6281gtw-ge"))
106 dreamplug_init(); 111 mv88f6281gtw_ge_init();
107
108 if (of_machine_is_compatible("globalscale,guruplug"))
109 guruplug_dt_init();
110
111 if (of_machine_is_compatible("globalscale,sheevaplug"))
112 sheevaplug_dt_init();
113
114 if (of_machine_is_compatible("dlink,dns-kirkwood"))
115 dnskw_init();
116
117 if (of_machine_is_compatible("iom,iconnect"))
118 iconnect_init();
119
120 if (of_machine_is_compatible("raidsonic,ib-nas62x0"))
121 ib62x0_init();
122
123 if (of_machine_is_compatible("qnap,ts219"))
124 qnap_dt_ts219_init();
125
126 if (of_machine_is_compatible("seagate,dockstar"))
127 dockstar_dt_init();
128
129 if (of_machine_is_compatible("seagate,goflexnet"))
130 goflexnet_init();
131
132 if (of_machine_is_compatible("buffalo,lsxl"))
133 lsxl_init();
134
135 if (of_machine_is_compatible("iom,ix2-200"))
136 iomega_ix2_200_init();
137
138 if (of_machine_is_compatible("keymile,km_kirkwood"))
139 km_kirkwood_init();
140
141 if (of_machine_is_compatible("lacie,cloudbox") ||
142 of_machine_is_compatible("lacie,inetspace_v2") ||
143 of_machine_is_compatible("lacie,netspace_lite_v2") ||
144 of_machine_is_compatible("lacie,netspace_max_v2") ||
145 of_machine_is_compatible("lacie,netspace_mini_v2") ||
146 of_machine_is_compatible("lacie,netspace_v2"))
147 ns2_init();
148
149 if (of_machine_is_compatible("marvell,db-88f6281-bp") ||
150 of_machine_is_compatible("marvell,db-88f6282-bp"))
151 db88f628x_init();
152
153 if (of_machine_is_compatible("mpl,cec4"))
154 mplcec4_init();
155
156 if (of_machine_is_compatible("netgear,readynas-duo-v2"))
157 netgear_readynas_init();
158
159 if (of_machine_is_compatible("plathome,openblocks-a6"))
160 openblocks_a6_init();
161
162 if (of_machine_is_compatible("usi,topkick"))
163 usi_topkick_init();
164 112
165 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 113 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
166} 114}
167 115
168static const char * const kirkwood_dt_board_compat[] = { 116static const char * const kirkwood_dt_board_compat[] = {
169 "globalscale,dreamplug", 117 "marvell,kirkwood",
170 "globalscale,guruplug",
171 "globalscale,sheevaplug",
172 "dlink,dns-320",
173 "dlink,dns-325",
174 "iom,iconnect",
175 "raidsonic,ib-nas62x0",
176 "qnap,ts219",
177 "seagate,dockstar",
178 "seagate,goflexnet",
179 "buffalo,lsxl",
180 "iom,ix2-200",
181 "keymile,km_kirkwood",
182 "lacie,cloudbox",
183 "lacie,inetspace_v2",
184 "lacie,netspace_lite_v2",
185 "lacie,netspace_max_v2",
186 "lacie,netspace_mini_v2",
187 "lacie,netspace_v2",
188 "marvell,db-88f6281-bp",
189 "marvell,db-88f6282-bp",
190 "mpl,cec4",
191 "netgear,readynas-duo-v2",
192 "plathome,openblocks-a6",
193 "usi,topkick",
194 "zyxel,nsa310",
195 NULL 118 NULL
196}; 119};
197 120
198DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)") 121DT_MACHINE_START(KIRKWOOD_DT, "Marvell Kirkwood (Flattened Device Tree)")
199 /* Maintainer: Jason Cooper <jason@lakedaemon.net> */ 122 /* Maintainer: Jason Cooper <jason@lakedaemon.net> */
200 .map_io = kirkwood_map_io, 123 .map_io = kirkwood_map_io,
201 .init_early = kirkwood_init_early, 124 .init_early = kirkwood_dt_init_early,
202 .init_irq = orion_dt_init_irq, 125 .init_time = kirkwood_dt_time_init,
203 .init_time = kirkwood_timer_init,
204 .init_machine = kirkwood_dt_init, 126 .init_machine = kirkwood_dt_init,
205 .restart = kirkwood_restart, 127 .restart = kirkwood_restart,
206 .dt_compat = kirkwood_dt_board_compat, 128 .dt_compat = kirkwood_dt_board_compat,
diff --git a/arch/arm/mach-kirkwood/board-goflexnet.c b/arch/arm/mach-kirkwood/board-goflexnet.c
deleted file mode 100644
index 9db979aec82e..000000000000
--- a/arch/arm/mach-kirkwood/board-goflexnet.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
3 *
4 * arch/arm/mach-kirkwood/board-goflexnet.c
5 *
6 * Seagate GoFlext Net Board Init for drivers not converted to
7 * flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 *
13 * Copied and modified for Seagate GoFlex Net support by
14 * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
15 * GoFlex kernel patches.
16 *
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/mv643xx_eth.h>
22#include "common.h"
23
24static struct mv643xx_eth_platform_data goflexnet_ge00_data = {
25 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
26};
27
28void __init goflexnet_init(void)
29{
30 /*
31 * Basic setup. Needs to be called early.
32 */
33 kirkwood_ge00_init(&goflexnet_ge00_data);
34}
diff --git a/arch/arm/mach-kirkwood/board-guruplug.c b/arch/arm/mach-kirkwood/board-guruplug.c
deleted file mode 100644
index a857163954a5..000000000000
--- a/arch/arm/mach-kirkwood/board-guruplug.c
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/board-guruplug.c
3 *
4 * Marvell Guruplug Reference Board Init for drivers not converted to
5 * flattened device tree yet.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/mv643xx_eth.h>
15#include <linux/gpio.h>
16#include "common.h"
17
18static struct mv643xx_eth_platform_data guruplug_ge00_data = {
19 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
20};
21
22static struct mv643xx_eth_platform_data guruplug_ge01_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
24};
25
26void __init guruplug_dt_init(void)
27{
28 /*
29 * Basic setup. Needs to be called early.
30 */
31 kirkwood_ge00_init(&guruplug_ge00_data);
32 kirkwood_ge01_init(&guruplug_ge01_data);
33}
diff --git a/arch/arm/mach-kirkwood/board-ib62x0.c b/arch/arm/mach-kirkwood/board-ib62x0.c
deleted file mode 100644
index 9a857ae83984..000000000000
--- a/arch/arm/mach-kirkwood/board-ib62x0.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright 2012 (C), Simon Baatz <gmbnomis@gmail.com>
3 *
4 * arch/arm/mach-kirkwood/board-ib62x0.c
5 *
6 * RaidSonic ICY BOX IB-NAS6210 & IB-NAS6220 init for drivers not
7 * converted to flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/mv643xx_eth.h>
17#include "common.h"
18
19static struct mv643xx_eth_platform_data ib62x0_ge00_data = {
20 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
21};
22
23void __init ib62x0_init(void)
24{
25 /*
26 * Basic setup. Needs to be called early.
27 */
28 kirkwood_ge00_init(&ib62x0_ge00_data);
29}
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
deleted file mode 100644
index 98b5ad1bba90..000000000000
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/board-iconnect.c
3 *
4 * Iomega i-connect Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/mv643xx_eth.h>
15#include "common.h"
16
17static struct mv643xx_eth_platform_data iconnect_ge00_data = {
18 .phy_addr = MV643XX_ETH_PHY_ADDR(11),
19};
20
21void __init iconnect_init(void)
22{
23 kirkwood_ge00_init(&iconnect_ge00_data);
24}
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
deleted file mode 100644
index e5f70415905a..000000000000
--- a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+++ /dev/null
@@ -1,34 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
3 *
4 * Iomega StorCenter ix2-200
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mv643xx_eth.h>
14#include <linux/ethtool.h>
15#include "common.h"
16
17static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
18 .phy_addr = MV643XX_ETH_PHY_NONE,
19 .speed = SPEED_1000,
20 .duplex = DUPLEX_FULL,
21};
22
23static struct mv643xx_eth_platform_data iomega_ix2_200_ge01_data = {
24 .phy_addr = MV643XX_ETH_PHY_ADDR(11),
25};
26
27void __init iomega_ix2_200_init(void)
28{
29 /*
30 * Basic setup. Needs to be called early.
31 */
32 kirkwood_ge00_init(&iomega_ix2_200_ge00_data);
33 kirkwood_ge01_init(&iomega_ix2_200_ge01_data);
34}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
deleted file mode 100644
index 44e4605ba0bf..000000000000
--- a/arch/arm/mach-kirkwood/board-km_kirkwood.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * arch/arm/mach-kirkwood/board-km_kirkwood.c
6 *
7 * Keymile km_kirkwood Reference Desing Init for drivers not converted to
8 * flattened device tree yet.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/clk.h>
19#include <linux/clk-private.h>
20#include "common.h"
21
22static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
23 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
24};
25
26void __init km_kirkwood_init(void)
27{
28 struct clk *sata_clk;
29 /*
30 * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
31 * SATA bits (14-15) of the Clock Gating Control Register. Since these
32 * devices are also not present in this variant, their clocks get
33 * disabled because unused when clk_disable_unused() gets called.
34 * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
35 */
36 sata_clk = clk_get_sys("sata_mv.0", "0");
37 if (!IS_ERR(sata_clk))
38 sata_clk->flags |= CLK_IGNORE_UNUSED;
39 sata_clk = clk_get_sys("sata_mv.0", "1");
40 if (!IS_ERR(sata_clk))
41 sata_clk->flags |= CLK_IGNORE_UNUSED;
42
43 kirkwood_ge00_init(&km_kirkwood_ge00_data);
44}
diff --git a/arch/arm/mach-kirkwood/board-lsxl.c b/arch/arm/mach-kirkwood/board-lsxl.c
deleted file mode 100644
index 348395238df6..000000000000
--- a/arch/arm/mach-kirkwood/board-lsxl.c
+++ /dev/null
@@ -1,36 +0,0 @@
1/*
2 * Copyright 2012 (C), Michael Walle <michael@walle.cc>
3 *
4 * arch/arm/mach-kirkwood/board-lsxl.c
5 *
6 * Buffalo Linkstation LS-XHL and LS-CHLv2 init for drivers not
7 * converted to flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mv643xx_eth.h>
18#include "common.h"
19
20static struct mv643xx_eth_platform_data lsxl_ge00_data = {
21 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
22};
23
24static struct mv643xx_eth_platform_data lsxl_ge01_data = {
25 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
26};
27
28void __init lsxl_init(void)
29{
30 /*
31 * Basic setup. Needs to be called early.
32 */
33
34 kirkwood_ge00_init(&lsxl_ge00_data);
35 kirkwood_ge01_init(&lsxl_ge01_data);
36}
diff --git a/arch/arm/mach-kirkwood/board-mplcec4.c b/arch/arm/mach-kirkwood/board-mplcec4.c
deleted file mode 100644
index 938712e248f1..000000000000
--- a/arch/arm/mach-kirkwood/board-mplcec4.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright (C) 2012 MPL AG, Switzerland
3 * Stefan Peter <s.peter@mpl.ch>
4 *
5 * arch/arm/mach-kirkwood/board-mplcec4.c
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/mv643xx_eth.h>
15#include "common.h"
16
17static struct mv643xx_eth_platform_data mplcec4_ge00_data = {
18 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
19};
20
21static struct mv643xx_eth_platform_data mplcec4_ge01_data = {
22 .phy_addr = MV643XX_ETH_PHY_ADDR(2),
23};
24
25void __init mplcec4_init(void)
26{
27 /*
28 * Basic setup. Needs to be called early.
29 */
30 kirkwood_ge00_init(&mplcec4_ge00_data);
31 kirkwood_ge01_init(&mplcec4_ge01_data);
32}
33
34
35
diff --git a/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
new file mode 100644
index 000000000000..ee5eea678c11
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
@@ -0,0 +1,50 @@
1/*
2 * arch/arm/mach-kirkwood/board-mv88f6281gtw_ge.c
3 *
4 * Marvell 88F6281 GTW GE Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/timer.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/ethtool.h>
18#include <linux/gpio.h>
19#include <net/dsa.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/pci.h>
23#include <mach/kirkwood.h>
24#include "common.h"
25
26static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = {
27 .phy_addr = MV643XX_ETH_PHY_NONE,
28 .speed = SPEED_1000,
29 .duplex = DUPLEX_FULL,
30};
31
32static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = {
33 .port_names[0] = "lan1",
34 .port_names[1] = "lan2",
35 .port_names[2] = "lan3",
36 .port_names[3] = "lan4",
37 .port_names[4] = "wan",
38 .port_names[5] = "cpu",
39};
40
41static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = {
42 .nr_chips = 1,
43 .chip = &mv88f6281gtw_ge_switch_chip_data,
44};
45
46void __init mv88f6281gtw_ge_init(void)
47{
48 kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data);
49 kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ);
50}
diff --git a/arch/arm/mach-kirkwood/board-ns2.c b/arch/arm/mach-kirkwood/board-ns2.c
deleted file mode 100644
index f8f660525ace..000000000000
--- a/arch/arm/mach-kirkwood/board-ns2.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Copyright 2012 (C), Simon Guinot <simon.guinot@sequanux.org>
3 *
4 * arch/arm/mach-kirkwood/board-ns2.c
5 *
6 * LaCie Network Space v2 board (and parents) initialization for drivers
7 * not converted to flattened device tree yet.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/platform_device.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/of.h>
19#include "common.h"
20
21static struct mv643xx_eth_platform_data ns2_ge00_data = {
22 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
23};
24
25void __init ns2_init(void)
26{
27 /*
28 * Basic setup. Needs to be called early.
29 */
30 if (of_machine_is_compatible("lacie,cloudbox") ||
31 of_machine_is_compatible("lacie,netspace_lite_v2") ||
32 of_machine_is_compatible("lacie,netspace_mini_v2"))
33 ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
34 kirkwood_ge00_init(&ns2_ge00_data);
35}
diff --git a/arch/arm/mach-kirkwood/board-openblocks_a6.c b/arch/arm/mach-kirkwood/board-openblocks_a6.c
deleted file mode 100644
index b11d8fdeca93..000000000000
--- a/arch/arm/mach-kirkwood/board-openblocks_a6.c
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright 2012 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
3 *
4 * arch/arm/mach-kirkwood/board-openblocks_a6.c
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mv643xx_eth.h>
14#include "common.h"
15
16static struct mv643xx_eth_platform_data openblocks_ge00_data = {
17 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
18};
19
20void __init openblocks_a6_init(void)
21{
22 /*
23 * Basic setup. Needs to be called early.
24 */
25 kirkwood_ge00_init(&openblocks_ge00_data);
26}
diff --git a/arch/arm/mach-kirkwood/board-readynas.c b/arch/arm/mach-kirkwood/board-readynas.c
deleted file mode 100644
index 341b82d9cadb..000000000000
--- a/arch/arm/mach-kirkwood/board-readynas.c
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
3 * converted to DT.
4 *
5 * Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
16#include <linux/mv643xx_eth.h>
17#include <mach/kirkwood.h>
18#include "common.h"
19
20static struct mv643xx_eth_platform_data netgear_readynas_ge00_data = {
21 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
22};
23
24void __init netgear_readynas_init(void)
25{
26 kirkwood_ge00_init(&netgear_readynas_ge00_data);
27}
diff --git a/arch/arm/mach-kirkwood/board-sheevaplug.c b/arch/arm/mach-kirkwood/board-sheevaplug.c
deleted file mode 100644
index fa389373ca74..000000000000
--- a/arch/arm/mach-kirkwood/board-sheevaplug.c
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/board-sheevaplug.c
3 *
4 * Marvell Sheevaplug Reference Board Init for drivers not converted to
5 * flattened device tree yet.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/mv643xx_eth.h>
15#include "common.h"
16
17static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
18 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
19};
20
21void __init sheevaplug_dt_init(void)
22{
23 /*
24 * Basic setup. Needs to be called early.
25 */
26 kirkwood_ge00_init(&sheevaplug_ge00_data);
27}
diff --git a/arch/arm/mach-kirkwood/board-ts219.c b/arch/arm/mach-kirkwood/board-ts219.c
deleted file mode 100644
index 860f44ab457d..000000000000
--- a/arch/arm/mach-kirkwood/board-ts219.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 *
3 * QNAP TS-11x/TS-21x Turbo NAS Board Setup via DT
4 *
5 * Copyright (C) 2012 Andrew Lunn <andrew@lunn.ch>
6 *
7 * Based on the board file ts219-setup.c:
8 *
9 * Copyright (C) 2009 Martin Michlmayr <tbm@cyrius.com>
10 * Copyright (C) 2008 Byron Bradley <byron.bbradley@gmail.com>
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/platform_device.h>
21#include <linux/mv643xx_eth.h>
22#include <asm/mach-types.h>
23#include <asm/mach/arch.h>
24#include <mach/kirkwood.h>
25#include "common.h"
26
27static struct mv643xx_eth_platform_data qnap_ts219_ge00_data = {
28 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
29};
30
31void __init qnap_dt_ts219_init(void)
32{
33 u32 dev, rev;
34
35 kirkwood_pcie_id(&dev, &rev);
36 if (dev == MV88F6282_DEV_ID)
37 qnap_ts219_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
38
39 kirkwood_ge00_init(&qnap_ts219_ge00_data);
40}
diff --git a/arch/arm/mach-kirkwood/board-usi_topkick.c b/arch/arm/mach-kirkwood/board-usi_topkick.c
deleted file mode 100644
index 1cc04ec33f0b..000000000000
--- a/arch/arm/mach-kirkwood/board-usi_topkick.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/*
2 * Copyright 2012 (C), Jason Cooper <jason@lakedaemon.net>
3 *
4 * arch/arm/mach-kirkwood/board-usi_topkick.c
5 *
6 * USI Topkick Init for drivers not converted to flattened device tree yet.
7 *
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/mv643xx_eth.h>
16#include <linux/gpio.h>
17#include "common.h"
18
19static struct mv643xx_eth_platform_data topkick_ge00_data = {
20 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
21};
22
23void __init usi_topkick_init(void)
24{
25 /*
26 * Basic setup. Needs to be called early.
27 */
28 kirkwood_ge00_init(&topkick_ge00_data);
29}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1663de090984..176761134a66 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -37,6 +37,12 @@
37#include <linux/platform_data/dma-mv_xor.h> 37#include <linux/platform_data/dma-mv_xor.h>
38#include "common.h" 38#include "common.h"
39 39
40/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
41#define KIRKWOOD_MBUS_NAND_TARGET 0x01
42#define KIRKWOOD_MBUS_NAND_ATTR 0x2f
43#define KIRKWOOD_MBUS_SRAM_TARGET 0x03
44#define KIRKWOOD_MBUS_SRAM_ATTR 0x01
45
40/***************************************************************************** 46/*****************************************************************************
41 * I/O Address Mapping 47 * I/O Address Mapping
42 ****************************************************************************/ 48 ****************************************************************************/
@@ -528,10 +534,6 @@ void __init kirkwood_cpuidle_init(void)
528void __init kirkwood_init_early(void) 534void __init kirkwood_init_early(void)
529{ 535{
530 orion_time_set_base(TIMER_VIRT_BASE); 536 orion_time_set_base(TIMER_VIRT_BASE);
531
532 mvebu_mbus_init("marvell,kirkwood-mbus",
533 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
534 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ);
535} 537}
536 538
537int kirkwood_tclk; 539int kirkwood_tclk;
@@ -666,10 +668,14 @@ char * __init kirkwood_id(void)
666 668
667void __init kirkwood_setup_wins(void) 669void __init kirkwood_setup_wins(void)
668{ 670{
669 mvebu_mbus_add_window("nand", KIRKWOOD_NAND_MEM_PHYS_BASE, 671 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_NAND_TARGET,
670 KIRKWOOD_NAND_MEM_SIZE); 672 KIRKWOOD_MBUS_NAND_ATTR,
671 mvebu_mbus_add_window("sram", KIRKWOOD_SRAM_PHYS_BASE, 673 KIRKWOOD_NAND_MEM_PHYS_BASE,
672 KIRKWOOD_SRAM_SIZE); 674 KIRKWOOD_NAND_MEM_SIZE);
675 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_SRAM_TARGET,
676 KIRKWOOD_MBUS_SRAM_ATTR,
677 KIRKWOOD_SRAM_PHYS_BASE,
678 KIRKWOOD_SRAM_SIZE);
673} 679}
674 680
675void __init kirkwood_l2_init(void) 681void __init kirkwood_l2_init(void)
@@ -697,6 +703,10 @@ void __init kirkwood_init(void)
697 */ 703 */
698 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG); 704 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
699 705
706 BUG_ON(mvebu_mbus_init("marvell,kirkwood-mbus",
707 BRIDGE_WINS_BASE, BRIDGE_WINS_SZ,
708 DDR_WINDOW_CPU_BASE, DDR_WINDOW_CPU_SZ));
709
700 kirkwood_setup_wins(); 710 kirkwood_setup_wins();
701 711
702 kirkwood_l2_init(); 712 kirkwood_l2_init();
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index fcf3ba682e24..1296de94febf 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -59,119 +59,10 @@ void kirkwood_restart(enum reboot_mode, const char *);
59void kirkwood_clk_init(void); 59void kirkwood_clk_init(void);
60 60
61/* board init functions for boards not fully converted to fdt */ 61/* board init functions for boards not fully converted to fdt */
62#ifdef CONFIG_MACH_DREAMPLUG_DT 62#ifdef CONFIG_MACH_MV88F6281GTW_GE_DT
63void dreamplug_init(void); 63void mv88f6281gtw_ge_init(void);
64#else 64#else
65static inline void dreamplug_init(void) {}; 65static inline void mv88f6281gtw_ge_init(void) {};
66#endif
67#ifdef CONFIG_MACH_GURUPLUG_DT
68void guruplug_dt_init(void);
69#else
70static inline void guruplug_dt_init(void) {};
71#endif
72#ifdef CONFIG_MACH_SHEEVAPLUG_DT
73void sheevaplug_dt_init(void);
74#else
75static inline void sheevaplug_dt_init(void) {};
76#endif
77#ifdef CONFIG_MACH_TS219_DT
78void qnap_dt_ts219_init(void);
79#else
80static inline void qnap_dt_ts219_init(void) {};
81#endif
82
83#ifdef CONFIG_MACH_DLINK_KIRKWOOD_DT
84void dnskw_init(void);
85#else
86static inline void dnskw_init(void) {};
87#endif
88
89#ifdef CONFIG_MACH_ICONNECT_DT
90void iconnect_init(void);
91#else
92static inline void iconnect_init(void) {};
93#endif
94
95#ifdef CONFIG_MACH_IB62X0_DT
96void ib62x0_init(void);
97#else
98static inline void ib62x0_init(void) {};
99#endif
100
101#ifdef CONFIG_MACH_DOCKSTAR_DT
102void dockstar_dt_init(void);
103#else
104static inline void dockstar_dt_init(void) {};
105#endif
106
107#ifdef CONFIG_MACH_GOFLEXNET_DT
108void goflexnet_init(void);
109#else
110static inline void goflexnet_init(void) {};
111#endif
112
113#ifdef CONFIG_MACH_LSXL_DT
114void lsxl_init(void);
115#else
116static inline void lsxl_init(void) {};
117#endif
118
119#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
120void iomega_ix2_200_init(void);
121#else
122static inline void iomega_ix2_200_init(void) {};
123#endif
124
125#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
126void km_kirkwood_init(void);
127#else
128static inline void km_kirkwood_init(void) {};
129#endif
130
131#ifdef CONFIG_MACH_DB88F628X_BP_DT
132void db88f628x_init(void);
133#else
134static inline void db88f628x_init(void) {};
135#endif
136
137#ifdef CONFIG_MACH_MPLCEC4_DT
138void mplcec4_init(void);
139#else
140static inline void mplcec4_init(void) {};
141#endif
142
143#if defined(CONFIG_MACH_INETSPACE_V2_DT) || \
144 defined(CONFIG_MACH_NETSPACE_V2_DT) || \
145 defined(CONFIG_MACH_NETSPACE_MAX_V2_DT) || \
146 defined(CONFIG_MACH_NETSPACE_LITE_V2_DT) || \
147 defined(CONFIG_MACH_NETSPACE_MINI_V2_DT)
148void ns2_init(void);
149#else
150static inline void ns2_init(void) {};
151#endif
152
153#ifdef CONFIG_MACH_OPENBLOCKS_A6_DT
154void openblocks_a6_init(void);
155#else
156static inline void openblocks_a6_init(void) {};
157#endif
158
159#ifdef CONFIG_MACH_READYNAS_DT
160void netgear_readynas_init(void);
161#else
162static inline void netgear_readynas_init(void) {};
163#endif
164
165#ifdef CONFIG_MACH_TOPKICK_DT
166void usi_topkick_init(void);
167#else
168static inline void usi_topkick_init(void) {};
169#endif
170
171#ifdef CONFIG_MACH_CLOUDBOX_DT
172void cloudbox_init(void);
173#else
174static inline void cloudbox_init(void) {};
175#endif 66#endif
176 67
177/* early init functions not converted to fdt yet */ 68/* early init functions not converted to fdt yet */
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
deleted file mode 100644
index 060ccf9cb63f..000000000000
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/dockstar-setup.c
3 *
4 * Seagate FreeAgent DockStar Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/ata_platform.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include <linux/leds.h>
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <mach/kirkwood.h>
22#include "common.h"
23#include "mpp.h"
24
25static struct mtd_partition dockstar_nand_parts[] = {
26 {
27 .name = "u-boot",
28 .offset = 0,
29 .size = SZ_1M
30 }, {
31 .name = "uImage",
32 .offset = MTDPART_OFS_NXTBLK,
33 .size = SZ_4M
34 }, {
35 .name = "root",
36 .offset = MTDPART_OFS_NXTBLK,
37 .size = MTDPART_SIZ_FULL
38 },
39};
40
41static struct mv643xx_eth_platform_data dockstar_ge00_data = {
42 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
43};
44
45static struct gpio_led dockstar_led_pins[] = {
46 {
47 .name = "dockstar:green:health",
48 .default_trigger = "default-on",
49 .gpio = 46,
50 .active_low = 1,
51 },
52 {
53 .name = "dockstar:orange:misc",
54 .default_trigger = "none",
55 .gpio = 47,
56 .active_low = 1,
57 },
58};
59
60static struct gpio_led_platform_data dockstar_led_data = {
61 .leds = dockstar_led_pins,
62 .num_leds = ARRAY_SIZE(dockstar_led_pins),
63};
64
65static struct platform_device dockstar_leds = {
66 .name = "leds-gpio",
67 .id = -1,
68 .dev = {
69 .platform_data = &dockstar_led_data,
70 }
71};
72
73static unsigned int dockstar_mpp_config[] __initdata = {
74 MPP29_GPIO, /* USB Power Enable */
75 MPP46_GPIO, /* LED green */
76 MPP47_GPIO, /* LED orange */
77 0
78};
79
80static void __init dockstar_init(void)
81{
82 /*
83 * Basic setup. Needs to be called early.
84 */
85 kirkwood_init();
86
87 /* setup gpio pin select */
88 kirkwood_mpp_conf(dockstar_mpp_config);
89
90 kirkwood_uart0_init();
91 kirkwood_nand_init(ARRAY_AND_SIZE(dockstar_nand_parts), 25);
92
93 if (gpio_request(29, "USB Power Enable") != 0 ||
94 gpio_direction_output(29, 1) != 0)
95 pr_err("can't set up GPIO 29 (USB Power Enable)\n");
96 kirkwood_ehci_init();
97
98 kirkwood_ge00_init(&dockstar_ge00_data);
99
100 platform_device_register(&dockstar_leds);
101}
102
103MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
104 .atag_offset = 0x100,
105 .init_machine = dockstar_init,
106 .map_io = kirkwood_map_io,
107 .init_early = kirkwood_init_early,
108 .init_irq = kirkwood_init_irq,
109 .init_time = kirkwood_timer_init,
110 .restart = kirkwood_restart,
111MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
deleted file mode 100644
index 08dd739aa709..000000000000
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ /dev/null
@@ -1,133 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/guruplug-setup.c
3 *
4 * Marvell GuruPlug Reference Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/partitions.h>
15#include <linux/ata_platform.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include <linux/leds.h>
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <mach/kirkwood.h>
22#include <linux/platform_data/mmc-mvsdio.h>
23#include "common.h"
24#include "mpp.h"
25
26static struct mtd_partition guruplug_nand_parts[] = {
27 {
28 .name = "u-boot",
29 .offset = 0,
30 .size = SZ_1M
31 }, {
32 .name = "uImage",
33 .offset = MTDPART_OFS_NXTBLK,
34 .size = SZ_4M
35 }, {
36 .name = "root",
37 .offset = MTDPART_OFS_NXTBLK,
38 .size = MTDPART_SIZ_FULL
39 },
40};
41
42static struct mv643xx_eth_platform_data guruplug_ge00_data = {
43 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
44};
45
46static struct mv643xx_eth_platform_data guruplug_ge01_data = {
47 .phy_addr = MV643XX_ETH_PHY_ADDR(1),
48};
49
50static struct mv_sata_platform_data guruplug_sata_data = {
51 .n_ports = 1,
52};
53
54static struct mvsdio_platform_data guruplug_mvsdio_data = {
55 /* unfortunately the CD signal has not been connected */
56 .gpio_card_detect = -1,
57 .gpio_write_protect = -1,
58};
59
60static struct gpio_led guruplug_led_pins[] = {
61 {
62 .name = "guruplug:red:health",
63 .gpio = 46,
64 .active_low = 1,
65 },
66 {
67 .name = "guruplug:green:health",
68 .gpio = 47,
69 .active_low = 1,
70 },
71 {
72 .name = "guruplug:red:wmode",
73 .gpio = 48,
74 .active_low = 1,
75 },
76 {
77 .name = "guruplug:green:wmode",
78 .gpio = 49,
79 .active_low = 1,
80 },
81};
82
83static struct gpio_led_platform_data guruplug_led_data = {
84 .leds = guruplug_led_pins,
85 .num_leds = ARRAY_SIZE(guruplug_led_pins),
86};
87
88static struct platform_device guruplug_leds = {
89 .name = "leds-gpio",
90 .id = -1,
91 .dev = {
92 .platform_data = &guruplug_led_data,
93 }
94};
95
96static unsigned int guruplug_mpp_config[] __initdata = {
97 MPP46_GPIO, /* M_RLED */
98 MPP47_GPIO, /* M_GLED */
99 MPP48_GPIO, /* B_RLED */
100 MPP49_GPIO, /* B_GLED */
101 0
102};
103
104static void __init guruplug_init(void)
105{
106 /*
107 * Basic setup. Needs to be called early.
108 */
109 kirkwood_init();
110 kirkwood_mpp_conf(guruplug_mpp_config);
111
112 kirkwood_uart0_init();
113 kirkwood_nand_init(ARRAY_AND_SIZE(guruplug_nand_parts), 25);
114
115 kirkwood_ehci_init();
116 kirkwood_ge00_init(&guruplug_ge00_data);
117 kirkwood_ge01_init(&guruplug_ge01_data);
118 kirkwood_sata_init(&guruplug_sata_data);
119 kirkwood_sdio_init(&guruplug_mvsdio_data);
120
121 platform_device_register(&guruplug_leds);
122}
123
124MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
125 /* Maintainer: Siddarth Gore <gores@marvell.com> */
126 .atag_offset = 0x100,
127 .init_machine = guruplug_init,
128 .map_io = kirkwood_map_io,
129 .init_early = kirkwood_init_early,
130 .init_irq = kirkwood_init_irq,
131 .init_time = kirkwood_timer_init,
132 .restart = kirkwood_restart,
133MACHINE_END
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
deleted file mode 100644
index ba384b992bef..000000000000
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ /dev/null
@@ -1,172 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
3 *
4 * Marvell 88F6281 GTW GE Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/timer.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/ethtool.h>
20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
23#include <linux/gpio_keys.h>
24#include <linux/spi/flash.h>
25#include <linux/spi/spi.h>
26#include <net/dsa.h>
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/pci.h>
30#include <mach/kirkwood.h>
31#include "common.h"
32#include "mpp.h"
33
34static struct mv643xx_eth_platform_data mv88f6281gtw_ge_ge00_data = {
35 .phy_addr = MV643XX_ETH_PHY_NONE,
36 .speed = SPEED_1000,
37 .duplex = DUPLEX_FULL,
38};
39
40static struct dsa_chip_data mv88f6281gtw_ge_switch_chip_data = {
41 .port_names[0] = "lan1",
42 .port_names[1] = "lan2",
43 .port_names[2] = "lan3",
44 .port_names[3] = "lan4",
45 .port_names[4] = "wan",
46 .port_names[5] = "cpu",
47};
48
49static struct dsa_platform_data mv88f6281gtw_ge_switch_plat_data = {
50 .nr_chips = 1,
51 .chip = &mv88f6281gtw_ge_switch_chip_data,
52};
53
54static const struct flash_platform_data mv88f6281gtw_ge_spi_slave_data = {
55 .type = "mx25l12805d",
56};
57
58static struct spi_board_info __initdata mv88f6281gtw_ge_spi_slave_info[] = {
59 {
60 .modalias = "m25p80",
61 .platform_data = &mv88f6281gtw_ge_spi_slave_data,
62 .irq = -1,
63 .max_speed_hz = 50000000,
64 .bus_num = 0,
65 .chip_select = 0,
66 },
67};
68
69static struct gpio_keys_button mv88f6281gtw_ge_button_pins[] = {
70 {
71 .code = KEY_RESTART,
72 .gpio = 47,
73 .desc = "SWR Button",
74 .active_low = 1,
75 }, {
76 .code = KEY_WPS_BUTTON,
77 .gpio = 46,
78 .desc = "WPS Button",
79 .active_low = 1,
80 },
81};
82
83static struct gpio_keys_platform_data mv88f6281gtw_ge_button_data = {
84 .buttons = mv88f6281gtw_ge_button_pins,
85 .nbuttons = ARRAY_SIZE(mv88f6281gtw_ge_button_pins),
86};
87
88static struct platform_device mv88f6281gtw_ge_buttons = {
89 .name = "gpio-keys",
90 .id = -1,
91 .num_resources = 0,
92 .dev = {
93 .platform_data = &mv88f6281gtw_ge_button_data,
94 },
95};
96
97static struct gpio_led mv88f6281gtw_ge_led_pins[] = {
98 {
99 .name = "gtw:green:Status",
100 .gpio = 20,
101 .active_low = 0,
102 }, {
103 .name = "gtw:red:Status",
104 .gpio = 21,
105 .active_low = 0,
106 }, {
107 .name = "gtw:green:USB",
108 .gpio = 12,
109 .active_low = 0,
110 },
111};
112
113static struct gpio_led_platform_data mv88f6281gtw_ge_led_data = {
114 .leds = mv88f6281gtw_ge_led_pins,
115 .num_leds = ARRAY_SIZE(mv88f6281gtw_ge_led_pins),
116};
117
118static struct platform_device mv88f6281gtw_ge_leds = {
119 .name = "leds-gpio",
120 .id = -1,
121 .dev = {
122 .platform_data = &mv88f6281gtw_ge_led_data,
123 },
124};
125
126static unsigned int mv88f6281gtw_ge_mpp_config[] __initdata = {
127 MPP12_GPO, /* Status#_USB pin */
128 MPP20_GPIO, /* Status#_GLED pin */
129 MPP21_GPIO, /* Status#_RLED pin */
130 MPP46_GPIO, /* WPS_Switch pin */
131 MPP47_GPIO, /* SW_Init pin */
132 0
133};
134
135static void __init mv88f6281gtw_ge_init(void)
136{
137 /*
138 * Basic setup. Needs to be called early.
139 */
140 kirkwood_init();
141 kirkwood_mpp_conf(mv88f6281gtw_ge_mpp_config);
142
143 kirkwood_ehci_init();
144 kirkwood_ge00_init(&mv88f6281gtw_ge_ge00_data);
145 kirkwood_ge00_switch_init(&mv88f6281gtw_ge_switch_plat_data, NO_IRQ);
146 spi_register_board_info(mv88f6281gtw_ge_spi_slave_info,
147 ARRAY_SIZE(mv88f6281gtw_ge_spi_slave_info));
148 kirkwood_spi_init();
149 kirkwood_uart0_init();
150 platform_device_register(&mv88f6281gtw_ge_leds);
151 platform_device_register(&mv88f6281gtw_ge_buttons);
152}
153
154static int __init mv88f6281gtw_ge_pci_init(void)
155{
156 if (machine_is_mv88f6281gtw_ge())
157 kirkwood_pcie_init(KW_PCIE0);
158
159 return 0;
160}
161subsys_initcall(mv88f6281gtw_ge_pci_init);
162
163MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
164 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
165 .atag_offset = 0x100,
166 .init_machine = mv88f6281gtw_ge_init,
167 .map_io = kirkwood_map_io,
168 .init_early = kirkwood_init_early,
169 .init_irq = kirkwood_init_irq,
170 .init_time = kirkwood_timer_init,
171 .restart = kirkwood_restart,
172MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
deleted file mode 100644
index 3b706611da8e..000000000000
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ /dev/null
@@ -1,293 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/netspace_v2-setup.c
3 *
4 * LaCie Network Space v2 board setup
5 *
6 * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
7 * Copyright (C) 2009 Benoît Canet <benoit.canet@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#include <linux/kernel.h>
25#include <linux/init.h>
26#include <linux/platform_device.h>
27#include <linux/ata_platform.h>
28#include <linux/mv643xx_eth.h>
29#include <linux/input.h>
30#include <linux/gpio.h>
31#include <linux/gpio_keys.h>
32#include <linux/leds.h>
33#include <linux/gpio-fan.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <mach/kirkwood.h>
37#include <linux/platform_data/leds-kirkwood-ns2.h>
38#include "common.h"
39#include "mpp.h"
40#include "lacie_v2-common.h"
41
42/*****************************************************************************
43 * Ethernet
44 ****************************************************************************/
45
46static struct mv643xx_eth_platform_data netspace_v2_ge00_data = {
47 .phy_addr = MV643XX_ETH_PHY_ADDR(8),
48};
49
50/*****************************************************************************
51 * SATA
52 ****************************************************************************/
53
54static struct mv_sata_platform_data netspace_v2_sata_data = {
55 .n_ports = 2,
56};
57
58/*****************************************************************************
59 * GPIO keys
60 ****************************************************************************/
61
62#define NETSPACE_V2_PUSH_BUTTON 32
63
64static struct gpio_keys_button netspace_v2_buttons[] = {
65 [0] = {
66 .code = KEY_POWER,
67 .gpio = NETSPACE_V2_PUSH_BUTTON,
68 .desc = "Power push button",
69 .active_low = 0,
70 },
71};
72
73static struct gpio_keys_platform_data netspace_v2_button_data = {
74 .buttons = netspace_v2_buttons,
75 .nbuttons = ARRAY_SIZE(netspace_v2_buttons),
76};
77
78static struct platform_device netspace_v2_gpio_buttons = {
79 .name = "gpio-keys",
80 .id = -1,
81 .dev = {
82 .platform_data = &netspace_v2_button_data,
83 },
84};
85
86/*****************************************************************************
87 * GPIO LEDs
88 ****************************************************************************/
89
90#define NETSPACE_V2_GPIO_RED_LED 12
91
92static struct gpio_led netspace_v2_gpio_led_pins[] = {
93 {
94 .name = "ns_v2:red:fail",
95 .gpio = NETSPACE_V2_GPIO_RED_LED,
96 },
97};
98
99static struct gpio_led_platform_data netspace_v2_gpio_leds_data = {
100 .num_leds = ARRAY_SIZE(netspace_v2_gpio_led_pins),
101 .leds = netspace_v2_gpio_led_pins,
102};
103
104static struct platform_device netspace_v2_gpio_leds = {
105 .name = "leds-gpio",
106 .id = -1,
107 .dev = {
108 .platform_data = &netspace_v2_gpio_leds_data,
109 },
110};
111
112/*****************************************************************************
113 * Dual-GPIO CPLD LEDs
114 ****************************************************************************/
115
116#define NETSPACE_V2_GPIO_BLUE_LED_SLOW 29
117#define NETSPACE_V2_GPIO_BLUE_LED_CMD 30
118
119static struct ns2_led netspace_v2_led_pins[] = {
120 {
121 .name = "ns_v2:blue:sata",
122 .cmd = NETSPACE_V2_GPIO_BLUE_LED_CMD,
123 .slow = NETSPACE_V2_GPIO_BLUE_LED_SLOW,
124 },
125};
126
127static struct ns2_led_platform_data netspace_v2_leds_data = {
128 .num_leds = ARRAY_SIZE(netspace_v2_led_pins),
129 .leds = netspace_v2_led_pins,
130};
131
132static struct platform_device netspace_v2_leds = {
133 .name = "leds-ns2",
134 .id = -1,
135 .dev = {
136 .platform_data = &netspace_v2_leds_data,
137 },
138};
139
140/*****************************************************************************
141 * GPIO fan
142 ****************************************************************************/
143
144/* Designed for fan 40x40x16: ADDA AD0412LB-D50 6000rpm@12v */
145static struct gpio_fan_speed netspace_max_v2_fan_speed[] = {
146 { 0, 0 },
147 { 1500, 15 },
148 { 1700, 14 },
149 { 1800, 13 },
150 { 2100, 12 },
151 { 3100, 11 },
152 { 3300, 10 },
153 { 4300, 9 },
154 { 5500, 8 },
155};
156
157static unsigned netspace_max_v2_fan_ctrl[] = { 22, 7, 33, 23 };
158
159static struct gpio_fan_alarm netspace_max_v2_fan_alarm = {
160 .gpio = 25,
161 .active_low = 1,
162};
163
164static struct gpio_fan_platform_data netspace_max_v2_fan_data = {
165 .num_ctrl = ARRAY_SIZE(netspace_max_v2_fan_ctrl),
166 .ctrl = netspace_max_v2_fan_ctrl,
167 .alarm = &netspace_max_v2_fan_alarm,
168 .num_speed = ARRAY_SIZE(netspace_max_v2_fan_speed),
169 .speed = netspace_max_v2_fan_speed,
170};
171
172static struct platform_device netspace_max_v2_gpio_fan = {
173 .name = "gpio-fan",
174 .id = -1,
175 .dev = {
176 .platform_data = &netspace_max_v2_fan_data,
177 },
178};
179
180/*****************************************************************************
181 * General Setup
182 ****************************************************************************/
183
184static unsigned int netspace_v2_mpp_config[] __initdata = {
185 MPP0_SPI_SCn,
186 MPP1_SPI_MOSI,
187 MPP2_SPI_SCK,
188 MPP3_SPI_MISO,
189 MPP4_NF_IO6,
190 MPP5_NF_IO7,
191 MPP6_SYSRST_OUTn,
192 MPP7_GPO, /* Fan speed (bit 1) */
193 MPP8_TW0_SDA,
194 MPP9_TW0_SCK,
195 MPP10_UART0_TXD,
196 MPP11_UART0_RXD,
197 MPP12_GPO, /* Red led */
198 MPP14_GPIO, /* USB fuse */
199 MPP16_GPIO, /* SATA 0 power */
200 MPP17_GPIO, /* SATA 1 power */
201 MPP18_NF_IO0,
202 MPP19_NF_IO1,
203 MPP20_SATA1_ACTn,
204 MPP21_SATA0_ACTn,
205 MPP22_GPIO, /* Fan speed (bit 0) */
206 MPP23_GPIO, /* Fan power */
207 MPP24_GPIO, /* USB mode select */
208 MPP25_GPIO, /* Fan rotation fail */
209 MPP26_GPIO, /* USB device vbus */
210 MPP28_GPIO, /* USB enable host vbus */
211 MPP29_GPIO, /* Blue led (slow register) */
212 MPP30_GPIO, /* Blue led (command register) */
213 MPP31_GPIO, /* Board power off */
214 MPP32_GPIO, /* Power button (0 = Released, 1 = Pushed) */
215 MPP33_GPO, /* Fan speed (bit 2) */
216 0
217};
218
219#define NETSPACE_V2_GPIO_POWER_OFF 31
220
221static void netspace_v2_power_off(void)
222{
223 gpio_set_value(NETSPACE_V2_GPIO_POWER_OFF, 1);
224}
225
226static void __init netspace_v2_init(void)
227{
228 /*
229 * Basic setup. Needs to be called early.
230 */
231 kirkwood_init();
232 kirkwood_mpp_conf(netspace_v2_mpp_config);
233
234 if (machine_is_netspace_max_v2())
235 lacie_v2_hdd_power_init(2);
236 else
237 lacie_v2_hdd_power_init(1);
238
239 kirkwood_ehci_init();
240 kirkwood_ge00_init(&netspace_v2_ge00_data);
241 kirkwood_sata_init(&netspace_v2_sata_data);
242 kirkwood_uart0_init();
243 lacie_v2_register_flash();
244 lacie_v2_register_i2c_devices();
245
246 platform_device_register(&netspace_v2_leds);
247 platform_device_register(&netspace_v2_gpio_leds);
248 platform_device_register(&netspace_v2_gpio_buttons);
249 if (machine_is_netspace_max_v2())
250 platform_device_register(&netspace_max_v2_gpio_fan);
251
252 if (gpio_request(NETSPACE_V2_GPIO_POWER_OFF, "power-off") == 0 &&
253 gpio_direction_output(NETSPACE_V2_GPIO_POWER_OFF, 0) == 0)
254 pm_power_off = netspace_v2_power_off;
255 else
256 pr_err("netspace_v2: failed to configure power-off GPIO\n");
257}
258
259#ifdef CONFIG_MACH_NETSPACE_V2
260MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
261 .atag_offset = 0x100,
262 .init_machine = netspace_v2_init,
263 .map_io = kirkwood_map_io,
264 .init_early = kirkwood_init_early,
265 .init_irq = kirkwood_init_irq,
266 .init_time = kirkwood_timer_init,
267 .restart = kirkwood_restart,
268MACHINE_END
269#endif
270
271#ifdef CONFIG_MACH_INETSPACE_V2
272MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
273 .atag_offset = 0x100,
274 .init_machine = netspace_v2_init,
275 .map_io = kirkwood_map_io,
276 .init_early = kirkwood_init_early,
277 .init_irq = kirkwood_init_irq,
278 .init_time = kirkwood_timer_init,
279 .restart = kirkwood_restart,
280MACHINE_END
281#endif
282
283#ifdef CONFIG_MACH_NETSPACE_MAX_V2
284MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
285 .atag_offset = 0x100,
286 .init_machine = netspace_v2_init,
287 .map_io = kirkwood_map_io,
288 .init_early = kirkwood_init_early,
289 .init_irq = kirkwood_init_irq,
290 .init_time = kirkwood_timer_init,
291 .restart = kirkwood_restart,
292MACHINE_END
293#endif
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index 6a6eb548307d..e5cf84103583 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -158,7 +158,8 @@ static void __init openrd_init(void)
158 kirkwood_mpp_conf(openrd_mpp_config); 158 kirkwood_mpp_conf(openrd_mpp_config);
159 159
160 kirkwood_uart0_init(); 160 kirkwood_uart0_init();
161 kirkwood_nand_init(ARRAY_AND_SIZE(openrd_nand_parts), 25); 161 kirkwood_nand_init(openrd_nand_parts, ARRAY_SIZE(openrd_nand_parts),
162 25);
162 163
163 kirkwood_ehci_init(); 164 kirkwood_ehci_init();
164 165
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ddcb09f5bdd3..12d86f39f380 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -20,6 +20,16 @@
20#include <mach/bridge-regs.h> 20#include <mach/bridge-regs.h>
21#include "common.h" 21#include "common.h"
22 22
23/* These can go away once Kirkwood uses the mvebu-mbus DT binding */
24#define KIRKWOOD_MBUS_PCIE0_MEM_TARGET 0x4
25#define KIRKWOOD_MBUS_PCIE0_MEM_ATTR 0xe8
26#define KIRKWOOD_MBUS_PCIE0_IO_TARGET 0x4
27#define KIRKWOOD_MBUS_PCIE0_IO_ATTR 0xe0
28#define KIRKWOOD_MBUS_PCIE1_MEM_TARGET 0x4
29#define KIRKWOOD_MBUS_PCIE1_MEM_ATTR 0xd8
30#define KIRKWOOD_MBUS_PCIE1_IO_TARGET 0x4
31#define KIRKWOOD_MBUS_PCIE1_IO_ATTR 0xd0
32
23static void kirkwood_enable_pcie_clk(const char *port) 33static void kirkwood_enable_pcie_clk(const char *port)
24{ 34{
25 struct clk *clk; 35 struct clk *clk;
@@ -254,26 +264,24 @@ static void __init add_pcie_port(int index, void __iomem *base)
254 264
255void __init kirkwood_pcie_init(unsigned int portmask) 265void __init kirkwood_pcie_init(unsigned int portmask)
256{ 266{
257 mvebu_mbus_add_window_remap_flags("pcie0.0", 267 mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE0_IO_TARGET,
268 KIRKWOOD_MBUS_PCIE0_IO_ATTR,
258 KIRKWOOD_PCIE_IO_PHYS_BASE, 269 KIRKWOOD_PCIE_IO_PHYS_BASE,
259 KIRKWOOD_PCIE_IO_SIZE, 270 KIRKWOOD_PCIE_IO_SIZE,
260 KIRKWOOD_PCIE_IO_BUS_BASE, 271 KIRKWOOD_PCIE_IO_BUS_BASE);
261 MVEBU_MBUS_PCI_IO); 272 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE0_MEM_TARGET,
262 mvebu_mbus_add_window_remap_flags("pcie0.0", 273 KIRKWOOD_MBUS_PCIE0_MEM_ATTR,
263 KIRKWOOD_PCIE_MEM_PHYS_BASE, 274 KIRKWOOD_PCIE_MEM_PHYS_BASE,
264 KIRKWOOD_PCIE_MEM_SIZE, 275 KIRKWOOD_PCIE_MEM_SIZE);
265 MVEBU_MBUS_NO_REMAP, 276 mvebu_mbus_add_window_remap_by_id(KIRKWOOD_MBUS_PCIE1_IO_TARGET,
266 MVEBU_MBUS_PCI_MEM); 277 KIRKWOOD_MBUS_PCIE1_IO_ATTR,
267 mvebu_mbus_add_window_remap_flags("pcie1.0",
268 KIRKWOOD_PCIE1_IO_PHYS_BASE, 278 KIRKWOOD_PCIE1_IO_PHYS_BASE,
269 KIRKWOOD_PCIE1_IO_SIZE, 279 KIRKWOOD_PCIE1_IO_SIZE,
270 KIRKWOOD_PCIE1_IO_BUS_BASE, 280 KIRKWOOD_PCIE1_IO_BUS_BASE);
271 MVEBU_MBUS_PCI_IO); 281 mvebu_mbus_add_window_by_id(KIRKWOOD_MBUS_PCIE1_MEM_TARGET,
272 mvebu_mbus_add_window_remap_flags("pcie1.0", 282 KIRKWOOD_MBUS_PCIE1_MEM_ATTR,
273 KIRKWOOD_PCIE1_MEM_PHYS_BASE, 283 KIRKWOOD_PCIE1_MEM_PHYS_BASE,
274 KIRKWOOD_PCIE1_MEM_SIZE, 284 KIRKWOOD_PCIE1_MEM_SIZE);
275 MVEBU_MBUS_NO_REMAP,
276 MVEBU_MBUS_PCI_MEM);
277 285
278 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE; 286 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
279 287
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index d24223166e06..5154bd2a3ad3 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -87,7 +87,9 @@ static void __init rd88f6281_init(void)
87 kirkwood_init(); 87 kirkwood_init();
88 kirkwood_mpp_conf(rd88f6281_mpp_config); 88 kirkwood_mpp_conf(rd88f6281_mpp_config);
89 89
90 kirkwood_nand_init(ARRAY_AND_SIZE(rd88f6281_nand_parts), 25); 90 kirkwood_nand_init(rd88f6281_nand_parts,
91 ARRAY_SIZE(rd88f6281_nand_parts),
92 25);
91 kirkwood_ehci_init(); 93 kirkwood_ehci_init();
92 94
93 kirkwood_ge00_init(&rd88f6281_ge00_data); 95 kirkwood_ge00_init(&rd88f6281_ge00_data);
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
deleted file mode 100644
index 55b68fa39f45..000000000000
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ /dev/null
@@ -1,161 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/sheevaplug-setup.c
3 *
4 * Marvell SheevaPlug Reference Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/ata_platform.h>
15#include <linux/mtd/partitions.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/gpio.h>
18#include <linux/leds.h>
19#include <asm/mach-types.h>
20#include <asm/mach/arch.h>
21#include <mach/kirkwood.h>
22#include <linux/platform_data/mmc-mvsdio.h>
23#include "common.h"
24#include "mpp.h"
25
26static struct mtd_partition sheevaplug_nand_parts[] = {
27 {
28 .name = "u-boot",
29 .offset = 0,
30 .size = SZ_1M
31 }, {
32 .name = "uImage",
33 .offset = MTDPART_OFS_NXTBLK,
34 .size = SZ_4M
35 }, {
36 .name = "root",
37 .offset = MTDPART_OFS_NXTBLK,
38 .size = MTDPART_SIZ_FULL
39 },
40};
41
42static struct mv643xx_eth_platform_data sheevaplug_ge00_data = {
43 .phy_addr = MV643XX_ETH_PHY_ADDR(0),
44};
45
46static struct mv_sata_platform_data sheeva_esata_sata_data = {
47 .n_ports = 2,
48};
49
50static struct mvsdio_platform_data sheevaplug_mvsdio_data = {
51 /* unfortunately the CD signal has not been connected */
52};
53
54static struct mvsdio_platform_data sheeva_esata_mvsdio_data = {
55 .gpio_write_protect = 44, /* MPP44 used as SD write protect */
56 .gpio_card_detect = 47, /* MPP47 used as SD card detect */
57};
58
59static struct gpio_led sheevaplug_led_pins[] = {
60 {
61 .name = "plug:red:misc",
62 .default_trigger = "none",
63 .gpio = 46,
64 .active_low = 1,
65 },
66 {
67 .name = "plug:green:health",
68 .default_trigger = "default-on",
69 .gpio = 49,
70 .active_low = 1,
71 },
72};
73
74static struct gpio_led_platform_data sheevaplug_led_data = {
75 .leds = sheevaplug_led_pins,
76 .num_leds = ARRAY_SIZE(sheevaplug_led_pins),
77};
78
79static struct platform_device sheevaplug_leds = {
80 .name = "leds-gpio",
81 .id = -1,
82 .dev = {
83 .platform_data = &sheevaplug_led_data,
84 }
85};
86
87static unsigned int sheevaplug_mpp_config[] __initdata = {
88 MPP29_GPIO, /* USB Power Enable */
89 MPP46_GPIO, /* LED Red */
90 MPP49_GPIO, /* LED */
91 0
92};
93
94static unsigned int sheeva_esata_mpp_config[] __initdata = {
95 MPP29_GPIO, /* USB Power Enable */
96 MPP44_GPIO, /* SD Write Protect */
97 MPP47_GPIO, /* SD Card Detect */
98 MPP49_GPIO, /* LED Green */
99 0
100};
101
102static void __init sheevaplug_init(void)
103{
104 /*
105 * Basic setup. Needs to be called early.
106 */
107 kirkwood_init();
108
109 /* setup gpio pin select */
110 if (machine_is_esata_sheevaplug())
111 kirkwood_mpp_conf(sheeva_esata_mpp_config);
112 else
113 kirkwood_mpp_conf(sheevaplug_mpp_config);
114
115 kirkwood_uart0_init();
116 kirkwood_nand_init(ARRAY_AND_SIZE(sheevaplug_nand_parts), 25);
117
118 if (gpio_request(29, "USB Power Enable") != 0 ||
119 gpio_direction_output(29, 1) != 0)
120 pr_err("can't set up GPIO 29 (USB Power Enable)\n");
121 kirkwood_ehci_init();
122
123 kirkwood_ge00_init(&sheevaplug_ge00_data);
124
125 /* honor lower power consumption for plugs with out eSATA */
126 if (machine_is_esata_sheevaplug())
127 kirkwood_sata_init(&sheeva_esata_sata_data);
128
129 /* enable sd wp and sd cd on plugs with esata */
130 if (machine_is_esata_sheevaplug())
131 kirkwood_sdio_init(&sheeva_esata_mvsdio_data);
132 else
133 kirkwood_sdio_init(&sheevaplug_mvsdio_data);
134
135 platform_device_register(&sheevaplug_leds);
136}
137
138#ifdef CONFIG_MACH_SHEEVAPLUG
139MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
140 /* Maintainer: shadi Ammouri <shadi@marvell.com> */
141 .atag_offset = 0x100,
142 .init_machine = sheevaplug_init,
143 .map_io = kirkwood_map_io,
144 .init_early = kirkwood_init_early,
145 .init_irq = kirkwood_init_irq,
146 .init_time = kirkwood_timer_init,
147 .restart = kirkwood_restart,
148MACHINE_END
149#endif
150
151#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
152MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
153 .atag_offset = 0x100,
154 .init_machine = sheevaplug_init,
155 .map_io = kirkwood_map_io,
156 .init_early = kirkwood_init_early,
157 .init_irq = kirkwood_init_irq,
158 .init_time = kirkwood_timer_init,
159 .restart = kirkwood_restart,
160MACHINE_END
161#endif
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 456d6386edf8..9f9c0441a917 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -20,7 +20,7 @@
20#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/i2c-algo-bit.h> 21#include <linux/i2c-algo-bit.h>
22#include <linux/i2c-gpio.h> 22#include <linux/i2c-gpio.h>
23#include <linux/i2c/pca953x.h> 23#include <linux/platform_data/pca953x.h>
24 24
25#include <linux/mtd/mtd.h> 25#include <linux/mtd/mtd.h>
26#include <linux/mtd/map.h> 26#include <linux/mtd/map.h>
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155d6fb8..9b702a1dc7b0 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
2# Makefile for Marvell's PXA168 processors line 2# Makefile for Marvell's PXA168 processors line
3# 3#
4 4
5obj-y += common.o devices.o time.o irq.o 5obj-y += common.o devices.o time.o
6 6
7# SoC support 7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o 8obj-$(CONFIG_CPU_PXA168) += pxa168.o
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 991d7e9877de..cf445bae6d77 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -3,7 +3,6 @@
3 3
4extern void timer_init(int irq); 4extern void timer_init(int irq);
5 5
6extern void __init icu_init_irq(void);
7extern void __init mmp_map_io(void); 6extern void __init mmp_map_io(void);
8extern void mmp_restart(enum reboot_mode, const char *); 7extern void mmp_restart(enum reboot_mode, const char *);
9extern void __init pxa168_clk_init(void); 8extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
deleted file mode 100644
index bd152e24e6d7..000000000000
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <asm/irq.h>
10#include <mach/regs-icu.h>
11
12 .macro get_irqnr_preamble, base, tmp
13 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
14 and \tmp, \tmp, #0xff00
15 cmp \tmp, #0x5800
16 ldr \base, =mmp_icu_base
17 ldr \base, [\base, #0]
18 addne \base, \base, #0x10c @ PJ1 AP INT SEL register
19 addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 ldr \tmp, [\base, #0]
24 and \irqnr, \tmp, #0x3f
25 tst \tmp, #(1 << 6)
26 .endm
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 459c2d03eb5c..a83ba7cb525d 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -4,6 +4,7 @@
4#include <linux/reboot.h> 4#include <linux/reboot.h>
5 5
6extern void pxa168_timer_init(void); 6extern void pxa168_timer_init(void);
7extern void __init icu_init_irq(void);
7extern void __init pxa168_init_irq(void); 8extern void __init pxa168_init_irq(void);
8extern void pxa168_restart(enum reboot_mode, const char *); 9extern void pxa168_restart(enum reboot_mode, const char *);
9extern void pxa168_clear_keypad_wakeup(void); 10extern void pxa168_clear_keypad_wakeup(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b914afa1fcdc..92253203f5b4 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -2,6 +2,7 @@
2#define __ASM_MACH_PXA910_H 2#define __ASM_MACH_PXA910_H
3 3
4extern void pxa910_timer_init(void); 4extern void pxa910_timer_init(void);
5extern void __init icu_init_irq(void);
5extern void __init pxa910_init_irq(void); 6extern void __init pxa910_init_irq(void);
6 7
7#include <linux/i2c.h> 8#include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/irq.c b/arch/arm/mach-mmp/irq.c
deleted file mode 100644
index 3c71246cd994..000000000000
--- a/arch/arm/mach-mmp/irq.c
+++ /dev/null
@@ -1,463 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/irq.c
3 *
4 * Generic IRQ handling, GPIO IRQ demultiplexing, etc.
5 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd.
6 *
7 * Author: Bin Yang <bin.yang@marvell.com>
8 * Haojian Zhuang <haojian.zhuang@gmail.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/io.h>
20#include <linux/ioport.h>
21#include <linux/of_address.h>
22#include <linux/of_irq.h>
23
24#include <mach/irqs.h>
25
26#ifdef CONFIG_CPU_MMP2
27#include <mach/pm-mmp2.h>
28#endif
29#ifdef CONFIG_CPU_PXA910
30#include <mach/pm-pxa910.h>
31#endif
32
33#include "common.h"
34
35#define MAX_ICU_NR 16
36
37struct icu_chip_data {
38 int nr_irqs;
39 unsigned int virq_base;
40 unsigned int cascade_irq;
41 void __iomem *reg_status;
42 void __iomem *reg_mask;
43 unsigned int conf_enable;
44 unsigned int conf_disable;
45 unsigned int conf_mask;
46 unsigned int clr_mfp_irq_base;
47 unsigned int clr_mfp_hwirq;
48 struct irq_domain *domain;
49};
50
51struct mmp_intc_conf {
52 unsigned int conf_enable;
53 unsigned int conf_disable;
54 unsigned int conf_mask;
55};
56
57void __iomem *mmp_icu_base;
58static struct icu_chip_data icu_data[MAX_ICU_NR];
59static int max_icu_nr;
60
61extern void mmp2_clear_pmic_int(void);
62
63static void icu_mask_ack_irq(struct irq_data *d)
64{
65 struct irq_domain *domain = d->domain;
66 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
67 int hwirq;
68 u32 r;
69
70 hwirq = d->irq - data->virq_base;
71 if (data == &icu_data[0]) {
72 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
73 r &= ~data->conf_mask;
74 r |= data->conf_disable;
75 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
76 } else {
77#ifdef CONFIG_CPU_MMP2
78 if ((data->virq_base == data->clr_mfp_irq_base)
79 && (hwirq == data->clr_mfp_hwirq))
80 mmp2_clear_pmic_int();
81#endif
82 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
83 writel_relaxed(r, data->reg_mask);
84 }
85}
86
87static void icu_mask_irq(struct irq_data *d)
88{
89 struct irq_domain *domain = d->domain;
90 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
91 int hwirq;
92 u32 r;
93
94 hwirq = d->irq - data->virq_base;
95 if (data == &icu_data[0]) {
96 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
97 r &= ~data->conf_mask;
98 r |= data->conf_disable;
99 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
100 } else {
101 r = readl_relaxed(data->reg_mask) | (1 << hwirq);
102 writel_relaxed(r, data->reg_mask);
103 }
104}
105
106static void icu_unmask_irq(struct irq_data *d)
107{
108 struct irq_domain *domain = d->domain;
109 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data;
110 int hwirq;
111 u32 r;
112
113 hwirq = d->irq - data->virq_base;
114 if (data == &icu_data[0]) {
115 r = readl_relaxed(mmp_icu_base + (hwirq << 2));
116 r &= ~data->conf_mask;
117 r |= data->conf_enable;
118 writel_relaxed(r, mmp_icu_base + (hwirq << 2));
119 } else {
120 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq);
121 writel_relaxed(r, data->reg_mask);
122 }
123}
124
125static struct irq_chip icu_irq_chip = {
126 .name = "icu_irq",
127 .irq_mask = icu_mask_irq,
128 .irq_mask_ack = icu_mask_ack_irq,
129 .irq_unmask = icu_unmask_irq,
130};
131
132static void icu_mux_irq_demux(unsigned int irq, struct irq_desc *desc)
133{
134 struct irq_domain *domain;
135 struct icu_chip_data *data;
136 int i;
137 unsigned long mask, status, n;
138
139 for (i = 1; i < max_icu_nr; i++) {
140 if (irq == icu_data[i].cascade_irq) {
141 domain = icu_data[i].domain;
142 data = (struct icu_chip_data *)domain->host_data;
143 break;
144 }
145 }
146 if (i >= max_icu_nr) {
147 pr_err("Spurious irq %d in MMP INTC\n", irq);
148 return;
149 }
150
151 mask = readl_relaxed(data->reg_mask);
152 while (1) {
153 status = readl_relaxed(data->reg_status) & ~mask;
154 if (status == 0)
155 break;
156 for_each_set_bit(n, &status, BITS_PER_LONG) {
157 generic_handle_irq(icu_data[i].virq_base + n);
158 }
159 }
160}
161
162static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq,
163 irq_hw_number_t hw)
164{
165 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
166 set_irq_flags(irq, IRQF_VALID);
167 return 0;
168}
169
170static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node,
171 const u32 *intspec, unsigned int intsize,
172 unsigned long *out_hwirq,
173 unsigned int *out_type)
174{
175 *out_hwirq = intspec[0];
176 return 0;
177}
178
179const struct irq_domain_ops mmp_irq_domain_ops = {
180 .map = mmp_irq_domain_map,
181 .xlate = mmp_irq_domain_xlate,
182};
183
184static struct mmp_intc_conf mmp_conf = {
185 .conf_enable = 0x51,
186 .conf_disable = 0x0,
187 .conf_mask = 0x7f,
188};
189
190static struct mmp_intc_conf mmp2_conf = {
191 .conf_enable = 0x20,
192 .conf_disable = 0x0,
193 .conf_mask = 0x7f,
194};
195
196/* MMP (ARMv5) */
197void __init icu_init_irq(void)
198{
199 int irq;
200
201 max_icu_nr = 1;
202 mmp_icu_base = ioremap(0xd4282000, 0x1000);
203 icu_data[0].conf_enable = mmp_conf.conf_enable;
204 icu_data[0].conf_disable = mmp_conf.conf_disable;
205 icu_data[0].conf_mask = mmp_conf.conf_mask;
206 icu_data[0].nr_irqs = 64;
207 icu_data[0].virq_base = 0;
208 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
209 &irq_domain_simple_ops,
210 &icu_data[0]);
211 for (irq = 0; irq < 64; irq++) {
212 icu_mask_irq(irq_get_irq_data(irq));
213 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
214 set_irq_flags(irq, IRQF_VALID);
215 }
216 irq_set_default_host(icu_data[0].domain);
217#ifdef CONFIG_CPU_PXA910
218 icu_irq_chip.irq_set_wake = pxa910_set_wake;
219#endif
220}
221
222/* MMP2 (ARMv7) */
223void __init mmp2_init_icu(void)
224{
225 int irq;
226
227 max_icu_nr = 8;
228 mmp_icu_base = ioremap(0xd4282000, 0x1000);
229 icu_data[0].conf_enable = mmp2_conf.conf_enable;
230 icu_data[0].conf_disable = mmp2_conf.conf_disable;
231 icu_data[0].conf_mask = mmp2_conf.conf_mask;
232 icu_data[0].nr_irqs = 64;
233 icu_data[0].virq_base = 0;
234 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,
235 &irq_domain_simple_ops,
236 &icu_data[0]);
237 icu_data[1].reg_status = mmp_icu_base + 0x150;
238 icu_data[1].reg_mask = mmp_icu_base + 0x168;
239 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE;
240 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE;
241 icu_data[1].nr_irqs = 2;
242 icu_data[1].cascade_irq = 4;
243 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE;
244 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
245 icu_data[1].virq_base, 0,
246 &irq_domain_simple_ops,
247 &icu_data[1]);
248 icu_data[2].reg_status = mmp_icu_base + 0x154;
249 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
250 icu_data[2].nr_irqs = 2;
251 icu_data[2].cascade_irq = 5;
252 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE;
253 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
254 icu_data[2].virq_base, 0,
255 &irq_domain_simple_ops,
256 &icu_data[2]);
257 icu_data[3].reg_status = mmp_icu_base + 0x180;
258 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
259 icu_data[3].nr_irqs = 3;
260 icu_data[3].cascade_irq = 9;
261 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE;
262 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
263 icu_data[3].virq_base, 0,
264 &irq_domain_simple_ops,
265 &icu_data[3]);
266 icu_data[4].reg_status = mmp_icu_base + 0x158;
267 icu_data[4].reg_mask = mmp_icu_base + 0x170;
268 icu_data[4].nr_irqs = 5;
269 icu_data[4].cascade_irq = 17;
270 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE;
271 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
272 icu_data[4].virq_base, 0,
273 &irq_domain_simple_ops,
274 &icu_data[4]);
275 icu_data[5].reg_status = mmp_icu_base + 0x15c;
276 icu_data[5].reg_mask = mmp_icu_base + 0x174;
277 icu_data[5].nr_irqs = 15;
278 icu_data[5].cascade_irq = 35;
279 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE;
280 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
281 icu_data[5].virq_base, 0,
282 &irq_domain_simple_ops,
283 &icu_data[5]);
284 icu_data[6].reg_status = mmp_icu_base + 0x160;
285 icu_data[6].reg_mask = mmp_icu_base + 0x178;
286 icu_data[6].nr_irqs = 2;
287 icu_data[6].cascade_irq = 51;
288 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE;
289 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
290 icu_data[6].virq_base, 0,
291 &irq_domain_simple_ops,
292 &icu_data[6]);
293 icu_data[7].reg_status = mmp_icu_base + 0x188;
294 icu_data[7].reg_mask = mmp_icu_base + 0x184;
295 icu_data[7].nr_irqs = 2;
296 icu_data[7].cascade_irq = 55;
297 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE;
298 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
299 icu_data[7].virq_base, 0,
300 &irq_domain_simple_ops,
301 &icu_data[7]);
302 for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) {
303 icu_mask_irq(irq_get_irq_data(irq));
304 switch (irq) {
305 case IRQ_MMP2_PMIC_MUX:
306 case IRQ_MMP2_RTC_MUX:
307 case IRQ_MMP2_KEYPAD_MUX:
308 case IRQ_MMP2_TWSI_MUX:
309 case IRQ_MMP2_MISC_MUX:
310 case IRQ_MMP2_MIPI_HSI1_MUX:
311 case IRQ_MMP2_MIPI_HSI0_MUX:
312 irq_set_chip(irq, &icu_irq_chip);
313 irq_set_chained_handler(irq, icu_mux_irq_demux);
314 break;
315 default:
316 irq_set_chip_and_handler(irq, &icu_irq_chip,
317 handle_level_irq);
318 break;
319 }
320 set_irq_flags(irq, IRQF_VALID);
321 }
322 irq_set_default_host(icu_data[0].domain);
323#ifdef CONFIG_CPU_MMP2
324 icu_irq_chip.irq_set_wake = mmp2_set_wake;
325#endif
326}
327
328#ifdef CONFIG_OF
329static const struct of_device_id intc_ids[] __initconst = {
330 { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
331 { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
332 {}
333};
334
335static const struct of_device_id mmp_mux_irq_match[] __initconst = {
336 { .compatible = "mrvl,mmp2-mux-intc" },
337 {}
338};
339
340int __init mmp2_mux_init(struct device_node *parent)
341{
342 struct device_node *node;
343 const struct of_device_id *of_id;
344 struct resource res;
345 int i, irq_base, ret, irq;
346 u32 nr_irqs, mfp_irq;
347
348 node = parent;
349 max_icu_nr = 1;
350 for (i = 1; i < MAX_ICU_NR; i++) {
351 node = of_find_matching_node(node, mmp_mux_irq_match);
352 if (!node)
353 break;
354 of_id = of_match_node(&mmp_mux_irq_match[0], node);
355 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
356 &nr_irqs);
357 if (ret) {
358 pr_err("Not found mrvl,intc-nr-irqs property\n");
359 ret = -EINVAL;
360 goto err;
361 }
362 ret = of_address_to_resource(node, 0, &res);
363 if (ret < 0) {
364 pr_err("Not found reg property\n");
365 ret = -EINVAL;
366 goto err;
367 }
368 icu_data[i].reg_status = mmp_icu_base + res.start;
369 ret = of_address_to_resource(node, 1, &res);
370 if (ret < 0) {
371 pr_err("Not found reg property\n");
372 ret = -EINVAL;
373 goto err;
374 }
375 icu_data[i].reg_mask = mmp_icu_base + res.start;
376 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
377 if (!icu_data[i].cascade_irq) {
378 ret = -EINVAL;
379 goto err;
380 }
381
382 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
383 if (irq_base < 0) {
384 pr_err("Failed to allocate IRQ numbers for mux intc\n");
385 ret = irq_base;
386 goto err;
387 }
388 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
389 &mfp_irq)) {
390 icu_data[i].clr_mfp_irq_base = irq_base;
391 icu_data[i].clr_mfp_hwirq = mfp_irq;
392 }
393 irq_set_chained_handler(icu_data[i].cascade_irq,
394 icu_mux_irq_demux);
395 icu_data[i].nr_irqs = nr_irqs;
396 icu_data[i].virq_base = irq_base;
397 icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
398 irq_base, 0,
399 &mmp_irq_domain_ops,
400 &icu_data[i]);
401 for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
402 icu_mask_irq(irq_get_irq_data(irq));
403 }
404 max_icu_nr = i;
405 return 0;
406err:
407 of_node_put(node);
408 max_icu_nr = i;
409 return ret;
410}
411
412void __init mmp_dt_irq_init(void)
413{
414 struct device_node *node;
415 const struct of_device_id *of_id;
416 struct mmp_intc_conf *conf;
417 int nr_irqs, irq_base, ret, irq;
418
419 node = of_find_matching_node(NULL, intc_ids);
420 if (!node) {
421 pr_err("Failed to find interrupt controller in arch-mmp\n");
422 return;
423 }
424 of_id = of_match_node(intc_ids, node);
425 conf = of_id->data;
426
427 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
428 if (ret) {
429 pr_err("Not found mrvl,intc-nr-irqs property\n");
430 return;
431 }
432
433 mmp_icu_base = of_iomap(node, 0);
434 if (!mmp_icu_base) {
435 pr_err("Failed to get interrupt controller register\n");
436 return;
437 }
438
439 irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0);
440 if (irq_base < 0) {
441 pr_err("Failed to allocate IRQ numbers\n");
442 goto err;
443 } else if (irq_base != NR_IRQS_LEGACY) {
444 pr_err("ICU's irqbase should be started from 0\n");
445 goto err;
446 }
447 icu_data[0].conf_enable = conf->conf_enable;
448 icu_data[0].conf_disable = conf->conf_disable;
449 icu_data[0].conf_mask = conf->conf_mask;
450 icu_data[0].nr_irqs = nr_irqs;
451 icu_data[0].virq_base = 0;
452 icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0,
453 &mmp_irq_domain_ops,
454 &icu_data[0]);
455 irq_set_default_host(icu_data[0].domain);
456 for (irq = 0; irq < nr_irqs; irq++)
457 icu_mask_irq(irq_get_irq_data(irq));
458 mmp2_mux_init(node);
459 return;
460err:
461 iounmap(mmp_icu_base);
462}
463#endif
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index b37915dc4470..cca529ceecb7 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -9,17 +9,13 @@
9 * publishhed by the Free Software Foundation. 9 * publishhed by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/irq.h> 12#include <linux/irqchip.h>
13#include <linux/irqdomain.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h> 13#include <linux/of_platform.h>
16#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
17#include <asm/mach/time.h> 15#include <asm/mach/time.h>
18#include <mach/irqs.h>
19 16
20#include "common.h" 17#include "common.h"
21 18
22extern void __init mmp_dt_irq_init(void);
23extern void __init mmp_dt_init_timer(void); 19extern void __init mmp_dt_init_timer(void);
24 20
25static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { 21static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = {
64 60
65DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") 61DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
66 .map_io = mmp_map_io, 62 .map_io = mmp_map_io,
67 .init_irq = mmp_dt_irq_init,
68 .init_time = mmp_dt_init_timer, 63 .init_time = mmp_dt_init_timer,
69 .init_machine = pxa168_dt_init, 64 .init_machine = pxa168_dt_init,
70 .dt_compat = mmp_dt_board_compat, 65 .dt_compat = mmp_dt_board_compat,
@@ -72,7 +67,6 @@ MACHINE_END
72 67
73DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") 68DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
74 .map_io = mmp_map_io, 69 .map_io = mmp_map_io,
75 .init_irq = mmp_dt_irq_init,
76 .init_time = mmp_dt_init_timer, 70 .init_time = mmp_dt_init_timer,
77 .init_machine = pxa910_dt_init, 71 .init_machine = pxa910_dt_init,
78 .dt_compat = mmp_dt_board_compat, 72 .dt_compat = mmp_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 4ac256720f7d..023cb453f157 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -10,18 +10,13 @@
10 */ 10 */
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/irq.h> 13#include <linux/irqchip.h>
14#include <linux/irqdomain.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 14#include <linux/of_platform.h>
17#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 16#include <asm/mach/time.h>
19#include <mach/irqs.h>
20#include <mach/regs-apbc.h>
21 17
22#include "common.h" 18#include "common.h"
23 19
24extern void __init mmp_dt_irq_init(void);
25extern void __init mmp_dt_init_timer(void); 20extern void __init mmp_dt_init_timer(void);
26 21
27static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { 22static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
49 44
50DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") 45DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
51 .map_io = mmp_map_io, 46 .map_io = mmp_map_io,
52 .init_irq = mmp_dt_irq_init,
53 .init_time = mmp_dt_init_timer, 47 .init_time = mmp_dt_init_timer,
54 .init_machine = mmp2_dt_init, 48 .init_machine = mmp2_dt_init,
55 .dt_compat = mmp2_dt_board_compat, 49 .dt_compat = mmp2_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c7592f168bbd..a70b5530bd42 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,8 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqchip/mmp.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17 19
18#include <asm/hardware/cache-tauros2.h> 20#include <asm/hardware/cache-tauros2.h>
@@ -26,6 +28,7 @@
26#include <mach/mfp.h> 28#include <mach/mfp.h>
27#include <mach/devices.h> 29#include <mach/devices.h>
28#include <mach/mmp2.h> 30#include <mach/mmp2.h>
31#include <mach/pm-mmp2.h>
29 32
30#include "common.h" 33#include "common.h"
31 34
@@ -94,6 +97,9 @@ void mmp2_clear_pmic_int(void)
94void __init mmp2_init_irq(void) 97void __init mmp2_init_irq(void)
95{ 98{
96 mmp2_init_icu(); 99 mmp2_init_icu();
100#ifdef CONFIG_PM
101 icu_irq_chip.irq_set_wake = mmp2_set_wake;
102#endif
97} 103}
98 104
99static int __init mmp2_init(void) 105static int __init mmp2_init(void)
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index ce6393acad86..eb57ee196842 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/list.h> 13#include <linux/list.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqchip/mmp.h>
15#include <linux/platform_device.h> 17#include <linux/platform_device.h>
16 18
17#include <asm/hardware/cache-tauros2.h> 19#include <asm/hardware/cache-tauros2.h>
@@ -23,6 +25,8 @@
23#include <mach/dma.h> 25#include <mach/dma.h>
24#include <mach/mfp.h> 26#include <mach/mfp.h>
25#include <mach/devices.h> 27#include <mach/devices.h>
28#include <mach/pm-pxa910.h>
29#include <mach/pxa910.h>
26 30
27#include "common.h" 31#include "common.h"
28 32
@@ -79,6 +83,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
79void __init pxa910_init_irq(void) 83void __init pxa910_init_irq(void)
80{ 84{
81 icu_init_irq(); 85 icu_init_irq();
86#ifdef CONFIG_PM
87 icu_irq_chip.irq_set_wake = pxa910_set_wake;
88#endif
82} 89}
83 90
84static int __init pxa910_init(void) 91static int __init pxa910_init(void)
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index 8483906d4308..702232996c8c 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,7 +15,7 @@
15#include <linux/mtd/partitions.h> 15#include <linux/mtd/partitions.h>
16#include <linux/mtd/onenand.h> 16#include <linux/mtd/onenand.h>
17#include <linux/interrupt.h> 17#include <linux/interrupt.h>
18#include <linux/i2c/pca953x.h> 18#include <linux/platform_data/pca953x.h>
19#include <linux/gpio.h> 19#include <linux/gpio.h>
20#include <linux/gpio-pxa.h> 20#include <linux/gpio-pxa.h>
21#include <linux/mfd/88pm860x.h> 21#include <linux/mfd/88pm860x.h>
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index d257ff40e16b..d872634c2f85 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,17 +1,16 @@
1obj-y += io.o timer.o 1obj-y += timer.o
2obj-y += clock.o 2obj-y += clock.o
3 3
4obj-$(CONFIG_MSM_VIC) += irq-vic.o 4obj-$(CONFIG_MSM_VIC) += irq-vic.o
5obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
6 5
7obj-$(CONFIG_ARCH_MSM7X00A) += irq.o 6obj-$(CONFIG_ARCH_MSM7X00A) += irq.o
8obj-$(CONFIG_ARCH_QSD8X50) += sirc.o 7obj-$(CONFIG_ARCH_QSD8X50) += sirc.o
9 8
10obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o 9obj-$(CONFIG_MSM_PROC_COMM) += proc_comm.o clock-pcom.o vreg.o
11 10
12obj-$(CONFIG_ARCH_MSM7X00A) += dma.o 11obj-$(CONFIG_ARCH_MSM7X00A) += dma.o io.o
13obj-$(CONFIG_ARCH_MSM7X30) += dma.o 12obj-$(CONFIG_ARCH_MSM7X30) += dma.o io.o
14obj-$(CONFIG_ARCH_QSD8X50) += dma.o 13obj-$(CONFIG_ARCH_QSD8X50) += dma.o io.o
15 14
16obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o 15obj-$(CONFIG_MSM_SMD) += smd.o smd_debug.o
17obj-$(CONFIG_MSM_SMD) += last_radio_log.o 16obj-$(CONFIG_MSM_SMD) += last_radio_log.o
diff --git a/arch/arm/mach-msm/board-dt-8660.c b/arch/arm/mach-msm/board-dt-8660.c
index 492f5cd87b0a..c2946892f5e3 100644
--- a/arch/arm/mach-msm/board-dt-8660.c
+++ b/arch/arm/mach-msm/board-dt-8660.c
@@ -15,8 +15,8 @@
15#include <linux/of_platform.h> 15#include <linux/of_platform.h>
16 16
17#include <asm/mach/arch.h> 17#include <asm/mach/arch.h>
18#include <asm/mach/map.h>
18 19
19#include <mach/board.h>
20#include "common.h" 20#include "common.h"
21 21
22static void __init msm8x60_init_late(void) 22static void __init msm8x60_init_late(void)
@@ -42,9 +42,7 @@ static const char *msm8x60_fluid_match[] __initdata = {
42 42
43DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)") 43DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
44 .smp = smp_ops(msm_smp_ops), 44 .smp = smp_ops(msm_smp_ops),
45 .map_io = msm_map_msm8x60_io,
46 .init_machine = msm8x60_dt_init, 45 .init_machine = msm8x60_dt_init,
47 .init_late = msm8x60_init_late, 46 .init_late = msm8x60_init_late,
48 .init_time = msm_dt_timer_init,
49 .dt_compat = msm8x60_fluid_match, 47 .dt_compat = msm8x60_fluid_match,
50MACHINE_END 48MACHINE_END
diff --git a/arch/arm/mach-msm/board-dt-8960.c b/arch/arm/mach-msm/board-dt-8960.c
index bb5530957c4f..d4ca52c45111 100644
--- a/arch/arm/mach-msm/board-dt-8960.c
+++ b/arch/arm/mach-msm/board-dt-8960.c
@@ -14,6 +14,7 @@
14#include <linux/of_platform.h> 14#include <linux/of_platform.h>
15 15
16#include <asm/mach/arch.h> 16#include <asm/mach/arch.h>
17#include <asm/mach/map.h>
17 18
18#include "common.h" 19#include "common.h"
19 20
@@ -29,8 +30,6 @@ static const char * const msm8960_dt_match[] __initconst = {
29 30
30DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") 31DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)")
31 .smp = smp_ops(msm_smp_ops), 32 .smp = smp_ops(msm_smp_ops),
32 .map_io = msm_map_msm8960_io,
33 .init_time = msm_dt_timer_init,
34 .init_machine = msm_dt_init, 33 .init_machine = msm_dt_init,
35 .dt_compat = msm8960_dt_match, 34 .dt_compat = msm8960_dt_match,
36MACHINE_END 35MACHINE_END
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 803651ad4f62..a77529887cbc 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -29,7 +29,6 @@
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/irqs.h> 31#include <mach/irqs.h>
32#include <mach/board.h>
33#include <mach/msm_iomap.h> 32#include <mach/msm_iomap.h>
34 33
35#include <linux/mtd/nand.h> 34#include <linux/mtd/nand.h>
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 30c3496db593..7d9981cb400e 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -28,12 +28,12 @@
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/board.h>
32#include <mach/hardware.h> 31#include <mach/hardware.h>
33 32
34#include "board-mahimahi.h" 33#include "board-mahimahi.h"
35#include "devices.h" 34#include "devices.h"
36#include "proc_comm.h" 35#include "proc_comm.h"
36#include "common.h"
37 37
38static uint debug_uart; 38static uint debug_uart;
39 39
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index db3d8c0bc8a4..f9af5a46e8b6 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -30,7 +30,6 @@
30#include <asm/memory.h> 30#include <asm/memory.h>
31#include <asm/setup.h> 31#include <asm/setup.h>
32 32
33#include <mach/board.h>
34#include <mach/msm_iomap.h> 33#include <mach/msm_iomap.h>
35#include <mach/dma.h> 34#include <mach/dma.h>
36 35
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index f14a73d86bc0..5f933bc50783 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -28,7 +28,6 @@
28#include <asm/io.h> 28#include <asm/io.h>
29#include <asm/setup.h> 29#include <asm/setup.h>
30 30
31#include <mach/board.h>
32#include <mach/irqs.h> 31#include <mach/irqs.h>
33#include <mach/sirc.h> 32#include <mach/sirc.h>
34#include <mach/vreg.h> 33#include <mach/vreg.h>
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 70730111b37c..327605174d63 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -28,7 +28,6 @@
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30#include <mach/vreg.h> 30#include <mach/vreg.h>
31#include <mach/board.h>
32 31
33#include <asm/io.h> 32#include <asm/io.h>
34#include <asm/delay.h> 33#include <asm/delay.h>
@@ -41,6 +40,7 @@
41#include "board-sapphire.h" 40#include "board-sapphire.h"
42#include "proc_comm.h" 41#include "proc_comm.h"
43#include "devices.h" 42#include "devices.h"
43#include "common.h"
44 44
45void msm_init_irq(void); 45void msm_init_irq(void);
46void msm_init_gpio(void); 46void msm_init_gpio(void);
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 64a46eb4fc49..ccf6621bc664 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -25,7 +25,6 @@
25#include <asm/mach/map.h> 25#include <asm/mach/map.h>
26#include <asm/setup.h> 26#include <asm/setup.h>
27 27
28#include <mach/board.h>
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30#include <mach/msm_iomap.h> 29#include <mach/msm_iomap.h>
31 30
diff --git a/arch/arm/mach-msm/board-trout.h b/arch/arm/mach-msm/board-trout.h
index 651851c3e1dd..b2379ede43bc 100644
--- a/arch/arm/mach-msm/board-trout.h
+++ b/arch/arm/mach-msm/board-trout.h
@@ -4,7 +4,7 @@
4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H 4#ifndef __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H 5#define __ARCH_ARM_MACH_MSM_BOARD_TROUT_H
6 6
7#include <mach/board.h> 7#include "common.h"
8 8
9#define MSM_SMI_BASE 0x00000000 9#define MSM_SMI_BASE 0x00000000
10#define MSM_SMI_SIZE 0x00800000 10#define MSM_SMI_SIZE 0x00800000
diff --git a/arch/arm/mach-msm/common.h b/arch/arm/mach-msm/common.h
index 421cf7751a80..33c7725adae2 100644
--- a/arch/arm/mach-msm/common.h
+++ b/arch/arm/mach-msm/common.h
@@ -14,13 +14,10 @@
14 14
15extern void msm7x01_timer_init(void); 15extern void msm7x01_timer_init(void);
16extern void msm7x30_timer_init(void); 16extern void msm7x30_timer_init(void);
17extern void msm_dt_timer_init(void);
18extern void qsd8x50_timer_init(void); 17extern void qsd8x50_timer_init(void);
19 18
20extern void msm_map_common_io(void); 19extern void msm_map_common_io(void);
21extern void msm_map_msm7x30_io(void); 20extern void msm_map_msm7x30_io(void);
22extern void msm_map_msm8x60_io(void);
23extern void msm_map_msm8960_io(void);
24extern void msm_map_qsd8x50_io(void); 21extern void msm_map_qsd8x50_io(void);
25 22
26extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, 23extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
@@ -29,4 +26,19 @@ extern void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
29extern struct smp_operations msm_smp_ops; 26extern struct smp_operations msm_smp_ops;
30extern void msm_cpu_die(unsigned int cpu); 27extern void msm_cpu_die(unsigned int cpu);
31 28
29struct msm_mmc_platform_data;
30
31extern void msm_add_devices(void);
32extern void msm_init_irq(void);
33extern void msm_init_gpio(void);
34extern int msm_add_sdcc(unsigned int controller,
35 struct msm_mmc_platform_data *plat,
36 unsigned int stat_irq, unsigned long stat_irq_flags);
37
38#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
39extern int smd_debugfs_init(void);
40#else
41static inline int smd_debugfs_init(void) { return 0; }
42#endif
43
32#endif 44#endif
diff --git a/arch/arm/mach-msm/devices-iommu.c b/arch/arm/mach-msm/devices-iommu.c
deleted file mode 100644
index 0fb7a17df398..000000000000
--- a/arch/arm/mach-msm/devices-iommu.c
+++ /dev/null
@@ -1,912 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#include <linux/kernel.h>
19#include <linux/platform_device.h>
20#include <linux/bootmem.h>
21#include <linux/module.h>
22#include <mach/irqs.h>
23#include <mach/iommu.h>
24
25static struct resource msm_iommu_jpegd_resources[] = {
26 {
27 .start = 0x07300000,
28 .end = 0x07300000 + SZ_1M - 1,
29 .name = "physbase",
30 .flags = IORESOURCE_MEM,
31 },
32 {
33 .name = "nonsecure_irq",
34 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
35 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
36 .flags = IORESOURCE_IRQ,
37 },
38 {
39 .name = "secure_irq",
40 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
41 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
42 .flags = IORESOURCE_IRQ,
43 },
44};
45
46static struct resource msm_iommu_vpe_resources[] = {
47 {
48 .start = 0x07400000,
49 .end = 0x07400000 + SZ_1M - 1,
50 .name = "physbase",
51 .flags = IORESOURCE_MEM,
52 },
53 {
54 .name = "nonsecure_irq",
55 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
56 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
57 .flags = IORESOURCE_IRQ,
58 },
59 {
60 .name = "secure_irq",
61 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
62 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
63 .flags = IORESOURCE_IRQ,
64 },
65};
66
67static struct resource msm_iommu_mdp0_resources[] = {
68 {
69 .start = 0x07500000,
70 .end = 0x07500000 + SZ_1M - 1,
71 .name = "physbase",
72 .flags = IORESOURCE_MEM,
73 },
74 {
75 .name = "nonsecure_irq",
76 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
77 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
78 .flags = IORESOURCE_IRQ,
79 },
80 {
81 .name = "secure_irq",
82 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
83 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
84 .flags = IORESOURCE_IRQ,
85 },
86};
87
88static struct resource msm_iommu_mdp1_resources[] = {
89 {
90 .start = 0x07600000,
91 .end = 0x07600000 + SZ_1M - 1,
92 .name = "physbase",
93 .flags = IORESOURCE_MEM,
94 },
95 {
96 .name = "nonsecure_irq",
97 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
98 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
99 .flags = IORESOURCE_IRQ,
100 },
101 {
102 .name = "secure_irq",
103 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
104 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
105 .flags = IORESOURCE_IRQ,
106 },
107};
108
109static struct resource msm_iommu_rot_resources[] = {
110 {
111 .start = 0x07700000,
112 .end = 0x07700000 + SZ_1M - 1,
113 .name = "physbase",
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .name = "nonsecure_irq",
118 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
119 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
120 .flags = IORESOURCE_IRQ,
121 },
122 {
123 .name = "secure_irq",
124 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
125 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
126 .flags = IORESOURCE_IRQ,
127 },
128};
129
130static struct resource msm_iommu_ijpeg_resources[] = {
131 {
132 .start = 0x07800000,
133 .end = 0x07800000 + SZ_1M - 1,
134 .name = "physbase",
135 .flags = IORESOURCE_MEM,
136 },
137 {
138 .name = "nonsecure_irq",
139 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
140 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
141 .flags = IORESOURCE_IRQ,
142 },
143 {
144 .name = "secure_irq",
145 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
146 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151static struct resource msm_iommu_vfe_resources[] = {
152 {
153 .start = 0x07900000,
154 .end = 0x07900000 + SZ_1M - 1,
155 .name = "physbase",
156 .flags = IORESOURCE_MEM,
157 },
158 {
159 .name = "nonsecure_irq",
160 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
161 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
162 .flags = IORESOURCE_IRQ,
163 },
164 {
165 .name = "secure_irq",
166 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
167 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
168 .flags = IORESOURCE_IRQ,
169 },
170};
171
172static struct resource msm_iommu_vcodec_a_resources[] = {
173 {
174 .start = 0x07A00000,
175 .end = 0x07A00000 + SZ_1M - 1,
176 .name = "physbase",
177 .flags = IORESOURCE_MEM,
178 },
179 {
180 .name = "nonsecure_irq",
181 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
182 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
183 .flags = IORESOURCE_IRQ,
184 },
185 {
186 .name = "secure_irq",
187 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
188 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct resource msm_iommu_vcodec_b_resources[] = {
194 {
195 .start = 0x07B00000,
196 .end = 0x07B00000 + SZ_1M - 1,
197 .name = "physbase",
198 .flags = IORESOURCE_MEM,
199 },
200 {
201 .name = "nonsecure_irq",
202 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
203 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
204 .flags = IORESOURCE_IRQ,
205 },
206 {
207 .name = "secure_irq",
208 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
209 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
210 .flags = IORESOURCE_IRQ,
211 },
212};
213
214static struct resource msm_iommu_gfx3d_resources[] = {
215 {
216 .start = 0x07C00000,
217 .end = 0x07C00000 + SZ_1M - 1,
218 .name = "physbase",
219 .flags = IORESOURCE_MEM,
220 },
221 {
222 .name = "nonsecure_irq",
223 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
224 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
225 .flags = IORESOURCE_IRQ,
226 },
227 {
228 .name = "secure_irq",
229 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
230 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
231 .flags = IORESOURCE_IRQ,
232 },
233};
234
235static struct resource msm_iommu_gfx2d0_resources[] = {
236 {
237 .start = 0x07D00000,
238 .end = 0x07D00000 + SZ_1M - 1,
239 .name = "physbase",
240 .flags = IORESOURCE_MEM,
241 },
242 {
243 .name = "nonsecure_irq",
244 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
245 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
246 .flags = IORESOURCE_IRQ,
247 },
248 {
249 .name = "secure_irq",
250 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
251 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
252 .flags = IORESOURCE_IRQ,
253 },
254};
255
256static struct resource msm_iommu_gfx2d1_resources[] = {
257 {
258 .start = 0x07E00000,
259 .end = 0x07E00000 + SZ_1M - 1,
260 .name = "physbase",
261 .flags = IORESOURCE_MEM,
262 },
263 {
264 .name = "nonsecure_irq",
265 .start = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
266 .end = SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ,
267 .flags = IORESOURCE_IRQ,
268 },
269 {
270 .name = "secure_irq",
271 .start = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
272 .end = SMMU_GFX2D1_CB_SC_SECURE_IRQ,
273 .flags = IORESOURCE_IRQ,
274 },
275};
276
277static struct platform_device msm_root_iommu_dev = {
278 .name = "msm_iommu",
279 .id = -1,
280};
281
282static struct msm_iommu_dev jpegd_iommu = {
283 .name = "jpegd",
284 .ncb = 2,
285};
286
287static struct msm_iommu_dev vpe_iommu = {
288 .name = "vpe",
289 .ncb = 2,
290};
291
292static struct msm_iommu_dev mdp0_iommu = {
293 .name = "mdp0",
294 .ncb = 2,
295};
296
297static struct msm_iommu_dev mdp1_iommu = {
298 .name = "mdp1",
299 .ncb = 2,
300};
301
302static struct msm_iommu_dev rot_iommu = {
303 .name = "rot",
304 .ncb = 2,
305};
306
307static struct msm_iommu_dev ijpeg_iommu = {
308 .name = "ijpeg",
309 .ncb = 2,
310};
311
312static struct msm_iommu_dev vfe_iommu = {
313 .name = "vfe",
314 .ncb = 2,
315};
316
317static struct msm_iommu_dev vcodec_a_iommu = {
318 .name = "vcodec_a",
319 .ncb = 2,
320};
321
322static struct msm_iommu_dev vcodec_b_iommu = {
323 .name = "vcodec_b",
324 .ncb = 2,
325};
326
327static struct msm_iommu_dev gfx3d_iommu = {
328 .name = "gfx3d",
329 .ncb = 3,
330};
331
332static struct msm_iommu_dev gfx2d0_iommu = {
333 .name = "gfx2d0",
334 .ncb = 2,
335};
336
337static struct msm_iommu_dev gfx2d1_iommu = {
338 .name = "gfx2d1",
339 .ncb = 2,
340};
341
342static struct platform_device msm_device_iommu_jpegd = {
343 .name = "msm_iommu",
344 .id = 0,
345 .dev = {
346 .parent = &msm_root_iommu_dev.dev,
347 },
348 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
349 .resource = msm_iommu_jpegd_resources,
350};
351
352static struct platform_device msm_device_iommu_vpe = {
353 .name = "msm_iommu",
354 .id = 1,
355 .dev = {
356 .parent = &msm_root_iommu_dev.dev,
357 },
358 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
359 .resource = msm_iommu_vpe_resources,
360};
361
362static struct platform_device msm_device_iommu_mdp0 = {
363 .name = "msm_iommu",
364 .id = 2,
365 .dev = {
366 .parent = &msm_root_iommu_dev.dev,
367 },
368 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
369 .resource = msm_iommu_mdp0_resources,
370};
371
372static struct platform_device msm_device_iommu_mdp1 = {
373 .name = "msm_iommu",
374 .id = 3,
375 .dev = {
376 .parent = &msm_root_iommu_dev.dev,
377 },
378 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
379 .resource = msm_iommu_mdp1_resources,
380};
381
382static struct platform_device msm_device_iommu_rot = {
383 .name = "msm_iommu",
384 .id = 4,
385 .dev = {
386 .parent = &msm_root_iommu_dev.dev,
387 },
388 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
389 .resource = msm_iommu_rot_resources,
390};
391
392static struct platform_device msm_device_iommu_ijpeg = {
393 .name = "msm_iommu",
394 .id = 5,
395 .dev = {
396 .parent = &msm_root_iommu_dev.dev,
397 },
398 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
399 .resource = msm_iommu_ijpeg_resources,
400};
401
402static struct platform_device msm_device_iommu_vfe = {
403 .name = "msm_iommu",
404 .id = 6,
405 .dev = {
406 .parent = &msm_root_iommu_dev.dev,
407 },
408 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
409 .resource = msm_iommu_vfe_resources,
410};
411
412static struct platform_device msm_device_iommu_vcodec_a = {
413 .name = "msm_iommu",
414 .id = 7,
415 .dev = {
416 .parent = &msm_root_iommu_dev.dev,
417 },
418 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
419 .resource = msm_iommu_vcodec_a_resources,
420};
421
422static struct platform_device msm_device_iommu_vcodec_b = {
423 .name = "msm_iommu",
424 .id = 8,
425 .dev = {
426 .parent = &msm_root_iommu_dev.dev,
427 },
428 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
429 .resource = msm_iommu_vcodec_b_resources,
430};
431
432static struct platform_device msm_device_iommu_gfx3d = {
433 .name = "msm_iommu",
434 .id = 9,
435 .dev = {
436 .parent = &msm_root_iommu_dev.dev,
437 },
438 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
439 .resource = msm_iommu_gfx3d_resources,
440};
441
442static struct platform_device msm_device_iommu_gfx2d0 = {
443 .name = "msm_iommu",
444 .id = 10,
445 .dev = {
446 .parent = &msm_root_iommu_dev.dev,
447 },
448 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
449 .resource = msm_iommu_gfx2d0_resources,
450};
451
452struct platform_device msm_device_iommu_gfx2d1 = {
453 .name = "msm_iommu",
454 .id = 11,
455 .dev = {
456 .parent = &msm_root_iommu_dev.dev,
457 },
458 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d1_resources),
459 .resource = msm_iommu_gfx2d1_resources,
460};
461
462static struct msm_iommu_ctx_dev jpegd_src_ctx = {
463 .name = "jpegd_src",
464 .num = 0,
465 .mids = {0, -1}
466};
467
468static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
469 .name = "jpegd_dst",
470 .num = 1,
471 .mids = {1, -1}
472};
473
474static struct msm_iommu_ctx_dev vpe_src_ctx = {
475 .name = "vpe_src",
476 .num = 0,
477 .mids = {0, -1}
478};
479
480static struct msm_iommu_ctx_dev vpe_dst_ctx = {
481 .name = "vpe_dst",
482 .num = 1,
483 .mids = {1, -1}
484};
485
486static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
487 .name = "mdp_vg1",
488 .num = 0,
489 .mids = {0, 2, -1}
490};
491
492static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
493 .name = "mdp_rgb1",
494 .num = 1,
495 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
496};
497
498static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
499 .name = "mdp_vg2",
500 .num = 0,
501 .mids = {0, 2, -1}
502};
503
504static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
505 .name = "mdp_rgb2",
506 .num = 1,
507 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
508};
509
510static struct msm_iommu_ctx_dev rot_src_ctx = {
511 .name = "rot_src",
512 .num = 0,
513 .mids = {0, -1}
514};
515
516static struct msm_iommu_ctx_dev rot_dst_ctx = {
517 .name = "rot_dst",
518 .num = 1,
519 .mids = {1, -1}
520};
521
522static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
523 .name = "ijpeg_src",
524 .num = 0,
525 .mids = {0, -1}
526};
527
528static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
529 .name = "ijpeg_dst",
530 .num = 1,
531 .mids = {1, -1}
532};
533
534static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
535 .name = "vfe_imgwr",
536 .num = 0,
537 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
538};
539
540static struct msm_iommu_ctx_dev vfe_misc_ctx = {
541 .name = "vfe_misc",
542 .num = 1,
543 .mids = {0, 1, 9, -1}
544};
545
546static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
547 .name = "vcodec_a_stream",
548 .num = 0,
549 .mids = {2, 5, -1}
550};
551
552static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
553 .name = "vcodec_a_mm1",
554 .num = 1,
555 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
556};
557
558static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
559 .name = "vcodec_b_mm2",
560 .num = 0,
561 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
562};
563
564static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
565 .name = "gfx3d_user",
566 .num = 0,
567 .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
568};
569
570static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
571 .name = "gfx3d_priv",
572 .num = 1,
573 .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
574 31, -1}
575};
576
577static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
578 .name = "gfx2d0_2d0",
579 .num = 0,
580 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
581};
582
583static struct msm_iommu_ctx_dev gfx2d1_2d1_ctx = {
584 .name = "gfx2d1_2d1",
585 .num = 0,
586 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
587};
588
589static struct platform_device msm_device_jpegd_src_ctx = {
590 .name = "msm_iommu_ctx",
591 .id = 0,
592 .dev = {
593 .parent = &msm_device_iommu_jpegd.dev,
594 },
595};
596
597static struct platform_device msm_device_jpegd_dst_ctx = {
598 .name = "msm_iommu_ctx",
599 .id = 1,
600 .dev = {
601 .parent = &msm_device_iommu_jpegd.dev,
602 },
603};
604
605static struct platform_device msm_device_vpe_src_ctx = {
606 .name = "msm_iommu_ctx",
607 .id = 2,
608 .dev = {
609 .parent = &msm_device_iommu_vpe.dev,
610 },
611};
612
613static struct platform_device msm_device_vpe_dst_ctx = {
614 .name = "msm_iommu_ctx",
615 .id = 3,
616 .dev = {
617 .parent = &msm_device_iommu_vpe.dev,
618 },
619};
620
621static struct platform_device msm_device_mdp_vg1_ctx = {
622 .name = "msm_iommu_ctx",
623 .id = 4,
624 .dev = {
625 .parent = &msm_device_iommu_mdp0.dev,
626 },
627};
628
629static struct platform_device msm_device_mdp_rgb1_ctx = {
630 .name = "msm_iommu_ctx",
631 .id = 5,
632 .dev = {
633 .parent = &msm_device_iommu_mdp0.dev,
634 },
635};
636
637static struct platform_device msm_device_mdp_vg2_ctx = {
638 .name = "msm_iommu_ctx",
639 .id = 6,
640 .dev = {
641 .parent = &msm_device_iommu_mdp1.dev,
642 },
643};
644
645static struct platform_device msm_device_mdp_rgb2_ctx = {
646 .name = "msm_iommu_ctx",
647 .id = 7,
648 .dev = {
649 .parent = &msm_device_iommu_mdp1.dev,
650 },
651};
652
653static struct platform_device msm_device_rot_src_ctx = {
654 .name = "msm_iommu_ctx",
655 .id = 8,
656 .dev = {
657 .parent = &msm_device_iommu_rot.dev,
658 },
659};
660
661static struct platform_device msm_device_rot_dst_ctx = {
662 .name = "msm_iommu_ctx",
663 .id = 9,
664 .dev = {
665 .parent = &msm_device_iommu_rot.dev,
666 },
667};
668
669static struct platform_device msm_device_ijpeg_src_ctx = {
670 .name = "msm_iommu_ctx",
671 .id = 10,
672 .dev = {
673 .parent = &msm_device_iommu_ijpeg.dev,
674 },
675};
676
677static struct platform_device msm_device_ijpeg_dst_ctx = {
678 .name = "msm_iommu_ctx",
679 .id = 11,
680 .dev = {
681 .parent = &msm_device_iommu_ijpeg.dev,
682 },
683};
684
685static struct platform_device msm_device_vfe_imgwr_ctx = {
686 .name = "msm_iommu_ctx",
687 .id = 12,
688 .dev = {
689 .parent = &msm_device_iommu_vfe.dev,
690 },
691};
692
693static struct platform_device msm_device_vfe_misc_ctx = {
694 .name = "msm_iommu_ctx",
695 .id = 13,
696 .dev = {
697 .parent = &msm_device_iommu_vfe.dev,
698 },
699};
700
701static struct platform_device msm_device_vcodec_a_stream_ctx = {
702 .name = "msm_iommu_ctx",
703 .id = 14,
704 .dev = {
705 .parent = &msm_device_iommu_vcodec_a.dev,
706 },
707};
708
709static struct platform_device msm_device_vcodec_a_mm1_ctx = {
710 .name = "msm_iommu_ctx",
711 .id = 15,
712 .dev = {
713 .parent = &msm_device_iommu_vcodec_a.dev,
714 },
715};
716
717static struct platform_device msm_device_vcodec_b_mm2_ctx = {
718 .name = "msm_iommu_ctx",
719 .id = 16,
720 .dev = {
721 .parent = &msm_device_iommu_vcodec_b.dev,
722 },
723};
724
725static struct platform_device msm_device_gfx3d_user_ctx = {
726 .name = "msm_iommu_ctx",
727 .id = 17,
728 .dev = {
729 .parent = &msm_device_iommu_gfx3d.dev,
730 },
731};
732
733static struct platform_device msm_device_gfx3d_priv_ctx = {
734 .name = "msm_iommu_ctx",
735 .id = 18,
736 .dev = {
737 .parent = &msm_device_iommu_gfx3d.dev,
738 },
739};
740
741static struct platform_device msm_device_gfx2d0_2d0_ctx = {
742 .name = "msm_iommu_ctx",
743 .id = 19,
744 .dev = {
745 .parent = &msm_device_iommu_gfx2d0.dev,
746 },
747};
748
749static struct platform_device msm_device_gfx2d1_2d1_ctx = {
750 .name = "msm_iommu_ctx",
751 .id = 20,
752 .dev = {
753 .parent = &msm_device_iommu_gfx2d1.dev,
754 },
755};
756
757static struct platform_device *msm_iommu_devs[] = {
758 &msm_device_iommu_jpegd,
759 &msm_device_iommu_vpe,
760 &msm_device_iommu_mdp0,
761 &msm_device_iommu_mdp1,
762 &msm_device_iommu_rot,
763 &msm_device_iommu_ijpeg,
764 &msm_device_iommu_vfe,
765 &msm_device_iommu_vcodec_a,
766 &msm_device_iommu_vcodec_b,
767 &msm_device_iommu_gfx3d,
768 &msm_device_iommu_gfx2d0,
769 &msm_device_iommu_gfx2d1,
770};
771
772static struct msm_iommu_dev *msm_iommu_data[] = {
773 &jpegd_iommu,
774 &vpe_iommu,
775 &mdp0_iommu,
776 &mdp1_iommu,
777 &rot_iommu,
778 &ijpeg_iommu,
779 &vfe_iommu,
780 &vcodec_a_iommu,
781 &vcodec_b_iommu,
782 &gfx3d_iommu,
783 &gfx2d0_iommu,
784 &gfx2d1_iommu,
785};
786
787static struct platform_device *msm_iommu_ctx_devs[] = {
788 &msm_device_jpegd_src_ctx,
789 &msm_device_jpegd_dst_ctx,
790 &msm_device_vpe_src_ctx,
791 &msm_device_vpe_dst_ctx,
792 &msm_device_mdp_vg1_ctx,
793 &msm_device_mdp_rgb1_ctx,
794 &msm_device_mdp_vg2_ctx,
795 &msm_device_mdp_rgb2_ctx,
796 &msm_device_rot_src_ctx,
797 &msm_device_rot_dst_ctx,
798 &msm_device_ijpeg_src_ctx,
799 &msm_device_ijpeg_dst_ctx,
800 &msm_device_vfe_imgwr_ctx,
801 &msm_device_vfe_misc_ctx,
802 &msm_device_vcodec_a_stream_ctx,
803 &msm_device_vcodec_a_mm1_ctx,
804 &msm_device_vcodec_b_mm2_ctx,
805 &msm_device_gfx3d_user_ctx,
806 &msm_device_gfx3d_priv_ctx,
807 &msm_device_gfx2d0_2d0_ctx,
808 &msm_device_gfx2d1_2d1_ctx,
809};
810
811static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
812 &jpegd_src_ctx,
813 &jpegd_dst_ctx,
814 &vpe_src_ctx,
815 &vpe_dst_ctx,
816 &mdp_vg1_ctx,
817 &mdp_rgb1_ctx,
818 &mdp_vg2_ctx,
819 &mdp_rgb2_ctx,
820 &rot_src_ctx,
821 &rot_dst_ctx,
822 &ijpeg_src_ctx,
823 &ijpeg_dst_ctx,
824 &vfe_imgwr_ctx,
825 &vfe_misc_ctx,
826 &vcodec_a_stream_ctx,
827 &vcodec_a_mm1_ctx,
828 &vcodec_b_mm2_ctx,
829 &gfx3d_user_ctx,
830 &gfx3d_priv_ctx,
831 &gfx2d0_2d0_ctx,
832 &gfx2d1_2d1_ctx,
833};
834
835static int __init msm8x60_iommu_init(void)
836{
837 int ret, i;
838
839 ret = platform_device_register(&msm_root_iommu_dev);
840 if (ret != 0) {
841 pr_err("Failed to register root IOMMU device!\n");
842 goto failure;
843 }
844
845 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
846 ret = platform_device_add_data(msm_iommu_devs[i],
847 msm_iommu_data[i],
848 sizeof(struct msm_iommu_dev));
849 if (ret != 0) {
850 pr_err("platform_device_add_data failed, "
851 "i = %d\n", i);
852 goto failure_unwind;
853 }
854
855 ret = platform_device_register(msm_iommu_devs[i]);
856
857 if (ret != 0) {
858 pr_err("platform_device_register iommu failed, "
859 "i = %d\n", i);
860 goto failure_unwind;
861 }
862 }
863
864 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
865 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
866 msm_iommu_ctx_data[i],
867 sizeof(*msm_iommu_ctx_devs[i]));
868 if (ret != 0) {
869 pr_err("platform_device_add_data iommu failed, "
870 "i = %d\n", i);
871 goto failure_unwind2;
872 }
873
874 ret = platform_device_register(msm_iommu_ctx_devs[i]);
875 if (ret != 0) {
876 pr_err("platform_device_register ctx failed, "
877 "i = %d\n", i);
878 goto failure_unwind2;
879 }
880 }
881 return 0;
882
883failure_unwind2:
884 while (--i >= 0)
885 platform_device_unregister(msm_iommu_ctx_devs[i]);
886failure_unwind:
887 while (--i >= 0)
888 platform_device_unregister(msm_iommu_devs[i]);
889
890 platform_device_unregister(&msm_root_iommu_dev);
891failure:
892 return ret;
893}
894
895static void __exit msm8x60_iommu_exit(void)
896{
897 int i;
898
899 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
900 platform_device_unregister(msm_iommu_ctx_devs[i]);
901
902 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
903 platform_device_unregister(msm_iommu_devs[i]);
904
905 platform_device_unregister(&msm_root_iommu_dev);
906}
907
908subsys_initcall(msm8x60_iommu_init);
909module_exit(msm8x60_iommu_exit);
910
911MODULE_LICENSE("GPL v2");
912MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index 14e286948f69..c15ea8ab20a7 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -21,10 +21,10 @@
21#include <mach/irqs.h> 21#include <mach/irqs.h>
22#include <mach/msm_iomap.h> 22#include <mach/msm_iomap.h>
23#include <mach/dma.h> 23#include <mach/dma.h>
24#include <mach/board.h>
25 24
26#include "devices.h" 25#include "devices.h"
27#include "smd_private.h" 26#include "smd_private.h"
27#include "common.h"
28 28
29#include <asm/mach/flash.h> 29#include <asm/mach/flash.h>
30 30
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 2ed89b25d304..9e1e9ce07b1a 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -21,9 +21,9 @@
21#include <mach/irqs.h> 21#include <mach/irqs.h>
22#include <mach/msm_iomap.h> 22#include <mach/msm_iomap.h>
23#include <mach/dma.h> 23#include <mach/dma.h>
24#include <mach/board.h>
25 24
26#include "devices.h" 25#include "devices.h"
26#include "common.h"
27 27
28#include <asm/mach/flash.h> 28#include <asm/mach/flash.h>
29 29
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
deleted file mode 100644
index c34e246a3e07..000000000000
--- a/arch/arm/mach-msm/include/mach/board.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* arch/arm/mach-msm/include/mach/board.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#ifndef __ASM_ARCH_MSM_BOARD_H
18#define __ASM_ARCH_MSM_BOARD_H
19
20#include <linux/types.h>
21#include <linux/platform_data/mmc-msm_sdcc.h>
22
23/* common init routines for use by arch/arm/mach-msm/board-*.c */
24
25void __init msm_add_devices(void);
26void __init msm_init_irq(void);
27void __init msm_init_gpio(void);
28int __init msm_add_sdcc(unsigned int controller,
29 struct msm_mmc_platform_data *plat,
30 unsigned int stat_irq, unsigned long stat_irq_flags);
31
32#if defined(CONFIG_MSM_SMD) && defined(CONFIG_DEBUG_FS)
33int smd_debugfs_init(void);
34#else
35static inline int smd_debugfs_init(void) { return 0; }
36#endif
37
38#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h
deleted file mode 100644
index 5c7c955e6d25..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu.h
+++ /dev/null
@@ -1,120 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef MSM_IOMMU_H
19#define MSM_IOMMU_H
20
21#include <linux/interrupt.h>
22#include <linux/clk.h>
23
24/* Sharability attributes of MSM IOMMU mappings */
25#define MSM_IOMMU_ATTR_NON_SH 0x0
26#define MSM_IOMMU_ATTR_SH 0x4
27
28/* Cacheability attributes of MSM IOMMU mappings */
29#define MSM_IOMMU_ATTR_NONCACHED 0x0
30#define MSM_IOMMU_ATTR_CACHED_WB_WA 0x1
31#define MSM_IOMMU_ATTR_CACHED_WB_NWA 0x2
32#define MSM_IOMMU_ATTR_CACHED_WT 0x3
33
34/* Mask for the cache policy attribute */
35#define MSM_IOMMU_CP_MASK 0x03
36
37/* Maximum number of Machine IDs that we are allowing to be mapped to the same
38 * context bank. The number of MIDs mapped to the same CB does not affect
39 * performance, but there is a practical limit on how many distinct MIDs may
40 * be present. These mappings are typically determined at design time and are
41 * not expected to change at run time.
42 */
43#define MAX_NUM_MIDS 32
44
45/**
46 * struct msm_iommu_dev - a single IOMMU hardware instance
47 * name Human-readable name given to this IOMMU HW instance
48 * ncb Number of context banks present on this IOMMU HW instance
49 */
50struct msm_iommu_dev {
51 const char *name;
52 int ncb;
53};
54
55/**
56 * struct msm_iommu_ctx_dev - an IOMMU context bank instance
57 * name Human-readable name given to this context bank
58 * num Index of this context bank within the hardware
59 * mids List of Machine IDs that are to be mapped into this context
60 * bank, terminated by -1. The MID is a set of signals on the
61 * AXI bus that identifies the function associated with a specific
62 * memory request. (See ARM spec).
63 */
64struct msm_iommu_ctx_dev {
65 const char *name;
66 int num;
67 int mids[MAX_NUM_MIDS];
68};
69
70
71/**
72 * struct msm_iommu_drvdata - A single IOMMU hardware instance
73 * @base: IOMMU config port base address (VA)
74 * @ncb The number of contexts on this IOMMU
75 * @irq: Interrupt number
76 * @clk: The bus clock for this IOMMU hardware instance
77 * @pclk: The clock for the IOMMU bus interconnect
78 *
79 * A msm_iommu_drvdata holds the global driver data about a single piece
80 * of an IOMMU hardware instance.
81 */
82struct msm_iommu_drvdata {
83 void __iomem *base;
84 int irq;
85 int ncb;
86 struct clk *clk;
87 struct clk *pclk;
88};
89
90/**
91 * struct msm_iommu_ctx_drvdata - an IOMMU context bank instance
92 * @num: Hardware context number of this context
93 * @pdev: Platform device associated wit this HW instance
94 * @attached_elm: List element for domains to track which devices are
95 * attached to them
96 *
97 * A msm_iommu_ctx_drvdata holds the driver data for a single context bank
98 * within each IOMMU hardware instance
99 */
100struct msm_iommu_ctx_drvdata {
101 int num;
102 struct platform_device *pdev;
103 struct list_head attached_elm;
104};
105
106/*
107 * Look up an IOMMU context device by its context name. NULL if none found.
108 * Useful for testing and drivers that do not yet fully have IOMMU stuff in
109 * their platform devices.
110 */
111struct device *msm_iommu_get_ctx(const char *ctx_name);
112
113/*
114 * Interrupt handler for the IOMMU context fault interrupt. Hooking the
115 * interrupt is not supported in the API yet, but this will print an error
116 * message and dump useful IOMMU registers.
117 */
118irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id);
119
120#endif
diff --git a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h b/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
deleted file mode 100644
index fc160101dead..000000000000
--- a/arch/arm/mach-msm/include/mach/iommu_hw-8xxx.h
+++ /dev/null
@@ -1,1865 +0,0 @@
1/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 */
17
18#ifndef __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
19#define __ARCH_ARM_MACH_MSM_IOMMU_HW_8XXX_H
20
21#define CTX_SHIFT 12
22
23#define GET_GLOBAL_REG(reg, base) (readl((base) + (reg)))
24#define GET_CTX_REG(reg, base, ctx) \
25 (readl((base) + (reg) + ((ctx) << CTX_SHIFT)))
26
27#define SET_GLOBAL_REG(reg, base, val) writel((val), ((base) + (reg)))
28
29#define SET_CTX_REG(reg, base, ctx, val) \
30 writel((val), ((base) + (reg) + ((ctx) << CTX_SHIFT)))
31
32/* Wrappers for numbered registers */
33#define SET_GLOBAL_REG_N(b, n, r, v) SET_GLOBAL_REG(b, ((r) + (n << 2)), (v))
34#define GET_GLOBAL_REG_N(b, n, r) GET_GLOBAL_REG(b, ((r) + (n << 2)))
35
36/* Field wrappers */
37#define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT)
38#define GET_CONTEXT_FIELD(b, c, r, F) \
39 GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT)
40
41#define SET_GLOBAL_FIELD(b, r, F, v) \
42 SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v))
43#define SET_CONTEXT_FIELD(b, c, r, F, v) \
44 SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v))
45
46#define GET_FIELD(addr, mask, shift) ((readl(addr) >> (shift)) & (mask))
47
48#define SET_FIELD(addr, mask, shift, v) \
49do { \
50 int t = readl(addr); \
51 writel((t & ~((mask) << (shift))) + (((v) & (mask)) << (shift)), addr);\
52} while (0)
53
54
55#define NUM_FL_PTE 4096
56#define NUM_SL_PTE 256
57#define NUM_TEX_CLASS 8
58
59/* First-level page table bits */
60#define FL_BASE_MASK 0xFFFFFC00
61#define FL_TYPE_TABLE (1 << 0)
62#define FL_TYPE_SECT (2 << 0)
63#define FL_SUPERSECTION (1 << 18)
64#define FL_AP_WRITE (1 << 10)
65#define FL_AP_READ (1 << 11)
66#define FL_SHARED (1 << 16)
67#define FL_BUFFERABLE (1 << 2)
68#define FL_CACHEABLE (1 << 3)
69#define FL_TEX0 (1 << 12)
70#define FL_OFFSET(va) (((va) & 0xFFF00000) >> 20)
71#define FL_NG (1 << 17)
72
73/* Second-level page table bits */
74#define SL_BASE_MASK_LARGE 0xFFFF0000
75#define SL_BASE_MASK_SMALL 0xFFFFF000
76#define SL_TYPE_LARGE (1 << 0)
77#define SL_TYPE_SMALL (2 << 0)
78#define SL_AP0 (1 << 4)
79#define SL_AP1 (2 << 4)
80#define SL_SHARED (1 << 10)
81#define SL_BUFFERABLE (1 << 2)
82#define SL_CACHEABLE (1 << 3)
83#define SL_TEX0 (1 << 6)
84#define SL_OFFSET(va) (((va) & 0xFF000) >> 12)
85#define SL_NG (1 << 11)
86
87/* Memory type and cache policy attributes */
88#define MT_SO 0
89#define MT_DEV 1
90#define MT_NORMAL 2
91#define CP_NONCACHED 0
92#define CP_WB_WA 1
93#define CP_WT 2
94#define CP_WB_NWA 3
95
96/* Global register setters / getters */
97#define SET_M2VCBR_N(b, N, v) SET_GLOBAL_REG_N(M2VCBR_N, N, (b), (v))
98#define SET_CBACR_N(b, N, v) SET_GLOBAL_REG_N(CBACR_N, N, (b), (v))
99#define SET_TLBRSW(b, v) SET_GLOBAL_REG(TLBRSW, (b), (v))
100#define SET_TLBTR0(b, v) SET_GLOBAL_REG(TLBTR0, (b), (v))
101#define SET_TLBTR1(b, v) SET_GLOBAL_REG(TLBTR1, (b), (v))
102#define SET_TLBTR2(b, v) SET_GLOBAL_REG(TLBTR2, (b), (v))
103#define SET_TESTBUSCR(b, v) SET_GLOBAL_REG(TESTBUSCR, (b), (v))
104#define SET_GLOBAL_TLBIALL(b, v) SET_GLOBAL_REG(GLOBAL_TLBIALL, (b), (v))
105#define SET_TLBIVMID(b, v) SET_GLOBAL_REG(TLBIVMID, (b), (v))
106#define SET_CR(b, v) SET_GLOBAL_REG(CR, (b), (v))
107#define SET_EAR(b, v) SET_GLOBAL_REG(EAR, (b), (v))
108#define SET_ESR(b, v) SET_GLOBAL_REG(ESR, (b), (v))
109#define SET_ESRRESTORE(b, v) SET_GLOBAL_REG(ESRRESTORE, (b), (v))
110#define SET_ESYNR0(b, v) SET_GLOBAL_REG(ESYNR0, (b), (v))
111#define SET_ESYNR1(b, v) SET_GLOBAL_REG(ESYNR1, (b), (v))
112#define SET_RPU_ACR(b, v) SET_GLOBAL_REG(RPU_ACR, (b), (v))
113
114#define GET_M2VCBR_N(b, N) GET_GLOBAL_REG_N(M2VCBR_N, N, (b))
115#define GET_CBACR_N(b, N) GET_GLOBAL_REG_N(CBACR_N, N, (b))
116#define GET_TLBTR0(b) GET_GLOBAL_REG(TLBTR0, (b))
117#define GET_TLBTR1(b) GET_GLOBAL_REG(TLBTR1, (b))
118#define GET_TLBTR2(b) GET_GLOBAL_REG(TLBTR2, (b))
119#define GET_TESTBUSCR(b) GET_GLOBAL_REG(TESTBUSCR, (b))
120#define GET_GLOBAL_TLBIALL(b) GET_GLOBAL_REG(GLOBAL_TLBIALL, (b))
121#define GET_TLBIVMID(b) GET_GLOBAL_REG(TLBIVMID, (b))
122#define GET_CR(b) GET_GLOBAL_REG(CR, (b))
123#define GET_EAR(b) GET_GLOBAL_REG(EAR, (b))
124#define GET_ESR(b) GET_GLOBAL_REG(ESR, (b))
125#define GET_ESRRESTORE(b) GET_GLOBAL_REG(ESRRESTORE, (b))
126#define GET_ESYNR0(b) GET_GLOBAL_REG(ESYNR0, (b))
127#define GET_ESYNR1(b) GET_GLOBAL_REG(ESYNR1, (b))
128#define GET_REV(b) GET_GLOBAL_REG(REV, (b))
129#define GET_IDR(b) GET_GLOBAL_REG(IDR, (b))
130#define GET_RPU_ACR(b) GET_GLOBAL_REG(RPU_ACR, (b))
131
132
133/* Context register setters/getters */
134#define SET_SCTLR(b, c, v) SET_CTX_REG(SCTLR, (b), (c), (v))
135#define SET_ACTLR(b, c, v) SET_CTX_REG(ACTLR, (b), (c), (v))
136#define SET_CONTEXTIDR(b, c, v) SET_CTX_REG(CONTEXTIDR, (b), (c), (v))
137#define SET_TTBR0(b, c, v) SET_CTX_REG(TTBR0, (b), (c), (v))
138#define SET_TTBR1(b, c, v) SET_CTX_REG(TTBR1, (b), (c), (v))
139#define SET_TTBCR(b, c, v) SET_CTX_REG(TTBCR, (b), (c), (v))
140#define SET_PAR(b, c, v) SET_CTX_REG(PAR, (b), (c), (v))
141#define SET_FSR(b, c, v) SET_CTX_REG(FSR, (b), (c), (v))
142#define SET_FSRRESTORE(b, c, v) SET_CTX_REG(FSRRESTORE, (b), (c), (v))
143#define SET_FAR(b, c, v) SET_CTX_REG(FAR, (b), (c), (v))
144#define SET_FSYNR0(b, c, v) SET_CTX_REG(FSYNR0, (b), (c), (v))
145#define SET_FSYNR1(b, c, v) SET_CTX_REG(FSYNR1, (b), (c), (v))
146#define SET_PRRR(b, c, v) SET_CTX_REG(PRRR, (b), (c), (v))
147#define SET_NMRR(b, c, v) SET_CTX_REG(NMRR, (b), (c), (v))
148#define SET_TLBLKCR(b, c, v) SET_CTX_REG(TLBLCKR, (b), (c), (v))
149#define SET_V2PSR(b, c, v) SET_CTX_REG(V2PSR, (b), (c), (v))
150#define SET_TLBFLPTER(b, c, v) SET_CTX_REG(TLBFLPTER, (b), (c), (v))
151#define SET_TLBSLPTER(b, c, v) SET_CTX_REG(TLBSLPTER, (b), (c), (v))
152#define SET_BFBCR(b, c, v) SET_CTX_REG(BFBCR, (b), (c), (v))
153#define SET_CTX_TLBIALL(b, c, v) SET_CTX_REG(CTX_TLBIALL, (b), (c), (v))
154#define SET_TLBIASID(b, c, v) SET_CTX_REG(TLBIASID, (b), (c), (v))
155#define SET_TLBIVA(b, c, v) SET_CTX_REG(TLBIVA, (b), (c), (v))
156#define SET_TLBIVAA(b, c, v) SET_CTX_REG(TLBIVAA, (b), (c), (v))
157#define SET_V2PPR(b, c, v) SET_CTX_REG(V2PPR, (b), (c), (v))
158#define SET_V2PPW(b, c, v) SET_CTX_REG(V2PPW, (b), (c), (v))
159#define SET_V2PUR(b, c, v) SET_CTX_REG(V2PUR, (b), (c), (v))
160#define SET_V2PUW(b, c, v) SET_CTX_REG(V2PUW, (b), (c), (v))
161#define SET_RESUME(b, c, v) SET_CTX_REG(RESUME, (b), (c), (v))
162
163#define GET_SCTLR(b, c) GET_CTX_REG(SCTLR, (b), (c))
164#define GET_ACTLR(b, c) GET_CTX_REG(ACTLR, (b), (c))
165#define GET_CONTEXTIDR(b, c) GET_CTX_REG(CONTEXTIDR, (b), (c))
166#define GET_TTBR0(b, c) GET_CTX_REG(TTBR0, (b), (c))
167#define GET_TTBR1(b, c) GET_CTX_REG(TTBR1, (b), (c))
168#define GET_TTBCR(b, c) GET_CTX_REG(TTBCR, (b), (c))
169#define GET_PAR(b, c) GET_CTX_REG(PAR, (b), (c))
170#define GET_FSR(b, c) GET_CTX_REG(FSR, (b), (c))
171#define GET_FSRRESTORE(b, c) GET_CTX_REG(FSRRESTORE, (b), (c))
172#define GET_FAR(b, c) GET_CTX_REG(FAR, (b), (c))
173#define GET_FSYNR0(b, c) GET_CTX_REG(FSYNR0, (b), (c))
174#define GET_FSYNR1(b, c) GET_CTX_REG(FSYNR1, (b), (c))
175#define GET_PRRR(b, c) GET_CTX_REG(PRRR, (b), (c))
176#define GET_NMRR(b, c) GET_CTX_REG(NMRR, (b), (c))
177#define GET_TLBLCKR(b, c) GET_CTX_REG(TLBLCKR, (b), (c))
178#define GET_V2PSR(b, c) GET_CTX_REG(V2PSR, (b), (c))
179#define GET_TLBFLPTER(b, c) GET_CTX_REG(TLBFLPTER, (b), (c))
180#define GET_TLBSLPTER(b, c) GET_CTX_REG(TLBSLPTER, (b), (c))
181#define GET_BFBCR(b, c) GET_CTX_REG(BFBCR, (b), (c))
182#define GET_CTX_TLBIALL(b, c) GET_CTX_REG(CTX_TLBIALL, (b), (c))
183#define GET_TLBIASID(b, c) GET_CTX_REG(TLBIASID, (b), (c))
184#define GET_TLBIVA(b, c) GET_CTX_REG(TLBIVA, (b), (c))
185#define GET_TLBIVAA(b, c) GET_CTX_REG(TLBIVAA, (b), (c))
186#define GET_V2PPR(b, c) GET_CTX_REG(V2PPR, (b), (c))
187#define GET_V2PPW(b, c) GET_CTX_REG(V2PPW, (b), (c))
188#define GET_V2PUR(b, c) GET_CTX_REG(V2PUR, (b), (c))
189#define GET_V2PUW(b, c) GET_CTX_REG(V2PUW, (b), (c))
190#define GET_RESUME(b, c) GET_CTX_REG(RESUME, (b), (c))
191
192
193/* Global field setters / getters */
194/* Global Field Setters: */
195/* CBACR_N */
196#define SET_RWVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID, v)
197#define SET_RWE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE, v)
198#define SET_RWGE(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE, v)
199#define SET_CBVMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID, v)
200#define SET_IRPTNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX, v)
201
202
203/* M2VCBR_N */
204#define SET_VMID(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID, v)
205#define SET_CBNDX(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX, v)
206#define SET_BYPASSD(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD, v)
207#define SET_BPRCOSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH, v)
208#define SET_BPRCISH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH, v)
209#define SET_BPRCNSH(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH, v)
210#define SET_BPSHCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG, v)
211#define SET_NSCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG, v)
212#define SET_BPMTCFG(b, n, v) SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG, v)
213#define SET_BPMEMTYPE(b, n, v) \
214 SET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE, v)
215
216
217/* CR */
218#define SET_RPUE(b, v) SET_GLOBAL_FIELD(b, CR, RPUE, v)
219#define SET_RPUERE(b, v) SET_GLOBAL_FIELD(b, CR, RPUERE, v)
220#define SET_RPUEIE(b, v) SET_GLOBAL_FIELD(b, CR, RPUEIE, v)
221#define SET_DCDEE(b, v) SET_GLOBAL_FIELD(b, CR, DCDEE, v)
222#define SET_CLIENTPD(b, v) SET_GLOBAL_FIELD(b, CR, CLIENTPD, v)
223#define SET_STALLD(b, v) SET_GLOBAL_FIELD(b, CR, STALLD, v)
224#define SET_TLBLKCRWE(b, v) SET_GLOBAL_FIELD(b, CR, TLBLKCRWE, v)
225#define SET_CR_TLBIALLCFG(b, v) SET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG, v)
226#define SET_TLBIVMIDCFG(b, v) SET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG, v)
227#define SET_CR_HUME(b, v) SET_GLOBAL_FIELD(b, CR, CR_HUME, v)
228
229
230/* ESR */
231#define SET_CFG(b, v) SET_GLOBAL_FIELD(b, ESR, CFG, v)
232#define SET_BYPASS(b, v) SET_GLOBAL_FIELD(b, ESR, BYPASS, v)
233#define SET_ESR_MULTI(b, v) SET_GLOBAL_FIELD(b, ESR, ESR_MULTI, v)
234
235
236/* ESYNR0 */
237#define SET_ESYNR0_AMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID, v)
238#define SET_ESYNR0_APID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID, v)
239#define SET_ESYNR0_ABID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID, v)
240#define SET_ESYNR0_AVMID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID, v)
241#define SET_ESYNR0_ATID(b, v) SET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID, v)
242
243
244/* ESYNR1 */
245#define SET_ESYNR1_AMEMTYPE(b, v) \
246 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE, v)
247#define SET_ESYNR1_ASHARED(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED, v)
248#define SET_ESYNR1_AINNERSHARED(b, v) \
249 SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED, v)
250#define SET_ESYNR1_APRIV(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV, v)
251#define SET_ESYNR1_APROTNS(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS, v)
252#define SET_ESYNR1_AINST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST, v)
253#define SET_ESYNR1_AWRITE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE, v)
254#define SET_ESYNR1_ABURST(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST, v)
255#define SET_ESYNR1_ALEN(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN, v)
256#define SET_ESYNR1_ASIZE(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE, v)
257#define SET_ESYNR1_ALOCK(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK, v)
258#define SET_ESYNR1_AOOO(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO, v)
259#define SET_ESYNR1_AFULL(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL, v)
260#define SET_ESYNR1_AC(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC, v)
261#define SET_ESYNR1_DCD(b, v) SET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD, v)
262
263
264/* TESTBUSCR */
265#define SET_TBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBE, v)
266#define SET_SPDMBE(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE, v)
267#define SET_WGSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL, v)
268#define SET_TBLSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL, v)
269#define SET_TBHSEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL, v)
270#define SET_SPDM0SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL, v)
271#define SET_SPDM1SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL, v)
272#define SET_SPDM2SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL, v)
273#define SET_SPDM3SEL(b, v) SET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL, v)
274
275
276/* TLBIVMID */
277#define SET_TLBIVMID_VMID(b, v) SET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID, v)
278
279
280/* TLBRSW */
281#define SET_TLBRSW_INDEX(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBRSW_INDEX, v)
282#define SET_TLBBFBS(b, v) SET_GLOBAL_FIELD(b, TLBRSW, TLBBFBS, v)
283
284
285/* TLBTR0 */
286#define SET_PR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PR, v)
287#define SET_PW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, PW, v)
288#define SET_UR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UR, v)
289#define SET_UW(b, v) SET_GLOBAL_FIELD(b, TLBTR0, UW, v)
290#define SET_XN(b, v) SET_GLOBAL_FIELD(b, TLBTR0, XN, v)
291#define SET_NSDESC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, NSDESC, v)
292#define SET_ISH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, ISH, v)
293#define SET_SH(b, v) SET_GLOBAL_FIELD(b, TLBTR0, SH, v)
294#define SET_MT(b, v) SET_GLOBAL_FIELD(b, TLBTR0, MT, v)
295#define SET_DPSIZR(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZR, v)
296#define SET_DPSIZC(b, v) SET_GLOBAL_FIELD(b, TLBTR0, DPSIZC, v)
297
298
299/* TLBTR1 */
300#define SET_TLBTR1_VMID(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID, v)
301#define SET_TLBTR1_PA(b, v) SET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA, v)
302
303
304/* TLBTR2 */
305#define SET_TLBTR2_ASID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID, v)
306#define SET_TLBTR2_V(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V, v)
307#define SET_TLBTR2_NSTID(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID, v)
308#define SET_TLBTR2_NV(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV, v)
309#define SET_TLBTR2_VA(b, v) SET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA, v)
310
311
312/* Global Field Getters */
313/* CBACR_N */
314#define GET_RWVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWVMID)
315#define GET_RWE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWE)
316#define GET_RWGE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), RWGE)
317#define GET_CBVMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), CBVMID)
318#define GET_IRPTNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(CBACR_N), IRPTNDX)
319
320
321/* M2VCBR_N */
322#define GET_VMID(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), VMID)
323#define GET_CBNDX(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), CBNDX)
324#define GET_BYPASSD(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BYPASSD)
325#define GET_BPRCOSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCOSH)
326#define GET_BPRCISH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCISH)
327#define GET_BPRCNSH(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPRCNSH)
328#define GET_BPSHCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPSHCFG)
329#define GET_NSCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), NSCFG)
330#define GET_BPMTCFG(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMTCFG)
331#define GET_BPMEMTYPE(b, n) GET_GLOBAL_FIELD(b, (n<<2)|(M2VCBR_N), BPMEMTYPE)
332
333
334/* CR */
335#define GET_RPUE(b) GET_GLOBAL_FIELD(b, CR, RPUE)
336#define GET_RPUERE(b) GET_GLOBAL_FIELD(b, CR, RPUERE)
337#define GET_RPUEIE(b) GET_GLOBAL_FIELD(b, CR, RPUEIE)
338#define GET_DCDEE(b) GET_GLOBAL_FIELD(b, CR, DCDEE)
339#define GET_CLIENTPD(b) GET_GLOBAL_FIELD(b, CR, CLIENTPD)
340#define GET_STALLD(b) GET_GLOBAL_FIELD(b, CR, STALLD)
341#define GET_TLBLKCRWE(b) GET_GLOBAL_FIELD(b, CR, TLBLKCRWE)
342#define GET_CR_TLBIALLCFG(b) GET_GLOBAL_FIELD(b, CR, CR_TLBIALLCFG)
343#define GET_TLBIVMIDCFG(b) GET_GLOBAL_FIELD(b, CR, TLBIVMIDCFG)
344#define GET_CR_HUME(b) GET_GLOBAL_FIELD(b, CR, CR_HUME)
345
346
347/* ESR */
348#define GET_CFG(b) GET_GLOBAL_FIELD(b, ESR, CFG)
349#define GET_BYPASS(b) GET_GLOBAL_FIELD(b, ESR, BYPASS)
350#define GET_ESR_MULTI(b) GET_GLOBAL_FIELD(b, ESR, ESR_MULTI)
351
352
353/* ESYNR0 */
354#define GET_ESYNR0_AMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AMID)
355#define GET_ESYNR0_APID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_APID)
356#define GET_ESYNR0_ABID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ABID)
357#define GET_ESYNR0_AVMID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_AVMID)
358#define GET_ESYNR0_ATID(b) GET_GLOBAL_FIELD(b, ESYNR0, ESYNR0_ATID)
359
360
361/* ESYNR1 */
362#define GET_ESYNR1_AMEMTYPE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AMEMTYPE)
363#define GET_ESYNR1_ASHARED(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASHARED)
364#define GET_ESYNR1_AINNERSHARED(b) \
365 GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINNERSHARED)
366#define GET_ESYNR1_APRIV(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APRIV)
367#define GET_ESYNR1_APROTNS(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_APROTNS)
368#define GET_ESYNR1_AINST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AINST)
369#define GET_ESYNR1_AWRITE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AWRITE)
370#define GET_ESYNR1_ABURST(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ABURST)
371#define GET_ESYNR1_ALEN(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALEN)
372#define GET_ESYNR1_ASIZE(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ASIZE)
373#define GET_ESYNR1_ALOCK(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_ALOCK)
374#define GET_ESYNR1_AOOO(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AOOO)
375#define GET_ESYNR1_AFULL(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AFULL)
376#define GET_ESYNR1_AC(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_AC)
377#define GET_ESYNR1_DCD(b) GET_GLOBAL_FIELD(b, ESYNR1, ESYNR1_DCD)
378
379
380/* IDR */
381#define GET_NM2VCBMT(b) GET_GLOBAL_FIELD(b, IDR, NM2VCBMT)
382#define GET_HTW(b) GET_GLOBAL_FIELD(b, IDR, HTW)
383#define GET_HUM(b) GET_GLOBAL_FIELD(b, IDR, HUM)
384#define GET_TLBSIZE(b) GET_GLOBAL_FIELD(b, IDR, TLBSIZE)
385#define GET_NCB(b) GET_GLOBAL_FIELD(b, IDR, NCB)
386#define GET_NIRPT(b) GET_GLOBAL_FIELD(b, IDR, NIRPT)
387
388
389/* REV */
390#define GET_MAJOR(b) GET_GLOBAL_FIELD(b, REV, MAJOR)
391#define GET_MINOR(b) GET_GLOBAL_FIELD(b, REV, MINOR)
392
393
394/* TESTBUSCR */
395#define GET_TBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBE)
396#define GET_SPDMBE(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDMBE)
397#define GET_WGSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, WGSEL)
398#define GET_TBLSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBLSEL)
399#define GET_TBHSEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, TBHSEL)
400#define GET_SPDM0SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM0SEL)
401#define GET_SPDM1SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM1SEL)
402#define GET_SPDM2SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM2SEL)
403#define GET_SPDM3SEL(b) GET_GLOBAL_FIELD(b, TESTBUSCR, SPDM3SEL)
404
405
406/* TLBIVMID */
407#define GET_TLBIVMID_VMID(b) GET_GLOBAL_FIELD(b, TLBIVMID, TLBIVMID_VMID)
408
409
410/* TLBTR0 */
411#define GET_PR(b) GET_GLOBAL_FIELD(b, TLBTR0, PR)
412#define GET_PW(b) GET_GLOBAL_FIELD(b, TLBTR0, PW)
413#define GET_UR(b) GET_GLOBAL_FIELD(b, TLBTR0, UR)
414#define GET_UW(b) GET_GLOBAL_FIELD(b, TLBTR0, UW)
415#define GET_XN(b) GET_GLOBAL_FIELD(b, TLBTR0, XN)
416#define GET_NSDESC(b) GET_GLOBAL_FIELD(b, TLBTR0, NSDESC)
417#define GET_ISH(b) GET_GLOBAL_FIELD(b, TLBTR0, ISH)
418#define GET_SH(b) GET_GLOBAL_FIELD(b, TLBTR0, SH)
419#define GET_MT(b) GET_GLOBAL_FIELD(b, TLBTR0, MT)
420#define GET_DPSIZR(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZR)
421#define GET_DPSIZC(b) GET_GLOBAL_FIELD(b, TLBTR0, DPSIZC)
422
423
424/* TLBTR1 */
425#define GET_TLBTR1_VMID(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_VMID)
426#define GET_TLBTR1_PA(b) GET_GLOBAL_FIELD(b, TLBTR1, TLBTR1_PA)
427
428
429/* TLBTR2 */
430#define GET_TLBTR2_ASID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_ASID)
431#define GET_TLBTR2_V(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_V)
432#define GET_TLBTR2_NSTID(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NSTID)
433#define GET_TLBTR2_NV(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_NV)
434#define GET_TLBTR2_VA(b) GET_GLOBAL_FIELD(b, TLBTR2, TLBTR2_VA)
435
436
437/* Context Register setters / getters */
438/* Context Register setters */
439/* ACTLR */
440#define SET_CFERE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFERE, v)
441#define SET_CFEIE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFEIE, v)
442#define SET_PTSHCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG, v)
443#define SET_RCOSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCOSH, v)
444#define SET_RCISH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCISH, v)
445#define SET_RCNSH(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, RCNSH, v)
446#define SET_PRIVCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG, v)
447#define SET_DNA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNA, v)
448#define SET_DNLV2PA(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA, v)
449#define SET_TLBMCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG, v)
450#define SET_CFCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, CFCFG, v)
451#define SET_TIPCF(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, TIPCF, v)
452#define SET_V2PCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG, v)
453#define SET_HUME(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, HUME, v)
454#define SET_PTMTCFG(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG, v)
455#define SET_PTMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE, v)
456
457
458/* BFBCR */
459#define SET_BFBDFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE, v)
460#define SET_BFBSFE(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE, v)
461#define SET_SFVS(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SFVS, v)
462#define SET_FLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, FLVIC, v)
463#define SET_SLVIC(b, c, v) SET_CONTEXT_FIELD(b, c, BFBCR, SLVIC, v)
464
465
466/* CONTEXTIDR */
467#define SET_CONTEXTIDR_ASID(b, c, v) \
468 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID, v)
469#define SET_CONTEXTIDR_PROCID(b, c, v) \
470 SET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID, v)
471
472
473/* FSR */
474#define SET_TF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TF, v)
475#define SET_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, AFF, v)
476#define SET_APF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, APF, v)
477#define SET_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, TLBMF, v)
478#define SET_HTWDEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWDEEF, v)
479#define SET_HTWSEEF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, HTWSEEF, v)
480#define SET_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MHF, v)
481#define SET_SL(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SL, v)
482#define SET_SS(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, SS, v)
483#define SET_MULTI(b, c, v) SET_CONTEXT_FIELD(b, c, FSR, MULTI, v)
484
485
486/* FSYNR0 */
487#define SET_AMID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, AMID, v)
488#define SET_APID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, APID, v)
489#define SET_ABID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ABID, v)
490#define SET_ATID(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR0, ATID, v)
491
492
493/* FSYNR1 */
494#define SET_AMEMTYPE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE, v)
495#define SET_ASHARED(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED, v)
496#define SET_AINNERSHARED(b, c, v) \
497 SET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED, v)
498#define SET_APRIV(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APRIV, v)
499#define SET_APROTNS(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS, v)
500#define SET_AINST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AINST, v)
501#define SET_AWRITE(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE, v)
502#define SET_ABURST(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ABURST, v)
503#define SET_ALEN(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALEN, v)
504#define SET_FSYNR1_ASIZE(b, c, v) \
505 SET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE, v)
506#define SET_ALOCK(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK, v)
507#define SET_AFULL(b, c, v) SET_CONTEXT_FIELD(b, c, FSYNR1, AFULL, v)
508
509
510/* NMRR */
511#define SET_ICPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC0, v)
512#define SET_ICPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC1, v)
513#define SET_ICPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC2, v)
514#define SET_ICPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC3, v)
515#define SET_ICPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC4, v)
516#define SET_ICPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC5, v)
517#define SET_ICPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC6, v)
518#define SET_ICPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, ICPC7, v)
519#define SET_OCPC0(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC0, v)
520#define SET_OCPC1(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC1, v)
521#define SET_OCPC2(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC2, v)
522#define SET_OCPC3(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC3, v)
523#define SET_OCPC4(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC4, v)
524#define SET_OCPC5(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC5, v)
525#define SET_OCPC6(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC6, v)
526#define SET_OCPC7(b, c, v) SET_CONTEXT_FIELD(b, c, NMRR, OCPC7, v)
527
528
529/* PAR */
530#define SET_FAULT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT, v)
531
532#define SET_FAULT_TF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TF, v)
533#define SET_FAULT_AFF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF, v)
534#define SET_FAULT_APF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_APF, v)
535#define SET_FAULT_TLBMF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF, v)
536#define SET_FAULT_HTWDEEF(b, c, v) \
537 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF, v)
538#define SET_FAULT_HTWSEEF(b, c, v) \
539 SET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF, v)
540#define SET_FAULT_MHF(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF, v)
541#define SET_FAULT_SL(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SL, v)
542#define SET_FAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, FAULT_SS, v)
543
544#define SET_NOFAULT_SS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SS, v)
545#define SET_NOFAULT_MT(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_MT, v)
546#define SET_NOFAULT_SH(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_SH, v)
547#define SET_NOFAULT_NS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NS, v)
548#define SET_NOFAULT_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NOFAULT_NOS, v)
549#define SET_NPFAULT_PA(b, c, v) SET_CONTEXT_FIELD(b, c, PAR, NPFAULT_PA, v)
550
551
552/* PRRR */
553#define SET_MTC0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC0, v)
554#define SET_MTC1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC1, v)
555#define SET_MTC2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC2, v)
556#define SET_MTC3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC3, v)
557#define SET_MTC4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC4, v)
558#define SET_MTC5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC5, v)
559#define SET_MTC6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC6, v)
560#define SET_MTC7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, MTC7, v)
561#define SET_SHDSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH0, v)
562#define SET_SHDSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHDSH1, v)
563#define SET_SHNMSH0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0, v)
564#define SET_SHNMSH1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1, v)
565#define SET_NOS0(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS0, v)
566#define SET_NOS1(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS1, v)
567#define SET_NOS2(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS2, v)
568#define SET_NOS3(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS3, v)
569#define SET_NOS4(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS4, v)
570#define SET_NOS5(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS5, v)
571#define SET_NOS6(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS6, v)
572#define SET_NOS7(b, c, v) SET_CONTEXT_FIELD(b, c, PRRR, NOS7, v)
573
574
575/* RESUME */
576#define SET_TNR(b, c, v) SET_CONTEXT_FIELD(b, c, RESUME, TNR, v)
577
578
579/* SCTLR */
580#define SET_M(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, M, v)
581#define SET_TRE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, TRE, v)
582#define SET_AFE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFE, v)
583#define SET_HAF(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, HAF, v)
584#define SET_BE(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, BE, v)
585#define SET_AFFD(b, c, v) SET_CONTEXT_FIELD(b, c, SCTLR, AFFD, v)
586
587
588/* TLBLKCR */
589#define SET_LKE(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, LKE, v)
590#define SET_TLBLKCR_TLBIALLCFG(b, c, v) \
591 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG, v)
592#define SET_TLBIASIDCFG(b, c, v) \
593 SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG, v)
594#define SET_TLBIVAACFG(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG, v)
595#define SET_FLOOR(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR, v)
596#define SET_VICTIM(b, c, v) SET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM, v)
597
598
599/* TTBCR */
600#define SET_N(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, N, v)
601#define SET_PD0(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD0, v)
602#define SET_PD1(b, c, v) SET_CONTEXT_FIELD(b, c, TTBCR, PD1, v)
603
604
605/* TTBR0 */
606#define SET_TTBR0_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH, v)
607#define SET_TTBR0_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH, v)
608#define SET_TTBR0_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN, v)
609#define SET_TTBR0_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS, v)
610#define SET_TTBR0_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL, v)
611#define SET_TTBR0_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA, v)
612
613
614/* TTBR1 */
615#define SET_TTBR1_IRGNH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH, v)
616#define SET_TTBR1_SH(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH, v)
617#define SET_TTBR1_ORGN(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN, v)
618#define SET_TTBR1_NOS(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS, v)
619#define SET_TTBR1_IRGNL(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL, v)
620#define SET_TTBR1_PA(b, c, v) SET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA, v)
621
622
623/* V2PSR */
624#define SET_HIT(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, HIT, v)
625#define SET_INDEX(b, c, v) SET_CONTEXT_FIELD(b, c, V2PSR, INDEX, v)
626
627
628/* Context Register getters */
629/* ACTLR */
630#define GET_CFERE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFERE)
631#define GET_CFEIE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFEIE)
632#define GET_PTSHCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTSHCFG)
633#define GET_RCOSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCOSH)
634#define GET_RCISH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCISH)
635#define GET_RCNSH(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, RCNSH)
636#define GET_PRIVCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PRIVCFG)
637#define GET_DNA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNA)
638#define GET_DNLV2PA(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, DNLV2PA)
639#define GET_TLBMCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TLBMCFG)
640#define GET_CFCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, CFCFG)
641#define GET_TIPCF(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, TIPCF)
642#define GET_V2PCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, V2PCFG)
643#define GET_HUME(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, HUME)
644#define GET_PTMTCFG(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMTCFG)
645#define GET_PTMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, ACTLR, PTMEMTYPE)
646
647/* BFBCR */
648#define GET_BFBDFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBDFE)
649#define GET_BFBSFE(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, BFBSFE)
650#define GET_SFVS(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SFVS)
651#define GET_FLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, FLVIC)
652#define GET_SLVIC(b, c) GET_CONTEXT_FIELD(b, c, BFBCR, SLVIC)
653
654
655/* CONTEXTIDR */
656#define GET_CONTEXTIDR_ASID(b, c) \
657 GET_CONTEXT_FIELD(b, c, CONTEXTIDR, CONTEXTIDR_ASID)
658#define GET_CONTEXTIDR_PROCID(b, c) GET_CONTEXT_FIELD(b, c, CONTEXTIDR, PROCID)
659
660
661/* FSR */
662#define GET_TF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TF)
663#define GET_AFF(b, c) GET_CONTEXT_FIELD(b, c, FSR, AFF)
664#define GET_APF(b, c) GET_CONTEXT_FIELD(b, c, FSR, APF)
665#define GET_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, FSR, TLBMF)
666#define GET_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWDEEF)
667#define GET_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, FSR, HTWSEEF)
668#define GET_MHF(b, c) GET_CONTEXT_FIELD(b, c, FSR, MHF)
669#define GET_SL(b, c) GET_CONTEXT_FIELD(b, c, FSR, SL)
670#define GET_SS(b, c) GET_CONTEXT_FIELD(b, c, FSR, SS)
671#define GET_MULTI(b, c) GET_CONTEXT_FIELD(b, c, FSR, MULTI)
672
673
674/* FSYNR0 */
675#define GET_AMID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, AMID)
676#define GET_APID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, APID)
677#define GET_ABID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ABID)
678#define GET_ATID(b, c) GET_CONTEXT_FIELD(b, c, FSYNR0, ATID)
679
680
681/* FSYNR1 */
682#define GET_AMEMTYPE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AMEMTYPE)
683#define GET_ASHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ASHARED)
684#define GET_AINNERSHARED(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINNERSHARED)
685#define GET_APRIV(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APRIV)
686#define GET_APROTNS(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, APROTNS)
687#define GET_AINST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AINST)
688#define GET_AWRITE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AWRITE)
689#define GET_ABURST(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ABURST)
690#define GET_ALEN(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALEN)
691#define GET_FSYNR1_ASIZE(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, FSYNR1_ASIZE)
692#define GET_ALOCK(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, ALOCK)
693#define GET_AFULL(b, c) GET_CONTEXT_FIELD(b, c, FSYNR1, AFULL)
694
695
696/* NMRR */
697#define GET_ICPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC0)
698#define GET_ICPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC1)
699#define GET_ICPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC2)
700#define GET_ICPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC3)
701#define GET_ICPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC4)
702#define GET_ICPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC5)
703#define GET_ICPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC6)
704#define GET_ICPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, ICPC7)
705#define GET_OCPC0(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC0)
706#define GET_OCPC1(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC1)
707#define GET_OCPC2(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC2)
708#define GET_OCPC3(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC3)
709#define GET_OCPC4(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC4)
710#define GET_OCPC5(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC5)
711#define GET_OCPC6(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC6)
712#define GET_OCPC7(b, c) GET_CONTEXT_FIELD(b, c, NMRR, OCPC7)
713#define NMRR_ICP(nmrr, n) (((nmrr) & (3 << ((n) * 2))) >> ((n) * 2))
714#define NMRR_OCP(nmrr, n) (((nmrr) & (3 << ((n) * 2 + 16))) >> \
715 ((n) * 2 + 16))
716
717/* PAR */
718#define GET_FAULT(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT)
719
720#define GET_FAULT_TF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TF)
721#define GET_FAULT_AFF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_AFF)
722#define GET_FAULT_APF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_APF)
723#define GET_FAULT_TLBMF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_TLBMF)
724#define GET_FAULT_HTWDEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWDEEF)
725#define GET_FAULT_HTWSEEF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_HTWSEEF)
726#define GET_FAULT_MHF(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_MHF)
727#define GET_FAULT_SL(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SL)
728#define GET_FAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, FAULT_SS)
729
730#define GET_NOFAULT_SS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SS)
731#define GET_NOFAULT_MT(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_MT)
732#define GET_NOFAULT_SH(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_SH)
733#define GET_NOFAULT_NS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NS)
734#define GET_NOFAULT_NOS(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NOFAULT_NOS)
735#define GET_NPFAULT_PA(b, c) GET_CONTEXT_FIELD(b, c, PAR, PAR_NPFAULT_PA)
736
737
738/* PRRR */
739#define GET_MTC0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC0)
740#define GET_MTC1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC1)
741#define GET_MTC2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC2)
742#define GET_MTC3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC3)
743#define GET_MTC4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC4)
744#define GET_MTC5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC5)
745#define GET_MTC6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC6)
746#define GET_MTC7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, MTC7)
747#define GET_SHDSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH0)
748#define GET_SHDSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHDSH1)
749#define GET_SHNMSH0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH0)
750#define GET_SHNMSH1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, SHNMSH1)
751#define GET_NOS0(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS0)
752#define GET_NOS1(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS1)
753#define GET_NOS2(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS2)
754#define GET_NOS3(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS3)
755#define GET_NOS4(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS4)
756#define GET_NOS5(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS5)
757#define GET_NOS6(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS6)
758#define GET_NOS7(b, c) GET_CONTEXT_FIELD(b, c, PRRR, NOS7)
759#define PRRR_NOS(prrr, n) ((prrr) & (1 << ((n) + 24)) ? 1 : 0)
760#define PRRR_MT(prrr, n) ((((prrr) & (3 << ((n) * 2))) >> ((n) * 2)))
761
762
763/* RESUME */
764#define GET_TNR(b, c) GET_CONTEXT_FIELD(b, c, RESUME, TNR)
765
766
767/* SCTLR */
768#define GET_M(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, M)
769#define GET_TRE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, TRE)
770#define GET_AFE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFE)
771#define GET_HAF(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, HAF)
772#define GET_BE(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, BE)
773#define GET_AFFD(b, c) GET_CONTEXT_FIELD(b, c, SCTLR, AFFD)
774
775
776/* TLBLKCR */
777#define GET_LKE(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, LKE)
778#define GET_TLBLCKR_TLBIALLCFG(b, c) \
779 GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBLCKR_TLBIALLCFG)
780#define GET_TLBIASIDCFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIASIDCFG)
781#define GET_TLBIVAACFG(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, TLBIVAACFG)
782#define GET_FLOOR(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, FLOOR)
783#define GET_VICTIM(b, c) GET_CONTEXT_FIELD(b, c, TLBLKCR, VICTIM)
784
785
786/* TTBCR */
787#define GET_N(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, N)
788#define GET_PD0(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD0)
789#define GET_PD1(b, c) GET_CONTEXT_FIELD(b, c, TTBCR, PD1)
790
791
792/* TTBR0 */
793#define GET_TTBR0_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNH)
794#define GET_TTBR0_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_SH)
795#define GET_TTBR0_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_ORGN)
796#define GET_TTBR0_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_NOS)
797#define GET_TTBR0_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_IRGNL)
798#define GET_TTBR0_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR0, TTBR0_PA)
799
800
801/* TTBR1 */
802#define GET_TTBR1_IRGNH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNH)
803#define GET_TTBR1_SH(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_SH)
804#define GET_TTBR1_ORGN(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_ORGN)
805#define GET_TTBR1_NOS(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_NOS)
806#define GET_TTBR1_IRGNL(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_IRGNL)
807#define GET_TTBR1_PA(b, c) GET_CONTEXT_FIELD(b, c, TTBR1, TTBR1_PA)
808
809
810/* V2PSR */
811#define GET_HIT(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, HIT)
812#define GET_INDEX(b, c) GET_CONTEXT_FIELD(b, c, V2PSR, INDEX)
813
814
815/* Global Registers */
816#define M2VCBR_N (0xFF000)
817#define CBACR_N (0xFF800)
818#define TLBRSW (0xFFE00)
819#define TLBTR0 (0xFFE80)
820#define TLBTR1 (0xFFE84)
821#define TLBTR2 (0xFFE88)
822#define TESTBUSCR (0xFFE8C)
823#define GLOBAL_TLBIALL (0xFFF00)
824#define TLBIVMID (0xFFF04)
825#define CR (0xFFF80)
826#define EAR (0xFFF84)
827#define ESR (0xFFF88)
828#define ESRRESTORE (0xFFF8C)
829#define ESYNR0 (0xFFF90)
830#define ESYNR1 (0xFFF94)
831#define REV (0xFFFF4)
832#define IDR (0xFFFF8)
833#define RPU_ACR (0xFFFFC)
834
835
836/* Context Bank Registers */
837#define SCTLR (0x000)
838#define ACTLR (0x004)
839#define CONTEXTIDR (0x008)
840#define TTBR0 (0x010)
841#define TTBR1 (0x014)
842#define TTBCR (0x018)
843#define PAR (0x01C)
844#define FSR (0x020)
845#define FSRRESTORE (0x024)
846#define FAR (0x028)
847#define FSYNR0 (0x02C)
848#define FSYNR1 (0x030)
849#define PRRR (0x034)
850#define NMRR (0x038)
851#define TLBLCKR (0x03C)
852#define V2PSR (0x040)
853#define TLBFLPTER (0x044)
854#define TLBSLPTER (0x048)
855#define BFBCR (0x04C)
856#define CTX_TLBIALL (0x800)
857#define TLBIASID (0x804)
858#define TLBIVA (0x808)
859#define TLBIVAA (0x80C)
860#define V2PPR (0x810)
861#define V2PPW (0x814)
862#define V2PUR (0x818)
863#define V2PUW (0x81C)
864#define RESUME (0x820)
865
866
867/* Global Register Fields */
868/* CBACRn */
869#define RWVMID (RWVMID_MASK << RWVMID_SHIFT)
870#define RWE (RWE_MASK << RWE_SHIFT)
871#define RWGE (RWGE_MASK << RWGE_SHIFT)
872#define CBVMID (CBVMID_MASK << CBVMID_SHIFT)
873#define IRPTNDX (IRPTNDX_MASK << IRPTNDX_SHIFT)
874
875
876/* CR */
877#define RPUE (RPUE_MASK << RPUE_SHIFT)
878#define RPUERE (RPUERE_MASK << RPUERE_SHIFT)
879#define RPUEIE (RPUEIE_MASK << RPUEIE_SHIFT)
880#define DCDEE (DCDEE_MASK << DCDEE_SHIFT)
881#define CLIENTPD (CLIENTPD_MASK << CLIENTPD_SHIFT)
882#define STALLD (STALLD_MASK << STALLD_SHIFT)
883#define TLBLKCRWE (TLBLKCRWE_MASK << TLBLKCRWE_SHIFT)
884#define CR_TLBIALLCFG (CR_TLBIALLCFG_MASK << CR_TLBIALLCFG_SHIFT)
885#define TLBIVMIDCFG (TLBIVMIDCFG_MASK << TLBIVMIDCFG_SHIFT)
886#define CR_HUME (CR_HUME_MASK << CR_HUME_SHIFT)
887
888
889/* ESR */
890#define CFG (CFG_MASK << CFG_SHIFT)
891#define BYPASS (BYPASS_MASK << BYPASS_SHIFT)
892#define ESR_MULTI (ESR_MULTI_MASK << ESR_MULTI_SHIFT)
893
894
895/* ESYNR0 */
896#define ESYNR0_AMID (ESYNR0_AMID_MASK << ESYNR0_AMID_SHIFT)
897#define ESYNR0_APID (ESYNR0_APID_MASK << ESYNR0_APID_SHIFT)
898#define ESYNR0_ABID (ESYNR0_ABID_MASK << ESYNR0_ABID_SHIFT)
899#define ESYNR0_AVMID (ESYNR0_AVMID_MASK << ESYNR0_AVMID_SHIFT)
900#define ESYNR0_ATID (ESYNR0_ATID_MASK << ESYNR0_ATID_SHIFT)
901
902
903/* ESYNR1 */
904#define ESYNR1_AMEMTYPE (ESYNR1_AMEMTYPE_MASK << ESYNR1_AMEMTYPE_SHIFT)
905#define ESYNR1_ASHARED (ESYNR1_ASHARED_MASK << ESYNR1_ASHARED_SHIFT)
906#define ESYNR1_AINNERSHARED (ESYNR1_AINNERSHARED_MASK<< \
907 ESYNR1_AINNERSHARED_SHIFT)
908#define ESYNR1_APRIV (ESYNR1_APRIV_MASK << ESYNR1_APRIV_SHIFT)
909#define ESYNR1_APROTNS (ESYNR1_APROTNS_MASK << ESYNR1_APROTNS_SHIFT)
910#define ESYNR1_AINST (ESYNR1_AINST_MASK << ESYNR1_AINST_SHIFT)
911#define ESYNR1_AWRITE (ESYNR1_AWRITE_MASK << ESYNR1_AWRITE_SHIFT)
912#define ESYNR1_ABURST (ESYNR1_ABURST_MASK << ESYNR1_ABURST_SHIFT)
913#define ESYNR1_ALEN (ESYNR1_ALEN_MASK << ESYNR1_ALEN_SHIFT)
914#define ESYNR1_ASIZE (ESYNR1_ASIZE_MASK << ESYNR1_ASIZE_SHIFT)
915#define ESYNR1_ALOCK (ESYNR1_ALOCK_MASK << ESYNR1_ALOCK_SHIFT)
916#define ESYNR1_AOOO (ESYNR1_AOOO_MASK << ESYNR1_AOOO_SHIFT)
917#define ESYNR1_AFULL (ESYNR1_AFULL_MASK << ESYNR1_AFULL_SHIFT)
918#define ESYNR1_AC (ESYNR1_AC_MASK << ESYNR1_AC_SHIFT)
919#define ESYNR1_DCD (ESYNR1_DCD_MASK << ESYNR1_DCD_SHIFT)
920
921
922/* IDR */
923#define NM2VCBMT (NM2VCBMT_MASK << NM2VCBMT_SHIFT)
924#define HTW (HTW_MASK << HTW_SHIFT)
925#define HUM (HUM_MASK << HUM_SHIFT)
926#define TLBSIZE (TLBSIZE_MASK << TLBSIZE_SHIFT)
927#define NCB (NCB_MASK << NCB_SHIFT)
928#define NIRPT (NIRPT_MASK << NIRPT_SHIFT)
929
930
931/* M2VCBRn */
932#define VMID (VMID_MASK << VMID_SHIFT)
933#define CBNDX (CBNDX_MASK << CBNDX_SHIFT)
934#define BYPASSD (BYPASSD_MASK << BYPASSD_SHIFT)
935#define BPRCOSH (BPRCOSH_MASK << BPRCOSH_SHIFT)
936#define BPRCISH (BPRCISH_MASK << BPRCISH_SHIFT)
937#define BPRCNSH (BPRCNSH_MASK << BPRCNSH_SHIFT)
938#define BPSHCFG (BPSHCFG_MASK << BPSHCFG_SHIFT)
939#define NSCFG (NSCFG_MASK << NSCFG_SHIFT)
940#define BPMTCFG (BPMTCFG_MASK << BPMTCFG_SHIFT)
941#define BPMEMTYPE (BPMEMTYPE_MASK << BPMEMTYPE_SHIFT)
942
943
944/* REV */
945#define IDR_MINOR (MINOR_MASK << MINOR_SHIFT)
946#define IDR_MAJOR (MAJOR_MASK << MAJOR_SHIFT)
947
948
949/* TESTBUSCR */
950#define TBE (TBE_MASK << TBE_SHIFT)
951#define SPDMBE (SPDMBE_MASK << SPDMBE_SHIFT)
952#define WGSEL (WGSEL_MASK << WGSEL_SHIFT)
953#define TBLSEL (TBLSEL_MASK << TBLSEL_SHIFT)
954#define TBHSEL (TBHSEL_MASK << TBHSEL_SHIFT)
955#define SPDM0SEL (SPDM0SEL_MASK << SPDM0SEL_SHIFT)
956#define SPDM1SEL (SPDM1SEL_MASK << SPDM1SEL_SHIFT)
957#define SPDM2SEL (SPDM2SEL_MASK << SPDM2SEL_SHIFT)
958#define SPDM3SEL (SPDM3SEL_MASK << SPDM3SEL_SHIFT)
959
960
961/* TLBIVMID */
962#define TLBIVMID_VMID (TLBIVMID_VMID_MASK << TLBIVMID_VMID_SHIFT)
963
964
965/* TLBRSW */
966#define TLBRSW_INDEX (TLBRSW_INDEX_MASK << TLBRSW_INDEX_SHIFT)
967#define TLBBFBS (TLBBFBS_MASK << TLBBFBS_SHIFT)
968
969
970/* TLBTR0 */
971#define PR (PR_MASK << PR_SHIFT)
972#define PW (PW_MASK << PW_SHIFT)
973#define UR (UR_MASK << UR_SHIFT)
974#define UW (UW_MASK << UW_SHIFT)
975#define XN (XN_MASK << XN_SHIFT)
976#define NSDESC (NSDESC_MASK << NSDESC_SHIFT)
977#define ISH (ISH_MASK << ISH_SHIFT)
978#define SH (SH_MASK << SH_SHIFT)
979#define MT (MT_MASK << MT_SHIFT)
980#define DPSIZR (DPSIZR_MASK << DPSIZR_SHIFT)
981#define DPSIZC (DPSIZC_MASK << DPSIZC_SHIFT)
982
983
984/* TLBTR1 */
985#define TLBTR1_VMID (TLBTR1_VMID_MASK << TLBTR1_VMID_SHIFT)
986#define TLBTR1_PA (TLBTR1_PA_MASK << TLBTR1_PA_SHIFT)
987
988
989/* TLBTR2 */
990#define TLBTR2_ASID (TLBTR2_ASID_MASK << TLBTR2_ASID_SHIFT)
991#define TLBTR2_V (TLBTR2_V_MASK << TLBTR2_V_SHIFT)
992#define TLBTR2_NSTID (TLBTR2_NSTID_MASK << TLBTR2_NSTID_SHIFT)
993#define TLBTR2_NV (TLBTR2_NV_MASK << TLBTR2_NV_SHIFT)
994#define TLBTR2_VA (TLBTR2_VA_MASK << TLBTR2_VA_SHIFT)
995
996
997/* Context Register Fields */
998/* ACTLR */
999#define CFERE (CFERE_MASK << CFERE_SHIFT)
1000#define CFEIE (CFEIE_MASK << CFEIE_SHIFT)
1001#define PTSHCFG (PTSHCFG_MASK << PTSHCFG_SHIFT)
1002#define RCOSH (RCOSH_MASK << RCOSH_SHIFT)
1003#define RCISH (RCISH_MASK << RCISH_SHIFT)
1004#define RCNSH (RCNSH_MASK << RCNSH_SHIFT)
1005#define PRIVCFG (PRIVCFG_MASK << PRIVCFG_SHIFT)
1006#define DNA (DNA_MASK << DNA_SHIFT)
1007#define DNLV2PA (DNLV2PA_MASK << DNLV2PA_SHIFT)
1008#define TLBMCFG (TLBMCFG_MASK << TLBMCFG_SHIFT)
1009#define CFCFG (CFCFG_MASK << CFCFG_SHIFT)
1010#define TIPCF (TIPCF_MASK << TIPCF_SHIFT)
1011#define V2PCFG (V2PCFG_MASK << V2PCFG_SHIFT)
1012#define HUME (HUME_MASK << HUME_SHIFT)
1013#define PTMTCFG (PTMTCFG_MASK << PTMTCFG_SHIFT)
1014#define PTMEMTYPE (PTMEMTYPE_MASK << PTMEMTYPE_SHIFT)
1015
1016
1017/* BFBCR */
1018#define BFBDFE (BFBDFE_MASK << BFBDFE_SHIFT)
1019#define BFBSFE (BFBSFE_MASK << BFBSFE_SHIFT)
1020#define SFVS (SFVS_MASK << SFVS_SHIFT)
1021#define FLVIC (FLVIC_MASK << FLVIC_SHIFT)
1022#define SLVIC (SLVIC_MASK << SLVIC_SHIFT)
1023
1024
1025/* CONTEXTIDR */
1026#define CONTEXTIDR_ASID (CONTEXTIDR_ASID_MASK << CONTEXTIDR_ASID_SHIFT)
1027#define PROCID (PROCID_MASK << PROCID_SHIFT)
1028
1029
1030/* FSR */
1031#define TF (TF_MASK << TF_SHIFT)
1032#define AFF (AFF_MASK << AFF_SHIFT)
1033#define APF (APF_MASK << APF_SHIFT)
1034#define TLBMF (TLBMF_MASK << TLBMF_SHIFT)
1035#define HTWDEEF (HTWDEEF_MASK << HTWDEEF_SHIFT)
1036#define HTWSEEF (HTWSEEF_MASK << HTWSEEF_SHIFT)
1037#define MHF (MHF_MASK << MHF_SHIFT)
1038#define SL (SL_MASK << SL_SHIFT)
1039#define SS (SS_MASK << SS_SHIFT)
1040#define MULTI (MULTI_MASK << MULTI_SHIFT)
1041
1042
1043/* FSYNR0 */
1044#define AMID (AMID_MASK << AMID_SHIFT)
1045#define APID (APID_MASK << APID_SHIFT)
1046#define ABID (ABID_MASK << ABID_SHIFT)
1047#define ATID (ATID_MASK << ATID_SHIFT)
1048
1049
1050/* FSYNR1 */
1051#define AMEMTYPE (AMEMTYPE_MASK << AMEMTYPE_SHIFT)
1052#define ASHARED (ASHARED_MASK << ASHARED_SHIFT)
1053#define AINNERSHARED (AINNERSHARED_MASK << AINNERSHARED_SHIFT)
1054#define APRIV (APRIV_MASK << APRIV_SHIFT)
1055#define APROTNS (APROTNS_MASK << APROTNS_SHIFT)
1056#define AINST (AINST_MASK << AINST_SHIFT)
1057#define AWRITE (AWRITE_MASK << AWRITE_SHIFT)
1058#define ABURST (ABURST_MASK << ABURST_SHIFT)
1059#define ALEN (ALEN_MASK << ALEN_SHIFT)
1060#define FSYNR1_ASIZE (FSYNR1_ASIZE_MASK << FSYNR1_ASIZE_SHIFT)
1061#define ALOCK (ALOCK_MASK << ALOCK_SHIFT)
1062#define AFULL (AFULL_MASK << AFULL_SHIFT)
1063
1064
1065/* NMRR */
1066#define ICPC0 (ICPC0_MASK << ICPC0_SHIFT)
1067#define ICPC1 (ICPC1_MASK << ICPC1_SHIFT)
1068#define ICPC2 (ICPC2_MASK << ICPC2_SHIFT)
1069#define ICPC3 (ICPC3_MASK << ICPC3_SHIFT)
1070#define ICPC4 (ICPC4_MASK << ICPC4_SHIFT)
1071#define ICPC5 (ICPC5_MASK << ICPC5_SHIFT)
1072#define ICPC6 (ICPC6_MASK << ICPC6_SHIFT)
1073#define ICPC7 (ICPC7_MASK << ICPC7_SHIFT)
1074#define OCPC0 (OCPC0_MASK << OCPC0_SHIFT)
1075#define OCPC1 (OCPC1_MASK << OCPC1_SHIFT)
1076#define OCPC2 (OCPC2_MASK << OCPC2_SHIFT)
1077#define OCPC3 (OCPC3_MASK << OCPC3_SHIFT)
1078#define OCPC4 (OCPC4_MASK << OCPC4_SHIFT)
1079#define OCPC5 (OCPC5_MASK << OCPC5_SHIFT)
1080#define OCPC6 (OCPC6_MASK << OCPC6_SHIFT)
1081#define OCPC7 (OCPC7_MASK << OCPC7_SHIFT)
1082
1083
1084/* PAR */
1085#define FAULT (FAULT_MASK << FAULT_SHIFT)
1086/* If a fault is present, these are the
1087same as the fault fields in the FAR */
1088#define FAULT_TF (FAULT_TF_MASK << FAULT_TF_SHIFT)
1089#define FAULT_AFF (FAULT_AFF_MASK << FAULT_AFF_SHIFT)
1090#define FAULT_APF (FAULT_APF_MASK << FAULT_APF_SHIFT)
1091#define FAULT_TLBMF (FAULT_TLBMF_MASK << FAULT_TLBMF_SHIFT)
1092#define FAULT_HTWDEEF (FAULT_HTWDEEF_MASK << FAULT_HTWDEEF_SHIFT)
1093#define FAULT_HTWSEEF (FAULT_HTWSEEF_MASK << FAULT_HTWSEEF_SHIFT)
1094#define FAULT_MHF (FAULT_MHF_MASK << FAULT_MHF_SHIFT)
1095#define FAULT_SL (FAULT_SL_MASK << FAULT_SL_SHIFT)
1096#define FAULT_SS (FAULT_SS_MASK << FAULT_SS_SHIFT)
1097
1098/* If NO fault is present, the following fields are in effect */
1099/* (FAULT remains as before) */
1100#define PAR_NOFAULT_SS (PAR_NOFAULT_SS_MASK << PAR_NOFAULT_SS_SHIFT)
1101#define PAR_NOFAULT_MT (PAR_NOFAULT_MT_MASK << PAR_NOFAULT_MT_SHIFT)
1102#define PAR_NOFAULT_SH (PAR_NOFAULT_SH_MASK << PAR_NOFAULT_SH_SHIFT)
1103#define PAR_NOFAULT_NS (PAR_NOFAULT_NS_MASK << PAR_NOFAULT_NS_SHIFT)
1104#define PAR_NOFAULT_NOS (PAR_NOFAULT_NOS_MASK << PAR_NOFAULT_NOS_SHIFT)
1105#define PAR_NPFAULT_PA (PAR_NPFAULT_PA_MASK << PAR_NPFAULT_PA_SHIFT)
1106
1107
1108/* PRRR */
1109#define MTC0 (MTC0_MASK << MTC0_SHIFT)
1110#define MTC1 (MTC1_MASK << MTC1_SHIFT)
1111#define MTC2 (MTC2_MASK << MTC2_SHIFT)
1112#define MTC3 (MTC3_MASK << MTC3_SHIFT)
1113#define MTC4 (MTC4_MASK << MTC4_SHIFT)
1114#define MTC5 (MTC5_MASK << MTC5_SHIFT)
1115#define MTC6 (MTC6_MASK << MTC6_SHIFT)
1116#define MTC7 (MTC7_MASK << MTC7_SHIFT)
1117#define SHDSH0 (SHDSH0_MASK << SHDSH0_SHIFT)
1118#define SHDSH1 (SHDSH1_MASK << SHDSH1_SHIFT)
1119#define SHNMSH0 (SHNMSH0_MASK << SHNMSH0_SHIFT)
1120#define SHNMSH1 (SHNMSH1_MASK << SHNMSH1_SHIFT)
1121#define NOS0 (NOS0_MASK << NOS0_SHIFT)
1122#define NOS1 (NOS1_MASK << NOS1_SHIFT)
1123#define NOS2 (NOS2_MASK << NOS2_SHIFT)
1124#define NOS3 (NOS3_MASK << NOS3_SHIFT)
1125#define NOS4 (NOS4_MASK << NOS4_SHIFT)
1126#define NOS5 (NOS5_MASK << NOS5_SHIFT)
1127#define NOS6 (NOS6_MASK << NOS6_SHIFT)
1128#define NOS7 (NOS7_MASK << NOS7_SHIFT)
1129
1130
1131/* RESUME */
1132#define TNR (TNR_MASK << TNR_SHIFT)
1133
1134
1135/* SCTLR */
1136#define M (M_MASK << M_SHIFT)
1137#define TRE (TRE_MASK << TRE_SHIFT)
1138#define AFE (AFE_MASK << AFE_SHIFT)
1139#define HAF (HAF_MASK << HAF_SHIFT)
1140#define BE (BE_MASK << BE_SHIFT)
1141#define AFFD (AFFD_MASK << AFFD_SHIFT)
1142
1143
1144/* TLBIASID */
1145#define TLBIASID_ASID (TLBIASID_ASID_MASK << TLBIASID_ASID_SHIFT)
1146
1147
1148/* TLBIVA */
1149#define TLBIVA_ASID (TLBIVA_ASID_MASK << TLBIVA_ASID_SHIFT)
1150#define TLBIVA_VA (TLBIVA_VA_MASK << TLBIVA_VA_SHIFT)
1151
1152
1153/* TLBIVAA */
1154#define TLBIVAA_VA (TLBIVAA_VA_MASK << TLBIVAA_VA_SHIFT)
1155
1156
1157/* TLBLCKR */
1158#define LKE (LKE_MASK << LKE_SHIFT)
1159#define TLBLCKR_TLBIALLCFG (TLBLCKR_TLBIALLCFG_MASK<<TLBLCKR_TLBIALLCFG_SHIFT)
1160#define TLBIASIDCFG (TLBIASIDCFG_MASK << TLBIASIDCFG_SHIFT)
1161#define TLBIVAACFG (TLBIVAACFG_MASK << TLBIVAACFG_SHIFT)
1162#define FLOOR (FLOOR_MASK << FLOOR_SHIFT)
1163#define VICTIM (VICTIM_MASK << VICTIM_SHIFT)
1164
1165
1166/* TTBCR */
1167#define N (N_MASK << N_SHIFT)
1168#define PD0 (PD0_MASK << PD0_SHIFT)
1169#define PD1 (PD1_MASK << PD1_SHIFT)
1170
1171
1172/* TTBR0 */
1173#define TTBR0_IRGNH (TTBR0_IRGNH_MASK << TTBR0_IRGNH_SHIFT)
1174#define TTBR0_SH (TTBR0_SH_MASK << TTBR0_SH_SHIFT)
1175#define TTBR0_ORGN (TTBR0_ORGN_MASK << TTBR0_ORGN_SHIFT)
1176#define TTBR0_NOS (TTBR0_NOS_MASK << TTBR0_NOS_SHIFT)
1177#define TTBR0_IRGNL (TTBR0_IRGNL_MASK << TTBR0_IRGNL_SHIFT)
1178#define TTBR0_PA (TTBR0_PA_MASK << TTBR0_PA_SHIFT)
1179
1180
1181/* TTBR1 */
1182#define TTBR1_IRGNH (TTBR1_IRGNH_MASK << TTBR1_IRGNH_SHIFT)
1183#define TTBR1_SH (TTBR1_SH_MASK << TTBR1_SH_SHIFT)
1184#define TTBR1_ORGN (TTBR1_ORGN_MASK << TTBR1_ORGN_SHIFT)
1185#define TTBR1_NOS (TTBR1_NOS_MASK << TTBR1_NOS_SHIFT)
1186#define TTBR1_IRGNL (TTBR1_IRGNL_MASK << TTBR1_IRGNL_SHIFT)
1187#define TTBR1_PA (TTBR1_PA_MASK << TTBR1_PA_SHIFT)
1188
1189
1190/* V2PSR */
1191#define HIT (HIT_MASK << HIT_SHIFT)
1192#define INDEX (INDEX_MASK << INDEX_SHIFT)
1193
1194
1195/* V2Pxx */
1196#define V2Pxx_INDEX (V2Pxx_INDEX_MASK << V2Pxx_INDEX_SHIFT)
1197#define V2Pxx_VA (V2Pxx_VA_MASK << V2Pxx_VA_SHIFT)
1198
1199
1200/* Global Register Masks */
1201/* CBACRn */
1202#define RWVMID_MASK 0x1F
1203#define RWE_MASK 0x01
1204#define RWGE_MASK 0x01
1205#define CBVMID_MASK 0x1F
1206#define IRPTNDX_MASK 0xFF
1207
1208
1209/* CR */
1210#define RPUE_MASK 0x01
1211#define RPUERE_MASK 0x01
1212#define RPUEIE_MASK 0x01
1213#define DCDEE_MASK 0x01
1214#define CLIENTPD_MASK 0x01
1215#define STALLD_MASK 0x01
1216#define TLBLKCRWE_MASK 0x01
1217#define CR_TLBIALLCFG_MASK 0x01
1218#define TLBIVMIDCFG_MASK 0x01
1219#define CR_HUME_MASK 0x01
1220
1221
1222/* ESR */
1223#define CFG_MASK 0x01
1224#define BYPASS_MASK 0x01
1225#define ESR_MULTI_MASK 0x01
1226
1227
1228/* ESYNR0 */
1229#define ESYNR0_AMID_MASK 0xFF
1230#define ESYNR0_APID_MASK 0x1F
1231#define ESYNR0_ABID_MASK 0x07
1232#define ESYNR0_AVMID_MASK 0x1F
1233#define ESYNR0_ATID_MASK 0xFF
1234
1235
1236/* ESYNR1 */
1237#define ESYNR1_AMEMTYPE_MASK 0x07
1238#define ESYNR1_ASHARED_MASK 0x01
1239#define ESYNR1_AINNERSHARED_MASK 0x01
1240#define ESYNR1_APRIV_MASK 0x01
1241#define ESYNR1_APROTNS_MASK 0x01
1242#define ESYNR1_AINST_MASK 0x01
1243#define ESYNR1_AWRITE_MASK 0x01
1244#define ESYNR1_ABURST_MASK 0x01
1245#define ESYNR1_ALEN_MASK 0x0F
1246#define ESYNR1_ASIZE_MASK 0x01
1247#define ESYNR1_ALOCK_MASK 0x03
1248#define ESYNR1_AOOO_MASK 0x01
1249#define ESYNR1_AFULL_MASK 0x01
1250#define ESYNR1_AC_MASK 0x01
1251#define ESYNR1_DCD_MASK 0x01
1252
1253
1254/* IDR */
1255#define NM2VCBMT_MASK 0x1FF
1256#define HTW_MASK 0x01
1257#define HUM_MASK 0x01
1258#define TLBSIZE_MASK 0x0F
1259#define NCB_MASK 0xFF
1260#define NIRPT_MASK 0xFF
1261
1262
1263/* M2VCBRn */
1264#define VMID_MASK 0x1F
1265#define CBNDX_MASK 0xFF
1266#define BYPASSD_MASK 0x01
1267#define BPRCOSH_MASK 0x01
1268#define BPRCISH_MASK 0x01
1269#define BPRCNSH_MASK 0x01
1270#define BPSHCFG_MASK 0x03
1271#define NSCFG_MASK 0x03
1272#define BPMTCFG_MASK 0x01
1273#define BPMEMTYPE_MASK 0x07
1274
1275
1276/* REV */
1277#define MINOR_MASK 0x0F
1278#define MAJOR_MASK 0x0F
1279
1280
1281/* TESTBUSCR */
1282#define TBE_MASK 0x01
1283#define SPDMBE_MASK 0x01
1284#define WGSEL_MASK 0x03
1285#define TBLSEL_MASK 0x03
1286#define TBHSEL_MASK 0x03
1287#define SPDM0SEL_MASK 0x0F
1288#define SPDM1SEL_MASK 0x0F
1289#define SPDM2SEL_MASK 0x0F
1290#define SPDM3SEL_MASK 0x0F
1291
1292
1293/* TLBIMID */
1294#define TLBIVMID_VMID_MASK 0x1F
1295
1296
1297/* TLBRSW */
1298#define TLBRSW_INDEX_MASK 0xFF
1299#define TLBBFBS_MASK 0x03
1300
1301
1302/* TLBTR0 */
1303#define PR_MASK 0x01
1304#define PW_MASK 0x01
1305#define UR_MASK 0x01
1306#define UW_MASK 0x01
1307#define XN_MASK 0x01
1308#define NSDESC_MASK 0x01
1309#define ISH_MASK 0x01
1310#define SH_MASK 0x01
1311#define MT_MASK 0x07
1312#define DPSIZR_MASK 0x07
1313#define DPSIZC_MASK 0x07
1314
1315
1316/* TLBTR1 */
1317#define TLBTR1_VMID_MASK 0x1F
1318#define TLBTR1_PA_MASK 0x000FFFFF
1319
1320
1321/* TLBTR2 */
1322#define TLBTR2_ASID_MASK 0xFF
1323#define TLBTR2_V_MASK 0x01
1324#define TLBTR2_NSTID_MASK 0x01
1325#define TLBTR2_NV_MASK 0x01
1326#define TLBTR2_VA_MASK 0x000FFFFF
1327
1328
1329/* Global Register Shifts */
1330/* CBACRn */
1331#define RWVMID_SHIFT 0
1332#define RWE_SHIFT 8
1333#define RWGE_SHIFT 9
1334#define CBVMID_SHIFT 16
1335#define IRPTNDX_SHIFT 24
1336
1337
1338/* CR */
1339#define RPUE_SHIFT 0
1340#define RPUERE_SHIFT 1
1341#define RPUEIE_SHIFT 2
1342#define DCDEE_SHIFT 3
1343#define CLIENTPD_SHIFT 4
1344#define STALLD_SHIFT 5
1345#define TLBLKCRWE_SHIFT 6
1346#define CR_TLBIALLCFG_SHIFT 7
1347#define TLBIVMIDCFG_SHIFT 8
1348#define CR_HUME_SHIFT 9
1349
1350
1351/* ESR */
1352#define CFG_SHIFT 0
1353#define BYPASS_SHIFT 1
1354#define ESR_MULTI_SHIFT 31
1355
1356
1357/* ESYNR0 */
1358#define ESYNR0_AMID_SHIFT 0
1359#define ESYNR0_APID_SHIFT 8
1360#define ESYNR0_ABID_SHIFT 13
1361#define ESYNR0_AVMID_SHIFT 16
1362#define ESYNR0_ATID_SHIFT 24
1363
1364
1365/* ESYNR1 */
1366#define ESYNR1_AMEMTYPE_SHIFT 0
1367#define ESYNR1_ASHARED_SHIFT 3
1368#define ESYNR1_AINNERSHARED_SHIFT 4
1369#define ESYNR1_APRIV_SHIFT 5
1370#define ESYNR1_APROTNS_SHIFT 6
1371#define ESYNR1_AINST_SHIFT 7
1372#define ESYNR1_AWRITE_SHIFT 8
1373#define ESYNR1_ABURST_SHIFT 10
1374#define ESYNR1_ALEN_SHIFT 12
1375#define ESYNR1_ASIZE_SHIFT 16
1376#define ESYNR1_ALOCK_SHIFT 20
1377#define ESYNR1_AOOO_SHIFT 22
1378#define ESYNR1_AFULL_SHIFT 24
1379#define ESYNR1_AC_SHIFT 30
1380#define ESYNR1_DCD_SHIFT 31
1381
1382
1383/* IDR */
1384#define NM2VCBMT_SHIFT 0
1385#define HTW_SHIFT 9
1386#define HUM_SHIFT 10
1387#define TLBSIZE_SHIFT 12
1388#define NCB_SHIFT 16
1389#define NIRPT_SHIFT 24
1390
1391
1392/* M2VCBRn */
1393#define VMID_SHIFT 0
1394#define CBNDX_SHIFT 8
1395#define BYPASSD_SHIFT 16
1396#define BPRCOSH_SHIFT 17
1397#define BPRCISH_SHIFT 18
1398#define BPRCNSH_SHIFT 19
1399#define BPSHCFG_SHIFT 20
1400#define NSCFG_SHIFT 22
1401#define BPMTCFG_SHIFT 24
1402#define BPMEMTYPE_SHIFT 25
1403
1404
1405/* REV */
1406#define MINOR_SHIFT 0
1407#define MAJOR_SHIFT 4
1408
1409
1410/* TESTBUSCR */
1411#define TBE_SHIFT 0
1412#define SPDMBE_SHIFT 1
1413#define WGSEL_SHIFT 8
1414#define TBLSEL_SHIFT 12
1415#define TBHSEL_SHIFT 14
1416#define SPDM0SEL_SHIFT 16
1417#define SPDM1SEL_SHIFT 20
1418#define SPDM2SEL_SHIFT 24
1419#define SPDM3SEL_SHIFT 28
1420
1421
1422/* TLBIMID */
1423#define TLBIVMID_VMID_SHIFT 0
1424
1425
1426/* TLBRSW */
1427#define TLBRSW_INDEX_SHIFT 0
1428#define TLBBFBS_SHIFT 8
1429
1430
1431/* TLBTR0 */
1432#define PR_SHIFT 0
1433#define PW_SHIFT 1
1434#define UR_SHIFT 2
1435#define UW_SHIFT 3
1436#define XN_SHIFT 4
1437#define NSDESC_SHIFT 6
1438#define ISH_SHIFT 7
1439#define SH_SHIFT 8
1440#define MT_SHIFT 9
1441#define DPSIZR_SHIFT 16
1442#define DPSIZC_SHIFT 20
1443
1444
1445/* TLBTR1 */
1446#define TLBTR1_VMID_SHIFT 0
1447#define TLBTR1_PA_SHIFT 12
1448
1449
1450/* TLBTR2 */
1451#define TLBTR2_ASID_SHIFT 0
1452#define TLBTR2_V_SHIFT 8
1453#define TLBTR2_NSTID_SHIFT 9
1454#define TLBTR2_NV_SHIFT 10
1455#define TLBTR2_VA_SHIFT 12
1456
1457
1458/* Context Register Masks */
1459/* ACTLR */
1460#define CFERE_MASK 0x01
1461#define CFEIE_MASK 0x01
1462#define PTSHCFG_MASK 0x03
1463#define RCOSH_MASK 0x01
1464#define RCISH_MASK 0x01
1465#define RCNSH_MASK 0x01
1466#define PRIVCFG_MASK 0x03
1467#define DNA_MASK 0x01
1468#define DNLV2PA_MASK 0x01
1469#define TLBMCFG_MASK 0x03
1470#define CFCFG_MASK 0x01
1471#define TIPCF_MASK 0x01
1472#define V2PCFG_MASK 0x03
1473#define HUME_MASK 0x01
1474#define PTMTCFG_MASK 0x01
1475#define PTMEMTYPE_MASK 0x07
1476
1477
1478/* BFBCR */
1479#define BFBDFE_MASK 0x01
1480#define BFBSFE_MASK 0x01
1481#define SFVS_MASK 0x01
1482#define FLVIC_MASK 0x0F
1483#define SLVIC_MASK 0x0F
1484
1485
1486/* CONTEXTIDR */
1487#define CONTEXTIDR_ASID_MASK 0xFF
1488#define PROCID_MASK 0x00FFFFFF
1489
1490
1491/* FSR */
1492#define TF_MASK 0x01
1493#define AFF_MASK 0x01
1494#define APF_MASK 0x01
1495#define TLBMF_MASK 0x01
1496#define HTWDEEF_MASK 0x01
1497#define HTWSEEF_MASK 0x01
1498#define MHF_MASK 0x01
1499#define SL_MASK 0x01
1500#define SS_MASK 0x01
1501#define MULTI_MASK 0x01
1502
1503
1504/* FSYNR0 */
1505#define AMID_MASK 0xFF
1506#define APID_MASK 0x1F
1507#define ABID_MASK 0x07
1508#define ATID_MASK 0xFF
1509
1510
1511/* FSYNR1 */
1512#define AMEMTYPE_MASK 0x07
1513#define ASHARED_MASK 0x01
1514#define AINNERSHARED_MASK 0x01
1515#define APRIV_MASK 0x01
1516#define APROTNS_MASK 0x01
1517#define AINST_MASK 0x01
1518#define AWRITE_MASK 0x01
1519#define ABURST_MASK 0x01
1520#define ALEN_MASK 0x0F
1521#define FSYNR1_ASIZE_MASK 0x07
1522#define ALOCK_MASK 0x03
1523#define AFULL_MASK 0x01
1524
1525
1526/* NMRR */
1527#define ICPC0_MASK 0x03
1528#define ICPC1_MASK 0x03
1529#define ICPC2_MASK 0x03
1530#define ICPC3_MASK 0x03
1531#define ICPC4_MASK 0x03
1532#define ICPC5_MASK 0x03
1533#define ICPC6_MASK 0x03
1534#define ICPC7_MASK 0x03
1535#define OCPC0_MASK 0x03
1536#define OCPC1_MASK 0x03
1537#define OCPC2_MASK 0x03
1538#define OCPC3_MASK 0x03
1539#define OCPC4_MASK 0x03
1540#define OCPC5_MASK 0x03
1541#define OCPC6_MASK 0x03
1542#define OCPC7_MASK 0x03
1543
1544
1545/* PAR */
1546#define FAULT_MASK 0x01
1547/* If a fault is present, these are the
1548same as the fault fields in the FAR */
1549#define FAULT_TF_MASK 0x01
1550#define FAULT_AFF_MASK 0x01
1551#define FAULT_APF_MASK 0x01
1552#define FAULT_TLBMF_MASK 0x01
1553#define FAULT_HTWDEEF_MASK 0x01
1554#define FAULT_HTWSEEF_MASK 0x01
1555#define FAULT_MHF_MASK 0x01
1556#define FAULT_SL_MASK 0x01
1557#define FAULT_SS_MASK 0x01
1558
1559/* If NO fault is present, the following
1560 * fields are in effect
1561 * (FAULT remains as before) */
1562#define PAR_NOFAULT_SS_MASK 0x01
1563#define PAR_NOFAULT_MT_MASK 0x07
1564#define PAR_NOFAULT_SH_MASK 0x01
1565#define PAR_NOFAULT_NS_MASK 0x01
1566#define PAR_NOFAULT_NOS_MASK 0x01
1567#define PAR_NPFAULT_PA_MASK 0x000FFFFF
1568
1569
1570/* PRRR */
1571#define MTC0_MASK 0x03
1572#define MTC1_MASK 0x03
1573#define MTC2_MASK 0x03
1574#define MTC3_MASK 0x03
1575#define MTC4_MASK 0x03
1576#define MTC5_MASK 0x03
1577#define MTC6_MASK 0x03
1578#define MTC7_MASK 0x03
1579#define SHDSH0_MASK 0x01
1580#define SHDSH1_MASK 0x01
1581#define SHNMSH0_MASK 0x01
1582#define SHNMSH1_MASK 0x01
1583#define NOS0_MASK 0x01
1584#define NOS1_MASK 0x01
1585#define NOS2_MASK 0x01
1586#define NOS3_MASK 0x01
1587#define NOS4_MASK 0x01
1588#define NOS5_MASK 0x01
1589#define NOS6_MASK 0x01
1590#define NOS7_MASK 0x01
1591
1592
1593/* RESUME */
1594#define TNR_MASK 0x01
1595
1596
1597/* SCTLR */
1598#define M_MASK 0x01
1599#define TRE_MASK 0x01
1600#define AFE_MASK 0x01
1601#define HAF_MASK 0x01
1602#define BE_MASK 0x01
1603#define AFFD_MASK 0x01
1604
1605
1606/* TLBIASID */
1607#define TLBIASID_ASID_MASK 0xFF
1608
1609
1610/* TLBIVA */
1611#define TLBIVA_ASID_MASK 0xFF
1612#define TLBIVA_VA_MASK 0x000FFFFF
1613
1614
1615/* TLBIVAA */
1616#define TLBIVAA_VA_MASK 0x000FFFFF
1617
1618
1619/* TLBLCKR */
1620#define LKE_MASK 0x01
1621#define TLBLCKR_TLBIALLCFG_MASK 0x01
1622#define TLBIASIDCFG_MASK 0x01
1623#define TLBIVAACFG_MASK 0x01
1624#define FLOOR_MASK 0xFF
1625#define VICTIM_MASK 0xFF
1626
1627
1628/* TTBCR */
1629#define N_MASK 0x07
1630#define PD0_MASK 0x01
1631#define PD1_MASK 0x01
1632
1633
1634/* TTBR0 */
1635#define TTBR0_IRGNH_MASK 0x01
1636#define TTBR0_SH_MASK 0x01
1637#define TTBR0_ORGN_MASK 0x03
1638#define TTBR0_NOS_MASK 0x01
1639#define TTBR0_IRGNL_MASK 0x01
1640#define TTBR0_PA_MASK 0x0003FFFF
1641
1642
1643/* TTBR1 */
1644#define TTBR1_IRGNH_MASK 0x01
1645#define TTBR1_SH_MASK 0x01
1646#define TTBR1_ORGN_MASK 0x03
1647#define TTBR1_NOS_MASK 0x01
1648#define TTBR1_IRGNL_MASK 0x01
1649#define TTBR1_PA_MASK 0x0003FFFF
1650
1651
1652/* V2PSR */
1653#define HIT_MASK 0x01
1654#define INDEX_MASK 0xFF
1655
1656
1657/* V2Pxx */
1658#define V2Pxx_INDEX_MASK 0xFF
1659#define V2Pxx_VA_MASK 0x000FFFFF
1660
1661
1662/* Context Register Shifts */
1663/* ACTLR */
1664#define CFERE_SHIFT 0
1665#define CFEIE_SHIFT 1
1666#define PTSHCFG_SHIFT 2
1667#define RCOSH_SHIFT 4
1668#define RCISH_SHIFT 5
1669#define RCNSH_SHIFT 6
1670#define PRIVCFG_SHIFT 8
1671#define DNA_SHIFT 10
1672#define DNLV2PA_SHIFT 11
1673#define TLBMCFG_SHIFT 12
1674#define CFCFG_SHIFT 14
1675#define TIPCF_SHIFT 15
1676#define V2PCFG_SHIFT 16
1677#define HUME_SHIFT 18
1678#define PTMTCFG_SHIFT 20
1679#define PTMEMTYPE_SHIFT 21
1680
1681
1682/* BFBCR */
1683#define BFBDFE_SHIFT 0
1684#define BFBSFE_SHIFT 1
1685#define SFVS_SHIFT 2
1686#define FLVIC_SHIFT 4
1687#define SLVIC_SHIFT 8
1688
1689
1690/* CONTEXTIDR */
1691#define CONTEXTIDR_ASID_SHIFT 0
1692#define PROCID_SHIFT 8
1693
1694
1695/* FSR */
1696#define TF_SHIFT 1
1697#define AFF_SHIFT 2
1698#define APF_SHIFT 3
1699#define TLBMF_SHIFT 4
1700#define HTWDEEF_SHIFT 5
1701#define HTWSEEF_SHIFT 6
1702#define MHF_SHIFT 7
1703#define SL_SHIFT 16
1704#define SS_SHIFT 30
1705#define MULTI_SHIFT 31
1706
1707
1708/* FSYNR0 */
1709#define AMID_SHIFT 0
1710#define APID_SHIFT 8
1711#define ABID_SHIFT 13
1712#define ATID_SHIFT 24
1713
1714
1715/* FSYNR1 */
1716#define AMEMTYPE_SHIFT 0
1717#define ASHARED_SHIFT 3
1718#define AINNERSHARED_SHIFT 4
1719#define APRIV_SHIFT 5
1720#define APROTNS_SHIFT 6
1721#define AINST_SHIFT 7
1722#define AWRITE_SHIFT 8
1723#define ABURST_SHIFT 10
1724#define ALEN_SHIFT 12
1725#define FSYNR1_ASIZE_SHIFT 16
1726#define ALOCK_SHIFT 20
1727#define AFULL_SHIFT 24
1728
1729
1730/* NMRR */
1731#define ICPC0_SHIFT 0
1732#define ICPC1_SHIFT 2
1733#define ICPC2_SHIFT 4
1734#define ICPC3_SHIFT 6
1735#define ICPC4_SHIFT 8
1736#define ICPC5_SHIFT 10
1737#define ICPC6_SHIFT 12
1738#define ICPC7_SHIFT 14
1739#define OCPC0_SHIFT 16
1740#define OCPC1_SHIFT 18
1741#define OCPC2_SHIFT 20
1742#define OCPC3_SHIFT 22
1743#define OCPC4_SHIFT 24
1744#define OCPC5_SHIFT 26
1745#define OCPC6_SHIFT 28
1746#define OCPC7_SHIFT 30
1747
1748
1749/* PAR */
1750#define FAULT_SHIFT 0
1751/* If a fault is present, these are the
1752same as the fault fields in the FAR */
1753#define FAULT_TF_SHIFT 1
1754#define FAULT_AFF_SHIFT 2
1755#define FAULT_APF_SHIFT 3
1756#define FAULT_TLBMF_SHIFT 4
1757#define FAULT_HTWDEEF_SHIFT 5
1758#define FAULT_HTWSEEF_SHIFT 6
1759#define FAULT_MHF_SHIFT 7
1760#define FAULT_SL_SHIFT 16
1761#define FAULT_SS_SHIFT 30
1762
1763/* If NO fault is present, the following
1764 * fields are in effect
1765 * (FAULT remains as before) */
1766#define PAR_NOFAULT_SS_SHIFT 1
1767#define PAR_NOFAULT_MT_SHIFT 4
1768#define PAR_NOFAULT_SH_SHIFT 7
1769#define PAR_NOFAULT_NS_SHIFT 9
1770#define PAR_NOFAULT_NOS_SHIFT 10
1771#define PAR_NPFAULT_PA_SHIFT 12
1772
1773
1774/* PRRR */
1775#define MTC0_SHIFT 0
1776#define MTC1_SHIFT 2
1777#define MTC2_SHIFT 4
1778#define MTC3_SHIFT 6
1779#define MTC4_SHIFT 8
1780#define MTC5_SHIFT 10
1781#define MTC6_SHIFT 12
1782#define MTC7_SHIFT 14
1783#define SHDSH0_SHIFT 16
1784#define SHDSH1_SHIFT 17
1785#define SHNMSH0_SHIFT 18
1786#define SHNMSH1_SHIFT 19
1787#define NOS0_SHIFT 24
1788#define NOS1_SHIFT 25
1789#define NOS2_SHIFT 26
1790#define NOS3_SHIFT 27
1791#define NOS4_SHIFT 28
1792#define NOS5_SHIFT 29
1793#define NOS6_SHIFT 30
1794#define NOS7_SHIFT 31
1795
1796
1797/* RESUME */
1798#define TNR_SHIFT 0
1799
1800
1801/* SCTLR */
1802#define M_SHIFT 0
1803#define TRE_SHIFT 1
1804#define AFE_SHIFT 2
1805#define HAF_SHIFT 3
1806#define BE_SHIFT 4
1807#define AFFD_SHIFT 5
1808
1809
1810/* TLBIASID */
1811#define TLBIASID_ASID_SHIFT 0
1812
1813
1814/* TLBIVA */
1815#define TLBIVA_ASID_SHIFT 0
1816#define TLBIVA_VA_SHIFT 12
1817
1818
1819/* TLBIVAA */
1820#define TLBIVAA_VA_SHIFT 12
1821
1822
1823/* TLBLCKR */
1824#define LKE_SHIFT 0
1825#define TLBLCKR_TLBIALLCFG_SHIFT 1
1826#define TLBIASIDCFG_SHIFT 2
1827#define TLBIVAACFG_SHIFT 3
1828#define FLOOR_SHIFT 8
1829#define VICTIM_SHIFT 8
1830
1831
1832/* TTBCR */
1833#define N_SHIFT 3
1834#define PD0_SHIFT 4
1835#define PD1_SHIFT 5
1836
1837
1838/* TTBR0 */
1839#define TTBR0_IRGNH_SHIFT 0
1840#define TTBR0_SH_SHIFT 1
1841#define TTBR0_ORGN_SHIFT 3
1842#define TTBR0_NOS_SHIFT 5
1843#define TTBR0_IRGNL_SHIFT 6
1844#define TTBR0_PA_SHIFT 14
1845
1846
1847/* TTBR1 */
1848#define TTBR1_IRGNH_SHIFT 0
1849#define TTBR1_SH_SHIFT 1
1850#define TTBR1_ORGN_SHIFT 3
1851#define TTBR1_NOS_SHIFT 5
1852#define TTBR1_IRGNL_SHIFT 6
1853#define TTBR1_PA_SHIFT 14
1854
1855
1856/* V2PSR */
1857#define HIT_SHIFT 0
1858#define INDEX_SHIFT 8
1859
1860
1861/* V2Pxx */
1862#define V2Pxx_INDEX_SHIFT 0
1863#define V2Pxx_VA_SHIFT 12
1864
1865#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h b/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
deleted file mode 100644
index 7bca8d7108d6..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8960.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8960_H
24#define __ASM_ARCH_MSM_IOMAP_8960_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * If you add or remove entries here, you'll want to edit the
30 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
31 * changes.
32 *
33 */
34
35#define MSM8960_TMR_PHYS 0x0200A000
36#define MSM8960_TMR_SIZE SZ_4K
37
38#define MSM8960_TMR0_PHYS 0x0208A000
39#define MSM8960_TMR0_SIZE SZ_4K
40
41#ifdef CONFIG_DEBUG_MSM8960_UART
42#define MSM_DEBUG_UART_BASE 0xF0040000
43#define MSM_DEBUG_UART_PHYS 0x16440000
44#endif
45
46#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
deleted file mode 100644
index 75a7b62c1c74..000000000000
--- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h
+++ /dev/null
@@ -1,53 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2008-2011, Code Aurora Forum. All rights reserved.
4 * Author: Brian Swetland <swetland@google.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 *
16 * The MSM peripherals are spread all over across 768MB of physical
17 * space, which makes just having a simple IO_ADDRESS macro to slide
18 * them into the right virtual location rough. Instead, we will
19 * provide a master phys->virt mapping for peripherals here.
20 *
21 */
22
23#ifndef __ASM_ARCH_MSM_IOMAP_8X60_H
24#define __ASM_ARCH_MSM_IOMAP_8X60_H
25
26/* Physical base address and size of peripherals.
27 * Ordered by the virtual base addresses they will be mapped at.
28 *
29 * MSM_VIC_BASE must be an value that can be loaded via a "mov"
30 * instruction, otherwise entry-macro.S will not compile.
31 *
32 * If you add or remove entries here, you'll want to edit the
33 * msm_io_desc array in arch/arm/mach-msm/io.c to reflect your
34 * changes.
35 *
36 */
37
38#define MSM_TLMM_BASE IOMEM(0xF0004000)
39#define MSM_TLMM_PHYS 0x00800000
40#define MSM_TLMM_SIZE SZ_16K
41
42#define MSM8X60_TMR_PHYS 0x02000000
43#define MSM8X60_TMR_SIZE SZ_4K
44
45#define MSM8X60_TMR0_PHYS 0x02040000
46#define MSM8X60_TMR0_SIZE SZ_4K
47
48#ifdef CONFIG_DEBUG_MSM8660_UART
49#define MSM_DEBUG_UART_BASE 0xF0040000
50#define MSM_DEBUG_UART_PHYS 0x19C40000
51#endif
52
53#endif
diff --git a/arch/arm/mach-msm/include/mach/msm_iomap.h b/arch/arm/mach-msm/include/mach/msm_iomap.h
index c56e81ffdcde..0e4f49157684 100644
--- a/arch/arm/mach-msm/include/mach/msm_iomap.h
+++ b/arch/arm/mach-msm/include/mach/msm_iomap.h
@@ -45,25 +45,8 @@
45#include "msm_iomap-7x00.h" 45#include "msm_iomap-7x00.h"
46#endif 46#endif
47 47
48#include "msm_iomap-8x60.h"
49#include "msm_iomap-8960.h"
50
51#define MSM_DEBUG_UART_SIZE SZ_4K
52#if defined(CONFIG_DEBUG_MSM_UART1)
53#define MSM_DEBUG_UART_BASE 0xE1000000
54#define MSM_DEBUG_UART_PHYS MSM_UART1_PHYS
55#elif defined(CONFIG_DEBUG_MSM_UART2)
56#define MSM_DEBUG_UART_BASE 0xE1000000
57#define MSM_DEBUG_UART_PHYS MSM_UART2_PHYS
58#elif defined(CONFIG_DEBUG_MSM_UART3)
59#define MSM_DEBUG_UART_BASE 0xE1000000
60#define MSM_DEBUG_UART_PHYS MSM_UART3_PHYS
61#endif
62
63/* Virtual addresses shared across all MSM targets. */ 48/* Virtual addresses shared across all MSM targets. */
64#define MSM_CSR_BASE IOMEM(0xE0001000) 49#define MSM_CSR_BASE IOMEM(0xE0001000)
65#define MSM_TMR_BASE IOMEM(0xF0200000)
66#define MSM_TMR0_BASE IOMEM(0xF0201000)
67#define MSM_GPIO1_BASE IOMEM(0xE0003000) 50#define MSM_GPIO1_BASE IOMEM(0xE0003000)
68#define MSM_GPIO2_BASE IOMEM(0xE0004000) 51#define MSM_GPIO2_BASE IOMEM(0xE0004000)
69 52
diff --git a/arch/arm/mach-msm/include/mach/uncompress.h b/arch/arm/mach-msm/include/mach/uncompress.h
deleted file mode 100644
index 94324870fb04..000000000000
--- a/arch/arm/mach-msm/include/mach/uncompress.h
+++ /dev/null
@@ -1,63 +0,0 @@
1/*
2 * Copyright (C) 2007 Google, Inc.
3 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MSM_UNCOMPRESS_H
17#define __ASM_ARCH_MSM_UNCOMPRESS_H
18
19#include <asm/barrier.h>
20#include <asm/processor.h>
21#include <mach/msm_iomap.h>
22
23#define UART_CSR (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08))
24#define UART_TF (*(volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x0c))
25
26#define UART_DM_SR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x08)))
27#define UART_DM_CR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x10)))
28#define UART_DM_ISR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x14)))
29#define UART_DM_NCHAR (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x40)))
30#define UART_DM_TF (*((volatile uint32_t *)(MSM_DEBUG_UART_PHYS + 0x70)))
31
32static void putc(int c)
33{
34#if defined(MSM_DEBUG_UART_PHYS)
35#ifdef CONFIG_MSM_HAS_DEBUG_UART_HS
36 /*
37 * Wait for TX_READY to be set; but skip it if we have a
38 * TX underrun.
39 */
40 if (!(UART_DM_SR & 0x08))
41 while (!(UART_DM_ISR & 0x80))
42 cpu_relax();
43
44 UART_DM_CR = 0x300;
45 UART_DM_NCHAR = 0x1;
46 UART_DM_TF = c;
47#else
48 while (!(UART_CSR & 0x04))
49 cpu_relax();
50 UART_TF = c;
51#endif
52#endif
53}
54
55static inline void flush(void)
56{
57}
58
59static inline void arch_decomp_setup(void)
60{
61}
62
63#endif
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index 3dc04ccaf59f..adc8971c7266 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -18,6 +18,7 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/bug.h>
21#include <linux/init.h> 22#include <linux/init.h>
22#include <linux/io.h> 23#include <linux/io.h>
23#include <linux/export.h> 24#include <linux/export.h>
@@ -27,8 +28,6 @@
27#include <mach/msm_iomap.h> 28#include <mach/msm_iomap.h>
28#include <asm/mach/map.h> 29#include <asm/mach/map.h>
29 30
30#include <mach/board.h>
31
32#include "common.h" 31#include "common.h"
33 32
34#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \ 33#define MSM_CHIP_DEVICE_TYPE(name, chip, mem_type) { \
@@ -52,26 +51,38 @@ static struct map_desc msm_io_desc[] __initdata = {
52 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED), 51 MSM_CHIP_DEVICE_TYPE(GPIO1, MSM7X00, MT_DEVICE_NONSHARED),
53 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED), 52 MSM_CHIP_DEVICE_TYPE(GPIO2, MSM7X00, MT_DEVICE_NONSHARED),
54 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED), 53 MSM_DEVICE_TYPE(CLK_CTL, MT_DEVICE_NONSHARED),
55#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
56 defined(CONFIG_DEBUG_MSM_UART3)
57 MSM_DEVICE_TYPE(DEBUG_UART, MT_DEVICE_NONSHARED),
58#endif
59 { 54 {
60 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 55 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
61 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 56 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
62 .length = MSM_SHARED_RAM_SIZE, 57 .length = MSM_SHARED_RAM_SIZE,
63 .type = MT_DEVICE, 58 .type = MT_DEVICE,
64 }, 59 },
60#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
61 defined(CONFIG_DEBUG_MSM_UART3)
62 {
63 /* Must be last: virtual and pfn filled in by debug_ll_addr() */
64 .length = SZ_4K,
65 .type = MT_DEVICE_NONSHARED,
66 }
67#endif
65}; 68};
66 69
67void __init msm_map_common_io(void) 70void __init msm_map_common_io(void)
68{ 71{
72 size_t size = ARRAY_SIZE(msm_io_desc);
73
69 /* Make sure the peripheral register window is closed, since 74 /* Make sure the peripheral register window is closed, since
70 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which 75 * we will use PTE flags (TEX[1]=1,B=0,C=1) to determine which
71 * pages are peripheral interface or not. 76 * pages are peripheral interface or not.
72 */ 77 */
73 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0)); 78 asm("mcr p15, 0, %0, c15, c2, 4" : : "r" (0));
74 iotable_init(msm_io_desc, ARRAY_SIZE(msm_io_desc)); 79#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
80 defined(CONFIG_DEBUG_MSM_UART3)
81 debug_ll_addr(&msm_io_desc[size - 1].pfn,
82 &msm_io_desc[size - 1].virtual);
83 msm_io_desc[size - 1].pfn = __phys_to_pfn(msm_io_desc[size - 1].pfn);
84#endif
85 iotable_init(msm_io_desc, size);
75} 86}
76#endif 87#endif
77 88
@@ -87,10 +98,6 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
87 MSM_DEVICE(SCPLL), 98 MSM_DEVICE(SCPLL),
88 MSM_DEVICE(AD5), 99 MSM_DEVICE(AD5),
89 MSM_DEVICE(MDC), 100 MSM_DEVICE(MDC),
90#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
91 defined(CONFIG_DEBUG_MSM_UART3)
92 MSM_DEVICE(DEBUG_UART),
93#endif
94 { 101 {
95 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 102 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
96 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 103 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -101,40 +108,11 @@ static struct map_desc qsd8x50_io_desc[] __initdata = {
101 108
102void __init msm_map_qsd8x50_io(void) 109void __init msm_map_qsd8x50_io(void)
103{ 110{
111 debug_ll_io_init();
104 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc)); 112 iotable_init(qsd8x50_io_desc, ARRAY_SIZE(qsd8x50_io_desc));
105} 113}
106#endif /* CONFIG_ARCH_QSD8X50 */ 114#endif /* CONFIG_ARCH_QSD8X50 */
107 115
108#ifdef CONFIG_ARCH_MSM8X60
109static struct map_desc msm8x60_io_desc[] __initdata = {
110 MSM_CHIP_DEVICE(TMR, MSM8X60),
111 MSM_CHIP_DEVICE(TMR0, MSM8X60),
112#ifdef CONFIG_DEBUG_MSM8660_UART
113 MSM_DEVICE(DEBUG_UART),
114#endif
115};
116
117void __init msm_map_msm8x60_io(void)
118{
119 iotable_init(msm8x60_io_desc, ARRAY_SIZE(msm8x60_io_desc));
120}
121#endif /* CONFIG_ARCH_MSM8X60 */
122
123#ifdef CONFIG_ARCH_MSM8960
124static struct map_desc msm8960_io_desc[] __initdata = {
125 MSM_CHIP_DEVICE(TMR, MSM8960),
126 MSM_CHIP_DEVICE(TMR0, MSM8960),
127#ifdef CONFIG_DEBUG_MSM8960_UART
128 MSM_DEVICE(DEBUG_UART),
129#endif
130};
131
132void __init msm_map_msm8960_io(void)
133{
134 iotable_init(msm8960_io_desc, ARRAY_SIZE(msm8960_io_desc));
135}
136#endif /* CONFIG_ARCH_MSM8960 */
137
138#ifdef CONFIG_ARCH_MSM7X30 116#ifdef CONFIG_ARCH_MSM7X30
139static struct map_desc msm7x30_io_desc[] __initdata = { 117static struct map_desc msm7x30_io_desc[] __initdata = {
140 MSM_DEVICE(VIC), 118 MSM_DEVICE(VIC),
@@ -150,10 +128,6 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
150 MSM_DEVICE(SAW), 128 MSM_DEVICE(SAW),
151 MSM_DEVICE(GCC), 129 MSM_DEVICE(GCC),
152 MSM_DEVICE(TCSR), 130 MSM_DEVICE(TCSR),
153#if defined(CONFIG_DEBUG_MSM_UART1) || defined(CONFIG_DEBUG_MSM_UART2) || \
154 defined(CONFIG_DEBUG_MSM_UART3)
155 MSM_DEVICE(DEBUG_UART),
156#endif
157 { 131 {
158 .virtual = (unsigned long) MSM_SHARED_RAM_BASE, 132 .virtual = (unsigned long) MSM_SHARED_RAM_BASE,
159 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS), 133 .pfn = __phys_to_pfn(MSM_SHARED_RAM_PHYS),
@@ -164,10 +138,12 @@ static struct map_desc msm7x30_io_desc[] __initdata = {
164 138
165void __init msm_map_msm7x30_io(void) 139void __init msm_map_msm7x30_io(void)
166{ 140{
141 debug_ll_io_init();
167 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc)); 142 iotable_init(msm7x30_io_desc, ARRAY_SIZE(msm7x30_io_desc));
168} 143}
169#endif /* CONFIG_ARCH_MSM7X30 */ 144#endif /* CONFIG_ARCH_MSM7X30 */
170 145
146#ifdef CONFIG_ARCH_MSM7X00A
171void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size, 147void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
172 unsigned int mtype, void *caller) 148 unsigned int mtype, void *caller)
173{ 149{
@@ -182,3 +158,4 @@ void __iomem *__msm_ioremap_caller(phys_addr_t phys_addr, size_t size,
182 158
183 return __arm_ioremap_caller(phys_addr, size, mtype, caller); 159 return __arm_ioremap_caller(phys_addr, size, mtype, caller);
184} 160}
161#endif
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 8697cfc0d0b6..696fb73296d0 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -16,6 +16,7 @@
16 16
17#include <linux/clocksource.h> 17#include <linux/clocksource.h>
18#include <linux/clockchips.h> 18#include <linux/clockchips.h>
19#include <linux/cpu.h>
19#include <linux/init.h> 20#include <linux/init.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
21#include <linux/irq.h> 22#include <linux/irq.h>
@@ -26,7 +27,6 @@
26#include <linux/sched_clock.h> 27#include <linux/sched_clock.h>
27 28
28#include <asm/mach/time.h> 29#include <asm/mach/time.h>
29#include <asm/localtimer.h>
30 30
31#include "common.h" 31#include "common.h"
32 32
@@ -49,7 +49,7 @@ static void __iomem *sts_base;
49 49
50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) 50static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
51{ 51{
52 struct clock_event_device *evt = *(struct clock_event_device **)dev_id; 52 struct clock_event_device *evt = dev_id;
53 /* Stop the timer tick */ 53 /* Stop the timer tick */
54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) { 54 if (evt->mode == CLOCK_EVT_MODE_ONESHOT) {
55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE); 55 u32 ctrl = readl_relaxed(event_base + TIMER_ENABLE);
@@ -101,18 +101,7 @@ static void msm_timer_set_mode(enum clock_event_mode mode,
101 writel_relaxed(ctrl, event_base + TIMER_ENABLE); 101 writel_relaxed(ctrl, event_base + TIMER_ENABLE);
102} 102}
103 103
104static struct clock_event_device msm_clockevent = { 104static struct clock_event_device __percpu *msm_evt;
105 .name = "gp_timer",
106 .features = CLOCK_EVT_FEAT_ONESHOT,
107 .rating = 200,
108 .set_next_event = msm_timer_set_next_event,
109 .set_mode = msm_timer_set_mode,
110};
111
112static union {
113 struct clock_event_device *evt;
114 struct clock_event_device * __percpu *percpu_evt;
115} msm_evt;
116 105
117static void __iomem *source_base; 106static void __iomem *source_base;
118 107
@@ -138,23 +127,34 @@ static struct clocksource msm_clocksource = {
138 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 127 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
139}; 128};
140 129
141#ifdef CONFIG_LOCAL_TIMERS 130static int msm_timer_irq;
131static int msm_timer_has_ppi;
132
142static int msm_local_timer_setup(struct clock_event_device *evt) 133static int msm_local_timer_setup(struct clock_event_device *evt)
143{ 134{
144 /* Use existing clock_event for cpu 0 */ 135 int cpu = smp_processor_id();
145 if (!smp_processor_id()) 136 int err;
146 return 0; 137
147 138 evt->irq = msm_timer_irq;
148 evt->irq = msm_clockevent.irq; 139 evt->name = "msm_timer";
149 evt->name = "local_timer"; 140 evt->features = CLOCK_EVT_FEAT_ONESHOT;
150 evt->features = msm_clockevent.features; 141 evt->rating = 200;
151 evt->rating = msm_clockevent.rating;
152 evt->set_mode = msm_timer_set_mode; 142 evt->set_mode = msm_timer_set_mode;
153 evt->set_next_event = msm_timer_set_next_event; 143 evt->set_next_event = msm_timer_set_next_event;
144 evt->cpumask = cpumask_of(cpu);
145
146 clockevents_config_and_register(evt, GPT_HZ, 4, 0xffffffff);
147
148 if (msm_timer_has_ppi) {
149 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
150 } else {
151 err = request_irq(evt->irq, msm_timer_interrupt,
152 IRQF_TIMER | IRQF_NOBALANCING |
153 IRQF_TRIGGER_RISING, "gp_timer", evt);
154 if (err)
155 pr_err("request_irq failed\n");
156 }
154 157
155 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
156 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
157 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
158 return 0; 158 return 0;
159} 159}
160 160
@@ -164,11 +164,28 @@ static void msm_local_timer_stop(struct clock_event_device *evt)
164 disable_percpu_irq(evt->irq); 164 disable_percpu_irq(evt->irq);
165} 165}
166 166
167static struct local_timer_ops msm_local_timer_ops = { 167static int msm_timer_cpu_notify(struct notifier_block *self,
168 .setup = msm_local_timer_setup, 168 unsigned long action, void *hcpu)
169 .stop = msm_local_timer_stop, 169{
170 /*
171 * Grab cpu pointer in each case to avoid spurious
172 * preemptible warnings
173 */
174 switch (action & ~CPU_TASKS_FROZEN) {
175 case CPU_STARTING:
176 msm_local_timer_setup(this_cpu_ptr(msm_evt));
177 break;
178 case CPU_DYING:
179 msm_local_timer_stop(this_cpu_ptr(msm_evt));
180 break;
181 }
182
183 return NOTIFY_OK;
184}
185
186static struct notifier_block msm_timer_cpu_nb = {
187 .notifier_call = msm_timer_cpu_notify,
170}; 188};
171#endif /* CONFIG_LOCAL_TIMERS */
172 189
173static notrace u32 msm_sched_clock_read(void) 190static notrace u32 msm_sched_clock_read(void)
174{ 191{
@@ -178,38 +195,35 @@ static notrace u32 msm_sched_clock_read(void)
178static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, 195static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
179 bool percpu) 196 bool percpu)
180{ 197{
181 struct clock_event_device *ce = &msm_clockevent;
182 struct clocksource *cs = &msm_clocksource; 198 struct clocksource *cs = &msm_clocksource;
183 int res; 199 int res = 0;
200
201 msm_timer_irq = irq;
202 msm_timer_has_ppi = percpu;
203
204 msm_evt = alloc_percpu(struct clock_event_device);
205 if (!msm_evt) {
206 pr_err("memory allocation failed for clockevents\n");
207 goto err;
208 }
184 209
185 ce->cpumask = cpumask_of(0); 210 if (percpu)
186 ce->irq = irq; 211 res = request_percpu_irq(irq, msm_timer_interrupt,
212 "gp_timer", msm_evt);
187 213
188 clockevents_config_and_register(ce, GPT_HZ, 4, 0xffffffff); 214 if (res) {
189 if (percpu) { 215 pr_err("request_percpu_irq failed\n");
190 msm_evt.percpu_evt = alloc_percpu(struct clock_event_device *); 216 } else {
191 if (!msm_evt.percpu_evt) { 217 res = register_cpu_notifier(&msm_timer_cpu_nb);
192 pr_err("memory allocation failed for %s\n", ce->name); 218 if (res) {
219 free_percpu_irq(irq, msm_evt);
193 goto err; 220 goto err;
194 } 221 }
195 *__this_cpu_ptr(msm_evt.percpu_evt) = ce; 222
196 res = request_percpu_irq(ce->irq, msm_timer_interrupt, 223 /* Immediately configure the timer on the boot CPU */
197 ce->name, msm_evt.percpu_evt); 224 msm_local_timer_setup(__this_cpu_ptr(msm_evt));
198 if (!res) {
199 enable_percpu_irq(ce->irq, IRQ_TYPE_EDGE_RISING);
200#ifdef CONFIG_LOCAL_TIMERS
201 local_timer_register(&msm_local_timer_ops);
202#endif
203 }
204 } else {
205 msm_evt.evt = ce;
206 res = request_irq(ce->irq, msm_timer_interrupt,
207 IRQF_TIMER | IRQF_NOBALANCING |
208 IRQF_TRIGGER_RISING, ce->name, &msm_evt.evt);
209 } 225 }
210 226
211 if (res)
212 pr_err("request_irq failed for %s\n", ce->name);
213err: 227err:
214 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE); 228 writel_relaxed(TIMER_ENABLE_EN, source_base + TIMER_ENABLE);
215 res = clocksource_register_hz(cs, dgt_hz); 229 res = clocksource_register_hz(cs, dgt_hz);
@@ -219,15 +233,8 @@ err:
219} 233}
220 234
221#ifdef CONFIG_OF 235#ifdef CONFIG_OF
222static const struct of_device_id msm_timer_match[] __initconst = { 236static void __init msm_dt_timer_init(struct device_node *np)
223 { .compatible = "qcom,kpss-timer" },
224 { .compatible = "qcom,scss-timer" },
225 { },
226};
227
228void __init msm_dt_timer_init(void)
229{ 237{
230 struct device_node *np;
231 u32 freq; 238 u32 freq;
232 int irq; 239 int irq;
233 struct resource res; 240 struct resource res;
@@ -235,12 +242,6 @@ void __init msm_dt_timer_init(void)
235 void __iomem *base; 242 void __iomem *base;
236 void __iomem *cpu0_base; 243 void __iomem *cpu0_base;
237 244
238 np = of_find_matching_node(NULL, msm_timer_match);
239 if (!np) {
240 pr_err("Can't find msm timer DT node\n");
241 return;
242 }
243
244 base = of_iomap(np, 0); 245 base = of_iomap(np, 0);
245 if (!base) { 246 if (!base) {
246 pr_err("Failed to map event base\n"); 247 pr_err("Failed to map event base\n");
@@ -283,6 +284,8 @@ void __init msm_dt_timer_init(void)
283 284
284 msm_timer_init(freq, 32, irq, !!percpu_offset); 285 msm_timer_init(freq, 32, irq, !!percpu_offset);
285} 286}
287CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
288CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
286#endif 289#endif
287 290
288static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, 291static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index dc26a654c496..445e553f4a28 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -18,6 +18,11 @@
18#include <mach/mv78xx0.h> 18#include <mach/mv78xx0.h>
19#include "common.h" 19#include "common.h"
20 20
21#define MV78XX0_MBUS_PCIE_MEM_TARGET(port, lane) ((port) ? 8 : 4)
22#define MV78XX0_MBUS_PCIE_MEM_ATTR(port, lane) (0xf8 & ~(0x10 << (lane)))
23#define MV78XX0_MBUS_PCIE_IO_TARGET(port, lane) ((port) ? 8 : 4)
24#define MV78XX0_MBUS_PCIE_IO_ATTR(port, lane) (0xf0 & ~(0x10 << (lane)))
25
21struct pcie_port { 26struct pcie_port {
22 u8 maj; 27 u8 maj;
23 u8 min; 28 u8 min;
@@ -71,7 +76,6 @@ static void __init mv78xx0_pcie_preinit(void)
71 start = MV78XX0_PCIE_MEM_PHYS_BASE; 76 start = MV78XX0_PCIE_MEM_PHYS_BASE;
72 for (i = 0; i < num_pcie_ports; i++) { 77 for (i = 0; i < num_pcie_ports; i++) {
73 struct pcie_port *pp = pcie_port + i; 78 struct pcie_port *pp = pcie_port + i;
74 char winname[MVEBU_MBUS_MAX_WINNAME_SZ];
75 79
76 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name), 80 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
77 "PCIe %d.%d MEM", pp->maj, pp->min); 81 "PCIe %d.%d MEM", pp->maj, pp->min);
@@ -85,17 +89,12 @@ static void __init mv78xx0_pcie_preinit(void)
85 if (request_resource(&iomem_resource, &pp->res)) 89 if (request_resource(&iomem_resource, &pp->res))
86 panic("can't allocate PCIe MEM sub-space"); 90 panic("can't allocate PCIe MEM sub-space");
87 91
88 snprintf(winname, sizeof(winname), "pcie%d.%d", 92 mvebu_mbus_add_window_by_id(MV78XX0_MBUS_PCIE_MEM_TARGET(pp->maj, pp->min),
89 pp->maj, pp->min); 93 MV78XX0_MBUS_PCIE_MEM_ATTR(pp->maj, pp->min),
90 94 pp->res.start, resource_size(&pp->res));
91 mvebu_mbus_add_window_remap_flags(winname, 95 mvebu_mbus_add_window_remap_by_id(MV78XX0_MBUS_PCIE_IO_TARGET(pp->maj, pp->min),
92 pp->res.start, 96 MV78XX0_MBUS_PCIE_IO_ATTR(pp->maj, pp->min),
93 resource_size(&pp->res), 97 i * SZ_64K, SZ_64K, 0);
94 MVEBU_MBUS_NO_REMAP,
95 MVEBU_MBUS_PCI_MEM);
96 mvebu_mbus_add_window_remap_flags(winname,
97 i * SZ_64K, SZ_64K,
98 0, MVEBU_MBUS_PCI_IO);
99 } 98 }
100} 99}
101 100
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index 97cbb8021919..829b57306328 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -34,44 +34,12 @@ static void __init armada_370_xp_map_io(void)
34 debug_ll_io_init(); 34 debug_ll_io_init();
35} 35}
36 36
37/*
38 * This initialization will be replaced by a DT-based
39 * initialization once the mvebu-mbus driver gains DT support.
40 */
41
42#define ARMADA_370_XP_MBUS_WINS_OFFS 0x20000
43#define ARMADA_370_XP_MBUS_WINS_SIZE 0x100
44#define ARMADA_370_XP_SDRAM_WINS_OFFS 0x20180
45#define ARMADA_370_XP_SDRAM_WINS_SIZE 0x20
46
47static void __init armada_370_xp_mbus_init(void)
48{
49 char *mbus_soc_name;
50 struct device_node *dn;
51 const __be32 mbus_wins_offs = cpu_to_be32(ARMADA_370_XP_MBUS_WINS_OFFS);
52 const __be32 sdram_wins_offs = cpu_to_be32(ARMADA_370_XP_SDRAM_WINS_OFFS);
53
54 if (of_machine_is_compatible("marvell,armada370"))
55 mbus_soc_name = "marvell,armada370-mbus";
56 else
57 mbus_soc_name = "marvell,armadaxp-mbus";
58
59 dn = of_find_node_by_name(NULL, "internal-regs");
60 BUG_ON(!dn);
61
62 mvebu_mbus_init(mbus_soc_name,
63 of_translate_address(dn, &mbus_wins_offs),
64 ARMADA_370_XP_MBUS_WINS_SIZE,
65 of_translate_address(dn, &sdram_wins_offs),
66 ARMADA_370_XP_SDRAM_WINS_SIZE);
67}
68
69static void __init armada_370_xp_timer_and_clk_init(void) 37static void __init armada_370_xp_timer_and_clk_init(void)
70{ 38{
71 of_clk_init(NULL); 39 of_clk_init(NULL);
72 armada_370_xp_timer_init(); 40 armada_370_xp_timer_init();
73 coherency_init(); 41 coherency_init();
74 armada_370_xp_mbus_init(); 42 BUG_ON(mvebu_mbus_dt_init());
75#ifdef CONFIG_CACHE_L2X0 43#ifdef CONFIG_CACHE_L2X0
76 l2x0_of_init(0, ~0UL); 44 l2x0_of_init(0, ~0UL);
77#endif 45#endif
diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
index 594b63db4215..ff69c2df298b 100644
--- a/arch/arm/mach-mvebu/platsmp.c
+++ b/arch/arm/mach-mvebu/platsmp.c
@@ -21,6 +21,7 @@
21#include <linux/smp.h> 21#include <linux/smp.h>
22#include <linux/clk.h> 22#include <linux/clk.h>
23#include <linux/of.h> 23#include <linux/of.h>
24#include <linux/of_address.h>
24#include <linux/mbus.h> 25#include <linux/mbus.h>
25#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
26#include <asm/smp_plat.h> 27#include <asm/smp_plat.h>
@@ -29,6 +30,9 @@
29#include "pmsu.h" 30#include "pmsu.h"
30#include "coherency.h" 31#include "coherency.h"
31 32
33#define AXP_BOOTROM_BASE 0xfff00000
34#define AXP_BOOTROM_SIZE 0x100000
35
32static struct clk *__init get_cpu_clk(int cpu) 36static struct clk *__init get_cpu_clk(int cpu)
33{ 37{
34 struct clk *cpu_clk; 38 struct clk *cpu_clk;
@@ -82,37 +86,39 @@ static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
82 86
83static void __init armada_xp_smp_init_cpus(void) 87static void __init armada_xp_smp_init_cpus(void)
84{ 88{
85 struct device_node *np; 89 unsigned int ncores = num_possible_cpus();
86 unsigned int i, ncores;
87
88 np = of_find_node_by_name(NULL, "cpus");
89 if (!np)
90 panic("No 'cpus' node found\n");
91 90
92 ncores = of_get_child_count(np);
93 if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS) 91 if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
94 panic("Invalid number of CPUs in DT\n"); 92 panic("Invalid number of CPUs in DT\n");
95 93
96 /* Limit possible CPUs to defconfig */
97 if (ncores > nr_cpu_ids) {
98 pr_warn("SMP: %d CPUs physically present. Only %d configured.",
99 ncores, nr_cpu_ids);
100 pr_warn("Clipping CPU count to %d\n", nr_cpu_ids);
101 ncores = nr_cpu_ids;
102 }
103
104 for (i = 0; i < ncores; i++)
105 set_cpu_possible(i, true);
106
107 set_smp_cross_call(armada_mpic_send_doorbell); 94 set_smp_cross_call(armada_mpic_send_doorbell);
108} 95}
109 96
110void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus) 97void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
111{ 98{
99 struct device_node *node;
100 struct resource res;
101 int err;
102
112 set_secondary_cpus_clock(); 103 set_secondary_cpus_clock();
113 flush_cache_all(); 104 flush_cache_all();
114 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0); 105 set_cpu_coherent(cpu_logical_map(smp_processor_id()), 0);
115 mvebu_mbus_add_window("bootrom", 0xfff00000, SZ_1M); 106
107 /*
108 * In order to boot the secondary CPUs we need to ensure
109 * the bootROM is mapped at the correct address.
110 */
111 node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
112 if (!node)
113 panic("Cannot find 'marvell,bootrom' compatible node");
114
115 err = of_address_to_resource(node, 0, &res);
116 if (err < 0)
117 panic("Cannot get 'bootrom' node address");
118
119 if (res.start != AXP_BOOTROM_BASE ||
120 resource_size(&res) != AXP_BOOTROM_SIZE)
121 panic("The address for the BootROM is incorrect");
116} 122}
117 123
118struct smp_operations armada_xp_smp_ops __initdata = { 124struct smp_operations armada_xp_smp_ops __initdata = {
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 4ce27b536dc9..98f6e2adb53e 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -14,6 +14,7 @@
14#include <linux/clk/mxs.h> 14#include <linux/clk/mxs.h>
15#include <linux/clkdev.h> 15#include <linux/clkdev.h>
16#include <linux/clocksource.h> 16#include <linux/clocksource.h>
17#include <linux/clk-provider.h>
17#include <linux/delay.h> 18#include <linux/delay.h>
18#include <linux/err.h> 19#include <linux/err.h>
19#include <linux/gpio.h> 20#include <linux/gpio.h>
@@ -61,6 +62,8 @@
61static u32 chipid; 62static u32 chipid;
62static u32 socid; 63static u32 socid;
63 64
65static void __iomem *reset_addr;
66
64static inline void __mxs_setl(u32 mask, void __iomem *reg) 67static inline void __mxs_setl(u32 mask, void __iomem *reg)
65{ 68{
66 __raw_writel(mask, reg + MXS_SET_ADDR); 69 __raw_writel(mask, reg + MXS_SET_ADDR);
@@ -393,12 +396,33 @@ static const char __init *mxs_get_revision(void)
393 u32 rev = mxs_get_cpu_rev(); 396 u32 rev = mxs_get_cpu_rev();
394 397
395 if (rev != MXS_CHIP_REV_UNKNOWN) 398 if (rev != MXS_CHIP_REV_UNKNOWN)
396 return kasprintf(GFP_KERNEL, "TO%d.%d", (rev >> 4) & 0xf, 399 return kasprintf(GFP_KERNEL, "%d.%d", (rev >> 4) & 0xf,
397 rev & 0xf); 400 rev & 0xf);
398 else 401 else
399 return kasprintf(GFP_KERNEL, "%s", "Unknown"); 402 return kasprintf(GFP_KERNEL, "%s", "Unknown");
400} 403}
401 404
405#define MX23_CLKCTRL_RESET_OFFSET 0x120
406#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
407
408static int __init mxs_restart_init(void)
409{
410 struct device_node *np;
411
412 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
413 reset_addr = of_iomap(np, 0);
414 if (!reset_addr)
415 return -ENODEV;
416
417 if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
418 reset_addr += MX23_CLKCTRL_RESET_OFFSET;
419 else
420 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
421 of_node_put(np);
422
423 return 0;
424}
425
402static void __init mxs_machine_init(void) 426static void __init mxs_machine_init(void)
403{ 427{
404 struct device_node *root; 428 struct device_node *root;
@@ -433,21 +457,18 @@ static void __init mxs_machine_init(void)
433 imx28_evk_init(); 457 imx28_evk_init();
434 else if (of_machine_is_compatible("bluegiga,apx4devkit")) 458 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
435 apx4devkit_init(); 459 apx4devkit_init();
436 else if (of_machine_is_compatible("crystalfontz,cfa10037") || 460 else if (of_machine_is_compatible("crystalfontz,cfa10036"))
437 of_machine_is_compatible("crystalfontz,cfa10049") ||
438 of_machine_is_compatible("crystalfontz,cfa10055") ||
439 of_machine_is_compatible("crystalfontz,cfa10057"))
440 crystalfontz_init(); 461 crystalfontz_init();
441 462
442 of_platform_populate(NULL, of_default_bus_match_table, 463 of_platform_populate(NULL, of_default_bus_match_table,
443 NULL, parent); 464 NULL, parent);
444 465
466 mxs_restart_init();
467
445 if (of_machine_is_compatible("karo,tx28")) 468 if (of_machine_is_compatible("karo,tx28"))
446 tx28_post_init(); 469 tx28_post_init();
447} 470}
448 471
449#define MX23_CLKCTRL_RESET_OFFSET 0x120
450#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
451#define MXS_CLKCTRL_RESET_CHIP (1 << 1) 472#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
452 473
453/* 474/*
@@ -455,28 +476,16 @@ static void __init mxs_machine_init(void)
455 */ 476 */
456static void mxs_restart(enum reboot_mode mode, const char *cmd) 477static void mxs_restart(enum reboot_mode mode, const char *cmd)
457{ 478{
458 struct device_node *np; 479 if (reset_addr) {
459 void __iomem *reset_addr; 480 /* reset the chip */
481 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
460 482
461 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl"); 483 pr_err("Failed to assert the chip reset\n");
462 reset_addr = of_iomap(np, 0);
463 if (!reset_addr)
464 goto soft;
465 484
466 if (of_device_is_compatible(np, "fsl,imx23-clkctrl")) 485 /* Delay to allow the serial port to show the message */
467 reset_addr += MX23_CLKCTRL_RESET_OFFSET; 486 mdelay(50);
468 else 487 }
469 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
470
471 /* reset the chip */
472 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
473
474 pr_err("Failed to assert the chip reset\n");
475
476 /* Delay to allow the serial port to show the message */
477 mdelay(50);
478 488
479soft:
480 /* We'll take a jump through zero as a poor second */ 489 /* We'll take a jump through zero as a poor second */
481 soft_restart(0); 490 soft_restart(0);
482} 491}
@@ -487,6 +496,7 @@ static void __init mxs_timer_init(void)
487 mx23_clocks_init(); 496 mx23_clocks_init();
488 else 497 else
489 mx28_clocks_init(); 498 mx28_clocks_init();
499 of_clk_init(NULL);
490 clocksource_of_init(); 500 clocksource_of_init();
491} 501}
492 502
diff --git a/arch/arm/mach-mxs/pm.c b/arch/arm/mach-mxs/pm.c
index b2494d2db2c4..0170e99fd70f 100644
--- a/arch/arm/mach-mxs/pm.c
+++ b/arch/arm/mach-mxs/pm.c
@@ -15,6 +15,7 @@
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/suspend.h> 16#include <linux/suspend.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include "pm.h"
18 19
19static int mxs_suspend_enter(suspend_state_t state) 20static int mxs_suspend_enter(suspend_state_t state)
20{ 21{
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
index 5981c3db9b41..4d42da49753c 100644
--- a/arch/arm/mach-nomadik/Kconfig
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -27,6 +27,7 @@ config MACH_NOMADIK_8815NHK
27 select NOMADIK_8815 27 select NOMADIK_8815
28 select I2C 28 select I2C
29 select I2C_ALGOBIT 29 select I2C_ALGOBIT
30 select I2C_NOMADIK
30 31
31endmenu 32endmenu
32endif 33endif
diff --git a/arch/arm/mach-omap1/include/mach/soc.h b/arch/arm/mach-omap1/include/mach/soc.h
index 6cf9c1cc2bef..612bd1cc257c 100644
--- a/arch/arm/mach-omap1/include/mach/soc.h
+++ b/arch/arm/mach-omap1/include/mach/soc.h
@@ -195,6 +195,7 @@ IS_OMAP_TYPE(1710, 0x1710)
195#define cpu_is_omap34xx() 0 195#define cpu_is_omap34xx() 0
196#define cpu_is_omap44xx() 0 196#define cpu_is_omap44xx() 0
197#define soc_is_omap54xx() 0 197#define soc_is_omap54xx() 0
198#define soc_is_dra7xx() 0
198#define soc_is_am33xx() 0 199#define soc_is_am33xx() 0
199#define cpu_class_is_omap1() 1 200#define cpu_class_is_omap1() 1
200#define cpu_class_is_omap2() 0 201#define cpu_class_is_omap2() 0
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 3eed0006d189..b5fb5f7992df 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -37,9 +37,8 @@ config ARCH_OMAP4
37 select CACHE_L2X0 37 select CACHE_L2X0
38 select CPU_V7 38 select CPU_V7
39 select HAVE_ARM_SCU if SMP 39 select HAVE_ARM_SCU if SMP
40 select HAVE_ARM_TWD if LOCAL_TIMERS 40 select HAVE_ARM_TWD if SMP
41 select HAVE_SMP 41 select HAVE_SMP
42 select LOCAL_TIMERS if SMP
43 select OMAP_INTERCONNECT 42 select OMAP_INTERCONNECT
44 select PL310_ERRATA_588369 43 select PL310_ERRATA_588369
45 select PL310_ERRATA_727915 44 select PL310_ERRATA_727915
@@ -65,7 +64,7 @@ config SOC_OMAP5
65 select ARM_ERRATA_798181 if SMP 64 select ARM_ERRATA_798181 if SMP
66 65
67config SOC_AM33XX 66config SOC_AM33XX
68 bool "AM33XX support" 67 bool "TI AM33XX"
69 depends on ARCH_MULTI_V7 68 depends on ARCH_MULTI_V7
70 select ARCH_OMAP2PLUS 69 select ARCH_OMAP2PLUS
71 select ARM_CPU_SUSPEND if PM 70 select ARM_CPU_SUSPEND if PM
@@ -118,7 +117,7 @@ config ARCH_OMAP2PLUS_TYPICAL
118 select I2C 117 select I2C
119 select I2C_OMAP 118 select I2C_OMAP
120 select MENELAUS if ARCH_OMAP2 119 select MENELAUS if ARCH_OMAP2
121 select NEON if ARCH_OMAP3 || ARCH_OMAP4 || SOC_OMAP5 120 select NEON if CPU_V7
122 select PM_RUNTIME 121 select PM_RUNTIME
123 select REGULATOR 122 select REGULATOR
124 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 123 select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4
@@ -132,9 +131,17 @@ config SOC_HAS_OMAP2_SDRC
132 131
133config SOC_HAS_REALTIME_COUNTER 132config SOC_HAS_REALTIME_COUNTER
134 bool "Real time free running counter" 133 bool "Real time free running counter"
135 depends on SOC_OMAP5 134 depends on SOC_OMAP5 || SOC_DRA7XX
136 default y 135 default y
137 136
137config SOC_DRA7XX
138 bool "TI DRA7XX"
139 select ARM_ARCH_TIMER
140 select CPU_V7
141 select ARM_GIC
142 select HAVE_SMP
143 select COMMON_CLK
144
138comment "OMAP Core Type" 145comment "OMAP Core Type"
139 depends on ARCH_OMAP2 146 depends on ARCH_OMAP2
140 147
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index d4f671547c37..afb457c3135b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common) 23obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common) 24obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common) 25obj-$(CONFIG_SOC_AM43XX) += $(hwmod-common) $(secure-common)
26obj-$(CONFIG_SOC_DRA7XX) += prm44xx.o $(hwmod-common) $(secure-common)
26 27
27ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),) 28ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
28obj-y += mcbsp.o 29obj-y += mcbsp.o
@@ -39,6 +40,7 @@ omap-4-5-common = omap4-common.o omap-wakeupgen.o
39obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o 40obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common) $(smp-y) sleep44xx.o
40obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o 41obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common) $(smp-y) sleep44xx.o
41obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common) 42obj-$(CONFIG_SOC_AM43XX) += $(omap-4-5-common)
43obj-$(CONFIG_SOC_DRA7XX) += $(omap-4-5-common) $(smp-y)
42 44
43plus_sec := $(call as-instr,.arch_extension sec,+sec) 45plus_sec := $(call as-instr,.arch_extension sec,+sec)
44AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec) 46AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -61,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
61obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 63obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
62obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o 64obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
63obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 65obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
64 67
65# Pin multiplexing 68# Pin multiplexing
66obj-$(CONFIG_SOC_OMAP2420) += mux2420.o 69obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@@ -87,6 +90,7 @@ obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
87obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o 90obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
88obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o 91obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
89obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o 92obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
93obj-$(CONFIG_SOC_DRA7XX) += omap-mpuss-lowpower.o
90obj-$(CONFIG_PM_DEBUG) += pm-debug.o 94obj-$(CONFIG_PM_DEBUG) += pm-debug.o
91 95
92obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o 96obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
@@ -114,6 +118,7 @@ omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
114 vc44xx_data.o vp44xx_data.o 118 vc44xx_data.o vp44xx_data.o
115obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) 119obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
116obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common) 120obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
121obj-$(CONFIG_SOC_DRA7XX) += $(omap-prcm-4-5-common)
117 122
118# OMAP voltage domains 123# OMAP voltage domains
119voltagedomain-common := voltage.o vc.o vp.o 124voltagedomain-common := voltage.o vc.o vp.o
@@ -143,6 +148,8 @@ obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
143obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common) 148obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
144obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 149obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
145obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o 150obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
151obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
152obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
146 153
147# PRCM clockdomain control 154# PRCM clockdomain control
148clockdomain-common += clockdomain.o 155clockdomain-common += clockdomain.o
@@ -160,6 +167,8 @@ obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
160obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common) 167obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
161obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 168obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
162obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o 169obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
170obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
171obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
163 172
164# Clock framework 173# Clock framework
165obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 174obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -203,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
203obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 212obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
204obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 213obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
205obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 214obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
215obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
206 216
207# EMU peripherals 217# EMU peripherals
208obj-$(CONFIG_OMAP3_EMU) += emu.o 218obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
index 1eae96212315..c88d8df753c2 100644
--- a/arch/arm/mach-omap2/am33xx-restart.c
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -24,8 +24,8 @@ void am33xx_restart(enum reboot_mode mode, const char *cmd)
24{ 24{
25 /* TODO: Handle mode and cmd if necessary */ 25 /* TODO: Handle mode and cmd if necessary */
26 26
27 am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK, 27 am33xx_prm_rmw_reg_bits(AM33XX_RST_GLOBAL_WARM_SW_MASK,
28 AM33XX_GLOBAL_WARM_SW_RST_MASK, 28 AM33XX_RST_GLOBAL_WARM_SW_MASK,
29 AM33XX_PRM_DEVICE_MOD, 29 AM33XX_PRM_DEVICE_MOD,
30 AM33XX_PRM_RSTCTRL_OFFSET); 30 AM33XX_PRM_RSTCTRL_OFFSET);
31 31
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index fc53911d0d13..0d499a1878f6 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -110,8 +110,6 @@ static void __init am3517_crane_i2c_init(void)
110 110
111static void __init am3517_crane_init(void) 111static void __init am3517_crane_init(void)
112{ 112{
113 int ret;
114
115 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB); 113 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
116 omap_serial_init(); 114 omap_serial_init();
117 omap_sdrc_init(NULL, NULL); 115 omap_sdrc_init(NULL, NULL);
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 8cc2c9e9fb03..543d9a882de3 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -21,7 +21,7 @@
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/gpio.h> 23#include <linux/gpio.h>
24#include <linux/i2c/pca953x.h> 24#include <linux/platform_data/pca953x.h>
25#include <linux/can/platform/ti_hecc.h> 25#include <linux/can/platform/ti_hecc.h>
26#include <linux/davinci_emac.h> 26#include <linux/davinci_emac.h>
27#include <linux/mmc/host.h> 27#include <linux/mmc/host.h>
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index be5d005ebad2..39c78387ddec 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -222,3 +222,22 @@ DT_MACHINE_START(AM43_DT, "Generic AM43 (Flattened Device Tree)")
222 .dt_compat = am43_boards_compat, 222 .dt_compat = am43_boards_compat,
223MACHINE_END 223MACHINE_END
224#endif 224#endif
225
226#ifdef CONFIG_SOC_DRA7XX
227static const char *dra7xx_boards_compat[] __initdata = {
228 "ti,dra7",
229 NULL,
230};
231
232DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
233 .reserve = omap_reserve,
234 .smp = smp_ops(omap4_smp_ops),
235 .map_io = omap5_map_io,
236 .init_early = dra7xx_init_early,
237 .init_irq = omap_gic_of_init,
238 .init_machine = omap_generic_init,
239 .init_time = omap5_realtime_timer_init,
240 .dt_compat = dra7xx_boards_compat,
241 .restart = omap44xx_restart,
242MACHINE_END
243#endif
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ba6534d7f155..865d30ee812f 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -421,6 +421,10 @@ static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); 421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); 422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423 423
424static struct clk rng_fck;
425DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
426DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
427
424/* 428/*
425 * Modules clock nodes 429 * Modules clock nodes
426 * 430 *
@@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
966 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), 970 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
967 CLK(NULL, "sha0_fck", &sha0_fck), 971 CLK(NULL, "sha0_fck", &sha0_fck),
968 CLK(NULL, "aes0_fck", &aes0_fck), 972 CLK(NULL, "aes0_fck", &aes0_fck),
973 CLK(NULL, "rng_fck", &rng_fck),
969 CLK(NULL, "timer1_fck", &timer1_fck), 974 CLK(NULL, "timer1_fck", &timer1_fck),
970 CLK(NULL, "timer2_fck", &timer2_fck), 975 CLK(NULL, "timer2_fck", &timer2_fck),
971 CLK(NULL, "timer3_fck", &timer3_fck), 976 CLK(NULL, "timer3_fck", &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a474334..1d5b5290d2af 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void)
1707 omap2_clk_disable_autoidle_all(); 1707 omap2_clk_disable_autoidle_all();
1708 1708
1709 /* 1709 /*
1710 * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
1711 * when its in bypass. So always lock USB before ABE DPLL.
1712 */
1713 /*
1714 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1715 * domain can transition to retention state when not in use.
1716 */
1717 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1718 if (rc)
1719 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1720
1721 /*
1710 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 1722 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
1711 * state when turning the ABE clock domain. Workaround this by 1723 * state when turning the ABE clock domain. Workaround this by
1712 * locking the ABE DPLL on boot. 1724 * locking the ABE DPLL on boot.
@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
1718 if (rc) 1730 if (rc)
1719 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 1731 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1720 1732
1721 /*
1722 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1723 * domain can transition to retention state when not in use.
1724 */
1725 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1726 if (rc)
1727 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1728
1729 return 0; 1733 return 0;
1730} 1734}
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index daeecf1b89fa..4b03394fa0c5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
217extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void); 219extern void __init omap54xx_clockdomains_init(void);
220extern void __init dra7xx_clockdomains_init(void);
220 221
221extern void clkdm_add_autodeps(struct clockdomain *clkdm); 222extern void clkdm_add_autodeps(struct clockdomain *clkdm);
222extern void clkdm_del_autodeps(struct clockdomain *clkdm); 223extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
new file mode 100644
index 000000000000..57d5df0c1fbd
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -0,0 +1,740 @@
1/*
2 * DRA7xx Clock domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/io.h>
25
26#include "clockdomain.h"
27#include "cm1_7xx.h"
28#include "cm2_7xx.h"
29
30#include "cm-regbits-7xx.h"
31#include "prm7xx.h"
32#include "prcm44xx.h"
33#include "prcm_mpu7xx.h"
34
35/* Static Dependencies for DRA7xx Clock Domains */
36
37static struct clkdm_dep cam_wkup_sleep_deps[] = {
38 { .clkdm_name = "emif_clkdm" },
39 { NULL },
40};
41
42static struct clkdm_dep dma_wkup_sleep_deps[] = {
43 { .clkdm_name = "dss_clkdm" },
44 { .clkdm_name = "emif_clkdm" },
45 { .clkdm_name = "ipu_clkdm" },
46 { .clkdm_name = "ipu1_clkdm" },
47 { .clkdm_name = "ipu2_clkdm" },
48 { .clkdm_name = "iva_clkdm" },
49 { .clkdm_name = "l3init_clkdm" },
50 { .clkdm_name = "l4cfg_clkdm" },
51 { .clkdm_name = "l4per_clkdm" },
52 { .clkdm_name = "l4per2_clkdm" },
53 { .clkdm_name = "l4per3_clkdm" },
54 { .clkdm_name = "l4sec_clkdm" },
55 { .clkdm_name = "pcie_clkdm" },
56 { .clkdm_name = "wkupaon_clkdm" },
57 { NULL },
58};
59
60static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
61 { .clkdm_name = "atl_clkdm" },
62 { .clkdm_name = "cam_clkdm" },
63 { .clkdm_name = "dsp2_clkdm" },
64 { .clkdm_name = "dss_clkdm" },
65 { .clkdm_name = "emif_clkdm" },
66 { .clkdm_name = "eve1_clkdm" },
67 { .clkdm_name = "eve2_clkdm" },
68 { .clkdm_name = "eve3_clkdm" },
69 { .clkdm_name = "eve4_clkdm" },
70 { .clkdm_name = "gmac_clkdm" },
71 { .clkdm_name = "gpu_clkdm" },
72 { .clkdm_name = "ipu_clkdm" },
73 { .clkdm_name = "ipu1_clkdm" },
74 { .clkdm_name = "ipu2_clkdm" },
75 { .clkdm_name = "iva_clkdm" },
76 { .clkdm_name = "l3init_clkdm" },
77 { .clkdm_name = "l4per_clkdm" },
78 { .clkdm_name = "l4per2_clkdm" },
79 { .clkdm_name = "l4per3_clkdm" },
80 { .clkdm_name = "l4sec_clkdm" },
81 { .clkdm_name = "pcie_clkdm" },
82 { .clkdm_name = "vpe_clkdm" },
83 { .clkdm_name = "wkupaon_clkdm" },
84 { NULL },
85};
86
87static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
88 { .clkdm_name = "atl_clkdm" },
89 { .clkdm_name = "cam_clkdm" },
90 { .clkdm_name = "dsp1_clkdm" },
91 { .clkdm_name = "dss_clkdm" },
92 { .clkdm_name = "emif_clkdm" },
93 { .clkdm_name = "eve1_clkdm" },
94 { .clkdm_name = "eve2_clkdm" },
95 { .clkdm_name = "eve3_clkdm" },
96 { .clkdm_name = "eve4_clkdm" },
97 { .clkdm_name = "gmac_clkdm" },
98 { .clkdm_name = "gpu_clkdm" },
99 { .clkdm_name = "ipu_clkdm" },
100 { .clkdm_name = "ipu1_clkdm" },
101 { .clkdm_name = "ipu2_clkdm" },
102 { .clkdm_name = "iva_clkdm" },
103 { .clkdm_name = "l3init_clkdm" },
104 { .clkdm_name = "l4per_clkdm" },
105 { .clkdm_name = "l4per2_clkdm" },
106 { .clkdm_name = "l4per3_clkdm" },
107 { .clkdm_name = "l4sec_clkdm" },
108 { .clkdm_name = "pcie_clkdm" },
109 { .clkdm_name = "vpe_clkdm" },
110 { .clkdm_name = "wkupaon_clkdm" },
111 { NULL },
112};
113
114static struct clkdm_dep dss_wkup_sleep_deps[] = {
115 { .clkdm_name = "emif_clkdm" },
116 { .clkdm_name = "iva_clkdm" },
117 { NULL },
118};
119
120static struct clkdm_dep eve1_wkup_sleep_deps[] = {
121 { .clkdm_name = "emif_clkdm" },
122 { .clkdm_name = "eve2_clkdm" },
123 { .clkdm_name = "eve3_clkdm" },
124 { .clkdm_name = "eve4_clkdm" },
125 { .clkdm_name = "iva_clkdm" },
126 { NULL },
127};
128
129static struct clkdm_dep eve2_wkup_sleep_deps[] = {
130 { .clkdm_name = "emif_clkdm" },
131 { .clkdm_name = "eve1_clkdm" },
132 { .clkdm_name = "eve3_clkdm" },
133 { .clkdm_name = "eve4_clkdm" },
134 { .clkdm_name = "iva_clkdm" },
135 { NULL },
136};
137
138static struct clkdm_dep eve3_wkup_sleep_deps[] = {
139 { .clkdm_name = "emif_clkdm" },
140 { .clkdm_name = "eve1_clkdm" },
141 { .clkdm_name = "eve2_clkdm" },
142 { .clkdm_name = "eve4_clkdm" },
143 { .clkdm_name = "iva_clkdm" },
144 { NULL },
145};
146
147static struct clkdm_dep eve4_wkup_sleep_deps[] = {
148 { .clkdm_name = "emif_clkdm" },
149 { .clkdm_name = "eve1_clkdm" },
150 { .clkdm_name = "eve2_clkdm" },
151 { .clkdm_name = "eve3_clkdm" },
152 { .clkdm_name = "iva_clkdm" },
153 { NULL },
154};
155
156static struct clkdm_dep gmac_wkup_sleep_deps[] = {
157 { .clkdm_name = "emif_clkdm" },
158 { .clkdm_name = "l4per2_clkdm" },
159 { NULL },
160};
161
162static struct clkdm_dep gpu_wkup_sleep_deps[] = {
163 { .clkdm_name = "emif_clkdm" },
164 { .clkdm_name = "iva_clkdm" },
165 { NULL },
166};
167
168static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
169 { .clkdm_name = "atl_clkdm" },
170 { .clkdm_name = "dsp1_clkdm" },
171 { .clkdm_name = "dsp2_clkdm" },
172 { .clkdm_name = "dss_clkdm" },
173 { .clkdm_name = "emif_clkdm" },
174 { .clkdm_name = "eve1_clkdm" },
175 { .clkdm_name = "eve2_clkdm" },
176 { .clkdm_name = "eve3_clkdm" },
177 { .clkdm_name = "eve4_clkdm" },
178 { .clkdm_name = "gmac_clkdm" },
179 { .clkdm_name = "gpu_clkdm" },
180 { .clkdm_name = "ipu_clkdm" },
181 { .clkdm_name = "ipu2_clkdm" },
182 { .clkdm_name = "iva_clkdm" },
183 { .clkdm_name = "l3init_clkdm" },
184 { .clkdm_name = "l3main1_clkdm" },
185 { .clkdm_name = "l4cfg_clkdm" },
186 { .clkdm_name = "l4per_clkdm" },
187 { .clkdm_name = "l4per2_clkdm" },
188 { .clkdm_name = "l4per3_clkdm" },
189 { .clkdm_name = "l4sec_clkdm" },
190 { .clkdm_name = "pcie_clkdm" },
191 { .clkdm_name = "vpe_clkdm" },
192 { .clkdm_name = "wkupaon_clkdm" },
193 { NULL },
194};
195
196static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
197 { .clkdm_name = "atl_clkdm" },
198 { .clkdm_name = "dsp1_clkdm" },
199 { .clkdm_name = "dsp2_clkdm" },
200 { .clkdm_name = "dss_clkdm" },
201 { .clkdm_name = "emif_clkdm" },
202 { .clkdm_name = "eve1_clkdm" },
203 { .clkdm_name = "eve2_clkdm" },
204 { .clkdm_name = "eve3_clkdm" },
205 { .clkdm_name = "eve4_clkdm" },
206 { .clkdm_name = "gmac_clkdm" },
207 { .clkdm_name = "gpu_clkdm" },
208 { .clkdm_name = "ipu_clkdm" },
209 { .clkdm_name = "ipu1_clkdm" },
210 { .clkdm_name = "iva_clkdm" },
211 { .clkdm_name = "l3init_clkdm" },
212 { .clkdm_name = "l3main1_clkdm" },
213 { .clkdm_name = "l4cfg_clkdm" },
214 { .clkdm_name = "l4per_clkdm" },
215 { .clkdm_name = "l4per2_clkdm" },
216 { .clkdm_name = "l4per3_clkdm" },
217 { .clkdm_name = "l4sec_clkdm" },
218 { .clkdm_name = "pcie_clkdm" },
219 { .clkdm_name = "vpe_clkdm" },
220 { .clkdm_name = "wkupaon_clkdm" },
221 { NULL },
222};
223
224static struct clkdm_dep iva_wkup_sleep_deps[] = {
225 { .clkdm_name = "emif_clkdm" },
226 { NULL },
227};
228
229static struct clkdm_dep l3init_wkup_sleep_deps[] = {
230 { .clkdm_name = "emif_clkdm" },
231 { .clkdm_name = "iva_clkdm" },
232 { .clkdm_name = "l4cfg_clkdm" },
233 { .clkdm_name = "l4per_clkdm" },
234 { .clkdm_name = "l4per3_clkdm" },
235 { .clkdm_name = "l4sec_clkdm" },
236 { .clkdm_name = "wkupaon_clkdm" },
237 { NULL },
238};
239
240static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
241 { .clkdm_name = "dsp1_clkdm" },
242 { .clkdm_name = "dsp2_clkdm" },
243 { .clkdm_name = "ipu1_clkdm" },
244 { .clkdm_name = "ipu2_clkdm" },
245 { NULL },
246};
247
248static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
249 { .clkdm_name = "emif_clkdm" },
250 { .clkdm_name = "l4per_clkdm" },
251 { NULL },
252};
253
254static struct clkdm_dep mpu_wkup_sleep_deps[] = {
255 { .clkdm_name = "cam_clkdm" },
256 { .clkdm_name = "dsp1_clkdm" },
257 { .clkdm_name = "dsp2_clkdm" },
258 { .clkdm_name = "dss_clkdm" },
259 { .clkdm_name = "emif_clkdm" },
260 { .clkdm_name = "eve1_clkdm" },
261 { .clkdm_name = "eve2_clkdm" },
262 { .clkdm_name = "eve3_clkdm" },
263 { .clkdm_name = "eve4_clkdm" },
264 { .clkdm_name = "gmac_clkdm" },
265 { .clkdm_name = "gpu_clkdm" },
266 { .clkdm_name = "ipu_clkdm" },
267 { .clkdm_name = "ipu1_clkdm" },
268 { .clkdm_name = "ipu2_clkdm" },
269 { .clkdm_name = "iva_clkdm" },
270 { .clkdm_name = "l3init_clkdm" },
271 { .clkdm_name = "l3main1_clkdm" },
272 { .clkdm_name = "l4cfg_clkdm" },
273 { .clkdm_name = "l4per_clkdm" },
274 { .clkdm_name = "l4per2_clkdm" },
275 { .clkdm_name = "l4per3_clkdm" },
276 { .clkdm_name = "l4sec_clkdm" },
277 { .clkdm_name = "pcie_clkdm" },
278 { .clkdm_name = "vpe_clkdm" },
279 { .clkdm_name = "wkupaon_clkdm" },
280 { NULL },
281};
282
283static struct clkdm_dep pcie_wkup_sleep_deps[] = {
284 { .clkdm_name = "atl_clkdm" },
285 { .clkdm_name = "cam_clkdm" },
286 { .clkdm_name = "dsp1_clkdm" },
287 { .clkdm_name = "dsp2_clkdm" },
288 { .clkdm_name = "dss_clkdm" },
289 { .clkdm_name = "emif_clkdm" },
290 { .clkdm_name = "eve1_clkdm" },
291 { .clkdm_name = "eve2_clkdm" },
292 { .clkdm_name = "eve3_clkdm" },
293 { .clkdm_name = "eve4_clkdm" },
294 { .clkdm_name = "gmac_clkdm" },
295 { .clkdm_name = "gpu_clkdm" },
296 { .clkdm_name = "ipu_clkdm" },
297 { .clkdm_name = "ipu1_clkdm" },
298 { .clkdm_name = "iva_clkdm" },
299 { .clkdm_name = "l3init_clkdm" },
300 { .clkdm_name = "l4cfg_clkdm" },
301 { .clkdm_name = "l4per_clkdm" },
302 { .clkdm_name = "l4per2_clkdm" },
303 { .clkdm_name = "l4per3_clkdm" },
304 { .clkdm_name = "l4sec_clkdm" },
305 { .clkdm_name = "vpe_clkdm" },
306 { NULL },
307};
308
309static struct clkdm_dep vpe_wkup_sleep_deps[] = {
310 { .clkdm_name = "emif_clkdm" },
311 { .clkdm_name = "l4per3_clkdm" },
312 { NULL },
313};
314
315static struct clockdomain l4per3_7xx_clkdm = {
316 .name = "l4per3_clkdm",
317 .pwrdm = { .name = "l4per_pwrdm" },
318 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
319 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
320 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
321 .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
322 .flags = CLKDM_CAN_HWSUP_SWSUP,
323};
324
325static struct clockdomain l4per2_7xx_clkdm = {
326 .name = "l4per2_clkdm",
327 .pwrdm = { .name = "l4per_pwrdm" },
328 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
329 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
330 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
331 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
332 .wkdep_srcs = l4per2_wkup_sleep_deps,
333 .sleepdep_srcs = l4per2_wkup_sleep_deps,
334 .flags = CLKDM_CAN_HWSUP_SWSUP,
335};
336
337static struct clockdomain mpu0_7xx_clkdm = {
338 .name = "mpu0_clkdm",
339 .pwrdm = { .name = "cpu0_pwrdm" },
340 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
341 .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
342 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
343 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
344};
345
346static struct clockdomain iva_7xx_clkdm = {
347 .name = "iva_clkdm",
348 .pwrdm = { .name = "iva_pwrdm" },
349 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
350 .cm_inst = DRA7XX_CM_CORE_IVA_INST,
351 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
352 .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
353 .wkdep_srcs = iva_wkup_sleep_deps,
354 .sleepdep_srcs = iva_wkup_sleep_deps,
355 .flags = CLKDM_CAN_HWSUP_SWSUP,
356};
357
358static struct clockdomain coreaon_7xx_clkdm = {
359 .name = "coreaon_clkdm",
360 .pwrdm = { .name = "coreaon_pwrdm" },
361 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
362 .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
363 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
364 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
365};
366
367static struct clockdomain ipu1_7xx_clkdm = {
368 .name = "ipu1_clkdm",
369 .pwrdm = { .name = "ipu_pwrdm" },
370 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
371 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
372 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
373 .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
374 .wkdep_srcs = ipu1_wkup_sleep_deps,
375 .sleepdep_srcs = ipu1_wkup_sleep_deps,
376 .flags = CLKDM_CAN_HWSUP_SWSUP,
377};
378
379static struct clockdomain ipu2_7xx_clkdm = {
380 .name = "ipu2_clkdm",
381 .pwrdm = { .name = "core_pwrdm" },
382 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
383 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
384 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
385 .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
386 .wkdep_srcs = ipu2_wkup_sleep_deps,
387 .sleepdep_srcs = ipu2_wkup_sleep_deps,
388 .flags = CLKDM_CAN_HWSUP_SWSUP,
389};
390
391static struct clockdomain l3init_7xx_clkdm = {
392 .name = "l3init_clkdm",
393 .pwrdm = { .name = "l3init_pwrdm" },
394 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
395 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
396 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
397 .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
398 .wkdep_srcs = l3init_wkup_sleep_deps,
399 .sleepdep_srcs = l3init_wkup_sleep_deps,
400 .flags = CLKDM_CAN_HWSUP_SWSUP,
401};
402
403static struct clockdomain l4sec_7xx_clkdm = {
404 .name = "l4sec_clkdm",
405 .pwrdm = { .name = "l4per_pwrdm" },
406 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
407 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
408 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
409 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
410 .wkdep_srcs = l4sec_wkup_sleep_deps,
411 .sleepdep_srcs = l4sec_wkup_sleep_deps,
412 .flags = CLKDM_CAN_HWSUP_SWSUP,
413};
414
415static struct clockdomain l3main1_7xx_clkdm = {
416 .name = "l3main1_clkdm",
417 .pwrdm = { .name = "core_pwrdm" },
418 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
419 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
420 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
421 .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
422 .flags = CLKDM_CAN_HWSUP,
423};
424
425static struct clockdomain vpe_7xx_clkdm = {
426 .name = "vpe_clkdm",
427 .pwrdm = { .name = "vpe_pwrdm" },
428 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
429 .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
430 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
431 .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
432 .wkdep_srcs = vpe_wkup_sleep_deps,
433 .sleepdep_srcs = vpe_wkup_sleep_deps,
434 .flags = CLKDM_CAN_HWSUP_SWSUP,
435};
436
437static struct clockdomain mpu_7xx_clkdm = {
438 .name = "mpu_clkdm",
439 .pwrdm = { .name = "mpu_pwrdm" },
440 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
441 .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
442 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
443 .wkdep_srcs = mpu_wkup_sleep_deps,
444 .sleepdep_srcs = mpu_wkup_sleep_deps,
445 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
446};
447
448static struct clockdomain custefuse_7xx_clkdm = {
449 .name = "custefuse_clkdm",
450 .pwrdm = { .name = "custefuse_pwrdm" },
451 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
452 .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
453 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
454 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
455};
456
457static struct clockdomain ipu_7xx_clkdm = {
458 .name = "ipu_clkdm",
459 .pwrdm = { .name = "ipu_pwrdm" },
460 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
461 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
462 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
463 .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
464 .flags = CLKDM_CAN_HWSUP_SWSUP,
465};
466
467static struct clockdomain mpu1_7xx_clkdm = {
468 .name = "mpu1_clkdm",
469 .pwrdm = { .name = "cpu1_pwrdm" },
470 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
471 .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
472 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
473 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
474};
475
476static struct clockdomain gmac_7xx_clkdm = {
477 .name = "gmac_clkdm",
478 .pwrdm = { .name = "l3init_pwrdm" },
479 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
480 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
481 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
482 .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
483 .wkdep_srcs = gmac_wkup_sleep_deps,
484 .sleepdep_srcs = gmac_wkup_sleep_deps,
485 .flags = CLKDM_CAN_HWSUP_SWSUP,
486};
487
488static struct clockdomain l4cfg_7xx_clkdm = {
489 .name = "l4cfg_clkdm",
490 .pwrdm = { .name = "core_pwrdm" },
491 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
492 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
493 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
494 .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
495 .flags = CLKDM_CAN_HWSUP,
496};
497
498static struct clockdomain dma_7xx_clkdm = {
499 .name = "dma_clkdm",
500 .pwrdm = { .name = "core_pwrdm" },
501 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
502 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
503 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
504 .wkdep_srcs = dma_wkup_sleep_deps,
505 .sleepdep_srcs = dma_wkup_sleep_deps,
506 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
507};
508
509static struct clockdomain rtc_7xx_clkdm = {
510 .name = "rtc_clkdm",
511 .pwrdm = { .name = "rtc_pwrdm" },
512 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
513 .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
514 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
515 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
516};
517
518static struct clockdomain pcie_7xx_clkdm = {
519 .name = "pcie_clkdm",
520 .pwrdm = { .name = "l3init_pwrdm" },
521 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
522 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
523 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
524 .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
525 .wkdep_srcs = pcie_wkup_sleep_deps,
526 .sleepdep_srcs = pcie_wkup_sleep_deps,
527 .flags = CLKDM_CAN_HWSUP_SWSUP,
528};
529
530static struct clockdomain atl_7xx_clkdm = {
531 .name = "atl_clkdm",
532 .pwrdm = { .name = "core_pwrdm" },
533 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
534 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
535 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
536 .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
537 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
538};
539
540static struct clockdomain l3instr_7xx_clkdm = {
541 .name = "l3instr_clkdm",
542 .pwrdm = { .name = "core_pwrdm" },
543 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
544 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
545 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
546};
547
548static struct clockdomain dss_7xx_clkdm = {
549 .name = "dss_clkdm",
550 .pwrdm = { .name = "dss_pwrdm" },
551 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
552 .cm_inst = DRA7XX_CM_CORE_DSS_INST,
553 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
554 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
555 .wkdep_srcs = dss_wkup_sleep_deps,
556 .sleepdep_srcs = dss_wkup_sleep_deps,
557 .flags = CLKDM_CAN_HWSUP_SWSUP,
558};
559
560static struct clockdomain emif_7xx_clkdm = {
561 .name = "emif_clkdm",
562 .pwrdm = { .name = "core_pwrdm" },
563 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
564 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
565 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
566 .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
567 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
568};
569
570static struct clockdomain emu_7xx_clkdm = {
571 .name = "emu_clkdm",
572 .pwrdm = { .name = "emu_pwrdm" },
573 .prcm_partition = DRA7XX_PRM_PARTITION,
574 .cm_inst = DRA7XX_PRM_EMU_CM_INST,
575 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
576 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
577};
578
579static struct clockdomain dsp2_7xx_clkdm = {
580 .name = "dsp2_clkdm",
581 .pwrdm = { .name = "dsp2_pwrdm" },
582 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
583 .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
584 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
585 .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
586 .wkdep_srcs = dsp2_wkup_sleep_deps,
587 .sleepdep_srcs = dsp2_wkup_sleep_deps,
588 .flags = CLKDM_CAN_HWSUP_SWSUP,
589};
590
591static struct clockdomain dsp1_7xx_clkdm = {
592 .name = "dsp1_clkdm",
593 .pwrdm = { .name = "dsp1_pwrdm" },
594 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
595 .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
596 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
597 .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
598 .wkdep_srcs = dsp1_wkup_sleep_deps,
599 .sleepdep_srcs = dsp1_wkup_sleep_deps,
600 .flags = CLKDM_CAN_HWSUP_SWSUP,
601};
602
603static struct clockdomain cam_7xx_clkdm = {
604 .name = "cam_clkdm",
605 .pwrdm = { .name = "cam_pwrdm" },
606 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
607 .cm_inst = DRA7XX_CM_CORE_CAM_INST,
608 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
609 .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
610 .wkdep_srcs = cam_wkup_sleep_deps,
611 .sleepdep_srcs = cam_wkup_sleep_deps,
612 .flags = CLKDM_CAN_HWSUP_SWSUP,
613};
614
615static struct clockdomain l4per_7xx_clkdm = {
616 .name = "l4per_clkdm",
617 .pwrdm = { .name = "l4per_pwrdm" },
618 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
619 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
620 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
621 .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
622 .flags = CLKDM_CAN_HWSUP_SWSUP,
623};
624
625static struct clockdomain gpu_7xx_clkdm = {
626 .name = "gpu_clkdm",
627 .pwrdm = { .name = "gpu_pwrdm" },
628 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
629 .cm_inst = DRA7XX_CM_CORE_GPU_INST,
630 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
631 .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
632 .wkdep_srcs = gpu_wkup_sleep_deps,
633 .sleepdep_srcs = gpu_wkup_sleep_deps,
634 .flags = CLKDM_CAN_HWSUP_SWSUP,
635};
636
637static struct clockdomain eve4_7xx_clkdm = {
638 .name = "eve4_clkdm",
639 .pwrdm = { .name = "eve4_pwrdm" },
640 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
641 .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
642 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
643 .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
644 .wkdep_srcs = eve4_wkup_sleep_deps,
645 .sleepdep_srcs = eve4_wkup_sleep_deps,
646 .flags = CLKDM_CAN_HWSUP_SWSUP,
647};
648
649static struct clockdomain eve2_7xx_clkdm = {
650 .name = "eve2_clkdm",
651 .pwrdm = { .name = "eve2_pwrdm" },
652 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
653 .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
654 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
655 .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
656 .wkdep_srcs = eve2_wkup_sleep_deps,
657 .sleepdep_srcs = eve2_wkup_sleep_deps,
658 .flags = CLKDM_CAN_HWSUP_SWSUP,
659};
660
661static struct clockdomain eve3_7xx_clkdm = {
662 .name = "eve3_clkdm",
663 .pwrdm = { .name = "eve3_pwrdm" },
664 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
665 .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
666 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
667 .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
668 .wkdep_srcs = eve3_wkup_sleep_deps,
669 .sleepdep_srcs = eve3_wkup_sleep_deps,
670 .flags = CLKDM_CAN_HWSUP_SWSUP,
671};
672
673static struct clockdomain wkupaon_7xx_clkdm = {
674 .name = "wkupaon_clkdm",
675 .pwrdm = { .name = "wkupaon_pwrdm" },
676 .prcm_partition = DRA7XX_PRM_PARTITION,
677 .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
678 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
679 .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
680 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
681};
682
683static struct clockdomain eve1_7xx_clkdm = {
684 .name = "eve1_clkdm",
685 .pwrdm = { .name = "eve1_pwrdm" },
686 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
687 .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
688 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
689 .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
690 .wkdep_srcs = eve1_wkup_sleep_deps,
691 .sleepdep_srcs = eve1_wkup_sleep_deps,
692 .flags = CLKDM_CAN_HWSUP_SWSUP,
693};
694
695/* As clockdomains are added or removed above, this list must also be changed */
696static struct clockdomain *clockdomains_dra7xx[] __initdata = {
697 &l4per3_7xx_clkdm,
698 &l4per2_7xx_clkdm,
699 &mpu0_7xx_clkdm,
700 &iva_7xx_clkdm,
701 &coreaon_7xx_clkdm,
702 &ipu1_7xx_clkdm,
703 &ipu2_7xx_clkdm,
704 &l3init_7xx_clkdm,
705 &l4sec_7xx_clkdm,
706 &l3main1_7xx_clkdm,
707 &vpe_7xx_clkdm,
708 &mpu_7xx_clkdm,
709 &custefuse_7xx_clkdm,
710 &ipu_7xx_clkdm,
711 &mpu1_7xx_clkdm,
712 &gmac_7xx_clkdm,
713 &l4cfg_7xx_clkdm,
714 &dma_7xx_clkdm,
715 &rtc_7xx_clkdm,
716 &pcie_7xx_clkdm,
717 &atl_7xx_clkdm,
718 &l3instr_7xx_clkdm,
719 &dss_7xx_clkdm,
720 &emif_7xx_clkdm,
721 &emu_7xx_clkdm,
722 &dsp2_7xx_clkdm,
723 &dsp1_7xx_clkdm,
724 &cam_7xx_clkdm,
725 &l4per_7xx_clkdm,
726 &gpu_7xx_clkdm,
727 &eve4_7xx_clkdm,
728 &eve2_7xx_clkdm,
729 &eve3_7xx_clkdm,
730 &wkupaon_7xx_clkdm,
731 &eve1_7xx_clkdm,
732 NULL
733};
734
735void __init dra7xx_clockdomains_init(void)
736{
737 clkdm_register_platform_funcs(&omap4_clkdm_operations);
738 clkdm_register_clkdms(clockdomains_dra7xx);
739 clkdm_complete_init();
740}
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 669ef51b17a8..8538669cc2ad 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,439 +14,121 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17/* Bits shared between registers */
18
19/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
20#define OMAP24XX_EN_CAM_SHIFT 31 17#define OMAP24XX_EN_CAM_SHIFT 31
21#define OMAP24XX_EN_CAM_MASK (1 << 31)
22#define OMAP24XX_EN_WDT4_SHIFT 29 18#define OMAP24XX_EN_WDT4_SHIFT 29
23#define OMAP24XX_EN_WDT4_MASK (1 << 29)
24#define OMAP2420_EN_WDT3_SHIFT 28 19#define OMAP2420_EN_WDT3_SHIFT 28
25#define OMAP2420_EN_WDT3_MASK (1 << 28)
26#define OMAP24XX_EN_MSPRO_SHIFT 27 20#define OMAP24XX_EN_MSPRO_SHIFT 27
27#define OMAP24XX_EN_MSPRO_MASK (1 << 27)
28#define OMAP24XX_EN_FAC_SHIFT 25 21#define OMAP24XX_EN_FAC_SHIFT 25
29#define OMAP24XX_EN_FAC_MASK (1 << 25)
30#define OMAP2420_EN_EAC_SHIFT 24 22#define OMAP2420_EN_EAC_SHIFT 24
31#define OMAP2420_EN_EAC_MASK (1 << 24)
32#define OMAP24XX_EN_HDQ_SHIFT 23 23#define OMAP24XX_EN_HDQ_SHIFT 23
33#define OMAP24XX_EN_HDQ_MASK (1 << 23)
34#define OMAP2420_EN_I2C2_SHIFT 20 24#define OMAP2420_EN_I2C2_SHIFT 20
35#define OMAP2420_EN_I2C2_MASK (1 << 20)
36#define OMAP2420_EN_I2C1_SHIFT 19 25#define OMAP2420_EN_I2C1_SHIFT 19
37#define OMAP2420_EN_I2C1_MASK (1 << 19)
38
39/* CM_FCLKEN2_CORE and CM_ICLKEN2_CORE shared bits */
40#define OMAP2430_EN_MCBSP5_SHIFT 5 26#define OMAP2430_EN_MCBSP5_SHIFT 5
41#define OMAP2430_EN_MCBSP5_MASK (1 << 5)
42#define OMAP2430_EN_MCBSP4_SHIFT 4 27#define OMAP2430_EN_MCBSP4_SHIFT 4
43#define OMAP2430_EN_MCBSP4_MASK (1 << 4)
44#define OMAP2430_EN_MCBSP3_SHIFT 3 28#define OMAP2430_EN_MCBSP3_SHIFT 3
45#define OMAP2430_EN_MCBSP3_MASK (1 << 3)
46#define OMAP24XX_EN_SSI_SHIFT 1 29#define OMAP24XX_EN_SSI_SHIFT 1
47#define OMAP24XX_EN_SSI_MASK (1 << 1)
48
49/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
50#define OMAP24XX_EN_MPU_WDT_SHIFT 3 30#define OMAP24XX_EN_MPU_WDT_SHIFT 3
51#define OMAP24XX_EN_MPU_WDT_MASK (1 << 3)
52
53/* Bits specific to each register */
54
55/* CM_IDLEST_MPU */
56/* 2430 only */
57#define OMAP2430_ST_MPU_MASK (1 << 0)
58
59/* CM_CLKSEL_MPU */
60#define OMAP24XX_CLKSEL_MPU_SHIFT 0 31#define OMAP24XX_CLKSEL_MPU_SHIFT 0
61#define OMAP24XX_CLKSEL_MPU_MASK (0x1f << 0)
62#define OMAP24XX_CLKSEL_MPU_WIDTH 5 32#define OMAP24XX_CLKSEL_MPU_WIDTH 5
63
64/* CM_CLKSTCTRL_MPU */
65#define OMAP24XX_AUTOSTATE_MPU_SHIFT 0
66#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0) 33#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
67
68/* CM_FCLKEN1_CORE specific bits*/
69#define OMAP24XX_EN_TV_SHIFT 2 34#define OMAP24XX_EN_TV_SHIFT 2
70#define OMAP24XX_EN_TV_MASK (1 << 2)
71#define OMAP24XX_EN_DSS2_SHIFT 1 35#define OMAP24XX_EN_DSS2_SHIFT 1
72#define OMAP24XX_EN_DSS2_MASK (1 << 1)
73#define OMAP24XX_EN_DSS1_SHIFT 0 36#define OMAP24XX_EN_DSS1_SHIFT 0
74#define OMAP24XX_EN_DSS1_MASK (1 << 0) 37#define OMAP24XX_EN_DSS1_MASK (1 << 0)
75
76/* CM_FCLKEN2_CORE specific bits */
77#define OMAP2430_EN_I2CHS2_SHIFT 20 38#define OMAP2430_EN_I2CHS2_SHIFT 20
78#define OMAP2430_EN_I2CHS2_MASK (1 << 20)
79#define OMAP2430_EN_I2CHS1_SHIFT 19 39#define OMAP2430_EN_I2CHS1_SHIFT 19
80#define OMAP2430_EN_I2CHS1_MASK (1 << 19)
81#define OMAP2430_EN_MMCHSDB2_SHIFT 17 40#define OMAP2430_EN_MMCHSDB2_SHIFT 17
82#define OMAP2430_EN_MMCHSDB2_MASK (1 << 17)
83#define OMAP2430_EN_MMCHSDB1_SHIFT 16 41#define OMAP2430_EN_MMCHSDB1_SHIFT 16
84#define OMAP2430_EN_MMCHSDB1_MASK (1 << 16)
85
86/* CM_ICLKEN1_CORE specific bits */
87#define OMAP24XX_EN_MAILBOXES_SHIFT 30 42#define OMAP24XX_EN_MAILBOXES_SHIFT 30
88#define OMAP24XX_EN_MAILBOXES_MASK (1 << 30)
89#define OMAP24XX_EN_DSS_SHIFT 0
90#define OMAP24XX_EN_DSS_MASK (1 << 0)
91
92/* CM_ICLKEN2_CORE specific bits */
93
94/* CM_ICLKEN3_CORE */
95/* 2430 only */
96#define OMAP2430_EN_SDRC_SHIFT 2 43#define OMAP2430_EN_SDRC_SHIFT 2
97#define OMAP2430_EN_SDRC_MASK (1 << 2)
98
99/* CM_ICLKEN4_CORE */
100#define OMAP24XX_EN_PKA_SHIFT 4 44#define OMAP24XX_EN_PKA_SHIFT 4
101#define OMAP24XX_EN_PKA_MASK (1 << 4)
102#define OMAP24XX_EN_AES_SHIFT 3 45#define OMAP24XX_EN_AES_SHIFT 3
103#define OMAP24XX_EN_AES_MASK (1 << 3)
104#define OMAP24XX_EN_RNG_SHIFT 2 46#define OMAP24XX_EN_RNG_SHIFT 2
105#define OMAP24XX_EN_RNG_MASK (1 << 2)
106#define OMAP24XX_EN_SHA_SHIFT 1 47#define OMAP24XX_EN_SHA_SHIFT 1
107#define OMAP24XX_EN_SHA_MASK (1 << 1)
108#define OMAP24XX_EN_DES_SHIFT 0 48#define OMAP24XX_EN_DES_SHIFT 0
109#define OMAP24XX_EN_DES_MASK (1 << 0)
110
111/* CM_IDLEST1_CORE specific bits */
112#define OMAP24XX_ST_MAILBOXES_SHIFT 30 49#define OMAP24XX_ST_MAILBOXES_SHIFT 30
113#define OMAP24XX_ST_MAILBOXES_MASK (1 << 30)
114#define OMAP24XX_ST_WDT4_SHIFT 29
115#define OMAP24XX_ST_WDT4_MASK (1 << 29)
116#define OMAP2420_ST_WDT3_SHIFT 28
117#define OMAP2420_ST_WDT3_MASK (1 << 28)
118#define OMAP24XX_ST_MSPRO_SHIFT 27
119#define OMAP24XX_ST_MSPRO_MASK (1 << 27)
120#define OMAP24XX_ST_FAC_SHIFT 25
121#define OMAP24XX_ST_FAC_MASK (1 << 25)
122#define OMAP2420_ST_EAC_SHIFT 24
123#define OMAP2420_ST_EAC_MASK (1 << 24)
124#define OMAP24XX_ST_HDQ_SHIFT 23 50#define OMAP24XX_ST_HDQ_SHIFT 23
125#define OMAP24XX_ST_HDQ_MASK (1 << 23)
126#define OMAP2420_ST_I2C2_SHIFT 20 51#define OMAP2420_ST_I2C2_SHIFT 20
127#define OMAP2420_ST_I2C2_MASK (1 << 20)
128#define OMAP2430_ST_I2CHS1_SHIFT 19 52#define OMAP2430_ST_I2CHS1_SHIFT 19
129#define OMAP2430_ST_I2CHS1_MASK (1 << 19)
130#define OMAP2420_ST_I2C1_SHIFT 19 53#define OMAP2420_ST_I2C1_SHIFT 19
131#define OMAP2420_ST_I2C1_MASK (1 << 19)
132#define OMAP2430_ST_I2CHS2_SHIFT 20 54#define OMAP2430_ST_I2CHS2_SHIFT 20
133#define OMAP2430_ST_I2CHS2_MASK (1 << 20)
134#define OMAP24XX_ST_MCBSP2_SHIFT 16 55#define OMAP24XX_ST_MCBSP2_SHIFT 16
135#define OMAP24XX_ST_MCBSP2_MASK (1 << 16)
136#define OMAP24XX_ST_MCBSP1_SHIFT 15 56#define OMAP24XX_ST_MCBSP1_SHIFT 15
137#define OMAP24XX_ST_MCBSP1_MASK (1 << 15)
138#define OMAP24XX_ST_DSS_SHIFT 0 57#define OMAP24XX_ST_DSS_SHIFT 0
139#define OMAP24XX_ST_DSS_MASK (1 << 0)
140
141/* CM_IDLEST2_CORE */
142#define OMAP2430_ST_MCBSP5_SHIFT 5 58#define OMAP2430_ST_MCBSP5_SHIFT 5
143#define OMAP2430_ST_MCBSP5_MASK (1 << 5)
144#define OMAP2430_ST_MCBSP4_SHIFT 4 59#define OMAP2430_ST_MCBSP4_SHIFT 4
145#define OMAP2430_ST_MCBSP4_MASK (1 << 4)
146#define OMAP2430_ST_MCBSP3_SHIFT 3 60#define OMAP2430_ST_MCBSP3_SHIFT 3
147#define OMAP2430_ST_MCBSP3_MASK (1 << 3)
148#define OMAP24XX_ST_SSI_SHIFT 1
149#define OMAP24XX_ST_SSI_MASK (1 << 1)
150
151/* CM_IDLEST3_CORE */
152/* 2430 only */
153#define OMAP2430_ST_SDRC_MASK (1 << 2)
154
155/* CM_IDLEST4_CORE */
156#define OMAP24XX_ST_PKA_SHIFT 4
157#define OMAP24XX_ST_PKA_MASK (1 << 4)
158#define OMAP24XX_ST_AES_SHIFT 3 61#define OMAP24XX_ST_AES_SHIFT 3
159#define OMAP24XX_ST_AES_MASK (1 << 3)
160#define OMAP24XX_ST_RNG_SHIFT 2 62#define OMAP24XX_ST_RNG_SHIFT 2
161#define OMAP24XX_ST_RNG_MASK (1 << 2)
162#define OMAP24XX_ST_SHA_SHIFT 1 63#define OMAP24XX_ST_SHA_SHIFT 1
163#define OMAP24XX_ST_SHA_MASK (1 << 1)
164#define OMAP24XX_ST_DES_SHIFT 0
165#define OMAP24XX_ST_DES_MASK (1 << 0)
166
167/* CM_AUTOIDLE1_CORE */
168#define OMAP24XX_AUTO_CAM_MASK (1 << 31)
169#define OMAP24XX_AUTO_MAILBOXES_MASK (1 << 30)
170#define OMAP24XX_AUTO_WDT4_MASK (1 << 29)
171#define OMAP2420_AUTO_WDT3_MASK (1 << 28)
172#define OMAP24XX_AUTO_MSPRO_MASK (1 << 27)
173#define OMAP2420_AUTO_MMC_MASK (1 << 26)
174#define OMAP24XX_AUTO_FAC_MASK (1 << 25)
175#define OMAP2420_AUTO_EAC_MASK (1 << 24)
176#define OMAP24XX_AUTO_HDQ_MASK (1 << 23)
177#define OMAP24XX_AUTO_UART2_MASK (1 << 22)
178#define OMAP24XX_AUTO_UART1_MASK (1 << 21)
179#define OMAP24XX_AUTO_I2C2_MASK (1 << 20)
180#define OMAP24XX_AUTO_I2C1_MASK (1 << 19)
181#define OMAP24XX_AUTO_MCSPI2_MASK (1 << 18)
182#define OMAP24XX_AUTO_MCSPI1_MASK (1 << 17)
183#define OMAP24XX_AUTO_MCBSP2_MASK (1 << 16)
184#define OMAP24XX_AUTO_MCBSP1_MASK (1 << 15)
185#define OMAP24XX_AUTO_GPT12_MASK (1 << 14)
186#define OMAP24XX_AUTO_GPT11_MASK (1 << 13)
187#define OMAP24XX_AUTO_GPT10_MASK (1 << 12)
188#define OMAP24XX_AUTO_GPT9_MASK (1 << 11)
189#define OMAP24XX_AUTO_GPT8_MASK (1 << 10)
190#define OMAP24XX_AUTO_GPT7_MASK (1 << 9)
191#define OMAP24XX_AUTO_GPT6_MASK (1 << 8)
192#define OMAP24XX_AUTO_GPT5_MASK (1 << 7)
193#define OMAP24XX_AUTO_GPT4_MASK (1 << 6)
194#define OMAP24XX_AUTO_GPT3_MASK (1 << 5)
195#define OMAP24XX_AUTO_GPT2_MASK (1 << 4)
196#define OMAP2420_AUTO_VLYNQ_MASK (1 << 3)
197#define OMAP24XX_AUTO_DSS_MASK (1 << 0)
198
199/* CM_AUTOIDLE2_CORE */
200#define OMAP2430_AUTO_MDM_INTC_MASK (1 << 11)
201#define OMAP2430_AUTO_GPIO5_MASK (1 << 10)
202#define OMAP2430_AUTO_MCSPI3_MASK (1 << 9)
203#define OMAP2430_AUTO_MMCHS2_MASK (1 << 8)
204#define OMAP2430_AUTO_MMCHS1_MASK (1 << 7)
205#define OMAP2430_AUTO_USBHS_MASK (1 << 6)
206#define OMAP2430_AUTO_MCBSP5_MASK (1 << 5)
207#define OMAP2430_AUTO_MCBSP4_MASK (1 << 4)
208#define OMAP2430_AUTO_MCBSP3_MASK (1 << 3)
209#define OMAP24XX_AUTO_UART3_MASK (1 << 2)
210#define OMAP24XX_AUTO_SSI_MASK (1 << 1)
211#define OMAP24XX_AUTO_USB_MASK (1 << 0)
212
213/* CM_AUTOIDLE3_CORE */
214#define OMAP24XX_AUTO_SDRC_SHIFT 2 64#define OMAP24XX_AUTO_SDRC_SHIFT 2
215#define OMAP24XX_AUTO_SDRC_MASK (1 << 2)
216#define OMAP24XX_AUTO_GPMC_SHIFT 1 65#define OMAP24XX_AUTO_GPMC_SHIFT 1
217#define OMAP24XX_AUTO_GPMC_MASK (1 << 1)
218#define OMAP24XX_AUTO_SDMA_SHIFT 0 66#define OMAP24XX_AUTO_SDMA_SHIFT 0
219#define OMAP24XX_AUTO_SDMA_MASK (1 << 0)
220
221/* CM_AUTOIDLE4_CORE */
222#define OMAP24XX_AUTO_PKA_MASK (1 << 4)
223#define OMAP24XX_AUTO_AES_MASK (1 << 3)
224#define OMAP24XX_AUTO_RNG_MASK (1 << 2)
225#define OMAP24XX_AUTO_SHA_MASK (1 << 1)
226#define OMAP24XX_AUTO_DES_MASK (1 << 0)
227
228/* CM_CLKSEL1_CORE */
229#define OMAP24XX_CLKSEL_USB_SHIFT 25
230#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25) 67#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
231#define OMAP24XX_CLKSEL_SSI_SHIFT 20
232#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20) 68#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
233#define OMAP2420_CLKSEL_VLYNQ_SHIFT 15
234#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15) 69#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
235#define OMAP24XX_CLKSEL_DSS2_SHIFT 13
236#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13) 70#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
237#define OMAP24XX_CLKSEL_DSS1_SHIFT 8
238#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8) 71#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
239#define OMAP24XX_CLKSEL_L4_SHIFT 5 72#define OMAP24XX_CLKSEL_L4_SHIFT 5
240#define OMAP24XX_CLKSEL_L4_MASK (0x3 << 5)
241#define OMAP24XX_CLKSEL_L4_WIDTH 2 73#define OMAP24XX_CLKSEL_L4_WIDTH 2
242#define OMAP24XX_CLKSEL_L3_SHIFT 0 74#define OMAP24XX_CLKSEL_L3_SHIFT 0
243#define OMAP24XX_CLKSEL_L3_MASK (0x1f << 0)
244#define OMAP24XX_CLKSEL_L3_WIDTH 5 75#define OMAP24XX_CLKSEL_L3_WIDTH 5
245
246/* CM_CLKSEL2_CORE */
247#define OMAP24XX_CLKSEL_GPT12_SHIFT 22
248#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22) 76#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
249#define OMAP24XX_CLKSEL_GPT11_SHIFT 20
250#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20) 77#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
251#define OMAP24XX_CLKSEL_GPT10_SHIFT 18
252#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18) 78#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
253#define OMAP24XX_CLKSEL_GPT9_SHIFT 16
254#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16) 79#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
255#define OMAP24XX_CLKSEL_GPT8_SHIFT 14
256#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14) 80#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
257#define OMAP24XX_CLKSEL_GPT7_SHIFT 12
258#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12) 81#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
259#define OMAP24XX_CLKSEL_GPT6_SHIFT 10
260#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10) 82#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
261#define OMAP24XX_CLKSEL_GPT5_SHIFT 8
262#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8) 83#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
263#define OMAP24XX_CLKSEL_GPT4_SHIFT 6
264#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6) 84#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
265#define OMAP24XX_CLKSEL_GPT3_SHIFT 4
266#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4) 85#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
267#define OMAP24XX_CLKSEL_GPT2_SHIFT 2
268#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2) 86#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
269
270/* CM_CLKSTCTRL_CORE */
271#define OMAP24XX_AUTOSTATE_DSS_SHIFT 2
272#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2) 87#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
273#define OMAP24XX_AUTOSTATE_L4_SHIFT 1
274#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1) 88#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
275#define OMAP24XX_AUTOSTATE_L3_SHIFT 0
276#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0) 89#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
277
278/* CM_FCLKEN_GFX */
279#define OMAP24XX_EN_3D_SHIFT 2 90#define OMAP24XX_EN_3D_SHIFT 2
280#define OMAP24XX_EN_3D_MASK (1 << 2)
281#define OMAP24XX_EN_2D_SHIFT 1 91#define OMAP24XX_EN_2D_SHIFT 1
282#define OMAP24XX_EN_2D_MASK (1 << 1)
283
284/* CM_ICLKEN_GFX specific bits */
285
286/* CM_IDLEST_GFX specific bits */
287
288/* CM_CLKSEL_GFX specific bits */
289
290/* CM_CLKSTCTRL_GFX */
291#define OMAP24XX_AUTOSTATE_GFX_SHIFT 0
292#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0) 92#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
293
294/* CM_FCLKEN_WKUP specific bits */
295
296/* CM_ICLKEN_WKUP specific bits */
297#define OMAP2430_EN_ICR_SHIFT 6 93#define OMAP2430_EN_ICR_SHIFT 6
298#define OMAP2430_EN_ICR_MASK (1 << 6)
299#define OMAP24XX_EN_OMAPCTRL_SHIFT 5 94#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
300#define OMAP24XX_EN_OMAPCTRL_MASK (1 << 5)
301#define OMAP24XX_EN_WDT1_SHIFT 4 95#define OMAP24XX_EN_WDT1_SHIFT 4
302#define OMAP24XX_EN_WDT1_MASK (1 << 4)
303#define OMAP24XX_EN_32KSYNC_SHIFT 1 96#define OMAP24XX_EN_32KSYNC_SHIFT 1
304#define OMAP24XX_EN_32KSYNC_MASK (1 << 1)
305
306/* CM_IDLEST_WKUP specific bits */
307#define OMAP2430_ST_ICR_SHIFT 6
308#define OMAP2430_ST_ICR_MASK (1 << 6)
309#define OMAP24XX_ST_OMAPCTRL_SHIFT 5
310#define OMAP24XX_ST_OMAPCTRL_MASK (1 << 5)
311#define OMAP24XX_ST_WDT1_SHIFT 4
312#define OMAP24XX_ST_WDT1_MASK (1 << 4)
313#define OMAP24XX_ST_MPU_WDT_SHIFT 3 97#define OMAP24XX_ST_MPU_WDT_SHIFT 3
314#define OMAP24XX_ST_MPU_WDT_MASK (1 << 3)
315#define OMAP24XX_ST_32KSYNC_SHIFT 1 98#define OMAP24XX_ST_32KSYNC_SHIFT 1
316#define OMAP24XX_ST_32KSYNC_MASK (1 << 1)
317
318/* CM_AUTOIDLE_WKUP */
319#define OMAP24XX_AUTO_OMAPCTRL_MASK (1 << 5)
320#define OMAP24XX_AUTO_WDT1_MASK (1 << 4)
321#define OMAP24XX_AUTO_MPU_WDT_MASK (1 << 3)
322#define OMAP24XX_AUTO_GPIOS_MASK (1 << 2)
323#define OMAP24XX_AUTO_32KSYNC_MASK (1 << 1)
324#define OMAP24XX_AUTO_GPT1_MASK (1 << 0)
325
326/* CM_CLKSEL_WKUP */
327#define OMAP24XX_CLKSEL_GPT1_SHIFT 0
328#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0) 99#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
329
330/* CM_CLKEN_PLL */
331#define OMAP24XX_EN_54M_PLL_SHIFT 6 100#define OMAP24XX_EN_54M_PLL_SHIFT 6
332#define OMAP24XX_EN_54M_PLL_MASK (0x3 << 6)
333#define OMAP24XX_EN_96M_PLL_SHIFT 2 101#define OMAP24XX_EN_96M_PLL_SHIFT 2
334#define OMAP24XX_EN_96M_PLL_MASK (0x3 << 2)
335#define OMAP24XX_EN_DPLL_SHIFT 0
336#define OMAP24XX_EN_DPLL_MASK (0x3 << 0) 102#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
337
338/* CM_IDLEST_CKGEN */
339#define OMAP24XX_ST_54M_APLL_SHIFT 9 103#define OMAP24XX_ST_54M_APLL_SHIFT 9
340#define OMAP24XX_ST_54M_APLL_MASK (1 << 9)
341#define OMAP24XX_ST_96M_APLL_SHIFT 8 104#define OMAP24XX_ST_96M_APLL_SHIFT 8
342#define OMAP24XX_ST_96M_APLL_MASK (1 << 8)
343#define OMAP24XX_ST_54M_CLK_MASK (1 << 6)
344#define OMAP24XX_ST_12M_CLK_MASK (1 << 5)
345#define OMAP24XX_ST_48M_CLK_MASK (1 << 4)
346#define OMAP24XX_ST_96M_CLK_MASK (1 << 2)
347#define OMAP24XX_ST_CORE_CLK_SHIFT 0
348#define OMAP24XX_ST_CORE_CLK_MASK (0x3 << 0)
349
350/* CM_AUTOIDLE_PLL */
351#define OMAP24XX_AUTO_54M_SHIFT 6
352#define OMAP24XX_AUTO_54M_MASK (0x3 << 6) 105#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
353#define OMAP24XX_AUTO_96M_SHIFT 2
354#define OMAP24XX_AUTO_96M_MASK (0x3 << 2) 106#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
355#define OMAP24XX_AUTO_DPLL_SHIFT 0 107#define OMAP24XX_AUTO_DPLL_SHIFT 0
356#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) 108#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
357
358/* CM_CLKSEL1_PLL */
359#define OMAP2430_MAXDPLLFASTLOCK_SHIFT 28
360#define OMAP2430_MAXDPLLFASTLOCK_MASK (0x7 << 28)
361#define OMAP24XX_APLLS_CLKIN_SHIFT 23 109#define OMAP24XX_APLLS_CLKIN_SHIFT 23
362#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) 110#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
363#define OMAP24XX_DPLL_MULT_SHIFT 12
364#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) 111#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
365#define OMAP24XX_DPLL_DIV_SHIFT 8
366#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 112#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
367#define OMAP24XX_54M_SOURCE_SHIFT 5 113#define OMAP24XX_54M_SOURCE_SHIFT 5
368#define OMAP24XX_54M_SOURCE_MASK (1 << 5)
369#define OMAP24XX_54M_SOURCE_WIDTH 1 114#define OMAP24XX_54M_SOURCE_WIDTH 1
370#define OMAP2430_96M_SOURCE_SHIFT 4 115#define OMAP2430_96M_SOURCE_SHIFT 4
371#define OMAP2430_96M_SOURCE_MASK (1 << 4)
372#define OMAP2430_96M_SOURCE_WIDTH 1 116#define OMAP2430_96M_SOURCE_WIDTH 1
373#define OMAP24XX_48M_SOURCE_SHIFT 3
374#define OMAP24XX_48M_SOURCE_MASK (1 << 3) 117#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
375#define OMAP2430_ALTCLK_SOURCE_SHIFT 0
376#define OMAP2430_ALTCLK_SOURCE_MASK (0x7 << 0)
377
378/* CM_CLKSEL2_PLL */
379#define OMAP24XX_CORE_CLK_SRC_SHIFT 0
380#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0) 118#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
381
382/* CM_FCLKEN_DSP */
383#define OMAP2420_EN_IVA_COP_SHIFT 10 119#define OMAP2420_EN_IVA_COP_SHIFT 10
384#define OMAP2420_EN_IVA_COP_MASK (1 << 10)
385#define OMAP2420_EN_IVA_MPU_SHIFT 8 120#define OMAP2420_EN_IVA_MPU_SHIFT 8
386#define OMAP2420_EN_IVA_MPU_MASK (1 << 8)
387#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0 121#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
388#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_MASK (1 << 0)
389
390/* CM_ICLKEN_DSP */
391#define OMAP2420_EN_DSP_IPI_SHIFT 1 122#define OMAP2420_EN_DSP_IPI_SHIFT 1
392#define OMAP2420_EN_DSP_IPI_MASK (1 << 1)
393
394/* CM_IDLEST_DSP */
395#define OMAP2420_ST_IVA_MASK (1 << 8)
396#define OMAP2420_ST_IPI_MASK (1 << 1)
397#define OMAP24XX_ST_DSP_MASK (1 << 0)
398
399/* CM_AUTOIDLE_DSP */
400#define OMAP2420_AUTO_DSP_IPI_MASK (1 << 1)
401
402/* CM_CLKSEL_DSP */
403#define OMAP2420_SYNC_IVA_MASK (1 << 13)
404#define OMAP2420_CLKSEL_IVA_SHIFT 8
405#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8) 123#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
406#define OMAP24XX_SYNC_DSP_MASK (1 << 7)
407#define OMAP24XX_CLKSEL_DSP_IF_SHIFT 5
408#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5) 124#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
409#define OMAP24XX_CLKSEL_DSP_SHIFT 0
410#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0) 125#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
411
412/* CM_CLKSTCTRL_DSP */
413#define OMAP2420_AUTOSTATE_IVA_SHIFT 8
414#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8) 126#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
415#define OMAP24XX_AUTOSTATE_DSP_SHIFT 0
416#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0) 127#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
417
418/* CM_FCLKEN_MDM */
419/* 2430 only */
420#define OMAP2430_EN_OSC_SHIFT 1 128#define OMAP2430_EN_OSC_SHIFT 1
421#define OMAP2430_EN_OSC_MASK (1 << 1)
422
423/* CM_ICLKEN_MDM */
424/* 2430 only */
425#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0 129#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
426#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_MASK (1 << 0)
427
428/* CM_IDLEST_MDM specific bits */
429/* 2430 only */
430
431/* CM_AUTOIDLE_MDM */
432/* 2430 only */
433#define OMAP2430_AUTO_OSC_MASK (1 << 1)
434#define OMAP2430_AUTO_MDM_MASK (1 << 0)
435
436/* CM_CLKSEL_MDM */
437/* 2430 only */
438#define OMAP2430_SYNC_MDM_MASK (1 << 4)
439#define OMAP2430_CLKSEL_MDM_SHIFT 0
440#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0) 130#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
441
442/* CM_CLKSTCTRL_MDM */
443/* 2430 only */
444#define OMAP2430_AUTOSTATE_MDM_SHIFT 0
445#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0) 131#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
446
447/* OMAP24XX CM_CLKSTCTRL_*.AUTOSTATE_* register bit values */
448#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0 132#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
449#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1 133#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
450
451
452#endif 134#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index adf7bb79b18f..c0823fd6d5e0 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -20,798 +20,49 @@
20#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 20#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
21#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H 21#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
22 22
23/*
24 * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
25 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
26 */
27#define AM33XX_AUTO_DPLL_MODE_SHIFT 0
28#define AM33XX_AUTO_DPLL_MODE_WIDTH 3
29#define AM33XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
30
31/* Used by CM_WKUP_CLKSTCTRL */
32#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT 14
33#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH 1
34#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK (1 << 16)
35
36/* Used by CM_PER_L4LS_CLKSTCTRL */
37#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT 11
38#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH 1
39#define AM33XX_CLKACTIVITY_CAN_CLK_MASK (1 << 11)
40
41/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
42#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT 4
43#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH 1
44#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK (1 << 4)
45
46/* Used by CM_PER_CPSW_CLKSTCTRL */
47#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT 4
48#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH 1
49#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK (1 << 4)
50
51/* Used by CM_PER_L4HS_CLKSTCTRL */
52#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT 4
53#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH 1
54#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK (1 << 4)
55
56/* Used by CM_PER_L4HS_CLKSTCTRL */
57#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT 5
58#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH 1
59#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK (1 << 5)
60
61/* Used by CM_PER_L4HS_CLKSTCTRL */
62#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT 6
63#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH 1
64#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK (1 << 6)
65
66/* Used by CM_PER_L3_CLKSTCTRL */
67#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT 6
68#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH 1
69#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK (1 << 6)
70
71/* Used by CM_CEFUSE_CLKSTCTRL */
72#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
73#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 1
74#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
75
76/* Used by CM_L3_AON_CLKSTCTRL */
77#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT 2
78#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH 1
79#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK (1 << 2)
80
81/* Used by CM_L3_AON_CLKSTCTRL */
82#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT 4
83#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH 1
84#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK (1 << 4)
85
86/* Used by CM_PER_L3_CLKSTCTRL */
87#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT 2
88#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH 1
89#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK (1 << 2)
90
91/* Used by CM_GFX_L3_CLKSTCTRL */
92#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT 9
93#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH 1
94#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK (1 << 9)
95
96/* Used by CM_GFX_L3_CLKSTCTRL */
97#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT 8
98#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH 1
99#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK (1 << 8)
100
101/* Used by CM_WKUP_CLKSTCTRL */
102#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT 8
103#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH 1
104#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK (1 << 8)
105
106/* Used by CM_PER_L4LS_CLKSTCTRL */
107#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT 19
108#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH 1
109#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK (1 << 19)
110
111/* Used by CM_PER_L4LS_CLKSTCTRL */
112#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT 20
113#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH 1
114#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK (1 << 20)
115
116/* Used by CM_PER_L4LS_CLKSTCTRL */
117#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT 21
118#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH 1
119#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK (1 << 21)
120
121/* Used by CM_PER_L4LS_CLKSTCTRL */
122#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT 22
123#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH 1
124#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK (1 << 22)
125
126/* Used by CM_PER_L4LS_CLKSTCTRL */
127#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT 26
128#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH 1
129#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK (1 << 26)
130
131/* Used by CM_PER_L4LS_CLKSTCTRL */
132#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT 18
133#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH 1
134#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK (1 << 18)
135
136/* Used by CM_WKUP_CLKSTCTRL */
137#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT 11
138#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH 1
139#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK (1 << 11)
140
141/* Used by CM_PER_L4LS_CLKSTCTRL */
142#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT 24
143#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH 1
144#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK (1 << 24)
145
146/* Used by CM_PER_PRUSS_CLKSTCTRL */
147#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT 5
148#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH 1
149#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK (1 << 5)
150
151/* Used by CM_PER_PRUSS_CLKSTCTRL */
152#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT 4
153#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH 1
154#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK (1 << 4)
155
156/* Used by CM_PER_PRUSS_CLKSTCTRL */
157#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT 6
158#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH 1
159#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK (1 << 6)
160
161/* Used by CM_PER_L3S_CLKSTCTRL */
162#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT 3
163#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH 1
164#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK (1 << 3)
165
166/* Used by CM_L3_AON_CLKSTCTRL */
167#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT 3
168#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH 1
169#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK (1 << 3)
170
171/* Used by CM_PER_L3_CLKSTCTRL */
172#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT 4
173#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH 1
174#define AM33XX_CLKACTIVITY_L3_GCLK_MASK (1 << 4)
175
176/* Used by CM_PER_L4FW_CLKSTCTRL */
177#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT 8
178#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH 1
179#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK (1 << 8)
180
181/* Used by CM_PER_L4HS_CLKSTCTRL */
182#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT 3
183#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH 1
184#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK (1 << 3)
185
186/* Used by CM_PER_L4LS_CLKSTCTRL */
187#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT 8
188#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH 1
189#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK (1 << 8)
190
191/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
192#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT 8
193#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH 1
194#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK (1 << 8)
195
196/* Used by CM_CEFUSE_CLKSTCTRL */
197#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
198#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 1
199#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
200
201/* Used by CM_RTC_CLKSTCTRL */
202#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT 8
203#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH 1
204#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK (1 << 8)
205
206/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
207#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT 2
208#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH 1
209#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK (1 << 2)
210
211/* Used by CM_WKUP_CLKSTCTRL */
212#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT 2
213#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH 1
214#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK (1 << 2)
215
216/* Used by CM_PER_L4LS_CLKSTCTRL */
217#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT 17
218#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH 1
219#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK (1 << 17)
220
221/* Used by CM_PER_LCDC_CLKSTCTRL */
222#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT 4
223#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH 1
224#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK (1 << 4)
225
226/* Used by CM_PER_LCDC_CLKSTCTRL */
227#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT 5
228#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH 1
229#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK (1 << 5)
230
231/* Used by CM_PER_L3_CLKSTCTRL */
232#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT 7
233#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH 1
234#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK (1 << 7)
235
236/* Used by CM_PER_L3_CLKSTCTRL */
237#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT 3
238#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH 1
239#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK (1 << 3)
240
241/* Used by CM_MPU_CLKSTCTRL */
242#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT 2
243#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH 1
244#define AM33XX_CLKACTIVITY_MPU_CLK_MASK (1 << 2)
245
246/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
247#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT 4
248#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH 1
249#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK (1 << 4)
250
251/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
252#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT 5
253#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH 1
254#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK (1 << 5)
255
256/* Used by CM_RTC_CLKSTCTRL */
257#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT 9
258#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH 1
259#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK (1 << 9)
260
261/* Used by CM_PER_L4LS_CLKSTCTRL */
262#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT 25
263#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH 1
264#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK (1 << 25)
265
266/* Used by CM_WKUP_CLKSTCTRL */
267#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT 3
268#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH 1
269#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK (1 << 3)
270
271/* Used by CM_WKUP_CLKSTCTRL */
272#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT 10
273#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH 1
274#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK (1 << 10)
275
276/* Used by CM_WKUP_CLKSTCTRL */
277#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT 13
278#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH 1
279#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK (1 << 13)
280
281/* Used by CM_PER_L4LS_CLKSTCTRL */
282#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT 14
283#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH 1
284#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK (1 << 14)
285
286/* Used by CM_PER_L4LS_CLKSTCTRL */
287#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT 15
288#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH 1
289#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK (1 << 15)
290
291/* Used by CM_PER_L4LS_CLKSTCTRL */
292#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT 16
293#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH 1
294#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK (1 << 16)
295
296/* Used by CM_PER_L4LS_CLKSTCTRL */
297#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT 27
298#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH 1
299#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK (1 << 27)
300
301/* Used by CM_PER_L4LS_CLKSTCTRL */
302#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT 28
303#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH 1
304#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK (1 << 28)
305
306/* Used by CM_PER_L4LS_CLKSTCTRL */
307#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT 13
308#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH 1
309#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK (1 << 13)
310
311/* Used by CM_WKUP_CLKSTCTRL */
312#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT 12
313#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH 1
314#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK (1 << 12)
315
316/* Used by CM_PER_L4LS_CLKSTCTRL */
317#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT 10
318#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH 1
319#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK (1 << 10)
320
321/* Used by CM_WKUP_CLKSTCTRL */
322#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT 9
323#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH 1
324#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK (1 << 9)
325
326/* Used by CM_WKUP_CLKSTCTRL */
327#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT 4
328#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH 1
329#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK (1 << 4)
330
331/* Used by CLKSEL_GFX_FCLK */
332#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT 0
333#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH 1
334#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK (1 << 0)
335
336/* Used by CM_CLKOUT_CTRL */
337#define AM33XX_CLKOUT2DIV_SHIFT 3 23#define AM33XX_CLKOUT2DIV_SHIFT 3
338#define AM33XX_CLKOUT2DIV_WIDTH 3 24#define AM33XX_CLKOUT2DIV_WIDTH 3
339#define AM33XX_CLKOUT2DIV_MASK (0x7 << 3)
340
341/* Used by CM_CLKOUT_CTRL */
342#define AM33XX_CLKOUT2EN_SHIFT 7 25#define AM33XX_CLKOUT2EN_SHIFT 7
343#define AM33XX_CLKOUT2EN_WIDTH 1
344#define AM33XX_CLKOUT2EN_MASK (1 << 7)
345
346/* Used by CM_CLKOUT_CTRL */
347#define AM33XX_CLKOUT2SOURCE_SHIFT 0
348#define AM33XX_CLKOUT2SOURCE_WIDTH 3
349#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0) 26#define AM33XX_CLKOUT2SOURCE_MASK (0x7 << 0)
350
351/*
352 * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
353 * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
354 * CLKSEL_TIMER7_CLK
355 */
356#define AM33XX_CLKSEL_SHIFT 0
357#define AM33XX_CLKSEL_WIDTH 1
358#define AM33XX_CLKSEL_MASK (0x01 << 0)
359
360/*
361 * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
362 * CM_CPTS_RFT_CLKSEL
363 */
364#define AM33XX_CLKSEL_0_0_SHIFT 0 27#define AM33XX_CLKSEL_0_0_SHIFT 0
365#define AM33XX_CLKSEL_0_0_WIDTH 1 28#define AM33XX_CLKSEL_0_0_WIDTH 1
366#define AM33XX_CLKSEL_0_0_MASK (1 << 0) 29#define AM33XX_CLKSEL_0_0_MASK (1 << 0)
367
368#define AM33XX_CLKSEL_0_1_SHIFT 0
369#define AM33XX_CLKSEL_0_1_WIDTH 2
370#define AM33XX_CLKSEL_0_1_MASK (3 << 0) 30#define AM33XX_CLKSEL_0_1_MASK (3 << 0)
371
372/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
373#define AM33XX_CLKSEL_0_2_SHIFT 0
374#define AM33XX_CLKSEL_0_2_WIDTH 3
375#define AM33XX_CLKSEL_0_2_MASK (7 << 0) 31#define AM33XX_CLKSEL_0_2_MASK (7 << 0)
376
377/* Used by CLKSEL_GFX_FCLK */
378#define AM33XX_CLKSEL_GFX_FCLK_SHIFT 1
379#define AM33XX_CLKSEL_GFX_FCLK_WIDTH 1
380#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1) 32#define AM33XX_CLKSEL_GFX_FCLK_MASK (1 << 1)
381
382/*
383 * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
384 * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
385 * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
386 * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
387 * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
388 * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
389 */
390#define AM33XX_CLKTRCTRL_SHIFT 0 33#define AM33XX_CLKTRCTRL_SHIFT 0
391#define AM33XX_CLKTRCTRL_WIDTH 2
392#define AM33XX_CLKTRCTRL_MASK (0x3 << 0) 34#define AM33XX_CLKTRCTRL_MASK (0x3 << 0)
393
394/*
395 * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
396 * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
397 * CM_SSC_DELTAMSTEP_DPLL_PER
398 */
399#define AM33XX_DELTAMSTEP_SHIFT 0
400#define AM33XX_DELTAMSTEP_WIDTH 20
401#define AM33XX_DELTAMSTEP_MASK (0xfffff << 0)
402
403/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
404#define AM33XX_DPLL_BYP_CLKSEL_SHIFT 23
405#define AM33XX_DPLL_BYP_CLKSEL_WIDTH 1
406#define AM33XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
407
408/* Used by CM_CLKDCOLDO_DPLL_PER */
409#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
410#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 1
411#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
412
413/* Used by CM_CLKDCOLDO_DPLL_PER */
414#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT 12
415#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH 1
416#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK (1 << 12)
417
418/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
419#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0 35#define AM33XX_DPLL_CLKOUT_DIV_SHIFT 0
420#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5 36#define AM33XX_DPLL_CLKOUT_DIV_WIDTH 5
421#define AM33XX_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
422
423/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
424#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT 0
425#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH 7
426#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
427
428/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
429#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT 5
430#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH 1
431#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
432
433/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
434#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT 7
435#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH 1
436#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK (1 << 7)
437
438/*
439 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
440 * CM_DIV_M2_DPLL_PER
441 */
442#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
443#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH 1
444#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
445
446/*
447 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
448 * CM_CLKSEL_DPLL_MPU
449 */
450#define AM33XX_DPLL_DIV_SHIFT 0
451#define AM33XX_DPLL_DIV_WIDTH 7
452#define AM33XX_DPLL_DIV_MASK (0x7f << 0) 37#define AM33XX_DPLL_DIV_MASK (0x7f << 0)
453
454#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0) 38#define AM33XX_DPLL_PER_DIV_MASK (0xff << 0)
455
456/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
457#define AM33XX_DPLL_DIV_0_7_SHIFT 0
458#define AM33XX_DPLL_DIV_0_7_WIDTH 8
459#define AM33XX_DPLL_DIV_0_7_MASK (0xff << 0)
460
461/*
462 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
463 * CM_CLKMODE_DPLL_MPU
464 */
465#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT 8
466#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH 1
467#define AM33XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
468
469/*
470 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
471 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
472 */
473#define AM33XX_DPLL_EN_SHIFT 0
474#define AM33XX_DPLL_EN_WIDTH 3
475#define AM33XX_DPLL_EN_MASK (0x7 << 0) 39#define AM33XX_DPLL_EN_MASK (0x7 << 0)
476
477/*
478 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
479 * CM_CLKMODE_DPLL_MPU
480 */
481#define AM33XX_DPLL_LPMODE_EN_SHIFT 10
482#define AM33XX_DPLL_LPMODE_EN_WIDTH 1
483#define AM33XX_DPLL_LPMODE_EN_MASK (1 << 10)
484
485/*
486 * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
487 * CM_CLKSEL_DPLL_MPU
488 */
489#define AM33XX_DPLL_MULT_SHIFT 8
490#define AM33XX_DPLL_MULT_WIDTH 11
491#define AM33XX_DPLL_MULT_MASK (0x7ff << 8) 40#define AM33XX_DPLL_MULT_MASK (0x7ff << 8)
492
493/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
494#define AM33XX_DPLL_MULT_PERIPH_SHIFT 8
495#define AM33XX_DPLL_MULT_PERIPH_WIDTH 12
496#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8) 41#define AM33XX_DPLL_MULT_PERIPH_MASK (0xfff << 8)
497
498/*
499 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
500 * CM_CLKMODE_DPLL_MPU
501 */
502#define AM33XX_DPLL_REGM4XEN_SHIFT 11
503#define AM33XX_DPLL_REGM4XEN_WIDTH 1
504#define AM33XX_DPLL_REGM4XEN_MASK (1 << 11)
505
506/* Used by CM_CLKSEL_DPLL_PERIPH */
507#define AM33XX_DPLL_SD_DIV_SHIFT 24
508#define AM33XX_DPLL_SD_DIV_WIDTH 8
509#define AM33XX_DPLL_SD_DIV_MASK (0xff << 24)
510
511/*
512 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
513 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
514 */
515#define AM33XX_DPLL_SSC_ACK_SHIFT 13
516#define AM33XX_DPLL_SSC_ACK_WIDTH 1
517#define AM33XX_DPLL_SSC_ACK_MASK (1 << 13)
518
519/*
520 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
521 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
522 */
523#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
524#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH 1
525#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
526
527/*
528 * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
529 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
530 */
531#define AM33XX_DPLL_SSC_EN_SHIFT 12
532#define AM33XX_DPLL_SSC_EN_WIDTH 1
533#define AM33XX_DPLL_SSC_EN_MASK (1 << 12)
534
535/* Used by CM_DIV_M4_DPLL_CORE */
536#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0 42#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
537#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5 43#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH 5
538#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
539
540/* Used by CM_DIV_M4_DPLL_CORE */
541#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
542#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 1
543#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
544
545/* Used by CM_DIV_M4_DPLL_CORE */
546#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
547#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 1
548#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
549
550/* Used by CM_DIV_M4_DPLL_CORE */
551#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
552#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH 1
553#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
554
555/* Used by CM_DIV_M5_DPLL_CORE */
556#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0 44#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
557#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5 45#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH 5
558#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
559
560/* Used by CM_DIV_M5_DPLL_CORE */
561#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
562#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 1
563#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
564
565/* Used by CM_DIV_M5_DPLL_CORE */
566#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
567#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 1
568#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
569
570/* Used by CM_DIV_M5_DPLL_CORE */
571#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
572#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH 1
573#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
574
575/* Used by CM_DIV_M6_DPLL_CORE */
576#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0 46#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
577#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5 47#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH 5
578#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
579
580/* Used by CM_DIV_M6_DPLL_CORE */
581#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
582#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 1
583#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
584
585/* Used by CM_DIV_M6_DPLL_CORE */
586#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
587#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 1
588#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
589
590/* Used by CM_DIV_M6_DPLL_CORE */
591#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
592#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH 1
593#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
594
595/*
596 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
597 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
598 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
599 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
600 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
601 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
602 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
603 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
604 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
605 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
606 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
607 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
608 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
609 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
610 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
611 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
612 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
613 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
614 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
615 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
616 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
617 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
618 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
619 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
620 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
621 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
622 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
623 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
624 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
625 * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
626 * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
627 */
628#define AM33XX_IDLEST_SHIFT 16 48#define AM33XX_IDLEST_SHIFT 16
629#define AM33XX_IDLEST_WIDTH 2
630#define AM33XX_IDLEST_MASK (0x3 << 16) 49#define AM33XX_IDLEST_MASK (0x3 << 16)
631
632/* Used by CM_MAC_CLKSEL */
633#define AM33XX_MII_CLK_SEL_SHIFT 2
634#define AM33XX_MII_CLK_SEL_WIDTH 1
635#define AM33XX_MII_CLK_SEL_MASK (1 << 2)
636
637/*
638 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
639 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
640 * CM_SSC_MODFREQDIV_DPLL_PER
641 */
642#define AM33XX_MODFREQDIV_EXPONENT_SHIFT 8
643#define AM33XX_MODFREQDIV_EXPONENT_WIDTH 3
644#define AM33XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
645
646/*
647 * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
648 * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
649 * CM_SSC_MODFREQDIV_DPLL_PER
650 */
651#define AM33XX_MODFREQDIV_MANTISSA_SHIFT 0
652#define AM33XX_MODFREQDIV_MANTISSA_WIDTH 7
653#define AM33XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
654
655/*
656 * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
657 * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
658 * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
659 * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
660 * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
661 * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
662 * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
663 * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
664 * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
665 * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
666 * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
667 * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
668 * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
669 * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
670 * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
671 * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
672 * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
673 * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
674 * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
675 * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
676 * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
677 * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
678 * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
679 * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
680 * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
681 * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
682 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
683 * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
684 * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
685 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
686 * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
687 * CM_CEFUSE_CEFUSE_CLKCTRL
688 */
689#define AM33XX_MODULEMODE_SHIFT 0 50#define AM33XX_MODULEMODE_SHIFT 0
690#define AM33XX_MODULEMODE_WIDTH 2
691#define AM33XX_MODULEMODE_MASK (0x3 << 0) 51#define AM33XX_MODULEMODE_MASK (0x3 << 0)
692
693/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
694#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30 52#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT 30
695#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH 1
696#define AM33XX_OPTCLK_DEBUG_CLKA_MASK (1 << 30)
697
698/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
699#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19 53#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT 19
700#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH 1
701#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK (1 << 19)
702
703/* Used by CM_WKUP_GPIO0_CLKCTRL */
704#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18 54#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT 18
705#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH 1
706#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK (1 << 18)
707
708/* Used by CM_PER_GPIO1_CLKCTRL */
709#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18 55#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT 18
710#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH 1
711#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK (1 << 18)
712
713/* Used by CM_PER_GPIO2_CLKCTRL */
714#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18 56#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT 18
715#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH 1
716#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK (1 << 18)
717
718/* Used by CM_PER_GPIO3_CLKCTRL */
719#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18 57#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT 18
720#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH 1
721#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK (1 << 18)
722
723/* Used by CM_PER_GPIO4_CLKCTRL */
724#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT 18
725#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH 1
726#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK (1 << 18)
727
728/* Used by CM_PER_GPIO5_CLKCTRL */
729#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT 18
730#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH 1
731#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK (1 << 18)
732
733/* Used by CM_PER_GPIO6_CLKCTRL */
734#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT 18
735#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH 1
736#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK (1 << 18)
737
738/*
739 * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
740 * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
741 * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
742 * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
743 * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
744 * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
745 */
746#define AM33XX_STBYST_SHIFT 18
747#define AM33XX_STBYST_WIDTH 1
748#define AM33XX_STBYST_MASK (1 << 18)
749
750/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
751#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27 58#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT 27
752#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3 59#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH 3
753#define AM33XX_STM_PMD_CLKDIVSEL_MASK (0x7 << 27)
754
755/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
756#define AM33XX_STM_PMD_CLKSEL_SHIFT 22 60#define AM33XX_STM_PMD_CLKSEL_SHIFT 22
757#define AM33XX_STM_PMD_CLKSEL_WIDTH 2 61#define AM33XX_STM_PMD_CLKSEL_WIDTH 2
758#define AM33XX_STM_PMD_CLKSEL_MASK (0x3 << 22)
759
760/*
761 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
762 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
763 */
764#define AM33XX_ST_DPLL_CLK_SHIFT 0
765#define AM33XX_ST_DPLL_CLK_WIDTH 1
766#define AM33XX_ST_DPLL_CLK_MASK (1 << 0) 62#define AM33XX_ST_DPLL_CLK_MASK (1 << 0)
767
768/* Used by CM_CLKDCOLDO_DPLL_PER */
769#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8 63#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT 8
770#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH 1
771#define AM33XX_ST_DPLL_CLKDCOLDO_MASK (1 << 8)
772
773/*
774 * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
775 * CM_DIV_M2_DPLL_PER
776 */
777#define AM33XX_ST_DPLL_CLKOUT_SHIFT 9
778#define AM33XX_ST_DPLL_CLKOUT_WIDTH 1
779#define AM33XX_ST_DPLL_CLKOUT_MASK (1 << 9)
780
781/* Used by CM_DIV_M4_DPLL_CORE */
782#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT 9
783#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH 1
784#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
785
786/* Used by CM_DIV_M5_DPLL_CORE */
787#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT 9
788#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH 1
789#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
790
791/* Used by CM_DIV_M6_DPLL_CORE */
792#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT 9
793#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH 1
794#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
795
796/*
797 * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
798 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
799 */
800#define AM33XX_ST_MN_BYPASS_SHIFT 8
801#define AM33XX_ST_MN_BYPASS_WIDTH 1
802#define AM33XX_ST_MN_BYPASS_MASK (1 << 8)
803
804/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
805#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24 64#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT 24
806#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3 65#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH 3
807#define AM33XX_TRC_PMD_CLKDIVSEL_MASK (0x7 << 24)
808
809/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
810#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20 66#define AM33XX_TRC_PMD_CLKSEL_SHIFT 20
811#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2 67#define AM33XX_TRC_PMD_CLKSEL_WIDTH 2
812#define AM33XX_TRC_PMD_CLKSEL_MASK (0x3 << 20)
813
814/* Used by CONTROL_SEC_CLK_CTRL */
815#define AM33XX_TIMER0_CLKSEL_WIDTH 2
816#define AM33XX_TIMER0_CLKSEL_MASK (0x3 << 4)
817#endif 68#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index adf78d325804..04dab2fcf862 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,833 +14,201 @@
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 */ 15 */
16 16
17/* Bits shared between registers */
18
19/* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */
20#define OMAP3430ES2_EN_MMC3_MASK (1 << 30)
21#define OMAP3430ES2_EN_MMC3_SHIFT 30 17#define OMAP3430ES2_EN_MMC3_SHIFT 30
22#define OMAP3430_EN_MSPRO_MASK (1 << 23)
23#define OMAP3430_EN_MSPRO_SHIFT 23 18#define OMAP3430_EN_MSPRO_SHIFT 23
24#define OMAP3430_EN_HDQ_MASK (1 << 22)
25#define OMAP3430_EN_HDQ_SHIFT 22 19#define OMAP3430_EN_HDQ_SHIFT 22
26#define OMAP3430ES1_EN_FSHOSTUSB_MASK (1 << 5)
27#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5 20#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
28#define OMAP3430ES1_EN_D2D_MASK (1 << 3)
29#define OMAP3430ES1_EN_D2D_SHIFT 3 21#define OMAP3430ES1_EN_D2D_SHIFT 3
30#define OMAP3430_EN_SSI_MASK (1 << 0)
31#define OMAP3430_EN_SSI_SHIFT 0 22#define OMAP3430_EN_SSI_SHIFT 0
32
33/* CM_FCLKEN3_CORE and CM_ICLKEN3_CORE shared bits */
34#define OMAP3430ES2_EN_USBTLL_SHIFT 2 23#define OMAP3430ES2_EN_USBTLL_SHIFT 2
35#define OMAP3430ES2_EN_USBTLL_MASK (1 << 2)
36
37/* CM_FCLKEN_WKUP and CM_ICLKEN_WKUP shared bits */
38#define OMAP3430_EN_WDT2_MASK (1 << 5)
39#define OMAP3430_EN_WDT2_SHIFT 5 24#define OMAP3430_EN_WDT2_SHIFT 5
40
41/* CM_ICLKEN_CAM, CM_FCLKEN_CAM shared bits */
42#define OMAP3430_EN_CAM_MASK (1 << 0)
43#define OMAP3430_EN_CAM_SHIFT 0 25#define OMAP3430_EN_CAM_SHIFT 0
44
45/* CM_FCLKEN_PER, CM_ICLKEN_PER shared bits */
46#define OMAP3430_EN_WDT3_MASK (1 << 12)
47#define OMAP3430_EN_WDT3_SHIFT 12 26#define OMAP3430_EN_WDT3_SHIFT 12
48
49/* CM_CLKSEL2_EMU, CM_CLKSEL3_EMU shared bits */
50#define OMAP3430_OVERRIDE_ENABLE_MASK (1 << 19)
51
52
53/* Bits specific to each register */
54
55/* CM_FCLKEN_IVA2 */
56#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0) 27#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
57#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0 28#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
58
59/* CM_CLKEN_PLL_IVA2 */
60#define OMAP3430_IVA2_DPLL_RAMPTIME_SHIFT 8
61#define OMAP3430_IVA2_DPLL_RAMPTIME_MASK (0x3 << 8)
62#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
63#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4) 29#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
64#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3 30#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
65#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_MASK (1 << 3)
66#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
67#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0) 31#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
68
69/* CM_IDLEST_IVA2 */
70#define OMAP3430_ST_IVA2_SHIFT 0 32#define OMAP3430_ST_IVA2_SHIFT 0
71#define OMAP3430_ST_IVA2_MASK (1 << 0)
72
73/* CM_IDLEST_PLL_IVA2 */
74#define OMAP3430_ST_IVA2_CLK_SHIFT 0
75#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0) 33#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
76
77/* CM_AUTOIDLE_PLL_IVA2 */
78#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
79#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0) 34#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
80
81/* CM_CLKSEL1_PLL_IVA2 */
82#define OMAP3430_IVA2_CLK_SRC_SHIFT 19 35#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
83#define OMAP3430_IVA2_CLK_SRC_MASK (0x7 << 19)
84#define OMAP3430_IVA2_CLK_SRC_WIDTH 3 36#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
85#define OMAP3430_IVA2_DPLL_MULT_SHIFT 8
86#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8) 37#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
87#define OMAP3430_IVA2_DPLL_DIV_SHIFT 0
88#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0) 38#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
89
90/* CM_CLKSEL2_PLL_IVA2 */
91#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0 39#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
92#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
93#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5 40#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
94
95/* CM_CLKSTCTRL_IVA2 */
96#define OMAP3430_CLKTRCTRL_IVA2_SHIFT 0
97#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0) 41#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
98
99/* CM_CLKSTST_IVA2 */
100#define OMAP3430_CLKACTIVITY_IVA2_SHIFT 0
101#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0) 42#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
102
103/* CM_REVISION specific bits */
104
105/* CM_SYSCONFIG specific bits */
106
107/* CM_CLKEN_PLL_MPU */
108#define OMAP3430_MPU_DPLL_RAMPTIME_SHIFT 8
109#define OMAP3430_MPU_DPLL_RAMPTIME_MASK (0x3 << 8)
110#define OMAP3430_MPU_DPLL_FREQSEL_SHIFT 4
111#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4) 43#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
112#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3 44#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
113#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_MASK (1 << 3)
114#define OMAP3430_EN_MPU_DPLL_SHIFT 0
115#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0) 45#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
116
117/* CM_IDLEST_MPU */
118#define OMAP3430_ST_MPU_MASK (1 << 0)
119
120/* CM_IDLEST_PLL_MPU */
121#define OMAP3430_ST_MPU_CLK_SHIFT 0 46#define OMAP3430_ST_MPU_CLK_SHIFT 0
122#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 47#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
123#define OMAP3430_ST_MPU_CLK_WIDTH 1 48#define OMAP3430_ST_MPU_CLK_WIDTH 1
124
125/* CM_AUTOIDLE_PLL_MPU */
126#define OMAP3430_AUTO_MPU_DPLL_SHIFT 0
127#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0) 49#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
128
129/* CM_CLKSEL1_PLL_MPU */
130#define OMAP3430_MPU_CLK_SRC_SHIFT 19 50#define OMAP3430_MPU_CLK_SRC_SHIFT 19
131#define OMAP3430_MPU_CLK_SRC_MASK (0x7 << 19)
132#define OMAP3430_MPU_CLK_SRC_WIDTH 3 51#define OMAP3430_MPU_CLK_SRC_WIDTH 3
133#define OMAP3430_MPU_DPLL_MULT_SHIFT 8
134#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8) 52#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
135#define OMAP3430_MPU_DPLL_DIV_SHIFT 0
136#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0) 53#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
137
138/* CM_CLKSEL2_PLL_MPU */
139#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0 54#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
140#define OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
141#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5 55#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
142
143/* CM_CLKSTCTRL_MPU */
144#define OMAP3430_CLKTRCTRL_MPU_SHIFT 0
145#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0) 56#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
146
147/* CM_CLKSTST_MPU */
148#define OMAP3430_CLKACTIVITY_MPU_SHIFT 0
149#define OMAP3430_CLKACTIVITY_MPU_MASK (1 << 0)
150
151/* CM_FCLKEN1_CORE specific bits */
152#define OMAP3430_EN_MODEM_MASK (1 << 31)
153#define OMAP3430_EN_MODEM_SHIFT 31 57#define OMAP3430_EN_MODEM_SHIFT 31
154
155/* CM_ICLKEN1_CORE specific bits */
156#define OMAP3430_EN_ICR_MASK (1 << 29)
157#define OMAP3430_EN_ICR_SHIFT 29 58#define OMAP3430_EN_ICR_SHIFT 29
158#define OMAP3430_EN_AES2_MASK (1 << 28)
159#define OMAP3430_EN_AES2_SHIFT 28 59#define OMAP3430_EN_AES2_SHIFT 28
160#define OMAP3430_EN_SHA12_MASK (1 << 27)
161#define OMAP3430_EN_SHA12_SHIFT 27 60#define OMAP3430_EN_SHA12_SHIFT 27
162#define OMAP3430_EN_DES2_MASK (1 << 26)
163#define OMAP3430_EN_DES2_SHIFT 26 61#define OMAP3430_EN_DES2_SHIFT 26
164#define OMAP3430ES1_EN_FAC_MASK (1 << 8)
165#define OMAP3430ES1_EN_FAC_SHIFT 8 62#define OMAP3430ES1_EN_FAC_SHIFT 8
166#define OMAP3430_EN_MAILBOXES_MASK (1 << 7)
167#define OMAP3430_EN_MAILBOXES_SHIFT 7 63#define OMAP3430_EN_MAILBOXES_SHIFT 7
168#define OMAP3430_EN_OMAPCTRL_MASK (1 << 6)
169#define OMAP3430_EN_OMAPCTRL_SHIFT 6 64#define OMAP3430_EN_OMAPCTRL_SHIFT 6
170#define OMAP3430_EN_SAD2D_MASK (1 << 3)
171#define OMAP3430_EN_SAD2D_SHIFT 3 65#define OMAP3430_EN_SAD2D_SHIFT 3
172#define OMAP3430_EN_SDRC_MASK (1 << 1)
173#define OMAP3430_EN_SDRC_SHIFT 1 66#define OMAP3430_EN_SDRC_SHIFT 1
174
175/* AM35XX specific CM_ICLKEN1_CORE bits */
176#define AM35XX_EN_IPSS_MASK (1 << 4)
177#define AM35XX_EN_IPSS_SHIFT 4 67#define AM35XX_EN_IPSS_SHIFT 4
178
179/* CM_ICLKEN2_CORE */
180#define OMAP3430_EN_PKA_MASK (1 << 4)
181#define OMAP3430_EN_PKA_SHIFT 4 68#define OMAP3430_EN_PKA_SHIFT 4
182#define OMAP3430_EN_AES1_MASK (1 << 3)
183#define OMAP3430_EN_AES1_SHIFT 3 69#define OMAP3430_EN_AES1_SHIFT 3
184#define OMAP3430_EN_RNG_MASK (1 << 2)
185#define OMAP3430_EN_RNG_SHIFT 2 70#define OMAP3430_EN_RNG_SHIFT 2
186#define OMAP3430_EN_SHA11_MASK (1 << 1)
187#define OMAP3430_EN_SHA11_SHIFT 1 71#define OMAP3430_EN_SHA11_SHIFT 1
188#define OMAP3430_EN_DES1_MASK (1 << 0)
189#define OMAP3430_EN_DES1_SHIFT 0 72#define OMAP3430_EN_DES1_SHIFT 0
190
191/* CM_ICLKEN3_CORE */
192#define OMAP3430_EN_MAD2D_SHIFT 3 73#define OMAP3430_EN_MAD2D_SHIFT 3
193#define OMAP3430_EN_MAD2D_MASK (1 << 3)
194
195/* CM_FCLKEN3_CORE specific bits */
196#define OMAP3430ES2_EN_TS_SHIFT 1 74#define OMAP3430ES2_EN_TS_SHIFT 1
197#define OMAP3430ES2_EN_TS_MASK (1 << 1)
198#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0 75#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
199#define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0)
200
201/* CM_IDLEST1_CORE specific bits */
202#define OMAP3430ES2_ST_MMC3_SHIFT 30
203#define OMAP3430ES2_ST_MMC3_MASK (1 << 30)
204#define OMAP3430_ST_ICR_SHIFT 29
205#define OMAP3430_ST_ICR_MASK (1 << 29)
206#define OMAP3430_ST_AES2_SHIFT 28 76#define OMAP3430_ST_AES2_SHIFT 28
207#define OMAP3430_ST_AES2_MASK (1 << 28)
208#define OMAP3430_ST_SHA12_SHIFT 27 77#define OMAP3430_ST_SHA12_SHIFT 27
209#define OMAP3430_ST_SHA12_MASK (1 << 27)
210#define OMAP3430_ST_DES2_SHIFT 26
211#define OMAP3430_ST_DES2_MASK (1 << 26)
212#define OMAP3430_ST_MSPRO_SHIFT 23
213#define OMAP3430_ST_MSPRO_MASK (1 << 23)
214#define AM35XX_ST_UART4_SHIFT 23 78#define AM35XX_ST_UART4_SHIFT 23
215#define AM35XX_ST_UART4_MASK (1 << 23)
216#define OMAP3430_ST_HDQ_SHIFT 22 79#define OMAP3430_ST_HDQ_SHIFT 22
217#define OMAP3430_ST_HDQ_MASK (1 << 22)
218#define OMAP3430ES1_ST_FAC_SHIFT 8
219#define OMAP3430ES1_ST_FAC_MASK (1 << 8)
220#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 80#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8
221#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8)
222#define OMAP3430_ST_MAILBOXES_SHIFT 7 81#define OMAP3430_ST_MAILBOXES_SHIFT 7
223#define OMAP3430_ST_MAILBOXES_MASK (1 << 7)
224#define OMAP3430_ST_OMAPCTRL_SHIFT 6
225#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6)
226#define OMAP3430_ST_SAD2D_SHIFT 3 82#define OMAP3430_ST_SAD2D_SHIFT 3
227#define OMAP3430_ST_SAD2D_MASK (1 << 3)
228#define OMAP3430_ST_SDMA_SHIFT 2 83#define OMAP3430_ST_SDMA_SHIFT 2
229#define OMAP3430_ST_SDMA_MASK (1 << 2)
230#define OMAP3430_ST_SDRC_SHIFT 1
231#define OMAP3430_ST_SDRC_MASK (1 << 1)
232#define OMAP3430_ST_SSI_STDBY_SHIFT 0
233#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0)
234
235/* AM35xx specific CM_IDLEST1_CORE bits */
236#define AM35XX_ST_IPSS_SHIFT 5 84#define AM35XX_ST_IPSS_SHIFT 5
237#define AM35XX_ST_IPSS_MASK (1 << 5)
238
239/* CM_IDLEST2_CORE */
240#define OMAP3430_ST_PKA_SHIFT 4
241#define OMAP3430_ST_PKA_MASK (1 << 4)
242#define OMAP3430_ST_AES1_SHIFT 3
243#define OMAP3430_ST_AES1_MASK (1 << 3)
244#define OMAP3430_ST_RNG_SHIFT 2
245#define OMAP3430_ST_RNG_MASK (1 << 2)
246#define OMAP3430_ST_SHA11_SHIFT 1
247#define OMAP3430_ST_SHA11_MASK (1 << 1)
248#define OMAP3430_ST_DES1_SHIFT 0
249#define OMAP3430_ST_DES1_MASK (1 << 0)
250
251/* CM_IDLEST3_CORE */
252#define OMAP3430ES2_ST_USBTLL_SHIFT 2 85#define OMAP3430ES2_ST_USBTLL_SHIFT 2
253#define OMAP3430ES2_ST_USBTLL_MASK (1 << 2)
254#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0
255#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0)
256
257/* CM_AUTOIDLE1_CORE */
258#define OMAP3430_AUTO_MODEM_MASK (1 << 31)
259#define OMAP3430_AUTO_MODEM_SHIFT 31
260#define OMAP3430ES2_AUTO_MMC3_MASK (1 << 30)
261#define OMAP3430ES2_AUTO_MMC3_SHIFT 30
262#define OMAP3430ES2_AUTO_ICR_MASK (1 << 29)
263#define OMAP3430ES2_AUTO_ICR_SHIFT 29
264#define OMAP3430_AUTO_AES2_MASK (1 << 28)
265#define OMAP3430_AUTO_AES2_SHIFT 28
266#define OMAP3430_AUTO_SHA12_MASK (1 << 27)
267#define OMAP3430_AUTO_SHA12_SHIFT 27
268#define OMAP3430_AUTO_DES2_MASK (1 << 26)
269#define OMAP3430_AUTO_DES2_SHIFT 26
270#define OMAP3430_AUTO_MMC2_MASK (1 << 25)
271#define OMAP3430_AUTO_MMC2_SHIFT 25
272#define OMAP3430_AUTO_MMC1_MASK (1 << 24)
273#define OMAP3430_AUTO_MMC1_SHIFT 24
274#define OMAP3430_AUTO_MSPRO_MASK (1 << 23)
275#define OMAP3430_AUTO_MSPRO_SHIFT 23
276#define OMAP3430_AUTO_HDQ_MASK (1 << 22)
277#define OMAP3430_AUTO_HDQ_SHIFT 22
278#define OMAP3430_AUTO_MCSPI4_MASK (1 << 21)
279#define OMAP3430_AUTO_MCSPI4_SHIFT 21
280#define OMAP3430_AUTO_MCSPI3_MASK (1 << 20)
281#define OMAP3430_AUTO_MCSPI3_SHIFT 20
282#define OMAP3430_AUTO_MCSPI2_MASK (1 << 19)
283#define OMAP3430_AUTO_MCSPI2_SHIFT 19
284#define OMAP3430_AUTO_MCSPI1_MASK (1 << 18)
285#define OMAP3430_AUTO_MCSPI1_SHIFT 18
286#define OMAP3430_AUTO_I2C3_MASK (1 << 17)
287#define OMAP3430_AUTO_I2C3_SHIFT 17
288#define OMAP3430_AUTO_I2C2_MASK (1 << 16)
289#define OMAP3430_AUTO_I2C2_SHIFT 16
290#define OMAP3430_AUTO_I2C1_MASK (1 << 15)
291#define OMAP3430_AUTO_I2C1_SHIFT 15
292#define OMAP3430_AUTO_UART2_MASK (1 << 14)
293#define OMAP3430_AUTO_UART2_SHIFT 14
294#define OMAP3430_AUTO_UART1_MASK (1 << 13)
295#define OMAP3430_AUTO_UART1_SHIFT 13
296#define OMAP3430_AUTO_GPT11_MASK (1 << 12)
297#define OMAP3430_AUTO_GPT11_SHIFT 12
298#define OMAP3430_AUTO_GPT10_MASK (1 << 11)
299#define OMAP3430_AUTO_GPT10_SHIFT 11
300#define OMAP3430_AUTO_MCBSP5_MASK (1 << 10)
301#define OMAP3430_AUTO_MCBSP5_SHIFT 10
302#define OMAP3430_AUTO_MCBSP1_MASK (1 << 9)
303#define OMAP3430_AUTO_MCBSP1_SHIFT 9
304#define OMAP3430ES1_AUTO_FAC_MASK (1 << 8)
305#define OMAP3430ES1_AUTO_FAC_SHIFT 8
306#define OMAP3430_AUTO_MAILBOXES_MASK (1 << 7)
307#define OMAP3430_AUTO_MAILBOXES_SHIFT 7
308#define OMAP3430_AUTO_OMAPCTRL_MASK (1 << 6)
309#define OMAP3430_AUTO_OMAPCTRL_SHIFT 6
310#define OMAP3430ES1_AUTO_FSHOSTUSB_MASK (1 << 5)
311#define OMAP3430ES1_AUTO_FSHOSTUSB_SHIFT 5
312#define OMAP3430_AUTO_HSOTGUSB_MASK (1 << 4)
313#define OMAP3430_AUTO_HSOTGUSB_SHIFT 4
314#define OMAP3430ES1_AUTO_D2D_MASK (1 << 3)
315#define OMAP3430ES1_AUTO_D2D_SHIFT 3
316#define OMAP3430_AUTO_SAD2D_MASK (1 << 3)
317#define OMAP3430_AUTO_SAD2D_SHIFT 3
318#define OMAP3430_AUTO_SSI_MASK (1 << 0)
319#define OMAP3430_AUTO_SSI_SHIFT 0
320
321/* CM_AUTOIDLE2_CORE */
322#define OMAP3430_AUTO_PKA_MASK (1 << 4)
323#define OMAP3430_AUTO_PKA_SHIFT 4
324#define OMAP3430_AUTO_AES1_MASK (1 << 3)
325#define OMAP3430_AUTO_AES1_SHIFT 3
326#define OMAP3430_AUTO_RNG_MASK (1 << 2)
327#define OMAP3430_AUTO_RNG_SHIFT 2
328#define OMAP3430_AUTO_SHA11_MASK (1 << 1)
329#define OMAP3430_AUTO_SHA11_SHIFT 1
330#define OMAP3430_AUTO_DES1_MASK (1 << 0)
331#define OMAP3430_AUTO_DES1_SHIFT 0
332
333/* CM_AUTOIDLE3_CORE */
334#define OMAP3430ES2_AUTO_USBHOST (1 << 0)
335#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
336#define OMAP3430ES2_AUTO_USBTLL (1 << 2)
337#define OMAP3430ES2_AUTO_USBTLL_SHIFT 2
338#define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2)
339#define OMAP3430_AUTO_MAD2D_SHIFT 3
340#define OMAP3430_AUTO_MAD2D_MASK (1 << 3)
341
342/* CM_CLKSEL_CORE */
343#define OMAP3430_CLKSEL_SSI_SHIFT 8
344#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8) 86#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
345#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7) 87#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
346#define OMAP3430_CLKSEL_GPT11_SHIFT 7
347#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6) 88#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
348#define OMAP3430_CLKSEL_GPT10_SHIFT 6
349#define OMAP3430ES1_CLKSEL_FSHOSTUSB_SHIFT 4
350#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4) 89#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
351#define OMAP3430_CLKSEL_L4_SHIFT 2 90#define OMAP3430_CLKSEL_L4_SHIFT 2
352#define OMAP3430_CLKSEL_L4_MASK (0x3 << 2)
353#define OMAP3430_CLKSEL_L4_WIDTH 2 91#define OMAP3430_CLKSEL_L4_WIDTH 2
354#define OMAP3430_CLKSEL_L3_SHIFT 0 92#define OMAP3430_CLKSEL_L3_SHIFT 0
355#define OMAP3430_CLKSEL_L3_MASK (0x3 << 0)
356#define OMAP3430_CLKSEL_L3_WIDTH 2 93#define OMAP3430_CLKSEL_L3_WIDTH 2
357#define OMAP3630_CLKSEL_96M_SHIFT 12
358#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12) 94#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
359#define OMAP3630_CLKSEL_96M_WIDTH 2
360
361/* CM_CLKSTCTRL_CORE */
362#define OMAP3430ES1_CLKTRCTRL_D2D_SHIFT 4
363#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4) 95#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
364#define OMAP3430_CLKTRCTRL_L4_SHIFT 2
365#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2) 96#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
366#define OMAP3430_CLKTRCTRL_L3_SHIFT 0
367#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0) 97#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
368
369/* CM_CLKSTST_CORE */
370#define OMAP3430ES1_CLKACTIVITY_D2D_SHIFT 2
371#define OMAP3430ES1_CLKACTIVITY_D2D_MASK (1 << 2)
372#define OMAP3430_CLKACTIVITY_L4_SHIFT 1
373#define OMAP3430_CLKACTIVITY_L4_MASK (1 << 1)
374#define OMAP3430_CLKACTIVITY_L3_SHIFT 0
375#define OMAP3430_CLKACTIVITY_L3_MASK (1 << 0)
376
377/* CM_FCLKEN_GFX */
378#define OMAP3430ES1_EN_3D_MASK (1 << 2)
379#define OMAP3430ES1_EN_3D_SHIFT 2 98#define OMAP3430ES1_EN_3D_SHIFT 2
380#define OMAP3430ES1_EN_2D_MASK (1 << 1)
381#define OMAP3430ES1_EN_2D_SHIFT 1 99#define OMAP3430ES1_EN_2D_SHIFT 1
382
383/* CM_ICLKEN_GFX specific bits */
384
385/* CM_IDLEST_GFX specific bits */
386
387/* CM_CLKSEL_GFX specific bits */
388
389/* CM_SLEEPDEP_GFX specific bits */
390
391/* CM_CLKSTCTRL_GFX */
392#define OMAP3430ES1_CLKTRCTRL_GFX_SHIFT 0
393#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0) 100#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
394
395/* CM_CLKSTST_GFX */
396#define OMAP3430ES1_CLKACTIVITY_GFX_SHIFT 0
397#define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0)
398
399/* CM_FCLKEN_SGX */
400#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 101#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
401#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1)
402
403/* CM_IDLEST_SGX */
404#define OMAP3430ES2_ST_SGX_SHIFT 1
405#define OMAP3430ES2_ST_SGX_MASK (1 << 1)
406
407/* CM_ICLKEN_SGX */
408#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 102#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
409#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0)
410
411/* CM_CLKSEL_SGX */
412#define OMAP3430ES2_CLKSEL_SGX_SHIFT 0
413#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0) 103#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
414
415/* CM_CLKSTCTRL_SGX */
416#define OMAP3430ES2_CLKTRCTRL_SGX_SHIFT 0
417#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0) 104#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
418
419/* CM_CLKSTST_SGX */
420#define OMAP3430ES2_CLKACTIVITY_SGX_SHIFT 0
421#define OMAP3430ES2_CLKACTIVITY_SGX_MASK (1 << 0)
422
423/* CM_FCLKEN_WKUP specific bits */
424#define OMAP3430ES2_EN_USIMOCP_SHIFT 9 105#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
425#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9)
426
427/* CM_ICLKEN_WKUP specific bits */
428#define OMAP3430_EN_WDT1_MASK (1 << 4)
429#define OMAP3430_EN_WDT1_SHIFT 4 106#define OMAP3430_EN_WDT1_SHIFT 4
430#define OMAP3430_EN_32KSYNC_MASK (1 << 2)
431#define OMAP3430_EN_32KSYNC_SHIFT 2 107#define OMAP3430_EN_32KSYNC_SHIFT 2
432
433/* CM_IDLEST_WKUP specific bits */
434#define OMAP3430ES2_ST_USIMOCP_SHIFT 9
435#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9)
436#define OMAP3430_ST_WDT2_SHIFT 5 108#define OMAP3430_ST_WDT2_SHIFT 5
437#define OMAP3430_ST_WDT2_MASK (1 << 5)
438#define OMAP3430_ST_WDT1_SHIFT 4
439#define OMAP3430_ST_WDT1_MASK (1 << 4)
440#define OMAP3430_ST_32KSYNC_SHIFT 2 109#define OMAP3430_ST_32KSYNC_SHIFT 2
441#define OMAP3430_ST_32KSYNC_MASK (1 << 2)
442
443/* CM_AUTOIDLE_WKUP */
444#define OMAP3430ES2_AUTO_USIMOCP_MASK (1 << 9)
445#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9
446#define OMAP3430_AUTO_WDT2_MASK (1 << 5)
447#define OMAP3430_AUTO_WDT2_SHIFT 5
448#define OMAP3430_AUTO_WDT1_MASK (1 << 4)
449#define OMAP3430_AUTO_WDT1_SHIFT 4
450#define OMAP3430_AUTO_GPIO1_MASK (1 << 3)
451#define OMAP3430_AUTO_GPIO1_SHIFT 3
452#define OMAP3430_AUTO_32KSYNC_MASK (1 << 2)
453#define OMAP3430_AUTO_32KSYNC_SHIFT 2
454#define OMAP3430_AUTO_GPT12_MASK (1 << 1)
455#define OMAP3430_AUTO_GPT12_SHIFT 1
456#define OMAP3430_AUTO_GPT1_MASK (1 << 0)
457#define OMAP3430_AUTO_GPT1_SHIFT 0
458
459/* CM_CLKSEL_WKUP */
460#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3) 110#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
461#define OMAP3430_CLKSEL_RM_SHIFT 1 111#define OMAP3430_CLKSEL_RM_SHIFT 1
462#define OMAP3430_CLKSEL_RM_MASK (0x3 << 1)
463#define OMAP3430_CLKSEL_RM_WIDTH 2 112#define OMAP3430_CLKSEL_RM_WIDTH 2
464#define OMAP3430_CLKSEL_GPT1_SHIFT 0
465#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0) 113#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
466
467/* CM_CLKEN_PLL */
468#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31 114#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
469#define OMAP3430_PWRDN_CAM_SHIFT 30 115#define OMAP3430_PWRDN_CAM_SHIFT 30
470#define OMAP3430_PWRDN_DSS1_SHIFT 29 116#define OMAP3430_PWRDN_DSS1_SHIFT 29
471#define OMAP3430_PWRDN_TV_SHIFT 28 117#define OMAP3430_PWRDN_TV_SHIFT 28
472#define OMAP3430_PWRDN_96M_SHIFT 27 118#define OMAP3430_PWRDN_96M_SHIFT 27
473#define OMAP3430_PERIPH_DPLL_RAMPTIME_SHIFT 24
474#define OMAP3430_PERIPH_DPLL_RAMPTIME_MASK (0x3 << 24)
475#define OMAP3430_PERIPH_DPLL_FREQSEL_SHIFT 20
476#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20) 119#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
477#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19 120#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
478#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_MASK (1 << 19)
479#define OMAP3430_EN_PERIPH_DPLL_SHIFT 16
480#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16) 121#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
481#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12 122#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
482#define OMAP3430_CORE_DPLL_RAMPTIME_SHIFT 8
483#define OMAP3430_CORE_DPLL_RAMPTIME_MASK (0x3 << 8)
484#define OMAP3430_CORE_DPLL_FREQSEL_SHIFT 4
485#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4) 123#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
486#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3 124#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
487#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_MASK (1 << 3)
488#define OMAP3430_EN_CORE_DPLL_SHIFT 0
489#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0) 125#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
490
491/* CM_CLKEN2_PLL */
492#define OMAP3430ES2_EN_PERIPH2_DPLL_LPMODE_SHIFT 10
493#define OMAP3430ES2_PERIPH2_DPLL_RAMPTIME_MASK (0x3 << 8)
494#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_SHIFT 4
495#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4) 126#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
496#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3 127#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
497#define OMAP3430ES2_EN_PERIPH2_DPLL_SHIFT 0
498#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0) 128#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
499
500/* CM_IDLEST_CKGEN */
501#define OMAP3430_ST_54M_CLK_MASK (1 << 5)
502#define OMAP3430_ST_12M_CLK_MASK (1 << 4)
503#define OMAP3430_ST_48M_CLK_MASK (1 << 3)
504#define OMAP3430_ST_96M_CLK_MASK (1 << 2)
505#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
506#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1) 129#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
507#define OMAP3430_ST_CORE_CLK_SHIFT 0
508#define OMAP3430_ST_CORE_CLK_MASK (1 << 0) 130#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
509
510/* CM_IDLEST2_CKGEN */
511#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2
512#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2)
513#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
514#define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1)
515#define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0
516#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0) 131#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
517
518/* CM_AUTOIDLE_PLL */
519#define OMAP3430_AUTO_PERIPH_DPLL_SHIFT 3
520#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3) 132#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
521#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
522#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 133#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
523
524/* CM_AUTOIDLE2_PLL */
525#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
526#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0) 134#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
527
528/* CM_CLKSEL1_PLL */
529/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
530#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 135#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
531#define OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK (0x1f << 27)
532#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5 136#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
533#define OMAP3430_CORE_DPLL_MULT_SHIFT 16
534#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) 137#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
535#define OMAP3430_CORE_DPLL_DIV_SHIFT 8
536#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) 138#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
537#define OMAP3430_SOURCE_96M_SHIFT 6 139#define OMAP3430_SOURCE_96M_SHIFT 6
538#define OMAP3430_SOURCE_96M_MASK (1 << 6)
539#define OMAP3430_SOURCE_96M_WIDTH 1 140#define OMAP3430_SOURCE_96M_WIDTH 1
540#define OMAP3430_SOURCE_54M_SHIFT 5 141#define OMAP3430_SOURCE_54M_SHIFT 5
541#define OMAP3430_SOURCE_54M_MASK (1 << 5)
542#define OMAP3430_SOURCE_54M_WIDTH 1 142#define OMAP3430_SOURCE_54M_WIDTH 1
543#define OMAP3430_SOURCE_48M_SHIFT 3
544#define OMAP3430_SOURCE_48M_MASK (1 << 3) 143#define OMAP3430_SOURCE_48M_MASK (1 << 3)
545
546/* CM_CLKSEL2_PLL */
547#define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8
548#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8) 144#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
549#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8) 145#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
550#define OMAP3430_PERIPH_DPLL_DIV_SHIFT 0
551#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0) 146#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
552#define OMAP3630_PERIPH_DPLL_DCO_SEL_SHIFT 21
553#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21) 147#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
554#define OMAP3630_PERIPH_DPLL_SD_DIV_SHIFT 24
555#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24) 148#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
556
557/* CM_CLKSEL3_PLL */
558#define OMAP3430_DIV_96M_SHIFT 0 149#define OMAP3430_DIV_96M_SHIFT 0
559#define OMAP3430_DIV_96M_MASK (0x1f << 0)
560#define OMAP3430_DIV_96M_WIDTH 5
561#define OMAP3630_DIV_96M_MASK (0x3f << 0)
562#define OMAP3630_DIV_96M_WIDTH 6 150#define OMAP3630_DIV_96M_WIDTH 6
563
564/* CM_CLKSEL4_PLL */
565#define OMAP3430ES2_PERIPH2_DPLL_MULT_SHIFT 8
566#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8) 151#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
567#define OMAP3430ES2_PERIPH2_DPLL_DIV_SHIFT 0
568#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0) 152#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
569
570/* CM_CLKSEL5_PLL */
571#define OMAP3430ES2_DIV_120M_SHIFT 0 153#define OMAP3430ES2_DIV_120M_SHIFT 0
572#define OMAP3430ES2_DIV_120M_MASK (0x1f << 0)
573#define OMAP3430ES2_DIV_120M_WIDTH 5 154#define OMAP3430ES2_DIV_120M_WIDTH 5
574
575/* CM_CLKOUT_CTRL */
576#define OMAP3430_CLKOUT2_EN_SHIFT 7 155#define OMAP3430_CLKOUT2_EN_SHIFT 7
577#define OMAP3430_CLKOUT2_EN_MASK (1 << 7)
578#define OMAP3430_CLKOUT2_DIV_SHIFT 3 156#define OMAP3430_CLKOUT2_DIV_SHIFT 3
579#define OMAP3430_CLKOUT2_DIV_MASK (0x7 << 3)
580#define OMAP3430_CLKOUT2_DIV_WIDTH 3 157#define OMAP3430_CLKOUT2_DIV_WIDTH 3
581#define OMAP3430_CLKOUT2SOURCE_SHIFT 0
582#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0) 158#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
583
584/* CM_FCLKEN_DSS */
585#define OMAP3430_EN_TV_MASK (1 << 2)
586#define OMAP3430_EN_TV_SHIFT 2 159#define OMAP3430_EN_TV_SHIFT 2
587#define OMAP3430_EN_DSS2_MASK (1 << 1)
588#define OMAP3430_EN_DSS2_SHIFT 1 160#define OMAP3430_EN_DSS2_SHIFT 1
589#define OMAP3430_EN_DSS1_MASK (1 << 0)
590#define OMAP3430_EN_DSS1_SHIFT 0 161#define OMAP3430_EN_DSS1_SHIFT 0
591
592/* CM_ICLKEN_DSS */
593#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_MASK (1 << 0)
594#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 162#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
595
596/* CM_IDLEST_DSS */
597#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 163#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
598#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1)
599#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 164#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
600#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0)
601#define OMAP3430ES1_ST_DSS_SHIFT 0 165#define OMAP3430ES1_ST_DSS_SHIFT 0
602#define OMAP3430ES1_ST_DSS_MASK (1 << 0)
603
604/* CM_AUTOIDLE_DSS */
605#define OMAP3430_AUTO_DSS_MASK (1 << 0)
606#define OMAP3430_AUTO_DSS_SHIFT 0
607
608/* CM_CLKSEL_DSS */
609#define OMAP3430_CLKSEL_TV_SHIFT 8 166#define OMAP3430_CLKSEL_TV_SHIFT 8
610#define OMAP3430_CLKSEL_TV_MASK (0x1f << 8)
611#define OMAP3430_CLKSEL_TV_WIDTH 5
612#define OMAP3630_CLKSEL_TV_MASK (0x3f << 8)
613#define OMAP3630_CLKSEL_TV_WIDTH 6 167#define OMAP3630_CLKSEL_TV_WIDTH 6
614#define OMAP3430_CLKSEL_DSS1_SHIFT 0 168#define OMAP3430_CLKSEL_DSS1_SHIFT 0
615#define OMAP3430_CLKSEL_DSS1_MASK (0x1f << 0)
616#define OMAP3430_CLKSEL_DSS1_WIDTH 5
617#define OMAP3630_CLKSEL_DSS1_MASK (0x3f << 0)
618#define OMAP3630_CLKSEL_DSS1_WIDTH 6 169#define OMAP3630_CLKSEL_DSS1_WIDTH 6
619
620/* CM_SLEEPDEP_DSS specific bits */
621
622/* CM_CLKSTCTRL_DSS */
623#define OMAP3430_CLKTRCTRL_DSS_SHIFT 0
624#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0) 170#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
625
626/* CM_CLKSTST_DSS */
627#define OMAP3430_CLKACTIVITY_DSS_SHIFT 0
628#define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0)
629
630/* CM_FCLKEN_CAM specific bits */
631#define OMAP3430_EN_CSI2_MASK (1 << 1)
632#define OMAP3430_EN_CSI2_SHIFT 1 171#define OMAP3430_EN_CSI2_SHIFT 1
633
634/* CM_ICLKEN_CAM specific bits */
635
636/* CM_IDLEST_CAM */
637#define OMAP3430_ST_CAM_MASK (1 << 0)
638
639/* CM_AUTOIDLE_CAM */
640#define OMAP3430_AUTO_CAM_MASK (1 << 0)
641#define OMAP3430_AUTO_CAM_SHIFT 0
642
643/* CM_CLKSEL_CAM */
644#define OMAP3430_CLKSEL_CAM_SHIFT 0 172#define OMAP3430_CLKSEL_CAM_SHIFT 0
645#define OMAP3430_CLKSEL_CAM_MASK (0x1f << 0)
646#define OMAP3430_CLKSEL_CAM_WIDTH 5
647#define OMAP3630_CLKSEL_CAM_MASK (0x3f << 0)
648#define OMAP3630_CLKSEL_CAM_WIDTH 6 173#define OMAP3630_CLKSEL_CAM_WIDTH 6
649
650/* CM_SLEEPDEP_CAM specific bits */
651
652/* CM_CLKSTCTRL_CAM */
653#define OMAP3430_CLKTRCTRL_CAM_SHIFT 0
654#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0) 174#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
655
656/* CM_CLKSTST_CAM */
657#define OMAP3430_CLKACTIVITY_CAM_SHIFT 0
658#define OMAP3430_CLKACTIVITY_CAM_MASK (1 << 0)
659
660/* CM_FCLKEN_PER specific bits */
661
662/* CM_ICLKEN_PER specific bits */
663
664/* CM_IDLEST_PER */
665#define OMAP3430_ST_WDT3_SHIFT 12
666#define OMAP3430_ST_WDT3_MASK (1 << 12)
667#define OMAP3430_ST_MCBSP4_SHIFT 2 175#define OMAP3430_ST_MCBSP4_SHIFT 2
668#define OMAP3430_ST_MCBSP4_MASK (1 << 2)
669#define OMAP3430_ST_MCBSP3_SHIFT 1 176#define OMAP3430_ST_MCBSP3_SHIFT 1
670#define OMAP3430_ST_MCBSP3_MASK (1 << 1)
671#define OMAP3430_ST_MCBSP2_SHIFT 0 177#define OMAP3430_ST_MCBSP2_SHIFT 0
672#define OMAP3430_ST_MCBSP2_MASK (1 << 0)
673
674/* CM_AUTOIDLE_PER */
675#define OMAP3630_AUTO_UART4_MASK (1 << 18)
676#define OMAP3630_AUTO_UART4_SHIFT 18
677#define OMAP3430_AUTO_GPIO6_MASK (1 << 17)
678#define OMAP3430_AUTO_GPIO6_SHIFT 17
679#define OMAP3430_AUTO_GPIO5_MASK (1 << 16)
680#define OMAP3430_AUTO_GPIO5_SHIFT 16
681#define OMAP3430_AUTO_GPIO4_MASK (1 << 15)
682#define OMAP3430_AUTO_GPIO4_SHIFT 15
683#define OMAP3430_AUTO_GPIO3_MASK (1 << 14)
684#define OMAP3430_AUTO_GPIO3_SHIFT 14
685#define OMAP3430_AUTO_GPIO2_MASK (1 << 13)
686#define OMAP3430_AUTO_GPIO2_SHIFT 13
687#define OMAP3430_AUTO_WDT3_MASK (1 << 12)
688#define OMAP3430_AUTO_WDT3_SHIFT 12
689#define OMAP3430_AUTO_UART3_MASK (1 << 11)
690#define OMAP3430_AUTO_UART3_SHIFT 11
691#define OMAP3430_AUTO_GPT9_MASK (1 << 10)
692#define OMAP3430_AUTO_GPT9_SHIFT 10
693#define OMAP3430_AUTO_GPT8_MASK (1 << 9)
694#define OMAP3430_AUTO_GPT8_SHIFT 9
695#define OMAP3430_AUTO_GPT7_MASK (1 << 8)
696#define OMAP3430_AUTO_GPT7_SHIFT 8
697#define OMAP3430_AUTO_GPT6_MASK (1 << 7)
698#define OMAP3430_AUTO_GPT6_SHIFT 7
699#define OMAP3430_AUTO_GPT5_MASK (1 << 6)
700#define OMAP3430_AUTO_GPT5_SHIFT 6
701#define OMAP3430_AUTO_GPT4_MASK (1 << 5)
702#define OMAP3430_AUTO_GPT4_SHIFT 5
703#define OMAP3430_AUTO_GPT3_MASK (1 << 4)
704#define OMAP3430_AUTO_GPT3_SHIFT 4
705#define OMAP3430_AUTO_GPT2_MASK (1 << 3)
706#define OMAP3430_AUTO_GPT2_SHIFT 3
707#define OMAP3430_AUTO_MCBSP4_MASK (1 << 2)
708#define OMAP3430_AUTO_MCBSP4_SHIFT 2
709#define OMAP3430_AUTO_MCBSP3_MASK (1 << 1)
710#define OMAP3430_AUTO_MCBSP3_SHIFT 1
711#define OMAP3430_AUTO_MCBSP2_MASK (1 << 0)
712#define OMAP3430_AUTO_MCBSP2_SHIFT 0
713
714/* CM_CLKSEL_PER */
715#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7) 178#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
716#define OMAP3430_CLKSEL_GPT9_SHIFT 7
717#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6) 179#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
718#define OMAP3430_CLKSEL_GPT8_SHIFT 6
719#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5) 180#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
720#define OMAP3430_CLKSEL_GPT7_SHIFT 5
721#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4) 181#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
722#define OMAP3430_CLKSEL_GPT6_SHIFT 4
723#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3) 182#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
724#define OMAP3430_CLKSEL_GPT5_SHIFT 3
725#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2) 183#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
726#define OMAP3430_CLKSEL_GPT4_SHIFT 2
727#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1) 184#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
728#define OMAP3430_CLKSEL_GPT3_SHIFT 1
729#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0) 185#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
730#define OMAP3430_CLKSEL_GPT2_SHIFT 0
731
732/* CM_SLEEPDEP_PER specific bits */
733#define OMAP3430_CM_SLEEPDEP_PER_EN_IVA2_MASK (1 << 2)
734
735/* CM_CLKSTCTRL_PER */
736#define OMAP3430_CLKTRCTRL_PER_SHIFT 0
737#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0) 186#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
738
739/* CM_CLKSTST_PER */
740#define OMAP3430_CLKACTIVITY_PER_SHIFT 0
741#define OMAP3430_CLKACTIVITY_PER_MASK (1 << 0)
742
743/* CM_CLKSEL1_EMU */
744#define OMAP3430_DIV_DPLL4_SHIFT 24 187#define OMAP3430_DIV_DPLL4_SHIFT 24
745#define OMAP3430_DIV_DPLL4_MASK (0x1f << 24)
746#define OMAP3430_DIV_DPLL4_WIDTH 5
747#define OMAP3630_DIV_DPLL4_MASK (0x3f << 24)
748#define OMAP3630_DIV_DPLL4_WIDTH 6 188#define OMAP3630_DIV_DPLL4_WIDTH 6
749#define OMAP3430_DIV_DPLL3_SHIFT 16 189#define OMAP3430_DIV_DPLL3_SHIFT 16
750#define OMAP3430_DIV_DPLL3_MASK (0x1f << 16)
751#define OMAP3430_DIV_DPLL3_WIDTH 5 190#define OMAP3430_DIV_DPLL3_WIDTH 5
752#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11 191#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
753#define OMAP3430_CLKSEL_TRACECLK_MASK (0x7 << 11)
754#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3 192#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
755#define OMAP3430_CLKSEL_PCLK_SHIFT 8 193#define OMAP3430_CLKSEL_PCLK_SHIFT 8
756#define OMAP3430_CLKSEL_PCLK_MASK (0x7 << 8)
757#define OMAP3430_CLKSEL_PCLK_WIDTH 3 194#define OMAP3430_CLKSEL_PCLK_WIDTH 3
758#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6 195#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
759#define OMAP3430_CLKSEL_PCLKX2_MASK (0x3 << 6)
760#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2 196#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
761#define OMAP3430_CLKSEL_ATCLK_SHIFT 4 197#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
762#define OMAP3430_CLKSEL_ATCLK_MASK (0x3 << 4)
763#define OMAP3430_CLKSEL_ATCLK_WIDTH 2 198#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
764#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2 199#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
765#define OMAP3430_TRACE_MUX_CTRL_MASK (0x3 << 2)
766#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2 200#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
767#define OMAP3430_MUX_CTRL_SHIFT 0
768#define OMAP3430_MUX_CTRL_MASK (0x3 << 0) 201#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
769#define OMAP3430_MUX_CTRL_WIDTH 2
770
771/* CM_CLKSTCTRL_EMU */
772#define OMAP3430_CLKTRCTRL_EMU_SHIFT 0
773#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0) 202#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
774
775/* CM_CLKSTST_EMU */
776#define OMAP3430_CLKACTIVITY_EMU_SHIFT 0
777#define OMAP3430_CLKACTIVITY_EMU_MASK (1 << 0)
778
779/* CM_CLKSEL2_EMU specific bits */
780#define OMAP3430_CORE_DPLL_EMU_MULT_SHIFT 8
781#define OMAP3430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
782#define OMAP3430_CORE_DPLL_EMU_DIV_SHIFT 0
783#define OMAP3430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
784
785/* CM_CLKSEL3_EMU specific bits */
786#define OMAP3430_PERIPH_DPLL_EMU_MULT_SHIFT 8
787#define OMAP3430_PERIPH_DPLL_EMU_MULT_MASK (0x7ff << 8)
788#define OMAP3430_PERIPH_DPLL_EMU_DIV_SHIFT 0
789#define OMAP3430_PERIPH_DPLL_EMU_DIV_MASK (0x7f << 0)
790
791/* CM_POLCTRL */
792#define OMAP3430_CLKOUT2_POL_MASK (1 << 0)
793
794/* CM_IDLEST_NEON */
795#define OMAP3430_ST_NEON_MASK (1 << 0)
796
797/* CM_CLKSTCTRL_NEON */
798#define OMAP3430_CLKTRCTRL_NEON_SHIFT 0
799#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0) 203#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
800
801/* CM_FCLKEN_USBHOST */
802#define OMAP3430ES2_EN_USBHOST2_SHIFT 1 204#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
803#define OMAP3430ES2_EN_USBHOST2_MASK (1 << 1)
804#define OMAP3430ES2_EN_USBHOST1_SHIFT 0 205#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
805#define OMAP3430ES2_EN_USBHOST1_MASK (1 << 0)
806
807/* CM_ICLKEN_USBHOST */
808#define OMAP3430ES2_EN_USBHOST_SHIFT 0 206#define OMAP3430ES2_EN_USBHOST_SHIFT 0
809#define OMAP3430ES2_EN_USBHOST_MASK (1 << 0)
810
811/* CM_IDLEST_USBHOST */
812#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 207#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
813#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1)
814#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 208#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
815#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0)
816
817/* CM_AUTOIDLE_USBHOST */
818#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0
819#define OMAP3430ES2_AUTO_USBHOST_MASK (1 << 0)
820
821/* CM_SLEEPDEP_USBHOST */
822#define OMAP3430ES2_EN_MPU_SHIFT 1
823#define OMAP3430ES2_EN_MPU_MASK (1 << 1)
824#define OMAP3430ES2_EN_IVA2_SHIFT 2
825#define OMAP3430ES2_EN_IVA2_MASK (1 << 2)
826
827/* CM_CLKSTCTRL_USBHOST */
828#define OMAP3430ES2_CLKTRCTRL_USBHOST_SHIFT 0
829#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0) 209#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
830
831/* CM_CLKSTST_USBHOST */
832#define OMAP3430ES2_CLKACTIVITY_USBHOST_SHIFT 0
833#define OMAP3430ES2_CLKACTIVITY_USBHOST_MASK (1 << 0)
834
835/*
836 *
837 */
838
839/* OMAP3XXX CM_CLKSTCTRL_*.CLKTRCTRL_* register bit values */
840#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0 210#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
841#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1 211#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
842#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2 212#define OMAP34XX_CLKSTCTRL_FORCE_WAKEUP 0x2
843#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3 213#define OMAP34XX_CLKSTCTRL_ENABLE_AUTO 0x3
844
845
846#endif 214#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 4c6c2f7de65b..4dbbd99b6e1e 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,1683 +22,125 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
24 24
25/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
26#define OMAP4430_ABE_DYNDEP_SHIFT 3
27#define OMAP4430_ABE_DYNDEP_WIDTH 0x1
28#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
29
30/*
31 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
32 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
33 */
34#define OMAP4430_ABE_STATDEP_SHIFT 3 25#define OMAP4430_ABE_STATDEP_SHIFT 3
35#define OMAP4430_ABE_STATDEP_WIDTH 0x1
36#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
37
38/* Used by CM_L4CFG_DYNAMICDEP */
39#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
40#define OMAP4430_ALWONCORE_DYNDEP_WIDTH 0x1
41#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
42
43/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
44#define OMAP4430_ALWONCORE_STATDEP_SHIFT 16
45#define OMAP4430_ALWONCORE_STATDEP_WIDTH 0x1
46#define OMAP4430_ALWONCORE_STATDEP_MASK (1 << 16)
47
48/*
49 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
50 * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
51 * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
52 */
53#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
54#define OMAP4430_AUTO_DPLL_MODE_WIDTH 0x3
55#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) 26#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
56
57/* Used by CM_L4CFG_DYNAMICDEP */
58#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
59#define OMAP4430_CEFUSE_DYNDEP_WIDTH 0x1
60#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
61
62/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
63#define OMAP4430_CEFUSE_STATDEP_SHIFT 17
64#define OMAP4430_CEFUSE_STATDEP_WIDTH 0x1
65#define OMAP4430_CEFUSE_STATDEP_MASK (1 << 17)
66
67/* Used by CM1_ABE_CLKSTCTRL */
68#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
69#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
70#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
71
72/* Used by CM1_ABE_CLKSTCTRL */
73#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT 12
74#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH 0x1
75#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK (1 << 12)
76
77/* Used by CM_WKUP_CLKSTCTRL */
78#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
79#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
80#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
81
82/* Used by CM1_ABE_CLKSTCTRL */
83#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT 11
84#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH 0x1
85#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK (1 << 11)
86
87/* Used by CM1_ABE_CLKSTCTRL */
88#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
89#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
90#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
91
92/* Used by CM_MEMIF_CLKSTCTRL */
93#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
94#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH 0x1
95#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
96
97/* Used by CM_MEMIF_CLKSTCTRL */
98#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
99#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH 0x1
100#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
101
102/* Used by CM_MEMIF_CLKSTCTRL */
103#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
104#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH 0x1
105#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
106
107/* Used by CM_CAM_CLKSTCTRL */
108#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT 9
109#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH 0x1
110#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK (1 << 9)
111
112/* Used by CM_ALWON_CLKSTCTRL */
113#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT 12
114#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH 0x1
115#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK (1 << 12)
116
117/* Used by CM_EMU_CLKSTCTRL */
118#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
119#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH 0x1
120#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
121
122/* Used by CM_L4CFG_CLKSTCTRL */
123#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
124#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH 0x1
125#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
126
127/* Used by CM_CEFUSE_CLKSTCTRL */
128#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
129#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH 0x1
130#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
131
132/* Used by CM_MEMIF_CLKSTCTRL */
133#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
134#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH 0x1
135#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
136
137/* Used by CM_L4PER_CLKSTCTRL */
138#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
139#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH 0x1
140#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
141
142/* Used by CM_L4PER_CLKSTCTRL */
143#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
144#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH 0x1
145#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
146
147/* Used by CM_L4PER_CLKSTCTRL */
148#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
149#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH 0x1
150#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
151
152/* Used by CM_L4PER_CLKSTCTRL */
153#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
154#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH 0x1
155#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
156
157/* Used by CM_L4PER_CLKSTCTRL */
158#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
159#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH 0x1
160#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
161
162/* Used by CM_L4PER_CLKSTCTRL */
163#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
164#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH 0x1
165#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
166
167/* Used by CM_DSS_CLKSTCTRL */
168#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT 10
169#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH 0x1
170#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK (1 << 10)
171
172/* Used by CM_DSS_CLKSTCTRL */
173#define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT 9
174#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH 0x1
175#define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK (1 << 9)
176
177/* Used by CM_DUCATI_CLKSTCTRL */
178#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT 8
179#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH 0x1
180#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK (1 << 8)
181
182/* Used by CM_EMU_CLKSTCTRL */
183#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT 8
184#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH 0x1
185#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK (1 << 8)
186
187/* Used by CM_CAM_CLKSTCTRL */
188#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
189#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH 0x1
190#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
191
192/* Used by CM_L4PER_CLKSTCTRL */
193#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
194#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH 0x1
195#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
196
197/* Used by CM1_ABE_CLKSTCTRL */
198#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
199#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
200#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
201
202/* Used by CM_DSS_CLKSTCTRL */
203#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
204#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH 0x1
205#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
206
207/* Used by CM_L3INIT_CLKSTCTRL */
208#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
209#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
210#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
211
212/* Used by CM_L3INIT_CLKSTCTRL */
213#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
214#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
215#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
216
217/* Used by CM_L3INIT_CLKSTCTRL */
218#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
219#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
220#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
221
222/* Used by CM_L3INIT_CLKSTCTRL */
223#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
224#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
225#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
226
227/* Used by CM_L3INIT_CLKSTCTRL */
228#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
229#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH 0x1
230#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
231
232/* Used by CM_L3INIT_CLKSTCTRL */
233#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
234#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH 0x1
235#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
236
237/* Used by CM_L3INIT_CLKSTCTRL */
238#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
239#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH 0x1
240#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
241
242/* Used by CM_L3INIT_CLKSTCTRL */
243#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
244#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH 0x1
245#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
246
247/* Used by CM_L3INIT_CLKSTCTRL */
248#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
249#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH 0x1
250#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
251
252/* Used by CM_L3INIT_CLKSTCTRL */
253#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
254#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH 0x1
255#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
256
257/* Used by CM_L3INIT_CLKSTCTRL */
258#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
259#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH 0x1
260#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
261
262/* Used by CM_L3INIT_CLKSTCTRL */
263#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
264#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH 0x1
265#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
266
267/* Used by CM_L3INIT_CLKSTCTRL */
268#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
269#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH 0x1
270#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
271
272/* Used by CM_CAM_CLKSTCTRL */
273#define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT 8
274#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH 0x1
275#define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK (1 << 8)
276
277/* Used by CM_IVAHD_CLKSTCTRL */
278#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT 8
279#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH 0x1
280#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK (1 << 8)
281
282/* Used by CM_D2D_CLKSTCTRL */
283#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
284#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH 0x1
285#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
286
287/* Used by CM_L3_1_CLKSTCTRL */
288#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
289#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH 0x1
290#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
291
292/* Used by CM_L3_2_CLKSTCTRL */
293#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
294#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH 0x1
295#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
296
297/* Used by CM_D2D_CLKSTCTRL */
298#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT 8
299#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH 0x1
300#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK (1 << 8)
301
302/* Used by CM_SDMA_CLKSTCTRL */
303#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT 8
304#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH 0x1
305#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK (1 << 8)
306
307/* Used by CM_DSS_CLKSTCTRL */
308#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
309#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH 0x1
310#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
311
312/* Used by CM_MEMIF_CLKSTCTRL */
313#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
314#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH 0x1
315#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
316
317/* Used by CM_GFX_CLKSTCTRL */
318#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
319#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH 0x1
320#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
321
322/* Used by CM_L3INIT_CLKSTCTRL */
323#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
324#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH 0x1
325#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
326
327/* Used by CM_L3INSTR_CLKSTCTRL */
328#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT 8
329#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH 0x1
330#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK (1 << 8)
331
332/* Used by CM_L4SEC_CLKSTCTRL */
333#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT 8
334#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH 0x1
335#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK (1 << 8)
336
337/* Used by CM_ALWON_CLKSTCTRL */
338#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT 8
339#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH 0x1
340#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK (1 << 8)
341
342/* Used by CM_CEFUSE_CLKSTCTRL */
343#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
344#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH 0x1
345#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
346
347/* Used by CM_L4CFG_CLKSTCTRL */
348#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
349#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH 0x1
350#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
351
352/* Used by CM_D2D_CLKSTCTRL */
353#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
354#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH 0x1
355#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
356
357/* Used by CM_L3INIT_CLKSTCTRL */
358#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
359#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH 0x1
360#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
361
362/* Used by CM_L4PER_CLKSTCTRL */
363#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
364#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH 0x1
365#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
366
367/* Used by CM_L4SEC_CLKSTCTRL */
368#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT 9
369#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH 0x1
370#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK (1 << 9)
371
372/* Used by CM_WKUP_CLKSTCTRL */
373#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
374#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH 0x1
375#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
376
377/* Used by CM_MPU_CLKSTCTRL */
378#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
379#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH 0x1
380#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
381
382/* Used by CM1_ABE_CLKSTCTRL */
383#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
384#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH 0x1
385#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
386
387/* Used by CM_L4PER_CLKSTCTRL */
388#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
389#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH 0x1
390#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
391
392/* Used by CM_L4PER_CLKSTCTRL */
393#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
394#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
395#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
396
397/* Used by CM_L4PER_CLKSTCTRL */
398#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
399#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
400#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
401
402/* Used by CM_L4PER_CLKSTCTRL */
403#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
404#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
405#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
406
407/* Used by CM_L4PER_CLKSTCTRL */
408#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
409#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH 0x1
410#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
411
412/* Used by CM_L4PER_CLKSTCTRL */
413#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
414#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH 0x1
415#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
416
417/* Used by CM_L4PER_CLKSTCTRL */
418#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
419#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
420
421/* Used by CM_L4PER_CLKSTCTRL */
422#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
423#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH 0x1
424#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
425
426/* Used by CM_L4PER_CLKSTCTRL */
427#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
428#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH 0x1
429#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
430
431/* Used by CM_MEMIF_CLKSTCTRL */
432#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
433#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH 0x1
434#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
435
436/* Used by CM_GFX_CLKSTCTRL */
437#define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT 9
438#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH 0x1
439#define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK (1 << 9)
440
441/* Used by CM_ALWON_CLKSTCTRL */
442#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT 11
443#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH 0x1
444#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK (1 << 11)
445
446/* Used by CM_ALWON_CLKSTCTRL */
447#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT 10
448#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH 0x1
449#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK (1 << 10)
450
451/* Used by CM_ALWON_CLKSTCTRL */
452#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT 9
453#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH 0x1
454#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK (1 << 9)
455
456/* Used by CM_WKUP_CLKSTCTRL */
457#define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT 8
458#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH 0x1
459#define OMAP4430_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
460
461/* Used by CM_TESLA_CLKSTCTRL */
462#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
463#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH 0x1
464#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
465
466/* Used by CM_L3INIT_CLKSTCTRL */
467#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
468#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
469#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
470
471/* Used by CM_L3INIT_CLKSTCTRL */
472#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
473#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
474#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
475
476/* Used by CM_L3INIT_CLKSTCTRL */
477#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
478#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
479#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
480
481/* Used by CM_L3INIT_CLKSTCTRL */
482#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
483#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH 0x1
484#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
485
486/* Used by CM_L3INIT_CLKSTCTRL */
487#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
488#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
489#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
490
491/* Used by CM_L3INIT_CLKSTCTRL */
492#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
493#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
494#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
495
496/* Used by CM_WKUP_CLKSTCTRL */
497#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
498#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH 0x1
499#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
500
501/* Used by CM_L3INIT_CLKSTCTRL */
502#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
503#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
504#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
505
506/* Used by CM_L3INIT_CLKSTCTRL */
507#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
508#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
509#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
510
511/* Used by CM_WKUP_CLKSTCTRL */
512#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
513#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH 0x1
514#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
515
516/* Used by CM_WKUP_CLKSTCTRL */
517#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
518#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH 0x1
519#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
520
521/*
522 * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
523 * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
524 * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
525 * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
526 * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
527 * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
528 */
529#define OMAP4430_CLKSEL_SHIFT 24 27#define OMAP4430_CLKSEL_SHIFT 24
530#define OMAP4430_CLKSEL_WIDTH 0x1 28#define OMAP4430_CLKSEL_WIDTH 0x1
531#define OMAP4430_CLKSEL_MASK (1 << 24) 29#define OMAP4430_CLKSEL_MASK (1 << 24)
532
533/*
534 * Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
535 * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
536 */
537#define OMAP4430_CLKSEL_0_0_SHIFT 0 30#define OMAP4430_CLKSEL_0_0_SHIFT 0
538#define OMAP4430_CLKSEL_0_0_WIDTH 0x1 31#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
539#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
540
541/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
542#define OMAP4430_CLKSEL_0_1_SHIFT 0 32#define OMAP4430_CLKSEL_0_1_SHIFT 0
543#define OMAP4430_CLKSEL_0_1_WIDTH 0x2 33#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
544#define OMAP4430_CLKSEL_0_1_MASK (0x3 << 0)
545
546/* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
547#define OMAP4430_CLKSEL_24_25_SHIFT 24 34#define OMAP4430_CLKSEL_24_25_SHIFT 24
548#define OMAP4430_CLKSEL_24_25_WIDTH 0x2 35#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
549#define OMAP4430_CLKSEL_24_25_MASK (0x3 << 24)
550
551/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
552#define OMAP4430_CLKSEL_60M_SHIFT 24 36#define OMAP4430_CLKSEL_60M_SHIFT 24
553#define OMAP4430_CLKSEL_60M_WIDTH 0x1 37#define OMAP4430_CLKSEL_60M_WIDTH 0x1
554#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
555
556/* Used by CM_MPU_MPU_CLKCTRL */
557#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
558#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
559#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
560
561/* Used by CM1_ABE_AESS_CLKCTRL */
562#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 38#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
563#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 39#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
564#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
565
566/* Used by CM_CLKSEL_CORE */
567#define OMAP4430_CLKSEL_CORE_SHIFT 0 40#define OMAP4430_CLKSEL_CORE_SHIFT 0
568#define OMAP4430_CLKSEL_CORE_WIDTH 0x1 41#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
569#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
570
571/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
572#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
573#define OMAP4430_CLKSEL_CORE_1_1_WIDTH 0x1
574#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
575
576/* Used by CM_WKUP_USIM_CLKCTRL */
577#define OMAP4430_CLKSEL_DIV_SHIFT 24 42#define OMAP4430_CLKSEL_DIV_SHIFT 24
578#define OMAP4430_CLKSEL_DIV_WIDTH 0x1 43#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
579#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
580
581/* Used by CM_MPU_MPU_CLKCTRL */
582#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
583#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH 0x1
584#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
585
586/* Used by CM_CAM_FDIF_CLKCTRL */
587#define OMAP4430_CLKSEL_FCLK_SHIFT 24 44#define OMAP4430_CLKSEL_FCLK_SHIFT 24
588#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 45#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
589#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
590
591/* Used by CM_L4PER_MCBSP4_CLKCTRL */
592#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 46#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
593#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 47#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
594#define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK (1 << 25)
595
596/*
597 * Renamed from CLKSEL_INTERNAL_SOURCE Used by CM1_ABE_DMIC_CLKCTRL,
598 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
599 * CM1_ABE_MCBSP3_CLKCTRL
600 */
601#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
602#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH 0x2
603#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
604
605/* Used by CM_CLKSEL_CORE */
606#define OMAP4430_CLKSEL_L3_SHIFT 4 48#define OMAP4430_CLKSEL_L3_SHIFT 4
607#define OMAP4430_CLKSEL_L3_WIDTH 0x1 49#define OMAP4430_CLKSEL_L3_WIDTH 0x1
608#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
609
610/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
611#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
612#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH 0x1
613#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
614
615/* Used by CM_CLKSEL_CORE */
616#define OMAP4430_CLKSEL_L4_SHIFT 8 50#define OMAP4430_CLKSEL_L4_SHIFT 8
617#define OMAP4430_CLKSEL_L4_WIDTH 0x1 51#define OMAP4430_CLKSEL_L4_WIDTH 0x1
618#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
619
620/* Used by CM_CLKSEL_ABE */
621#define OMAP4430_CLKSEL_OPP_SHIFT 0 52#define OMAP4430_CLKSEL_OPP_SHIFT 0
622#define OMAP4430_CLKSEL_OPP_WIDTH 0x2 53#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
623#define OMAP4430_CLKSEL_OPP_MASK (0x3 << 0)
624
625/* Used by CM_EMU_DEBUGSS_CLKCTRL */
626#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 54#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
627#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 55#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
628#define OMAP4430_CLKSEL_PMD_STM_CLK_MASK (0x7 << 27)
629
630/* Used by CM_EMU_DEBUGSS_CLKCTRL */
631#define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT 24
632#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH 0x3
633#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) 56#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
634
635/* Used by CM_GFX_GFX_CLKCTRL */
636#define OMAP4430_CLKSEL_SGX_FCLK_SHIFT 24
637#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH 0x1
638#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) 57#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
639
640/*
641 * Used by CM1_ABE_DMIC_CLKCTRL, CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL,
642 * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
643 */
644#define OMAP4430_CLKSEL_SOURCE_SHIFT 24
645#define OMAP4430_CLKSEL_SOURCE_WIDTH 0x2
646#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) 58#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
647
648/* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
649#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
650#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH 0x1
651#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) 59#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
652
653/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
654#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 60#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
655#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 61#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
656#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
657
658/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
659#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 62#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
660#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 63#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
661#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
662
663/*
664 * Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
665 * CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
666 * CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
667 * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
668 * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
669 * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
670 * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
671 */
672#define OMAP4430_CLKTRCTRL_SHIFT 0 64#define OMAP4430_CLKTRCTRL_SHIFT 0
673#define OMAP4430_CLKTRCTRL_WIDTH 0x2
674#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) 65#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
675
676/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
677#define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT 0
678#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH 0x7
679#define OMAP4430_CORE_DPLL_EMU_DIV_MASK (0x7f << 0)
680
681/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
682#define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT 8
683#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH 0xb
684#define OMAP4430_CORE_DPLL_EMU_MULT_MASK (0x7ff << 8)
685
686/* Used by REVISION_CM1, REVISION_CM2 */
687#define OMAP4430_CUSTOM_SHIFT 6
688#define OMAP4430_CUSTOM_WIDTH 0x2
689#define OMAP4430_CUSTOM_MASK (0x3 << 6)
690
691/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
692#define OMAP4430_D2D_DYNDEP_SHIFT 18
693#define OMAP4430_D2D_DYNDEP_WIDTH 0x1
694#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
695
696/* Used by CM_MPU_STATICDEP */
697#define OMAP4430_D2D_STATDEP_SHIFT 18
698#define OMAP4430_D2D_STATDEP_WIDTH 0x1
699#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
700
701/* Used by CM_CLKSEL_DPLL_MPU */
702#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
703#define OMAP4460_DCC_COUNT_MAX_WIDTH 0x8
704#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
705
706/* Used by CM_CLKSEL_DPLL_MPU */
707#define OMAP4460_DCC_EN_SHIFT 22
708#define OMAP4460_DCC_EN_MASK (1 << 22)
709
710/*
711 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
712 * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
713 * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
714 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
715 */
716#define OMAP4430_DELTAMSTEP_SHIFT 0
717#define OMAP4430_DELTAMSTEP_WIDTH 0x14
718#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
719
720/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
721#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
722#define OMAP4460_DELTAMSTEP_0_20_WIDTH 0x15
723#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
724
725/* Used by CM_DLL_CTRL */
726#define OMAP4430_DLL_OVERRIDE_SHIFT 0
727#define OMAP4430_DLL_OVERRIDE_WIDTH 0x1
728#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
729
730/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
731#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
732#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH 0x1
733#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
734
735/* Used by CM_SHADOW_FREQ_CONFIG1 */
736#define OMAP4430_DLL_RESET_SHIFT 3
737#define OMAP4430_DLL_RESET_WIDTH 0x1
738#define OMAP4430_DLL_RESET_MASK (1 << 3)
739
740/*
741 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
742 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
743 * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
744 */
745#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 66#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
746#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 67#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
747#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
748
749/* Used by CM_CLKDCOLDO_DPLL_USB */
750#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
751#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH 0x1
752#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
753
754/* Used by CM_CLKSEL_DPLL_CORE */
755#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
756#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
757#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
758
759/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
760#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
761#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH 0x5
762#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) 68#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
763
764/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
765#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
766#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH 0x1
767#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
768
769/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
770#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 69#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
771#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH 0x1
772#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
773
774/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
775#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT 10
776#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH 0x1
777#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) 70#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
778
779/*
780 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
781 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
782 */
783#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 71#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
784#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 72#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
785#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) 73#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
786
787/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
788#define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT 0
789#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH 0x7
790#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) 74#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
791
792/*
793 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
794 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
795 */
796#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
797#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH 0x1
798#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
799
800/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
801#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT 7
802#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH 0x1
803#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
804
805/*
806 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
807 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
808 */
809#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
810#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH 0x1
811#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) 75#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
812
813/* Used by CM_SHADOW_FREQ_CONFIG1 */
814#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
815#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH 0x3
816#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
817
818/* Used by CM_SHADOW_FREQ_CONFIG1 */
819#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
820#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH 0x5
821#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
822
823/* Used by CM_SHADOW_FREQ_CONFIG2 */
824#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
825#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH 0x5
826#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
827
828/*
829 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
830 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
831 * CM_CLKSEL_DPLL_UNIPRO
832 */
833#define OMAP4430_DPLL_DIV_SHIFT 0
834#define OMAP4430_DPLL_DIV_WIDTH 0x7
835#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) 76#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
836
837/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
838#define OMAP4430_DPLL_DIV_0_7_SHIFT 0
839#define OMAP4430_DPLL_DIV_0_7_WIDTH 0x8
840#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) 77#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
841
842/*
843 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
844 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
845 */
846#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
847#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH 0x1
848#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
849
850/* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
851#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT 3
852#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH 0x1
853#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
854
855/*
856 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
857 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
858 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
859 */
860#define OMAP4430_DPLL_EN_SHIFT 0
861#define OMAP4430_DPLL_EN_WIDTH 0x3
862#define OMAP4430_DPLL_EN_MASK (0x7 << 0) 78#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
863
864/*
865 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
866 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
867 * CM_CLKMODE_DPLL_UNIPRO
868 */
869#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
870#define OMAP4430_DPLL_LPMODE_EN_WIDTH 0x1
871#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) 79#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
872
873/*
874 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
875 * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
876 * CM_CLKSEL_DPLL_UNIPRO
877 */
878#define OMAP4430_DPLL_MULT_SHIFT 8
879#define OMAP4430_DPLL_MULT_WIDTH 0xb
880#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) 80#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
881
882/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
883#define OMAP4430_DPLL_MULT_USB_SHIFT 8
884#define OMAP4430_DPLL_MULT_USB_WIDTH 0xc
885#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) 81#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
886
887/*
888 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
889 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
890 * CM_CLKMODE_DPLL_UNIPRO
891 */
892#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
893#define OMAP4430_DPLL_REGM4XEN_WIDTH 0x1
894#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) 82#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
895
896/* Used by CM_CLKSEL_DPLL_USB */
897#define OMAP4430_DPLL_SD_DIV_SHIFT 24
898#define OMAP4430_DPLL_SD_DIV_WIDTH 0x8
899#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) 83#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
900
901/*
902 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
903 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
904 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
905 */
906#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
907#define OMAP4430_DPLL_SSC_ACK_WIDTH 0x1
908#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
909
910/*
911 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
912 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
913 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
914 */
915#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
916#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
917#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
918
919/*
920 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
921 * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
922 * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
923 */
924#define OMAP4430_DPLL_SSC_EN_SHIFT 12
925#define OMAP4430_DPLL_SSC_EN_WIDTH 0x1
926#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
927
928/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
929#define OMAP4430_DSS_DYNDEP_SHIFT 8
930#define OMAP4430_DSS_DYNDEP_WIDTH 0x1
931#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
932
933/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
934#define OMAP4430_DSS_STATDEP_SHIFT 8 84#define OMAP4430_DSS_STATDEP_SHIFT 8
935#define OMAP4430_DSS_STATDEP_WIDTH 0x1
936#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
937
938/* Used by CM_L3_2_DYNAMICDEP */
939#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
940#define OMAP4430_DUCATI_DYNDEP_WIDTH 0x1
941#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
942
943/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
944#define OMAP4430_DUCATI_STATDEP_SHIFT 0 85#define OMAP4430_DUCATI_STATDEP_SHIFT 0
945#define OMAP4430_DUCATI_STATDEP_WIDTH 0x1
946#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
947
948/* Used by CM_SHADOW_FREQ_CONFIG1 */
949#define OMAP4430_FREQ_UPDATE_SHIFT 0
950#define OMAP4430_FREQ_UPDATE_WIDTH 0x1
951#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
952
953/* Used by REVISION_CM1, REVISION_CM2 */
954#define OMAP4430_FUNC_SHIFT 16
955#define OMAP4430_FUNC_WIDTH 0xc
956#define OMAP4430_FUNC_MASK (0xfff << 16)
957
958/* Used by CM_L3_2_DYNAMICDEP */
959#define OMAP4430_GFX_DYNDEP_SHIFT 10
960#define OMAP4430_GFX_DYNDEP_WIDTH 0x1
961#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
962
963/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
964#define OMAP4430_GFX_STATDEP_SHIFT 10 86#define OMAP4430_GFX_STATDEP_SHIFT 10
965#define OMAP4430_GFX_STATDEP_WIDTH 0x1
966#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
967
968/* Used by CM_SHADOW_FREQ_CONFIG2 */
969#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
970#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH 0x1
971#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
972
973/*
974 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
975 * CM_DIV_M4_DPLL_PER
976 */
977#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
978#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH 0x5
979#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) 87#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
980
981/*
982 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
983 * CM_DIV_M4_DPLL_PER
984 */
985#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
986#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH 0x1
987#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
988
989/*
990 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
991 * CM_DIV_M4_DPLL_PER
992 */
993#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
994#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH 0x1
995#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
996
997/*
998 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
999 * CM_DIV_M4_DPLL_PER
1000 */
1001#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
1002#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH 0x1
1003#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
1004
1005/*
1006 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1007 * CM_DIV_M5_DPLL_PER
1008 */
1009#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
1010#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH 0x5
1011#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) 88#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
1012
1013/*
1014 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1015 * CM_DIV_M5_DPLL_PER
1016 */
1017#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
1018#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH 0x1
1019#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
1020
1021/*
1022 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1023 * CM_DIV_M5_DPLL_PER
1024 */
1025#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
1026#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH 0x1
1027#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
1028
1029/*
1030 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1031 * CM_DIV_M5_DPLL_PER
1032 */
1033#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
1034#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH 0x1
1035#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
1036
1037/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1038#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
1039#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH 0x5
1040#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) 89#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
1041
1042/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1043#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
1044#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH 0x1
1045#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
1046
1047/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1048#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
1049#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH 0x1
1050#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
1051
1052/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1053#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
1054#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH 0x1
1055#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
1056
1057/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1058#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
1059#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH 0x5
1060#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) 90#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
1061
1062/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1063#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
1064#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH 0x1
1065#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
1066
1067/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1068#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
1069#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH 0x1
1070#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
1071
1072/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1073#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
1074#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH 0x1
1075#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
1076
1077/*
1078 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1079 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1080 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1081 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1082 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
1083 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1084 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
1085 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
1086 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1087 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1088 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1089 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1090 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1091 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1092 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1093 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
1094 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
1095 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1096 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1097 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1098 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1099 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1100 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1101 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1102 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1103 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1104 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1105 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
1106 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
1107 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
1108 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1109 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1110 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1111 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1112 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1113 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
1114 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
1115 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1116 */
1117#define OMAP4430_IDLEST_SHIFT 16 91#define OMAP4430_IDLEST_SHIFT 16
1118#define OMAP4430_IDLEST_WIDTH 0x2
1119#define OMAP4430_IDLEST_MASK (0x3 << 16) 92#define OMAP4430_IDLEST_MASK (0x3 << 16)
1120
1121/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
1122#define OMAP4430_ISS_DYNDEP_SHIFT 9
1123#define OMAP4430_ISS_DYNDEP_WIDTH 0x1
1124#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
1125
1126/*
1127 * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
1128 * CM_TESLA_STATICDEP
1129 */
1130#define OMAP4430_ISS_STATDEP_SHIFT 9
1131#define OMAP4430_ISS_STATDEP_WIDTH 0x1
1132#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
1133
1134/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
1135#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
1136#define OMAP4430_IVAHD_DYNDEP_WIDTH 0x1
1137#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
1138
1139/*
1140 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1141 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
1142 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1143 */
1144#define OMAP4430_IVAHD_STATDEP_SHIFT 2 93#define OMAP4430_IVAHD_STATDEP_SHIFT 2
1145#define OMAP4430_IVAHD_STATDEP_WIDTH 0x1
1146#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
1147
1148/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1149#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
1150#define OMAP4430_L3INIT_DYNDEP_WIDTH 0x1
1151#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
1152
1153/*
1154 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
1155 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1156 */
1157#define OMAP4430_L3INIT_STATDEP_SHIFT 7 94#define OMAP4430_L3INIT_STATDEP_SHIFT 7
1158#define OMAP4430_L3INIT_STATDEP_WIDTH 0x1
1159#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
1160
1161/*
1162 * Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
1163 * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1164 */
1165#define OMAP4430_L3_1_DYNDEP_SHIFT 5
1166#define OMAP4430_L3_1_DYNDEP_WIDTH 0x1
1167#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
1168
1169/*
1170 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1171 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1172 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1173 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1174 */
1175#define OMAP4430_L3_1_STATDEP_SHIFT 5 95#define OMAP4430_L3_1_STATDEP_SHIFT 5
1176#define OMAP4430_L3_1_STATDEP_WIDTH 0x1
1177#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
1178
1179/*
1180 * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
1181 * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
1182 * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1183 * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
1184 */
1185#define OMAP4430_L3_2_DYNDEP_SHIFT 6
1186#define OMAP4430_L3_2_DYNDEP_WIDTH 0x1
1187#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
1188
1189/*
1190 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1191 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1192 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1193 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1194 */
1195#define OMAP4430_L3_2_STATDEP_SHIFT 6 96#define OMAP4430_L3_2_STATDEP_SHIFT 6
1196#define OMAP4430_L3_2_STATDEP_WIDTH 0x1
1197#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
1198
1199/* Used by CM_L3_1_DYNAMICDEP */
1200#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
1201#define OMAP4430_L4CFG_DYNDEP_WIDTH 0x1
1202#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
1203
1204/*
1205 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1206 * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1207 */
1208#define OMAP4430_L4CFG_STATDEP_SHIFT 12 97#define OMAP4430_L4CFG_STATDEP_SHIFT 12
1209#define OMAP4430_L4CFG_STATDEP_WIDTH 0x1
1210#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
1211
1212/* Used by CM_L3_2_DYNAMICDEP */
1213#define OMAP4430_L4PER_DYNDEP_SHIFT 13
1214#define OMAP4430_L4PER_DYNDEP_WIDTH 0x1
1215#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
1216
1217/*
1218 * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
1219 * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1220 */
1221#define OMAP4430_L4PER_STATDEP_SHIFT 13 98#define OMAP4430_L4PER_STATDEP_SHIFT 13
1222#define OMAP4430_L4PER_STATDEP_WIDTH 0x1
1223#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
1224
1225/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1226#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
1227#define OMAP4430_L4SEC_DYNDEP_WIDTH 0x1
1228#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
1229
1230/*
1231 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1232 * CM_SDMA_STATICDEP
1233 */
1234#define OMAP4430_L4SEC_STATDEP_SHIFT 14 99#define OMAP4430_L4SEC_STATDEP_SHIFT 14
1235#define OMAP4430_L4SEC_STATDEP_WIDTH 0x1
1236#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
1237
1238/* Used by CM_L4CFG_DYNAMICDEP */
1239#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
1240#define OMAP4430_L4WKUP_DYNDEP_WIDTH 0x1
1241#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
1242
1243/*
1244 * Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
1245 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1246 */
1247#define OMAP4430_L4WKUP_STATDEP_SHIFT 15 100#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
1248#define OMAP4430_L4WKUP_STATDEP_WIDTH 0x1
1249#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
1250
1251/*
1252 * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1253 * CM_MPU_DYNAMICDEP
1254 */
1255#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
1256#define OMAP4430_MEMIF_DYNDEP_WIDTH 0x1
1257#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
1258
1259/*
1260 * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
1261 * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
1262 * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
1263 * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
1264 */
1265#define OMAP4430_MEMIF_STATDEP_SHIFT 4 101#define OMAP4430_MEMIF_STATDEP_SHIFT 4
1266#define OMAP4430_MEMIF_STATDEP_WIDTH 0x1
1267#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
1268
1269/*
1270 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1271 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1272 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1273 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1274 */
1275#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
1276#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH 0x3
1277#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1278
1279/*
1280 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1281 * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
1282 * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
1283 * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
1284 */
1285#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
1286#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH 0x7
1287#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1288
1289/*
1290 * Used by CM1_ABE_AESS_CLKCTRL, CM1_ABE_DMIC_CLKCTRL, CM1_ABE_L4ABE_CLKCTRL,
1291 * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
1292 * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
1293 * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
1294 * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
1295 * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1296 * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
1297 * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
1298 * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1299 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1300 * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1301 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
1302 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1303 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
1304 * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1305 * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
1306 * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
1307 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1308 * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
1309 * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
1310 * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
1311 * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
1312 * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
1313 * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
1314 * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
1315 * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1316 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
1317 * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
1318 * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
1319 * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
1320 * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1321 * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
1322 * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
1323 * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
1324 * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
1325 * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
1326 * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
1327 * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
1328 */
1329#define OMAP4430_MODULEMODE_SHIFT 0 102#define OMAP4430_MODULEMODE_SHIFT 0
1330#define OMAP4430_MODULEMODE_WIDTH 0x2
1331#define OMAP4430_MODULEMODE_MASK (0x3 << 0) 103#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
1332
1333/* Used by CM_L4CFG_DYNAMICDEP */
1334#define OMAP4460_MPU_DYNDEP_SHIFT 19
1335#define OMAP4460_MPU_DYNDEP_WIDTH 0x1
1336#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
1337
1338/* Used by CM_DSS_DSS_CLKCTRL */
1339#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 104#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1340#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1341#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1342
1343/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1344#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 105#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
1345#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH 0x1
1346#define OMAP4430_OPTFCLKEN_BGAP_32K_MASK (1 << 8)
1347
1348/* Used by CM_ALWON_USBPHY_CLKCTRL */
1349#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 106#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
1350#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH 0x1
1351#define OMAP4430_OPTFCLKEN_CLK32K_MASK (1 << 8)
1352
1353/* Used by CM_CAM_ISS_CLKCTRL */
1354#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 107#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
1355#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1356#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1357
1358/*
1359 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1360 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1361 * CM_WKUP_GPIO1_CLKCTRL
1362 */
1363#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 108#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
1364#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH 0x1
1365#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
1366
1367/* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
1368#define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT 8
1369#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1370#define OMAP4430_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1371
1372/* Used by CM_DSS_DSS_CLKCTRL */
1373#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 109#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
1374#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH 0x1
1375#define OMAP4430_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1376
1377/* Used by CM_WKUP_USIM_CLKCTRL */
1378#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 110#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
1379#define OMAP4430_OPTFCLKEN_FCLK_WIDTH 0x1
1380#define OMAP4430_OPTFCLKEN_FCLK_MASK (1 << 8)
1381
1382/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1383#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 111#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
1384#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH 0x1
1385#define OMAP4430_OPTFCLKEN_FCLK0_MASK (1 << 8)
1386
1387/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1388#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 112#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
1389#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH 0x1
1390#define OMAP4430_OPTFCLKEN_FCLK1_MASK (1 << 9)
1391
1392/* Used by CM1_ABE_SLIMBUS_CLKCTRL */
1393#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 113#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
1394#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH 0x1
1395#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
1396
1397/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1398#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 114#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
1399#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH 0x1
1400#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
1401
1402/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1403#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 115#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1404#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1405#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1406
1407/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1408#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 116#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1409#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1410#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1411
1412/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1413#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 117#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1414#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1415#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1416
1417/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1418#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 118#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1419#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1420#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1421
1422/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1423#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 119#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
1424#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH 0x1
1425#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK (1 << 8)
1426
1427/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1428#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 120#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
1429#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH 0x1
1430#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK (1 << 9)
1431
1432/* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
1433#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 121#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
1434#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH 0x1
1435#define OMAP4430_OPTFCLKEN_PHY_48M_MASK (1 << 8)
1436
1437/* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
1438#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 122#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
1439#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1440#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 10)
1441
1442/* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
1443#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 123#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
1444#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH 0x1
1445#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK (1 << 11)
1446
1447/* Used by CM_DSS_DSS_CLKCTRL */
1448#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 124#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
1449#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1450#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1451
1452/* Used by CM_WKUP_BANDGAP_CLKCTRL */
1453#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 125#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
1454#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH 0x1
1455#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
1456
1457/* Used by CM_DSS_DSS_CLKCTRL */
1458#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 126#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
1459#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH 0x1
1460#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
1461
1462/* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
1463#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
1464#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH 0x1
1465#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
1466
1467/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1468#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 127#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1469#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1470#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1471
1472/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1473#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 128#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1474#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1475#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1476
1477/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
1478#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 129#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1479#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1480#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1481
1482/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1483#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 130#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1484#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1485#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1486
1487/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1488#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 131#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1489#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1490#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1491
1492/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
1493#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 132#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1494#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1495#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1496
1497/* Used by CM_L3INIT_USB_OTG_CLKCTRL */
1498#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 133#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
1499#define OMAP4430_OPTFCLKEN_XCLK_WIDTH 0x1
1500#define OMAP4430_OPTFCLKEN_XCLK_MASK (1 << 8)
1501
1502/* Used by CM_EMU_OVERRIDE_DPLL_CORE */
1503#define OMAP4430_OVERRIDE_ENABLE_SHIFT 19
1504#define OMAP4430_OVERRIDE_ENABLE_WIDTH 0x1
1505#define OMAP4430_OVERRIDE_ENABLE_MASK (1 << 19)
1506
1507/* Used by CM_CLKSEL_ABE */
1508#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 134#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
1509#define OMAP4430_PAD_CLKS_GATE_WIDTH 0x1
1510#define OMAP4430_PAD_CLKS_GATE_MASK (1 << 8)
1511
1512/* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
1513#define OMAP4430_PERF_CURRENT_SHIFT 0
1514#define OMAP4430_PERF_CURRENT_WIDTH 0x8
1515#define OMAP4430_PERF_CURRENT_MASK (0xff << 0)
1516
1517/*
1518 * Used by CM_CORE_DVFS_PERF1, CM_CORE_DVFS_PERF2, CM_CORE_DVFS_PERF3,
1519 * CM_CORE_DVFS_PERF4, CM_IVA_DVFS_PERF_ABE, CM_IVA_DVFS_PERF_IVAHD,
1520 * CM_IVA_DVFS_PERF_TESLA
1521 */
1522#define OMAP4430_PERF_REQ_SHIFT 0
1523#define OMAP4430_PERF_REQ_WIDTH 0x8
1524#define OMAP4430_PERF_REQ_MASK (0xff << 0)
1525
1526/* Used by CM_RESTORE_ST */
1527#define OMAP4430_PHASE1_COMPLETED_SHIFT 0
1528#define OMAP4430_PHASE1_COMPLETED_WIDTH 0x1
1529#define OMAP4430_PHASE1_COMPLETED_MASK (1 << 0)
1530
1531/* Used by CM_RESTORE_ST */
1532#define OMAP4430_PHASE2A_COMPLETED_SHIFT 1
1533#define OMAP4430_PHASE2A_COMPLETED_WIDTH 0x1
1534#define OMAP4430_PHASE2A_COMPLETED_MASK (1 << 1)
1535
1536/* Used by CM_RESTORE_ST */
1537#define OMAP4430_PHASE2B_COMPLETED_SHIFT 2
1538#define OMAP4430_PHASE2B_COMPLETED_WIDTH 0x1
1539#define OMAP4430_PHASE2B_COMPLETED_MASK (1 << 2)
1540
1541/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1542#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 135#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
1543#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 136#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
1544#define OMAP4430_PMD_STM_MUX_CTRL_MASK (0x3 << 20)
1545
1546/* Used by CM_EMU_DEBUGSS_CLKCTRL */
1547#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 137#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
1548#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 138#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
1549#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
1550
1551/* Used by CM_DYN_DEP_PRESCAL */
1552#define OMAP4430_PRESCAL_SHIFT 0
1553#define OMAP4430_PRESCAL_WIDTH 0x6
1554#define OMAP4430_PRESCAL_MASK (0x3f << 0)
1555
1556/* Used by REVISION_CM1, REVISION_CM2 */
1557#define OMAP4430_R_RTL_SHIFT 11
1558#define OMAP4430_R_RTL_WIDTH 0x5
1559#define OMAP4430_R_RTL_MASK (0x1f << 11)
1560
1561/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
1562#define OMAP4430_SAR_MODE_SHIFT 4
1563#define OMAP4430_SAR_MODE_WIDTH 0x1
1564#define OMAP4430_SAR_MODE_MASK (1 << 4)
1565
1566/* Used by CM_SCALE_FCLK */
1567#define OMAP4430_SCALE_FCLK_SHIFT 0 139#define OMAP4430_SCALE_FCLK_SHIFT 0
1568#define OMAP4430_SCALE_FCLK_WIDTH 0x1 140#define OMAP4430_SCALE_FCLK_WIDTH 0x1
1569#define OMAP4430_SCALE_FCLK_MASK (1 << 0)
1570
1571/* Used by REVISION_CM1, REVISION_CM2 */
1572#define OMAP4430_SCHEME_SHIFT 30
1573#define OMAP4430_SCHEME_WIDTH 0x2
1574#define OMAP4430_SCHEME_MASK (0x3 << 30)
1575
1576/* Used by CM_L4CFG_DYNAMICDEP */
1577#define OMAP4430_SDMA_DYNDEP_SHIFT 11
1578#define OMAP4430_SDMA_DYNDEP_WIDTH 0x1
1579#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
1580
1581/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1582#define OMAP4430_SDMA_STATDEP_SHIFT 11
1583#define OMAP4430_SDMA_STATDEP_WIDTH 0x1
1584#define OMAP4430_SDMA_STATDEP_MASK (1 << 11)
1585
1586/* Used by CM_CLKSEL_ABE */
1587#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 141#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
1588#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH 0x1
1589#define OMAP4430_SLIMBUS_CLK_GATE_MASK (1 << 10)
1590
1591/*
1592 * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
1593 * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
1594 * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
1595 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
1596 * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
1597 * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1598 * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
1599 */
1600#define OMAP4430_STBYST_SHIFT 18
1601#define OMAP4430_STBYST_WIDTH 0x1
1602#define OMAP4430_STBYST_MASK (1 << 18)
1603
1604/*
1605 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1606 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1607 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1608 */
1609#define OMAP4430_ST_DPLL_CLK_SHIFT 0
1610#define OMAP4430_ST_DPLL_CLK_WIDTH 0x1
1611#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) 142#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
1612
1613/* Used by CM_CLKDCOLDO_DPLL_USB */
1614#define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT 9
1615#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1616#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1617
1618/*
1619 * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
1620 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
1621 */
1622#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
1623#define OMAP4430_ST_DPLL_CLKOUT_WIDTH 0x1
1624#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
1625
1626/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
1627#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
1628#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH 0x1
1629#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
1630
1631/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
1632#define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT 11
1633#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH 0x1
1634#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
1635
1636/*
1637 * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
1638 * CM_DIV_M4_DPLL_PER
1639 */
1640#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
1641#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH 0x1
1642#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
1643
1644/*
1645 * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
1646 * CM_DIV_M5_DPLL_PER
1647 */
1648#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
1649#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH 0x1
1650#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
1651
1652/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
1653#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
1654#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH 0x1
1655#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
1656
1657/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
1658#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
1659#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH 0x1
1660#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
1661
1662/*
1663 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDRPHY,
1664 * CM_IDLEST_DPLL_IVA, CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER,
1665 * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
1666 */
1667#define OMAP4430_ST_MN_BYPASS_SHIFT 8
1668#define OMAP4430_ST_MN_BYPASS_WIDTH 0x1
1669#define OMAP4430_ST_MN_BYPASS_MASK (1 << 8)
1670
1671/* Used by CM_SYS_CLKSEL */
1672#define OMAP4430_SYS_CLKSEL_SHIFT 0 143#define OMAP4430_SYS_CLKSEL_SHIFT 0
1673#define OMAP4430_SYS_CLKSEL_WIDTH 0x3 144#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
1674#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
1675
1676/* Used by CM_L4CFG_DYNAMICDEP */
1677#define OMAP4430_TESLA_DYNDEP_SHIFT 1
1678#define OMAP4430_TESLA_DYNDEP_WIDTH 0x1
1679#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
1680
1681/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
1682#define OMAP4430_TESLA_STATDEP_SHIFT 1 145#define OMAP4430_TESLA_STATDEP_SHIFT 1
1683#define OMAP4430_TESLA_STATDEP_WIDTH 0x1
1684#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
1685
1686/*
1687 * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1688 * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1689 * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
1690 */
1691#define OMAP4430_WINDOWSIZE_SHIFT 24
1692#define OMAP4430_WINDOWSIZE_WIDTH 0x4
1693#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
1694
1695/* Used by REVISION_CM1, REVISION_CM2 */
1696#define OMAP4430_X_MAJOR_SHIFT 8
1697#define OMAP4430_X_MAJOR_WIDTH 0x3
1698#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
1699
1700/* Used by REVISION_CM1, REVISION_CM2 */
1701#define OMAP4430_Y_MINOR_SHIFT 0
1702#define OMAP4430_Y_MINOR_WIDTH 0x6
1703#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
1704#endif 146#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-54xx.h b/arch/arm/mach-omap2/cm-regbits-54xx.h
index e83b8e352b6e..896ae9fc4cfb 100644
--- a/arch/arm/mach-omap2/cm-regbits-54xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-54xx.h
@@ -21,1717 +21,84 @@
21#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 21#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H 22#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_54XX_H
23 23
24/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_MPU_DYNAMICDEP */
25#define OMAP54XX_ABE_DYNDEP_SHIFT 3
26#define OMAP54XX_ABE_DYNDEP_WIDTH 0x1
27#define OMAP54XX_ABE_DYNDEP_MASK (1 << 3)
28
29/*
30 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
31 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
32 */
33#define OMAP54XX_ABE_STATDEP_SHIFT 3 24#define OMAP54XX_ABE_STATDEP_SHIFT 3
34#define OMAP54XX_ABE_STATDEP_WIDTH 0x1
35#define OMAP54XX_ABE_STATDEP_MASK (1 << 3)
36
37/*
38 * Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_IVA,
39 * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO1,
40 * CM_AUTOIDLE_DPLL_UNIPRO2, CM_AUTOIDLE_DPLL_USB
41 */
42#define OMAP54XX_AUTO_DPLL_MODE_SHIFT 0
43#define OMAP54XX_AUTO_DPLL_MODE_WIDTH 0x3
44#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0) 25#define OMAP54XX_AUTO_DPLL_MODE_MASK (0x7 << 0)
45
46/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
47#define OMAP54XX_C2C_DYNDEP_SHIFT 18
48#define OMAP54XX_C2C_DYNDEP_WIDTH 0x1
49#define OMAP54XX_C2C_DYNDEP_MASK (1 << 18)
50
51/* Used by CM_MPU_STATICDEP */
52#define OMAP54XX_C2C_STATDEP_SHIFT 18
53#define OMAP54XX_C2C_STATDEP_WIDTH 0x1
54#define OMAP54XX_C2C_STATDEP_MASK (1 << 18)
55
56/* Used by CM_IPU_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
57#define OMAP54XX_CAM_DYNDEP_SHIFT 9
58#define OMAP54XX_CAM_DYNDEP_WIDTH 0x1
59#define OMAP54XX_CAM_DYNDEP_MASK (1 << 9)
60
61/*
62 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
63 * CM_MPU_STATICDEP
64 */
65#define OMAP54XX_CAM_STATDEP_SHIFT 9
66#define OMAP54XX_CAM_STATDEP_WIDTH 0x1
67#define OMAP54XX_CAM_STATDEP_MASK (1 << 9)
68
69/* Used by CM_ABE_CLKSTCTRL */
70#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_SHIFT 13
71#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_WIDTH 0x1
72#define OMAP54XX_CLKACTIVITY_ABE_24M_GFCLK_MASK (1 << 13)
73
74/* Used by CM_ABE_CLKSTCTRL */
75#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_SHIFT 12
76#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_WIDTH 0x1
77#define OMAP54XX_CLKACTIVITY_ABE_32K_CLK_MASK (1 << 12)
78
79/* Used by CM_ABE_CLKSTCTRL */
80#define OMAP54XX_CLKACTIVITY_ABE_GICLK_SHIFT 9
81#define OMAP54XX_CLKACTIVITY_ABE_GICLK_WIDTH 0x1
82#define OMAP54XX_CLKACTIVITY_ABE_GICLK_MASK (1 << 9)
83
84/* Used by CM_WKUPAON_CLKSTCTRL */
85#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_SHIFT 9
86#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_WIDTH 0x1
87#define OMAP54XX_CLKACTIVITY_ABE_LP_CLK_MASK (1 << 9)
88
89/* Used by CM_ABE_CLKSTCTRL */
90#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_SHIFT 11
91#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_WIDTH 0x1
92#define OMAP54XX_CLKACTIVITY_ABE_SYS_CLK_MASK (1 << 11)
93
94/* Used by CM_ABE_CLKSTCTRL */
95#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
96#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_WIDTH 0x1
97#define OMAP54XX_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
98
99/* Used by CM_DSS_CLKSTCTRL */
100#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_SHIFT 13
101#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_WIDTH 0x1
102#define OMAP54XX_CLKACTIVITY_BB2D_GFCLK_MASK (1 << 13)
103
104/* Used by CM_C2C_CLKSTCTRL */
105#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_SHIFT 9
106#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_WIDTH 0x1
107#define OMAP54XX_CLKACTIVITY_C2C_GFCLK_MASK (1 << 9)
108
109/* Used by CM_C2C_CLKSTCTRL */
110#define OMAP54XX_CLKACTIVITY_C2C_GICLK_SHIFT 10
111#define OMAP54XX_CLKACTIVITY_C2C_GICLK_WIDTH 0x1
112#define OMAP54XX_CLKACTIVITY_C2C_GICLK_MASK (1 << 10)
113
114/* Used by CM_C2C_CLKSTCTRL */
115#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_SHIFT 8
116#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_WIDTH 0x1
117#define OMAP54XX_CLKACTIVITY_C2C_L4_GICLK_MASK (1 << 8)
118
119/* Used by CM_CAM_CLKSTCTRL */
120#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_SHIFT 11
121#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_WIDTH 0x1
122#define OMAP54XX_CLKACTIVITY_CAM_BOOST_GCLK_MASK (1 << 11)
123
124/* Used by CM_CAM_CLKSTCTRL */
125#define OMAP54XX_CLKACTIVITY_CAM_GCLK_SHIFT 8
126#define OMAP54XX_CLKACTIVITY_CAM_GCLK_WIDTH 0x1
127#define OMAP54XX_CLKACTIVITY_CAM_GCLK_MASK (1 << 8)
128
129/* Used by CM_CAM_CLKSTCTRL */
130#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_SHIFT 12
131#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_WIDTH 0x1
132#define OMAP54XX_CLKACTIVITY_CAM_L3_GICLK_MASK (1 << 12)
133
134/* Used by CM_COREAON_CLKSTCTRL */
135#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_SHIFT 12
136#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_WIDTH 0x1
137#define OMAP54XX_CLKACTIVITY_COREAON_32K_GFCLK_MASK (1 << 12)
138
139/* Used by CM_COREAON_CLKSTCTRL */
140#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_SHIFT 14
141#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_WIDTH 0x1
142#define OMAP54XX_CLKACTIVITY_COREAON_IO_SRCOMP_GFCLK_MASK (1 << 14)
143
144/* Used by CM_COREAON_CLKSTCTRL */
145#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_SHIFT 8
146#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_WIDTH 0x1
147#define OMAP54XX_CLKACTIVITY_COREAON_L4_GICLK_MASK (1 << 8)
148
149/* Used by CM_CAM_CLKSTCTRL */
150#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_SHIFT 9
151#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_WIDTH 0x1
152#define OMAP54XX_CLKACTIVITY_CSI_PHY_GFCLK_MASK (1 << 9)
153
154/* Used by CM_CUSTEFUSE_CLKSTCTRL */
155#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_SHIFT 8
156#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_WIDTH 0x1
157#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_L4_GICLK_MASK (1 << 8)
158
159/* Used by CM_CUSTEFUSE_CLKSTCTRL */
160#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_SHIFT 9
161#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_WIDTH 0x1
162#define OMAP54XX_CLKACTIVITY_CUSTEFUSE_SYS_GFCLK_MASK (1 << 9)
163
164/* Used by CM_EMIF_CLKSTCTRL */
165#define OMAP54XX_CLKACTIVITY_DLL_GCLK_SHIFT 9
166#define OMAP54XX_CLKACTIVITY_DLL_GCLK_WIDTH 0x1
167#define OMAP54XX_CLKACTIVITY_DLL_GCLK_MASK (1 << 9)
168
169/* Used by CM_DMA_CLKSTCTRL */
170#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_SHIFT 8
171#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_WIDTH 0x1
172#define OMAP54XX_CLKACTIVITY_DMA_L3_GICLK_MASK (1 << 8)
173
174/* Used by CM_DSP_CLKSTCTRL */
175#define OMAP54XX_CLKACTIVITY_DSP_GCLK_SHIFT 8
176#define OMAP54XX_CLKACTIVITY_DSP_GCLK_WIDTH 0x1
177#define OMAP54XX_CLKACTIVITY_DSP_GCLK_MASK (1 << 8)
178
179/* Used by CM_DSS_CLKSTCTRL */
180#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_SHIFT 9
181#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_WIDTH 0x1
182#define OMAP54XX_CLKACTIVITY_DSS_GFCLK_MASK (1 << 9)
183
184/* Used by CM_DSS_CLKSTCTRL */
185#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_SHIFT 8
186#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_WIDTH 0x1
187#define OMAP54XX_CLKACTIVITY_DSS_L3_GICLK_MASK (1 << 8)
188
189/* Used by CM_DSS_CLKSTCTRL */
190#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_SHIFT 10
191#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_WIDTH 0x1
192#define OMAP54XX_CLKACTIVITY_DSS_SYS_GFCLK_MASK (1 << 10)
193
194/* Used by CM_EMIF_CLKSTCTRL */
195#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_SHIFT 8
196#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_WIDTH 0x1
197#define OMAP54XX_CLKACTIVITY_EMIF_L3_GICLK_MASK (1 << 8)
198
199/* Used by CM_EMIF_CLKSTCTRL */
200#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_SHIFT 11
201#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_WIDTH 0x1
202#define OMAP54XX_CLKACTIVITY_EMIF_LL_GCLK_MASK (1 << 11)
203
204/* Used by CM_EMIF_CLKSTCTRL */
205#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_SHIFT 10
206#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_WIDTH 0x1
207#define OMAP54XX_CLKACTIVITY_EMIF_PHY_GCLK_MASK (1 << 10)
208
209/* Used by CM_EMU_CLKSTCTRL */
210#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_SHIFT 8
211#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_WIDTH 0x1
212#define OMAP54XX_CLKACTIVITY_EMU_SYS_GCLK_MASK (1 << 8)
213
214/* Used by CM_CAM_CLKSTCTRL */
215#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_SHIFT 10
216#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_WIDTH 0x1
217#define OMAP54XX_CLKACTIVITY_FDIF_GCLK_MASK (1 << 10)
218
219/* Used by CM_ABE_CLKSTCTRL */
220#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT 10
221#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH 0x1
222#define OMAP54XX_CLKACTIVITY_FUNC_24M_GFCLK_MASK (1 << 10)
223
224/* Used by CM_GPU_CLKSTCTRL */
225#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_SHIFT 9
226#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_WIDTH 0x1
227#define OMAP54XX_CLKACTIVITY_GPU_CORE_GCLK_MASK (1 << 9)
228
229/* Used by CM_GPU_CLKSTCTRL */
230#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_SHIFT 10
231#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_WIDTH 0x1
232#define OMAP54XX_CLKACTIVITY_GPU_HYD_GCLK_MASK (1 << 10)
233
234/* Used by CM_GPU_CLKSTCTRL */
235#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_SHIFT 8
236#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_WIDTH 0x1
237#define OMAP54XX_CLKACTIVITY_GPU_SYS_GCLK_MASK (1 << 8)
238
239/* Used by CM_DSS_CLKSTCTRL */
240#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_SHIFT 12
241#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_WIDTH 0x1
242#define OMAP54XX_CLKACTIVITY_HDMI_CEC_GFCLK_MASK (1 << 12)
243
244/* Used by CM_DSS_CLKSTCTRL */
245#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_SHIFT 11
246#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_WIDTH 0x1
247#define OMAP54XX_CLKACTIVITY_HDMI_PHY_GFCLK_MASK (1 << 11)
248
249/* Used by CM_L3INIT_CLKSTCTRL */
250#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
251#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH 0x1
252#define OMAP54XX_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
253
254/* Used by CM_L3INIT_CLKSTCTRL */
255#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
256#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH 0x1
257#define OMAP54XX_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
258
259/* Used by CM_L3INIT_CLKSTCTRL */
260#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
261#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH 0x1
262#define OMAP54XX_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
263
264/* Used by CM_L3INIT_CLKSTCTRL */
265#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
266#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH 0x1
267#define OMAP54XX_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
268
269/* Used by CM_L3INIT_CLKSTCTRL */
270#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_SHIFT 6
271#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_WIDTH 0x1
272#define OMAP54XX_CLKACTIVITY_HSIC_P3_480M_GFCLK_MASK (1 << 6)
273
274/* Used by CM_L3INIT_CLKSTCTRL */
275#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_SHIFT 7
276#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_WIDTH 0x1
277#define OMAP54XX_CLKACTIVITY_HSIC_P3_GFCLK_MASK (1 << 7)
278
279/* Used by CM_L3INIT_CLKSTCTRL */
280#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_SHIFT 16
281#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_WIDTH 0x1
282#define OMAP54XX_CLKACTIVITY_HSI_GFCLK_MASK (1 << 16)
283
284/* Used by CM_IPU_CLKSTCTRL */
285#define OMAP54XX_CLKACTIVITY_IPU_GCLK_SHIFT 8
286#define OMAP54XX_CLKACTIVITY_IPU_GCLK_WIDTH 0x1
287#define OMAP54XX_CLKACTIVITY_IPU_GCLK_MASK (1 << 8)
288
289/* Used by CM_IVA_CLKSTCTRL */
290#define OMAP54XX_CLKACTIVITY_IVA_GCLK_SHIFT 8
291#define OMAP54XX_CLKACTIVITY_IVA_GCLK_WIDTH 0x1
292#define OMAP54XX_CLKACTIVITY_IVA_GCLK_MASK (1 << 8)
293
294/* Used by CM_L3INIT_CLKSTCTRL */
295#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_SHIFT 12
296#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_WIDTH 0x1
297#define OMAP54XX_CLKACTIVITY_L3INIT_48M_GFCLK_MASK (1 << 12)
298
299/* Used by CM_L3INIT_CLKSTCTRL */
300#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_SHIFT 28
301#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_WIDTH 0x1
302#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P1_GFCLK_MASK (1 << 28)
303
304/* Used by CM_L3INIT_CLKSTCTRL */
305#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_SHIFT 29
306#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_WIDTH 0x1
307#define OMAP54XX_CLKACTIVITY_L3INIT_60M_P2_GFCLK_MASK (1 << 29)
308
309/* Used by CM_L3INIT_CLKSTCTRL */
310#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_SHIFT 8
311#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_WIDTH 0x1
312#define OMAP54XX_CLKACTIVITY_L3INIT_L3_GICLK_MASK (1 << 8)
313
314/* Used by CM_L3INIT_CLKSTCTRL */
315#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_SHIFT 9
316#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_WIDTH 0x1
317#define OMAP54XX_CLKACTIVITY_L3INIT_L4_GICLK_MASK (1 << 9)
318
319/* Used by CM_L3INIT_CLKSTCTRL */
320#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_SHIFT 11
321#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_WIDTH 0x1
322#define OMAP54XX_CLKACTIVITY_L3INIT_USB_OTG_SS_LFPS_TX_GFCLK_MASK (1 << 11)
323
324/* Used by CM_L3INSTR_CLKSTCTRL */
325#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_SHIFT 9
326#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_WIDTH 0x1
327#define OMAP54XX_CLKACTIVITY_L3INSTR_DLL_AGING_GCLK_MASK (1 << 9)
328
329/* Used by CM_L3INSTR_CLKSTCTRL */
330#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_SHIFT 8
331#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_WIDTH 0x1
332#define OMAP54XX_CLKACTIVITY_L3INSTR_L3_GICLK_MASK (1 << 8)
333
334/* Used by CM_L3INSTR_CLKSTCTRL */
335#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_SHIFT 10
336#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_WIDTH 0x1
337#define OMAP54XX_CLKACTIVITY_L3INSTR_TS_GCLK_MASK (1 << 10)
338
339/* Used by CM_L3MAIN1_CLKSTCTRL */
340#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_SHIFT 8
341#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_WIDTH 0x1
342#define OMAP54XX_CLKACTIVITY_L3MAIN1_L3_GICLK_MASK (1 << 8)
343
344/* Used by CM_L3MAIN2_CLKSTCTRL */
345#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_SHIFT 8
346#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_WIDTH 0x1
347#define OMAP54XX_CLKACTIVITY_L3MAIN2_L3_GICLK_MASK (1 << 8)
348
349/* Used by CM_L4CFG_CLKSTCTRL */
350#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_SHIFT 8
351#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_WIDTH 0x1
352#define OMAP54XX_CLKACTIVITY_L4CFG_L4_GICLK_MASK (1 << 8)
353
354/* Used by CM_L4PER_CLKSTCTRL */
355#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_SHIFT 8
356#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_WIDTH 0x1
357#define OMAP54XX_CLKACTIVITY_L4PER_L4_GICLK_MASK (1 << 8)
358
359/* Used by CM_L4SEC_CLKSTCTRL */
360#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_SHIFT 8
361#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_WIDTH 0x1
362#define OMAP54XX_CLKACTIVITY_L4SEC_L3_GICLK_MASK (1 << 8)
363
364/* Used by CM_L4SEC_CLKSTCTRL */
365#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_SHIFT 9
366#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_WIDTH 0x1
367#define OMAP54XX_CLKACTIVITY_L4SEC_L4_GICLK_MASK (1 << 9)
368
369/* Used by CM_MIPIEXT_CLKSTCTRL */
370#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_SHIFT 8
371#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_WIDTH 0x1
372#define OMAP54XX_CLKACTIVITY_MIPIEXT_L3_GICLK_MASK (1 << 8)
373
374/* Used by CM_MIPIEXT_CLKSTCTRL */
375#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_SHIFT 11
376#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_WIDTH 0x1
377#define OMAP54XX_CLKACTIVITY_MIPIEXT_PHY_REF_GFCLK_MASK (1 << 11)
378
379/* Used by CM_L3INIT_CLKSTCTRL */
380#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_SHIFT 2
381#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_WIDTH 0x1
382#define OMAP54XX_CLKACTIVITY_MMC1_32K_GFCLK_MASK (1 << 2)
383
384/* Used by CM_L3INIT_CLKSTCTRL */
385#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_SHIFT 17
386#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_WIDTH 0x1
387#define OMAP54XX_CLKACTIVITY_MMC1_GFCLK_MASK (1 << 17)
388
389/* Used by CM_L3INIT_CLKSTCTRL */
390#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_SHIFT 18
391#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_WIDTH 0x1
392#define OMAP54XX_CLKACTIVITY_MMC2_GFCLK_MASK (1 << 18)
393
394/* Used by CM_MPU_CLKSTCTRL */
395#define OMAP54XX_CLKACTIVITY_MPU_GCLK_SHIFT 8
396#define OMAP54XX_CLKACTIVITY_MPU_GCLK_WIDTH 0x1
397#define OMAP54XX_CLKACTIVITY_MPU_GCLK_MASK (1 << 8)
398
399/* Used by CM_ABE_CLKSTCTRL */
400#define OMAP54XX_CLKACTIVITY_PAD_CLKS_SHIFT 14
401#define OMAP54XX_CLKACTIVITY_PAD_CLKS_WIDTH 0x1
402#define OMAP54XX_CLKACTIVITY_PAD_CLKS_MASK (1 << 14)
403
404/* Used by CM_ABE_CLKSTCTRL */
405#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_SHIFT 15
406#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_WIDTH 0x1
407#define OMAP54XX_CLKACTIVITY_PAD_SLIMBUS1_CLK_MASK (1 << 15)
408
409/* Used by CM_L3INIT_CLKSTCTRL */
410#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_SHIFT 3
411#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_WIDTH 0x1
412#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP1_MASK (1 << 3)
413
414/* Used by CM_L3INIT_CLKSTCTRL */
415#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_SHIFT 4
416#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_WIDTH 0x1
417#define OMAP54XX_CLKACTIVITY_PAD_XCLK60MHSP2_MASK (1 << 4)
418
419/* Used by CM_L4PER_CLKSTCTRL */
420#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_SHIFT 15
421#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_WIDTH 0x1
422#define OMAP54XX_CLKACTIVITY_PER_12M_GFCLK_MASK (1 << 15)
423
424/* Used by CM_L4PER_CLKSTCTRL */
425#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
426#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_WIDTH 0x1
427#define OMAP54XX_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
428
429/* Used by CM_L4PER_CLKSTCTRL */
430#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
431#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_WIDTH 0x1
432#define OMAP54XX_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
433
434/* Used by CM_L4PER_CLKSTCTRL */
435#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
436#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_WIDTH 0x1
437#define OMAP54XX_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
438
439/* Used by CM_L3INIT_CLKSTCTRL */
440#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_SHIFT 19
441#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_WIDTH 0x1
442#define OMAP54XX_CLKACTIVITY_SATA_REF_GFCLK_MASK (1 << 19)
443
444/* Used by CM_COREAON_CLKSTCTRL */
445#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_SHIFT 11
446#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_WIDTH 0x1
447#define OMAP54XX_CLKACTIVITY_SR_CORE_SYS_GFCLK_MASK (1 << 11)
448
449/* Used by CM_COREAON_CLKSTCTRL */
450#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_SHIFT 10
451#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_WIDTH 0x1
452#define OMAP54XX_CLKACTIVITY_SR_MM_SYS_GFCLK_MASK (1 << 10)
453
454/* Used by CM_COREAON_CLKSTCTRL */
455#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_SHIFT 9
456#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_WIDTH 0x1
457#define OMAP54XX_CLKACTIVITY_SR_MPU_SYS_GFCLK_MASK (1 << 9)
458
459/* Used by CM_WKUPAON_CLKSTCTRL */
460#define OMAP54XX_CLKACTIVITY_SYS_CLK_SHIFT 8
461#define OMAP54XX_CLKACTIVITY_SYS_CLK_WIDTH 0x1
462#define OMAP54XX_CLKACTIVITY_SYS_CLK_MASK (1 << 8)
463
464/* Used by CM_WKUPAON_CLKSTCTRL */
465#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_SHIFT 15
466#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_WIDTH 0x1
467#define OMAP54XX_CLKACTIVITY_SYS_CLK_ALL_MASK (1 << 15)
468
469/* Used by CM_WKUPAON_CLKSTCTRL */
470#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_SHIFT 14
471#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_WIDTH 0x1
472#define OMAP54XX_CLKACTIVITY_SYS_CLK_FUNC_MASK (1 << 14)
473
474/* Used by CM_L4PER_CLKSTCTRL */
475#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_SHIFT 9
476#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_WIDTH 0x1
477#define OMAP54XX_CLKACTIVITY_TIMER10_GFCLK_MASK (1 << 9)
478
479/* Used by CM_L4PER_CLKSTCTRL */
480#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_SHIFT 10
481#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_WIDTH 0x1
482#define OMAP54XX_CLKACTIVITY_TIMER11_GFCLK_MASK (1 << 10)
483
484/* Used by CM_L4PER_CLKSTCTRL */
485#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_SHIFT 11
486#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_WIDTH 0x1
487#define OMAP54XX_CLKACTIVITY_TIMER2_GFCLK_MASK (1 << 11)
488
489/* Used by CM_L4PER_CLKSTCTRL */
490#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_SHIFT 12
491#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_WIDTH 0x1
492#define OMAP54XX_CLKACTIVITY_TIMER3_GFCLK_MASK (1 << 12)
493
494/* Used by CM_L4PER_CLKSTCTRL */
495#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_SHIFT 13
496#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_WIDTH 0x1
497#define OMAP54XX_CLKACTIVITY_TIMER4_GFCLK_MASK (1 << 13)
498
499/* Used by CM_L4PER_CLKSTCTRL */
500#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_SHIFT 14
501#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_WIDTH 0x1
502#define OMAP54XX_CLKACTIVITY_TIMER9_GFCLK_MASK (1 << 14)
503
504/* Used by CM_L3INIT_CLKSTCTRL */
505#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
506#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH 0x1
507#define OMAP54XX_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
508
509/* Used by CM_L3INIT_CLKSTCTRL */
510#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
511#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH 0x1
512#define OMAP54XX_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
513
514/* Used by CM_L3INIT_CLKSTCTRL */
515#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
516#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH 0x1
517#define OMAP54XX_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
518
519/* Used by CM_MIPIEXT_CLKSTCTRL */
520#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_SHIFT 10
521#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_WIDTH 0x1
522#define OMAP54XX_CLKACTIVITY_UNIPRO1_DPLL_CLK_MASK (1 << 10)
523
524/* Used by CM_MIPIEXT_CLKSTCTRL */
525#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_SHIFT 13
526#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_WIDTH 0x1
527#define OMAP54XX_CLKACTIVITY_UNIPRO1_PHY_GFCLK_MASK (1 << 13)
528
529/* Used by CM_MIPIEXT_CLKSTCTRL */
530#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_SHIFT 12
531#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_WIDTH 0x1
532#define OMAP54XX_CLKACTIVITY_UNIPRO1_TXPHY_LS_GFCLK_MASK (1 << 12)
533
534/* Used by CM_L3INIT_CLKSTCTRL */
535#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_SHIFT 10
536#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_WIDTH 0x1
537#define OMAP54XX_CLKACTIVITY_UNIPRO2_DPLL_CLK_MASK (1 << 10)
538
539/* Used by CM_L3INIT_CLKSTCTRL */
540#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_SHIFT 13
541#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_WIDTH 0x1
542#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_GFCLK_MASK (1 << 13)
543
544/* Used by CM_L3INIT_CLKSTCTRL */
545#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_SHIFT 5
546#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_WIDTH 0x1
547#define OMAP54XX_CLKACTIVITY_UNIPRO2_PHY_REF_GFCLK_MASK (1 << 5)
548
549/* Used by CM_L3INIT_CLKSTCTRL */
550#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
551#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_WIDTH 0x1
552#define OMAP54XX_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
553
554/* Used by CM_L3INIT_CLKSTCTRL */
555#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
556#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH 0x1
557#define OMAP54XX_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
558
559/* Used by CM_L3INIT_CLKSTCTRL */
560#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_SHIFT 31
561#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_WIDTH 0x1
562#define OMAP54XX_CLKACTIVITY_USB_OTG_SS_REF_CLK_MASK (1 << 31)
563
564/* Used by CM_L3INIT_CLKSTCTRL */
565#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
566#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH 0x1
567#define OMAP54XX_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
568
569/* Used by CM_L3INIT_CLKSTCTRL */
570#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
571#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH 0x1
572#define OMAP54XX_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
573
574/* Used by CM_WKUPAON_CLKSTCTRL */
575#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_SHIFT 11
576#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_WIDTH 0x1
577#define OMAP54XX_CLKACTIVITY_WKUPAON_32K_GFCLK_MASK (1 << 11)
578
579/* Used by CM_WKUPAON_CLKSTCTRL */
580#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_SHIFT 12
581#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_WIDTH 0x1
582#define OMAP54XX_CLKACTIVITY_WKUPAON_GICLK_MASK (1 << 12)
583
584/* Used by CM_WKUPAON_CLKSTCTRL */
585#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_SHIFT 13
586#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_WIDTH 0x1
587#define OMAP54XX_CLKACTIVITY_WKUPAON_IO_SRCOMP_GFCLK_MASK (1 << 13)
588
589/* Used by CM_COREAON_IO_SRCOMP_CLKCTRL, CM_WKUPAON_IO_SRCOMP_CLKCTRL */
590#define OMAP54XX_CLKEN_SRCOMP_FCLK_SHIFT 8
591#define OMAP54XX_CLKEN_SRCOMP_FCLK_WIDTH 0x1
592#define OMAP54XX_CLKEN_SRCOMP_FCLK_MASK (1 << 8)
593
594/*
595 * Used by CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
596 * CM_ABE_TIMER8_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
597 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
598 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL
599 */
600#define OMAP54XX_CLKSEL_SHIFT 24 26#define OMAP54XX_CLKSEL_SHIFT 24
601#define OMAP54XX_CLKSEL_WIDTH 0x1 27#define OMAP54XX_CLKSEL_WIDTH 0x1
602#define OMAP54XX_CLKSEL_MASK (1 << 24)
603
604/*
605 * Renamed from CLKSEL Used by CM_CLKSEL_ABE_DSS_SYS, CM_CLKSEL_ABE_PLL_REF,
606 * CM_CLKSEL_USB_60MHZ, CM_CLKSEL_WKUPAON
607 */
608#define OMAP54XX_CLKSEL_0_0_SHIFT 0 28#define OMAP54XX_CLKSEL_0_0_SHIFT 0
609#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1 29#define OMAP54XX_CLKSEL_0_0_WIDTH 0x1
610#define OMAP54XX_CLKSEL_0_0_MASK (1 << 0)
611
612/* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
613#define OMAP54XX_CLKSEL_0_1_SHIFT 0
614#define OMAP54XX_CLKSEL_0_1_WIDTH 0x2
615#define OMAP54XX_CLKSEL_0_1_MASK (0x3 << 0)
616
617/* Renamed from CLKSEL Used by CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL */
618#define OMAP54XX_CLKSEL_24_25_SHIFT 24
619#define OMAP54XX_CLKSEL_24_25_WIDTH 0x2
620#define OMAP54XX_CLKSEL_24_25_MASK (0x3 << 24)
621
622/* Used by CM_MPU_MPU_CLKCTRL */
623#define OMAP54XX_CLKSEL_ABE_DIV_MODE_SHIFT 26
624#define OMAP54XX_CLKSEL_ABE_DIV_MODE_WIDTH 0x1
625#define OMAP54XX_CLKSEL_ABE_DIV_MODE_MASK (1 << 26)
626
627/* Used by CM_ABE_AESS_CLKCTRL */
628#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24 30#define OMAP54XX_CLKSEL_AESS_FCLK_SHIFT 24
629#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1 31#define OMAP54XX_CLKSEL_AESS_FCLK_WIDTH 0x1
630#define OMAP54XX_CLKSEL_AESS_FCLK_MASK (1 << 24)
631
632/* Used by CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL */
633#define OMAP54XX_CLKSEL_DIV_SHIFT 25 32#define OMAP54XX_CLKSEL_DIV_SHIFT 25
634#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1 33#define OMAP54XX_CLKSEL_DIV_WIDTH 0x1
635#define OMAP54XX_CLKSEL_DIV_MASK (1 << 25)
636
637/* Used by CM_MPU_MPU_CLKCTRL */
638#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_SHIFT 24
639#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_WIDTH 0x2
640#define OMAP54XX_CLKSEL_EMIF_DIV_MODE_MASK (0x3 << 24)
641
642/* Used by CM_CAM_FDIF_CLKCTRL */
643#define OMAP54XX_CLKSEL_FCLK_SHIFT 24 34#define OMAP54XX_CLKSEL_FCLK_SHIFT 24
644#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1 35#define OMAP54XX_CLKSEL_FCLK_WIDTH 0x1
645#define OMAP54XX_CLKSEL_FCLK_MASK (1 << 24)
646
647/* Used by CM_GPU_GPU_CLKCTRL */
648#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24 36#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_SHIFT 24
649#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1 37#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_WIDTH 0x1
650#define OMAP54XX_CLKSEL_GPU_CORE_GCLK_MASK (1 << 24)
651
652/* Used by CM_GPU_GPU_CLKCTRL */
653#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25 38#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_SHIFT 25
654#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1 39#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_WIDTH 0x1
655#define OMAP54XX_CLKSEL_GPU_HYD_GCLK_MASK (1 << 25)
656
657/* Used by CM_GPU_GPU_CLKCTRL */
658#define OMAP54XX_CLKSEL_GPU_SYS_CLK_SHIFT 26
659#define OMAP54XX_CLKSEL_GPU_SYS_CLK_WIDTH 0x1
660#define OMAP54XX_CLKSEL_GPU_SYS_CLK_MASK (1 << 26)
661
662/*
663 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
664 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
665 */
666#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26 40#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_SHIFT 26
667#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2 41#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_WIDTH 0x2
668#define OMAP54XX_CLKSEL_INTERNAL_SOURCE_MASK (0x3 << 26)
669
670/* Used by CM_CLKSEL_CORE */
671#define OMAP54XX_CLKSEL_L3_SHIFT 4
672#define OMAP54XX_CLKSEL_L3_WIDTH 0x1
673#define OMAP54XX_CLKSEL_L3_MASK (1 << 4)
674
675/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
676#define OMAP54XX_CLKSEL_L3_1_1_SHIFT 1
677#define OMAP54XX_CLKSEL_L3_1_1_WIDTH 0x1
678#define OMAP54XX_CLKSEL_L3_1_1_MASK (1 << 1)
679
680/* Used by CM_CLKSEL_CORE */
681#define OMAP54XX_CLKSEL_L4_SHIFT 8
682#define OMAP54XX_CLKSEL_L4_WIDTH 0x1
683#define OMAP54XX_CLKSEL_L4_MASK (1 << 8)
684
685/* Used by CM_EMIF_EMIF1_CLKCTRL */
686#define OMAP54XX_CLKSEL_LL_SHIFT 24
687#define OMAP54XX_CLKSEL_LL_WIDTH 0x1
688#define OMAP54XX_CLKSEL_LL_MASK (1 << 24)
689
690/* Used by CM_CLKSEL_ABE */
691#define OMAP54XX_CLKSEL_OPP_SHIFT 0 42#define OMAP54XX_CLKSEL_OPP_SHIFT 0
692#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2 43#define OMAP54XX_CLKSEL_OPP_WIDTH 0x2
693#define OMAP54XX_CLKSEL_OPP_MASK (0x3 << 0)
694
695/* Renamed from CLKSEL_OPP Used by CM_L3INIT_UNIPRO2_CLKCTRL */
696#define OMAP54XX_CLKSEL_OPP_24_24_SHIFT 24
697#define OMAP54XX_CLKSEL_OPP_24_24_WIDTH 0x1
698#define OMAP54XX_CLKSEL_OPP_24_24_MASK (1 << 24)
699
700/*
701 * Used by CM_ABE_DMIC_CLKCTRL, CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL,
702 * CM_ABE_MCBSP2_CLKCTRL, CM_ABE_MCBSP3_CLKCTRL
703 */
704#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24 44#define OMAP54XX_CLKSEL_SOURCE_SHIFT 24
705#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2 45#define OMAP54XX_CLKSEL_SOURCE_WIDTH 0x2
706#define OMAP54XX_CLKSEL_SOURCE_MASK (0x3 << 24)
707
708/*
709 * Renamed from CLKSEL_SOURCE Used by CM_L3INIT_MMC1_CLKCTRL,
710 * CM_L3INIT_MMC2_CLKCTRL
711 */
712#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24 46#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_SHIFT 24
713#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1 47#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_WIDTH 0x1
714#define OMAP54XX_CLKSEL_SOURCE_L3INIT_MMC1_MASK (1 << 24)
715
716/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
717#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24 48#define OMAP54XX_CLKSEL_UTMI_P1_SHIFT 24
718#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1 49#define OMAP54XX_CLKSEL_UTMI_P1_WIDTH 0x1
719#define OMAP54XX_CLKSEL_UTMI_P1_MASK (1 << 24)
720
721/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
722#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25 50#define OMAP54XX_CLKSEL_UTMI_P2_SHIFT 25
723#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1 51#define OMAP54XX_CLKSEL_UTMI_P2_WIDTH 0x1
724#define OMAP54XX_CLKSEL_UTMI_P2_MASK (1 << 25)
725
726/*
727 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
728 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
729 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
730 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
731 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE, CM_DIV_M2_DPLL_ABE,
732 * CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER,
733 * CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2, CM_DIV_M2_DPLL_USB,
734 * CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
735 */
736#define OMAP54XX_CLKST_SHIFT 9
737#define OMAP54XX_CLKST_WIDTH 0x1
738#define OMAP54XX_CLKST_MASK (1 << 9)
739
740/*
741 * Used by CM_ABE_CLKSTCTRL, CM_C2C_CLKSTCTRL, CM_CAM_CLKSTCTRL,
742 * CM_COREAON_CLKSTCTRL, CM_CUSTEFUSE_CLKSTCTRL, CM_DMA_CLKSTCTRL,
743 * CM_DSP_CLKSTCTRL, CM_DSS_CLKSTCTRL, CM_EMIF_CLKSTCTRL, CM_EMU_CLKSTCTRL,
744 * CM_GPU_CLKSTCTRL, CM_IPU_CLKSTCTRL, CM_IVA_CLKSTCTRL, CM_L3INIT_CLKSTCTRL,
745 * CM_L3INSTR_CLKSTCTRL, CM_L3MAIN1_CLKSTCTRL, CM_L3MAIN2_CLKSTCTRL,
746 * CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL, CM_L4SEC_CLKSTCTRL,
747 * CM_MIPIEXT_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_WKUPAON_CLKSTCTRL
748 */
749#define OMAP54XX_CLKTRCTRL_SHIFT 0
750#define OMAP54XX_CLKTRCTRL_WIDTH 0x2
751#define OMAP54XX_CLKTRCTRL_MASK (0x3 << 0)
752
753/* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER */
754#define OMAP54XX_CLKX2ST_SHIFT 11
755#define OMAP54XX_CLKX2ST_WIDTH 0x1
756#define OMAP54XX_CLKX2ST_MASK (1 << 11)
757
758/* Used by CM_L4CFG_DYNAMICDEP */
759#define OMAP54XX_COREAON_DYNDEP_SHIFT 16
760#define OMAP54XX_COREAON_DYNDEP_WIDTH 0x1
761#define OMAP54XX_COREAON_DYNDEP_MASK (1 << 16)
762
763/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
764#define OMAP54XX_COREAON_STATDEP_SHIFT 16
765#define OMAP54XX_COREAON_STATDEP_WIDTH 0x1
766#define OMAP54XX_COREAON_STATDEP_MASK (1 << 16)
767
768/* Used by CM_L4CFG_DYNAMICDEP */
769#define OMAP54XX_CUSTEFUSE_DYNDEP_SHIFT 17
770#define OMAP54XX_CUSTEFUSE_DYNDEP_WIDTH 0x1
771#define OMAP54XX_CUSTEFUSE_DYNDEP_MASK (1 << 17)
772
773/* Used by CM_DSP_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
774#define OMAP54XX_CUSTEFUSE_STATDEP_SHIFT 17
775#define OMAP54XX_CUSTEFUSE_STATDEP_WIDTH 0x1
776#define OMAP54XX_CUSTEFUSE_STATDEP_MASK (1 << 17)
777
778/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
779#define OMAP54XX_CUSTOM_SHIFT 6
780#define OMAP54XX_CUSTOM_WIDTH 0x2
781#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
782
783/*
784 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
785 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
786 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
787 */
788#define OMAP54XX_DCC_EN_SHIFT 22
789#define OMAP54XX_DCC_EN_WIDTH 0x1
790#define OMAP54XX_DCC_EN_MASK (1 << 22)
791
792/*
793 * Used by CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS,
794 * CM_CORE_AON_DEBUG_DSS_FD_TRANS, CM_CORE_AON_DEBUG_EMIF_FD_TRANS,
795 * CM_CORE_AON_DEBUG_L4SEC_FD_TRANS
796 */
797#define OMAP54XX_CM_DEBUG_OUT_SHIFT 0
798#define OMAP54XX_CM_DEBUG_OUT_WIDTH 0xd
799#define OMAP54XX_CM_DEBUG_OUT_MASK (0x1fff << 0)
800
801/*
802 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS,
803 * CM_CORE_AON_DEBUG_L3INIT_FD_TRANS, CM_CORE_AON_DEBUG_L4PER_FD_TRANS
804 */
805#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
806#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
807#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
808
809/*
810 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_C2C_FD_TRANS,
811 * CM_CORE_AON_DEBUG_COREAON_FD_TRANS, CM_CORE_AON_DEBUG_L4CFG_FD_TRANS
812 */
813#define OMAP54XX_DEBUG_OUT_0_8_SHIFT 0
814#define OMAP54XX_DEBUG_OUT_0_8_WIDTH 0x9
815#define OMAP54XX_DEBUG_OUT_0_8_MASK (0x1ff << 0)
816
817/*
818 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS,
819 * CM_CORE_AON_DEBUG_DMA_FD_TRANS, CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS
820 */
821#define OMAP54XX_DEBUG_OUT_0_4_SHIFT 0
822#define OMAP54XX_DEBUG_OUT_0_4_WIDTH 0x5
823#define OMAP54XX_DEBUG_OUT_0_4_MASK (0x1f << 0)
824
825/*
826 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_DSP_FD_TRANS,
827 * CM_CORE_AON_DEBUG_IPU_FD_TRANS, CM_CORE_AON_DEBUG_MPU_FD_TRANS
828 */
829#define OMAP54XX_DEBUG_OUT_0_5_SHIFT 0
830#define OMAP54XX_DEBUG_OUT_0_5_WIDTH 0x6
831#define OMAP54XX_DEBUG_OUT_0_5_MASK (0x3f << 0)
832
833/*
834 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_CAM_FD_TRANS,
835 * CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS
836 */
837#define OMAP54XX_DEBUG_OUT_0_10_SHIFT 0
838#define OMAP54XX_DEBUG_OUT_0_10_WIDTH 0xb
839#define OMAP54XX_DEBUG_OUT_0_10_MASK (0x7ff << 0)
840
841/*
842 * Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_IVA_FD_TRANS,
843 * CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS
844 */
845#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
846#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
847#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
848
849/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_ABE_FD_TRANS2 */
850#define OMAP54XX_DEBUG_OUT_0_19_SHIFT 0
851#define OMAP54XX_DEBUG_OUT_0_19_WIDTH 0x14
852#define OMAP54XX_DEBUG_OUT_0_19_MASK (0xfffff << 0)
853
854/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_GPU_FD_TRANS */
855#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
856#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
857#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
858
859/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2 */
860#define OMAP54XX_DEBUG_OUT_0_26_SHIFT 0
861#define OMAP54XX_DEBUG_OUT_0_26_WIDTH 0x1b
862#define OMAP54XX_DEBUG_OUT_0_26_MASK (0x7ffffff << 0)
863
864/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS */
865#define OMAP54XX_DEBUG_OUT_0_13_SHIFT 0
866#define OMAP54XX_DEBUG_OUT_0_13_WIDTH 0xe
867#define OMAP54XX_DEBUG_OUT_0_13_MASK (0x3fff << 0)
868
869/* Renamed from DEBUG_OUT Used by CM_CORE_AON_DEBUG_L4PER_FD_TRANS2 */
870#define OMAP54XX_DEBUG_OUT_0_21_SHIFT 0
871#define OMAP54XX_DEBUG_OUT_0_21_WIDTH 0x16
872#define OMAP54XX_DEBUG_OUT_0_21_MASK (0x3fffff << 0)
873
874/*
875 * Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
876 * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
877 * CM_SSC_DELTAMSTEP_DPLL_PER
878 */
879#define OMAP54XX_DELTAMSTEP_SHIFT 0
880#define OMAP54XX_DELTAMSTEP_WIDTH 0x14
881#define OMAP54XX_DELTAMSTEP_MASK (0xfffff << 0)
882
883/*
884 * Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_UNIPRO1,
885 * CM_SSC_DELTAMSTEP_DPLL_UNIPRO2, CM_SSC_DELTAMSTEP_DPLL_USB
886 */
887#define OMAP54XX_DELTAMSTEP_0_20_SHIFT 0
888#define OMAP54XX_DELTAMSTEP_0_20_WIDTH 0x15
889#define OMAP54XX_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
890
891/*
892 * Used by CM_DIV_H11_DPLL_CORE, CM_DIV_H11_DPLL_IVA, CM_DIV_H11_DPLL_PER,
893 * CM_DIV_H12_DPLL_CORE, CM_DIV_H12_DPLL_IVA, CM_DIV_H12_DPLL_PER,
894 * CM_DIV_H13_DPLL_CORE, CM_DIV_H13_DPLL_PER, CM_DIV_H14_DPLL_CORE,
895 * CM_DIV_H14_DPLL_PER, CM_DIV_H21_DPLL_CORE, CM_DIV_H22_DPLL_CORE,
896 * CM_DIV_H23_DPLL_CORE, CM_DIV_H24_DPLL_CORE
897 */
898#define OMAP54XX_DIVHS_SHIFT 0
899#define OMAP54XX_DIVHS_WIDTH 0x6
900#define OMAP54XX_DIVHS_MASK (0x3f << 0) 52#define OMAP54XX_DIVHS_MASK (0x3f << 0)
901
902/*
903 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
904 * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M3_DPLL_ABE,
905 * CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER
906 */
907#define OMAP54XX_DIVHS_0_4_SHIFT 0
908#define OMAP54XX_DIVHS_0_4_WIDTH 0x5
909#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0) 53#define OMAP54XX_DIVHS_0_4_MASK (0x1f << 0)
910
911/*
912 * Renamed from DIVHS Used by CM_DIV_M2_DPLL_UNIPRO1, CM_DIV_M2_DPLL_UNIPRO2,
913 * CM_DIV_M2_DPLL_USB
914 */
915#define OMAP54XX_DIVHS_0_6_SHIFT 0
916#define OMAP54XX_DIVHS_0_6_WIDTH 0x7
917#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0) 54#define OMAP54XX_DIVHS_0_6_MASK (0x7f << 0)
918
919/* Used by CM_DLL_CTRL */
920#define OMAP54XX_DLL_OVERRIDE_SHIFT 0
921#define OMAP54XX_DLL_OVERRIDE_WIDTH 0x1
922#define OMAP54XX_DLL_OVERRIDE_MASK (1 << 0)
923
924/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
925#define OMAP54XX_DLL_OVERRIDE_2_2_SHIFT 2
926#define OMAP54XX_DLL_OVERRIDE_2_2_WIDTH 0x1
927#define OMAP54XX_DLL_OVERRIDE_2_2_MASK (1 << 2)
928
929/* Used by CM_SHADOW_FREQ_CONFIG1 */
930#define OMAP54XX_DLL_RESET_SHIFT 3
931#define OMAP54XX_DLL_RESET_WIDTH 0x1
932#define OMAP54XX_DLL_RESET_MASK (1 << 3)
933
934/*
935 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
936 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO1,
937 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
938 */
939#define OMAP54XX_DPLL_BYP_CLKSEL_SHIFT 23
940#define OMAP54XX_DPLL_BYP_CLKSEL_WIDTH 0x1
941#define OMAP54XX_DPLL_BYP_CLKSEL_MASK (1 << 23)
942
943/* Used by CM_CLKSEL_DPLL_CORE */
944#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
945#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_WIDTH 0x1
946#define OMAP54XX_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
947
948/* Used by CM_SHADOW_FREQ_CONFIG1 */
949#define OMAP54XX_DPLL_CORE_DPLL_EN_SHIFT 8
950#define OMAP54XX_DPLL_CORE_DPLL_EN_WIDTH 0x3
951#define OMAP54XX_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
952
953/* Used by CM_SHADOW_FREQ_CONFIG2 */
954#define OMAP54XX_DPLL_CORE_H12_DIV_SHIFT 2
955#define OMAP54XX_DPLL_CORE_H12_DIV_WIDTH 0x6
956#define OMAP54XX_DPLL_CORE_H12_DIV_MASK (0x3f << 2)
957
958/* Used by CM_SHADOW_FREQ_CONFIG1 */
959#define OMAP54XX_DPLL_CORE_M2_DIV_SHIFT 11
960#define OMAP54XX_DPLL_CORE_M2_DIV_WIDTH 0x5
961#define OMAP54XX_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
962
963/*
964 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
965 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
966 */
967#define OMAP54XX_DPLL_DIV_SHIFT 0
968#define OMAP54XX_DPLL_DIV_WIDTH 0x7
969#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0) 55#define OMAP54XX_DPLL_DIV_MASK (0x7f << 0)
970
971/*
972 * Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_UNIPRO1,
973 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
974 */
975#define OMAP54XX_DPLL_DIV_0_7_SHIFT 0
976#define OMAP54XX_DPLL_DIV_0_7_WIDTH 0x8
977#define OMAP54XX_DPLL_DIV_0_7_MASK (0xff << 0)
978
979/*
980 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
981 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
982 */
983#define OMAP54XX_DPLL_DRIFTGUARD_EN_SHIFT 8
984#define OMAP54XX_DPLL_DRIFTGUARD_EN_WIDTH 0x1
985#define OMAP54XX_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
986
987/*
988 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
989 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
990 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
991 */
992#define OMAP54XX_DPLL_EN_SHIFT 0
993#define OMAP54XX_DPLL_EN_WIDTH 0x3
994#define OMAP54XX_DPLL_EN_MASK (0x7 << 0) 56#define OMAP54XX_DPLL_EN_MASK (0x7 << 0)
995
996/*
997 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
998 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
999 */
1000#define OMAP54XX_DPLL_LPMODE_EN_SHIFT 10
1001#define OMAP54XX_DPLL_LPMODE_EN_WIDTH 0x1
1002#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10) 57#define OMAP54XX_DPLL_LPMODE_EN_MASK (1 << 10)
1003
1004/*
1005 * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_IVA,
1006 * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER
1007 */
1008#define OMAP54XX_DPLL_MULT_SHIFT 8
1009#define OMAP54XX_DPLL_MULT_WIDTH 0xb
1010#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8) 58#define OMAP54XX_DPLL_MULT_MASK (0x7ff << 8)
1011
1012/*
1013 * Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_UNIPRO1,
1014 * CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB
1015 */
1016#define OMAP54XX_DPLL_MULT_UNIPRO1_SHIFT 8
1017#define OMAP54XX_DPLL_MULT_UNIPRO1_WIDTH 0xc
1018#define OMAP54XX_DPLL_MULT_UNIPRO1_MASK (0xfff << 8)
1019
1020/*
1021 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1022 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
1023 */
1024#define OMAP54XX_DPLL_REGM4XEN_SHIFT 11
1025#define OMAP54XX_DPLL_REGM4XEN_WIDTH 0x1
1026#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11) 59#define OMAP54XX_DPLL_REGM4XEN_MASK (1 << 11)
1027
1028/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1029#define OMAP54XX_DPLL_SD_DIV_SHIFT 24
1030#define OMAP54XX_DPLL_SD_DIV_WIDTH 0x8
1031#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24) 60#define OMAP54XX_DPLL_SD_DIV_MASK (0xff << 24)
1032
1033/* Used by CM_CLKSEL_DPLL_UNIPRO1, CM_CLKSEL_DPLL_UNIPRO2, CM_CLKSEL_DPLL_USB */
1034#define OMAP54XX_DPLL_SELFREQDCO_SHIFT 21
1035#define OMAP54XX_DPLL_SELFREQDCO_WIDTH 0x1
1036#define OMAP54XX_DPLL_SELFREQDCO_MASK (1 << 21)
1037
1038/*
1039 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1040 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1041 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1042 */
1043#define OMAP54XX_DPLL_SSC_ACK_SHIFT 13
1044#define OMAP54XX_DPLL_SSC_ACK_WIDTH 0x1
1045#define OMAP54XX_DPLL_SSC_ACK_MASK (1 << 13)
1046
1047/*
1048 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1049 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1050 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1051 */
1052#define OMAP54XX_DPLL_SSC_DOWNSPREAD_SHIFT 14
1053#define OMAP54XX_DPLL_SSC_DOWNSPREAD_WIDTH 0x1
1054#define OMAP54XX_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
1055
1056/*
1057 * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_IVA,
1058 * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO1,
1059 * CM_CLKMODE_DPLL_UNIPRO2, CM_CLKMODE_DPLL_USB
1060 */
1061#define OMAP54XX_DPLL_SSC_EN_SHIFT 12
1062#define OMAP54XX_DPLL_SSC_EN_WIDTH 0x1
1063#define OMAP54XX_DPLL_SSC_EN_MASK (1 << 12)
1064
1065/* Used by CM_L4CFG_DYNAMICDEP */
1066#define OMAP54XX_DSP_DYNDEP_SHIFT 1
1067#define OMAP54XX_DSP_DYNDEP_WIDTH 0x1
1068#define OMAP54XX_DSP_DYNDEP_MASK (1 << 1)
1069
1070/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1071#define OMAP54XX_DSP_STATDEP_SHIFT 1 61#define OMAP54XX_DSP_STATDEP_SHIFT 1
1072#define OMAP54XX_DSP_STATDEP_WIDTH 0x1
1073#define OMAP54XX_DSP_STATDEP_MASK (1 << 1)
1074
1075/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1076#define OMAP54XX_DSS_DYNDEP_SHIFT 8
1077#define OMAP54XX_DSS_DYNDEP_WIDTH 0x1
1078#define OMAP54XX_DSS_DYNDEP_MASK (1 << 8)
1079
1080/* Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1081#define OMAP54XX_DSS_STATDEP_SHIFT 8 62#define OMAP54XX_DSS_STATDEP_SHIFT 8
1082#define OMAP54XX_DSS_STATDEP_WIDTH 0x1
1083#define OMAP54XX_DSS_STATDEP_MASK (1 << 8)
1084
1085/*
1086 * Used by CM_C2C_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
1087 * CM_MIPIEXT_DYNAMICDEP, CM_MPU_DYNAMICDEP
1088 */
1089#define OMAP54XX_EMIF_DYNDEP_SHIFT 4
1090#define OMAP54XX_EMIF_DYNDEP_WIDTH 0x1
1091#define OMAP54XX_EMIF_DYNDEP_MASK (1 << 4)
1092
1093/*
1094 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1095 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1096 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1097 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1098 */
1099#define OMAP54XX_EMIF_STATDEP_SHIFT 4 63#define OMAP54XX_EMIF_STATDEP_SHIFT 4
1100#define OMAP54XX_EMIF_STATDEP_WIDTH 0x1
1101#define OMAP54XX_EMIF_STATDEP_MASK (1 << 4)
1102
1103/* Used by CM_SHADOW_FREQ_CONFIG1 */
1104#define OMAP54XX_FREQ_UPDATE_SHIFT 0
1105#define OMAP54XX_FREQ_UPDATE_WIDTH 0x1
1106#define OMAP54XX_FREQ_UPDATE_MASK (1 << 0)
1107
1108/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1109#define OMAP54XX_FUNC_SHIFT 16
1110#define OMAP54XX_FUNC_WIDTH 0xc
1111#define OMAP54XX_FUNC_MASK (0xfff << 16)
1112
1113/* Used by CM_SHADOW_FREQ_CONFIG2 */
1114#define OMAP54XX_GPMC_FREQ_UPDATE_SHIFT 0
1115#define OMAP54XX_GPMC_FREQ_UPDATE_WIDTH 0x1
1116#define OMAP54XX_GPMC_FREQ_UPDATE_MASK (1 << 0)
1117
1118/* Used by CM_L3MAIN2_DYNAMICDEP */
1119#define OMAP54XX_GPU_DYNDEP_SHIFT 10
1120#define OMAP54XX_GPU_DYNDEP_WIDTH 0x1
1121#define OMAP54XX_GPU_DYNDEP_MASK (1 << 10)
1122
1123/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1124#define OMAP54XX_GPU_STATDEP_SHIFT 10 64#define OMAP54XX_GPU_STATDEP_SHIFT 10
1125#define OMAP54XX_GPU_STATDEP_WIDTH 0x1
1126#define OMAP54XX_GPU_STATDEP_MASK (1 << 10)
1127
1128/*
1129 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1130 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1131 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1132 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1133 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1134 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1135 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1136 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1137 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1138 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1139 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1140 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1141 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1142 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1143 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1144 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1145 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1146 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1147 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1148 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1149 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1150 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1151 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1152 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1153 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1154 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1155 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1156 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1157 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1158 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1159 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1160 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1161 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1162 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1163 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1164 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1165 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1166 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1167 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1168 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1169 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1170 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1171 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1172 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1173 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1174 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1175 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1176 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1177 */
1178#define OMAP54XX_IDLEST_SHIFT 16
1179#define OMAP54XX_IDLEST_WIDTH 0x2
1180#define OMAP54XX_IDLEST_MASK (0x3 << 16)
1181
1182/* Used by CM_L3MAIN2_DYNAMICDEP */
1183#define OMAP54XX_IPU_DYNDEP_SHIFT 0
1184#define OMAP54XX_IPU_DYNDEP_WIDTH 0x1
1185#define OMAP54XX_IPU_DYNDEP_MASK (1 << 0)
1186
1187/* Used by CM_DMA_STATICDEP, CM_MPU_STATICDEP */
1188#define OMAP54XX_IPU_STATDEP_SHIFT 0 65#define OMAP54XX_IPU_STATDEP_SHIFT 0
1189#define OMAP54XX_IPU_STATDEP_WIDTH 0x1
1190#define OMAP54XX_IPU_STATDEP_MASK (1 << 0)
1191
1192/* Used by CM_DSP_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP */
1193#define OMAP54XX_IVA_DYNDEP_SHIFT 2
1194#define OMAP54XX_IVA_DYNDEP_WIDTH 0x1
1195#define OMAP54XX_IVA_DYNDEP_MASK (1 << 2)
1196
1197/*
1198 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1199 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1200 * CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1201 */
1202#define OMAP54XX_IVA_STATDEP_SHIFT 2 66#define OMAP54XX_IVA_STATDEP_SHIFT 2
1203#define OMAP54XX_IVA_STATDEP_WIDTH 0x1
1204#define OMAP54XX_IVA_STATDEP_MASK (1 << 2)
1205
1206/* Used by CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1207#define OMAP54XX_L3INIT_DYNDEP_SHIFT 7
1208#define OMAP54XX_L3INIT_DYNDEP_WIDTH 0x1
1209#define OMAP54XX_L3INIT_DYNDEP_MASK (1 << 7)
1210
1211/*
1212 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1213 * CM_IPU_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1214 */
1215#define OMAP54XX_L3INIT_STATDEP_SHIFT 7 67#define OMAP54XX_L3INIT_STATDEP_SHIFT 7
1216#define OMAP54XX_L3INIT_STATDEP_WIDTH 0x1
1217#define OMAP54XX_L3INIT_STATDEP_MASK (1 << 7)
1218
1219/*
1220 * Used by CM_DSP_DYNAMICDEP, CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP,
1221 * CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP
1222 */
1223#define OMAP54XX_L3MAIN1_DYNDEP_SHIFT 5
1224#define OMAP54XX_L3MAIN1_DYNDEP_WIDTH 0x1
1225#define OMAP54XX_L3MAIN1_DYNDEP_MASK (1 << 5)
1226
1227/*
1228 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1229 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1230 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1231 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1232 */
1233#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5 68#define OMAP54XX_L3MAIN1_STATDEP_SHIFT 5
1234#define OMAP54XX_L3MAIN1_STATDEP_WIDTH 0x1
1235#define OMAP54XX_L3MAIN1_STATDEP_MASK (1 << 5)
1236
1237/*
1238 * Used by CM_C2C_DYNAMICDEP, CM_CAM_DYNAMICDEP, CM_DMA_DYNAMICDEP,
1239 * CM_DSS_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GPU_DYNAMICDEP, CM_IPU_DYNAMICDEP,
1240 * CM_IVA_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP,
1241 * CM_L4CFG_DYNAMICDEP, CM_L4SEC_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP
1242 */
1243#define OMAP54XX_L3MAIN2_DYNDEP_SHIFT 6
1244#define OMAP54XX_L3MAIN2_DYNDEP_WIDTH 0x1
1245#define OMAP54XX_L3MAIN2_DYNDEP_MASK (1 << 6)
1246
1247/*
1248 * Used by CM_C2C_STATICDEP, CM_CAM_STATICDEP, CM_DMA_STATICDEP,
1249 * CM_DSP_STATICDEP, CM_DSS_STATICDEP, CM_GPU_STATICDEP, CM_IPU_STATICDEP,
1250 * CM_IVA_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1251 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1252 */
1253#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6 69#define OMAP54XX_L3MAIN2_STATDEP_SHIFT 6
1254#define OMAP54XX_L3MAIN2_STATDEP_WIDTH 0x1
1255#define OMAP54XX_L3MAIN2_STATDEP_MASK (1 << 6)
1256
1257/* Used by CM_L3MAIN1_DYNAMICDEP */
1258#define OMAP54XX_L4CFG_DYNDEP_SHIFT 12
1259#define OMAP54XX_L4CFG_DYNDEP_WIDTH 0x1
1260#define OMAP54XX_L4CFG_DYNDEP_MASK (1 << 12)
1261
1262/*
1263 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1264 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1265 */
1266#define OMAP54XX_L4CFG_STATDEP_SHIFT 12 70#define OMAP54XX_L4CFG_STATDEP_SHIFT 12
1267#define OMAP54XX_L4CFG_STATDEP_WIDTH 0x1
1268#define OMAP54XX_L4CFG_STATDEP_MASK (1 << 12)
1269
1270/* Used by CM_L3MAIN2_DYNAMICDEP */
1271#define OMAP54XX_L4PER_DYNDEP_SHIFT 13
1272#define OMAP54XX_L4PER_DYNDEP_WIDTH 0x1
1273#define OMAP54XX_L4PER_DYNDEP_MASK (1 << 13)
1274
1275/*
1276 * Used by CM_C2C_STATICDEP, CM_DMA_STATICDEP, CM_DSP_STATICDEP,
1277 * CM_IPU_STATICDEP, CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP,
1278 * CM_MIPIEXT_STATICDEP, CM_MPU_STATICDEP
1279 */
1280#define OMAP54XX_L4PER_STATDEP_SHIFT 13 71#define OMAP54XX_L4PER_STATDEP_SHIFT 13
1281#define OMAP54XX_L4PER_STATDEP_WIDTH 0x1
1282#define OMAP54XX_L4PER_STATDEP_MASK (1 << 13)
1283
1284/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
1285#define OMAP54XX_L4SEC_DYNDEP_SHIFT 14
1286#define OMAP54XX_L4SEC_DYNDEP_WIDTH 0x1
1287#define OMAP54XX_L4SEC_DYNDEP_MASK (1 << 14)
1288
1289/*
1290 * Used by CM_DMA_STATICDEP, CM_IPU_STATICDEP, CM_L3INIT_STATICDEP,
1291 * CM_MPU_STATICDEP
1292 */
1293#define OMAP54XX_L4SEC_STATDEP_SHIFT 14 72#define OMAP54XX_L4SEC_STATDEP_SHIFT 14
1294#define OMAP54XX_L4SEC_STATDEP_WIDTH 0x1
1295#define OMAP54XX_L4SEC_STATDEP_MASK (1 << 14)
1296
1297/* Used by CM_L3MAIN2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
1298#define OMAP54XX_MIPIEXT_DYNDEP_SHIFT 21
1299#define OMAP54XX_MIPIEXT_DYNDEP_WIDTH 0x1
1300#define OMAP54XX_MIPIEXT_DYNDEP_MASK (1 << 21)
1301
1302/* Used by CM_MPU_STATICDEP */
1303#define OMAP54XX_MIPIEXT_STATDEP_SHIFT 21
1304#define OMAP54XX_MIPIEXT_STATDEP_WIDTH 0x1
1305#define OMAP54XX_MIPIEXT_STATDEP_MASK (1 << 21)
1306
1307/*
1308 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1309 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1310 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1311 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1312 */
1313#define OMAP54XX_MODFREQDIV_EXPONENT_SHIFT 8
1314#define OMAP54XX_MODFREQDIV_EXPONENT_WIDTH 0x3
1315#define OMAP54XX_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
1316
1317/*
1318 * Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
1319 * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
1320 * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO1,
1321 * CM_SSC_MODFREQDIV_DPLL_UNIPRO2, CM_SSC_MODFREQDIV_DPLL_USB
1322 */
1323#define OMAP54XX_MODFREQDIV_MANTISSA_SHIFT 0
1324#define OMAP54XX_MODFREQDIV_MANTISSA_WIDTH 0x7
1325#define OMAP54XX_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
1326
1327/*
1328 * Used by CM_ABE_AESS_CLKCTRL, CM_ABE_DMIC_CLKCTRL, CM_ABE_L4_ABE_CLKCTRL,
1329 * CM_ABE_MCASP_CLKCTRL, CM_ABE_MCBSP1_CLKCTRL, CM_ABE_MCBSP2_CLKCTRL,
1330 * CM_ABE_MCBSP3_CLKCTRL, CM_ABE_MCPDM_CLKCTRL, CM_ABE_SLIMBUS1_CLKCTRL,
1331 * CM_ABE_TIMER5_CLKCTRL, CM_ABE_TIMER6_CLKCTRL, CM_ABE_TIMER7_CLKCTRL,
1332 * CM_ABE_TIMER8_CLKCTRL, CM_ABE_WD_TIMER3_CLKCTRL, CM_C2C_C2C_CLKCTRL,
1333 * CM_C2C_C2C_OCP_FW_CLKCTRL, CM_C2C_MODEM_ICR_CLKCTRL, CM_CAM_CAL_CLKCTRL,
1334 * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CM_CORE_AON_PROFILING_CLKCTRL,
1335 * CM_CM_CORE_PROFILING_CLKCTRL, CM_COREAON_SMARTREFLEX_CORE_CLKCTRL,
1336 * CM_COREAON_SMARTREFLEX_MM_CLKCTRL, CM_COREAON_SMARTREFLEX_MPU_CLKCTRL,
1337 * CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL,
1338 * CM_DSP_DSP_CLKCTRL, CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL,
1339 * CM_EMIF_DMM_CLKCTRL, CM_EMIF_EMIF1_CLKCTRL, CM_EMIF_EMIF2_CLKCTRL,
1340 * CM_EMIF_EMIF_OCP_FW_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1341 * CM_EMU_MPU_EMU_DBG_CLKCTRL, CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL,
1342 * CM_IVA_IVA_CLKCTRL, CM_IVA_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL,
1343 * CM_L3INIT_IEEE1500_2_OCP_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
1344 * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MPHY_UNIPRO2_CLKCTRL,
1345 * CM_L3INIT_OCP2SCP1_CLKCTRL, CM_L3INIT_OCP2SCP3_CLKCTRL,
1346 * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_UNIPRO2_CLKCTRL,
1347 * CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_OTG_SS_CLKCTRL,
1348 * CM_L3INIT_USB_TLL_HS_CLKCTRL, CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL,
1349 * CM_L3INSTR_DLL_AGING_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
1350 * CM_L3INSTR_L3_MAIN_3_CLKCTRL, CM_L3INSTR_OCP_WP_NOC_CLKCTRL,
1351 * CM_L3MAIN1_L3_MAIN_1_CLKCTRL, CM_L3MAIN2_GPMC_CLKCTRL,
1352 * CM_L3MAIN2_L3_MAIN_2_CLKCTRL, CM_L3MAIN2_OCMC_RAM_CLKCTRL,
1353 * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL,
1354 * CM_L4CFG_OCP2SCP2_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
1355 * CM_L4CFG_SPINLOCK_CLKCTRL, CM_L4PER_ELM_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL,
1356 * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL,
1357 * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL,
1358 * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL,
1359 * CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL,
1360 * CM_L4PER_L4_PER_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
1361 * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMC3_CLKCTRL,
1362 * CM_L4PER_MMC4_CLKCTRL, CM_L4PER_MMC5_CLKCTRL, CM_L4PER_TIMER10_CLKCTRL,
1363 * CM_L4PER_TIMER11_CLKCTRL, CM_L4PER_TIMER2_CLKCTRL, CM_L4PER_TIMER3_CLKCTRL,
1364 * CM_L4PER_TIMER4_CLKCTRL, CM_L4PER_TIMER9_CLKCTRL, CM_L4PER_UART1_CLKCTRL,
1365 * CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL,
1366 * CM_L4PER_UART5_CLKCTRL, CM_L4PER_UART6_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
1367 * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
1368 * CM_L4SEC_DMA_CRYPTO_CLKCTRL, CM_L4SEC_FPKA_CLKCTRL, CM_L4SEC_RNG_CLKCTRL,
1369 * CM_L4SEC_SHA2MD5_CLKCTRL, CM_MIPIEXT_LLI_CLKCTRL,
1370 * CM_MIPIEXT_LLI_OCP_FW_CLKCTRL, CM_MIPIEXT_MPHY_CLKCTRL, CM_MPU_MPU_CLKCTRL,
1371 * CM_MPU_MPU_MPU_DBG_CLKCTRL, CM_WKUPAON_COUNTER_32K_CLKCTRL,
1372 * CM_WKUPAON_GPIO1_CLKCTRL, CM_WKUPAON_KBD_CLKCTRL,
1373 * CM_WKUPAON_L4_WKUP_CLKCTRL, CM_WKUPAON_SAR_RAM_CLKCTRL,
1374 * CM_WKUPAON_TIMER12_CLKCTRL, CM_WKUPAON_TIMER1_CLKCTRL,
1375 * CM_WKUPAON_WD_TIMER1_CLKCTRL, CM_WKUPAON_WD_TIMER2_CLKCTRL
1376 */
1377#define OMAP54XX_MODULEMODE_SHIFT 0
1378#define OMAP54XX_MODULEMODE_WIDTH 0x2
1379#define OMAP54XX_MODULEMODE_MASK (0x3 << 0)
1380
1381/* Used by CM_L4CFG_DYNAMICDEP */
1382#define OMAP54XX_MPU_DYNDEP_SHIFT 19
1383#define OMAP54XX_MPU_DYNDEP_WIDTH 0x1
1384#define OMAP54XX_MPU_DYNDEP_MASK (1 << 19)
1385
1386/* Used by CM_DSS_DSS_CLKCTRL */
1387#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11 73#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_SHIFT 11
1388#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_WIDTH 0x1
1389#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_MASK (1 << 11)
1390
1391/* Renamed from OPTFCLKEN_32KHZ_CLK Used by CM_L3INIT_MMC1_CLKCTRL */
1392#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8 74#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_SHIFT 8
1393#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_WIDTH 0x1
1394#define OMAP54XX_OPTFCLKEN_32KHZ_CLK_8_8_MASK (1 << 8)
1395
1396/* Used by CM_DSS_DSS_CLKCTRL */
1397#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9 75#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_SHIFT 9
1398#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_WIDTH 0x1
1399#define OMAP54XX_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
1400
1401/* Used by CM_COREAON_USB_PHY_CORE_CLKCTRL */
1402#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8 76#define OMAP54XX_OPTFCLKEN_CLK32K_SHIFT 8
1403#define OMAP54XX_OPTFCLKEN_CLK32K_WIDTH 0x1
1404#define OMAP54XX_OPTFCLKEN_CLK32K_MASK (1 << 8)
1405
1406/* Used by CM_CAM_ISS_CLKCTRL */
1407#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8 77#define OMAP54XX_OPTFCLKEN_CTRLCLK_SHIFT 8
1408#define OMAP54XX_OPTFCLKEN_CTRLCLK_WIDTH 0x1
1409#define OMAP54XX_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
1410
1411/*
1412 * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
1413 * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
1414 * CM_L4PER_GPIO7_CLKCTRL, CM_L4PER_GPIO8_CLKCTRL, CM_WKUPAON_GPIO1_CLKCTRL
1415 */
1416#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8 78#define OMAP54XX_OPTFCLKEN_DBCLK_SHIFT 8
1417#define OMAP54XX_OPTFCLKEN_DBCLK_WIDTH 0x1
1418#define OMAP54XX_OPTFCLKEN_DBCLK_MASK (1 << 8)
1419
1420/* Used by CM_EMIF_EMIF_DLL_CLKCTRL */
1421#define OMAP54XX_OPTFCLKEN_DLL_CLK_SHIFT 8
1422#define OMAP54XX_OPTFCLKEN_DLL_CLK_WIDTH 0x1
1423#define OMAP54XX_OPTFCLKEN_DLL_CLK_MASK (1 << 8)
1424
1425/* Used by CM_DSS_DSS_CLKCTRL */
1426#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8 79#define OMAP54XX_OPTFCLKEN_DSSCLK_SHIFT 8
1427#define OMAP54XX_OPTFCLKEN_DSSCLK_WIDTH 0x1
1428#define OMAP54XX_OPTFCLKEN_DSSCLK_MASK (1 << 8)
1429
1430/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1431#define OMAP54XX_OPTFCLKEN_FCLK0_SHIFT 8
1432#define OMAP54XX_OPTFCLKEN_FCLK0_WIDTH 0x1
1433#define OMAP54XX_OPTFCLKEN_FCLK0_MASK (1 << 8)
1434
1435/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1436#define OMAP54XX_OPTFCLKEN_FCLK1_SHIFT 9
1437#define OMAP54XX_OPTFCLKEN_FCLK1_WIDTH 0x1
1438#define OMAP54XX_OPTFCLKEN_FCLK1_MASK (1 << 9)
1439
1440/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1441#define OMAP54XX_OPTFCLKEN_FCLK2_SHIFT 10
1442#define OMAP54XX_OPTFCLKEN_FCLK2_WIDTH 0x1
1443#define OMAP54XX_OPTFCLKEN_FCLK2_MASK (1 << 10)
1444
1445/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1446#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_SHIFT 15
1447#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_WIDTH 0x1
1448#define OMAP54XX_OPTFCLKEN_FUNC48M_CLK_MASK (1 << 15)
1449
1450/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1451#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 80#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
1452#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH 0x1
1453#define OMAP54XX_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
1454
1455/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1456#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 81#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
1457#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH 0x1
1458#define OMAP54XX_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
1459
1460/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1461#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7 82#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_SHIFT 7
1462#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_WIDTH 0x1
1463#define OMAP54XX_OPTFCLKEN_HSIC480M_P3_CLK_MASK (1 << 7)
1464
1465/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1466#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 83#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
1467#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH 0x1
1468#define OMAP54XX_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
1469
1470/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1471#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 84#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
1472#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH 0x1
1473#define OMAP54XX_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
1474
1475/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1476#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6 85#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_SHIFT 6
1477#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_WIDTH 0x1
1478#define OMAP54XX_OPTFCLKEN_HSIC60M_P3_CLK_MASK (1 << 6)
1479
1480/* Used by CM_L3INIT_USB_OTG_SS_CLKCTRL */
1481#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8 86#define OMAP54XX_OPTFCLKEN_REFCLK960M_SHIFT 8
1482#define OMAP54XX_OPTFCLKEN_REFCLK960M_WIDTH 0x1
1483#define OMAP54XX_OPTFCLKEN_REFCLK960M_MASK (1 << 8)
1484
1485/* Used by CM_L3INIT_SATA_CLKCTRL */
1486#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8 87#define OMAP54XX_OPTFCLKEN_REF_CLK_SHIFT 8
1487#define OMAP54XX_OPTFCLKEN_REF_CLK_WIDTH 0x1
1488#define OMAP54XX_OPTFCLKEN_REF_CLK_MASK (1 << 8)
1489
1490/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1491#define OMAP54XX_OPTFCLKEN_SCRM_CORE_SHIFT 8
1492#define OMAP54XX_OPTFCLKEN_SCRM_CORE_WIDTH 0x1
1493#define OMAP54XX_OPTFCLKEN_SCRM_CORE_MASK (1 << 8)
1494
1495/* Used by CM_WKUPAON_SCRM_CLKCTRL */
1496#define OMAP54XX_OPTFCLKEN_SCRM_PER_SHIFT 9
1497#define OMAP54XX_OPTFCLKEN_SCRM_PER_WIDTH 0x1
1498#define OMAP54XX_OPTFCLKEN_SCRM_PER_MASK (1 << 9)
1499
1500/* Used by CM_ABE_SLIMBUS1_CLKCTRL */
1501#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11 88#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_SHIFT 11
1502#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_WIDTH 0x1
1503#define OMAP54XX_OPTFCLKEN_SLIMBUS_CLK_MASK (1 << 11)
1504
1505/* Used by CM_DSS_DSS_CLKCTRL */
1506#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10 89#define OMAP54XX_OPTFCLKEN_SYS_CLK_SHIFT 10
1507#define OMAP54XX_OPTFCLKEN_SYS_CLK_WIDTH 0x1
1508#define OMAP54XX_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
1509
1510/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1511#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8 90#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_SHIFT 8
1512#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_WIDTH 0x1
1513#define OMAP54XX_OPTFCLKEN_TXPHY_CLK_MASK (1 << 8)
1514
1515/* Used by CM_MIPIEXT_LLI_CLKCTRL */
1516#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9 91#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_SHIFT 9
1517#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_WIDTH 0x1
1518#define OMAP54XX_OPTFCLKEN_TXPHY_LS_CLK_MASK (1 << 9)
1519
1520/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1521#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 92#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
1522#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_WIDTH 0x1
1523#define OMAP54XX_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
1524
1525/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1526#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 93#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
1527#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_WIDTH 0x1
1528#define OMAP54XX_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
1529
1530/* Used by CM_L3INIT_USB_TLL_HS_CLKCTRL */
1531#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 94#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
1532#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_WIDTH 0x1
1533#define OMAP54XX_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
1534
1535/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1536#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 95#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
1537#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_WIDTH 0x1
1538#define OMAP54XX_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
1539
1540/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1541#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 96#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
1542#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_WIDTH 0x1
1543#define OMAP54XX_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
1544
1545/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL */
1546#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 97#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
1547#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_WIDTH 0x1
1548#define OMAP54XX_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
1549
1550/* Used by CM_CORE_AON_DEBUG_OUT, CM_CORE_DEBUG_OUT */
1551#define OMAP54XX_OUTPUT_SHIFT 0
1552#define OMAP54XX_OUTPUT_WIDTH 0x20
1553#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
1554
1555/* Used by CM_CLKSEL_ABE */
1556#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8 98#define OMAP54XX_PAD_CLKS_GATE_SHIFT 8
1557#define OMAP54XX_PAD_CLKS_GATE_WIDTH 0x1
1558#define OMAP54XX_PAD_CLKS_GATE_MASK (1 << 8)
1559
1560/* Used by CM_RESTORE_ST */
1561#define OMAP54XX_PHASE1_COMPLETED_SHIFT 0
1562#define OMAP54XX_PHASE1_COMPLETED_WIDTH 0x1
1563#define OMAP54XX_PHASE1_COMPLETED_MASK (1 << 0)
1564
1565/* Used by CM_RESTORE_ST */
1566#define OMAP54XX_PHASE2A_COMPLETED_SHIFT 1
1567#define OMAP54XX_PHASE2A_COMPLETED_WIDTH 0x1
1568#define OMAP54XX_PHASE2A_COMPLETED_MASK (1 << 1)
1569
1570/* Used by CM_RESTORE_ST */
1571#define OMAP54XX_PHASE2B_COMPLETED_SHIFT 2
1572#define OMAP54XX_PHASE2B_COMPLETED_WIDTH 0x1
1573#define OMAP54XX_PHASE2B_COMPLETED_MASK (1 << 2)
1574
1575/* Used by CM_DYN_DEP_PRESCAL */
1576#define OMAP54XX_PRESCAL_SHIFT 0
1577#define OMAP54XX_PRESCAL_WIDTH 0x6
1578#define OMAP54XX_PRESCAL_MASK (0x3f << 0)
1579
1580/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1581#define OMAP54XX_R_RTL_SHIFT 11
1582#define OMAP54XX_R_RTL_WIDTH 0x5
1583#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1584
1585/* Used by CM_L3INIT_USB_HOST_HS_CLKCTRL, CM_L3INIT_USB_TLL_HS_CLKCTRL */
1586#define OMAP54XX_SAR_MODE_SHIFT 4
1587#define OMAP54XX_SAR_MODE_WIDTH 0x1
1588#define OMAP54XX_SAR_MODE_MASK (1 << 4)
1589
1590/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1591#define OMAP54XX_SCHEME_SHIFT 30
1592#define OMAP54XX_SCHEME_WIDTH 0x2
1593#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1594
1595/* Used by CM_L4CFG_DYNAMICDEP */
1596#define OMAP54XX_SDMA_DYNDEP_SHIFT 11
1597#define OMAP54XX_SDMA_DYNDEP_WIDTH 0x1
1598#define OMAP54XX_SDMA_DYNDEP_MASK (1 << 11)
1599
1600/* Used by CM_IPU_STATICDEP, CM_MPU_STATICDEP */
1601#define OMAP54XX_SDMA_STATDEP_SHIFT 11
1602#define OMAP54XX_SDMA_STATDEP_WIDTH 0x1
1603#define OMAP54XX_SDMA_STATDEP_MASK (1 << 11)
1604
1605/* Used by CM_CORE_AON_DEBUG_CFG */
1606#define OMAP54XX_SEL0_SHIFT 0
1607#define OMAP54XX_SEL0_WIDTH 0x7
1608#define OMAP54XX_SEL0_MASK (0x7f << 0)
1609
1610/* Renamed from SEL0 Used by CM_CORE_DEBUG_CFG */
1611#define OMAP54XX_SEL0_0_7_SHIFT 0
1612#define OMAP54XX_SEL0_0_7_WIDTH 0x8
1613#define OMAP54XX_SEL0_0_7_MASK (0xff << 0)
1614
1615/* Used by CM_CORE_AON_DEBUG_CFG */
1616#define OMAP54XX_SEL1_SHIFT 8
1617#define OMAP54XX_SEL1_WIDTH 0x7
1618#define OMAP54XX_SEL1_MASK (0x7f << 8)
1619
1620/* Renamed from SEL1 Used by CM_CORE_DEBUG_CFG */
1621#define OMAP54XX_SEL1_CORE_DEBUG_CFG_SHIFT 8
1622#define OMAP54XX_SEL1_CORE_DEBUG_CFG_WIDTH 0x8
1623#define OMAP54XX_SEL1_CORE_DEBUG_CFG_MASK (0xff << 8)
1624
1625/* Used by CM_CORE_AON_DEBUG_CFG */
1626#define OMAP54XX_SEL2_SHIFT 16
1627#define OMAP54XX_SEL2_WIDTH 0x7
1628#define OMAP54XX_SEL2_MASK (0x7f << 16)
1629
1630/* Renamed from SEL2 Used by CM_CORE_DEBUG_CFG */
1631#define OMAP54XX_SEL2_CORE_DEBUG_CFG_SHIFT 16
1632#define OMAP54XX_SEL2_CORE_DEBUG_CFG_WIDTH 0x8
1633#define OMAP54XX_SEL2_CORE_DEBUG_CFG_MASK (0xff << 16)
1634
1635/* Used by CM_CORE_AON_DEBUG_CFG */
1636#define OMAP54XX_SEL3_SHIFT 24
1637#define OMAP54XX_SEL3_WIDTH 0x7
1638#define OMAP54XX_SEL3_MASK (0x7f << 24)
1639
1640/* Renamed from SEL3 Used by CM_CORE_DEBUG_CFG */
1641#define OMAP54XX_SEL3_CORE_DEBUG_CFG_SHIFT 24
1642#define OMAP54XX_SEL3_CORE_DEBUG_CFG_WIDTH 0x8
1643#define OMAP54XX_SEL3_CORE_DEBUG_CFG_MASK (0xff << 24)
1644
1645/* Used by CM_CLKSEL_ABE */
1646#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10 99#define OMAP54XX_SLIMBUS1_CLK_GATE_SHIFT 10
1647#define OMAP54XX_SLIMBUS1_CLK_GATE_WIDTH 0x1
1648#define OMAP54XX_SLIMBUS1_CLK_GATE_MASK (1 << 10)
1649
1650/*
1651 * Used by CM_ABE_AESS_CLKCTRL, CM_C2C_C2C_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
1652 * CM_CAM_ISS_CLKCTRL, CM_DMA_DMA_SYSTEM_CLKCTRL, CM_DSP_DSP_CLKCTRL,
1653 * CM_DSS_BB2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL,
1654 * CM_GPU_GPU_CLKCTRL, CM_IPU_IPU_CLKCTRL, CM_IVA_IVA_CLKCTRL,
1655 * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_IEEE1500_2_OCP_CLKCTRL,
1656 * CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_SATA_CLKCTRL,
1657 * CM_L3INIT_UNIPRO2_CLKCTRL, CM_L3INIT_USB_HOST_HS_CLKCTRL,
1658 * CM_L3INIT_USB_OTG_SS_CLKCTRL, CM_L4SEC_DMA_CRYPTO_CLKCTRL,
1659 * CM_MIPIEXT_LLI_CLKCTRL, CM_MPU_MPU_CLKCTRL
1660 */
1661#define OMAP54XX_STBYST_SHIFT 18
1662#define OMAP54XX_STBYST_WIDTH 0x1
1663#define OMAP54XX_STBYST_MASK (1 << 18)
1664
1665/*
1666 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1667 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1668 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1669 */
1670#define OMAP54XX_ST_DPLL_CLK_SHIFT 0
1671#define OMAP54XX_ST_DPLL_CLK_WIDTH 0x1
1672#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0) 100#define OMAP54XX_ST_DPLL_CLK_MASK (1 << 0)
1673
1674/*
1675 * Used by CM_CLKDCOLDO_DPLL_UNIPRO1, CM_CLKDCOLDO_DPLL_UNIPRO2,
1676 * CM_CLKDCOLDO_DPLL_USB
1677 */
1678#define OMAP54XX_ST_DPLL_CLKDCOLDO_SHIFT 9
1679#define OMAP54XX_ST_DPLL_CLKDCOLDO_WIDTH 0x1
1680#define OMAP54XX_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
1681
1682/*
1683 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1684 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1685 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1686 */
1687#define OMAP54XX_ST_DPLL_INIT_SHIFT 4
1688#define OMAP54XX_ST_DPLL_INIT_WIDTH 0x1
1689#define OMAP54XX_ST_DPLL_INIT_MASK (1 << 4)
1690
1691/*
1692 * Used by CM_IDLEST_DPLL_ABE, CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_IVA,
1693 * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER, CM_IDLEST_DPLL_UNIPRO1,
1694 * CM_IDLEST_DPLL_UNIPRO2, CM_IDLEST_DPLL_USB
1695 */
1696#define OMAP54XX_ST_DPLL_MODE_SHIFT 1
1697#define OMAP54XX_ST_DPLL_MODE_WIDTH 0x3
1698#define OMAP54XX_ST_DPLL_MODE_MASK (0x7 << 1)
1699
1700/* Used by CM_CLKSEL_SYS */
1701#define OMAP54XX_SYS_CLKSEL_SHIFT 0 101#define OMAP54XX_SYS_CLKSEL_SHIFT 0
1702#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3 102#define OMAP54XX_SYS_CLKSEL_WIDTH 0x3
1703#define OMAP54XX_SYS_CLKSEL_MASK (0x7 << 0)
1704
1705/*
1706 * Used by CM_C2C_DYNAMICDEP, CM_DSP_DYNAMICDEP, CM_EMU_DYNAMICDEP,
1707 * CM_IPU_DYNAMICDEP, CM_L3MAIN1_DYNAMICDEP, CM_L3MAIN2_DYNAMICDEP,
1708 * CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP, CM_MIPIEXT_DYNAMICDEP,
1709 * CM_MPU_DYNAMICDEP
1710 */
1711#define OMAP54XX_WINDOWSIZE_SHIFT 24
1712#define OMAP54XX_WINDOWSIZE_WIDTH 0x4
1713#define OMAP54XX_WINDOWSIZE_MASK (0xf << 24)
1714
1715/* Used by CM_L3MAIN1_DYNAMICDEP */
1716#define OMAP54XX_WKUPAON_DYNDEP_SHIFT 15
1717#define OMAP54XX_WKUPAON_DYNDEP_WIDTH 0x1
1718#define OMAP54XX_WKUPAON_DYNDEP_MASK (1 << 15)
1719
1720/*
1721 * Used by CM_DMA_STATICDEP, CM_DSP_STATICDEP, CM_IPU_STATICDEP,
1722 * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP
1723 */
1724#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15 103#define OMAP54XX_WKUPAON_STATDEP_SHIFT 15
1725#define OMAP54XX_WKUPAON_STATDEP_WIDTH 0x1
1726#define OMAP54XX_WKUPAON_STATDEP_MASK (1 << 15)
1727
1728/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1729#define OMAP54XX_X_MAJOR_SHIFT 8
1730#define OMAP54XX_X_MAJOR_WIDTH 0x3
1731#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
1732
1733/* Used by REVISION_CM_CORE, REVISION_CM_CORE_AON */
1734#define OMAP54XX_Y_MINOR_SHIFT 0
1735#define OMAP54XX_Y_MINOR_WIDTH 0x6
1736#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
1737#endif 104#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
new file mode 100644
index 000000000000..ad8f81ce9b16
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -0,0 +1,51 @@
1/*
2 * DRA7xx Clock Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
24
25#define DRA7XX_ATL_STATDEP_SHIFT 30
26#define DRA7XX_CAM_STATDEP_SHIFT 9
27#define DRA7XX_DSP1_STATDEP_SHIFT 1
28#define DRA7XX_DSP2_STATDEP_SHIFT 18
29#define DRA7XX_DSS_STATDEP_SHIFT 8
30#define DRA7XX_EMIF_STATDEP_SHIFT 4
31#define DRA7XX_EVE1_STATDEP_SHIFT 19
32#define DRA7XX_EVE2_STATDEP_SHIFT 20
33#define DRA7XX_EVE3_STATDEP_SHIFT 21
34#define DRA7XX_EVE4_STATDEP_SHIFT 22
35#define DRA7XX_GMAC_STATDEP_SHIFT 25
36#define DRA7XX_GPU_STATDEP_SHIFT 10
37#define DRA7XX_IPU1_STATDEP_SHIFT 23
38#define DRA7XX_IPU2_STATDEP_SHIFT 0
39#define DRA7XX_IPU_STATDEP_SHIFT 24
40#define DRA7XX_IVA_STATDEP_SHIFT 2
41#define DRA7XX_L3INIT_STATDEP_SHIFT 7
42#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
43#define DRA7XX_L4CFG_STATDEP_SHIFT 12
44#define DRA7XX_L4PER2_STATDEP_SHIFT 26
45#define DRA7XX_L4PER3_STATDEP_SHIFT 27
46#define DRA7XX_L4PER_STATDEP_SHIFT 13
47#define DRA7XX_L4SEC_STATDEP_SHIFT 14
48#define DRA7XX_PCIE_STATDEP_SHIFT 29
49#define DRA7XX_VPE_STATDEP_SHIFT 28
50#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
51#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
new file mode 100644
index 000000000000..ca6fa1febaac
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -0,0 +1,324 @@
1/*
2 * DRA7xx CM1 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
25
26#include "cm_44xx_54xx.h"
27
28/* CM1 base address */
29#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
30
31#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
33
34/* CM_CORE_AON instances */
35#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
36#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
37#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
38#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
39#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
40#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
41#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
42#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
43#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
44#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
45#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
46#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
47#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
48#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
49
50/* CM_CORE_AON clockdomain register offsets (from instance start) */
51#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
52#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
53#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
54#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
55#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
56#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
62
63/* CM_CORE_AON */
64
65/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
66#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
67#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
68#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
69#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
70#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
71#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
72#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
73#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
74
75/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
76#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
77#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
78#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
79#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
80#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
81#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
82#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
83#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
84#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
85#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
86#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
87#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
88#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
89#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
90#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
91#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
92#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
93#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
94#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
95#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
96#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
97#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
98#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
99#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
100#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
101#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
102#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
103#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
104#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
105#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
106#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
107#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
108#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
109#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
110#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
111#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
112#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
113#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
114#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
115#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
116#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
117#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
118#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
119#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
120#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
121#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
122#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
123#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
124#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
125#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
126#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
127#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
128#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
129#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
130#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
131#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
132#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
133#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
134#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
135#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
136#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
137#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
138#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
139#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
140#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
141#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
142#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
143#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
144#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
145#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
146#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
147#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
148#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
149#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
150#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
151#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
152#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
153#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
154#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
155#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
156#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
157#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
158#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
159#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
160#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
161#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
162#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
163#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
164#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
165#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
166#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
167#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
168#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
169#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
170#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
171#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
172#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
173#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
174#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
175#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
176#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
177#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
178#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
179#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
180#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
181#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
182#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
183#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
184#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
185#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
186#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
187#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
188#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
189#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
190#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
191#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
192#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
193#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
194#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
195#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
196#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
197#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
198#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
199#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
200#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
201#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
202#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
203#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
204#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
205#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
206#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
207#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
208#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
209#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
210#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
211#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
212#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
213#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
214#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
215#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
216#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
217#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
218#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
219#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
220#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
221#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
222#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
223#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
224#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
225#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
226#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
227#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
228#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
229#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
230#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
231#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
232#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
233#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
234#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
235#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
236#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
237#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
238#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
239#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
240#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
241#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
242#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
243
244/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
245#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
246#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
247#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
248#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
249#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
250#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
251#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
252
253/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
254#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
255#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
256#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
257#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
258#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
259
260/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
261#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
262#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
263#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
264#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
265#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
266#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
267#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
268#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
269#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
270#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
271#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
272#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
273#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
274#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
275#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
276#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
277#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
278#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
279#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
280#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
281
282/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
283#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
284#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
285#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
286#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
287#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
288
289/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
290#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
291#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
292#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
293#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
294
295/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
296#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
299#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
300
301/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
302#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
303#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
304#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
305#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
306
307/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
308#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
309#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
310#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
311#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
312
313/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
314#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
315#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
316#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
317
318/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
319#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
320#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
321#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
322#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
323
324#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
new file mode 100644
index 000000000000..9ad7594e7622
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -0,0 +1,513 @@
1/*
2 * DRA7xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
24
25#include "cm_44xx_54xx.h"
26
27/* CM2 base address */
28#define DRA7XX_CM_CORE_BASE 0x4a008000
29
30#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
32
33/* CM_CORE instances */
34#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
35#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
36#define DRA7XX_CM_CORE_COREAON_INST 0x0600
37#define DRA7XX_CM_CORE_CORE_INST 0x0700
38#define DRA7XX_CM_CORE_IVA_INST 0x0f00
39#define DRA7XX_CM_CORE_CAM_INST 0x1000
40#define DRA7XX_CM_CORE_DSS_INST 0x1100
41#define DRA7XX_CM_CORE_GPU_INST 0x1200
42#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
43#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
44#define DRA7XX_CM_CORE_L4PER_INST 0x1700
45#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
46
47/* CM_CORE clockdomain register offsets (from instance start) */
48#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
49#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
50#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
51#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
52#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
53#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
54#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
55#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
56#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
62#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
63#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
64#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
65#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
66#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
67#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
68
69/* CM_CORE */
70
71/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
72#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
73#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
74#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
75#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
76
77/* CM_CORE.CKGEN_CM_CORE register offsets */
78#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
79#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
80#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
81#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
82#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
83#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
84#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
85#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
86#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
87#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
88#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
89#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
90#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
91#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
92#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
93#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
94#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
95#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
96#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
97#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
98#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
99#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
100#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
101#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
102#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
103#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
104#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
105#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
106#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
107#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
108#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
109#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
110#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
111#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
112#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
113#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
114#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
115#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
116#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
117#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
118#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
119#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
120#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
121#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
122#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
123#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
124#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
125#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
126#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
127#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
128#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
129#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
130#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
131#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
132#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
133#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
134#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
135#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
136
137/* CM_CORE.COREAON_CM_CORE register offsets */
138#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
139#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
140#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
141#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
142#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
143#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
144#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
145#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
146#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
147#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
148#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
149#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
150#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
151#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
152#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
153#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
154#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
155#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
156#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
157#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
158#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
159#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
160#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
161#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
162#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
163#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
164#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
165
166/* CM_CORE.CORE_CM_CORE register offsets */
167#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
168#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
169#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
170#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
171#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
172#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
173#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
174#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
175#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
176#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
177#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
178#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
179#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
180#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
181#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
182#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
183#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
184#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
185#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
186#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
187#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
188#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
189#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
190#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
191#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
192#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
193#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
194#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
195#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
196#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
197#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
198#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
199#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
200#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
201#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
202#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
203#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
204#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
205#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
206#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
207#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
208#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
209#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
210#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
211#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
212#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
213#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
214#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
215#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
216#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
217#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
218#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
219#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
220#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
221#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
222#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
223#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
224#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
225#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
226#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
227#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
228#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
229#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
230#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
231#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
232#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
233#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
234#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
235#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
236#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
237#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
238#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
239#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
240#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
241#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
242#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
243#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
244#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
245#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
246#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
247#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
248#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
249#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
250#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
251#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
252#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
253#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
254#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
255#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
256#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
257#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
258#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
259#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
260#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
261#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
262#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
263#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
264#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
265#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
266#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
267#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
268#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
269#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
270#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
271#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
272#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
273#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
274#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
275#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
276#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
277#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
278#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
279#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
280#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
281#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
282#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
283#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
284#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
285#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
286#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
287#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
288#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
289#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
290#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
291#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
292#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
293#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
294
295/* CM_CORE.IVA_CM_CORE register offsets */
296#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
299#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
300#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
301#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
302#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
303
304/* CM_CORE.CAM_CM_CORE register offsets */
305#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
306#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
307#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
308#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
309#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
310#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
311#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
312#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
313#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
314#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
315#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
316#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
317#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
318#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
319
320/* CM_CORE.DSS_CM_CORE register offsets */
321#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
322#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
323#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
324#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
325#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
326#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
327#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
328#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
329#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
330
331/* CM_CORE.GPU_CM_CORE register offsets */
332#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
333#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
334#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
335#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
336#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
337
338/* CM_CORE.L3INIT_CM_CORE register offsets */
339#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
340#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
341#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
342#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
343#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
344#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
345#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
346#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
347#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
348#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
349#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
350#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
351#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
352#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
353#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
354#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
355#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
356#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
363#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
364#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
365#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
366#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
367#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
368#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
369#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
370#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
371
372/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
373#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
374#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
375#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
376
377/* CM_CORE.L4PER_CM_CORE register offsets */
378#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
379#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
380#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
381#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
382#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
383#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
384#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
385#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
386#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
387#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
388#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
389#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
390#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
391#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
392#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
393#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
394#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
395#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
396#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
397#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
398#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
399#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
400#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
401#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
402#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
403#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
404#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
405#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
406#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
407#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
408#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
409#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
410#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
411#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
412#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
413#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
414#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
415#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
416#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
417#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
418#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
419#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
420#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
421#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
422#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
423#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
424#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
425#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
426#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
427#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
428#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
429#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
430#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
431#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
432#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
433#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
434#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
435#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
436#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
437#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
438#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
439#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
440#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
441#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
442#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
443#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
444#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
445#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
446#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
447#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
448#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
449#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
450#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
451#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
452#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
453#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
454#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
455#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
456#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
457#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
458#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
459#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
460#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
461#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
462#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
463#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
464#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
465#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
466#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
467#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
468#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
469#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
470#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
471#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
472#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
473#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
474#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
475#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
476#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
477#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
478#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
479#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
480#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
481#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
482#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
483#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
484#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
485#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
486#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
487#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
488#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
489#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
490#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
491#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
492#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
493#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
494#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
495#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
496#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
497#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
498#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
499#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
500#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
501#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
502#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
503#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
504#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
505#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
506#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
507#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
508#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
509#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
510#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
511#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
512
513#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index dfcc182ecff9..4a5684b96492 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -110,6 +110,7 @@ void omap3630_init_late(void);
110void am35xx_init_late(void); 110void am35xx_init_late(void);
111void ti81xx_init_late(void); 111void ti81xx_init_late(void);
112int omap2_common_pm_late_init(void); 112int omap2_common_pm_late_init(void);
113void dra7xx_init_early(void);
113 114
114#ifdef CONFIG_SOC_BUS 115#ifdef CONFIG_SOC_BUS
115void omap_soc_device_init(void); 116void omap_soc_device_init(void);
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 3c1279f27d1f..5c5315ba129b 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -327,44 +327,6 @@ static void omap_init_audio(void)
327static inline void omap_init_audio(void) {} 327static inline void omap_init_audio(void) {}
328#endif 328#endif
329 329
330#if defined(CONFIG_SND_OMAP_SOC_MCPDM) || \
331 defined(CONFIG_SND_OMAP_SOC_MCPDM_MODULE)
332
333static void __init omap_init_mcpdm(void)
334{
335 struct omap_hwmod *oh;
336 struct platform_device *pdev;
337
338 oh = omap_hwmod_lookup("mcpdm");
339 if (!oh)
340 return;
341
342 pdev = omap_device_build("omap-mcpdm", -1, oh, NULL, 0);
343 WARN(IS_ERR(pdev), "Can't build omap_device for omap-mcpdm.\n");
344}
345#else
346static inline void omap_init_mcpdm(void) {}
347#endif
348
349#if defined(CONFIG_SND_OMAP_SOC_DMIC) || \
350 defined(CONFIG_SND_OMAP_SOC_DMIC_MODULE)
351
352static void __init omap_init_dmic(void)
353{
354 struct omap_hwmod *oh;
355 struct platform_device *pdev;
356
357 oh = omap_hwmod_lookup("dmic");
358 if (!oh)
359 return;
360
361 pdev = omap_device_build("omap-dmic", -1, oh, NULL, 0);
362 WARN(IS_ERR(pdev), "Can't build omap_device for omap-dmic.\n");
363}
364#else
365static inline void omap_init_dmic(void) {}
366#endif
367
368#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \ 330#if defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI) || \
369 defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE) 331 defined(CONFIG_SND_OMAP_SOC_OMAP_HDMI_MODULE)
370 332
@@ -565,17 +527,15 @@ static int __init omap2_init_devices(void)
565 omap_init_mbox(); 527 omap_init_mbox();
566 /* If dtb is there, the devices will be created dynamically */ 528 /* If dtb is there, the devices will be created dynamically */
567 if (!of_have_populated_dt()) { 529 if (!of_have_populated_dt()) {
568 omap_init_dmic();
569 omap_init_mcpdm();
570 omap_init_mcspi(); 530 omap_init_mcspi();
571 omap_init_sham(); 531 omap_init_sham();
572 omap_init_aes(); 532 omap_init_aes();
533 omap_init_rng();
573 } else { 534 } else {
574 /* These can be removed when bindings are done */ 535 /* These can be removed when bindings are done */
575 omap_init_wl12xx_of(); 536 omap_init_wl12xx_of();
576 } 537 }
577 omap_init_sti(); 538 omap_init_sti();
578 omap_init_rng();
579 omap_init_vout(); 539 omap_init_vout();
580 540
581 return 0; 541 return 0;
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index f3fdd6afa213..9f4795aff48a 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -149,7 +149,7 @@ struct omap3_gpmc_regs {
149 149
150static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; 150static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ];
151static struct irq_chip gpmc_irq_chip; 151static struct irq_chip gpmc_irq_chip;
152static unsigned gpmc_irq_start; 152static int gpmc_irq_start;
153 153
154static struct resource gpmc_mem_root; 154static struct resource gpmc_mem_root;
155static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 155static struct resource gpmc_cs_mem[GPMC_CS_NUM];
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2dc62a25f2c3..0289adcb6efb 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -61,7 +61,7 @@ int omap_type(void)
61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS); 61 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
62 } else if (cpu_is_omap44xx()) { 62 } else if (cpu_is_omap44xx()) {
63 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS); 63 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
64 } else if (soc_is_omap54xx()) { 64 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
65 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS); 65 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
66 val &= OMAP5_DEVICETYPE_MASK; 66 val &= OMAP5_DEVICETYPE_MASK;
67 val >>= 6; 67 val >>= 6;
@@ -116,7 +116,7 @@ static u16 tap_prod_id;
116 116
117void omap_get_die_id(struct omap_die_id *odi) 117void omap_get_die_id(struct omap_die_id *odi)
118{ 118{
119 if (cpu_is_omap44xx() || soc_is_omap54xx()) { 119 if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
120 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0); 120 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
121 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1); 121 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
122 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2); 122 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 4a3f06f02859..ff2113ce4014 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -251,7 +251,7 @@ static struct map_desc omap44xx_io_desc[] __initdata = {
251}; 251};
252#endif 252#endif
253 253
254#ifdef CONFIG_SOC_OMAP5 254#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
255static struct map_desc omap54xx_io_desc[] __initdata = { 255static struct map_desc omap54xx_io_desc[] __initdata = {
256 { 256 {
257 .virtual = L3_54XX_VIRT, 257 .virtual = L3_54XX_VIRT,
@@ -333,7 +333,7 @@ void __init omap4_map_io(void)
333} 333}
334#endif 334#endif
335 335
336#ifdef CONFIG_SOC_OMAP5 336#if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
337void __init omap5_map_io(void) 337void __init omap5_map_io(void)
338{ 338{
339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc)); 339 iotable_init(omap54xx_io_desc, ARRAY_SIZE(omap54xx_io_desc));
@@ -653,6 +653,27 @@ void __init omap5_init_early(void)
653} 653}
654#endif 654#endif
655 655
656#ifdef CONFIG_SOC_DRA7XX
657void __init dra7xx_init_early(void)
658{
659 omap2_set_globals_tap(-1, OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE));
660 omap2_set_globals_control(OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE),
661 OMAP2_L4_IO_ADDRESS(DRA7XX_CTRL_BASE));
662 omap2_set_globals_prm(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE));
663 omap2_set_globals_cm(OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE),
664 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE));
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap_prm_base_init();
667 omap_cm_base_init();
668 omap44xx_prm_init();
669 dra7xx_powerdomains_init();
670 dra7xx_clockdomains_init();
671 dra7xx_hwmod_init();
672 omap_hwmod_init_postsetup();
673}
674#endif
675
676
656void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, 677void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
657 struct omap_sdrc_params *sdrc_cs1) 678 struct omap_sdrc_params *sdrc_cs1)
658{ 679{
diff --git a/arch/arm/mach-omap2/omap54xx.h b/arch/arm/mach-omap2/omap54xx.h
index a086ba15868b..2d35c5709408 100644
--- a/arch/arm/mach-omap2/omap54xx.h
+++ b/arch/arm/mach-omap2/omap54xx.h
@@ -30,4 +30,8 @@
30#define OMAP54XX_CTRL_BASE 0x4a002800 30#define OMAP54XX_CTRL_BASE 0x4a002800
31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000 31#define OMAP54XX_SAR_RAM_BASE 0x4ae26000
32 32
33#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
34#define DRA7XX_CTRL_BASE 0x4a003400
35#define DRA7XX_TAP_BASE 0x4ae0c000
36
33#endif /* __ASM_SOC_OMAP555554XX_H */ 37#endif /* __ASM_SOC_OMAP555554XX_H */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 7f4db12b1459..d9ee0ff094d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1405,7 +1405,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
1405 (sf & SYSC_HAS_CLOCKACTIVITY)) 1405 (sf & SYSC_HAS_CLOCKACTIVITY))
1406 _set_clockactivity(oh, oh->class->sysc->clockact, &v); 1406 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
1407 1407
1408 _write_sysconfig(v, oh); 1408 /* If the cached value is the same as the new value, skip the write */
1409 if (oh->_sysc_cache != v)
1410 _write_sysconfig(v, oh);
1409 1411
1410 /* 1412 /*
1411 * Set the autoidle bit only after setting the smartidle bit 1413 * Set the autoidle bit only after setting the smartidle bit
@@ -4113,7 +4115,7 @@ void __init omap_hwmod_init(void)
4113 soc_ops.assert_hardreset = _omap2_assert_hardreset; 4115 soc_ops.assert_hardreset = _omap2_assert_hardreset;
4114 soc_ops.deassert_hardreset = _omap2_deassert_hardreset; 4116 soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
4115 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted; 4117 soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
4116 } else if (cpu_is_omap44xx() || soc_is_omap54xx()) { 4118 } else if (cpu_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
4117 soc_ops.enable_module = _omap4_enable_module; 4119 soc_ops.enable_module = _omap4_enable_module;
4118 soc_ops.disable_module = _omap4_disable_module; 4120 soc_ops.disable_module = _omap4_disable_module;
4119 soc_ops.wait_target_ready = _omap4_wait_target_ready; 4121 soc_ops.wait_target_ready = _omap4_wait_target_ready;
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index e1482a9b3bc2..d02acf9308d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
751extern int omap44xx_hwmod_init(void); 751extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void); 752extern int omap54xx_hwmod_init(void);
753extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
754extern int dra7xx_hwmod_init(void);
754 755
755extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 756extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
756 757
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b93b51c..215894f8910d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
325 * 325 *
326 * - cEFUSE (doesn't fall under any ocp_if) 326 * - cEFUSE (doesn't fall under any ocp_if)
327 * - clkdiv32k 327 * - clkdiv32k
328 * - debugss
329 * - ocp watch point 328 * - ocp watch point
330 */ 329 */
331#if 0 330#if 0
@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
369 }, 368 },
370}; 369};
371 370
372/*
373 * 'debugss' class
374 * debug sub system
375 */
376static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
377 .name = "debugss",
378};
379
380static struct omap_hwmod am33xx_debugss_hwmod = {
381 .name = "debugss",
382 .class = &am33xx_debugss_hwmod_class,
383 .clkdm_name = "l3_aon_clkdm",
384 .main_clk = "debugss_ick",
385 .prcm = {
386 .omap4 = {
387 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
388 .modulemode = MODULEMODE_SWCTRL,
389 },
390 },
391};
392
393/* ocpwp */ 371/* ocpwp */
394static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 372static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
395 .name = "ocpwp", 373 .name = "ocpwp",
@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
482 }, 460 },
483}; 461};
484 462
463/*
464 * 'debugss' class
465 * debug sub system
466 */
467static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
468 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
469 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
470};
471
472static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
473 .name = "debugss",
474};
475
476static struct omap_hwmod am33xx_debugss_hwmod = {
477 .name = "debugss",
478 .class = &am33xx_debugss_hwmod_class,
479 .clkdm_name = "l3_aon_clkdm",
480 .main_clk = "trace_clk_div_ck",
481 .prcm = {
482 .omap4 = {
483 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
484 .modulemode = MODULEMODE_SWCTRL,
485 },
486 },
487 .opt_clks = debugss_opt_clks,
488 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
489};
490
485/* 'smartreflex' class */ 491/* 'smartreflex' class */
486static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 492static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
487 .name = "smartreflex", 493 .name = "smartreflex",
@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1796 .user = OCP_USER_MPU | OCP_USER_SDMA, 1802 .user = OCP_USER_MPU | OCP_USER_SDMA,
1797}; 1803};
1798 1804
1805/* l3_main -> debugss */
1806static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
1807 {
1808 .pa_start = 0x4b000000,
1809 .pa_end = 0x4b000000 + SZ_16M - 1,
1810 .flags = ADDR_TYPE_RT
1811 },
1812 { }
1813};
1814
1815static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
1816 .master = &am33xx_l3_main_hwmod,
1817 .slave = &am33xx_debugss_hwmod,
1818 .clk = "dpll_core_m4_ck",
1819 .addr = am33xx_debugss_addrs,
1820 .user = OCP_USER_MPU,
1821};
1822
1799/* l4 wkup -> smartreflex0 */ 1823/* l4 wkup -> smartreflex0 */
1800static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { 1824static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
1801 .master = &am33xx_l4_wkup_hwmod, 1825 .master = &am33xx_l4_wkup_hwmod,
@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2470 &am33xx_pruss__l3_main, 2494 &am33xx_pruss__l3_main,
2471 &am33xx_wkup_m3__l4_wkup, 2495 &am33xx_wkup_m3__l4_wkup,
2472 &am33xx_gfx__l3_main, 2496 &am33xx_gfx__l3_main,
2497 &am33xx_l3_main__debugss,
2473 &am33xx_l4_wkup__wkup_m3, 2498 &am33xx_l4_wkup__wkup_m3,
2474 &am33xx_l4_wkup__control, 2499 &am33xx_l4_wkup__control,
2475 &am33xx_l4_wkup__smartreflex0, 2500 &am33xx_l4_wkup__smartreflex0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 3c70f5c1860f..cde415570e04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -32,7 +32,6 @@
32#include "cm1_54xx.h" 32#include "cm1_54xx.h"
33#include "cm2_54xx.h" 33#include "cm2_54xx.h"
34#include "prm54xx.h" 34#include "prm54xx.h"
35#include "prm-regbits-54xx.h"
36#include "i2c.h" 35#include "i2c.h"
37#include "mmc.h" 36#include "mmc.h"
38#include "wd_timer.h" 37#include "wd_timer.h"
@@ -741,6 +740,39 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
741}; 740};
742 741
743/* 742/*
743 * 'mailbox' class
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
749 .rev_offs = 0x0000,
750 .sysc_offs = 0x0010,
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
752 SYSC_HAS_SOFTRESET),
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
755};
756
757static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
758 .name = "mailbox",
759 .sysc = &omap54xx_mailbox_sysc,
760};
761
762/* mailbox */
763static struct omap_hwmod omap54xx_mailbox_hwmod = {
764 .name = "mailbox",
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
767 .prcm = {
768 .omap4 = {
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
771 },
772 },
773};
774
775/*
744 * 'mcbsp' class 776 * 'mcbsp' class
745 * multi channel buffered serial port controller 777 * multi channel buffered serial port controller
746 */ 778 */
@@ -1808,6 +1840,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1808 .user = OCP_USER_MPU | OCP_USER_SDMA, 1840 .user = OCP_USER_MPU | OCP_USER_SDMA,
1809}; 1841};
1810 1842
1843/* l4_cfg -> mailbox */
1844static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1845 .master = &omap54xx_l4_cfg_hwmod,
1846 .slave = &omap54xx_mailbox_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
1811/* l4_abe -> mcbsp1 */ 1851/* l4_abe -> mcbsp1 */
1812static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { 1852static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1813 .master = &omap54xx_l4_abe_hwmod, 1853 .master = &omap54xx_l4_abe_hwmod,
@@ -2108,6 +2148,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2108 &omap54xx_l4_per__i2c4, 2148 &omap54xx_l4_per__i2c4,
2109 &omap54xx_l4_per__i2c5, 2149 &omap54xx_l4_per__i2c5,
2110 &omap54xx_l4_wkup__kbd, 2150 &omap54xx_l4_wkup__kbd,
2151 &omap54xx_l4_cfg__mailbox,
2111 &omap54xx_l4_abe__mcbsp1, 2152 &omap54xx_l4_abe__mcbsp1,
2112 &omap54xx_l4_abe__mcbsp2, 2153 &omap54xx_l4_abe__mcbsp2,
2113 &omap54xx_l4_abe__mcbsp3, 2154 &omap54xx_l4_abe__mcbsp3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
new file mode 100644
index 000000000000..db32d5380b11
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -0,0 +1,2724 @@
1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
275/*
276 * 'dcan' class
277 *
278 */
279
280static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282};
283
284/* dcan1 */
285static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297};
298
299/* dcan2 */
300static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312};
313
314/*
315 * 'dma' class
316 *
317 */
318
319static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331};
332
333static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336};
337
338/* dma dev_attr */
339static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343};
344
345/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367};
368
369/*
370 * 'dss' class
371 *
372 */
373
374static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378};
379
380static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384};
385
386/* dss */
387static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390};
391
392static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399};
400
401static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417};
418
419/*
420 * 'dispc' class
421 * display controller
422 */
423
424static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435};
436
437static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440};
441
442/* dss_dispc */
443/* dss_dispc dev_attr */
444static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447};
448
449static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461};
462
463/*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476};
477
478static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481};
482
483/* dss_hdmi */
484
485static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487};
488
489static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502};
503
504/*
505 * 'elm' class
506 *
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519};
520
521static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524};
525
526/* elm */
527
528static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539};
540
541/*
542 * 'gpio' class
543 *
544 */
545
546static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556};
557
558static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562};
563
564/* gpio dev_attr */
565static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568};
569
570/* gpio1 */
571static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573};
574
575static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590};
591
592/* gpio2 */
593static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595};
596
597static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613};
614
615/* gpio3 */
616static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618};
619
620static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636};
637
638/* gpio4 */
639static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641};
642
643static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659};
660
661/* gpio5 */
662static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664};
665
666static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682};
683
684/* gpio6 */
685static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687};
688
689static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705};
706
707/* gpio7 */
708static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710};
711
712static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728};
729
730/* gpio8 */
731static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733};
734
735static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751};
752
753/*
754 * 'gpmc' class
755 *
756 */
757
758static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767};
768
769static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772};
773
774/* gpmc */
775
776static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789};
790
791/*
792 * 'hdq1w' class
793 *
794 */
795
796static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803};
804
805static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808};
809
810/* hdq1w */
811
812static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825};
826
827/*
828 * 'i2c' class
829 *
830 */
831
832static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842};
843
844static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849};
850
851/* i2c dev_attr */
852static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854};
855
856/* i2c1 */
857static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871};
872
873/* i2c2 */
874static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888};
889
890/* i2c3 */
891static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905};
906
907/* i2c4 */
908static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922};
923
924/* i2c5 */
925static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939};
940
941/*
942 * 'mcspi' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954};
955
956static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960};
961
962/* mcspi1 */
963/* mcspi1 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966};
967
968static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981};
982
983/* mcspi2 */
984/* mcspi2 dev_attr */
985static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987};
988
989static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002};
1003
1004/* mcspi3 */
1005/* mcspi3 dev_attr */
1006static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008};
1009
1010static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023};
1024
1025/* mcspi4 */
1026/* mcspi4 dev_attr */
1027static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029};
1030
1031static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044};
1045
1046/*
1047 * 'mmc' class
1048 *
1049 */
1050
1051static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061};
1062
1063static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066};
1067
1068/* mmc1 */
1069static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071};
1072
1073/* mmc1 dev_attr */
1074static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076};
1077
1078static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093};
1094
1095/* mmc2 */
1096static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098};
1099
1100static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114};
1115
1116/* mmc3 */
1117static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119};
1120
1121static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135};
1136
1137/* mmc4 */
1138static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140};
1141
1142static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156};
1157
1158/*
1159 * 'mpu' class
1160 *
1161 */
1162
1163static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165};
1166
1167/* mpu */
1168static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196};
1197
1198static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201};
1202
1203/* ocp2scp1 */
1204static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216};
1217
1218/*
1219 * 'qspi' class
1220 *
1221 */
1222
1223static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227 SIDLE_SMART_WKUP),
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1229};
1230
1231static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232 .name = "qspi",
1233 .sysc = &dra7xx_qspi_sysc,
1234};
1235
1236/* qspi */
1237static struct omap_hwmod dra7xx_qspi_hwmod = {
1238 .name = "qspi",
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249};
1250
1251/*
1252 * 'sata' class
1253 *
1254 */
1255
1256static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1263};
1264
1265static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266 .name = "sata",
1267 .sysc = &dra7xx_sata_sysc,
1268};
1269
1270/* sata */
1271static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273};
1274
1275static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata",
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290};
1291
1292/*
1293 * 'smartreflex' class
1294 *
1295 */
1296
1297/* The IP is not compliant to type1 / type2 scheme */
1298static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 .sidle_shift = 24,
1300 .enwkup_shift = 26,
1301};
1302
1303static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1309};
1310
1311static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1314 .rev = 2,
1315};
1316
1317/* smartreflex_core */
1318/* smartreflex_core dev_attr */
1319static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1321};
1322
1323static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1328 .prcm = {
1329 .omap4 = {
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .dev_attr = &smartreflex_core_dev_attr,
1336};
1337
1338/* smartreflex_mpu */
1339/* smartreflex_mpu dev_attr */
1340static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1342};
1343
1344static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1357};
1358
1359/*
1360 * 'spinlock' class
1361 *
1362 */
1363
1364static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1370 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1372 SIDLE_SMART_WKUP),
1373 .sysc_fields = &omap_hwmod_sysc_type1,
1374};
1375
1376static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1377 .name = "spinlock",
1378 .sysc = &dra7xx_spinlock_sysc,
1379};
1380
1381/* spinlock */
1382static struct omap_hwmod dra7xx_spinlock_hwmod = {
1383 .name = "spinlock",
1384 .class = &dra7xx_spinlock_hwmod_class,
1385 .clkdm_name = "l4cfg_clkdm",
1386 .main_clk = "l3_iclk_div",
1387 .prcm = {
1388 .omap4 = {
1389 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1390 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1391 },
1392 },
1393};
1394
1395/*
1396 * 'timer' class
1397 *
1398 * This class contains several variants: ['timer_1ms', 'timer_secure',
1399 * 'timer']
1400 */
1401
1402static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1403 .rev_offs = 0x0000,
1404 .sysc_offs = 0x0010,
1405 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1406 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408 SIDLE_SMART_WKUP),
1409 .sysc_fields = &omap_hwmod_sysc_type2,
1410};
1411
1412static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1413 .name = "timer",
1414 .sysc = &dra7xx_timer_1ms_sysc,
1415};
1416
1417static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1418 .rev_offs = 0x0000,
1419 .sysc_offs = 0x0010,
1420 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1421 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423 SIDLE_SMART_WKUP),
1424 .sysc_fields = &omap_hwmod_sysc_type2,
1425};
1426
1427static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1428 .name = "timer",
1429 .sysc = &dra7xx_timer_secure_sysc,
1430};
1431
1432static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1433 .rev_offs = 0x0000,
1434 .sysc_offs = 0x0010,
1435 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1436 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1437 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438 SIDLE_SMART_WKUP),
1439 .sysc_fields = &omap_hwmod_sysc_type2,
1440};
1441
1442static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1443 .name = "timer",
1444 .sysc = &dra7xx_timer_sysc,
1445};
1446
1447/* timer1 */
1448static struct omap_hwmod dra7xx_timer1_hwmod = {
1449 .name = "timer1",
1450 .class = &dra7xx_timer_1ms_hwmod_class,
1451 .clkdm_name = "wkupaon_clkdm",
1452 .main_clk = "timer1_gfclk_mux",
1453 .prcm = {
1454 .omap4 = {
1455 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1456 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1457 .modulemode = MODULEMODE_SWCTRL,
1458 },
1459 },
1460};
1461
1462/* timer2 */
1463static struct omap_hwmod dra7xx_timer2_hwmod = {
1464 .name = "timer2",
1465 .class = &dra7xx_timer_1ms_hwmod_class,
1466 .clkdm_name = "l4per_clkdm",
1467 .main_clk = "timer2_gfclk_mux",
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1473 },
1474 },
1475};
1476
1477/* timer3 */
1478static struct omap_hwmod dra7xx_timer3_hwmod = {
1479 .name = "timer3",
1480 .class = &dra7xx_timer_hwmod_class,
1481 .clkdm_name = "l4per_clkdm",
1482 .main_clk = "timer3_gfclk_mux",
1483 .prcm = {
1484 .omap4 = {
1485 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1486 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1487 .modulemode = MODULEMODE_SWCTRL,
1488 },
1489 },
1490};
1491
1492/* timer4 */
1493static struct omap_hwmod dra7xx_timer4_hwmod = {
1494 .name = "timer4",
1495 .class = &dra7xx_timer_secure_hwmod_class,
1496 .clkdm_name = "l4per_clkdm",
1497 .main_clk = "timer4_gfclk_mux",
1498 .prcm = {
1499 .omap4 = {
1500 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1501 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1502 .modulemode = MODULEMODE_SWCTRL,
1503 },
1504 },
1505};
1506
1507/* timer5 */
1508static struct omap_hwmod dra7xx_timer5_hwmod = {
1509 .name = "timer5",
1510 .class = &dra7xx_timer_hwmod_class,
1511 .clkdm_name = "ipu_clkdm",
1512 .main_clk = "timer5_gfclk_mux",
1513 .prcm = {
1514 .omap4 = {
1515 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1516 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520};
1521
1522/* timer6 */
1523static struct omap_hwmod dra7xx_timer6_hwmod = {
1524 .name = "timer6",
1525 .class = &dra7xx_timer_hwmod_class,
1526 .clkdm_name = "ipu_clkdm",
1527 .main_clk = "timer6_gfclk_mux",
1528 .prcm = {
1529 .omap4 = {
1530 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1531 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1532 .modulemode = MODULEMODE_SWCTRL,
1533 },
1534 },
1535};
1536
1537/* timer7 */
1538static struct omap_hwmod dra7xx_timer7_hwmod = {
1539 .name = "timer7",
1540 .class = &dra7xx_timer_hwmod_class,
1541 .clkdm_name = "ipu_clkdm",
1542 .main_clk = "timer7_gfclk_mux",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1546 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1547 .modulemode = MODULEMODE_SWCTRL,
1548 },
1549 },
1550};
1551
1552/* timer8 */
1553static struct omap_hwmod dra7xx_timer8_hwmod = {
1554 .name = "timer8",
1555 .class = &dra7xx_timer_hwmod_class,
1556 .clkdm_name = "ipu_clkdm",
1557 .main_clk = "timer8_gfclk_mux",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1561 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1562 .modulemode = MODULEMODE_SWCTRL,
1563 },
1564 },
1565};
1566
1567/* timer9 */
1568static struct omap_hwmod dra7xx_timer9_hwmod = {
1569 .name = "timer9",
1570 .class = &dra7xx_timer_hwmod_class,
1571 .clkdm_name = "l4per_clkdm",
1572 .main_clk = "timer9_gfclk_mux",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1577 .modulemode = MODULEMODE_SWCTRL,
1578 },
1579 },
1580};
1581
1582/* timer10 */
1583static struct omap_hwmod dra7xx_timer10_hwmod = {
1584 .name = "timer10",
1585 .class = &dra7xx_timer_1ms_hwmod_class,
1586 .clkdm_name = "l4per_clkdm",
1587 .main_clk = "timer10_gfclk_mux",
1588 .prcm = {
1589 .omap4 = {
1590 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595};
1596
1597/* timer11 */
1598static struct omap_hwmod dra7xx_timer11_hwmod = {
1599 .name = "timer11",
1600 .class = &dra7xx_timer_hwmod_class,
1601 .clkdm_name = "l4per_clkdm",
1602 .main_clk = "timer11_gfclk_mux",
1603 .prcm = {
1604 .omap4 = {
1605 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1606 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1607 .modulemode = MODULEMODE_SWCTRL,
1608 },
1609 },
1610};
1611
1612/*
1613 * 'uart' class
1614 *
1615 */
1616
1617static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1618 .rev_offs = 0x0050,
1619 .sysc_offs = 0x0054,
1620 .syss_offs = 0x0058,
1621 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1622 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1623 SYSS_HAS_RESET_STATUS),
1624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625 SIDLE_SMART_WKUP),
1626 .sysc_fields = &omap_hwmod_sysc_type1,
1627};
1628
1629static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1630 .name = "uart",
1631 .sysc = &dra7xx_uart_sysc,
1632};
1633
1634/* uart1 */
1635static struct omap_hwmod dra7xx_uart1_hwmod = {
1636 .name = "uart1",
1637 .class = &dra7xx_uart_hwmod_class,
1638 .clkdm_name = "l4per_clkdm",
1639 .main_clk = "uart1_gfclk_mux",
1640 .flags = HWMOD_SWSUP_SIDLE_ACT,
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1644 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648};
1649
1650/* uart2 */
1651static struct omap_hwmod dra7xx_uart2_hwmod = {
1652 .name = "uart2",
1653 .class = &dra7xx_uart_hwmod_class,
1654 .clkdm_name = "l4per_clkdm",
1655 .main_clk = "uart2_gfclk_mux",
1656 .flags = HWMOD_SWSUP_SIDLE_ACT,
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664};
1665
1666/* uart3 */
1667static struct omap_hwmod dra7xx_uart3_hwmod = {
1668 .name = "uart3",
1669 .class = &dra7xx_uart_hwmod_class,
1670 .clkdm_name = "l4per_clkdm",
1671 .main_clk = "uart3_gfclk_mux",
1672 .flags = HWMOD_SWSUP_SIDLE_ACT,
1673 .prcm = {
1674 .omap4 = {
1675 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1676 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1677 .modulemode = MODULEMODE_SWCTRL,
1678 },
1679 },
1680};
1681
1682/* uart4 */
1683static struct omap_hwmod dra7xx_uart4_hwmod = {
1684 .name = "uart4",
1685 .class = &dra7xx_uart_hwmod_class,
1686 .clkdm_name = "l4per_clkdm",
1687 .main_clk = "uart4_gfclk_mux",
1688 .flags = HWMOD_SWSUP_SIDLE_ACT,
1689 .prcm = {
1690 .omap4 = {
1691 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1692 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1693 .modulemode = MODULEMODE_SWCTRL,
1694 },
1695 },
1696};
1697
1698/* uart5 */
1699static struct omap_hwmod dra7xx_uart5_hwmod = {
1700 .name = "uart5",
1701 .class = &dra7xx_uart_hwmod_class,
1702 .clkdm_name = "l4per_clkdm",
1703 .main_clk = "uart5_gfclk_mux",
1704 .flags = HWMOD_SWSUP_SIDLE_ACT,
1705 .prcm = {
1706 .omap4 = {
1707 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1708 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1709 .modulemode = MODULEMODE_SWCTRL,
1710 },
1711 },
1712};
1713
1714/* uart6 */
1715static struct omap_hwmod dra7xx_uart6_hwmod = {
1716 .name = "uart6",
1717 .class = &dra7xx_uart_hwmod_class,
1718 .clkdm_name = "ipu_clkdm",
1719 .main_clk = "uart6_gfclk_mux",
1720 .flags = HWMOD_SWSUP_SIDLE_ACT,
1721 .prcm = {
1722 .omap4 = {
1723 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1724 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1725 .modulemode = MODULEMODE_SWCTRL,
1726 },
1727 },
1728};
1729
1730/*
1731 * 'usb_otg_ss' class
1732 *
1733 */
1734
1735static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1736 .name = "usb_otg_ss",
1737};
1738
1739/* usb_otg_ss1 */
1740static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1741 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1742};
1743
1744static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1745 .name = "usb_otg_ss1",
1746 .class = &dra7xx_usb_otg_ss_hwmod_class,
1747 .clkdm_name = "l3init_clkdm",
1748 .main_clk = "dpll_core_h13x2_ck",
1749 .prcm = {
1750 .omap4 = {
1751 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1752 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1753 .modulemode = MODULEMODE_HWCTRL,
1754 },
1755 },
1756 .opt_clks = usb_otg_ss1_opt_clks,
1757 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1758};
1759
1760/* usb_otg_ss2 */
1761static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1762 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1763};
1764
1765static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1766 .name = "usb_otg_ss2",
1767 .class = &dra7xx_usb_otg_ss_hwmod_class,
1768 .clkdm_name = "l3init_clkdm",
1769 .main_clk = "dpll_core_h13x2_ck",
1770 .prcm = {
1771 .omap4 = {
1772 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1773 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1774 .modulemode = MODULEMODE_HWCTRL,
1775 },
1776 },
1777 .opt_clks = usb_otg_ss2_opt_clks,
1778 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1779};
1780
1781/* usb_otg_ss3 */
1782static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1783 .name = "usb_otg_ss3",
1784 .class = &dra7xx_usb_otg_ss_hwmod_class,
1785 .clkdm_name = "l3init_clkdm",
1786 .main_clk = "dpll_core_h13x2_ck",
1787 .prcm = {
1788 .omap4 = {
1789 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1790 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1791 .modulemode = MODULEMODE_HWCTRL,
1792 },
1793 },
1794};
1795
1796/* usb_otg_ss4 */
1797static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1798 .name = "usb_otg_ss4",
1799 .class = &dra7xx_usb_otg_ss_hwmod_class,
1800 .clkdm_name = "l3init_clkdm",
1801 .main_clk = "dpll_core_h13x2_ck",
1802 .prcm = {
1803 .omap4 = {
1804 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1805 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1806 .modulemode = MODULEMODE_HWCTRL,
1807 },
1808 },
1809};
1810
1811/*
1812 * 'vcp' class
1813 *
1814 */
1815
1816static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1817 .name = "vcp",
1818};
1819
1820/* vcp1 */
1821static struct omap_hwmod dra7xx_vcp1_hwmod = {
1822 .name = "vcp1",
1823 .class = &dra7xx_vcp_hwmod_class,
1824 .clkdm_name = "l3main1_clkdm",
1825 .main_clk = "l3_iclk_div",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1829 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1830 },
1831 },
1832};
1833
1834/* vcp2 */
1835static struct omap_hwmod dra7xx_vcp2_hwmod = {
1836 .name = "vcp2",
1837 .class = &dra7xx_vcp_hwmod_class,
1838 .clkdm_name = "l3main1_clkdm",
1839 .main_clk = "l3_iclk_div",
1840 .prcm = {
1841 .omap4 = {
1842 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1843 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1844 },
1845 },
1846};
1847
1848/*
1849 * 'wd_timer' class
1850 *
1851 */
1852
1853static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1854 .rev_offs = 0x0000,
1855 .sysc_offs = 0x0010,
1856 .syss_offs = 0x0014,
1857 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1858 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1859 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860 SIDLE_SMART_WKUP),
1861 .sysc_fields = &omap_hwmod_sysc_type1,
1862};
1863
1864static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1865 .name = "wd_timer",
1866 .sysc = &dra7xx_wd_timer_sysc,
1867 .pre_shutdown = &omap2_wd_timer_disable,
1868 .reset = &omap2_wd_timer_reset,
1869};
1870
1871/* wd_timer2 */
1872static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1873 .name = "wd_timer2",
1874 .class = &dra7xx_wd_timer_hwmod_class,
1875 .clkdm_name = "wkupaon_clkdm",
1876 .main_clk = "sys_32k_ck",
1877 .prcm = {
1878 .omap4 = {
1879 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1880 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1881 .modulemode = MODULEMODE_SWCTRL,
1882 },
1883 },
1884};
1885
1886
1887/*
1888 * Interfaces
1889 */
1890
1891/* l3_main_2 -> l3_instr */
1892static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1893 .master = &dra7xx_l3_main_2_hwmod,
1894 .slave = &dra7xx_l3_instr_hwmod,
1895 .clk = "l3_iclk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_cfg -> l3_main_1 */
1900static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1901 .master = &dra7xx_l4_cfg_hwmod,
1902 .slave = &dra7xx_l3_main_1_hwmod,
1903 .clk = "l3_iclk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* mpu -> l3_main_1 */
1908static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1909 .master = &dra7xx_mpu_hwmod,
1910 .slave = &dra7xx_l3_main_1_hwmod,
1911 .clk = "l3_iclk_div",
1912 .user = OCP_USER_MPU,
1913};
1914
1915/* l3_main_1 -> l3_main_2 */
1916static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1917 .master = &dra7xx_l3_main_1_hwmod,
1918 .slave = &dra7xx_l3_main_2_hwmod,
1919 .clk = "l3_iclk_div",
1920 .user = OCP_USER_MPU,
1921};
1922
1923/* l4_cfg -> l3_main_2 */
1924static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1925 .master = &dra7xx_l4_cfg_hwmod,
1926 .slave = &dra7xx_l3_main_2_hwmod,
1927 .clk = "l3_iclk_div",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l3_main_1 -> l4_cfg */
1932static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1933 .master = &dra7xx_l3_main_1_hwmod,
1934 .slave = &dra7xx_l4_cfg_hwmod,
1935 .clk = "l3_iclk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l3_main_1 -> l4_per1 */
1940static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1941 .master = &dra7xx_l3_main_1_hwmod,
1942 .slave = &dra7xx_l4_per1_hwmod,
1943 .clk = "l3_iclk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l3_main_1 -> l4_per2 */
1948static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1949 .master = &dra7xx_l3_main_1_hwmod,
1950 .slave = &dra7xx_l4_per2_hwmod,
1951 .clk = "l3_iclk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l3_main_1 -> l4_per3 */
1956static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1957 .master = &dra7xx_l3_main_1_hwmod,
1958 .slave = &dra7xx_l4_per3_hwmod,
1959 .clk = "l3_iclk_div",
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1961};
1962
1963/* l3_main_1 -> l4_wkup */
1964static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1965 .master = &dra7xx_l3_main_1_hwmod,
1966 .slave = &dra7xx_l4_wkup_hwmod,
1967 .clk = "wkupaon_iclk_mux",
1968 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969};
1970
1971/* l4_per2 -> atl */
1972static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1973 .master = &dra7xx_l4_per2_hwmod,
1974 .slave = &dra7xx_atl_hwmod,
1975 .clk = "l3_iclk_div",
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977};
1978
1979/* l3_main_1 -> bb2d */
1980static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1981 .master = &dra7xx_l3_main_1_hwmod,
1982 .slave = &dra7xx_bb2d_hwmod,
1983 .clk = "l3_iclk_div",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* l4_wkup -> counter_32k */
1988static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1989 .master = &dra7xx_l4_wkup_hwmod,
1990 .slave = &dra7xx_counter_32k_hwmod,
1991 .clk = "wkupaon_iclk_mux",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_wkup -> ctrl_module_wkup */
1996static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1997 .master = &dra7xx_l4_wkup_hwmod,
1998 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1999 .clk = "wkupaon_iclk_mux",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_wkup -> dcan1 */
2004static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2005 .master = &dra7xx_l4_wkup_hwmod,
2006 .slave = &dra7xx_dcan1_hwmod,
2007 .clk = "wkupaon_iclk_mux",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per2 -> dcan2 */
2012static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2013 .master = &dra7xx_l4_per2_hwmod,
2014 .slave = &dra7xx_dcan2_hwmod,
2015 .clk = "l3_iclk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2020 {
2021 .pa_start = 0x4a056000,
2022 .pa_end = 0x4a056fff,
2023 .flags = ADDR_TYPE_RT
2024 },
2025 { }
2026};
2027
2028/* l4_cfg -> dma_system */
2029static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2030 .master = &dra7xx_l4_cfg_hwmod,
2031 .slave = &dra7xx_dma_system_hwmod,
2032 .clk = "l3_iclk_div",
2033 .addr = dra7xx_dma_system_addrs,
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2038 {
2039 .name = "family",
2040 .pa_start = 0x58000000,
2041 .pa_end = 0x5800007f,
2042 .flags = ADDR_TYPE_RT
2043 },
2044};
2045
2046/* l3_main_1 -> dss */
2047static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2048 .master = &dra7xx_l3_main_1_hwmod,
2049 .slave = &dra7xx_dss_hwmod,
2050 .clk = "l3_iclk_div",
2051 .addr = dra7xx_dss_addrs,
2052 .user = OCP_USER_MPU | OCP_USER_SDMA,
2053};
2054
2055static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2056 {
2057 .name = "dispc",
2058 .pa_start = 0x58001000,
2059 .pa_end = 0x58001fff,
2060 .flags = ADDR_TYPE_RT
2061 },
2062};
2063
2064/* l3_main_1 -> dispc */
2065static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2066 .master = &dra7xx_l3_main_1_hwmod,
2067 .slave = &dra7xx_dss_dispc_hwmod,
2068 .clk = "l3_iclk_div",
2069 .addr = dra7xx_dss_dispc_addrs,
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2071};
2072
2073static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2074 {
2075 .name = "hdmi_wp",
2076 .pa_start = 0x58040000,
2077 .pa_end = 0x580400ff,
2078 .flags = ADDR_TYPE_RT
2079 },
2080 { }
2081};
2082
2083/* l3_main_1 -> dispc */
2084static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2085 .master = &dra7xx_l3_main_1_hwmod,
2086 .slave = &dra7xx_dss_hdmi_hwmod,
2087 .clk = "l3_iclk_div",
2088 .addr = dra7xx_dss_hdmi_addrs,
2089 .user = OCP_USER_MPU | OCP_USER_SDMA,
2090};
2091
2092static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2093 {
2094 .pa_start = 0x48078000,
2095 .pa_end = 0x48078fff,
2096 .flags = ADDR_TYPE_RT
2097 },
2098 { }
2099};
2100
2101/* l4_per1 -> elm */
2102static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2103 .master = &dra7xx_l4_per1_hwmod,
2104 .slave = &dra7xx_elm_hwmod,
2105 .clk = "l3_iclk_div",
2106 .addr = dra7xx_elm_addrs,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* l4_wkup -> gpio1 */
2111static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2112 .master = &dra7xx_l4_wkup_hwmod,
2113 .slave = &dra7xx_gpio1_hwmod,
2114 .clk = "wkupaon_iclk_mux",
2115 .user = OCP_USER_MPU | OCP_USER_SDMA,
2116};
2117
2118/* l4_per1 -> gpio2 */
2119static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2120 .master = &dra7xx_l4_per1_hwmod,
2121 .slave = &dra7xx_gpio2_hwmod,
2122 .clk = "l3_iclk_div",
2123 .user = OCP_USER_MPU | OCP_USER_SDMA,
2124};
2125
2126/* l4_per1 -> gpio3 */
2127static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2128 .master = &dra7xx_l4_per1_hwmod,
2129 .slave = &dra7xx_gpio3_hwmod,
2130 .clk = "l3_iclk_div",
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132};
2133
2134/* l4_per1 -> gpio4 */
2135static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2136 .master = &dra7xx_l4_per1_hwmod,
2137 .slave = &dra7xx_gpio4_hwmod,
2138 .clk = "l3_iclk_div",
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140};
2141
2142/* l4_per1 -> gpio5 */
2143static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2144 .master = &dra7xx_l4_per1_hwmod,
2145 .slave = &dra7xx_gpio5_hwmod,
2146 .clk = "l3_iclk_div",
2147 .user = OCP_USER_MPU | OCP_USER_SDMA,
2148};
2149
2150/* l4_per1 -> gpio6 */
2151static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2152 .master = &dra7xx_l4_per1_hwmod,
2153 .slave = &dra7xx_gpio6_hwmod,
2154 .clk = "l3_iclk_div",
2155 .user = OCP_USER_MPU | OCP_USER_SDMA,
2156};
2157
2158/* l4_per1 -> gpio7 */
2159static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2160 .master = &dra7xx_l4_per1_hwmod,
2161 .slave = &dra7xx_gpio7_hwmod,
2162 .clk = "l3_iclk_div",
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164};
2165
2166/* l4_per1 -> gpio8 */
2167static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2168 .master = &dra7xx_l4_per1_hwmod,
2169 .slave = &dra7xx_gpio8_hwmod,
2170 .clk = "l3_iclk_div",
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172};
2173
2174static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2175 {
2176 .pa_start = 0x50000000,
2177 .pa_end = 0x500003ff,
2178 .flags = ADDR_TYPE_RT
2179 },
2180 { }
2181};
2182
2183/* l3_main_1 -> gpmc */
2184static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2185 .master = &dra7xx_l3_main_1_hwmod,
2186 .slave = &dra7xx_gpmc_hwmod,
2187 .clk = "l3_iclk_div",
2188 .addr = dra7xx_gpmc_addrs,
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2190};
2191
2192static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2193 {
2194 .pa_start = 0x480b2000,
2195 .pa_end = 0x480b201f,
2196 .flags = ADDR_TYPE_RT
2197 },
2198 { }
2199};
2200
2201/* l4_per1 -> hdq1w */
2202static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2203 .master = &dra7xx_l4_per1_hwmod,
2204 .slave = &dra7xx_hdq1w_hwmod,
2205 .clk = "l3_iclk_div",
2206 .addr = dra7xx_hdq1w_addrs,
2207 .user = OCP_USER_MPU | OCP_USER_SDMA,
2208};
2209
2210/* l4_per1 -> i2c1 */
2211static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2212 .master = &dra7xx_l4_per1_hwmod,
2213 .slave = &dra7xx_i2c1_hwmod,
2214 .clk = "l3_iclk_div",
2215 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216};
2217
2218/* l4_per1 -> i2c2 */
2219static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2220 .master = &dra7xx_l4_per1_hwmod,
2221 .slave = &dra7xx_i2c2_hwmod,
2222 .clk = "l3_iclk_div",
2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2224};
2225
2226/* l4_per1 -> i2c3 */
2227static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2228 .master = &dra7xx_l4_per1_hwmod,
2229 .slave = &dra7xx_i2c3_hwmod,
2230 .clk = "l3_iclk_div",
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232};
2233
2234/* l4_per1 -> i2c4 */
2235static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2236 .master = &dra7xx_l4_per1_hwmod,
2237 .slave = &dra7xx_i2c4_hwmod,
2238 .clk = "l3_iclk_div",
2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240};
2241
2242/* l4_per1 -> i2c5 */
2243static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2244 .master = &dra7xx_l4_per1_hwmod,
2245 .slave = &dra7xx_i2c5_hwmod,
2246 .clk = "l3_iclk_div",
2247 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248};
2249
2250/* l4_per1 -> mcspi1 */
2251static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2252 .master = &dra7xx_l4_per1_hwmod,
2253 .slave = &dra7xx_mcspi1_hwmod,
2254 .clk = "l3_iclk_div",
2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256};
2257
2258/* l4_per1 -> mcspi2 */
2259static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2260 .master = &dra7xx_l4_per1_hwmod,
2261 .slave = &dra7xx_mcspi2_hwmod,
2262 .clk = "l3_iclk_div",
2263 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264};
2265
2266/* l4_per1 -> mcspi3 */
2267static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2268 .master = &dra7xx_l4_per1_hwmod,
2269 .slave = &dra7xx_mcspi3_hwmod,
2270 .clk = "l3_iclk_div",
2271 .user = OCP_USER_MPU | OCP_USER_SDMA,
2272};
2273
2274/* l4_per1 -> mcspi4 */
2275static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2276 .master = &dra7xx_l4_per1_hwmod,
2277 .slave = &dra7xx_mcspi4_hwmod,
2278 .clk = "l3_iclk_div",
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280};
2281
2282/* l4_per1 -> mmc1 */
2283static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2284 .master = &dra7xx_l4_per1_hwmod,
2285 .slave = &dra7xx_mmc1_hwmod,
2286 .clk = "l3_iclk_div",
2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
2290/* l4_per1 -> mmc2 */
2291static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2292 .master = &dra7xx_l4_per1_hwmod,
2293 .slave = &dra7xx_mmc2_hwmod,
2294 .clk = "l3_iclk_div",
2295 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296};
2297
2298/* l4_per1 -> mmc3 */
2299static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2300 .master = &dra7xx_l4_per1_hwmod,
2301 .slave = &dra7xx_mmc3_hwmod,
2302 .clk = "l3_iclk_div",
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304};
2305
2306/* l4_per1 -> mmc4 */
2307static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2308 .master = &dra7xx_l4_per1_hwmod,
2309 .slave = &dra7xx_mmc4_hwmod,
2310 .clk = "l3_iclk_div",
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312};
2313
2314/* l4_cfg -> mpu */
2315static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2316 .master = &dra7xx_l4_cfg_hwmod,
2317 .slave = &dra7xx_mpu_hwmod,
2318 .clk = "l3_iclk_div",
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320};
2321
2322static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2323 {
2324 .pa_start = 0x4a080000,
2325 .pa_end = 0x4a08001f,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329};
2330
2331/* l4_cfg -> ocp2scp1 */
2332static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2333 .master = &dra7xx_l4_cfg_hwmod,
2334 .slave = &dra7xx_ocp2scp1_hwmod,
2335 .clk = "l4_root_clk_div",
2336 .addr = dra7xx_ocp2scp1_addrs,
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2341 {
2342 .pa_start = 0x4b300000,
2343 .pa_end = 0x4b30007f,
2344 .flags = ADDR_TYPE_RT
2345 },
2346 { }
2347};
2348
2349/* l3_main_1 -> qspi */
2350static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2351 .master = &dra7xx_l3_main_1_hwmod,
2352 .slave = &dra7xx_qspi_hwmod,
2353 .clk = "l3_iclk_div",
2354 .addr = dra7xx_qspi_addrs,
2355 .user = OCP_USER_MPU | OCP_USER_SDMA,
2356};
2357
2358static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2359 {
2360 .name = "sysc",
2361 .pa_start = 0x4a141100,
2362 .pa_end = 0x4a141107,
2363 .flags = ADDR_TYPE_RT
2364 },
2365 { }
2366};
2367
2368/* l4_cfg -> sata */
2369static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2370 .master = &dra7xx_l4_cfg_hwmod,
2371 .slave = &dra7xx_sata_hwmod,
2372 .clk = "l3_iclk_div",
2373 .addr = dra7xx_sata_addrs,
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2375};
2376
2377static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2378 {
2379 .pa_start = 0x4a0dd000,
2380 .pa_end = 0x4a0dd07f,
2381 .flags = ADDR_TYPE_RT
2382 },
2383 { }
2384};
2385
2386/* l4_cfg -> smartreflex_core */
2387static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2388 .master = &dra7xx_l4_cfg_hwmod,
2389 .slave = &dra7xx_smartreflex_core_hwmod,
2390 .clk = "l4_root_clk_div",
2391 .addr = dra7xx_smartreflex_core_addrs,
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393};
2394
2395static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2396 {
2397 .pa_start = 0x4a0d9000,
2398 .pa_end = 0x4a0d907f,
2399 .flags = ADDR_TYPE_RT
2400 },
2401 { }
2402};
2403
2404/* l4_cfg -> smartreflex_mpu */
2405static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2406 .master = &dra7xx_l4_cfg_hwmod,
2407 .slave = &dra7xx_smartreflex_mpu_hwmod,
2408 .clk = "l4_root_clk_div",
2409 .addr = dra7xx_smartreflex_mpu_addrs,
2410 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411};
2412
2413static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2414 {
2415 .pa_start = 0x4a0f6000,
2416 .pa_end = 0x4a0f6fff,
2417 .flags = ADDR_TYPE_RT
2418 },
2419 { }
2420};
2421
2422/* l4_cfg -> spinlock */
2423static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2424 .master = &dra7xx_l4_cfg_hwmod,
2425 .slave = &dra7xx_spinlock_hwmod,
2426 .clk = "l3_iclk_div",
2427 .addr = dra7xx_spinlock_addrs,
2428 .user = OCP_USER_MPU | OCP_USER_SDMA,
2429};
2430
2431/* l4_wkup -> timer1 */
2432static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2433 .master = &dra7xx_l4_wkup_hwmod,
2434 .slave = &dra7xx_timer1_hwmod,
2435 .clk = "wkupaon_iclk_mux",
2436 .user = OCP_USER_MPU | OCP_USER_SDMA,
2437};
2438
2439/* l4_per1 -> timer2 */
2440static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2441 .master = &dra7xx_l4_per1_hwmod,
2442 .slave = &dra7xx_timer2_hwmod,
2443 .clk = "l3_iclk_div",
2444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2445};
2446
2447/* l4_per1 -> timer3 */
2448static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2449 .master = &dra7xx_l4_per1_hwmod,
2450 .slave = &dra7xx_timer3_hwmod,
2451 .clk = "l3_iclk_div",
2452 .user = OCP_USER_MPU | OCP_USER_SDMA,
2453};
2454
2455/* l4_per1 -> timer4 */
2456static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2457 .master = &dra7xx_l4_per1_hwmod,
2458 .slave = &dra7xx_timer4_hwmod,
2459 .clk = "l3_iclk_div",
2460 .user = OCP_USER_MPU | OCP_USER_SDMA,
2461};
2462
2463/* l4_per3 -> timer5 */
2464static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2465 .master = &dra7xx_l4_per3_hwmod,
2466 .slave = &dra7xx_timer5_hwmod,
2467 .clk = "l3_iclk_div",
2468 .user = OCP_USER_MPU | OCP_USER_SDMA,
2469};
2470
2471/* l4_per3 -> timer6 */
2472static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2473 .master = &dra7xx_l4_per3_hwmod,
2474 .slave = &dra7xx_timer6_hwmod,
2475 .clk = "l3_iclk_div",
2476 .user = OCP_USER_MPU | OCP_USER_SDMA,
2477};
2478
2479/* l4_per3 -> timer7 */
2480static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2481 .master = &dra7xx_l4_per3_hwmod,
2482 .slave = &dra7xx_timer7_hwmod,
2483 .clk = "l3_iclk_div",
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485};
2486
2487/* l4_per3 -> timer8 */
2488static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2489 .master = &dra7xx_l4_per3_hwmod,
2490 .slave = &dra7xx_timer8_hwmod,
2491 .clk = "l3_iclk_div",
2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493};
2494
2495/* l4_per1 -> timer9 */
2496static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2497 .master = &dra7xx_l4_per1_hwmod,
2498 .slave = &dra7xx_timer9_hwmod,
2499 .clk = "l3_iclk_div",
2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
2501};
2502
2503/* l4_per1 -> timer10 */
2504static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2505 .master = &dra7xx_l4_per1_hwmod,
2506 .slave = &dra7xx_timer10_hwmod,
2507 .clk = "l3_iclk_div",
2508 .user = OCP_USER_MPU | OCP_USER_SDMA,
2509};
2510
2511/* l4_per1 -> timer11 */
2512static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2513 .master = &dra7xx_l4_per1_hwmod,
2514 .slave = &dra7xx_timer11_hwmod,
2515 .clk = "l3_iclk_div",
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517};
2518
2519/* l4_per1 -> uart1 */
2520static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2521 .master = &dra7xx_l4_per1_hwmod,
2522 .slave = &dra7xx_uart1_hwmod,
2523 .clk = "l3_iclk_div",
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* l4_per1 -> uart2 */
2528static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2529 .master = &dra7xx_l4_per1_hwmod,
2530 .slave = &dra7xx_uart2_hwmod,
2531 .clk = "l3_iclk_div",
2532 .user = OCP_USER_MPU | OCP_USER_SDMA,
2533};
2534
2535/* l4_per1 -> uart3 */
2536static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2537 .master = &dra7xx_l4_per1_hwmod,
2538 .slave = &dra7xx_uart3_hwmod,
2539 .clk = "l3_iclk_div",
2540 .user = OCP_USER_MPU | OCP_USER_SDMA,
2541};
2542
2543/* l4_per1 -> uart4 */
2544static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2545 .master = &dra7xx_l4_per1_hwmod,
2546 .slave = &dra7xx_uart4_hwmod,
2547 .clk = "l3_iclk_div",
2548 .user = OCP_USER_MPU | OCP_USER_SDMA,
2549};
2550
2551/* l4_per1 -> uart5 */
2552static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2553 .master = &dra7xx_l4_per1_hwmod,
2554 .slave = &dra7xx_uart5_hwmod,
2555 .clk = "l3_iclk_div",
2556 .user = OCP_USER_MPU | OCP_USER_SDMA,
2557};
2558
2559/* l4_per1 -> uart6 */
2560static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2561 .master = &dra7xx_l4_per1_hwmod,
2562 .slave = &dra7xx_uart6_hwmod,
2563 .clk = "l3_iclk_div",
2564 .user = OCP_USER_MPU | OCP_USER_SDMA,
2565};
2566
2567/* l4_per3 -> usb_otg_ss1 */
2568static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2569 .master = &dra7xx_l4_per3_hwmod,
2570 .slave = &dra7xx_usb_otg_ss1_hwmod,
2571 .clk = "dpll_core_h13x2_ck",
2572 .user = OCP_USER_MPU | OCP_USER_SDMA,
2573};
2574
2575/* l4_per3 -> usb_otg_ss2 */
2576static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2577 .master = &dra7xx_l4_per3_hwmod,
2578 .slave = &dra7xx_usb_otg_ss2_hwmod,
2579 .clk = "dpll_core_h13x2_ck",
2580 .user = OCP_USER_MPU | OCP_USER_SDMA,
2581};
2582
2583/* l4_per3 -> usb_otg_ss3 */
2584static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2585 .master = &dra7xx_l4_per3_hwmod,
2586 .slave = &dra7xx_usb_otg_ss3_hwmod,
2587 .clk = "dpll_core_h13x2_ck",
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2589};
2590
2591/* l4_per3 -> usb_otg_ss4 */
2592static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2593 .master = &dra7xx_l4_per3_hwmod,
2594 .slave = &dra7xx_usb_otg_ss4_hwmod,
2595 .clk = "dpll_core_h13x2_ck",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597};
2598
2599/* l3_main_1 -> vcp1 */
2600static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2601 .master = &dra7xx_l3_main_1_hwmod,
2602 .slave = &dra7xx_vcp1_hwmod,
2603 .clk = "l3_iclk_div",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605};
2606
2607/* l4_per2 -> vcp1 */
2608static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2609 .master = &dra7xx_l4_per2_hwmod,
2610 .slave = &dra7xx_vcp1_hwmod,
2611 .clk = "l3_iclk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613};
2614
2615/* l3_main_1 -> vcp2 */
2616static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2617 .master = &dra7xx_l3_main_1_hwmod,
2618 .slave = &dra7xx_vcp2_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621};
2622
2623/* l4_per2 -> vcp2 */
2624static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2625 .master = &dra7xx_l4_per2_hwmod,
2626 .slave = &dra7xx_vcp2_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629};
2630
2631/* l4_wkup -> wd_timer2 */
2632static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2633 .master = &dra7xx_l4_wkup_hwmod,
2634 .slave = &dra7xx_wd_timer2_hwmod,
2635 .clk = "wkupaon_iclk_mux",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2640 &dra7xx_l3_main_2__l3_instr,
2641 &dra7xx_l4_cfg__l3_main_1,
2642 &dra7xx_mpu__l3_main_1,
2643 &dra7xx_l3_main_1__l3_main_2,
2644 &dra7xx_l4_cfg__l3_main_2,
2645 &dra7xx_l3_main_1__l4_cfg,
2646 &dra7xx_l3_main_1__l4_per1,
2647 &dra7xx_l3_main_1__l4_per2,
2648 &dra7xx_l3_main_1__l4_per3,
2649 &dra7xx_l3_main_1__l4_wkup,
2650 &dra7xx_l4_per2__atl,
2651 &dra7xx_l3_main_1__bb2d,
2652 &dra7xx_l4_wkup__counter_32k,
2653 &dra7xx_l4_wkup__ctrl_module_wkup,
2654 &dra7xx_l4_wkup__dcan1,
2655 &dra7xx_l4_per2__dcan2,
2656 &dra7xx_l4_cfg__dma_system,
2657 &dra7xx_l3_main_1__dss,
2658 &dra7xx_l3_main_1__dispc,
2659 &dra7xx_l3_main_1__hdmi,
2660 &dra7xx_l4_per1__elm,
2661 &dra7xx_l4_wkup__gpio1,
2662 &dra7xx_l4_per1__gpio2,
2663 &dra7xx_l4_per1__gpio3,
2664 &dra7xx_l4_per1__gpio4,
2665 &dra7xx_l4_per1__gpio5,
2666 &dra7xx_l4_per1__gpio6,
2667 &dra7xx_l4_per1__gpio7,
2668 &dra7xx_l4_per1__gpio8,
2669 &dra7xx_l3_main_1__gpmc,
2670 &dra7xx_l4_per1__hdq1w,
2671 &dra7xx_l4_per1__i2c1,
2672 &dra7xx_l4_per1__i2c2,
2673 &dra7xx_l4_per1__i2c3,
2674 &dra7xx_l4_per1__i2c4,
2675 &dra7xx_l4_per1__i2c5,
2676 &dra7xx_l4_per1__mcspi1,
2677 &dra7xx_l4_per1__mcspi2,
2678 &dra7xx_l4_per1__mcspi3,
2679 &dra7xx_l4_per1__mcspi4,
2680 &dra7xx_l4_per1__mmc1,
2681 &dra7xx_l4_per1__mmc2,
2682 &dra7xx_l4_per1__mmc3,
2683 &dra7xx_l4_per1__mmc4,
2684 &dra7xx_l4_cfg__mpu,
2685 &dra7xx_l4_cfg__ocp2scp1,
2686 &dra7xx_l3_main_1__qspi,
2687 &dra7xx_l4_cfg__sata,
2688 &dra7xx_l4_cfg__smartreflex_core,
2689 &dra7xx_l4_cfg__smartreflex_mpu,
2690 &dra7xx_l4_cfg__spinlock,
2691 &dra7xx_l4_wkup__timer1,
2692 &dra7xx_l4_per1__timer2,
2693 &dra7xx_l4_per1__timer3,
2694 &dra7xx_l4_per1__timer4,
2695 &dra7xx_l4_per3__timer5,
2696 &dra7xx_l4_per3__timer6,
2697 &dra7xx_l4_per3__timer7,
2698 &dra7xx_l4_per3__timer8,
2699 &dra7xx_l4_per1__timer9,
2700 &dra7xx_l4_per1__timer10,
2701 &dra7xx_l4_per1__timer11,
2702 &dra7xx_l4_per1__uart1,
2703 &dra7xx_l4_per1__uart2,
2704 &dra7xx_l4_per1__uart3,
2705 &dra7xx_l4_per1__uart4,
2706 &dra7xx_l4_per1__uart5,
2707 &dra7xx_l4_per1__uart6,
2708 &dra7xx_l4_per3__usb_otg_ss1,
2709 &dra7xx_l4_per3__usb_otg_ss2,
2710 &dra7xx_l4_per3__usb_otg_ss3,
2711 &dra7xx_l4_per3__usb_otg_ss4,
2712 &dra7xx_l3_main_1__vcp1,
2713 &dra7xx_l4_per2__vcp1,
2714 &dra7xx_l3_main_1__vcp2,
2715 &dra7xx_l4_per2__vcp2,
2716 &dra7xx_l4_wkup__wd_timer2,
2717 NULL,
2718};
2719
2720int __init dra7xx_hwmod_init(void)
2721{
2722 omap_hwmod_init();
2723 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2724}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index e4d7bd6f94b8..baf3d8bf6bea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
256extern void am33xx_powerdomains_init(void); 256extern void am33xx_powerdomains_init(void);
257extern void omap44xx_powerdomains_init(void); 257extern void omap44xx_powerdomains_init(void);
258extern void omap54xx_powerdomains_init(void); 258extern void omap54xx_powerdomains_init(void);
259extern void dra7xx_powerdomains_init(void);
259 260
260extern struct pwrdm_ops omap2_pwrdm_operations; 261extern struct pwrdm_ops omap2_pwrdm_operations;
261extern struct pwrdm_ops omap3_pwrdm_operations; 262extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e2d4bd804523..328c1037cb60 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = {
336 .voltdm = { .name = "core" }, 336 .voltdm = { .name = "core" },
337}; 337};
338 338
339static struct powerdomain alwon_81xx_pwrdm = {
340 .name = "alwon_pwrdm",
341 .prcm_offs = TI81XX_PRM_ALWON_MOD,
342 .pwrsts = PWRSTS_OFF_ON,
343 .voltdm = { .name = "core" },
344};
345
339static struct powerdomain device_81xx_pwrdm = { 346static struct powerdomain device_81xx_pwrdm = {
340 .name = "device_pwrdm", 347 .name = "device_pwrdm",
341 .prcm_offs = TI81XX_PRM_DEVICE_MOD, 348 .prcm_offs = TI81XX_PRM_DEVICE_MOD,
@@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
442}; 449};
443 450
444static struct powerdomain *powerdomains_ti81xx[] __initdata = { 451static struct powerdomain *powerdomains_ti81xx[] __initdata = {
452 &alwon_81xx_pwrdm,
445 &device_81xx_pwrdm, 453 &device_81xx_pwrdm,
446 &active_816x_pwrdm, 454 &active_816x_pwrdm,
447 &default_816x_pwrdm, 455 &default_816x_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains54xx_data.c b/arch/arm/mach-omap2/powerdomains54xx_data.c
index 81f8a7cc26ee..ce1d752af991 100644
--- a/arch/arm/mach-omap2/powerdomains54xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains54xx_data.c
@@ -25,7 +25,6 @@
25 25
26#include "prcm-common.h" 26#include "prcm-common.h"
27#include "prcm44xx.h" 27#include "prcm44xx.h"
28#include "prm-regbits-54xx.h"
29#include "prm54xx.h" 28#include "prm54xx.h"
30#include "prcm_mpu54xx.h" 29#include "prcm_mpu54xx.h"
31 30
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
new file mode 100644
index 000000000000..48151d1cfde0
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -0,0 +1,454 @@
1/*
2 * DRA7xx Power domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25
26#include "powerdomain.h"
27
28#include "prcm-common.h"
29#include "prcm44xx.h"
30#include "prm7xx.h"
31#include "prcm_mpu7xx.h"
32
33/* iva_7xx_pwrdm: IVA-HD power domain */
34static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm",
36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54};
55
56/* rtc_7xx_pwrdm: */
57static struct powerdomain rtc_7xx_pwrdm = {
58 .name = "rtc_pwrdm",
59 .prcm_offs = DRA7XX_PRM_RTC_INST,
60 .prcm_partition = DRA7XX_PRM_PARTITION,
61 .pwrsts = PWRSTS_ON,
62};
63
64/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
65static struct powerdomain custefuse_7xx_pwrdm = {
66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_OFF_ON,
70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
71};
72
73/* ipu_7xx_pwrdm: Audio back end power domain */
74static struct powerdomain ipu_7xx_pwrdm = {
75 .name = "ipu_pwrdm",
76 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_RET_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */
88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90};
91
92/* dss_7xx_pwrdm: Display subsystem power domain */
93static struct powerdomain dss_7xx_pwrdm = {
94 .name = "dss_pwrdm",
95 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_RET_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */
105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107};
108
109/* l4per_7xx_pwrdm: Target peripherals power domain */
110static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON,
115 .pwrsts_logic_ret = PWRSTS_OFF_RET,
116 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */
124 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126};
127
128/* gpu_7xx_pwrdm: 3D accelerator power domain */
129static struct powerdomain gpu_7xx_pwrdm = {
130 .name = "gpu_pwrdm",
131 .prcm_offs = DRA7XX_PRM_GPU_INST,
132 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */
140 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142};
143
144/* wkupaon_7xx_pwrdm: Wake-up power domain */
145static struct powerdomain wkupaon_7xx_pwrdm = {
146 .name = "wkupaon_pwrdm",
147 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
148 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON,
150 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */
155 },
156};
157
158/* core_7xx_pwrdm: CORE power domain */
159static struct powerdomain core_7xx_pwrdm = {
160 .name = "core_pwrdm",
161 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_RET_ON,
164 .pwrsts_logic_ret = PWRSTS_OFF_RET,
165 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
179 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181};
182
183/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
184static struct powerdomain coreaon_7xx_pwrdm = {
185 .name = "coreaon_pwrdm",
186 .prcm_offs = DRA7XX_PRM_COREAON_INST,
187 .prcm_partition = DRA7XX_PRM_PARTITION,
188 .pwrsts = PWRSTS_ON,
189};
190
191/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
192static struct powerdomain cpu0_7xx_pwrdm = {
193 .name = "cpu0_pwrdm",
194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
196 .pwrsts = PWRSTS_OFF_RET_ON,
197 .pwrsts_logic_ret = PWRSTS_OFF_RET,
198 .banks = 1,
199 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
201 },
202 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */
204 },
205};
206
207/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
208static struct powerdomain cpu1_7xx_pwrdm = {
209 .name = "cpu1_pwrdm",
210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
212 .pwrsts = PWRSTS_OFF_RET_ON,
213 .pwrsts_logic_ret = PWRSTS_OFF_RET,
214 .banks = 1,
215 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
217 },
218 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */
220 },
221};
222
223/* vpe_7xx_pwrdm: */
224static struct powerdomain vpe_7xx_pwrdm = {
225 .name = "vpe_pwrdm",
226 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */
236 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238};
239
240/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
241static struct powerdomain mpu_7xx_pwrdm = {
242 .name = "mpu_pwrdm",
243 .prcm_offs = DRA7XX_PRM_MPU_INST,
244 .prcm_partition = DRA7XX_PRM_PARTITION,
245 .pwrsts = PWRSTS_RET_ON,
246 .pwrsts_logic_ret = PWRSTS_OFF_RET,
247 .banks = 2,
248 .pwrsts_mem_ret = {
249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
250 [1] = PWRSTS_RET, /* mpu_ram */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */
255 },
256};
257
258/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
259static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON,
264 .pwrsts_logic_ret = PWRSTS_OFF_RET,
265 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
275 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277};
278
279/* eve3_7xx_pwrdm: */
280static struct powerdomain eve3_7xx_pwrdm = {
281 .name = "eve3_pwrdm",
282 .prcm_offs = DRA7XX_PRM_EVE3_INST,
283 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */
291 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293};
294
295/* emu_7xx_pwrdm: Emulation power domain */
296static struct powerdomain emu_7xx_pwrdm = {
297 .name = "emu_pwrdm",
298 .prcm_offs = DRA7XX_PRM_EMU_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */
307 },
308};
309
310/* dsp2_7xx_pwrdm: */
311static struct powerdomain dsp2_7xx_pwrdm = {
312 .name = "dsp2_pwrdm",
313 .prcm_offs = DRA7XX_PRM_DSP2_INST,
314 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
326 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328};
329
330/* dsp1_7xx_pwrdm: Tesla processor power domain */
331static struct powerdomain dsp1_7xx_pwrdm = {
332 .name = "dsp1_pwrdm",
333 .prcm_offs = DRA7XX_PRM_DSP1_INST,
334 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
346 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348};
349
350/* cam_7xx_pwrdm: Camera subsystem power domain */
351static struct powerdomain cam_7xx_pwrdm = {
352 .name = "cam_pwrdm",
353 .prcm_offs = DRA7XX_PRM_CAM_INST,
354 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */
362 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364};
365
366/* eve4_7xx_pwrdm: */
367static struct powerdomain eve4_7xx_pwrdm = {
368 .name = "eve4_pwrdm",
369 .prcm_offs = DRA7XX_PRM_EVE4_INST,
370 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */
378 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380};
381
382/* eve2_7xx_pwrdm: */
383static struct powerdomain eve2_7xx_pwrdm = {
384 .name = "eve2_pwrdm",
385 .prcm_offs = DRA7XX_PRM_EVE2_INST,
386 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */
394 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396};
397
398/* eve1_7xx_pwrdm: */
399static struct powerdomain eve1_7xx_pwrdm = {
400 .name = "eve1_pwrdm",
401 .prcm_offs = DRA7XX_PRM_EVE1_INST,
402 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */
410 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412};
413
414/*
415 * The following power domains are not under SW control
416 *
417 * mpuaon
418 * mmaon
419 */
420
421/* As powerdomains are added or removed above, this list must also be changed */
422static struct powerdomain *powerdomains_dra7xx[] __initdata = {
423 &iva_7xx_pwrdm,
424 &rtc_7xx_pwrdm,
425 &custefuse_7xx_pwrdm,
426 &ipu_7xx_pwrdm,
427 &dss_7xx_pwrdm,
428 &l4per_7xx_pwrdm,
429 &gpu_7xx_pwrdm,
430 &wkupaon_7xx_pwrdm,
431 &core_7xx_pwrdm,
432 &coreaon_7xx_pwrdm,
433 &cpu0_7xx_pwrdm,
434 &cpu1_7xx_pwrdm,
435 &vpe_7xx_pwrdm,
436 &mpu_7xx_pwrdm,
437 &l3init_7xx_pwrdm,
438 &eve3_7xx_pwrdm,
439 &emu_7xx_pwrdm,
440 &dsp2_7xx_pwrdm,
441 &dsp1_7xx_pwrdm,
442 &cam_7xx_pwrdm,
443 &eve4_7xx_pwrdm,
444 &eve2_7xx_pwrdm,
445 &eve1_7xx_pwrdm,
446 NULL
447};
448
449void __init dra7xx_powerdomains_init(void)
450{
451 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
452 pwrdm_register_pwrdms(powerdomains_dra7xx);
453 pwrdm_complete_init();
454}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index ff1ac4a82a04..0e841fd9498a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -58,6 +58,7 @@
58#define TI816X_PRM_IVAHD1_MOD 0x0d00 58#define TI816X_PRM_IVAHD1_MOD 0x0d00
59#define TI816X_PRM_IVAHD2_MOD 0x0e00 59#define TI816X_PRM_IVAHD2_MOD 0x0e00
60#define TI816X_PRM_SGX_MOD 0x0f00 60#define TI816X_PRM_SGX_MOD 0x0f00
61#define TI81XX_PRM_ALWON_MOD 0x1800
61 62
62/* 24XX register bits shared between CM & PRM registers */ 63/* 24XX register bits shared between CM & PRM registers */
63 64
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index f429cdd5a118..4fea2cfdf2c3 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -38,6 +38,11 @@
38#define OMAP54XX_SCRM_PARTITION 4 38#define OMAP54XX_SCRM_PARTITION 4
39#define OMAP54XX_PRCM_MPU_PARTITION 5 39#define OMAP54XX_PRCM_MPU_PARTITION 5
40 40
41#define DRA7XX_PRM_PARTITION 1
42#define DRA7XX_CM_CORE_AON_PARTITION 2
43#define DRA7XX_CM_CORE_PARTITION 3
44#define DRA7XX_MPU_PRCM_PARTITION 5
45
41/* 46/*
42 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition 47 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
43 * IDs, plus one 48 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
new file mode 100644
index 000000000000..9ebb5ce0878f
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -0,0 +1,78 @@
1/*
2 * DRA7xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
24
25#include "prcm_mpu_44xx_54xx.h"
26
27#define DRA7XX_PRCM_MPU_BASE 0x48243000
28
29#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
31
32/* MPU_PRCM instances */
33#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
34#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
35#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
36#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
37#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
38#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
42#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
43
44
45/* MPU_PRCM */
46
47/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
48#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
49
50/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
51#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
52#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
53
54/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
55#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
56#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
57#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
58#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
59#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
60
61/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
62#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
63#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
64#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
65
66/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
67#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
68#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
69#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
70#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
71#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
72
73/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
74#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
75#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
76#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
77
78#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h
index 91aa5106d637..37fc905c9636 100644
--- a/arch/arm/mach-omap2/prm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-24xx.h
@@ -16,274 +16,27 @@
16 16
17#include "prm2xxx.h" 17#include "prm2xxx.h"
18 18
19/* Bits shared between registers */
20
21/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
22#define OMAP24XX_VOLTTRANS_ST_MASK (1 << 2)
23#define OMAP24XX_WKUP2_ST_MASK (1 << 1)
24#define OMAP24XX_WKUP1_ST_MASK (1 << 0)
25
26/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
27#define OMAP24XX_VOLTTRANS_EN_MASK (1 << 2)
28#define OMAP24XX_WKUP2_EN_MASK (1 << 1)
29#define OMAP24XX_WKUP1_EN_MASK (1 << 0)
30
31/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
32#define OMAP24XX_EN_MPU_SHIFT 1
33#define OMAP24XX_EN_MPU_MASK (1 << 1)
34#define OMAP24XX_EN_CORE_SHIFT 0 19#define OMAP24XX_EN_CORE_SHIFT 0
35#define OMAP24XX_EN_CORE_MASK (1 << 0)
36
37/*
38 * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
39 * shared bits
40 */
41#define OMAP24XX_MEMONSTATE_SHIFT 10
42#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
43#define OMAP24XX_MEMRETSTATE_MASK (1 << 3)
44
45/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
46#define OMAP24XX_FORCESTATE_MASK (1 << 18) 20#define OMAP24XX_FORCESTATE_MASK (1 << 18)
47
48/*
49 * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
50 * PM_PWSTST_MDM shared bits
51 */
52#define OMAP24XX_CLKACTIVITY_MASK (1 << 19)
53
54/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
55#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
56#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
57
58/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
59#define OMAP2430_MEMSTATEST_SHIFT 10
60#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
61
62/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
63#define OMAP24XX_POWERSTATEST_SHIFT 0
64#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
65
66
67/* Bits specific to each register */
68
69/* PRCM_REVISION */
70#define OMAP24XX_REV_SHIFT 0
71#define OMAP24XX_REV_MASK (0xff << 0)
72
73/* PRCM_SYSCONFIG */
74#define OMAP24XX_AUTOIDLE_MASK (1 << 0) 21#define OMAP24XX_AUTOIDLE_MASK (1 << 0)
75
76/* PRCM_IRQSTATUS_MPU specific bits */
77#define OMAP2430_DPLL_RECAL_ST_MASK (1 << 6)
78#define OMAP24XX_TRANSITION_ST_MASK (1 << 5)
79#define OMAP24XX_EVGENOFF_ST_MASK (1 << 4)
80#define OMAP24XX_EVGENON_ST_MASK (1 << 3)
81
82/* PRCM_IRQENABLE_MPU specific bits */
83#define OMAP2430_DPLL_RECAL_EN_MASK (1 << 6)
84#define OMAP24XX_TRANSITION_EN_MASK (1 << 5)
85#define OMAP24XX_EVGENOFF_EN_MASK (1 << 4)
86#define OMAP24XX_EVGENON_EN_MASK (1 << 3)
87
88/* PRCM_VOLTCTRL */
89#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15) 22#define OMAP24XX_AUTO_EXTVOLT_MASK (1 << 15)
90#define OMAP24XX_FORCE_EXTVOLT_MASK (1 << 14)
91#define OMAP24XX_SETOFF_LEVEL_SHIFT 12 23#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
92#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
93#define OMAP24XX_MEMRETCTRL_MASK (1 << 8) 24#define OMAP24XX_MEMRETCTRL_MASK (1 << 8)
94#define OMAP24XX_SETRET_LEVEL_SHIFT 6 25#define OMAP24XX_SETRET_LEVEL_SHIFT 6
95#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
96#define OMAP24XX_VOLT_LEVEL_SHIFT 0 26#define OMAP24XX_VOLT_LEVEL_SHIFT 0
97#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
98
99/* PRCM_VOLTST */
100#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
101#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
102
103/* PRCM_CLKSRC_CTRL specific bits */
104
105/* PRCM_CLKOUT_CTRL */
106#define OMAP2420_CLKOUT2_EN_SHIFT 15 27#define OMAP2420_CLKOUT2_EN_SHIFT 15
107#define OMAP2420_CLKOUT2_EN_MASK (1 << 15)
108#define OMAP2420_CLKOUT2_DIV_SHIFT 11 28#define OMAP2420_CLKOUT2_DIV_SHIFT 11
109#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
110#define OMAP2420_CLKOUT2_DIV_WIDTH 3 29#define OMAP2420_CLKOUT2_DIV_WIDTH 3
111#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
112#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8) 30#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
113#define OMAP24XX_CLKOUT_EN_SHIFT 7 31#define OMAP24XX_CLKOUT_EN_SHIFT 7
114#define OMAP24XX_CLKOUT_EN_MASK (1 << 7)
115#define OMAP24XX_CLKOUT_DIV_SHIFT 3 32#define OMAP24XX_CLKOUT_DIV_SHIFT 3
116#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
117#define OMAP24XX_CLKOUT_DIV_WIDTH 3 33#define OMAP24XX_CLKOUT_DIV_WIDTH 3
118#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
119#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0) 34#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
120
121/* PRCM_CLKEMUL_CTRL */
122#define OMAP24XX_EMULATION_EN_SHIFT 0 35#define OMAP24XX_EMULATION_EN_SHIFT 0
123#define OMAP24XX_EMULATION_EN_MASK (1 << 0)
124
125/* PRCM_CLKCFG_CTRL */
126#define OMAP24XX_VALID_CONFIG_MASK (1 << 0)
127
128/* PRCM_CLKCFG_STATUS */
129#define OMAP24XX_CONFIG_STATUS_MASK (1 << 0)
130
131/* PRCM_VOLTSETUP specific bits */
132
133/* PRCM_CLKSSETUP specific bits */
134
135/* PRCM_POLCTRL */
136#define OMAP2420_CLKOUT2_POL_MASK (1 << 10)
137#define OMAP24XX_CLKOUT_POL_MASK (1 << 9)
138#define OMAP24XX_CLKREQ_POL_MASK (1 << 8)
139#define OMAP2430_USE_POWEROK_MASK (1 << 2)
140#define OMAP2430_POWEROK_POL_MASK (1 << 1)
141#define OMAP24XX_EXTVOL_POL_MASK (1 << 0)
142
143/* RM_RSTST_MPU specific bits */
144/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
145
146/* PM_WKDEP_MPU specific bits */
147#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5 36#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
148#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
149#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2 37#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
150#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
151
152/* PM_EVGENCTRL_MPU specific bits */
153
154/* PM_EVEGENONTIM_MPU specific bits */
155
156/* PM_EVEGENOFFTIM_MPU specific bits */
157
158/* PM_PWSTCTRL_MPU specific bits */
159#define OMAP2430_FORCESTATE_MASK (1 << 18)
160
161/* PM_PWSTST_MPU specific bits */
162/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
163
164/* PM_WKEN1_CORE specific bits */
165
166/* PM_WKEN2_CORE specific bits */
167
168/* PM_WKST1_CORE specific bits*/
169
170/* PM_WKST2_CORE specific bits */
171
172/* PM_WKDEP_CORE specific bits*/
173#define OMAP2430_PM_WKDEP_CORE_EN_MDM_MASK (1 << 5)
174#define OMAP24XX_PM_WKDEP_CORE_EN_GFX_MASK (1 << 3)
175#define OMAP24XX_PM_WKDEP_CORE_EN_DSP_MASK (1 << 2)
176
177/* PM_PWSTCTRL_CORE specific bits */
178#define OMAP24XX_MEMORYCHANGE_MASK (1 << 20)
179#define OMAP24XX_MEM3ONSTATE_SHIFT 14
180#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
181#define OMAP24XX_MEM2ONSTATE_SHIFT 12
182#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
183#define OMAP24XX_MEM1ONSTATE_SHIFT 10
184#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
185#define OMAP24XX_MEM3RETSTATE_MASK (1 << 5)
186#define OMAP24XX_MEM2RETSTATE_MASK (1 << 4)
187#define OMAP24XX_MEM1RETSTATE_MASK (1 << 3)
188
189/* PM_PWSTST_CORE specific bits */
190#define OMAP24XX_MEM3STATEST_SHIFT 14
191#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
192#define OMAP24XX_MEM2STATEST_SHIFT 12
193#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
194#define OMAP24XX_MEM1STATEST_SHIFT 10
195#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
196
197/* RM_RSTCTRL_GFX */
198#define OMAP24XX_GFX_RST_MASK (1 << 0)
199
200/* RM_RSTST_GFX specific bits */
201#define OMAP24XX_GFX_SW_RST_MASK (1 << 4)
202
203/* PM_PWSTCTRL_GFX specific bits */
204
205/* PM_WKDEP_GFX specific bits */
206/* 2430 often calls EN_WAKEUP "EN_WKUP" */
207
208/* RM_RSTCTRL_WKUP specific bits */
209
210/* RM_RSTTIME_WKUP specific bits */
211
212/* RM_RSTST_WKUP specific bits */
213/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
214#define OMAP24XX_EXTWMPU_RST_SHIFT 6 38#define OMAP24XX_EXTWMPU_RST_SHIFT 6
215#define OMAP24XX_EXTWMPU_RST_MASK (1 << 6)
216#define OMAP24XX_SECU_WD_RST_SHIFT 5 39#define OMAP24XX_SECU_WD_RST_SHIFT 5
217#define OMAP24XX_SECU_WD_RST_MASK (1 << 5)
218#define OMAP24XX_MPU_WD_RST_SHIFT 4 40#define OMAP24XX_MPU_WD_RST_SHIFT 4
219#define OMAP24XX_MPU_WD_RST_MASK (1 << 4)
220#define OMAP24XX_SECU_VIOL_RST_SHIFT 3 41#define OMAP24XX_SECU_VIOL_RST_SHIFT 3
221#define OMAP24XX_SECU_VIOL_RST_MASK (1 << 3)
222
223/* PM_WKEN_WKUP specific bits */
224
225/* PM_WKST_WKUP specific bits */
226
227/* RM_RSTCTRL_DSP */
228#define OMAP2420_RST_IVA_MASK (1 << 8)
229#define OMAP24XX_RST2_DSP_MASK (1 << 1)
230#define OMAP24XX_RST1_DSP_MASK (1 << 0)
231
232/* RM_RSTST_DSP specific bits */
233/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
234#define OMAP2420_IVA_SW_RST_MASK (1 << 8)
235#define OMAP24XX_DSP_SW_RST2_MASK (1 << 5)
236#define OMAP24XX_DSP_SW_RST1_MASK (1 << 4)
237
238/* PM_WKDEP_DSP specific bits */
239
240/* PM_PWSTCTRL_DSP specific bits */
241/* 2430 only: MEMONSTATE, MEMRETSTATE */
242#define OMAP2420_MEMIONSTATE_SHIFT 12
243#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
244#define OMAP2420_MEMIRETSTATE_MASK (1 << 4)
245
246/* PM_PWSTST_DSP specific bits */
247/* MEMSTATEST is 2430 only */
248#define OMAP2420_MEMISTATEST_SHIFT 12
249#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
250
251/* PRCM_IRQSTATUS_DSP specific bits */
252
253/* PRCM_IRQENABLE_DSP specific bits */
254
255/* RM_RSTCTRL_MDM */
256/* 2430 only */
257#define OMAP2430_PWRON1_MDM_MASK (1 << 1)
258#define OMAP2430_RST1_MDM_MASK (1 << 0)
259
260/* RM_RSTST_MDM specific bits */
261/* 2430 only */
262#define OMAP2430_MDM_SECU_VIOL_MASK (1 << 6)
263#define OMAP2430_MDM_SW_PWRON1_MASK (1 << 5)
264#define OMAP2430_MDM_SW_RST1_MASK (1 << 4)
265
266/* PM_WKEN_MDM */
267/* 2430 only */
268#define OMAP2430_PM_WKEN_MDM_EN_MDM_MASK (1 << 0)
269
270/* PM_WKST_MDM specific bits */
271/* 2430 only */
272
273/* PM_WKDEP_MDM specific bits */
274/* 2430 only */
275
276/* PM_PWSTCTRL_MDM specific bits */
277/* 2430 only */
278#define OMAP2430_KILLDOMAINWKUP_MASK (1 << 19)
279
280/* PM_PWSTST_MDM specific bits */
281/* 2430 only */
282
283/* PRCM_IRQSTATUS_IVA */
284/* 2420 only */
285
286/* PRCM_IRQENABLE_IVA */
287/* 2420 only */
288
289#endif 42#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
index 0221b5c20e87..84feecee4fe6 100644
--- a/arch/arm/mach-omap2/prm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -18,340 +18,35 @@
18 18
19#include "prm.h" 19#include "prm.h"
20 20
21/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
22#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT 1
23#define AM33XX_ABBOFF_ACT_EXPORT_MASK (1 << 1)
24
25/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
26#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT 2
27#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
28
29/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
30#define AM33XX_AIPOFF_SHIFT 8
31#define AM33XX_AIPOFF_MASK (1 << 8)
32
33/* Used by PM_WKUP_PWRSTST */
34#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT 17
35#define AM33XX_DEBUGSS_MEM_STATEST_MASK (0x3 << 17)
36
37/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
38#define AM33XX_DISABLE_RTA_EXPORT_SHIFT 0
39#define AM33XX_DISABLE_RTA_EXPORT_MASK (1 << 0)
40
41/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
42#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT 12
43#define AM33XX_DPLL_CORE_RECAL_EN_MASK (1 << 12)
44
45/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
46#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT 12
47#define AM33XX_DPLL_CORE_RECAL_ST_MASK (1 << 12)
48
49/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
50#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT 14
51#define AM33XX_DPLL_DDR_RECAL_EN_MASK (1 << 14)
52
53/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
54#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT 14
55#define AM33XX_DPLL_DDR_RECAL_ST_MASK (1 << 14)
56
57/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
58#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT 15
59#define AM33XX_DPLL_DISP_RECAL_EN_MASK (1 << 15)
60
61/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
62#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT 13
63#define AM33XX_DPLL_DISP_RECAL_ST_MASK (1 << 13)
64
65/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
66#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT 11
67#define AM33XX_DPLL_MPU_RECAL_EN_MASK (1 << 11)
68
69/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
70#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT 11
71#define AM33XX_DPLL_MPU_RECAL_ST_MASK (1 << 11)
72
73/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
74#define AM33XX_DPLL_PER_RECAL_EN_SHIFT 13
75#define AM33XX_DPLL_PER_RECAL_EN_MASK (1 << 13)
76
77/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
78#define AM33XX_DPLL_PER_RECAL_ST_SHIFT 15
79#define AM33XX_DPLL_PER_RECAL_ST_MASK (1 << 15)
80
81/* Used by RM_WKUP_RSTST */
82#define AM33XX_EMULATION_M3_RST_SHIFT 6
83#define AM33XX_EMULATION_M3_RST_MASK (1 << 6)
84
85/* Used by RM_MPU_RSTST */
86#define AM33XX_EMULATION_MPU_RST_SHIFT 5
87#define AM33XX_EMULATION_MPU_RST_MASK (1 << 5)
88
89/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
90#define AM33XX_ENFUNC1_EXPORT_SHIFT 3
91#define AM33XX_ENFUNC1_EXPORT_MASK (1 << 3)
92
93/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
94#define AM33XX_ENFUNC3_EXPORT_SHIFT 5
95#define AM33XX_ENFUNC3_EXPORT_MASK (1 << 5)
96
97/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
98#define AM33XX_ENFUNC4_SHIFT 6
99#define AM33XX_ENFUNC4_MASK (1 << 6)
100
101/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
102#define AM33XX_ENFUNC5_SHIFT 7
103#define AM33XX_ENFUNC5_MASK (1 << 7)
104
105/* Used by PRM_RSTST */
106#define AM33XX_EXTERNAL_WARM_RST_SHIFT 5
107#define AM33XX_EXTERNAL_WARM_RST_MASK (1 << 5)
108
109/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
110#define AM33XX_FORCEWKUP_EN_SHIFT 10
111#define AM33XX_FORCEWKUP_EN_MASK (1 << 10)
112
113/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
114#define AM33XX_FORCEWKUP_ST_SHIFT 10
115#define AM33XX_FORCEWKUP_ST_MASK (1 << 10)
116
117/* Used by PM_GFX_PWRSTCTRL */
118#define AM33XX_GFX_MEM_ONSTATE_SHIFT 17
119#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17) 21#define AM33XX_GFX_MEM_ONSTATE_MASK (0x3 << 17)
120
121/* Used by PM_GFX_PWRSTCTRL */
122#define AM33XX_GFX_MEM_RETSTATE_SHIFT 6
123#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6) 22#define AM33XX_GFX_MEM_RETSTATE_MASK (1 << 6)
124
125/* Used by PM_GFX_PWRSTST */
126#define AM33XX_GFX_MEM_STATEST_SHIFT 4
127#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4) 23#define AM33XX_GFX_MEM_STATEST_MASK (0x3 << 4)
128
129/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
130#define AM33XX_GFX_RST_SHIFT 0
131#define AM33XX_GFX_RST_MASK (1 << 0)
132
133/* Used by PRM_RSTST */
134#define AM33XX_GLOBAL_COLD_RST_SHIFT 0
135#define AM33XX_GLOBAL_COLD_RST_MASK (1 << 0)
136
137/* Used by PRM_RSTST */
138#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT 1
139#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1) 24#define AM33XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
140 25#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
141/* Used by RM_WKUP_RSTST */
142#define AM33XX_ICECRUSHER_M3_RST_SHIFT 7
143#define AM33XX_ICECRUSHER_M3_RST_MASK (1 << 7)
144
145/* Used by RM_MPU_RSTST */
146#define AM33XX_ICECRUSHER_MPU_RST_SHIFT 6
147#define AM33XX_ICECRUSHER_MPU_RST_MASK (1 << 6)
148
149/* Used by PRM_RSTST */
150#define AM33XX_ICEPICK_RST_SHIFT 9
151#define AM33XX_ICEPICK_RST_MASK (1 << 9)
152
153/* Used by RM_PER_RSTCTRL */
154#define AM33XX_PRUSS_LRST_SHIFT 1
155#define AM33XX_PRUSS_LRST_MASK (1 << 1)
156
157/* Used by PM_PER_PWRSTCTRL */
158#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT 5
159#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5) 26#define AM33XX_PRUSS_MEM_ONSTATE_MASK (0x3 << 5)
160
161/* Used by PM_PER_PWRSTCTRL */
162#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT 7
163#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7) 27#define AM33XX_PRUSS_MEM_RETSTATE_MASK (1 << 7)
164
165/* Used by PM_PER_PWRSTST */
166#define AM33XX_PRUSS_MEM_STATEST_SHIFT 23
167#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23) 28#define AM33XX_PRUSS_MEM_STATEST_MASK (0x3 << 23)
168
169/*
170 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
171 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
172 */
173#define AM33XX_INTRANSITION_SHIFT 20
174#define AM33XX_INTRANSITION_MASK (1 << 20)
175
176/* Used by PM_CEFUSE_PWRSTST */
177#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24 29#define AM33XX_LASTPOWERSTATEENTERED_SHIFT 24
178#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 30#define AM33XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
179
180/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
181#define AM33XX_LOGICRETSTATE_SHIFT 2
182#define AM33XX_LOGICRETSTATE_MASK (1 << 2) 31#define AM33XX_LOGICRETSTATE_MASK (1 << 2)
183
184/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
185#define AM33XX_LOGICRETSTATE_3_3_SHIFT 3
186#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3) 32#define AM33XX_LOGICRETSTATE_3_3_MASK (1 << 3)
187
188/*
189 * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
190 * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
191 */
192#define AM33XX_LOGICSTATEST_SHIFT 2 33#define AM33XX_LOGICSTATEST_SHIFT 2
193#define AM33XX_LOGICSTATEST_MASK (1 << 2) 34#define AM33XX_LOGICSTATEST_MASK (1 << 2)
194
195/*
196 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
197 * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
198 */
199#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4 35#define AM33XX_LOWPOWERSTATECHANGE_SHIFT 4
200#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4) 36#define AM33XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
201
202/* Used by PM_MPU_PWRSTCTRL */
203#define AM33XX_MPU_L1_ONSTATE_SHIFT 18
204#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18) 37#define AM33XX_MPU_L1_ONSTATE_MASK (0x3 << 18)
205
206/* Used by PM_MPU_PWRSTCTRL */
207#define AM33XX_MPU_L1_RETSTATE_SHIFT 22
208#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22) 38#define AM33XX_MPU_L1_RETSTATE_MASK (1 << 22)
209
210/* Used by PM_MPU_PWRSTST */
211#define AM33XX_MPU_L1_STATEST_SHIFT 6
212#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6) 39#define AM33XX_MPU_L1_STATEST_MASK (0x3 << 6)
213
214/* Used by PM_MPU_PWRSTCTRL */
215#define AM33XX_MPU_L2_ONSTATE_SHIFT 20
216#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20) 40#define AM33XX_MPU_L2_ONSTATE_MASK (0x3 << 20)
217
218/* Used by PM_MPU_PWRSTCTRL */
219#define AM33XX_MPU_L2_RETSTATE_SHIFT 23
220#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23) 41#define AM33XX_MPU_L2_RETSTATE_MASK (1 << 23)
221
222/* Used by PM_MPU_PWRSTST */
223#define AM33XX_MPU_L2_STATEST_SHIFT 8
224#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8) 42#define AM33XX_MPU_L2_STATEST_MASK (0x3 << 8)
225
226/* Used by PM_MPU_PWRSTCTRL */
227#define AM33XX_MPU_RAM_ONSTATE_SHIFT 16
228#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16) 43#define AM33XX_MPU_RAM_ONSTATE_MASK (0x3 << 16)
229
230/* Used by PM_MPU_PWRSTCTRL */
231#define AM33XX_MPU_RAM_RETSTATE_SHIFT 24
232#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24) 44#define AM33XX_MPU_RAM_RETSTATE_MASK (1 << 24)
233
234/* Used by PM_MPU_PWRSTST */
235#define AM33XX_MPU_RAM_STATEST_SHIFT 4
236#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4) 45#define AM33XX_MPU_RAM_STATEST_MASK (0x3 << 4)
237
238/* Used by PRM_RSTST */
239#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT 2
240#define AM33XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
241
242/* Used by PRM_SRAM_COUNT */
243#define AM33XX_PCHARGECNT_VALUE_SHIFT 0
244#define AM33XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
245
246/* Used by RM_PER_RSTCTRL */
247#define AM33XX_PCI_LRST_SHIFT 0
248#define AM33XX_PCI_LRST_MASK (1 << 0)
249
250/* Renamed from PCI_LRST Used by RM_PER_RSTST */
251#define AM33XX_PCI_LRST_5_5_SHIFT 5
252#define AM33XX_PCI_LRST_5_5_MASK (1 << 5)
253
254/* Used by PM_PER_PWRSTCTRL */
255#define AM33XX_PER_MEM_ONSTATE_SHIFT 25
256#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25) 46#define AM33XX_PER_MEM_ONSTATE_MASK (0x3 << 25)
257
258/* Used by PM_PER_PWRSTCTRL */
259#define AM33XX_PER_MEM_RETSTATE_SHIFT 29
260#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29) 47#define AM33XX_PER_MEM_RETSTATE_MASK (1 << 29)
261
262/* Used by PM_PER_PWRSTST */
263#define AM33XX_PER_MEM_STATEST_SHIFT 17
264#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17) 48#define AM33XX_PER_MEM_STATEST_MASK (0x3 << 17)
265
266/*
267 * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
268 * PM_MPU_PWRSTCTRL
269 */
270#define AM33XX_POWERSTATE_SHIFT 0
271#define AM33XX_POWERSTATE_MASK (0x3 << 0)
272
273/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
274#define AM33XX_POWERSTATEST_SHIFT 0
275#define AM33XX_POWERSTATEST_MASK (0x3 << 0)
276
277/* Used by PM_PER_PWRSTCTRL */
278#define AM33XX_RAM_MEM_ONSTATE_SHIFT 30
279#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30) 49#define AM33XX_RAM_MEM_ONSTATE_MASK (0x3 << 30)
280
281/* Used by PM_PER_PWRSTCTRL */
282#define AM33XX_RAM_MEM_RETSTATE_SHIFT 27
283#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27) 50#define AM33XX_RAM_MEM_RETSTATE_MASK (1 << 27)
284
285/* Used by PM_PER_PWRSTST */
286#define AM33XX_RAM_MEM_STATEST_SHIFT 21
287#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21) 51#define AM33XX_RAM_MEM_STATEST_MASK (0x3 << 21)
288
289/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
290#define AM33XX_RETMODE_ENABLE_SHIFT 0
291#define AM33XX_RETMODE_ENABLE_MASK (1 << 0)
292
293/* Used by REVISION_PRM */
294#define AM33XX_REV_SHIFT 0
295#define AM33XX_REV_MASK (0xff << 0)
296
297/* Used by PRM_RSTTIME */
298#define AM33XX_RSTTIME1_SHIFT 0
299#define AM33XX_RSTTIME1_MASK (0xff << 0)
300
301/* Used by PRM_RSTTIME */
302#define AM33XX_RSTTIME2_SHIFT 8
303#define AM33XX_RSTTIME2_MASK (0x1f << 8)
304
305/* Used by PRM_RSTCTRL */
306#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT 1
307#define AM33XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
308
309/* Used by PRM_RSTCTRL */
310#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT 0
311#define AM33XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
312
313/* Used by PRM_SRAM_COUNT */
314#define AM33XX_SLPCNT_VALUE_SHIFT 16
315#define AM33XX_SLPCNT_VALUE_MASK (0xff << 16)
316
317/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
318#define AM33XX_SRAMLDO_STATUS_SHIFT 8
319#define AM33XX_SRAMLDO_STATUS_MASK (1 << 8)
320
321/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
322#define AM33XX_SRAM_IN_TRANSITION_SHIFT 9
323#define AM33XX_SRAM_IN_TRANSITION_MASK (1 << 9)
324
325/* Used by PRM_SRAM_COUNT */
326#define AM33XX_STARTUP_COUNT_SHIFT 24
327#define AM33XX_STARTUP_COUNT_MASK (0xff << 24)
328
329/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
330#define AM33XX_TRANSITION_EN_SHIFT 8
331#define AM33XX_TRANSITION_EN_MASK (1 << 8)
332
333/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
334#define AM33XX_TRANSITION_ST_SHIFT 8
335#define AM33XX_TRANSITION_ST_MASK (1 << 8)
336
337/* Used by PRM_SRAM_COUNT */
338#define AM33XX_VSETUPCNT_VALUE_SHIFT 8
339#define AM33XX_VSETUPCNT_VALUE_MASK (0xff << 8)
340
341/* Used by PRM_RSTST */
342#define AM33XX_WDT0_RST_SHIFT 3
343#define AM33XX_WDT0_RST_MASK (1 << 3)
344
345/* Used by PRM_RSTST */
346#define AM33XX_WDT1_RST_SHIFT 4
347#define AM33XX_WDT1_RST_MASK (1 << 4)
348
349/* Used by RM_WKUP_RSTCTRL */
350#define AM33XX_WKUP_M3_LRST_SHIFT 3
351#define AM33XX_WKUP_M3_LRST_MASK (1 << 3)
352
353/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
354#define AM33XX_WKUP_M3_LRST_5_5_SHIFT 5
355#define AM33XX_WKUP_M3_LRST_5_5_MASK (1 << 5)
356
357#endif 52#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index b0a2142eeb91..cebad565ed37 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -16,115 +16,25 @@
16 16
17#include "prm3xxx.h" 17#include "prm3xxx.h"
18 18
19/* Shared register bits */
20
21/* PRM_VC_CMD_VAL_0, PRM_VC_CMD_VAL_1 shared bits */
22#define OMAP3430_ON_SHIFT 24
23#define OMAP3430_ON_MASK (0xff << 24)
24#define OMAP3430_ONLP_SHIFT 16
25#define OMAP3430_ONLP_MASK (0xff << 16)
26#define OMAP3430_RET_SHIFT 8
27#define OMAP3430_RET_MASK (0xff << 8)
28#define OMAP3430_OFF_SHIFT 0
29#define OMAP3430_OFF_MASK (0xff << 0)
30
31/* PRM_VP1_CONFIG, PRM_VP2_CONFIG shared bits */
32#define OMAP3430_ERROROFFSET_SHIFT 24
33#define OMAP3430_ERROROFFSET_MASK (0xff << 24) 19#define OMAP3430_ERROROFFSET_MASK (0xff << 24)
34#define OMAP3430_ERRORGAIN_SHIFT 16
35#define OMAP3430_ERRORGAIN_MASK (0xff << 16) 20#define OMAP3430_ERRORGAIN_MASK (0xff << 16)
36#define OMAP3430_INITVOLTAGE_SHIFT 8
37#define OMAP3430_INITVOLTAGE_MASK (0xff << 8) 21#define OMAP3430_INITVOLTAGE_MASK (0xff << 8)
38#define OMAP3430_TIMEOUTEN_MASK (1 << 3) 22#define OMAP3430_TIMEOUTEN_MASK (1 << 3)
39#define OMAP3430_INITVDD_MASK (1 << 2) 23#define OMAP3430_INITVDD_MASK (1 << 2)
40#define OMAP3430_FORCEUPDATE_MASK (1 << 1) 24#define OMAP3430_FORCEUPDATE_MASK (1 << 1)
41#define OMAP3430_VPENABLE_MASK (1 << 0) 25#define OMAP3430_VPENABLE_MASK (1 << 0)
42
43/* PRM_VP1_VSTEPMIN, PRM_VP2_VSTEPMIN shared bits */
44#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8 26#define OMAP3430_SMPSWAITTIMEMIN_SHIFT 8
45#define OMAP3430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
46#define OMAP3430_VSTEPMIN_SHIFT 0 27#define OMAP3430_VSTEPMIN_SHIFT 0
47#define OMAP3430_VSTEPMIN_MASK (0xff << 0)
48
49/* PRM_VP1_VSTEPMAX, PRM_VP2_VSTEPMAX shared bits */
50#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8 28#define OMAP3430_SMPSWAITTIMEMAX_SHIFT 8
51#define OMAP3430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
52#define OMAP3430_VSTEPMAX_SHIFT 0 29#define OMAP3430_VSTEPMAX_SHIFT 0
53#define OMAP3430_VSTEPMAX_MASK (0xff << 0)
54
55/* PRM_VP1_VLIMITTO, PRM_VP2_VLIMITTO shared bits */
56#define OMAP3430_VDDMAX_SHIFT 24 30#define OMAP3430_VDDMAX_SHIFT 24
57#define OMAP3430_VDDMAX_MASK (0xff << 24)
58#define OMAP3430_VDDMIN_SHIFT 16 31#define OMAP3430_VDDMIN_SHIFT 16
59#define OMAP3430_VDDMIN_MASK (0xff << 16)
60#define OMAP3430_TIMEOUT_SHIFT 0 32#define OMAP3430_TIMEOUT_SHIFT 0
61#define OMAP3430_TIMEOUT_MASK (0xffff << 0)
62
63/* PRM_VP1_VOLTAGE, PRM_VP2_VOLTAGE shared bits */
64#define OMAP3430_VPVOLTAGE_SHIFT 0
65#define OMAP3430_VPVOLTAGE_MASK (0xff << 0) 33#define OMAP3430_VPVOLTAGE_MASK (0xff << 0)
66
67/* PRM_VP1_STATUS, PRM_VP2_STATUS shared bits */
68#define OMAP3430_VPINIDLE_MASK (1 << 0)
69
70/* PM_WKDEP_IVA2, PM_WKDEP_MPU shared bits */
71#define OMAP3430_EN_PER_SHIFT 7 34#define OMAP3430_EN_PER_SHIFT 7
72#define OMAP3430_EN_PER_MASK (1 << 7)
73
74/* PM_PWSTCTRL_IVA2, PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE shared bits */
75#define OMAP3430_MEMORYCHANGE_MASK (1 << 3)
76
77/* PM_PWSTST_IVA2, PM_PWSTST_CORE shared bits */
78#define OMAP3430_LOGICSTATEST_MASK (1 << 2) 35#define OMAP3430_LOGICSTATEST_MASK (1 << 2)
79
80/* PM_PREPWSTST_IVA2, PM_PREPWSTST_CORE shared bits */
81#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2) 36#define OMAP3430_LASTLOGICSTATEENTERED_MASK (1 << 2)
82
83/*
84 * PM_PREPWSTST_IVA2, PM_PREPWSTST_MPU, PM_PREPWSTST_CORE,
85 * PM_PREPWSTST_GFX, PM_PREPWSTST_DSS, PM_PREPWSTST_CAM,
86 * PM_PREPWSTST_PER, PM_PREPWSTST_NEON shared bits
87 */
88#define OMAP3430_LASTPOWERSTATEENTERED_SHIFT 0
89#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0) 37#define OMAP3430_LASTPOWERSTATEENTERED_MASK (0x3 << 0)
90
91/* PRM_IRQSTATUS_IVA2, PRM_IRQSTATUS_MPU shared bits */
92#define OMAP3430_WKUP_ST_MASK (1 << 0)
93
94/* PRM_IRQENABLE_IVA2, PRM_IRQENABLE_MPU shared bits */
95#define OMAP3430_WKUP_EN_MASK (1 << 0)
96
97/* PM_MPUGRPSEL1_CORE, PM_IVA2GRPSEL1_CORE shared bits */
98#define OMAP3430_GRPSEL_MMC2_MASK (1 << 25)
99#define OMAP3430_GRPSEL_MMC1_MASK (1 << 24)
100#define OMAP3430_GRPSEL_MCSPI4_MASK (1 << 21)
101#define OMAP3430_GRPSEL_MCSPI3_MASK (1 << 20)
102#define OMAP3430_GRPSEL_MCSPI2_MASK (1 << 19)
103#define OMAP3430_GRPSEL_MCSPI1_MASK (1 << 18)
104#define OMAP3430_GRPSEL_I2C3_SHIFT 17
105#define OMAP3430_GRPSEL_I2C3_MASK (1 << 17)
106#define OMAP3430_GRPSEL_I2C2_SHIFT 16
107#define OMAP3430_GRPSEL_I2C2_MASK (1 << 16)
108#define OMAP3430_GRPSEL_I2C1_SHIFT 15
109#define OMAP3430_GRPSEL_I2C1_MASK (1 << 15)
110#define OMAP3430_GRPSEL_UART2_MASK (1 << 14)
111#define OMAP3430_GRPSEL_UART1_MASK (1 << 13)
112#define OMAP3430_GRPSEL_GPT11_MASK (1 << 12)
113#define OMAP3430_GRPSEL_GPT10_MASK (1 << 11)
114#define OMAP3430_GRPSEL_MCBSP5_MASK (1 << 10)
115#define OMAP3430_GRPSEL_MCBSP1_MASK (1 << 9)
116#define OMAP3430_GRPSEL_HSOTGUSB_MASK (1 << 4)
117#define OMAP3430_GRPSEL_D2D_MASK (1 << 3)
118
119/*
120 * PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM,
121 * PM_PWSTCTRL_PER shared bits
122 */
123#define OMAP3430_MEMONSTATE_SHIFT 16
124#define OMAP3430_MEMONSTATE_MASK (0x3 << 16)
125#define OMAP3430_MEMRETSTATE_MASK (1 << 8)
126
127/* PM_MPUGRPSEL_PER, PM_IVA2GRPSEL_PER shared bits */
128#define OMAP3630_GRPSEL_UART4_MASK (1 << 18) 38#define OMAP3630_GRPSEL_UART4_MASK (1 << 18)
129#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17) 39#define OMAP3430_GRPSEL_GPIO6_MASK (1 << 17)
130#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16) 40#define OMAP3430_GRPSEL_GPIO5_MASK (1 << 16)
@@ -132,480 +42,89 @@
132#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14) 42#define OMAP3430_GRPSEL_GPIO3_MASK (1 << 14)
133#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13) 43#define OMAP3430_GRPSEL_GPIO2_MASK (1 << 13)
134#define OMAP3430_GRPSEL_UART3_MASK (1 << 11) 44#define OMAP3430_GRPSEL_UART3_MASK (1 << 11)
135#define OMAP3430_GRPSEL_GPT9_MASK (1 << 10)
136#define OMAP3430_GRPSEL_GPT8_MASK (1 << 9)
137#define OMAP3430_GRPSEL_GPT7_MASK (1 << 8)
138#define OMAP3430_GRPSEL_GPT6_MASK (1 << 7)
139#define OMAP3430_GRPSEL_GPT5_MASK (1 << 6)
140#define OMAP3430_GRPSEL_GPT4_MASK (1 << 5)
141#define OMAP3430_GRPSEL_GPT3_MASK (1 << 4)
142#define OMAP3430_GRPSEL_GPT2_MASK (1 << 3)
143#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2) 45#define OMAP3430_GRPSEL_MCBSP4_MASK (1 << 2)
144#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1) 46#define OMAP3430_GRPSEL_MCBSP3_MASK (1 << 1)
145#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0) 47#define OMAP3430_GRPSEL_MCBSP2_MASK (1 << 0)
146
147/* PM_MPUGRPSEL_WKUP, PM_IVA2GRPSEL_WKUP shared bits */
148#define OMAP3430_GRPSEL_IO_MASK (1 << 8)
149#define OMAP3430_GRPSEL_SR2_MASK (1 << 7)
150#define OMAP3430_GRPSEL_SR1_MASK (1 << 6)
151#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3) 48#define OMAP3430_GRPSEL_GPIO1_MASK (1 << 3)
152#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1) 49#define OMAP3430_GRPSEL_GPT12_MASK (1 << 1)
153#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0) 50#define OMAP3430_GRPSEL_GPT1_MASK (1 << 0)
154
155/* Bits specific to each register */
156
157/* RM_RSTCTRL_IVA2 */
158#define OMAP3430_RST3_IVA2_MASK (1 << 2) 51#define OMAP3430_RST3_IVA2_MASK (1 << 2)
159#define OMAP3430_RST2_IVA2_MASK (1 << 1) 52#define OMAP3430_RST2_IVA2_MASK (1 << 1)
160#define OMAP3430_RST1_IVA2_MASK (1 << 0) 53#define OMAP3430_RST1_IVA2_MASK (1 << 0)
161
162/* RM_RSTST_IVA2 specific bits */
163#define OMAP3430_EMULATION_VSEQ_RST_MASK (1 << 13)
164#define OMAP3430_EMULATION_VHWA_RST_MASK (1 << 12)
165#define OMAP3430_EMULATION_IVA2_RST_MASK (1 << 11)
166#define OMAP3430_IVA2_SW_RST3_MASK (1 << 10)
167#define OMAP3430_IVA2_SW_RST2_MASK (1 << 9)
168#define OMAP3430_IVA2_SW_RST1_MASK (1 << 8)
169
170/* PM_WKDEP_IVA2 specific bits */
171
172/* PM_PWSTCTRL_IVA2 specific bits */
173#define OMAP3430_L2FLATMEMONSTATE_SHIFT 22
174#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22) 54#define OMAP3430_L2FLATMEMONSTATE_MASK (0x3 << 22)
175#define OMAP3430_SHAREDL2CACHEFLATONSTATE_SHIFT 20
176#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20) 55#define OMAP3430_SHAREDL2CACHEFLATONSTATE_MASK (0x3 << 20)
177#define OMAP3430_L1FLATMEMONSTATE_SHIFT 18
178#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18) 56#define OMAP3430_L1FLATMEMONSTATE_MASK (0x3 << 18)
179#define OMAP3430_SHAREDL1CACHEFLATONSTATE_SHIFT 16
180#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16) 57#define OMAP3430_SHAREDL1CACHEFLATONSTATE_MASK (0x3 << 16)
181#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11) 58#define OMAP3430_L2FLATMEMRETSTATE_MASK (1 << 11)
182#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10) 59#define OMAP3430_SHAREDL2CACHEFLATRETSTATE_MASK (1 << 10)
183#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9) 60#define OMAP3430_L1FLATMEMRETSTATE_MASK (1 << 9)
184#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8) 61#define OMAP3430_SHAREDL1CACHEFLATRETSTATE_MASK (1 << 8)
185
186/* PM_PWSTST_IVA2 specific bits */
187#define OMAP3430_L2FLATMEMSTATEST_SHIFT 10
188#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10) 62#define OMAP3430_L2FLATMEMSTATEST_MASK (0x3 << 10)
189#define OMAP3430_SHAREDL2CACHEFLATSTATEST_SHIFT 8
190#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8) 63#define OMAP3430_SHAREDL2CACHEFLATSTATEST_MASK (0x3 << 8)
191#define OMAP3430_L1FLATMEMSTATEST_SHIFT 6
192#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6) 64#define OMAP3430_L1FLATMEMSTATEST_MASK (0x3 << 6)
193#define OMAP3430_SHAREDL1CACHEFLATSTATEST_SHIFT 4
194#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4) 65#define OMAP3430_SHAREDL1CACHEFLATSTATEST_MASK (0x3 << 4)
195
196/* PM_PREPWSTST_IVA2 specific bits */
197#define OMAP3430_LASTL2FLATMEMSTATEENTERED_SHIFT 10
198#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10) 66#define OMAP3430_LASTL2FLATMEMSTATEENTERED_MASK (0x3 << 10)
199#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_SHIFT 8
200#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8) 67#define OMAP3430_LASTSHAREDL2CACHEFLATSTATEENTERED_MASK (0x3 << 8)
201#define OMAP3430_LASTL1FLATMEMSTATEENTERED_SHIFT 6
202#define OMAP3430_LASTL1FLATMEMSTATEENTERED_MASK (0x3 << 6)
203#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_SHIFT 4
204#define OMAP3430_LASTSHAREDL1CACHEFLATSTATEENTERED_MASK (0x3 << 4)
205
206/* PRM_IRQSTATUS_IVA2 specific bits */
207#define OMAP3430_PRM_IRQSTATUS_IVA2_IVA2_DPLL_ST_MASK (1 << 2)
208#define OMAP3430_FORCEWKUP_ST_MASK (1 << 1)
209
210/* PRM_IRQENABLE_IVA2 specific bits */
211#define OMAP3430_PRM_IRQENABLE_IVA2_IVA2_DPLL_RECAL_EN_MASK (1 << 2)
212#define OMAP3430_FORCEWKUP_EN_MASK (1 << 1)
213
214/* PRM_REVISION specific bits */
215
216/* PRM_SYSCONFIG specific bits */
217
218/* PRM_IRQSTATUS_MPU specific bits */
219#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25 68#define OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT 25
220#define OMAP3430ES2_SND_PERIPH_DPLL_ST_MASK (1 << 25)
221#define OMAP3430_VC_TIMEOUTERR_ST_MASK (1 << 24)
222#define OMAP3430_VC_RAERR_ST_MASK (1 << 23)
223#define OMAP3430_VC_SAERR_ST_MASK (1 << 22)
224#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21) 69#define OMAP3430_VP2_TRANXDONE_ST_MASK (1 << 21)
225#define OMAP3430_VP2_EQVALUE_ST_MASK (1 << 20)
226#define OMAP3430_VP2_NOSMPSACK_ST_MASK (1 << 19)
227#define OMAP3430_VP2_MAXVDD_ST_MASK (1 << 18)
228#define OMAP3430_VP2_MINVDD_ST_MASK (1 << 17)
229#define OMAP3430_VP2_OPPCHANGEDONE_ST_MASK (1 << 16)
230#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15) 70#define OMAP3430_VP1_TRANXDONE_ST_MASK (1 << 15)
231#define OMAP3430_VP1_EQVALUE_ST_MASK (1 << 14)
232#define OMAP3430_VP1_NOSMPSACK_ST_MASK (1 << 13)
233#define OMAP3430_VP1_MAXVDD_ST_MASK (1 << 12)
234#define OMAP3430_VP1_MINVDD_ST_MASK (1 << 11)
235#define OMAP3430_VP1_OPPCHANGEDONE_ST_MASK (1 << 10)
236#define OMAP3430_IO_ST_MASK (1 << 9)
237#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_MASK (1 << 8)
238#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8 71#define OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT 8
239#define OMAP3430_MPU_DPLL_ST_MASK (1 << 7)
240#define OMAP3430_MPU_DPLL_ST_SHIFT 7 72#define OMAP3430_MPU_DPLL_ST_SHIFT 7
241#define OMAP3430_PERIPH_DPLL_ST_MASK (1 << 6)
242#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6 73#define OMAP3430_PERIPH_DPLL_ST_SHIFT 6
243#define OMAP3430_CORE_DPLL_ST_MASK (1 << 5)
244#define OMAP3430_CORE_DPLL_ST_SHIFT 5 74#define OMAP3430_CORE_DPLL_ST_SHIFT 5
245#define OMAP3430_TRANSITION_ST_MASK (1 << 4)
246#define OMAP3430_EVGENOFF_ST_MASK (1 << 3)
247#define OMAP3430_EVGENON_ST_MASK (1 << 2)
248#define OMAP3430_FS_USB_WKUP_ST_MASK (1 << 1)
249
250/* PRM_IRQENABLE_MPU specific bits */
251#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25 75#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT 25
252#define OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_MASK (1 << 25)
253#define OMAP3430_VC_TIMEOUTERR_EN_MASK (1 << 24)
254#define OMAP3430_VC_RAERR_EN_MASK (1 << 23)
255#define OMAP3430_VC_SAERR_EN_MASK (1 << 22)
256#define OMAP3430_VP2_TRANXDONE_EN_MASK (1 << 21)
257#define OMAP3430_VP2_EQVALUE_EN_MASK (1 << 20)
258#define OMAP3430_VP2_NOSMPSACK_EN_MASK (1 << 19)
259#define OMAP3430_VP2_MAXVDD_EN_MASK (1 << 18)
260#define OMAP3430_VP2_MINVDD_EN_MASK (1 << 17)
261#define OMAP3430_VP2_OPPCHANGEDONE_EN_MASK (1 << 16)
262#define OMAP3430_VP1_TRANXDONE_EN_MASK (1 << 15)
263#define OMAP3430_VP1_EQVALUE_EN_MASK (1 << 14)
264#define OMAP3430_VP1_NOSMPSACK_EN_MASK (1 << 13)
265#define OMAP3430_VP1_MAXVDD_EN_MASK (1 << 12)
266#define OMAP3430_VP1_MINVDD_EN_MASK (1 << 11)
267#define OMAP3430_VP1_OPPCHANGEDONE_EN_MASK (1 << 10)
268#define OMAP3430_IO_EN_MASK (1 << 9)
269#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_MASK (1 << 8)
270#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8 76#define OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT 8
271#define OMAP3430_MPU_DPLL_RECAL_EN_MASK (1 << 7)
272#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7 77#define OMAP3430_MPU_DPLL_RECAL_EN_SHIFT 7
273#define OMAP3430_PERIPH_DPLL_RECAL_EN_MASK (1 << 6)
274#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6 78#define OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT 6
275#define OMAP3430_CORE_DPLL_RECAL_EN_MASK (1 << 5)
276#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5 79#define OMAP3430_CORE_DPLL_RECAL_EN_SHIFT 5
277#define OMAP3430_TRANSITION_EN_MASK (1 << 4)
278#define OMAP3430_EVGENOFF_EN_MASK (1 << 3)
279#define OMAP3430_EVGENON_EN_MASK (1 << 2)
280#define OMAP3430_FS_USB_WKUP_EN_MASK (1 << 1)
281
282/* RM_RSTST_MPU specific bits */
283#define OMAP3430_EMULATION_MPU_RST_MASK (1 << 11)
284
285/* PM_WKDEP_MPU specific bits */
286#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5 80#define OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT 5
287#define OMAP3430_PM_WKDEP_MPU_EN_DSS_MASK (1 << 5)
288#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2 81#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT 2
289#define OMAP3430_PM_WKDEP_MPU_EN_IVA2_MASK (1 << 2)
290
291/* PM_EVGENCTRL_MPU */
292#define OMAP3430_OFFLOADMODE_SHIFT 3
293#define OMAP3430_OFFLOADMODE_MASK (0x3 << 3)
294#define OMAP3430_ONLOADMODE_SHIFT 1
295#define OMAP3430_ONLOADMODE_MASK (0x3 << 1)
296#define OMAP3430_ENABLE_MASK (1 << 0)
297
298/* PM_EVGENONTIM_MPU */
299#define OMAP3430_ONTIMEVAL_SHIFT 0
300#define OMAP3430_ONTIMEVAL_MASK (0xffffffff << 0)
301
302/* PM_EVGENOFFTIM_MPU */
303#define OMAP3430_OFFTIMEVAL_SHIFT 0
304#define OMAP3430_OFFTIMEVAL_MASK (0xffffffff << 0)
305
306/* PM_PWSTCTRL_MPU specific bits */
307#define OMAP3430_L2CACHEONSTATE_SHIFT 16
308#define OMAP3430_L2CACHEONSTATE_MASK (0x3 << 16)
309#define OMAP3430_L2CACHERETSTATE_MASK (1 << 8)
310#define OMAP3430_LOGICL1CACHERETSTATE_MASK (1 << 2)
311
312/* PM_PWSTST_MPU specific bits */
313#define OMAP3430_L2CACHESTATEST_SHIFT 6
314#define OMAP3430_L2CACHESTATEST_MASK (0x3 << 6)
315#define OMAP3430_LOGICL1CACHESTATEST_MASK (1 << 2)
316
317/* PM_PREPWSTST_MPU specific bits */
318#define OMAP3430_LASTL2CACHESTATEENTERED_SHIFT 6
319#define OMAP3430_LASTL2CACHESTATEENTERED_MASK (0x3 << 6)
320#define OMAP3430_LASTLOGICL1CACHESTATEENTERED_MASK (1 << 2)
321
322/* RM_RSTCTRL_CORE */
323#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1) 82#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK (1 << 1)
324#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0) 83#define OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK (1 << 0)
325
326/* RM_RSTST_CORE specific bits */
327#define OMAP3430_MODEM_SECURITY_VIOL_RST_MASK (1 << 10)
328#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RSTPWRON_MASK (1 << 9)
329#define OMAP3430_RM_RSTST_CORE_MODEM_SW_RST_MASK (1 << 8)
330
331/* PM_WKEN1_CORE specific bits */
332
333/* PM_MPUGRPSEL1_CORE specific bits */
334#define OMAP3430_GRPSEL_FSHOSTUSB_MASK (1 << 5)
335
336/* PM_IVA2GRPSEL1_CORE specific bits */
337
338/* PM_WKST1_CORE specific bits */
339
340/* PM_PWSTCTRL_CORE specific bits */
341#define OMAP3430_MEM2ONSTATE_SHIFT 18
342#define OMAP3430_MEM2ONSTATE_MASK (0x3 << 18)
343#define OMAP3430_MEM1ONSTATE_SHIFT 16
344#define OMAP3430_MEM1ONSTATE_MASK (0x3 << 16)
345#define OMAP3430_MEM2RETSTATE_MASK (1 << 9)
346#define OMAP3430_MEM1RETSTATE_MASK (1 << 8)
347
348/* PM_PWSTST_CORE specific bits */
349#define OMAP3430_MEM2STATEST_SHIFT 6
350#define OMAP3430_MEM2STATEST_MASK (0x3 << 6)
351#define OMAP3430_MEM1STATEST_SHIFT 4
352#define OMAP3430_MEM1STATEST_MASK (0x3 << 4)
353
354/* PM_PREPWSTST_CORE specific bits */
355#define OMAP3430_LASTMEM2STATEENTERED_SHIFT 6
356#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6) 84#define OMAP3430_LASTMEM2STATEENTERED_MASK (0x3 << 6)
357#define OMAP3430_LASTMEM1STATEENTERED_SHIFT 4
358#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4) 85#define OMAP3430_LASTMEM1STATEENTERED_MASK (0x3 << 4)
359
360/* RM_RSTST_GFX specific bits */
361
362/* PM_WKDEP_GFX specific bits */
363#define OMAP3430_PM_WKDEP_GFX_EN_IVA2_MASK (1 << 2)
364
365/* PM_PWSTCTRL_GFX specific bits */
366
367/* PM_PWSTST_GFX specific bits */
368
369/* PM_PREPWSTST_GFX specific bits */
370
371/* PM_WKEN_WKUP specific bits */
372#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16) 86#define OMAP3430_EN_IO_CHAIN_MASK (1 << 16)
373#define OMAP3430_EN_IO_MASK (1 << 8) 87#define OMAP3430_EN_IO_MASK (1 << 8)
374#define OMAP3430_EN_GPIO1_MASK (1 << 3) 88#define OMAP3430_EN_GPIO1_MASK (1 << 3)
375
376/* PM_MPUGRPSEL_WKUP specific bits */
377
378/* PM_IVA2GRPSEL_WKUP specific bits */
379
380/* PM_WKST_WKUP specific bits */
381#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16) 89#define OMAP3430_ST_IO_CHAIN_MASK (1 << 16)
382#define OMAP3430_ST_IO_MASK (1 << 8) 90#define OMAP3430_ST_IO_MASK (1 << 8)
383
384/* PRM_CLKSEL */
385#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0 91#define OMAP3430_SYS_CLKIN_SEL_SHIFT 0
386#define OMAP3430_SYS_CLKIN_SEL_MASK (0x7 << 0)
387#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3 92#define OMAP3430_SYS_CLKIN_SEL_WIDTH 3
388
389/* PRM_CLKOUT_CTRL */
390#define OMAP3430_CLKOUT_EN_MASK (1 << 7)
391#define OMAP3430_CLKOUT_EN_SHIFT 7 93#define OMAP3430_CLKOUT_EN_SHIFT 7
392
393/* RM_RSTST_DSS specific bits */
394
395/* PM_WKEN_DSS */
396#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0) 94#define OMAP3430_PM_WKEN_DSS_EN_DSS_MASK (1 << 0)
397
398/* PM_WKDEP_DSS specific bits */
399#define OMAP3430_PM_WKDEP_DSS_EN_IVA2_MASK (1 << 2)
400
401/* PM_PWSTCTRL_DSS specific bits */
402
403/* PM_PWSTST_DSS specific bits */
404
405/* PM_PREPWSTST_DSS specific bits */
406
407/* RM_RSTST_CAM specific bits */
408
409/* PM_WKDEP_CAM specific bits */
410#define OMAP3430_PM_WKDEP_CAM_EN_IVA2_MASK (1 << 2)
411
412/* PM_PWSTCTRL_CAM specific bits */
413
414/* PM_PWSTST_CAM specific bits */
415
416/* PM_PREPWSTST_CAM specific bits */
417
418/* PM_PWSTCTRL_USBHOST specific bits */
419#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4 95#define OMAP3430ES2_SAVEANDRESTORE_SHIFT 4
420
421/* RM_RSTST_PER specific bits */
422
423/* PM_WKEN_PER specific bits */
424
425/* PM_MPUGRPSEL_PER specific bits */
426
427/* PM_IVA2GRPSEL_PER specific bits */
428
429/* PM_WKST_PER specific bits */
430
431/* PM_WKDEP_PER specific bits */
432#define OMAP3430_PM_WKDEP_PER_EN_IVA2_MASK (1 << 2)
433
434/* PM_PWSTCTRL_PER specific bits */
435
436/* PM_PWSTST_PER specific bits */
437
438/* PM_PREPWSTST_PER specific bits */
439
440/* RM_RSTST_EMU specific bits */
441
442/* PM_PWSTST_EMU specific bits */
443
444/* PRM_VC_SMPS_SA */
445#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16 96#define OMAP3430_PRM_VC_SMPS_SA_SA1_SHIFT 16
446#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16) 97#define OMAP3430_PRM_VC_SMPS_SA_SA1_MASK (0x7f << 16)
447#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0 98#define OMAP3430_PRM_VC_SMPS_SA_SA0_SHIFT 0
448#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0) 99#define OMAP3430_PRM_VC_SMPS_SA_SA0_MASK (0x7f << 0)
449
450/* PRM_VC_SMPS_VOL_RA */
451#define OMAP3430_VOLRA1_SHIFT 16
452#define OMAP3430_VOLRA1_MASK (0xff << 16) 100#define OMAP3430_VOLRA1_MASK (0xff << 16)
453#define OMAP3430_VOLRA0_SHIFT 0
454#define OMAP3430_VOLRA0_MASK (0xff << 0) 101#define OMAP3430_VOLRA0_MASK (0xff << 0)
455
456/* PRM_VC_SMPS_CMD_RA */
457#define OMAP3430_CMDRA1_SHIFT 16
458#define OMAP3430_CMDRA1_MASK (0xff << 16) 102#define OMAP3430_CMDRA1_MASK (0xff << 16)
459#define OMAP3430_CMDRA0_SHIFT 0
460#define OMAP3430_CMDRA0_MASK (0xff << 0) 103#define OMAP3430_CMDRA0_MASK (0xff << 0)
461
462/* PRM_VC_CMD_VAL_0 specific bits */
463#define OMAP3430_VC_CMD_ON_SHIFT 24 104#define OMAP3430_VC_CMD_ON_SHIFT 24
464#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24) 105#define OMAP3430_VC_CMD_ON_MASK (0xFF << 24)
465#define OMAP3430_VC_CMD_ONLP_SHIFT 16 106#define OMAP3430_VC_CMD_ONLP_SHIFT 16
466#define OMAP3430_VC_CMD_ONLP_MASK (0xFF << 16)
467#define OMAP3430_VC_CMD_RET_SHIFT 8 107#define OMAP3430_VC_CMD_RET_SHIFT 8
468#define OMAP3430_VC_CMD_RET_MASK (0xFF << 8)
469#define OMAP3430_VC_CMD_OFF_SHIFT 0 108#define OMAP3430_VC_CMD_OFF_SHIFT 0
470#define OMAP3430_VC_CMD_OFF_MASK (0xFF << 0)
471
472/* PRM_VC_CMD_VAL_1 specific bits */
473
474/* PRM_VC_CH_CONF */
475#define OMAP3430_CMD1_MASK (1 << 20)
476#define OMAP3430_RACEN1_MASK (1 << 19)
477#define OMAP3430_RAC1_MASK (1 << 18)
478#define OMAP3430_RAV1_MASK (1 << 17)
479#define OMAP3430_PRM_VC_CH_CONF_SA1_MASK (1 << 16)
480#define OMAP3430_CMD0_MASK (1 << 4)
481#define OMAP3430_RACEN0_MASK (1 << 3)
482#define OMAP3430_RAC0_MASK (1 << 2)
483#define OMAP3430_RAV0_MASK (1 << 1)
484#define OMAP3430_PRM_VC_CH_CONF_SA0_MASK (1 << 0)
485
486/* PRM_VC_I2C_CFG */
487#define OMAP3430_HSMASTER_MASK (1 << 5)
488#define OMAP3430_SREN_MASK (1 << 4)
489#define OMAP3430_HSEN_MASK (1 << 3) 109#define OMAP3430_HSEN_MASK (1 << 3)
490#define OMAP3430_MCODE_SHIFT 0
491#define OMAP3430_MCODE_MASK (0x7 << 0) 110#define OMAP3430_MCODE_MASK (0x7 << 0)
492
493/* PRM_VC_BYPASS_VAL */
494#define OMAP3430_VALID_MASK (1 << 24) 111#define OMAP3430_VALID_MASK (1 << 24)
495#define OMAP3430_DATA_SHIFT 16 112#define OMAP3430_DATA_SHIFT 16
496#define OMAP3430_DATA_MASK (0xff << 16)
497#define OMAP3430_REGADDR_SHIFT 8 113#define OMAP3430_REGADDR_SHIFT 8
498#define OMAP3430_REGADDR_MASK (0xff << 8)
499#define OMAP3430_SLAVEADDR_SHIFT 0 114#define OMAP3430_SLAVEADDR_SHIFT 0
500#define OMAP3430_SLAVEADDR_MASK (0x7f << 0)
501
502/* PRM_RSTCTRL */
503#define OMAP3430_RST_DPLL3_MASK (1 << 2)
504#define OMAP3430_RST_GS_MASK (1 << 1)
505
506/* PRM_RSTTIME */
507#define OMAP3430_RSTTIME2_SHIFT 8
508#define OMAP3430_RSTTIME2_MASK (0x1f << 8)
509#define OMAP3430_RSTTIME1_SHIFT 0
510#define OMAP3430_RSTTIME1_MASK (0xff << 0)
511
512/* PRM_RSTST */
513#define OMAP3430_ICECRUSHER_RST_SHIFT 10 115#define OMAP3430_ICECRUSHER_RST_SHIFT 10
514#define OMAP3430_ICECRUSHER_RST_MASK (1 << 10)
515#define OMAP3430_ICEPICK_RST_SHIFT 9 116#define OMAP3430_ICEPICK_RST_SHIFT 9
516#define OMAP3430_ICEPICK_RST_MASK (1 << 9)
517#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8 117#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT 8
518#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK (1 << 8)
519#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7 118#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT 7
520#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK (1 << 7)
521#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6 119#define OMAP3430_EXTERNAL_WARM_RST_SHIFT 6
522#define OMAP3430_EXTERNAL_WARM_RST_MASK (1 << 6)
523#define OMAP3430_SECURE_WD_RST_SHIFT 5 120#define OMAP3430_SECURE_WD_RST_SHIFT 5
524#define OMAP3430_SECURE_WD_RST_MASK (1 << 5)
525#define OMAP3430_MPU_WD_RST_SHIFT 4 121#define OMAP3430_MPU_WD_RST_SHIFT 4
526#define OMAP3430_MPU_WD_RST_MASK (1 << 4)
527#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3 122#define OMAP3430_SECURITY_VIOL_RST_SHIFT 3
528#define OMAP3430_SECURITY_VIOL_RST_MASK (1 << 3)
529#define OMAP3430_GLOBAL_SW_RST_SHIFT 1 123#define OMAP3430_GLOBAL_SW_RST_SHIFT 1
530#define OMAP3430_GLOBAL_SW_RST_MASK (1 << 1)
531#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0 124#define OMAP3430_GLOBAL_COLD_RST_SHIFT 0
532#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0) 125#define OMAP3430_GLOBAL_COLD_RST_MASK (1 << 0)
533
534/* PRM_VOLTCTRL */
535#define OMAP3430_SEL_VMODE_MASK (1 << 4)
536#define OMAP3430_SEL_OFF_MASK (1 << 3) 126#define OMAP3430_SEL_OFF_MASK (1 << 3)
537#define OMAP3430_AUTO_OFF_MASK (1 << 2) 127#define OMAP3430_AUTO_OFF_MASK (1 << 2)
538#define OMAP3430_AUTO_RET_MASK (1 << 1)
539#define OMAP3430_AUTO_SLEEP_MASK (1 << 0)
540
541/* PRM_SRAM_PCHARGE */
542#define OMAP3430_PCHARGE_TIME_SHIFT 0
543#define OMAP3430_PCHARGE_TIME_MASK (0xff << 0)
544
545/* PRM_CLKSRC_CTRL */
546#define OMAP3430_SYSCLKDIV_SHIFT 6
547#define OMAP3430_SYSCLKDIV_MASK (0x3 << 6)
548#define OMAP3430_AUTOEXTCLKMODE_SHIFT 3
549#define OMAP3430_AUTOEXTCLKMODE_MASK (0x3 << 3)
550#define OMAP3430_SYSCLKSEL_SHIFT 0
551#define OMAP3430_SYSCLKSEL_MASK (0x3 << 0)
552
553/* PRM_VOLTSETUP1 */
554#define OMAP3430_SETUP_TIME2_SHIFT 16
555#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16) 128#define OMAP3430_SETUP_TIME2_MASK (0xffff << 16)
556#define OMAP3430_SETUP_TIME1_SHIFT 0
557#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0) 129#define OMAP3430_SETUP_TIME1_MASK (0xffff << 0)
558
559/* PRM_VOLTOFFSET */
560#define OMAP3430_OFFSET_TIME_SHIFT 0
561#define OMAP3430_OFFSET_TIME_MASK (0xffff << 0)
562
563/* PRM_CLKSETUP */
564#define OMAP3430_SETUP_TIME_SHIFT 0
565#define OMAP3430_SETUP_TIME_MASK (0xffff << 0)
566
567/* PRM_POLCTRL */
568#define OMAP3430_OFFMODE_POL_MASK (1 << 3)
569#define OMAP3430_CLKOUT_POL_MASK (1 << 2)
570#define OMAP3430_CLKREQ_POL_MASK (1 << 1)
571#define OMAP3430_EXTVOL_POL_MASK (1 << 0)
572
573/* PRM_VOLTSETUP2 */
574#define OMAP3430_OFFMODESETUPTIME_SHIFT 0
575#define OMAP3430_OFFMODESETUPTIME_MASK (0xffff << 0)
576
577/* PRM_VP1_CONFIG specific bits */
578
579/* PRM_VP1_VSTEPMIN specific bits */
580
581/* PRM_VP1_VSTEPMAX specific bits */
582
583/* PRM_VP1_VLIMITTO specific bits */
584
585/* PRM_VP1_VOLTAGE specific bits */
586
587/* PRM_VP1_STATUS specific bits */
588
589/* PRM_VP2_CONFIG specific bits */
590
591/* PRM_VP2_VSTEPMIN specific bits */
592
593/* PRM_VP2_VSTEPMAX specific bits */
594
595/* PRM_VP2_VLIMITTO specific bits */
596
597/* PRM_VP2_VOLTAGE specific bits */
598
599/* PRM_VP2_STATUS specific bits */
600
601/* RM_RSTST_NEON specific bits */
602
603/* PM_WKDEP_NEON specific bits */
604
605/* PM_PWSTCTRL_NEON specific bits */
606
607/* PM_PWSTST_NEON specific bits */
608
609/* PM_PREPWSTST_NEON specific bits */
610
611#endif 130#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 3cb247bebdaa..b1c7a33e00e7 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -22,2306 +22,80 @@
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 22#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H 23#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H
24 24
25
26/*
27 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
28 * PRM_LDO_SRAM_MPU_SETUP
29 */
30#define OMAP4430_ABBOFF_ACT_EXPORT_SHIFT 1
31#define OMAP4430_ABBOFF_ACT_EXPORT_MASK (1 << 1)
32
33/*
34 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
35 * PRM_LDO_SRAM_MPU_SETUP
36 */
37#define OMAP4430_ABBOFF_SLEEP_EXPORT_SHIFT 2
38#define OMAP4430_ABBOFF_SLEEP_EXPORT_MASK (1 << 2)
39
40/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
41#define OMAP4430_ABB_IVA_DONE_EN_SHIFT 31
42#define OMAP4430_ABB_IVA_DONE_EN_MASK (1 << 31)
43
44/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
45#define OMAP4430_ABB_IVA_DONE_ST_SHIFT 31
46#define OMAP4430_ABB_IVA_DONE_ST_MASK (1 << 31)
47
48/* Used by PRM_IRQENABLE_MPU_2 */
49#define OMAP4430_ABB_MPU_DONE_EN_SHIFT 7
50#define OMAP4430_ABB_MPU_DONE_EN_MASK (1 << 7)
51
52/* Used by PRM_IRQSTATUS_MPU_2 */
53#define OMAP4430_ABB_MPU_DONE_ST_SHIFT 7
54#define OMAP4430_ABB_MPU_DONE_ST_MASK (1 << 7)
55
56/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
57#define OMAP4430_ACTIVE_FBB_SEL_SHIFT 2
58#define OMAP4430_ACTIVE_FBB_SEL_MASK (1 << 2)
59
60/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
61#define OMAP4430_ACTIVE_RBB_SEL_SHIFT 1
62#define OMAP4430_ACTIVE_RBB_SEL_MASK (1 << 1)
63
64/* Used by PM_ABE_PWRSTCTRL */
65#define OMAP4430_AESSMEM_ONSTATE_SHIFT 16
66#define OMAP4430_AESSMEM_ONSTATE_MASK (0x3 << 16)
67
68/* Used by PM_ABE_PWRSTCTRL */
69#define OMAP4430_AESSMEM_RETSTATE_SHIFT 8
70#define OMAP4430_AESSMEM_RETSTATE_MASK (1 << 8)
71
72/* Used by PM_ABE_PWRSTST */
73#define OMAP4430_AESSMEM_STATEST_SHIFT 4
74#define OMAP4430_AESSMEM_STATEST_MASK (0x3 << 4)
75
76/*
77 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
78 * PRM_LDO_SRAM_MPU_SETUP
79 */
80#define OMAP4430_AIPOFF_SHIFT 8
81#define OMAP4430_AIPOFF_MASK (1 << 8)
82
83/* Used by PRM_VOLTCTRL */
84#define OMAP4430_AUTO_CTRL_VDD_CORE_L_SHIFT 0
85#define OMAP4430_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
86
87/* Used by PRM_VOLTCTRL */
88#define OMAP4430_AUTO_CTRL_VDD_IVA_L_SHIFT 4
89#define OMAP4430_AUTO_CTRL_VDD_IVA_L_MASK (0x3 << 4)
90
91/* Used by PRM_VOLTCTRL */
92#define OMAP4430_AUTO_CTRL_VDD_MPU_L_SHIFT 2
93#define OMAP4430_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
94
95/* Used by PRM_VC_ERRST */
96#define OMAP4430_BYPS_RA_ERR_SHIFT 25
97#define OMAP4430_BYPS_RA_ERR_MASK (1 << 25)
98
99/* Used by PRM_VC_ERRST */
100#define OMAP4430_BYPS_SA_ERR_SHIFT 24
101#define OMAP4430_BYPS_SA_ERR_MASK (1 << 24)
102
103/* Used by PRM_VC_ERRST */
104#define OMAP4430_BYPS_TIMEOUT_ERR_SHIFT 26
105#define OMAP4430_BYPS_TIMEOUT_ERR_MASK (1 << 26)
106
107/* Used by PRM_RSTST */
108#define OMAP4430_C2C_RST_SHIFT 10 25#define OMAP4430_C2C_RST_SHIFT 10
109#define OMAP4430_C2C_RST_MASK (1 << 10)
110
111/* Used by PM_CAM_PWRSTCTRL */
112#define OMAP4430_CAM_MEM_ONSTATE_SHIFT 16
113#define OMAP4430_CAM_MEM_ONSTATE_MASK (0x3 << 16)
114
115/* Used by PM_CAM_PWRSTST */
116#define OMAP4430_CAM_MEM_STATEST_SHIFT 4
117#define OMAP4430_CAM_MEM_STATEST_MASK (0x3 << 4)
118
119/* Used by PRM_CLKREQCTRL */
120#define OMAP4430_CLKREQ_COND_SHIFT 0
121#define OMAP4430_CLKREQ_COND_MASK (0x7 << 0)
122
123/* Used by PRM_VC_VAL_SMPS_RA_CMD */
124#define OMAP4430_CMDRA_VDD_CORE_L_SHIFT 0
125#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0) 26#define OMAP4430_CMDRA_VDD_CORE_L_MASK (0xff << 0)
126
127/* Used by PRM_VC_VAL_SMPS_RA_CMD */
128#define OMAP4430_CMDRA_VDD_IVA_L_SHIFT 8
129#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8) 27#define OMAP4430_CMDRA_VDD_IVA_L_MASK (0xff << 8)
130
131/* Used by PRM_VC_VAL_SMPS_RA_CMD */
132#define OMAP4430_CMDRA_VDD_MPU_L_SHIFT 16
133#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16) 28#define OMAP4430_CMDRA_VDD_MPU_L_MASK (0xff << 16)
134
135/* Used by PRM_VC_CFG_CHANNEL */
136#define OMAP4430_CMD_VDD_CORE_L_SHIFT 4
137#define OMAP4430_CMD_VDD_CORE_L_MASK (1 << 4)
138
139/* Used by PRM_VC_CFG_CHANNEL */
140#define OMAP4430_CMD_VDD_IVA_L_SHIFT 12
141#define OMAP4430_CMD_VDD_IVA_L_MASK (1 << 12)
142
143/* Used by PRM_VC_CFG_CHANNEL */
144#define OMAP4430_CMD_VDD_MPU_L_SHIFT 17
145#define OMAP4430_CMD_VDD_MPU_L_MASK (1 << 17)
146
147/* Used by PM_CORE_PWRSTCTRL */
148#define OMAP4430_CORE_OCMRAM_ONSTATE_SHIFT 18
149#define OMAP4430_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
150
151/* Used by PM_CORE_PWRSTCTRL */
152#define OMAP4430_CORE_OCMRAM_RETSTATE_SHIFT 9
153#define OMAP4430_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
154
155/* Used by PM_CORE_PWRSTST */
156#define OMAP4430_CORE_OCMRAM_STATEST_SHIFT 6
157#define OMAP4430_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
158
159/* Used by PM_CORE_PWRSTCTRL */
160#define OMAP4430_CORE_OTHER_BANK_ONSTATE_SHIFT 16
161#define OMAP4430_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
162
163/* Used by PM_CORE_PWRSTCTRL */
164#define OMAP4430_CORE_OTHER_BANK_RETSTATE_SHIFT 8
165#define OMAP4430_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
166
167/* Used by PM_CORE_PWRSTST */
168#define OMAP4430_CORE_OTHER_BANK_STATEST_SHIFT 4
169#define OMAP4430_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
170
171/* Used by REVISION_PRM */
172#define OMAP4430_CUSTOM_SHIFT 6
173#define OMAP4430_CUSTOM_MASK (0x3 << 6)
174
175/* Used by PRM_VC_VAL_BYPASS */
176#define OMAP4430_DATA_SHIFT 16 29#define OMAP4430_DATA_SHIFT 16
177#define OMAP4430_DATA_MASK (0xff << 16)
178
179/* Used by PRM_DEVICE_OFF_CTRL */
180#define OMAP4430_DEVICE_OFF_ENABLE_SHIFT 0
181#define OMAP4430_DEVICE_OFF_ENABLE_MASK (1 << 0)
182
183/* Used by PRM_VC_CFG_I2C_MODE */
184#define OMAP4430_DFILTEREN_SHIFT 6
185#define OMAP4430_DFILTEREN_MASK (1 << 6)
186
187/*
188 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
189 * PRM_LDO_SRAM_MPU_SETUP, PRM_SRAM_WKUP_SETUP
190 */
191#define OMAP4430_DISABLE_RTA_EXPORT_SHIFT 0
192#define OMAP4430_DISABLE_RTA_EXPORT_MASK (1 << 0)
193
194/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
195#define OMAP4430_DPLL_ABE_RECAL_EN_SHIFT 4
196#define OMAP4430_DPLL_ABE_RECAL_EN_MASK (1 << 4)
197
198/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
199#define OMAP4430_DPLL_ABE_RECAL_ST_SHIFT 4
200#define OMAP4430_DPLL_ABE_RECAL_ST_MASK (1 << 4)
201
202/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
203#define OMAP4430_DPLL_CORE_RECAL_EN_SHIFT 0
204#define OMAP4430_DPLL_CORE_RECAL_EN_MASK (1 << 0)
205
206/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
207#define OMAP4430_DPLL_CORE_RECAL_ST_SHIFT 0
208#define OMAP4430_DPLL_CORE_RECAL_ST_MASK (1 << 0)
209
210/* Used by PRM_IRQENABLE_MPU */
211#define OMAP4430_DPLL_DDRPHY_RECAL_EN_SHIFT 6
212#define OMAP4430_DPLL_DDRPHY_RECAL_EN_MASK (1 << 6)
213
214/* Used by PRM_IRQSTATUS_MPU */
215#define OMAP4430_DPLL_DDRPHY_RECAL_ST_SHIFT 6
216#define OMAP4430_DPLL_DDRPHY_RECAL_ST_MASK (1 << 6)
217
218/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU, PRM_IRQENABLE_TESLA */
219#define OMAP4430_DPLL_IVA_RECAL_EN_SHIFT 2
220#define OMAP4430_DPLL_IVA_RECAL_EN_MASK (1 << 2)
221
222/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU, PRM_IRQSTATUS_TESLA */
223#define OMAP4430_DPLL_IVA_RECAL_ST_SHIFT 2
224#define OMAP4430_DPLL_IVA_RECAL_ST_MASK (1 << 2)
225
226/* Used by PRM_IRQENABLE_MPU */
227#define OMAP4430_DPLL_MPU_RECAL_EN_SHIFT 1
228#define OMAP4430_DPLL_MPU_RECAL_EN_MASK (1 << 1)
229
230/* Used by PRM_IRQSTATUS_MPU */
231#define OMAP4430_DPLL_MPU_RECAL_ST_SHIFT 1
232#define OMAP4430_DPLL_MPU_RECAL_ST_MASK (1 << 1)
233
234/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
235#define OMAP4430_DPLL_PER_RECAL_EN_SHIFT 3
236#define OMAP4430_DPLL_PER_RECAL_EN_MASK (1 << 3)
237
238/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
239#define OMAP4430_DPLL_PER_RECAL_ST_SHIFT 3
240#define OMAP4430_DPLL_PER_RECAL_ST_MASK (1 << 3)
241
242/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
243#define OMAP4430_DPLL_UNIPRO_RECAL_EN_SHIFT 7
244#define OMAP4430_DPLL_UNIPRO_RECAL_EN_MASK (1 << 7)
245
246/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
247#define OMAP4430_DPLL_UNIPRO_RECAL_ST_SHIFT 7
248#define OMAP4430_DPLL_UNIPRO_RECAL_ST_MASK (1 << 7)
249
250/* Used by PM_DSS_PWRSTCTRL */
251#define OMAP4430_DSS_MEM_ONSTATE_SHIFT 16
252#define OMAP4430_DSS_MEM_ONSTATE_MASK (0x3 << 16)
253
254/* Used by PM_DSS_PWRSTCTRL */
255#define OMAP4430_DSS_MEM_RETSTATE_SHIFT 8
256#define OMAP4430_DSS_MEM_RETSTATE_MASK (1 << 8)
257
258/* Used by PM_DSS_PWRSTST */
259#define OMAP4430_DSS_MEM_STATEST_SHIFT 4
260#define OMAP4430_DSS_MEM_STATEST_MASK (0x3 << 4)
261
262/* Used by PM_CORE_PWRSTCTRL */
263#define OMAP4430_DUCATI_L2RAM_ONSTATE_SHIFT 20
264#define OMAP4430_DUCATI_L2RAM_ONSTATE_MASK (0x3 << 20)
265
266/* Used by PM_CORE_PWRSTCTRL */
267#define OMAP4430_DUCATI_L2RAM_RETSTATE_SHIFT 10
268#define OMAP4430_DUCATI_L2RAM_RETSTATE_MASK (1 << 10)
269
270/* Used by PM_CORE_PWRSTST */
271#define OMAP4430_DUCATI_L2RAM_STATEST_SHIFT 8
272#define OMAP4430_DUCATI_L2RAM_STATEST_MASK (0x3 << 8)
273
274/* Used by PM_CORE_PWRSTCTRL */
275#define OMAP4430_DUCATI_UNICACHE_ONSTATE_SHIFT 22
276#define OMAP4430_DUCATI_UNICACHE_ONSTATE_MASK (0x3 << 22)
277
278/* Used by PM_CORE_PWRSTCTRL */
279#define OMAP4430_DUCATI_UNICACHE_RETSTATE_SHIFT 11
280#define OMAP4430_DUCATI_UNICACHE_RETSTATE_MASK (1 << 11)
281
282/* Used by PM_CORE_PWRSTST */
283#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
284#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
285
286/* Used by PRM_DEVICE_OFF_CTRL */
287#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
288#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
289
290/* Used by PRM_DEVICE_OFF_CTRL */
291#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
292#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
293
294/* Used by RM_MPU_RSTST */
295#define OMAP4430_EMULATION_RST_SHIFT 0
296#define OMAP4430_EMULATION_RST_MASK (1 << 0)
297
298/* Used by RM_DUCATI_RSTST */
299#define OMAP4430_EMULATION_RST1ST_SHIFT 3
300#define OMAP4430_EMULATION_RST1ST_MASK (1 << 3)
301
302/* Used by RM_DUCATI_RSTST */
303#define OMAP4430_EMULATION_RST2ST_SHIFT 4
304#define OMAP4430_EMULATION_RST2ST_MASK (1 << 4)
305
306/* Used by RM_IVAHD_RSTST */
307#define OMAP4430_EMULATION_SEQ1_RST1ST_SHIFT 3
308#define OMAP4430_EMULATION_SEQ1_RST1ST_MASK (1 << 3)
309
310/* Used by RM_IVAHD_RSTST */
311#define OMAP4430_EMULATION_SEQ2_RST2ST_SHIFT 4
312#define OMAP4430_EMULATION_SEQ2_RST2ST_MASK (1 << 4)
313
314/* Used by PM_EMU_PWRSTCTRL */
315#define OMAP4430_EMU_BANK_ONSTATE_SHIFT 16
316#define OMAP4430_EMU_BANK_ONSTATE_MASK (0x3 << 16)
317
318/* Used by PM_EMU_PWRSTST */
319#define OMAP4430_EMU_BANK_STATEST_SHIFT 4
320#define OMAP4430_EMU_BANK_STATEST_MASK (0x3 << 4)
321
322/*
323 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
324 * PRM_LDO_SRAM_MPU_SETUP
325 */
326#define OMAP4430_ENFUNC1_EXPORT_SHIFT 3
327#define OMAP4430_ENFUNC1_EXPORT_MASK (1 << 3)
328
329/*
330 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
331 * PRM_LDO_SRAM_MPU_SETUP
332 */
333#define OMAP4430_ENFUNC3_EXPORT_SHIFT 5
334#define OMAP4430_ENFUNC3_EXPORT_MASK (1 << 5)
335
336/*
337 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
338 * PRM_LDO_SRAM_MPU_SETUP
339 */
340#define OMAP4430_ENFUNC4_SHIFT 6
341#define OMAP4430_ENFUNC4_MASK (1 << 6)
342
343/*
344 * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP,
345 * PRM_LDO_SRAM_MPU_SETUP
346 */
347#define OMAP4430_ENFUNC5_SHIFT 7
348#define OMAP4430_ENFUNC5_MASK (1 << 7)
349
350/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
351#define OMAP4430_ERRORGAIN_SHIFT 16
352#define OMAP4430_ERRORGAIN_MASK (0xff << 16) 30#define OMAP4430_ERRORGAIN_MASK (0xff << 16)
353
354/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
355#define OMAP4430_ERROROFFSET_SHIFT 24
356#define OMAP4430_ERROROFFSET_MASK (0xff << 24) 31#define OMAP4430_ERROROFFSET_MASK (0xff << 24)
357
358/* Used by PRM_RSTST */
359#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5 32#define OMAP4430_EXTERNAL_WARM_RST_SHIFT 5
360#define OMAP4430_EXTERNAL_WARM_RST_MASK (1 << 5)
361
362/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
363#define OMAP4430_FORCEUPDATE_SHIFT 1
364#define OMAP4430_FORCEUPDATE_MASK (1 << 1) 33#define OMAP4430_FORCEUPDATE_MASK (1 << 1)
365
366/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
367#define OMAP4430_FORCEUPDATEWAIT_SHIFT 8
368#define OMAP4430_FORCEUPDATEWAIT_MASK (0xffffff << 8)
369
370/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_TESLA */
371#define OMAP4430_FORCEWKUP_EN_SHIFT 10
372#define OMAP4430_FORCEWKUP_EN_MASK (1 << 10)
373
374/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_TESLA */
375#define OMAP4430_FORCEWKUP_ST_SHIFT 10
376#define OMAP4430_FORCEWKUP_ST_MASK (1 << 10)
377
378/* Used by REVISION_PRM */
379#define OMAP4430_FUNC_SHIFT 16
380#define OMAP4430_FUNC_MASK (0xfff << 16)
381
382/* Used by PM_GFX_PWRSTCTRL */
383#define OMAP4430_GFX_MEM_ONSTATE_SHIFT 16
384#define OMAP4430_GFX_MEM_ONSTATE_MASK (0x3 << 16)
385
386/* Used by PM_GFX_PWRSTST */
387#define OMAP4430_GFX_MEM_STATEST_SHIFT 4
388#define OMAP4430_GFX_MEM_STATEST_MASK (0x3 << 4)
389
390/* Used by PRM_RSTST */
391#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0 34#define OMAP4430_GLOBAL_COLD_RST_SHIFT 0
392#define OMAP4430_GLOBAL_COLD_RST_MASK (1 << 0)
393
394/* Used by PRM_RSTST */
395#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1 35#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
396#define OMAP4430_GLOBAL_WARM_SW_RST_MASK (1 << 1)
397
398/* Used by PRM_IO_PMCTRL */
399#define OMAP4430_GLOBAL_WUEN_SHIFT 16
400#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16) 36#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
401
402/* Used by PRM_VC_CFG_I2C_MODE */
403#define OMAP4430_HSMCODE_SHIFT 0
404#define OMAP4430_HSMCODE_MASK (0x7 << 0) 37#define OMAP4430_HSMCODE_MASK (0x7 << 0)
405
406/* Used by PRM_VC_CFG_I2C_MODE */
407#define OMAP4430_HSMODEEN_SHIFT 3
408#define OMAP4430_HSMODEEN_MASK (1 << 3) 38#define OMAP4430_HSMODEEN_MASK (1 << 3)
409
410/* Used by PRM_VC_CFG_I2C_CLK */
411#define OMAP4430_HSSCLH_SHIFT 16
412#define OMAP4430_HSSCLH_MASK (0xff << 16)
413
414/* Used by PRM_VC_CFG_I2C_CLK */
415#define OMAP4430_HSSCLL_SHIFT 24 39#define OMAP4430_HSSCLL_SHIFT 24
416#define OMAP4430_HSSCLL_MASK (0xff << 24)
417
418/* Used by PM_IVAHD_PWRSTCTRL */
419#define OMAP4430_HWA_MEM_ONSTATE_SHIFT 16
420#define OMAP4430_HWA_MEM_ONSTATE_MASK (0x3 << 16)
421
422/* Used by PM_IVAHD_PWRSTCTRL */
423#define OMAP4430_HWA_MEM_RETSTATE_SHIFT 8
424#define OMAP4430_HWA_MEM_RETSTATE_MASK (1 << 8)
425
426/* Used by PM_IVAHD_PWRSTST */
427#define OMAP4430_HWA_MEM_STATEST_SHIFT 4
428#define OMAP4430_HWA_MEM_STATEST_MASK (0x3 << 4)
429
430/* Used by RM_MPU_RSTST */
431#define OMAP4430_ICECRUSHER_MPU_RST_SHIFT 1
432#define OMAP4430_ICECRUSHER_MPU_RST_MASK (1 << 1)
433
434/* Used by RM_DUCATI_RSTST */
435#define OMAP4430_ICECRUSHER_RST1ST_SHIFT 5
436#define OMAP4430_ICECRUSHER_RST1ST_MASK (1 << 5)
437
438/* Used by RM_DUCATI_RSTST */
439#define OMAP4430_ICECRUSHER_RST2ST_SHIFT 6
440#define OMAP4430_ICECRUSHER_RST2ST_MASK (1 << 6)
441
442/* Used by RM_IVAHD_RSTST */
443#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_SHIFT 5
444#define OMAP4430_ICECRUSHER_SEQ1_RST1ST_MASK (1 << 5)
445
446/* Used by RM_IVAHD_RSTST */
447#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_SHIFT 6
448#define OMAP4430_ICECRUSHER_SEQ2_RST2ST_MASK (1 << 6)
449
450/* Used by PRM_RSTST */
451#define OMAP4430_ICEPICK_RST_SHIFT 9 40#define OMAP4430_ICEPICK_RST_SHIFT 9
452#define OMAP4430_ICEPICK_RST_MASK (1 << 9)
453
454/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
455#define OMAP4430_INITVDD_SHIFT 2
456#define OMAP4430_INITVDD_MASK (1 << 2) 41#define OMAP4430_INITVDD_MASK (1 << 2)
457
458/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
459#define OMAP4430_INITVOLTAGE_SHIFT 8
460#define OMAP4430_INITVOLTAGE_MASK (0xff << 8) 42#define OMAP4430_INITVOLTAGE_MASK (0xff << 8)
461
462/*
463 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
464 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
465 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
466 */
467#define OMAP4430_INTRANSITION_SHIFT 20
468#define OMAP4430_INTRANSITION_MASK (1 << 20)
469
470/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
471#define OMAP4430_IO_EN_SHIFT 9
472#define OMAP4430_IO_EN_MASK (1 << 9)
473
474/* Used by PRM_IO_PMCTRL */
475#define OMAP4430_IO_ON_STATUS_SHIFT 5
476#define OMAP4430_IO_ON_STATUS_MASK (1 << 5)
477
478/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
479#define OMAP4430_IO_ST_SHIFT 9
480#define OMAP4430_IO_ST_MASK (1 << 9)
481
482/* Used by PRM_IO_PMCTRL */
483#define OMAP4430_ISOCLK_OVERRIDE_SHIFT 0
484#define OMAP4430_ISOCLK_OVERRIDE_MASK (1 << 0)
485
486/* Used by PRM_IO_PMCTRL */
487#define OMAP4430_ISOCLK_STATUS_SHIFT 1
488#define OMAP4430_ISOCLK_STATUS_MASK (1 << 1)
489
490/* Used by PRM_IO_PMCTRL */
491#define OMAP4430_ISOOVR_EXTEND_SHIFT 4
492#define OMAP4430_ISOOVR_EXTEND_MASK (1 << 4)
493
494/* Used by PRM_IO_COUNT */
495#define OMAP4430_ISO_2_ON_TIME_SHIFT 0
496#define OMAP4430_ISO_2_ON_TIME_MASK (0xff << 0)
497
498/* Used by PM_L3INIT_PWRSTCTRL */
499#define OMAP4430_L3INIT_BANK1_ONSTATE_SHIFT 16
500#define OMAP4430_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
501
502/* Used by PM_L3INIT_PWRSTCTRL */
503#define OMAP4430_L3INIT_BANK1_RETSTATE_SHIFT 8
504#define OMAP4430_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
505
506/* Used by PM_L3INIT_PWRSTST */
507#define OMAP4430_L3INIT_BANK1_STATEST_SHIFT 4
508#define OMAP4430_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
509
510/*
511 * Used by PM_ABE_PWRSTST, PM_CORE_PWRSTST, PM_IVAHD_PWRSTST,
512 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
513 */
514#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24 43#define OMAP4430_LASTPOWERSTATEENTERED_SHIFT 24
515#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24) 44#define OMAP4430_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
516
517/*
518 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL,
519 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
520 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
521 */
522#define OMAP4430_LOGICRETSTATE_SHIFT 2 45#define OMAP4430_LOGICRETSTATE_SHIFT 2
523#define OMAP4430_LOGICRETSTATE_MASK (1 << 2) 46#define OMAP4430_LOGICRETSTATE_MASK (1 << 2)
524
525/*
526 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
527 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
528 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
529 */
530#define OMAP4430_LOGICSTATEST_SHIFT 2 47#define OMAP4430_LOGICSTATEST_SHIFT 2
531#define OMAP4430_LOGICSTATEST_MASK (1 << 2) 48#define OMAP4430_LOGICSTATEST_MASK (1 << 2)
532
533/*
534 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
535 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
536 * RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT, RM_ABE_TIMER5_CONTEXT,
537 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
538 * RM_ABE_WDT3_CONTEXT, RM_ALWON_MDMINTC_CONTEXT, RM_ALWON_SR_CORE_CONTEXT,
539 * RM_ALWON_SR_IVA_CONTEXT, RM_ALWON_SR_MPU_CONTEXT, RM_CAM_FDIF_CONTEXT,
540 * RM_CAM_ISS_CONTEXT, RM_CEFUSE_CEFUSE_CONTEXT, RM_D2D_SAD2D_CONTEXT,
541 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT,
542 * RM_DUCATI_DUCATI_CONTEXT, RM_EMU_DEBUGSS_CONTEXT, RM_GFX_GFX_CONTEXT,
543 * RM_IVAHD_IVAHD_CONTEXT, RM_IVAHD_SL2_CONTEXT, RM_L3INIT_CCPTX_CONTEXT,
544 * RM_L3INIT_EMAC_CONTEXT, RM_L3INIT_P1500_CONTEXT, RM_L3INIT_PCIESS_CONTEXT,
545 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
546 * RM_L3INIT_USBPHYOCP2SCP_CONTEXT, RM_L3INIT_XHPI_CONTEXT,
547 * RM_L3INSTR_L3_3_CONTEXT, RM_L3INSTR_L3_INSTR_CONTEXT,
548 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_L3_2_CONTEXT,
549 * RM_L3_2_OCMC_RAM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_SAR_ROM_CONTEXT,
550 * RM_L4PER_ADC_CONTEXT, RM_L4PER_DMTIMER10_CONTEXT,
551 * RM_L4PER_DMTIMER11_CONTEXT, RM_L4PER_DMTIMER2_CONTEXT,
552 * RM_L4PER_DMTIMER3_CONTEXT, RM_L4PER_DMTIMER4_CONTEXT,
553 * RM_L4PER_DMTIMER9_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
554 * RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT, RM_L4PER_I2C2_CONTEXT,
555 * RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT, RM_L4PER_I2C5_CONTEXT,
556 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCASP2_CONTEXT, RM_L4PER_MCASP3_CONTEXT,
557 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MCSPI1_CONTEXT, RM_L4PER_MCSPI2_CONTEXT,
558 * RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT, RM_L4PER_MGATE_CONTEXT,
559 * RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT, RM_L4PER_MMCSD5_CONTEXT,
560 * RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT,
561 * RM_L4SEC_PKAEIP29_CONTEXT, RM_MEMIF_DLL_CONTEXT, RM_MEMIF_DLL_H_CONTEXT,
562 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
563 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MPU_MPU_CONTEXT, RM_TESLA_TESLA_CONTEXT,
564 * RM_WKUP_GPIO1_CONTEXT, RM_WKUP_KEYBOARD_CONTEXT, RM_WKUP_L4WKUP_CONTEXT,
565 * RM_WKUP_RTC_CONTEXT, RM_WKUP_SARRAM_CONTEXT, RM_WKUP_SYNCTIMER_CONTEXT,
566 * RM_WKUP_TIMER12_CONTEXT, RM_WKUP_TIMER1_CONTEXT, RM_WKUP_USIM_CONTEXT,
567 * RM_WKUP_WDT1_CONTEXT, RM_WKUP_WDT2_CONTEXT
568 */
569#define OMAP4430_LOSTCONTEXT_DFF_SHIFT 0
570#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0) 49#define OMAP4430_LOSTCONTEXT_DFF_MASK (1 << 0)
571
572/*
573 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_D2D_SAD2D_CONTEXT,
574 * RM_D2D_SAD2D_FW_CONTEXT, RM_DSS_DSS_CONTEXT, RM_DUCATI_DUCATI_CONTEXT,
575 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
576 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_USB_HOST_CONTEXT,
577 * RM_L3INIT_USB_HOST_FS_CONTEXT, RM_L3INIT_USB_OTG_CONTEXT,
578 * RM_L3INIT_USB_TLL_CONTEXT, RM_L3INSTR_L3_3_CONTEXT,
579 * RM_L3INSTR_OCP_WP1_CONTEXT, RM_L3_1_L3_1_CONTEXT, RM_L3_2_GPMC_CONTEXT,
580 * RM_L3_2_L3_2_CONTEXT, RM_L4CFG_HW_SEM_CONTEXT, RM_L4CFG_L4_CFG_CONTEXT,
581 * RM_L4CFG_MAILBOX_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
582 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
583 * RM_L4PER_I2C1_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT,
584 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
585 * RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT, RM_L4SEC_CRYPTODMA_CONTEXT,
586 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_RNG_CONTEXT, RM_L4SEC_SHA2MD51_CONTEXT,
587 * RM_MEMIF_DMM_CONTEXT, RM_MEMIF_EMIF_1_CONTEXT, RM_MEMIF_EMIF_2_CONTEXT,
588 * RM_MEMIF_EMIF_FW_CONTEXT, RM_MEMIF_EMIF_H1_CONTEXT,
589 * RM_MEMIF_EMIF_H2_CONTEXT, RM_SDMA_SDMA_CONTEXT, RM_TESLA_TESLA_CONTEXT
590 */
591#define OMAP4430_LOSTCONTEXT_RFF_SHIFT 1
592#define OMAP4430_LOSTCONTEXT_RFF_MASK (1 << 1)
593
594/* Used by RM_ABE_AESS_CONTEXT */
595#define OMAP4430_LOSTMEM_AESSMEM_SHIFT 8
596#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8) 50#define OMAP4430_LOSTMEM_AESSMEM_MASK (1 << 8)
597
598/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
599#define OMAP4430_LOSTMEM_CAM_MEM_SHIFT 8
600#define OMAP4430_LOSTMEM_CAM_MEM_MASK (1 << 8)
601
602/* Used by RM_L3INSTR_OCP_WP1_CONTEXT */
603#define OMAP4430_LOSTMEM_CORE_NRET_BANK_SHIFT 8
604#define OMAP4430_LOSTMEM_CORE_NRET_BANK_MASK (1 << 8)
605
606/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_MEMIF_DMM_CONTEXT */
607#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_SHIFT 9
608#define OMAP4430_LOSTMEM_CORE_NRET_BANK_9_9_MASK (1 << 9)
609
610/* Used by RM_L3_2_OCMC_RAM_CONTEXT */
611#define OMAP4430_LOSTMEM_CORE_OCMRAM_SHIFT 8
612#define OMAP4430_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
613
614/*
615 * Used by RM_D2D_MODEM_ICR_CONTEXT, RM_MEMIF_DMM_CONTEXT,
616 * RM_SDMA_SDMA_CONTEXT
617 */
618#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
619#define OMAP4430_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
620
621/* Used by RM_DSS_DEISS_CONTEXT, RM_DSS_DSS_CONTEXT */
622#define OMAP4430_LOSTMEM_DSS_MEM_SHIFT 8
623#define OMAP4430_LOSTMEM_DSS_MEM_MASK (1 << 8)
624
625/* Used by RM_DUCATI_DUCATI_CONTEXT */
626#define OMAP4430_LOSTMEM_DUCATI_L2RAM_SHIFT 9
627#define OMAP4430_LOSTMEM_DUCATI_L2RAM_MASK (1 << 9)
628
629/* Used by RM_DUCATI_DUCATI_CONTEXT */
630#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_SHIFT 8
631#define OMAP4430_LOSTMEM_DUCATI_UNICACHE_MASK (1 << 8)
632
633/* Used by RM_EMU_DEBUGSS_CONTEXT */
634#define OMAP4430_LOSTMEM_EMU_BANK_SHIFT 8
635#define OMAP4430_LOSTMEM_EMU_BANK_MASK (1 << 8)
636
637/* Used by RM_GFX_GFX_CONTEXT */
638#define OMAP4430_LOSTMEM_GFX_MEM_SHIFT 8
639#define OMAP4430_LOSTMEM_GFX_MEM_MASK (1 << 8)
640
641/* Used by RM_IVAHD_IVAHD_CONTEXT */
642#define OMAP4430_LOSTMEM_HWA_MEM_SHIFT 10
643#define OMAP4430_LOSTMEM_HWA_MEM_MASK (1 << 10)
644
645/*
646 * Used by RM_L3INIT_CCPTX_CONTEXT, RM_L3INIT_EMAC_CONTEXT,
647 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
648 * RM_L3INIT_MMC6_CONTEXT, RM_L3INIT_PCIESS_CONTEXT, RM_L3INIT_SATA_CONTEXT,
649 * RM_L3INIT_TPPSS_CONTEXT, RM_L3INIT_UNIPRO1_CONTEXT,
650 * RM_L3INIT_USB_OTG_CONTEXT, RM_L3INIT_XHPI_CONTEXT
651 */
652#define OMAP4430_LOSTMEM_L3INIT_BANK1_SHIFT 8
653#define OMAP4430_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
654
655/* Used by RM_MPU_MPU_CONTEXT */
656#define OMAP4430_LOSTMEM_MPU_L1_SHIFT 8
657#define OMAP4430_LOSTMEM_MPU_L1_MASK (1 << 8)
658
659/* Used by RM_MPU_MPU_CONTEXT */
660#define OMAP4430_LOSTMEM_MPU_L2_SHIFT 9
661#define OMAP4430_LOSTMEM_MPU_L2_MASK (1 << 9)
662
663/* Used by RM_MPU_MPU_CONTEXT */
664#define OMAP4430_LOSTMEM_MPU_RAM_SHIFT 10
665#define OMAP4430_LOSTMEM_MPU_RAM_MASK (1 << 10)
666
667/*
668 * Used by RM_L4PER_HECC1_CONTEXT, RM_L4PER_HECC2_CONTEXT,
669 * RM_L4PER_MCBSP4_CONTEXT, RM_L4PER_MMCSD3_CONTEXT, RM_L4PER_MMCSD4_CONTEXT,
670 * RM_L4PER_MMCSD5_CONTEXT, RM_L4PER_SLIMBUS2_CONTEXT, RM_L4SEC_PKAEIP29_CONTEXT
671 */
672#define OMAP4430_LOSTMEM_NONRETAINED_BANK_SHIFT 8
673#define OMAP4430_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
674
675/*
676 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
677 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_PDM_CONTEXT, RM_ABE_SLIMBUS_CONTEXT
678 */
679#define OMAP4430_LOSTMEM_PERIHPMEM_SHIFT 8
680#define OMAP4430_LOSTMEM_PERIHPMEM_MASK (1 << 8)
681
682/*
683 * Used by RM_L4PER_MSPROHG_CONTEXT, RM_L4PER_UART1_CONTEXT,
684 * RM_L4PER_UART2_CONTEXT, RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT,
685 * RM_L4SEC_CRYPTODMA_CONTEXT
686 */
687#define OMAP4430_LOSTMEM_RETAINED_BANK_SHIFT 8
688#define OMAP4430_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
689
690/* Used by RM_IVAHD_SL2_CONTEXT */
691#define OMAP4430_LOSTMEM_SL2_MEM_SHIFT 8
692#define OMAP4430_LOSTMEM_SL2_MEM_MASK (1 << 8)
693
694/* Used by RM_IVAHD_IVAHD_CONTEXT */
695#define OMAP4430_LOSTMEM_TCM1_MEM_SHIFT 8
696#define OMAP4430_LOSTMEM_TCM1_MEM_MASK (1 << 8)
697
698/* Used by RM_IVAHD_IVAHD_CONTEXT */
699#define OMAP4430_LOSTMEM_TCM2_MEM_SHIFT 9
700#define OMAP4430_LOSTMEM_TCM2_MEM_MASK (1 << 9)
701
702/* Used by RM_TESLA_TESLA_CONTEXT */
703#define OMAP4430_LOSTMEM_TESLA_EDMA_SHIFT 10
704#define OMAP4430_LOSTMEM_TESLA_EDMA_MASK (1 << 10)
705
706/* Used by RM_TESLA_TESLA_CONTEXT */
707#define OMAP4430_LOSTMEM_TESLA_L1_SHIFT 8
708#define OMAP4430_LOSTMEM_TESLA_L1_MASK (1 << 8)
709
710/* Used by RM_TESLA_TESLA_CONTEXT */
711#define OMAP4430_LOSTMEM_TESLA_L2_SHIFT 9
712#define OMAP4430_LOSTMEM_TESLA_L2_MASK (1 << 9)
713
714/* Used by RM_WKUP_SARRAM_CONTEXT */
715#define OMAP4430_LOSTMEM_WKUP_BANK_SHIFT 8
716#define OMAP4430_LOSTMEM_WKUP_BANK_MASK (1 << 8)
717
718/*
719 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
720 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_GFX_PWRSTCTRL, PM_IVAHD_PWRSTCTRL,
721 * PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
722 */
723#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4 51#define OMAP4430_LOWPOWERSTATECHANGE_SHIFT 4
724#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4) 52#define OMAP4430_LOWPOWERSTATECHANGE_MASK (1 << 4)
725
726/* Used by PRM_MODEM_IF_CTRL */
727#define OMAP4430_MODEM_READY_SHIFT 1
728#define OMAP4430_MODEM_READY_MASK (1 << 1)
729
730/* Used by PRM_MODEM_IF_CTRL */
731#define OMAP4430_MODEM_SHUTDOWN_IRQ_SHIFT 9
732#define OMAP4430_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
733
734/* Used by PRM_MODEM_IF_CTRL */
735#define OMAP4430_MODEM_SLEEP_ST_SHIFT 16
736#define OMAP4430_MODEM_SLEEP_ST_MASK (1 << 16)
737
738/* Used by PRM_MODEM_IF_CTRL */
739#define OMAP4430_MODEM_WAKE_IRQ_SHIFT 8
740#define OMAP4430_MODEM_WAKE_IRQ_MASK (1 << 8)
741
742/* Used by PM_MPU_PWRSTCTRL */
743#define OMAP4430_MPU_L1_ONSTATE_SHIFT 16
744#define OMAP4430_MPU_L1_ONSTATE_MASK (0x3 << 16)
745
746/* Used by PM_MPU_PWRSTCTRL */
747#define OMAP4430_MPU_L1_RETSTATE_SHIFT 8
748#define OMAP4430_MPU_L1_RETSTATE_MASK (1 << 8)
749
750/* Used by PM_MPU_PWRSTST */
751#define OMAP4430_MPU_L1_STATEST_SHIFT 4
752#define OMAP4430_MPU_L1_STATEST_MASK (0x3 << 4)
753
754/* Used by PM_MPU_PWRSTCTRL */
755#define OMAP4430_MPU_L2_ONSTATE_SHIFT 18
756#define OMAP4430_MPU_L2_ONSTATE_MASK (0x3 << 18)
757
758/* Used by PM_MPU_PWRSTCTRL */
759#define OMAP4430_MPU_L2_RETSTATE_SHIFT 9
760#define OMAP4430_MPU_L2_RETSTATE_MASK (1 << 9)
761
762/* Used by PM_MPU_PWRSTST */
763#define OMAP4430_MPU_L2_STATEST_SHIFT 6
764#define OMAP4430_MPU_L2_STATEST_MASK (0x3 << 6)
765
766/* Used by PM_MPU_PWRSTCTRL */
767#define OMAP4430_MPU_RAM_ONSTATE_SHIFT 20
768#define OMAP4430_MPU_RAM_ONSTATE_MASK (0x3 << 20)
769
770/* Used by PM_MPU_PWRSTCTRL */
771#define OMAP4430_MPU_RAM_RETSTATE_SHIFT 10
772#define OMAP4430_MPU_RAM_RETSTATE_MASK (1 << 10)
773
774/* Used by PM_MPU_PWRSTST */
775#define OMAP4430_MPU_RAM_STATEST_SHIFT 8
776#define OMAP4430_MPU_RAM_STATEST_MASK (0x3 << 8)
777
778/* Used by PRM_RSTST */
779#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2 53#define OMAP4430_MPU_SECURITY_VIOL_RST_SHIFT 2
780#define OMAP4430_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
781
782/* Used by PRM_RSTST */
783#define OMAP4430_MPU_WDT_RST_SHIFT 3 54#define OMAP4430_MPU_WDT_RST_SHIFT 3
784#define OMAP4430_MPU_WDT_RST_MASK (1 << 3)
785
786/* Used by PM_L4PER_PWRSTCTRL */
787#define OMAP4430_NONRETAINED_BANK_ONSTATE_SHIFT 18
788#define OMAP4430_NONRETAINED_BANK_ONSTATE_MASK (0x3 << 18)
789
790/* Used by PM_L4PER_PWRSTCTRL */
791#define OMAP4430_NONRETAINED_BANK_RETSTATE_SHIFT 9
792#define OMAP4430_NONRETAINED_BANK_RETSTATE_MASK (1 << 9)
793
794/* Used by PM_L4PER_PWRSTST */
795#define OMAP4430_NONRETAINED_BANK_STATEST_SHIFT 6
796#define OMAP4430_NONRETAINED_BANK_STATEST_MASK (0x3 << 6)
797
798/* Used by PM_CORE_PWRSTCTRL */
799#define OMAP4430_OCP_NRET_BANK_ONSTATE_SHIFT 24
800#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24) 55#define OMAP4430_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
801
802/* Used by PM_CORE_PWRSTCTRL */
803#define OMAP4430_OCP_NRET_BANK_RETSTATE_SHIFT 12
804#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12) 56#define OMAP4430_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
805
806/* Used by PM_CORE_PWRSTST */
807#define OMAP4430_OCP_NRET_BANK_STATEST_SHIFT 12
808#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12) 57#define OMAP4430_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
809
810/*
811 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
812 * PRM_VC_VAL_CMD_VDD_MPU_L
813 */
814#define OMAP4430_OFF_SHIFT 0 58#define OMAP4430_OFF_SHIFT 0
815#define OMAP4430_OFF_MASK (0xff << 0)
816
817/*
818 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
819 * PRM_VC_VAL_CMD_VDD_MPU_L
820 */
821#define OMAP4430_ON_SHIFT 24 59#define OMAP4430_ON_SHIFT 24
822#define OMAP4430_ON_MASK (0xff << 24) 60#define OMAP4430_ON_MASK (0xff << 24)
823
824/*
825 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
826 * PRM_VC_VAL_CMD_VDD_MPU_L
827 */
828#define OMAP4430_ONLP_SHIFT 16 61#define OMAP4430_ONLP_SHIFT 16
829#define OMAP4430_ONLP_MASK (0xff << 16)
830
831/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
832#define OMAP4430_OPP_CHANGE_SHIFT 2
833#define OMAP4430_OPP_CHANGE_MASK (1 << 2)
834
835/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
836#define OMAP4430_OPP_SEL_SHIFT 0
837#define OMAP4430_OPP_SEL_MASK (0x3 << 0)
838
839/* Used by PRM_SRAM_COUNT */
840#define OMAP4430_PCHARGECNT_VALUE_SHIFT 0
841#define OMAP4430_PCHARGECNT_VALUE_MASK (0x3f << 0)
842
843/* Used by PRM_PSCON_COUNT */
844#define OMAP4430_PCHARGE_TIME_SHIFT 0
845#define OMAP4430_PCHARGE_TIME_MASK (0xff << 0)
846
847/* Used by PM_ABE_PWRSTCTRL */
848#define OMAP4430_PERIPHMEM_ONSTATE_SHIFT 20
849#define OMAP4430_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
850
851/* Used by PM_ABE_PWRSTCTRL */
852#define OMAP4430_PERIPHMEM_RETSTATE_SHIFT 10
853#define OMAP4430_PERIPHMEM_RETSTATE_MASK (1 << 10)
854
855/* Used by PM_ABE_PWRSTST */
856#define OMAP4430_PERIPHMEM_STATEST_SHIFT 8
857#define OMAP4430_PERIPHMEM_STATEST_MASK (0x3 << 8)
858
859/* Used by PRM_PHASE1_CNDP */
860#define OMAP4430_PHASE1_CNDP_SHIFT 0
861#define OMAP4430_PHASE1_CNDP_MASK (0xffffffff << 0)
862
863/* Used by PRM_PHASE2A_CNDP */
864#define OMAP4430_PHASE2A_CNDP_SHIFT 0
865#define OMAP4430_PHASE2A_CNDP_MASK (0xffffffff << 0)
866
867/* Used by PRM_PHASE2B_CNDP */
868#define OMAP4430_PHASE2B_CNDP_SHIFT 0
869#define OMAP4430_PHASE2B_CNDP_MASK (0xffffffff << 0)
870
871/* Used by PRM_PSCON_COUNT */
872#define OMAP4430_PONOUT_2_PGOODIN_TIME_SHIFT 8
873#define OMAP4430_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
874
875/*
876 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL,
877 * PM_CORE_PWRSTCTRL, PM_DSS_PWRSTCTRL, PM_EMU_PWRSTCTRL, PM_GFX_PWRSTCTRL,
878 * PM_IVAHD_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_L4PER_PWRSTCTRL,
879 * PM_MPU_PWRSTCTRL, PM_TESLA_PWRSTCTRL
880 */
881#define OMAP4430_POWERSTATE_SHIFT 0
882#define OMAP4430_POWERSTATE_MASK (0x3 << 0)
883
884/*
885 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CEFUSE_PWRSTST, PM_CORE_PWRSTST,
886 * PM_DSS_PWRSTST, PM_EMU_PWRSTST, PM_GFX_PWRSTST, PM_IVAHD_PWRSTST,
887 * PM_L3INIT_PWRSTST, PM_L4PER_PWRSTST, PM_MPU_PWRSTST, PM_TESLA_PWRSTST
888 */
889#define OMAP4430_POWERSTATEST_SHIFT 0
890#define OMAP4430_POWERSTATEST_MASK (0x3 << 0)
891
892/* Used by PRM_PWRREQCTRL */
893#define OMAP4430_PWRREQ_COND_SHIFT 0
894#define OMAP4430_PWRREQ_COND_MASK (0x3 << 0)
895
896/* Used by PRM_VC_CFG_CHANNEL */
897#define OMAP4430_RACEN_VDD_CORE_L_SHIFT 3
898#define OMAP4430_RACEN_VDD_CORE_L_MASK (1 << 3)
899
900/* Used by PRM_VC_CFG_CHANNEL */
901#define OMAP4430_RACEN_VDD_IVA_L_SHIFT 11
902#define OMAP4430_RACEN_VDD_IVA_L_MASK (1 << 11)
903
904/* Used by PRM_VC_CFG_CHANNEL */
905#define OMAP4430_RACEN_VDD_MPU_L_SHIFT 20
906#define OMAP4430_RACEN_VDD_MPU_L_MASK (1 << 20)
907
908/* Used by PRM_VC_CFG_CHANNEL */
909#define OMAP4430_RAC_VDD_CORE_L_SHIFT 2
910#define OMAP4430_RAC_VDD_CORE_L_MASK (1 << 2)
911
912/* Used by PRM_VC_CFG_CHANNEL */
913#define OMAP4430_RAC_VDD_IVA_L_SHIFT 10
914#define OMAP4430_RAC_VDD_IVA_L_MASK (1 << 10)
915
916/* Used by PRM_VC_CFG_CHANNEL */
917#define OMAP4430_RAC_VDD_MPU_L_SHIFT 19
918#define OMAP4430_RAC_VDD_MPU_L_MASK (1 << 19)
919
920/*
921 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
922 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
923 * PRM_VOLTSETUP_MPU_RET_SLEEP
924 */
925#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16 62#define OMAP4430_RAMP_DOWN_COUNT_SHIFT 16
926#define OMAP4430_RAMP_DOWN_COUNT_MASK (0x3f << 16)
927
928/*
929 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
930 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
931 * PRM_VOLTSETUP_MPU_RET_SLEEP
932 */
933#define OMAP4430_RAMP_DOWN_PRESCAL_SHIFT 24
934#define OMAP4430_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
935
936/*
937 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
938 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
939 * PRM_VOLTSETUP_MPU_RET_SLEEP
940 */
941#define OMAP4430_RAMP_UP_COUNT_SHIFT 0 63#define OMAP4430_RAMP_UP_COUNT_SHIFT 0
942#define OMAP4430_RAMP_UP_COUNT_MASK (0x3f << 0)
943
944/*
945 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
946 * PRM_VOLTSETUP_IVA_OFF, PRM_VOLTSETUP_IVA_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
947 * PRM_VOLTSETUP_MPU_RET_SLEEP
948 */
949#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8 64#define OMAP4430_RAMP_UP_PRESCAL_SHIFT 8
950#define OMAP4430_RAMP_UP_PRESCAL_MASK (0x3 << 8)
951
952/* Used by PRM_VC_CFG_CHANNEL */
953#define OMAP4430_RAV_VDD_CORE_L_SHIFT 1
954#define OMAP4430_RAV_VDD_CORE_L_MASK (1 << 1)
955
956/* Used by PRM_VC_CFG_CHANNEL */
957#define OMAP4430_RAV_VDD_IVA_L_SHIFT 9
958#define OMAP4430_RAV_VDD_IVA_L_MASK (1 << 9)
959
960/* Used by PRM_VC_CFG_CHANNEL */
961#define OMAP4430_RAV_VDD_MPU_L_SHIFT 18
962#define OMAP4430_RAV_VDD_MPU_L_MASK (1 << 18)
963
964/* Used by PRM_VC_VAL_BYPASS */
965#define OMAP4430_REGADDR_SHIFT 8 65#define OMAP4430_REGADDR_SHIFT 8
966#define OMAP4430_REGADDR_MASK (0xff << 8)
967
968/*
969 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_IVA_L,
970 * PRM_VC_VAL_CMD_VDD_MPU_L
971 */
972#define OMAP4430_RET_SHIFT 8 66#define OMAP4430_RET_SHIFT 8
973#define OMAP4430_RET_MASK (0xff << 8)
974
975/* Used by PM_L4PER_PWRSTCTRL */
976#define OMAP4430_RETAINED_BANK_ONSTATE_SHIFT 16
977#define OMAP4430_RETAINED_BANK_ONSTATE_MASK (0x3 << 16)
978
979/* Used by PM_L4PER_PWRSTCTRL */
980#define OMAP4430_RETAINED_BANK_RETSTATE_SHIFT 8
981#define OMAP4430_RETAINED_BANK_RETSTATE_MASK (1 << 8)
982
983/* Used by PM_L4PER_PWRSTST */
984#define OMAP4430_RETAINED_BANK_STATEST_SHIFT 4
985#define OMAP4430_RETAINED_BANK_STATEST_MASK (0x3 << 4)
986
987/*
988 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
989 * PRM_LDO_SRAM_MPU_CTRL
990 */
991#define OMAP4430_RETMODE_ENABLE_SHIFT 0
992#define OMAP4430_RETMODE_ENABLE_MASK (1 << 0)
993
994/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
995#define OMAP4430_RST1_SHIFT 0
996#define OMAP4430_RST1_MASK (1 << 0)
997
998/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
999#define OMAP4430_RST1ST_SHIFT 0
1000#define OMAP4430_RST1ST_MASK (1 << 0)
1001
1002/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL, RM_TESLA_RSTCTRL */
1003#define OMAP4430_RST2_SHIFT 1
1004#define OMAP4430_RST2_MASK (1 << 1)
1005
1006/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST, RM_TESLA_RSTST */
1007#define OMAP4430_RST2ST_SHIFT 1
1008#define OMAP4430_RST2ST_MASK (1 << 1)
1009
1010/* Used by RM_DUCATI_RSTCTRL, RM_IVAHD_RSTCTRL */
1011#define OMAP4430_RST3_SHIFT 2
1012#define OMAP4430_RST3_MASK (1 << 2)
1013
1014/* Used by RM_DUCATI_RSTST, RM_IVAHD_RSTST */
1015#define OMAP4430_RST3ST_SHIFT 2
1016#define OMAP4430_RST3ST_MASK (1 << 2)
1017
1018/* Used by PRM_RSTTIME */
1019#define OMAP4430_RSTTIME1_SHIFT 0
1020#define OMAP4430_RSTTIME1_MASK (0x3ff << 0)
1021
1022/* Used by PRM_RSTTIME */
1023#define OMAP4430_RSTTIME2_SHIFT 10
1024#define OMAP4430_RSTTIME2_MASK (0x1f << 10)
1025
1026/* Used by PRM_RSTCTRL */
1027#define OMAP4430_RST_GLOBAL_COLD_SW_SHIFT 1
1028#define OMAP4430_RST_GLOBAL_COLD_SW_MASK (1 << 1)
1029
1030/* Used by PRM_RSTCTRL */
1031#define OMAP4430_RST_GLOBAL_WARM_SW_SHIFT 0
1032#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0) 67#define OMAP4430_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1033
1034/* Used by REVISION_PRM */
1035#define OMAP4430_R_RTL_SHIFT 11
1036#define OMAP4430_R_RTL_MASK (0x1f << 11)
1037
1038/* Used by PRM_VC_CFG_CHANNEL */
1039#define OMAP4430_SA_VDD_CORE_L_SHIFT 0 68#define OMAP4430_SA_VDD_CORE_L_SHIFT 0
1040#define OMAP4430_SA_VDD_CORE_L_MASK (1 << 0)
1041
1042/* Renamed from SA_VDD_CORE_L Used by PRM_VC_SMPS_SA */
1043#define OMAP4430_SA_VDD_CORE_L_0_6_SHIFT 0
1044#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0) 69#define OMAP4430_SA_VDD_CORE_L_0_6_MASK (0x7f << 0)
1045
1046/* Used by PRM_VC_CFG_CHANNEL */
1047#define OMAP4430_SA_VDD_IVA_L_SHIFT 8 70#define OMAP4430_SA_VDD_IVA_L_SHIFT 8
1048#define OMAP4430_SA_VDD_IVA_L_MASK (1 << 8)
1049
1050/* Renamed from SA_VDD_IVA_L Used by PRM_VC_SMPS_SA */
1051#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_SHIFT 8
1052#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8) 71#define OMAP4430_SA_VDD_IVA_L_PRM_VC_SMPS_SA_MASK (0x7f << 8)
1053
1054/* Used by PRM_VC_CFG_CHANNEL */
1055#define OMAP4430_SA_VDD_MPU_L_SHIFT 16 72#define OMAP4430_SA_VDD_MPU_L_SHIFT 16
1056#define OMAP4430_SA_VDD_MPU_L_MASK (1 << 16)
1057
1058/* Renamed from SA_VDD_MPU_L Used by PRM_VC_SMPS_SA */
1059#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_SHIFT 16
1060#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16) 73#define OMAP4430_SA_VDD_MPU_L_PRM_VC_SMPS_SA_MASK (0x7f << 16)
1061
1062/* Used by REVISION_PRM */
1063#define OMAP4430_SCHEME_SHIFT 30
1064#define OMAP4430_SCHEME_MASK (0x3 << 30)
1065
1066/* Used by PRM_VC_CFG_I2C_CLK */
1067#define OMAP4430_SCLH_SHIFT 0 74#define OMAP4430_SCLH_SHIFT 0
1068#define OMAP4430_SCLH_MASK (0xff << 0)
1069
1070/* Used by PRM_VC_CFG_I2C_CLK */
1071#define OMAP4430_SCLL_SHIFT 8 75#define OMAP4430_SCLL_SHIFT 8
1072#define OMAP4430_SCLL_MASK (0xff << 8)
1073
1074/* Used by PRM_RSTST */
1075#define OMAP4430_SECURE_WDT_RST_SHIFT 4 76#define OMAP4430_SECURE_WDT_RST_SHIFT 4
1076#define OMAP4430_SECURE_WDT_RST_MASK (1 << 4)
1077
1078/* Used by PM_IVAHD_PWRSTCTRL */
1079#define OMAP4430_SL2_MEM_ONSTATE_SHIFT 18
1080#define OMAP4430_SL2_MEM_ONSTATE_MASK (0x3 << 18)
1081
1082/* Used by PM_IVAHD_PWRSTCTRL */
1083#define OMAP4430_SL2_MEM_RETSTATE_SHIFT 9
1084#define OMAP4430_SL2_MEM_RETSTATE_MASK (1 << 9)
1085
1086/* Used by PM_IVAHD_PWRSTST */
1087#define OMAP4430_SL2_MEM_STATEST_SHIFT 6
1088#define OMAP4430_SL2_MEM_STATEST_MASK (0x3 << 6)
1089
1090/* Used by PRM_VC_VAL_BYPASS */
1091#define OMAP4430_SLAVEADDR_SHIFT 0 77#define OMAP4430_SLAVEADDR_SHIFT 0
1092#define OMAP4430_SLAVEADDR_MASK (0x7f << 0)
1093
1094/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1095#define OMAP4430_SLEEP_RBB_SEL_SHIFT 3
1096#define OMAP4430_SLEEP_RBB_SEL_MASK (1 << 3)
1097
1098/* Used by PRM_SRAM_COUNT */
1099#define OMAP4430_SLPCNT_VALUE_SHIFT 16
1100#define OMAP4430_SLPCNT_VALUE_MASK (0xff << 16)
1101
1102/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1103#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8 78#define OMAP4430_SMPSWAITTIMEMAX_SHIFT 8
1104#define OMAP4430_SMPSWAITTIMEMAX_MASK (0xffff << 8)
1105
1106/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1107#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8 79#define OMAP4430_SMPSWAITTIMEMIN_SHIFT 8
1108#define OMAP4430_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1109
1110/* Used by PRM_VC_ERRST */
1111#define OMAP4430_SMPS_RA_ERR_CORE_SHIFT 1
1112#define OMAP4430_SMPS_RA_ERR_CORE_MASK (1 << 1)
1113
1114/* Used by PRM_VC_ERRST */
1115#define OMAP4430_SMPS_RA_ERR_IVA_SHIFT 9
1116#define OMAP4430_SMPS_RA_ERR_IVA_MASK (1 << 9)
1117
1118/* Used by PRM_VC_ERRST */
1119#define OMAP4430_SMPS_RA_ERR_MPU_SHIFT 17
1120#define OMAP4430_SMPS_RA_ERR_MPU_MASK (1 << 17)
1121
1122/* Used by PRM_VC_ERRST */
1123#define OMAP4430_SMPS_SA_ERR_CORE_SHIFT 0
1124#define OMAP4430_SMPS_SA_ERR_CORE_MASK (1 << 0)
1125
1126/* Used by PRM_VC_ERRST */
1127#define OMAP4430_SMPS_SA_ERR_IVA_SHIFT 8
1128#define OMAP4430_SMPS_SA_ERR_IVA_MASK (1 << 8)
1129
1130/* Used by PRM_VC_ERRST */
1131#define OMAP4430_SMPS_SA_ERR_MPU_SHIFT 16
1132#define OMAP4430_SMPS_SA_ERR_MPU_MASK (1 << 16)
1133
1134/* Used by PRM_VC_ERRST */
1135#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1136#define OMAP4430_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1137
1138/* Used by PRM_VC_ERRST */
1139#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_SHIFT 10
1140#define OMAP4430_SMPS_TIMEOUT_ERR_IVA_MASK (1 << 10)
1141
1142/* Used by PRM_VC_ERRST */
1143#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_SHIFT 18
1144#define OMAP4430_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 18)
1145
1146/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1147#define OMAP4430_SR2EN_SHIFT 0
1148#define OMAP4430_SR2EN_MASK (1 << 0)
1149
1150/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1151#define OMAP4430_SR2_IN_TRANSITION_SHIFT 6
1152#define OMAP4430_SR2_IN_TRANSITION_MASK (1 << 6)
1153
1154/* Used by PRM_LDO_ABB_IVA_CTRL, PRM_LDO_ABB_MPU_CTRL */
1155#define OMAP4430_SR2_STATUS_SHIFT 3
1156#define OMAP4430_SR2_STATUS_MASK (0x3 << 3)
1157
1158/* Used by PRM_LDO_ABB_IVA_SETUP, PRM_LDO_ABB_MPU_SETUP */
1159#define OMAP4430_SR2_WTCNT_VALUE_SHIFT 8
1160#define OMAP4430_SR2_WTCNT_VALUE_MASK (0xff << 8)
1161
1162/*
1163 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1164 * PRM_LDO_SRAM_MPU_CTRL
1165 */
1166#define OMAP4430_SRAMLDO_STATUS_SHIFT 8
1167#define OMAP4430_SRAMLDO_STATUS_MASK (1 << 8)
1168
1169/*
1170 * Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_IVA_CTRL,
1171 * PRM_LDO_SRAM_MPU_CTRL
1172 */
1173#define OMAP4430_SRAM_IN_TRANSITION_SHIFT 9
1174#define OMAP4430_SRAM_IN_TRANSITION_MASK (1 << 9)
1175
1176/* Used by PRM_VC_CFG_I2C_MODE */
1177#define OMAP4430_SRMODEEN_SHIFT 4
1178#define OMAP4430_SRMODEEN_MASK (1 << 4)
1179
1180/* Used by PRM_VOLTSETUP_WARMRESET */
1181#define OMAP4430_STABLE_COUNT_SHIFT 0
1182#define OMAP4430_STABLE_COUNT_MASK (0x3f << 0)
1183
1184/* Used by PRM_VOLTSETUP_WARMRESET */
1185#define OMAP4430_STABLE_PRESCAL_SHIFT 8
1186#define OMAP4430_STABLE_PRESCAL_MASK (0x3 << 8)
1187
1188/* Used by PRM_LDO_BANDGAP_SETUP */
1189#define OMAP4430_STARTUP_COUNT_SHIFT 0
1190#define OMAP4430_STARTUP_COUNT_MASK (0xff << 0)
1191
1192/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1193#define OMAP4430_STARTUP_COUNT_24_31_SHIFT 24
1194#define OMAP4430_STARTUP_COUNT_24_31_MASK (0xff << 24)
1195
1196/* Used by PM_IVAHD_PWRSTCTRL */
1197#define OMAP4430_TCM1_MEM_ONSTATE_SHIFT 20
1198#define OMAP4430_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
1199
1200/* Used by PM_IVAHD_PWRSTCTRL */
1201#define OMAP4430_TCM1_MEM_RETSTATE_SHIFT 10
1202#define OMAP4430_TCM1_MEM_RETSTATE_MASK (1 << 10)
1203
1204/* Used by PM_IVAHD_PWRSTST */
1205#define OMAP4430_TCM1_MEM_STATEST_SHIFT 8
1206#define OMAP4430_TCM1_MEM_STATEST_MASK (0x3 << 8)
1207
1208/* Used by PM_IVAHD_PWRSTCTRL */
1209#define OMAP4430_TCM2_MEM_ONSTATE_SHIFT 22
1210#define OMAP4430_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
1211
1212/* Used by PM_IVAHD_PWRSTCTRL */
1213#define OMAP4430_TCM2_MEM_RETSTATE_SHIFT 11
1214#define OMAP4430_TCM2_MEM_RETSTATE_MASK (1 << 11)
1215
1216/* Used by PM_IVAHD_PWRSTST */
1217#define OMAP4430_TCM2_MEM_STATEST_SHIFT 10
1218#define OMAP4430_TCM2_MEM_STATEST_MASK (0x3 << 10)
1219
1220/* Used by RM_TESLA_RSTST */
1221#define OMAP4430_TESLASS_EMU_RSTST_SHIFT 2
1222#define OMAP4430_TESLASS_EMU_RSTST_MASK (1 << 2)
1223
1224/* Used by RM_TESLA_RSTST */
1225#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_SHIFT 3
1226#define OMAP4430_TESLA_DSP_EMU_REQ_RSTST_MASK (1 << 3)
1227
1228/* Used by PM_TESLA_PWRSTCTRL */
1229#define OMAP4430_TESLA_EDMA_ONSTATE_SHIFT 20
1230#define OMAP4430_TESLA_EDMA_ONSTATE_MASK (0x3 << 20)
1231
1232/* Used by PM_TESLA_PWRSTCTRL */
1233#define OMAP4430_TESLA_EDMA_RETSTATE_SHIFT 10
1234#define OMAP4430_TESLA_EDMA_RETSTATE_MASK (1 << 10)
1235
1236/* Used by PM_TESLA_PWRSTST */
1237#define OMAP4430_TESLA_EDMA_STATEST_SHIFT 8
1238#define OMAP4430_TESLA_EDMA_STATEST_MASK (0x3 << 8)
1239
1240/* Used by PM_TESLA_PWRSTCTRL */
1241#define OMAP4430_TESLA_L1_ONSTATE_SHIFT 16
1242#define OMAP4430_TESLA_L1_ONSTATE_MASK (0x3 << 16)
1243
1244/* Used by PM_TESLA_PWRSTCTRL */
1245#define OMAP4430_TESLA_L1_RETSTATE_SHIFT 8
1246#define OMAP4430_TESLA_L1_RETSTATE_MASK (1 << 8)
1247
1248/* Used by PM_TESLA_PWRSTST */
1249#define OMAP4430_TESLA_L1_STATEST_SHIFT 4
1250#define OMAP4430_TESLA_L1_STATEST_MASK (0x3 << 4)
1251
1252/* Used by PM_TESLA_PWRSTCTRL */
1253#define OMAP4430_TESLA_L2_ONSTATE_SHIFT 18
1254#define OMAP4430_TESLA_L2_ONSTATE_MASK (0x3 << 18)
1255
1256/* Used by PM_TESLA_PWRSTCTRL */
1257#define OMAP4430_TESLA_L2_RETSTATE_SHIFT 9
1258#define OMAP4430_TESLA_L2_RETSTATE_MASK (1 << 9)
1259
1260/* Used by PM_TESLA_PWRSTST */
1261#define OMAP4430_TESLA_L2_STATEST_SHIFT 6
1262#define OMAP4430_TESLA_L2_STATEST_MASK (0x3 << 6)
1263
1264/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1265#define OMAP4430_TIMEOUT_SHIFT 0 80#define OMAP4430_TIMEOUT_SHIFT 0
1266#define OMAP4430_TIMEOUT_MASK (0xffff << 0)
1267
1268/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
1269#define OMAP4430_TIMEOUTEN_SHIFT 3
1270#define OMAP4430_TIMEOUTEN_MASK (1 << 3) 81#define OMAP4430_TIMEOUTEN_MASK (1 << 3)
1271
1272/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1273#define OMAP4430_TRANSITION_EN_SHIFT 8
1274#define OMAP4430_TRANSITION_EN_MASK (1 << 8)
1275
1276/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1277#define OMAP4430_TRANSITION_ST_SHIFT 8
1278#define OMAP4430_TRANSITION_ST_MASK (1 << 8)
1279
1280/* Used by PRM_VC_VAL_BYPASS */
1281#define OMAP4430_VALID_SHIFT 24
1282#define OMAP4430_VALID_MASK (1 << 24) 82#define OMAP4430_VALID_MASK (1 << 24)
1283
1284/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1285#define OMAP4430_VC_BYPASSACK_EN_SHIFT 14
1286#define OMAP4430_VC_BYPASSACK_EN_MASK (1 << 14)
1287
1288/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1289#define OMAP4430_VC_BYPASSACK_ST_SHIFT 14
1290#define OMAP4430_VC_BYPASSACK_ST_MASK (1 << 14)
1291
1292/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1293#define OMAP4430_VC_CORE_VPACK_EN_SHIFT 22
1294#define OMAP4430_VC_CORE_VPACK_EN_MASK (1 << 22)
1295
1296/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1297#define OMAP4430_VC_CORE_VPACK_ST_SHIFT 22
1298#define OMAP4430_VC_CORE_VPACK_ST_MASK (1 << 22)
1299
1300/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1301#define OMAP4430_VC_IVA_VPACK_EN_SHIFT 30
1302#define OMAP4430_VC_IVA_VPACK_EN_MASK (1 << 30)
1303
1304/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1305#define OMAP4430_VC_IVA_VPACK_ST_SHIFT 30
1306#define OMAP4430_VC_IVA_VPACK_ST_MASK (1 << 30)
1307
1308/* Used by PRM_IRQENABLE_MPU_2 */
1309#define OMAP4430_VC_MPU_VPACK_EN_SHIFT 6
1310#define OMAP4430_VC_MPU_VPACK_EN_MASK (1 << 6)
1311
1312/* Used by PRM_IRQSTATUS_MPU_2 */
1313#define OMAP4430_VC_MPU_VPACK_ST_SHIFT 6
1314#define OMAP4430_VC_MPU_VPACK_ST_MASK (1 << 6)
1315
1316/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1317#define OMAP4430_VC_RAERR_EN_SHIFT 12
1318#define OMAP4430_VC_RAERR_EN_MASK (1 << 12)
1319
1320/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1321#define OMAP4430_VC_RAERR_ST_SHIFT 12
1322#define OMAP4430_VC_RAERR_ST_MASK (1 << 12)
1323
1324/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1325#define OMAP4430_VC_SAERR_EN_SHIFT 11
1326#define OMAP4430_VC_SAERR_EN_MASK (1 << 11)
1327
1328/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1329#define OMAP4430_VC_SAERR_ST_SHIFT 11
1330#define OMAP4430_VC_SAERR_ST_MASK (1 << 11)
1331
1332/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1333#define OMAP4430_VC_TOERR_EN_SHIFT 13
1334#define OMAP4430_VC_TOERR_EN_MASK (1 << 13)
1335
1336/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1337#define OMAP4430_VC_TOERR_ST_SHIFT 13
1338#define OMAP4430_VC_TOERR_ST_MASK (1 << 13)
1339
1340/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1341#define OMAP4430_VDDMAX_SHIFT 24 83#define OMAP4430_VDDMAX_SHIFT 24
1342#define OMAP4430_VDDMAX_MASK (0xff << 24)
1343
1344/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_IVA_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1345#define OMAP4430_VDDMIN_SHIFT 16 84#define OMAP4430_VDDMIN_SHIFT 16
1346#define OMAP4430_VDDMIN_MASK (0xff << 16)
1347
1348/* Used by PRM_VOLTCTRL */
1349#define OMAP4430_VDD_CORE_I2C_DISABLE_SHIFT 12
1350#define OMAP4430_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
1351
1352/* Used by PRM_RSTST */
1353#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8 85#define OMAP4430_VDD_CORE_VOLT_MGR_RST_SHIFT 8
1354#define OMAP4430_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
1355
1356/* Used by PRM_VOLTCTRL */
1357#define OMAP4430_VDD_IVA_I2C_DISABLE_SHIFT 14
1358#define OMAP4430_VDD_IVA_I2C_DISABLE_MASK (1 << 14)
1359
1360/* Used by PRM_VOLTCTRL */
1361#define OMAP4430_VDD_IVA_PRESENCE_SHIFT 9
1362#define OMAP4430_VDD_IVA_PRESENCE_MASK (1 << 9)
1363
1364/* Used by PRM_RSTST */
1365#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7 86#define OMAP4430_VDD_IVA_VOLT_MGR_RST_SHIFT 7
1366#define OMAP4430_VDD_IVA_VOLT_MGR_RST_MASK (1 << 7)
1367
1368/* Used by PRM_VOLTCTRL */
1369#define OMAP4430_VDD_MPU_I2C_DISABLE_SHIFT 13
1370#define OMAP4430_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
1371
1372/* Used by PRM_VOLTCTRL */
1373#define OMAP4430_VDD_MPU_PRESENCE_SHIFT 8
1374#define OMAP4430_VDD_MPU_PRESENCE_MASK (1 << 8)
1375
1376/* Used by PRM_RSTST */
1377#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6 87#define OMAP4430_VDD_MPU_VOLT_MGR_RST_SHIFT 6
1378#define OMAP4430_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1379
1380/* Used by PRM_VC_ERRST */
1381#define OMAP4430_VFSM_RA_ERR_CORE_SHIFT 4
1382#define OMAP4430_VFSM_RA_ERR_CORE_MASK (1 << 4)
1383
1384/* Used by PRM_VC_ERRST */
1385#define OMAP4430_VFSM_RA_ERR_IVA_SHIFT 12
1386#define OMAP4430_VFSM_RA_ERR_IVA_MASK (1 << 12)
1387
1388/* Used by PRM_VC_ERRST */
1389#define OMAP4430_VFSM_RA_ERR_MPU_SHIFT 20
1390#define OMAP4430_VFSM_RA_ERR_MPU_MASK (1 << 20)
1391
1392/* Used by PRM_VC_ERRST */
1393#define OMAP4430_VFSM_SA_ERR_CORE_SHIFT 3
1394#define OMAP4430_VFSM_SA_ERR_CORE_MASK (1 << 3)
1395
1396/* Used by PRM_VC_ERRST */
1397#define OMAP4430_VFSM_SA_ERR_IVA_SHIFT 11
1398#define OMAP4430_VFSM_SA_ERR_IVA_MASK (1 << 11)
1399
1400/* Used by PRM_VC_ERRST */
1401#define OMAP4430_VFSM_SA_ERR_MPU_SHIFT 19
1402#define OMAP4430_VFSM_SA_ERR_MPU_MASK (1 << 19)
1403
1404/* Used by PRM_VC_ERRST */
1405#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1406#define OMAP4430_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1407
1408/* Used by PRM_VC_ERRST */
1409#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_SHIFT 13
1410#define OMAP4430_VFSM_TIMEOUT_ERR_IVA_MASK (1 << 13)
1411
1412/* Used by PRM_VC_ERRST */
1413#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_SHIFT 21
1414#define OMAP4430_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 21)
1415
1416/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1417#define OMAP4430_VOLRA_VDD_CORE_L_SHIFT 0
1418#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0) 88#define OMAP4430_VOLRA_VDD_CORE_L_MASK (0xff << 0)
1419
1420/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1421#define OMAP4430_VOLRA_VDD_IVA_L_SHIFT 8
1422#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8) 89#define OMAP4430_VOLRA_VDD_IVA_L_MASK (0xff << 8)
1423
1424/* Used by PRM_VC_VAL_SMPS_RA_VOL */
1425#define OMAP4430_VOLRA_VDD_MPU_L_SHIFT 16
1426#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16) 90#define OMAP4430_VOLRA_VDD_MPU_L_MASK (0xff << 16)
1427
1428/* Used by PRM_VP_CORE_CONFIG, PRM_VP_IVA_CONFIG, PRM_VP_MPU_CONFIG */
1429#define OMAP4430_VPENABLE_SHIFT 0
1430#define OMAP4430_VPENABLE_MASK (1 << 0) 91#define OMAP4430_VPENABLE_MASK (1 << 0)
1431
1432/* Used by PRM_VP_CORE_STATUS, PRM_VP_IVA_STATUS, PRM_VP_MPU_STATUS */
1433#define OMAP4430_VPINIDLE_SHIFT 0
1434#define OMAP4430_VPINIDLE_MASK (1 << 0)
1435
1436/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_IVA_VOLTAGE, PRM_VP_MPU_VOLTAGE */
1437#define OMAP4430_VPVOLTAGE_SHIFT 0
1438#define OMAP4430_VPVOLTAGE_MASK (0xff << 0) 92#define OMAP4430_VPVOLTAGE_MASK (0xff << 0)
1439
1440/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1441#define OMAP4430_VP_CORE_EQVALUE_EN_SHIFT 20
1442#define OMAP4430_VP_CORE_EQVALUE_EN_MASK (1 << 20)
1443
1444/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1445#define OMAP4430_VP_CORE_EQVALUE_ST_SHIFT 20
1446#define OMAP4430_VP_CORE_EQVALUE_ST_MASK (1 << 20)
1447
1448/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1449#define OMAP4430_VP_CORE_MAXVDD_EN_SHIFT 18
1450#define OMAP4430_VP_CORE_MAXVDD_EN_MASK (1 << 18)
1451
1452/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1453#define OMAP4430_VP_CORE_MAXVDD_ST_SHIFT 18
1454#define OMAP4430_VP_CORE_MAXVDD_ST_MASK (1 << 18)
1455
1456/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1457#define OMAP4430_VP_CORE_MINVDD_EN_SHIFT 17
1458#define OMAP4430_VP_CORE_MINVDD_EN_MASK (1 << 17)
1459
1460/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1461#define OMAP4430_VP_CORE_MINVDD_ST_SHIFT 17
1462#define OMAP4430_VP_CORE_MINVDD_ST_MASK (1 << 17)
1463
1464/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1465#define OMAP4430_VP_CORE_NOSMPSACK_EN_SHIFT 19
1466#define OMAP4430_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
1467
1468/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1469#define OMAP4430_VP_CORE_NOSMPSACK_ST_SHIFT 19
1470#define OMAP4430_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
1471
1472/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1473#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
1474#define OMAP4430_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
1475
1476/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1477#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
1478#define OMAP4430_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
1479
1480/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1481#define OMAP4430_VP_CORE_TRANXDONE_EN_SHIFT 21
1482#define OMAP4430_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
1483
1484/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1485#define OMAP4430_VP_CORE_TRANXDONE_ST_SHIFT 21
1486#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21) 93#define OMAP4430_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
1487
1488/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1489#define OMAP4430_VP_IVA_EQVALUE_EN_SHIFT 28
1490#define OMAP4430_VP_IVA_EQVALUE_EN_MASK (1 << 28)
1491
1492/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1493#define OMAP4430_VP_IVA_EQVALUE_ST_SHIFT 28
1494#define OMAP4430_VP_IVA_EQVALUE_ST_MASK (1 << 28)
1495
1496/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1497#define OMAP4430_VP_IVA_MAXVDD_EN_SHIFT 26
1498#define OMAP4430_VP_IVA_MAXVDD_EN_MASK (1 << 26)
1499
1500/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1501#define OMAP4430_VP_IVA_MAXVDD_ST_SHIFT 26
1502#define OMAP4430_VP_IVA_MAXVDD_ST_MASK (1 << 26)
1503
1504/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1505#define OMAP4430_VP_IVA_MINVDD_EN_SHIFT 25
1506#define OMAP4430_VP_IVA_MINVDD_EN_MASK (1 << 25)
1507
1508/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1509#define OMAP4430_VP_IVA_MINVDD_ST_SHIFT 25
1510#define OMAP4430_VP_IVA_MINVDD_ST_MASK (1 << 25)
1511
1512/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1513#define OMAP4430_VP_IVA_NOSMPSACK_EN_SHIFT 27
1514#define OMAP4430_VP_IVA_NOSMPSACK_EN_MASK (1 << 27)
1515
1516/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1517#define OMAP4430_VP_IVA_NOSMPSACK_ST_SHIFT 27
1518#define OMAP4430_VP_IVA_NOSMPSACK_ST_MASK (1 << 27)
1519
1520/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1521#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_SHIFT 24
1522#define OMAP4430_VP_IVA_OPPCHANGEDONE_EN_MASK (1 << 24)
1523
1524/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1525#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_SHIFT 24
1526#define OMAP4430_VP_IVA_OPPCHANGEDONE_ST_MASK (1 << 24)
1527
1528/* Used by PRM_IRQENABLE_DUCATI, PRM_IRQENABLE_MPU */
1529#define OMAP4430_VP_IVA_TRANXDONE_EN_SHIFT 29
1530#define OMAP4430_VP_IVA_TRANXDONE_EN_MASK (1 << 29)
1531
1532/* Used by PRM_IRQSTATUS_DUCATI, PRM_IRQSTATUS_MPU */
1533#define OMAP4430_VP_IVA_TRANXDONE_ST_SHIFT 29
1534#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29) 94#define OMAP4430_VP_IVA_TRANXDONE_ST_MASK (1 << 29)
1535
1536/* Used by PRM_IRQENABLE_MPU_2 */
1537#define OMAP4430_VP_MPU_EQVALUE_EN_SHIFT 4
1538#define OMAP4430_VP_MPU_EQVALUE_EN_MASK (1 << 4)
1539
1540/* Used by PRM_IRQSTATUS_MPU_2 */
1541#define OMAP4430_VP_MPU_EQVALUE_ST_SHIFT 4
1542#define OMAP4430_VP_MPU_EQVALUE_ST_MASK (1 << 4)
1543
1544/* Used by PRM_IRQENABLE_MPU_2 */
1545#define OMAP4430_VP_MPU_MAXVDD_EN_SHIFT 2
1546#define OMAP4430_VP_MPU_MAXVDD_EN_MASK (1 << 2)
1547
1548/* Used by PRM_IRQSTATUS_MPU_2 */
1549#define OMAP4430_VP_MPU_MAXVDD_ST_SHIFT 2
1550#define OMAP4430_VP_MPU_MAXVDD_ST_MASK (1 << 2)
1551
1552/* Used by PRM_IRQENABLE_MPU_2 */
1553#define OMAP4430_VP_MPU_MINVDD_EN_SHIFT 1
1554#define OMAP4430_VP_MPU_MINVDD_EN_MASK (1 << 1)
1555
1556/* Used by PRM_IRQSTATUS_MPU_2 */
1557#define OMAP4430_VP_MPU_MINVDD_ST_SHIFT 1
1558#define OMAP4430_VP_MPU_MINVDD_ST_MASK (1 << 1)
1559
1560/* Used by PRM_IRQENABLE_MPU_2 */
1561#define OMAP4430_VP_MPU_NOSMPSACK_EN_SHIFT 3
1562#define OMAP4430_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
1563
1564/* Used by PRM_IRQSTATUS_MPU_2 */
1565#define OMAP4430_VP_MPU_NOSMPSACK_ST_SHIFT 3
1566#define OMAP4430_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
1567
1568/* Used by PRM_IRQENABLE_MPU_2 */
1569#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
1570#define OMAP4430_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
1571
1572/* Used by PRM_IRQSTATUS_MPU_2 */
1573#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
1574#define OMAP4430_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
1575
1576/* Used by PRM_IRQENABLE_MPU_2 */
1577#define OMAP4430_VP_MPU_TRANXDONE_EN_SHIFT 5
1578#define OMAP4430_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
1579
1580/* Used by PRM_IRQSTATUS_MPU_2 */
1581#define OMAP4430_VP_MPU_TRANXDONE_ST_SHIFT 5
1582#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5) 95#define OMAP4430_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
1583
1584/* Used by PRM_SRAM_COUNT */
1585#define OMAP4430_VSETUPCNT_VALUE_SHIFT 8
1586#define OMAP4430_VSETUPCNT_VALUE_MASK (0xff << 8)
1587
1588/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_IVA_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1589#define OMAP4430_VSTEPMAX_SHIFT 0 96#define OMAP4430_VSTEPMAX_SHIFT 0
1590#define OMAP4430_VSTEPMAX_MASK (0xff << 0)
1591
1592/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_IVA_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1593#define OMAP4430_VSTEPMIN_SHIFT 0 97#define OMAP4430_VSTEPMIN_SHIFT 0
1594#define OMAP4430_VSTEPMIN_MASK (0xff << 0)
1595
1596/* Used by PRM_MODEM_IF_CTRL */
1597#define OMAP4430_WAKE_MODEM_SHIFT 0
1598#define OMAP4430_WAKE_MODEM_MASK (1 << 0)
1599
1600/* Used by PM_DSS_DSS_WKDEP */
1601#define OMAP4430_WKUPDEP_DISPC_DUCATI_SHIFT 1
1602#define OMAP4430_WKUPDEP_DISPC_DUCATI_MASK (1 << 1)
1603
1604/* Used by PM_DSS_DSS_WKDEP */
1605#define OMAP4430_WKUPDEP_DISPC_MPU_SHIFT 0
1606#define OMAP4430_WKUPDEP_DISPC_MPU_MASK (1 << 0)
1607
1608/* Used by PM_DSS_DSS_WKDEP */
1609#define OMAP4430_WKUPDEP_DISPC_SDMA_SHIFT 3
1610#define OMAP4430_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
1611
1612/* Used by PM_DSS_DSS_WKDEP */
1613#define OMAP4430_WKUPDEP_DISPC_TESLA_SHIFT 2
1614#define OMAP4430_WKUPDEP_DISPC_TESLA_MASK (1 << 2)
1615
1616/* Used by PM_ABE_DMIC_WKDEP */
1617#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
1618#define OMAP4430_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
1619
1620/* Used by PM_ABE_DMIC_WKDEP */
1621#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_SHIFT 6
1622#define OMAP4430_WKUPDEP_DMIC_DMA_TESLA_MASK (1 << 6)
1623
1624/* Used by PM_ABE_DMIC_WKDEP */
1625#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
1626#define OMAP4430_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
1627
1628/* Used by PM_ABE_DMIC_WKDEP */
1629#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_SHIFT 2
1630#define OMAP4430_WKUPDEP_DMIC_IRQ_TESLA_MASK (1 << 2)
1631
1632/* Used by PM_L4PER_DMTIMER10_WKDEP */
1633#define OMAP4430_WKUPDEP_DMTIMER10_MPU_SHIFT 0
1634#define OMAP4430_WKUPDEP_DMTIMER10_MPU_MASK (1 << 0)
1635
1636/* Used by PM_L4PER_DMTIMER11_WKDEP */
1637#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_SHIFT 1
1638#define OMAP4430_WKUPDEP_DMTIMER11_DUCATI_MASK (1 << 1)
1639
1640/* Used by PM_L4PER_DMTIMER11_WKDEP */
1641#define OMAP4430_WKUPDEP_DMTIMER11_MPU_SHIFT 0
1642#define OMAP4430_WKUPDEP_DMTIMER11_MPU_MASK (1 << 0)
1643
1644/* Used by PM_L4PER_DMTIMER2_WKDEP */
1645#define OMAP4430_WKUPDEP_DMTIMER2_MPU_SHIFT 0
1646#define OMAP4430_WKUPDEP_DMTIMER2_MPU_MASK (1 << 0)
1647
1648/* Used by PM_L4PER_DMTIMER3_WKDEP */
1649#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_SHIFT 1
1650#define OMAP4430_WKUPDEP_DMTIMER3_DUCATI_MASK (1 << 1)
1651
1652/* Used by PM_L4PER_DMTIMER3_WKDEP */
1653#define OMAP4430_WKUPDEP_DMTIMER3_MPU_SHIFT 0
1654#define OMAP4430_WKUPDEP_DMTIMER3_MPU_MASK (1 << 0)
1655
1656/* Used by PM_L4PER_DMTIMER4_WKDEP */
1657#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_SHIFT 1
1658#define OMAP4430_WKUPDEP_DMTIMER4_DUCATI_MASK (1 << 1)
1659
1660/* Used by PM_L4PER_DMTIMER4_WKDEP */
1661#define OMAP4430_WKUPDEP_DMTIMER4_MPU_SHIFT 0
1662#define OMAP4430_WKUPDEP_DMTIMER4_MPU_MASK (1 << 0)
1663
1664/* Used by PM_L4PER_DMTIMER9_WKDEP */
1665#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_SHIFT 1
1666#define OMAP4430_WKUPDEP_DMTIMER9_DUCATI_MASK (1 << 1)
1667
1668/* Used by PM_L4PER_DMTIMER9_WKDEP */
1669#define OMAP4430_WKUPDEP_DMTIMER9_MPU_SHIFT 0
1670#define OMAP4430_WKUPDEP_DMTIMER9_MPU_MASK (1 << 0)
1671
1672/* Used by PM_DSS_DSS_WKDEP */
1673#define OMAP4430_WKUPDEP_DSI1_DUCATI_SHIFT 5
1674#define OMAP4430_WKUPDEP_DSI1_DUCATI_MASK (1 << 5)
1675
1676/* Used by PM_DSS_DSS_WKDEP */
1677#define OMAP4430_WKUPDEP_DSI1_MPU_SHIFT 4
1678#define OMAP4430_WKUPDEP_DSI1_MPU_MASK (1 << 4)
1679
1680/* Used by PM_DSS_DSS_WKDEP */
1681#define OMAP4430_WKUPDEP_DSI1_SDMA_SHIFT 7
1682#define OMAP4430_WKUPDEP_DSI1_SDMA_MASK (1 << 7)
1683
1684/* Used by PM_DSS_DSS_WKDEP */
1685#define OMAP4430_WKUPDEP_DSI1_TESLA_SHIFT 6
1686#define OMAP4430_WKUPDEP_DSI1_TESLA_MASK (1 << 6)
1687
1688/* Used by PM_DSS_DSS_WKDEP */
1689#define OMAP4430_WKUPDEP_DSI2_DUCATI_SHIFT 9
1690#define OMAP4430_WKUPDEP_DSI2_DUCATI_MASK (1 << 9)
1691
1692/* Used by PM_DSS_DSS_WKDEP */
1693#define OMAP4430_WKUPDEP_DSI2_MPU_SHIFT 8
1694#define OMAP4430_WKUPDEP_DSI2_MPU_MASK (1 << 8)
1695
1696/* Used by PM_DSS_DSS_WKDEP */
1697#define OMAP4430_WKUPDEP_DSI2_SDMA_SHIFT 11
1698#define OMAP4430_WKUPDEP_DSI2_SDMA_MASK (1 << 11)
1699
1700/* Used by PM_DSS_DSS_WKDEP */
1701#define OMAP4430_WKUPDEP_DSI2_TESLA_SHIFT 10
1702#define OMAP4430_WKUPDEP_DSI2_TESLA_MASK (1 << 10)
1703
1704/* Used by PM_WKUP_GPIO1_WKDEP */
1705#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_SHIFT 1
1706#define OMAP4430_WKUPDEP_GPIO1_IRQ1_DUCATI_MASK (1 << 1)
1707
1708/* Used by PM_WKUP_GPIO1_WKDEP */
1709#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
1710#define OMAP4430_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
1711
1712/* Used by PM_WKUP_GPIO1_WKDEP */
1713#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_SHIFT 6
1714#define OMAP4430_WKUPDEP_GPIO1_IRQ2_TESLA_MASK (1 << 6)
1715
1716/* Used by PM_L4PER_GPIO2_WKDEP */
1717#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_SHIFT 1
1718#define OMAP4430_WKUPDEP_GPIO2_IRQ1_DUCATI_MASK (1 << 1)
1719
1720/* Used by PM_L4PER_GPIO2_WKDEP */
1721#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
1722#define OMAP4430_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
1723
1724/* Used by PM_L4PER_GPIO2_WKDEP */
1725#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_SHIFT 6
1726#define OMAP4430_WKUPDEP_GPIO2_IRQ2_TESLA_MASK (1 << 6)
1727
1728/* Used by PM_L4PER_GPIO3_WKDEP */
1729#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
1730#define OMAP4430_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
1731
1732/* Used by PM_L4PER_GPIO3_WKDEP */
1733#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_SHIFT 6
1734#define OMAP4430_WKUPDEP_GPIO3_IRQ2_TESLA_MASK (1 << 6)
1735
1736/* Used by PM_L4PER_GPIO4_WKDEP */
1737#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
1738#define OMAP4430_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
1739
1740/* Used by PM_L4PER_GPIO4_WKDEP */
1741#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_SHIFT 6
1742#define OMAP4430_WKUPDEP_GPIO4_IRQ2_TESLA_MASK (1 << 6)
1743
1744/* Used by PM_L4PER_GPIO5_WKDEP */
1745#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
1746#define OMAP4430_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
1747
1748/* Used by PM_L4PER_GPIO5_WKDEP */
1749#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_SHIFT 6
1750#define OMAP4430_WKUPDEP_GPIO5_IRQ2_TESLA_MASK (1 << 6)
1751
1752/* Used by PM_L4PER_GPIO6_WKDEP */
1753#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
1754#define OMAP4430_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
1755
1756/* Used by PM_L4PER_GPIO6_WKDEP */
1757#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_SHIFT 6
1758#define OMAP4430_WKUPDEP_GPIO6_IRQ2_TESLA_MASK (1 << 6)
1759
1760/* Used by PM_DSS_DSS_WKDEP */
1761#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
1762#define OMAP4430_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
1763
1764/* Used by PM_DSS_DSS_WKDEP */
1765#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_SHIFT 13
1766#define OMAP4430_WKUPDEP_HDMIIRQ_DUCATI_MASK (1 << 13)
1767
1768/* Used by PM_DSS_DSS_WKDEP */
1769#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
1770#define OMAP4430_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
1771
1772/* Used by PM_DSS_DSS_WKDEP */
1773#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_SHIFT 14
1774#define OMAP4430_WKUPDEP_HDMIIRQ_TESLA_MASK (1 << 14)
1775
1776/* Used by PM_L4PER_HECC1_WKDEP */
1777#define OMAP4430_WKUPDEP_HECC1_MPU_SHIFT 0
1778#define OMAP4430_WKUPDEP_HECC1_MPU_MASK (1 << 0)
1779
1780/* Used by PM_L4PER_HECC2_WKDEP */
1781#define OMAP4430_WKUPDEP_HECC2_MPU_SHIFT 0
1782#define OMAP4430_WKUPDEP_HECC2_MPU_MASK (1 << 0)
1783
1784/* Used by PM_L3INIT_HSI_WKDEP */
1785#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_SHIFT 6
1786#define OMAP4430_WKUPDEP_HSI_DSP_TESLA_MASK (1 << 6)
1787
1788/* Used by PM_L3INIT_HSI_WKDEP */
1789#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_SHIFT 1
1790#define OMAP4430_WKUPDEP_HSI_MCU_DUCATI_MASK (1 << 1)
1791
1792/* Used by PM_L3INIT_HSI_WKDEP */
1793#define OMAP4430_WKUPDEP_HSI_MCU_MPU_SHIFT 0
1794#define OMAP4430_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
1795
1796/* Used by PM_L4PER_I2C1_WKDEP */
1797#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
1798#define OMAP4430_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
1799
1800/* Used by PM_L4PER_I2C1_WKDEP */
1801#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_SHIFT 1
1802#define OMAP4430_WKUPDEP_I2C1_IRQ_DUCATI_MASK (1 << 1)
1803
1804/* Used by PM_L4PER_I2C1_WKDEP */
1805#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
1806#define OMAP4430_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
1807
1808/* Used by PM_L4PER_I2C2_WKDEP */
1809#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
1810#define OMAP4430_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
1811
1812/* Used by PM_L4PER_I2C2_WKDEP */
1813#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_SHIFT 1
1814#define OMAP4430_WKUPDEP_I2C2_IRQ_DUCATI_MASK (1 << 1)
1815
1816/* Used by PM_L4PER_I2C2_WKDEP */
1817#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
1818#define OMAP4430_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
1819
1820/* Used by PM_L4PER_I2C3_WKDEP */
1821#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
1822#define OMAP4430_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
1823
1824/* Used by PM_L4PER_I2C3_WKDEP */
1825#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_SHIFT 1
1826#define OMAP4430_WKUPDEP_I2C3_IRQ_DUCATI_MASK (1 << 1)
1827
1828/* Used by PM_L4PER_I2C3_WKDEP */
1829#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
1830#define OMAP4430_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
1831
1832/* Used by PM_L4PER_I2C4_WKDEP */
1833#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
1834#define OMAP4430_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
1835
1836/* Used by PM_L4PER_I2C4_WKDEP */
1837#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_SHIFT 1
1838#define OMAP4430_WKUPDEP_I2C4_IRQ_DUCATI_MASK (1 << 1)
1839
1840/* Used by PM_L4PER_I2C4_WKDEP */
1841#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
1842#define OMAP4430_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
1843
1844/* Used by PM_L4PER_I2C5_WKDEP */
1845#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_SHIFT 7
1846#define OMAP4430_WKUPDEP_I2C5_DMA_SDMA_MASK (1 << 7)
1847
1848/* Used by PM_L4PER_I2C5_WKDEP */
1849#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
1850#define OMAP4430_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
1851
1852/* Used by PM_WKUP_KEYBOARD_WKDEP */
1853#define OMAP4430_WKUPDEP_KEYBOARD_MPU_SHIFT 0
1854#define OMAP4430_WKUPDEP_KEYBOARD_MPU_MASK (1 << 0)
1855
1856/* Used by PM_ABE_MCASP_WKDEP */
1857#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_SHIFT 7
1858#define OMAP4430_WKUPDEP_MCASP1_DMA_SDMA_MASK (1 << 7)
1859
1860/* Used by PM_ABE_MCASP_WKDEP */
1861#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_SHIFT 6
1862#define OMAP4430_WKUPDEP_MCASP1_DMA_TESLA_MASK (1 << 6)
1863
1864/* Used by PM_ABE_MCASP_WKDEP */
1865#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_SHIFT 0
1866#define OMAP4430_WKUPDEP_MCASP1_IRQ_MPU_MASK (1 << 0)
1867
1868/* Used by PM_ABE_MCASP_WKDEP */
1869#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_SHIFT 2
1870#define OMAP4430_WKUPDEP_MCASP1_IRQ_TESLA_MASK (1 << 2)
1871
1872/* Used by PM_L4PER_MCASP2_WKDEP */
1873#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_SHIFT 7
1874#define OMAP4430_WKUPDEP_MCASP2_DMA_SDMA_MASK (1 << 7)
1875
1876/* Used by PM_L4PER_MCASP2_WKDEP */
1877#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_SHIFT 6
1878#define OMAP4430_WKUPDEP_MCASP2_DMA_TESLA_MASK (1 << 6)
1879
1880/* Used by PM_L4PER_MCASP2_WKDEP */
1881#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_SHIFT 0
1882#define OMAP4430_WKUPDEP_MCASP2_IRQ_MPU_MASK (1 << 0)
1883
1884/* Used by PM_L4PER_MCASP2_WKDEP */
1885#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_SHIFT 2
1886#define OMAP4430_WKUPDEP_MCASP2_IRQ_TESLA_MASK (1 << 2)
1887
1888/* Used by PM_L4PER_MCASP3_WKDEP */
1889#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_SHIFT 7
1890#define OMAP4430_WKUPDEP_MCASP3_DMA_SDMA_MASK (1 << 7)
1891
1892/* Used by PM_L4PER_MCASP3_WKDEP */
1893#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_SHIFT 6
1894#define OMAP4430_WKUPDEP_MCASP3_DMA_TESLA_MASK (1 << 6)
1895
1896/* Used by PM_L4PER_MCASP3_WKDEP */
1897#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_SHIFT 0
1898#define OMAP4430_WKUPDEP_MCASP3_IRQ_MPU_MASK (1 << 0)
1899
1900/* Used by PM_L4PER_MCASP3_WKDEP */
1901#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_SHIFT 2
1902#define OMAP4430_WKUPDEP_MCASP3_IRQ_TESLA_MASK (1 << 2)
1903
1904/* Used by PM_ABE_MCBSP1_WKDEP */
1905#define OMAP4430_WKUPDEP_MCBSP1_MPU_SHIFT 0
1906#define OMAP4430_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
1907
1908/* Used by PM_ABE_MCBSP1_WKDEP */
1909#define OMAP4430_WKUPDEP_MCBSP1_SDMA_SHIFT 3
1910#define OMAP4430_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
1911
1912/* Used by PM_ABE_MCBSP1_WKDEP */
1913#define OMAP4430_WKUPDEP_MCBSP1_TESLA_SHIFT 2
1914#define OMAP4430_WKUPDEP_MCBSP1_TESLA_MASK (1 << 2)
1915
1916/* Used by PM_ABE_MCBSP2_WKDEP */
1917#define OMAP4430_WKUPDEP_MCBSP2_MPU_SHIFT 0
1918#define OMAP4430_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
1919
1920/* Used by PM_ABE_MCBSP2_WKDEP */
1921#define OMAP4430_WKUPDEP_MCBSP2_SDMA_SHIFT 3
1922#define OMAP4430_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
1923
1924/* Used by PM_ABE_MCBSP2_WKDEP */
1925#define OMAP4430_WKUPDEP_MCBSP2_TESLA_SHIFT 2
1926#define OMAP4430_WKUPDEP_MCBSP2_TESLA_MASK (1 << 2)
1927
1928/* Used by PM_ABE_MCBSP3_WKDEP */
1929#define OMAP4430_WKUPDEP_MCBSP3_MPU_SHIFT 0
1930#define OMAP4430_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
1931
1932/* Used by PM_ABE_MCBSP3_WKDEP */
1933#define OMAP4430_WKUPDEP_MCBSP3_SDMA_SHIFT 3
1934#define OMAP4430_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
1935
1936/* Used by PM_ABE_MCBSP3_WKDEP */
1937#define OMAP4430_WKUPDEP_MCBSP3_TESLA_SHIFT 2
1938#define OMAP4430_WKUPDEP_MCBSP3_TESLA_MASK (1 << 2)
1939
1940/* Used by PM_L4PER_MCBSP4_WKDEP */
1941#define OMAP4430_WKUPDEP_MCBSP4_MPU_SHIFT 0
1942#define OMAP4430_WKUPDEP_MCBSP4_MPU_MASK (1 << 0)
1943
1944/* Used by PM_L4PER_MCBSP4_WKDEP */
1945#define OMAP4430_WKUPDEP_MCBSP4_SDMA_SHIFT 3
1946#define OMAP4430_WKUPDEP_MCBSP4_SDMA_MASK (1 << 3)
1947
1948/* Used by PM_L4PER_MCBSP4_WKDEP */
1949#define OMAP4430_WKUPDEP_MCBSP4_TESLA_SHIFT 2
1950#define OMAP4430_WKUPDEP_MCBSP4_TESLA_MASK (1 << 2)
1951
1952/* Used by PM_L4PER_MCSPI1_WKDEP */
1953#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_SHIFT 1
1954#define OMAP4430_WKUPDEP_MCSPI1_DUCATI_MASK (1 << 1)
1955
1956/* Used by PM_L4PER_MCSPI1_WKDEP */
1957#define OMAP4430_WKUPDEP_MCSPI1_MPU_SHIFT 0
1958#define OMAP4430_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
1959
1960/* Used by PM_L4PER_MCSPI1_WKDEP */
1961#define OMAP4430_WKUPDEP_MCSPI1_SDMA_SHIFT 3
1962#define OMAP4430_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
1963
1964/* Used by PM_L4PER_MCSPI1_WKDEP */
1965#define OMAP4430_WKUPDEP_MCSPI1_TESLA_SHIFT 2
1966#define OMAP4430_WKUPDEP_MCSPI1_TESLA_MASK (1 << 2)
1967
1968/* Used by PM_L4PER_MCSPI2_WKDEP */
1969#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_SHIFT 1
1970#define OMAP4430_WKUPDEP_MCSPI2_DUCATI_MASK (1 << 1)
1971
1972/* Used by PM_L4PER_MCSPI2_WKDEP */
1973#define OMAP4430_WKUPDEP_MCSPI2_MPU_SHIFT 0
1974#define OMAP4430_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
1975
1976/* Used by PM_L4PER_MCSPI2_WKDEP */
1977#define OMAP4430_WKUPDEP_MCSPI2_SDMA_SHIFT 3
1978#define OMAP4430_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
1979
1980/* Used by PM_L4PER_MCSPI3_WKDEP */
1981#define OMAP4430_WKUPDEP_MCSPI3_MPU_SHIFT 0
1982#define OMAP4430_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
1983
1984/* Used by PM_L4PER_MCSPI3_WKDEP */
1985#define OMAP4430_WKUPDEP_MCSPI3_SDMA_SHIFT 3
1986#define OMAP4430_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
1987
1988/* Used by PM_L4PER_MCSPI4_WKDEP */
1989#define OMAP4430_WKUPDEP_MCSPI4_MPU_SHIFT 0
1990#define OMAP4430_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
1991
1992/* Used by PM_L4PER_MCSPI4_WKDEP */
1993#define OMAP4430_WKUPDEP_MCSPI4_SDMA_SHIFT 3
1994#define OMAP4430_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
1995
1996/* Used by PM_L3INIT_MMC1_WKDEP */
1997#define OMAP4430_WKUPDEP_MMC1_DUCATI_SHIFT 1
1998#define OMAP4430_WKUPDEP_MMC1_DUCATI_MASK (1 << 1)
1999
2000/* Used by PM_L3INIT_MMC1_WKDEP */
2001#define OMAP4430_WKUPDEP_MMC1_MPU_SHIFT 0
2002#define OMAP4430_WKUPDEP_MMC1_MPU_MASK (1 << 0)
2003
2004/* Used by PM_L3INIT_MMC1_WKDEP */
2005#define OMAP4430_WKUPDEP_MMC1_SDMA_SHIFT 3
2006#define OMAP4430_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
2007
2008/* Used by PM_L3INIT_MMC1_WKDEP */
2009#define OMAP4430_WKUPDEP_MMC1_TESLA_SHIFT 2
2010#define OMAP4430_WKUPDEP_MMC1_TESLA_MASK (1 << 2)
2011
2012/* Used by PM_L3INIT_MMC2_WKDEP */
2013#define OMAP4430_WKUPDEP_MMC2_DUCATI_SHIFT 1
2014#define OMAP4430_WKUPDEP_MMC2_DUCATI_MASK (1 << 1)
2015
2016/* Used by PM_L3INIT_MMC2_WKDEP */
2017#define OMAP4430_WKUPDEP_MMC2_MPU_SHIFT 0
2018#define OMAP4430_WKUPDEP_MMC2_MPU_MASK (1 << 0)
2019
2020/* Used by PM_L3INIT_MMC2_WKDEP */
2021#define OMAP4430_WKUPDEP_MMC2_SDMA_SHIFT 3
2022#define OMAP4430_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
2023
2024/* Used by PM_L3INIT_MMC2_WKDEP */
2025#define OMAP4430_WKUPDEP_MMC2_TESLA_SHIFT 2
2026#define OMAP4430_WKUPDEP_MMC2_TESLA_MASK (1 << 2)
2027
2028/* Used by PM_L3INIT_MMC6_WKDEP */
2029#define OMAP4430_WKUPDEP_MMC6_DUCATI_SHIFT 1
2030#define OMAP4430_WKUPDEP_MMC6_DUCATI_MASK (1 << 1)
2031
2032/* Used by PM_L3INIT_MMC6_WKDEP */
2033#define OMAP4430_WKUPDEP_MMC6_MPU_SHIFT 0
2034#define OMAP4430_WKUPDEP_MMC6_MPU_MASK (1 << 0)
2035
2036/* Used by PM_L3INIT_MMC6_WKDEP */
2037#define OMAP4430_WKUPDEP_MMC6_TESLA_SHIFT 2
2038#define OMAP4430_WKUPDEP_MMC6_TESLA_MASK (1 << 2)
2039
2040/* Used by PM_L4PER_MMCSD3_WKDEP */
2041#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_SHIFT 1
2042#define OMAP4430_WKUPDEP_MMCSD3_DUCATI_MASK (1 << 1)
2043
2044/* Used by PM_L4PER_MMCSD3_WKDEP */
2045#define OMAP4430_WKUPDEP_MMCSD3_MPU_SHIFT 0
2046#define OMAP4430_WKUPDEP_MMCSD3_MPU_MASK (1 << 0)
2047
2048/* Used by PM_L4PER_MMCSD3_WKDEP */
2049#define OMAP4430_WKUPDEP_MMCSD3_SDMA_SHIFT 3
2050#define OMAP4430_WKUPDEP_MMCSD3_SDMA_MASK (1 << 3)
2051
2052/* Used by PM_L4PER_MMCSD4_WKDEP */
2053#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_SHIFT 1
2054#define OMAP4430_WKUPDEP_MMCSD4_DUCATI_MASK (1 << 1)
2055
2056/* Used by PM_L4PER_MMCSD4_WKDEP */
2057#define OMAP4430_WKUPDEP_MMCSD4_MPU_SHIFT 0
2058#define OMAP4430_WKUPDEP_MMCSD4_MPU_MASK (1 << 0)
2059
2060/* Used by PM_L4PER_MMCSD4_WKDEP */
2061#define OMAP4430_WKUPDEP_MMCSD4_SDMA_SHIFT 3
2062#define OMAP4430_WKUPDEP_MMCSD4_SDMA_MASK (1 << 3)
2063
2064/* Used by PM_L4PER_MMCSD5_WKDEP */
2065#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_SHIFT 1
2066#define OMAP4430_WKUPDEP_MMCSD5_DUCATI_MASK (1 << 1)
2067
2068/* Used by PM_L4PER_MMCSD5_WKDEP */
2069#define OMAP4430_WKUPDEP_MMCSD5_MPU_SHIFT 0
2070#define OMAP4430_WKUPDEP_MMCSD5_MPU_MASK (1 << 0)
2071
2072/* Used by PM_L4PER_MMCSD5_WKDEP */
2073#define OMAP4430_WKUPDEP_MMCSD5_SDMA_SHIFT 3
2074#define OMAP4430_WKUPDEP_MMCSD5_SDMA_MASK (1 << 3)
2075
2076/* Used by PM_L3INIT_PCIESS_WKDEP */
2077#define OMAP4430_WKUPDEP_PCIESS_MPU_SHIFT 0
2078#define OMAP4430_WKUPDEP_PCIESS_MPU_MASK (1 << 0)
2079
2080/* Used by PM_L3INIT_PCIESS_WKDEP */
2081#define OMAP4430_WKUPDEP_PCIESS_TESLA_SHIFT 2
2082#define OMAP4430_WKUPDEP_PCIESS_TESLA_MASK (1 << 2)
2083
2084/* Used by PM_ABE_PDM_WKDEP */
2085#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_SHIFT 7
2086#define OMAP4430_WKUPDEP_PDM_DMA_SDMA_MASK (1 << 7)
2087
2088/* Used by PM_ABE_PDM_WKDEP */
2089#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_SHIFT 6
2090#define OMAP4430_WKUPDEP_PDM_DMA_TESLA_MASK (1 << 6)
2091
2092/* Used by PM_ABE_PDM_WKDEP */
2093#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_SHIFT 0
2094#define OMAP4430_WKUPDEP_PDM_IRQ_MPU_MASK (1 << 0)
2095
2096/* Used by PM_ABE_PDM_WKDEP */
2097#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_SHIFT 2
2098#define OMAP4430_WKUPDEP_PDM_IRQ_TESLA_MASK (1 << 2)
2099
2100/* Used by PM_WKUP_RTC_WKDEP */
2101#define OMAP4430_WKUPDEP_RTC_MPU_SHIFT 0
2102#define OMAP4430_WKUPDEP_RTC_MPU_MASK (1 << 0)
2103
2104/* Used by PM_L3INIT_SATA_WKDEP */
2105#define OMAP4430_WKUPDEP_SATA_MPU_SHIFT 0
2106#define OMAP4430_WKUPDEP_SATA_MPU_MASK (1 << 0)
2107
2108/* Used by PM_L3INIT_SATA_WKDEP */
2109#define OMAP4430_WKUPDEP_SATA_TESLA_SHIFT 2
2110#define OMAP4430_WKUPDEP_SATA_TESLA_MASK (1 << 2)
2111
2112/* Used by PM_ABE_SLIMBUS_WKDEP */
2113#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
2114#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
2115
2116/* Used by PM_ABE_SLIMBUS_WKDEP */
2117#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_SHIFT 6
2118#define OMAP4430_WKUPDEP_SLIMBUS1_DMA_TESLA_MASK (1 << 6)
2119
2120/* Used by PM_ABE_SLIMBUS_WKDEP */
2121#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
2122#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
2123
2124/* Used by PM_ABE_SLIMBUS_WKDEP */
2125#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_SHIFT 2
2126#define OMAP4430_WKUPDEP_SLIMBUS1_IRQ_TESLA_MASK (1 << 2)
2127
2128/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2129#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_SHIFT 7
2130#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_SDMA_MASK (1 << 7)
2131
2132/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2133#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_SHIFT 6
2134#define OMAP4430_WKUPDEP_SLIMBUS2_DMA_TESLA_MASK (1 << 6)
2135
2136/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2137#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_SHIFT 0
2138#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_MPU_MASK (1 << 0)
2139
2140/* Used by PM_L4PER_SLIMBUS2_WKDEP */
2141#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_SHIFT 2
2142#define OMAP4430_WKUPDEP_SLIMBUS2_IRQ_TESLA_MASK (1 << 2)
2143
2144/* Used by PM_ALWON_SR_CORE_WKDEP */
2145#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_SHIFT 1
2146#define OMAP4430_WKUPDEP_SR_CORE_DUCATI_MASK (1 << 1)
2147
2148/* Used by PM_ALWON_SR_CORE_WKDEP */
2149#define OMAP4430_WKUPDEP_SR_CORE_MPU_SHIFT 0
2150#define OMAP4430_WKUPDEP_SR_CORE_MPU_MASK (1 << 0)
2151
2152/* Used by PM_ALWON_SR_IVA_WKDEP */
2153#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_SHIFT 1
2154#define OMAP4430_WKUPDEP_SR_IVA_DUCATI_MASK (1 << 1)
2155
2156/* Used by PM_ALWON_SR_IVA_WKDEP */
2157#define OMAP4430_WKUPDEP_SR_IVA_MPU_SHIFT 0
2158#define OMAP4430_WKUPDEP_SR_IVA_MPU_MASK (1 << 0)
2159
2160/* Used by PM_ALWON_SR_MPU_WKDEP */
2161#define OMAP4430_WKUPDEP_SR_MPU_MPU_SHIFT 0
2162#define OMAP4430_WKUPDEP_SR_MPU_MPU_MASK (1 << 0)
2163
2164/* Used by PM_WKUP_TIMER12_WKDEP */
2165#define OMAP4430_WKUPDEP_TIMER12_MPU_SHIFT 0
2166#define OMAP4430_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
2167
2168/* Used by PM_WKUP_TIMER1_WKDEP */
2169#define OMAP4430_WKUPDEP_TIMER1_MPU_SHIFT 0
2170#define OMAP4430_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
2171
2172/* Used by PM_ABE_TIMER5_WKDEP */
2173#define OMAP4430_WKUPDEP_TIMER5_MPU_SHIFT 0
2174#define OMAP4430_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
2175
2176/* Used by PM_ABE_TIMER5_WKDEP */
2177#define OMAP4430_WKUPDEP_TIMER5_TESLA_SHIFT 2
2178#define OMAP4430_WKUPDEP_TIMER5_TESLA_MASK (1 << 2)
2179
2180/* Used by PM_ABE_TIMER6_WKDEP */
2181#define OMAP4430_WKUPDEP_TIMER6_MPU_SHIFT 0
2182#define OMAP4430_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
2183
2184/* Used by PM_ABE_TIMER6_WKDEP */
2185#define OMAP4430_WKUPDEP_TIMER6_TESLA_SHIFT 2
2186#define OMAP4430_WKUPDEP_TIMER6_TESLA_MASK (1 << 2)
2187
2188/* Used by PM_ABE_TIMER7_WKDEP */
2189#define OMAP4430_WKUPDEP_TIMER7_MPU_SHIFT 0
2190#define OMAP4430_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
2191
2192/* Used by PM_ABE_TIMER7_WKDEP */
2193#define OMAP4430_WKUPDEP_TIMER7_TESLA_SHIFT 2
2194#define OMAP4430_WKUPDEP_TIMER7_TESLA_MASK (1 << 2)
2195
2196/* Used by PM_ABE_TIMER8_WKDEP */
2197#define OMAP4430_WKUPDEP_TIMER8_MPU_SHIFT 0
2198#define OMAP4430_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
2199
2200/* Used by PM_ABE_TIMER8_WKDEP */
2201#define OMAP4430_WKUPDEP_TIMER8_TESLA_SHIFT 2
2202#define OMAP4430_WKUPDEP_TIMER8_TESLA_MASK (1 << 2)
2203
2204/* Used by PM_L4PER_UART1_WKDEP */
2205#define OMAP4430_WKUPDEP_UART1_MPU_SHIFT 0
2206#define OMAP4430_WKUPDEP_UART1_MPU_MASK (1 << 0)
2207
2208/* Used by PM_L4PER_UART1_WKDEP */
2209#define OMAP4430_WKUPDEP_UART1_SDMA_SHIFT 3
2210#define OMAP4430_WKUPDEP_UART1_SDMA_MASK (1 << 3)
2211
2212/* Used by PM_L4PER_UART2_WKDEP */
2213#define OMAP4430_WKUPDEP_UART2_MPU_SHIFT 0
2214#define OMAP4430_WKUPDEP_UART2_MPU_MASK (1 << 0)
2215
2216/* Used by PM_L4PER_UART2_WKDEP */
2217#define OMAP4430_WKUPDEP_UART2_SDMA_SHIFT 3
2218#define OMAP4430_WKUPDEP_UART2_SDMA_MASK (1 << 3)
2219
2220/* Used by PM_L4PER_UART3_WKDEP */
2221#define OMAP4430_WKUPDEP_UART3_DUCATI_SHIFT 1
2222#define OMAP4430_WKUPDEP_UART3_DUCATI_MASK (1 << 1)
2223
2224/* Used by PM_L4PER_UART3_WKDEP */
2225#define OMAP4430_WKUPDEP_UART3_MPU_SHIFT 0
2226#define OMAP4430_WKUPDEP_UART3_MPU_MASK (1 << 0)
2227
2228/* Used by PM_L4PER_UART3_WKDEP */
2229#define OMAP4430_WKUPDEP_UART3_SDMA_SHIFT 3
2230#define OMAP4430_WKUPDEP_UART3_SDMA_MASK (1 << 3)
2231
2232/* Used by PM_L4PER_UART3_WKDEP */
2233#define OMAP4430_WKUPDEP_UART3_TESLA_SHIFT 2
2234#define OMAP4430_WKUPDEP_UART3_TESLA_MASK (1 << 2)
2235
2236/* Used by PM_L4PER_UART4_WKDEP */
2237#define OMAP4430_WKUPDEP_UART4_MPU_SHIFT 0
2238#define OMAP4430_WKUPDEP_UART4_MPU_MASK (1 << 0)
2239
2240/* Used by PM_L4PER_UART4_WKDEP */
2241#define OMAP4430_WKUPDEP_UART4_SDMA_SHIFT 3
2242#define OMAP4430_WKUPDEP_UART4_SDMA_MASK (1 << 3)
2243
2244/* Used by PM_L3INIT_UNIPRO1_WKDEP */
2245#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_SHIFT 1
2246#define OMAP4430_WKUPDEP_UNIPRO1_DUCATI_MASK (1 << 1)
2247
2248/* Used by PM_L3INIT_UNIPRO1_WKDEP */
2249#define OMAP4430_WKUPDEP_UNIPRO1_MPU_SHIFT 0
2250#define OMAP4430_WKUPDEP_UNIPRO1_MPU_MASK (1 << 0)
2251
2252/* Used by PM_L3INIT_USB_HOST_WKDEP */
2253#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_SHIFT 1
2254#define OMAP4430_WKUPDEP_USB_HOST_DUCATI_MASK (1 << 1)
2255
2256/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
2257#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_SHIFT 1
2258#define OMAP4430_WKUPDEP_USB_HOST_FS_DUCATI_MASK (1 << 1)
2259
2260/* Used by PM_L3INIT_USB_HOST_FS_WKDEP */
2261#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_SHIFT 0
2262#define OMAP4430_WKUPDEP_USB_HOST_FS_MPU_MASK (1 << 0)
2263
2264/* Used by PM_L3INIT_USB_HOST_WKDEP */
2265#define OMAP4430_WKUPDEP_USB_HOST_MPU_SHIFT 0
2266#define OMAP4430_WKUPDEP_USB_HOST_MPU_MASK (1 << 0)
2267
2268/* Used by PM_L3INIT_USB_OTG_WKDEP */
2269#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_SHIFT 1
2270#define OMAP4430_WKUPDEP_USB_OTG_DUCATI_MASK (1 << 1)
2271
2272/* Used by PM_L3INIT_USB_OTG_WKDEP */
2273#define OMAP4430_WKUPDEP_USB_OTG_MPU_SHIFT 0
2274#define OMAP4430_WKUPDEP_USB_OTG_MPU_MASK (1 << 0)
2275
2276/* Used by PM_L3INIT_USB_TLL_WKDEP */
2277#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_SHIFT 1
2278#define OMAP4430_WKUPDEP_USB_TLL_DUCATI_MASK (1 << 1)
2279
2280/* Used by PM_L3INIT_USB_TLL_WKDEP */
2281#define OMAP4430_WKUPDEP_USB_TLL_MPU_SHIFT 0
2282#define OMAP4430_WKUPDEP_USB_TLL_MPU_MASK (1 << 0)
2283
2284/* Used by PM_WKUP_USIM_WKDEP */
2285#define OMAP4430_WKUPDEP_USIM_MPU_SHIFT 0
2286#define OMAP4430_WKUPDEP_USIM_MPU_MASK (1 << 0)
2287
2288/* Used by PM_WKUP_USIM_WKDEP */
2289#define OMAP4430_WKUPDEP_USIM_SDMA_SHIFT 3
2290#define OMAP4430_WKUPDEP_USIM_SDMA_MASK (1 << 3)
2291
2292/* Used by PM_WKUP_WDT2_WKDEP */
2293#define OMAP4430_WKUPDEP_WDT2_DUCATI_SHIFT 1
2294#define OMAP4430_WKUPDEP_WDT2_DUCATI_MASK (1 << 1)
2295
2296/* Used by PM_WKUP_WDT2_WKDEP */
2297#define OMAP4430_WKUPDEP_WDT2_MPU_SHIFT 0
2298#define OMAP4430_WKUPDEP_WDT2_MPU_MASK (1 << 0)
2299
2300/* Used by PM_ABE_WDT3_WKDEP */
2301#define OMAP4430_WKUPDEP_WDT3_MPU_SHIFT 0
2302#define OMAP4430_WKUPDEP_WDT3_MPU_MASK (1 << 0)
2303
2304/* Used by PM_L3INIT_HSI_WKDEP */
2305#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_SHIFT 8
2306#define OMAP4430_WKUPDEP_WGM_HSI_WAKE_MPU_MASK (1 << 8)
2307
2308/* Used by PM_L3INIT_XHPI_WKDEP */
2309#define OMAP4430_WKUPDEP_XHPI_DUCATI_SHIFT 1
2310#define OMAP4430_WKUPDEP_XHPI_DUCATI_MASK (1 << 1)
2311
2312/* Used by PRM_IO_PMCTRL */
2313#define OMAP4430_WUCLK_CTRL_SHIFT 8
2314#define OMAP4430_WUCLK_CTRL_MASK (1 << 8) 98#define OMAP4430_WUCLK_CTRL_MASK (1 << 8)
2315
2316/* Used by PRM_IO_PMCTRL */
2317#define OMAP4430_WUCLK_STATUS_SHIFT 9 99#define OMAP4430_WUCLK_STATUS_SHIFT 9
2318#define OMAP4430_WUCLK_STATUS_MASK (1 << 9) 100#define OMAP4430_WUCLK_STATUS_MASK (1 << 9)
2319
2320/* Used by REVISION_PRM */
2321#define OMAP4430_X_MAJOR_SHIFT 8
2322#define OMAP4430_X_MAJOR_MASK (0x7 << 8)
2323
2324/* Used by REVISION_PRM */
2325#define OMAP4430_Y_MINOR_SHIFT 0
2326#define OMAP4430_Y_MINOR_MASK (0x3f << 0)
2327#endif 101#endif
diff --git a/arch/arm/mach-omap2/prm-regbits-54xx.h b/arch/arm/mach-omap2/prm-regbits-54xx.h
deleted file mode 100644
index be31b21aa9c6..000000000000
--- a/arch/arm/mach-omap2/prm-regbits-54xx.h
+++ /dev/null
@@ -1,2701 +0,0 @@
1/*
2 * OMAP54xx Power Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley (paul@pwsan.com)
7 * Rajendra Nayak (rnayak@ti.com)
8 * Benoit Cousson (b-cousson@ti.com)
9 *
10 * This file is automatically generated from the OMAP hardware databases.
11 * We respectfully ask that any modifications to this file be coordinated
12 * with the public linux-omap@vger.kernel.org mailing list and the
13 * authors above to ensure that the autogeneration scripts are kept
14 * up-to-date with the file contents.
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20
21#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
22#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_54XX_H
23
24/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
25#define OMAP54XX_ABBOFF_ACT_SHIFT 1
26#define OMAP54XX_ABBOFF_ACT_WIDTH 0x1
27#define OMAP54XX_ABBOFF_ACT_MASK (1 << 1)
28
29/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
30#define OMAP54XX_ABBOFF_SLEEP_SHIFT 2
31#define OMAP54XX_ABBOFF_SLEEP_WIDTH 0x1
32#define OMAP54XX_ABBOFF_SLEEP_MASK (1 << 2)
33
34/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
35#define OMAP54XX_ABB_MM_DONE_EN_SHIFT 31
36#define OMAP54XX_ABB_MM_DONE_EN_WIDTH 0x1
37#define OMAP54XX_ABB_MM_DONE_EN_MASK (1 << 31)
38
39/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
40#define OMAP54XX_ABB_MM_DONE_ST_SHIFT 31
41#define OMAP54XX_ABB_MM_DONE_ST_WIDTH 0x1
42#define OMAP54XX_ABB_MM_DONE_ST_MASK (1 << 31)
43
44/* Used by PRM_IRQENABLE_MPU_2 */
45#define OMAP54XX_ABB_MPU_DONE_EN_SHIFT 7
46#define OMAP54XX_ABB_MPU_DONE_EN_WIDTH 0x1
47#define OMAP54XX_ABB_MPU_DONE_EN_MASK (1 << 7)
48
49/* Used by PRM_IRQSTATUS_MPU_2 */
50#define OMAP54XX_ABB_MPU_DONE_ST_SHIFT 7
51#define OMAP54XX_ABB_MPU_DONE_ST_WIDTH 0x1
52#define OMAP54XX_ABB_MPU_DONE_ST_MASK (1 << 7)
53
54/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
55#define OMAP54XX_ACTIVE_FBB_SEL_SHIFT 2
56#define OMAP54XX_ACTIVE_FBB_SEL_WIDTH 0x1
57#define OMAP54XX_ACTIVE_FBB_SEL_MASK (1 << 2)
58
59/* Used by PM_ABE_PWRSTCTRL */
60#define OMAP54XX_AESSMEM_ONSTATE_SHIFT 16
61#define OMAP54XX_AESSMEM_ONSTATE_WIDTH 0x2
62#define OMAP54XX_AESSMEM_ONSTATE_MASK (0x3 << 16)
63
64/* Used by PM_ABE_PWRSTCTRL */
65#define OMAP54XX_AESSMEM_RETSTATE_SHIFT 8
66#define OMAP54XX_AESSMEM_RETSTATE_WIDTH 0x1
67#define OMAP54XX_AESSMEM_RETSTATE_MASK (1 << 8)
68
69/* Used by PM_ABE_PWRSTST */
70#define OMAP54XX_AESSMEM_STATEST_SHIFT 4
71#define OMAP54XX_AESSMEM_STATEST_WIDTH 0x2
72#define OMAP54XX_AESSMEM_STATEST_MASK (0x3 << 4)
73
74/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
75#define OMAP54XX_AIPOFF_SHIFT 8
76#define OMAP54XX_AIPOFF_WIDTH 0x1
77#define OMAP54XX_AIPOFF_MASK (1 << 8)
78
79/* Used by PRM_VOLTCTRL */
80#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_SHIFT 0
81#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_WIDTH 0x2
82#define OMAP54XX_AUTO_CTRL_VDD_CORE_L_MASK (0x3 << 0)
83
84/* Used by PRM_VOLTCTRL */
85#define OMAP54XX_AUTO_CTRL_VDD_MM_L_SHIFT 4
86#define OMAP54XX_AUTO_CTRL_VDD_MM_L_WIDTH 0x2
87#define OMAP54XX_AUTO_CTRL_VDD_MM_L_MASK (0x3 << 4)
88
89/* Used by PRM_VOLTCTRL */
90#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_SHIFT 2
91#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_WIDTH 0x2
92#define OMAP54XX_AUTO_CTRL_VDD_MPU_L_MASK (0x3 << 2)
93
94/* Used by PRM_VC_BYPASS_ERRST */
95#define OMAP54XX_BYPS_RA_ERR_SHIFT 1
96#define OMAP54XX_BYPS_RA_ERR_WIDTH 0x1
97#define OMAP54XX_BYPS_RA_ERR_MASK (1 << 1)
98
99/* Used by PRM_VC_BYPASS_ERRST */
100#define OMAP54XX_BYPS_SA_ERR_SHIFT 0
101#define OMAP54XX_BYPS_SA_ERR_WIDTH 0x1
102#define OMAP54XX_BYPS_SA_ERR_MASK (1 << 0)
103
104/* Used by PRM_VC_BYPASS_ERRST */
105#define OMAP54XX_BYPS_TIMEOUT_ERR_SHIFT 2
106#define OMAP54XX_BYPS_TIMEOUT_ERR_WIDTH 0x1
107#define OMAP54XX_BYPS_TIMEOUT_ERR_MASK (1 << 2)
108
109/* Used by PRM_RSTST */
110#define OMAP54XX_C2C_RST_SHIFT 10
111#define OMAP54XX_C2C_RST_WIDTH 0x1
112#define OMAP54XX_C2C_RST_MASK (1 << 10)
113
114/* Used by PM_CAM_PWRSTCTRL */
115#define OMAP54XX_CAM_MEM_ONSTATE_SHIFT 16
116#define OMAP54XX_CAM_MEM_ONSTATE_WIDTH 0x2
117#define OMAP54XX_CAM_MEM_ONSTATE_MASK (0x3 << 16)
118
119/* Used by PM_CAM_PWRSTST */
120#define OMAP54XX_CAM_MEM_STATEST_SHIFT 4
121#define OMAP54XX_CAM_MEM_STATEST_WIDTH 0x2
122#define OMAP54XX_CAM_MEM_STATEST_MASK (0x3 << 4)
123
124/* Used by PRM_CLKREQCTRL */
125#define OMAP54XX_CLKREQ_COND_SHIFT 0
126#define OMAP54XX_CLKREQ_COND_WIDTH 0x3
127#define OMAP54XX_CLKREQ_COND_MASK (0x7 << 0)
128
129/* Used by PRM_VC_SMPS_CORE_CONFIG */
130#define OMAP54XX_CMDRA_VDD_CORE_L_SHIFT 16
131#define OMAP54XX_CMDRA_VDD_CORE_L_WIDTH 0x8
132#define OMAP54XX_CMDRA_VDD_CORE_L_MASK (0xff << 16)
133
134/* Used by PRM_VC_SMPS_MM_CONFIG */
135#define OMAP54XX_CMDRA_VDD_MM_L_SHIFT 16
136#define OMAP54XX_CMDRA_VDD_MM_L_WIDTH 0x8
137#define OMAP54XX_CMDRA_VDD_MM_L_MASK (0xff << 16)
138
139/* Used by PRM_VC_SMPS_MPU_CONFIG */
140#define OMAP54XX_CMDRA_VDD_MPU_L_SHIFT 16
141#define OMAP54XX_CMDRA_VDD_MPU_L_WIDTH 0x8
142#define OMAP54XX_CMDRA_VDD_MPU_L_MASK (0xff << 16)
143
144/* Used by PRM_VC_SMPS_CORE_CONFIG */
145#define OMAP54XX_CMD_VDD_CORE_L_SHIFT 28
146#define OMAP54XX_CMD_VDD_CORE_L_WIDTH 0x1
147#define OMAP54XX_CMD_VDD_CORE_L_MASK (1 << 28)
148
149/* Used by PRM_VC_SMPS_MM_CONFIG */
150#define OMAP54XX_CMD_VDD_MM_L_SHIFT 28
151#define OMAP54XX_CMD_VDD_MM_L_WIDTH 0x1
152#define OMAP54XX_CMD_VDD_MM_L_MASK (1 << 28)
153
154/* Used by PRM_VC_SMPS_MPU_CONFIG */
155#define OMAP54XX_CMD_VDD_MPU_L_SHIFT 28
156#define OMAP54XX_CMD_VDD_MPU_L_WIDTH 0x1
157#define OMAP54XX_CMD_VDD_MPU_L_MASK (1 << 28)
158
159/* Used by PM_CORE_PWRSTCTRL */
160#define OMAP54XX_CORE_OCMRAM_ONSTATE_SHIFT 18
161#define OMAP54XX_CORE_OCMRAM_ONSTATE_WIDTH 0x2
162#define OMAP54XX_CORE_OCMRAM_ONSTATE_MASK (0x3 << 18)
163
164/* Used by PM_CORE_PWRSTCTRL */
165#define OMAP54XX_CORE_OCMRAM_RETSTATE_SHIFT 9
166#define OMAP54XX_CORE_OCMRAM_RETSTATE_WIDTH 0x1
167#define OMAP54XX_CORE_OCMRAM_RETSTATE_MASK (1 << 9)
168
169/* Used by PM_CORE_PWRSTST */
170#define OMAP54XX_CORE_OCMRAM_STATEST_SHIFT 6
171#define OMAP54XX_CORE_OCMRAM_STATEST_WIDTH 0x2
172#define OMAP54XX_CORE_OCMRAM_STATEST_MASK (0x3 << 6)
173
174/* Used by PM_CORE_PWRSTCTRL */
175#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_SHIFT 16
176#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_WIDTH 0x2
177#define OMAP54XX_CORE_OTHER_BANK_ONSTATE_MASK (0x3 << 16)
178
179/* Used by PM_CORE_PWRSTCTRL */
180#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_SHIFT 8
181#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_WIDTH 0x1
182#define OMAP54XX_CORE_OTHER_BANK_RETSTATE_MASK (1 << 8)
183
184/* Used by PM_CORE_PWRSTST */
185#define OMAP54XX_CORE_OTHER_BANK_STATEST_SHIFT 4
186#define OMAP54XX_CORE_OTHER_BANK_STATEST_WIDTH 0x2
187#define OMAP54XX_CORE_OTHER_BANK_STATEST_MASK (0x3 << 4)
188
189/* Used by REVISION_PRM */
190#define OMAP54XX_CUSTOM_SHIFT 6
191#define OMAP54XX_CUSTOM_WIDTH 0x2
192#define OMAP54XX_CUSTOM_MASK (0x3 << 6)
193
194/* Used by PRM_VC_VAL_BYPASS */
195#define OMAP54XX_DATA_SHIFT 16
196#define OMAP54XX_DATA_WIDTH 0x8
197#define OMAP54XX_DATA_MASK (0xff << 16)
198
199/* Used by PRM_DEBUG_CORE_RET_TRANS */
200#define OMAP54XX_PRM_DEBUG_OUT_SHIFT 0
201#define OMAP54XX_PRM_DEBUG_OUT_WIDTH 0x1c
202#define OMAP54XX_PRM_DEBUG_OUT_MASK (0xfffffff << 0)
203
204/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MM_RET_TRANS */
205#define OMAP54XX_DEBUG_OUT_0_9_SHIFT 0
206#define OMAP54XX_DEBUG_OUT_0_9_WIDTH 0xa
207#define OMAP54XX_DEBUG_OUT_0_9_MASK (0x3ff << 0)
208
209/* Renamed from DEBUG_OUT Used by PRM_DEBUG_MPU_RET_TRANS */
210#define OMAP54XX_DEBUG_OUT_0_6_SHIFT 0
211#define OMAP54XX_DEBUG_OUT_0_6_WIDTH 0x7
212#define OMAP54XX_DEBUG_OUT_0_6_MASK (0x7f << 0)
213
214/* Renamed from DEBUG_OUT Used by PRM_DEBUG_OFF_TRANS */
215#define OMAP54XX_DEBUG_OUT_0_31_SHIFT 0
216#define OMAP54XX_DEBUG_OUT_0_31_WIDTH 0x20
217#define OMAP54XX_DEBUG_OUT_0_31_MASK (0xffffffff << 0)
218
219/* Renamed from DEBUG_OUT Used by PRM_DEBUG_WKUPAON_FD_TRANS */
220#define OMAP54XX_DEBUG_OUT_0_11_SHIFT 0
221#define OMAP54XX_DEBUG_OUT_0_11_WIDTH 0xc
222#define OMAP54XX_DEBUG_OUT_0_11_MASK (0xfff << 0)
223
224/* Used by PRM_DEVICE_OFF_CTRL */
225#define OMAP54XX_DEVICE_OFF_ENABLE_SHIFT 0
226#define OMAP54XX_DEVICE_OFF_ENABLE_WIDTH 0x1
227#define OMAP54XX_DEVICE_OFF_ENABLE_MASK (1 << 0)
228
229/* Used by PRM_VC_CFG_I2C_MODE */
230#define OMAP54XX_DFILTEREN_SHIFT 6
231#define OMAP54XX_DFILTEREN_WIDTH 0x1
232#define OMAP54XX_DFILTEREN_MASK (1 << 6)
233
234/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
235#define OMAP54XX_DPLL_ABE_RECAL_EN_SHIFT 4
236#define OMAP54XX_DPLL_ABE_RECAL_EN_WIDTH 0x1
237#define OMAP54XX_DPLL_ABE_RECAL_EN_MASK (1 << 4)
238
239/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
240#define OMAP54XX_DPLL_ABE_RECAL_ST_SHIFT 4
241#define OMAP54XX_DPLL_ABE_RECAL_ST_WIDTH 0x1
242#define OMAP54XX_DPLL_ABE_RECAL_ST_MASK (1 << 4)
243
244/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
245#define OMAP54XX_DPLL_CORE_RECAL_EN_SHIFT 0
246#define OMAP54XX_DPLL_CORE_RECAL_EN_WIDTH 0x1
247#define OMAP54XX_DPLL_CORE_RECAL_EN_MASK (1 << 0)
248
249/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
250#define OMAP54XX_DPLL_CORE_RECAL_ST_SHIFT 0
251#define OMAP54XX_DPLL_CORE_RECAL_ST_WIDTH 0x1
252#define OMAP54XX_DPLL_CORE_RECAL_ST_MASK (1 << 0)
253
254/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
255#define OMAP54XX_DPLL_IVA_RECAL_EN_SHIFT 2
256#define OMAP54XX_DPLL_IVA_RECAL_EN_WIDTH 0x1
257#define OMAP54XX_DPLL_IVA_RECAL_EN_MASK (1 << 2)
258
259/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
260#define OMAP54XX_DPLL_IVA_RECAL_ST_SHIFT 2
261#define OMAP54XX_DPLL_IVA_RECAL_ST_WIDTH 0x1
262#define OMAP54XX_DPLL_IVA_RECAL_ST_MASK (1 << 2)
263
264/* Used by PRM_IRQENABLE_MPU */
265#define OMAP54XX_DPLL_MPU_RECAL_EN_SHIFT 1
266#define OMAP54XX_DPLL_MPU_RECAL_EN_WIDTH 0x1
267#define OMAP54XX_DPLL_MPU_RECAL_EN_MASK (1 << 1)
268
269/* Used by PRM_IRQSTATUS_MPU */
270#define OMAP54XX_DPLL_MPU_RECAL_ST_SHIFT 1
271#define OMAP54XX_DPLL_MPU_RECAL_ST_WIDTH 0x1
272#define OMAP54XX_DPLL_MPU_RECAL_ST_MASK (1 << 1)
273
274/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
275#define OMAP54XX_DPLL_PER_RECAL_EN_SHIFT 3
276#define OMAP54XX_DPLL_PER_RECAL_EN_WIDTH 0x1
277#define OMAP54XX_DPLL_PER_RECAL_EN_MASK (1 << 3)
278
279/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
280#define OMAP54XX_DPLL_PER_RECAL_ST_SHIFT 3
281#define OMAP54XX_DPLL_PER_RECAL_ST_WIDTH 0x1
282#define OMAP54XX_DPLL_PER_RECAL_ST_MASK (1 << 3)
283
284/* Used by PM_DSP_PWRSTCTRL */
285#define OMAP54XX_DSP_EDMA_ONSTATE_SHIFT 20
286#define OMAP54XX_DSP_EDMA_ONSTATE_WIDTH 0x2
287#define OMAP54XX_DSP_EDMA_ONSTATE_MASK (0x3 << 20)
288
289/* Used by PM_DSP_PWRSTCTRL */
290#define OMAP54XX_DSP_EDMA_RETSTATE_SHIFT 10
291#define OMAP54XX_DSP_EDMA_RETSTATE_WIDTH 0x1
292#define OMAP54XX_DSP_EDMA_RETSTATE_MASK (1 << 10)
293
294/* Used by PM_DSP_PWRSTST */
295#define OMAP54XX_DSP_EDMA_STATEST_SHIFT 8
296#define OMAP54XX_DSP_EDMA_STATEST_WIDTH 0x2
297#define OMAP54XX_DSP_EDMA_STATEST_MASK (0x3 << 8)
298
299/* Used by PM_DSP_PWRSTCTRL */
300#define OMAP54XX_DSP_L1_ONSTATE_SHIFT 16
301#define OMAP54XX_DSP_L1_ONSTATE_WIDTH 0x2
302#define OMAP54XX_DSP_L1_ONSTATE_MASK (0x3 << 16)
303
304/* Used by PM_DSP_PWRSTCTRL */
305#define OMAP54XX_DSP_L1_RETSTATE_SHIFT 8
306#define OMAP54XX_DSP_L1_RETSTATE_WIDTH 0x1
307#define OMAP54XX_DSP_L1_RETSTATE_MASK (1 << 8)
308
309/* Used by PM_DSP_PWRSTST */
310#define OMAP54XX_DSP_L1_STATEST_SHIFT 4
311#define OMAP54XX_DSP_L1_STATEST_WIDTH 0x2
312#define OMAP54XX_DSP_L1_STATEST_MASK (0x3 << 4)
313
314/* Used by PM_DSP_PWRSTCTRL */
315#define OMAP54XX_DSP_L2_ONSTATE_SHIFT 18
316#define OMAP54XX_DSP_L2_ONSTATE_WIDTH 0x2
317#define OMAP54XX_DSP_L2_ONSTATE_MASK (0x3 << 18)
318
319/* Used by PM_DSP_PWRSTCTRL */
320#define OMAP54XX_DSP_L2_RETSTATE_SHIFT 9
321#define OMAP54XX_DSP_L2_RETSTATE_WIDTH 0x1
322#define OMAP54XX_DSP_L2_RETSTATE_MASK (1 << 9)
323
324/* Used by PM_DSP_PWRSTST */
325#define OMAP54XX_DSP_L2_STATEST_SHIFT 6
326#define OMAP54XX_DSP_L2_STATEST_WIDTH 0x2
327#define OMAP54XX_DSP_L2_STATEST_MASK (0x3 << 6)
328
329/* Used by PM_DSS_PWRSTCTRL */
330#define OMAP54XX_DSS_MEM_ONSTATE_SHIFT 16
331#define OMAP54XX_DSS_MEM_ONSTATE_WIDTH 0x2
332#define OMAP54XX_DSS_MEM_ONSTATE_MASK (0x3 << 16)
333
334/* Used by PM_DSS_PWRSTCTRL */
335#define OMAP54XX_DSS_MEM_RETSTATE_SHIFT 8
336#define OMAP54XX_DSS_MEM_RETSTATE_WIDTH 0x1
337#define OMAP54XX_DSS_MEM_RETSTATE_MASK (1 << 8)
338
339/* Used by PM_DSS_PWRSTST */
340#define OMAP54XX_DSS_MEM_STATEST_SHIFT 4
341#define OMAP54XX_DSS_MEM_STATEST_WIDTH 0x2
342#define OMAP54XX_DSS_MEM_STATEST_MASK (0x3 << 4)
343
344/* Used by PRM_DEVICE_OFF_CTRL */
345#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_SHIFT 8
346#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_WIDTH 0x1
347#define OMAP54XX_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
348
349/* Used by PRM_DEVICE_OFF_CTRL */
350#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_SHIFT 9
351#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_WIDTH 0x1
352#define OMAP54XX_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
353
354/* Used by PM_EMU_PWRSTCTRL */
355#define OMAP54XX_EMU_BANK_ONSTATE_SHIFT 16
356#define OMAP54XX_EMU_BANK_ONSTATE_WIDTH 0x2
357#define OMAP54XX_EMU_BANK_ONSTATE_MASK (0x3 << 16)
358
359/* Used by PM_EMU_PWRSTST */
360#define OMAP54XX_EMU_BANK_STATEST_SHIFT 4
361#define OMAP54XX_EMU_BANK_STATEST_WIDTH 0x2
362#define OMAP54XX_EMU_BANK_STATEST_MASK (0x3 << 4)
363
364/*
365 * Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP,
366 * PRM_SRAM_WKUP_SETUP
367 */
368#define OMAP54XX_ENABLE_RTA_SHIFT 0
369#define OMAP54XX_ENABLE_RTA_WIDTH 0x1
370#define OMAP54XX_ENABLE_RTA_MASK (1 << 0)
371
372/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
373#define OMAP54XX_ENFUNC1_SHIFT 3
374#define OMAP54XX_ENFUNC1_WIDTH 0x1
375#define OMAP54XX_ENFUNC1_MASK (1 << 3)
376
377/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
378#define OMAP54XX_ENFUNC2_SHIFT 4
379#define OMAP54XX_ENFUNC2_WIDTH 0x1
380#define OMAP54XX_ENFUNC2_MASK (1 << 4)
381
382/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
383#define OMAP54XX_ENFUNC3_SHIFT 5
384#define OMAP54XX_ENFUNC3_WIDTH 0x1
385#define OMAP54XX_ENFUNC3_MASK (1 << 5)
386
387/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
388#define OMAP54XX_ENFUNC4_SHIFT 6
389#define OMAP54XX_ENFUNC4_WIDTH 0x1
390#define OMAP54XX_ENFUNC4_MASK (1 << 6)
391
392/* Used by PRM_SLDO_CORE_SETUP, PRM_SLDO_MM_SETUP, PRM_SLDO_MPU_SETUP */
393#define OMAP54XX_ENFUNC5_SHIFT 7
394#define OMAP54XX_ENFUNC5_WIDTH 0x1
395#define OMAP54XX_ENFUNC5_MASK (1 << 7)
396
397/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
398#define OMAP54XX_ERRORGAIN_SHIFT 16
399#define OMAP54XX_ERRORGAIN_WIDTH 0x8
400#define OMAP54XX_ERRORGAIN_MASK (0xff << 16)
401
402/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
403#define OMAP54XX_ERROROFFSET_SHIFT 24
404#define OMAP54XX_ERROROFFSET_WIDTH 0x8
405#define OMAP54XX_ERROROFFSET_MASK (0xff << 24)
406
407/* Used by PRM_RSTST */
408#define OMAP54XX_EXTERNAL_WARM_RST_SHIFT 5
409#define OMAP54XX_EXTERNAL_WARM_RST_WIDTH 0x1
410#define OMAP54XX_EXTERNAL_WARM_RST_MASK (1 << 5)
411
412/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
413#define OMAP54XX_FORCEUPDATE_SHIFT 1
414#define OMAP54XX_FORCEUPDATE_WIDTH 0x1
415#define OMAP54XX_FORCEUPDATE_MASK (1 << 1)
416
417/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
418#define OMAP54XX_FORCEUPDATEWAIT_SHIFT 8
419#define OMAP54XX_FORCEUPDATEWAIT_WIDTH 0x18
420#define OMAP54XX_FORCEUPDATEWAIT_MASK (0xffffff << 8)
421
422/* Used by PRM_IRQENABLE_DSP, PRM_IRQENABLE_IPU */
423#define OMAP54XX_FORCEWKUP_EN_SHIFT 10
424#define OMAP54XX_FORCEWKUP_EN_WIDTH 0x1
425#define OMAP54XX_FORCEWKUP_EN_MASK (1 << 10)
426
427/* Used by PRM_IRQSTATUS_DSP, PRM_IRQSTATUS_IPU */
428#define OMAP54XX_FORCEWKUP_ST_SHIFT 10
429#define OMAP54XX_FORCEWKUP_ST_WIDTH 0x1
430#define OMAP54XX_FORCEWKUP_ST_MASK (1 << 10)
431
432/* Used by REVISION_PRM */
433#define OMAP54XX_FUNC_SHIFT 16
434#define OMAP54XX_FUNC_WIDTH 0xc
435#define OMAP54XX_FUNC_MASK (0xfff << 16)
436
437/* Used by PRM_RSTST */
438#define OMAP54XX_GLOBAL_COLD_RST_SHIFT 0
439#define OMAP54XX_GLOBAL_COLD_RST_WIDTH 0x1
440#define OMAP54XX_GLOBAL_COLD_RST_MASK (1 << 0)
441
442/* Used by PRM_RSTST */
443#define OMAP54XX_GLOBAL_WARM_SW_RST_SHIFT 1
444#define OMAP54XX_GLOBAL_WARM_SW_RST_WIDTH 0x1
445#define OMAP54XX_GLOBAL_WARM_SW_RST_MASK (1 << 1)
446
447/* Used by PRM_IO_PMCTRL */
448#define OMAP54XX_GLOBAL_WUEN_SHIFT 16
449#define OMAP54XX_GLOBAL_WUEN_WIDTH 0x1
450#define OMAP54XX_GLOBAL_WUEN_MASK (1 << 16)
451
452/* Used by PM_GPU_PWRSTCTRL */
453#define OMAP54XX_GPU_MEM_ONSTATE_SHIFT 16
454#define OMAP54XX_GPU_MEM_ONSTATE_WIDTH 0x2
455#define OMAP54XX_GPU_MEM_ONSTATE_MASK (0x3 << 16)
456
457/* Used by PM_GPU_PWRSTST */
458#define OMAP54XX_GPU_MEM_STATEST_SHIFT 4
459#define OMAP54XX_GPU_MEM_STATEST_WIDTH 0x2
460#define OMAP54XX_GPU_MEM_STATEST_MASK (0x3 << 4)
461
462/* Used by PRM_VC_CFG_I2C_MODE */
463#define OMAP54XX_HSMCODE_SHIFT 0
464#define OMAP54XX_HSMCODE_WIDTH 0x3
465#define OMAP54XX_HSMCODE_MASK (0x7 << 0)
466
467/* Used by PRM_VC_CFG_I2C_MODE */
468#define OMAP54XX_HSMODEEN_SHIFT 3
469#define OMAP54XX_HSMODEEN_WIDTH 0x1
470#define OMAP54XX_HSMODEEN_MASK (1 << 3)
471
472/* Used by PRM_VC_CFG_I2C_CLK */
473#define OMAP54XX_HSSCLH_SHIFT 16
474#define OMAP54XX_HSSCLH_WIDTH 0x8
475#define OMAP54XX_HSSCLH_MASK (0xff << 16)
476
477/* Used by PRM_VC_CFG_I2C_CLK */
478#define OMAP54XX_HSSCLL_SHIFT 24
479#define OMAP54XX_HSSCLL_WIDTH 0x8
480#define OMAP54XX_HSSCLL_MASK (0xff << 24)
481
482/* Used by PM_IVA_PWRSTCTRL */
483#define OMAP54XX_HWA_MEM_ONSTATE_SHIFT 16
484#define OMAP54XX_HWA_MEM_ONSTATE_WIDTH 0x2
485#define OMAP54XX_HWA_MEM_ONSTATE_MASK (0x3 << 16)
486
487/* Used by PM_IVA_PWRSTCTRL */
488#define OMAP54XX_HWA_MEM_RETSTATE_SHIFT 8
489#define OMAP54XX_HWA_MEM_RETSTATE_WIDTH 0x1
490#define OMAP54XX_HWA_MEM_RETSTATE_MASK (1 << 8)
491
492/* Used by PM_IVA_PWRSTST */
493#define OMAP54XX_HWA_MEM_STATEST_SHIFT 4
494#define OMAP54XX_HWA_MEM_STATEST_WIDTH 0x2
495#define OMAP54XX_HWA_MEM_STATEST_MASK (0x3 << 4)
496
497/* Used by PRM_RSTST */
498#define OMAP54XX_ICEPICK_RST_SHIFT 9
499#define OMAP54XX_ICEPICK_RST_WIDTH 0x1
500#define OMAP54XX_ICEPICK_RST_MASK (1 << 9)
501
502/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
503#define OMAP54XX_INITVDD_SHIFT 2
504#define OMAP54XX_INITVDD_WIDTH 0x1
505#define OMAP54XX_INITVDD_MASK (1 << 2)
506
507/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
508#define OMAP54XX_INITVOLTAGE_SHIFT 8
509#define OMAP54XX_INITVOLTAGE_WIDTH 0x8
510#define OMAP54XX_INITVOLTAGE_MASK (0xff << 8)
511
512/*
513 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
514 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
515 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST,
516 * PRM_VOLTST_MM, PRM_VOLTST_MPU
517 */
518#define OMAP54XX_INTRANSITION_SHIFT 20
519#define OMAP54XX_INTRANSITION_WIDTH 0x1
520#define OMAP54XX_INTRANSITION_MASK (1 << 20)
521
522/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
523#define OMAP54XX_IO_EN_SHIFT 9
524#define OMAP54XX_IO_EN_WIDTH 0x1
525#define OMAP54XX_IO_EN_MASK (1 << 9)
526
527/* Used by PRM_IO_PMCTRL */
528#define OMAP54XX_IO_ON_STATUS_SHIFT 5
529#define OMAP54XX_IO_ON_STATUS_WIDTH 0x1
530#define OMAP54XX_IO_ON_STATUS_MASK (1 << 5)
531
532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
533#define OMAP54XX_IO_ST_SHIFT 9
534#define OMAP54XX_IO_ST_WIDTH 0x1
535#define OMAP54XX_IO_ST_MASK (1 << 9)
536
537/* Used by PM_CORE_PWRSTCTRL */
538#define OMAP54XX_IPU_L2RAM_ONSTATE_SHIFT 20
539#define OMAP54XX_IPU_L2RAM_ONSTATE_WIDTH 0x2
540#define OMAP54XX_IPU_L2RAM_ONSTATE_MASK (0x3 << 20)
541
542/* Used by PM_CORE_PWRSTCTRL */
543#define OMAP54XX_IPU_L2RAM_RETSTATE_SHIFT 10
544#define OMAP54XX_IPU_L2RAM_RETSTATE_WIDTH 0x1
545#define OMAP54XX_IPU_L2RAM_RETSTATE_MASK (1 << 10)
546
547/* Used by PM_CORE_PWRSTST */
548#define OMAP54XX_IPU_L2RAM_STATEST_SHIFT 8
549#define OMAP54XX_IPU_L2RAM_STATEST_WIDTH 0x2
550#define OMAP54XX_IPU_L2RAM_STATEST_MASK (0x3 << 8)
551
552/* Used by PM_CORE_PWRSTCTRL */
553#define OMAP54XX_IPU_UNICACHE_ONSTATE_SHIFT 22
554#define OMAP54XX_IPU_UNICACHE_ONSTATE_WIDTH 0x2
555#define OMAP54XX_IPU_UNICACHE_ONSTATE_MASK (0x3 << 22)
556
557/* Used by PM_CORE_PWRSTCTRL */
558#define OMAP54XX_IPU_UNICACHE_RETSTATE_SHIFT 11
559#define OMAP54XX_IPU_UNICACHE_RETSTATE_WIDTH 0x1
560#define OMAP54XX_IPU_UNICACHE_RETSTATE_MASK (1 << 11)
561
562/* Used by PM_CORE_PWRSTST */
563#define OMAP54XX_IPU_UNICACHE_STATEST_SHIFT 10
564#define OMAP54XX_IPU_UNICACHE_STATEST_WIDTH 0x2
565#define OMAP54XX_IPU_UNICACHE_STATEST_MASK (0x3 << 10)
566
567/* Used by PRM_IO_PMCTRL */
568#define OMAP54XX_ISOCLK_OVERRIDE_SHIFT 0
569#define OMAP54XX_ISOCLK_OVERRIDE_WIDTH 0x1
570#define OMAP54XX_ISOCLK_OVERRIDE_MASK (1 << 0)
571
572/* Used by PRM_IO_PMCTRL */
573#define OMAP54XX_ISOCLK_STATUS_SHIFT 1
574#define OMAP54XX_ISOCLK_STATUS_WIDTH 0x1
575#define OMAP54XX_ISOCLK_STATUS_MASK (1 << 1)
576
577/* Used by PRM_IO_PMCTRL */
578#define OMAP54XX_ISOOVR_EXTEND_SHIFT 4
579#define OMAP54XX_ISOOVR_EXTEND_WIDTH 0x1
580#define OMAP54XX_ISOOVR_EXTEND_MASK (1 << 4)
581
582/* Used by PRM_IO_COUNT */
583#define OMAP54XX_ISO_2_ON_TIME_SHIFT 0
584#define OMAP54XX_ISO_2_ON_TIME_WIDTH 0x8
585#define OMAP54XX_ISO_2_ON_TIME_MASK (0xff << 0)
586
587/* Used by PM_L3INIT_PWRSTCTRL */
588#define OMAP54XX_L3INIT_BANK1_ONSTATE_SHIFT 16
589#define OMAP54XX_L3INIT_BANK1_ONSTATE_WIDTH 0x2
590#define OMAP54XX_L3INIT_BANK1_ONSTATE_MASK (0x3 << 16)
591
592/* Used by PM_L3INIT_PWRSTCTRL */
593#define OMAP54XX_L3INIT_BANK1_RETSTATE_SHIFT 8
594#define OMAP54XX_L3INIT_BANK1_RETSTATE_WIDTH 0x1
595#define OMAP54XX_L3INIT_BANK1_RETSTATE_MASK (1 << 8)
596
597/* Used by PM_L3INIT_PWRSTST */
598#define OMAP54XX_L3INIT_BANK1_STATEST_SHIFT 4
599#define OMAP54XX_L3INIT_BANK1_STATEST_WIDTH 0x2
600#define OMAP54XX_L3INIT_BANK1_STATEST_MASK (0x3 << 4)
601
602/* Used by PM_L3INIT_PWRSTCTRL */
603#define OMAP54XX_L3INIT_BANK2_ONSTATE_SHIFT 18
604#define OMAP54XX_L3INIT_BANK2_ONSTATE_WIDTH 0x2
605#define OMAP54XX_L3INIT_BANK2_ONSTATE_MASK (0x3 << 18)
606
607/* Used by PM_L3INIT_PWRSTCTRL */
608#define OMAP54XX_L3INIT_BANK2_RETSTATE_SHIFT 9
609#define OMAP54XX_L3INIT_BANK2_RETSTATE_WIDTH 0x1
610#define OMAP54XX_L3INIT_BANK2_RETSTATE_MASK (1 << 9)
611
612/* Used by PM_L3INIT_PWRSTST */
613#define OMAP54XX_L3INIT_BANK2_STATEST_SHIFT 6
614#define OMAP54XX_L3INIT_BANK2_STATEST_WIDTH 0x2
615#define OMAP54XX_L3INIT_BANK2_STATEST_MASK (0x3 << 6)
616
617/*
618 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
619 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
620 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
621 */
622#define OMAP54XX_LASTPOWERSTATEENTERED_SHIFT 24
623#define OMAP54XX_LASTPOWERSTATEENTERED_WIDTH 0x2
624#define OMAP54XX_LASTPOWERSTATEENTERED_MASK (0x3 << 24)
625
626/* Used by PRM_RSTST */
627#define OMAP54XX_LLI_RST_SHIFT 14
628#define OMAP54XX_LLI_RST_WIDTH 0x1
629#define OMAP54XX_LLI_RST_MASK (1 << 14)
630
631/*
632 * Used by PM_ABE_PWRSTCTRL, PM_CORE_PWRSTCTRL, PM_DSP_PWRSTCTRL,
633 * PM_DSS_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
634 */
635#define OMAP54XX_LOGICRETSTATE_SHIFT 2
636#define OMAP54XX_LOGICRETSTATE_WIDTH 0x1
637#define OMAP54XX_LOGICRETSTATE_MASK (1 << 2)
638
639/*
640 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
641 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
642 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
643 */
644#define OMAP54XX_LOGICSTATEST_SHIFT 2
645#define OMAP54XX_LOGICSTATEST_WIDTH 0x1
646#define OMAP54XX_LOGICSTATEST_MASK (1 << 2)
647
648/*
649 * Used by RM_ABE_AESS_CONTEXT, RM_ABE_DMIC_CONTEXT, RM_ABE_MCASP_CONTEXT,
650 * RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT, RM_ABE_MCBSP3_CONTEXT,
651 * RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT, RM_ABE_TIMER5_CONTEXT,
652 * RM_ABE_TIMER6_CONTEXT, RM_ABE_TIMER7_CONTEXT, RM_ABE_TIMER8_CONTEXT,
653 * RM_ABE_WD_TIMER3_CONTEXT, RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
654 * RM_CAM_CAL_CONTEXT, RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT,
655 * RM_COREAON_SMARTREFLEX_CORE_CONTEXT, RM_COREAON_SMARTREFLEX_MM_CONTEXT,
656 * RM_COREAON_SMARTREFLEX_MPU_CONTEXT, RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT,
657 * RM_DSP_DSP_CONTEXT, RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT,
658 * RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT, RM_EMIF_EMIF2_CONTEXT,
659 * RM_EMIF_EMIF_DLL_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT,
660 * RM_EMU_DEBUGSS_CONTEXT, RM_GPU_GPU_CONTEXT, RM_IPU_IPU_CONTEXT,
661 * RM_IVA_IVA_CONTEXT, RM_IVA_SL2_CONTEXT, RM_L3INIT_IEEE1500_2_OCP_CONTEXT,
662 * RM_L3INIT_OCP2SCP1_CONTEXT, RM_L3INIT_OCP2SCP3_CONTEXT,
663 * RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
664 * RM_L3INSTR_L3_INSTR_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
665 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
666 * RM_L3MAIN2_L3_MAIN_2_CONTEXT, RM_L3MAIN2_OCMC_RAM_CONTEXT,
667 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_OCP2SCP2_CONTEXT,
668 * RM_L4CFG_SAR_ROM_CONTEXT, RM_L4PER_ELM_CONTEXT, RM_L4PER_HDQ1W_CONTEXT,
669 * RM_L4PER_I2C2_CONTEXT, RM_L4PER_I2C3_CONTEXT, RM_L4PER_I2C4_CONTEXT,
670 * RM_L4PER_I2C5_CONTEXT, RM_L4PER_L4_PER_CONTEXT, RM_L4PER_MCSPI1_CONTEXT,
671 * RM_L4PER_MCSPI2_CONTEXT, RM_L4PER_MCSPI3_CONTEXT, RM_L4PER_MCSPI4_CONTEXT,
672 * RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
673 * RM_L4PER_TIMER10_CONTEXT, RM_L4PER_TIMER11_CONTEXT, RM_L4PER_TIMER2_CONTEXT,
674 * RM_L4PER_TIMER3_CONTEXT, RM_L4PER_TIMER4_CONTEXT, RM_L4PER_TIMER9_CONTEXT,
675 * RM_L4SEC_FPKA_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
676 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT,
677 * RM_WKUPAON_COUNTER_32K_CONTEXT, RM_WKUPAON_GPIO1_CONTEXT,
678 * RM_WKUPAON_KBD_CONTEXT, RM_WKUPAON_L4_WKUP_CONTEXT,
679 * RM_WKUPAON_SAR_RAM_CONTEXT, RM_WKUPAON_TIMER12_CONTEXT,
680 * RM_WKUPAON_TIMER1_CONTEXT, RM_WKUPAON_WD_TIMER1_CONTEXT,
681 * RM_WKUPAON_WD_TIMER2_CONTEXT
682 */
683#define OMAP54XX_LOSTCONTEXT_DFF_SHIFT 0
684#define OMAP54XX_LOSTCONTEXT_DFF_WIDTH 0x1
685#define OMAP54XX_LOSTCONTEXT_DFF_MASK (1 << 0)
686
687/*
688 * Used by RM_C2C_C2C_CONTEXT, RM_C2C_C2C_OCP_FW_CONTEXT,
689 * RM_C2C_MODEM_ICR_CONTEXT, RM_DMA_DMA_SYSTEM_CONTEXT, RM_DSP_DSP_CONTEXT,
690 * RM_DSS_DSS_CONTEXT, RM_EMIF_DMM_CONTEXT, RM_EMIF_EMIF1_CONTEXT,
691 * RM_EMIF_EMIF2_CONTEXT, RM_EMIF_EMIF_OCP_FW_CONTEXT, RM_IPU_IPU_CONTEXT,
692 * RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT, RM_L3INIT_MMC2_CONTEXT,
693 * RM_L3INIT_USB_HOST_HS_CONTEXT, RM_L3INIT_USB_OTG_SS_CONTEXT,
694 * RM_L3INIT_USB_TLL_HS_CONTEXT, RM_L3INSTR_L3_MAIN_3_CONTEXT,
695 * RM_L3INSTR_OCP_WP_NOC_CONTEXT, RM_L3MAIN1_L3_MAIN_1_CONTEXT,
696 * RM_L3MAIN2_GPMC_CONTEXT, RM_L3MAIN2_L3_MAIN_2_CONTEXT,
697 * RM_L4CFG_L4_CFG_CONTEXT, RM_L4CFG_MAILBOX_CONTEXT,
698 * RM_L4CFG_SPINLOCK_CONTEXT, RM_L4PER_GPIO2_CONTEXT, RM_L4PER_GPIO3_CONTEXT,
699 * RM_L4PER_GPIO4_CONTEXT, RM_L4PER_GPIO5_CONTEXT, RM_L4PER_GPIO6_CONTEXT,
700 * RM_L4PER_GPIO7_CONTEXT, RM_L4PER_GPIO8_CONTEXT, RM_L4PER_I2C1_CONTEXT,
701 * RM_L4PER_L4_PER_CONTEXT, RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
702 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
703 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_AES1_CONTEXT, RM_L4SEC_AES2_CONTEXT,
704 * RM_L4SEC_DES3DES_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT, RM_L4SEC_RNG_CONTEXT,
705 * RM_L4SEC_SHA2MD5_CONTEXT, RM_MIPIEXT_LLI_CONTEXT,
706 * RM_MIPIEXT_LLI_OCP_FW_CONTEXT, RM_MIPIEXT_MPHY_CONTEXT, RM_MPU_MPU_CONTEXT
707 */
708#define OMAP54XX_LOSTCONTEXT_RFF_SHIFT 1
709#define OMAP54XX_LOSTCONTEXT_RFF_WIDTH 0x1
710#define OMAP54XX_LOSTCONTEXT_RFF_MASK (1 << 1)
711
712/* Used by RM_ABE_AESS_CONTEXT */
713#define OMAP54XX_LOSTMEM_AESSMEM_SHIFT 8
714#define OMAP54XX_LOSTMEM_AESSMEM_WIDTH 0x1
715#define OMAP54XX_LOSTMEM_AESSMEM_MASK (1 << 8)
716
717/* Used by RM_CAM_CAL_CONTEXT */
718#define OMAP54XX_LOSTMEM_CAL_MEM_SHIFT 8
719#define OMAP54XX_LOSTMEM_CAL_MEM_WIDTH 0x1
720#define OMAP54XX_LOSTMEM_CAL_MEM_MASK (1 << 8)
721
722/* Used by RM_CAM_FDIF_CONTEXT, RM_CAM_ISS_CONTEXT */
723#define OMAP54XX_LOSTMEM_CAM_MEM_SHIFT 8
724#define OMAP54XX_LOSTMEM_CAM_MEM_WIDTH 0x1
725#define OMAP54XX_LOSTMEM_CAM_MEM_MASK (1 << 8)
726
727/* Used by RM_EMIF_DMM_CONTEXT */
728#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_SHIFT 9
729#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_WIDTH 0x1
730#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_MASK (1 << 9)
731
732/* Renamed from LOSTMEM_CORE_NRET_BANK Used by RM_L3INSTR_OCP_WP_NOC_CONTEXT */
733#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_SHIFT 8
734#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_WIDTH 0x1
735#define OMAP54XX_LOSTMEM_CORE_NRET_BANK_8_8_MASK (1 << 8)
736
737/* Used by RM_L3MAIN2_OCMC_RAM_CONTEXT */
738#define OMAP54XX_LOSTMEM_CORE_OCMRAM_SHIFT 8
739#define OMAP54XX_LOSTMEM_CORE_OCMRAM_WIDTH 0x1
740#define OMAP54XX_LOSTMEM_CORE_OCMRAM_MASK (1 << 8)
741
742/* Used by RM_DMA_DMA_SYSTEM_CONTEXT, RM_EMIF_DMM_CONTEXT */
743#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_SHIFT 8
744#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_WIDTH 0x1
745#define OMAP54XX_LOSTMEM_CORE_OTHER_BANK_MASK (1 << 8)
746
747/* Used by RM_DSP_DSP_CONTEXT */
748#define OMAP54XX_LOSTMEM_DSP_EDMA_SHIFT 10
749#define OMAP54XX_LOSTMEM_DSP_EDMA_WIDTH 0x1
750#define OMAP54XX_LOSTMEM_DSP_EDMA_MASK (1 << 10)
751
752/* Used by RM_DSP_DSP_CONTEXT */
753#define OMAP54XX_LOSTMEM_DSP_L1_SHIFT 8
754#define OMAP54XX_LOSTMEM_DSP_L1_WIDTH 0x1
755#define OMAP54XX_LOSTMEM_DSP_L1_MASK (1 << 8)
756
757/* Used by RM_DSP_DSP_CONTEXT */
758#define OMAP54XX_LOSTMEM_DSP_L2_SHIFT 9
759#define OMAP54XX_LOSTMEM_DSP_L2_WIDTH 0x1
760#define OMAP54XX_LOSTMEM_DSP_L2_MASK (1 << 9)
761
762/* Used by RM_DSS_BB2D_CONTEXT, RM_DSS_DSS_CONTEXT */
763#define OMAP54XX_LOSTMEM_DSS_MEM_SHIFT 8
764#define OMAP54XX_LOSTMEM_DSS_MEM_WIDTH 0x1
765#define OMAP54XX_LOSTMEM_DSS_MEM_MASK (1 << 8)
766
767/* Used by RM_EMU_DEBUGSS_CONTEXT */
768#define OMAP54XX_LOSTMEM_EMU_BANK_SHIFT 8
769#define OMAP54XX_LOSTMEM_EMU_BANK_WIDTH 0x1
770#define OMAP54XX_LOSTMEM_EMU_BANK_MASK (1 << 8)
771
772/* Used by RM_GPU_GPU_CONTEXT */
773#define OMAP54XX_LOSTMEM_GPU_MEM_SHIFT 8
774#define OMAP54XX_LOSTMEM_GPU_MEM_WIDTH 0x1
775#define OMAP54XX_LOSTMEM_GPU_MEM_MASK (1 << 8)
776
777/* Used by RM_IVA_IVA_CONTEXT */
778#define OMAP54XX_LOSTMEM_HWA_MEM_SHIFT 10
779#define OMAP54XX_LOSTMEM_HWA_MEM_WIDTH 0x1
780#define OMAP54XX_LOSTMEM_HWA_MEM_MASK (1 << 10)
781
782/* Used by RM_IPU_IPU_CONTEXT */
783#define OMAP54XX_LOSTMEM_IPU_L2RAM_SHIFT 9
784#define OMAP54XX_LOSTMEM_IPU_L2RAM_WIDTH 0x1
785#define OMAP54XX_LOSTMEM_IPU_L2RAM_MASK (1 << 9)
786
787/* Used by RM_IPU_IPU_CONTEXT */
788#define OMAP54XX_LOSTMEM_IPU_UNICACHE_SHIFT 8
789#define OMAP54XX_LOSTMEM_IPU_UNICACHE_WIDTH 0x1
790#define OMAP54XX_LOSTMEM_IPU_UNICACHE_MASK (1 << 8)
791
792/*
793 * Used by RM_L3INIT_HSI_CONTEXT, RM_L3INIT_MMC1_CONTEXT,
794 * RM_L3INIT_MMC2_CONTEXT, RM_L3INIT_SATA_CONTEXT, RM_L3INIT_UNIPRO2_CONTEXT,
795 * RM_L3INIT_USB_OTG_SS_CONTEXT
796 */
797#define OMAP54XX_LOSTMEM_L3INIT_BANK1_SHIFT 8
798#define OMAP54XX_LOSTMEM_L3INIT_BANK1_WIDTH 0x1
799#define OMAP54XX_LOSTMEM_L3INIT_BANK1_MASK (1 << 8)
800
801/* Used by RM_MPU_MPU_CONTEXT */
802#define OMAP54XX_LOSTMEM_MPU_L2_SHIFT 9
803#define OMAP54XX_LOSTMEM_MPU_L2_WIDTH 0x1
804#define OMAP54XX_LOSTMEM_MPU_L2_MASK (1 << 9)
805
806/* Used by RM_MPU_MPU_CONTEXT */
807#define OMAP54XX_LOSTMEM_MPU_RAM_SHIFT 10
808#define OMAP54XX_LOSTMEM_MPU_RAM_WIDTH 0x1
809#define OMAP54XX_LOSTMEM_MPU_RAM_MASK (1 << 10)
810
811/*
812 * Used by RM_L4PER_MMC3_CONTEXT, RM_L4PER_MMC4_CONTEXT, RM_L4PER_MMC5_CONTEXT,
813 * RM_L4SEC_FPKA_CONTEXT
814 */
815#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_SHIFT 8
816#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_WIDTH 0x1
817#define OMAP54XX_LOSTMEM_NONRETAINED_BANK_MASK (1 << 8)
818
819/*
820 * Used by RM_ABE_DMIC_CONTEXT, RM_ABE_MCBSP1_CONTEXT, RM_ABE_MCBSP2_CONTEXT,
821 * RM_ABE_MCBSP3_CONTEXT, RM_ABE_MCPDM_CONTEXT, RM_ABE_SLIMBUS1_CONTEXT
822 */
823#define OMAP54XX_LOSTMEM_PERIHPMEM_SHIFT 8
824#define OMAP54XX_LOSTMEM_PERIHPMEM_WIDTH 0x1
825#define OMAP54XX_LOSTMEM_PERIHPMEM_MASK (1 << 8)
826
827/*
828 * Used by RM_L4PER_UART1_CONTEXT, RM_L4PER_UART2_CONTEXT,
829 * RM_L4PER_UART3_CONTEXT, RM_L4PER_UART4_CONTEXT, RM_L4PER_UART5_CONTEXT,
830 * RM_L4PER_UART6_CONTEXT, RM_L4SEC_DMA_CRYPTO_CONTEXT
831 */
832#define OMAP54XX_LOSTMEM_RETAINED_BANK_SHIFT 8
833#define OMAP54XX_LOSTMEM_RETAINED_BANK_WIDTH 0x1
834#define OMAP54XX_LOSTMEM_RETAINED_BANK_MASK (1 << 8)
835
836/* Used by RM_IVA_SL2_CONTEXT */
837#define OMAP54XX_LOSTMEM_SL2_MEM_SHIFT 8
838#define OMAP54XX_LOSTMEM_SL2_MEM_WIDTH 0x1
839#define OMAP54XX_LOSTMEM_SL2_MEM_MASK (1 << 8)
840
841/* Used by RM_IVA_IVA_CONTEXT */
842#define OMAP54XX_LOSTMEM_TCM1_MEM_SHIFT 8
843#define OMAP54XX_LOSTMEM_TCM1_MEM_WIDTH 0x1
844#define OMAP54XX_LOSTMEM_TCM1_MEM_MASK (1 << 8)
845
846/* Used by RM_IVA_IVA_CONTEXT */
847#define OMAP54XX_LOSTMEM_TCM2_MEM_SHIFT 9
848#define OMAP54XX_LOSTMEM_TCM2_MEM_WIDTH 0x1
849#define OMAP54XX_LOSTMEM_TCM2_MEM_MASK (1 << 9)
850
851/* Used by RM_WKUPAON_SAR_RAM_CONTEXT */
852#define OMAP54XX_LOSTMEM_WKUP_BANK_SHIFT 8
853#define OMAP54XX_LOSTMEM_WKUP_BANK_WIDTH 0x1
854#define OMAP54XX_LOSTMEM_WKUP_BANK_MASK (1 << 8)
855
856/*
857 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
858 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
859 * PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL, PM_MPU_PWRSTCTRL
860 */
861#define OMAP54XX_LOWPOWERSTATECHANGE_SHIFT 4
862#define OMAP54XX_LOWPOWERSTATECHANGE_WIDTH 0x1
863#define OMAP54XX_LOWPOWERSTATECHANGE_MASK (1 << 4)
864
865/* Used by PRM_DEBUG_TRANS_CFG */
866#define OMAP54XX_MODE_SHIFT 0
867#define OMAP54XX_MODE_WIDTH 0x2
868#define OMAP54XX_MODE_MASK (0x3 << 0)
869
870/* Used by PRM_MODEM_IF_CTRL */
871#define OMAP54XX_MODEM_SHUTDOWN_IRQ_SHIFT 9
872#define OMAP54XX_MODEM_SHUTDOWN_IRQ_WIDTH 0x1
873#define OMAP54XX_MODEM_SHUTDOWN_IRQ_MASK (1 << 9)
874
875/* Used by PRM_MODEM_IF_CTRL */
876#define OMAP54XX_MODEM_WAKE_IRQ_SHIFT 8
877#define OMAP54XX_MODEM_WAKE_IRQ_WIDTH 0x1
878#define OMAP54XX_MODEM_WAKE_IRQ_MASK (1 << 8)
879
880/* Used by PM_MPU_PWRSTCTRL */
881#define OMAP54XX_MPU_L2_ONSTATE_SHIFT 18
882#define OMAP54XX_MPU_L2_ONSTATE_WIDTH 0x2
883#define OMAP54XX_MPU_L2_ONSTATE_MASK (0x3 << 18)
884
885/* Used by PM_MPU_PWRSTCTRL */
886#define OMAP54XX_MPU_L2_RETSTATE_SHIFT 9
887#define OMAP54XX_MPU_L2_RETSTATE_WIDTH 0x1
888#define OMAP54XX_MPU_L2_RETSTATE_MASK (1 << 9)
889
890/* Used by PM_MPU_PWRSTST */
891#define OMAP54XX_MPU_L2_STATEST_SHIFT 6
892#define OMAP54XX_MPU_L2_STATEST_WIDTH 0x2
893#define OMAP54XX_MPU_L2_STATEST_MASK (0x3 << 6)
894
895/* Used by PM_MPU_PWRSTCTRL */
896#define OMAP54XX_MPU_RAM_ONSTATE_SHIFT 20
897#define OMAP54XX_MPU_RAM_ONSTATE_WIDTH 0x2
898#define OMAP54XX_MPU_RAM_ONSTATE_MASK (0x3 << 20)
899
900/* Used by PM_MPU_PWRSTCTRL */
901#define OMAP54XX_MPU_RAM_RETSTATE_SHIFT 10
902#define OMAP54XX_MPU_RAM_RETSTATE_WIDTH 0x1
903#define OMAP54XX_MPU_RAM_RETSTATE_MASK (1 << 10)
904
905/* Used by PM_MPU_PWRSTST */
906#define OMAP54XX_MPU_RAM_STATEST_SHIFT 8
907#define OMAP54XX_MPU_RAM_STATEST_WIDTH 0x2
908#define OMAP54XX_MPU_RAM_STATEST_MASK (0x3 << 8)
909
910/* Used by PRM_RSTST */
911#define OMAP54XX_MPU_SECURITY_VIOL_RST_SHIFT 2
912#define OMAP54XX_MPU_SECURITY_VIOL_RST_WIDTH 0x1
913#define OMAP54XX_MPU_SECURITY_VIOL_RST_MASK (1 << 2)
914
915/* Used by PRM_RSTST */
916#define OMAP54XX_MPU_WDT_RST_SHIFT 3
917#define OMAP54XX_MPU_WDT_RST_WIDTH 0x1
918#define OMAP54XX_MPU_WDT_RST_MASK (1 << 3)
919
920/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
921#define OMAP54XX_NOCAP_SHIFT 4
922#define OMAP54XX_NOCAP_WIDTH 0x1
923#define OMAP54XX_NOCAP_MASK (1 << 4)
924
925/* Used by PM_CORE_PWRSTCTRL */
926#define OMAP54XX_OCP_NRET_BANK_ONSTATE_SHIFT 24
927#define OMAP54XX_OCP_NRET_BANK_ONSTATE_WIDTH 0x2
928#define OMAP54XX_OCP_NRET_BANK_ONSTATE_MASK (0x3 << 24)
929
930/* Used by PM_CORE_PWRSTCTRL */
931#define OMAP54XX_OCP_NRET_BANK_RETSTATE_SHIFT 12
932#define OMAP54XX_OCP_NRET_BANK_RETSTATE_WIDTH 0x1
933#define OMAP54XX_OCP_NRET_BANK_RETSTATE_MASK (1 << 12)
934
935/* Used by PM_CORE_PWRSTST */
936#define OMAP54XX_OCP_NRET_BANK_STATEST_SHIFT 12
937#define OMAP54XX_OCP_NRET_BANK_STATEST_WIDTH 0x2
938#define OMAP54XX_OCP_NRET_BANK_STATEST_MASK (0x3 << 12)
939
940/*
941 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
942 * PRM_VC_VAL_CMD_VDD_MPU_L
943 */
944#define OMAP54XX_OFF_SHIFT 0
945#define OMAP54XX_OFF_WIDTH 0x8
946#define OMAP54XX_OFF_MASK (0xff << 0)
947
948/*
949 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
950 * PRM_VC_VAL_CMD_VDD_MPU_L
951 */
952#define OMAP54XX_ON_SHIFT 24
953#define OMAP54XX_ON_WIDTH 0x8
954#define OMAP54XX_ON_MASK (0xff << 24)
955
956/*
957 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
958 * PRM_VC_VAL_CMD_VDD_MPU_L
959 */
960#define OMAP54XX_ONLP_SHIFT 16
961#define OMAP54XX_ONLP_WIDTH 0x8
962#define OMAP54XX_ONLP_MASK (0xff << 16)
963
964/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
965#define OMAP54XX_OPP_CHANGE_SHIFT 2
966#define OMAP54XX_OPP_CHANGE_WIDTH 0x1
967#define OMAP54XX_OPP_CHANGE_MASK (1 << 2)
968
969/* Used by PRM_VC_VAL_BYPASS */
970#define OMAP54XX_OPP_CHANGE_EMIF_LVL_SHIFT 25
971#define OMAP54XX_OPP_CHANGE_EMIF_LVL_WIDTH 0x1
972#define OMAP54XX_OPP_CHANGE_EMIF_LVL_MASK (1 << 25)
973
974/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
975#define OMAP54XX_OPP_SEL_SHIFT 0
976#define OMAP54XX_OPP_SEL_WIDTH 0x2
977#define OMAP54XX_OPP_SEL_MASK (0x3 << 0)
978
979/* Used by PRM_DEBUG_OUT */
980#define OMAP54XX_OUTPUT_SHIFT 0
981#define OMAP54XX_OUTPUT_WIDTH 0x20
982#define OMAP54XX_OUTPUT_MASK (0xffffffff << 0)
983
984/* Used by PRM_SRAM_COUNT */
985#define OMAP54XX_PCHARGECNT_VALUE_SHIFT 0
986#define OMAP54XX_PCHARGECNT_VALUE_WIDTH 0x6
987#define OMAP54XX_PCHARGECNT_VALUE_MASK (0x3f << 0)
988
989/* Used by PRM_PSCON_COUNT */
990#define OMAP54XX_PCHARGE_TIME_SHIFT 0
991#define OMAP54XX_PCHARGE_TIME_WIDTH 0x8
992#define OMAP54XX_PCHARGE_TIME_MASK (0xff << 0)
993
994/* Used by PM_ABE_PWRSTCTRL */
995#define OMAP54XX_PERIPHMEM_ONSTATE_SHIFT 20
996#define OMAP54XX_PERIPHMEM_ONSTATE_WIDTH 0x2
997#define OMAP54XX_PERIPHMEM_ONSTATE_MASK (0x3 << 20)
998
999/* Used by PM_ABE_PWRSTCTRL */
1000#define OMAP54XX_PERIPHMEM_RETSTATE_SHIFT 10
1001#define OMAP54XX_PERIPHMEM_RETSTATE_WIDTH 0x1
1002#define OMAP54XX_PERIPHMEM_RETSTATE_MASK (1 << 10)
1003
1004/* Used by PM_ABE_PWRSTST */
1005#define OMAP54XX_PERIPHMEM_STATEST_SHIFT 8
1006#define OMAP54XX_PERIPHMEM_STATEST_WIDTH 0x2
1007#define OMAP54XX_PERIPHMEM_STATEST_MASK (0x3 << 8)
1008
1009/* Used by PRM_PHASE1_CNDP */
1010#define OMAP54XX_PHASE1_CNDP_SHIFT 0
1011#define OMAP54XX_PHASE1_CNDP_WIDTH 0x20
1012#define OMAP54XX_PHASE1_CNDP_MASK (0xffffffff << 0)
1013
1014/* Used by PRM_PHASE2A_CNDP */
1015#define OMAP54XX_PHASE2A_CNDP_SHIFT 0
1016#define OMAP54XX_PHASE2A_CNDP_WIDTH 0x20
1017#define OMAP54XX_PHASE2A_CNDP_MASK (0xffffffff << 0)
1018
1019/* Used by PRM_PHASE2B_CNDP */
1020#define OMAP54XX_PHASE2B_CNDP_SHIFT 0
1021#define OMAP54XX_PHASE2B_CNDP_WIDTH 0x20
1022#define OMAP54XX_PHASE2B_CNDP_MASK (0xffffffff << 0)
1023
1024/* Used by PRM_PSCON_COUNT */
1025#define OMAP54XX_PONOUT_2_PGOODIN_TIME_SHIFT 8
1026#define OMAP54XX_PONOUT_2_PGOODIN_TIME_WIDTH 0x8
1027#define OMAP54XX_PONOUT_2_PGOODIN_TIME_MASK (0xff << 8)
1028
1029/*
1030 * Used by PM_ABE_PWRSTCTRL, PM_CAM_PWRSTCTRL, PM_CORE_PWRSTCTRL,
1031 * PM_CUSTEFUSE_PWRSTCTRL, PM_DSP_PWRSTCTRL, PM_DSS_PWRSTCTRL,
1032 * PM_EMU_PWRSTCTRL, PM_GPU_PWRSTCTRL, PM_IVA_PWRSTCTRL, PM_L3INIT_PWRSTCTRL,
1033 * PM_MPU_PWRSTCTRL
1034 */
1035#define OMAP54XX_POWERSTATE_SHIFT 0
1036#define OMAP54XX_POWERSTATE_WIDTH 0x2
1037#define OMAP54XX_POWERSTATE_MASK (0x3 << 0)
1038
1039/*
1040 * Used by PM_ABE_PWRSTST, PM_CAM_PWRSTST, PM_CORE_PWRSTST,
1041 * PM_CUSTEFUSE_PWRSTST, PM_DSP_PWRSTST, PM_DSS_PWRSTST, PM_EMU_PWRSTST,
1042 * PM_GPU_PWRSTST, PM_IVA_PWRSTST, PM_L3INIT_PWRSTST, PM_MPU_PWRSTST
1043 */
1044#define OMAP54XX_POWERSTATEST_SHIFT 0
1045#define OMAP54XX_POWERSTATEST_WIDTH 0x2
1046#define OMAP54XX_POWERSTATEST_MASK (0x3 << 0)
1047
1048/* Used by PRM_PWRREQCTRL */
1049#define OMAP54XX_PWRREQ_COND_SHIFT 0
1050#define OMAP54XX_PWRREQ_COND_WIDTH 0x2
1051#define OMAP54XX_PWRREQ_COND_MASK (0x3 << 0)
1052
1053/* Used by PRM_VC_SMPS_CORE_CONFIG */
1054#define OMAP54XX_RACEN_VDD_CORE_L_SHIFT 27
1055#define OMAP54XX_RACEN_VDD_CORE_L_WIDTH 0x1
1056#define OMAP54XX_RACEN_VDD_CORE_L_MASK (1 << 27)
1057
1058/* Used by PRM_VC_SMPS_MM_CONFIG */
1059#define OMAP54XX_RACEN_VDD_MM_L_SHIFT 27
1060#define OMAP54XX_RACEN_VDD_MM_L_WIDTH 0x1
1061#define OMAP54XX_RACEN_VDD_MM_L_MASK (1 << 27)
1062
1063/* Used by PRM_VC_SMPS_MPU_CONFIG */
1064#define OMAP54XX_RACEN_VDD_MPU_L_SHIFT 27
1065#define OMAP54XX_RACEN_VDD_MPU_L_WIDTH 0x1
1066#define OMAP54XX_RACEN_VDD_MPU_L_MASK (1 << 27)
1067
1068/* Used by PRM_VC_SMPS_CORE_CONFIG */
1069#define OMAP54XX_RAC_VDD_CORE_L_SHIFT 26
1070#define OMAP54XX_RAC_VDD_CORE_L_WIDTH 0x1
1071#define OMAP54XX_RAC_VDD_CORE_L_MASK (1 << 26)
1072
1073/* Used by PRM_VC_SMPS_MM_CONFIG */
1074#define OMAP54XX_RAC_VDD_MM_L_SHIFT 26
1075#define OMAP54XX_RAC_VDD_MM_L_WIDTH 0x1
1076#define OMAP54XX_RAC_VDD_MM_L_MASK (1 << 26)
1077
1078/* Used by PRM_VC_SMPS_MPU_CONFIG */
1079#define OMAP54XX_RAC_VDD_MPU_L_SHIFT 26
1080#define OMAP54XX_RAC_VDD_MPU_L_WIDTH 0x1
1081#define OMAP54XX_RAC_VDD_MPU_L_MASK (1 << 26)
1082
1083/*
1084 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1085 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1086 * PRM_VOLTSETUP_MPU_RET_SLEEP
1087 */
1088#define OMAP54XX_RAMP_DOWN_COUNT_SHIFT 16
1089#define OMAP54XX_RAMP_DOWN_COUNT_WIDTH 0x6
1090#define OMAP54XX_RAMP_DOWN_COUNT_MASK (0x3f << 16)
1091
1092/*
1093 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1094 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1095 * PRM_VOLTSETUP_MPU_RET_SLEEP
1096 */
1097#define OMAP54XX_RAMP_DOWN_PRESCAL_SHIFT 24
1098#define OMAP54XX_RAMP_DOWN_PRESCAL_WIDTH 0x2
1099#define OMAP54XX_RAMP_DOWN_PRESCAL_MASK (0x3 << 24)
1100
1101/*
1102 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1103 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1104 * PRM_VOLTSETUP_MPU_RET_SLEEP
1105 */
1106#define OMAP54XX_RAMP_UP_COUNT_SHIFT 0
1107#define OMAP54XX_RAMP_UP_COUNT_WIDTH 0x6
1108#define OMAP54XX_RAMP_UP_COUNT_MASK (0x3f << 0)
1109
1110/*
1111 * Used by PRM_VOLTSETUP_CORE_OFF, PRM_VOLTSETUP_CORE_RET_SLEEP,
1112 * PRM_VOLTSETUP_MM_OFF, PRM_VOLTSETUP_MM_RET_SLEEP, PRM_VOLTSETUP_MPU_OFF,
1113 * PRM_VOLTSETUP_MPU_RET_SLEEP
1114 */
1115#define OMAP54XX_RAMP_UP_PRESCAL_SHIFT 8
1116#define OMAP54XX_RAMP_UP_PRESCAL_WIDTH 0x2
1117#define OMAP54XX_RAMP_UP_PRESCAL_MASK (0x3 << 8)
1118
1119/* Used by PRM_VC_SMPS_CORE_CONFIG */
1120#define OMAP54XX_RAV_VDD_CORE_L_SHIFT 25
1121#define OMAP54XX_RAV_VDD_CORE_L_WIDTH 0x1
1122#define OMAP54XX_RAV_VDD_CORE_L_MASK (1 << 25)
1123
1124/* Used by PRM_VC_SMPS_MM_CONFIG */
1125#define OMAP54XX_RAV_VDD_MM_L_SHIFT 25
1126#define OMAP54XX_RAV_VDD_MM_L_WIDTH 0x1
1127#define OMAP54XX_RAV_VDD_MM_L_MASK (1 << 25)
1128
1129/* Used by PRM_VC_SMPS_MPU_CONFIG */
1130#define OMAP54XX_RAV_VDD_MPU_L_SHIFT 25
1131#define OMAP54XX_RAV_VDD_MPU_L_WIDTH 0x1
1132#define OMAP54XX_RAV_VDD_MPU_L_MASK (1 << 25)
1133
1134/* Used by PRM_VC_VAL_BYPASS */
1135#define OMAP54XX_REGADDR_SHIFT 8
1136#define OMAP54XX_REGADDR_WIDTH 0x8
1137#define OMAP54XX_REGADDR_MASK (0xff << 8)
1138
1139/*
1140 * Used by PRM_VC_VAL_CMD_VDD_CORE_L, PRM_VC_VAL_CMD_VDD_MM_L,
1141 * PRM_VC_VAL_CMD_VDD_MPU_L
1142 */
1143#define OMAP54XX_RET_SHIFT 8
1144#define OMAP54XX_RET_WIDTH 0x8
1145#define OMAP54XX_RET_MASK (0xff << 8)
1146
1147/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1148#define OMAP54XX_RETMODE_ENABLE_SHIFT 0
1149#define OMAP54XX_RETMODE_ENABLE_WIDTH 0x1
1150#define OMAP54XX_RETMODE_ENABLE_MASK (1 << 0)
1151
1152/* Used by PRM_RSTTIME */
1153#define OMAP54XX_RSTTIME1_SHIFT 0
1154#define OMAP54XX_RSTTIME1_WIDTH 0xa
1155#define OMAP54XX_RSTTIME1_MASK (0x3ff << 0)
1156
1157/* Used by PRM_RSTTIME */
1158#define OMAP54XX_RSTTIME2_SHIFT 10
1159#define OMAP54XX_RSTTIME2_WIDTH 0x5
1160#define OMAP54XX_RSTTIME2_MASK (0x1f << 10)
1161
1162/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1163#define OMAP54XX_RST_CPU0_SHIFT 0
1164#define OMAP54XX_RST_CPU0_WIDTH 0x1
1165#define OMAP54XX_RST_CPU0_MASK (1 << 0)
1166
1167/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1168#define OMAP54XX_RST_CPU1_SHIFT 1
1169#define OMAP54XX_RST_CPU1_WIDTH 0x1
1170#define OMAP54XX_RST_CPU1_MASK (1 << 1)
1171
1172/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1173#define OMAP54XX_RST_DSP_SHIFT 0
1174#define OMAP54XX_RST_DSP_WIDTH 0x1
1175#define OMAP54XX_RST_DSP_MASK (1 << 0)
1176
1177/* Used by RM_DSP_RSTST */
1178#define OMAP54XX_RST_DSP_EMU_SHIFT 2
1179#define OMAP54XX_RST_DSP_EMU_WIDTH 0x1
1180#define OMAP54XX_RST_DSP_EMU_MASK (1 << 2)
1181
1182/* Used by RM_DSP_RSTST */
1183#define OMAP54XX_RST_DSP_EMU_REQ_SHIFT 3
1184#define OMAP54XX_RST_DSP_EMU_REQ_WIDTH 0x1
1185#define OMAP54XX_RST_DSP_EMU_REQ_MASK (1 << 3)
1186
1187/* Used by RM_DSP_RSTCTRL, RM_DSP_RSTST */
1188#define OMAP54XX_RST_DSP_MMU_CACHE_SHIFT 1
1189#define OMAP54XX_RST_DSP_MMU_CACHE_WIDTH 0x1
1190#define OMAP54XX_RST_DSP_MMU_CACHE_MASK (1 << 1)
1191
1192/* Used by RM_IPU_RSTST */
1193#define OMAP54XX_RST_EMULATION_CPU0_SHIFT 3
1194#define OMAP54XX_RST_EMULATION_CPU0_WIDTH 0x1
1195#define OMAP54XX_RST_EMULATION_CPU0_MASK (1 << 3)
1196
1197/* Used by RM_IPU_RSTST */
1198#define OMAP54XX_RST_EMULATION_CPU1_SHIFT 4
1199#define OMAP54XX_RST_EMULATION_CPU1_WIDTH 0x1
1200#define OMAP54XX_RST_EMULATION_CPU1_MASK (1 << 4)
1201
1202/* Used by RM_IVA_RSTST */
1203#define OMAP54XX_RST_EMULATION_SEQ1_SHIFT 3
1204#define OMAP54XX_RST_EMULATION_SEQ1_WIDTH 0x1
1205#define OMAP54XX_RST_EMULATION_SEQ1_MASK (1 << 3)
1206
1207/* Used by RM_IVA_RSTST */
1208#define OMAP54XX_RST_EMULATION_SEQ2_SHIFT 4
1209#define OMAP54XX_RST_EMULATION_SEQ2_WIDTH 0x1
1210#define OMAP54XX_RST_EMULATION_SEQ2_MASK (1 << 4)
1211
1212/* Used by PRM_RSTCTRL */
1213#define OMAP54XX_RST_GLOBAL_COLD_SW_SHIFT 1
1214#define OMAP54XX_RST_GLOBAL_COLD_SW_WIDTH 0x1
1215#define OMAP54XX_RST_GLOBAL_COLD_SW_MASK (1 << 1)
1216
1217/* Used by PRM_RSTCTRL */
1218#define OMAP54XX_RST_GLOBAL_WARM_SW_SHIFT 0
1219#define OMAP54XX_RST_GLOBAL_WARM_SW_WIDTH 0x1
1220#define OMAP54XX_RST_GLOBAL_WARM_SW_MASK (1 << 0)
1221
1222/* Used by RM_IPU_RSTST */
1223#define OMAP54XX_RST_ICECRUSHER_CPU0_SHIFT 5
1224#define OMAP54XX_RST_ICECRUSHER_CPU0_WIDTH 0x1
1225#define OMAP54XX_RST_ICECRUSHER_CPU0_MASK (1 << 5)
1226
1227/* Used by RM_IPU_RSTST */
1228#define OMAP54XX_RST_ICECRUSHER_CPU1_SHIFT 6
1229#define OMAP54XX_RST_ICECRUSHER_CPU1_WIDTH 0x1
1230#define OMAP54XX_RST_ICECRUSHER_CPU1_MASK (1 << 6)
1231
1232/* Used by RM_IVA_RSTST */
1233#define OMAP54XX_RST_ICECRUSHER_SEQ1_SHIFT 5
1234#define OMAP54XX_RST_ICECRUSHER_SEQ1_WIDTH 0x1
1235#define OMAP54XX_RST_ICECRUSHER_SEQ1_MASK (1 << 5)
1236
1237/* Used by RM_IVA_RSTST */
1238#define OMAP54XX_RST_ICECRUSHER_SEQ2_SHIFT 6
1239#define OMAP54XX_RST_ICECRUSHER_SEQ2_WIDTH 0x1
1240#define OMAP54XX_RST_ICECRUSHER_SEQ2_MASK (1 << 6)
1241
1242/* Used by RM_IPU_RSTCTRL, RM_IPU_RSTST */
1243#define OMAP54XX_RST_IPU_MMU_CACHE_SHIFT 2
1244#define OMAP54XX_RST_IPU_MMU_CACHE_WIDTH 0x1
1245#define OMAP54XX_RST_IPU_MMU_CACHE_MASK (1 << 2)
1246
1247/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1248#define OMAP54XX_RST_LOGIC_SHIFT 2
1249#define OMAP54XX_RST_LOGIC_WIDTH 0x1
1250#define OMAP54XX_RST_LOGIC_MASK (1 << 2)
1251
1252/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1253#define OMAP54XX_RST_SEQ1_SHIFT 0
1254#define OMAP54XX_RST_SEQ1_WIDTH 0x1
1255#define OMAP54XX_RST_SEQ1_MASK (1 << 0)
1256
1257/* Used by RM_IVA_RSTCTRL, RM_IVA_RSTST */
1258#define OMAP54XX_RST_SEQ2_SHIFT 1
1259#define OMAP54XX_RST_SEQ2_WIDTH 0x1
1260#define OMAP54XX_RST_SEQ2_MASK (1 << 1)
1261
1262/* Used by REVISION_PRM */
1263#define OMAP54XX_R_RTL_SHIFT 11
1264#define OMAP54XX_R_RTL_WIDTH 0x5
1265#define OMAP54XX_R_RTL_MASK (0x1f << 11)
1266
1267/* Used by PRM_VC_SMPS_CORE_CONFIG */
1268#define OMAP54XX_SA_VDD_CORE_L_SHIFT 0
1269#define OMAP54XX_SA_VDD_CORE_L_WIDTH 0x7
1270#define OMAP54XX_SA_VDD_CORE_L_MASK (0x7f << 0)
1271
1272/* Used by PRM_VC_SMPS_MM_CONFIG */
1273#define OMAP54XX_SA_VDD_MM_L_SHIFT 0
1274#define OMAP54XX_SA_VDD_MM_L_WIDTH 0x7
1275#define OMAP54XX_SA_VDD_MM_L_MASK (0x7f << 0)
1276
1277/* Used by PRM_VC_SMPS_MPU_CONFIG */
1278#define OMAP54XX_SA_VDD_MPU_L_SHIFT 0
1279#define OMAP54XX_SA_VDD_MPU_L_WIDTH 0x7
1280#define OMAP54XX_SA_VDD_MPU_L_MASK (0x7f << 0)
1281
1282/* Used by REVISION_PRM */
1283#define OMAP54XX_SCHEME_SHIFT 30
1284#define OMAP54XX_SCHEME_WIDTH 0x2
1285#define OMAP54XX_SCHEME_MASK (0x3 << 30)
1286
1287/* Used by PRM_VC_CFG_I2C_CLK */
1288#define OMAP54XX_SCLH_SHIFT 0
1289#define OMAP54XX_SCLH_WIDTH 0x8
1290#define OMAP54XX_SCLH_MASK (0xff << 0)
1291
1292/* Used by PRM_VC_CFG_I2C_CLK */
1293#define OMAP54XX_SCLL_SHIFT 8
1294#define OMAP54XX_SCLL_WIDTH 0x8
1295#define OMAP54XX_SCLL_MASK (0xff << 8)
1296
1297/* Used by PRM_RSTST */
1298#define OMAP54XX_SECURE_WDT_RST_SHIFT 4
1299#define OMAP54XX_SECURE_WDT_RST_WIDTH 0x1
1300#define OMAP54XX_SECURE_WDT_RST_MASK (1 << 4)
1301
1302/* Used by PRM_VC_SMPS_CORE_CONFIG */
1303#define OMAP54XX_SEL_SA_VDD_CORE_L_SHIFT 24
1304#define OMAP54XX_SEL_SA_VDD_CORE_L_WIDTH 0x1
1305#define OMAP54XX_SEL_SA_VDD_CORE_L_MASK (1 << 24)
1306
1307/* Used by PRM_VC_SMPS_MM_CONFIG */
1308#define OMAP54XX_SEL_SA_VDD_MM_L_SHIFT 24
1309#define OMAP54XX_SEL_SA_VDD_MM_L_WIDTH 0x1
1310#define OMAP54XX_SEL_SA_VDD_MM_L_MASK (1 << 24)
1311
1312/* Used by PRM_VC_SMPS_MPU_CONFIG */
1313#define OMAP54XX_SEL_SA_VDD_MPU_L_SHIFT 24
1314#define OMAP54XX_SEL_SA_VDD_MPU_L_WIDTH 0x1
1315#define OMAP54XX_SEL_SA_VDD_MPU_L_MASK (1 << 24)
1316
1317/* Used by PM_IVA_PWRSTCTRL */
1318#define OMAP54XX_SL2_MEM_ONSTATE_SHIFT 18
1319#define OMAP54XX_SL2_MEM_ONSTATE_WIDTH 0x2
1320#define OMAP54XX_SL2_MEM_ONSTATE_MASK (0x3 << 18)
1321
1322/* Used by PM_IVA_PWRSTCTRL */
1323#define OMAP54XX_SL2_MEM_RETSTATE_SHIFT 9
1324#define OMAP54XX_SL2_MEM_RETSTATE_WIDTH 0x1
1325#define OMAP54XX_SL2_MEM_RETSTATE_MASK (1 << 9)
1326
1327/* Used by PM_IVA_PWRSTST */
1328#define OMAP54XX_SL2_MEM_STATEST_SHIFT 6
1329#define OMAP54XX_SL2_MEM_STATEST_WIDTH 0x2
1330#define OMAP54XX_SL2_MEM_STATEST_MASK (0x3 << 6)
1331
1332/* Used by PRM_VC_VAL_BYPASS */
1333#define OMAP54XX_SLAVEADDR_SHIFT 0
1334#define OMAP54XX_SLAVEADDR_WIDTH 0x7
1335#define OMAP54XX_SLAVEADDR_MASK (0x7f << 0)
1336
1337/* Used by PRM_SRAM_COUNT */
1338#define OMAP54XX_SLPCNT_VALUE_SHIFT 16
1339#define OMAP54XX_SLPCNT_VALUE_WIDTH 0x8
1340#define OMAP54XX_SLPCNT_VALUE_MASK (0xff << 16)
1341
1342/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1343#define OMAP54XX_SMPSWAITTIMEMAX_SHIFT 8
1344#define OMAP54XX_SMPSWAITTIMEMAX_WIDTH 0x10
1345#define OMAP54XX_SMPSWAITTIMEMAX_MASK (0xffff << 8)
1346
1347/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1348#define OMAP54XX_SMPSWAITTIMEMIN_SHIFT 8
1349#define OMAP54XX_SMPSWAITTIMEMIN_WIDTH 0x10
1350#define OMAP54XX_SMPSWAITTIMEMIN_MASK (0xffff << 8)
1351
1352/* Used by PRM_VC_CORE_ERRST */
1353#define OMAP54XX_SMPS_RA_ERR_CORE_SHIFT 1
1354#define OMAP54XX_SMPS_RA_ERR_CORE_WIDTH 0x1
1355#define OMAP54XX_SMPS_RA_ERR_CORE_MASK (1 << 1)
1356
1357/* Used by PRM_VC_MM_ERRST */
1358#define OMAP54XX_SMPS_RA_ERR_MM_SHIFT 1
1359#define OMAP54XX_SMPS_RA_ERR_MM_WIDTH 0x1
1360#define OMAP54XX_SMPS_RA_ERR_MM_MASK (1 << 1)
1361
1362/* Used by PRM_VC_MPU_ERRST */
1363#define OMAP54XX_SMPS_RA_ERR_MPU_SHIFT 1
1364#define OMAP54XX_SMPS_RA_ERR_MPU_WIDTH 0x1
1365#define OMAP54XX_SMPS_RA_ERR_MPU_MASK (1 << 1)
1366
1367/* Used by PRM_VC_CORE_ERRST */
1368#define OMAP54XX_SMPS_SA_ERR_CORE_SHIFT 0
1369#define OMAP54XX_SMPS_SA_ERR_CORE_WIDTH 0x1
1370#define OMAP54XX_SMPS_SA_ERR_CORE_MASK (1 << 0)
1371
1372/* Used by PRM_VC_MM_ERRST */
1373#define OMAP54XX_SMPS_SA_ERR_MM_SHIFT 0
1374#define OMAP54XX_SMPS_SA_ERR_MM_WIDTH 0x1
1375#define OMAP54XX_SMPS_SA_ERR_MM_MASK (1 << 0)
1376
1377/* Used by PRM_VC_MPU_ERRST */
1378#define OMAP54XX_SMPS_SA_ERR_MPU_SHIFT 0
1379#define OMAP54XX_SMPS_SA_ERR_MPU_WIDTH 0x1
1380#define OMAP54XX_SMPS_SA_ERR_MPU_MASK (1 << 0)
1381
1382/* Used by PRM_VC_CORE_ERRST */
1383#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_SHIFT 2
1384#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_WIDTH 0x1
1385#define OMAP54XX_SMPS_TIMEOUT_ERR_CORE_MASK (1 << 2)
1386
1387/* Used by PRM_VC_MM_ERRST */
1388#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_SHIFT 2
1389#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_WIDTH 0x1
1390#define OMAP54XX_SMPS_TIMEOUT_ERR_MM_MASK (1 << 2)
1391
1392/* Used by PRM_VC_MPU_ERRST */
1393#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_SHIFT 2
1394#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_WIDTH 0x1
1395#define OMAP54XX_SMPS_TIMEOUT_ERR_MPU_MASK (1 << 2)
1396
1397/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1398#define OMAP54XX_SR2EN_SHIFT 0
1399#define OMAP54XX_SR2EN_WIDTH 0x1
1400#define OMAP54XX_SR2EN_MASK (1 << 0)
1401
1402/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1403#define OMAP54XX_SR2_IN_TRANSITION_SHIFT 6
1404#define OMAP54XX_SR2_IN_TRANSITION_WIDTH 0x1
1405#define OMAP54XX_SR2_IN_TRANSITION_MASK (1 << 6)
1406
1407/* Used by PRM_ABBLDO_MM_CTRL, PRM_ABBLDO_MPU_CTRL */
1408#define OMAP54XX_SR2_STATUS_SHIFT 3
1409#define OMAP54XX_SR2_STATUS_WIDTH 0x2
1410#define OMAP54XX_SR2_STATUS_MASK (0x3 << 3)
1411
1412/* Used by PRM_ABBLDO_MM_SETUP, PRM_ABBLDO_MPU_SETUP */
1413#define OMAP54XX_SR2_WTCNT_VALUE_SHIFT 8
1414#define OMAP54XX_SR2_WTCNT_VALUE_WIDTH 0x8
1415#define OMAP54XX_SR2_WTCNT_VALUE_MASK (0xff << 8)
1416
1417/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1418#define OMAP54XX_SRAMLDO_STATUS_SHIFT 8
1419#define OMAP54XX_SRAMLDO_STATUS_WIDTH 0x1
1420#define OMAP54XX_SRAMLDO_STATUS_MASK (1 << 8)
1421
1422/* Used by PRM_SLDO_CORE_CTRL, PRM_SLDO_MM_CTRL, PRM_SLDO_MPU_CTRL */
1423#define OMAP54XX_SRAM_IN_TRANSITION_SHIFT 9
1424#define OMAP54XX_SRAM_IN_TRANSITION_WIDTH 0x1
1425#define OMAP54XX_SRAM_IN_TRANSITION_MASK (1 << 9)
1426
1427/* Used by PRM_VC_CFG_I2C_MODE */
1428#define OMAP54XX_SRMODEEN_SHIFT 4
1429#define OMAP54XX_SRMODEEN_WIDTH 0x1
1430#define OMAP54XX_SRMODEEN_MASK (1 << 4)
1431
1432/* Used by PRM_VOLTSETUP_WARMRESET */
1433#define OMAP54XX_STABLE_COUNT_SHIFT 0
1434#define OMAP54XX_STABLE_COUNT_WIDTH 0x6
1435#define OMAP54XX_STABLE_COUNT_MASK (0x3f << 0)
1436
1437/* Used by PRM_VOLTSETUP_WARMRESET */
1438#define OMAP54XX_STABLE_PRESCAL_SHIFT 8
1439#define OMAP54XX_STABLE_PRESCAL_WIDTH 0x2
1440#define OMAP54XX_STABLE_PRESCAL_MASK (0x3 << 8)
1441
1442/* Used by PRM_BANDGAP_SETUP */
1443#define OMAP54XX_STARTUP_COUNT_SHIFT 0
1444#define OMAP54XX_STARTUP_COUNT_WIDTH 0x8
1445#define OMAP54XX_STARTUP_COUNT_MASK (0xff << 0)
1446
1447/* Renamed from STARTUP_COUNT Used by PRM_SRAM_COUNT */
1448#define OMAP54XX_STARTUP_COUNT_24_31_SHIFT 24
1449#define OMAP54XX_STARTUP_COUNT_24_31_WIDTH 0x8
1450#define OMAP54XX_STARTUP_COUNT_24_31_MASK (0xff << 24)
1451
1452/* Used by PM_IVA_PWRSTCTRL */
1453#define OMAP54XX_TCM1_MEM_ONSTATE_SHIFT 20
1454#define OMAP54XX_TCM1_MEM_ONSTATE_WIDTH 0x2
1455#define OMAP54XX_TCM1_MEM_ONSTATE_MASK (0x3 << 20)
1456
1457/* Used by PM_IVA_PWRSTCTRL */
1458#define OMAP54XX_TCM1_MEM_RETSTATE_SHIFT 10
1459#define OMAP54XX_TCM1_MEM_RETSTATE_WIDTH 0x1
1460#define OMAP54XX_TCM1_MEM_RETSTATE_MASK (1 << 10)
1461
1462/* Used by PM_IVA_PWRSTST */
1463#define OMAP54XX_TCM1_MEM_STATEST_SHIFT 8
1464#define OMAP54XX_TCM1_MEM_STATEST_WIDTH 0x2
1465#define OMAP54XX_TCM1_MEM_STATEST_MASK (0x3 << 8)
1466
1467/* Used by PM_IVA_PWRSTCTRL */
1468#define OMAP54XX_TCM2_MEM_ONSTATE_SHIFT 22
1469#define OMAP54XX_TCM2_MEM_ONSTATE_WIDTH 0x2
1470#define OMAP54XX_TCM2_MEM_ONSTATE_MASK (0x3 << 22)
1471
1472/* Used by PM_IVA_PWRSTCTRL */
1473#define OMAP54XX_TCM2_MEM_RETSTATE_SHIFT 11
1474#define OMAP54XX_TCM2_MEM_RETSTATE_WIDTH 0x1
1475#define OMAP54XX_TCM2_MEM_RETSTATE_MASK (1 << 11)
1476
1477/* Used by PM_IVA_PWRSTST */
1478#define OMAP54XX_TCM2_MEM_STATEST_SHIFT 10
1479#define OMAP54XX_TCM2_MEM_STATEST_WIDTH 0x2
1480#define OMAP54XX_TCM2_MEM_STATEST_MASK (0x3 << 10)
1481
1482/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1483#define OMAP54XX_TIMEOUT_SHIFT 0
1484#define OMAP54XX_TIMEOUT_WIDTH 0x10
1485#define OMAP54XX_TIMEOUT_MASK (0xffff << 0)
1486
1487/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1488#define OMAP54XX_TIMEOUTEN_SHIFT 3
1489#define OMAP54XX_TIMEOUTEN_WIDTH 0x1
1490#define OMAP54XX_TIMEOUTEN_MASK (1 << 3)
1491
1492/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1493#define OMAP54XX_TRANSITION_EN_SHIFT 8
1494#define OMAP54XX_TRANSITION_EN_WIDTH 0x1
1495#define OMAP54XX_TRANSITION_EN_MASK (1 << 8)
1496
1497/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1498#define OMAP54XX_TRANSITION_ST_SHIFT 8
1499#define OMAP54XX_TRANSITION_ST_WIDTH 0x1
1500#define OMAP54XX_TRANSITION_ST_MASK (1 << 8)
1501
1502/* Used by PRM_DEBUG_TRANS_CFG */
1503#define OMAP54XX_TRIGGER_CLEAR_SHIFT 2
1504#define OMAP54XX_TRIGGER_CLEAR_WIDTH 0x1
1505#define OMAP54XX_TRIGGER_CLEAR_MASK (1 << 2)
1506
1507/* Used by PRM_RSTST */
1508#define OMAP54XX_TSHUT_CORE_RST_SHIFT 13
1509#define OMAP54XX_TSHUT_CORE_RST_WIDTH 0x1
1510#define OMAP54XX_TSHUT_CORE_RST_MASK (1 << 13)
1511
1512/* Used by PRM_RSTST */
1513#define OMAP54XX_TSHUT_MM_RST_SHIFT 12
1514#define OMAP54XX_TSHUT_MM_RST_WIDTH 0x1
1515#define OMAP54XX_TSHUT_MM_RST_MASK (1 << 12)
1516
1517/* Used by PRM_RSTST */
1518#define OMAP54XX_TSHUT_MPU_RST_SHIFT 11
1519#define OMAP54XX_TSHUT_MPU_RST_WIDTH 0x1
1520#define OMAP54XX_TSHUT_MPU_RST_MASK (1 << 11)
1521
1522/* Used by PRM_VC_VAL_BYPASS */
1523#define OMAP54XX_VALID_SHIFT 24
1524#define OMAP54XX_VALID_WIDTH 0x1
1525#define OMAP54XX_VALID_MASK (1 << 24)
1526
1527/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1528#define OMAP54XX_VC_BYPASSACK_EN_SHIFT 14
1529#define OMAP54XX_VC_BYPASSACK_EN_WIDTH 0x1
1530#define OMAP54XX_VC_BYPASSACK_EN_MASK (1 << 14)
1531
1532/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1533#define OMAP54XX_VC_BYPASSACK_ST_SHIFT 14
1534#define OMAP54XX_VC_BYPASSACK_ST_WIDTH 0x1
1535#define OMAP54XX_VC_BYPASSACK_ST_MASK (1 << 14)
1536
1537/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1538#define OMAP54XX_VC_CORE_VPACK_EN_SHIFT 22
1539#define OMAP54XX_VC_CORE_VPACK_EN_WIDTH 0x1
1540#define OMAP54XX_VC_CORE_VPACK_EN_MASK (1 << 22)
1541
1542/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1543#define OMAP54XX_VC_CORE_VPACK_ST_SHIFT 22
1544#define OMAP54XX_VC_CORE_VPACK_ST_WIDTH 0x1
1545#define OMAP54XX_VC_CORE_VPACK_ST_MASK (1 << 22)
1546
1547/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1548#define OMAP54XX_VC_MM_VPACK_EN_SHIFT 30
1549#define OMAP54XX_VC_MM_VPACK_EN_WIDTH 0x1
1550#define OMAP54XX_VC_MM_VPACK_EN_MASK (1 << 30)
1551
1552/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1553#define OMAP54XX_VC_MM_VPACK_ST_SHIFT 30
1554#define OMAP54XX_VC_MM_VPACK_ST_WIDTH 0x1
1555#define OMAP54XX_VC_MM_VPACK_ST_MASK (1 << 30)
1556
1557/* Used by PRM_IRQENABLE_MPU_2 */
1558#define OMAP54XX_VC_MPU_VPACK_EN_SHIFT 6
1559#define OMAP54XX_VC_MPU_VPACK_EN_WIDTH 0x1
1560#define OMAP54XX_VC_MPU_VPACK_EN_MASK (1 << 6)
1561
1562/* Used by PRM_IRQSTATUS_MPU_2 */
1563#define OMAP54XX_VC_MPU_VPACK_ST_SHIFT 6
1564#define OMAP54XX_VC_MPU_VPACK_ST_WIDTH 0x1
1565#define OMAP54XX_VC_MPU_VPACK_ST_MASK (1 << 6)
1566
1567/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1568#define OMAP54XX_VC_RAERR_EN_SHIFT 12
1569#define OMAP54XX_VC_RAERR_EN_WIDTH 0x1
1570#define OMAP54XX_VC_RAERR_EN_MASK (1 << 12)
1571
1572/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1573#define OMAP54XX_VC_RAERR_ST_SHIFT 12
1574#define OMAP54XX_VC_RAERR_ST_WIDTH 0x1
1575#define OMAP54XX_VC_RAERR_ST_MASK (1 << 12)
1576
1577/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1578#define OMAP54XX_VC_SAERR_EN_SHIFT 11
1579#define OMAP54XX_VC_SAERR_EN_WIDTH 0x1
1580#define OMAP54XX_VC_SAERR_EN_MASK (1 << 11)
1581
1582/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1583#define OMAP54XX_VC_SAERR_ST_SHIFT 11
1584#define OMAP54XX_VC_SAERR_ST_WIDTH 0x1
1585#define OMAP54XX_VC_SAERR_ST_MASK (1 << 11)
1586
1587/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1588#define OMAP54XX_VC_TOERR_EN_SHIFT 13
1589#define OMAP54XX_VC_TOERR_EN_WIDTH 0x1
1590#define OMAP54XX_VC_TOERR_EN_MASK (1 << 13)
1591
1592/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1593#define OMAP54XX_VC_TOERR_ST_SHIFT 13
1594#define OMAP54XX_VC_TOERR_ST_WIDTH 0x1
1595#define OMAP54XX_VC_TOERR_ST_MASK (1 << 13)
1596
1597/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1598#define OMAP54XX_VDDMAX_SHIFT 24
1599#define OMAP54XX_VDDMAX_WIDTH 0x8
1600#define OMAP54XX_VDDMAX_MASK (0xff << 24)
1601
1602/* Used by PRM_VP_CORE_VLIMITTO, PRM_VP_MM_VLIMITTO, PRM_VP_MPU_VLIMITTO */
1603#define OMAP54XX_VDDMIN_SHIFT 16
1604#define OMAP54XX_VDDMIN_WIDTH 0x8
1605#define OMAP54XX_VDDMIN_MASK (0xff << 16)
1606
1607/* Used by PRM_VOLTCTRL */
1608#define OMAP54XX_VDD_CORE_I2C_DISABLE_SHIFT 12
1609#define OMAP54XX_VDD_CORE_I2C_DISABLE_WIDTH 0x1
1610#define OMAP54XX_VDD_CORE_I2C_DISABLE_MASK (1 << 12)
1611
1612/* Used by PRM_RSTST */
1613#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_SHIFT 8
1614#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_WIDTH 0x1
1615#define OMAP54XX_VDD_CORE_VOLT_MGR_RST_MASK (1 << 8)
1616
1617/* Used by PRM_VOLTCTRL */
1618#define OMAP54XX_VDD_MM_I2C_DISABLE_SHIFT 14
1619#define OMAP54XX_VDD_MM_I2C_DISABLE_WIDTH 0x1
1620#define OMAP54XX_VDD_MM_I2C_DISABLE_MASK (1 << 14)
1621
1622/* Used by PRM_VOLTCTRL */
1623#define OMAP54XX_VDD_MM_PRESENCE_SHIFT 9
1624#define OMAP54XX_VDD_MM_PRESENCE_WIDTH 0x1
1625#define OMAP54XX_VDD_MM_PRESENCE_MASK (1 << 9)
1626
1627/* Used by PRM_RSTST */
1628#define OMAP54XX_VDD_MM_VOLT_MGR_RST_SHIFT 7
1629#define OMAP54XX_VDD_MM_VOLT_MGR_RST_WIDTH 0x1
1630#define OMAP54XX_VDD_MM_VOLT_MGR_RST_MASK (1 << 7)
1631
1632/* Used by PRM_VOLTCTRL */
1633#define OMAP54XX_VDD_MPU_I2C_DISABLE_SHIFT 13
1634#define OMAP54XX_VDD_MPU_I2C_DISABLE_WIDTH 0x1
1635#define OMAP54XX_VDD_MPU_I2C_DISABLE_MASK (1 << 13)
1636
1637/* Used by PRM_VOLTCTRL */
1638#define OMAP54XX_VDD_MPU_PRESENCE_SHIFT 8
1639#define OMAP54XX_VDD_MPU_PRESENCE_WIDTH 0x1
1640#define OMAP54XX_VDD_MPU_PRESENCE_MASK (1 << 8)
1641
1642/* Used by PRM_RSTST */
1643#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_SHIFT 6
1644#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_WIDTH 0x1
1645#define OMAP54XX_VDD_MPU_VOLT_MGR_RST_MASK (1 << 6)
1646
1647/* Used by PRM_VC_CORE_ERRST */
1648#define OMAP54XX_VFSM_RA_ERR_CORE_SHIFT 4
1649#define OMAP54XX_VFSM_RA_ERR_CORE_WIDTH 0x1
1650#define OMAP54XX_VFSM_RA_ERR_CORE_MASK (1 << 4)
1651
1652/* Used by PRM_VC_MM_ERRST */
1653#define OMAP54XX_VFSM_RA_ERR_MM_SHIFT 4
1654#define OMAP54XX_VFSM_RA_ERR_MM_WIDTH 0x1
1655#define OMAP54XX_VFSM_RA_ERR_MM_MASK (1 << 4)
1656
1657/* Used by PRM_VC_MPU_ERRST */
1658#define OMAP54XX_VFSM_RA_ERR_MPU_SHIFT 4
1659#define OMAP54XX_VFSM_RA_ERR_MPU_WIDTH 0x1
1660#define OMAP54XX_VFSM_RA_ERR_MPU_MASK (1 << 4)
1661
1662/* Used by PRM_VC_CORE_ERRST */
1663#define OMAP54XX_VFSM_SA_ERR_CORE_SHIFT 3
1664#define OMAP54XX_VFSM_SA_ERR_CORE_WIDTH 0x1
1665#define OMAP54XX_VFSM_SA_ERR_CORE_MASK (1 << 3)
1666
1667/* Used by PRM_VC_MM_ERRST */
1668#define OMAP54XX_VFSM_SA_ERR_MM_SHIFT 3
1669#define OMAP54XX_VFSM_SA_ERR_MM_WIDTH 0x1
1670#define OMAP54XX_VFSM_SA_ERR_MM_MASK (1 << 3)
1671
1672/* Used by PRM_VC_MPU_ERRST */
1673#define OMAP54XX_VFSM_SA_ERR_MPU_SHIFT 3
1674#define OMAP54XX_VFSM_SA_ERR_MPU_WIDTH 0x1
1675#define OMAP54XX_VFSM_SA_ERR_MPU_MASK (1 << 3)
1676
1677/* Used by PRM_VC_CORE_ERRST */
1678#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_SHIFT 5
1679#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_WIDTH 0x1
1680#define OMAP54XX_VFSM_TIMEOUT_ERR_CORE_MASK (1 << 5)
1681
1682/* Used by PRM_VC_MM_ERRST */
1683#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_SHIFT 5
1684#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_WIDTH 0x1
1685#define OMAP54XX_VFSM_TIMEOUT_ERR_MM_MASK (1 << 5)
1686
1687/* Used by PRM_VC_MPU_ERRST */
1688#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_SHIFT 5
1689#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_WIDTH 0x1
1690#define OMAP54XX_VFSM_TIMEOUT_ERR_MPU_MASK (1 << 5)
1691
1692/* Used by PRM_VC_SMPS_CORE_CONFIG */
1693#define OMAP54XX_VOLRA_VDD_CORE_L_SHIFT 8
1694#define OMAP54XX_VOLRA_VDD_CORE_L_WIDTH 0x8
1695#define OMAP54XX_VOLRA_VDD_CORE_L_MASK (0xff << 8)
1696
1697/* Used by PRM_VC_SMPS_MM_CONFIG */
1698#define OMAP54XX_VOLRA_VDD_MM_L_SHIFT 8
1699#define OMAP54XX_VOLRA_VDD_MM_L_WIDTH 0x8
1700#define OMAP54XX_VOLRA_VDD_MM_L_MASK (0xff << 8)
1701
1702/* Used by PRM_VC_SMPS_MPU_CONFIG */
1703#define OMAP54XX_VOLRA_VDD_MPU_L_SHIFT 8
1704#define OMAP54XX_VOLRA_VDD_MPU_L_WIDTH 0x8
1705#define OMAP54XX_VOLRA_VDD_MPU_L_MASK (0xff << 8)
1706
1707/* Used by PRM_VOLTST_MM, PRM_VOLTST_MPU */
1708#define OMAP54XX_VOLTSTATEST_SHIFT 0
1709#define OMAP54XX_VOLTSTATEST_WIDTH 0x2
1710#define OMAP54XX_VOLTSTATEST_MASK (0x3 << 0)
1711
1712/* Used by PRM_VP_CORE_CONFIG, PRM_VP_MM_CONFIG, PRM_VP_MPU_CONFIG */
1713#define OMAP54XX_VPENABLE_SHIFT 0
1714#define OMAP54XX_VPENABLE_WIDTH 0x1
1715#define OMAP54XX_VPENABLE_MASK (1 << 0)
1716
1717/* Used by PRM_VP_CORE_STATUS, PRM_VP_MM_STATUS, PRM_VP_MPU_STATUS */
1718#define OMAP54XX_VPINIDLE_SHIFT 0
1719#define OMAP54XX_VPINIDLE_WIDTH 0x1
1720#define OMAP54XX_VPINIDLE_MASK (1 << 0)
1721
1722/* Used by PRM_VP_CORE_VOLTAGE, PRM_VP_MM_VOLTAGE, PRM_VP_MPU_VOLTAGE */
1723#define OMAP54XX_VPVOLTAGE_SHIFT 0
1724#define OMAP54XX_VPVOLTAGE_WIDTH 0x8
1725#define OMAP54XX_VPVOLTAGE_MASK (0xff << 0)
1726
1727/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1728#define OMAP54XX_VP_CORE_EQVALUE_EN_SHIFT 20
1729#define OMAP54XX_VP_CORE_EQVALUE_EN_WIDTH 0x1
1730#define OMAP54XX_VP_CORE_EQVALUE_EN_MASK (1 << 20)
1731
1732/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1733#define OMAP54XX_VP_CORE_EQVALUE_ST_SHIFT 20
1734#define OMAP54XX_VP_CORE_EQVALUE_ST_WIDTH 0x1
1735#define OMAP54XX_VP_CORE_EQVALUE_ST_MASK (1 << 20)
1736
1737/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1738#define OMAP54XX_VP_CORE_MAXVDD_EN_SHIFT 18
1739#define OMAP54XX_VP_CORE_MAXVDD_EN_WIDTH 0x1
1740#define OMAP54XX_VP_CORE_MAXVDD_EN_MASK (1 << 18)
1741
1742/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1743#define OMAP54XX_VP_CORE_MAXVDD_ST_SHIFT 18
1744#define OMAP54XX_VP_CORE_MAXVDD_ST_WIDTH 0x1
1745#define OMAP54XX_VP_CORE_MAXVDD_ST_MASK (1 << 18)
1746
1747/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1748#define OMAP54XX_VP_CORE_MINVDD_EN_SHIFT 17
1749#define OMAP54XX_VP_CORE_MINVDD_EN_WIDTH 0x1
1750#define OMAP54XX_VP_CORE_MINVDD_EN_MASK (1 << 17)
1751
1752/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1753#define OMAP54XX_VP_CORE_MINVDD_ST_SHIFT 17
1754#define OMAP54XX_VP_CORE_MINVDD_ST_WIDTH 0x1
1755#define OMAP54XX_VP_CORE_MINVDD_ST_MASK (1 << 17)
1756
1757/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1758#define OMAP54XX_VP_CORE_NOSMPSACK_EN_SHIFT 19
1759#define OMAP54XX_VP_CORE_NOSMPSACK_EN_WIDTH 0x1
1760#define OMAP54XX_VP_CORE_NOSMPSACK_EN_MASK (1 << 19)
1761
1762/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1763#define OMAP54XX_VP_CORE_NOSMPSACK_ST_SHIFT 19
1764#define OMAP54XX_VP_CORE_NOSMPSACK_ST_WIDTH 0x1
1765#define OMAP54XX_VP_CORE_NOSMPSACK_ST_MASK (1 << 19)
1766
1767/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1768#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_SHIFT 16
1769#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_WIDTH 0x1
1770#define OMAP54XX_VP_CORE_OPPCHANGEDONE_EN_MASK (1 << 16)
1771
1772/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1773#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_SHIFT 16
1774#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_WIDTH 0x1
1775#define OMAP54XX_VP_CORE_OPPCHANGEDONE_ST_MASK (1 << 16)
1776
1777/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1778#define OMAP54XX_VP_CORE_TRANXDONE_EN_SHIFT 21
1779#define OMAP54XX_VP_CORE_TRANXDONE_EN_WIDTH 0x1
1780#define OMAP54XX_VP_CORE_TRANXDONE_EN_MASK (1 << 21)
1781
1782/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1783#define OMAP54XX_VP_CORE_TRANXDONE_ST_SHIFT 21
1784#define OMAP54XX_VP_CORE_TRANXDONE_ST_WIDTH 0x1
1785#define OMAP54XX_VP_CORE_TRANXDONE_ST_MASK (1 << 21)
1786
1787/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1788#define OMAP54XX_VP_MM_EQVALUE_EN_SHIFT 28
1789#define OMAP54XX_VP_MM_EQVALUE_EN_WIDTH 0x1
1790#define OMAP54XX_VP_MM_EQVALUE_EN_MASK (1 << 28)
1791
1792/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1793#define OMAP54XX_VP_MM_EQVALUE_ST_SHIFT 28
1794#define OMAP54XX_VP_MM_EQVALUE_ST_WIDTH 0x1
1795#define OMAP54XX_VP_MM_EQVALUE_ST_MASK (1 << 28)
1796
1797/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1798#define OMAP54XX_VP_MM_MAXVDD_EN_SHIFT 26
1799#define OMAP54XX_VP_MM_MAXVDD_EN_WIDTH 0x1
1800#define OMAP54XX_VP_MM_MAXVDD_EN_MASK (1 << 26)
1801
1802/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1803#define OMAP54XX_VP_MM_MAXVDD_ST_SHIFT 26
1804#define OMAP54XX_VP_MM_MAXVDD_ST_WIDTH 0x1
1805#define OMAP54XX_VP_MM_MAXVDD_ST_MASK (1 << 26)
1806
1807/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1808#define OMAP54XX_VP_MM_MINVDD_EN_SHIFT 25
1809#define OMAP54XX_VP_MM_MINVDD_EN_WIDTH 0x1
1810#define OMAP54XX_VP_MM_MINVDD_EN_MASK (1 << 25)
1811
1812/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1813#define OMAP54XX_VP_MM_MINVDD_ST_SHIFT 25
1814#define OMAP54XX_VP_MM_MINVDD_ST_WIDTH 0x1
1815#define OMAP54XX_VP_MM_MINVDD_ST_MASK (1 << 25)
1816
1817/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1818#define OMAP54XX_VP_MM_NOSMPSACK_EN_SHIFT 27
1819#define OMAP54XX_VP_MM_NOSMPSACK_EN_WIDTH 0x1
1820#define OMAP54XX_VP_MM_NOSMPSACK_EN_MASK (1 << 27)
1821
1822/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1823#define OMAP54XX_VP_MM_NOSMPSACK_ST_SHIFT 27
1824#define OMAP54XX_VP_MM_NOSMPSACK_ST_WIDTH 0x1
1825#define OMAP54XX_VP_MM_NOSMPSACK_ST_MASK (1 << 27)
1826
1827/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1828#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_SHIFT 24
1829#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_WIDTH 0x1
1830#define OMAP54XX_VP_MM_OPPCHANGEDONE_EN_MASK (1 << 24)
1831
1832/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1833#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_SHIFT 24
1834#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_WIDTH 0x1
1835#define OMAP54XX_VP_MM_OPPCHANGEDONE_ST_MASK (1 << 24)
1836
1837/* Used by PRM_IRQENABLE_IPU, PRM_IRQENABLE_MPU */
1838#define OMAP54XX_VP_MM_TRANXDONE_EN_SHIFT 29
1839#define OMAP54XX_VP_MM_TRANXDONE_EN_WIDTH 0x1
1840#define OMAP54XX_VP_MM_TRANXDONE_EN_MASK (1 << 29)
1841
1842/* Used by PRM_IRQSTATUS_IPU, PRM_IRQSTATUS_MPU */
1843#define OMAP54XX_VP_MM_TRANXDONE_ST_SHIFT 29
1844#define OMAP54XX_VP_MM_TRANXDONE_ST_WIDTH 0x1
1845#define OMAP54XX_VP_MM_TRANXDONE_ST_MASK (1 << 29)
1846
1847/* Used by PRM_IRQENABLE_MPU_2 */
1848#define OMAP54XX_VP_MPU_EQVALUE_EN_SHIFT 4
1849#define OMAP54XX_VP_MPU_EQVALUE_EN_WIDTH 0x1
1850#define OMAP54XX_VP_MPU_EQVALUE_EN_MASK (1 << 4)
1851
1852/* Used by PRM_IRQSTATUS_MPU_2 */
1853#define OMAP54XX_VP_MPU_EQVALUE_ST_SHIFT 4
1854#define OMAP54XX_VP_MPU_EQVALUE_ST_WIDTH 0x1
1855#define OMAP54XX_VP_MPU_EQVALUE_ST_MASK (1 << 4)
1856
1857/* Used by PRM_IRQENABLE_MPU_2 */
1858#define OMAP54XX_VP_MPU_MAXVDD_EN_SHIFT 2
1859#define OMAP54XX_VP_MPU_MAXVDD_EN_WIDTH 0x1
1860#define OMAP54XX_VP_MPU_MAXVDD_EN_MASK (1 << 2)
1861
1862/* Used by PRM_IRQSTATUS_MPU_2 */
1863#define OMAP54XX_VP_MPU_MAXVDD_ST_SHIFT 2
1864#define OMAP54XX_VP_MPU_MAXVDD_ST_WIDTH 0x1
1865#define OMAP54XX_VP_MPU_MAXVDD_ST_MASK (1 << 2)
1866
1867/* Used by PRM_IRQENABLE_MPU_2 */
1868#define OMAP54XX_VP_MPU_MINVDD_EN_SHIFT 1
1869#define OMAP54XX_VP_MPU_MINVDD_EN_WIDTH 0x1
1870#define OMAP54XX_VP_MPU_MINVDD_EN_MASK (1 << 1)
1871
1872/* Used by PRM_IRQSTATUS_MPU_2 */
1873#define OMAP54XX_VP_MPU_MINVDD_ST_SHIFT 1
1874#define OMAP54XX_VP_MPU_MINVDD_ST_WIDTH 0x1
1875#define OMAP54XX_VP_MPU_MINVDD_ST_MASK (1 << 1)
1876
1877/* Used by PRM_IRQENABLE_MPU_2 */
1878#define OMAP54XX_VP_MPU_NOSMPSACK_EN_SHIFT 3
1879#define OMAP54XX_VP_MPU_NOSMPSACK_EN_WIDTH 0x1
1880#define OMAP54XX_VP_MPU_NOSMPSACK_EN_MASK (1 << 3)
1881
1882/* Used by PRM_IRQSTATUS_MPU_2 */
1883#define OMAP54XX_VP_MPU_NOSMPSACK_ST_SHIFT 3
1884#define OMAP54XX_VP_MPU_NOSMPSACK_ST_WIDTH 0x1
1885#define OMAP54XX_VP_MPU_NOSMPSACK_ST_MASK (1 << 3)
1886
1887/* Used by PRM_IRQENABLE_MPU_2 */
1888#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_SHIFT 0
1889#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_WIDTH 0x1
1890#define OMAP54XX_VP_MPU_OPPCHANGEDONE_EN_MASK (1 << 0)
1891
1892/* Used by PRM_IRQSTATUS_MPU_2 */
1893#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_SHIFT 0
1894#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_WIDTH 0x1
1895#define OMAP54XX_VP_MPU_OPPCHANGEDONE_ST_MASK (1 << 0)
1896
1897/* Used by PRM_IRQENABLE_MPU_2 */
1898#define OMAP54XX_VP_MPU_TRANXDONE_EN_SHIFT 5
1899#define OMAP54XX_VP_MPU_TRANXDONE_EN_WIDTH 0x1
1900#define OMAP54XX_VP_MPU_TRANXDONE_EN_MASK (1 << 5)
1901
1902/* Used by PRM_IRQSTATUS_MPU_2 */
1903#define OMAP54XX_VP_MPU_TRANXDONE_ST_SHIFT 5
1904#define OMAP54XX_VP_MPU_TRANXDONE_ST_WIDTH 0x1
1905#define OMAP54XX_VP_MPU_TRANXDONE_ST_MASK (1 << 5)
1906
1907/* Used by PRM_SRAM_COUNT */
1908#define OMAP54XX_VSETUPCNT_VALUE_SHIFT 8
1909#define OMAP54XX_VSETUPCNT_VALUE_WIDTH 0x8
1910#define OMAP54XX_VSETUPCNT_VALUE_MASK (0xff << 8)
1911
1912/* Used by PRM_VP_CORE_VSTEPMAX, PRM_VP_MM_VSTEPMAX, PRM_VP_MPU_VSTEPMAX */
1913#define OMAP54XX_VSTEPMAX_SHIFT 0
1914#define OMAP54XX_VSTEPMAX_WIDTH 0x8
1915#define OMAP54XX_VSTEPMAX_MASK (0xff << 0)
1916
1917/* Used by PRM_VP_CORE_VSTEPMIN, PRM_VP_MM_VSTEPMIN, PRM_VP_MPU_VSTEPMIN */
1918#define OMAP54XX_VSTEPMIN_SHIFT 0
1919#define OMAP54XX_VSTEPMIN_WIDTH 0x8
1920#define OMAP54XX_VSTEPMIN_MASK (0xff << 0)
1921
1922/* Used by PM_DSS_DSS_WKDEP */
1923#define OMAP54XX_WKUPDEP_DISPC_DSP_SHIFT 2
1924#define OMAP54XX_WKUPDEP_DISPC_DSP_WIDTH 0x1
1925#define OMAP54XX_WKUPDEP_DISPC_DSP_MASK (1 << 2)
1926
1927/* Used by PM_DSS_DSS_WKDEP */
1928#define OMAP54XX_WKUPDEP_DISPC_IPU_SHIFT 1
1929#define OMAP54XX_WKUPDEP_DISPC_IPU_WIDTH 0x1
1930#define OMAP54XX_WKUPDEP_DISPC_IPU_MASK (1 << 1)
1931
1932/* Used by PM_DSS_DSS_WKDEP */
1933#define OMAP54XX_WKUPDEP_DISPC_MPU_SHIFT 0
1934#define OMAP54XX_WKUPDEP_DISPC_MPU_WIDTH 0x1
1935#define OMAP54XX_WKUPDEP_DISPC_MPU_MASK (1 << 0)
1936
1937/* Used by PM_DSS_DSS_WKDEP */
1938#define OMAP54XX_WKUPDEP_DISPC_SDMA_SHIFT 3
1939#define OMAP54XX_WKUPDEP_DISPC_SDMA_WIDTH 0x1
1940#define OMAP54XX_WKUPDEP_DISPC_SDMA_MASK (1 << 3)
1941
1942/* Used by PM_ABE_DMIC_WKDEP */
1943#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_SHIFT 6
1944#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_WIDTH 0x1
1945#define OMAP54XX_WKUPDEP_DMIC_DMA_DSP_MASK (1 << 6)
1946
1947/* Used by PM_ABE_DMIC_WKDEP */
1948#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_SHIFT 7
1949#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_WIDTH 0x1
1950#define OMAP54XX_WKUPDEP_DMIC_DMA_SDMA_MASK (1 << 7)
1951
1952/* Used by PM_ABE_DMIC_WKDEP */
1953#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_SHIFT 2
1954#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_WIDTH 0x1
1955#define OMAP54XX_WKUPDEP_DMIC_IRQ_DSP_MASK (1 << 2)
1956
1957/* Used by PM_ABE_DMIC_WKDEP */
1958#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_SHIFT 0
1959#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_WIDTH 0x1
1960#define OMAP54XX_WKUPDEP_DMIC_IRQ_MPU_MASK (1 << 0)
1961
1962/* Used by PM_DSS_DSS_WKDEP */
1963#define OMAP54XX_WKUPDEP_DSI1_A_DSP_SHIFT 6
1964#define OMAP54XX_WKUPDEP_DSI1_A_DSP_WIDTH 0x1
1965#define OMAP54XX_WKUPDEP_DSI1_A_DSP_MASK (1 << 6)
1966
1967/* Used by PM_DSS_DSS_WKDEP */
1968#define OMAP54XX_WKUPDEP_DSI1_A_IPU_SHIFT 5
1969#define OMAP54XX_WKUPDEP_DSI1_A_IPU_WIDTH 0x1
1970#define OMAP54XX_WKUPDEP_DSI1_A_IPU_MASK (1 << 5)
1971
1972/* Used by PM_DSS_DSS_WKDEP */
1973#define OMAP54XX_WKUPDEP_DSI1_A_MPU_SHIFT 4
1974#define OMAP54XX_WKUPDEP_DSI1_A_MPU_WIDTH 0x1
1975#define OMAP54XX_WKUPDEP_DSI1_A_MPU_MASK (1 << 4)
1976
1977/* Used by PM_DSS_DSS_WKDEP */
1978#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_SHIFT 7
1979#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_WIDTH 0x1
1980#define OMAP54XX_WKUPDEP_DSI1_A_SDMA_MASK (1 << 7)
1981
1982/* Used by PM_DSS_DSS_WKDEP */
1983#define OMAP54XX_WKUPDEP_DSI1_B_DSP_SHIFT 10
1984#define OMAP54XX_WKUPDEP_DSI1_B_DSP_WIDTH 0x1
1985#define OMAP54XX_WKUPDEP_DSI1_B_DSP_MASK (1 << 10)
1986
1987/* Used by PM_DSS_DSS_WKDEP */
1988#define OMAP54XX_WKUPDEP_DSI1_B_IPU_SHIFT 9
1989#define OMAP54XX_WKUPDEP_DSI1_B_IPU_WIDTH 0x1
1990#define OMAP54XX_WKUPDEP_DSI1_B_IPU_MASK (1 << 9)
1991
1992/* Used by PM_DSS_DSS_WKDEP */
1993#define OMAP54XX_WKUPDEP_DSI1_B_MPU_SHIFT 8
1994#define OMAP54XX_WKUPDEP_DSI1_B_MPU_WIDTH 0x1
1995#define OMAP54XX_WKUPDEP_DSI1_B_MPU_MASK (1 << 8)
1996
1997/* Used by PM_DSS_DSS_WKDEP */
1998#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_SHIFT 11
1999#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_WIDTH 0x1
2000#define OMAP54XX_WKUPDEP_DSI1_B_SDMA_MASK (1 << 11)
2001
2002/* Used by PM_DSS_DSS_WKDEP */
2003#define OMAP54XX_WKUPDEP_DSI1_C_DSP_SHIFT 17
2004#define OMAP54XX_WKUPDEP_DSI1_C_DSP_WIDTH 0x1
2005#define OMAP54XX_WKUPDEP_DSI1_C_DSP_MASK (1 << 17)
2006
2007/* Used by PM_DSS_DSS_WKDEP */
2008#define OMAP54XX_WKUPDEP_DSI1_C_IPU_SHIFT 16
2009#define OMAP54XX_WKUPDEP_DSI1_C_IPU_WIDTH 0x1
2010#define OMAP54XX_WKUPDEP_DSI1_C_IPU_MASK (1 << 16)
2011
2012/* Used by PM_DSS_DSS_WKDEP */
2013#define OMAP54XX_WKUPDEP_DSI1_C_MPU_SHIFT 15
2014#define OMAP54XX_WKUPDEP_DSI1_C_MPU_WIDTH 0x1
2015#define OMAP54XX_WKUPDEP_DSI1_C_MPU_MASK (1 << 15)
2016
2017/* Used by PM_DSS_DSS_WKDEP */
2018#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_SHIFT 18
2019#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_WIDTH 0x1
2020#define OMAP54XX_WKUPDEP_DSI1_C_SDMA_MASK (1 << 18)
2021
2022/* Used by PM_WKUPAON_GPIO1_WKDEP */
2023#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_SHIFT 1
2024#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_WIDTH 0x1
2025#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_IPU_MASK (1 << 1)
2026
2027/* Used by PM_WKUPAON_GPIO1_WKDEP */
2028#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_SHIFT 0
2029#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_WIDTH 0x1
2030#define OMAP54XX_WKUPDEP_GPIO1_IRQ1_MPU_MASK (1 << 0)
2031
2032/* Used by PM_WKUPAON_GPIO1_WKDEP */
2033#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_SHIFT 6
2034#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_WIDTH 0x1
2035#define OMAP54XX_WKUPDEP_GPIO1_IRQ2_DSP_MASK (1 << 6)
2036
2037/* Used by PM_L4PER_GPIO2_WKDEP */
2038#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_SHIFT 1
2039#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_WIDTH 0x1
2040#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_IPU_MASK (1 << 1)
2041
2042/* Used by PM_L4PER_GPIO2_WKDEP */
2043#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_SHIFT 0
2044#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_WIDTH 0x1
2045#define OMAP54XX_WKUPDEP_GPIO2_IRQ1_MPU_MASK (1 << 0)
2046
2047/* Used by PM_L4PER_GPIO2_WKDEP */
2048#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_SHIFT 6
2049#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_WIDTH 0x1
2050#define OMAP54XX_WKUPDEP_GPIO2_IRQ2_DSP_MASK (1 << 6)
2051
2052/* Used by PM_L4PER_GPIO3_WKDEP */
2053#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_SHIFT 0
2054#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_WIDTH 0x1
2055#define OMAP54XX_WKUPDEP_GPIO3_IRQ1_MPU_MASK (1 << 0)
2056
2057/* Used by PM_L4PER_GPIO3_WKDEP */
2058#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_SHIFT 6
2059#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_WIDTH 0x1
2060#define OMAP54XX_WKUPDEP_GPIO3_IRQ2_DSP_MASK (1 << 6)
2061
2062/* Used by PM_L4PER_GPIO4_WKDEP */
2063#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_SHIFT 0
2064#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_WIDTH 0x1
2065#define OMAP54XX_WKUPDEP_GPIO4_IRQ1_MPU_MASK (1 << 0)
2066
2067/* Used by PM_L4PER_GPIO4_WKDEP */
2068#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_SHIFT 6
2069#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_WIDTH 0x1
2070#define OMAP54XX_WKUPDEP_GPIO4_IRQ2_DSP_MASK (1 << 6)
2071
2072/* Used by PM_L4PER_GPIO5_WKDEP */
2073#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_SHIFT 0
2074#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_WIDTH 0x1
2075#define OMAP54XX_WKUPDEP_GPIO5_IRQ1_MPU_MASK (1 << 0)
2076
2077/* Used by PM_L4PER_GPIO5_WKDEP */
2078#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_SHIFT 6
2079#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_WIDTH 0x1
2080#define OMAP54XX_WKUPDEP_GPIO5_IRQ2_DSP_MASK (1 << 6)
2081
2082/* Used by PM_L4PER_GPIO6_WKDEP */
2083#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_SHIFT 0
2084#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_WIDTH 0x1
2085#define OMAP54XX_WKUPDEP_GPIO6_IRQ1_MPU_MASK (1 << 0)
2086
2087/* Used by PM_L4PER_GPIO6_WKDEP */
2088#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_SHIFT 6
2089#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_WIDTH 0x1
2090#define OMAP54XX_WKUPDEP_GPIO6_IRQ2_DSP_MASK (1 << 6)
2091
2092/* Used by PM_L4PER_GPIO7_WKDEP */
2093#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_SHIFT 0
2094#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_WIDTH 0x1
2095#define OMAP54XX_WKUPDEP_GPIO7_IRQ1_MPU_MASK (1 << 0)
2096
2097/* Used by PM_L4PER_GPIO8_WKDEP */
2098#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_SHIFT 0
2099#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_WIDTH 0x1
2100#define OMAP54XX_WKUPDEP_GPIO8_IRQ1_MPU_MASK (1 << 0)
2101
2102/* Used by PM_DSS_DSS_WKDEP */
2103#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_SHIFT 19
2104#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_WIDTH 0x1
2105#define OMAP54XX_WKUPDEP_HDMIDMA_SDMA_MASK (1 << 19)
2106
2107/* Used by PM_DSS_DSS_WKDEP */
2108#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_SHIFT 14
2109#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_WIDTH 0x1
2110#define OMAP54XX_WKUPDEP_HDMIIRQ_DSP_MASK (1 << 14)
2111
2112/* Used by PM_DSS_DSS_WKDEP */
2113#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_SHIFT 13
2114#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_WIDTH 0x1
2115#define OMAP54XX_WKUPDEP_HDMIIRQ_IPU_MASK (1 << 13)
2116
2117/* Used by PM_DSS_DSS_WKDEP */
2118#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_SHIFT 12
2119#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_WIDTH 0x1
2120#define OMAP54XX_WKUPDEP_HDMIIRQ_MPU_MASK (1 << 12)
2121
2122/* Used by PM_L3INIT_HSI_WKDEP */
2123#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_SHIFT 6
2124#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_WIDTH 0x1
2125#define OMAP54XX_WKUPDEP_HSI_DSP_DSP_MASK (1 << 6)
2126
2127/* Used by PM_L3INIT_HSI_WKDEP */
2128#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_SHIFT 1
2129#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_WIDTH 0x1
2130#define OMAP54XX_WKUPDEP_HSI_MCU_IPU_MASK (1 << 1)
2131
2132/* Used by PM_L3INIT_HSI_WKDEP */
2133#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_SHIFT 0
2134#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_WIDTH 0x1
2135#define OMAP54XX_WKUPDEP_HSI_MCU_MPU_MASK (1 << 0)
2136
2137/* Used by PM_L4PER_I2C1_WKDEP */
2138#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_SHIFT 7
2139#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_WIDTH 0x1
2140#define OMAP54XX_WKUPDEP_I2C1_DMA_SDMA_MASK (1 << 7)
2141
2142/* Used by PM_L4PER_I2C1_WKDEP */
2143#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_SHIFT 1
2144#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_WIDTH 0x1
2145#define OMAP54XX_WKUPDEP_I2C1_IRQ_IPU_MASK (1 << 1)
2146
2147/* Used by PM_L4PER_I2C1_WKDEP */
2148#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_SHIFT 0
2149#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_WIDTH 0x1
2150#define OMAP54XX_WKUPDEP_I2C1_IRQ_MPU_MASK (1 << 0)
2151
2152/* Used by PM_L4PER_I2C2_WKDEP */
2153#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_SHIFT 7
2154#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_WIDTH 0x1
2155#define OMAP54XX_WKUPDEP_I2C2_DMA_SDMA_MASK (1 << 7)
2156
2157/* Used by PM_L4PER_I2C2_WKDEP */
2158#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_SHIFT 1
2159#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_WIDTH 0x1
2160#define OMAP54XX_WKUPDEP_I2C2_IRQ_IPU_MASK (1 << 1)
2161
2162/* Used by PM_L4PER_I2C2_WKDEP */
2163#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_SHIFT 0
2164#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_WIDTH 0x1
2165#define OMAP54XX_WKUPDEP_I2C2_IRQ_MPU_MASK (1 << 0)
2166
2167/* Used by PM_L4PER_I2C3_WKDEP */
2168#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_SHIFT 7
2169#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_WIDTH 0x1
2170#define OMAP54XX_WKUPDEP_I2C3_DMA_SDMA_MASK (1 << 7)
2171
2172/* Used by PM_L4PER_I2C3_WKDEP */
2173#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_SHIFT 1
2174#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_WIDTH 0x1
2175#define OMAP54XX_WKUPDEP_I2C3_IRQ_IPU_MASK (1 << 1)
2176
2177/* Used by PM_L4PER_I2C3_WKDEP */
2178#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_SHIFT 0
2179#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_WIDTH 0x1
2180#define OMAP54XX_WKUPDEP_I2C3_IRQ_MPU_MASK (1 << 0)
2181
2182/* Used by PM_L4PER_I2C4_WKDEP */
2183#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_SHIFT 7
2184#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_WIDTH 0x1
2185#define OMAP54XX_WKUPDEP_I2C4_DMA_SDMA_MASK (1 << 7)
2186
2187/* Used by PM_L4PER_I2C4_WKDEP */
2188#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_SHIFT 1
2189#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_WIDTH 0x1
2190#define OMAP54XX_WKUPDEP_I2C4_IRQ_IPU_MASK (1 << 1)
2191
2192/* Used by PM_L4PER_I2C4_WKDEP */
2193#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_SHIFT 0
2194#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_WIDTH 0x1
2195#define OMAP54XX_WKUPDEP_I2C4_IRQ_MPU_MASK (1 << 0)
2196
2197/* Used by PM_L4PER_I2C5_WKDEP */
2198#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_SHIFT 0
2199#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_WIDTH 0x1
2200#define OMAP54XX_WKUPDEP_I2C5_IRQ_MPU_MASK (1 << 0)
2201
2202/* Used by PM_WKUPAON_KBD_WKDEP */
2203#define OMAP54XX_WKUPDEP_KBD_MPU_SHIFT 0
2204#define OMAP54XX_WKUPDEP_KBD_MPU_WIDTH 0x1
2205#define OMAP54XX_WKUPDEP_KBD_MPU_MASK (1 << 0)
2206
2207/* Used by PM_ABE_MCASP_WKDEP */
2208#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_SHIFT 6
2209#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_WIDTH 0x1
2210#define OMAP54XX_WKUPDEP_MCASP_DMA_DSP_MASK (1 << 6)
2211
2212/* Used by PM_ABE_MCASP_WKDEP */
2213#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_SHIFT 7
2214#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_WIDTH 0x1
2215#define OMAP54XX_WKUPDEP_MCASP_DMA_SDMA_MASK (1 << 7)
2216
2217/* Used by PM_ABE_MCASP_WKDEP */
2218#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_SHIFT 2
2219#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_WIDTH 0x1
2220#define OMAP54XX_WKUPDEP_MCASP_IRQ_DSP_MASK (1 << 2)
2221
2222/* Used by PM_ABE_MCASP_WKDEP */
2223#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_SHIFT 0
2224#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_WIDTH 0x1
2225#define OMAP54XX_WKUPDEP_MCASP_IRQ_MPU_MASK (1 << 0)
2226
2227/* Used by PM_ABE_MCBSP1_WKDEP */
2228#define OMAP54XX_WKUPDEP_MCBSP1_DSP_SHIFT 2
2229#define OMAP54XX_WKUPDEP_MCBSP1_DSP_WIDTH 0x1
2230#define OMAP54XX_WKUPDEP_MCBSP1_DSP_MASK (1 << 2)
2231
2232/* Used by PM_ABE_MCBSP1_WKDEP */
2233#define OMAP54XX_WKUPDEP_MCBSP1_MPU_SHIFT 0
2234#define OMAP54XX_WKUPDEP_MCBSP1_MPU_WIDTH 0x1
2235#define OMAP54XX_WKUPDEP_MCBSP1_MPU_MASK (1 << 0)
2236
2237/* Used by PM_ABE_MCBSP1_WKDEP */
2238#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_SHIFT 3
2239#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_WIDTH 0x1
2240#define OMAP54XX_WKUPDEP_MCBSP1_SDMA_MASK (1 << 3)
2241
2242/* Used by PM_ABE_MCBSP2_WKDEP */
2243#define OMAP54XX_WKUPDEP_MCBSP2_DSP_SHIFT 2
2244#define OMAP54XX_WKUPDEP_MCBSP2_DSP_WIDTH 0x1
2245#define OMAP54XX_WKUPDEP_MCBSP2_DSP_MASK (1 << 2)
2246
2247/* Used by PM_ABE_MCBSP2_WKDEP */
2248#define OMAP54XX_WKUPDEP_MCBSP2_MPU_SHIFT 0
2249#define OMAP54XX_WKUPDEP_MCBSP2_MPU_WIDTH 0x1
2250#define OMAP54XX_WKUPDEP_MCBSP2_MPU_MASK (1 << 0)
2251
2252/* Used by PM_ABE_MCBSP2_WKDEP */
2253#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_SHIFT 3
2254#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_WIDTH 0x1
2255#define OMAP54XX_WKUPDEP_MCBSP2_SDMA_MASK (1 << 3)
2256
2257/* Used by PM_ABE_MCBSP3_WKDEP */
2258#define OMAP54XX_WKUPDEP_MCBSP3_DSP_SHIFT 2
2259#define OMAP54XX_WKUPDEP_MCBSP3_DSP_WIDTH 0x1
2260#define OMAP54XX_WKUPDEP_MCBSP3_DSP_MASK (1 << 2)
2261
2262/* Used by PM_ABE_MCBSP3_WKDEP */
2263#define OMAP54XX_WKUPDEP_MCBSP3_MPU_SHIFT 0
2264#define OMAP54XX_WKUPDEP_MCBSP3_MPU_WIDTH 0x1
2265#define OMAP54XX_WKUPDEP_MCBSP3_MPU_MASK (1 << 0)
2266
2267/* Used by PM_ABE_MCBSP3_WKDEP */
2268#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_SHIFT 3
2269#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_WIDTH 0x1
2270#define OMAP54XX_WKUPDEP_MCBSP3_SDMA_MASK (1 << 3)
2271
2272/* Used by PM_ABE_MCPDM_WKDEP */
2273#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_SHIFT 6
2274#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_WIDTH 0x1
2275#define OMAP54XX_WKUPDEP_MCPDM_DMA_DSP_MASK (1 << 6)
2276
2277/* Used by PM_ABE_MCPDM_WKDEP */
2278#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_SHIFT 7
2279#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_WIDTH 0x1
2280#define OMAP54XX_WKUPDEP_MCPDM_DMA_SDMA_MASK (1 << 7)
2281
2282/* Used by PM_ABE_MCPDM_WKDEP */
2283#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_SHIFT 2
2284#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_WIDTH 0x1
2285#define OMAP54XX_WKUPDEP_MCPDM_IRQ_DSP_MASK (1 << 2)
2286
2287/* Used by PM_ABE_MCPDM_WKDEP */
2288#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_SHIFT 0
2289#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_WIDTH 0x1
2290#define OMAP54XX_WKUPDEP_MCPDM_IRQ_MPU_MASK (1 << 0)
2291
2292/* Used by PM_L4PER_MCSPI1_WKDEP */
2293#define OMAP54XX_WKUPDEP_MCSPI1_DSP_SHIFT 2
2294#define OMAP54XX_WKUPDEP_MCSPI1_DSP_WIDTH 0x1
2295#define OMAP54XX_WKUPDEP_MCSPI1_DSP_MASK (1 << 2)
2296
2297/* Used by PM_L4PER_MCSPI1_WKDEP */
2298#define OMAP54XX_WKUPDEP_MCSPI1_IPU_SHIFT 1
2299#define OMAP54XX_WKUPDEP_MCSPI1_IPU_WIDTH 0x1
2300#define OMAP54XX_WKUPDEP_MCSPI1_IPU_MASK (1 << 1)
2301
2302/* Used by PM_L4PER_MCSPI1_WKDEP */
2303#define OMAP54XX_WKUPDEP_MCSPI1_MPU_SHIFT 0
2304#define OMAP54XX_WKUPDEP_MCSPI1_MPU_WIDTH 0x1
2305#define OMAP54XX_WKUPDEP_MCSPI1_MPU_MASK (1 << 0)
2306
2307/* Used by PM_L4PER_MCSPI1_WKDEP */
2308#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_SHIFT 3
2309#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_WIDTH 0x1
2310#define OMAP54XX_WKUPDEP_MCSPI1_SDMA_MASK (1 << 3)
2311
2312/* Used by PM_L4PER_MCSPI2_WKDEP */
2313#define OMAP54XX_WKUPDEP_MCSPI2_IPU_SHIFT 1
2314#define OMAP54XX_WKUPDEP_MCSPI2_IPU_WIDTH 0x1
2315#define OMAP54XX_WKUPDEP_MCSPI2_IPU_MASK (1 << 1)
2316
2317/* Used by PM_L4PER_MCSPI2_WKDEP */
2318#define OMAP54XX_WKUPDEP_MCSPI2_MPU_SHIFT 0
2319#define OMAP54XX_WKUPDEP_MCSPI2_MPU_WIDTH 0x1
2320#define OMAP54XX_WKUPDEP_MCSPI2_MPU_MASK (1 << 0)
2321
2322/* Used by PM_L4PER_MCSPI2_WKDEP */
2323#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_SHIFT 3
2324#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_WIDTH 0x1
2325#define OMAP54XX_WKUPDEP_MCSPI2_SDMA_MASK (1 << 3)
2326
2327/* Used by PM_L4PER_MCSPI3_WKDEP */
2328#define OMAP54XX_WKUPDEP_MCSPI3_MPU_SHIFT 0
2329#define OMAP54XX_WKUPDEP_MCSPI3_MPU_WIDTH 0x1
2330#define OMAP54XX_WKUPDEP_MCSPI3_MPU_MASK (1 << 0)
2331
2332/* Used by PM_L4PER_MCSPI3_WKDEP */
2333#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_SHIFT 3
2334#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_WIDTH 0x1
2335#define OMAP54XX_WKUPDEP_MCSPI3_SDMA_MASK (1 << 3)
2336
2337/* Used by PM_L4PER_MCSPI4_WKDEP */
2338#define OMAP54XX_WKUPDEP_MCSPI4_MPU_SHIFT 0
2339#define OMAP54XX_WKUPDEP_MCSPI4_MPU_WIDTH 0x1
2340#define OMAP54XX_WKUPDEP_MCSPI4_MPU_MASK (1 << 0)
2341
2342/* Used by PM_L4PER_MCSPI4_WKDEP */
2343#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_SHIFT 3
2344#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_WIDTH 0x1
2345#define OMAP54XX_WKUPDEP_MCSPI4_SDMA_MASK (1 << 3)
2346
2347/* Used by PM_L3INIT_MMC1_WKDEP */
2348#define OMAP54XX_WKUPDEP_MMC1_DSP_SHIFT 2
2349#define OMAP54XX_WKUPDEP_MMC1_DSP_WIDTH 0x1
2350#define OMAP54XX_WKUPDEP_MMC1_DSP_MASK (1 << 2)
2351
2352/* Used by PM_L3INIT_MMC1_WKDEP */
2353#define OMAP54XX_WKUPDEP_MMC1_IPU_SHIFT 1
2354#define OMAP54XX_WKUPDEP_MMC1_IPU_WIDTH 0x1
2355#define OMAP54XX_WKUPDEP_MMC1_IPU_MASK (1 << 1)
2356
2357/* Used by PM_L3INIT_MMC1_WKDEP */
2358#define OMAP54XX_WKUPDEP_MMC1_MPU_SHIFT 0
2359#define OMAP54XX_WKUPDEP_MMC1_MPU_WIDTH 0x1
2360#define OMAP54XX_WKUPDEP_MMC1_MPU_MASK (1 << 0)
2361
2362/* Used by PM_L3INIT_MMC1_WKDEP */
2363#define OMAP54XX_WKUPDEP_MMC1_SDMA_SHIFT 3
2364#define OMAP54XX_WKUPDEP_MMC1_SDMA_WIDTH 0x1
2365#define OMAP54XX_WKUPDEP_MMC1_SDMA_MASK (1 << 3)
2366
2367/* Used by PM_L3INIT_MMC2_WKDEP */
2368#define OMAP54XX_WKUPDEP_MMC2_DSP_SHIFT 2
2369#define OMAP54XX_WKUPDEP_MMC2_DSP_WIDTH 0x1
2370#define OMAP54XX_WKUPDEP_MMC2_DSP_MASK (1 << 2)
2371
2372/* Used by PM_L3INIT_MMC2_WKDEP */
2373#define OMAP54XX_WKUPDEP_MMC2_IPU_SHIFT 1
2374#define OMAP54XX_WKUPDEP_MMC2_IPU_WIDTH 0x1
2375#define OMAP54XX_WKUPDEP_MMC2_IPU_MASK (1 << 1)
2376
2377/* Used by PM_L3INIT_MMC2_WKDEP */
2378#define OMAP54XX_WKUPDEP_MMC2_MPU_SHIFT 0
2379#define OMAP54XX_WKUPDEP_MMC2_MPU_WIDTH 0x1
2380#define OMAP54XX_WKUPDEP_MMC2_MPU_MASK (1 << 0)
2381
2382/* Used by PM_L3INIT_MMC2_WKDEP */
2383#define OMAP54XX_WKUPDEP_MMC2_SDMA_SHIFT 3
2384#define OMAP54XX_WKUPDEP_MMC2_SDMA_WIDTH 0x1
2385#define OMAP54XX_WKUPDEP_MMC2_SDMA_MASK (1 << 3)
2386
2387/* Used by PM_L4PER_MMC3_WKDEP */
2388#define OMAP54XX_WKUPDEP_MMC3_IPU_SHIFT 1
2389#define OMAP54XX_WKUPDEP_MMC3_IPU_WIDTH 0x1
2390#define OMAP54XX_WKUPDEP_MMC3_IPU_MASK (1 << 1)
2391
2392/* Used by PM_L4PER_MMC3_WKDEP */
2393#define OMAP54XX_WKUPDEP_MMC3_MPU_SHIFT 0
2394#define OMAP54XX_WKUPDEP_MMC3_MPU_WIDTH 0x1
2395#define OMAP54XX_WKUPDEP_MMC3_MPU_MASK (1 << 0)
2396
2397/* Used by PM_L4PER_MMC3_WKDEP */
2398#define OMAP54XX_WKUPDEP_MMC3_SDMA_SHIFT 3
2399#define OMAP54XX_WKUPDEP_MMC3_SDMA_WIDTH 0x1
2400#define OMAP54XX_WKUPDEP_MMC3_SDMA_MASK (1 << 3)
2401
2402/* Used by PM_L4PER_MMC4_WKDEP */
2403#define OMAP54XX_WKUPDEP_MMC4_MPU_SHIFT 0
2404#define OMAP54XX_WKUPDEP_MMC4_MPU_WIDTH 0x1
2405#define OMAP54XX_WKUPDEP_MMC4_MPU_MASK (1 << 0)
2406
2407/* Used by PM_L4PER_MMC4_WKDEP */
2408#define OMAP54XX_WKUPDEP_MMC4_SDMA_SHIFT 3
2409#define OMAP54XX_WKUPDEP_MMC4_SDMA_WIDTH 0x1
2410#define OMAP54XX_WKUPDEP_MMC4_SDMA_MASK (1 << 3)
2411
2412/* Used by PM_L4PER_MMC5_WKDEP */
2413#define OMAP54XX_WKUPDEP_MMC5_MPU_SHIFT 0
2414#define OMAP54XX_WKUPDEP_MMC5_MPU_WIDTH 0x1
2415#define OMAP54XX_WKUPDEP_MMC5_MPU_MASK (1 << 0)
2416
2417/* Used by PM_L4PER_MMC5_WKDEP */
2418#define OMAP54XX_WKUPDEP_MMC5_SDMA_SHIFT 3
2419#define OMAP54XX_WKUPDEP_MMC5_SDMA_WIDTH 0x1
2420#define OMAP54XX_WKUPDEP_MMC5_SDMA_MASK (1 << 3)
2421
2422/* Used by PM_L3INIT_SATA_WKDEP */
2423#define OMAP54XX_WKUPDEP_SATA_MPU_SHIFT 0
2424#define OMAP54XX_WKUPDEP_SATA_MPU_WIDTH 0x1
2425#define OMAP54XX_WKUPDEP_SATA_MPU_MASK (1 << 0)
2426
2427/* Used by PM_ABE_SLIMBUS1_WKDEP */
2428#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_SHIFT 6
2429#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_WIDTH 0x1
2430#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_DSP_MASK (1 << 6)
2431
2432/* Used by PM_ABE_SLIMBUS1_WKDEP */
2433#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_SHIFT 7
2434#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_WIDTH 0x1
2435#define OMAP54XX_WKUPDEP_SLIMBUS1_DMA_SDMA_MASK (1 << 7)
2436
2437/* Used by PM_ABE_SLIMBUS1_WKDEP */
2438#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_SHIFT 2
2439#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_WIDTH 0x1
2440#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_DSP_MASK (1 << 2)
2441
2442/* Used by PM_ABE_SLIMBUS1_WKDEP */
2443#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_SHIFT 0
2444#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_WIDTH 0x1
2445#define OMAP54XX_WKUPDEP_SLIMBUS1_IRQ_MPU_MASK (1 << 0)
2446
2447/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2448#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_SHIFT 1
2449#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_WIDTH 0x1
2450#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_IPU_MASK (1 << 1)
2451
2452/* Used by PM_COREAON_SMARTREFLEX_CORE_WKDEP */
2453#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_SHIFT 0
2454#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_WIDTH 0x1
2455#define OMAP54XX_WKUPDEP_SMARTREFLEX_CORE_MPU_MASK (1 << 0)
2456
2457/* Used by PM_COREAON_SMARTREFLEX_MM_WKDEP */
2458#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_SHIFT 0
2459#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_WIDTH 0x1
2460#define OMAP54XX_WKUPDEP_SMARTREFLEX_MM_MPU_MASK (1 << 0)
2461
2462/* Used by PM_COREAON_SMARTREFLEX_MPU_WKDEP */
2463#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_SHIFT 0
2464#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_WIDTH 0x1
2465#define OMAP54XX_WKUPDEP_SMARTREFLEX_MPU_MPU_MASK (1 << 0)
2466
2467/* Used by PM_L4PER_TIMER10_WKDEP */
2468#define OMAP54XX_WKUPDEP_TIMER10_MPU_SHIFT 0
2469#define OMAP54XX_WKUPDEP_TIMER10_MPU_WIDTH 0x1
2470#define OMAP54XX_WKUPDEP_TIMER10_MPU_MASK (1 << 0)
2471
2472/* Used by PM_L4PER_TIMER11_WKDEP */
2473#define OMAP54XX_WKUPDEP_TIMER11_IPU_SHIFT 1
2474#define OMAP54XX_WKUPDEP_TIMER11_IPU_WIDTH 0x1
2475#define OMAP54XX_WKUPDEP_TIMER11_IPU_MASK (1 << 1)
2476
2477/* Used by PM_L4PER_TIMER11_WKDEP */
2478#define OMAP54XX_WKUPDEP_TIMER11_MPU_SHIFT 0
2479#define OMAP54XX_WKUPDEP_TIMER11_MPU_WIDTH 0x1
2480#define OMAP54XX_WKUPDEP_TIMER11_MPU_MASK (1 << 0)
2481
2482/* Used by PM_WKUPAON_TIMER12_WKDEP */
2483#define OMAP54XX_WKUPDEP_TIMER12_MPU_SHIFT 0
2484#define OMAP54XX_WKUPDEP_TIMER12_MPU_WIDTH 0x1
2485#define OMAP54XX_WKUPDEP_TIMER12_MPU_MASK (1 << 0)
2486
2487/* Used by PM_WKUPAON_TIMER1_WKDEP */
2488#define OMAP54XX_WKUPDEP_TIMER1_MPU_SHIFT 0
2489#define OMAP54XX_WKUPDEP_TIMER1_MPU_WIDTH 0x1
2490#define OMAP54XX_WKUPDEP_TIMER1_MPU_MASK (1 << 0)
2491
2492/* Used by PM_L4PER_TIMER2_WKDEP */
2493#define OMAP54XX_WKUPDEP_TIMER2_MPU_SHIFT 0
2494#define OMAP54XX_WKUPDEP_TIMER2_MPU_WIDTH 0x1
2495#define OMAP54XX_WKUPDEP_TIMER2_MPU_MASK (1 << 0)
2496
2497/* Used by PM_L4PER_TIMER3_WKDEP */
2498#define OMAP54XX_WKUPDEP_TIMER3_IPU_SHIFT 1
2499#define OMAP54XX_WKUPDEP_TIMER3_IPU_WIDTH 0x1
2500#define OMAP54XX_WKUPDEP_TIMER3_IPU_MASK (1 << 1)
2501
2502/* Used by PM_L4PER_TIMER3_WKDEP */
2503#define OMAP54XX_WKUPDEP_TIMER3_MPU_SHIFT 0
2504#define OMAP54XX_WKUPDEP_TIMER3_MPU_WIDTH 0x1
2505#define OMAP54XX_WKUPDEP_TIMER3_MPU_MASK (1 << 0)
2506
2507/* Used by PM_L4PER_TIMER4_WKDEP */
2508#define OMAP54XX_WKUPDEP_TIMER4_IPU_SHIFT 1
2509#define OMAP54XX_WKUPDEP_TIMER4_IPU_WIDTH 0x1
2510#define OMAP54XX_WKUPDEP_TIMER4_IPU_MASK (1 << 1)
2511
2512/* Used by PM_L4PER_TIMER4_WKDEP */
2513#define OMAP54XX_WKUPDEP_TIMER4_MPU_SHIFT 0
2514#define OMAP54XX_WKUPDEP_TIMER4_MPU_WIDTH 0x1
2515#define OMAP54XX_WKUPDEP_TIMER4_MPU_MASK (1 << 0)
2516
2517/* Used by PM_ABE_TIMER5_WKDEP */
2518#define OMAP54XX_WKUPDEP_TIMER5_DSP_SHIFT 2
2519#define OMAP54XX_WKUPDEP_TIMER5_DSP_WIDTH 0x1
2520#define OMAP54XX_WKUPDEP_TIMER5_DSP_MASK (1 << 2)
2521
2522/* Used by PM_ABE_TIMER5_WKDEP */
2523#define OMAP54XX_WKUPDEP_TIMER5_MPU_SHIFT 0
2524#define OMAP54XX_WKUPDEP_TIMER5_MPU_WIDTH 0x1
2525#define OMAP54XX_WKUPDEP_TIMER5_MPU_MASK (1 << 0)
2526
2527/* Used by PM_ABE_TIMER6_WKDEP */
2528#define OMAP54XX_WKUPDEP_TIMER6_DSP_SHIFT 2
2529#define OMAP54XX_WKUPDEP_TIMER6_DSP_WIDTH 0x1
2530#define OMAP54XX_WKUPDEP_TIMER6_DSP_MASK (1 << 2)
2531
2532/* Used by PM_ABE_TIMER6_WKDEP */
2533#define OMAP54XX_WKUPDEP_TIMER6_MPU_SHIFT 0
2534#define OMAP54XX_WKUPDEP_TIMER6_MPU_WIDTH 0x1
2535#define OMAP54XX_WKUPDEP_TIMER6_MPU_MASK (1 << 0)
2536
2537/* Used by PM_ABE_TIMER7_WKDEP */
2538#define OMAP54XX_WKUPDEP_TIMER7_DSP_SHIFT 2
2539#define OMAP54XX_WKUPDEP_TIMER7_DSP_WIDTH 0x1
2540#define OMAP54XX_WKUPDEP_TIMER7_DSP_MASK (1 << 2)
2541
2542/* Used by PM_ABE_TIMER7_WKDEP */
2543#define OMAP54XX_WKUPDEP_TIMER7_MPU_SHIFT 0
2544#define OMAP54XX_WKUPDEP_TIMER7_MPU_WIDTH 0x1
2545#define OMAP54XX_WKUPDEP_TIMER7_MPU_MASK (1 << 0)
2546
2547/* Used by PM_ABE_TIMER8_WKDEP */
2548#define OMAP54XX_WKUPDEP_TIMER8_DSP_SHIFT 2
2549#define OMAP54XX_WKUPDEP_TIMER8_DSP_WIDTH 0x1
2550#define OMAP54XX_WKUPDEP_TIMER8_DSP_MASK (1 << 2)
2551
2552/* Used by PM_ABE_TIMER8_WKDEP */
2553#define OMAP54XX_WKUPDEP_TIMER8_MPU_SHIFT 0
2554#define OMAP54XX_WKUPDEP_TIMER8_MPU_WIDTH 0x1
2555#define OMAP54XX_WKUPDEP_TIMER8_MPU_MASK (1 << 0)
2556
2557/* Used by PM_L4PER_TIMER9_WKDEP */
2558#define OMAP54XX_WKUPDEP_TIMER9_IPU_SHIFT 1
2559#define OMAP54XX_WKUPDEP_TIMER9_IPU_WIDTH 0x1
2560#define OMAP54XX_WKUPDEP_TIMER9_IPU_MASK (1 << 1)
2561
2562/* Used by PM_L4PER_TIMER9_WKDEP */
2563#define OMAP54XX_WKUPDEP_TIMER9_MPU_SHIFT 0
2564#define OMAP54XX_WKUPDEP_TIMER9_MPU_WIDTH 0x1
2565#define OMAP54XX_WKUPDEP_TIMER9_MPU_MASK (1 << 0)
2566
2567/* Used by PM_L4PER_UART1_WKDEP */
2568#define OMAP54XX_WKUPDEP_UART1_MPU_SHIFT 0
2569#define OMAP54XX_WKUPDEP_UART1_MPU_WIDTH 0x1
2570#define OMAP54XX_WKUPDEP_UART1_MPU_MASK (1 << 0)
2571
2572/* Used by PM_L4PER_UART1_WKDEP */
2573#define OMAP54XX_WKUPDEP_UART1_SDMA_SHIFT 3
2574#define OMAP54XX_WKUPDEP_UART1_SDMA_WIDTH 0x1
2575#define OMAP54XX_WKUPDEP_UART1_SDMA_MASK (1 << 3)
2576
2577/* Used by PM_L4PER_UART2_WKDEP */
2578#define OMAP54XX_WKUPDEP_UART2_MPU_SHIFT 0
2579#define OMAP54XX_WKUPDEP_UART2_MPU_WIDTH 0x1
2580#define OMAP54XX_WKUPDEP_UART2_MPU_MASK (1 << 0)
2581
2582/* Used by PM_L4PER_UART2_WKDEP */
2583#define OMAP54XX_WKUPDEP_UART2_SDMA_SHIFT 3
2584#define OMAP54XX_WKUPDEP_UART2_SDMA_WIDTH 0x1
2585#define OMAP54XX_WKUPDEP_UART2_SDMA_MASK (1 << 3)
2586
2587/* Used by PM_L4PER_UART3_WKDEP */
2588#define OMAP54XX_WKUPDEP_UART3_DSP_SHIFT 2
2589#define OMAP54XX_WKUPDEP_UART3_DSP_WIDTH 0x1
2590#define OMAP54XX_WKUPDEP_UART3_DSP_MASK (1 << 2)
2591
2592/* Used by PM_L4PER_UART3_WKDEP */
2593#define OMAP54XX_WKUPDEP_UART3_IPU_SHIFT 1
2594#define OMAP54XX_WKUPDEP_UART3_IPU_WIDTH 0x1
2595#define OMAP54XX_WKUPDEP_UART3_IPU_MASK (1 << 1)
2596
2597/* Used by PM_L4PER_UART3_WKDEP */
2598#define OMAP54XX_WKUPDEP_UART3_MPU_SHIFT 0
2599#define OMAP54XX_WKUPDEP_UART3_MPU_WIDTH 0x1
2600#define OMAP54XX_WKUPDEP_UART3_MPU_MASK (1 << 0)
2601
2602/* Used by PM_L4PER_UART3_WKDEP */
2603#define OMAP54XX_WKUPDEP_UART3_SDMA_SHIFT 3
2604#define OMAP54XX_WKUPDEP_UART3_SDMA_WIDTH 0x1
2605#define OMAP54XX_WKUPDEP_UART3_SDMA_MASK (1 << 3)
2606
2607/* Used by PM_L4PER_UART4_WKDEP */
2608#define OMAP54XX_WKUPDEP_UART4_MPU_SHIFT 0
2609#define OMAP54XX_WKUPDEP_UART4_MPU_WIDTH 0x1
2610#define OMAP54XX_WKUPDEP_UART4_MPU_MASK (1 << 0)
2611
2612/* Used by PM_L4PER_UART4_WKDEP */
2613#define OMAP54XX_WKUPDEP_UART4_SDMA_SHIFT 3
2614#define OMAP54XX_WKUPDEP_UART4_SDMA_WIDTH 0x1
2615#define OMAP54XX_WKUPDEP_UART4_SDMA_MASK (1 << 3)
2616
2617/* Used by PM_L4PER_UART5_WKDEP */
2618#define OMAP54XX_WKUPDEP_UART5_MPU_SHIFT 0
2619#define OMAP54XX_WKUPDEP_UART5_MPU_WIDTH 0x1
2620#define OMAP54XX_WKUPDEP_UART5_MPU_MASK (1 << 0)
2621
2622/* Used by PM_L4PER_UART5_WKDEP */
2623#define OMAP54XX_WKUPDEP_UART5_SDMA_SHIFT 3
2624#define OMAP54XX_WKUPDEP_UART5_SDMA_WIDTH 0x1
2625#define OMAP54XX_WKUPDEP_UART5_SDMA_MASK (1 << 3)
2626
2627/* Used by PM_L4PER_UART6_WKDEP */
2628#define OMAP54XX_WKUPDEP_UART6_MPU_SHIFT 0
2629#define OMAP54XX_WKUPDEP_UART6_MPU_WIDTH 0x1
2630#define OMAP54XX_WKUPDEP_UART6_MPU_MASK (1 << 0)
2631
2632/* Used by PM_L4PER_UART6_WKDEP */
2633#define OMAP54XX_WKUPDEP_UART6_SDMA_SHIFT 3
2634#define OMAP54XX_WKUPDEP_UART6_SDMA_WIDTH 0x1
2635#define OMAP54XX_WKUPDEP_UART6_SDMA_MASK (1 << 3)
2636
2637/* Used by PM_L3INIT_UNIPRO2_WKDEP */
2638#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_SHIFT 0
2639#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_WIDTH 0x1
2640#define OMAP54XX_WKUPDEP_UNIPRO2_MPU_MASK (1 << 0)
2641
2642/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2643#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_SHIFT 1
2644#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_WIDTH 0x1
2645#define OMAP54XX_WKUPDEP_USB_HOST_HS_IPU_MASK (1 << 1)
2646
2647/* Used by PM_L3INIT_USB_HOST_HS_WKDEP */
2648#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_SHIFT 0
2649#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_WIDTH 0x1
2650#define OMAP54XX_WKUPDEP_USB_HOST_HS_MPU_MASK (1 << 0)
2651
2652/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2653#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_SHIFT 1
2654#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_WIDTH 0x1
2655#define OMAP54XX_WKUPDEP_USB_OTG_SS_IPU_MASK (1 << 1)
2656
2657/* Used by PM_L3INIT_USB_OTG_SS_WKDEP */
2658#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_SHIFT 0
2659#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_WIDTH 0x1
2660#define OMAP54XX_WKUPDEP_USB_OTG_SS_MPU_MASK (1 << 0)
2661
2662/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2663#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_SHIFT 1
2664#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_WIDTH 0x1
2665#define OMAP54XX_WKUPDEP_USB_TLL_HS_IPU_MASK (1 << 1)
2666
2667/* Used by PM_L3INIT_USB_TLL_HS_WKDEP */
2668#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_SHIFT 0
2669#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_WIDTH 0x1
2670#define OMAP54XX_WKUPDEP_USB_TLL_HS_MPU_MASK (1 << 0)
2671
2672/* Used by PM_WKUPAON_WD_TIMER2_WKDEP */
2673#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_SHIFT 0
2674#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_WIDTH 0x1
2675#define OMAP54XX_WKUPDEP_WD_TIMER2_MPU_MASK (1 << 0)
2676
2677/* Used by PM_ABE_WD_TIMER3_WKDEP */
2678#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_SHIFT 0
2679#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_WIDTH 0x1
2680#define OMAP54XX_WKUPDEP_WD_TIMER3_MPU_MASK (1 << 0)
2681
2682/* Used by PRM_IO_PMCTRL */
2683#define OMAP54XX_WUCLK_CTRL_SHIFT 8
2684#define OMAP54XX_WUCLK_CTRL_WIDTH 0x1
2685#define OMAP54XX_WUCLK_CTRL_MASK (1 << 8)
2686
2687/* Used by PRM_IO_PMCTRL */
2688#define OMAP54XX_WUCLK_STATUS_SHIFT 9
2689#define OMAP54XX_WUCLK_STATUS_WIDTH 0x1
2690#define OMAP54XX_WUCLK_STATUS_MASK (1 << 9)
2691
2692/* Used by REVISION_PRM */
2693#define OMAP54XX_X_MAJOR_SHIFT 8
2694#define OMAP54XX_X_MAJOR_WIDTH 0x3
2695#define OMAP54XX_X_MAJOR_MASK (0x7 << 8)
2696
2697/* Used by REVISION_PRM */
2698#define OMAP54XX_Y_MINOR_SHIFT 0
2699#define OMAP54XX_Y_MINOR_WIDTH 0x6
2700#define OMAP54XX_Y_MINOR_MASK (0x3f << 0)
2701#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 415c7e0c9393..03a603476cfc 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
620 return 0; 620 return 0;
621} 621}
622 622
623static int omap4_check_vcvp(void)
624{
625 /* No VC/VP on dra7xx devices */
626 if (soc_is_dra7xx())
627 return 0;
628
629 return 1;
630}
631
623struct pwrdm_ops omap4_pwrdm_operations = { 632struct pwrdm_ops omap4_pwrdm_operations = {
624 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, 633 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
625 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, 634 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
@@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
637 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, 646 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
638 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, 647 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
639 .pwrdm_wait_transition = omap4_pwrdm_wait_transition, 648 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
649 .pwrdm_has_voltdm = omap4_check_vcvp,
640}; 650};
641 651
642/* 652/*
@@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
650 660
651int __init omap44xx_prm_init(void) 661int __init omap44xx_prm_init(void)
652{ 662{
653 if (!cpu_is_omap44xx() && !soc_is_omap54xx()) 663 if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
654 return 0; 664 return 0;
655 665
656 return prm_register(&omap44xx_prm_ll_data); 666 return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
new file mode 100644
index 000000000000..d92a8404edc7
--- /dev/null
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -0,0 +1,678 @@
1/*
2 * DRA7xx PRM instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
24
25#include "prm44xx_54xx.h"
26#include "prcm-common.h"
27#include "prm.h"
28
29#define DRA7XX_PRM_BASE 0x4ae06000
30
31#define DRA7XX_PRM_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
33
34
35/* PRM instances */
36#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
37#define DRA7XX_PRM_CKGEN_INST 0x0100
38#define DRA7XX_PRM_MPU_INST 0x0300
39#define DRA7XX_PRM_DSP1_INST 0x0400
40#define DRA7XX_PRM_IPU_INST 0x0500
41#define DRA7XX_PRM_COREAON_INST 0x0628
42#define DRA7XX_PRM_CORE_INST 0x0700
43#define DRA7XX_PRM_IVA_INST 0x0f00
44#define DRA7XX_PRM_CAM_INST 0x1000
45#define DRA7XX_PRM_DSS_INST 0x1100
46#define DRA7XX_PRM_GPU_INST 0x1200
47#define DRA7XX_PRM_L3INIT_INST 0x1300
48#define DRA7XX_PRM_L4PER_INST 0x1400
49#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
50#define DRA7XX_PRM_WKUPAON_INST 0x1724
51#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
52#define DRA7XX_PRM_EMU_INST 0x1900
53#define DRA7XX_PRM_EMU_CM_INST 0x1a00
54#define DRA7XX_PRM_DSP2_INST 0x1b00
55#define DRA7XX_PRM_EVE1_INST 0x1b40
56#define DRA7XX_PRM_EVE2_INST 0x1b80
57#define DRA7XX_PRM_EVE3_INST 0x1bc0
58#define DRA7XX_PRM_EVE4_INST 0x1c00
59#define DRA7XX_PRM_RTC_INST 0x1c60
60#define DRA7XX_PRM_VPE_INST 0x1c80
61#define DRA7XX_PRM_DEVICE_INST 0x1d00
62#define DRA7XX_PRM_INSTR_INST 0x1f00
63
64/* PRM clockdomain register offsets (from instance start) */
65#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
66#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
67
68/* PRM */
69
70/* PRM.OCP_SOCKET_PRM register offsets */
71#define DRA7XX_REVISION_PRM_OFFSET 0x0000
72#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
73#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
74#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
75#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
76#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
77#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
78#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
79#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
80#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
81#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
82#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
83#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
84#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
85#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
86#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
87#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
88#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
89#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
90#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
91#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
92#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
93#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
94#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
95#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
96#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
97#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
98
99/* PRM.CKGEN_PRM register offsets */
100#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
101#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
102#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
103#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
104#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
105#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
106#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
107#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
108#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
109#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
110#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
111#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
112#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
113#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
114#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
115#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
116#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
117#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
118#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
119#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
120#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
121#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
122#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
123#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
124#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
125#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
126#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
127#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
128#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
129#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
130#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
131#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
132#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
133#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
134#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
135#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
136#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
137#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
138#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
139#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
140#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
141#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
142#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
143#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
144#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
145#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
146#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
147#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
148#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
149#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
150#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
151#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
152#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
153#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
154#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
155#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
156#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
157#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
158#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
159#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
160#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
161#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
162#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
163#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
164#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
165#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
166#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
167#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
168#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
169#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
170#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
171#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
172#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
173#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
174#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
175#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
176#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
177#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
178#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
179#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
180#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
181#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
182#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
183#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
184#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
185#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
186#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
187#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
188#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
189#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
190#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
191#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
192#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
193#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
194#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
195#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
196#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
197#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
198#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
199#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
200#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
201#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
202#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
203#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
204#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
205#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
206#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
207#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
208
209/* PRM.MPU_PRM register offsets */
210#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
211#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
212#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
213
214/* PRM.DSP1_PRM register offsets */
215#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
216#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
217#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
218#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
219#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
220
221/* PRM.IPU_PRM register offsets */
222#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
223#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
224#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
225#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
226#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
227#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
228#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
229#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
230#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
231#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
232#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
233#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
234#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
235#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
236#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
237#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
238#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
239#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
240#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
241
242/* PRM.COREAON_PRM register offsets */
243#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
244#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
245#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
246#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
247#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
248#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
249#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
250#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
251#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
252#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
253#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
254#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
255#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
256#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
257
258/* PRM.CORE_PRM register offsets */
259#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
260#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
261#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
262#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
263#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
264#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
265#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
266#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
267#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
268#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
269#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
270#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
271#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
272#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
273#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
274#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
275#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
276#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
277#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
278#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
279#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
280#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
281#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
282#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
283#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
284#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
285#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
286#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
287#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
288#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
289#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
290#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
291#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
292#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
293#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
294#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
295#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
296#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
297#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
298#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
299#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
300#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
301#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
302#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
303#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
304#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
305#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
306#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
307#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
308#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
309#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
310#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
311#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
312#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
313#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
314#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
315#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
316#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
317#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
318#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
319#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
320#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
321#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
322#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
323#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
324
325/* PRM.IVA_PRM register offsets */
326#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
327#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
328#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
329#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
330#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
331#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
332
333/* PRM.CAM_PRM register offsets */
334#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
335#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
336#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
337#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
338#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
339#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
340#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
341#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
342#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
343#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
344#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
345
346/* PRM.DSS_PRM register offsets */
347#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
348#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
349#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
350#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
351#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
352#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
353#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
354
355/* PRM.GPU_PRM register offsets */
356#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
357#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
358#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
359
360/* PRM.L3INIT_PRM register offsets */
361#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
362#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
363#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
364#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
365#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
366#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
367#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
368#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
369#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
370#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
371#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
372#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
373#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
380#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
381#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
382
383/* PRM.L4PER_PRM register offsets */
384#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
385#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
386#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
387#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
388#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
389#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
390#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
391#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
392#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
393#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
394#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
395#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
396#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
397#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
398#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
399#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
400#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
401#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
402#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
403#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
404#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
405#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
406#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
407#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
408#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
409#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
410#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
411#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
412#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
413#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
414#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
415#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
416#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
417#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
418#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
419#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
420#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
421#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
422#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
423#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
424#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
425#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
426#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
427#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
428#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
429#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
430#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
431#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
432#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
433#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
434#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
435#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
436#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
437#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
438#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
439#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
440#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
441#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
442#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
443#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
444#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
445#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
446#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
447#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
448#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
449#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
450#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
451#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
452#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
453#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
454#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
455#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
456#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
457#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
458#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
459#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
460#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
461#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
462#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
463#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
464#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
465#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
466#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
467#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
468#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
469#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
470#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
471#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
472#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
473#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
474#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
475#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
476#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
477#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
478#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
479#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
480#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
481#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
482#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
483#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
484#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
485#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
486#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
487#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
488#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
489#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
490#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
491#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
492
493/* PRM.CUSTEFUSE_PRM register offsets */
494#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
495#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
496#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
497
498/* PRM.WKUPAON_PRM register offsets */
499#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
500#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
501#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
502#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
503#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
504#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
505#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
506#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
507#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
508#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
509#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
510#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
511#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
512#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
513#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
514#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
515#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
516#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
517#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
518#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
519#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
520#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
521#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
522#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
523#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
524#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
525#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
526
527/* PRM.WKUPAON_CM register offsets */
528#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
529#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
530#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
531#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
532#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
533#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
534#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
535#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
536#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
537#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
538#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
539#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
540#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
541#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
542#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
543#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
544#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
545#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
546#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
547#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
548#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
549#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
550#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
551#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
552#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
553#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
554#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
555#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
556#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
557#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
558#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
559#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
560#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
561#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
562#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
563#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
564#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
565#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
566#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
567#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
568#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
569
570/* PRM.EMU_PRM register offsets */
571#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
572#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
573#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
574
575/* PRM.EMU_CM register offsets */
576#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
577#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
578#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
579#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
580#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
581#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
582
583/* PRM.DSP2_PRM register offsets */
584#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
585#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
586#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
587#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
588#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
589
590/* PRM.EVE1_PRM register offsets */
591#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
592#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
593#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
594#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
595#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
596#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
597
598/* PRM.EVE2_PRM register offsets */
599#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
600#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
601#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
602#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
603#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
604#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
605
606/* PRM.EVE3_PRM register offsets */
607#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
608#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
609#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
610#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
611#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
612#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
613
614/* PRM.EVE4_PRM register offsets */
615#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
616#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
617#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
618#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
619#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
620#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
621
622/* PRM.RTC_PRM register offsets */
623#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
624#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
625
626/* PRM.VPE_PRM register offsets */
627#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
628#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
629#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
630#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
631
632/* PRM.DEVICE_PRM register offsets */
633#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
634#define DRA7XX_PRM_RSTST_OFFSET 0x0004
635#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
636#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
637#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
638#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
639#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
640#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
641#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
642#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
643#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
644#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
645#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
646#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
647#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
648#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
649#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
650#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
651#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
652#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
653#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
654#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
655#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
656#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
657#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
658#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
659#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
660#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
661#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
662#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
663#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
664#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
665#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
666#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
667#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
668#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
669#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
670#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
671#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
672#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
673#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
674#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
675#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
676#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
677
678#endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c12320c0ae95..6334b96b4097 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -20,10 +20,13 @@
20#include "common.h" 20#include "common.h"
21#include "prcm-common.h" 21#include "prcm-common.h"
22#include "prm44xx.h" 22#include "prm44xx.h"
23#include "prm54xx.h"
24#include "prm7xx.h"
23#include "prminst44xx.h" 25#include "prminst44xx.h"
24#include "prm-regbits-44xx.h" 26#include "prm-regbits-44xx.h"
25#include "prcm44xx.h" 27#include "prcm44xx.h"
26#include "prcm_mpu44xx.h" 28#include "prcm_mpu44xx.h"
29#include "soc.h"
27 30
28static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 31static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
29 32
@@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
165void omap4_prminst_global_warm_sw_reset(void) 168void omap4_prminst_global_warm_sw_reset(void)
166{ 169{
167 u32 v; 170 u32 v;
168 171 s16 dev_inst;
169 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 172
170 OMAP4430_PRM_DEVICE_INST, 173 if (cpu_is_omap44xx())
171 OMAP4_PRM_RSTCTRL_OFFSET); 174 dev_inst = OMAP4430_PRM_DEVICE_INST;
175 else if (soc_is_omap54xx())
176 dev_inst = OMAP54XX_PRM_DEVICE_INST;
177 else if (soc_is_dra7xx())
178 dev_inst = DRA7XX_PRM_DEVICE_INST;
179 else
180 return;
181
182 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
183 OMAP4_PRM_RSTCTRL_OFFSET);
172 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
173 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
174 OMAP4430_PRM_DEVICE_INST, 186 OMAP4430_PRM_DEVICE_INST,
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 8c616e436bc7..4588df1447ed 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -8,6 +8,7 @@
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com> 10 * Added OMAP4/5 specific defines - Santosh Shilimkar<santosh.shilimkar@ti.com>
11 * Added DRA7xxx specific defines - Sricharan R<r.sricharan@ti.com>
11 * 12 *
12 * This program is free software; you can redistribute it and/or modify 13 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by 14 * it under the terms of the GNU General Public License as published by
@@ -35,6 +36,7 @@
35#ifndef __ASSEMBLY__ 36#ifndef __ASSEMBLY__
36 37
37#include <linux/bitops.h> 38#include <linux/bitops.h>
39#include <linux/of.h>
38 40
39/* 41/*
40 * Test if multicore OMAP support is needed 42 * Test if multicore OMAP support is needed
@@ -105,6 +107,15 @@
105# endif 107# endif
106#endif 108#endif
107 109
110#ifdef CONFIG_SOC_DRA7XX
111# ifdef OMAP_NAME
112# undef MULTI_OMAP2
113# define MULTI_OMAP2
114# else
115# define OMAP_NAME DRA7XX
116# endif
117#endif
118
108/* 119/*
109 * Omap device type i.e. EMU/HS/TST/GP/BAD 120 * Omap device type i.e. EMU/HS/TST/GP/BAD
110 */ 121 */
@@ -233,6 +244,7 @@ IS_AM_SUBCLASS(437x, 0x437)
233#define cpu_is_omap447x() 0 244#define cpu_is_omap447x() 0
234#define soc_is_omap54xx() 0 245#define soc_is_omap54xx() 0
235#define soc_is_omap543x() 0 246#define soc_is_omap543x() 0
247#define soc_is_dra7xx() 0
236 248
237#if defined(MULTI_OMAP2) 249#if defined(MULTI_OMAP2)
238# if defined(CONFIG_ARCH_OMAP2) 250# if defined(CONFIG_ARCH_OMAP2)
@@ -379,6 +391,11 @@ IS_OMAP_TYPE(3430, 0x3430)
379# define soc_is_omap543x() is_omap543x() 391# define soc_is_omap543x() is_omap543x()
380#endif 392#endif
381 393
394#if defined(CONFIG_SOC_DRA7XX)
395#undef soc_is_dra7xx
396#define soc_is_dra7xx() (of_machine_is_compatible("ti,dra7"))
397#endif
398
382/* Various silicon revisions for omap2 */ 399/* Various silicon revisions for omap2 */
383#define OMAP242X_CLASS 0x24200024 400#define OMAP242X_CLASS 0x24200024
384#define OMAP2420_REV_ES1_0 OMAP242X_CLASS 401#define OMAP2420_REV_ES1_0 OMAP242X_CLASS
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index b37e1fcbad56..fa74a0625da1 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -537,7 +537,7 @@ static void __init realtime_counter_init(void)
537 reg |= num; 537 reg |= num;
538 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); 538 __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET);
539 539
540 reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & 540 reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) &
541 NUMERATOR_DENUMERATOR_MASK; 541 NUMERATOR_DENUMERATOR_MASK;
542 reg |= den; 542 reg |= den;
543 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); 543 __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
@@ -594,13 +594,14 @@ OMAP_SYS_GP_TIMER_INIT(3, 2, "timer_sys_ck", NULL,
594 1, "timer_sys_ck", "ti,timer-alwon"); 594 1, "timer_sys_ck", "ti,timer-alwon");
595#endif 595#endif
596 596
597#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) 597#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \
598 defined(CONFIG_SOC_DRA7XX)
598static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon", 599static OMAP_SYS_32K_TIMER_INIT(4, 1, "timer_32k_ck", "ti,timer-alwon",
599 2, "sys_clkin_ck", NULL); 600 2, "sys_clkin_ck", NULL);
600#endif 601#endif
601 602
602#ifdef CONFIG_ARCH_OMAP4 603#ifdef CONFIG_ARCH_OMAP4
603#ifdef CONFIG_LOCAL_TIMERS 604#ifdef CONFIG_HAVE_ARM_TWD
604static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29); 605static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, OMAP44XX_LOCAL_TWD_BASE, 29);
605void __init omap4_local_timer_init(void) 606void __init omap4_local_timer_init(void)
606{ 607{
@@ -619,12 +620,12 @@ void __init omap4_local_timer_init(void)
619 pr_err("twd_local_timer_register failed %d\n", err); 620 pr_err("twd_local_timer_register failed %d\n", err);
620 } 621 }
621} 622}
622#else /* CONFIG_LOCAL_TIMERS */ 623#else
623void __init omap4_local_timer_init(void) 624void __init omap4_local_timer_init(void)
624{ 625{
625 omap4_sync32k_timer_init(); 626 omap4_sync32k_timer_init();
626} 627}
627#endif /* CONFIG_LOCAL_TIMERS */ 628#endif /* CONFIG_HAVE_ARM_TWD */
628#endif /* CONFIG_ARCH_OMAP4 */ 629#endif /* CONFIG_ARCH_OMAP4 */
629 630
630#ifdef CONFIG_SOC_OMAP5 631#ifdef CONFIG_SOC_OMAP5
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index b41599f98a8e..91a5852b44f3 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -174,8 +174,10 @@ void __init orion5x_xor_init(void)
174 ****************************************************************************/ 174 ****************************************************************************/
175static void __init orion5x_crypto_init(void) 175static void __init orion5x_crypto_init(void)
176{ 176{
177 mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE, 177 mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
178 ORION5X_SRAM_SIZE); 178 ORION_MBUS_SRAM_ATTR,
179 ORION5X_SRAM_PHYS_BASE,
180 ORION5X_SRAM_SIZE);
179 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE, 181 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 SZ_8K, IRQ_ORION5X_CESA); 182 SZ_8K, IRQ_ORION5X_CESA);
181} 183}
@@ -222,22 +224,24 @@ void orion5x_setup_wins(void)
222 * The PCIe windows will no longer be statically allocated 224 * The PCIe windows will no longer be statically allocated
223 * here once Orion5x is migrated to the pci-mvebu driver. 225 * here once Orion5x is migrated to the pci-mvebu driver.
224 */ 226 */
225 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE, 227 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
228 ORION_MBUS_PCIE_IO_ATTR,
229 ORION5X_PCIE_IO_PHYS_BASE,
226 ORION5X_PCIE_IO_SIZE, 230 ORION5X_PCIE_IO_SIZE,
227 ORION5X_PCIE_IO_BUS_BASE, 231 ORION5X_PCIE_IO_BUS_BASE);
228 MVEBU_MBUS_PCI_IO); 232 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
229 mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE, 233 ORION_MBUS_PCIE_MEM_ATTR,
230 ORION5X_PCIE_MEM_SIZE, 234 ORION5X_PCIE_MEM_PHYS_BASE,
231 MVEBU_MBUS_NO_REMAP, 235 ORION5X_PCIE_MEM_SIZE);
232 MVEBU_MBUS_PCI_MEM); 236 mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
233 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE, 237 ORION_MBUS_PCI_IO_ATTR,
238 ORION5X_PCI_IO_PHYS_BASE,
234 ORION5X_PCI_IO_SIZE, 239 ORION5X_PCI_IO_SIZE,
235 ORION5X_PCI_IO_BUS_BASE, 240 ORION5X_PCI_IO_BUS_BASE);
236 MVEBU_MBUS_PCI_IO); 241 mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
237 mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE, 242 ORION_MBUS_PCI_MEM_ATTR,
238 ORION5X_PCI_MEM_SIZE, 243 ORION5X_PCI_MEM_PHYS_BASE,
239 MVEBU_MBUS_NO_REMAP, 244 ORION5X_PCI_MEM_SIZE);
240 MVEBU_MBUS_PCI_MEM);
241} 245}
242 246
243int orion5x_tclk; 247int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index a909afb384fb..f565f9944af2 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -7,6 +7,23 @@ struct dsa_platform_data;
7struct mv643xx_eth_platform_data; 7struct mv643xx_eth_platform_data;
8struct mv_sata_platform_data; 8struct mv_sata_platform_data;
9 9
10#define ORION_MBUS_PCIE_MEM_TARGET 0x04
11#define ORION_MBUS_PCIE_MEM_ATTR 0x59
12#define ORION_MBUS_PCIE_IO_TARGET 0x04
13#define ORION_MBUS_PCIE_IO_ATTR 0x51
14#define ORION_MBUS_PCIE_WA_TARGET 0x04
15#define ORION_MBUS_PCIE_WA_ATTR 0x79
16#define ORION_MBUS_PCI_MEM_TARGET 0x03
17#define ORION_MBUS_PCI_MEM_ATTR 0x59
18#define ORION_MBUS_PCI_IO_TARGET 0x03
19#define ORION_MBUS_PCI_IO_ATTR 0x51
20#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
21#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
22#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
23#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
24#define ORION_MBUS_SRAM_TARGET 0x00
25#define ORION_MBUS_SRAM_ATTR 0x00
26
10/* 27/*
11 * Basic Orion init functions used early by machine-setup. 28 * Basic Orion init functions used early by machine-setup.
12 */ 29 */
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 16c88bbabc98..8f68b745c1d5 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -317,8 +317,10 @@ static void __init d2net_init(void)
317 d2net_sata_power_init(); 317 d2net_sata_power_init();
318 orion5x_sata_init(&d2net_sata_data); 318 orion5x_sata_init(&d2net_sata_data);
319 319
320 mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE, 320 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
321 D2NET_NOR_BOOT_SIZE); 321 ORION_MBUS_DEVBUS_BOOT_ATTR,
322 D2NET_NOR_BOOT_BASE,
323 D2NET_NOR_BOOT_SIZE);
322 platform_device_register(&d2net_nor_flash); 324 platform_device_register(&d2net_nor_flash);
323 325
324 platform_device_register(&d2net_gpio_buttons); 326 platform_device_register(&d2net_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 4e1263da38bb..4b2aefd1d961 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -340,19 +340,27 @@ static void __init db88f5281_init(void)
340 orion5x_uart0_init(); 340 orion5x_uart0_init();
341 orion5x_uart1_init(); 341 orion5x_uart1_init();
342 342
343 mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE, 343 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
344 DB88F5281_NOR_BOOT_SIZE); 344 ORION_MBUS_DEVBUS_BOOT_ATTR,
345 DB88F5281_NOR_BOOT_BASE,
346 DB88F5281_NOR_BOOT_SIZE);
345 platform_device_register(&db88f5281_boot_flash); 347 platform_device_register(&db88f5281_boot_flash);
346 348
347 mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE, 349 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
348 DB88F5281_7SEG_SIZE); 350 ORION_MBUS_DEVBUS_ATTR(0),
351 DB88F5281_7SEG_BASE,
352 DB88F5281_7SEG_SIZE);
349 353
350 mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE, 354 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
351 DB88F5281_NOR_SIZE); 355 ORION_MBUS_DEVBUS_ATTR(1),
356 DB88F5281_NOR_BASE,
357 DB88F5281_NOR_SIZE);
352 platform_device_register(&db88f5281_nor_flash); 358 platform_device_register(&db88f5281_nor_flash);
353 359
354 mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE, 360 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
355 DB88F5281_NAND_SIZE); 361 ORION_MBUS_DEVBUS_ATTR(2),
362 DB88F5281_NAND_BASE,
363 DB88F5281_NAND_SIZE);
356 platform_device_register(&db88f5281_nand_flash); 364 platform_device_register(&db88f5281_nand_flash);
357 365
358 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); 366 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 9e6baf581ed3..70974732cbf0 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -611,8 +611,10 @@ static void __init dns323_init(void)
611 /* setup flash mapping 611 /* setup flash mapping
612 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 612 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
613 */ 613 */
614 mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE, 614 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
615 DNS323_NOR_BOOT_SIZE); 615 ORION_MBUS_DEVBUS_BOOT_ATTR,
616 DNS323_NOR_BOOT_BASE,
617 DNS323_NOR_BOOT_SIZE);
616 platform_device_register(&dns323_nor_flash); 618 platform_device_register(&dns323_nor_flash);
617 619
618 /* Sort out LEDs, Buttons and i2c devices */ 620 /* Sort out LEDs, Buttons and i2c devices */
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index 147615510dd0..f66c1b2ee8c1 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -23,8 +23,8 @@
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/pci.h> 24#include <linux/pci.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/mbus.h>
26#include <linux/mtd/physmap.h> 27#include <linux/mtd/physmap.h>
27#include <linux/mv643xx_eth.h>
28#include <linux/leds.h> 28#include <linux/leds.h>
29#include <linux/gpio_keys.h> 29#include <linux/gpio_keys.h>
30#include <linux/input.h> 30#include <linux/input.h>
@@ -96,14 +96,6 @@ static struct platform_device edmini_v2_nor_flash = {
96}; 96};
97 97
98/***************************************************************************** 98/*****************************************************************************
99 * Ethernet
100 ****************************************************************************/
101
102static struct mv643xx_eth_platform_data edmini_v2_eth_data = {
103 .phy_addr = 8,
104};
105
106/*****************************************************************************
107 * RTC 5C372a on I2C bus 99 * RTC 5C372a on I2C bus
108 ****************************************************************************/ 100 ****************************************************************************/
109 101
@@ -152,10 +144,11 @@ void __init edmini_v2_init(void)
152 * Configure peripherals. 144 * Configure peripherals.
153 */ 145 */
154 orion5x_ehci0_init(); 146 orion5x_ehci0_init();
155 orion5x_eth_init(&edmini_v2_eth_data);
156 147
157 mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE, 148 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
158 EDMINI_V2_NOR_BOOT_SIZE); 149 ORION_MBUS_DEVBUS_BOOT_ATTR,
150 EDMINI_V2_NOR_BOOT_BASE,
151 EDMINI_V2_NOR_BOOT_SIZE);
159 platform_device_register(&edmini_v2_nor_flash); 152 platform_device_register(&edmini_v2_nor_flash);
160 153
161 pr_notice("edmini_v2: USB device port, flash write and power-off " 154 pr_notice("edmini_v2: USB device port, flash write and power-off "
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index aae10e4a917c..fe6a48a325e8 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -359,13 +359,17 @@ static void __init kurobox_pro_init(void)
359 orion5x_uart1_init(); 359 orion5x_uart1_init();
360 orion5x_xor_init(); 360 orion5x_xor_init();
361 361
362 mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE, 362 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
363 KUROBOX_PRO_NOR_BOOT_SIZE); 363 ORION_MBUS_DEVBUS_BOOT_ATTR,
364 KUROBOX_PRO_NOR_BOOT_BASE,
365 KUROBOX_PRO_NOR_BOOT_SIZE);
364 platform_device_register(&kurobox_pro_nor_flash); 366 platform_device_register(&kurobox_pro_nor_flash);
365 367
366 if (machine_is_kurobox_pro()) { 368 if (machine_is_kurobox_pro()) {
367 mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE, 369 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
368 KUROBOX_PRO_NAND_SIZE); 370 ORION_MBUS_DEVBUS_ATTR(0),
371 KUROBOX_PRO_NAND_BASE,
372 KUROBOX_PRO_NAND_SIZE);
369 platform_device_register(&kurobox_pro_nand_flash); 373 platform_device_register(&kurobox_pro_nand_flash);
370 } 374 }
371 375
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6234977b5aea..028ea038d404 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -294,8 +294,10 @@ static void __init lschl_init(void)
294 orion5x_uart0_init(); 294 orion5x_uart0_init();
295 orion5x_xor_init(); 295 orion5x_xor_init();
296 296
297 mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE, 297 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
298 LSCHL_NOR_BOOT_SIZE); 298 ORION_MBUS_DEVBUS_BOOT_ATTR,
299 LSCHL_NOR_BOOT_BASE,
300 LSCHL_NOR_BOOT_SIZE);
299 platform_device_register(&lschl_nor_flash); 301 platform_device_register(&lschl_nor_flash);
300 302
301 platform_device_register(&lschl_leds); 303 platform_device_register(&lschl_leds);
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index fe04c4b64569..32b7129b767d 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -243,8 +243,10 @@ static void __init ls_hgl_init(void)
243 orion5x_uart0_init(); 243 orion5x_uart0_init();
244 orion5x_xor_init(); 244 orion5x_xor_init();
245 245
246 mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE, 246 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
247 LS_HGL_NOR_BOOT_SIZE); 247 ORION_MBUS_DEVBUS_BOOT_ATTR,
248 LS_HGL_NOR_BOOT_BASE,
249 LS_HGL_NOR_BOOT_SIZE);
248 platform_device_register(&ls_hgl_nor_flash); 250 platform_device_register(&ls_hgl_nor_flash);
249 251
250 platform_device_register(&ls_hgl_button_device); 252 platform_device_register(&ls_hgl_button_device);
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ca4dbe973daf..a6493e76f96d 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -244,8 +244,10 @@ static void __init lsmini_init(void)
244 orion5x_uart0_init(); 244 orion5x_uart0_init();
245 orion5x_xor_init(); 245 orion5x_xor_init();
246 246
247 mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE, 247 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
248 LSMINI_NOR_BOOT_SIZE); 248 ORION_MBUS_DEVBUS_BOOT_ATTR,
249 LSMINI_NOR_BOOT_BASE,
250 LSMINI_NOR_BOOT_SIZE);
249 platform_device_register(&lsmini_nor_flash); 251 platform_device_register(&lsmini_nor_flash);
250 252
251 platform_device_register(&lsmini_button_device); 253 platform_device_register(&lsmini_button_device);
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 827acbafc9dc..e105130ba51c 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -241,8 +241,10 @@ static void __init mss2_init(void)
241 orion5x_uart0_init(); 241 orion5x_uart0_init();
242 orion5x_xor_init(); 242 orion5x_xor_init();
243 243
244 mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE, 244 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
245 MSS2_NOR_BOOT_SIZE); 245 ORION_MBUS_DEVBUS_BOOT_ATTR,
246 MSS2_NOR_BOOT_BASE,
247 MSS2_NOR_BOOT_SIZE);
246 platform_device_register(&mss2_nor_flash); 248 platform_device_register(&mss2_nor_flash);
247 249
248 platform_device_register(&mss2_button_device); 250 platform_device_register(&mss2_button_device);
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 92600ae2b4b6..e032f01da49e 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -204,8 +204,10 @@ static void __init mv2120_init(void)
204 orion5x_uart0_init(); 204 orion5x_uart0_init();
205 orion5x_xor_init(); 205 orion5x_xor_init();
206 206
207 mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE, 207 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
208 MV2120_NOR_BOOT_SIZE); 208 ORION_MBUS_DEVBUS_BOOT_ATTR,
209 MV2120_NOR_BOOT_BASE,
210 MV2120_NOR_BOOT_SIZE);
209 platform_device_register(&mv2120_nor_flash); 211 platform_device_register(&mv2120_nor_flash);
210 212
211 platform_device_register(&mv2120_button_device); 213 platform_device_register(&mv2120_button_device);
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index dd0641a0d074..ba73dc7ffb9e 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -397,8 +397,10 @@ static void __init net2big_init(void)
397 net2big_sata_power_init(); 397 net2big_sata_power_init();
398 orion5x_sata_init(&net2big_sata_data); 398 orion5x_sata_init(&net2big_sata_data);
399 399
400 mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE, 400 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
401 NET2BIG_NOR_BOOT_SIZE); 401 ORION_MBUS_DEVBUS_BOOT_ATTR,
402 NET2BIG_NOR_BOOT_BASE,
403 NET2BIG_NOR_BOOT_SIZE);
402 platform_device_register(&net2big_nor_flash); 404 platform_device_register(&net2big_nor_flash);
403 405
404 platform_device_register(&net2big_gpio_buttons); 406 platform_device_register(&net2big_gpio_buttons);
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 503368023bb1..7fab67053030 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -157,11 +157,10 @@ static int __init pcie_setup(struct pci_sys_data *sys)
157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 "read transaction workaround\n"); 159 "read transaction workaround\n");
160 mvebu_mbus_add_window_remap_flags("pcie0.0", 160 mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
161 ORION5X_PCIE_WA_PHYS_BASE, 161 ORION_MBUS_PCIE_WA_ATTR,
162 ORION5X_PCIE_WA_SIZE, 162 ORION5X_PCIE_WA_PHYS_BASE,
163 MVEBU_MBUS_NO_REMAP, 163 ORION5X_PCIE_WA_SIZE);
164 MVEBU_MBUS_PCI_WA);
165 pcie_ops.read = pcie_rd_conf_wa; 164 pcie_ops.read = pcie_rd_conf_wa;
166 } 165 }
167 166
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 1c4498bf650a..213b3e143c57 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -123,8 +123,10 @@ static void __init rd88f5181l_fxo_init(void)
123 orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ); 123 orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
124 orion5x_uart0_init(); 124 orion5x_uart0_init();
125 125
126 mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE, 126 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
127 RD88F5181L_FXO_NOR_BOOT_SIZE); 127 ORION_MBUS_DEVBUS_BOOT_ATTR,
128 RD88F5181L_FXO_NOR_BOOT_BASE,
129 RD88F5181L_FXO_NOR_BOOT_SIZE);
128 platform_device_register(&rd88f5181l_fxo_nor_boot_flash); 130 platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
129} 131}
130 132
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index adabe34c4fc6..594800e1d691 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -130,8 +130,10 @@ static void __init rd88f5181l_ge_init(void)
130 orion5x_i2c_init(); 130 orion5x_i2c_init();
131 orion5x_uart0_init(); 131 orion5x_uart0_init();
132 132
133 mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE, 133 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
134 RD88F5181L_GE_NOR_BOOT_SIZE); 134 ORION_MBUS_DEVBUS_BOOT_ATTR,
135 RD88F5181L_GE_NOR_BOOT_BASE,
136 RD88F5181L_GE_NOR_BOOT_SIZE);
135 platform_device_register(&rd88f5181l_ge_nor_boot_flash); 137 platform_device_register(&rd88f5181l_ge_nor_boot_flash);
136 138
137 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1); 139 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 66e77ec91532..b1cf68493ffc 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -264,11 +264,14 @@ static void __init rd88f5182_init(void)
264 orion5x_uart0_init(); 264 orion5x_uart0_init();
265 orion5x_xor_init(); 265 orion5x_xor_init();
266 266
267 mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE, 267 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
268 RD88F5182_NOR_BOOT_SIZE); 268 ORION_MBUS_DEVBUS_BOOT_ATTR,
269 269 RD88F5182_NOR_BOOT_BASE,
270 mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE, 270 RD88F5182_NOR_BOOT_SIZE);
271 RD88F5182_NOR_SIZE); 271 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
272 ORION_MBUS_DEVBUS_ATTR(1),
273 RD88F5182_NOR_BASE,
274 RD88F5182_NOR_SIZE);
272 platform_device_register(&rd88f5182_nor_flash); 275 platform_device_register(&rd88f5182_nor_flash);
273 platform_device_register(&rd88f5182_gpio_leds); 276 platform_device_register(&rd88f5182_gpio_leds);
274 277
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index a0bfa53e7556..7e9064844698 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -329,8 +329,10 @@ static void __init tsp2_init(void)
329 /* 329 /*
330 * Configure peripherals. 330 * Configure peripherals.
331 */ 331 */
332 mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE, 332 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
333 TSP2_NOR_BOOT_SIZE); 333 ORION_MBUS_DEVBUS_BOOT_ATTR,
334 TSP2_NOR_BOOT_BASE,
335 TSP2_NOR_BOOT_SIZE);
334 platform_device_register(&tsp2_nor_flash); 336 platform_device_register(&tsp2_nor_flash);
335 337
336 orion5x_ehci0_init(); 338 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 80174f0f168e..e90c0618fdad 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -286,8 +286,10 @@ static void __init qnap_ts209_init(void)
286 /* 286 /*
287 * Configure peripherals. 287 * Configure peripherals.
288 */ 288 */
289 mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE, 289 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
290 QNAP_TS209_NOR_BOOT_SIZE); 290 ORION_MBUS_DEVBUS_BOOT_ATTR,
291 QNAP_TS209_NOR_BOOT_BASE,
292 QNAP_TS209_NOR_BOOT_SIZE);
291 platform_device_register(&qnap_ts209_nor_flash); 293 platform_device_register(&qnap_ts209_nor_flash);
292 294
293 orion5x_ehci0_init(); 295 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 92592790d6da..5c079d312015 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -277,8 +277,10 @@ static void __init qnap_ts409_init(void)
277 /* 277 /*
278 * Configure peripherals. 278 * Configure peripherals.
279 */ 279 */
280 mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE, 280 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
281 QNAP_TS409_NOR_BOOT_SIZE); 281 ORION_MBUS_DEVBUS_BOOT_ATTR,
282 QNAP_TS409_NOR_BOOT_BASE,
283 QNAP_TS409_NOR_BOOT_SIZE);
282 platform_device_register(&qnap_ts409_nor_flash); 284 platform_device_register(&qnap_ts409_nor_flash);
283 285
284 orion5x_ehci0_init(); 286 orion5x_ehci0_init();
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 6b84863c018d..80a56ee245b3 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -127,8 +127,10 @@ static void __init wnr854t_init(void)
127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ); 127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
128 orion5x_uart0_init(); 128 orion5x_uart0_init();
129 129
130 mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE, 130 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
131 WNR854T_NOR_BOOT_SIZE); 131 ORION_MBUS_DEVBUS_BOOT_ATTR,
132 WNR854T_NOR_BOOT_BASE,
133 WNR854T_NOR_BOOT_SIZE);
132 platform_device_register(&wnr854t_nor_flash); 134 platform_device_register(&wnr854t_nor_flash);
133} 135}
134 136
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fae684bc54f2..670e30dc0d1b 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -213,8 +213,10 @@ static void __init wrt350n_v2_init(void)
213 orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ); 213 orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
214 orion5x_uart0_init(); 214 orion5x_uart0_init();
215 215
216 mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE, 216 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
217 WRT350N_V2_NOR_BOOT_SIZE); 217 ORION_MBUS_DEVBUS_BOOT_ATTR,
218 WRT350N_V2_NOR_BOOT_BASE,
219 WRT350N_V2_NOR_BOOT_SIZE);
218 platform_device_register(&wrt350n_v2_nor_flash); 220 platform_device_register(&wrt350n_v2_nor_flash);
219 platform_device_register(&wrt350n_v2_leds); 221 platform_device_register(&wrt350n_v2_leds);
220 platform_device_register(&wrt350n_v2_button_device); 222 platform_device_register(&wrt350n_v2_button_device);
diff --git a/arch/arm/mach-prima2/pm.c b/arch/arm/mach-prima2/pm.c
index 02cc34388b05..c4525a88e5da 100644
--- a/arch/arm/mach-prima2/pm.c
+++ b/arch/arm/mach-prima2/pm.c
@@ -34,7 +34,10 @@ static void sirfsoc_set_wakeup_source(void)
34 pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base + 34 pwr_trigger_en_reg = sirfsoc_rtc_iobrg_readl(sirfsoc_pwrc_base +
35 SIRFSOC_PWRC_TRIGGER_EN); 35 SIRFSOC_PWRC_TRIGGER_EN);
36#define X_ON_KEY_B (1 << 0) 36#define X_ON_KEY_B (1 << 0)
37 sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B, 37#define RTC_ALARM0_B (1 << 2)
38#define RTC_ALARM1_B (1 << 3)
39 sirfsoc_rtc_iobrg_writel(pwr_trigger_en_reg | X_ON_KEY_B |
40 RTC_ALARM0_B | RTC_ALARM1_B,
38 sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN); 41 sirfsoc_pwrc_base + SIRFSOC_PWRC_TRIGGER_EN);
39} 42}
40 43
@@ -85,12 +88,6 @@ static const struct platform_suspend_ops sirfsoc_pm_ops = {
85 .valid = suspend_valid_only_mem, 88 .valid = suspend_valid_only_mem,
86}; 89};
87 90
88int __init sirfsoc_pm_init(void)
89{
90 suspend_set_ops(&sirfsoc_pm_ops);
91 return 0;
92}
93
94static const struct of_device_id pwrc_ids[] = { 91static const struct of_device_id pwrc_ids[] = {
95 { .compatible = "sirf,prima2-pwrc" }, 92 { .compatible = "sirf,prima2-pwrc" },
96 {} 93 {}
@@ -118,7 +115,6 @@ static int __init sirfsoc_of_pwrc_init(void)
118 115
119 return 0; 116 return 0;
120} 117}
121postcore_initcall(sirfsoc_of_pwrc_init);
122 118
123static const struct of_device_id memc_ids[] = { 119static const struct of_device_id memc_ids[] = {
124 { .compatible = "sirf,prima2-memc" }, 120 { .compatible = "sirf,prima2-memc" },
@@ -149,4 +145,11 @@ static int __init sirfsoc_memc_init(void)
149{ 145{
150 return platform_driver_register(&sirfsoc_memc_driver); 146 return platform_driver_register(&sirfsoc_memc_driver);
151} 147}
152postcore_initcall(sirfsoc_memc_init); 148
149int __init sirfsoc_pm_init(void)
150{
151 sirfsoc_of_pwrc_init();
152 sirfsoc_memc_init();
153 suspend_set_ops(&sirfsoc_pm_ops);
154 return 0;
155}
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index 8091aac89edf..f9423493ed36 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -29,7 +29,7 @@
29#include <linux/pwm_backlight.h> 29#include <linux/pwm_backlight.h>
30 30
31#include <linux/i2c.h> 31#include <linux/i2c.h>
32#include <linux/i2c/pca953x.h> 32#include <linux/platform_data/pca953x.h>
33#include <linux/i2c/pxa-i2c.h> 33#include <linux/i2c/pxa-i2c.h>
34 34
35#include <linux/mfd/da903x.h> 35#include <linux/mfd/da903x.h>
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 3a3362fa793e..8eb4e23c561d 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -30,7 +30,7 @@
30#include <linux/power_supply.h> 30#include <linux/power_supply.h>
31#include <linux/apm-emulation.h> 31#include <linux/apm-emulation.h>
32#include <linux/i2c.h> 32#include <linux/i2c.h>
33#include <linux/i2c/pca953x.h> 33#include <linux/platform_data/pca953x.h>
34#include <linux/i2c/pxa-i2c.h> 34#include <linux/i2c/pxa-i2c.h>
35#include <linux/regulator/userspace-consumer.h> 35#include <linux/regulator/userspace-consumer.h>
36 36
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 13e5b00eae90..3133ba82c508 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -408,7 +408,7 @@ struct pxacamera_platform_data pcm990_pxacamera_platform_data = {
408 .mclk_10khz = 1000, 408 .mclk_10khz = 1000,
409}; 409};
410 410
411#include <linux/i2c/pca953x.h> 411#include <linux/platform_data/pca953x.h>
412 412
413static struct pca953x_platform_data pca9536_data = { 413static struct pca953x_platform_data pca9536_data = {
414 .gpio_base = PXA_NR_BUILTIN_GPIO, 414 .gpio_base = PXA_NR_BUILTIN_GPIO,
diff --git a/arch/arm/mach-pxa/pxa-dt.c b/arch/arm/mach-pxa/pxa-dt.c
index 3835979a0dd3..f6a2c4b1c1dc 100644
--- a/arch/arm/mach-pxa/pxa-dt.c
+++ b/arch/arm/mach-pxa/pxa-dt.c
@@ -28,7 +28,7 @@ static const struct of_dev_auxdata pxa3xx_auxdata_lookup[] __initconst = {
28 OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL), 28 OF_DEV_AUXDATA("mrvl,pxa-uart", 0x40700000, "pxa2xx-uart.2", NULL),
29 OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL), 29 OF_DEV_AUXDATA("mrvl,pxa-uart", 0x41600000, "pxa2xx-uart.3", NULL),
30 OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL), 30 OF_DEV_AUXDATA("marvell,pxa-mmc", 0x41100000, "pxa2xx-mci.0", NULL),
31 OF_DEV_AUXDATA("mrvl,pxa-gpio", 0x40e00000, "pxa-gpio", NULL), 31 OF_DEV_AUXDATA("intel,pxa3xx-gpio", 0x40e00000, "pxa3xx-gpio", NULL),
32 OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL), 32 OF_DEV_AUXDATA("marvell,pxa-ohci", 0x4c000000, "pxa27x-ohci", NULL),
33 OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL), 33 OF_DEV_AUXDATA("mrvl,pxa-i2c", 0x40301680, "pxa2xx-i2c.0", NULL),
34 OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL), 34 OF_DEV_AUXDATA("mrvl,pwri2c", 0x40f500c0, "pxa3xx-i2c.1", NULL),
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 4c29173026e8..0b11c1af51c4 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -20,7 +20,7 @@
20#include <linux/leds.h> 20#include <linux/leds.h>
21#include <linux/i2c.h> 21#include <linux/i2c.h>
22#include <linux/i2c/pxa-i2c.h> 22#include <linux/i2c/pxa-i2c.h>
23#include <linux/i2c/pca953x.h> 23#include <linux/platform_data/pca953x.h>
24#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
25#include <linux/spi/ads7846.h> 25#include <linux/spi/ads7846.h>
26#include <linux/spi/corgi_lcd.h> 26#include <linux/spi/corgi_lcd.h>
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 04a0aea23873..b19d1c361cab 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -26,7 +26,7 @@
26#include <linux/mtd/physmap.h> 26#include <linux/mtd/physmap.h>
27#include <linux/i2c.h> 27#include <linux/i2c.h>
28#include <linux/i2c/pxa-i2c.h> 28#include <linux/i2c/pxa-i2c.h>
29#include <linux/i2c/pca953x.h> 29#include <linux/platform_data/pca953x.h>
30#include <linux/apm-emulation.h> 30#include <linux/apm-emulation.h>
31#include <linux/can/platform/mcp251x.h> 31#include <linux/can/platform/mcp251x.h>
32#include <linux/regulator/fixed.h> 32#include <linux/regulator/fixed.h>
diff --git a/arch/arm/mach-pxa/zylonite_pxa300.c b/arch/arm/mach-pxa/zylonite_pxa300.c
index 86e59c043de2..869bce7c3f24 100644
--- a/arch/arm/mach-pxa/zylonite_pxa300.c
+++ b/arch/arm/mach-pxa/zylonite_pxa300.c
@@ -18,7 +18,7 @@
18#include <linux/init.h> 18#include <linux/init.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/i2c/pxa-i2c.h> 20#include <linux/i2c/pxa-i2c.h>
21#include <linux/i2c/pca953x.h> 21#include <linux/platform_data/pca953x.h>
22#include <linux/gpio.h> 22#include <linux/gpio.h>
23 23
24#include <mach/pxa300.h> 24#include <mach/pxa300.h>
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d210c0f9c2c4..9db2029aa632 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -13,7 +13,7 @@ config REALVIEW_EB_A9MP
13 depends on MACH_REALVIEW_EB 13 depends on MACH_REALVIEW_EB
14 select CPU_V7 14 select CPU_V7
15 select HAVE_ARM_SCU if SMP 15 select HAVE_ARM_SCU if SMP
16 select HAVE_ARM_TWD if LOCAL_TIMERS 16 select HAVE_ARM_TWD if SMP
17 select HAVE_SMP 17 select HAVE_SMP
18 select MIGHT_HAVE_CACHE_L2X0 18 select MIGHT_HAVE_CACHE_L2X0
19 help 19 help
@@ -26,7 +26,7 @@ config REALVIEW_EB_ARM11MP
26 select ARCH_HAS_BARRIERS if SMP 26 select ARCH_HAS_BARRIERS if SMP
27 select CPU_V6K 27 select CPU_V6K
28 select HAVE_ARM_SCU if SMP 28 select HAVE_ARM_SCU if SMP
29 select HAVE_ARM_TWD if LOCAL_TIMERS 29 select HAVE_ARM_TWD if SMP
30 select HAVE_SMP 30 select HAVE_SMP
31 select MIGHT_HAVE_CACHE_L2X0 31 select MIGHT_HAVE_CACHE_L2X0
32 help 32 help
@@ -48,7 +48,7 @@ config MACH_REALVIEW_PB11MP
48 select ARM_GIC 48 select ARM_GIC
49 select CPU_V6K 49 select CPU_V6K
50 select HAVE_ARM_SCU if SMP 50 select HAVE_ARM_SCU if SMP
51 select HAVE_ARM_TWD if LOCAL_TIMERS 51 select HAVE_ARM_TWD if SMP
52 select HAVE_PATA_PLATFORM 52 select HAVE_PATA_PLATFORM
53 select HAVE_SMP 53 select HAVE_SMP
54 select MIGHT_HAVE_CACHE_L2X0 54 select MIGHT_HAVE_CACHE_L2X0
@@ -92,7 +92,7 @@ config MACH_REALVIEW_PBX
92 select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET 92 select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET
93 select ARM_GIC 93 select ARM_GIC
94 select HAVE_ARM_SCU if SMP 94 select HAVE_ARM_SCU if SMP
95 select HAVE_ARM_TWD if LOCAL_TIMERS 95 select HAVE_ARM_TWD if SMP
96 select HAVE_PATA_PLATFORM 96 select HAVE_PATA_PLATFORM
97 select HAVE_SMP 97 select HAVE_SMP
98 select MIGHT_HAVE_CACHE_L2X0 98 select MIGHT_HAVE_CACHE_L2X0
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 7791ac76f945..dba2173e70f3 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -30,7 +30,6 @@ config CPU_S3C2410
30 select S3C2410_CLOCK 30 select S3C2410_CLOCK
31 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ 31 select ARM_S3C2410_CPUFREQ if ARM_S3C24XX_CPUFREQ
32 select S3C2410_PM if PM 32 select S3C2410_PM if PM
33 select SAMSUNG_HRT
34 select SAMSUNG_WDT_RESET 33 select SAMSUNG_WDT_RESET
35 help 34 help
36 Support for S3C2410 and S3C2410A family from the S3C24XX line 35 Support for S3C2410 and S3C2410A family from the S3C24XX line
@@ -42,7 +41,6 @@ config CPU_S3C2412
42 select CPU_LLSERIAL_S3C2440 41 select CPU_LLSERIAL_S3C2440
43 select S3C2412_DMA if S3C24XX_DMA 42 select S3C2412_DMA if S3C24XX_DMA
44 select S3C2412_PM if PM 43 select S3C2412_PM if PM
45 select SAMSUNG_HRT
46 help 44 help
47 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line 45 Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line
48 46
@@ -54,7 +52,6 @@ config CPU_S3C2416
54 select S3C2443_COMMON 52 select S3C2443_COMMON
55 select S3C2443_DMA if S3C24XX_DMA 53 select S3C2443_DMA if S3C24XX_DMA
56 select SAMSUNG_CLKSRC 54 select SAMSUNG_CLKSRC
57 select SAMSUNG_HRT
58 help 55 help
59 Support for the S3C2416 SoC from the S3C24XX line 56 Support for the S3C2416 SoC from the S3C24XX line
60 57
@@ -65,7 +62,6 @@ config CPU_S3C2440
65 select S3C2410_CLOCK 62 select S3C2410_CLOCK
66 select S3C2410_PM if PM 63 select S3C2410_PM if PM
67 select S3C2440_DMA if S3C24XX_DMA 64 select S3C2440_DMA if S3C24XX_DMA
68 select SAMSUNG_HRT
69 help 65 help
70 Support for S3C2440 Samsung Mobile CPU based systems. 66 Support for S3C2440 Samsung Mobile CPU based systems.
71 67
@@ -75,7 +71,6 @@ config CPU_S3C2442
75 select CPU_LLSERIAL_S3C2440 71 select CPU_LLSERIAL_S3C2440
76 select S3C2410_CLOCK 72 select S3C2410_CLOCK
77 select S3C2410_PM if PM 73 select S3C2410_PM if PM
78 select SAMSUNG_HRT
79 help 74 help
80 Support for S3C2442 Samsung Mobile CPU based systems. 75 Support for S3C2442 Samsung Mobile CPU based systems.
81 76
@@ -91,7 +86,6 @@ config CPU_S3C2443
91 select S3C2443_COMMON 86 select S3C2443_COMMON
92 select S3C2443_DMA if S3C24XX_DMA 87 select S3C2443_DMA if S3C24XX_DMA
93 select SAMSUNG_CLKSRC 88 select SAMSUNG_CLKSRC
94 select SAMSUNG_HRT
95 help 89 help
96 Support for the S3C2443 SoC from the S3C24XX line 90 Support for the S3C2443 SoC from the S3C24XX line
97 91
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 564553694b54..d39d3c787580 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -281,6 +281,5 @@ int __init s3c2410_baseclk_add(void)
281 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on", 281 (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
282 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on"); 282 (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
283 283
284 s3c_pwmclk_init();
285 return 0; 284 return 0;
286} 285}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index 2cc017da88fe..d8f253f2b486 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -757,6 +757,5 @@ int __init s3c2412_baseclk_add(void)
757 } 757 }
758 758
759 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup)); 759 clkdev_add_table(s3c2412_clk_lookup, ARRAY_SIZE(s3c2412_clk_lookup));
760 s3c_pwmclk_init();
761 return 0; 760 return 0;
762} 761}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 036056cea57c..d421a72920a5 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -168,6 +168,4 @@ void __init s3c2416_init_clocks(int xtal)
168 s3c24xx_register_clock(&hsmmc0_clk); 168 s3c24xx_register_clock(&hsmmc0_clk);
169 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup)); 169 clkdev_add_table(s3c2416_clk_lookup, ARRAY_SIZE(s3c2416_clk_lookup));
170 170
171 s3c_pwmclk_init();
172
173} 171}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index 0a53051b0787..76cd31f7804e 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -209,6 +209,4 @@ void __init s3c2443_init_clocks(int xtal)
209 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 209 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
210 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); 210 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
211 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup)); 211 clkdev_add_table(s3c2443_clk_lookup, ARRAY_SIZE(s3c2443_clk_lookup));
212
213 s3c_pwmclk_init();
214} 212}
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index c157103ed8eb..457261c98433 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -27,6 +27,7 @@
27#include <linux/interrupt.h> 27#include <linux/interrupt.h>
28#include <linux/ioport.h> 28#include <linux/ioport.h>
29#include <linux/serial_core.h> 29#include <linux/serial_core.h>
30#include <clocksource/samsung_pwm.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
31#include <linux/delay.h> 32#include <linux/delay.h>
32#include <linux/io.h> 33#include <linux/io.h>
@@ -49,6 +50,7 @@
49#include <plat/clock.h> 50#include <plat/clock.h>
50#include <plat/cpu-freq.h> 51#include <plat/cpu-freq.h>
51#include <plat/pll.h> 52#include <plat/pll.h>
53#include <plat/pwm-core.h>
52 54
53#include "common.h" 55#include "common.h"
54 56
@@ -216,6 +218,13 @@ static void s3c24xx_default_idle(void)
216 S3C2410_CLKCON); 218 S3C2410_CLKCON);
217} 219}
218 220
221static struct samsung_pwm_variant s3c24xx_pwm_variant = {
222 .bits = 16,
223 .div_base = 1,
224 .has_tint_cstat = false,
225 .tclk_mask = (1 << 4),
226};
227
219void __init s3c24xx_init_io(struct map_desc *mach_desc, int size) 228void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
220{ 229{
221 arm_pm_idle = s3c24xx_default_idle; 230 arm_pm_idle = s3c24xx_default_idle;
@@ -232,6 +241,24 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
232 s3c24xx_init_cpu(); 241 s3c24xx_init_cpu();
233 242
234 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 243 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
244
245 samsung_pwm_set_platdata(&s3c24xx_pwm_variant);
246}
247
248void __init samsung_set_timer_source(unsigned int event, unsigned int source)
249{
250 s3c24xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
251 s3c24xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
252}
253
254void __init samsung_timer_init(void)
255{
256 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
257 IRQ_TIMER0, IRQ_TIMER1, IRQ_TIMER2, IRQ_TIMER3, IRQ_TIMER4,
258 };
259
260 samsung_pwm_clocksource_init(S3C_VA_TIMER,
261 timer_irqs, &s3c24xx_pwm_variant);
235} 262}
236 263
237/* Serial port registrations */ 264/* Serial port registrations */
diff --git a/arch/arm/mach-s3c24xx/include/mach/map.h b/arch/arm/mach-s3c24xx/include/mach/map.h
index 8ba381f2dbe1..444793f0f5f1 100644
--- a/arch/arm/mach-s3c24xx/include/mach/map.h
+++ b/arch/arm/mach-s3c24xx/include/mach/map.h
@@ -167,4 +167,6 @@
167#define S3C_PA_SPI0 S3C2443_PA_SPI0 167#define S3C_PA_SPI0 S3C2443_PA_SPI0
168#define S3C_PA_SPI1 S3C2443_PA_SPI1 168#define S3C_PA_SPI1 S3C2443_PA_SPI1
169 169
170#define SAMSUNG_PA_TIMER S3C2410_PA_TIMER
171
170#endif /* __ASM_ARCH_MAP_H */ 172#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
index af4334d6b4d5..74dd47988b41 100644
--- a/arch/arm/mach-s3c24xx/mach-h1940.c
+++ b/arch/arm/mach-s3c24xx/mach-h1940.c
@@ -512,7 +512,7 @@ static struct platform_pwm_backlight_data backlight_data = {
512static struct platform_device h1940_backlight = { 512static struct platform_device h1940_backlight = {
513 .name = "pwm-backlight", 513 .name = "pwm-backlight",
514 .dev = { 514 .dev = {
515 .parent = &s3c_device_timer[0].dev, 515 .parent = &samsung_device_pwm.dev,
516 .platform_data = &backlight_data, 516 .platform_data = &backlight_data,
517 }, 517 },
518 .id = -1, 518 .id = -1,
@@ -632,7 +632,7 @@ static struct platform_device *h1940_devices[] __initdata = {
632 &h1940_device_bluetooth, 632 &h1940_device_bluetooth,
633 &s3c_device_sdi, 633 &s3c_device_sdi,
634 &s3c_device_rtc, 634 &s3c_device_rtc,
635 &s3c_device_timer[0], 635 &samsung_device_pwm,
636 &h1940_backlight, 636 &h1940_backlight,
637 &h1940_lcd_powerdev, 637 &h1940_lcd_powerdev,
638 &s3c_device_adc, 638 &s3c_device_adc,
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index 44ca018e1f96..206b1f7546d1 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -530,7 +530,7 @@ static struct platform_pwm_backlight_data rx1950_backlight_data = {
530static struct platform_device rx1950_backlight = { 530static struct platform_device rx1950_backlight = {
531 .name = "pwm-backlight", 531 .name = "pwm-backlight",
532 .dev = { 532 .dev = {
533 .parent = &s3c_device_timer[0].dev, 533 .parent = &samsung_device_pwm.dev,
534 .platform_data = &rx1950_backlight_data, 534 .platform_data = &rx1950_backlight_data,
535 }, 535 },
536}; 536};
@@ -717,8 +717,7 @@ static struct platform_device *rx1950_devices[] __initdata = {
717 &s3c_device_sdi, 717 &s3c_device_sdi,
718 &s3c_device_adc, 718 &s3c_device_adc,
719 &s3c_device_ts, 719 &s3c_device_ts,
720 &s3c_device_timer[0], 720 &samsung_device_pwm,
721 &s3c_device_timer[1],
722 &rx1950_backlight, 721 &rx1950_backlight,
723 &rx1950_device_gpiokeys, 722 &rx1950_device_gpiokeys,
724 &power_supply, 723 &power_supply,
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index 20578536aec7..041da5172423 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -17,13 +17,11 @@ config PLAT_S3C64XX
17# Configuration options for the S3C6410 CPU 17# Configuration options for the S3C6410 CPU
18 18
19config CPU_S3C6400 19config CPU_S3C6400
20 select SAMSUNG_HRT
21 bool 20 bool
22 help 21 help
23 Enable S3C6400 CPU support 22 Enable S3C6400 CPU support
24 23
25config CPU_S3C6410 24config CPU_S3C6410
26 select SAMSUNG_HRT
27 bool 25 bool
28 help 26 help
29 Enable S3C6410 CPU support 27 Enable S3C6410 CPU support
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 8499415be9cd..c1bcc4a6d3a8 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -1004,6 +1004,4 @@ void __init s3c64xx_register_clocks(unsigned long xtal,
1004 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++) 1004 for (cnt = 0; cnt < ARRAY_SIZE(clksrc_cdev); cnt++)
1005 s3c_register_clksrc(clksrc_cdev[cnt], 1); 1005 s3c_register_clksrc(clksrc_cdev[cnt], 1);
1006 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup)); 1006 clkdev_add_table(s3c64xx_clk_lookup, ARRAY_SIZE(s3c64xx_clk_lookup));
1007
1008 s3c_pwmclk_init();
1009} 1007}
diff --git a/arch/arm/mach-s3c64xx/common.c b/arch/arm/mach-s3c64xx/common.c
index 3f62e467b129..73d79cf5e141 100644
--- a/arch/arm/mach-s3c64xx/common.c
+++ b/arch/arm/mach-s3c64xx/common.c
@@ -27,6 +27,7 @@
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/irqchip/arm-vic.h> 29#include <linux/irqchip/arm-vic.h>
30#include <clocksource/samsung_pwm.h>
30 31
31#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
32#include <asm/mach/map.h> 33#include <asm/mach/map.h>
@@ -42,7 +43,7 @@
42#include <plat/pm.h> 43#include <plat/pm.h>
43#include <plat/gpio-cfg.h> 44#include <plat/gpio-cfg.h>
44#include <plat/irq-uart.h> 45#include <plat/irq-uart.h>
45#include <plat/irq-vic-timer.h> 46#include <plat/pwm-core.h>
46#include <plat/regs-irqtype.h> 47#include <plat/regs-irqtype.h>
47#include <plat/regs-serial.h> 48#include <plat/regs-serial.h>
48#include <plat/watchdog-reset.h> 49#include <plat/watchdog-reset.h>
@@ -149,6 +150,30 @@ static struct device s3c64xx_dev = {
149 .bus = &s3c64xx_subsys, 150 .bus = &s3c64xx_subsys,
150}; 151};
151 152
153static struct samsung_pwm_variant s3c64xx_pwm_variant = {
154 .bits = 32,
155 .div_base = 0,
156 .has_tint_cstat = true,
157 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
158};
159
160void __init samsung_set_timer_source(unsigned int event, unsigned int source)
161{
162 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
163 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
164}
165
166void __init samsung_timer_init(void)
167{
168 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
169 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
170 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
171 };
172
173 samsung_pwm_clocksource_init(S3C_VA_TIMER,
174 timer_irqs, &s3c64xx_pwm_variant);
175}
176
152/* read cpu identification code */ 177/* read cpu identification code */
153 178
154void __init s3c64xx_init_io(struct map_desc *mach_desc, int size) 179void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
@@ -161,6 +186,8 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
161 s3c64xx_init_cpu(); 186 s3c64xx_init_cpu();
162 187
163 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 188 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
189
190 samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
164} 191}
165 192
166static __init int s3c64xx_dev_init(void) 193static __init int s3c64xx_dev_init(void)
@@ -195,9 +222,6 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
195 /* initialise the pair of VICs */ 222 /* initialise the pair of VICs */
196 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME); 223 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
197 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME); 224 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
198
199 /* add the timer sub-irqs */
200 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
201} 225}
202 226
203#define eint_offset(irq) ((irq) - IRQ_EINT(0)) 227#define eint_offset(irq) ((irq) - IRQ_EINT(0))
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 96d60e0d9372..67bbd1dd04c2 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -107,14 +107,6 @@
107#define IRQ_TC IRQ_PENDN 107#define IRQ_TC IRQ_PENDN
108#define IRQ_ADC S3C64XX_IRQ_VIC1(31) 108#define IRQ_ADC S3C64XX_IRQ_VIC1(31)
109 109
110#define S3C64XX_TIMER_IRQ(x) S3C_IRQ(64 + (x))
111
112#define IRQ_TIMER0 S3C64XX_TIMER_IRQ(0)
113#define IRQ_TIMER1 S3C64XX_TIMER_IRQ(1)
114#define IRQ_TIMER2 S3C64XX_TIMER_IRQ(2)
115#define IRQ_TIMER3 S3C64XX_TIMER_IRQ(3)
116#define IRQ_TIMER4 S3C64XX_TIMER_IRQ(4)
117
118/* compatibility for device defines */ 110/* compatibility for device defines */
119 111
120#define IRQ_IIC1 IRQ_S3C6410_IIC1 112#define IRQ_IIC1 IRQ_S3C6410_IIC1
diff --git a/arch/arm/mach-s3c64xx/include/mach/map.h b/arch/arm/mach-s3c64xx/include/mach/map.h
index 8e2097bb208a..f55ccb1ce893 100644
--- a/arch/arm/mach-s3c64xx/include/mach/map.h
+++ b/arch/arm/mach-s3c64xx/include/mach/map.h
@@ -121,5 +121,6 @@
121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC 121#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON 122#define SAMSUNG_PA_CFCON S3C64XX_PA_CFCON
123#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD 123#define SAMSUNG_PA_KEYPAD S3C64XX_PA_KEYPAD
124#define SAMSUNG_PA_TIMER S3C64XX_PA_TIMER
124 125
125#endif /* __ASM_ARCH_6400_MAP_H */ 126#endif /* __ASM_ARCH_6400_MAP_H */
diff --git a/arch/arm/mach-s3c64xx/irq-pm.c b/arch/arm/mach-s3c64xx/irq-pm.c
index 0c7e1d960ca4..c3da1b68d03e 100644
--- a/arch/arm/mach-s3c64xx/irq-pm.c
+++ b/arch/arm/mach-s3c64xx/irq-pm.c
@@ -22,7 +22,6 @@
22#include <mach/map.h> 22#include <mach/map.h>
23 23
24#include <plat/regs-serial.h> 24#include <plat/regs-serial.h>
25#include <plat/regs-timer.h>
26#include <mach/regs-gpio.h> 25#include <mach/regs-gpio.h>
27#include <plat/cpu.h> 26#include <plat/cpu.h>
28#include <plat/pm.h> 27#include <plat/pm.h>
@@ -43,7 +42,6 @@ static struct sleep_save irq_save[] = {
43 SAVE_ITEM(S3C64XX_EINT0FLTCON2), 42 SAVE_ITEM(S3C64XX_EINT0FLTCON2),
44 SAVE_ITEM(S3C64XX_EINT0FLTCON3), 43 SAVE_ITEM(S3C64XX_EINT0FLTCON3),
45 SAVE_ITEM(S3C64XX_EINT0MASK), 44 SAVE_ITEM(S3C64XX_EINT0MASK),
46 SAVE_ITEM(S3C64XX_TINT_CSTAT),
47}; 45};
48 46
49static struct irq_grp_save { 47static struct irq_grp_save {
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index 8ad88ace795a..eb8e5a1aca42 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -30,7 +30,7 @@
30#include <linux/basic_mmio_gpio.h> 30#include <linux/basic_mmio_gpio.h>
31#include <linux/spi/spi.h> 31#include <linux/spi/spi.h>
32 32
33#include <linux/i2c/pca953x.h> 33#include <linux/platform_data/pca953x.h>
34#include <linux/platform_data/s3c-hsotg.h> 34#include <linux/platform_data/s3c-hsotg.h>
35 35
36#include <video/platform_lcd.h> 36#include <video/platform_lcd.h>
@@ -120,7 +120,7 @@ static struct platform_device crag6410_backlight_device = {
120 .name = "pwm-backlight", 120 .name = "pwm-backlight",
121 .id = -1, 121 .id = -1,
122 .dev = { 122 .dev = {
123 .parent = &s3c_device_timer[0].dev, 123 .parent = &samsung_device_pwm.dev,
124 .platform_data = &crag6410_backlight_data, 124 .platform_data = &crag6410_backlight_data,
125 }, 125 },
126}; 126};
@@ -375,7 +375,7 @@ static struct platform_device *crag6410_devices[] __initdata = {
375 &s3c_device_fb, 375 &s3c_device_fb,
376 &s3c_device_ohci, 376 &s3c_device_ohci,
377 &s3c_device_usb_hsotg, 377 &s3c_device_usb_hsotg,
378 &s3c_device_timer[0], 378 &samsung_device_pwm,
379 &s3c64xx_device_iis0, 379 &s3c64xx_device_iis0,
380 &s3c64xx_device_iis1, 380 &s3c64xx_device_iis1,
381 &samsung_device_keypad, 381 &samsung_device_keypad,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index 5b7f357d8c22..f39569e0f2e6 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -123,7 +123,7 @@ static struct platform_pwm_backlight_data hmt_backlight_data = {
123static struct platform_device hmt_backlight_device = { 123static struct platform_device hmt_backlight_device = {
124 .name = "pwm-backlight", 124 .name = "pwm-backlight",
125 .dev = { 125 .dev = {
126 .parent = &s3c_device_timer[1].dev, 126 .parent = &samsung_device_pwm.dev,
127 .platform_data = &hmt_backlight_data, 127 .platform_data = &hmt_backlight_data,
128 }, 128 },
129}; 129};
@@ -239,7 +239,7 @@ static struct platform_device *hmt_devices[] __initdata = {
239 &s3c_device_nand, 239 &s3c_device_nand,
240 &s3c_device_fb, 240 &s3c_device_fb,
241 &s3c_device_ohci, 241 &s3c_device_ohci,
242 &s3c_device_timer[1], 242 &samsung_device_pwm,
243 &hmt_backlight_device, 243 &hmt_backlight_device,
244 &hmt_leds_device, 244 &hmt_leds_device,
245}; 245};
diff --git a/arch/arm/mach-s3c64xx/mach-smartq.c b/arch/arm/mach-s3c64xx/mach-smartq.c
index 58ac99041274..86d980b448fd 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq.c
@@ -157,7 +157,7 @@ static struct platform_pwm_backlight_data smartq_backlight_data = {
157static struct platform_device smartq_backlight_device = { 157static struct platform_device smartq_backlight_device = {
158 .name = "pwm-backlight", 158 .name = "pwm-backlight",
159 .dev = { 159 .dev = {
160 .parent = &s3c_device_timer[1].dev, 160 .parent = &samsung_device_pwm.dev,
161 .platform_data = &smartq_backlight_data, 161 .platform_data = &smartq_backlight_data,
162 }, 162 },
163}; 163};
@@ -246,7 +246,7 @@ static struct platform_device *smartq_devices[] __initdata = {
246 &s3c_device_i2c0, 246 &s3c_device_i2c0,
247 &s3c_device_ohci, 247 &s3c_device_ohci,
248 &s3c_device_rtc, 248 &s3c_device_rtc,
249 &s3c_device_timer[1], 249 &samsung_device_pwm,
250 &s3c_device_ts, 250 &s3c_device_ts,
251 &s3c_device_usb_hsotg, 251 &s3c_device_usb_hsotg,
252 &s3c64xx_device_iis0, 252 &s3c64xx_device_iis0,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index bd3295a19ad7..d90b450c5645 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -274,6 +274,7 @@ static struct platform_device *smdk6410_devices[] __initdata = {
274 &s3c_device_i2c1, 274 &s3c_device_i2c1,
275 &s3c_device_fb, 275 &s3c_device_fb,
276 &s3c_device_ohci, 276 &s3c_device_ohci,
277 &samsung_device_pwm,
277 &s3c_device_usb_hsotg, 278 &s3c_device_usb_hsotg,
278 &s3c64xx_device_iisv4, 279 &s3c64xx_device_iisv4,
279 &samsung_device_keypad, 280 &samsung_device_keypad,
@@ -691,9 +692,9 @@ static void __init smdk6410_machine_init(void)
691 692
692 s3c_ide_set_platdata(&smdk6410_ide_pdata); 693 s3c_ide_set_platdata(&smdk6410_ide_pdata);
693 694
694 samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
695
696 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices)); 695 platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
696
697 samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
697} 698}
698 699
699MACHINE_START(SMDK6410, "SMDK6410") 700MACHINE_START(SMDK6410, "SMDK6410")
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 5a707bdb9ea0..bb2111b3751e 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -11,14 +11,12 @@ config CPU_S5P6440
11 bool 11 bool
12 select S5P_SLEEP if PM 12 select S5P_SLEEP if PM
13 select SAMSUNG_DMADEV 13 select SAMSUNG_DMADEV
14 select SAMSUNG_HRT
15 select SAMSUNG_WAKEMASK if PM 14 select SAMSUNG_WAKEMASK if PM
16 help 15 help
17 Enable S5P6440 CPU support 16 Enable S5P6440 CPU support
18 17
19config CPU_S5P6450 18config CPU_S5P6450
20 bool 19 bool
21 select SAMSUNG_HRT
22 select S5P_SLEEP if PM 20 select S5P_SLEEP if PM
23 select SAMSUNG_DMADEV 21 select SAMSUNG_DMADEV
24 select SAMSUNG_WAKEMASK if PM 22 select SAMSUNG_WAKEMASK if PM
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 3537815247f1..ae34a1d5e10a 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -629,6 +629,4 @@ void __init s5p6440_register_clocks(void)
629 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup)); 629 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
630 630
631 s3c24xx_register_clock(&dummy_apb_pclk); 631 s3c24xx_register_clock(&dummy_apb_pclk);
632
633 s3c_pwmclk_init();
634} 632}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index af384ddd2dcf..0b3ca2ed53e9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -698,6 +698,4 @@ void __init s5p6450_register_clocks(void)
698 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup)); 698 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
699 699
700 s3c24xx_register_clock(&dummy_apb_pclk); 700 s3c24xx_register_clock(&dummy_apb_pclk);
701
702 s3c_pwmclk_init();
703} 701}
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
index dfdfdc320ce7..42e14f2e7ca7 100644
--- a/arch/arm/mach-s5p64x0/common.c
+++ b/arch/arm/mach-s5p64x0/common.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20#include <linux/device.h> 20#include <linux/device.h>
21#include <linux/serial_core.h> 21#include <linux/serial_core.h>
22#include <clocksource/samsung_pwm.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <linux/sched.h> 24#include <linux/sched.h>
24#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
@@ -47,6 +48,7 @@
47#include <plat/fb-core.h> 48#include <plat/fb-core.h>
48#include <plat/spi-core.h> 49#include <plat/spi-core.h>
49#include <plat/gpio-cfg.h> 50#include <plat/gpio-cfg.h>
51#include <plat/pwm-core.h>
50#include <plat/regs-irqtype.h> 52#include <plat/regs-irqtype.h>
51#include <plat/regs-serial.h> 53#include <plat/regs-serial.h>
52#include <plat/watchdog-reset.h> 54#include <plat/watchdog-reset.h>
@@ -157,6 +159,30 @@ static void s5p64x0_idle(void)
157 cpu_do_idle(); 159 cpu_do_idle();
158} 160}
159 161
162static struct samsung_pwm_variant s5p64x0_pwm_variant = {
163 .bits = 32,
164 .div_base = 0,
165 .has_tint_cstat = true,
166 .tclk_mask = 0,
167};
168
169void __init samsung_set_timer_source(unsigned int event, unsigned int source)
170{
171 s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
172 s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
173}
174
175void __init samsung_timer_init(void)
176{
177 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
178 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
179 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
180 };
181
182 samsung_pwm_clocksource_init(S3C_VA_TIMER,
183 timer_irqs, &s5p64x0_pwm_variant);
184}
185
160/* 186/*
161 * s5p64x0_map_io 187 * s5p64x0_map_io
162 * 188 *
@@ -176,6 +202,7 @@ void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
176 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 202 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
177 samsung_wdt_reset_init(S3C_VA_WATCHDOG); 203 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
178 204
205 samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
179} 206}
180 207
181void __init s5p6440_map_io(void) 208void __init s5p6440_map_io(void)
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 5b845e849b30..53982db9d259 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -141,8 +141,6 @@
141 141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) 142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143 143
144#define IRQ_TIMER_BASE (11)
145
146/* Set the default NR_IRQS */ 144/* Set the default NR_IRQS */
147 145
148#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) 146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index 0c0175dbfa34..50a6e96d6389 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -76,6 +76,7 @@
76#define S5P_PA_TIMER S5P64X0_PA_TIMER 76#define S5P_PA_TIMER S5P64X0_PA_TIMER
77 77
78#define SAMSUNG_PA_ADC S5P64X0_PA_ADC 78#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
79#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER
79 80
80/* UART */ 81/* UART */
81 82
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 73f71a698a34..0b00304c1e91 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -162,6 +162,7 @@ static struct platform_device *smdk6440_devices[] __initdata = {
162 &s3c_device_rtc, 162 &s3c_device_rtc,
163 &s3c_device_i2c0, 163 &s3c_device_i2c0,
164 &s3c_device_i2c1, 164 &s3c_device_i2c1,
165 &samsung_device_pwm,
165 &s3c_device_ts, 166 &s3c_device_ts,
166 &s3c_device_wdt, 167 &s3c_device_wdt,
167 &s5p6440_device_iis, 168 &s5p6440_device_iis,
@@ -254,8 +255,6 @@ static void __init smdk6440_machine_init(void)
254 i2c_register_board_info(1, smdk6440_i2c_devs1, 255 i2c_register_board_info(1, smdk6440_i2c_devs1,
255 ARRAY_SIZE(smdk6440_i2c_devs1)); 256 ARRAY_SIZE(smdk6440_i2c_devs1));
256 257
257 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
258
259 s5p6440_set_lcd_interface(); 258 s5p6440_set_lcd_interface();
260 s3c_fb_set_platdata(&smdk6440_lcd_pdata); 259 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
261 260
@@ -264,6 +263,8 @@ static void __init smdk6440_machine_init(void)
264 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata); 263 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
265 264
266 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); 265 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
266
267 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
267} 268}
268 269
269MACHINE_START(SMDK6440, "SMDK6440") 270MACHINE_START(SMDK6440, "SMDK6440")
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 18303e12019f..5949296e88fd 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -180,6 +180,7 @@ static struct platform_device *smdk6450_devices[] __initdata = {
180 &s3c_device_rtc, 180 &s3c_device_rtc,
181 &s3c_device_i2c0, 181 &s3c_device_i2c0,
182 &s3c_device_i2c1, 182 &s3c_device_i2c1,
183 &samsung_device_pwm,
183 &s3c_device_ts, 184 &s3c_device_ts,
184 &s3c_device_wdt, 185 &s3c_device_wdt,
185 &s5p6450_device_iis0, 186 &s5p6450_device_iis0,
@@ -273,8 +274,6 @@ static void __init smdk6450_machine_init(void)
273 i2c_register_board_info(1, smdk6450_i2c_devs1, 274 i2c_register_board_info(1, smdk6450_i2c_devs1,
274 ARRAY_SIZE(smdk6450_i2c_devs1)); 275 ARRAY_SIZE(smdk6450_i2c_devs1));
275 276
276 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
277
278 s5p6450_set_lcd_interface(); 277 s5p6450_set_lcd_interface();
279 s3c_fb_set_platdata(&smdk6450_lcd_pdata); 278 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
280 279
@@ -283,6 +282,8 @@ static void __init smdk6450_machine_init(void)
283 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata); 282 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
284 283
285 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); 284 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
285
286 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
286} 287}
287 288
288MACHINE_START(SMDK6450, "SMDK6450") 289MACHINE_START(SMDK6450, "SMDK6450")
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
index 97c2a08ad490..861e15cea691 100644
--- a/arch/arm/mach-s5p64x0/pm.c
+++ b/arch/arm/mach-s5p64x0/pm.c
@@ -18,7 +18,6 @@
18 18
19#include <plat/cpu.h> 19#include <plat/cpu.h>
20#include <plat/pm.h> 20#include <plat/pm.h>
21#include <plat/regs-timer.h>
22#include <plat/wakeup-mask.h> 21#include <plat/wakeup-mask.h>
23 22
24#include <mach/regs-clock.h> 23#include <mach/regs-clock.h>
@@ -48,8 +47,6 @@ static struct sleep_save s5p64x0_misc_save[] = {
48 SAVE_ITEM(S5P64X0_MEM0CONSLP1), 47 SAVE_ITEM(S5P64X0_MEM0CONSLP1),
49 SAVE_ITEM(S5P64X0_MEM0DRVCON), 48 SAVE_ITEM(S5P64X0_MEM0DRVCON),
50 SAVE_ITEM(S5P64X0_MEM1DRVCON), 49 SAVE_ITEM(S5P64X0_MEM1DRVCON),
51
52 SAVE_ITEM(S3C64XX_TINT_CSTAT),
53}; 50};
54 51
55/* DPLL is present only in S5P6450 */ 52/* DPLL is present only in S5P6450 */
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 2f456a4533ba..15170be97a74 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -11,7 +11,6 @@ config CPU_S5PC100
11 bool 11 bool
12 select S5P_EXT_INT 12 select S5P_EXT_INT
13 select SAMSUNG_DMADEV 13 select SAMSUNG_DMADEV
14 select SAMSUNG_HRT
15 help 14 help
16 Enable S5PC100 CPU support 15 Enable S5PC100 CPU support
17 16
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index a206dc35eff1..d0dc10ee7729 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -1358,6 +1358,4 @@ void __init s5pc100_register_clocks(void)
1358 s3c_disable_clocks(clk_cdev[ptr], 1); 1358 s3c_disable_clocks(clk_cdev[ptr], 1);
1359 1359
1360 s3c24xx_register_clock(&dummy_apb_pclk); 1360 s3c24xx_register_clock(&dummy_apb_pclk);
1361
1362 s3c_pwmclk_init();
1363} 1361}
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
index 4bdfecf6d024..c5a8eeacf81c 100644
--- a/arch/arm/mach-s5pc100/common.c
+++ b/arch/arm/mach-s5pc100/common.c
@@ -22,6 +22,7 @@
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/device.h> 23#include <linux/device.h>
24#include <linux/serial_core.h> 24#include <linux/serial_core.h>
25#include <clocksource/samsung_pwm.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/sched.h> 27#include <linux/sched.h>
27#include <linux/reboot.h> 28#include <linux/reboot.h>
@@ -46,6 +47,7 @@
46#include <plat/fb-core.h> 47#include <plat/fb-core.h>
47#include <plat/iic-core.h> 48#include <plat/iic-core.h>
48#include <plat/onenand-core.h> 49#include <plat/onenand-core.h>
50#include <plat/pwm-core.h>
49#include <plat/spi-core.h> 51#include <plat/spi-core.h>
50#include <plat/regs-serial.h> 52#include <plat/regs-serial.h>
51#include <plat/watchdog-reset.h> 53#include <plat/watchdog-reset.h>
@@ -132,6 +134,30 @@ static struct map_desc s5pc100_iodesc[] __initdata = {
132 } 134 }
133}; 135};
134 136
137static struct samsung_pwm_variant s5pc100_pwm_variant = {
138 .bits = 32,
139 .div_base = 0,
140 .has_tint_cstat = true,
141 .tclk_mask = (1 << 5),
142};
143
144void __init samsung_set_timer_source(unsigned int event, unsigned int source)
145{
146 s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
147 s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
148}
149
150void __init samsung_timer_init(void)
151{
152 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
153 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
154 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
155 };
156
157 samsung_pwm_clocksource_init(S3C_VA_TIMER,
158 timer_irqs, &s5pc100_pwm_variant);
159}
160
135/* 161/*
136 * s5pc100_map_io 162 * s5pc100_map_io
137 * 163 *
@@ -149,6 +175,8 @@ void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
149 s5p_init_cpu(S5P_VA_CHIPID); 175 s5p_init_cpu(S5P_VA_CHIPID);
150 176
151 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 177 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
178
179 samsung_pwm_set_platdata(&s5pc100_pwm_variant);
152} 180}
153 181
154void __init s5pc100_map_io(void) 182void __init s5pc100_map_io(void)
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
index 2870f12c7926..d2eb4757381f 100644
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -97,8 +97,6 @@
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31) 97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31) 98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99 99
100#define IRQ_TIMER_BASE (11)
101
102#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
103#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
104 102
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 54bc4f82e17a..2550b6112b82 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -116,6 +116,7 @@
116#define SAMSUNG_PA_ADC S5PC100_PA_TSADC 116#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
117#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON 117#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
118#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD 118#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
119#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER
119 120
120#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) 121#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
121 122
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 8c880f76f274..7c57a221785e 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -194,6 +194,7 @@ static struct platform_device *smdkc100_devices[] __initdata = {
194 &s3c_device_hsmmc0, 194 &s3c_device_hsmmc0,
195 &s3c_device_hsmmc1, 195 &s3c_device_hsmmc1,
196 &s3c_device_hsmmc2, 196 &s3c_device_hsmmc2,
197 &samsung_device_pwm,
197 &s3c_device_ts, 198 &s3c_device_ts,
198 &s3c_device_wdt, 199 &s3c_device_wdt,
199 &smdkc100_lcd_powerdev, 200 &smdkc100_lcd_powerdev,
@@ -246,9 +247,9 @@ static void __init smdkc100_machine_init(void)
246 gpio_request(S5PC100_GPH0(6), "GPH0"); 247 gpio_request(S5PC100_GPH0(6), "GPH0");
247 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); 248 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
248 249
249 samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
250
251 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); 250 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
251
252 samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
252} 253}
253 254
254MACHINE_START(SMDKC100, "SMDKC100") 255MACHINE_START(SMDKC100, "SMDKC100")
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 0963283a7c5d..caaedafbbf5f 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -15,7 +15,6 @@ config CPU_S5PV210
15 select S5P_PM if PM 15 select S5P_PM if PM
16 select S5P_SLEEP if PM 16 select S5P_SLEEP if PM
17 select SAMSUNG_DMADEV 17 select SAMSUNG_DMADEV
18 select SAMSUNG_HRT
19 help 18 help
20 Enable S5PV210 CPU support 19 Enable S5PV210 CPU support
21 20
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index f051f53e35b7..ca463724a3df 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -1362,5 +1362,4 @@ void __init s5pv210_register_clocks(void)
1362 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) 1362 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1363 s3c_disable_clocks(clk_cdev[ptr], 1); 1363 s3c_disable_clocks(clk_cdev[ptr], 1);
1364 1364
1365 s3c_pwmclk_init();
1366} 1365}
diff --git a/arch/arm/mach-s5pv210/common.c b/arch/arm/mach-s5pv210/common.c
index 023f1a796a9c..26027a29b8a1 100644
--- a/arch/arm/mach-s5pv210/common.c
+++ b/arch/arm/mach-s5pv210/common.c
@@ -19,6 +19,7 @@
19#include <linux/clk.h> 19#include <linux/clk.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/device.h> 21#include <linux/device.h>
22#include <clocksource/samsung_pwm.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23#include <linux/sched.h> 24#include <linux/sched.h>
24#include <linux/dma-mapping.h> 25#include <linux/dma-mapping.h>
@@ -42,6 +43,7 @@
42#include <plat/fimc-core.h> 43#include <plat/fimc-core.h>
43#include <plat/iic-core.h> 44#include <plat/iic-core.h>
44#include <plat/keypad-core.h> 45#include <plat/keypad-core.h>
46#include <plat/pwm-core.h>
45#include <plat/tv-core.h> 47#include <plat/tv-core.h>
46#include <plat/spi-core.h> 48#include <plat/spi-core.h>
47#include <plat/regs-serial.h> 49#include <plat/regs-serial.h>
@@ -148,6 +150,30 @@ void s5pv210_restart(enum reboot_mode mode, const char *cmd)
148 __raw_writel(0x1, S5P_SWRESET); 150 __raw_writel(0x1, S5P_SWRESET);
149} 151}
150 152
153static struct samsung_pwm_variant s5pv210_pwm_variant = {
154 .bits = 32,
155 .div_base = 0,
156 .has_tint_cstat = true,
157 .tclk_mask = (1 << 5),
158};
159
160void __init samsung_set_timer_source(unsigned int event, unsigned int source)
161{
162 s5pv210_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
163 s5pv210_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
164}
165
166void __init samsung_timer_init(void)
167{
168 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
169 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
170 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
171 };
172
173 samsung_pwm_clocksource_init(S3C_VA_TIMER,
174 timer_irqs, &s5pv210_pwm_variant);
175}
176
151/* 177/*
152 * s5pv210_map_io 178 * s5pv210_map_io
153 * 179 *
@@ -165,6 +191,8 @@ void __init s5pv210_init_io(struct map_desc *mach_desc, int size)
165 s5p_init_cpu(S5P_VA_CHIPID); 191 s5p_init_cpu(S5P_VA_CHIPID);
166 192
167 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); 193 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
194
195 samsung_pwm_set_platdata(&s5pv210_pwm_variant);
168} 196}
169 197
170void __init s5pv210_map_io(void) 198void __init s5pv210_map_io(void)
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index e777e010ed2e..5e0de3a31f3d 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -118,8 +118,6 @@
118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8) 118#define IRQ_MDNIE3 S5P_IRQ_VIC3(8)
119#define IRQ_VIC_END S5P_IRQ_VIC3(31) 119#define IRQ_VIC_END S5P_IRQ_VIC3(31)
120 120
121#define IRQ_TIMER_BASE (11)
122
123#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) 121#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
124#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) 122#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
125 123
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index b7c8a1917ffc..763929aca52d 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -139,6 +139,7 @@
139#define SAMSUNG_PA_ADC S5PV210_PA_ADC 139#define SAMSUNG_PA_ADC S5PV210_PA_ADC
140#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON 140#define SAMSUNG_PA_CFCON S5PV210_PA_CFCON
141#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD 141#define SAMSUNG_PA_KEYPAD S5PV210_PA_KEYPAD
142#define SAMSUNG_PA_TIMER S5PV210_PA_TIMER
142 143
143/* UART */ 144/* UART */
144 145
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index d50b6f124465..6d72bb992e38 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -218,6 +218,7 @@ static struct platform_device *smdkv210_devices[] __initdata = {
218 &s3c_device_i2c0, 218 &s3c_device_i2c0,
219 &s3c_device_i2c1, 219 &s3c_device_i2c1,
220 &s3c_device_i2c2, 220 &s3c_device_i2c2,
221 &samsung_device_pwm,
221 &s3c_device_rtc, 222 &s3c_device_rtc,
222 &s3c_device_ts, 223 &s3c_device_ts,
223 &s3c_device_usb_hsotg, 224 &s3c_device_usb_hsotg,
@@ -316,11 +317,11 @@ static void __init smdkv210_machine_init(void)
316 317
317 s3c_fb_set_platdata(&smdkv210_lcd0_pdata); 318 s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
318 319
319 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
320
321 s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata); 320 s3c_hsotg_set_platdata(&smdkv210_hsotg_pdata);
322 321
323 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices)); 322 platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
323
324 samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
324} 325}
325 326
326MACHINE_START(SMDKV210, "SMDKV210") 327MACHINE_START(SMDKV210, "SMDKV210")
diff --git a/arch/arm/mach-s5pv210/pm.c b/arch/arm/mach-s5pv210/pm.c
index 2b68a67b6e95..3cf3f9c8ddd1 100644
--- a/arch/arm/mach-s5pv210/pm.c
+++ b/arch/arm/mach-s5pv210/pm.c
@@ -21,7 +21,6 @@
21 21
22#include <plat/cpu.h> 22#include <plat/cpu.h>
23#include <plat/pm.h> 23#include <plat/pm.h>
24#include <plat/regs-timer.h>
25 24
26#include <mach/regs-irq.h> 25#include <mach/regs-irq.h>
27#include <mach/regs-clock.h> 26#include <mach/regs-clock.h>
@@ -77,15 +76,6 @@ static struct sleep_save s5pv210_core_save[] = {
77 /* Clock ETC */ 76 /* Clock ETC */
78 SAVE_ITEM(S5P_CLK_OUT), 77 SAVE_ITEM(S5P_CLK_OUT),
79 SAVE_ITEM(S5P_MDNIE_SEL), 78 SAVE_ITEM(S5P_MDNIE_SEL),
80
81 /* PWM Register */
82 SAVE_ITEM(S3C2410_TCFG0),
83 SAVE_ITEM(S3C2410_TCFG1),
84 SAVE_ITEM(S3C64XX_TINT_CSTAT),
85 SAVE_ITEM(S3C2410_TCON),
86 SAVE_ITEM(S3C2410_TCNTB(0)),
87 SAVE_ITEM(S3C2410_TCMPB(0)),
88 SAVE_ITEM(S3C2410_TCNTO(0)),
89}; 79};
90 80
91static int s5pv210_cpu_suspend(unsigned long arg) 81static int s5pv210_cpu_suspend(unsigned long arg)
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 3912ce91fee4..1f94c310c477 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -1,3 +1,41 @@
1config ARCH_SHMOBILE_MULTI
2 bool "SH-Mobile Series" if ARCH_MULTI_V7
3 depends on MMU
4 select CPU_V7
5 select GENERIC_CLOCKEVENTS
6 select HAVE_ARM_SCU if SMP
7 select HAVE_ARM_TWD if LOCAL_TIMERS
8 select HAVE_SMP
9 select ARM_GIC
10 select MIGHT_HAVE_CACHE_L2X0
11 select NO_IOPORT
12 select PINCTRL
13 select ARCH_REQUIRE_GPIOLIB
14 select CLKDEV_LOOKUP
15
16if ARCH_SHMOBILE_MULTI
17
18comment "SH-Mobile System Type"
19
20config ARCH_EMEV2
21 bool "Emma Mobile EV2"
22
23comment "SH-Mobile Board Type"
24
25config MACH_KZM9D_REFERENCE
26 bool "KZM9D board - Reference Device Tree Implementation"
27 depends on ARCH_EMEV2
28 select REGULATOR_FIXED_VOLTAGE if REGULATOR
29 ---help---
30 Use reference implementation of KZM9D board support
31 which makes a greater use of device tree at the expense
32 of not supporting a number of devices.
33
34 This is intended to aid developers
35
36comment "SH-Mobile System Configuration"
37endif
38
1if ARCH_SHMOBILE 39if ARCH_SHMOBILE
2 40
3comment "SH-Mobile System Type" 41comment "SH-Mobile System Type"
@@ -23,9 +61,10 @@ config ARCH_R8A73A4
23 select ARCH_WANT_OPTIONAL_GPIOLIB 61 select ARCH_WANT_OPTIONAL_GPIOLIB
24 select ARM_GIC 62 select ARM_GIC
25 select CPU_V7 63 select CPU_V7
26 select HAVE_ARM_ARCH_TIMER
27 select SH_CLK_CPG 64 select SH_CLK_CPG
28 select RENESAS_IRQC 65 select RENESAS_IRQC
66 select ARCH_HAS_CPUFREQ
67 select ARCH_HAS_OPP
29 68
30config ARCH_R8A7740 69config ARCH_R8A7740
31 bool "R-Mobile A1 (R8A77400)" 70 bool "R-Mobile A1 (R8A77400)"
@@ -59,7 +98,6 @@ config ARCH_R8A7790
59 select ARCH_WANT_OPTIONAL_GPIOLIB 98 select ARCH_WANT_OPTIONAL_GPIOLIB
60 select ARM_GIC 99 select ARM_GIC
61 select CPU_V7 100 select CPU_V7
62 select HAVE_ARM_ARCH_TIMER
63 select SH_CLK_CPG 101 select SH_CLK_CPG
64 select RENESAS_IRQC 102 select RENESAS_IRQC
65 103
@@ -71,18 +109,22 @@ config ARCH_EMEV2
71 109
72comment "SH-Mobile Board Type" 110comment "SH-Mobile Board Type"
73 111
74config MACH_AG5EVM
75 bool "AG5EVM board"
76 depends on ARCH_SH73A0
77 select ARCH_REQUIRE_GPIOLIB
78 select REGULATOR_FIXED_VOLTAGE if REGULATOR
79 select SH_LCD_MIPI_DSI
80
81config MACH_APE6EVM 112config MACH_APE6EVM
82 bool "APE6EVM board" 113 bool "APE6EVM board"
83 depends on ARCH_R8A73A4 114 depends on ARCH_R8A73A4
84 select USE_OF 115 select USE_OF
85 116
117config MACH_APE6EVM_REFERENCE
118 bool "APE6EVM board - Reference Device Tree Implementation"
119 depends on ARCH_R8A73A4
120 select USE_OF
121 ---help---
122 Use reference implementation of APE6EVM board support
123 which makes a greater use of device tree at the expense
124 of not supporting a number of devices.
125
126 This is intended to aid developers
127
86config MACH_MACKEREL 128config MACH_MACKEREL
87 bool "mackerel board" 129 bool "mackerel board"
88 depends on ARCH_SH7372 130 depends on ARCH_SH7372
@@ -91,12 +133,6 @@ config MACH_MACKEREL
91 select SND_SOC_AK4642 if SND_SIMPLE_CARD 133 select SND_SOC_AK4642 if SND_SIMPLE_CARD
92 select USE_OF 134 select USE_OF
93 135
94config MACH_KOTA2
95 bool "KOTA2 board"
96 depends on ARCH_SH73A0
97 select ARCH_REQUIRE_GPIOLIB
98 select REGULATOR_FIXED_VOLTAGE if REGULATOR
99
100config MACH_ARMADILLO800EVA 136config MACH_ARMADILLO800EVA
101 bool "Armadillo-800 EVA board" 137 bool "Armadillo-800 EVA board"
102 depends on ARCH_R8A7740 138 depends on ARCH_R8A7740
@@ -124,13 +160,29 @@ config MACH_BOCKW
124 depends on ARCH_R8A7778 160 depends on ARCH_R8A7778
125 select ARCH_REQUIRE_GPIOLIB 161 select ARCH_REQUIRE_GPIOLIB
126 select RENESAS_INTC_IRQPIN 162 select RENESAS_INTC_IRQPIN
163 select REGULATOR_FIXED_VOLTAGE if REGULATOR
164 select USE_OF
165
166config MACH_BOCKW_REFERENCE
167 bool "BOCK-W - Reference Device Tree Implementation"
168 depends on ARCH_R8A7778
169 select ARCH_REQUIRE_GPIOLIB
170 select RENESAS_INTC_IRQPIN
171 select REGULATOR_FIXED_VOLTAGE if REGULATOR
127 select USE_OF 172 select USE_OF
173 ---help---
174 Use reference implementation of BockW board support
175 which makes use of device tree at the expense
176 of not supporting a number of devices.
177
178 This is intended to aid developers
128 179
129config MACH_MARZEN 180config MACH_MARZEN
130 bool "MARZEN board" 181 bool "MARZEN board"
131 depends on ARCH_R8A7779 182 depends on ARCH_R8A7779
132 select ARCH_REQUIRE_GPIOLIB 183 select ARCH_REQUIRE_GPIOLIB
133 select REGULATOR_FIXED_VOLTAGE if REGULATOR 184 select REGULATOR_FIXED_VOLTAGE if REGULATOR
185 select USE_OF
134 186
135config MACH_MARZEN_REFERENCE 187config MACH_MARZEN_REFERENCE
136 bool "MARZEN board - Reference Device Tree Implementation" 188 bool "MARZEN board - Reference Device Tree Implementation"
@@ -150,12 +202,35 @@ config MACH_LAGER
150 depends on ARCH_R8A7790 202 depends on ARCH_R8A7790
151 select USE_OF 203 select USE_OF
152 204
205config MACH_LAGER_REFERENCE
206 bool "Lager board - Reference Device Tree Implementation"
207 depends on ARCH_R8A7790
208 select USE_OF
209 ---help---
210 Use reference implementation of Lager board support
211 which makes use of device tree at the expense
212 of not supporting a number of devices.
213
214 This is intended to aid developers
215
153config MACH_KZM9D 216config MACH_KZM9D
154 bool "KZM9D board" 217 bool "KZM9D board"
155 depends on ARCH_EMEV2 218 depends on ARCH_EMEV2
156 select REGULATOR_FIXED_VOLTAGE if REGULATOR 219 select REGULATOR_FIXED_VOLTAGE if REGULATOR
157 select USE_OF 220 select USE_OF
158 221
222config MACH_KZM9D_REFERENCE
223 bool "KZM9D board - Reference Device Tree Implementation"
224 depends on ARCH_EMEV2
225 select REGULATOR_FIXED_VOLTAGE if REGULATOR
226 select USE_OF
227 ---help---
228 Use reference implementation of KZM9D board support
229 which makes a greater use of device tree at the expense
230 of not supporting a number of devices.
231
232 This is intended to aid developers
233
159config MACH_KZM9G 234config MACH_KZM9G
160 bool "KZM-A9-GT board" 235 bool "KZM-A9-GT board"
161 depends on ARCH_SH73A0 236 depends on ARCH_SH73A0
@@ -186,6 +261,15 @@ config CPU_HAS_INTEVT
186 bool 261 bool
187 default y 262 default y
188 263
264config SH_CLK_CPG
265 bool
266
267source "drivers/sh/Kconfig"
268
269endif
270
271if ARCH_SHMOBILE || ARCH_SHMOBILE_MULTI
272
189menu "Timer and clock configuration" 273menu "Timer and clock configuration"
190 274
191config SHMOBILE_TIMER_HZ 275config SHMOBILE_TIMER_HZ
@@ -220,9 +304,4 @@ config EM_TIMER_STI
220 304
221endmenu 305endmenu
222 306
223config SH_CLK_CPG
224 bool
225
226source "drivers/sh/Kconfig"
227
228endif 307endif
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 6165a517f580..2705bfa8c113 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -2,50 +2,65 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/arch/arm/mach-shmobile/include
6
5# Common objects 7# Common objects
6obj-y := timer.o console.o clock.o 8obj-y := timer.o console.o
7 9
8# CPU objects 10# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o clock-sh7372.o intc-sh7372.o 11obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o clock-sh73a0.o intc-sh73a0.o 12obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o clock-r8a73a4.o 13obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o clock-r8a7740.o intc-r8a7740.o 14obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o
13obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o clock-r8a7778.o 15obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
14obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o clock-r8a7779.o intc-r8a7779.o 16obj-$(CONFIG_ARCH_R8A7779) += setup-r8a7779.o
15obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o clock-r8a7790.o 17obj-$(CONFIG_ARCH_R8A7790) += setup-r8a7790.o
16obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o 18obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o
19
20# Clock objects
21ifndef CONFIG_COMMON_CLK
22obj-y += clock.o
23obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
24obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
25obj-$(CONFIG_ARCH_R8A73A4) += clock-r8a73a4.o
26obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
27obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
28obj-$(CONFIG_ARCH_R8A7779) += clock-r8a7779.o
29obj-$(CONFIG_ARCH_R8A7790) += clock-r8a7790.o
30obj-$(CONFIG_ARCH_EMEV2) += clock-emev2.o
31endif
17 32
18# SMP objects 33# SMP objects
19smp-y := platsmp.o headsmp.o 34smp-y := platsmp.o headsmp.o
20smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o 35smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o platsmp-scu.o
21smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o 36smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o platsmp-scu.o
22smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o 37smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o platsmp-scu.o
23 38
24# IRQ objects 39# IRQ objects
25obj-$(CONFIG_ARCH_SH7372) += entry-intc.o 40obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
26obj-$(CONFIG_ARCH_R8A7740) += entry-intc.o
27 41
28# PM objects 42# PM objects
29obj-$(CONFIG_SUSPEND) += suspend.o 43obj-$(CONFIG_SUSPEND) += suspend.o
30obj-$(CONFIG_CPU_IDLE) += cpuidle.o 44obj-$(CONFIG_CPU_IDLE) += cpuidle.o
31obj-$(CONFIG_ARCH_SHMOBILE) += pm-rmobile.o 45obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o pm-rmobile.o
32obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
33obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o
34obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
35obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o 46obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
47obj-$(CONFIG_ARCH_R8A7740) += pm-r8a7740.o pm-rmobile.o
48obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
36 49
37# Board objects 50# Board objects
38obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
39obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o 51obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
52obj-$(CONFIG_MACH_APE6EVM_REFERENCE) += board-ape6evm-reference.o
40obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 53obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
41obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
42obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 54obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
55obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
43obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 56obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
44obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o 57obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
45obj-$(CONFIG_MACH_LAGER) += board-lager.o 58obj-$(CONFIG_MACH_LAGER) += board-lager.o
59obj-$(CONFIG_MACH_LAGER_REFERENCE) += board-lager-reference.o
46obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 60obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
47obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o 61obj-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += board-armadillo800eva-reference.o
48obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o 62obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
63obj-$(CONFIG_MACH_KZM9D_REFERENCE) += board-kzm9d-reference.o
49obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 64obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
50obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o 65obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
51 66
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 84c6868580f0..6a504fe7d86c 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,15 +1,17 @@
1# per-board load address for uImage 1# per-board load address for uImage
2loadaddr-y := 2loadaddr-y :=
3loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000
4loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000 3loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
4loadaddr-$(CONFIG_MACH_APE6EVM_REFERENCE) += 0x40008000
5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000 5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
6loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000 6loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000 8loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
9loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000 9loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
10loadaddr-$(CONFIG_MACH_KZM9D_REFERENCE) += 0x40008000
10loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 11loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
11loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 12loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
12loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000 13loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
14loadaddr-$(CONFIG_MACH_LAGER_REFERENCE) += 0x40008000
13loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000 15loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
14loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 16loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
15loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000 17loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
deleted file mode 100644
index c7540710906f..000000000000
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ /dev/null
@@ -1,672 +0,0 @@
1/*
2 * arch/arm/mach-shmobile/board-ag5evm.c
3 *
4 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
5 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/irq.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf-generic.h>
28#include <linux/platform_device.h>
29#include <linux/delay.h>
30#include <linux/io.h>
31#include <linux/dma-mapping.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
34#include <linux/serial_sci.h>
35#include <linux/smsc911x.h>
36#include <linux/gpio.h>
37#include <linux/videodev2.h>
38#include <linux/input.h>
39#include <linux/input/sh_keysc.h>
40#include <linux/mmc/host.h>
41#include <linux/mmc/sh_mmcif.h>
42#include <linux/mmc/sh_mobile_sdhi.h>
43#include <linux/mfd/tmio.h>
44#include <linux/sh_clk.h>
45#include <linux/irqchip/arm-gic.h>
46#include <video/sh_mobile_lcdc.h>
47#include <video/sh_mipi_dsi.h>
48#include <sound/sh_fsi.h>
49#include <mach/hardware.h>
50#include <mach/irqs.h>
51#include <mach/sh73a0.h>
52#include <mach/common.h>
53#include <asm/mach-types.h>
54#include <asm/mach/arch.h>
55#include <asm/hardware/cache-l2x0.h>
56#include <asm/traps.h>
57
58/* Dummy supplies, where voltage doesn't matter */
59static struct regulator_consumer_supply dummy_supplies[] = {
60 REGULATOR_SUPPLY("vddvario", "smsc911x"),
61 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
62};
63
64static struct resource smsc9220_resources[] = {
65 [0] = {
66 .start = 0x14000000,
67 .end = 0x14000000 + SZ_64K - 1,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76static struct smsc911x_platform_config smsc9220_platdata = {
77 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
78 .phy_interface = PHY_INTERFACE_MODE_MII,
79 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
80 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
81};
82
83static struct platform_device eth_device = {
84 .name = "smsc911x",
85 .id = 0,
86 .dev = {
87 .platform_data = &smsc9220_platdata,
88 },
89 .resource = smsc9220_resources,
90 .num_resources = ARRAY_SIZE(smsc9220_resources),
91};
92
93static struct sh_keysc_info keysc_platdata = {
94 .mode = SH_KEYSC_MODE_6,
95 .scan_timing = 3,
96 .delay = 100,
97 .keycodes = {
98 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E, KEY_F, KEY_G,
99 KEY_H, KEY_I, KEY_J, KEY_K, KEY_L, KEY_M, KEY_N,
100 KEY_O, KEY_P, KEY_Q, KEY_R, KEY_S, KEY_T, KEY_U,
101 KEY_V, KEY_W, KEY_X, KEY_Y, KEY_Z, KEY_HOME, KEY_SLEEP,
102 KEY_SPACE, KEY_9, KEY_6, KEY_3, KEY_WAKEUP, KEY_RIGHT, \
103 KEY_COFFEE,
104 KEY_0, KEY_8, KEY_5, KEY_2, KEY_DOWN, KEY_ENTER, KEY_UP,
105 KEY_KPASTERISK, KEY_7, KEY_4, KEY_1, KEY_STOP, KEY_LEFT, \
106 KEY_COMPUTER,
107 },
108};
109
110static struct resource keysc_resources[] = {
111 [0] = {
112 .name = "KEYSC",
113 .start = 0xe61b0000,
114 .end = 0xe61b0098 - 1,
115 .flags = IORESOURCE_MEM,
116 },
117 [1] = {
118 .start = gic_spi(71),
119 .flags = IORESOURCE_IRQ,
120 },
121};
122
123static struct platform_device keysc_device = {
124 .name = "sh_keysc",
125 .id = 0,
126 .num_resources = ARRAY_SIZE(keysc_resources),
127 .resource = keysc_resources,
128 .dev = {
129 .platform_data = &keysc_platdata,
130 },
131};
132
133/* FSI A */
134static struct resource fsi_resources[] = {
135 [0] = {
136 .name = "FSI",
137 .start = 0xEC230000,
138 .end = 0xEC230400 - 1,
139 .flags = IORESOURCE_MEM,
140 },
141 [1] = {
142 .start = gic_spi(146),
143 .flags = IORESOURCE_IRQ,
144 },
145};
146
147static struct platform_device fsi_device = {
148 .name = "sh_fsi2",
149 .id = -1,
150 .num_resources = ARRAY_SIZE(fsi_resources),
151 .resource = fsi_resources,
152};
153
154/* Fixed 1.8V regulator to be used by MMCIF */
155static struct regulator_consumer_supply fixed1v8_power_consumers[] =
156{
157 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
158 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
159};
160
161static struct resource sh_mmcif_resources[] = {
162 [0] = {
163 .name = "MMCIF",
164 .start = 0xe6bd0000,
165 .end = 0xe6bd00ff,
166 .flags = IORESOURCE_MEM,
167 },
168 [1] = {
169 .start = gic_spi(141),
170 .flags = IORESOURCE_IRQ,
171 },
172 [2] = {
173 .start = gic_spi(140),
174 .flags = IORESOURCE_IRQ,
175 },
176};
177
178static struct sh_mmcif_plat_data sh_mmcif_platdata = {
179 .sup_pclk = 0,
180 .ocr = MMC_VDD_165_195,
181 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
182 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
183 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
184};
185
186static struct platform_device mmc_device = {
187 .name = "sh_mmcif",
188 .id = 0,
189 .dev = {
190 .dma_mask = NULL,
191 .coherent_dma_mask = 0xffffffff,
192 .platform_data = &sh_mmcif_platdata,
193 },
194 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
195 .resource = sh_mmcif_resources,
196};
197
198/* IrDA */
199static struct resource irda_resources[] = {
200 [0] = {
201 .start = 0xE6D00000,
202 .end = 0xE6D01FD4 - 1,
203 .flags = IORESOURCE_MEM,
204 },
205 [1] = {
206 .start = gic_spi(95),
207 .flags = IORESOURCE_IRQ,
208 },
209};
210
211static struct platform_device irda_device = {
212 .name = "sh_irda",
213 .id = 0,
214 .resource = irda_resources,
215 .num_resources = ARRAY_SIZE(irda_resources),
216};
217
218/* MIPI-DSI */
219static struct resource mipidsi0_resources[] = {
220 [0] = {
221 .name = "DSI0",
222 .start = 0xfeab0000,
223 .end = 0xfeab3fff,
224 .flags = IORESOURCE_MEM,
225 },
226 [1] = {
227 .name = "DSI0",
228 .start = 0xfeab4000,
229 .end = 0xfeab7fff,
230 .flags = IORESOURCE_MEM,
231 },
232};
233
234static int sh_mipi_set_dot_clock(struct platform_device *pdev,
235 void __iomem *base,
236 int enable)
237{
238 struct clk *pck, *phy;
239 int ret;
240
241 pck = clk_get(&pdev->dev, "dsip_clk");
242 if (IS_ERR(pck)) {
243 ret = PTR_ERR(pck);
244 goto sh_mipi_set_dot_clock_pck_err;
245 }
246
247 phy = clk_get(&pdev->dev, "dsiphy_clk");
248 if (IS_ERR(phy)) {
249 ret = PTR_ERR(phy);
250 goto sh_mipi_set_dot_clock_phy_err;
251 }
252
253 if (enable) {
254 clk_set_rate(pck, clk_round_rate(pck, 24000000));
255 clk_set_rate(phy, clk_round_rate(pck, 510000000));
256 clk_enable(pck);
257 clk_enable(phy);
258 } else {
259 clk_disable(pck);
260 clk_disable(phy);
261 }
262
263 ret = 0;
264
265 clk_put(phy);
266sh_mipi_set_dot_clock_phy_err:
267 clk_put(pck);
268sh_mipi_set_dot_clock_pck_err:
269 return ret;
270}
271
272static struct sh_mipi_dsi_info mipidsi0_info = {
273 .data_format = MIPI_RGB888,
274 .channel = LCDC_CHAN_MAINLCD,
275 .lane = 2,
276 .vsynw_offset = 20,
277 .clksrc = 1,
278 .flags = SH_MIPI_DSI_HSABM |
279 SH_MIPI_DSI_SYNC_PULSES_MODE |
280 SH_MIPI_DSI_HSbyteCLK,
281 .set_dot_clock = sh_mipi_set_dot_clock,
282};
283
284static struct platform_device mipidsi0_device = {
285 .name = "sh-mipi-dsi",
286 .num_resources = ARRAY_SIZE(mipidsi0_resources),
287 .resource = mipidsi0_resources,
288 .id = 0,
289 .dev = {
290 .platform_data = &mipidsi0_info,
291 },
292};
293
294static unsigned char lcd_backlight_seq[3][2] = {
295 { 0x04, 0x07 },
296 { 0x23, 0x80 },
297 { 0x03, 0x01 },
298};
299
300static int lcd_backlight_set_brightness(int brightness)
301{
302 struct i2c_adapter *adap;
303 struct i2c_msg msg;
304 unsigned int i;
305 int ret;
306
307 if (brightness == 0) {
308 /* Reset the chip */
309 gpio_set_value(235, 0);
310 mdelay(24);
311 gpio_set_value(235, 1);
312 return 0;
313 }
314
315 adap = i2c_get_adapter(1);
316 if (adap == NULL)
317 return -ENODEV;
318
319 for (i = 0; i < ARRAY_SIZE(lcd_backlight_seq); i++) {
320 msg.addr = 0x6d;
321 msg.buf = &lcd_backlight_seq[i][0];
322 msg.len = 2;
323 msg.flags = 0;
324
325 ret = i2c_transfer(adap, &msg, 1);
326 if (ret < 0)
327 break;
328 }
329
330 i2c_put_adapter(adap);
331 return ret < 0 ? ret : 0;
332}
333
334/* LCDC0 */
335static const struct fb_videomode lcdc0_modes[] = {
336 {
337 .name = "R63302(QHD)",
338 .xres = 544,
339 .yres = 961,
340 .left_margin = 72,
341 .right_margin = 600,
342 .hsync_len = 16,
343 .upper_margin = 8,
344 .lower_margin = 8,
345 .vsync_len = 2,
346 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
347 },
348};
349
350static struct sh_mobile_lcdc_info lcdc0_info = {
351 .clock_source = LCDC_CLK_PERIPHERAL,
352 .ch[0] = {
353 .chan = LCDC_CHAN_MAINLCD,
354 .interface_type = RGB24,
355 .clock_divider = 1,
356 .flags = LCDC_FLAGS_DWPOL,
357 .fourcc = V4L2_PIX_FMT_RGB565,
358 .lcd_modes = lcdc0_modes,
359 .num_modes = ARRAY_SIZE(lcdc0_modes),
360 .panel_cfg = {
361 .width = 44,
362 .height = 79,
363 },
364 .bl_info = {
365 .name = "sh_mobile_lcdc_bl",
366 .max_brightness = 1,
367 .set_brightness = lcd_backlight_set_brightness,
368 },
369 .tx_dev = &mipidsi0_device,
370 }
371};
372
373static struct resource lcdc0_resources[] = {
374 [0] = {
375 .name = "LCDC0",
376 .start = 0xfe940000, /* P4-only space */
377 .end = 0xfe943fff,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = intcs_evt2irq(0x580),
382 .flags = IORESOURCE_IRQ,
383 },
384};
385
386static struct platform_device lcdc0_device = {
387 .name = "sh_mobile_lcdc_fb",
388 .num_resources = ARRAY_SIZE(lcdc0_resources),
389 .resource = lcdc0_resources,
390 .id = 0,
391 .dev = {
392 .platform_data = &lcdc0_info,
393 .coherent_dma_mask = ~0,
394 },
395};
396
397/* Fixed 2.8V regulators to be used by SDHI0 */
398static struct regulator_consumer_supply fixed2v8_power_consumers[] =
399{
400 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
401 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
402};
403
404/* SDHI0 */
405static struct sh_mobile_sdhi_info sdhi0_info = {
406 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
407 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
408 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
409 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
410 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
411 .cd_gpio = 251,
412};
413
414static struct resource sdhi0_resources[] = {
415 [0] = {
416 .name = "SDHI0",
417 .start = 0xee100000,
418 .end = 0xee1000ff,
419 .flags = IORESOURCE_MEM,
420 },
421 [1] = {
422 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
423 .start = gic_spi(83),
424 .flags = IORESOURCE_IRQ,
425 },
426 [2] = {
427 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
428 .start = gic_spi(84),
429 .flags = IORESOURCE_IRQ,
430 },
431 [3] = {
432 .name = SH_MOBILE_SDHI_IRQ_SDIO,
433 .start = gic_spi(85),
434 .flags = IORESOURCE_IRQ,
435 },
436};
437
438static struct platform_device sdhi0_device = {
439 .name = "sh_mobile_sdhi",
440 .id = 0,
441 .num_resources = ARRAY_SIZE(sdhi0_resources),
442 .resource = sdhi0_resources,
443 .dev = {
444 .platform_data = &sdhi0_info,
445 },
446};
447
448/* Fixed 3.3V regulator to be used by SDHI1 */
449static struct regulator_consumer_supply cn4_power_consumers[] =
450{
451 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
452 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
453};
454
455static struct regulator_init_data cn4_power_init_data = {
456 .constraints = {
457 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
458 },
459 .num_consumer_supplies = ARRAY_SIZE(cn4_power_consumers),
460 .consumer_supplies = cn4_power_consumers,
461};
462
463static struct fixed_voltage_config cn4_power_info = {
464 .supply_name = "CN4 SD/MMC Vdd",
465 .microvolts = 3300000,
466 .gpio = 114,
467 .enable_high = 1,
468 .init_data = &cn4_power_init_data,
469};
470
471static struct platform_device cn4_power = {
472 .name = "reg-fixed-voltage",
473 .id = 2,
474 .dev = {
475 .platform_data = &cn4_power_info,
476 },
477};
478
479static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
480{
481 static int power_gpio = -EINVAL;
482
483 if (power_gpio < 0) {
484 int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
485 "sdhi1_power");
486 if (!ret)
487 power_gpio = 114;
488 }
489
490 /*
491 * If requesting the GPIO above failed, it means, that the regulator got
492 * probed and grabbed the GPIO, but we don't know, whether the sdhi
493 * driver already uses the regulator. If it doesn't, we have to toggle
494 * the GPIO ourselves, even though it is now owned by the fixed
495 * regulator driver. We have to live with the race in case the driver
496 * gets unloaded and the GPIO freed between these two steps.
497 */
498 gpio_set_value(114, state);
499}
500
501static struct sh_mobile_sdhi_info sh_sdhi1_info = {
502 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
503 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
504 .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
505 .set_pwr = ag5evm_sdhi1_set_pwr,
506};
507
508static struct resource sdhi1_resources[] = {
509 [0] = {
510 .name = "SDHI1",
511 .start = 0xee120000,
512 .end = 0xee1200ff,
513 .flags = IORESOURCE_MEM,
514 },
515 [1] = {
516 .name = SH_MOBILE_SDHI_IRQ_CARD_DETECT,
517 .start = gic_spi(87),
518 .flags = IORESOURCE_IRQ,
519 },
520 [2] = {
521 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
522 .start = gic_spi(88),
523 .flags = IORESOURCE_IRQ,
524 },
525 [3] = {
526 .name = SH_MOBILE_SDHI_IRQ_SDIO,
527 .start = gic_spi(89),
528 .flags = IORESOURCE_IRQ,
529 },
530};
531
532static struct platform_device sdhi1_device = {
533 .name = "sh_mobile_sdhi",
534 .id = 1,
535 .dev = {
536 .platform_data = &sh_sdhi1_info,
537 },
538 .num_resources = ARRAY_SIZE(sdhi1_resources),
539 .resource = sdhi1_resources,
540};
541
542static struct platform_device *ag5evm_devices[] __initdata = {
543 &cn4_power,
544 &eth_device,
545 &keysc_device,
546 &fsi_device,
547 &mmc_device,
548 &irda_device,
549 &mipidsi0_device,
550 &lcdc0_device,
551 &sdhi0_device,
552 &sdhi1_device,
553};
554
555static unsigned long pin_pullup_conf[] = {
556 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
557};
558
559static const struct pinctrl_map ag5evm_pinctrl_map[] = {
560 /* FSIA */
561 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
562 "fsia_mclk_in", "fsia"),
563 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
564 "fsia_sclk_in", "fsia"),
565 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
566 "fsia_data_in", "fsia"),
567 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
568 "fsia_data_out", "fsia"),
569 /* I2C2 & I2C3 */
570 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
571 "i2c2_0", "i2c2"),
572 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
573 "i2c3_0", "i2c3"),
574 /* IrDA */
575 PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
576 "irda_0", "irda"),
577 /* KEYSC */
578 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
579 "keysc_in8", "keysc"),
580 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
581 "keysc_out04", "keysc"),
582 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
583 "keysc_out5", "keysc"),
584 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
585 "keysc_out6_0", "keysc"),
586 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
587 "keysc_out7_0", "keysc"),
588 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
589 "keysc_out8_0", "keysc"),
590 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
591 "keysc_out9_2", "keysc"),
592 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
593 "keysc_in8", pin_pullup_conf),
594 /* MMCIF */
595 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
596 "mmc0_data8_0", "mmc0"),
597 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
598 "mmc0_ctrl_0", "mmc0"),
599 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
600 "PORT279", pin_pullup_conf),
601 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
602 "mmc0_data8_0", pin_pullup_conf),
603 /* SCIFA2 */
604 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
605 "scifa2_data_0", "scifa2"),
606 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
607 "scifa2_ctrl_0", "scifa2"),
608 /* SDHI0 (CN15 [SD I/F]) */
609 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
610 "sdhi0_data4", "sdhi0"),
611 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
612 "sdhi0_ctrl", "sdhi0"),
613 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
614 "sdhi0_wp", "sdhi0"),
615 /* SDHI1 (CN4 [WLAN I/F]) */
616 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
617 "sdhi1_data4", "sdhi1"),
618 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
619 "sdhi1_ctrl", "sdhi1"),
620 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
621 "sdhi1_data4", pin_pullup_conf),
622 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
623 "PORT263", pin_pullup_conf),
624};
625
626static void __init ag5evm_init(void)
627{
628 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
629 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
630 regulator_register_always_on(1, "fixed-2.8V", fixed2v8_power_consumers,
631 ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
632 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
633
634 pinctrl_register_mappings(ag5evm_pinctrl_map,
635 ARRAY_SIZE(ag5evm_pinctrl_map));
636 sh73a0_pinmux_init();
637
638 /* enable MMCIF */
639 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
640
641 /* enable SMSC911X */
642 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
643 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
644
645 /* LCD panel */
646 gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
647 mdelay(1);
648 gpio_set_value(217, 1);
649 mdelay(100);
650
651 /* LCD backlight controller */
652 gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
653 lcd_backlight_set_brightness(0);
654
655#ifdef CONFIG_CACHE_L2X0
656 /* Shared attribute override enable, 64K*8way */
657 l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
658#endif
659 sh73a0_add_standard_devices();
660 platform_add_devices(ag5evm_devices, ARRAY_SIZE(ag5evm_devices));
661}
662
663MACHINE_START(AG5EVM, "ag5evm")
664 .smp = smp_ops(sh73a0_smp_ops),
665 .map_io = sh73a0_map_io,
666 .init_early = sh73a0_add_early_devices,
667 .nr_irqs = NR_IRQS_LEGACY,
668 .init_irq = sh73a0_init_irq,
669 .init_machine = ag5evm_init,
670 .init_late = shmobile_init_late,
671 .init_time = sh73a0_earlytimer_init,
672MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c
new file mode 100644
index 000000000000..a23fa714f7ac
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c
@@ -0,0 +1,63 @@
1/*
2 * APE6EVM board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/gpio.h>
22#include <linux/kernel.h>
23#include <linux/of_platform.h>
24#include <linux/pinctrl/machine.h>
25#include <linux/platform_device.h>
26#include <linux/sh_clk.h>
27#include <mach/common.h>
28#include <mach/r8a73a4.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31
32static void __init ape6evm_add_standard_devices(void)
33{
34
35 struct clk *parent;
36 struct clk *mp;
37
38 r8a73a4_clock_init();
39
40 /* MP clock parent = extal2 */
41 parent = clk_get(NULL, "extal2");
42 mp = clk_get(NULL, "mp");
43 BUG_ON(IS_ERR(parent) || IS_ERR(mp));
44
45 clk_set_parent(mp, parent);
46 clk_put(parent);
47 clk_put(mp);
48
49 r8a73a4_add_dt_devices();
50 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
51 platform_device_register_simple("cpufreq-cpu0", -1, NULL, 0);
52}
53
54static const char *ape6evm_boards_compat_dt[] __initdata = {
55 "renesas,ape6evm-reference",
56 NULL,
57};
58
59DT_MACHINE_START(APE6EVM_DT, "ape6evm")
60 .init_early = r8a73a4_init_delay,
61 .init_machine = ape6evm_add_standard_devices,
62 .dt_compat = ape6evm_boards_compat_dt,
63MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c
index 5eb0caa6a7d0..24b87eea9da3 100644
--- a/arch/arm/mach-shmobile/board-ape6evm.c
+++ b/arch/arm/mach-shmobile/board-ape6evm.c
@@ -19,9 +19,14 @@
19 */ 19 */
20 20
21#include <linux/gpio.h> 21#include <linux/gpio.h>
22#include <linux/gpio_keys.h>
23#include <linux/input.h>
22#include <linux/interrupt.h> 24#include <linux/interrupt.h>
23#include <linux/irqchip.h>
24#include <linux/kernel.h> 25#include <linux/kernel.h>
26#include <linux/mfd/tmio.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/sh_mmcif.h>
29#include <linux/mmc/sh_mobile_sdhi.h>
25#include <linux/pinctrl/machine.h> 30#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h> 31#include <linux/platform_device.h>
27#include <linux/regulator/fixed.h> 32#include <linux/regulator/fixed.h>
@@ -34,6 +39,58 @@
34#include <asm/mach-types.h> 39#include <asm/mach-types.h>
35#include <asm/mach/arch.h> 40#include <asm/mach/arch.h>
36 41
42/* LEDS */
43static struct gpio_led ape6evm_leds[] = {
44 {
45 .name = "gnss-en",
46 .gpio = 28,
47 .default_state = LEDS_GPIO_DEFSTATE_OFF,
48 }, {
49 .name = "nfc-nrst",
50 .gpio = 126,
51 .default_state = LEDS_GPIO_DEFSTATE_OFF,
52 }, {
53 .name = "gnss-nrst",
54 .gpio = 132,
55 .default_state = LEDS_GPIO_DEFSTATE_OFF,
56 }, {
57 .name = "bt-wakeup",
58 .gpio = 232,
59 .default_state = LEDS_GPIO_DEFSTATE_OFF,
60 }, {
61 .name = "strobe",
62 .gpio = 250,
63 .default_state = LEDS_GPIO_DEFSTATE_OFF,
64 }, {
65 .name = "bbresetout",
66 .gpio = 288,
67 .default_state = LEDS_GPIO_DEFSTATE_OFF,
68 },
69};
70
71static __initdata struct gpio_led_platform_data ape6evm_leds_pdata = {
72 .leds = ape6evm_leds,
73 .num_leds = ARRAY_SIZE(ape6evm_leds),
74};
75
76/* GPIO KEY */
77#define GPIO_KEY(c, g, d, ...) \
78 { .code = c, .gpio = g, .desc = d, .active_low = 1 }
79
80static struct gpio_keys_button gpio_buttons[] = {
81 GPIO_KEY(KEY_0, 324, "S16"),
82 GPIO_KEY(KEY_MENU, 325, "S17"),
83 GPIO_KEY(KEY_HOME, 326, "S18"),
84 GPIO_KEY(KEY_BACK, 327, "S19"),
85 GPIO_KEY(KEY_VOLUMEUP, 328, "S20"),
86 GPIO_KEY(KEY_VOLUMEDOWN, 329, "S21"),
87};
88
89static struct __initdata gpio_keys_platform_data ape6evm_keys_pdata = {
90 .buttons = gpio_buttons,
91 .nbuttons = ARRAY_SIZE(gpio_buttons),
92};
93
37/* Dummy supplies, where voltage doesn't matter */ 94/* Dummy supplies, where voltage doesn't matter */
38static struct regulator_consumer_supply dummy_supplies[] = { 95static struct regulator_consumer_supply dummy_supplies[] = {
39 REGULATOR_SUPPLY("vddvario", "smsc911x"), 96 REGULATOR_SUPPLY("vddvario", "smsc911x"),
@@ -41,7 +98,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
41}; 98};
42 99
43/* SMSC LAN9220 */ 100/* SMSC LAN9220 */
44static const struct resource lan9220_res[] = { 101static const struct resource lan9220_res[] __initconst = {
45 DEFINE_RES_MEM(0x08000000, 0x1000), 102 DEFINE_RES_MEM(0x08000000, 0x1000),
46 { 103 {
47 .start = irq_pin(40), /* IRQ40 */ 104 .start = irq_pin(40), /* IRQ40 */
@@ -49,19 +106,83 @@ static const struct resource lan9220_res[] = {
49 }, 106 },
50}; 107};
51 108
52static const struct smsc911x_platform_config lan9220_data = { 109static const struct smsc911x_platform_config lan9220_data __initconst = {
53 .flags = SMSC911X_USE_32BIT, 110 .flags = SMSC911X_USE_32BIT,
54 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 111 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
55 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, 112 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
56}; 113};
57 114
58static const struct pinctrl_map ape6evm_pinctrl_map[] = { 115/*
116 * On APE6EVM power is supplied to MMCIF by a tps80032 regulator. For now we
117 * model a VDD supply to MMCIF, using a fixed 3.3V regulator. Also use the
118 * static power supply for SDHI0 and SDHI1, whereas SDHI0's VccQ is also
119 * supplied by the same tps80032 regulator and thus can also be adjusted
120 * dynamically.
121 */
122static struct regulator_consumer_supply fixed3v3_power_consumers[] =
123{
124 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
125 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
126 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
127};
128
129/* MMCIF */
130static const struct sh_mmcif_plat_data mmcif0_pdata __initconst = {
131 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
132};
133
134static const struct resource mmcif0_resources[] __initconst = {
135 DEFINE_RES_MEM_NAMED(0xee200000, 0x100, "MMCIF0"),
136 DEFINE_RES_IRQ(gic_spi(169)),
137};
138
139/* SDHI0 */
140static const struct sh_mobile_sdhi_info sdhi0_pdata __initconst = {
141 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
142 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
143};
144
145static const struct resource sdhi0_resources[] __initconst = {
146 DEFINE_RES_MEM_NAMED(0xee100000, 0x100, "SDHI0"),
147 DEFINE_RES_IRQ(gic_spi(165)),
148};
149
150/* SDHI1 */
151static const struct sh_mobile_sdhi_info sdhi1_pdata __initconst = {
152 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE,
153 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
154 MMC_CAP_NEEDS_POLL,
155};
156
157static const struct resource sdhi1_resources[] __initconst = {
158 DEFINE_RES_MEM_NAMED(0xee120000, 0x100, "SDHI1"),
159 DEFINE_RES_IRQ(gic_spi(166)),
160};
161
162static const struct pinctrl_map ape6evm_pinctrl_map[] __initconst = {
59 /* SCIFA0 console */ 163 /* SCIFA0 console */
60 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4", 164 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a73a4",
61 "scifa0_data", "scifa0"), 165 "scifa0_data", "scifa0"),
62 /* SMSC */ 166 /* SMSC */
63 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4", 167 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a73a4",
64 "irqc_irq40", "irqc"), 168 "irqc_irq40", "irqc"),
169 /* MMCIF0 */
170 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
171 "mmc0_data8", "mmc0"),
172 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a73a4",
173 "mmc0_ctrl", "mmc0"),
174 /* SDHI0: uSD: no WP */
175 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
176 "sdhi0_data4", "sdhi0"),
177 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
178 "sdhi0_ctrl", "sdhi0"),
179 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a73a4",
180 "sdhi0_cd", "sdhi0"),
181 /* SDHI1 */
182 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
183 "sdhi1_data4", "sdhi1"),
184 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a73a4",
185 "sdhi1_ctrl", "sdhi1"),
65}; 186};
66 187
67static void __init ape6evm_add_standard_devices(void) 188static void __init ape6evm_add_standard_devices(void)
@@ -94,6 +215,23 @@ static void __init ape6evm_add_standard_devices(void)
94 platform_device_register_resndata(&platform_bus, "smsc911x", -1, 215 platform_device_register_resndata(&platform_bus, "smsc911x", -1,
95 lan9220_res, ARRAY_SIZE(lan9220_res), 216 lan9220_res, ARRAY_SIZE(lan9220_res),
96 &lan9220_data, sizeof(lan9220_data)); 217 &lan9220_data, sizeof(lan9220_data));
218 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
219 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
220 platform_device_register_resndata(&platform_bus, "sh_mmcif", 0,
221 mmcif0_resources, ARRAY_SIZE(mmcif0_resources),
222 &mmcif0_pdata, sizeof(mmcif0_pdata));
223 platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 0,
224 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
225 &sdhi0_pdata, sizeof(sdhi0_pdata));
226 platform_device_register_resndata(&platform_bus, "sh_mobile_sdhi", 1,
227 sdhi1_resources, ARRAY_SIZE(sdhi1_resources),
228 &sdhi1_pdata, sizeof(sdhi1_pdata));
229 platform_device_register_data(&platform_bus, "gpio-keys", -1,
230 &ape6evm_keys_pdata,
231 sizeof(ape6evm_keys_pdata));
232 platform_device_register_data(&platform_bus, "leds-gpio", -1,
233 &ape6evm_leds_pdata,
234 sizeof(ape6evm_leds_pdata));
97} 235}
98 236
99static const char *ape6evm_boards_compat_dt[] __initdata = { 237static const char *ape6evm_boards_compat_dt[] __initdata = {
@@ -102,8 +240,7 @@ static const char *ape6evm_boards_compat_dt[] __initdata = {
102}; 240};
103 241
104DT_MACHINE_START(APE6EVM_DT, "ape6evm") 242DT_MACHINE_START(APE6EVM_DT, "ape6evm")
105 .init_irq = irqchip_init, 243 .init_early = r8a73a4_init_delay,
106 .init_time = shmobile_timer_init,
107 .init_machine = ape6evm_add_standard_devices, 244 .init_machine = ape6evm_add_standard_devices,
108 .dt_compat = ape6evm_boards_compat_dt, 245 .dt_compat = ape6evm_boards_compat_dt,
109MACHINE_END 246MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
index 03b85fec2ddb..57d1a78367b6 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c
@@ -24,7 +24,6 @@
24#include <linux/kernel.h> 24#include <linux/kernel.h>
25#include <linux/gpio.h> 25#include <linux/gpio.h>
26#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/pinctrl/machine.h>
28#include <mach/common.h> 27#include <mach/common.h>
29#include <mach/r8a7740.h> 28#include <mach/r8a7740.h>
30#include <asm/mach/arch.h> 29#include <asm/mach/arch.h>
@@ -119,12 +118,6 @@
119 * usbhsf_power_ctrl() 118 * usbhsf_power_ctrl()
120 */ 119 */
121 120
122static const struct pinctrl_map eva_pinctrl_map[] = {
123 /* SCIFA1 */
124 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.1", "pfc-r8a7740",
125 "scifa1_data", "scifa1"),
126};
127
128static void __init eva_clock_init(void) 121static void __init eva_clock_init(void)
129{ 122{
130 struct clk *system = clk_get(NULL, "system_clk"); 123 struct clk *system = clk_get(NULL, "system_clk");
@@ -165,35 +158,26 @@ clock_error:
165 */ 158 */
166static void __init eva_init(void) 159static void __init eva_init(void)
167{ 160{
168
169 r8a7740_clock_init(MD_CK0 | MD_CK2); 161 r8a7740_clock_init(MD_CK0 | MD_CK2);
170 eva_clock_init(); 162 eva_clock_init();
171 163
172 pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
173 r8a7740_pinmux_init();
174
175 r8a7740_meram_workaround(); 164 r8a7740_meram_workaround();
176 165
177 /*
178 * Touchscreen
179 * TODO: Move reset GPIO over to .dts when we can reference it
180 */
181 gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
182
183#ifdef CONFIG_CACHE_L2X0 166#ifdef CONFIG_CACHE_L2X0
184 /* Early BRESP enable, Shared attribute override enable, 32K*8way */ 167 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
185 l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff); 168 l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
186#endif 169#endif
187 170
188 r8a7740_add_standard_devices_dt(); 171 r8a7740_add_standard_devices_dt();
172
189 r8a7740_pm_init(); 173 r8a7740_pm_init();
190} 174}
191 175
192#define RESCNT2 IOMEM(0xe6188020) 176#define RESCNT2 IOMEM(0xe6188020)
193static void eva_restart(char mode, const char *cmd) 177static void eva_restart(enum reboot_mode mode, const char *cmd)
194{ 178{
195 /* Do soft power on reset */ 179 /* Do soft power on reset */
196 writel((1 << 31), RESCNT2); 180 writel(1 << 31, RESCNT2);
197} 181}
198 182
199static const char *eva_boards_compat_dt[] __initdata = { 183static const char *eva_boards_compat_dt[] __initdata = {
@@ -206,7 +190,6 @@ DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva-reference")
206 .init_early = r8a7740_init_delay, 190 .init_early = r8a7740_init_delay,
207 .init_irq = r8a7740_init_irq_of, 191 .init_irq = r8a7740_init_irq_of,
208 .init_machine = eva_init, 192 .init_machine = eva_init,
209 .init_time = shmobile_timer_init,
210 .init_late = shmobile_init_late, 193 .init_late = shmobile_init_late,
211 .dt_compat = eva_boards_compat_dt, 194 .dt_compat = eva_boards_compat_dt,
212 .restart = eva_restart, 195 .restart = eva_restart,
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index 3a6ffa250fb1..5bd1479d3deb 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -31,6 +31,8 @@
31#include <linux/gpio_keys.h> 31#include <linux/gpio_keys.h>
32#include <linux/regulator/driver.h> 32#include <linux/regulator/driver.h>
33#include <linux/pinctrl/machine.h> 33#include <linux/pinctrl/machine.h>
34#include <linux/platform_data/pwm-renesas-tpu.h>
35#include <linux/pwm_backlight.h>
34#include <linux/regulator/fixed.h> 36#include <linux/regulator/fixed.h>
35#include <linux/regulator/gpio-regulator.h> 37#include <linux/regulator/gpio-regulator.h>
36#include <linux/regulator/machine.h> 38#include <linux/regulator/machine.h>
@@ -386,7 +388,50 @@ static struct platform_device sh_eth_device = {
386 .num_resources = ARRAY_SIZE(sh_eth_resources), 388 .num_resources = ARRAY_SIZE(sh_eth_resources),
387}; 389};
388 390
389/* LCDC */ 391/* PWM */
392static struct resource pwm_resources[] = {
393 [0] = {
394 .start = 0xe6600000,
395 .end = 0xe66000ff,
396 .flags = IORESOURCE_MEM,
397 },
398};
399
400static struct tpu_pwm_platform_data pwm_device_data = {
401 .channels[2] = {
402 .polarity = PWM_POLARITY_INVERSED,
403 }
404};
405
406static struct platform_device pwm_device = {
407 .name = "renesas-tpu-pwm",
408 .id = -1,
409 .dev = {
410 .platform_data = &pwm_device_data,
411 },
412 .num_resources = ARRAY_SIZE(pwm_resources),
413 .resource = pwm_resources,
414};
415
416static struct pwm_lookup pwm_lookup[] = {
417 PWM_LOOKUP("renesas-tpu-pwm", 2, "pwm-backlight.0", NULL),
418};
419
420/* LCDC and backlight */
421static struct platform_pwm_backlight_data pwm_backlight_data = {
422 .lth_brightness = 50,
423 .max_brightness = 255,
424 .dft_brightness = 255,
425 .pwm_period_ns = 33333, /* 30kHz */
426};
427
428static struct platform_device pwm_backlight_device = {
429 .name = "pwm-backlight",
430 .dev = {
431 .platform_data = &pwm_backlight_data,
432 },
433};
434
390static struct fb_videomode lcdc0_mode = { 435static struct fb_videomode lcdc0_mode = {
391 .name = "AMPIER/AM-800480", 436 .name = "AMPIER/AM-800480",
392 .xres = 800, 437 .xres = 800,
@@ -678,15 +723,6 @@ static struct platform_device vcc_sdhi1 = {
678}; 723};
679 724
680/* SDHI0 */ 725/* SDHI0 */
681/*
682 * FIXME
683 *
684 * It use polling mode here, since
685 * CD (= Card Detect) pin is not connected to SDHI0_CD.
686 * We can use IRQ31 as card detect irq,
687 * but it needs chattering removal operation
688 */
689#define IRQ31 irq_pin(31)
690static struct sh_mobile_sdhi_info sdhi0_info = { 726static struct sh_mobile_sdhi_info sdhi0_info = {
691 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX, 727 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
692 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 728 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
@@ -787,6 +823,8 @@ static struct sh_mmcif_plat_data sh_mmcif_plat = {
787 .caps = MMC_CAP_4_BIT_DATA | 823 .caps = MMC_CAP_4_BIT_DATA |
788 MMC_CAP_8_BIT_DATA | 824 MMC_CAP_8_BIT_DATA |
789 MMC_CAP_NONREMOVABLE, 825 MMC_CAP_NONREMOVABLE,
826 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
827 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
790}; 828};
791 829
792static struct resource sh_mmcif_resources[] = { 830static struct resource sh_mmcif_resources[] = {
@@ -1029,6 +1067,8 @@ static struct i2c_board_info i2c2_devices[] = {
1029 */ 1067 */
1030static struct platform_device *eva_devices[] __initdata = { 1068static struct platform_device *eva_devices[] __initdata = {
1031 &lcdc0_device, 1069 &lcdc0_device,
1070 &pwm_device,
1071 &pwm_backlight_device,
1032 &gpio_keys_device, 1072 &gpio_keys_device,
1033 &sh_eth_device, 1073 &sh_eth_device,
1034 &vcc_sdhi0, 1074 &vcc_sdhi0,
@@ -1100,6 +1140,9 @@ static const struct pinctrl_map eva_pinctrl_map[] = {
1100 /* ST1232 */ 1140 /* ST1232 */
1101 PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740", 1141 PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-r8a7740",
1102 "intc_irq10", "intc"), 1142 "intc_irq10", "intc"),
1143 /* TPU0 */
1144 PIN_MAP_MUX_GROUP_DEFAULT("renesas-tpu-pwm", "pfc-r8a7740",
1145 "tpu0_to2_1", "tpu0"),
1103 /* USBHS */ 1146 /* USBHS */
1104 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740", 1147 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-r8a7740",
1105 "intc_irq7_1", "intc"), 1148 "intc_irq7_1", "intc"),
@@ -1153,13 +1196,13 @@ static void __init eva_init(void)
1153 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 1196 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1154 1197
1155 pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map)); 1198 pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
1199 pwm_add_table(pwm_lookup, ARRAY_SIZE(pwm_lookup));
1156 1200
1157 r8a7740_pinmux_init(); 1201 r8a7740_pinmux_init();
1158 r8a7740_meram_workaround(); 1202 r8a7740_meram_workaround();
1159 1203
1160 /* LCDC0 */ 1204 /* LCDC0 */
1161 gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1205 gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1162 gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
1163 1206
1164 /* GETHER */ 1207 /* GETHER */
1165 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ 1208 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
@@ -1270,7 +1313,7 @@ static const char *eva_boards_compat_dt[] __initdata = {
1270DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva") 1313DT_MACHINE_START(ARMADILLO800EVA_DT, "armadillo800eva")
1271 .map_io = r8a7740_map_io, 1314 .map_io = r8a7740_map_io,
1272 .init_early = eva_add_early_devices, 1315 .init_early = eva_add_early_devices,
1273 .init_irq = r8a7740_init_irq, 1316 .init_irq = r8a7740_init_irq_of,
1274 .init_machine = eva_init, 1317 .init_machine = eva_init,
1275 .init_late = shmobile_init_late, 1318 .init_late = shmobile_init_late,
1276 .init_time = eva_earlytimer_init, 1319 .init_time = eva_earlytimer_init,
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
new file mode 100644
index 000000000000..1a7c893e1a52
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -0,0 +1,61 @@
1/*
2 * Bock-W board support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/of_platform.h>
22#include <linux/pinctrl/machine.h>
23#include <mach/common.h>
24#include <mach/r8a7778.h>
25#include <asm/mach/arch.h>
26
27/*
28 * see board-bock.c for checking detail of dip-switch
29 */
30
31static const struct pinctrl_map bockw_pinctrl_map[] = {
32 /* SCIF0 */
33 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
34 "scif0_data_a", "scif0"),
35 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
36 "scif0_ctrl", "scif0"),
37};
38
39static void __init bockw_init(void)
40{
41 r8a7778_clock_init();
42
43 pinctrl_register_mappings(bockw_pinctrl_map,
44 ARRAY_SIZE(bockw_pinctrl_map));
45 r8a7778_pinmux_init();
46 r8a7778_add_dt_devices();
47
48 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
49}
50
51static const char *bockw_boards_compat_dt[] __initdata = {
52 "renesas,bockw-reference",
53 NULL,
54};
55
56DT_MACHINE_START(BOCKW_DT, "bockw")
57 .init_early = r8a7778_init_delay,
58 .init_irq = r8a7778_init_irq_dt,
59 .init_machine = bockw_init,
60 .dt_compat = bockw_boards_compat_dt,
61MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c
index 35dd7f201a16..6b9faf3908f7 100644
--- a/arch/arm/mach-shmobile/board-bockw.c
+++ b/arch/arm/mach-shmobile/board-bockw.c
@@ -21,8 +21,11 @@
21 21
22#include <linux/mfd/tmio.h> 22#include <linux/mfd/tmio.h>
23#include <linux/mmc/host.h> 23#include <linux/mmc/host.h>
24#include <linux/mmc/sh_mobile_sdhi.h>
25#include <linux/mmc/sh_mmcif.h>
24#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
25#include <linux/pinctrl/machine.h> 27#include <linux/pinctrl/machine.h>
28#include <linux/platform_data/usb-rcar-phy.h>
26#include <linux/platform_device.h> 29#include <linux/platform_device.h>
27#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
28#include <linux/regulator/machine.h> 31#include <linux/regulator/machine.h>
@@ -66,28 +69,38 @@ static struct regulator_consumer_supply dummy_supplies[] = {
66 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 69 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
67}; 70};
68 71
69static struct smsc911x_platform_config smsc911x_data = { 72static struct smsc911x_platform_config smsc911x_data __initdata = {
70 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, 73 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
71 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, 74 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
72 .flags = SMSC911X_USE_32BIT, 75 .flags = SMSC911X_USE_32BIT,
73 .phy_interface = PHY_INTERFACE_MODE_MII, 76 .phy_interface = PHY_INTERFACE_MODE_MII,
74}; 77};
75 78
76static struct resource smsc911x_resources[] = { 79static struct resource smsc911x_resources[] __initdata = {
77 DEFINE_RES_MEM(0x18300000, 0x1000), 80 DEFINE_RES_MEM(0x18300000, 0x1000),
78 DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */ 81 DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
79}; 82};
80 83
81/* USB */ 84/* USB */
85static struct resource usb_phy_resources[] __initdata = {
86 DEFINE_RES_MEM(0xffe70800, 0x100),
87 DEFINE_RES_MEM(0xffe76000, 0x100),
88};
89
82static struct rcar_phy_platform_data usb_phy_platform_data __initdata; 90static struct rcar_phy_platform_data usb_phy_platform_data __initdata;
83 91
84/* SDHI */ 92/* SDHI */
85static struct sh_mobile_sdhi_info sdhi0_info = { 93static struct sh_mobile_sdhi_info sdhi0_info __initdata = {
86 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 94 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
87 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 95 .tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
88 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, 96 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
89}; 97};
90 98
99static struct resource sdhi0_resources[] __initdata = {
100 DEFINE_RES_MEM(0xFFE4C000, 0x100),
101 DEFINE_RES_IRQ(gic_iid(0x77)),
102};
103
91static struct sh_eth_plat_data ether_platform_data __initdata = { 104static struct sh_eth_plat_data ether_platform_data __initdata = {
92 .phy = 0x01, 105 .phy = 0x01,
93 .edmac_endian = EDMAC_LITTLE_ENDIAN, 106 .edmac_endian = EDMAC_LITTLE_ENDIAN,
@@ -136,7 +149,12 @@ static struct spi_board_info spi_board_info[] __initdata = {
136}; 149};
137 150
138/* MMC */ 151/* MMC */
139static struct sh_mmcif_plat_data sh_mmcif_plat = { 152static struct resource mmc_resources[] __initdata = {
153 DEFINE_RES_MEM(0xffe4e000, 0x100),
154 DEFINE_RES_IRQ(gic_iid(0x5d)),
155};
156
157static struct sh_mmcif_plat_data sh_mmcif_plat __initdata = {
140 .sup_pclk = 0, 158 .sup_pclk = 0,
141 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34, 159 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
142 .caps = MMC_CAP_4_BIT_DATA | 160 .caps = MMC_CAP_4_BIT_DATA |
@@ -217,11 +235,7 @@ static void __init bockw_init(void)
217 r8a7778_clock_init(); 235 r8a7778_clock_init();
218 r8a7778_init_irq_extpin(1); 236 r8a7778_init_irq_extpin(1);
219 r8a7778_add_standard_devices(); 237 r8a7778_add_standard_devices();
220 r8a7778_add_usb_phy_device(&usb_phy_platform_data);
221 r8a7778_add_ether_device(&ether_platform_data); 238 r8a7778_add_ether_device(&ether_platform_data);
222 r8a7778_add_i2c_device(0);
223 r8a7778_add_hspi_device(0);
224 r8a7778_add_mmc_device(&sh_mmcif_plat);
225 r8a7778_add_vin_device(0, &vin_platform_data); 239 r8a7778_add_vin_device(0, &vin_platform_data);
226 /* VIN1 has a pin conflict with Ether */ 240 /* VIN1 has a pin conflict with Ether */
227 if (!IS_ENABLED(CONFIG_SH_ETH)) 241 if (!IS_ENABLED(CONFIG_SH_ETH))
@@ -241,6 +255,19 @@ static void __init bockw_init(void)
241 ARRAY_SIZE(bockw_pinctrl_map)); 255 ARRAY_SIZE(bockw_pinctrl_map));
242 r8a7778_pinmux_init(); 256 r8a7778_pinmux_init();
243 257
258 platform_device_register_resndata(
259 &platform_bus, "sh_mmcif", -1,
260 mmc_resources, ARRAY_SIZE(mmc_resources),
261 &sh_mmcif_plat, sizeof(struct sh_mmcif_plat_data));
262
263 platform_device_register_resndata(
264 &platform_bus, "rcar_usb_phy", -1,
265 usb_phy_resources,
266 ARRAY_SIZE(usb_phy_resources),
267 &usb_phy_platform_data,
268 sizeof(struct rcar_phy_platform_data));
269
270
244 /* for SMSC */ 271 /* for SMSC */
245 base = ioremap_nocache(FPGA, SZ_1M); 272 base = ioremap_nocache(FPGA, SZ_1M);
246 if (base) { 273 if (base) {
@@ -276,7 +303,10 @@ static void __init bockw_init(void)
276 iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4); 303 iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
277 iounmap(base); 304 iounmap(base);
278 305
279 r8a7778_sdhi_init(0, &sdhi0_info); 306 platform_device_register_resndata(
307 &platform_bus, "sh_mobile_sdhi", 0,
308 sdhi0_resources, ARRAY_SIZE(sdhi0_resources),
309 &sdhi0_info, sizeof(struct sh_mobile_sdhi_info));
280 } 310 }
281} 311}
282 312
@@ -289,7 +319,6 @@ DT_MACHINE_START(BOCKW_DT, "bockw")
289 .init_early = r8a7778_init_delay, 319 .init_early = r8a7778_init_delay,
290 .init_irq = r8a7778_init_irq_dt, 320 .init_irq = r8a7778_init_irq_dt,
291 .init_machine = bockw_init, 321 .init_machine = bockw_init,
292 .init_time = shmobile_timer_init,
293 .dt_compat = bockw_boards_compat_dt, 322 .dt_compat = bockw_boards_compat_dt,
294 .init_late = r8a7778_init_late, 323 .init_late = r8a7778_init_late,
295MACHINE_END 324MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
deleted file mode 100644
index ef5ca0ef0cb5..000000000000
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ /dev/null
@@ -1,553 +0,0 @@
1/*
2 * kota2 board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 * Copyright (C) 2010 Takashi Yoshii <yoshii.takashi.zj@renesas.com>
7 * Copyright (C) 2009 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/pinctrl/pinconf-generic.h>
29#include <linux/platform_device.h>
30#include <linux/delay.h>
31#include <linux/io.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
34#include <linux/smsc911x.h>
35#include <linux/gpio.h>
36#include <linux/input.h>
37#include <linux/input/sh_keysc.h>
38#include <linux/gpio_keys.h>
39#include <linux/leds.h>
40#include <linux/irqchip/arm-gic.h>
41#include <linux/platform_data/leds-renesas-tpu.h>
42#include <linux/mmc/host.h>
43#include <linux/mmc/sh_mmcif.h>
44#include <linux/mfd/tmio.h>
45#include <linux/mmc/sh_mobile_sdhi.h>
46#include <mach/hardware.h>
47#include <mach/irqs.h>
48#include <mach/sh73a0.h>
49#include <mach/common.h>
50#include <asm/mach-types.h>
51#include <asm/mach/arch.h>
52#include <asm/mach/time.h>
53#include <asm/hardware/cache-l2x0.h>
54#include <asm/traps.h>
55
56/* Dummy supplies, where voltage doesn't matter */
57static struct regulator_consumer_supply dummy_supplies[] = {
58 REGULATOR_SUPPLY("vddvario", "smsc911x"),
59 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
60};
61
62/* SMSC 9220 */
63static struct resource smsc9220_resources[] = {
64 [0] = {
65 .start = 0x14000000, /* CS5A */
66 .end = 0x140000ff, /* A1->A7 */
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = SH73A0_PINT0_IRQ(2), /* PINTA2 */
71 .flags = IORESOURCE_IRQ,
72 },
73};
74
75static struct smsc911x_platform_config smsc9220_platdata = {
76 .flags = SMSC911X_USE_32BIT, /* 32-bit SW on 16-bit HW bus */
77 .phy_interface = PHY_INTERFACE_MODE_MII,
78 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
79 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
80};
81
82static struct platform_device eth_device = {
83 .name = "smsc911x",
84 .id = 0,
85 .dev = {
86 .platform_data = &smsc9220_platdata,
87 },
88 .resource = smsc9220_resources,
89 .num_resources = ARRAY_SIZE(smsc9220_resources),
90};
91
92/* KEYSC */
93static struct sh_keysc_info keysc_platdata = {
94 .mode = SH_KEYSC_MODE_6,
95 .scan_timing = 3,
96 .delay = 100,
97 .keycodes = {
98 KEY_NUMERIC_STAR, KEY_NUMERIC_0, KEY_NUMERIC_POUND,
99 0, 0, 0, 0, 0,
100 KEY_NUMERIC_7, KEY_NUMERIC_8, KEY_NUMERIC_9,
101 0, KEY_DOWN, 0, 0, 0,
102 KEY_NUMERIC_4, KEY_NUMERIC_5, KEY_NUMERIC_6,
103 KEY_LEFT, KEY_ENTER, KEY_RIGHT, 0, 0,
104 KEY_NUMERIC_1, KEY_NUMERIC_2, KEY_NUMERIC_3,
105 0, KEY_UP, 0, 0, 0,
106 0, 0, 0, 0, 0, 0, 0, 0,
107 0, 0, 0, 0, 0, 0, 0, 0,
108 0, 0, 0, 0, 0, 0, 0, 0,
109 0, 0, 0, 0, 0, 0, 0, 0,
110 },
111};
112
113static struct resource keysc_resources[] = {
114 [0] = {
115 .name = "KEYSC",
116 .start = 0xe61b0000,
117 .end = 0xe61b0098 - 1,
118 .flags = IORESOURCE_MEM,
119 },
120 [1] = {
121 .start = gic_spi(71),
122 .flags = IORESOURCE_IRQ,
123 },
124};
125
126static struct platform_device keysc_device = {
127 .name = "sh_keysc",
128 .id = 0,
129 .num_resources = ARRAY_SIZE(keysc_resources),
130 .resource = keysc_resources,
131 .dev = {
132 .platform_data = &keysc_platdata,
133 },
134};
135
136/* GPIO KEY */
137#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
138
139static struct gpio_keys_button gpio_buttons[] = {
140 GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
141 GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
142 GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
143 GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
144 GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
145 GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
146 GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
147 GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
148 /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
149 GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
150 /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
151};
152
153static struct gpio_keys_platform_data gpio_key_info = {
154 .buttons = gpio_buttons,
155 .nbuttons = ARRAY_SIZE(gpio_buttons),
156};
157
158static struct platform_device gpio_keys_device = {
159 .name = "gpio-keys",
160 .id = -1,
161 .dev = {
162 .platform_data = &gpio_key_info,
163 },
164};
165
166/* GPIO LED */
167#define GPIO_LED(n, g) { .name = n, .gpio = g }
168
169static struct gpio_led gpio_leds[] = {
170 GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
171 GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
172 GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
173};
174
175static struct gpio_led_platform_data gpio_leds_info = {
176 .leds = gpio_leds,
177 .num_leds = ARRAY_SIZE(gpio_leds),
178};
179
180static struct platform_device gpio_leds_device = {
181 .name = "leds-gpio",
182 .id = -1,
183 .dev = {
184 .platform_data = &gpio_leds_info,
185 },
186};
187
188/* TPU LED */
189static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
190 .name = "V2513",
191 .pin_gpio_fn = GPIO_FN_TPU1TO2,
192 .pin_gpio = 153,
193 .channel_offset = 0x90,
194 .timer_bit = 2,
195 .max_brightness = 1000,
196};
197
198static struct resource tpu12_resources[] = {
199 [0] = {
200 .name = "TPU12",
201 .start = 0xe6610090,
202 .end = 0xe66100b5,
203 .flags = IORESOURCE_MEM,
204 },
205};
206
207static struct platform_device leds_tpu12_device = {
208 .name = "leds-renesas-tpu",
209 .id = 12,
210 .dev = {
211 .platform_data = &led_renesas_tpu12_pdata,
212 },
213 .num_resources = ARRAY_SIZE(tpu12_resources),
214 .resource = tpu12_resources,
215};
216
217static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
218 .name = "V2514",
219 .pin_gpio_fn = GPIO_FN_TPU4TO1,
220 .pin_gpio = 199,
221 .channel_offset = 0x50,
222 .timer_bit = 1,
223 .max_brightness = 1000,
224};
225
226static struct resource tpu41_resources[] = {
227 [0] = {
228 .name = "TPU41",
229 .start = 0xe6640050,
230 .end = 0xe6640075,
231 .flags = IORESOURCE_MEM,
232 },
233};
234
235static struct platform_device leds_tpu41_device = {
236 .name = "leds-renesas-tpu",
237 .id = 41,
238 .dev = {
239 .platform_data = &led_renesas_tpu41_pdata,
240 },
241 .num_resources = ARRAY_SIZE(tpu41_resources),
242 .resource = tpu41_resources,
243};
244
245static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
246 .name = "V2515",
247 .pin_gpio_fn = GPIO_FN_TPU2TO1,
248 .pin_gpio = 197,
249 .channel_offset = 0x50,
250 .timer_bit = 1,
251 .max_brightness = 1000,
252};
253
254static struct resource tpu21_resources[] = {
255 [0] = {
256 .name = "TPU21",
257 .start = 0xe6620050,
258 .end = 0xe6620075,
259 .flags = IORESOURCE_MEM,
260 },
261};
262
263static struct platform_device leds_tpu21_device = {
264 .name = "leds-renesas-tpu",
265 .id = 21,
266 .dev = {
267 .platform_data = &led_renesas_tpu21_pdata,
268 },
269 .num_resources = ARRAY_SIZE(tpu21_resources),
270 .resource = tpu21_resources,
271};
272
273static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
274 .name = "KEYLED",
275 .pin_gpio_fn = GPIO_FN_TPU3TO0,
276 .pin_gpio = 163,
277 .channel_offset = 0x10,
278 .timer_bit = 0,
279 .max_brightness = 1000,
280};
281
282static struct resource tpu30_resources[] = {
283 [0] = {
284 .name = "TPU30",
285 .start = 0xe6630010,
286 .end = 0xe6630035,
287 .flags = IORESOURCE_MEM,
288 },
289};
290
291static struct platform_device leds_tpu30_device = {
292 .name = "leds-renesas-tpu",
293 .id = 30,
294 .dev = {
295 .platform_data = &led_renesas_tpu30_pdata,
296 },
297 .num_resources = ARRAY_SIZE(tpu30_resources),
298 .resource = tpu30_resources,
299};
300
301/* Fixed 1.8V regulator to be used by MMCIF */
302static struct regulator_consumer_supply fixed1v8_power_consumers[] =
303{
304 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
305 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
306};
307
308/* MMCIF */
309static struct resource mmcif_resources[] = {
310 [0] = {
311 .name = "MMCIF",
312 .start = 0xe6bd0000,
313 .end = 0xe6bd00ff,
314 .flags = IORESOURCE_MEM,
315 },
316 [1] = {
317 .start = gic_spi(140),
318 .flags = IORESOURCE_IRQ,
319 },
320 [2] = {
321 .start = gic_spi(141),
322 .flags = IORESOURCE_IRQ,
323 },
324};
325
326static struct sh_mmcif_plat_data mmcif_info = {
327 .ocr = MMC_VDD_165_195,
328 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
329};
330
331static struct platform_device mmcif_device = {
332 .name = "sh_mmcif",
333 .id = 0,
334 .dev = {
335 .platform_data = &mmcif_info,
336 },
337 .num_resources = ARRAY_SIZE(mmcif_resources),
338 .resource = mmcif_resources,
339};
340
341/* Fixed 3.3V regulator to be used by SDHI0 and SDHI1 */
342static struct regulator_consumer_supply fixed3v3_power_consumers[] =
343{
344 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
345 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
346 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
347 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
348};
349
350/* SDHI0 */
351static struct sh_mobile_sdhi_info sdhi0_info = {
352 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
353 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
354};
355
356static struct resource sdhi0_resources[] = {
357 [0] = {
358 .name = "SDHI0",
359 .start = 0xee100000,
360 .end = 0xee1000ff,
361 .flags = IORESOURCE_MEM,
362 },
363 [1] = {
364 .start = gic_spi(83),
365 .flags = IORESOURCE_IRQ,
366 },
367 [2] = {
368 .start = gic_spi(84),
369 .flags = IORESOURCE_IRQ,
370 },
371 [3] = {
372 .start = gic_spi(85),
373 .flags = IORESOURCE_IRQ,
374 },
375};
376
377static struct platform_device sdhi0_device = {
378 .name = "sh_mobile_sdhi",
379 .id = 0,
380 .num_resources = ARRAY_SIZE(sdhi0_resources),
381 .resource = sdhi0_resources,
382 .dev = {
383 .platform_data = &sdhi0_info,
384 },
385};
386
387/* SDHI1 */
388static struct sh_mobile_sdhi_info sdhi1_info = {
389 .tmio_caps = MMC_CAP_NONREMOVABLE | MMC_CAP_SDIO_IRQ,
390 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_HAS_IDLE_WAIT,
391};
392
393static struct resource sdhi1_resources[] = {
394 [0] = {
395 .name = "SDHI1",
396 .start = 0xee120000,
397 .end = 0xee1200ff,
398 .flags = IORESOURCE_MEM,
399 },
400 [1] = {
401 .start = gic_spi(87),
402 .flags = IORESOURCE_IRQ,
403 },
404 [2] = {
405 .start = gic_spi(88),
406 .flags = IORESOURCE_IRQ,
407 },
408 [3] = {
409 .start = gic_spi(89),
410 .flags = IORESOURCE_IRQ,
411 },
412};
413
414static struct platform_device sdhi1_device = {
415 .name = "sh_mobile_sdhi",
416 .id = 1,
417 .num_resources = ARRAY_SIZE(sdhi1_resources),
418 .resource = sdhi1_resources,
419 .dev = {
420 .platform_data = &sdhi1_info,
421 },
422};
423
424static struct platform_device *kota2_devices[] __initdata = {
425 &eth_device,
426 &keysc_device,
427 &gpio_keys_device,
428 &gpio_leds_device,
429 &leds_tpu12_device,
430 &leds_tpu41_device,
431 &leds_tpu21_device,
432 &leds_tpu30_device,
433 &mmcif_device,
434 &sdhi0_device,
435 &sdhi1_device,
436};
437
438static unsigned long pin_pullup_conf[] = {
439 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
440};
441
442static const struct pinctrl_map kota2_pinctrl_map[] = {
443 /* KEYSC */
444 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
445 "keysc_in8", "keysc"),
446 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
447 "keysc_out04", "keysc"),
448 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
449 "keysc_out5", "keysc"),
450 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
451 "keysc_out6_0", "keysc"),
452 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
453 "keysc_out7_0", "keysc"),
454 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
455 "keysc_out8_0", "keysc"),
456 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
457 "keysc_in8", pin_pullup_conf),
458 /* MMCIF */
459 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
460 "mmc0_data8_0", "mmc0"),
461 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
462 "mmc0_ctrl_0", "mmc0"),
463 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
464 "PORT279", pin_pullup_conf),
465 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
466 "mmc0_data8_0", pin_pullup_conf),
467 /* SCIFA2 (UART2) */
468 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
469 "scifa2_data_0", "scifa2"),
470 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
471 "scifa2_ctrl_0", "scifa2"),
472 /* SCIFA4 (UART1) */
473 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
474 "scifa4_data", "scifa4"),
475 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
476 "scifa4_ctrl", "scifa4"),
477 /* SCIFB (BT) */
478 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
479 "scifb_data_0", "scifb"),
480 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
481 "scifb_clk_0", "scifb"),
482 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
483 "scifb_ctrl_0", "scifb"),
484 /* SDHI0 (microSD) */
485 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
486 "sdhi0_data4", "sdhi0"),
487 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
488 "sdhi0_ctrl", "sdhi0"),
489 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
490 "sdhi0_cd", "sdhi0"),
491 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
492 "sdhi0_data4", pin_pullup_conf),
493 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
494 "PORT256", pin_pullup_conf),
495 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
496 "PORT251", pin_pullup_conf),
497 /* SDHI1 (BCM4330) */
498 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
499 "sdhi1_data4", "sdhi1"),
500 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
501 "sdhi1_ctrl", "sdhi1"),
502 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
503 "sdhi1_data4", pin_pullup_conf),
504 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
505 "PORT263", pin_pullup_conf),
506 /* SMSC911X */
507 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
508 "bsc_data_0_7", "bsc"),
509 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
510 "bsc_data_8_15", "bsc"),
511 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
512 "bsc_cs5_a", "bsc"),
513 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
514 "bsc_we0", "bsc"),
515};
516
517static void __init kota2_init(void)
518{
519 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
520 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
521 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
522 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
523 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
524
525 pinctrl_register_mappings(kota2_pinctrl_map,
526 ARRAY_SIZE(kota2_pinctrl_map));
527 sh73a0_pinmux_init();
528
529 /* SMSC911X */
530 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
531 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
532
533 /* MMCIF */
534 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
535
536#ifdef CONFIG_CACHE_L2X0
537 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
538 l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
539#endif
540 sh73a0_add_standard_devices();
541 platform_add_devices(kota2_devices, ARRAY_SIZE(kota2_devices));
542}
543
544MACHINE_START(KOTA2, "kota2")
545 .smp = smp_ops(sh73a0_smp_ops),
546 .map_io = sh73a0_map_io,
547 .init_early = sh73a0_add_early_devices,
548 .nr_irqs = NR_IRQS_LEGACY,
549 .init_irq = sh73a0_init_irq,
550 .init_machine = kota2_init,
551 .init_late = shmobile_init_late,
552 .init_time = sh73a0_earlytimer_init,
553MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d-reference.c b/arch/arm/mach-shmobile/board-kzm9d-reference.c
new file mode 100644
index 000000000000..8f8bb2fab076
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-kzm9d-reference.c
@@ -0,0 +1,47 @@
1/*
2 * kzm9d board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/of_platform.h>
23#include <mach/emev2.h>
24#include <mach/common.h>
25#include <asm/mach/arch.h>
26
27static void __init kzm9d_add_standard_devices(void)
28{
29 if (!IS_ENABLED(CONFIG_COMMON_CLK))
30 emev2_clock_init();
31
32 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
33}
34
35static const char *kzm9d_boards_compat_dt[] __initdata = {
36 "renesas,kzm9d-reference",
37 NULL,
38};
39
40DT_MACHINE_START(KZM9D_DT, "kzm9d")
41 .smp = smp_ops(emev2_smp_ops),
42 .map_io = emev2_map_io,
43 .init_early = emev2_init_delay,
44 .init_machine = kzm9d_add_standard_devices,
45 .init_late = shmobile_init_late,
46 .dt_compat = kzm9d_boards_compat_dt,
47MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9d.c b/arch/arm/mach-shmobile/board-kzm9d.c
index 4368000e1127..30c2cc695b12 100644
--- a/arch/arm/mach-shmobile/board-kzm9d.c
+++ b/arch/arm/mach-shmobile/board-kzm9d.c
@@ -85,9 +85,7 @@ static const char *kzm9d_boards_compat_dt[] __initdata = {
85DT_MACHINE_START(KZM9D_DT, "kzm9d") 85DT_MACHINE_START(KZM9D_DT, "kzm9d")
86 .smp = smp_ops(emev2_smp_ops), 86 .smp = smp_ops(emev2_smp_ops),
87 .map_io = emev2_map_io, 87 .map_io = emev2_map_io,
88 .init_early = emev2_add_early_devices, 88 .init_early = emev2_init_delay,
89 .nr_irqs = NR_IRQS_LEGACY,
90 .init_irq = emev2_init_irq,
91 .init_machine = kzm9d_add_standard_devices, 89 .init_machine = kzm9d_add_standard_devices,
92 .init_late = shmobile_init_late, 90 .init_late = shmobile_init_late,
93 .dt_compat = kzm9d_boards_compat_dt, 91 .dt_compat = kzm9d_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
index 44055fe8a45c..598e32488410 100644
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c
@@ -21,67 +21,19 @@
21 */ 21 */
22 22
23#include <linux/delay.h> 23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/io.h> 24#include <linux/io.h>
26#include <linux/irq.h> 25#include <linux/irq.h>
27#include <linux/irqchip.h>
28#include <linux/input.h> 26#include <linux/input.h>
29#include <linux/of_platform.h> 27#include <linux/of_platform.h>
30#include <linux/pinctrl/machine.h>
31#include <linux/pinctrl/pinconf-generic.h>
32#include <mach/sh73a0.h> 28#include <mach/sh73a0.h>
33#include <mach/common.h> 29#include <mach/common.h>
34#include <asm/hardware/cache-l2x0.h> 30#include <asm/hardware/cache-l2x0.h>
35#include <asm/mach-types.h> 31#include <asm/mach-types.h>
36#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
37 33
38static unsigned long pin_pullup_conf[] = {
39 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
40};
41
42static const struct pinctrl_map kzm_pinctrl_map[] = {
43 PIN_MAP_MUX_GROUP_DEFAULT("e6826000.i2c", "pfc-sh73a0",
44 "i2c3_1", "i2c3"),
45 /* MMCIF */
46 PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
47 "mmc0_data8_0", "mmc0"),
48 PIN_MAP_MUX_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
49 "mmc0_ctrl_0", "mmc0"),
50 PIN_MAP_CONFIGS_PIN_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
51 "PORT279", pin_pullup_conf),
52 PIN_MAP_CONFIGS_GROUP_DEFAULT("e6bd0000.mmcif", "pfc-sh73a0",
53 "mmc0_data8_0", pin_pullup_conf),
54 /* SCIFA4 */
55 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
56 "scifa4_data", "scifa4"),
57 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
58 "scifa4_ctrl", "scifa4"),
59 /* SDHI0 */
60 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
61 "sdhi0_data4", "sdhi0"),
62 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
63 "sdhi0_ctrl", "sdhi0"),
64 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
65 "sdhi0_cd", "sdhi0"),
66 PIN_MAP_MUX_GROUP_DEFAULT("ee100000.sdhi", "pfc-sh73a0",
67 "sdhi0_wp", "sdhi0"),
68 /* SDHI2 */
69 PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
70 "sdhi2_data4", "sdhi2"),
71 PIN_MAP_MUX_GROUP_DEFAULT("ee140000.sdhi", "pfc-sh73a0",
72 "sdhi2_ctrl", "sdhi2"),
73};
74
75static void __init kzm_init(void) 34static void __init kzm_init(void)
76{ 35{
77 sh73a0_add_standard_devices_dt(); 36 sh73a0_add_standard_devices_dt();
78 pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
79 sh73a0_pinmux_init();
80
81 /* enable SD */
82 gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
83
84 gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
85 37
86#ifdef CONFIG_CACHE_L2X0 38#ifdef CONFIG_CACHE_L2X0
87 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ 39 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
@@ -99,8 +51,6 @@ DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
99 .map_io = sh73a0_map_io, 51 .map_io = sh73a0_map_io,
100 .init_early = sh73a0_init_delay, 52 .init_early = sh73a0_init_delay,
101 .nr_irqs = NR_IRQS_LEGACY, 53 .nr_irqs = NR_IRQS_LEGACY,
102 .init_irq = irqchip_init,
103 .init_machine = kzm_init, 54 .init_machine = kzm_init,
104 .init_time = shmobile_timer_init,
105 .dt_compat = kzm9g_boards_compat_dt, 55 .dt_compat = kzm9g_boards_compat_dt,
106MACHINE_END 56MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 1068120d339f..f1994968d303 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -54,14 +54,14 @@
54/* 54/*
55 * external GPIO 55 * external GPIO
56 */ 56 */
57#define GPIO_PCF8575_BASE (GPIO_NR) 57#define GPIO_PCF8575_BASE (310)
58#define GPIO_PCF8575_PORT10 (GPIO_NR + 8) 58#define GPIO_PCF8575_PORT10 (GPIO_PCF8575_BASE + 8)
59#define GPIO_PCF8575_PORT11 (GPIO_NR + 9) 59#define GPIO_PCF8575_PORT11 (GPIO_PCF8575_BASE + 9)
60#define GPIO_PCF8575_PORT12 (GPIO_NR + 10) 60#define GPIO_PCF8575_PORT12 (GPIO_PCF8575_BASE + 10)
61#define GPIO_PCF8575_PORT13 (GPIO_NR + 11) 61#define GPIO_PCF8575_PORT13 (GPIO_PCF8575_BASE + 11)
62#define GPIO_PCF8575_PORT14 (GPIO_NR + 12) 62#define GPIO_PCF8575_PORT14 (GPIO_PCF8575_BASE + 12)
63#define GPIO_PCF8575_PORT15 (GPIO_NR + 13) 63#define GPIO_PCF8575_PORT15 (GPIO_PCF8575_BASE + 13)
64#define GPIO_PCF8575_PORT16 (GPIO_NR + 14) 64#define GPIO_PCF8575_PORT16 (GPIO_PCF8575_BASE + 14)
65 65
66/* Dummy supplies, where voltage doesn't matter */ 66/* Dummy supplies, where voltage doesn't matter */
67static struct regulator_consumer_supply dummy_supplies[] = { 67static struct regulator_consumer_supply dummy_supplies[] = {
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c
new file mode 100644
index 000000000000..9c316a1b2e32
--- /dev/null
+++ b/arch/arm/mach-shmobile/board-lager-reference.c
@@ -0,0 +1,45 @@
1/*
2 * Lager board support - Reference DT implementation
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Simon Horman
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/of_platform.h>
23#include <mach/r8a7790.h>
24#include <asm/mach/arch.h>
25
26static void __init lager_add_standard_devices(void)
27{
28 /* clocks are setup late during boot in the case of DT */
29 r8a7790_clock_init();
30
31 r8a7790_add_dt_devices();
32 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
33}
34
35static const char *lager_boards_compat_dt[] __initdata = {
36 "renesas,lager-reference",
37 NULL,
38};
39
40DT_MACHINE_START(LAGER_DT, "lager")
41 .init_early = r8a7790_init_delay,
42 .init_machine = lager_add_standard_devices,
43 .init_time = r8a7790_timer_init,
44 .dt_compat = lager_boards_compat_dt,
45MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c
index 8d6bd5c5efb9..4872939cdba2 100644
--- a/arch/arm/mach-shmobile/board-lager.c
+++ b/arch/arm/mach-shmobile/board-lager.c
@@ -22,13 +22,18 @@
22#include <linux/gpio_keys.h> 22#include <linux/gpio_keys.h>
23#include <linux/input.h> 23#include <linux/input.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irqchip.h>
26#include <linux/kernel.h> 25#include <linux/kernel.h>
27#include <linux/leds.h> 26#include <linux/leds.h>
27#include <linux/mmc/host.h>
28#include <linux/mmc/sh_mmcif.h>
28#include <linux/pinctrl/machine.h> 29#include <linux/pinctrl/machine.h>
29#include <linux/platform_data/gpio-rcar.h> 30#include <linux/platform_data/gpio-rcar.h>
30#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/regulator/fixed.h>
33#include <linux/regulator/machine.h>
34#include <linux/sh_eth.h>
31#include <mach/common.h> 35#include <mach/common.h>
36#include <mach/irqs.h>
32#include <mach/r8a7790.h> 37#include <mach/r8a7790.h>
33#include <asm/mach-types.h> 38#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 39#include <asm/mach/arch.h>
@@ -71,6 +76,36 @@ static __initdata struct gpio_keys_platform_data lager_keys_pdata = {
71 .nbuttons = ARRAY_SIZE(gpio_buttons), 76 .nbuttons = ARRAY_SIZE(gpio_buttons),
72}; 77};
73 78
79/* Fixed 3.3V regulator to be used by MMCIF */
80static struct regulator_consumer_supply fixed3v3_power_consumers[] =
81{
82 REGULATOR_SUPPLY("vmmc", "sh_mmcif.1"),
83};
84
85/* MMCIF */
86static struct sh_mmcif_plat_data mmcif1_pdata __initdata = {
87 .caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
88};
89
90static struct resource mmcif1_resources[] __initdata = {
91 DEFINE_RES_MEM_NAMED(0xee220000, 0x80, "MMCIF1"),
92 DEFINE_RES_IRQ(gic_spi(170)),
93};
94
95/* Ether */
96static struct sh_eth_plat_data ether_pdata __initdata = {
97 .phy = 0x1,
98 .edmac_endian = EDMAC_LITTLE_ENDIAN,
99 .register_type = SH_ETH_REG_FAST_RCAR,
100 .phy_interface = PHY_INTERFACE_MODE_RMII,
101 .ether_link_active_low = 1,
102};
103
104static struct resource ether_resources[] __initdata = {
105 DEFINE_RES_MEM(0xee700000, 0x400),
106 DEFINE_RES_IRQ(gic_spi(162)),
107};
108
74static const struct pinctrl_map lager_pinctrl_map[] = { 109static const struct pinctrl_map lager_pinctrl_map[] = {
75 /* SCIF0 (CN19: DEBUG SERIAL0) */ 110 /* SCIF0 (CN19: DEBUG SERIAL0) */
76 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790", 111 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.6", "pfc-r8a7790",
@@ -78,6 +113,20 @@ static const struct pinctrl_map lager_pinctrl_map[] = {
78 /* SCIF1 (CN20: DEBUG SERIAL1) */ 113 /* SCIF1 (CN20: DEBUG SERIAL1) */
79 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790", 114 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.7", "pfc-r8a7790",
80 "scif1_data", "scif1"), 115 "scif1_data", "scif1"),
116 /* MMCIF1 */
117 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
118 "mmc1_data8", "mmc1"),
119 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.1", "pfc-r8a7790",
120 "mmc1_ctrl", "mmc1"),
121 /* Ether */
122 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
123 "eth_link", "eth"),
124 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
125 "eth_mdio", "eth"),
126 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
127 "eth_rmii", "eth"),
128 PIN_MAP_MUX_GROUP_DEFAULT("r8a7790-ether", "pfc-r8a7790",
129 "intc_irq0", "intc"),
81}; 130};
82 131
83static void __init lager_add_standard_devices(void) 132static void __init lager_add_standard_devices(void)
@@ -95,6 +144,16 @@ static void __init lager_add_standard_devices(void)
95 platform_device_register_data(&platform_bus, "gpio-keys", -1, 144 platform_device_register_data(&platform_bus, "gpio-keys", -1,
96 &lager_keys_pdata, 145 &lager_keys_pdata,
97 sizeof(lager_keys_pdata)); 146 sizeof(lager_keys_pdata));
147 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
148 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
149 platform_device_register_resndata(&platform_bus, "sh_mmcif", 1,
150 mmcif1_resources, ARRAY_SIZE(mmcif1_resources),
151 &mmcif1_pdata, sizeof(mmcif1_pdata));
152
153 platform_device_register_resndata(&platform_bus, "r8a7790-ether", -1,
154 ether_resources,
155 ARRAY_SIZE(ether_resources),
156 &ether_pdata, sizeof(ether_pdata));
98} 157}
99 158
100static const char *lager_boards_compat_dt[] __initdata = { 159static const char *lager_boards_compat_dt[] __initdata = {
@@ -103,7 +162,7 @@ static const char *lager_boards_compat_dt[] __initdata = {
103}; 162};
104 163
105DT_MACHINE_START(LAGER_DT, "lager") 164DT_MACHINE_START(LAGER_DT, "lager")
106 .init_irq = irqchip_init, 165 .init_early = r8a7790_init_delay,
107 .init_time = r8a7790_timer_init, 166 .init_time = r8a7790_timer_init,
108 .init_machine = lager_add_standard_devices, 167 .init_machine = lager_add_standard_devices,
109 .dt_compat = lager_boards_compat_dt, 168 .dt_compat = lager_boards_compat_dt,
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 85f51a849a50..af06753eb809 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -41,6 +41,7 @@
41#include <linux/mtd/physmap.h> 41#include <linux/mtd/physmap.h>
42#include <linux/mtd/sh_flctl.h> 42#include <linux/mtd/sh_flctl.h>
43#include <linux/pinctrl/machine.h> 43#include <linux/pinctrl/machine.h>
44#include <linux/platform_data/gpio_backlight.h>
44#include <linux/pm_clock.h> 45#include <linux/pm_clock.h>
45#include <linux/regulator/fixed.h> 46#include <linux/regulator/fixed.h>
46#include <linux/regulator/machine.h> 47#include <linux/regulator/machine.h>
@@ -49,7 +50,6 @@
49#include <linux/tca6416_keypad.h> 50#include <linux/tca6416_keypad.h>
50#include <linux/usb/renesas_usbhs.h> 51#include <linux/usb/renesas_usbhs.h>
51#include <linux/dma-mapping.h> 52#include <linux/dma-mapping.h>
52
53#include <video/sh_mobile_hdmi.h> 53#include <video/sh_mobile_hdmi.h>
54#include <video/sh_mobile_lcdc.h> 54#include <video/sh_mobile_lcdc.h>
55#include <media/sh_mobile_ceu.h> 55#include <media/sh_mobile_ceu.h>
@@ -346,7 +346,7 @@ static struct platform_device meram_device = {
346 }, 346 },
347}; 347};
348 348
349/* LCDC */ 349/* LCDC and backlight */
350static struct fb_videomode mackerel_lcdc_modes[] = { 350static struct fb_videomode mackerel_lcdc_modes[] = {
351 { 351 {
352 .name = "WVGA Panel", 352 .name = "WVGA Panel",
@@ -362,13 +362,6 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
362 }, 362 },
363}; 363};
364 364
365static int mackerel_set_brightness(int brightness)
366{
367 gpio_set_value(31, brightness);
368
369 return 0;
370}
371
372static const struct sh_mobile_meram_cfg lcd_meram_cfg = { 365static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
373 .icb[0] = { 366 .icb[0] = {
374 .meram_size = 0x40, 367 .meram_size = 0x40,
@@ -393,11 +386,6 @@ static struct sh_mobile_lcdc_info lcdc_info = {
393 .width = 152, 386 .width = 152,
394 .height = 91, 387 .height = 91,
395 }, 388 },
396 .bl_info = {
397 .name = "sh_mobile_lcdc_bl",
398 .max_brightness = 1,
399 .set_brightness = mackerel_set_brightness,
400 },
401 .meram_cfg = &lcd_meram_cfg, 389 .meram_cfg = &lcd_meram_cfg,
402 } 390 }
403}; 391};
@@ -425,6 +413,20 @@ static struct platform_device lcdc_device = {
425 }, 413 },
426}; 414};
427 415
416static struct gpio_backlight_platform_data gpio_backlight_data = {
417 .fbdev = &lcdc_device.dev,
418 .gpio = 31,
419 .def_value = 1,
420 .name = "backlight",
421};
422
423static struct platform_device gpio_backlight_device = {
424 .name = "gpio-backlight",
425 .dev = {
426 .platform_data = &gpio_backlight_data,
427 },
428};
429
428/* HDMI */ 430/* HDMI */
429static struct sh_mobile_hdmi_info hdmi_info = { 431static struct sh_mobile_hdmi_info hdmi_info = {
430 .flags = HDMI_SND_SRC_SPDIF, 432 .flags = HDMI_SND_SRC_SPDIF,
@@ -1231,6 +1233,7 @@ static struct platform_device *mackerel_devices[] __initdata = {
1231 &nor_flash_device, 1233 &nor_flash_device,
1232 &smc911x_device, 1234 &smc911x_device,
1233 &lcdc_device, 1235 &lcdc_device,
1236 &gpio_backlight_device,
1234 &usbhs0_device, 1237 &usbhs0_device,
1235 &usbhs1_device, 1238 &usbhs1_device,
1236 &leds_device, 1239 &leds_device,
@@ -1441,9 +1444,6 @@ static void __init mackerel_init(void)
1441 ARRAY_SIZE(mackerel_pinctrl_map)); 1444 ARRAY_SIZE(mackerel_pinctrl_map));
1442 sh7372_pinmux_init(); 1445 sh7372_pinmux_init();
1443 1446
1444 /* backlight, off by default */
1445 gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
1446
1447 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1447 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1448 1448
1449 /* USBHS0 */ 1449 /* USBHS0 */
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c
index 480d882e42c7..3f4250a2d4eb 100644
--- a/arch/arm/mach-shmobile/board-marzen-reference.c
+++ b/arch/arm/mach-shmobile/board-marzen-reference.c
@@ -19,42 +19,14 @@
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 20 */
21 21
22#include <linux/pinctrl/machine.h>
23#include <mach/r8a7779.h> 22#include <mach/r8a7779.h>
24#include <mach/common.h> 23#include <mach/common.h>
25#include <mach/irqs.h> 24#include <mach/irqs.h>
26#include <asm/irq.h> 25#include <asm/irq.h>
27#include <asm/mach/arch.h> 26#include <asm/mach/arch.h>
28 27
29static const struct pinctrl_map marzen_pinctrl_map[] = {
30 /* SCIF2 (CN18: DEBUG0) */
31 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
32 "scif2_data_c", "scif2"),
33 /* SCIF4 (CN19: DEBUG1) */
34 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
35 "scif4_data", "scif4"),
36 /* SDHI0 */
37 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
38 "sdhi0_data4", "sdhi0"),
39 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
40 "sdhi0_ctrl", "sdhi0"),
41 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
42 "sdhi0_cd", "sdhi0"),
43 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
44 "sdhi0_wp", "sdhi0"),
45 /* SMSC */
46 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
47 "intc_irq1_b", "intc"),
48 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
49 "lbsc_ex_cs0", "lbsc"),
50};
51
52static void __init marzen_init(void) 28static void __init marzen_init(void)
53{ 29{
54 pinctrl_register_mappings(marzen_pinctrl_map,
55 ARRAY_SIZE(marzen_pinctrl_map));
56 r8a7779_pinmux_init();
57
58 r8a7779_add_standard_devices_dt(); 30 r8a7779_add_standard_devices_dt();
59} 31}
60 32
@@ -70,6 +42,5 @@ DT_MACHINE_START(MARZEN, "marzen")
70 .nr_irqs = NR_IRQS_LEGACY, 42 .nr_irqs = NR_IRQS_LEGACY,
71 .init_irq = r8a7779_init_irq_dt, 43 .init_irq = r8a7779_init_irq_dt,
72 .init_machine = marzen_init, 44 .init_machine = marzen_init,
73 .init_time = shmobile_timer_init,
74 .dt_compat = marzen_boards_compat_dt, 45 .dt_compat = marzen_boards_compat_dt,
75MACHINE_END 46MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index ca7fb2e63c60..3f5044fda4e3 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -30,6 +30,7 @@
30#include <linux/dma-mapping.h> 30#include <linux/dma-mapping.h>
31#include <linux/pinctrl/machine.h> 31#include <linux/pinctrl/machine.h>
32#include <linux/platform_data/gpio-rcar.h> 32#include <linux/platform_data/gpio-rcar.h>
33#include <linux/platform_data/usb-rcar-phy.h>
33#include <linux/regulator/fixed.h> 34#include <linux/regulator/fixed.h>
34#include <linux/regulator/machine.h> 35#include <linux/regulator/machine.h>
35#include <linux/smsc911x.h> 36#include <linux/smsc911x.h>
@@ -39,7 +40,6 @@
39#include <linux/mmc/sh_mobile_sdhi.h> 40#include <linux/mmc/sh_mobile_sdhi.h>
40#include <linux/mfd/tmio.h> 41#include <linux/mfd/tmio.h>
41#include <media/soc_camera.h> 42#include <media/soc_camera.h>
42#include <mach/hardware.h>
43#include <mach/r8a7779.h> 43#include <mach/r8a7779.h>
44#include <mach/common.h> 44#include <mach/common.h>
45#include <mach/irqs.h> 45#include <mach/irqs.h>
@@ -59,7 +59,26 @@ static struct regulator_consumer_supply dummy_supplies[] = {
59 REGULATOR_SUPPLY("vdd33a", "smsc911x"), 59 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
60}; 60};
61 61
62static struct rcar_phy_platform_data usb_phy_platform_data __initdata; 62/* USB PHY */
63static struct resource usb_phy_resources[] = {
64 [0] = {
65 .start = 0xffe70800,
66 .end = 0xffe70900 - 1,
67 .flags = IORESOURCE_MEM,
68 },
69};
70
71static struct rcar_phy_platform_data usb_phy_platform_data;
72
73static struct platform_device usb_phy = {
74 .name = "rcar_usb_phy",
75 .id = -1,
76 .dev = {
77 .platform_data = &usb_phy_platform_data,
78 },
79 .resource = usb_phy_resources,
80 .num_resources = ARRAY_SIZE(usb_phy_resources),
81};
63 82
64/* SMSC LAN89218 */ 83/* SMSC LAN89218 */
65static struct resource smsc911x_resources[] = { 84static struct resource smsc911x_resources[] = {
@@ -212,6 +231,7 @@ static struct platform_device *marzen_devices[] __initdata = {
212 &thermal_device, 231 &thermal_device,
213 &hspi_device, 232 &hspi_device,
214 &leds_device, 233 &leds_device,
234 &usb_phy,
215 &camera0_device, 235 &camera0_device,
216 &camera1_device, 236 &camera1_device,
217}; 237};
@@ -274,19 +294,23 @@ static void __init marzen_init(void)
274 r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */ 294 r8a7779_init_irq_extpin(1); /* IRQ1 as individual interrupt */
275 295
276 r8a7779_add_standard_devices(); 296 r8a7779_add_standard_devices();
277 r8a7779_add_usb_phy_device(&usb_phy_platform_data);
278 r8a7779_add_vin_device(1, &vin_platform_data); 297 r8a7779_add_vin_device(1, &vin_platform_data);
279 r8a7779_add_vin_device(3, &vin_platform_data); 298 r8a7779_add_vin_device(3, &vin_platform_data);
280 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); 299 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
281} 300}
282 301
283MACHINE_START(MARZEN, "marzen") 302static const char *marzen_boards_compat_dt[] __initdata = {
303 "renesas,marzen",
304 NULL,
305};
306
307DT_MACHINE_START(MARZEN, "marzen")
284 .smp = smp_ops(r8a7779_smp_ops), 308 .smp = smp_ops(r8a7779_smp_ops),
285 .map_io = r8a7779_map_io, 309 .map_io = r8a7779_map_io,
286 .init_early = r8a7779_add_early_devices, 310 .init_early = r8a7779_add_early_devices,
287 .nr_irqs = NR_IRQS_LEGACY, 311 .init_irq = r8a7779_init_irq_dt,
288 .init_irq = r8a7779_init_irq,
289 .init_machine = marzen_init, 312 .init_machine = marzen_init,
290 .init_late = r8a7779_init_late, 313 .init_late = r8a7779_init_late,
314 .dt_compat = marzen_boards_compat_dt,
291 .init_time = r8a7779_earlytimer_init, 315 .init_time = r8a7779_earlytimer_init,
292MACHINE_END 316MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-emev2.c b/arch/arm/mach-shmobile/clock-emev2.c
index 4710f1847bb7..5ac13ba71d54 100644
--- a/arch/arm/mach-shmobile/clock-emev2.c
+++ b/arch/arm/mach-shmobile/clock-emev2.c
@@ -40,7 +40,6 @@
40#define USIB2SCLKDIV 0x65c 40#define USIB2SCLKDIV 0x65c
41#define USIB3SCLKDIV 0x660 41#define USIB3SCLKDIV 0x660
42#define STI_CLKSEL 0x688 42#define STI_CLKSEL 0x688
43#define SMU_GENERAL_REG0 0x7c0
44 43
45/* not pretty, but hey */ 44/* not pretty, but hey */
46static void __iomem *smu_base; 45static void __iomem *smu_base;
@@ -51,11 +50,6 @@ static void emev2_smu_write(unsigned long value, int offs)
51 iowrite32(value, smu_base + offs); 50 iowrite32(value, smu_base + offs);
52} 51}
53 52
54void emev2_set_boot_vector(unsigned long value)
55{
56 emev2_smu_write(value, SMU_GENERAL_REG0);
57}
58
59static struct clk_mapping smu_mapping = { 53static struct clk_mapping smu_mapping = {
60 .phys = EMEV2_SMU_BASE, 54 .phys = EMEV2_SMU_BASE,
61 .len = PAGE_SIZE, 55 .len = PAGE_SIZE,
@@ -205,23 +199,11 @@ static struct clk_lookup lookups[] = {
205void __init emev2_clock_init(void) 199void __init emev2_clock_init(void)
206{ 200{
207 int k, ret = 0; 201 int k, ret = 0;
208 static int is_setup;
209
210 /* yuck, this is ugly as hell, but the non-smp case of clocks
211 * code is now designed to rely on ioremap() instead of static
212 * entity maps. in the case of smp we need access to the SMU
213 * register earlier than ioremap() is actually working without
214 * any static maps. to enable SMP in ugly but with dynamic
215 * mappings we have to call emev2_clock_init() from different
216 * places depending on UP and SMP...
217 */
218 if (is_setup++)
219 return;
220 202
221 smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE); 203 smu_base = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
222 BUG_ON(!smu_base); 204 BUG_ON(!smu_base);
223 205
224 /* setup STI timer to run on 37.768 kHz and deassert reset */ 206 /* setup STI timer to run on 32.768 kHz and deassert reset */
225 emev2_smu_write(0, STI_CLKSEL); 207 emev2_smu_write(0, STI_CLKSEL);
226 emev2_smu_write(1, STI_RSTCTRL); 208 emev2_smu_write(1, STI_RSTCTRL);
227 209
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 5f7fe628b8a1..8ea5ef6c79cc 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -30,10 +30,12 @@
30 30
31#define SMSTPCR2 0xe6150138 31#define SMSTPCR2 0xe6150138
32#define SMSTPCR3 0xe615013c 32#define SMSTPCR3 0xe615013c
33#define SMSTPCR4 0xe6150140
33#define SMSTPCR5 0xe6150144 34#define SMSTPCR5 0xe6150144
34 35
35#define FRQCRA 0xE6150000 36#define FRQCRA 0xE6150000
36#define FRQCRB 0xE6150004 37#define FRQCRB 0xE6150004
38#define FRQCRC 0xE61500E0
37#define VCLKCR1 0xE6150008 39#define VCLKCR1 0xE6150008
38#define VCLKCR2 0xE615000C 40#define VCLKCR2 0xE615000C
39#define VCLKCR3 0xE615001C 41#define VCLKCR3 0xE615001C
@@ -52,6 +54,7 @@
52#define HSICKCR 0xE615026C 54#define HSICKCR 0xE615026C
53#define M4CKCR 0xE6150098 55#define M4CKCR 0xE6150098
54#define PLLECR 0xE61500D0 56#define PLLECR 0xE61500D0
57#define PLL0CR 0xE61500D8
55#define PLL1CR 0xE6150028 58#define PLL1CR 0xE6150028
56#define PLL2CR 0xE615002C 59#define PLL2CR 0xE615002C
57#define PLL2SCR 0xE61501F4 60#define PLL2SCR 0xE61501F4
@@ -177,6 +180,7 @@ static struct sh_clk_ops pll_clk_ops = {
177 .mapping = &cpg_mapping, \ 180 .mapping = &cpg_mapping, \
178 } 181 }
179 182
183PLL_CLOCK(pll0_clk, &main_clk, pll_parent_main, 1, 20, PLL0CR, 0);
180PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1); 184PLL_CLOCK(pll1_clk, &main_clk, pll_parent_main, 1, 7, PLL1CR, 1);
181PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2); 185PLL_CLOCK(pll2_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2CR, 2);
182PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4); 186PLL_CLOCK(pll2s_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2SCR, 4);
@@ -184,6 +188,157 @@ PLL_CLOCK(pll2h_clk, &main_div2_clk, pll_parent_main_extal, 3, 5, PLL2HCR, 5);
184 188
185SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2); 189SH_FIXED_RATIO_CLK(pll1_div2_clk, pll1_clk, div2);
186 190
191static atomic_t frqcr_lock;
192
193/* Several clocks need to access FRQCRB, have to lock */
194static bool frqcr_kick_check(struct clk *clk)
195{
196 return !(ioread32(CPG_MAP(FRQCRB)) & BIT(31));
197}
198
199static int frqcr_kick_do(struct clk *clk)
200{
201 int i;
202
203 /* set KICK bit in FRQCRB to update hardware setting, check success */
204 iowrite32(ioread32(CPG_MAP(FRQCRB)) | BIT(31), CPG_MAP(FRQCRB));
205 for (i = 1000; i; i--)
206 if (ioread32(CPG_MAP(FRQCRB)) & BIT(31))
207 cpu_relax();
208 else
209 return 0;
210
211 return -ETIMEDOUT;
212}
213
214static int zclk_set_rate(struct clk *clk, unsigned long rate)
215{
216 void __iomem *frqcrc;
217 int ret;
218 unsigned long step, p_rate;
219 u32 val;
220
221 if (!clk->parent || !__clk_get(clk->parent))
222 return -ENODEV;
223
224 if (!atomic_inc_and_test(&frqcr_lock) || !frqcr_kick_check(clk)) {
225 ret = -EBUSY;
226 goto done;
227 }
228
229 /*
230 * Users are supposed to first call clk_set_rate() only with
231 * clk_round_rate() results. So, we don't fix wrong rates here, but
232 * guard against them anyway
233 */
234
235 p_rate = clk_get_rate(clk->parent);
236 if (rate == p_rate) {
237 val = 0;
238 } else {
239 step = DIV_ROUND_CLOSEST(p_rate, 32);
240
241 if (rate > p_rate || rate < step) {
242 ret = -EINVAL;
243 goto done;
244 }
245
246 val = 32 - rate / step;
247 }
248
249 frqcrc = clk->mapped_reg + (FRQCRC - (u32)clk->enable_reg);
250
251 iowrite32((ioread32(frqcrc) & ~(clk->div_mask << clk->enable_bit)) |
252 (val << clk->enable_bit), frqcrc);
253
254 ret = frqcr_kick_do(clk);
255
256done:
257 atomic_dec(&frqcr_lock);
258 __clk_put(clk->parent);
259 return ret;
260}
261
262static long zclk_round_rate(struct clk *clk, unsigned long rate)
263{
264 /*
265 * theoretical rate = parent rate * multiplier / 32,
266 * where 1 <= multiplier <= 32. Therefore we should do
267 * multiplier = rate * 32 / parent rate
268 * rounded rate = parent rate * multiplier / 32.
269 * However, multiplication before division won't fit in 32 bits, so
270 * we sacrifice some precision by first dividing and then multiplying.
271 * To find the nearest divisor we calculate both and pick up the best
272 * one. This avoids 64-bit arithmetics.
273 */
274 unsigned long step, mul_min, mul_max, rate_min, rate_max;
275
276 rate_max = clk_get_rate(clk->parent);
277
278 /* output freq <= parent */
279 if (rate >= rate_max)
280 return rate_max;
281
282 step = DIV_ROUND_CLOSEST(rate_max, 32);
283 /* output freq >= parent / 32 */
284 if (step >= rate)
285 return step;
286
287 mul_min = rate / step;
288 mul_max = DIV_ROUND_UP(rate, step);
289 rate_min = step * mul_min;
290 if (mul_max == mul_min)
291 return rate_min;
292
293 rate_max = step * mul_max;
294
295 if (rate_max - rate < rate - rate_min)
296 return rate_max;
297
298 return rate_min;
299}
300
301static unsigned long zclk_recalc(struct clk *clk)
302{
303 void __iomem *frqcrc = FRQCRC - (u32)clk->enable_reg + clk->mapped_reg;
304 unsigned int max = clk->div_mask + 1;
305 unsigned long val = ((ioread32(frqcrc) >> clk->enable_bit) &
306 clk->div_mask);
307
308 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), max) *
309 (max - val);
310}
311
312static struct sh_clk_ops zclk_ops = {
313 .recalc = zclk_recalc,
314 .set_rate = zclk_set_rate,
315 .round_rate = zclk_round_rate,
316};
317
318static struct clk z_clk = {
319 .parent = &pll0_clk,
320 .div_mask = 0x1f,
321 .enable_bit = 8,
322 /* We'll need to access FRQCRB and FRQCRC */
323 .enable_reg = (void __iomem *)FRQCRB,
324 .ops = &zclk_ops,
325};
326
327/*
328 * It seems only 1/2 divider is usable in manual mode. 1/2 / 2/3
329 * switching is only available in auto-DVFS mode
330 */
331SH_FIXED_RATIO_CLK(pll0_div2_clk, pll0_clk, div2);
332
333static struct clk z2_clk = {
334 .parent = &pll0_div2_clk,
335 .div_mask = 0x1f,
336 .enable_bit = 0,
337 /* We'll need to access FRQCRB and FRQCRC */
338 .enable_reg = (void __iomem *)FRQCRB,
339 .ops = &zclk_ops,
340};
341
187static struct clk *main_clks[] = { 342static struct clk *main_clks[] = {
188 &extalr_clk, 343 &extalr_clk,
189 &extal1_clk, 344 &extal1_clk,
@@ -195,22 +350,23 @@ static struct clk *main_clks[] = {
195 &main_div2_clk, 350 &main_div2_clk,
196 &fsiack_clk, 351 &fsiack_clk,
197 &fsibck_clk, 352 &fsibck_clk,
353 &pll0_clk,
198 &pll1_clk, 354 &pll1_clk,
199 &pll1_div2_clk, 355 &pll1_div2_clk,
200 &pll2_clk, 356 &pll2_clk,
201 &pll2s_clk, 357 &pll2s_clk,
202 &pll2h_clk, 358 &pll2h_clk,
359 &z_clk,
360 &pll0_div2_clk,
361 &z2_clk,
203}; 362};
204 363
205/* DIV4 */ 364/* DIV4 */
206static void div4_kick(struct clk *clk) 365static void div4_kick(struct clk *clk)
207{ 366{
208 unsigned long value; 367 if (!WARN(!atomic_inc_and_test(&frqcr_lock), "FRQCR* lock broken!\n"))
209 368 frqcr_kick_do(clk);
210 /* set KICK bit in FRQCRB to update hardware setting */ 369 atomic_dec(&frqcr_lock);
211 value = ioread32(CPG_MAP(FRQCRB));
212 value |= (1 << 31);
213 iowrite32(value, CPG_MAP(FRQCRB));
214} 370}
215 371
216static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10}; 372static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10};
@@ -349,8 +505,10 @@ static struct clk div6_clks[DIV6_NR] = {
349/* MSTP */ 505/* MSTP */
350enum { 506enum {
351 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, 507 MSTP217, MSTP216, MSTP207, MSTP206, MSTP204, MSTP203,
352 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, 508 MSTP329, MSTP323, MSTP318, MSTP317, MSTP316,
353 MSTP522, 509 MSTP315, MSTP314, MSTP313, MSTP312, MSTP305, MSTP300,
510 MSTP411, MSTP410, MSTP409,
511 MSTP522, MSTP515,
354 MSTP_NR 512 MSTP_NR
355}; 513};
356 514
@@ -361,12 +519,22 @@ static struct clk mstp_clks[MSTP_NR] = {
361 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */ 519 [MSTP207] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 7, 0), /* SCIFB1 */
362 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */ 520 [MSTP216] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 16, 0), /* SCIFB2 */
363 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */ 521 [MSTP217] = SH_CLK_MSTP32(&div6_clks[DIV6_MP], SMSTPCR2, 17, 0), /* SCIFB3 */
522 [MSTP300] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 0, 0), /* IIC2 */
364 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */ 523 [MSTP305] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC1],SMSTPCR3, 5, 0), /* MMCIF1 */
365 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */ 524 [MSTP312] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI2],SMSTPCR3, 12, 0), /* SDHI2 */
366 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */ 525 [MSTP313] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI1],SMSTPCR3, 13, 0), /* SDHI1 */
367 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */ 526 [MSTP314] = SH_CLK_MSTP32(&div6_clks[DIV6_SDHI0],SMSTPCR3, 14, 0), /* SDHI0 */
368 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */ 527 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0],SMSTPCR3, 15, 0), /* MMCIF0 */
528 [MSTP316] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 16, 0), /* IIC6 */
529 [MSTP317] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 17, 0), /* IIC7 */
530 [MSTP318] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* IIC0 */
531 [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
532 [MSTP329] = SH_CLK_MSTP32(&extalr_clk, SMSTPCR3, 29, 0), /* CMT10 */
533 [MSTP409] = SH_CLK_MSTP32(&main_div2_clk, SMSTPCR4, 9, 0), /* IIC5 */
534 [MSTP410] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
535 [MSTP411] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
369 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */ 536 [MSTP522] = SH_CLK_MSTP32(&extal2_clk, SMSTPCR5, 22, 0), /* Thermal */
537 [MSTP515] = SH_CLK_MSTP32(&div4_clks[DIV4_HP], SMSTPCR5, 15, 0), /* IIC8 */
370}; 538};
371 539
372static struct clk_lookup lookups[] = { 540static struct clk_lookup lookups[] = {
@@ -386,6 +554,9 @@ static struct clk_lookup lookups[] = {
386 CLKDEV_CON_ID("pll2s", &pll2s_clk), 554 CLKDEV_CON_ID("pll2s", &pll2s_clk),
387 CLKDEV_CON_ID("pll2h", &pll2h_clk), 555 CLKDEV_CON_ID("pll2h", &pll2h_clk),
388 556
557 /* CPU clock */
558 CLKDEV_DEV_ID("cpufreq-cpu0", &z_clk),
559
389 /* DIV6 */ 560 /* DIV6 */
390 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]), 561 CLKDEV_CON_ID("zb", &div6_clks[DIV6_ZB]),
391 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]), 562 CLKDEV_CON_ID("vck1", &div6_clks[DIV6_VCK1]),
@@ -408,6 +579,7 @@ static struct clk_lookup lookups[] = {
408 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]), 579 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP216]),
409 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]), 580 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP217]),
410 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]), 581 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
582 CLKDEV_DEV_ID("e6520000.i2c", &mstp_clks[MSTP300]),
411 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 583 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
412 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 584 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
413 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]), 585 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
@@ -418,6 +590,15 @@ static struct clk_lookup lookups[] = {
418 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 590 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
419 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 591 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
420 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 592 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
593 CLKDEV_DEV_ID("e6550000.i2c", &mstp_clks[MSTP316]),
594 CLKDEV_DEV_ID("e6560000.i2c", &mstp_clks[MSTP317]),
595 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
596 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
597 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
598 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
599 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
600 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
601 CLKDEV_DEV_ID("e6570000.i2c", &mstp_clks[MSTP515]),
421 602
422 /* for DT */ 603 /* for DT */
423 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]), 604 CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
@@ -429,6 +610,8 @@ void __init r8a73a4_clock_init(void)
429 int k, ret = 0; 610 int k, ret = 0;
430 u32 ckscr; 611 u32 ckscr;
431 612
613 atomic_set(&frqcr_lock, -1);
614
432 reg = ioremap_nocache(CKSCR, PAGE_SIZE); 615 reg = ioremap_nocache(CKSCR, PAGE_SIZE);
433 BUG_ON(!reg); 616 BUG_ON(!reg);
434 ckscr = ioread32(reg); 617 ckscr = ioread32(reg);
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index de10fd78bf2b..c826bca4024e 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = {
596 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), 596 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
597 CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]), 597 CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
598 CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]), 598 CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
599 CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]), 599 CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
600 CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
600 601
601 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), 602 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
602 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), 603 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c
index 5d71313df52d..fc36d3db0b4d 100644
--- a/arch/arm/mach-shmobile/clock-r8a7790.c
+++ b/arch/arm/mach-shmobile/clock-r8a7790.c
@@ -24,6 +24,7 @@
24#include <linux/clkdev.h> 24#include <linux/clkdev.h>
25#include <mach/clock.h> 25#include <mach/clock.h>
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/r8a7790.h>
27 28
28/* 29/*
29 * MD EXTAL PLL0 PLL1 PLL3 30 * MD EXTAL PLL0 PLL1 PLL3
@@ -42,16 +43,16 @@
42 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below 43 * see "p1 / 2" on R8A7790_CLOCK_ROOT() below
43 */ 44 */
44 45
45#define MD(nr) (1 << nr)
46
47#define CPG_BASE 0xe6150000 46#define CPG_BASE 0xe6150000
48#define CPG_LEN 0x1000 47#define CPG_LEN 0x1000
49 48
49#define SMSTPCR1 0xe6150134
50#define SMSTPCR2 0xe6150138 50#define SMSTPCR2 0xe6150138
51#define SMSTPCR3 0xe615013c 51#define SMSTPCR3 0xe615013c
52#define SMSTPCR5 0xe6150144
52#define SMSTPCR7 0xe615014c 53#define SMSTPCR7 0xe615014c
54#define SMSTPCR8 0xe6150990
53 55
54#define MODEMR 0xE6160060
55#define SDCKCR 0xE6150074 56#define SDCKCR 0xE6150074
56#define SD2CKCR 0xE6150078 57#define SD2CKCR 0xE6150078
57#define SD3CKCR 0xE615007C 58#define SD3CKCR 0xE615007C
@@ -180,16 +181,23 @@ static struct clk div6_clks[DIV6_NR] = {
180 181
181/* MSTP */ 182/* MSTP */
182enum { 183enum {
184 MSTP813,
183 MSTP721, MSTP720, 185 MSTP721, MSTP720,
184 MSTP717, MSTP716, 186 MSTP717, MSTP716,
187 MSTP522,
185 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304, 188 MSTP315, MSTP314, MSTP313, MSTP312, MSTP311, MSTP305, MSTP304,
186 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, 189 MSTP216, MSTP207, MSTP206, MSTP204, MSTP203, MSTP202,
190 MSTP124,
187 MSTP_NR 191 MSTP_NR
188}; 192};
189 193
190static struct clk mstp_clks[MSTP_NR] = { 194static struct clk mstp_clks[MSTP_NR] = {
195 [MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
191 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */ 196 [MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
192 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */ 197 [MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
198 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
199 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
200 [MSTP522] = SH_CLK_MSTP32(&extal_clk, SMSTPCR5, 22, 0), /* Thermal */
193 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */ 201 [MSTP315] = SH_CLK_MSTP32(&div6_clks[DIV6_MMC0], SMSTPCR3, 15, 0), /* MMC0 */
194 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */ 202 [MSTP314] = SH_CLK_MSTP32(&div4_clks[DIV4_SD0], SMSTPCR3, 14, 0), /* SDHI0 */
195 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */ 203 [MSTP313] = SH_CLK_MSTP32(&div4_clks[DIV4_SD1], SMSTPCR3, 13, 0), /* SDHI1 */
@@ -203,8 +211,7 @@ static struct clk mstp_clks[MSTP_NR] = {
203 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */ 211 [MSTP204] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 4, 0), /* SCIFA0 */
204 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */ 212 [MSTP203] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 3, 0), /* SCIFA1 */
205 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */ 213 [MSTP202] = SH_CLK_MSTP32(&mp_clk, SMSTPCR2, 2, 0), /* SCIFA2 */
206 [MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */ 214 [MSTP124] = SH_CLK_MSTP32(&rclk_clk, SMSTPCR1, 24, 0), /* CMT0 */
207 [MSTP716] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 16, 0), /* HSCIF1 */
208}; 215};
209 216
210static struct clk_lookup lookups[] = { 217static struct clk_lookup lookups[] = {
@@ -254,6 +261,8 @@ static struct clk_lookup lookups[] = {
254 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]), 261 CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
255 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]), 262 CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
256 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]), 263 CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
264 CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
265 CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
257 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]), 266 CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
258 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]), 267 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
259 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), 268 CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]),
@@ -266,6 +275,7 @@ static struct clk_lookup lookups[] = {
266 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]), 275 CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
267 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]), 276 CLKDEV_DEV_ID("ee220000.mmcif", &mstp_clks[MSTP305]),
268 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]), 277 CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
278 CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
269}; 279};
270 280
271#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \ 281#define R8A7790_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
@@ -280,14 +290,9 @@ static struct clk_lookup lookups[] = {
280 290
281void __init r8a7790_clock_init(void) 291void __init r8a7790_clock_init(void)
282{ 292{
283 void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE); 293 u32 mode = r8a7790_read_mode_pins();
284 u32 mode;
285 int k, ret = 0; 294 int k, ret = 0;
286 295
287 BUG_ON(!modemr);
288 mode = ioread32(modemr);
289 iounmap(modemr);
290
291 switch (mode & (MD(14) | MD(13))) { 296 switch (mode & (MD(14) | MD(13))) {
292 case 0: 297 case 0:
293 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88); 298 R8A7790_CLOCK_ROOT(15, &extal_clk, 172, 208, 106, 88);
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index d9fd0336b910..1942eaef5181 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -555,7 +555,7 @@ enum { MSTP001,
555 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200, 555 MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
556 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322, 556 MSTP331, MSTP329, MSTP328, MSTP325, MSTP323, MSTP322,
557 MSTP314, MSTP313, MSTP312, MSTP311, 557 MSTP314, MSTP313, MSTP312, MSTP311,
558 MSTP303, MSTP302, MSTP301, MSTP300, 558 MSTP304, MSTP303, MSTP302, MSTP301, MSTP300,
559 MSTP411, MSTP410, MSTP403, 559 MSTP411, MSTP410, MSTP403,
560 MSTP_NR }; 560 MSTP_NR };
561 561
@@ -593,6 +593,7 @@ static struct clk mstp_clks[MSTP_NR] = {
593 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */ 593 [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
594 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */ 594 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
595 [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */ 595 [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
596 [MSTP304] = MSTP(&main_div2_clk, SMSTPCR3, 4, 0), /* TPU0 */
596 [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */ 597 [MSTP303] = MSTP(&main_div2_clk, SMSTPCR3, 3, 0), /* TPU1 */
597 [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */ 598 [MSTP302] = MSTP(&main_div2_clk, SMSTPCR3, 2, 0), /* TPU2 */
598 [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */ 599 [MSTP301] = MSTP(&main_div2_clk, SMSTPCR3, 1, 0), /* TPU3 */
@@ -669,10 +670,11 @@ static struct clk_lookup lookups[] = {
669 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */ 670 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
670 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */ 671 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
671 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */ 672 CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
672 CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */ 673 CLKDEV_DEV_ID("renesas-tpu-pwm.0", &mstp_clks[MSTP304]), /* TPU0 */
673 CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */ 674 CLKDEV_DEV_ID("renesas-tpu-pwm.1", &mstp_clks[MSTP303]), /* TPU1 */
674 CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */ 675 CLKDEV_DEV_ID("renesas-tpu-pwm.2", &mstp_clks[MSTP302]), /* TPU2 */
675 CLKDEV_DEV_ID("leds-renesas-tpu.41", &mstp_clks[MSTP300]), /* TPU4 */ 676 CLKDEV_DEV_ID("renesas-tpu-pwm.3", &mstp_clks[MSTP301]), /* TPU3 */
677 CLKDEV_DEV_ID("renesas-tpu-pwm.4", &mstp_clks[MSTP300]), /* TPU4 */
676 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */ 678 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
677 CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */ 679 CLKDEV_DEV_ID("e6826000.i2c", &mstp_clks[MSTP411]), /* I2C3 */
678 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */ 680 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index bfd920083a3b..f45dde701d7b 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu)
37 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits 37 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
38 ldr r2, [r0, #8] @ SCU Power Status Register 38 ldr r2, [r0, #8] @ SCU Power Status Register
39 mov r3, #3 39 mov r3, #3
40 bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode) 40 lsl r3, r3, r1
41 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
41 str r2, [r0, #8] @ write back 42 str r2, [r0, #8] @ write back
42 43
43 b shmobile_invalidate_start 44 b shmobile_invalidate_start
44ENDPROC(shmobile_boot_scu) 45ENDPROC(shmobile_boot_scu)
45 46
46 .text 47 .text
48 .align 2
47 .globl shmobile_scu_base 49 .globl shmobile_scu_base
48shmobile_scu_base: 50shmobile_scu_base:
49 .space 4 51 .space 4
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index a9d212498987..f93751caf5cb 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,15 +24,68 @@ ENDPROC(shmobile_invalidate_start)
24 * This will be mapped at address 0 by SBAR register. 24 * This will be mapped at address 0 by SBAR register.
25 * We need _long_ jump to the physical address. 25 * We need _long_ jump to the physical address.
26 */ 26 */
27 .arm
27 .align 12 28 .align 12
28ENTRY(shmobile_boot_vector) 29ENTRY(shmobile_boot_vector)
29 ldr r0, 2f 30 ldr r0, 2f
30 ldr pc, 1f 31 ldr r1, 1f
32 bx r1
33
31ENDPROC(shmobile_boot_vector) 34ENDPROC(shmobile_boot_vector)
32 35
36 .align 2
33 .globl shmobile_boot_fn 37 .globl shmobile_boot_fn
34shmobile_boot_fn: 38shmobile_boot_fn:
351: .space 4 391: .space 4
36 .globl shmobile_boot_arg 40 .globl shmobile_boot_arg
37shmobile_boot_arg: 41shmobile_boot_arg:
382: .space 4 422: .space 4
43
44/*
45 * Per-CPU SMP boot function/argument selection code based on MPIDR
46 */
47
48ENTRY(shmobile_smp_boot)
49 @ r0 = MPIDR_HWID_BITMASK
50 mrc p15, 0, r1, c0, c0, 5 @ r1 = MPIDR
51 and r0, r1, r0 @ r0 = cpu_logical_map() value
52 mov r1, #0 @ r1 = CPU index
53 adr r5, 1f @ array of per-cpu mpidr values
54 adr r6, 2f @ array of per-cpu functions
55 adr r7, 3f @ array of per-cpu arguments
56
57shmobile_smp_boot_find_mpidr:
58 ldr r8, [r5, r1, lsl #2]
59 cmp r8, r0
60 bne shmobile_smp_boot_next
61
62 ldr r9, [r6, r1, lsl #2]
63 cmp r9, #0
64 bne shmobile_smp_boot_found
65
66shmobile_smp_boot_next:
67 add r1, r1, #1
68 cmp r1, #CONFIG_NR_CPUS
69 blo shmobile_smp_boot_find_mpidr
70
71 b shmobile_smp_sleep
72
73shmobile_smp_boot_found:
74 ldr r0, [r7, r1, lsl #2]
75 mov pc, r9
76ENDPROC(shmobile_smp_boot)
77
78ENTRY(shmobile_smp_sleep)
79 wfi
80 b shmobile_smp_boot
81ENDPROC(shmobile_smp_sleep)
82
83 .globl shmobile_smp_mpidr
84shmobile_smp_mpidr:
851: .space CONFIG_NR_CPUS * 4
86 .globl shmobile_smp_fn
87shmobile_smp_fn:
882: .space CONFIG_NR_CPUS * 4
89 .globl shmobile_smp_arg
90shmobile_smp_arg:
913: .space CONFIG_NR_CPUS * 4
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index e818f029d8e3..7b938681e756 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -2,7 +2,6 @@
2#define __ARCH_MACH_COMMON_H 2#define __ARCH_MACH_COMMON_H
3 3
4extern void shmobile_earlytimer_init(void); 4extern void shmobile_earlytimer_init(void);
5extern void shmobile_timer_init(void);
6extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz, 5extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
7 unsigned int mult, unsigned int div); 6 unsigned int mult, unsigned int div);
8struct twd_local_timer; 7struct twd_local_timer;
@@ -10,7 +9,16 @@ extern void shmobile_setup_console(void);
10extern void shmobile_boot_vector(void); 9extern void shmobile_boot_vector(void);
11extern unsigned long shmobile_boot_fn; 10extern unsigned long shmobile_boot_fn;
12extern unsigned long shmobile_boot_arg; 11extern unsigned long shmobile_boot_arg;
12extern void shmobile_smp_boot(void);
13extern void shmobile_smp_sleep(void);
14extern void shmobile_smp_hook(unsigned int cpu, unsigned long fn,
15 unsigned long arg);
13extern void shmobile_boot_scu(void); 16extern void shmobile_boot_scu(void);
17extern void shmobile_smp_scu_prepare_cpus(unsigned int max_cpus);
18extern int shmobile_smp_scu_boot_secondary(unsigned int cpu,
19 struct task_struct *idle);
20extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
21extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
14struct clk; 22struct clk;
15extern int shmobile_clk_init(void); 23extern int shmobile_clk_init(void);
16extern void shmobile_handle_irq_intc(struct pt_regs *); 24extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/include/mach/dma.h b/arch/arm/mach-shmobile/include/mach/dma.h
deleted file mode 100644
index 40a8c178f10d..000000000000
--- a/arch/arm/mach-shmobile/include/mach/dma.h
+++ /dev/null
@@ -1 +0,0 @@
1/* empty */
diff --git a/arch/arm/mach-shmobile/include/mach/emev2.h b/arch/arm/mach-shmobile/include/mach/emev2.h
index ac3751705cab..c2eb7568d9be 100644
--- a/arch/arm/mach-shmobile/include/mach/emev2.h
+++ b/arch/arm/mach-shmobile/include/mach/emev2.h
@@ -2,11 +2,9 @@
2#define __ASM_EMEV2_H__ 2#define __ASM_EMEV2_H__
3 3
4extern void emev2_map_io(void); 4extern void emev2_map_io(void);
5extern void emev2_init_irq(void); 5extern void emev2_init_delay(void);
6extern void emev2_add_early_devices(void);
7extern void emev2_add_standard_devices(void); 6extern void emev2_add_standard_devices(void);
8extern void emev2_clock_init(void); 7extern void emev2_clock_init(void);
9extern void emev2_set_boot_vector(unsigned long value);
10 8
11#define EMEV2_GPIO_BASE 200 9#define EMEV2_GPIO_BASE 200
12#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n)) 10#define EMEV2_GPIO_IRQ(n) (EMEV2_GPIO_BASE + (n))
diff --git a/arch/arm/mach-shmobile/include/mach/hardware.h b/arch/arm/mach-shmobile/include/mach/hardware.h
deleted file mode 100644
index 99264a5ce5e4..000000000000
--- a/arch/arm/mach-shmobile/include/mach/hardware.h
+++ /dev/null
@@ -1,4 +0,0 @@
1#ifndef __ASM_MACH_HARDWARE_H
2#define __ASM_MACH_HARDWARE_H
3
4#endif /* __ASM_MACH_HARDWARE_H */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
index f043103e32c9..f3a9b702da56 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a73a4.h
@@ -2,7 +2,9 @@
2#define __ASM_R8A73A4_H__ 2#define __ASM_R8A73A4_H__
3 3
4void r8a73a4_add_standard_devices(void); 4void r8a73a4_add_standard_devices(void);
5void r8a73a4_add_dt_devices(void);
5void r8a73a4_clock_init(void); 6void r8a73a4_clock_init(void);
6void r8a73a4_pinmux_init(void); 7void r8a73a4_pinmux_init(void);
8void r8a73a4_init_delay(void);
7 9
8#endif /* __ASM_R8A73A4_H__ */ 10#endif /* __ASM_R8A73A4_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index b34d19b5ca5c..d07932f872b6 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -42,11 +42,12 @@ enum {
42 SHDMA_SLAVE_FSIB_TX, 42 SHDMA_SLAVE_FSIB_TX,
43 SHDMA_SLAVE_USBHS_TX, 43 SHDMA_SLAVE_USBHS_TX,
44 SHDMA_SLAVE_USBHS_RX, 44 SHDMA_SLAVE_USBHS_RX,
45 SHDMA_SLAVE_MMCIF_TX,
46 SHDMA_SLAVE_MMCIF_RX,
45}; 47};
46 48
47extern void r8a7740_meram_workaround(void); 49extern void r8a7740_meram_workaround(void);
48extern void r8a7740_init_delay(void); 50extern void r8a7740_init_delay(void);
49extern void r8a7740_init_irq(void);
50extern void r8a7740_init_irq_of(void); 51extern void r8a7740_init_irq_of(void);
51extern void r8a7740_map_io(void); 52extern void r8a7740_map_io(void);
52extern void r8a7740_add_early_devices(void); 53extern void r8a7740_add_early_devices(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/include/mach/r8a7778.h
index a7c6d151cdd5..adfcf51b163d 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7778.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7778.h
@@ -18,29 +18,21 @@
18#ifndef __ASM_R8A7778_H__ 18#ifndef __ASM_R8A7778_H__
19#define __ASM_R8A7778_H__ 19#define __ASM_R8A7778_H__
20 20
21#include <linux/mmc/sh_mmcif.h>
22#include <linux/mmc/sh_mobile_sdhi.h>
23#include <linux/sh_eth.h> 21#include <linux/sh_eth.h>
24#include <linux/platform_data/usb-rcar-phy.h>
25#include <linux/platform_data/camera-rcar.h> 22#include <linux/platform_data/camera-rcar.h>
26 23
27extern void r8a7778_add_standard_devices(void); 24extern void r8a7778_add_standard_devices(void);
28extern void r8a7778_add_standard_devices_dt(void); 25extern void r8a7778_add_standard_devices_dt(void);
29extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata); 26extern void r8a7778_add_ether_device(struct sh_eth_plat_data *pdata);
30extern void r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
31extern void r8a7778_add_i2c_device(int id);
32extern void r8a7778_add_hspi_device(int id);
33extern void r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info);
34extern void r8a7778_add_vin_device(int id, 27extern void r8a7778_add_vin_device(int id,
35 struct rcar_vin_platform_data *pdata); 28 struct rcar_vin_platform_data *pdata);
29extern void r8a7778_add_dt_devices(void);
36 30
37extern void r8a7778_init_late(void); 31extern void r8a7778_init_late(void);
38extern void r8a7778_init_delay(void); 32extern void r8a7778_init_delay(void);
39extern void r8a7778_init_irq(void);
40extern void r8a7778_init_irq_dt(void); 33extern void r8a7778_init_irq_dt(void);
41extern void r8a7778_clock_init(void); 34extern void r8a7778_clock_init(void);
42extern void r8a7778_init_irq_extpin(int irlm); 35extern void r8a7778_init_irq_extpin(int irlm);
43extern void r8a7778_pinmux_init(void); 36extern void r8a7778_pinmux_init(void);
44extern void r8a7778_sdhi_init(int id, struct sh_mobile_sdhi_info *info);
45 37
46#endif /* __ASM_R8A7778_H__ */ 38#endif /* __ASM_R8A7778_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index 6d2b6417fe2a..11c740047e14 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,7 +4,6 @@
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6#include <linux/sh_eth.h> 6#include <linux/sh_eth.h>
7#include <linux/platform_data/usb-rcar-phy.h>
8#include <linux/platform_data/camera-rcar.h> 7#include <linux/platform_data/camera-rcar.h>
9 8
10struct platform_device; 9struct platform_device;
@@ -26,7 +25,6 @@ static inline struct r8a7779_pm_ch *to_r8a7779_ch(struct generic_pm_domain *d)
26} 25}
27 26
28extern void r8a7779_init_delay(void); 27extern void r8a7779_init_delay(void);
29extern void r8a7779_init_irq(void);
30extern void r8a7779_init_irq_extpin(int irlm); 28extern void r8a7779_init_irq_extpin(int irlm);
31extern void r8a7779_init_irq_dt(void); 29extern void r8a7779_init_irq_dt(void);
32extern void r8a7779_map_io(void); 30extern void r8a7779_map_io(void);
@@ -35,7 +33,6 @@ extern void r8a7779_add_early_devices(void);
35extern void r8a7779_add_standard_devices(void); 33extern void r8a7779_add_standard_devices(void);
36extern void r8a7779_add_standard_devices_dt(void); 34extern void r8a7779_add_standard_devices_dt(void);
37extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata); 35extern void r8a7779_add_ether_device(struct sh_eth_plat_data *pdata);
38extern void r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata);
39extern void r8a7779_add_vin_device(int idx, 36extern void r8a7779_add_vin_device(int idx,
40 struct rcar_vin_platform_data *pdata); 37 struct rcar_vin_platform_data *pdata);
41extern void r8a7779_init_late(void); 38extern void r8a7779_init_late(void);
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/include/mach/r8a7790.h
index 2e919e61fa0d..788d55952091 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7790.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7790.h
@@ -2,8 +2,13 @@
2#define __ASM_R8A7790_H__ 2#define __ASM_R8A7790_H__
3 3
4void r8a7790_add_standard_devices(void); 4void r8a7790_add_standard_devices(void);
5void r8a7790_add_dt_devices(void);
5void r8a7790_clock_init(void); 6void r8a7790_clock_init(void);
6void r8a7790_pinmux_init(void); 7void r8a7790_pinmux_init(void);
8void r8a7790_init_delay(void);
7void r8a7790_timer_init(void); 9void r8a7790_timer_init(void);
8 10
11#define MD(nr) BIT(nr)
12u32 r8a7790_read_mode_pins(void);
13
9#endif /* __ASM_R8A7790_H__ */ 14#endif /* __ASM_R8A7790_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index eb7a4320d487..359b582dc270 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -1,379 +1,6 @@
1#ifndef __ASM_SH73A0_H__ 1#ifndef __ASM_SH73A0_H__
2#define __ASM_SH73A0_H__ 2#define __ASM_SH73A0_H__
3 3
4/* Pin Function Controller:
5 * GPIO_FN_xx - GPIO used to select pin function and MSEL switch
6 * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU
7 */
8enum {
9 /* Hardware manual Table 25-1 (GPIO) */
10 GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4,
11 GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9,
12
13 GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14,
14 GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19,
15
16 GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24,
17 GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29,
18
19 GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34,
20 GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39,
21
22 GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44,
23 GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49,
24
25 GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54,
26 GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59,
27
28 GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64,
29 GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69,
30
31 GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74,
32 GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79,
33
34 GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84,
35 GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89,
36
37 GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94,
38 GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99,
39
40 GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104,
41 GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109,
42
43 GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114,
44 GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118,
45
46 GPIO_PORT128, GPIO_PORT129,
47
48 GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134,
49 GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139,
50
51 GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144,
52 GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149,
53
54 GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154,
55 GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159,
56
57 GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164,
58
59 GPIO_PORT192, GPIO_PORT193, GPIO_PORT194,
60 GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199,
61
62 GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204,
63 GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209,
64
65 GPIO_PORT210, GPIO_PORT211, GPIO_PORT212, GPIO_PORT213, GPIO_PORT214,
66 GPIO_PORT215, GPIO_PORT216, GPIO_PORT217, GPIO_PORT218, GPIO_PORT219,
67
68 GPIO_PORT220, GPIO_PORT221, GPIO_PORT222, GPIO_PORT223, GPIO_PORT224,
69 GPIO_PORT225, GPIO_PORT226, GPIO_PORT227, GPIO_PORT228, GPIO_PORT229,
70
71 GPIO_PORT230, GPIO_PORT231, GPIO_PORT232, GPIO_PORT233, GPIO_PORT234,
72 GPIO_PORT235, GPIO_PORT236, GPIO_PORT237, GPIO_PORT238, GPIO_PORT239,
73
74 GPIO_PORT240, GPIO_PORT241, GPIO_PORT242, GPIO_PORT243, GPIO_PORT244,
75 GPIO_PORT245, GPIO_PORT246, GPIO_PORT247, GPIO_PORT248, GPIO_PORT249,
76
77 GPIO_PORT250, GPIO_PORT251, GPIO_PORT252, GPIO_PORT253, GPIO_PORT254,
78 GPIO_PORT255, GPIO_PORT256, GPIO_PORT257, GPIO_PORT258, GPIO_PORT259,
79
80 GPIO_PORT260, GPIO_PORT261, GPIO_PORT262, GPIO_PORT263, GPIO_PORT264,
81 GPIO_PORT265, GPIO_PORT266, GPIO_PORT267, GPIO_PORT268, GPIO_PORT269,
82
83 GPIO_PORT270, GPIO_PORT271, GPIO_PORT272, GPIO_PORT273, GPIO_PORT274,
84 GPIO_PORT275, GPIO_PORT276, GPIO_PORT277, GPIO_PORT278, GPIO_PORT279,
85
86 GPIO_PORT280, GPIO_PORT281, GPIO_PORT282,
87
88 GPIO_PORT288, GPIO_PORT289,
89
90 GPIO_PORT290, GPIO_PORT291, GPIO_PORT292, GPIO_PORT293, GPIO_PORT294,
91 GPIO_PORT295, GPIO_PORT296, GPIO_PORT297, GPIO_PORT298, GPIO_PORT299,
92
93 GPIO_PORT300, GPIO_PORT301, GPIO_PORT302, GPIO_PORT303, GPIO_PORT304,
94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
95
96 /* Table 25-1 (Function 0-7) */
97 GPIO_FN_GPI0 = 310,
98 GPIO_FN_GPI1,
99 GPIO_FN_GPI2,
100 GPIO_FN_GPI3,
101 GPIO_FN_GPI4,
102 GPIO_FN_GPI5,
103 GPIO_FN_GPI6,
104 GPIO_FN_GPI7,
105 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
106 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
107 GPIO_FN_GPO5,
108 GPIO_FN_PORT16_VIO_CKOR,
109 GPIO_FN_PORT19_VIO_CKO2,
110 GPIO_FN_GPO0,
111 GPIO_FN_GPO1,
112 GPIO_FN_GPO2, GPIO_FN_STATUS0,
113 GPIO_FN_GPO3, GPIO_FN_STATUS1,
114 GPIO_FN_GPO4, GPIO_FN_STATUS2,
115 GPIO_FN_VINT,
116 GPIO_FN_TCKON,
117 GPIO_FN_XDVFS1,
118 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
119 GPIO_FN_XDVFS2,
120 GPIO_FN_PORT28_TPU1TO1,
121 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
122 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
123 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
124 GPIO_FN_XWUP,
125 GPIO_FN_VACK,
126 GPIO_FN_XTAL1L,
127 GPIO_FN_PORT49_IROUT,
128 GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
129
130 GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
131 GPIO_FN_BBIF2_TXD2,
132 GPIO_FN_TPU3TO3,
133 GPIO_FN_TPU3TO2,
134 GPIO_FN_TPU0TO0,
135 GPIO_FN_A0, GPIO_FN_BS_,
136 GPIO_FN_A12, GPIO_FN_TPU4TO2,
137 GPIO_FN_A13, GPIO_FN_TPU0TO1,
138 GPIO_FN_A14,
139 GPIO_FN_A15,
140 GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
141 GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
142 GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
143 GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
144 GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
145 GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
146 GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
147 GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
148 GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
149 GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
150 GPIO_FN_A26,
151 GPIO_FN_FCE1_,
152 GPIO_FN_DACK0,
153 GPIO_FN_FCE0_,
154 GPIO_FN_WAIT_, GPIO_FN_DREQ0,
155 GPIO_FN_FRB,
156 GPIO_FN_CKO,
157 GPIO_FN_NBRSTOUT_,
158 GPIO_FN_NBRST_,
159 GPIO_FN_BBIF2_TXD,
160 GPIO_FN_BBIF2_RXD,
161 GPIO_FN_BBIF2_SYNC,
162 GPIO_FN_BBIF2_SCK,
163 GPIO_FN_MFG3_IN2,
164 GPIO_FN_MFG3_IN1,
165 GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
166 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
167 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
168 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
169 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
170 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
171 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
172 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
173 GPIO_FN_HSI_TX_FLAG,
174 GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
175
176 GPIO_FN_VIO_HD,
177 GPIO_FN_VIO2_HD,
178 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
179 GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
180 GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
181 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
182 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
183 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
184 GPIO_FN_VIO_D6,
185 GPIO_FN_VIO_D7,
186 GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
187 GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
188 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
189 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
190 GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
191 GPIO_FN_VIO_D13,
192 GPIO_FN_VIO2_D5,
193 GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
194 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
195 GPIO_FN_VIO2_D7,
196 GPIO_FN_VIO_CLK,
197 GPIO_FN_VIO2_CLK,
198 GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
199 GPIO_FN_VIO_CKO,
200 GPIO_FN_A27, GPIO_FN_MFG0_IN1,
201 GPIO_FN_MFG0_IN2,
202 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
203 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
204 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
205 GPIO_FN_MSIOF2_MCK0,
206 GPIO_FN_MSIOF2_MCK1,
207 GPIO_FN_PORT156_MSIOF2_SS2,
208 GPIO_FN_PORT157_MSIOF2_RXD,
209 GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
210 GPIO_FN_NMI,
211 GPIO_FN_TPU3TO0,
212 GPIO_FN_BBIF2_TSYNC1,
213 GPIO_FN_BBIF2_TSCK1,
214 GPIO_FN_BBIF2_TXD1,
215 GPIO_FN_MFG2_OUT2,
216 GPIO_FN_TPU2TO1,
217 GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
218 GPIO_FN_D16,
219 GPIO_FN_D17,
220 GPIO_FN_D18,
221 GPIO_FN_D19,
222 GPIO_FN_D20,
223 GPIO_FN_D21,
224 GPIO_FN_D22,
225 GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
226 GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
227 GPIO_FN_D25,
228 GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
229 GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
230 GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
231 GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
232 GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
233 GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
234 GPIO_FN_DACK2,
235 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
236 GPIO_FN_DACK3,
237 GPIO_FN_PORT218_VIO_CKOR,
238 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
239 GPIO_FN_DREQ1,
240 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
241 GPIO_FN_DACK1, GPIO_FN_OVCN,
242 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
243
244 GPIO_FN_OVCN2,
245 GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
246 GPIO_FN_IDIN,
247 GPIO_FN_MFG1_IN1,
248 GPIO_FN_MSIOF1_TXD,
249 GPIO_FN_MSIOF1_TSYNC,
250 GPIO_FN_MSIOF1_TSCK,
251 GPIO_FN_MSIOF1_RXD,
252 GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
253 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
254 GPIO_FN_MSIOF1_MCK0,
255 GPIO_FN_MSIOF1_MCK1,
256 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
257 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
258 GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
259 GPIO_FN_TPU4TO0,
260 GPIO_FN_MFG4_IN2,
261 GPIO_FN_PORT243_VIO_CKO2,
262 GPIO_FN_MFG2_IN1,
263 GPIO_FN_MSIOF2R_RXD,
264 GPIO_FN_MFG2_IN2,
265 GPIO_FN_MSIOF2R_TXD,
266 GPIO_FN_MFG1_OUT1,
267 GPIO_FN_TPU1TO0,
268 GPIO_FN_MFG3_OUT2,
269 GPIO_FN_TPU3TO1,
270 GPIO_FN_MFG2_OUT1,
271 GPIO_FN_TPU2TO0,
272 GPIO_FN_MSIOF2R_TSCK,
273 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
274 GPIO_FN_MSIOF2R_TSYNC,
275 GPIO_FN_SDHICLK0,
276 GPIO_FN_SDHICD0,
277 GPIO_FN_SDHID0_0,
278 GPIO_FN_SDHID0_1,
279 GPIO_FN_SDHID0_2,
280 GPIO_FN_SDHID0_3,
281 GPIO_FN_SDHICMD0,
282 GPIO_FN_SDHIWP0,
283 GPIO_FN_SDHICLK1,
284 GPIO_FN_SDHID1_0, GPIO_FN_TS_SPSYNC2,
285 GPIO_FN_SDHID1_1, GPIO_FN_TS_SDAT2,
286 GPIO_FN_SDHID1_2, GPIO_FN_TS_SDEN2,
287 GPIO_FN_SDHID1_3, GPIO_FN_TS_SCK2,
288 GPIO_FN_SDHICMD1,
289 GPIO_FN_SDHICLK2,
290 GPIO_FN_SDHID2_0, GPIO_FN_TS_SPSYNC4,
291 GPIO_FN_SDHID2_1, GPIO_FN_TS_SDAT4,
292 GPIO_FN_SDHID2_2, GPIO_FN_TS_SDEN4,
293 GPIO_FN_SDHID2_3, GPIO_FN_TS_SCK4,
294 GPIO_FN_SDHICMD2,
295 GPIO_FN_MMCCLK0,
296 GPIO_FN_MMCD0_0,
297 GPIO_FN_MMCD0_1,
298 GPIO_FN_MMCD0_2,
299 GPIO_FN_MMCD0_3,
300 GPIO_FN_MMCD0_4, GPIO_FN_TS_SPSYNC5,
301 GPIO_FN_MMCD0_5, GPIO_FN_TS_SDAT5,
302 GPIO_FN_MMCD0_6, GPIO_FN_TS_SDEN5,
303 GPIO_FN_MMCD0_7, GPIO_FN_TS_SCK5,
304 GPIO_FN_MMCCMD0,
305 GPIO_FN_RESETOUTS_, GPIO_FN_EXTAL2OUT,
306 GPIO_FN_MCP_WAIT__MCP_FRB,
307 GPIO_FN_MCP_CKO, GPIO_FN_MMCCLK1,
308 GPIO_FN_MCP_D15_MCP_NAF15,
309 GPIO_FN_MCP_D14_MCP_NAF14,
310 GPIO_FN_MCP_D13_MCP_NAF13,
311 GPIO_FN_MCP_D12_MCP_NAF12,
312 GPIO_FN_MCP_D11_MCP_NAF11,
313 GPIO_FN_MCP_D10_MCP_NAF10,
314 GPIO_FN_MCP_D9_MCP_NAF9,
315 GPIO_FN_MCP_D8_MCP_NAF8, GPIO_FN_MMCCMD1,
316 GPIO_FN_MCP_D7_MCP_NAF7, GPIO_FN_MMCD1_7,
317
318 GPIO_FN_MCP_D6_MCP_NAF6, GPIO_FN_MMCD1_6,
319 GPIO_FN_MCP_D5_MCP_NAF5, GPIO_FN_MMCD1_5,
320 GPIO_FN_MCP_D4_MCP_NAF4, GPIO_FN_MMCD1_4,
321 GPIO_FN_MCP_D3_MCP_NAF3, GPIO_FN_MMCD1_3,
322 GPIO_FN_MCP_D2_MCP_NAF2, GPIO_FN_MMCD1_2,
323 GPIO_FN_MCP_D1_MCP_NAF1, GPIO_FN_MMCD1_1,
324 GPIO_FN_MCP_D0_MCP_NAF0, GPIO_FN_MMCD1_0,
325 GPIO_FN_MCP_NBRSTOUT_,
326 GPIO_FN_MCP_WE0__MCP_FWE, GPIO_FN_MCP_RDWR_MCP_FWE,
327
328 /* MSEL2 special case */
329 GPIO_FN_TSIF2_TS_XX1,
330 GPIO_FN_TSIF2_TS_XX2,
331 GPIO_FN_TSIF2_TS_XX3,
332 GPIO_FN_TSIF2_TS_XX4,
333 GPIO_FN_TSIF2_TS_XX5,
334 GPIO_FN_TSIF1_TS_XX1,
335 GPIO_FN_TSIF1_TS_XX2,
336 GPIO_FN_TSIF1_TS_XX3,
337 GPIO_FN_TSIF1_TS_XX4,
338 GPIO_FN_TSIF1_TS_XX5,
339 GPIO_FN_TSIF0_TS_XX1,
340 GPIO_FN_TSIF0_TS_XX2,
341 GPIO_FN_TSIF0_TS_XX3,
342 GPIO_FN_TSIF0_TS_XX4,
343 GPIO_FN_TSIF0_TS_XX5,
344 GPIO_FN_MST1_TS_XX1,
345 GPIO_FN_MST1_TS_XX2,
346 GPIO_FN_MST1_TS_XX3,
347 GPIO_FN_MST1_TS_XX4,
348 GPIO_FN_MST1_TS_XX5,
349 GPIO_FN_MST0_TS_XX1,
350 GPIO_FN_MST0_TS_XX2,
351 GPIO_FN_MST0_TS_XX3,
352 GPIO_FN_MST0_TS_XX4,
353 GPIO_FN_MST0_TS_XX5,
354
355 /* MSEL3 special cases */
356 GPIO_FN_SDHI0_VCCQ_MC0_ON,
357 GPIO_FN_SDHI0_VCCQ_MC0_OFF,
358 GPIO_FN_DEBUG_MON_VIO,
359 GPIO_FN_DEBUG_MON_LCDD,
360 GPIO_FN_LCDC_LCDC0,
361 GPIO_FN_LCDC_LCDC1,
362
363 /* MSEL4 special cases */
364 GPIO_FN_IRQ9_MEM_INT,
365 GPIO_FN_IRQ9_MCP_INT,
366 GPIO_FN_A11,
367 GPIO_FN_TPU4TO3,
368 GPIO_FN_RESETA_N_PU_ON,
369 GPIO_FN_RESETA_N_PU_OFF,
370 GPIO_FN_EDBGREQ_PD,
371 GPIO_FN_EDBGREQ_PU,
372
373 /* end of GPIO */
374 GPIO_NR,
375};
376
377/* DMA slave IDs */ 4/* DMA slave IDs */
378enum { 5enum {
379 SHDMA_SLAVE_INVALID, 6 SHDMA_SLAVE_INVALID,
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index f2d8744c1f14..c3c4669a2d72 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -1,7 +1,6 @@
1#ifndef ZBOOT_H 1#ifndef ZBOOT_H
2#define ZBOOT_H 2#define ZBOOT_H
3 3
4#include <asm/mach-types.h>
5#include <mach/zboot_macros.h> 4#include <mach/zboot_macros.h>
6 5
7/************************************************** 6/**************************************************
@@ -11,7 +10,6 @@
11 **************************************************/ 10 **************************************************/
12 11
13#ifdef CONFIG_MACH_MACKEREL 12#ifdef CONFIG_MACH_MACKEREL
14#define MACH_TYPE MACH_TYPE_MACKEREL
15#define MEMORY_START 0x40000000 13#define MEMORY_START 0x40000000
16#include "mach/head-mackerel.txt" 14#include "mach/head-mackerel.txt"
17#else 15#else
diff --git a/arch/arm/mach-shmobile/intc-r8a7740.c b/arch/arm/mach-shmobile/intc-r8a7740.c
deleted file mode 100644
index 8871f7717dc8..000000000000
--- a/arch/arm/mach-shmobile/intc-r8a7740.c
+++ /dev/null
@@ -1,68 +0,0 @@
1/*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/irqchip.h>
24#include <linux/irqchip/arm-gic.h>
25
26static void __init r8a7740_init_irq_common(void)
27{
28 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
29 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
30 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
31
32 /* route signals to GIC */
33 iowrite32(0x0, pfc_inta_ctrl);
34
35 /*
36 * To mask the shared interrupt to SPI 149 we must ensure to set
37 * PRIO *and* MASK. Else we run into IRQ floods when registering
38 * the intc_irqpin devices
39 */
40 iowrite32(0x0, intc_prio_base + 0x0);
41 iowrite32(0x0, intc_prio_base + 0x4);
42 iowrite32(0x0, intc_prio_base + 0x8);
43 iowrite32(0x0, intc_prio_base + 0xc);
44 iowrite8(0xff, intc_msk_base + 0x0);
45 iowrite8(0xff, intc_msk_base + 0x4);
46 iowrite8(0xff, intc_msk_base + 0x8);
47 iowrite8(0xff, intc_msk_base + 0xc);
48
49 iounmap(intc_prio_base);
50 iounmap(intc_msk_base);
51 iounmap(pfc_inta_ctrl);
52}
53
54void __init r8a7740_init_irq_of(void)
55{
56 irqchip_init();
57 r8a7740_init_irq_common();
58}
59
60void __init r8a7740_init_irq(void)
61{
62 void __iomem *gic_dist_base = ioremap_nocache(0xc2800000, 0x1000);
63 void __iomem *gic_cpu_base = ioremap_nocache(0xc2000000, 0x1000);
64
65 /* initialize the Generic Interrupt Controller PL390 r0p0 */
66 gic_init(0, 29, gic_dist_base, gic_cpu_base);
67 r8a7740_init_irq_common();
68}
diff --git a/arch/arm/mach-shmobile/intc-r8a7779.c b/arch/arm/mach-shmobile/intc-r8a7779.c
deleted file mode 100644
index b86dc8908724..000000000000
--- a/arch/arm/mach-shmobile/intc-r8a7779.c
+++ /dev/null
@@ -1,131 +0,0 @@
1/*
2 * r8a7779 processor support - INTC hardware block
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/kernel.h>
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/irqchip/arm-gic.h>
27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
28#include <linux/irqchip.h>
29#include <mach/common.h>
30#include <mach/intc.h>
31#include <mach/irqs.h>
32#include <mach/r8a7779.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35
36#define INT2SMSKCR0 IOMEM(0xfe7822a0)
37#define INT2SMSKCR1 IOMEM(0xfe7822a4)
38#define INT2SMSKCR2 IOMEM(0xfe7822a8)
39#define INT2SMSKCR3 IOMEM(0xfe7822ac)
40#define INT2SMSKCR4 IOMEM(0xfe7822b0)
41
42#define INT2NTSR0 IOMEM(0xfe700060)
43#define INT2NTSR1 IOMEM(0xfe700064)
44
45static struct renesas_intc_irqpin_config irqpin0_platform_data = {
46 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
47 .sense_bitfield_width = 2,
48};
49
50static struct resource irqpin0_resources[] = {
51 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
52 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
53 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
54 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
55 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
56 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
57 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
58 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
59 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
60};
61
62static struct platform_device irqpin0_device = {
63 .name = "renesas_intc_irqpin",
64 .id = 0,
65 .resource = irqpin0_resources,
66 .num_resources = ARRAY_SIZE(irqpin0_resources),
67 .dev = {
68 .platform_data = &irqpin0_platform_data,
69 },
70};
71
72void __init r8a7779_init_irq_extpin(int irlm)
73{
74 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
75 unsigned long tmp;
76
77 if (icr0) {
78 tmp = ioread32(icr0);
79 if (irlm)
80 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
81 else
82 tmp &= ~(1 << 23); /* IRL mode - not supported */
83 tmp |= (1 << 21); /* LVLMODE = 1 */
84 iowrite32(tmp, icr0);
85 iounmap(icr0);
86
87 if (irlm)
88 platform_device_register(&irqpin0_device);
89 } else
90 pr_warn("r8a7779: unable to setup external irq pin mode\n");
91}
92
93static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
94{
95 return 0; /* always allow wakeup */
96}
97
98static void __init r8a7779_init_irq_common(void)
99{
100 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
101
102 /* route all interrupts to ARM */
103 __raw_writel(0xffffffff, INT2NTSR0);
104 __raw_writel(0x3fffffff, INT2NTSR1);
105
106 /* unmask all known interrupts in INTCS2 */
107 __raw_writel(0xfffffff0, INT2SMSKCR0);
108 __raw_writel(0xfff7ffff, INT2SMSKCR1);
109 __raw_writel(0xfffbffdf, INT2SMSKCR2);
110 __raw_writel(0xbffffffc, INT2SMSKCR3);
111 __raw_writel(0x003fee3f, INT2SMSKCR4);
112}
113
114void __init r8a7779_init_irq(void)
115{
116 void __iomem *gic_dist_base = IOMEM(0xf0001000);
117 void __iomem *gic_cpu_base = IOMEM(0xf0000100);
118
119 /* use GIC to handle interrupts */
120 gic_init(0, 29, gic_dist_base, gic_cpu_base);
121
122 r8a7779_init_irq_common();
123}
124
125#ifdef CONFIG_OF
126void __init r8a7779_init_irq_dt(void)
127{
128 irqchip_init();
129 r8a7779_init_irq_common();
130}
131#endif
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c
new file mode 100644
index 000000000000..c96f50160be6
--- /dev/null
+++ b/arch/arm/mach-shmobile/platsmp-scu.c
@@ -0,0 +1,81 @@
1/*
2 * SMP support for SoCs with SCU covered by mach-shmobile
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/smp.h>
14#include <asm/cacheflush.h>
15#include <asm/smp_plat.h>
16#include <asm/smp_scu.h>
17#include <mach/common.h>
18
19void __init shmobile_smp_scu_prepare_cpus(unsigned int max_cpus)
20{
21 /* install boot code shared by all CPUs */
22 shmobile_boot_fn = virt_to_phys(shmobile_smp_boot);
23 shmobile_boot_arg = MPIDR_HWID_BITMASK;
24
25 /* enable SCU and cache coherency on booting CPU */
26 scu_enable(shmobile_scu_base);
27 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
28}
29
30int shmobile_smp_scu_boot_secondary(unsigned int cpu, struct task_struct *idle)
31{
32 /* For this particular CPU register SCU boot vector */
33 shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu),
34 (unsigned long)shmobile_scu_base);
35 return 0;
36}
37
38#ifdef CONFIG_HOTPLUG_CPU
39void shmobile_smp_scu_cpu_die(unsigned int cpu)
40{
41 /* For this particular CPU deregister boot vector */
42 shmobile_smp_hook(cpu, 0, 0);
43
44 dsb();
45 flush_cache_all();
46
47 /* disable cache coherency */
48 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
49
50 /* jump to shared mach-shmobile sleep / reset code */
51 shmobile_smp_sleep();
52}
53
54static int shmobile_smp_scu_psr_core_disabled(int cpu)
55{
56 unsigned long mask = SCU_PM_POWEROFF << (cpu * 8);
57
58 if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
59 return 1;
60
61 return 0;
62}
63
64int shmobile_smp_scu_cpu_kill(unsigned int cpu)
65{
66 int k;
67
68 /* this function is running on another CPU than the offline target,
69 * here we need wait for shutdown code in platform_cpu_die() to
70 * finish before asking SoC-specific code to power off the CPU core.
71 */
72 for (k = 0; k < 1000; k++) {
73 if (shmobile_smp_scu_psr_core_disabled(cpu))
74 return 1;
75
76 mdelay(1);
77 }
78
79 return 0;
80}
81#endif
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 1f958d7b0bac..d4ae616bcedb 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -12,6 +12,9 @@
12 */ 12 */
13#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/smp.h> 14#include <linux/smp.h>
15#include <asm/cacheflush.h>
16#include <asm/smp_plat.h>
17#include <mach/common.h>
15 18
16void __init shmobile_smp_init_cpus(unsigned int ncores) 19void __init shmobile_smp_init_cpus(unsigned int ncores)
17{ 20{
@@ -26,3 +29,18 @@ void __init shmobile_smp_init_cpus(unsigned int ncores)
26 for (i = 0; i < ncores; i++) 29 for (i = 0; i < ncores; i++)
27 set_cpu_possible(i, true); 30 set_cpu_possible(i, true);
28} 31}
32
33extern unsigned long shmobile_smp_fn[];
34extern unsigned long shmobile_smp_arg[];
35extern unsigned long shmobile_smp_mpidr[];
36
37void shmobile_smp_hook(unsigned int cpu, unsigned long fn, unsigned long arg)
38{
39 shmobile_smp_fn[cpu] = 0;
40 flush_cache_all();
41
42 shmobile_smp_mpidr[cpu] = cpu_logical_map(cpu);
43 shmobile_smp_fn[cpu] = fn;
44 shmobile_smp_arg[cpu] = arg;
45 flush_cache_all();
46}
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index 1ccddd228112..3ad531caf4f0 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -20,7 +20,6 @@
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/interrupt.h> 21#include <linux/interrupt.h>
22#include <linux/irq.h> 22#include <linux/irq.h>
23#include <linux/irqchip.h>
24#include <linux/platform_device.h> 23#include <linux/platform_device.h>
25#include <linux/platform_data/gpio-em.h> 24#include <linux/platform_data/gpio-em.h>
26#include <linux/of_platform.h> 25#include <linux/of_platform.h>
@@ -28,7 +27,6 @@
28#include <linux/input.h> 27#include <linux/input.h>
29#include <linux/io.h> 28#include <linux/io.h>
30#include <linux/irqchip/arm-gic.h> 29#include <linux/irqchip/arm-gic.h>
31#include <mach/hardware.h>
32#include <mach/common.h> 30#include <mach/common.h>
33#include <mach/emev2.h> 31#include <mach/emev2.h>
34#include <mach/irqs.h> 32#include <mach/irqs.h>
@@ -39,13 +37,6 @@
39 37
40static struct map_desc emev2_io_desc[] __initdata = { 38static struct map_desc emev2_io_desc[] __initdata = {
41#ifdef CONFIG_SMP 39#ifdef CONFIG_SMP
42 /* 128K entity map for 0xe0100000 (SMU) */
43 {
44 .virtual = 0xe0100000,
45 .pfn = __phys_to_pfn(0xe0100000),
46 .length = SZ_128K,
47 .type = MT_DEVICE
48 },
49 /* 2M mapping for SCU + L2 controller */ 40 /* 2M mapping for SCU + L2 controller */
50 { 41 {
51 .virtual = 0xf0000000, 42 .virtual = 0xf0000000,
@@ -63,102 +54,40 @@ void __init emev2_map_io(void)
63 54
64/* UART */ 55/* UART */
65static struct resource uart0_resources[] = { 56static struct resource uart0_resources[] = {
66 [0] = { 57 DEFINE_RES_MEM(0xe1020000, 0x38),
67 .start = 0xe1020000, 58 DEFINE_RES_IRQ(40),
68 .end = 0xe1020037,
69 .flags = IORESOURCE_MEM,
70 },
71 [1] = {
72 .start = 40,
73 .flags = IORESOURCE_IRQ,
74 }
75};
76
77static struct platform_device uart0_device = {
78 .name = "serial8250-em",
79 .id = 0,
80 .num_resources = ARRAY_SIZE(uart0_resources),
81 .resource = uart0_resources,
82}; 59};
83 60
84static struct resource uart1_resources[] = { 61static struct resource uart1_resources[] = {
85 [0] = { 62 DEFINE_RES_MEM(0xe1030000, 0x38),
86 .start = 0xe1030000, 63 DEFINE_RES_IRQ(41),
87 .end = 0xe1030037,
88 .flags = IORESOURCE_MEM,
89 },
90 [1] = {
91 .start = 41,
92 .flags = IORESOURCE_IRQ,
93 }
94};
95
96static struct platform_device uart1_device = {
97 .name = "serial8250-em",
98 .id = 1,
99 .num_resources = ARRAY_SIZE(uart1_resources),
100 .resource = uart1_resources,
101}; 64};
102 65
103static struct resource uart2_resources[] = { 66static struct resource uart2_resources[] = {
104 [0] = { 67 DEFINE_RES_MEM(0xe1040000, 0x38),
105 .start = 0xe1040000, 68 DEFINE_RES_IRQ(42),
106 .end = 0xe1040037,
107 .flags = IORESOURCE_MEM,
108 },
109 [1] = {
110 .start = 42,
111 .flags = IORESOURCE_IRQ,
112 }
113};
114
115static struct platform_device uart2_device = {
116 .name = "serial8250-em",
117 .id = 2,
118 .num_resources = ARRAY_SIZE(uart2_resources),
119 .resource = uart2_resources,
120}; 69};
121 70
122static struct resource uart3_resources[] = { 71static struct resource uart3_resources[] = {
123 [0] = { 72 DEFINE_RES_MEM(0xe1050000, 0x38),
124 .start = 0xe1050000, 73 DEFINE_RES_IRQ(43),
125 .end = 0xe1050037,
126 .flags = IORESOURCE_MEM,
127 },
128 [1] = {
129 .start = 43,
130 .flags = IORESOURCE_IRQ,
131 }
132}; 74};
133 75
134static struct platform_device uart3_device = { 76#define emev2_register_uart(idx) \
135 .name = "serial8250-em", 77 platform_device_register_simple("serial8250-em", idx, \
136 .id = 3, 78 uart##idx##_resources, \
137 .num_resources = ARRAY_SIZE(uart3_resources), 79 ARRAY_SIZE(uart##idx##_resources))
138 .resource = uart3_resources,
139};
140 80
141/* STI */ 81/* STI */
142static struct resource sti_resources[] = { 82static struct resource sti_resources[] = {
143 [0] = { 83 DEFINE_RES_MEM(0xe0180000, 0x54),
144 .name = "STI", 84 DEFINE_RES_IRQ(157),
145 .start = 0xe0180000,
146 .end = 0xe0180053,
147 .flags = IORESOURCE_MEM,
148 },
149 [1] = {
150 .start = 157,
151 .flags = IORESOURCE_IRQ,
152 },
153};
154
155static struct platform_device sti_device = {
156 .name = "em_sti",
157 .id = 0,
158 .resource = sti_resources,
159 .num_resources = ARRAY_SIZE(sti_resources),
160}; 85};
161 86
87#define emev2_register_sti() \
88 platform_device_register_simple("em_sti", 0, \
89 sti_resources, \
90 ARRAY_SIZE(sti_resources))
162 91
163/* GIO */ 92/* GIO */
164static struct gpio_em_config gio0_config = { 93static struct gpio_em_config gio0_config = {
@@ -168,36 +97,10 @@ static struct gpio_em_config gio0_config = {
168}; 97};
169 98
170static struct resource gio0_resources[] = { 99static struct resource gio0_resources[] = {
171 [0] = { 100 DEFINE_RES_MEM(0xe0050000, 0x2c),
172 .name = "GIO_000", 101 DEFINE_RES_MEM(0xe0050040, 0x20),
173 .start = 0xe0050000, 102 DEFINE_RES_IRQ(99),
174 .end = 0xe005002b, 103 DEFINE_RES_IRQ(100),
175 .flags = IORESOURCE_MEM,
176 },
177 [1] = {
178 .name = "GIO_000",
179 .start = 0xe0050040,
180 .end = 0xe005005f,
181 .flags = IORESOURCE_MEM,
182 },
183 [2] = {
184 .start = 99,
185 .flags = IORESOURCE_IRQ,
186 },
187 [3] = {
188 .start = 100,
189 .flags = IORESOURCE_IRQ,
190 },
191};
192
193static struct platform_device gio0_device = {
194 .name = "em_gio",
195 .id = 0,
196 .resource = gio0_resources,
197 .num_resources = ARRAY_SIZE(gio0_resources),
198 .dev = {
199 .platform_data = &gio0_config,
200 },
201}; 104};
202 105
203static struct gpio_em_config gio1_config = { 106static struct gpio_em_config gio1_config = {
@@ -207,36 +110,10 @@ static struct gpio_em_config gio1_config = {
207}; 110};
208 111
209static struct resource gio1_resources[] = { 112static struct resource gio1_resources[] = {
210 [0] = { 113 DEFINE_RES_MEM(0xe0050080, 0x2c),
211 .name = "GIO_032", 114 DEFINE_RES_MEM(0xe00500c0, 0x20),
212 .start = 0xe0050080, 115 DEFINE_RES_IRQ(101),
213 .end = 0xe00500ab, 116 DEFINE_RES_IRQ(102),
214 .flags = IORESOURCE_MEM,
215 },
216 [1] = {
217 .name = "GIO_032",
218 .start = 0xe00500c0,
219 .end = 0xe00500df,
220 .flags = IORESOURCE_MEM,
221 },
222 [2] = {
223 .start = 101,
224 .flags = IORESOURCE_IRQ,
225 },
226 [3] = {
227 .start = 102,
228 .flags = IORESOURCE_IRQ,
229 },
230};
231
232static struct platform_device gio1_device = {
233 .name = "em_gio",
234 .id = 1,
235 .resource = gio1_resources,
236 .num_resources = ARRAY_SIZE(gio1_resources),
237 .dev = {
238 .platform_data = &gio1_config,
239 },
240}; 117};
241 118
242static struct gpio_em_config gio2_config = { 119static struct gpio_em_config gio2_config = {
@@ -246,36 +123,10 @@ static struct gpio_em_config gio2_config = {
246}; 123};
247 124
248static struct resource gio2_resources[] = { 125static struct resource gio2_resources[] = {
249 [0] = { 126 DEFINE_RES_MEM(0xe0050100, 0x2c),
250 .name = "GIO_064", 127 DEFINE_RES_MEM(0xe0050140, 0x20),
251 .start = 0xe0050100, 128 DEFINE_RES_IRQ(103),
252 .end = 0xe005012b, 129 DEFINE_RES_IRQ(104),
253 .flags = IORESOURCE_MEM,
254 },
255 [1] = {
256 .name = "GIO_064",
257 .start = 0xe0050140,
258 .end = 0xe005015f,
259 .flags = IORESOURCE_MEM,
260 },
261 [2] = {
262 .start = 103,
263 .flags = IORESOURCE_IRQ,
264 },
265 [3] = {
266 .start = 104,
267 .flags = IORESOURCE_IRQ,
268 },
269};
270
271static struct platform_device gio2_device = {
272 .name = "em_gio",
273 .id = 2,
274 .resource = gio2_resources,
275 .num_resources = ARRAY_SIZE(gio2_resources),
276 .dev = {
277 .platform_data = &gio2_config,
278 },
279}; 130};
280 131
281static struct gpio_em_config gio3_config = { 132static struct gpio_em_config gio3_config = {
@@ -285,36 +136,10 @@ static struct gpio_em_config gio3_config = {
285}; 136};
286 137
287static struct resource gio3_resources[] = { 138static struct resource gio3_resources[] = {
288 [0] = { 139 DEFINE_RES_MEM(0xe0050180, 0x2c),
289 .name = "GIO_096", 140 DEFINE_RES_MEM(0xe00501c0, 0x20),
290 .start = 0xe0050180, 141 DEFINE_RES_IRQ(105),
291 .end = 0xe00501ab, 142 DEFINE_RES_IRQ(106),
292 .flags = IORESOURCE_MEM,
293 },
294 [1] = {
295 .name = "GIO_096",
296 .start = 0xe00501c0,
297 .end = 0xe00501df,
298 .flags = IORESOURCE_MEM,
299 },
300 [2] = {
301 .start = 105,
302 .flags = IORESOURCE_IRQ,
303 },
304 [3] = {
305 .start = 106,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device gio3_device = {
311 .name = "em_gio",
312 .id = 3,
313 .resource = gio3_resources,
314 .num_resources = ARRAY_SIZE(gio3_resources),
315 .dev = {
316 .platform_data = &gio3_config,
317 },
318}; 143};
319 144
320static struct gpio_em_config gio4_config = { 145static struct gpio_em_config gio4_config = {
@@ -324,126 +149,53 @@ static struct gpio_em_config gio4_config = {
324}; 149};
325 150
326static struct resource gio4_resources[] = { 151static struct resource gio4_resources[] = {
327 [0] = { 152 DEFINE_RES_MEM(0xe0050200, 0x2c),
328 .name = "GIO_128", 153 DEFINE_RES_MEM(0xe0050240, 0x20),
329 .start = 0xe0050200, 154 DEFINE_RES_IRQ(107),
330 .end = 0xe005022b, 155 DEFINE_RES_IRQ(108),
331 .flags = IORESOURCE_MEM,
332 },
333 [1] = {
334 .name = "GIO_128",
335 .start = 0xe0050240,
336 .end = 0xe005025f,
337 .flags = IORESOURCE_MEM,
338 },
339 [2] = {
340 .start = 107,
341 .flags = IORESOURCE_IRQ,
342 },
343 [3] = {
344 .start = 108,
345 .flags = IORESOURCE_IRQ,
346 },
347}; 156};
348 157
349static struct platform_device gio4_device = { 158#define emev2_register_gio(idx) \
350 .name = "em_gio", 159 platform_device_register_resndata(&platform_bus, "em_gio", \
351 .id = 4, 160 idx, gio##idx##_resources, \
352 .resource = gio4_resources, 161 ARRAY_SIZE(gio##idx##_resources), \
353 .num_resources = ARRAY_SIZE(gio4_resources), 162 &gio##idx##_config, \
354 .dev = { 163 sizeof(struct gpio_em_config))
355 .platform_data = &gio4_config,
356 },
357};
358 164
359static struct resource pmu_resources[] = { 165static struct resource pmu_resources[] = {
360 [0] = { 166 DEFINE_RES_IRQ(152),
361 .start = 152, 167 DEFINE_RES_IRQ(153),
362 .end = 152,
363 .flags = IORESOURCE_IRQ,
364 },
365 [1] = {
366 .start = 153,
367 .end = 153,
368 .flags = IORESOURCE_IRQ,
369 },
370};
371
372static struct platform_device pmu_device = {
373 .name = "arm-pmu",
374 .id = -1,
375 .num_resources = ARRAY_SIZE(pmu_resources),
376 .resource = pmu_resources,
377}; 168};
378 169
379static struct platform_device *emev2_early_devices[] __initdata = { 170#define emev2_register_pmu() \
380 &uart0_device, 171 platform_device_register_simple("arm-pmu", -1, \
381 &uart1_device, 172 pmu_resources, \
382 &uart2_device, 173 ARRAY_SIZE(pmu_resources))
383 &uart3_device,
384};
385
386static struct platform_device *emev2_late_devices[] __initdata = {
387 &sti_device,
388 &gio0_device,
389 &gio1_device,
390 &gio2_device,
391 &gio3_device,
392 &gio4_device,
393 &pmu_device,
394};
395 174
396void __init emev2_add_standard_devices(void) 175void __init emev2_add_standard_devices(void)
397{ 176{
398 emev2_clock_init(); 177 if (!IS_ENABLED(CONFIG_COMMON_CLK))
399 178 emev2_clock_init();
400 platform_add_devices(emev2_early_devices, 179
401 ARRAY_SIZE(emev2_early_devices)); 180 emev2_register_uart(0);
402 181 emev2_register_uart(1);
403 platform_add_devices(emev2_late_devices, 182 emev2_register_uart(2);
404 ARRAY_SIZE(emev2_late_devices)); 183 emev2_register_uart(3);
184 emev2_register_sti();
185 emev2_register_gio(0);
186 emev2_register_gio(1);
187 emev2_register_gio(2);
188 emev2_register_gio(3);
189 emev2_register_gio(4);
190 emev2_register_pmu();
405} 191}
406 192
407static void __init emev2_init_delay(void) 193void __init emev2_init_delay(void)
408{ 194{
409 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ 195 shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
410} 196}
411 197
412void __init emev2_add_early_devices(void)
413{
414 emev2_init_delay();
415
416 early_platform_add_devices(emev2_early_devices,
417 ARRAY_SIZE(emev2_early_devices));
418
419 /* setup early console here as well */
420 shmobile_setup_console();
421}
422
423void __init emev2_init_irq(void)
424{
425 void __iomem *gic_dist_base;
426 void __iomem *gic_cpu_base;
427
428 /* Static mappings, never released */
429 gic_dist_base = ioremap(0xe0028000, PAGE_SIZE);
430 gic_cpu_base = ioremap(0xe0020000, PAGE_SIZE);
431 BUG_ON(!gic_dist_base || !gic_cpu_base);
432
433 /* Use GIC to handle interrupts */
434 gic_init(0, 29, gic_dist_base, gic_cpu_base);
435}
436
437#ifdef CONFIG_USE_OF 198#ifdef CONFIG_USE_OF
438static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
439 { }
440};
441
442static void __init emev2_add_standard_devices_dt(void)
443{
444 of_platform_populate(NULL, of_default_bus_match_table,
445 emev2_auxdata_lookup, NULL);
446}
447 199
448static const char *emev2_boards_compat_dt[] __initdata = { 200static const char *emev2_boards_compat_dt[] __initdata = {
449 "renesas,emev2", 201 "renesas,emev2",
@@ -452,10 +204,8 @@ static const char *emev2_boards_compat_dt[] __initdata = {
452 204
453DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") 205DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)")
454 .smp = smp_ops(emev2_smp_ops), 206 .smp = smp_ops(emev2_smp_ops),
207 .map_io = emev2_map_io,
455 .init_early = emev2_init_delay, 208 .init_early = emev2_init_delay,
456 .nr_irqs = NR_IRQS_LEGACY,
457 .init_irq = irqchip_init,
458 .init_machine = emev2_add_standard_devices_dt,
459 .dt_compat = emev2_boards_compat_dt, 209 .dt_compat = emev2_boards_compat_dt,
460MACHINE_END 210MACHINE_END
461 211
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index 7f45c2edbca9..89491700afb7 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -18,11 +18,11 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20#include <linux/irq.h> 20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/kernel.h> 21#include <linux/kernel.h>
23#include <linux/of_platform.h> 22#include <linux/of_platform.h>
24#include <linux/platform_data/irq-renesas-irqc.h> 23#include <linux/platform_data/irq-renesas-irqc.h>
25#include <linux/serial_sci.h> 24#include <linux/serial_sci.h>
25#include <linux/sh_timer.h>
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/irqs.h> 27#include <mach/irqs.h>
28#include <mach/r8a73a4.h> 28#include <mach/r8a73a4.h>
@@ -169,7 +169,26 @@ static const struct resource thermal0_resources[] = {
169 thermal0_resources, \ 169 thermal0_resources, \
170 ARRAY_SIZE(thermal0_resources)) 170 ARRAY_SIZE(thermal0_resources))
171 171
172void __init r8a73a4_add_standard_devices(void) 172static struct sh_timer_config cmt10_platform_data = {
173 .name = "CMT10",
174 .timer_bit = 0,
175 .clockevent_rating = 80,
176};
177
178static struct resource cmt10_resources[] = {
179 DEFINE_RES_MEM(0xe6130010, 0x0c),
180 DEFINE_RES_MEM(0xe6130000, 0x04),
181 DEFINE_RES_IRQ(gic_spi(120)), /* CMT1_0 */
182};
183
184#define r8a7790_register_cmt(idx) \
185 platform_device_register_resndata(&platform_bus, "sh_cmt", \
186 idx, cmt##idx##_resources, \
187 ARRAY_SIZE(cmt##idx##_resources), \
188 &cmt##idx##_platform_data, \
189 sizeof(struct sh_timer_config))
190
191void __init r8a73a4_add_dt_devices(void)
173{ 192{
174 r8a73a4_register_scif(SCIFA0); 193 r8a73a4_register_scif(SCIFA0);
175 r8a73a4_register_scif(SCIFA1); 194 r8a73a4_register_scif(SCIFA1);
@@ -177,26 +196,33 @@ void __init r8a73a4_add_standard_devices(void)
177 r8a73a4_register_scif(SCIFB1); 196 r8a73a4_register_scif(SCIFB1);
178 r8a73a4_register_scif(SCIFB2); 197 r8a73a4_register_scif(SCIFB2);
179 r8a73a4_register_scif(SCIFB3); 198 r8a73a4_register_scif(SCIFB3);
199 r8a7790_register_cmt(10);
200}
201
202void __init r8a73a4_add_standard_devices(void)
203{
204 r8a73a4_add_dt_devices();
180 r8a73a4_register_irqc(0); 205 r8a73a4_register_irqc(0);
181 r8a73a4_register_irqc(1); 206 r8a73a4_register_irqc(1);
182 r8a73a4_register_thermal(); 207 r8a73a4_register_thermal();
183} 208}
184 209
185#ifdef CONFIG_USE_OF 210void __init r8a73a4_init_delay(void)
186void __init r8a73a4_add_standard_devices_dt(void)
187{ 211{
188 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 212#ifndef CONFIG_ARM_ARCH_TIMER
213 shmobile_setup_delay(1500, 2, 4); /* Cortex-A15 @ 1500MHz */
214#endif
189} 215}
190 216
217#ifdef CONFIG_USE_OF
218
191static const char *r8a73a4_boards_compat_dt[] __initdata = { 219static const char *r8a73a4_boards_compat_dt[] __initdata = {
192 "renesas,r8a73a4", 220 "renesas,r8a73a4",
193 NULL, 221 NULL,
194}; 222};
195 223
196DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)") 224DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
197 .init_irq = irqchip_init, 225 .init_early = r8a73a4_init_delay,
198 .init_machine = r8a73a4_add_standard_devices_dt,
199 .init_time = shmobile_timer_init,
200 .dt_compat = r8a73a4_boards_compat_dt, 226 .dt_compat = r8a73a4_boards_compat_dt,
201MACHINE_END 227MACHINE_END
202#endif /* CONFIG_USE_OF */ 228#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 00c5a707238b..b7d4b2c3bc29 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -22,6 +22,8 @@
22#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/io.h> 24#include <linux/io.h>
25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
25#include <linux/platform_data/irq-renesas-intc-irqpin.h> 27#include <linux/platform_data/irq-renesas-intc-irqpin.h>
26#include <linux/platform_device.h> 28#include <linux/platform_device.h>
27#include <linux/of_platform.h> 29#include <linux/of_platform.h>
@@ -588,6 +590,16 @@ static const struct sh_dmae_slave_config r8a7740_dmae_slaves[] = {
588 .addr = 0xfe1f0064, 590 .addr = 0xfe1f0064,
589 .chcr = CHCR_TX(XMIT_SZ_32BIT), 591 .chcr = CHCR_TX(XMIT_SZ_32BIT),
590 .mid_rid = 0xb5, 592 .mid_rid = 0xb5,
593 }, {
594 .slave_id = SHDMA_SLAVE_MMCIF_TX,
595 .addr = 0xe6bd0034,
596 .chcr = CHCR_TX(XMIT_SZ_32BIT),
597 .mid_rid = 0xd1,
598 }, {
599 .slave_id = SHDMA_SLAVE_MMCIF_RX,
600 .addr = 0xe6bd0034,
601 .chcr = CHCR_RX(XMIT_SZ_32BIT),
602 .mid_rid = 0xd2,
591 }, 603 },
592}; 604};
593 605
@@ -986,16 +998,22 @@ void __init r8a7740_add_early_devices(void)
986 998
987#ifdef CONFIG_USE_OF 999#ifdef CONFIG_USE_OF
988 1000
989static const struct of_dev_auxdata r8a7740_auxdata_lookup[] __initconst = { 1001void __init r8a7740_add_early_devices_dt(void)
990 { } 1002{
991}; 1003 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1004
1005 early_platform_add_devices(r8a7740_early_devices,
1006 ARRAY_SIZE(r8a7740_early_devices));
1007
1008 /* setup early console here as well */
1009 shmobile_setup_console();
1010}
992 1011
993void __init r8a7740_add_standard_devices_dt(void) 1012void __init r8a7740_add_standard_devices_dt(void)
994{ 1013{
995 platform_add_devices(r8a7740_devices_dt, 1014 platform_add_devices(r8a7740_devices_dt,
996 ARRAY_SIZE(r8a7740_devices_dt)); 1015 ARRAY_SIZE(r8a7740_devices_dt));
997 of_platform_populate(NULL, of_default_bus_match_table, 1016 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
998 r8a7740_auxdata_lookup, NULL);
999} 1017}
1000 1018
1001void __init r8a7740_init_delay(void) 1019void __init r8a7740_init_delay(void)
@@ -1003,6 +1021,36 @@ void __init r8a7740_init_delay(void)
1003 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */ 1021 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
1004}; 1022};
1005 1023
1024void __init r8a7740_init_irq_of(void)
1025{
1026 void __iomem *intc_prio_base = ioremap_nocache(0xe6900010, 0x10);
1027 void __iomem *intc_msk_base = ioremap_nocache(0xe6900040, 0x10);
1028 void __iomem *pfc_inta_ctrl = ioremap_nocache(0xe605807c, 0x4);
1029
1030 irqchip_init();
1031
1032 /* route signals to GIC */
1033 iowrite32(0x0, pfc_inta_ctrl);
1034
1035 /*
1036 * To mask the shared interrupt to SPI 149 we must ensure to set
1037 * PRIO *and* MASK. Else we run into IRQ floods when registering
1038 * the intc_irqpin devices
1039 */
1040 iowrite32(0x0, intc_prio_base + 0x0);
1041 iowrite32(0x0, intc_prio_base + 0x4);
1042 iowrite32(0x0, intc_prio_base + 0x8);
1043 iowrite32(0x0, intc_prio_base + 0xc);
1044 iowrite8(0xff, intc_msk_base + 0x0);
1045 iowrite8(0xff, intc_msk_base + 0x4);
1046 iowrite8(0xff, intc_msk_base + 0x8);
1047 iowrite8(0xff, intc_msk_base + 0xc);
1048
1049 iounmap(intc_prio_base);
1050 iounmap(intc_msk_base);
1051 iounmap(pfc_inta_ctrl);
1052}
1053
1006static void __init r8a7740_generic_init(void) 1054static void __init r8a7740_generic_init(void)
1007{ 1055{
1008 r8a7740_clock_init(0); 1056 r8a7740_clock_init(0);
@@ -1019,7 +1067,6 @@ DT_MACHINE_START(R8A7740_DT, "Generic R8A7740 (Flattened Device Tree)")
1019 .init_early = r8a7740_init_delay, 1067 .init_early = r8a7740_init_delay,
1020 .init_irq = r8a7740_init_irq_of, 1068 .init_irq = r8a7740_init_irq_of,
1021 .init_machine = r8a7740_generic_init, 1069 .init_machine = r8a7740_generic_init,
1022 .init_time = shmobile_timer_init,
1023 .dt_compat = r8a7740_boards_compat_dt, 1070 .dt_compat = r8a7740_boards_compat_dt,
1024MACHINE_END 1071MACHINE_END
1025 1072
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 0174f059eac3..6a2657ebd197 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -53,7 +53,7 @@
53 .irqs = SCIx_IRQ_MUXED(irq), \ 53 .irqs = SCIx_IRQ_MUXED(irq), \
54} 54}
55 55
56static struct plat_sci_port scif_platform_data[] = { 56static struct plat_sci_port scif_platform_data[] __initdata = {
57 SCIF_INFO(0xffe40000, gic_iid(0x66)), 57 SCIF_INFO(0xffe40000, gic_iid(0x66)),
58 SCIF_INFO(0xffe41000, gic_iid(0x67)), 58 SCIF_INFO(0xffe41000, gic_iid(0x67)),
59 SCIF_INFO(0xffe42000, gic_iid(0x68)), 59 SCIF_INFO(0xffe42000, gic_iid(0x68)),
@@ -63,24 +63,24 @@ static struct plat_sci_port scif_platform_data[] = {
63}; 63};
64 64
65/* TMU */ 65/* TMU */
66static struct resource sh_tmu0_resources[] = { 66static struct resource sh_tmu0_resources[] __initdata = {
67 DEFINE_RES_MEM(0xffd80008, 12), 67 DEFINE_RES_MEM(0xffd80008, 12),
68 DEFINE_RES_IRQ(gic_iid(0x40)), 68 DEFINE_RES_IRQ(gic_iid(0x40)),
69}; 69};
70 70
71static struct sh_timer_config sh_tmu0_platform_data = { 71static struct sh_timer_config sh_tmu0_platform_data __initdata = {
72 .name = "TMU00", 72 .name = "TMU00",
73 .channel_offset = 0x4, 73 .channel_offset = 0x4,
74 .timer_bit = 0, 74 .timer_bit = 0,
75 .clockevent_rating = 200, 75 .clockevent_rating = 200,
76}; 76};
77 77
78static struct resource sh_tmu1_resources[] = { 78static struct resource sh_tmu1_resources[] __initdata = {
79 DEFINE_RES_MEM(0xffd80014, 12), 79 DEFINE_RES_MEM(0xffd80014, 12),
80 DEFINE_RES_IRQ(gic_iid(0x41)), 80 DEFINE_RES_IRQ(gic_iid(0x41)),
81}; 81};
82 82
83static struct sh_timer_config sh_tmu1_platform_data = { 83static struct sh_timer_config sh_tmu1_platform_data __initdata = {
84 .name = "TMU01", 84 .name = "TMU01",
85 .channel_offset = 0x10, 85 .channel_offset = 0x10,
86 .timer_bit = 1, 86 .timer_bit = 1,
@@ -95,20 +95,6 @@ static struct sh_timer_config sh_tmu1_platform_data = {
95 &sh_tmu##idx##_platform_data, \ 95 &sh_tmu##idx##_platform_data, \
96 sizeof(sh_tmu##idx##_platform_data)) 96 sizeof(sh_tmu##idx##_platform_data))
97 97
98/* USB PHY */
99static struct resource usb_phy_resources[] __initdata = {
100 DEFINE_RES_MEM(0xffe70800, 0x100),
101 DEFINE_RES_MEM(0xffe76000, 0x100),
102};
103
104void __init r8a7778_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
105{
106 platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
107 usb_phy_resources,
108 ARRAY_SIZE(usb_phy_resources),
109 pdata, sizeof(*pdata));
110}
111
112/* USB */ 98/* USB */
113static struct usb_phy *phy; 99static struct usb_phy *phy;
114 100
@@ -189,7 +175,7 @@ USB_PLATFORM_INFO(ehci);
189USB_PLATFORM_INFO(ohci); 175USB_PLATFORM_INFO(ohci);
190 176
191/* Ether */ 177/* Ether */
192static struct resource ether_resources[] = { 178static struct resource ether_resources[] __initdata = {
193 DEFINE_RES_MEM(0xfde00000, 0x400), 179 DEFINE_RES_MEM(0xfde00000, 0x400),
194 DEFINE_RES_IRQ(gic_iid(0x89)), 180 DEFINE_RES_IRQ(gic_iid(0x89)),
195}; 181};
@@ -203,17 +189,17 @@ void __init r8a7778_add_ether_device(struct sh_eth_plat_data *pdata)
203} 189}
204 190
205/* PFC/GPIO */ 191/* PFC/GPIO */
206static struct resource pfc_resources[] = { 192static struct resource pfc_resources[] __initdata = {
207 DEFINE_RES_MEM(0xfffc0000, 0x118), 193 DEFINE_RES_MEM(0xfffc0000, 0x118),
208}; 194};
209 195
210#define R8A7778_GPIO(idx) \ 196#define R8A7778_GPIO(idx) \
211static struct resource r8a7778_gpio##idx##_resources[] = { \ 197static struct resource r8a7778_gpio##idx##_resources[] __initdata = { \
212 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \ 198 DEFINE_RES_MEM(0xffc40000 + 0x1000 * (idx), 0x30), \
213 DEFINE_RES_IRQ(gic_iid(0x87)), \ 199 DEFINE_RES_IRQ(gic_iid(0x87)), \
214}; \ 200}; \
215 \ 201 \
216static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data = { \ 202static struct gpio_rcar_config r8a7778_gpio##idx##_platform_data __initdata = { \
217 .gpio_base = 32 * (idx), \ 203 .gpio_base = 32 * (idx), \
218 .irq_base = GPIO_IRQ_BASE(idx), \ 204 .irq_base = GPIO_IRQ_BASE(idx), \
219 .number_of_pins = 32, \ 205 .number_of_pins = 32, \
@@ -248,30 +234,6 @@ void __init r8a7778_pinmux_init(void)
248 r8a7778_register_gpio(4); 234 r8a7778_register_gpio(4);
249}; 235};
250 236
251/* SDHI */
252static struct resource sdhi_resources[] = {
253 /* SDHI0 */
254 DEFINE_RES_MEM(0xFFE4C000, 0x100),
255 DEFINE_RES_IRQ(gic_iid(0x77)),
256 /* SDHI1 */
257 DEFINE_RES_MEM(0xFFE4D000, 0x100),
258 DEFINE_RES_IRQ(gic_iid(0x78)),
259 /* SDHI2 */
260 DEFINE_RES_MEM(0xFFE4F000, 0x100),
261 DEFINE_RES_IRQ(gic_iid(0x76)),
262};
263
264void __init r8a7778_sdhi_init(int id,
265 struct sh_mobile_sdhi_info *info)
266{
267 BUG_ON(id < 0 || id > 2);
268
269 platform_device_register_resndata(
270 &platform_bus, "sh_mobile_sdhi", id,
271 sdhi_resources + (2 * id), 2,
272 info, sizeof(*info));
273}
274
275/* I2C */ 237/* I2C */
276static struct resource i2c_resources[] __initdata = { 238static struct resource i2c_resources[] __initdata = {
277 /* I2C0 */ 239 /* I2C0 */
@@ -288,7 +250,7 @@ static struct resource i2c_resources[] __initdata = {
288 DEFINE_RES_IRQ(gic_iid(0x6d)), 250 DEFINE_RES_IRQ(gic_iid(0x6d)),
289}; 251};
290 252
291void __init r8a7778_add_i2c_device(int id) 253static void __init r8a7778_register_i2c(int id)
292{ 254{
293 BUG_ON(id < 0 || id > 3); 255 BUG_ON(id < 0 || id > 3);
294 256
@@ -310,7 +272,7 @@ static struct resource hspi_resources[] __initdata = {
310 DEFINE_RES_IRQ(gic_iid(0x75)), 272 DEFINE_RES_IRQ(gic_iid(0x75)),
311}; 273};
312 274
313void __init r8a7778_add_hspi_device(int id) 275void __init r8a7778_register_hspi(int id)
314{ 276{
315 BUG_ON(id < 0 || id > 2); 277 BUG_ON(id < 0 || id > 2);
316 278
@@ -319,20 +281,6 @@ void __init r8a7778_add_hspi_device(int id)
319 hspi_resources + (2 * id), 2); 281 hspi_resources + (2 * id), 2);
320} 282}
321 283
322/* MMC */
323static struct resource mmc_resources[] __initdata = {
324 DEFINE_RES_MEM(0xffe4e000, 0x100),
325 DEFINE_RES_IRQ(gic_iid(0x5d)),
326};
327
328void __init r8a7778_add_mmc_device(struct sh_mmcif_plat_data *info)
329{
330 platform_device_register_resndata(
331 &platform_bus, "sh_mmcif", -1,
332 mmc_resources, ARRAY_SIZE(mmc_resources),
333 info, sizeof(*info));
334}
335
336/* VIN */ 284/* VIN */
337#define R8A7778_VIN(idx) \ 285#define R8A7778_VIN(idx) \
338static struct resource vin##idx##_resources[] __initdata = { \ 286static struct resource vin##idx##_resources[] __initdata = { \
@@ -367,7 +315,7 @@ void __init r8a7778_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
367 platform_device_register_full(vin_info_table[id]); 315 platform_device_register_full(vin_info_table[id]);
368} 316}
369 317
370void __init r8a7778_add_standard_devices(void) 318void __init r8a7778_add_dt_devices(void)
371{ 319{
372 int i; 320 int i;
373 321
@@ -391,6 +339,18 @@ void __init r8a7778_add_standard_devices(void)
391 r8a7778_register_tmu(1); 339 r8a7778_register_tmu(1);
392} 340}
393 341
342void __init r8a7778_add_standard_devices(void)
343{
344 r8a7778_add_dt_devices();
345 r8a7778_register_i2c(0);
346 r8a7778_register_i2c(1);
347 r8a7778_register_i2c(2);
348 r8a7778_register_i2c(3);
349 r8a7778_register_hspi(0);
350 r8a7778_register_hspi(1);
351 r8a7778_register_hspi(2);
352}
353
394void __init r8a7778_init_late(void) 354void __init r8a7778_init_late(void)
395{ 355{
396 phy = usb_get_phy(USB_PHY_TYPE_USB2); 356 phy = usb_get_phy(USB_PHY_TYPE_USB2);
@@ -399,12 +359,12 @@ void __init r8a7778_init_late(void)
399 platform_device_register_full(&ohci_info); 359 platform_device_register_full(&ohci_info);
400} 360}
401 361
402static struct renesas_intc_irqpin_config irqpin_platform_data = { 362static struct renesas_intc_irqpin_config irqpin_platform_data __initdata = {
403 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */ 363 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
404 .sense_bitfield_width = 2, 364 .sense_bitfield_width = 2,
405}; 365};
406 366
407static struct resource irqpin_resources[] = { 367static struct resource irqpin_resources[] __initdata = {
408 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */ 368 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
409 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */ 369 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
410 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */ 370 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
@@ -442,17 +402,25 @@ void __init r8a7778_init_irq_extpin(int irlm)
442 &irqpin_platform_data, sizeof(irqpin_platform_data)); 402 &irqpin_platform_data, sizeof(irqpin_platform_data));
443} 403}
444 404
405void __init r8a7778_init_delay(void)
406{
407 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
408}
409
410#ifdef CONFIG_USE_OF
445#define INT2SMSKCR0 0x82288 /* 0xfe782288 */ 411#define INT2SMSKCR0 0x82288 /* 0xfe782288 */
446#define INT2SMSKCR1 0x8228c /* 0xfe78228c */ 412#define INT2SMSKCR1 0x8228c /* 0xfe78228c */
447 413
448#define INT2NTSR0 0x00018 /* 0xfe700018 */ 414#define INT2NTSR0 0x00018 /* 0xfe700018 */
449#define INT2NTSR1 0x0002c /* 0xfe70002c */ 415#define INT2NTSR1 0x0002c /* 0xfe70002c */
450static void __init r8a7778_init_irq_common(void) 416void __init r8a7778_init_irq_dt(void)
451{ 417{
452 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000); 418 void __iomem *base = ioremap_nocache(0xfe700000, 0x00100000);
453 419
454 BUG_ON(!base); 420 BUG_ON(!base);
455 421
422 irqchip_init();
423
456 /* route all interrupts to ARM */ 424 /* route all interrupts to ARM */
457 __raw_writel(0x73ffffff, base + INT2NTSR0); 425 __raw_writel(0x73ffffff, base + INT2NTSR0);
458 __raw_writel(0xffffffff, base + INT2NTSR1); 426 __raw_writel(0xffffffff, base + INT2NTSR1);
@@ -464,43 +432,6 @@ static void __init r8a7778_init_irq_common(void)
464 iounmap(base); 432 iounmap(base);
465} 433}
466 434
467void __init r8a7778_init_irq(void)
468{
469 void __iomem *gic_dist_base;
470 void __iomem *gic_cpu_base;
471
472 gic_dist_base = ioremap_nocache(0xfe438000, PAGE_SIZE);
473 gic_cpu_base = ioremap_nocache(0xfe430000, PAGE_SIZE);
474 BUG_ON(!gic_dist_base || !gic_cpu_base);
475
476 /* use GIC to handle interrupts */
477 gic_init(0, 29, gic_dist_base, gic_cpu_base);
478
479 r8a7778_init_irq_common();
480}
481
482void __init r8a7778_init_delay(void)
483{
484 shmobile_setup_delay(800, 1, 3); /* Cortex-A9 @ 800MHz */
485}
486
487#ifdef CONFIG_USE_OF
488void __init r8a7778_init_irq_dt(void)
489{
490 irqchip_init();
491 r8a7778_init_irq_common();
492}
493
494static const struct of_dev_auxdata r8a7778_auxdata_lookup[] __initconst = {
495 {},
496};
497
498void __init r8a7778_add_standard_devices_dt(void)
499{
500 of_platform_populate(NULL, of_default_bus_match_table,
501 r8a7778_auxdata_lookup, NULL);
502}
503
504static const char *r8a7778_compat_dt[] __initdata = { 435static const char *r8a7778_compat_dt[] __initdata = {
505 "renesas,r8a7778", 436 "renesas,r8a7778",
506 NULL, 437 NULL,
@@ -509,8 +440,6 @@ static const char *r8a7778_compat_dt[] __initdata = {
509DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)") 440DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
510 .init_early = r8a7778_init_delay, 441 .init_early = r8a7778_init_delay,
511 .init_irq = r8a7778_init_irq_dt, 442 .init_irq = r8a7778_init_irq_dt,
512 .init_machine = r8a7778_add_standard_devices_dt,
513 .init_time = shmobile_timer_init,
514 .dt_compat = r8a7778_compat_dt, 443 .dt_compat = r8a7778_compat_dt,
515 .init_late = r8a7778_init_late, 444 .init_late = r8a7778_init_late,
516MACHINE_END 445MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 3d8928895503..b5b2f787da2e 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,14 +22,16 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqchip.h>
26#include <linux/irqchip/arm-gic.h>
25#include <linux/of_platform.h> 27#include <linux/of_platform.h>
26#include <linux/platform_data/gpio-rcar.h> 28#include <linux/platform_data/gpio-rcar.h>
29#include <linux/platform_data/irq-renesas-intc-irqpin.h>
27#include <linux/platform_device.h> 30#include <linux/platform_device.h>
28#include <linux/delay.h> 31#include <linux/delay.h>
29#include <linux/input.h> 32#include <linux/input.h>
30#include <linux/io.h> 33#include <linux/io.h>
31#include <linux/serial_sci.h> 34#include <linux/serial_sci.h>
32#include <linux/sh_intc.h>
33#include <linux/sh_timer.h> 35#include <linux/sh_timer.h>
34#include <linux/dma-mapping.h> 36#include <linux/dma-mapping.h>
35#include <linux/usb/otg.h> 37#include <linux/usb/otg.h>
@@ -37,7 +39,6 @@
37#include <linux/usb/ehci_pdriver.h> 39#include <linux/usb/ehci_pdriver.h>
38#include <linux/usb/ohci_pdriver.h> 40#include <linux/usb/ohci_pdriver.h>
39#include <linux/pm_runtime.h> 41#include <linux/pm_runtime.h>
40#include <mach/hardware.h>
41#include <mach/irqs.h> 42#include <mach/irqs.h>
42#include <mach/r8a7779.h> 43#include <mach/r8a7779.h>
43#include <mach/common.h> 44#include <mach/common.h>
@@ -69,6 +70,60 @@ void __init r8a7779_map_io(void)
69 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc)); 70 iotable_init(r8a7779_io_desc, ARRAY_SIZE(r8a7779_io_desc));
70} 71}
71 72
73/* IRQ */
74#define INT2SMSKCR0 IOMEM(0xfe7822a0)
75#define INT2SMSKCR1 IOMEM(0xfe7822a4)
76#define INT2SMSKCR2 IOMEM(0xfe7822a8)
77#define INT2SMSKCR3 IOMEM(0xfe7822ac)
78#define INT2SMSKCR4 IOMEM(0xfe7822b0)
79
80#define INT2NTSR0 IOMEM(0xfe700060)
81#define INT2NTSR1 IOMEM(0xfe700064)
82
83static struct renesas_intc_irqpin_config irqpin0_platform_data __initdata = {
84 .irq_base = irq_pin(0), /* IRQ0 -> IRQ3 */
85 .sense_bitfield_width = 2,
86};
87
88static struct resource irqpin0_resources[] __initdata = {
89 DEFINE_RES_MEM(0xfe78001c, 4), /* ICR1 */
90 DEFINE_RES_MEM(0xfe780010, 4), /* INTPRI */
91 DEFINE_RES_MEM(0xfe780024, 4), /* INTREQ */
92 DEFINE_RES_MEM(0xfe780044, 4), /* INTMSK0 */
93 DEFINE_RES_MEM(0xfe780064, 4), /* INTMSKCLR0 */
94 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ0 */
95 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ1 */
96 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ2 */
97 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ3 */
98};
99
100void __init r8a7779_init_irq_extpin(int irlm)
101{
102 void __iomem *icr0 = ioremap_nocache(0xfe780000, PAGE_SIZE);
103 u32 tmp;
104
105 if (!icr0) {
106 pr_warn("r8a7779: unable to setup external irq pin mode\n");
107 return;
108 }
109
110 tmp = ioread32(icr0);
111 if (irlm)
112 tmp |= 1 << 23; /* IRQ0 -> IRQ3 as individual pins */
113 else
114 tmp &= ~(1 << 23); /* IRL mode - not supported */
115 tmp |= (1 << 21); /* LVLMODE = 1 */
116 iowrite32(tmp, icr0);
117 iounmap(icr0);
118
119 if (irlm)
120 platform_device_register_resndata(
121 &platform_bus, "renesas_intc_irqpin", -1,
122 irqpin0_resources, ARRAY_SIZE(irqpin0_resources),
123 &irqpin0_platform_data, sizeof(irqpin0_platform_data));
124}
125
126/* PFC/GPIO */
72static struct resource r8a7779_pfc_resources[] = { 127static struct resource r8a7779_pfc_resources[] = {
73 DEFINE_RES_MEM(0xfffc0000, 0x023c), 128 DEFINE_RES_MEM(0xfffc0000, 0x023c),
74}; 129};
@@ -388,15 +443,6 @@ static struct platform_device sata_device = {
388 }, 443 },
389}; 444};
390 445
391/* USB PHY */
392static struct resource usb_phy_resources[] __initdata = {
393 [0] = {
394 .start = 0xffe70800,
395 .end = 0xffe70900 - 1,
396 .flags = IORESOURCE_MEM,
397 },
398};
399
400/* USB */ 446/* USB */
401static struct usb_phy *phy; 447static struct usb_phy *phy;
402 448
@@ -548,7 +594,7 @@ static struct platform_device ohci1_device = {
548}; 594};
549 595
550/* Ether */ 596/* Ether */
551static struct resource ether_resources[] = { 597static struct resource ether_resources[] __initdata = {
552 { 598 {
553 .start = 0xfde00000, 599 .start = 0xfde00000,
554 .end = 0xfde003ff, 600 .end = 0xfde003ff,
@@ -629,14 +675,6 @@ void __init r8a7779_add_ether_device(struct sh_eth_plat_data *pdata)
629 pdata, sizeof(*pdata)); 675 pdata, sizeof(*pdata));
630} 676}
631 677
632void __init r8a7779_add_usb_phy_device(struct rcar_phy_platform_data *pdata)
633{
634 platform_device_register_resndata(&platform_bus, "rcar_usb_phy", -1,
635 usb_phy_resources,
636 ARRAY_SIZE(usb_phy_resources),
637 pdata, sizeof(*pdata));
638}
639
640void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata) 678void __init r8a7779_add_vin_device(int id, struct rcar_vin_platform_data *pdata)
641{ 679{
642 BUG_ON(id < 0 || id > 3); 680 BUG_ON(id < 0 || id > 3);
@@ -697,15 +735,34 @@ void __init r8a7779_init_late(void)
697} 735}
698 736
699#ifdef CONFIG_USE_OF 737#ifdef CONFIG_USE_OF
738static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
739{
740 return 0; /* always allow wakeup */
741}
742
743void __init r8a7779_init_irq_dt(void)
744{
745 gic_arch_extn.irq_set_wake = r8a7779_set_wake;
746
747 irqchip_init();
748
749 /* route all interrupts to ARM */
750 __raw_writel(0xffffffff, INT2NTSR0);
751 __raw_writel(0x3fffffff, INT2NTSR1);
752
753 /* unmask all known interrupts in INTCS2 */
754 __raw_writel(0xfffffff0, INT2SMSKCR0);
755 __raw_writel(0xfff7ffff, INT2SMSKCR1);
756 __raw_writel(0xfffbffdf, INT2SMSKCR2);
757 __raw_writel(0xbffffffc, INT2SMSKCR3);
758 __raw_writel(0x003fee3f, INT2SMSKCR4);
759}
760
700void __init r8a7779_init_delay(void) 761void __init r8a7779_init_delay(void)
701{ 762{
702 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */ 763 shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
703} 764}
704 765
705static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
706 {},
707};
708
709void __init r8a7779_add_standard_devices_dt(void) 766void __init r8a7779_add_standard_devices_dt(void)
710{ 767{
711 /* clocks are setup late during boot in the case of DT */ 768 /* clocks are setup late during boot in the case of DT */
@@ -713,8 +770,7 @@ void __init r8a7779_add_standard_devices_dt(void)
713 770
714 platform_add_devices(r8a7779_devices_dt, 771 platform_add_devices(r8a7779_devices_dt,
715 ARRAY_SIZE(r8a7779_devices_dt)); 772 ARRAY_SIZE(r8a7779_devices_dt));
716 of_platform_populate(NULL, of_default_bus_match_table, 773 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
717 r8a7779_auxdata_lookup, NULL);
718} 774}
719 775
720static const char *r8a7779_compat_dt[] __initdata = { 776static const char *r8a7779_compat_dt[] __initdata = {
@@ -728,7 +784,6 @@ DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
728 .nr_irqs = NR_IRQS_LEGACY, 784 .nr_irqs = NR_IRQS_LEGACY,
729 .init_irq = r8a7779_init_irq_dt, 785 .init_irq = r8a7779_init_irq_dt,
730 .init_machine = r8a7779_add_standard_devices_dt, 786 .init_machine = r8a7779_add_standard_devices_dt,
731 .init_time = shmobile_timer_init,
732 .init_late = r8a7779_init_late, 787 .init_late = r8a7779_init_late,
733 .dt_compat = r8a7779_compat_dt, 788 .dt_compat = r8a7779_compat_dt,
734MACHINE_END 789MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c
index 28f94752b8ff..d0f5c9f9349a 100644
--- a/arch/arm/mach-shmobile/setup-r8a7790.c
+++ b/arch/arm/mach-shmobile/setup-r8a7790.c
@@ -18,13 +18,14 @@
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */ 19 */
20 20
21#include <linux/clocksource.h>
21#include <linux/irq.h> 22#include <linux/irq.h>
22#include <linux/irqchip.h>
23#include <linux/kernel.h> 23#include <linux/kernel.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/serial_sci.h>
26#include <linux/platform_data/gpio-rcar.h> 25#include <linux/platform_data/gpio-rcar.h>
27#include <linux/platform_data/irq-renesas-irqc.h> 26#include <linux/platform_data/irq-renesas-irqc.h>
27#include <linux/serial_sci.h>
28#include <linux/sh_timer.h>
28#include <mach/common.h> 29#include <mach/common.h>
29#include <mach/irqs.h> 30#include <mach/irqs.h>
30#include <mach/r8a7790.h> 31#include <mach/r8a7790.h>
@@ -149,7 +150,37 @@ static struct resource irqc0_resources[] __initdata = {
149 &irqc##idx##_data, \ 150 &irqc##idx##_data, \
150 sizeof(struct renesas_irqc_config)) 151 sizeof(struct renesas_irqc_config))
151 152
152void __init r8a7790_add_standard_devices(void) 153static struct resource thermal_resources[] __initdata = {
154 DEFINE_RES_MEM(0xe61f0000, 0x14),
155 DEFINE_RES_MEM(0xe61f0100, 0x38),
156 DEFINE_RES_IRQ(gic_spi(69)),
157};
158
159#define r8a7790_register_thermal() \
160 platform_device_register_simple("rcar_thermal", -1, \
161 thermal_resources, \
162 ARRAY_SIZE(thermal_resources))
163
164static struct sh_timer_config cmt00_platform_data __initdata = {
165 .name = "CMT00",
166 .timer_bit = 0,
167 .clockevent_rating = 80,
168};
169
170static struct resource cmt00_resources[] __initdata = {
171 DEFINE_RES_MEM(0xffca0510, 0x0c),
172 DEFINE_RES_MEM(0xffca0500, 0x04),
173 DEFINE_RES_IRQ(gic_spi(142)), /* CMT0_0 */
174};
175
176#define r8a7790_register_cmt(idx) \
177 platform_device_register_resndata(&platform_bus, "sh_cmt", \
178 idx, cmt##idx##_resources, \
179 ARRAY_SIZE(cmt##idx##_resources), \
180 &cmt##idx##_platform_data, \
181 sizeof(struct sh_timer_config))
182
183void __init r8a7790_add_dt_devices(void)
153{ 184{
154 r8a7790_register_scif(SCIFA0); 185 r8a7790_register_scif(SCIFA0);
155 r8a7790_register_scif(SCIFA1); 186 r8a7790_register_scif(SCIFA1);
@@ -161,35 +192,97 @@ void __init r8a7790_add_standard_devices(void)
161 r8a7790_register_scif(SCIF1); 192 r8a7790_register_scif(SCIF1);
162 r8a7790_register_scif(HSCIF0); 193 r8a7790_register_scif(HSCIF0);
163 r8a7790_register_scif(HSCIF1); 194 r8a7790_register_scif(HSCIF1);
195 r8a7790_register_cmt(00);
196}
197
198void __init r8a7790_add_standard_devices(void)
199{
200 r8a7790_add_dt_devices();
164 r8a7790_register_irqc(0); 201 r8a7790_register_irqc(0);
202 r8a7790_register_thermal();
165} 203}
166 204
205#define MODEMR 0xe6160060
206
207u32 __init r8a7790_read_mode_pins(void)
208{
209 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
210 u32 mode;
211
212 BUG_ON(!modemr);
213 mode = ioread32(modemr);
214 iounmap(modemr);
215
216 return mode;
217}
218
219#define CNTCR 0
220#define CNTFID0 0x20
221
167void __init r8a7790_timer_init(void) 222void __init r8a7790_timer_init(void)
168{ 223{
169 void __iomem *cntcr; 224#ifdef CONFIG_ARM_ARCH_TIMER
225 u32 mode = r8a7790_read_mode_pins();
226 void __iomem *base;
227 int extal_mhz = 0;
228 u32 freq;
229
230 /* At Linux boot time the r8a7790 arch timer comes up
231 * with the counter disabled. Moreover, it may also report
232 * a potentially incorrect fixed 13 MHz frequency. To be
233 * correct these registers need to be updated to use the
234 * frequency EXTAL / 2 which can be determined by the MD pins.
235 */
170 236
171 /* make sure arch timer is started by setting bit 0 of CNTCT */ 237 switch (mode & (MD(14) | MD(13))) {
172 cntcr = ioremap(0xe6080000, PAGE_SIZE); 238 case 0:
173 iowrite32(1, cntcr); 239 extal_mhz = 15;
174 iounmap(cntcr); 240 break;
241 case MD(13):
242 extal_mhz = 20;
243 break;
244 case MD(14):
245 extal_mhz = 26;
246 break;
247 case MD(13) | MD(14):
248 extal_mhz = 30;
249 break;
250 }
175 251
176 shmobile_timer_init(); 252 /* The arch timer frequency equals EXTAL / 2 */
253 freq = extal_mhz * (1000000 / 2);
254
255 /* Remap "armgcnt address map" space */
256 base = ioremap(0xe6080000, PAGE_SIZE);
257
258 /* Update registers with correct frequency */
259 iowrite32(freq, base + CNTFID0);
260 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
261
262 /* make sure arch timer is started by setting bit 0 of CNTCR */
263 iowrite32(1, base + CNTCR);
264 iounmap(base);
265#endif /* CONFIG_ARM_ARCH_TIMER */
266
267 clocksource_of_init();
177} 268}
178 269
179#ifdef CONFIG_USE_OF 270void __init r8a7790_init_delay(void)
180void __init r8a7790_add_standard_devices_dt(void)
181{ 271{
182 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 272#ifndef CONFIG_ARM_ARCH_TIMER
273 shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */
274#endif
183} 275}
184 276
277#ifdef CONFIG_USE_OF
278
185static const char *r8a7790_boards_compat_dt[] __initdata = { 279static const char *r8a7790_boards_compat_dt[] __initdata = {
186 "renesas,r8a7790", 280 "renesas,r8a7790",
187 NULL, 281 NULL,
188}; 282};
189 283
190DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") 284DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)")
191 .init_irq = irqchip_init, 285 .init_early = r8a7790_init_delay,
192 .init_machine = r8a7790_add_standard_devices_dt,
193 .init_time = r8a7790_timer_init, 286 .init_time = r8a7790_timer_init,
194 .dt_compat = r8a7790_boards_compat_dt, 287 .dt_compat = r8a7790_boards_compat_dt,
195MACHINE_END 288MACHINE_END
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index 5502d624aca6..311878391e18 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -35,7 +35,6 @@
35#include <linux/dma-mapping.h> 35#include <linux/dma-mapping.h>
36#include <linux/platform_data/sh_ipmmu.h> 36#include <linux/platform_data/sh_ipmmu.h>
37#include <mach/dma-register.h> 37#include <mach/dma-register.h>
38#include <mach/hardware.h>
39#include <mach/irqs.h> 38#include <mach/irqs.h>
40#include <mach/sh7372.h> 39#include <mach/sh7372.h>
41#include <mach/common.h> 40#include <mach/common.h>
@@ -1147,10 +1146,6 @@ void __init sh7372_add_early_devices_dt(void)
1147 shmobile_setup_console(); 1146 shmobile_setup_console();
1148} 1147}
1149 1148
1150static const struct of_dev_auxdata sh7372_auxdata_lookup[] __initconst = {
1151 { }
1152};
1153
1154void __init sh7372_add_standard_devices_dt(void) 1149void __init sh7372_add_standard_devices_dt(void)
1155{ 1150{
1156 /* clocks are setup late during boot in the case of DT */ 1151 /* clocks are setup late during boot in the case of DT */
@@ -1159,8 +1154,7 @@ void __init sh7372_add_standard_devices_dt(void)
1159 platform_add_devices(sh7372_early_devices, 1154 platform_add_devices(sh7372_early_devices,
1160 ARRAY_SIZE(sh7372_early_devices)); 1155 ARRAY_SIZE(sh7372_early_devices));
1161 1156
1162 of_platform_populate(NULL, of_default_bus_match_table, 1157 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
1163 sh7372_auxdata_lookup, NULL);
1164} 1158}
1165 1159
1166static const char *sh7372_boards_compat_dt[] __initdata = { 1160static const char *sh7372_boards_compat_dt[] __initdata = {
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 96e7ca1e4e11..22de17417fd7 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -22,7 +22,6 @@
22#include <linux/init.h> 22#include <linux/init.h>
23#include <linux/interrupt.h> 23#include <linux/interrupt.h>
24#include <linux/irq.h> 24#include <linux/irq.h>
25#include <linux/irqchip.h>
26#include <linux/platform_device.h> 25#include <linux/platform_device.h>
27#include <linux/of_platform.h> 26#include <linux/of_platform.h>
28#include <linux/delay.h> 27#include <linux/delay.h>
@@ -35,7 +34,6 @@
35#include <linux/platform_data/sh_ipmmu.h> 34#include <linux/platform_data/sh_ipmmu.h>
36#include <linux/platform_data/irq-renesas-intc-irqpin.h> 35#include <linux/platform_data/irq-renesas-intc-irqpin.h>
37#include <mach/dma-register.h> 36#include <mach/dma-register.h>
38#include <mach/hardware.h>
39#include <mach/irqs.h> 37#include <mach/irqs.h>
40#include <mach/sh73a0.h> 38#include <mach/sh73a0.h>
41#include <mach/common.h> 39#include <mach/common.h>
@@ -61,29 +59,16 @@ void __init sh73a0_map_io(void)
61 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); 59 iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc));
62} 60}
63 61
64static struct resource sh73a0_pfc_resources[] = { 62/* PFC */
65 [0] = { 63static struct resource pfc_resources[] __initdata = {
66 .start = 0xe6050000, 64 DEFINE_RES_MEM(0xe6050000, 0x8000),
67 .end = 0xe6057fff, 65 DEFINE_RES_MEM(0xe605801c, 0x000c),
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = 0xe605801c,
72 .end = 0xe6058027,
73 .flags = IORESOURCE_MEM,
74 }
75};
76
77static struct platform_device sh73a0_pfc_device = {
78 .name = "pfc-sh73a0",
79 .id = -1,
80 .resource = sh73a0_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh73a0_pfc_resources),
82}; 66};
83 67
84void __init sh73a0_pinmux_init(void) 68void __init sh73a0_pinmux_init(void)
85{ 69{
86 platform_device_register(&sh73a0_pfc_device); 70 platform_device_register_simple("pfc-sh73a0", -1, pfc_resources,
71 ARRAY_SIZE(pfc_resources));
87} 72}
88 73
89static struct plat_sci_port scif0_platform_data = { 74static struct plat_sci_port scif0_platform_data = {
@@ -958,10 +943,6 @@ void __init sh73a0_add_early_devices(void)
958 943
959#ifdef CONFIG_USE_OF 944#ifdef CONFIG_USE_OF
960 945
961static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
962 {},
963};
964
965void __init sh73a0_add_standard_devices_dt(void) 946void __init sh73a0_add_standard_devices_dt(void)
966{ 947{
967 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; 948 struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, };
@@ -971,8 +952,7 @@ void __init sh73a0_add_standard_devices_dt(void)
971 952
972 platform_add_devices(sh73a0_devices_dt, 953 platform_add_devices(sh73a0_devices_dt,
973 ARRAY_SIZE(sh73a0_devices_dt)); 954 ARRAY_SIZE(sh73a0_devices_dt));
974 of_platform_populate(NULL, of_default_bus_match_table, 955 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
975 sh73a0_auxdata_lookup, NULL);
976 956
977 /* Instantiate cpufreq-cpu0 */ 957 /* Instantiate cpufreq-cpu0 */
978 platform_device_register_full(&devinfo); 958 platform_device_register_full(&devinfo);
@@ -988,7 +968,6 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
988 .map_io = sh73a0_map_io, 968 .map_io = sh73a0_map_io,
989 .init_early = sh73a0_init_delay, 969 .init_early = sh73a0_init_delay,
990 .nr_irqs = NR_IRQS_LEGACY, 970 .nr_irqs = NR_IRQS_LEGACY,
991 .init_irq = irqchip_init,
992 .init_machine = sh73a0_add_standard_devices_dt, 971 .init_machine = sh73a0_add_standard_devices_dt,
993 .dt_compat = sh73a0_boards_compat_dt, 972 .dt_compat = sh73a0_boards_compat_dt,
994MACHINE_END 973MACHINE_END
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index 53f4840e4949..9782862899e8 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -41,6 +41,7 @@
41sh7372_resume_core_standby_sysc: 41sh7372_resume_core_standby_sysc:
42 ldr pc, 1f 42 ldr pc, 1f
43 43
44 .align 2
44 .globl sh7372_cpu_resume 45 .globl sh7372_cpu_resume
45sh7372_cpu_resume: 46sh7372_cpu_resume:
461: .space 4 471: .space 4
@@ -96,6 +97,7 @@ sh7372_do_idle_sysc:
961: 971:
97 b 1b 98 b 1b
98 99
100 .align 2
99kernel_flush: 101kernel_flush:
100 .word v7_flush_dcache_all 102 .word v7_flush_dcache_all
101#endif 103#endif
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 22a05a869d25..522de5ebb55f 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -29,41 +29,38 @@
29#include <asm/smp_scu.h> 29#include <asm/smp_scu.h>
30 30
31#define EMEV2_SCU_BASE 0x1e000000 31#define EMEV2_SCU_BASE 0x1e000000
32#define EMEV2_SMU_BASE 0xe0110000
33#define SMU_GENERAL_REG0 0x7c0
32 34
33static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle) 35static int emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
34{ 36{
37 int ret;
38
39 ret = shmobile_smp_scu_boot_secondary(cpu, idle);
40 if (ret)
41 return ret;
42
35 arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu))); 43 arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
36 return 0; 44 return 0;
37} 45}
38 46
39static void __init emev2_smp_prepare_cpus(unsigned int max_cpus) 47static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
40{ 48{
41 scu_enable(shmobile_scu_base); 49 void __iomem *smu;
42
43 /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
44 emev2_set_boot_vector(__pa(shmobile_boot_vector));
45 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
46 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
47
48 /* enable cache coherency on booting CPU */
49 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
50}
51 50
52static void __init emev2_smp_init_cpus(void) 51 /* Tell ROM loader about our vector (in headsmp.S) */
53{ 52 smu = ioremap(EMEV2_SMU_BASE, PAGE_SIZE);
54 unsigned int ncores; 53 if (smu) {
54 iowrite32(__pa(shmobile_boot_vector), smu + SMU_GENERAL_REG0);
55 iounmap(smu);
56 }
55 57
56 /* setup EMEV2 specific SCU base */ 58 /* setup EMEV2 specific SCU bits */
57 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE); 59 shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
58 emev2_clock_init(); /* need ioremapped SMU */ 60 shmobile_smp_scu_prepare_cpus(max_cpus);
59
60 ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
61
62 shmobile_smp_init_cpus(ncores);
63} 61}
64 62
65struct smp_operations emev2_smp_ops __initdata = { 63struct smp_operations emev2_smp_ops __initdata = {
66 .smp_init_cpus = emev2_smp_init_cpus,
67 .smp_prepare_cpus = emev2_smp_prepare_cpus, 64 .smp_prepare_cpus = emev2_smp_prepare_cpus,
68 .smp_boot_secondary = emev2_boot_secondary, 65 .smp_boot_secondary = emev2_boot_secondary,
69}; 66};
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 9bdf810f2a87..0f05e9fb722f 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -84,30 +84,34 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
84static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle) 84static int r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
85{ 85{
86 struct r8a7779_pm_ch *ch = NULL; 86 struct r8a7779_pm_ch *ch = NULL;
87 int ret = -EIO; 87 unsigned int lcpu = cpu_logical_map(cpu);
88 int ret;
88 89
89 cpu = cpu_logical_map(cpu); 90 ret = shmobile_smp_scu_boot_secondary(cpu, idle);
91 if (ret)
92 return ret;
90 93
91 if (cpu < ARRAY_SIZE(r8a7779_ch_cpu)) 94 if (lcpu < ARRAY_SIZE(r8a7779_ch_cpu))
92 ch = r8a7779_ch_cpu[cpu]; 95 ch = r8a7779_ch_cpu[lcpu];
93 96
94 if (ch) 97 if (ch)
95 ret = r8a7779_sysc_power_up(ch); 98 ret = r8a7779_sysc_power_up(ch);
99 else
100 ret = -EIO;
96 101
97 return ret; 102 return ret;
98} 103}
99 104
100static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus) 105static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
101{ 106{
102 scu_enable(shmobile_scu_base);
103
104 /* Map the reset vector (in headsmp-scu.S, headsmp.S) */ 107 /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
105 __raw_writel(__pa(shmobile_boot_vector), AVECR); 108 __raw_writel(__pa(shmobile_boot_vector), AVECR);
106 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu); 109 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
107 shmobile_boot_arg = (unsigned long)shmobile_scu_base; 110 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
108 111
109 /* enable cache coherency on booting CPU */ 112 /* setup r8a7779 specific SCU bits */
110 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 113 shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
114 shmobile_smp_scu_prepare_cpus(max_cpus);
111 115
112 r8a7779_pm_init(); 116 r8a7779_pm_init();
113 117
@@ -117,56 +121,15 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
117 r8a7779_platform_cpu_kill(3); 121 r8a7779_platform_cpu_kill(3);
118} 122}
119 123
120static void __init r8a7779_smp_init_cpus(void)
121{
122 /* setup r8a7779 specific SCU base */
123 shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
124
125 shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
126}
127
128#ifdef CONFIG_HOTPLUG_CPU 124#ifdef CONFIG_HOTPLUG_CPU
129static int r8a7779_scu_psr_core_disabled(int cpu)
130{
131 unsigned long mask = 3 << (cpu * 8);
132
133 if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
134 return 1;
135
136 return 0;
137}
138
139static int r8a7779_cpu_kill(unsigned int cpu) 125static int r8a7779_cpu_kill(unsigned int cpu)
140{ 126{
141 int k; 127 if (shmobile_smp_scu_cpu_kill(cpu))
142 128 return r8a7779_platform_cpu_kill(cpu);
143 /* this function is running on another CPU than the offline target,
144 * here we need wait for shutdown code in platform_cpu_die() to
145 * finish before asking SoC-specific code to power off the CPU core.
146 */
147 for (k = 0; k < 1000; k++) {
148 if (r8a7779_scu_psr_core_disabled(cpu))
149 return r8a7779_platform_cpu_kill(cpu);
150
151 mdelay(1);
152 }
153 129
154 return 0; 130 return 0;
155} 131}
156 132
157static void r8a7779_cpu_die(unsigned int cpu)
158{
159 dsb();
160 flush_cache_all();
161
162 /* disable cache coherency */
163 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
164
165 /* Endless loop until power off from r8a7779_cpu_kill() */
166 while (1)
167 cpu_do_idle();
168}
169
170static int r8a7779_cpu_disable(unsigned int cpu) 133static int r8a7779_cpu_disable(unsigned int cpu)
171{ 134{
172 /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */ 135 /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
@@ -175,12 +138,11 @@ static int r8a7779_cpu_disable(unsigned int cpu)
175#endif /* CONFIG_HOTPLUG_CPU */ 138#endif /* CONFIG_HOTPLUG_CPU */
176 139
177struct smp_operations r8a7779_smp_ops __initdata = { 140struct smp_operations r8a7779_smp_ops __initdata = {
178 .smp_init_cpus = r8a7779_smp_init_cpus,
179 .smp_prepare_cpus = r8a7779_smp_prepare_cpus, 141 .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
180 .smp_boot_secondary = r8a7779_boot_secondary, 142 .smp_boot_secondary = r8a7779_boot_secondary,
181#ifdef CONFIG_HOTPLUG_CPU 143#ifdef CONFIG_HOTPLUG_CPU
182 .cpu_kill = r8a7779_cpu_kill,
183 .cpu_die = r8a7779_cpu_die,
184 .cpu_disable = r8a7779_cpu_disable, 144 .cpu_disable = r8a7779_cpu_disable,
145 .cpu_die = shmobile_smp_scu_cpu_die,
146 .cpu_kill = r8a7779_cpu_kill,
185#endif 147#endif
186}; 148};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index d5fc3ed4e315..0baa24443793 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -20,14 +20,11 @@
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/init.h> 21#include <linux/init.h>
22#include <linux/smp.h> 22#include <linux/smp.h>
23#include <linux/spinlock.h>
24#include <linux/io.h> 23#include <linux/io.h>
25#include <linux/delay.h> 24#include <linux/delay.h>
26#include <mach/common.h> 25#include <mach/common.h>
27#include <asm/cacheflush.h>
28#include <asm/smp_plat.h>
29#include <mach/sh73a0.h> 26#include <mach/sh73a0.h>
30#include <asm/smp_scu.h> 27#include <asm/smp_plat.h>
31#include <asm/smp_twd.h> 28#include <asm/smp_twd.h>
32 29
33#define WUPCR IOMEM(0xe6151010) 30#define WUPCR IOMEM(0xe6151010)
@@ -36,8 +33,6 @@
36#define SBAR IOMEM(0xe6180020) 33#define SBAR IOMEM(0xe6180020)
37#define APARMBAREA IOMEM(0xe6f10020) 34#define APARMBAREA IOMEM(0xe6f10020)
38 35
39#define PSTR_SHUTDOWN_MODE 3
40
41#define SH73A0_SCU_BASE 0xf0000000 36#define SH73A0_SCU_BASE 0xf0000000
42 37
43#ifdef CONFIG_HAVE_ARM_TWD 38#ifdef CONFIG_HAVE_ARM_TWD
@@ -50,69 +45,33 @@ void __init sh73a0_register_twd(void)
50 45
51static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle) 46static int sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
52{ 47{
53 cpu = cpu_logical_map(cpu); 48 unsigned int lcpu = cpu_logical_map(cpu);
49 int ret;
54 50
55 if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3) 51 ret = shmobile_smp_scu_boot_secondary(cpu, idle);
56 __raw_writel(1 << cpu, WUPCR); /* wake up */ 52 if (ret)
53 return ret;
54
55 if (((__raw_readl(PSTR) >> (4 * lcpu)) & 3) == 3)
56 __raw_writel(1 << lcpu, WUPCR); /* wake up */
57 else 57 else
58 __raw_writel(1 << cpu, SRESCR); /* reset */ 58 __raw_writel(1 << lcpu, SRESCR); /* reset */
59 59
60 return 0; 60 return 0;
61} 61}
62 62
63static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus) 63static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
64{ 64{
65 scu_enable(shmobile_scu_base); 65 /* Map the reset vector (in headsmp.S) */
66
67 /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
68 __raw_writel(0, APARMBAREA); /* 4k */ 66 __raw_writel(0, APARMBAREA); /* 4k */
69 __raw_writel(__pa(shmobile_boot_vector), SBAR); 67 __raw_writel(__pa(shmobile_boot_vector), SBAR);
70 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
71 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
72 68
73 /* enable cache coherency on booting CPU */ 69 /* setup sh73a0 specific SCU bits */
74 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
75}
76
77static void __init sh73a0_smp_init_cpus(void)
78{
79 /* setup sh73a0 specific SCU base */
80 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE); 70 shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
81 71 shmobile_smp_scu_prepare_cpus(max_cpus);
82 shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
83} 72}
84 73
85#ifdef CONFIG_HOTPLUG_CPU 74#ifdef CONFIG_HOTPLUG_CPU
86static int sh73a0_cpu_kill(unsigned int cpu)
87{
88
89 int k;
90 u32 pstr;
91
92 /*
93 * wait until the power status register confirms the shutdown of the
94 * offline target
95 */
96 for (k = 0; k < 1000; k++) {
97 pstr = (__raw_readl(PSTR) >> (4 * cpu)) & 3;
98 if (pstr == PSTR_SHUTDOWN_MODE)
99 return 1;
100
101 mdelay(1);
102 }
103
104 return 0;
105}
106
107static void sh73a0_cpu_die(unsigned int cpu)
108{
109 /* Set power off mode. This takes the CPU out of the MP cluster */
110 scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
111
112 /* Enter shutdown mode */
113 cpu_do_idle();
114}
115
116static int sh73a0_cpu_disable(unsigned int cpu) 75static int sh73a0_cpu_disable(unsigned int cpu)
117{ 76{
118 return 0; /* CPU0 and CPU1 supported */ 77 return 0; /* CPU0 and CPU1 supported */
@@ -120,12 +79,11 @@ static int sh73a0_cpu_disable(unsigned int cpu)
120#endif /* CONFIG_HOTPLUG_CPU */ 79#endif /* CONFIG_HOTPLUG_CPU */
121 80
122struct smp_operations sh73a0_smp_ops __initdata = { 81struct smp_operations sh73a0_smp_ops __initdata = {
123 .smp_init_cpus = sh73a0_smp_init_cpus,
124 .smp_prepare_cpus = sh73a0_smp_prepare_cpus, 82 .smp_prepare_cpus = sh73a0_smp_prepare_cpus,
125 .smp_boot_secondary = sh73a0_boot_secondary, 83 .smp_boot_secondary = sh73a0_boot_secondary,
126#ifdef CONFIG_HOTPLUG_CPU 84#ifdef CONFIG_HOTPLUG_CPU
127 .cpu_kill = sh73a0_cpu_kill,
128 .cpu_die = sh73a0_cpu_die,
129 .cpu_disable = sh73a0_cpu_disable, 85 .cpu_disable = sh73a0_cpu_disable,
86 .cpu_die = shmobile_smp_scu_cpu_die,
87 .cpu_kill = shmobile_smp_scu_cpu_kill,
130#endif 88#endif
131}; 89};
diff --git a/arch/arm/mach-shmobile/timer.c b/arch/arm/mach-shmobile/timer.c
index f321dbeb2379..62d7052d6f21 100644
--- a/arch/arm/mach-shmobile/timer.c
+++ b/arch/arm/mach-shmobile/timer.c
@@ -59,7 +59,3 @@ void __init shmobile_earlytimer_init(void)
59 late_time_init = shmobile_late_time_init; 59 late_time_init = shmobile_late_time_init;
60} 60}
61 61
62void __init shmobile_timer_init(void)
63{
64 clocksource_of_init();
65}
diff --git a/arch/arm/mach-spear/Kconfig b/arch/arm/mach-spear/Kconfig
index 442917eedff3..df0d59afeb40 100644
--- a/arch/arm/mach-spear/Kconfig
+++ b/arch/arm/mach-spear/Kconfig
@@ -23,7 +23,7 @@ config ARCH_SPEAR13XX
23 select CPU_V7 23 select CPU_V7
24 select GPIO_SPEAR_SPICS 24 select GPIO_SPEAR_SPICS
25 select HAVE_ARM_SCU if SMP 25 select HAVE_ARM_SCU if SMP
26 select HAVE_ARM_TWD if LOCAL_TIMERS 26 select HAVE_ARM_TWD if SMP
27 select HAVE_SMP 27 select HAVE_SMP
28 select MIGHT_HAVE_CACHE_L2X0 28 select MIGHT_HAVE_CACHE_L2X0
29 select PINCTRL 29 select PINCTRL
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 5b045e302b43..3ab2f65f8a50 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -10,3 +10,5 @@ config ARCH_SUNXI
10 select SPARSE_IRQ 10 select SPARSE_IRQ
11 select SUN4I_TIMER 11 select SUN4I_TIMER
12 select PINCTRL_SUNXI 12 select PINCTRL_SUNXI
13 select ARM_GIC
14 select HAVE_SMP
diff --git a/arch/arm/mach-sunxi/Makefile.boot b/arch/arm/mach-sunxi/Makefile.boot
deleted file mode 100644
index 46d4cf0841c0..000000000000
--- a/arch/arm/mach-sunxi/Makefile.boot
+++ /dev/null
@@ -1 +0,0 @@
1zreladdr-$(CONFIG_ARCH_SUNXI) += 0x40008000
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 38a3c55527c8..e79fb3469341 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -27,10 +27,19 @@
27#include <asm/system_misc.h> 27#include <asm/system_misc.h>
28 28
29#define SUN4I_WATCHDOG_CTRL_REG 0x00 29#define SUN4I_WATCHDOG_CTRL_REG 0x00
30#define SUN4I_WATCHDOG_CTRL_RESTART (1 << 0) 30#define SUN4I_WATCHDOG_CTRL_RESTART BIT(0)
31#define SUN4I_WATCHDOG_MODE_REG 0x04 31#define SUN4I_WATCHDOG_MODE_REG 0x04
32#define SUN4I_WATCHDOG_MODE_ENABLE (1 << 0) 32#define SUN4I_WATCHDOG_MODE_ENABLE BIT(0)
33#define SUN4I_WATCHDOG_MODE_RESET_ENABLE (1 << 1) 33#define SUN4I_WATCHDOG_MODE_RESET_ENABLE BIT(1)
34
35#define SUN6I_WATCHDOG1_IRQ_REG 0x00
36#define SUN6I_WATCHDOG1_CTRL_REG 0x10
37#define SUN6I_WATCHDOG1_CTRL_RESTART BIT(0)
38#define SUN6I_WATCHDOG1_CONFIG_REG 0x14
39#define SUN6I_WATCHDOG1_CONFIG_RESTART BIT(0)
40#define SUN6I_WATCHDOG1_CONFIG_IRQ BIT(1)
41#define SUN6I_WATCHDOG1_MODE_REG 0x18
42#define SUN6I_WATCHDOG1_MODE_ENABLE BIT(0)
34 43
35static void __iomem *wdt_base; 44static void __iomem *wdt_base;
36 45
@@ -56,8 +65,36 @@ static void sun4i_restart(enum reboot_mode mode, const char *cmd)
56 } 65 }
57} 66}
58 67
68static void sun6i_restart(enum reboot_mode mode, const char *cmd)
69{
70 if (!wdt_base)
71 return;
72
73 /* Disable interrupts */
74 writel(0, wdt_base + SUN6I_WATCHDOG1_IRQ_REG);
75
76 /* We want to disable the IRQ and just reset the whole system */
77 writel(SUN6I_WATCHDOG1_CONFIG_RESTART,
78 wdt_base + SUN6I_WATCHDOG1_CONFIG_REG);
79
80 /* Enable timer. The default and lowest interval value is 0.5s */
81 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
82 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
83
84 /* Restart the watchdog. */
85 writel(SUN6I_WATCHDOG1_CTRL_RESTART,
86 wdt_base + SUN6I_WATCHDOG1_CTRL_REG);
87
88 while (1) {
89 mdelay(5);
90 writel(SUN6I_WATCHDOG1_MODE_ENABLE,
91 wdt_base + SUN6I_WATCHDOG1_MODE_REG);
92 }
93}
94
59static struct of_device_id sunxi_restart_ids[] = { 95static struct of_device_id sunxi_restart_ids[] = {
60 { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart }, 96 { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
97 { .compatible = "allwinner,sun6i-wdt", .data = sun6i_restart },
61 { /*sentinel*/ } 98 { /*sentinel*/ }
62}; 99};
63 100
@@ -96,6 +133,8 @@ static const char * const sunxi_board_dt_compat[] = {
96 "allwinner,sun4i-a10", 133 "allwinner,sun4i-a10",
97 "allwinner,sun5i-a10s", 134 "allwinner,sun5i-a10s",
98 "allwinner,sun5i-a13", 135 "allwinner,sun5i-a13",
136 "allwinner,sun6i-a31",
137 "allwinner,sun7i-a20",
99 NULL, 138 NULL,
100}; 139};
101 140
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ef3a8da49b2d..67a76f2dfb9f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -2,18 +2,25 @@ config ARCH_TEGRA
2 bool "NVIDIA Tegra" if ARCH_MULTI_V7 2 bool "NVIDIA Tegra" if ARCH_MULTI_V7
3 select ARCH_HAS_CPUFREQ 3 select ARCH_HAS_CPUFREQ
4 select ARCH_REQUIRE_GPIOLIB 4 select ARCH_REQUIRE_GPIOLIB
5 select ARM_GIC
5 select CLKDEV_LOOKUP 6 select CLKDEV_LOOKUP
6 select CLKSRC_MMIO 7 select CLKSRC_MMIO
7 select CLKSRC_OF 8 select CLKSRC_OF
8 select COMMON_CLK 9 select COMMON_CLK
10 select CPU_V7
9 select GENERIC_CLOCKEVENTS 11 select GENERIC_CLOCKEVENTS
10 select HAVE_ARM_SCU if SMP 12 select HAVE_ARM_SCU if SMP
11 select HAVE_ARM_TWD if LOCAL_TIMERS 13 select HAVE_ARM_TWD if SMP
12 select HAVE_CLK 14 select HAVE_CLK
13 select HAVE_SMP 15 select HAVE_SMP
14 select MIGHT_HAVE_CACHE_L2X0 16 select MIGHT_HAVE_CACHE_L2X0
17 select MIGHT_HAVE_PCI
18 select PINCTRL
15 select SOC_BUS 19 select SOC_BUS
16 select SPARSE_IRQ 20 select SPARSE_IRQ
21 select USB_ARCH_HAS_EHCI if USB_SUPPORT
22 select USB_ULPI if USB_PHY
23 select USB_ULPI_VIEWPORT if USB_PHY
17 select USE_OF 24 select USE_OF
18 help 25 help
19 This enables support for NVIDIA Tegra based systems. 26 This enables support for NVIDIA Tegra based systems.
@@ -27,15 +34,9 @@ config ARCH_TEGRA_2x_SOC
27 select ARM_ERRATA_720789 34 select ARM_ERRATA_720789
28 select ARM_ERRATA_754327 if SMP 35 select ARM_ERRATA_754327 if SMP
29 select ARM_ERRATA_764369 if SMP 36 select ARM_ERRATA_764369 if SMP
30 select ARM_GIC
31 select CPU_V7
32 select PINCTRL
33 select PINCTRL_TEGRA20 37 select PINCTRL_TEGRA20
34 select PL310_ERRATA_727915 if CACHE_L2X0 38 select PL310_ERRATA_727915 if CACHE_L2X0
35 select PL310_ERRATA_769419 if CACHE_L2X0 39 select PL310_ERRATA_769419 if CACHE_L2X0
36 select USB_ARCH_HAS_EHCI if USB_SUPPORT
37 select USB_ULPI if USB_PHY
38 select USB_ULPI_VIEWPORT if USB_PHY
39 help 40 help
40 Support for NVIDIA Tegra AP20 and T20 processors, based on the 41 Support for NVIDIA Tegra AP20 and T20 processors, based on the
41 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 42 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -44,14 +45,8 @@ config ARCH_TEGRA_3x_SOC
44 bool "Enable support for Tegra30 family" 45 bool "Enable support for Tegra30 family"
45 select ARM_ERRATA_754322 46 select ARM_ERRATA_754322
46 select ARM_ERRATA_764369 if SMP 47 select ARM_ERRATA_764369 if SMP
47 select ARM_GIC
48 select CPU_V7
49 select PINCTRL
50 select PINCTRL_TEGRA30 48 select PINCTRL_TEGRA30
51 select PL310_ERRATA_769419 if CACHE_L2X0 49 select PL310_ERRATA_769419 if CACHE_L2X0
52 select USB_ARCH_HAS_EHCI if USB_SUPPORT
53 select USB_ULPI if USB_PHY
54 select USB_ULPI_VIEWPORT if USB_PHY
55 help 50 help
56 Support for NVIDIA Tegra T30 processor family, based on the 51 Support for NVIDIA Tegra T30 processor family, based on the
57 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller 52 ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
@@ -59,20 +54,13 @@ config ARCH_TEGRA_3x_SOC
59config ARCH_TEGRA_114_SOC 54config ARCH_TEGRA_114_SOC
60 bool "Enable support for Tegra114 family" 55 bool "Enable support for Tegra114 family"
61 select HAVE_ARM_ARCH_TIMER 56 select HAVE_ARM_ARCH_TIMER
62 select ARM_GIC 57 select ARM_ERRATA_798181
63 select ARM_L1_CACHE_SHIFT_6 58 select ARM_L1_CACHE_SHIFT_6
64 select CPU_V7
65 select PINCTRL
66 select PINCTRL_TEGRA114 59 select PINCTRL_TEGRA114
67 help 60 help
68 Support for NVIDIA Tegra T114 processor family, based on the 61 Support for NVIDIA Tegra T114 processor family, based on the
69 ARM CortexA15MP CPU 62 ARM CortexA15MP CPU
70 63
71config TEGRA_PCI
72 bool "PCI Express support"
73 depends on ARCH_TEGRA_2x_SOC
74 select PCI
75
76config TEGRA_AHB 64config TEGRA_AHB
77 bool "Enable AHB driver for NVIDIA Tegra SoCs" 65 bool "Enable AHB driver for NVIDIA Tegra SoCs"
78 default y 66 default y
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 98b184efc110..e7e5f45c6558 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -17,24 +17,24 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o 17obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o 18obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
19obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o 19obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
20obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
20ifeq ($(CONFIG_CPU_IDLE),y) 21ifeq ($(CONFIG_CPU_IDLE),y)
21obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o 22obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
22endif 23endif
23obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o 24obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
24obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o 25obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
26obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
25ifeq ($(CONFIG_CPU_IDLE),y) 27ifeq ($(CONFIG_CPU_IDLE),y)
26obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o 28obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
27endif 29endif
28obj-$(CONFIG_SMP) += platsmp.o headsmp.o 30obj-$(CONFIG_SMP) += platsmp.o headsmp.o
29obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 31obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
30obj-$(CONFIG_TEGRA_PCI) += pcie.o
31 32
32obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o 33obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
33obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o 34obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
35obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
34ifeq ($(CONFIG_CPU_IDLE),y) 36ifeq ($(CONFIG_CPU_IDLE),y)
35obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o 37obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
36endif 38endif
37 39
38obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
39
40obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o 40obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
deleted file mode 100644
index 035b240b9e15..000000000000
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/mach-tegra/board-harmony-pcie.c
3 *
4 * Copyright (C) 2010 CompuLab, Ltd.
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/gpio.h>
20#include <linux/err.h>
21#include <linux/of_gpio.h>
22#include <linux/regulator/consumer.h>
23
24#include <asm/mach-types.h>
25
26#include "board.h"
27
28#ifdef CONFIG_TEGRA_PCI
29
30int __init harmony_pcie_init(void)
31{
32 struct device_node *np;
33 int en_vdd_1v05;
34 struct regulator *regulator = NULL;
35 int err;
36
37 np = of_find_node_by_path("/regulators/regulator@3");
38 if (!np) {
39 pr_err("%s: of_find_node_by_path failed\n", __func__);
40 return -ENODEV;
41 }
42
43 en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
44 if (en_vdd_1v05 < 0) {
45 pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
46 en_vdd_1v05);
47 return en_vdd_1v05;
48 }
49
50 err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
51 if (err) {
52 pr_err("%s: gpio_request failed: %d\n", __func__, err);
53 return err;
54 }
55
56 gpio_direction_output(en_vdd_1v05, 1);
57
58 regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
59 if (IS_ERR(regulator)) {
60 err = PTR_ERR(regulator);
61 pr_err("%s: regulator_get failed: %d\n", __func__, err);
62 goto err_reg;
63 }
64
65 err = regulator_enable(regulator);
66 if (err) {
67 pr_err("%s: regulator_enable failed: %d\n", __func__, err);
68 goto err_en;
69 }
70
71 err = tegra_pcie_init(true, true);
72 if (err) {
73 pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
74 goto err_pcie;
75 }
76
77 return 0;
78
79err_pcie:
80 regulator_disable(regulator);
81err_en:
82 regulator_put(regulator);
83err_reg:
84 gpio_free(en_vdd_1v05);
85
86 return err;
87}
88
89#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 9a6659fe2dc2..db6810dc0b3d 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -31,7 +31,6 @@ void __init tegra_init_early(void);
31void __init tegra_map_common_io(void); 31void __init tegra_map_common_io(void);
32void __init tegra_init_irq(void); 32void __init tegra_init_irq(void);
33void __init tegra_dt_init_irq(void); 33void __init tegra_dt_init_irq(void);
34int __init tegra_pcie_init(bool init_port0, bool init_port1);
35 34
36void tegra_init_late(void); 35void tegra_init_late(void);
37 36
@@ -48,13 +47,6 @@ int __init tegra_powergate_debugfs_init(void);
48static inline int tegra_powergate_debugfs_init(void) { return 0; } 47static inline int tegra_powergate_debugfs_init(void) { return 0; }
49#endif 48#endif
50 49
51int __init harmony_regulator_init(void);
52#ifdef CONFIG_TEGRA_PCI
53int __init harmony_pcie_init(void);
54#else
55static inline int harmony_pcie_init(void) { return 0; }
56#endif
57
58void __init tegra_paz00_wifikill_init(void); 50void __init tegra_paz00_wifikill_init(void);
59 51
60#endif 52#endif
diff --git a/arch/arm/mach-tegra/common.h b/arch/arm/mach-tegra/common.h
index 32f8eb3fe344..5900cc44f780 100644
--- a/arch/arm/mach-tegra/common.h
+++ b/arch/arm/mach-tegra/common.h
@@ -2,4 +2,3 @@ extern struct smp_operations tegra_smp_ops;
2 2
3extern int tegra_cpu_kill(unsigned int cpu); 3extern int tegra_cpu_kill(unsigned int cpu);
4extern void tegra_cpu_die(unsigned int cpu); 4extern void tegra_cpu_die(unsigned int cpu);
5extern int tegra_cpu_disable(unsigned int cpu);
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 1d1c6023f4a2..e0b87300243d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -17,15 +17,64 @@
17#include <linux/kernel.h> 17#include <linux/kernel.h>
18#include <linux/module.h> 18#include <linux/module.h>
19#include <linux/cpuidle.h> 19#include <linux/cpuidle.h>
20#include <linux/cpu_pm.h>
21#include <linux/clockchips.h>
20 22
21#include <asm/cpuidle.h> 23#include <asm/cpuidle.h>
24#include <asm/suspend.h>
25#include <asm/smp_plat.h>
26
27#include "pm.h"
28#include "sleep.h"
29
30#ifdef CONFIG_PM_SLEEP
31#define TEGRA114_MAX_STATES 2
32#else
33#define TEGRA114_MAX_STATES 1
34#endif
35
36#ifdef CONFIG_PM_SLEEP
37static int tegra114_idle_power_down(struct cpuidle_device *dev,
38 struct cpuidle_driver *drv,
39 int index)
40{
41 local_fiq_disable();
42
43 tegra_set_cpu_in_lp2();
44 cpu_pm_enter();
45
46 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &dev->cpu);
47
48 cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
49
50 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &dev->cpu);
51
52 cpu_pm_exit();
53 tegra_clear_cpu_in_lp2();
54
55 local_fiq_enable();
56
57 return index;
58}
59#endif
22 60
23static struct cpuidle_driver tegra_idle_driver = { 61static struct cpuidle_driver tegra_idle_driver = {
24 .name = "tegra_idle", 62 .name = "tegra_idle",
25 .owner = THIS_MODULE, 63 .owner = THIS_MODULE,
26 .state_count = 1, 64 .state_count = TEGRA114_MAX_STATES,
27 .states = { 65 .states = {
28 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600), 66 [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
67#ifdef CONFIG_PM_SLEEP
68 [1] = {
69 .enter = tegra114_idle_power_down,
70 .exit_latency = 500,
71 .target_residency = 1000,
72 .power_usage = 0,
73 .flags = CPUIDLE_FLAG_TIME_VALID,
74 .name = "powered-down",
75 .desc = "CPU power gated",
76 },
77#endif
29 }, 78 },
30}; 79};
31 80
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 706aa4215c36..b82dcaee2ef4 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -211,6 +211,18 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
211} 211}
212#endif 212#endif
213 213
214/*
215 * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
216 * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
217 * this, simply disable LP2 if the PCI driver and DT node are both enabled.
218 */
219void tegra20_cpuidle_pcie_irqs_in_use(void)
220{
221 pr_info_once(
222 "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
223 tegra_idle_driver.states[1].disabled = true;
224}
225
214int __init tegra20_cpuidle_init(void) 226int __init tegra20_cpuidle_init(void)
215{ 227{
216 return cpuidle_register(&tegra_idle_driver, cpu_possible_mask); 228 return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index e85973cef037..0961dfcf83a4 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -44,3 +44,13 @@ void __init tegra_cpuidle_init(void)
44 break; 44 break;
45 } 45 }
46} 46}
47
48void tegra_cpuidle_pcie_irqs_in_use(void)
49{
50 switch (tegra_chip_id) {
51 case TEGRA20:
52 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
53 tegra20_cpuidle_pcie_irqs_in_use();
54 break;
55 }
56}
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index 9ec2c1ab0fa4..c017dab60ffa 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -19,6 +19,7 @@
19 19
20#ifdef CONFIG_CPU_IDLE 20#ifdef CONFIG_CPU_IDLE
21int tegra20_cpuidle_init(void); 21int tegra20_cpuidle_init(void);
22void tegra20_cpuidle_pcie_irqs_in_use(void);
22int tegra30_cpuidle_init(void); 23int tegra30_cpuidle_init(void);
23int tegra114_cpuidle_init(void); 24int tegra114_cpuidle_init(void);
24void tegra_cpuidle_init(void); 25void tegra_cpuidle_init(void);
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c
index b477ef310dcd..5348543382bf 100644
--- a/arch/arm/mach-tegra/flowctrl.c
+++ b/arch/arm/mach-tegra/flowctrl.c
@@ -86,6 +86,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid)
86 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid; 86 reg |= TEGRA20_FLOW_CTRL_CSR_WFE_CPU0 << cpuid;
87 break; 87 break;
88 case TEGRA30: 88 case TEGRA30:
89 case TEGRA114:
89 /* clear wfe bitmap */ 90 /* clear wfe bitmap */
90 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; 91 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
91 /* clear wfi bitmap */ 92 /* clear wfi bitmap */
@@ -123,6 +124,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid)
123 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP; 124 reg &= ~TEGRA20_FLOW_CTRL_CSR_WFI_BITMAP;
124 break; 125 break;
125 case TEGRA30: 126 case TEGRA30:
127 case TEGRA114:
126 /* clear wfe bitmap */ 128 /* clear wfe bitmap */
127 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP; 129 reg &= ~TEGRA30_FLOW_CTRL_CSR_WFE_BITMAP;
128 /* clear wfi bitmap */ 130 /* clear wfi bitmap */
diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h
index 7a29bae799a7..c89aac60a143 100644
--- a/arch/arm/mach-tegra/flowctrl.h
+++ b/arch/arm/mach-tegra/flowctrl.h
@@ -28,9 +28,18 @@
28#define FLOW_CTRL_SCLK_RESUME (1 << 27) 28#define FLOW_CTRL_SCLK_RESUME (1 << 27)
29#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) 29#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10)
30#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) 30#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8)
31#define FLOW_CTRL_HALT_LIC_IRQ (1 << 11)
32#define FLOW_CTRL_HALT_LIC_FIQ (1 << 10)
33#define FLOW_CTRL_HALT_GIC_IRQ (1 << 9)
34#define FLOW_CTRL_HALT_GIC_FIQ (1 << 8)
31#define FLOW_CTRL_CPU0_CSR 0x8 35#define FLOW_CTRL_CPU0_CSR 0x8
32#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) 36#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15)
33#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) 37#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14)
38#define FLOW_CTRL_CSR_ENABLE_EXT_CRAIL (1 << 13)
39#define FLOW_CTRL_CSR_ENABLE_EXT_NCPU (1 << 12)
40#define FLOW_CTRL_CSR_ENABLE_EXT_MASK ( \
41 FLOW_CTRL_CSR_ENABLE_EXT_NCPU | \
42 FLOW_CTRL_CSR_ENABLE_EXT_CRAIL)
34#define FLOW_CTRL_CSR_ENABLE (1 << 0) 43#define FLOW_CTRL_CSR_ENABLE (1 << 0)
35#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 44#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
36#define FLOW_CTRL_CPU1_CSR 0x18 45#define FLOW_CTRL_CPU1_CSR 0x18
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 045c16f2dd51..2072e7322c39 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -6,6 +6,7 @@
6 .section ".text.head", "ax" 6 .section ".text.head", "ax"
7 7
8ENTRY(tegra_secondary_startup) 8ENTRY(tegra_secondary_startup)
9 bl v7_invalidate_l1 9 check_cpu_part_num 0xc09, r8, r9
10 bleq v7_invalidate_l1
10 b secondary_startup 11 b secondary_startup
11ENDPROC(tegra_secondary_startup) 12ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a52c10e0a857..04de2e860923 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -37,7 +37,7 @@ int tegra_cpu_kill(unsigned cpu)
37void __ref tegra_cpu_die(unsigned int cpu) 37void __ref tegra_cpu_die(unsigned int cpu)
38{ 38{
39 /* Clean L1 data cache */ 39 /* Clean L1 data cache */
40 tegra_disable_clean_inv_dcache(); 40 tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
41 41
42 /* Shut down the current CPU. */ 42 /* Shut down the current CPU. */
43 tegra_hotplug_shutdown(); 43 tegra_hotplug_shutdown();
@@ -46,17 +46,6 @@ void __ref tegra_cpu_die(unsigned int cpu)
46 BUG(); 46 BUG();
47} 47}
48 48
49int tegra_cpu_disable(unsigned int cpu)
50{
51 switch (tegra_chip_id) {
52 case TEGRA20:
53 case TEGRA30:
54 return cpu == 0 ? -EPERM : 0;
55 default:
56 return 0;
57 }
58}
59
60void __init tegra_hotplug_init(void) 49void __init tegra_hotplug_init(void)
61{ 50{
62 if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) 51 if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index 399fbca27102..3f5fa0749bde 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -24,6 +24,8 @@
24#define TEGRA_IRAM_BASE 0x40000000 24#define TEGRA_IRAM_BASE 0x40000000
25#define TEGRA_IRAM_SIZE SZ_256K 25#define TEGRA_IRAM_SIZE SZ_256K
26 26
27#define TEGRA_IRAM_CODE_AREA (TEGRA_IRAM_BASE + SZ_4K)
28
27#define TEGRA_HOST1X_BASE 0x50000000 29#define TEGRA_HOST1X_BASE 0x50000000
28#define TEGRA_HOST1X_SIZE 0x24000 30#define TEGRA_HOST1X_SIZE 0x24000
29 31
@@ -237,6 +239,12 @@
237#define TEGRA_KFUSE_BASE 0x7000FC00 239#define TEGRA_KFUSE_BASE 0x7000FC00
238#define TEGRA_KFUSE_SIZE SZ_1K 240#define TEGRA_KFUSE_SIZE SZ_1K
239 241
242#define TEGRA_EMC0_BASE 0x7001A000
243#define TEGRA_EMC0_SIZE SZ_2K
244
245#define TEGRA_EMC1_BASE 0x7001A800
246#define TEGRA_EMC1_SIZE SZ_2K
247
240#define TEGRA_CSITE_BASE 0x70040000 248#define TEGRA_CSITE_BASE 0x70040000
241#define TEGRA_CSITE_SIZE SZ_256K 249#define TEGRA_CSITE_SIZE SZ_256K
242 250
@@ -278,9 +286,6 @@
278#define IO_APB_VIRT IOMEM(0xFE300000) 286#define IO_APB_VIRT IOMEM(0xFE300000)
279#define IO_APB_SIZE SZ_1M 287#define IO_APB_SIZE SZ_1M
280 288
281#define TEGRA_PCIE_BASE 0x80000000
282#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
283
284#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 289#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
285#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 290#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
286 291
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 0de4eed1493d..1a74d562dca1 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,10 +18,12 @@
18 */ 18 */
19 19
20#include <linux/kernel.h> 20#include <linux/kernel.h>
21#include <linux/cpu_pm.h>
21#include <linux/interrupt.h> 22#include <linux/interrupt.h>
22#include <linux/irq.h> 23#include <linux/irq.h>
23#include <linux/io.h> 24#include <linux/io.h>
24#include <linux/of.h> 25#include <linux/of.h>
26#include <linux/of_address.h>
25#include <linux/irqchip/arm-gic.h> 27#include <linux/irqchip/arm-gic.h>
26#include <linux/syscore_ops.h> 28#include <linux/syscore_ops.h>
27 29
@@ -65,6 +67,7 @@ static u32 cpu_ier[TEGRA_MAX_NUM_ICTLRS];
65static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS]; 67static u32 cpu_iep[TEGRA_MAX_NUM_ICTLRS];
66 68
67static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS]; 69static u32 ictlr_wake_mask[TEGRA_MAX_NUM_ICTLRS];
70static void __iomem *tegra_gic_cpu_base;
68#endif 71#endif
69 72
70bool tegra_pending_sgi(void) 73bool tegra_pending_sgi(void)
@@ -213,8 +216,43 @@ int tegra_legacy_irq_syscore_init(void)
213 216
214 return 0; 217 return 0;
215} 218}
219
220static int tegra_gic_notifier(struct notifier_block *self,
221 unsigned long cmd, void *v)
222{
223 switch (cmd) {
224 case CPU_PM_ENTER:
225 writel_relaxed(0x1E0, tegra_gic_cpu_base + GIC_CPU_CTRL);
226 break;
227 }
228
229 return NOTIFY_OK;
230}
231
232static struct notifier_block tegra_gic_notifier_block = {
233 .notifier_call = tegra_gic_notifier,
234};
235
236static const struct of_device_id tegra114_dt_gic_match[] __initconst = {
237 { .compatible = "arm,cortex-a15-gic" },
238 { }
239};
240
241static void tegra114_gic_cpu_pm_registration(void)
242{
243 struct device_node *dn;
244
245 dn = of_find_matching_node(NULL, tegra114_dt_gic_match);
246 if (!dn)
247 return;
248
249 tegra_gic_cpu_base = of_iomap(dn, 1);
250
251 cpu_pm_register_notifier(&tegra_gic_notifier_block);
252}
216#else 253#else
217#define tegra_set_wake NULL 254#define tegra_set_wake NULL
255static void tegra114_gic_cpu_pm_registration(void) { }
218#endif 256#endif
219 257
220void __init tegra_init_irq(void) 258void __init tegra_init_irq(void)
@@ -252,4 +290,6 @@ void __init tegra_init_irq(void)
252 if (!of_have_populated_dt()) 290 if (!of_have_populated_dt())
253 gic_init(0, 29, distbase, 291 gic_init(0, 29, distbase,
254 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); 292 IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
293
294 tegra114_gic_cpu_pm_registration();
255} 295}
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
deleted file mode 100644
index 46144a19a7e7..000000000000
--- a/arch/arm/mach-tegra/pcie.c
+++ /dev/null
@@ -1,886 +0,0 @@
1/*
2 * arch/arm/mach-tegra/pci.c
3 *
4 * PCIe host controller driver for TEGRA(2) SOCs
5 *
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
8 *
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 *
12 * Bits taken from arch/arm/mach-dove/pcie.c
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/export.h>
36#include <linux/clk/tegra.h>
37#include <linux/tegra-powergate.h>
38
39#include <asm/sizes.h>
40#include <asm/mach/pci.h>
41
42#include "board.h"
43#include "iomap.h"
44
45/* Hack - need to parse this from DT */
46#define INT_PCIE_INTR 130
47
48/* register definitions */
49#define AFI_OFFSET 0x3800
50#define PADS_OFFSET 0x3000
51#define RP0_OFFSET 0x0000
52#define RP1_OFFSET 0x1000
53
54#define AFI_AXI_BAR0_SZ 0x00
55#define AFI_AXI_BAR1_SZ 0x04
56#define AFI_AXI_BAR2_SZ 0x08
57#define AFI_AXI_BAR3_SZ 0x0c
58#define AFI_AXI_BAR4_SZ 0x10
59#define AFI_AXI_BAR5_SZ 0x14
60
61#define AFI_AXI_BAR0_START 0x18
62#define AFI_AXI_BAR1_START 0x1c
63#define AFI_AXI_BAR2_START 0x20
64#define AFI_AXI_BAR3_START 0x24
65#define AFI_AXI_BAR4_START 0x28
66#define AFI_AXI_BAR5_START 0x2c
67
68#define AFI_FPCI_BAR0 0x30
69#define AFI_FPCI_BAR1 0x34
70#define AFI_FPCI_BAR2 0x38
71#define AFI_FPCI_BAR3 0x3c
72#define AFI_FPCI_BAR4 0x40
73#define AFI_FPCI_BAR5 0x44
74
75#define AFI_CACHE_BAR0_SZ 0x48
76#define AFI_CACHE_BAR0_ST 0x4c
77#define AFI_CACHE_BAR1_SZ 0x50
78#define AFI_CACHE_BAR1_ST 0x54
79
80#define AFI_MSI_BAR_SZ 0x60
81#define AFI_MSI_FPCI_BAR_ST 0x64
82#define AFI_MSI_AXI_BAR_ST 0x68
83
84#define AFI_CONFIGURATION 0xac
85#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
86
87#define AFI_FPCI_ERROR_MASKS 0xb0
88
89#define AFI_INTR_MASK 0xb4
90#define AFI_INTR_MASK_INT_MASK (1 << 0)
91#define AFI_INTR_MASK_MSI_MASK (1 << 8)
92
93#define AFI_INTR_CODE 0xb8
94#define AFI_INTR_CODE_MASK 0xf
95#define AFI_INTR_MASTER_ABORT 4
96#define AFI_INTR_LEGACY 6
97
98#define AFI_INTR_SIGNATURE 0xbc
99#define AFI_SM_INTR_ENABLE 0xc4
100
101#define AFI_AFI_INTR_ENABLE 0xc8
102#define AFI_INTR_EN_INI_SLVERR (1 << 0)
103#define AFI_INTR_EN_INI_DECERR (1 << 1)
104#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
105#define AFI_INTR_EN_TGT_DECERR (1 << 3)
106#define AFI_INTR_EN_TGT_WRERR (1 << 4)
107#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
108#define AFI_INTR_EN_AXI_DECERR (1 << 6)
109#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
110
111#define AFI_PCIE_CONFIG 0x0f8
112#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
113#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
114#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
115#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
116#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
117
118#define AFI_FUSE 0x104
119#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
120
121#define AFI_PEX0_CTRL 0x110
122#define AFI_PEX1_CTRL 0x118
123#define AFI_PEX_CTRL_RST (1 << 0)
124#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
125
126#define RP_VEND_XP 0x00000F00
127#define RP_VEND_XP_DL_UP (1 << 30)
128
129#define RP_LINK_CONTROL_STATUS 0x00000090
130#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
131
132#define PADS_CTL_SEL 0x0000009C
133
134#define PADS_CTL 0x000000A0
135#define PADS_CTL_IDDQ_1L (1 << 0)
136#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
137#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
138
139#define PADS_PLL_CTL 0x000000B8
140#define PADS_PLL_CTL_RST_B4SM (1 << 1)
141#define PADS_PLL_CTL_LOCKDET (1 << 8)
142#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
143#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
144#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
145#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
146#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
147#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
148#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
149
150/* PMC access is required for PCIE xclk (un)clamping */
151#define PMC_SCRATCH42 0x144
152#define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
153
154static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
155
156#define pmc_writel(value, reg) \
157 __raw_writel(value, reg_pmc_base + (reg))
158#define pmc_readl(reg) \
159 __raw_readl(reg_pmc_base + (reg))
160
161/*
162 * Tegra2 defines 1GB in the AXI address map for PCIe.
163 *
164 * That address space is split into different regions, with sizes and
165 * offsets as follows:
166 *
167 * 0x80000000 - 0x80003fff - PCI controller registers
168 * 0x80004000 - 0x80103fff - PCI configuration space
169 * 0x80104000 - 0x80203fff - PCI extended configuration space
170 * 0x80203fff - 0x803fffff - unused
171 * 0x80400000 - 0x8040ffff - downstream IO
172 * 0x80410000 - 0x8fffffff - unused
173 * 0x90000000 - 0x9fffffff - non-prefetchable memory
174 * 0xa0000000 - 0xbfffffff - prefetchable memory
175 */
176#define PCIE_REGS_SZ SZ_16K
177#define PCIE_CFG_OFF PCIE_REGS_SZ
178#define PCIE_CFG_SZ SZ_1M
179#define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
180#define PCIE_EXT_CFG_SZ SZ_1M
181#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
182
183#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
184#define MEM_SIZE_0 SZ_128M
185#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
186#define MEM_SIZE_1 SZ_128M
187#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
188#define PREFETCH_MEM_SIZE_0 SZ_128M
189#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
190#define PREFETCH_MEM_SIZE_1 SZ_128M
191
192#define PCIE_CONF_BUS(b) ((b) << 16)
193#define PCIE_CONF_DEV(d) ((d) << 11)
194#define PCIE_CONF_FUNC(f) ((f) << 8)
195#define PCIE_CONF_REG(r) \
196 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
197
198struct tegra_pcie_port {
199 int index;
200 u8 root_bus_nr;
201 void __iomem *base;
202
203 bool link_up;
204
205 char mem_space_name[16];
206 char prefetch_space_name[20];
207 struct resource res[2];
208};
209
210struct tegra_pcie_info {
211 struct tegra_pcie_port port[2];
212 int num_ports;
213
214 void __iomem *regs;
215 struct resource res_mmio;
216
217 struct clk *pex_clk;
218 struct clk *afi_clk;
219 struct clk *pcie_xclk;
220 struct clk *pll_e;
221};
222
223static struct tegra_pcie_info tegra_pcie;
224
225static inline void afi_writel(u32 value, unsigned long offset)
226{
227 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
228}
229
230static inline u32 afi_readl(unsigned long offset)
231{
232 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
233}
234
235static inline void pads_writel(u32 value, unsigned long offset)
236{
237 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
238}
239
240static inline u32 pads_readl(unsigned long offset)
241{
242 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
243}
244
245static struct tegra_pcie_port *bus_to_port(int bus)
246{
247 int i;
248
249 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
250 int rbus = tegra_pcie.port[i].root_bus_nr;
251 if (rbus != -1 && rbus == bus)
252 break;
253 }
254
255 return i >= 0 ? tegra_pcie.port + i : NULL;
256}
257
258static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260{
261 struct tegra_pcie_port *pp = bus_to_port(bus->number);
262 void __iomem *addr;
263
264 if (pp) {
265 if (devfn != 0) {
266 *val = 0xffffffff;
267 return PCIBIOS_DEVICE_NOT_FOUND;
268 }
269
270 addr = pp->base + (where & ~0x3);
271 } else {
272 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
273 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
274 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
275 PCIE_CONF_REG(where));
276 }
277
278 *val = readl(addr);
279
280 if (size == 1)
281 *val = (*val >> (8 * (where & 3))) & 0xff;
282 else if (size == 2)
283 *val = (*val >> (8 * (where & 3))) & 0xffff;
284
285 return PCIBIOS_SUCCESSFUL;
286}
287
288static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
290{
291 struct tegra_pcie_port *pp = bus_to_port(bus->number);
292 void __iomem *addr;
293
294 u32 mask;
295 u32 tmp;
296
297 if (pp) {
298 if (devfn != 0)
299 return PCIBIOS_DEVICE_NOT_FOUND;
300
301 addr = pp->base + (where & ~0x3);
302 } else {
303 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
304 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
305 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
306 PCIE_CONF_REG(where));
307 }
308
309 if (size == 4) {
310 writel(val, addr);
311 return PCIBIOS_SUCCESSFUL;
312 }
313
314 if (size == 2)
315 mask = ~(0xffff << ((where & 0x3) * 8));
316 else if (size == 1)
317 mask = ~(0xff << ((where & 0x3) * 8));
318 else
319 return PCIBIOS_BAD_REGISTER_NUMBER;
320
321 tmp = readl(addr) & mask;
322 tmp |= val << ((where & 0x3) * 8);
323 writel(tmp, addr);
324
325 return PCIBIOS_SUCCESSFUL;
326}
327
328static struct pci_ops tegra_pcie_ops = {
329 .read = tegra_pcie_read_conf,
330 .write = tegra_pcie_write_conf,
331};
332
333static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
334{
335 u16 reg;
336
337 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
338 pci_read_config_word(dev, PCI_COMMAND, &reg);
339 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
340 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
341 pci_write_config_word(dev, PCI_COMMAND, reg);
342 }
343}
344DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
345
346/* Tegra PCIE root complex wrongly reports device class */
347static void tegra_pcie_fixup_class(struct pci_dev *dev)
348{
349 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
350}
351DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
352DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
353
354/* Tegra PCIE requires relaxed ordering */
355static void tegra_pcie_relax_enable(struct pci_dev *dev)
356{
357 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
358}
359DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
360
361static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
362{
363 struct tegra_pcie_port *pp;
364
365 if (nr >= tegra_pcie.num_ports)
366 return 0;
367
368 pp = tegra_pcie.port + nr;
369 pp->root_bus_nr = sys->busnr;
370
371 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
372
373 /*
374 * IORESOURCE_MEM
375 */
376 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
377 "PCIe %d MEM", pp->index);
378 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
379 pp->res[0].name = pp->mem_space_name;
380 if (pp->index == 0) {
381 pp->res[0].start = MEM_BASE_0;
382 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
383 } else {
384 pp->res[0].start = MEM_BASE_1;
385 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
386 }
387 pp->res[0].flags = IORESOURCE_MEM;
388 if (request_resource(&iomem_resource, &pp->res[0]))
389 panic("Request PCIe Memory resource failed\n");
390 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
391
392 /*
393 * IORESOURCE_MEM | IORESOURCE_PREFETCH
394 */
395 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
396 "PCIe %d PREFETCH MEM", pp->index);
397 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
398 pp->res[1].name = pp->prefetch_space_name;
399 if (pp->index == 0) {
400 pp->res[1].start = PREFETCH_MEM_BASE_0;
401 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
402 } else {
403 pp->res[1].start = PREFETCH_MEM_BASE_1;
404 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
405 }
406 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
407 if (request_resource(&iomem_resource, &pp->res[1]))
408 panic("Request PCIe Prefetch Memory resource failed\n");
409 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
410
411 return 1;
412}
413
414static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
415{
416 return INT_PCIE_INTR;
417}
418
419static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
420 struct pci_sys_data *sys)
421{
422 struct tegra_pcie_port *pp;
423
424 if (nr >= tegra_pcie.num_ports)
425 return NULL;
426
427 pp = tegra_pcie.port + nr;
428 pp->root_bus_nr = sys->busnr;
429
430 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
431 &sys->resources);
432}
433
434static struct hw_pci tegra_pcie_hw __initdata = {
435 .nr_controllers = 2,
436 .setup = tegra_pcie_setup,
437 .scan = tegra_pcie_scan_bus,
438 .map_irq = tegra_pcie_map_irq,
439};
440
441
442static irqreturn_t tegra_pcie_isr(int irq, void *arg)
443{
444 const char *err_msg[] = {
445 "Unknown",
446 "AXI slave error",
447 "AXI decode error",
448 "Target abort",
449 "Master abort",
450 "Invalid write",
451 "Response decoding error",
452 "AXI response decoding error",
453 "Transcation timeout",
454 };
455
456 u32 code, signature;
457
458 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
459 signature = afi_readl(AFI_INTR_SIGNATURE);
460 afi_writel(0, AFI_INTR_CODE);
461
462 if (code == AFI_INTR_LEGACY)
463 return IRQ_NONE;
464
465 if (code >= ARRAY_SIZE(err_msg))
466 code = 0;
467
468 /*
469 * do not pollute kernel log with master abort reports since they
470 * happen a lot during enumeration
471 */
472 if (code == AFI_INTR_MASTER_ABORT)
473 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
474 else
475 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
476
477 return IRQ_HANDLED;
478}
479
480static void tegra_pcie_setup_translations(void)
481{
482 u32 fpci_bar;
483 u32 size;
484 u32 axi_address;
485
486 /* Bar 0: config Bar */
487 fpci_bar = ((u32)0xfdff << 16);
488 size = PCIE_CFG_SZ;
489 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
490 afi_writel(axi_address, AFI_AXI_BAR0_START);
491 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
492 afi_writel(fpci_bar, AFI_FPCI_BAR0);
493
494 /* Bar 1: extended config Bar */
495 fpci_bar = ((u32)0xfe1 << 20);
496 size = PCIE_EXT_CFG_SZ;
497 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
498 afi_writel(axi_address, AFI_AXI_BAR1_START);
499 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
500 afi_writel(fpci_bar, AFI_FPCI_BAR1);
501
502 /* Bar 2: downstream IO bar */
503 fpci_bar = ((__u32)0xfdfc << 16);
504 size = SZ_128K;
505 axi_address = TEGRA_PCIE_IO_BASE;
506 afi_writel(axi_address, AFI_AXI_BAR2_START);
507 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
508 afi_writel(fpci_bar, AFI_FPCI_BAR2);
509
510 /* Bar 3: prefetchable memory BAR */
511 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
512 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
513 axi_address = PREFETCH_MEM_BASE_0;
514 afi_writel(axi_address, AFI_AXI_BAR3_START);
515 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
516 afi_writel(fpci_bar, AFI_FPCI_BAR3);
517
518 /* Bar 4: non prefetchable memory BAR */
519 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
520 size = MEM_SIZE_0 + MEM_SIZE_1;
521 axi_address = MEM_BASE_0;
522 afi_writel(axi_address, AFI_AXI_BAR4_START);
523 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
524 afi_writel(fpci_bar, AFI_FPCI_BAR4);
525
526 /* Bar 5: NULL out the remaining BAR as it is not used */
527 fpci_bar = 0;
528 size = 0;
529 axi_address = 0;
530 afi_writel(axi_address, AFI_AXI_BAR5_START);
531 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
532 afi_writel(fpci_bar, AFI_FPCI_BAR5);
533
534 /* map all upstream transactions as uncached */
535 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
536 afi_writel(0, AFI_CACHE_BAR0_SZ);
537 afi_writel(0, AFI_CACHE_BAR1_ST);
538 afi_writel(0, AFI_CACHE_BAR1_SZ);
539
540 /* No MSI */
541 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
542 afi_writel(0, AFI_MSI_BAR_SZ);
543 afi_writel(0, AFI_MSI_AXI_BAR_ST);
544 afi_writel(0, AFI_MSI_BAR_SZ);
545}
546
547static int tegra_pcie_enable_controller(void)
548{
549 u32 val, reg;
550 int i, timeout;
551
552 /* Enable slot clock and pulse the reset signals */
553 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
554 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
555 afi_writel(val, reg);
556 val &= ~AFI_PEX_CTRL_RST;
557 afi_writel(val, reg);
558
559 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
560 afi_writel(val, reg);
561 }
562
563 /* Enable dual controller and both ports */
564 val = afi_readl(AFI_PCIE_CONFIG);
565 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
566 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
567 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
568 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
569 afi_writel(val, AFI_PCIE_CONFIG);
570
571 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
572 afi_writel(val, AFI_FUSE);
573
574 /* Initialze internal PHY, enable up to 16 PCIE lanes */
575 pads_writel(0x0, PADS_CTL_SEL);
576
577 /* override IDDQ to 1 on all 4 lanes */
578 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
579 pads_writel(val, PADS_CTL);
580
581 /*
582 * set up PHY PLL inputs select PLLE output as refclock,
583 * set TX ref sel to div10 (not div5)
584 */
585 val = pads_readl(PADS_PLL_CTL);
586 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
587 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
588 pads_writel(val, PADS_PLL_CTL);
589
590 /* take PLL out of reset */
591 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
592 pads_writel(val, PADS_PLL_CTL);
593
594 /*
595 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
596 * This doesn't exist in the documentation
597 */
598 pads_writel(0xfa5cfa5c, 0xc8);
599
600 /* Wait for the PLL to lock */
601 timeout = 300;
602 do {
603 val = pads_readl(PADS_PLL_CTL);
604 usleep_range(1000, 1000);
605 if (--timeout == 0) {
606 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
607 return -EBUSY;
608 }
609 } while (!(val & PADS_PLL_CTL_LOCKDET));
610
611 /* turn off IDDQ override */
612 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
613 pads_writel(val, PADS_CTL);
614
615 /* enable TX/RX data */
616 val = pads_readl(PADS_CTL);
617 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
618 pads_writel(val, PADS_CTL);
619
620 /* Take the PCIe interface module out of reset */
621 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
622
623 /* Finally enable PCIe */
624 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
625 afi_writel(val, AFI_CONFIGURATION);
626
627 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
628 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
629 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
630 afi_writel(val, AFI_AFI_INTR_ENABLE);
631 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
632
633 /* FIXME: No MSI for now, only INT */
634 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
635
636 /* Disable all execptions */
637 afi_writel(0, AFI_FPCI_ERROR_MASKS);
638
639 return 0;
640}
641
642static void tegra_pcie_xclk_clamp(bool clamp)
643{
644 u32 reg;
645
646 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
647
648 if (clamp)
649 reg |= PMC_SCRATCH42_PCX_CLAMP;
650
651 pmc_writel(reg, PMC_SCRATCH42);
652}
653
654static void tegra_pcie_power_off(void)
655{
656 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
657 tegra_periph_reset_assert(tegra_pcie.afi_clk);
658 tegra_periph_reset_assert(tegra_pcie.pex_clk);
659
660 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
661 tegra_pcie_xclk_clamp(true);
662}
663
664static int tegra_pcie_power_regate(void)
665{
666 int err;
667
668 tegra_pcie_power_off();
669
670 tegra_pcie_xclk_clamp(true);
671
672 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
673 tegra_periph_reset_assert(tegra_pcie.afi_clk);
674
675 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
676 tegra_pcie.pex_clk);
677 if (err) {
678 pr_err("PCIE: powerup sequence failed: %d\n", err);
679 return err;
680 }
681
682 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
683
684 tegra_pcie_xclk_clamp(false);
685
686 clk_prepare_enable(tegra_pcie.afi_clk);
687 clk_prepare_enable(tegra_pcie.pex_clk);
688 return clk_prepare_enable(tegra_pcie.pll_e);
689}
690
691static int tegra_pcie_clocks_get(void)
692{
693 int err;
694
695 tegra_pcie.pex_clk = clk_get(NULL, "pex");
696 if (IS_ERR(tegra_pcie.pex_clk))
697 return PTR_ERR(tegra_pcie.pex_clk);
698
699 tegra_pcie.afi_clk = clk_get(NULL, "afi");
700 if (IS_ERR(tegra_pcie.afi_clk)) {
701 err = PTR_ERR(tegra_pcie.afi_clk);
702 goto err_afi_clk;
703 }
704
705 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
706 if (IS_ERR(tegra_pcie.pcie_xclk)) {
707 err = PTR_ERR(tegra_pcie.pcie_xclk);
708 goto err_pcie_xclk;
709 }
710
711 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
712 if (IS_ERR(tegra_pcie.pll_e)) {
713 err = PTR_ERR(tegra_pcie.pll_e);
714 goto err_pll_e;
715 }
716
717 return 0;
718
719err_pll_e:
720 clk_put(tegra_pcie.pcie_xclk);
721err_pcie_xclk:
722 clk_put(tegra_pcie.afi_clk);
723err_afi_clk:
724 clk_put(tegra_pcie.pex_clk);
725
726 return err;
727}
728
729static void tegra_pcie_clocks_put(void)
730{
731 clk_put(tegra_pcie.pll_e);
732 clk_put(tegra_pcie.pcie_xclk);
733 clk_put(tegra_pcie.afi_clk);
734 clk_put(tegra_pcie.pex_clk);
735}
736
737static int __init tegra_pcie_get_resources(void)
738{
739 int err;
740
741 err = tegra_pcie_clocks_get();
742 if (err) {
743 pr_err("PCIE: failed to get clocks: %d\n", err);
744 return err;
745 }
746
747 err = tegra_pcie_power_regate();
748 if (err) {
749 pr_err("PCIE: failed to power up: %d\n", err);
750 goto err_pwr_on;
751 }
752
753 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
754 if (tegra_pcie.regs == NULL) {
755 pr_err("PCIE: Failed to map PCI/AFI registers\n");
756 err = -ENOMEM;
757 goto err_map_reg;
758 }
759
760 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
761 IRQF_SHARED, "PCIE", &tegra_pcie);
762 if (err) {
763 pr_err("PCIE: Failed to register IRQ: %d\n", err);
764 goto err_req_io;
765 }
766 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
767
768 return 0;
769
770err_req_io:
771 iounmap(tegra_pcie.regs);
772err_map_reg:
773 tegra_pcie_power_off();
774err_pwr_on:
775 tegra_pcie_clocks_put();
776
777 return err;
778}
779
780/*
781 * FIXME: If there are no PCIe cards attached, then calling this function
782 * can result in the increase of the bootup time as there are big timeout
783 * loops.
784 */
785#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
786static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
787 u32 reset_reg)
788{
789 u32 reg;
790 int retries = 3;
791 int timeout;
792
793 do {
794 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
795 while (timeout) {
796 reg = readl(pp->base + RP_VEND_XP);
797
798 if (reg & RP_VEND_XP_DL_UP)
799 break;
800
801 mdelay(1);
802 timeout--;
803 }
804
805 if (!timeout) {
806 pr_err("PCIE: port %d: link down, retrying\n", idx);
807 goto retry;
808 }
809
810 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
811 while (timeout) {
812 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
813
814 if (reg & 0x20000000)
815 return true;
816
817 mdelay(1);
818 timeout--;
819 }
820
821retry:
822 /* Pulse the PEX reset */
823 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
824 afi_writel(reg, reset_reg);
825 mdelay(1);
826 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
827 afi_writel(reg, reset_reg);
828
829 retries--;
830 } while (retries);
831
832 return false;
833}
834
835static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
836{
837 struct tegra_pcie_port *pp;
838
839 pp = tegra_pcie.port + tegra_pcie.num_ports;
840
841 pp->index = -1;
842 pp->base = tegra_pcie.regs + offset;
843 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
844
845 if (!pp->link_up) {
846 pp->base = NULL;
847 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
848 return;
849 }
850
851 tegra_pcie.num_ports++;
852 pp->index = index;
853 pp->root_bus_nr = -1;
854 memset(pp->res, 0, sizeof(pp->res));
855}
856
857int __init tegra_pcie_init(bool init_port0, bool init_port1)
858{
859 int err;
860
861 if (!(init_port0 || init_port1))
862 return -ENODEV;
863
864 pcibios_min_mem = 0;
865
866 err = tegra_pcie_get_resources();
867 if (err)
868 return err;
869
870 err = tegra_pcie_enable_controller();
871 if (err)
872 return err;
873
874 /* setup the AFI address translations */
875 tegra_pcie_setup_translations();
876
877 if (init_port0)
878 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
879
880 if (init_port1)
881 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
882
883 pci_common_init(&tegra_pcie_hw);
884
885 return 0;
886}
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 97b33a2a2d75..2d0203627fbb 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -196,6 +196,5 @@ struct smp_operations tegra_smp_ops __initdata = {
196#ifdef CONFIG_HOTPLUG_CPU 196#ifdef CONFIG_HOTPLUG_CPU
197 .cpu_kill = tegra_cpu_kill, 197 .cpu_kill = tegra_cpu_kill,
198 .cpu_die = tegra_cpu_die, 198 .cpu_die = tegra_cpu_die,
199 .cpu_disable = tegra_cpu_disable,
200#endif 199#endif
201}; 200};
diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c
new file mode 100644
index 000000000000..d65e1d786400
--- /dev/null
+++ b/arch/arm/mach-tegra/pm-tegra20.c
@@ -0,0 +1,34 @@
1/*
2 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/kernel.h>
17
18#include "pm.h"
19
20#ifdef CONFIG_PM_SLEEP
21extern u32 tegra20_iram_start, tegra20_iram_end;
22extern void tegra20_sleep_core_finish(unsigned long);
23
24void tegra20_lp1_iram_hook(void)
25{
26 tegra_lp1_iram.start_addr = &tegra20_iram_start;
27 tegra_lp1_iram.end_addr = &tegra20_iram_end;
28}
29
30void tegra20_sleep_core_init(void)
31{
32 tegra_sleep_core_finish = tegra20_sleep_core_finish;
33}
34#endif
diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c
new file mode 100644
index 000000000000..8fa326d6ff1a
--- /dev/null
+++ b/arch/arm/mach-tegra/pm-tegra30.c
@@ -0,0 +1,34 @@
1/*
2 * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/kernel.h>
17
18#include "pm.h"
19
20#ifdef CONFIG_PM_SLEEP
21extern u32 tegra30_iram_start, tegra30_iram_end;
22extern void tegra30_sleep_core_finish(unsigned long);
23
24void tegra30_lp1_iram_hook(void)
25{
26 tegra_lp1_iram.start_addr = &tegra30_iram_start;
27 tegra_lp1_iram.end_addr = &tegra30_iram_end;
28}
29
30void tegra30_sleep_core_init(void)
31{
32 tegra_sleep_core_finish = tegra30_sleep_core_finish;
33}
34#endif
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 261fec140c06..ed294a04e1d3 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -37,12 +37,18 @@
37#include "reset.h" 37#include "reset.h"
38#include "flowctrl.h" 38#include "flowctrl.h"
39#include "fuse.h" 39#include "fuse.h"
40#include "pm.h"
40#include "pmc.h" 41#include "pmc.h"
41#include "sleep.h" 42#include "sleep.h"
42 43
43#ifdef CONFIG_PM_SLEEP 44#ifdef CONFIG_PM_SLEEP
44static DEFINE_SPINLOCK(tegra_lp2_lock); 45static DEFINE_SPINLOCK(tegra_lp2_lock);
46static u32 iram_save_size;
47static void *iram_save_addr;
48struct tegra_lp1_iram tegra_lp1_iram;
45void (*tegra_tear_down_cpu)(void); 49void (*tegra_tear_down_cpu)(void);
50void (*tegra_sleep_core_finish)(unsigned long v2p);
51static int (*tegra_sleep_func)(unsigned long v2p);
46 52
47static void tegra_tear_down_cpu_init(void) 53static void tegra_tear_down_cpu_init(void)
48{ 54{
@@ -52,7 +58,9 @@ static void tegra_tear_down_cpu_init(void)
52 tegra_tear_down_cpu = tegra20_tear_down_cpu; 58 tegra_tear_down_cpu = tegra20_tear_down_cpu;
53 break; 59 break;
54 case TEGRA30: 60 case TEGRA30:
55 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC)) 61 case TEGRA114:
62 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
63 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
56 tegra_tear_down_cpu = tegra30_tear_down_cpu; 64 tegra_tear_down_cpu = tegra30_tear_down_cpu;
57 break; 65 break;
58 } 66 }
@@ -171,19 +179,109 @@ void tegra_idle_lp2_last(void)
171enum tegra_suspend_mode tegra_pm_validate_suspend_mode( 179enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
172 enum tegra_suspend_mode mode) 180 enum tegra_suspend_mode mode)
173{ 181{
174 /* Tegra114 didn't support any suspending mode yet. */
175 if (tegra_chip_id == TEGRA114)
176 return TEGRA_SUSPEND_NONE;
177
178 /* 182 /*
179 * The Tegra devices only support suspending to LP2 currently. 183 * The Tegra devices support suspending to LP1 or lower currently.
180 */ 184 */
181 if (mode > TEGRA_SUSPEND_LP2) 185 if (mode > TEGRA_SUSPEND_LP1)
182 return TEGRA_SUSPEND_LP2; 186 return TEGRA_SUSPEND_LP1;
183 187
184 return mode; 188 return mode;
185} 189}
186 190
191static int tegra_sleep_core(unsigned long v2p)
192{
193 setup_mm_for_reboot();
194 tegra_sleep_core_finish(v2p);
195
196 /* should never here */
197 BUG();
198
199 return 0;
200}
201
202/*
203 * tegra_lp1_iram_hook
204 *
205 * Hooking the address of LP1 reset vector and SDRAM self-refresh code in
206 * SDRAM. These codes not be copied to IRAM in this fuction. We need to
207 * copy these code to IRAM before LP0/LP1 suspend and restore the content
208 * of IRAM after resume.
209 */
210static bool tegra_lp1_iram_hook(void)
211{
212 switch (tegra_chip_id) {
213 case TEGRA20:
214 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
215 tegra20_lp1_iram_hook();
216 break;
217 case TEGRA30:
218 case TEGRA114:
219 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
220 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
221 tegra30_lp1_iram_hook();
222 break;
223 default:
224 break;
225 }
226
227 if (!tegra_lp1_iram.start_addr || !tegra_lp1_iram.end_addr)
228 return false;
229
230 iram_save_size = tegra_lp1_iram.end_addr - tegra_lp1_iram.start_addr;
231 iram_save_addr = kmalloc(iram_save_size, GFP_KERNEL);
232 if (!iram_save_addr)
233 return false;
234
235 return true;
236}
237
238static bool tegra_sleep_core_init(void)
239{
240 switch (tegra_chip_id) {
241 case TEGRA20:
242 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
243 tegra20_sleep_core_init();
244 break;
245 case TEGRA30:
246 case TEGRA114:
247 if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) ||
248 IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC))
249 tegra30_sleep_core_init();
250 break;
251 default:
252 break;
253 }
254
255 if (!tegra_sleep_core_finish)
256 return false;
257
258 return true;
259}
260
261static void tegra_suspend_enter_lp1(void)
262{
263 tegra_pmc_suspend();
264
265 /* copy the reset vector & SDRAM shutdown code into IRAM */
266 memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_CODE_AREA),
267 iram_save_size);
268 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), tegra_lp1_iram.start_addr,
269 iram_save_size);
270
271 *((u32 *)tegra_cpu_lp1_mask) = 1;
272}
273
274static void tegra_suspend_exit_lp1(void)
275{
276 tegra_pmc_resume();
277
278 /* restore IRAM */
279 memcpy(IO_ADDRESS(TEGRA_IRAM_CODE_AREA), iram_save_addr,
280 iram_save_size);
281
282 *(u32 *)tegra_cpu_lp1_mask = 0;
283}
284
187static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = { 285static const char *lp_state[TEGRA_MAX_SUSPEND_MODE] = {
188 [TEGRA_SUSPEND_NONE] = "none", 286 [TEGRA_SUSPEND_NONE] = "none",
189 [TEGRA_SUSPEND_LP2] = "LP2", 287 [TEGRA_SUSPEND_LP2] = "LP2",
@@ -207,6 +305,9 @@ static int tegra_suspend_enter(suspend_state_t state)
207 305
208 suspend_cpu_complex(); 306 suspend_cpu_complex();
209 switch (mode) { 307 switch (mode) {
308 case TEGRA_SUSPEND_LP1:
309 tegra_suspend_enter_lp1();
310 break;
210 case TEGRA_SUSPEND_LP2: 311 case TEGRA_SUSPEND_LP2:
211 tegra_set_cpu_in_lp2(); 312 tegra_set_cpu_in_lp2();
212 break; 313 break;
@@ -214,9 +315,12 @@ static int tegra_suspend_enter(suspend_state_t state)
214 break; 315 break;
215 } 316 }
216 317
217 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu); 318 cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, tegra_sleep_func);
218 319
219 switch (mode) { 320 switch (mode) {
321 case TEGRA_SUSPEND_LP1:
322 tegra_suspend_exit_lp1();
323 break;
220 case TEGRA_SUSPEND_LP2: 324 case TEGRA_SUSPEND_LP2:
221 tegra_clear_cpu_in_lp2(); 325 tegra_clear_cpu_in_lp2();
222 break; 326 break;
@@ -237,12 +341,36 @@ static const struct platform_suspend_ops tegra_suspend_ops = {
237 341
238void __init tegra_init_suspend(void) 342void __init tegra_init_suspend(void)
239{ 343{
240 if (tegra_pmc_get_suspend_mode() == TEGRA_SUSPEND_NONE) 344 enum tegra_suspend_mode mode = tegra_pmc_get_suspend_mode();
345
346 if (mode == TEGRA_SUSPEND_NONE)
241 return; 347 return;
242 348
243 tegra_tear_down_cpu_init(); 349 tegra_tear_down_cpu_init();
244 tegra_pmc_suspend_init(); 350 tegra_pmc_suspend_init();
245 351
352 if (mode >= TEGRA_SUSPEND_LP1) {
353 if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) {
354 pr_err("%s: unable to allocate memory for SDRAM"
355 "self-refresh -- LP0/LP1 unavailable\n",
356 __func__);
357 tegra_pmc_set_suspend_mode(TEGRA_SUSPEND_LP2);
358 mode = TEGRA_SUSPEND_LP2;
359 }
360 }
361
362 /* set up sleep function for cpu_suspend */
363 switch (mode) {
364 case TEGRA_SUSPEND_LP1:
365 tegra_sleep_func = tegra_sleep_core;
366 break;
367 case TEGRA_SUSPEND_LP2:
368 tegra_sleep_func = tegra_sleep_cpu;
369 break;
370 default:
371 break;
372 }
373
246 suspend_set_ops(&tegra_suspend_ops); 374 suspend_set_ops(&tegra_suspend_ops);
247} 375}
248#endif 376#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 94c4b9d9077c..fe204e5256e7 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -23,6 +23,18 @@
23 23
24#include "pmc.h" 24#include "pmc.h"
25 25
26struct tegra_lp1_iram {
27 void *start_addr;
28 void *end_addr;
29};
30extern struct tegra_lp1_iram tegra_lp1_iram;
31extern void (*tegra_sleep_core_finish)(unsigned long v2p);
32
33void tegra20_lp1_iram_hook(void);
34void tegra20_sleep_core_init(void);
35void tegra30_lp1_iram_hook(void);
36void tegra30_sleep_core_init(void);
37
26extern unsigned long l2x0_saved_regs_addr; 38extern unsigned long l2x0_saved_regs_addr;
27 39
28void save_cpu_arch_register(void); 40void save_cpu_arch_register(void);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index eb3fa4aee0e4..8acb881f7cfe 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -21,11 +21,14 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_address.h> 22#include <linux/of_address.h>
23 23
24#include "flowctrl.h"
24#include "fuse.h" 25#include "fuse.h"
25#include "pm.h" 26#include "pm.h"
26#include "pmc.h" 27#include "pmc.h"
27#include "sleep.h" 28#include "sleep.h"
28 29
30#define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
31#define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */
29#define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ 32#define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
30#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ 33#define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
31#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ 34#define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
@@ -193,16 +196,50 @@ enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
193 return pmc_pm_data.suspend_mode; 196 return pmc_pm_data.suspend_mode;
194} 197}
195 198
199void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
200{
201 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
202 return;
203
204 pmc_pm_data.suspend_mode = mode;
205}
206
207void tegra_pmc_suspend(void)
208{
209 tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41);
210}
211
212void tegra_pmc_resume(void)
213{
214 tegra_pmc_writel(0x0, PMC_SCRATCH41);
215}
216
196void tegra_pmc_pm_set(enum tegra_suspend_mode mode) 217void tegra_pmc_pm_set(enum tegra_suspend_mode mode)
197{ 218{
198 u32 reg; 219 u32 reg, csr_reg;
199 unsigned long rate = 0; 220 unsigned long rate = 0;
200 221
201 reg = tegra_pmc_readl(PMC_CTRL); 222 reg = tegra_pmc_readl(PMC_CTRL);
202 reg |= TEGRA_POWER_CPU_PWRREQ_OE; 223 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
203 reg &= ~TEGRA_POWER_EFFECT_LP0; 224 reg &= ~TEGRA_POWER_EFFECT_LP0;
204 225
226 switch (tegra_chip_id) {
227 case TEGRA20:
228 case TEGRA30:
229 break;
230 default:
231 /* Turn off CRAIL */
232 csr_reg = flowctrl_read_cpu_csr(0);
233 csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK;
234 csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL;
235 flowctrl_write_cpu_csr(0, csr_reg);
236 break;
237 }
238
205 switch (mode) { 239 switch (mode) {
240 case TEGRA_SUSPEND_LP1:
241 rate = 32768;
242 break;
206 case TEGRA_SUSPEND_LP2: 243 case TEGRA_SUSPEND_LP2:
207 rate = clk_get_rate(tegra_pclk); 244 rate = clk_get_rate(tegra_pclk);
208 break; 245 break;
@@ -224,6 +261,20 @@ void tegra_pmc_suspend_init(void)
224 reg = tegra_pmc_readl(PMC_CTRL); 261 reg = tegra_pmc_readl(PMC_CTRL);
225 reg |= TEGRA_POWER_CPU_PWRREQ_OE; 262 reg |= TEGRA_POWER_CPU_PWRREQ_OE;
226 tegra_pmc_writel(reg, PMC_CTRL); 263 tegra_pmc_writel(reg, PMC_CTRL);
264
265 reg = tegra_pmc_readl(PMC_CTRL);
266
267 if (!pmc_pm_data.sysclkreq_high)
268 reg |= TEGRA_POWER_SYSCLK_POLARITY;
269 else
270 reg &= ~TEGRA_POWER_SYSCLK_POLARITY;
271
272 /* configure the output polarity while the request is tristated */
273 tegra_pmc_writel(reg, PMC_CTRL);
274
275 /* now enable the request */
276 reg |= TEGRA_POWER_SYSCLK_OE;
277 tegra_pmc_writel(reg, PMC_CTRL);
227} 278}
228#endif 279#endif
229 280
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index e1c2df272f7d..549f8c7b762c 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -28,6 +28,9 @@ enum tegra_suspend_mode {
28 28
29#ifdef CONFIG_PM_SLEEP 29#ifdef CONFIG_PM_SLEEP
30enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); 30enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
31void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
32void tegra_pmc_suspend(void);
33void tegra_pmc_resume(void);
31void tegra_pmc_pm_set(enum tegra_suspend_mode mode); 34void tegra_pmc_pm_set(enum tegra_suspend_mode mode);
32void tegra_pmc_suspend_init(void); 35void tegra_pmc_suspend_init(void);
33#endif 36#endif
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 39dc9e7834f3..f527b2c2dea7 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -40,9 +40,12 @@
40 * re-enabling sdram. 40 * re-enabling sdram.
41 * 41 *
42 * r6: SoC ID 42 * r6: SoC ID
43 * r8: CPU part number
43 */ 44 */
44ENTRY(tegra_resume) 45ENTRY(tegra_resume)
45 bl v7_invalidate_l1 46 check_cpu_part_num 0xc09, r8, r9
47 bleq v7_invalidate_l1
48 blne tegra_init_l2_for_a15
46 49
47 cpu_id r0 50 cpu_id r0
48 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 51 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6
@@ -70,7 +73,8 @@ no_cpu0_chk:
70 str r1, [r2] 73 str r1, [r2]
711: 741:
72 75
73 check_cpu_part_num 0xc09, r8, r9 76 mov32 r9, 0xc09
77 cmp r8, r9
74 bne not_ca9 78 bne not_ca9
75#ifdef CONFIG_HAVE_ARM_SCU 79#ifdef CONFIG_HAVE_ARM_SCU
76 /* enable SCU */ 80 /* enable SCU */
@@ -178,6 +182,19 @@ after_errata:
1781: 1821:
179#endif 183#endif
180 184
185 /* Waking up from LP1? */
186 ldr r8, [r12, #RESET_DATA(MASK_LP1)]
187 tst r8, r11 @ if in_lp1
188 beq __is_not_lp1
189 cmp r10, #0
190 bne __die @ only CPU0 can be here
191 ldr lr, [r12, #RESET_DATA(STARTUP_LP1)]
192 cmp lr, #0
193 bleq __die @ no LP1 startup handler
194 THUMB( add lr, lr, #1 ) @ switch to Thumb mode
195 bx lr
196__is_not_lp1:
197
181 /* Waking up from LP2? */ 198 /* Waking up from LP2? */
182 ldr r9, [r12, #RESET_DATA(MASK_LP2)] 199 ldr r9, [r12, #RESET_DATA(MASK_LP2)]
183 tst r9, r11 @ if in_lp2 200 tst r9, r11 @ if in_lp2
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c
index 1ac434e0068f..fd0bbf8a6c94 100644
--- a/arch/arm/mach-tegra/reset.c
+++ b/arch/arm/mach-tegra/reset.c
@@ -81,6 +81,8 @@ void __init tegra_cpu_reset_handler_init(void)
81#endif 81#endif
82 82
83#ifdef CONFIG_PM_SLEEP 83#ifdef CONFIG_PM_SLEEP
84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP1] =
85 TEGRA_IRAM_CODE_AREA;
84 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] = 86 __tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_LP2] =
85 virt_to_phys((void *)tegra_resume); 87 virt_to_phys((void *)tegra_resume);
86#endif 88#endif
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index c90d8e9c4ad2..76a93434c6ee 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -39,6 +39,10 @@ void __tegra_cpu_reset_handler_end(void);
39void tegra_secondary_startup(void); 39void tegra_secondary_startup(void);
40 40
41#ifdef CONFIG_PM_SLEEP 41#ifdef CONFIG_PM_SLEEP
42#define tegra_cpu_lp1_mask \
43 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
44 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP1] - \
45 (u32)__tegra_cpu_reset_handler_start)))
42#define tegra_cpu_lp2_mask \ 46#define tegra_cpu_lp2_mask \
43 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \ 47 (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
44 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \ 48 ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index e3f2417c420e..5c3bd11c9838 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -23,10 +23,49 @@
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <asm/proc-fns.h> 24#include <asm/proc-fns.h>
25#include <asm/cp15.h> 25#include <asm/cp15.h>
26#include <asm/cache.h>
26 27
27#include "sleep.h" 28#include "sleep.h"
28#include "flowctrl.h" 29#include "flowctrl.h"
29 30
31#define EMC_CFG 0xc
32#define EMC_ADR_CFG 0x10
33#define EMC_REFRESH 0x70
34#define EMC_NOP 0xdc
35#define EMC_SELF_REF 0xe0
36#define EMC_REQ_CTRL 0x2b0
37#define EMC_EMC_STATUS 0x2b4
38
39#define CLK_RESET_CCLK_BURST 0x20
40#define CLK_RESET_CCLK_DIVIDER 0x24
41#define CLK_RESET_SCLK_BURST 0x28
42#define CLK_RESET_SCLK_DIVIDER 0x2c
43#define CLK_RESET_PLLC_BASE 0x80
44#define CLK_RESET_PLLM_BASE 0x90
45#define CLK_RESET_PLLP_BASE 0xa0
46
47#define APB_MISC_XM2CFGCPADCTRL 0x8c8
48#define APB_MISC_XM2CFGDPADCTRL 0x8cc
49#define APB_MISC_XM2CLKCFGPADCTRL 0x8d0
50#define APB_MISC_XM2COMPPADCTRL 0x8d4
51#define APB_MISC_XM2VTTGENPADCTRL 0x8d8
52#define APB_MISC_XM2CFGCPADCTRL2 0x8e4
53#define APB_MISC_XM2CFGDPADCTRL2 0x8e8
54
55.macro pll_enable, rd, r_car_base, pll_base
56 ldr \rd, [\r_car_base, #\pll_base]
57 tst \rd, #(1 << 30)
58 orreq \rd, \rd, #(1 << 30)
59 streq \rd, [\r_car_base, #\pll_base]
60.endm
61
62.macro emc_device_mask, rd, base
63 ldr \rd, [\base, #EMC_ADR_CFG]
64 tst \rd, #(0x3 << 24)
65 moveq \rd, #(0x1 << 8) @ just 1 device
66 movne \rd, #(0x3 << 8) @ 2 devices
67.endm
68
30#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 69#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
31/* 70/*
32 * tegra20_hotplug_shutdown(void) 71 * tegra20_hotplug_shutdown(void)
@@ -181,6 +220,28 @@ ENTRY(tegra20_cpu_is_resettable_soon)
181ENDPROC(tegra20_cpu_is_resettable_soon) 220ENDPROC(tegra20_cpu_is_resettable_soon)
182 221
183/* 222/*
223 * tegra20_sleep_core_finish(unsigned long v2p)
224 *
225 * Enters suspend in LP0 or LP1 by turning off the mmu and jumping to
226 * tegra20_tear_down_core in IRAM
227 */
228ENTRY(tegra20_sleep_core_finish)
229 /* Flush, disable the L1 data cache and exit SMP */
230 bl tegra_disable_clean_inv_dcache
231
232 mov32 r3, tegra_shut_off_mmu
233 add r3, r3, r0
234
235 mov32 r0, tegra20_tear_down_core
236 mov32 r1, tegra20_iram_start
237 sub r0, r0, r1
238 mov32 r1, TEGRA_IRAM_CODE_AREA
239 add r0, r0, r1
240
241 mov pc, r3
242ENDPROC(tegra20_sleep_core_finish)
243
244/*
184 * tegra20_sleep_cpu_secondary_finish(unsigned long v2p) 245 * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
185 * 246 *
186 * Enters WFI on secondary CPU by exiting coherency. 247 * Enters WFI on secondary CPU by exiting coherency.
@@ -191,6 +252,7 @@ ENTRY(tegra20_sleep_cpu_secondary_finish)
191 mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency 252 mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
192 253
193 /* Flush and disable the L1 data cache */ 254 /* Flush and disable the L1 data cache */
255 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
194 bl tegra_disable_clean_inv_dcache 256 bl tegra_disable_clean_inv_dcache
195 257
196 mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41 258 mov32 r0, TEGRA_PMC_VIRT + PMC_SCRATCH41
@@ -250,6 +312,150 @@ ENTRY(tegra20_tear_down_cpu)
250 b tegra20_enter_sleep 312 b tegra20_enter_sleep
251ENDPROC(tegra20_tear_down_cpu) 313ENDPROC(tegra20_tear_down_cpu)
252 314
315/* START OF ROUTINES COPIED TO IRAM */
316 .align L1_CACHE_SHIFT
317 .globl tegra20_iram_start
318tegra20_iram_start:
319
320/*
321 * tegra20_lp1_reset
322 *
323 * reset vector for LP1 restore; copied into IRAM during suspend.
324 * Brings the system back up to a safe staring point (SDRAM out of
325 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLP,
326 * system clock running on the same PLL that it suspended at), and
327 * jumps to tegra_resume to restore virtual addressing and PLLX.
328 * The physical address of tegra_resume expected to be stored in
329 * PMC_SCRATCH41.
330 *
331 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
332 */
333ENTRY(tegra20_lp1_reset)
334 /*
335 * The CPU and system bus are running at 32KHz and executing from
336 * IRAM when this code is executed; immediately switch to CLKM and
337 * enable PLLM, PLLP, PLLC.
338 */
339 mov32 r0, TEGRA_CLK_RESET_BASE
340
341 mov r1, #(1 << 28)
342 str r1, [r0, #CLK_RESET_SCLK_BURST]
343 str r1, [r0, #CLK_RESET_CCLK_BURST]
344 mov r1, #0
345 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
346 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
347
348 pll_enable r1, r0, CLK_RESET_PLLM_BASE
349 pll_enable r1, r0, CLK_RESET_PLLP_BASE
350 pll_enable r1, r0, CLK_RESET_PLLC_BASE
351
352 adr r2, tegra20_sdram_pad_address
353 adr r4, tegra20_sdram_pad_save
354 mov r5, #0
355
356 ldr r6, tegra20_sdram_pad_size
357padload:
358 ldr r7, [r2, r5] @ r7 is the addr in the pad_address
359
360 ldr r1, [r4, r5]
361 str r1, [r7] @ restore the value in pad_save
362
363 add r5, r5, #4
364 cmp r6, r5
365 bne padload
366
367padload_done:
368 /* 255uS delay for PLL stabilization */
369 mov32 r7, TEGRA_TMRUS_BASE
370 ldr r1, [r7]
371 add r1, r1, #0xff
372 wait_until r1, r7, r9
373
374 adr r4, tegra20_sclk_save
375 ldr r4, [r4]
376 str r4, [r0, #CLK_RESET_SCLK_BURST]
377 mov32 r4, ((1 << 28) | (4)) @ burst policy is PLLP
378 str r4, [r0, #CLK_RESET_CCLK_BURST]
379
380 mov32 r0, TEGRA_EMC_BASE
381 ldr r1, [r0, #EMC_CFG]
382 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP
383 str r1, [r0, #EMC_CFG]
384
385 mov r1, #0
386 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
387 mov r1, #1
388 str r1, [r0, #EMC_NOP]
389 str r1, [r0, #EMC_NOP]
390 str r1, [r0, #EMC_REFRESH]
391
392 emc_device_mask r1, r0
393
394exit_selfrefresh_loop:
395 ldr r2, [r0, #EMC_EMC_STATUS]
396 ands r2, r2, r1
397 bne exit_selfrefresh_loop
398
399 mov r1, #0 @ unstall all transactions
400 str r1, [r0, #EMC_REQ_CTRL]
401
402 mov32 r0, TEGRA_PMC_BASE
403 ldr r0, [r0, #PMC_SCRATCH41]
404 mov pc, r0 @ jump to tegra_resume
405ENDPROC(tegra20_lp1_reset)
406
407/*
408 * tegra20_tear_down_core
409 *
410 * copied into and executed from IRAM
411 * puts memory in self-refresh for LP0 and LP1
412 */
413tegra20_tear_down_core:
414 bl tegra20_sdram_self_refresh
415 bl tegra20_switch_cpu_to_clk32k
416 b tegra20_enter_sleep
417
418/*
419 * tegra20_switch_cpu_to_clk32k
420 *
421 * In LP0 and LP1 all PLLs will be turned off. Switch the CPU and system clock
422 * to the 32KHz clock.
423 */
424tegra20_switch_cpu_to_clk32k:
425 /*
426 * start by switching to CLKM to safely disable PLLs, then switch to
427 * CLKS.
428 */
429 mov r0, #(1 << 28)
430 str r0, [r5, #CLK_RESET_SCLK_BURST]
431 str r0, [r5, #CLK_RESET_CCLK_BURST]
432 mov r0, #0
433 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
434 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
435
436 /* 2uS delay delay between changing SCLK and disabling PLLs */
437 mov32 r7, TEGRA_TMRUS_BASE
438 ldr r1, [r7]
439 add r1, r1, #2
440 wait_until r1, r7, r9
441
442 /* disable PLLM, PLLP and PLLC */
443 ldr r0, [r5, #CLK_RESET_PLLM_BASE]
444 bic r0, r0, #(1 << 30)
445 str r0, [r5, #CLK_RESET_PLLM_BASE]
446 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
447 bic r0, r0, #(1 << 30)
448 str r0, [r5, #CLK_RESET_PLLP_BASE]
449 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
450 bic r0, r0, #(1 << 30)
451 str r0, [r5, #CLK_RESET_PLLC_BASE]
452
453 /* switch to CLKS */
454 mov r0, #0 /* brust policy = 32KHz */
455 str r0, [r5, #CLK_RESET_SCLK_BURST]
456
457 mov pc, lr
458
253/* 459/*
254 * tegra20_enter_sleep 460 * tegra20_enter_sleep
255 * 461 *
@@ -274,4 +480,95 @@ halted:
274 isb 480 isb
275 b halted 481 b halted
276 482
483/*
484 * tegra20_sdram_self_refresh
485 *
486 * called with MMU off and caches disabled
487 * puts sdram in self refresh
488 * must be executed from IRAM
489 */
490tegra20_sdram_self_refresh:
491 mov32 r1, TEGRA_EMC_BASE @ r1 reserved for emc base addr
492
493 mov r2, #3
494 str r2, [r1, #EMC_REQ_CTRL] @ stall incoming DRAM requests
495
496emcidle:
497 ldr r2, [r1, #EMC_EMC_STATUS]
498 tst r2, #4
499 beq emcidle
500
501 mov r2, #1
502 str r2, [r1, #EMC_SELF_REF]
503
504 emc_device_mask r2, r1
505
506emcself:
507 ldr r3, [r1, #EMC_EMC_STATUS]
508 and r3, r3, r2
509 cmp r3, r2
510 bne emcself @ loop until DDR in self-refresh
511
512 adr r2, tegra20_sdram_pad_address
513 adr r3, tegra20_sdram_pad_safe
514 adr r4, tegra20_sdram_pad_save
515 mov r5, #0
516
517 ldr r6, tegra20_sdram_pad_size
518padsave:
519 ldr r0, [r2, r5] @ r0 is the addr in the pad_address
520
521 ldr r1, [r0]
522 str r1, [r4, r5] @ save the content of the addr
523
524 ldr r1, [r3, r5]
525 str r1, [r0] @ set the save val to the addr
526
527 add r5, r5, #4
528 cmp r6, r5
529 bne padsave
530padsave_done:
531
532 mov32 r5, TEGRA_CLK_RESET_BASE
533 ldr r0, [r5, #CLK_RESET_SCLK_BURST]
534 adr r2, tegra20_sclk_save
535 str r0, [r2]
536 dsb
537 mov pc, lr
538
539tegra20_sdram_pad_address:
540 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL
541 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL
542 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CLKCFGPADCTRL
543 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2COMPPADCTRL
544 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2VTTGENPADCTRL
545 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGCPADCTRL2
546 .word TEGRA_APB_MISC_BASE + APB_MISC_XM2CFGDPADCTRL2
547
548tegra20_sdram_pad_size:
549 .word tegra20_sdram_pad_size - tegra20_sdram_pad_address
550
551tegra20_sdram_pad_safe:
552 .word 0x8
553 .word 0x8
554 .word 0x0
555 .word 0x8
556 .word 0x5500
557 .word 0x08080040
558 .word 0x0
559
560tegra20_sclk_save:
561 .word 0x0
562
563tegra20_sdram_pad_save:
564 .rept (tegra20_sdram_pad_size - tegra20_sdram_pad_address) / 4
565 .long 0
566 .endr
567
568 .ltorg
569/* dummy symbol for end of IRAM */
570 .align L1_CACHE_SHIFT
571 .globl tegra20_iram_end
572tegra20_iram_end:
573 b .
277#endif 574#endif
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index ada8821b48be..63fa91b5fafb 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -18,13 +18,118 @@
18 18
19#include <asm/assembler.h> 19#include <asm/assembler.h>
20#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
21#include <asm/cache.h>
21 22
22#include "fuse.h" 23#include "fuse.h"
23#include "sleep.h" 24#include "sleep.h"
24#include "flowctrl.h" 25#include "flowctrl.h"
25 26
27#define EMC_CFG 0xc
28#define EMC_ADR_CFG 0x10
29#define EMC_TIMING_CONTROL 0x28
30#define EMC_REFRESH 0x70
31#define EMC_NOP 0xdc
32#define EMC_SELF_REF 0xe0
33#define EMC_MRW 0xe8
34#define EMC_FBIO_CFG5 0x104
35#define EMC_AUTO_CAL_CONFIG 0x2a4
36#define EMC_AUTO_CAL_INTERVAL 0x2a8
37#define EMC_AUTO_CAL_STATUS 0x2ac
38#define EMC_REQ_CTRL 0x2b0
39#define EMC_CFG_DIG_DLL 0x2bc
40#define EMC_EMC_STATUS 0x2b4
41#define EMC_ZCAL_INTERVAL 0x2e0
42#define EMC_ZQ_CAL 0x2ec
43#define EMC_XM2VTTGENPADCTRL 0x310
44#define EMC_XM2VTTGENPADCTRL2 0x314
45
46#define PMC_CTRL 0x0
47#define PMC_CTRL_SIDE_EFFECT_LP0 (1 << 14) /* enter LP0 when CPU pwr gated */
48
49#define PMC_PLLP_WB0_OVERRIDE 0xf8
50#define PMC_IO_DPD_REQ 0x1b8
51#define PMC_IO_DPD_STATUS 0x1bc
52
53#define CLK_RESET_CCLK_BURST 0x20
54#define CLK_RESET_CCLK_DIVIDER 0x24
55#define CLK_RESET_SCLK_BURST 0x28
56#define CLK_RESET_SCLK_DIVIDER 0x2c
57
58#define CLK_RESET_PLLC_BASE 0x80
59#define CLK_RESET_PLLC_MISC 0x8c
60#define CLK_RESET_PLLM_BASE 0x90
61#define CLK_RESET_PLLM_MISC 0x9c
62#define CLK_RESET_PLLP_BASE 0xa0
63#define CLK_RESET_PLLP_MISC 0xac
64#define CLK_RESET_PLLA_BASE 0xb0
65#define CLK_RESET_PLLA_MISC 0xbc
66#define CLK_RESET_PLLX_BASE 0xe0
67#define CLK_RESET_PLLX_MISC 0xe4
68#define CLK_RESET_PLLX_MISC3 0x518
69#define CLK_RESET_PLLX_MISC3_IDDQ 3
70#define CLK_RESET_PLLM_MISC_IDDQ 5
71#define CLK_RESET_PLLC_MISC_IDDQ 26
72
73#define CLK_RESET_CLK_SOURCE_MSELECT 0x3b4
74
75#define MSELECT_CLKM (0x3 << 30)
76
77#define LOCK_DELAY 50 /* safety delay after lock is detected */
78
26#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */ 79#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
27 80
81.macro emc_device_mask, rd, base
82 ldr \rd, [\base, #EMC_ADR_CFG]
83 tst \rd, #0x1
84 moveq \rd, #(0x1 << 8) @ just 1 device
85 movne \rd, #(0x3 << 8) @ 2 devices
86.endm
87
88.macro emc_timing_update, rd, base
89 mov \rd, #1
90 str \rd, [\base, #EMC_TIMING_CONTROL]
911001:
92 ldr \rd, [\base, #EMC_EMC_STATUS]
93 tst \rd, #(0x1<<23) @ wait EMC_STATUS_TIMING_UPDATE_STALLED is clear
94 bne 1001b
95.endm
96
97.macro pll_enable, rd, r_car_base, pll_base, pll_misc
98 ldr \rd, [\r_car_base, #\pll_base]
99 tst \rd, #(1 << 30)
100 orreq \rd, \rd, #(1 << 30)
101 streq \rd, [\r_car_base, #\pll_base]
102 /* Enable lock detector */
103 .if \pll_misc
104 ldr \rd, [\r_car_base, #\pll_misc]
105 bic \rd, \rd, #(1 << 18)
106 str \rd, [\r_car_base, #\pll_misc]
107 ldr \rd, [\r_car_base, #\pll_misc]
108 ldr \rd, [\r_car_base, #\pll_misc]
109 orr \rd, \rd, #(1 << 18)
110 str \rd, [\r_car_base, #\pll_misc]
111 .endif
112.endm
113
114.macro pll_locked, rd, r_car_base, pll_base
1151:
116 ldr \rd, [\r_car_base, #\pll_base]
117 tst \rd, #(1 << 27)
118 beq 1b
119.endm
120
121.macro pll_iddq_exit, rd, car, iddq, iddq_bit
122 ldr \rd, [\car, #\iddq]
123 bic \rd, \rd, #(1<<\iddq_bit)
124 str \rd, [\car, #\iddq]
125.endm
126
127.macro pll_iddq_entry, rd, car, iddq, iddq_bit
128 ldr \rd, [\car, #\iddq]
129 orr \rd, \rd, #(1<<\iddq_bit)
130 str \rd, [\car, #\iddq]
131.endm
132
28#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP) 133#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
29/* 134/*
30 * tegra30_hotplug_shutdown(void) 135 * tegra30_hotplug_shutdown(void)
@@ -99,6 +204,8 @@ flow_ctrl_setting_for_lp2:
99 cmp r10, #TEGRA30 204 cmp r10, #TEGRA30
100 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2 205 moveq r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT @ For LP2
101 movne r3, #FLOW_CTRL_WAITEVENT 206 movne r3, #FLOW_CTRL_WAITEVENT
207 orrne r3, r3, #FLOW_CTRL_HALT_GIC_IRQ
208 orrne r3, r3, #FLOW_CTRL_HALT_GIC_FIQ
102flow_ctrl_done: 209flow_ctrl_done:
103 cmp r10, #TEGRA30 210 cmp r10, #TEGRA30
104 str r3, [r2] 211 str r3, [r2]
@@ -127,6 +234,41 @@ ENDPROC(tegra30_cpu_shutdown)
127 234
128#ifdef CONFIG_PM_SLEEP 235#ifdef CONFIG_PM_SLEEP
129/* 236/*
237 * tegra30_sleep_core_finish(unsigned long v2p)
238 *
239 * Enters suspend in LP0 or LP1 by turning off the MMU and jumping to
240 * tegra30_tear_down_core in IRAM
241 */
242ENTRY(tegra30_sleep_core_finish)
243 /* Flush, disable the L1 data cache and exit SMP */
244 bl tegra_disable_clean_inv_dcache
245
246 /*
247 * Preload all the address literals that are needed for the
248 * CPU power-gating process, to avoid loading from SDRAM which
249 * are not supported once SDRAM is put into self-refresh.
250 * LP0 / LP1 use physical address, since the MMU needs to be
251 * disabled before putting SDRAM into self-refresh to avoid
252 * memory access due to page table walks.
253 */
254 mov32 r4, TEGRA_PMC_BASE
255 mov32 r5, TEGRA_CLK_RESET_BASE
256 mov32 r6, TEGRA_FLOW_CTRL_BASE
257 mov32 r7, TEGRA_TMRUS_BASE
258
259 mov32 r3, tegra_shut_off_mmu
260 add r3, r3, r0
261
262 mov32 r0, tegra30_tear_down_core
263 mov32 r1, tegra30_iram_start
264 sub r0, r0, r1
265 mov32 r1, TEGRA_IRAM_CODE_AREA
266 add r0, r0, r1
267
268 mov pc, r3
269ENDPROC(tegra30_sleep_core_finish)
270
271/*
130 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p) 272 * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
131 * 273 *
132 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU. 274 * Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
@@ -135,6 +277,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
135 mov r7, lr 277 mov r7, lr
136 278
137 /* Flush and disable the L1 data cache */ 279 /* Flush and disable the L1 data cache */
280 mov r0, #TEGRA_FLUSH_CACHE_LOUIS
138 bl tegra_disable_clean_inv_dcache 281 bl tegra_disable_clean_inv_dcache
139 282
140 /* Powergate this CPU. */ 283 /* Powergate this CPU. */
@@ -155,6 +298,351 @@ ENTRY(tegra30_tear_down_cpu)
155 b tegra30_enter_sleep 298 b tegra30_enter_sleep
156ENDPROC(tegra30_tear_down_cpu) 299ENDPROC(tegra30_tear_down_cpu)
157 300
301/* START OF ROUTINES COPIED TO IRAM */
302 .align L1_CACHE_SHIFT
303 .globl tegra30_iram_start
304tegra30_iram_start:
305
306/*
307 * tegra30_lp1_reset
308 *
309 * reset vector for LP1 restore; copied into IRAM during suspend.
310 * Brings the system back up to a safe staring point (SDRAM out of
311 * self-refresh, PLLC, PLLM and PLLP reenabled, CPU running on PLLX,
312 * system clock running on the same PLL that it suspended at), and
313 * jumps to tegra_resume to restore virtual addressing.
314 * The physical address of tegra_resume expected to be stored in
315 * PMC_SCRATCH41.
316 *
317 * NOTE: THIS *MUST* BE RELOCATED TO TEGRA_IRAM_CODE_AREA.
318 */
319ENTRY(tegra30_lp1_reset)
320 /*
321 * The CPU and system bus are running at 32KHz and executing from
322 * IRAM when this code is executed; immediately switch to CLKM and
323 * enable PLLP, PLLM, PLLC, PLLA and PLLX.
324 */
325 mov32 r0, TEGRA_CLK_RESET_BASE
326
327 mov r1, #(1 << 28)
328 str r1, [r0, #CLK_RESET_SCLK_BURST]
329 str r1, [r0, #CLK_RESET_CCLK_BURST]
330 mov r1, #0
331 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
332 str r1, [r0, #CLK_RESET_SCLK_DIVIDER]
333
334 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
335 cmp r10, #TEGRA30
336 beq _no_pll_iddq_exit
337
338 pll_iddq_exit r1, r0, CLK_RESET_PLLM_MISC, CLK_RESET_PLLM_MISC_IDDQ
339 pll_iddq_exit r1, r0, CLK_RESET_PLLC_MISC, CLK_RESET_PLLC_MISC_IDDQ
340 pll_iddq_exit r1, r0, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
341
342 mov32 r7, TEGRA_TMRUS_BASE
343 ldr r1, [r7]
344 add r1, r1, #2
345 wait_until r1, r7, r3
346
347 /* enable PLLM via PMC */
348 mov32 r2, TEGRA_PMC_BASE
349 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
350 orr r1, r1, #(1 << 12)
351 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
352
353 pll_enable r1, r0, CLK_RESET_PLLM_BASE, 0
354 pll_enable r1, r0, CLK_RESET_PLLC_BASE, 0
355 pll_enable r1, r0, CLK_RESET_PLLX_BASE, 0
356
357 b _pll_m_c_x_done
358
359_no_pll_iddq_exit:
360 /* enable PLLM via PMC */
361 mov32 r2, TEGRA_PMC_BASE
362 ldr r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
363 orr r1, r1, #(1 << 12)
364 str r1, [r2, #PMC_PLLP_WB0_OVERRIDE]
365
366 pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC
367 pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC
368 pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC
369
370_pll_m_c_x_done:
371 pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
372 pll_enable r1, r0, CLK_RESET_PLLA_BASE, CLK_RESET_PLLA_MISC
373
374 pll_locked r1, r0, CLK_RESET_PLLM_BASE
375 pll_locked r1, r0, CLK_RESET_PLLP_BASE
376 pll_locked r1, r0, CLK_RESET_PLLA_BASE
377 pll_locked r1, r0, CLK_RESET_PLLC_BASE
378 pll_locked r1, r0, CLK_RESET_PLLX_BASE
379
380 mov32 r7, TEGRA_TMRUS_BASE
381 ldr r1, [r7]
382 add r1, r1, #LOCK_DELAY
383 wait_until r1, r7, r3
384
385 adr r5, tegra30_sdram_pad_save
386
387 ldr r4, [r5, #0x18] @ restore CLK_SOURCE_MSELECT
388 str r4, [r0, #CLK_RESET_CLK_SOURCE_MSELECT]
389
390 ldr r4, [r5, #0x1C] @ restore SCLK_BURST
391 str r4, [r0, #CLK_RESET_SCLK_BURST]
392
393 cmp r10, #TEGRA30
394 movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX
395 movteq r4, #:upper16:((1 << 28) | (0x8))
396 movwne r4, #:lower16:((1 << 28) | (0xe))
397 movtne r4, #:upper16:((1 << 28) | (0xe))
398 str r4, [r0, #CLK_RESET_CCLK_BURST]
399
400 /* Restore pad power state to normal */
401 ldr r1, [r5, #0x14] @ PMC_IO_DPD_STATUS
402 mvn r1, r1
403 bic r1, r1, #(1 << 31)
404 orr r1, r1, #(1 << 30)
405 str r1, [r2, #PMC_IO_DPD_REQ] @ DPD_OFF
406
407 cmp r10, #TEGRA30
408 movweq r0, #:lower16:TEGRA_EMC_BASE @ r0 reserved for emc base
409 movteq r0, #:upper16:TEGRA_EMC_BASE
410 movwne r0, #:lower16:TEGRA_EMC0_BASE
411 movtne r0, #:upper16:TEGRA_EMC0_BASE
412
413exit_self_refresh:
414 ldr r1, [r5, #0xC] @ restore EMC_XM2VTTGENPADCTRL
415 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
416 ldr r1, [r5, #0x10] @ restore EMC_XM2VTTGENPADCTRL2
417 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
418 ldr r1, [r5, #0x8] @ restore EMC_AUTO_CAL_INTERVAL
419 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
420
421 /* Relock DLL */
422 ldr r1, [r0, #EMC_CFG_DIG_DLL]
423 orr r1, r1, #(1 << 30) @ set DLL_RESET
424 str r1, [r0, #EMC_CFG_DIG_DLL]
425
426 emc_timing_update r1, r0
427
428 cmp r10, #TEGRA114
429 movweq r1, #:lower16:TEGRA_EMC1_BASE
430 movteq r1, #:upper16:TEGRA_EMC1_BASE
431 cmpeq r0, r1
432
433 ldr r1, [r0, #EMC_AUTO_CAL_CONFIG]
434 orr r1, r1, #(1 << 31) @ set AUTO_CAL_ACTIVE
435 orreq r1, r1, #(1 << 27) @ set slave mode for channel 1
436 str r1, [r0, #EMC_AUTO_CAL_CONFIG]
437
438emc_wait_auto_cal_onetime:
439 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
440 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
441 bne emc_wait_auto_cal_onetime
442
443 ldr r1, [r0, #EMC_CFG]
444 bic r1, r1, #(1 << 31) @ disable DRAM_CLK_STOP_PD
445 str r1, [r0, #EMC_CFG]
446
447 mov r1, #0
448 str r1, [r0, #EMC_SELF_REF] @ take DRAM out of self refresh
449 mov r1, #1
450 cmp r10, #TEGRA30
451 streq r1, [r0, #EMC_NOP]
452 streq r1, [r0, #EMC_NOP]
453 streq r1, [r0, #EMC_REFRESH]
454
455 emc_device_mask r1, r0
456
457exit_selfrefresh_loop:
458 ldr r2, [r0, #EMC_EMC_STATUS]
459 ands r2, r2, r1
460 bne exit_selfrefresh_loop
461
462 lsr r1, r1, #8 @ devSel, bit0:dev0, bit1:dev1
463
464 mov32 r7, TEGRA_TMRUS_BASE
465 ldr r2, [r0, #EMC_FBIO_CFG5]
466
467 and r2, r2, #3 @ check DRAM_TYPE
468 cmp r2, #2
469 beq emc_lpddr2
470
471 /* Issue a ZQ_CAL for dev0 - DDR3 */
472 mov32 r2, 0x80000011 @ DEV_SELECTION=2, LENGTH=LONG, CMD=1
473 str r2, [r0, #EMC_ZQ_CAL]
474 ldr r2, [r7]
475 add r2, r2, #10
476 wait_until r2, r7, r3
477
478 tst r1, #2
479 beq zcal_done
480
481 /* Issue a ZQ_CAL for dev1 - DDR3 */
482 mov32 r2, 0x40000011 @ DEV_SELECTION=1, LENGTH=LONG, CMD=1
483 str r2, [r0, #EMC_ZQ_CAL]
484 ldr r2, [r7]
485 add r2, r2, #10
486 wait_until r2, r7, r3
487 b zcal_done
488
489emc_lpddr2:
490 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
491 mov32 r2, 0x800A00AB @ DEV_SELECTION=2, MA=10, OP=0xAB
492 str r2, [r0, #EMC_MRW]
493 ldr r2, [r7]
494 add r2, r2, #1
495 wait_until r2, r7, r3
496
497 tst r1, #2
498 beq zcal_done
499
500 /* Issue a ZQ_CAL for dev0 - LPDDR2 */
501 mov32 r2, 0x400A00AB @ DEV_SELECTION=1, MA=10, OP=0xAB
502 str r2, [r0, #EMC_MRW]
503 ldr r2, [r7]
504 add r2, r2, #1
505 wait_until r2, r7, r3
506
507zcal_done:
508 mov r1, #0 @ unstall all transactions
509 str r1, [r0, #EMC_REQ_CTRL]
510 ldr r1, [r5, #0x4] @ restore EMC_ZCAL_INTERVAL
511 str r1, [r0, #EMC_ZCAL_INTERVAL]
512 ldr r1, [r5, #0x0] @ restore EMC_CFG
513 str r1, [r0, #EMC_CFG]
514
515 /* Tegra114 had dual EMC channel, now config the other one */
516 cmp r10, #TEGRA114
517 bne __no_dual_emc_chanl
518 mov32 r1, TEGRA_EMC1_BASE
519 cmp r0, r1
520 movne r0, r1
521 addne r5, r5, #0x20
522 bne exit_self_refresh
523__no_dual_emc_chanl:
524
525 mov32 r0, TEGRA_PMC_BASE
526 ldr r0, [r0, #PMC_SCRATCH41]
527 mov pc, r0 @ jump to tegra_resume
528ENDPROC(tegra30_lp1_reset)
529
530 .align L1_CACHE_SHIFT
531tegra30_sdram_pad_address:
532 .word TEGRA_EMC_BASE + EMC_CFG @0x0
533 .word TEGRA_EMC_BASE + EMC_ZCAL_INTERVAL @0x4
534 .word TEGRA_EMC_BASE + EMC_AUTO_CAL_INTERVAL @0x8
535 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL @0xc
536 .word TEGRA_EMC_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
537 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
538 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
539 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
540
541tegra114_sdram_pad_address:
542 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
543 .word TEGRA_EMC0_BASE + EMC_ZCAL_INTERVAL @0x4
544 .word TEGRA_EMC0_BASE + EMC_AUTO_CAL_INTERVAL @0x8
545 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL @0xc
546 .word TEGRA_EMC0_BASE + EMC_XM2VTTGENPADCTRL2 @0x10
547 .word TEGRA_PMC_BASE + PMC_IO_DPD_STATUS @0x14
548 .word TEGRA_CLK_RESET_BASE + CLK_RESET_CLK_SOURCE_MSELECT @0x18
549 .word TEGRA_CLK_RESET_BASE + CLK_RESET_SCLK_BURST @0x1c
550 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
551 .word TEGRA_EMC1_BASE + EMC_ZCAL_INTERVAL @0x24
552 .word TEGRA_EMC1_BASE + EMC_AUTO_CAL_INTERVAL @0x28
553 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL @0x2c
554 .word TEGRA_EMC1_BASE + EMC_XM2VTTGENPADCTRL2 @0x30
555
556tegra30_sdram_pad_size:
557 .word tegra114_sdram_pad_address - tegra30_sdram_pad_address
558
559tegra114_sdram_pad_size:
560 .word tegra30_sdram_pad_size - tegra114_sdram_pad_address
561
562 .type tegra30_sdram_pad_save, %object
563tegra30_sdram_pad_save:
564 .rept (tegra30_sdram_pad_size - tegra114_sdram_pad_address) / 4
565 .long 0
566 .endr
567
568/*
569 * tegra30_tear_down_core
570 *
571 * copied into and executed from IRAM
572 * puts memory in self-refresh for LP0 and LP1
573 */
574tegra30_tear_down_core:
575 bl tegra30_sdram_self_refresh
576 bl tegra30_switch_cpu_to_clk32k
577 b tegra30_enter_sleep
578
579/*
580 * tegra30_switch_cpu_to_clk32k
581 *
582 * In LP0 and LP1 all PLLs will be turned off. Switching the CPU and System CLK
583 * to the 32KHz clock.
584 * r4 = TEGRA_PMC_BASE
585 * r5 = TEGRA_CLK_RESET_BASE
586 * r6 = TEGRA_FLOW_CTRL_BASE
587 * r7 = TEGRA_TMRUS_BASE
588 * r10= SoC ID
589 */
590tegra30_switch_cpu_to_clk32k:
591 /*
592 * start by jumping to CLKM to safely disable PLLs, then jump to
593 * CLKS.
594 */
595 mov r0, #(1 << 28)
596 str r0, [r5, #CLK_RESET_SCLK_BURST]
597 /* 2uS delay delay between changing SCLK and CCLK */
598 ldr r1, [r7]
599 add r1, r1, #2
600 wait_until r1, r7, r9
601 str r0, [r5, #CLK_RESET_CCLK_BURST]
602 mov r0, #0
603 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
604 str r0, [r5, #CLK_RESET_SCLK_DIVIDER]
605
606 /* switch the clock source of mselect to be CLK_M */
607 ldr r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
608 orr r0, r0, #MSELECT_CLKM
609 str r0, [r5, #CLK_RESET_CLK_SOURCE_MSELECT]
610
611 /* 2uS delay delay between changing SCLK and disabling PLLs */
612 ldr r1, [r7]
613 add r1, r1, #2
614 wait_until r1, r7, r9
615
616 /* disable PLLM via PMC in LP1 */
617 ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
618 bic r0, r0, #(1 << 12)
619 str r0, [r4, #PMC_PLLP_WB0_OVERRIDE]
620
621 /* disable PLLP, PLLA, PLLC and PLLX */
622 ldr r0, [r5, #CLK_RESET_PLLP_BASE]
623 bic r0, r0, #(1 << 30)
624 str r0, [r5, #CLK_RESET_PLLP_BASE]
625 ldr r0, [r5, #CLK_RESET_PLLA_BASE]
626 bic r0, r0, #(1 << 30)
627 str r0, [r5, #CLK_RESET_PLLA_BASE]
628 ldr r0, [r5, #CLK_RESET_PLLC_BASE]
629 bic r0, r0, #(1 << 30)
630 str r0, [r5, #CLK_RESET_PLLC_BASE]
631 ldr r0, [r5, #CLK_RESET_PLLX_BASE]
632 bic r0, r0, #(1 << 30)
633 str r0, [r5, #CLK_RESET_PLLX_BASE]
634
635 cmp r10, #TEGRA30
636 beq _no_pll_in_iddq
637 pll_iddq_entry r1, r5, CLK_RESET_PLLX_MISC3, CLK_RESET_PLLX_MISC3_IDDQ
638_no_pll_in_iddq:
639
640 /* switch to CLKS */
641 mov r0, #0 /* brust policy = 32KHz */
642 str r0, [r5, #CLK_RESET_SCLK_BURST]
643
644 mov pc, lr
645
158/* 646/*
159 * tegra30_enter_sleep 647 * tegra30_enter_sleep
160 * 648 *
@@ -172,8 +660,12 @@ tegra30_enter_sleep:
172 orr r0, r0, #FLOW_CTRL_CSR_ENABLE 660 orr r0, r0, #FLOW_CTRL_CSR_ENABLE
173 str r0, [r6, r2] 661 str r0, [r6, r2]
174 662
663 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
664 cmp r10, #TEGRA30
175 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT 665 mov r0, #FLOW_CTRL_WAIT_FOR_INTERRUPT
176 orr r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ 666 orreq r0, r0, #FLOW_CTRL_HALT_CPU_IRQ | FLOW_CTRL_HALT_CPU_FIQ
667 orrne r0, r0, #FLOW_CTRL_HALT_LIC_IRQ | FLOW_CTRL_HALT_LIC_FIQ
668
177 cpu_to_halt_reg r2, r1 669 cpu_to_halt_reg r2, r1
178 str r0, [r6, r2] 670 str r0, [r6, r2]
179 dsb 671 dsb
@@ -187,4 +679,126 @@ halted:
187 /* !!!FIXME!!! Implement halt failure handler */ 679 /* !!!FIXME!!! Implement halt failure handler */
188 b halted 680 b halted
189 681
682/*
683 * tegra30_sdram_self_refresh
684 *
685 * called with MMU off and caches disabled
686 * must be executed from IRAM
687 * r4 = TEGRA_PMC_BASE
688 * r5 = TEGRA_CLK_RESET_BASE
689 * r6 = TEGRA_FLOW_CTRL_BASE
690 * r7 = TEGRA_TMRUS_BASE
691 * r10= SoC ID
692 */
693tegra30_sdram_self_refresh:
694
695 adr r8, tegra30_sdram_pad_save
696 tegra_get_soc_id TEGRA_APB_MISC_BASE, r10
697 cmp r10, #TEGRA30
698 adreq r2, tegra30_sdram_pad_address
699 ldreq r3, tegra30_sdram_pad_size
700 adrne r2, tegra114_sdram_pad_address
701 ldrne r3, tegra114_sdram_pad_size
702 mov r9, #0
703
704padsave:
705 ldr r0, [r2, r9] @ r0 is the addr in the pad_address
706
707 ldr r1, [r0]
708 str r1, [r8, r9] @ save the content of the addr
709
710 add r9, r9, #4
711 cmp r3, r9
712 bne padsave
713padsave_done:
714
715 dsb
716
717 cmp r10, #TEGRA30
718 ldreq r0, =TEGRA_EMC_BASE @ r0 reserved for emc base addr
719 ldrne r0, =TEGRA_EMC0_BASE
720
721enter_self_refresh:
722 cmp r10, #TEGRA30
723 mov r1, #0
724 str r1, [r0, #EMC_ZCAL_INTERVAL]
725 str r1, [r0, #EMC_AUTO_CAL_INTERVAL]
726 ldr r1, [r0, #EMC_CFG]
727 bic r1, r1, #(1 << 28)
728 bicne r1, r1, #(1 << 29)
729 str r1, [r0, #EMC_CFG] @ disable DYN_SELF_REF
730
731 emc_timing_update r1, r0
732
733 ldr r1, [r7]
734 add r1, r1, #5
735 wait_until r1, r7, r2
736
737emc_wait_auto_cal:
738 ldr r1, [r0, #EMC_AUTO_CAL_STATUS]
739 tst r1, #(1 << 31) @ wait until AUTO_CAL_ACTIVE is cleared
740 bne emc_wait_auto_cal
741
742 mov r1, #3
743 str r1, [r0, #EMC_REQ_CTRL] @ stall incoming DRAM requests
744
745emcidle:
746 ldr r1, [r0, #EMC_EMC_STATUS]
747 tst r1, #4
748 beq emcidle
749
750 mov r1, #1
751 str r1, [r0, #EMC_SELF_REF]
752
753 emc_device_mask r1, r0
754
755emcself:
756 ldr r2, [r0, #EMC_EMC_STATUS]
757 and r2, r2, r1
758 cmp r2, r1
759 bne emcself @ loop until DDR in self-refresh
760
761 /* Put VTTGEN in the lowest power mode */
762 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL]
763 mov32 r2, 0xF8F8FFFF @ clear XM2VTTGEN_DRVUP and XM2VTTGEN_DRVDN
764 and r1, r1, r2
765 str r1, [r0, #EMC_XM2VTTGENPADCTRL]
766 ldr r1, [r0, #EMC_XM2VTTGENPADCTRL2]
767 cmp r10, #TEGRA30
768 orreq r1, r1, #7 @ set E_NO_VTTGEN
769 orrne r1, r1, #0x3f
770 str r1, [r0, #EMC_XM2VTTGENPADCTRL2]
771
772 emc_timing_update r1, r0
773
774 /* Tegra114 had dual EMC channel, now config the other one */
775 cmp r10, #TEGRA114
776 bne no_dual_emc_chanl
777 mov32 r1, TEGRA_EMC1_BASE
778 cmp r0, r1
779 movne r0, r1
780 bne enter_self_refresh
781no_dual_emc_chanl:
782
783 ldr r1, [r4, #PMC_CTRL]
784 tst r1, #PMC_CTRL_SIDE_EFFECT_LP0
785 bne pmc_io_dpd_skip
786 /*
787 * Put DDR_DATA, DISC_ADDR_CMD, DDR_ADDR_CMD, POP_ADDR_CMD, POP_CLK
788 * and COMP in the lowest power mode when LP1.
789 */
790 mov32 r1, 0x8EC00000
791 str r1, [r4, #PMC_IO_DPD_REQ]
792pmc_io_dpd_skip:
793
794 dsb
795
796 mov pc, lr
797
798 .ltorg
799/* dummy symbol for end of IRAM */
800 .align L1_CACHE_SHIFT
801 .global tegra30_iram_end
802tegra30_iram_end:
803 b .
190#endif 804#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 9daaef26b0f6..8d06213fbc47 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -56,7 +56,9 @@ ENTRY(tegra_disable_clean_inv_dcache)
56 isb 56 isb
57 57
58 /* Flush the D-cache */ 58 /* Flush the D-cache */
59 bl v7_flush_dcache_louis 59 cmp r0, #TEGRA_FLUSH_CACHE_ALL
60 blne v7_flush_dcache_louis
61 bleq v7_flush_dcache_all
60 62
61 /* Trun off coherency */ 63 /* Trun off coherency */
62 exit_smp r4, r5 64 exit_smp r4, r5
@@ -67,15 +69,40 @@ ENDPROC(tegra_disable_clean_inv_dcache)
67 69
68#ifdef CONFIG_PM_SLEEP 70#ifdef CONFIG_PM_SLEEP
69/* 71/*
72 * tegra_init_l2_for_a15
73 *
74 * set up the correct L2 cache data RAM latency
75 */
76ENTRY(tegra_init_l2_for_a15)
77 mrc p15, 0, r0, c0, c0, 5
78 ubfx r0, r0, #8, #4
79 tst r0, #1 @ only need for cluster 0
80 bne _exit_init_l2_a15
81
82 mrc p15, 0x1, r0, c9, c0, 2
83 and r0, r0, #7
84 cmp r0, #2
85 bicne r0, r0, #7
86 orrne r0, r0, #2
87 mcrne p15, 0x1, r0, c9, c0, 2
88_exit_init_l2_a15:
89
90 mov pc, lr
91ENDPROC(tegra_init_l2_for_a15)
92
93/*
70 * tegra_sleep_cpu_finish(unsigned long v2p) 94 * tegra_sleep_cpu_finish(unsigned long v2p)
71 * 95 *
72 * enters suspend in LP2 by turning off the mmu and jumping to 96 * enters suspend in LP2 by turning off the mmu and jumping to
73 * tegra?_tear_down_cpu 97 * tegra?_tear_down_cpu
74 */ 98 */
75ENTRY(tegra_sleep_cpu_finish) 99ENTRY(tegra_sleep_cpu_finish)
100 mov r4, r0
76 /* Flush and disable the L1 data cache */ 101 /* Flush and disable the L1 data cache */
102 mov r0, #TEGRA_FLUSH_CACHE_ALL
77 bl tegra_disable_clean_inv_dcache 103 bl tegra_disable_clean_inv_dcache
78 104
105 mov r0, r4
79 mov32 r6, tegra_tear_down_cpu 106 mov32 r6, tegra_tear_down_cpu
80 ldr r1, [r6] 107 ldr r1, [r6]
81 add r1, r1, r0 108 add r1, r1, r0
@@ -107,10 +134,10 @@ ENTRY(tegra_shut_off_mmu)
107#ifdef CONFIG_CACHE_L2X0 134#ifdef CONFIG_CACHE_L2X0
108 /* Disable L2 cache */ 135 /* Disable L2 cache */
109 check_cpu_part_num 0xc09, r9, r10 136 check_cpu_part_num 0xc09, r9, r10
110 movweq r4, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000) 137 movweq r2, #:lower16:(TEGRA_ARM_PERIF_BASE + 0x3000)
111 movteq r4, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000) 138 movteq r2, #:upper16:(TEGRA_ARM_PERIF_BASE + 0x3000)
112 moveq r5, #0 139 moveq r3, #0
113 streq r5, [r4, #L2X0_CTRL] 140 streq r3, [r2, #L2X0_CTRL]
114#endif 141#endif
115 mov pc, r0 142 mov pc, r0
116ENDPROC(tegra_shut_off_mmu) 143ENDPROC(tegra_shut_off_mmu)
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 98b7da698f2b..a4edbb3abd3d 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -41,7 +41,19 @@
41#define CPU_NOT_RESETTABLE 0 41#define CPU_NOT_RESETTABLE 0
42#endif 42#endif
43 43
44/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
45#define TEGRA_FLUSH_CACHE_LOUIS 0
46#define TEGRA_FLUSH_CACHE_ALL 1
47
44#ifdef __ASSEMBLY__ 48#ifdef __ASSEMBLY__
49/* waits until the microsecond counter (base) is > rn */
50.macro wait_until, rn, base, tmp
51 add \rn, \rn, #1
521001: ldr \tmp, [\base]
53 cmp \tmp, \rn
54 bmi 1001b
55.endm
56
45/* returns the offset of the flow controller halt register for a cpu */ 57/* returns the offset of the flow controller halt register for a cpu */
46.macro cpu_to_halt_reg rd, rcpu 58.macro cpu_to_halt_reg rd, rcpu
47 cmp \rcpu, #0 59 cmp \rcpu, #0
@@ -144,7 +156,7 @@ void tegra_pen_lock(void);
144void tegra_pen_unlock(void); 156void tegra_pen_unlock(void);
145void tegra_resume(void); 157void tegra_resume(void);
146int tegra_sleep_cpu_finish(unsigned long); 158int tegra_sleep_cpu_finish(unsigned long);
147void tegra_disable_clean_inv_dcache(void); 159void tegra_disable_clean_inv_dcache(u32 flag);
148 160
149#ifdef CONFIG_HOTPLUG_CPU 161#ifdef CONFIG_HOTPLUG_CPU
150void tegra20_hotplug_shutdown(void); 162void tegra20_hotplug_shutdown(void);
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index fc97cfd52769..5b8605547a09 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -80,28 +80,6 @@ out:
80 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent); 80 of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
81} 81}
82 82
83static void __init trimslice_init(void)
84{
85#ifdef CONFIG_TEGRA_PCI
86 int ret;
87
88 ret = tegra_pcie_init(true, true);
89 if (ret)
90 pr_err("tegra_pci_init() failed: %d\n", ret);
91#endif
92}
93
94static void __init harmony_init(void)
95{
96#ifdef CONFIG_TEGRA_PCI
97 int ret;
98
99 ret = harmony_pcie_init();
100 if (ret)
101 pr_err("harmony_pcie_init() failed: %d\n", ret);
102#endif
103}
104
105static void __init paz00_init(void) 83static void __init paz00_init(void)
106{ 84{
107 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 85 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
@@ -112,8 +90,6 @@ static struct {
112 char *machine; 90 char *machine;
113 void (*init)(void); 91 void (*init)(void);
114} board_init_funcs[] = { 92} board_init_funcs[] = {
115 { "compulab,trimslice", trimslice_init },
116 { "nvidia,harmony", harmony_init },
117 { "compal,paz00", paz00_init }, 93 { "compal,paz00", paz00_init },
118}; 94};
119 95
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index b19b07204aaf..99a28d628297 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -8,7 +8,7 @@ config ARCH_U8500
8 select CPU_V7 8 select CPU_V7
9 select GENERIC_CLOCKEVENTS 9 select GENERIC_CLOCKEVENTS
10 select HAVE_ARM_SCU if SMP 10 select HAVE_ARM_SCU if SMP
11 select HAVE_ARM_TWD if LOCAL_TIMERS 11 select HAVE_ARM_TWD if SMP
12 select HAVE_SMP 12 select HAVE_SMP
13 select MIGHT_HAVE_CACHE_L2X0 13 select MIGHT_HAVE_CACHE_L2X0
14 help 14 help
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index bfe443daf4b0..ec0807247e60 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -17,7 +17,6 @@
17#include "ste-dma40-db8500.h" 17#include "ste-dma40-db8500.h"
18#include "board-mop500.h" 18#include "board-mop500.h"
19#include "devices-db8500.h" 19#include "devices-db8500.h"
20#include "pins-db8500.h"
21 20
22static struct stedma40_chan_cfg msp0_dma_rx = { 21static struct stedma40_chan_cfg msp0_dma_rx = {
23 .high_priority = true, 22 .high_priority = true,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 7936d40a5c37..0efb1560fc35 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -14,7 +14,6 @@
14 14
15#include <asm/mach-types.h> 15#include <asm/mach-types.h>
16 16
17#include "pins-db8500.h"
18#include "board-mop500.h" 17#include "board-mop500.h"
19 18
20enum custom_pin_cfg_t { 19enum custom_pin_cfg_t {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index df5d27a532e9..ad0806eff762 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -42,7 +42,6 @@
42#include <linux/platform_data/dma-ste-dma40.h> 42#include <linux/platform_data/dma-ste-dma40.h>
43 43
44#include <asm/mach-types.h> 44#include <asm/mach-types.h>
45#include <asm/mach/arch.h>
46 45
47#include "setup.h" 46#include "setup.h"
48#include "devices.h" 47#include "devices.h"
@@ -325,21 +324,19 @@ static struct lp55xx_platform_data __initdata lp5521_sec_data = {
325 .clock_mode = LP55XX_CLOCK_EXT, 324 .clock_mode = LP55XX_CLOCK_EXT,
326}; 325};
327 326
327/* I2C0 devices only available on the first HREF/MOP500 */
328static struct i2c_board_info __initdata mop500_i2c0_devices[] = { 328static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
329 { 329 {
330 I2C_BOARD_INFO("tc3589x", 0x42), 330 I2C_BOARD_INFO("tc3589x", 0x42),
331 .irq = NOMADIK_GPIO_TO_IRQ(217), 331 .irq = NOMADIK_GPIO_TO_IRQ(217),
332 .platform_data = &mop500_tc35892_data, 332 .platform_data = &mop500_tc35892_data,
333 }, 333 },
334 /* I2C0 devices only available prior to HREFv60 */
335 { 334 {
336 I2C_BOARD_INFO("tps61052", 0x33), 335 I2C_BOARD_INFO("tps61052", 0x33),
337 .platform_data = &mop500_tps61052_data, 336 .platform_data = &mop500_tps61052_data,
338 }, 337 },
339}; 338};
340 339
341#define NUM_PRE_V60_I2C0_DEVICES 1
342
343static struct i2c_board_info __initdata mop500_i2c2_devices[] = { 340static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
344 { 341 {
345 /* lp5521 LED driver, 1st device */ 342 /* lp5521 LED driver, 1st device */
@@ -357,6 +354,17 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
357 }, 354 },
358}; 355};
359 356
357static int __init mop500_i2c_board_init(void)
358{
359 if (machine_is_u8500())
360 mop500_uib_i2c_add(0, mop500_i2c0_devices,
361 ARRAY_SIZE(mop500_i2c0_devices));
362 mop500_uib_i2c_add(2, mop500_i2c2_devices,
363 ARRAY_SIZE(mop500_i2c2_devices));
364 return 0;
365}
366device_initcall(mop500_i2c_board_init);
367
360static void __init mop500_i2c_init(struct device *parent) 368static void __init mop500_i2c_init(struct device *parent)
361{ 369{
362 db8500_add_i2c0(parent, NULL); 370 db8500_add_i2c0(parent, NULL);
@@ -565,7 +573,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
565static void __init mop500_init_machine(void) 573static void __init mop500_init_machine(void)
566{ 574{
567 struct device *parent = NULL; 575 struct device *parent = NULL;
568 int i2c0_devs;
569 int i; 576 int i;
570 577
571 platform_device_register(&db8500_prcmu_device); 578 platform_device_register(&db8500_prcmu_device);
@@ -588,19 +595,13 @@ static void __init mop500_init_machine(void)
588 mop500_spi_init(parent); 595 mop500_spi_init(parent);
589 mop500_audio_init(parent); 596 mop500_audio_init(parent);
590 mop500_uart_init(parent); 597 mop500_uart_init(parent);
591
592 u8500_cryp1_hash1_init(parent); 598 u8500_cryp1_hash1_init(parent);
593 599
594 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
595
596 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
597 i2c_register_board_info(2, mop500_i2c2_devices,
598 ARRAY_SIZE(mop500_i2c2_devices));
599
600 /* This board has full regulator constraints */ 600 /* This board has full regulator constraints */
601 regulator_has_full_constraints(); 601 regulator_has_full_constraints();
602} 602}
603 603
604
604static void __init snowball_init_machine(void) 605static void __init snowball_init_machine(void)
605{ 606{
606 struct device *parent = NULL; 607 struct device *parent = NULL;
@@ -635,7 +636,6 @@ static void __init snowball_init_machine(void)
635static void __init hrefv60_init_machine(void) 636static void __init hrefv60_init_machine(void)
636{ 637{
637 struct device *parent = NULL; 638 struct device *parent = NULL;
638 int i2c0_devs;
639 int i; 639 int i;
640 640
641 platform_device_register(&db8500_prcmu_device); 641 platform_device_register(&db8500_prcmu_device);
@@ -664,14 +664,6 @@ static void __init hrefv60_init_machine(void)
664 mop500_audio_init(parent); 664 mop500_audio_init(parent);
665 mop500_uart_init(parent); 665 mop500_uart_init(parent);
666 666
667 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
668
669 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
670
671 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
672 i2c_register_board_info(2, mop500_i2c2_devices,
673 ARRAY_SIZE(mop500_i2c2_devices));
674
675 /* This board has full regulator constraints */ 667 /* This board has full regulator constraints */
676 regulator_has_full_constraints(); 668 regulator_has_full_constraints();
677} 669}
@@ -686,6 +678,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
686 .init_time = ux500_timer_init, 678 .init_time = ux500_timer_init,
687 .init_machine = mop500_init_machine, 679 .init_machine = mop500_init_machine,
688 .init_late = ux500_init_late, 680 .init_late = ux500_init_late,
681 .restart = ux500_restart,
689MACHINE_END 682MACHINE_END
690 683
691MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") 684MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
@@ -695,6 +688,7 @@ MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520")
695 .init_time = ux500_timer_init, 688 .init_time = ux500_timer_init,
696 .init_machine = mop500_init_machine, 689 .init_machine = mop500_init_machine,
697 .init_late = ux500_init_late, 690 .init_late = ux500_init_late,
691 .restart = ux500_restart,
698MACHINE_END 692MACHINE_END
699 693
700MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") 694MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
@@ -705,6 +699,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
705 .init_time = ux500_timer_init, 699 .init_time = ux500_timer_init,
706 .init_machine = hrefv60_init_machine, 700 .init_machine = hrefv60_init_machine,
707 .init_late = ux500_init_late, 701 .init_late = ux500_init_late,
702 .restart = ux500_restart,
708MACHINE_END 703MACHINE_END
709 704
710MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") 705MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
@@ -716,4 +711,5 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
716 .init_time = ux500_timer_init, 711 .init_time = ux500_timer_init,
717 .init_machine = snowball_init_machine, 712 .init_machine = snowball_init_machine,
718 .init_late = NULL, 713 .init_late = NULL,
714 .restart = ux500_restart,
719MACHINE_END 715MACHINE_END
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 12eee8167525..301c3460d96a 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -26,7 +26,6 @@
26 26
27#include <asm/pmu.h> 27#include <asm/pmu.h>
28#include <asm/mach/map.h> 28#include <asm/mach/map.h>
29#include <asm/mach/arch.h>
30 29
31#include "setup.h" 30#include "setup.h"
32#include "devices.h" 31#include "devices.h"
@@ -157,7 +156,8 @@ static void __init db8500_add_gpios(struct device *parent)
157 .supports_sleepmode = true, 156 .supports_sleepmode = true,
158 }; 157 };
159 158
160 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 159 dbx500_add_gpios(parent, db8500_gpio_base,
160 ARRAY_SIZE(db8500_gpio_base),
161 IRQ_DB8500_GPIO0, &pdata); 161 IRQ_DB8500_GPIO0, &pdata);
162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); 162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
163} 163}
@@ -223,10 +223,10 @@ static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
223 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL), 223 OF_DEV_AUXDATA("arm,pl011", 0x80121000, "uart1", NULL),
224 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL), 224 OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", NULL),
225 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat), 225 OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0", &ssp0_plat),
226 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", &mop500_sdi0_data), 226 OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0", NULL),
227 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", &mop500_sdi1_data), 227 OF_DEV_AUXDATA("arm,pl18x", 0x80118000, "sdi1", NULL),
228 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", &mop500_sdi2_data), 228 OF_DEV_AUXDATA("arm,pl18x", 0x80005000, "sdi2", NULL),
229 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", &mop500_sdi4_data), 229 OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4", NULL),
230 /* Requires clock name bindings. */ 230 /* Requires clock name bindings. */
231 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL), 231 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
232 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL), 232 OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
@@ -325,6 +325,7 @@ DT_MACHINE_START(U8500_DT, "ST-Ericsson Ux5x0 platform (Device Tree Support)")
325 .init_machine = u8500_init_machine, 325 .init_machine = u8500_init_machine,
326 .init_late = NULL, 326 .init_late = NULL,
327 .dt_compat = stericsson_dt_platform_compat, 327 .dt_compat = stericsson_dt_platform_compat,
328 .restart = ux500_restart,
328MACHINE_END 329MACHINE_END
329 330
330#endif 331#endif
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e6fb0239151b..5d7eebcabc63 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -31,6 +31,14 @@
31#include "db8500-regs.h" 31#include "db8500-regs.h"
32#include "id.h" 32#include "id.h"
33 33
34void ux500_restart(enum reboot_mode mode, const char *cmd)
35{
36 local_irq_disable();
37 local_fiq_disable();
38
39 prcmu_system_reset(0);
40}
41
34/* 42/*
35 * FIXME: Should we set up the GPIO domain here? 43 * FIXME: Should we set up the GPIO domain here?
36 * 44 *
diff --git a/arch/arm/mach-ux500/devices-db8500.c b/arch/arm/mach-ux500/devices-db8500.c
index 516a6f57d159..bc316062e0c2 100644
--- a/arch/arm/mach-ux500/devices-db8500.c
+++ b/arch/arm/mach-ux500/devices-db8500.c
@@ -49,6 +49,7 @@ struct stedma40_platform_data dma40_plat_data = {
49struct platform_device u8500_dma40_device = { 49struct platform_device u8500_dma40_device = {
50 .dev = { 50 .dev = {
51 .platform_data = &dma40_plat_data, 51 .platform_data = &dma40_plat_data,
52 .coherent_dma_mask = DMA_BIT_MASK(32),
52 }, 53 },
53 .name = "dma40", 54 .name = "dma40",
54 .id = 0, 55 .id = 0,
diff --git a/arch/arm/mach-ux500/headsmp.S b/arch/arm/mach-ux500/headsmp.S
index 08da5589bcd8..9cdea049485d 100644
--- a/arch/arm/mach-ux500/headsmp.S
+++ b/arch/arm/mach-ux500/headsmp.S
@@ -11,8 +11,6 @@
11#include <linux/linkage.h> 11#include <linux/linkage.h>
12#include <linux/init.h> 12#include <linux/init.h>
13 13
14 __INIT
15
16/* 14/*
17 * U8500 specific entry point for secondary CPUs. 15 * U8500 specific entry point for secondary CPUs.
18 */ 16 */
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
deleted file mode 100644
index 062c7acf4576..000000000000
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ /dev/null
@@ -1,746 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_PINS_DB8500_H
9#define __MACH_PINS_DB8500_H
10
11/*
12 * TODO: Eventually encode all non-board specific pull up/down configuration
13 * here.
14 */
15
16#define GPIO0_GPIO PIN_CFG(0, GPIO)
17#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
18#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
19#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
20
21#define GPIO1_GPIO PIN_CFG(1, GPIO)
22#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
23#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
24#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
25
26#define GPIO2_GPIO PIN_CFG(2, GPIO)
27#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
28#define GPIO2_NONE PIN_CFG(2, ALT_B)
29#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
30
31#define GPIO3_GPIO PIN_CFG(3, GPIO)
32#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
33#define GPIO3_NONE PIN_CFG(3, ALT_B)
34#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
35
36#define GPIO4_GPIO PIN_CFG(4, GPIO)
37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
38#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
40
41#define GPIO5_GPIO PIN_CFG(5, GPIO)
42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
43#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
45
46#define GPIO6_GPIO PIN_CFG(6, GPIO)
47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
48#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
50
51#define GPIO7_GPIO PIN_CFG(7, GPIO)
52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
53#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
55
56#define GPIO8_GPIO PIN_CFG(8, GPIO)
57#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
58#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
59
60#define GPIO9_GPIO PIN_CFG(9, GPIO)
61#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
62#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
63
64#define GPIO10_GPIO PIN_CFG(10, GPIO)
65#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
66#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
68
69#define GPIO11_GPIO PIN_CFG(11, GPIO)
70#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
71#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
73
74#define GPIO12_GPIO PIN_CFG(12, GPIO)
75#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
76#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
77
78#define GPIO13_GPIO PIN_CFG(13, GPIO)
79#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
80
81#define GPIO14_GPIO PIN_CFG(14, GPIO)
82#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
83
84#define GPIO15_GPIO PIN_CFG(15, GPIO)
85#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
86#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
87
88#define GPIO16_GPIO PIN_CFG(16, GPIO)
89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
90#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
92
93#define GPIO17_GPIO PIN_CFG(17, GPIO)
94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
95#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97
98#define GPIO18_GPIO PIN_CFG(18, GPIO)
99#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP)
100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
102
103#define GPIO19_GPIO PIN_CFG(19, GPIO)
104#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP)
105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
107
108#define GPIO20_GPIO PIN_CFG(20, GPIO)
109#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP)
110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
112
113#define GPIO21_GPIO PIN_CFG(21, GPIO)
114#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP)
115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
117
118#define GPIO22_GPIO PIN_CFG(22, GPIO)
119#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP)
120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
122
123#define GPIO23_GPIO PIN_CFG(23, GPIO)
124#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP)
125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
127
128#define GPIO24_GPIO PIN_CFG(24, GPIO)
129#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP)
130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
131#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
132
133#define GPIO25_GPIO PIN_CFG(25, GPIO)
134#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP)
135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
137
138#define GPIO26_GPIO PIN_CFG(26, GPIO)
139#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP)
140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
142
143#define GPIO27_GPIO PIN_CFG(27, GPIO)
144#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP)
145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
147
148#define GPIO28_GPIO PIN_CFG(28, GPIO)
149#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP)
150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
152
153#define GPIO29_GPIO PIN_CFG(29, GPIO)
154#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
155#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
156#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
157
158#define GPIO30_GPIO PIN_CFG(30, GPIO)
159#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
160#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
161#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
162
163#define GPIO31_GPIO PIN_CFG(31, GPIO)
164#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
165#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
166#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
167
168#define GPIO32_GPIO PIN_CFG(32, GPIO)
169#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
170#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
171#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
172
173#define GPIO33_GPIO PIN_CFG(33, GPIO)
174#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
175#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
176#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
177
178#define GPIO34_GPIO PIN_CFG(34, GPIO)
179#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
180#define GPIO34_NONE PIN_CFG(34, ALT_B)
181#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
182
183#define GPIO35_GPIO PIN_CFG(35, GPIO)
184#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
185#define GPIO35_NONE PIN_CFG(35, ALT_B)
186#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
187
188#define GPIO36_GPIO PIN_CFG(36, GPIO)
189#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
190#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
191#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
192
193#define GPIO64_GPIO PIN_CFG(64, GPIO)
194#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
195#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
196#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
197
198#define GPIO65_GPIO PIN_CFG(65, GPIO)
199#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
200#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
201#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
202
203#define GPIO66_GPIO PIN_CFG(66, GPIO)
204#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
205#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
206#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
207
208#define GPIO67_GPIO PIN_CFG(67, GPIO)
209#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
210#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
211#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
212
213#define GPIO68_GPIO PIN_CFG(68, GPIO)
214#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
215#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
216#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
217
218#define GPIO69_GPIO PIN_CFG(69, GPIO)
219#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
220#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
221#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
222
223#define GPIO70_GPIO PIN_CFG(70, GPIO)
224#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
225#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
226#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
227
228#define GPIO71_GPIO PIN_CFG(71, GPIO)
229#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
230#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
231#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
232
233#define GPIO72_GPIO PIN_CFG(72, GPIO)
234#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
235#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
236#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
237
238#define GPIO73_GPIO PIN_CFG(73, GPIO)
239#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
240#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
241#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
242
243#define GPIO74_GPIO PIN_CFG(74, GPIO)
244#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
245#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
246#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
247
248#define GPIO75_GPIO PIN_CFG(75, GPIO)
249#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
250#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
251#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
252
253#define GPIO76_GPIO PIN_CFG(76, GPIO)
254#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
255#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
256#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
257
258#define GPIO77_GPIO PIN_CFG(77, GPIO)
259#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
260#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
261#define GPIO77_NONE PIN_CFG(77, ALT_C)
262
263#define GPIO78_GPIO PIN_CFG(78, GPIO)
264#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
265#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
266#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
267
268#define GPIO79_GPIO PIN_CFG(79, GPIO)
269#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
270#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
271#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
272
273#define GPIO80_GPIO PIN_CFG(80, GPIO)
274#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
275#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
276#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
277
278#define GPIO81_GPIO PIN_CFG(81, GPIO)
279#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
280#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
281#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
282
283#define GPIO82_GPIO PIN_CFG(82, GPIO)
284#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
285#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
286
287#define GPIO83_GPIO PIN_CFG(83, GPIO)
288#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
289#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
290
291#define GPIO84_GPIO PIN_CFG(84, GPIO)
292#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
293#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
294
295#define GPIO85_GPIO PIN_CFG(85, GPIO)
296#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
297#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
298
299#define GPIO86_GPIO PIN_CFG(86, GPIO)
300#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
301#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
302#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
303
304#define GPIO87_GPIO PIN_CFG(87, GPIO)
305#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
306#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
307#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
308
309#define GPIO88_GPIO PIN_CFG(88, GPIO)
310#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
311#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
312#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
313
314#define GPIO89_GPIO PIN_CFG(89, GPIO)
315#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
316#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
317#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
318
319#define GPIO90_GPIO PIN_CFG(90, GPIO)
320#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
321#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
322#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
323
324#define GPIO91_GPIO PIN_CFG(91, GPIO)
325#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
326#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
327#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
328
329#define GPIO92_GPIO PIN_CFG(92, GPIO)
330#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
331#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
332#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
333
334#define GPIO93_GPIO PIN_CFG(93, GPIO)
335#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
336#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
337#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
338
339#define GPIO94_GPIO PIN_CFG(94, GPIO)
340#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
341#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
342#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
343
344#define GPIO95_GPIO PIN_CFG(95, GPIO)
345#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
346#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
347#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
348
349#define GPIO96_GPIO PIN_CFG(96, GPIO)
350#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
351#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
352#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
353
354#define GPIO97_GPIO PIN_CFG(97, GPIO)
355#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
356#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
358
359#define GPIO128_GPIO PIN_CFG(128, GPIO)
360#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP)
361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
362
363#define GPIO129_GPIO PIN_CFG(129, GPIO)
364#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP)
365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
366
367#define GPIO130_GPIO PIN_CFG(130, GPIO)
368#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP)
369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
371
372#define GPIO131_GPIO PIN_CFG(131, GPIO)
373#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP)
374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
375
376#define GPIO132_GPIO PIN_CFG(132, GPIO)
377#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP)
378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
379
380#define GPIO133_GPIO PIN_CFG(133, GPIO)
381#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP)
382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
383
384#define GPIO134_GPIO PIN_CFG(134, GPIO)
385#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP)
386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
387
388#define GPIO135_GPIO PIN_CFG(135, GPIO)
389#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP)
390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
391
392#define GPIO136_GPIO PIN_CFG(136, GPIO)
393#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP)
394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
395
396#define GPIO137_GPIO PIN_CFG(137, GPIO)
397#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP)
398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
399
400#define GPIO138_GPIO PIN_CFG(138, GPIO)
401#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP)
402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
403
404#define GPIO139_GPIO PIN_CFG(139, GPIO)
405#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
406#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
407#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
408
409#define GPIO140_GPIO PIN_CFG(140, GPIO)
410#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
411#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
412#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
413
414#define GPIO141_GPIO PIN_CFG(141, GPIO)
415#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
416#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
417#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
418
419#define GPIO142_GPIO PIN_CFG(142, GPIO)
420#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
421#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
422#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
423
424#define GPIO143_GPIO PIN_CFG(143, GPIO)
425#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
426
427#define GPIO144_GPIO PIN_CFG(144, GPIO)
428#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
429
430#define GPIO145_GPIO PIN_CFG(145, GPIO)
431#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
432
433#define GPIO146_GPIO PIN_CFG(146, GPIO)
434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
435
436#define GPIO147_GPIO PIN_CFG(147, GPIO)
437#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
438
439#define GPIO148_GPIO PIN_CFG(148, GPIO)
440#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
441
442#define GPIO149_GPIO PIN_CFG(149, GPIO)
443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
444#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
445#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
446
447#define GPIO150_GPIO PIN_CFG(150, GPIO)
448#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
449#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
450
451#define GPIO151_GPIO PIN_CFG(151, GPIO)
452#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
453#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
454#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
455
456#define GPIO152_GPIO PIN_CFG(152, GPIO)
457#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
458#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
460
461#define GPIO153_GPIO PIN_CFG(153, GPIO)
462#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
465
466#define GPIO154_GPIO PIN_CFG(154, GPIO)
467#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
470
471#define GPIO155_GPIO PIN_CFG(155, GPIO)
472#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
475
476#define GPIO156_GPIO PIN_CFG(156, GPIO)
477#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
480
481#define GPIO157_GPIO PIN_CFG(157, GPIO)
482#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
485
486#define GPIO158_GPIO PIN_CFG(158, GPIO)
487#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
490
491#define GPIO159_GPIO PIN_CFG(159, GPIO)
492#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
495
496#define GPIO160_GPIO PIN_CFG(160, GPIO)
497#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
499#define GPIO160_NONE PIN_CFG(160, ALT_C)
500
501#define GPIO161_GPIO PIN_CFG(161, GPIO)
502#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
505
506#define GPIO162_GPIO PIN_CFG(162, GPIO)
507#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
510
511#define GPIO163_GPIO PIN_CFG(163, GPIO)
512#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
515
516#define GPIO164_GPIO PIN_CFG(164, GPIO)
517#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
520
521#define GPIO165_GPIO PIN_CFG(165, GPIO)
522#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
525
526#define GPIO166_GPIO PIN_CFG(166, GPIO)
527#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
530
531#define GPIO167_GPIO PIN_CFG(167, GPIO)
532#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
535
536#define GPIO168_GPIO PIN_CFG(168, GPIO)
537#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
539#define GPIO168_NONE PIN_CFG(168, ALT_C)
540
541#define GPIO169_GPIO PIN_CFG(169, GPIO)
542#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
543#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
544#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
545
546#define GPIO170_GPIO PIN_CFG(170, GPIO)
547#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
548#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
549#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
550
551#define GPIO171_GPIO PIN_CFG(171, GPIO)
552#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
553#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
554#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
555
556#define GPIO192_GPIO PIN_CFG(192, GPIO)
557#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
558
559#define GPIO193_GPIO PIN_CFG(193, GPIO)
560#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
561
562#define GPIO194_GPIO PIN_CFG(194, GPIO)
563#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
564
565#define GPIO195_GPIO PIN_CFG(195, GPIO)
566#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
567
568#define GPIO196_GPIO PIN_CFG(196, GPIO)
569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
570
571#define GPIO197_GPIO PIN_CFG(197, GPIO)
572#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP)
573
574#define GPIO198_GPIO PIN_CFG(198, GPIO)
575#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP)
576
577#define GPIO199_GPIO PIN_CFG(199, GPIO)
578#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP)
579
580#define GPIO200_GPIO PIN_CFG(200, GPIO)
581#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP)
582
583#define GPIO201_GPIO PIN_CFG(201, GPIO)
584#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP)
585
586#define GPIO202_GPIO PIN_CFG(202, GPIO)
587#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP)
588#define GPIO202_PWL PIN_CFG(202, ALT_B)
589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
590
591#define GPIO203_GPIO PIN_CFG(203, GPIO)
592#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP)
593
594#define GPIO204_GPIO PIN_CFG(204, GPIO)
595#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP)
596
597#define GPIO205_GPIO PIN_CFG(205, GPIO)
598#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP)
599
600#define GPIO206_GPIO PIN_CFG(206, GPIO)
601#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP)
602
603#define GPIO207_GPIO PIN_CFG(207, GPIO)
604#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP)
605
606#define GPIO208_GPIO PIN_CFG(208, GPIO)
607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
608
609#define GPIO209_GPIO PIN_CFG(209, GPIO)
610#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
611#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
612
613#define GPIO210_GPIO PIN_CFG(210, GPIO)
614#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
615
616#define GPIO211_GPIO PIN_CFG(211, GPIO)
617#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
618
619#define GPIO212_GPIO PIN_CFG(212, GPIO)
620#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
621#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
622
623#define GPIO213_GPIO PIN_CFG(213, GPIO)
624#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
625#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
626
627#define GPIO214_GPIO PIN_CFG(214, GPIO)
628#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
629#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
630
631#define GPIO215_GPIO PIN_CFG(215, GPIO)
632#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
633#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
634#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
635#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C)
636
637#define GPIO216_GPIO PIN_CFG(216, GPIO)
638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
640#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
642
643#define GPIO217_GPIO PIN_CFG(217, GPIO)
644#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
645#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
646#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
647#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C)
648
649#define GPIO218_GPIO PIN_CFG(218, GPIO)
650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
652#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
654
655#define GPIO219_GPIO PIN_CFG(219, GPIO)
656#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
657#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
658
659#define GPIO220_GPIO PIN_CFG(220, GPIO)
660#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
661#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
662#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
663
664#define GPIO221_GPIO PIN_CFG(221, GPIO)
665#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
666#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
667
668#define GPIO222_GPIO PIN_CFG(222, GPIO)
669#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
670#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
671
672#define GPIO223_GPIO PIN_CFG(223, GPIO)
673#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
674#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
675#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
676
677#define GPIO224_GPIO PIN_CFG(224, GPIO)
678#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
679#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
680#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
681
682#define GPIO225_GPIO PIN_CFG(225, GPIO)
683#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
684#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
685#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
686
687#define GPIO226_GPIO PIN_CFG(226, GPIO)
688#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
689#define GPIO226_PWL PIN_CFG(226, ALT_B)
690#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
691
692#define GPIO227_GPIO PIN_CFG(227, GPIO)
693#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
694
695#define GPIO228_GPIO PIN_CFG(228, GPIO)
696#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
697
698#define GPIO229_GPIO PIN_CFG(229, GPIO)
699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
700#define GPIO229_PWL PIN_CFG(229, ALT_B)
701#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
702
703#define GPIO230_GPIO PIN_CFG(230, GPIO)
704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
705#define GPIO230_PWL PIN_CFG(230, ALT_B)
706#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
707
708#define GPIO256_GPIO PIN_CFG(256, GPIO)
709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
710
711#define GPIO257_GPIO PIN_CFG(257, GPIO)
712#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
713
714#define GPIO258_GPIO PIN_CFG(258, GPIO)
715#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
716#define GPIO258_NONE PIN_CFG(258, ALT_B)
717#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
718
719#define GPIO259_GPIO PIN_CFG(259, GPIO)
720#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
721
722#define GPIO260_GPIO PIN_CFG(260, GPIO)
723#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
724
725#define GPIO261_GPIO PIN_CFG(261, GPIO)
726#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
727
728#define GPIO262_GPIO PIN_CFG(262, GPIO)
729#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
730
731#define GPIO263_GPIO PIN_CFG(263, GPIO)
732#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
733
734#define GPIO264_GPIO PIN_CFG(264, GPIO)
735#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
736
737#define GPIO265_GPIO PIN_CFG(265, GPIO)
738#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
739
740#define GPIO266_GPIO PIN_CFG(266, GPIO)
741#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
742
743#define GPIO267_GPIO PIN_CFG(267, GPIO)
744#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
745
746#endif
diff --git a/arch/arm/mach-ux500/setup.h b/arch/arm/mach-ux500/setup.h
index cad3ca86c540..656324aad18e 100644
--- a/arch/arm/mach-ux500/setup.h
+++ b/arch/arm/mach-ux500/setup.h
@@ -11,10 +11,13 @@
11#ifndef __ASM_ARCH_SETUP_H 11#ifndef __ASM_ARCH_SETUP_H
12#define __ASM_ARCH_SETUP_H 12#define __ASM_ARCH_SETUP_H
13 13
14#include <asm/mach/arch.h>
14#include <asm/mach/time.h> 15#include <asm/mach/time.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/mfd/abx500/ab8500.h> 17#include <linux/mfd/abx500/ab8500.h>
17 18
19void ux500_restart(enum reboot_mode mode, const char *cmd);
20
18void __init ux500_map_io(void); 21void __init ux500_map_io(void);
19extern void __init u8500_map_io(void); 22extern void __init u8500_map_io(void);
20 23
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index b8bbabec6310..365795447804 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -10,7 +10,7 @@ config ARCH_VEXPRESS
10 select CPU_V7 10 select CPU_V7
11 select GENERIC_CLOCKEVENTS 11 select GENERIC_CLOCKEVENTS
12 select HAVE_ARM_SCU if SMP 12 select HAVE_ARM_SCU if SMP
13 select HAVE_ARM_TWD if LOCAL_TIMERS 13 select HAVE_ARM_TWD if SMP
14 select HAVE_CLK 14 select HAVE_CLK
15 select HAVE_PATA_PLATFORM 15 select HAVE_PATA_PLATFORM
16 select HAVE_SMP 16 select HAVE_SMP
@@ -66,4 +66,12 @@ config ARCH_VEXPRESS_DCSCB
66 This is needed to provide CPU and cluster power management 66 This is needed to provide CPU and cluster power management
67 on RTSM implementing big.LITTLE. 67 on RTSM implementing big.LITTLE.
68 68
69config ARCH_VEXPRESS_TC2_PM
70 bool "Versatile Express TC2 power management"
71 depends on MCPM
72 select ARM_CCI
73 help
74 Support for CPU and cluster power management on Versatile Express
75 with a TC2 (A15x2 A7x3) big.LITTLE core tile.
76
69endmenu 77endmenu
diff --git a/arch/arm/mach-vexpress/Makefile b/arch/arm/mach-vexpress/Makefile
index 48ba89a8149f..36ea8247123a 100644
--- a/arch/arm/mach-vexpress/Makefile
+++ b/arch/arm/mach-vexpress/Makefile
@@ -7,5 +7,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
7obj-y := v2m.o 7obj-y := v2m.o
8obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o 8obj-$(CONFIG_ARCH_VEXPRESS_CA9X4) += ct-ca9x4.o
9obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o 9obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o
10obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o spc.o
10obj-$(CONFIG_SMP) += platsmp.o 11obj-$(CONFIG_SMP) += platsmp.o
11obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 12obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-vexpress/dcscb.c b/arch/arm/mach-vexpress/dcscb.c
index 16d57a8a9d5a..3a6384c6c435 100644
--- a/arch/arm/mach-vexpress/dcscb.c
+++ b/arch/arm/mach-vexpress/dcscb.c
@@ -136,14 +136,35 @@ static void dcscb_power_down(void)
136 /* 136 /*
137 * Flush all cache levels for this cluster. 137 * Flush all cache levels for this cluster.
138 * 138 *
139 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need 139 * To do so we do:
140 * a preliminary flush here for those CPUs. At least, that's 140 * - Clear the SCTLR.C bit to prevent further cache allocations
141 * the theory -- without the extra flush, Linux explodes on 141 * - Flush the whole cache
142 * RTSM (to be investigated). 142 * - Clear the ACTLR "SMP" bit to disable local coherency
143 *
144 * Let's do it in the safest possible way i.e. with
145 * no memory access within the following sequence
146 * including to the stack.
147 *
148 * Note: fp is preserved to the stack explicitly prior doing
149 * this since adding it to the clobber list is incompatible
150 * with having CONFIG_FRAME_POINTER=y.
143 */ 151 */
144 flush_cache_all(); 152 asm volatile(
145 set_cr(get_cr() & ~CR_C); 153 "str fp, [sp, #-4]! \n\t"
146 flush_cache_all(); 154 "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
155 "bic r0, r0, #"__stringify(CR_C)" \n\t"
156 "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
157 "isb \n\t"
158 "bl v7_flush_dcache_all \n\t"
159 "clrex \n\t"
160 "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
161 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
162 "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
163 "isb \n\t"
164 "dsb \n\t"
165 "ldr fp, [sp], #4"
166 : : : "r0","r1","r2","r3","r4","r5","r6","r7",
167 "r9","r10","lr","memory");
147 168
148 /* 169 /*
149 * This is a harmless no-op. On platforms with a real 170 * This is a harmless no-op. On platforms with a real
@@ -152,9 +173,6 @@ static void dcscb_power_down(void)
152 */ 173 */
153 outer_flush_all(); 174 outer_flush_all();
154 175
155 /* Disable local coherency by clearing the ACTLR "SMP" bit: */
156 set_auxcr(get_auxcr() & ~(1 << 6));
157
158 /* 176 /*
159 * Disable cluster-level coherency by masking 177 * Disable cluster-level coherency by masking
160 * incoming snoops and DVM messages: 178 * incoming snoops and DVM messages:
@@ -167,18 +185,24 @@ static void dcscb_power_down(void)
167 185
168 /* 186 /*
169 * Flush the local CPU cache. 187 * Flush the local CPU cache.
170 * 188 * Let's do it in the safest possible way as above.
171 * A15/A7 can hit in the cache with SCTLR.C=0, so we don't need
172 * a preliminary flush here for those CPUs. At least, that's
173 * the theory -- without the extra flush, Linux explodes on
174 * RTSM (to be investigated).
175 */ 189 */
176 flush_cache_louis(); 190 asm volatile(
177 set_cr(get_cr() & ~CR_C); 191 "str fp, [sp, #-4]! \n\t"
178 flush_cache_louis(); 192 "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
179 193 "bic r0, r0, #"__stringify(CR_C)" \n\t"
180 /* Disable local coherency by clearing the ACTLR "SMP" bit: */ 194 "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
181 set_auxcr(get_auxcr() & ~(1 << 6)); 195 "isb \n\t"
196 "bl v7_flush_dcache_louis \n\t"
197 "clrex \n\t"
198 "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
199 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
200 "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
201 "isb \n\t"
202 "dsb \n\t"
203 "ldr fp, [sp], #4"
204 : : : "r0","r1","r2","r3","r4","r5","r6","r7",
205 "r9","r10","lr","memory");
182 } 206 }
183 207
184 __mcpm_cpu_down(cpu, cluster); 208 __mcpm_cpu_down(cpu, cluster);
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
new file mode 100644
index 000000000000..eefb029197ca
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.c
@@ -0,0 +1,180 @@
1/*
2 * Versatile Express Serial Power Controller (SPC) support
3 *
4 * Copyright (C) 2013 ARM Ltd.
5 *
6 * Authors: Sudeep KarkadaNagesha <sudeep.karkadanagesha@arm.com>
7 * Achin Gupta <achin.gupta@arm.com>
8 * Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
15 * kind, whether express or implied; without even the implied warranty
16 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19
20#include <linux/err.h>
21#include <linux/io.h>
22#include <linux/slab.h>
23
24#include <asm/cacheflush.h>
25
26#define SPCLOG "vexpress-spc: "
27
28/* SPC wake-up IRQs status and mask */
29#define WAKE_INT_MASK 0x24
30#define WAKE_INT_RAW 0x28
31#define WAKE_INT_STAT 0x2c
32/* SPC power down registers */
33#define A15_PWRDN_EN 0x30
34#define A7_PWRDN_EN 0x34
35/* SPC per-CPU mailboxes */
36#define A15_BX_ADDR0 0x68
37#define A7_BX_ADDR0 0x78
38
39/* wake-up interrupt masks */
40#define GBL_WAKEUP_INT_MSK (0x3 << 10)
41
42/* TC2 static dual-cluster configuration */
43#define MAX_CLUSTERS 2
44
45struct ve_spc_drvdata {
46 void __iomem *baseaddr;
47 /*
48 * A15s cluster identifier
49 * It corresponds to A15 processors MPIDR[15:8] bitfield
50 */
51 u32 a15_clusid;
52};
53
54static struct ve_spc_drvdata *info;
55
56static inline bool cluster_is_a15(u32 cluster)
57{
58 return cluster == info->a15_clusid;
59}
60
61/**
62 * ve_spc_global_wakeup_irq()
63 *
64 * Function to set/clear global wakeup IRQs. Not protected by locking since
65 * it might be used in code paths where normal cacheable locks are not
66 * working. Locking must be provided by the caller to ensure atomicity.
67 *
68 * @set: if true, global wake-up IRQs are set, if false they are cleared
69 */
70void ve_spc_global_wakeup_irq(bool set)
71{
72 u32 reg;
73
74 reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
75
76 if (set)
77 reg |= GBL_WAKEUP_INT_MSK;
78 else
79 reg &= ~GBL_WAKEUP_INT_MSK;
80
81 writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
82}
83
84/**
85 * ve_spc_cpu_wakeup_irq()
86 *
87 * Function to set/clear per-CPU wake-up IRQs. Not protected by locking since
88 * it might be used in code paths where normal cacheable locks are not
89 * working. Locking must be provided by the caller to ensure atomicity.
90 *
91 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
92 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
93 * @set: if true, wake-up IRQs are set, if false they are cleared
94 */
95void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
96{
97 u32 mask, reg;
98
99 if (cluster >= MAX_CLUSTERS)
100 return;
101
102 mask = 1 << cpu;
103
104 if (!cluster_is_a15(cluster))
105 mask <<= 4;
106
107 reg = readl_relaxed(info->baseaddr + WAKE_INT_MASK);
108
109 if (set)
110 reg |= mask;
111 else
112 reg &= ~mask;
113
114 writel_relaxed(reg, info->baseaddr + WAKE_INT_MASK);
115}
116
117/**
118 * ve_spc_set_resume_addr() - set the jump address used for warm boot
119 *
120 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
121 * @cpu: mpidr[7:0] bitfield describing cpu affinity level
122 * @addr: physical resume address
123 */
124void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr)
125{
126 void __iomem *baseaddr;
127
128 if (cluster >= MAX_CLUSTERS)
129 return;
130
131 if (cluster_is_a15(cluster))
132 baseaddr = info->baseaddr + A15_BX_ADDR0 + (cpu << 2);
133 else
134 baseaddr = info->baseaddr + A7_BX_ADDR0 + (cpu << 2);
135
136 writel_relaxed(addr, baseaddr);
137}
138
139/**
140 * ve_spc_powerdown()
141 *
142 * Function to enable/disable cluster powerdown. Not protected by locking
143 * since it might be used in code paths where normal cacheable locks are not
144 * working. Locking must be provided by the caller to ensure atomicity.
145 *
146 * @cluster: mpidr[15:8] bitfield describing cluster affinity level
147 * @enable: if true enables powerdown, if false disables it
148 */
149void ve_spc_powerdown(u32 cluster, bool enable)
150{
151 u32 pwdrn_reg;
152
153 if (cluster >= MAX_CLUSTERS)
154 return;
155
156 pwdrn_reg = cluster_is_a15(cluster) ? A15_PWRDN_EN : A7_PWRDN_EN;
157 writel_relaxed(enable, info->baseaddr + pwdrn_reg);
158}
159
160int __init ve_spc_init(void __iomem *baseaddr, u32 a15_clusid)
161{
162 info = kzalloc(sizeof(*info), GFP_KERNEL);
163 if (!info) {
164 pr_err(SPCLOG "unable to allocate mem\n");
165 return -ENOMEM;
166 }
167
168 info->baseaddr = baseaddr;
169 info->a15_clusid = a15_clusid;
170
171 /*
172 * Multi-cluster systems may need this data when non-coherent, during
173 * cluster power-up/power-down. Make sure driver info reaches main
174 * memory.
175 */
176 sync_cache_w(info);
177 sync_cache_w(&info);
178
179 return 0;
180}
diff --git a/arch/arm/mach-vexpress/spc.h b/arch/arm/mach-vexpress/spc.h
new file mode 100644
index 000000000000..5f7e4a446a17
--- /dev/null
+++ b/arch/arm/mach-vexpress/spc.h
@@ -0,0 +1,24 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14
15#ifndef __SPC_H_
16#define __SPC_H_
17
18int __init ve_spc_init(void __iomem *base, u32 a15_clusid);
19void ve_spc_global_wakeup_irq(bool set);
20void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set);
21void ve_spc_set_resume_addr(u32 cluster, u32 cpu, u32 addr);
22void ve_spc_powerdown(u32 cluster, bool enable);
23
24#endif
diff --git a/arch/arm/mach-vexpress/tc2_pm.c b/arch/arm/mach-vexpress/tc2_pm.c
new file mode 100644
index 000000000000..7aeb5d60e484
--- /dev/null
+++ b/arch/arm/mach-vexpress/tc2_pm.c
@@ -0,0 +1,354 @@
1/*
2 * arch/arm/mach-vexpress/tc2_pm.c - TC2 power management support
3 *
4 * Created by: Nicolas Pitre, October 2012
5 * Copyright: (C) 2012-2013 Linaro Limited
6 *
7 * Some portions of this file were originally written by Achin Gupta
8 * Copyright: (C) 2012 ARM Limited
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/kernel.h>
18#include <linux/of_address.h>
19#include <linux/spinlock.h>
20#include <linux/errno.h>
21#include <linux/irqchip/arm-gic.h>
22
23#include <asm/mcpm.h>
24#include <asm/proc-fns.h>
25#include <asm/cacheflush.h>
26#include <asm/cputype.h>
27#include <asm/cp15.h>
28
29#include <linux/arm-cci.h>
30
31#include "spc.h"
32
33/* SCC conf registers */
34#define A15_CONF 0x400
35#define A7_CONF 0x500
36#define SYS_INFO 0x700
37#define SPC_BASE 0xb00
38
39/*
40 * We can't use regular spinlocks. In the switcher case, it is possible
41 * for an outbound CPU to call power_down() after its inbound counterpart
42 * is already live using the same logical CPU number which trips lockdep
43 * debugging.
44 */
45static arch_spinlock_t tc2_pm_lock = __ARCH_SPIN_LOCK_UNLOCKED;
46
47#define TC2_CLUSTERS 2
48#define TC2_MAX_CPUS_PER_CLUSTER 3
49
50static unsigned int tc2_nr_cpus[TC2_CLUSTERS];
51
52/* Keep per-cpu usage count to cope with unordered up/down requests */
53static int tc2_pm_use_count[TC2_MAX_CPUS_PER_CLUSTER][TC2_CLUSTERS];
54
55#define tc2_cluster_unused(cluster) \
56 (!tc2_pm_use_count[0][cluster] && \
57 !tc2_pm_use_count[1][cluster] && \
58 !tc2_pm_use_count[2][cluster])
59
60static int tc2_pm_power_up(unsigned int cpu, unsigned int cluster)
61{
62 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
63 if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster])
64 return -EINVAL;
65
66 /*
67 * Since this is called with IRQs enabled, and no arch_spin_lock_irq
68 * variant exists, we need to disable IRQs manually here.
69 */
70 local_irq_disable();
71 arch_spin_lock(&tc2_pm_lock);
72
73 if (tc2_cluster_unused(cluster))
74 ve_spc_powerdown(cluster, false);
75
76 tc2_pm_use_count[cpu][cluster]++;
77 if (tc2_pm_use_count[cpu][cluster] == 1) {
78 ve_spc_set_resume_addr(cluster, cpu,
79 virt_to_phys(mcpm_entry_point));
80 ve_spc_cpu_wakeup_irq(cluster, cpu, true);
81 } else if (tc2_pm_use_count[cpu][cluster] != 2) {
82 /*
83 * The only possible values are:
84 * 0 = CPU down
85 * 1 = CPU (still) up
86 * 2 = CPU requested to be up before it had a chance
87 * to actually make itself down.
88 * Any other value is a bug.
89 */
90 BUG();
91 }
92
93 arch_spin_unlock(&tc2_pm_lock);
94 local_irq_enable();
95
96 return 0;
97}
98
99static void tc2_pm_down(u64 residency)
100{
101 unsigned int mpidr, cpu, cluster;
102 bool last_man = false, skip_wfi = false;
103
104 mpidr = read_cpuid_mpidr();
105 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
106 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
107
108 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
109 BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
110
111 __mcpm_cpu_going_down(cpu, cluster);
112
113 arch_spin_lock(&tc2_pm_lock);
114 BUG_ON(__mcpm_cluster_state(cluster) != CLUSTER_UP);
115 tc2_pm_use_count[cpu][cluster]--;
116 if (tc2_pm_use_count[cpu][cluster] == 0) {
117 ve_spc_cpu_wakeup_irq(cluster, cpu, true);
118 if (tc2_cluster_unused(cluster)) {
119 ve_spc_powerdown(cluster, true);
120 ve_spc_global_wakeup_irq(true);
121 last_man = true;
122 }
123 } else if (tc2_pm_use_count[cpu][cluster] == 1) {
124 /*
125 * A power_up request went ahead of us.
126 * Even if we do not want to shut this CPU down,
127 * the caller expects a certain state as if the WFI
128 * was aborted. So let's continue with cache cleaning.
129 */
130 skip_wfi = true;
131 } else
132 BUG();
133
134 if (last_man && __mcpm_outbound_enter_critical(cpu, cluster)) {
135 arch_spin_unlock(&tc2_pm_lock);
136
137 if (read_cpuid_part_number() == ARM_CPU_PART_CORTEX_A15) {
138 /*
139 * On the Cortex-A15 we need to disable
140 * L2 prefetching before flushing the cache.
141 */
142 asm volatile(
143 "mcr p15, 1, %0, c15, c0, 3 \n\t"
144 "isb \n\t"
145 "dsb "
146 : : "r" (0x400) );
147 }
148
149 /*
150 * We need to disable and flush the whole (L1 and L2) cache.
151 * Let's do it in the safest possible way i.e. with
152 * no memory access within the following sequence
153 * including the stack.
154 *
155 * Note: fp is preserved to the stack explicitly prior doing
156 * this since adding it to the clobber list is incompatible
157 * with having CONFIG_FRAME_POINTER=y.
158 */
159 asm volatile(
160 "str fp, [sp, #-4]! \n\t"
161 "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
162 "bic r0, r0, #"__stringify(CR_C)" \n\t"
163 "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
164 "isb \n\t"
165 "bl v7_flush_dcache_all \n\t"
166 "clrex \n\t"
167 "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
168 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
169 "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
170 "isb \n\t"
171 "dsb \n\t"
172 "ldr fp, [sp], #4"
173 : : : "r0","r1","r2","r3","r4","r5","r6","r7",
174 "r9","r10","lr","memory");
175
176 cci_disable_port_by_cpu(mpidr);
177
178 __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
179 } else {
180 /*
181 * If last man then undo any setup done previously.
182 */
183 if (last_man) {
184 ve_spc_powerdown(cluster, false);
185 ve_spc_global_wakeup_irq(false);
186 }
187
188 arch_spin_unlock(&tc2_pm_lock);
189
190 /*
191 * We need to disable and flush only the L1 cache.
192 * Let's do it in the safest possible way as above.
193 */
194 asm volatile(
195 "str fp, [sp, #-4]! \n\t"
196 "mrc p15, 0, r0, c1, c0, 0 @ get CR \n\t"
197 "bic r0, r0, #"__stringify(CR_C)" \n\t"
198 "mcr p15, 0, r0, c1, c0, 0 @ set CR \n\t"
199 "isb \n\t"
200 "bl v7_flush_dcache_louis \n\t"
201 "clrex \n\t"
202 "mrc p15, 0, r0, c1, c0, 1 @ get AUXCR \n\t"
203 "bic r0, r0, #(1 << 6) @ disable local coherency \n\t"
204 "mcr p15, 0, r0, c1, c0, 1 @ set AUXCR \n\t"
205 "isb \n\t"
206 "dsb \n\t"
207 "ldr fp, [sp], #4"
208 : : : "r0","r1","r2","r3","r4","r5","r6","r7",
209 "r9","r10","lr","memory");
210 }
211
212 __mcpm_cpu_down(cpu, cluster);
213
214 /* Now we are prepared for power-down, do it: */
215 if (!skip_wfi)
216 wfi();
217
218 /* Not dead at this point? Let our caller cope. */
219}
220
221static void tc2_pm_power_down(void)
222{
223 tc2_pm_down(0);
224}
225
226static void tc2_pm_suspend(u64 residency)
227{
228 unsigned int mpidr, cpu, cluster;
229
230 mpidr = read_cpuid_mpidr();
231 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
232 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
233 ve_spc_set_resume_addr(cluster, cpu, virt_to_phys(mcpm_entry_point));
234 gic_cpu_if_down();
235 tc2_pm_down(residency);
236}
237
238static void tc2_pm_powered_up(void)
239{
240 unsigned int mpidr, cpu, cluster;
241 unsigned long flags;
242
243 mpidr = read_cpuid_mpidr();
244 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
245 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
246
247 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
248 BUG_ON(cluster >= TC2_CLUSTERS || cpu >= TC2_MAX_CPUS_PER_CLUSTER);
249
250 local_irq_save(flags);
251 arch_spin_lock(&tc2_pm_lock);
252
253 if (tc2_cluster_unused(cluster)) {
254 ve_spc_powerdown(cluster, false);
255 ve_spc_global_wakeup_irq(false);
256 }
257
258 if (!tc2_pm_use_count[cpu][cluster])
259 tc2_pm_use_count[cpu][cluster] = 1;
260
261 ve_spc_cpu_wakeup_irq(cluster, cpu, false);
262 ve_spc_set_resume_addr(cluster, cpu, 0);
263
264 arch_spin_unlock(&tc2_pm_lock);
265 local_irq_restore(flags);
266}
267
268static const struct mcpm_platform_ops tc2_pm_power_ops = {
269 .power_up = tc2_pm_power_up,
270 .power_down = tc2_pm_power_down,
271 .suspend = tc2_pm_suspend,
272 .powered_up = tc2_pm_powered_up,
273};
274
275static bool __init tc2_pm_usage_count_init(void)
276{
277 unsigned int mpidr, cpu, cluster;
278
279 mpidr = read_cpuid_mpidr();
280 cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
281 cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
282
283 pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster);
284 if (cluster >= TC2_CLUSTERS || cpu >= tc2_nr_cpus[cluster]) {
285 pr_err("%s: boot CPU is out of bound!\n", __func__);
286 return false;
287 }
288 tc2_pm_use_count[cpu][cluster] = 1;
289 return true;
290}
291
292/*
293 * Enable cluster-level coherency, in preparation for turning on the MMU.
294 */
295static void __naked tc2_pm_power_up_setup(unsigned int affinity_level)
296{
297 asm volatile (" \n"
298" cmp r0, #1 \n"
299" bxne lr \n"
300" b cci_enable_port_for_self ");
301}
302
303static int __init tc2_pm_init(void)
304{
305 int ret;
306 void __iomem *scc;
307 u32 a15_cluster_id, a7_cluster_id, sys_info;
308 struct device_node *np;
309
310 /*
311 * The power management-related features are hidden behind
312 * SCC registers. We need to extract runtime information like
313 * cluster ids and number of CPUs really available in clusters.
314 */
315 np = of_find_compatible_node(NULL, NULL,
316 "arm,vexpress-scc,v2p-ca15_a7");
317 scc = of_iomap(np, 0);
318 if (!scc)
319 return -ENODEV;
320
321 a15_cluster_id = readl_relaxed(scc + A15_CONF) & 0xf;
322 a7_cluster_id = readl_relaxed(scc + A7_CONF) & 0xf;
323 if (a15_cluster_id >= TC2_CLUSTERS || a7_cluster_id >= TC2_CLUSTERS)
324 return -EINVAL;
325
326 sys_info = readl_relaxed(scc + SYS_INFO);
327 tc2_nr_cpus[a15_cluster_id] = (sys_info >> 16) & 0xf;
328 tc2_nr_cpus[a7_cluster_id] = (sys_info >> 20) & 0xf;
329
330 /*
331 * A subset of the SCC registers is also used to communicate
332 * with the SPC (power controller). We need to be able to
333 * drive it very early in the boot process to power up
334 * processors, so we initialize the SPC driver here.
335 */
336 ret = ve_spc_init(scc + SPC_BASE, a15_cluster_id);
337 if (ret)
338 return ret;
339
340 if (!cci_probed())
341 return -ENODEV;
342
343 if (!tc2_pm_usage_count_init())
344 return -EINVAL;
345
346 ret = mcpm_platform_register(&tc2_pm_power_ops);
347 if (!ret) {
348 mcpm_sync_init(tc2_pm_power_up_setup);
349 pr_info("TC2 power management initialized\n");
350 }
351 return ret;
352}
353
354early_initcall(tc2_pm_init);
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index c1d61f281e68..04f8a4a6e755 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -6,7 +6,7 @@ config ARCH_ZYNQ
6 select CPU_V7 6 select CPU_V7
7 select GENERIC_CLOCKEVENTS 7 select GENERIC_CLOCKEVENTS
8 select HAVE_ARM_SCU if SMP 8 select HAVE_ARM_SCU if SMP
9 select HAVE_ARM_TWD if LOCAL_TIMERS 9 select HAVE_ARM_TWD if SMP
10 select ICST 10 select ICST
11 select MIGHT_HAVE_CACHE_L2X0 11 select MIGHT_HAVE_CACHE_L2X0
12 select USE_OF 12 select USE_OF
diff --git a/arch/arm/mach-zynq/hotplug.c b/arch/arm/mach-zynq/hotplug.c
index c89672bd1de2..5052c70326e4 100644
--- a/arch/arm/mach-zynq/hotplug.c
+++ b/arch/arm/mach-zynq/hotplug.c
@@ -40,44 +40,6 @@ static inline void zynq_cpu_enter_lowpower(void)
40 : "cc"); 40 : "cc");
41} 41}
42 42
43static inline void zynq_cpu_leave_lowpower(void)
44{
45 unsigned int v;
46
47 asm volatile(
48 " mrc p15, 0, %0, c1, c0, 0\n"
49 " orr %0, %0, %1\n"
50 " mcr p15, 0, %0, c1, c0, 0\n"
51 " mrc p15, 0, %0, c1, c0, 1\n"
52 " orr %0, %0, #0x40\n"
53 " mcr p15, 0, %0, c1, c0, 1\n"
54 : "=&r" (v)
55 : "Ir" (CR_C)
56 : "cc");
57}
58
59static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
60{
61 /*
62 * there is no power-control hardware on this platform, so all
63 * we can do is put the core into WFI; this is safe as the calling
64 * code will have already disabled interrupts
65 */
66 for (;;) {
67 dsb();
68 wfi();
69
70 /*
71 * Getting here, means that we have come out of WFI without
72 * having been woken up - this shouldn't happen
73 *
74 * Just note it happening - when we're woken, we can report
75 * its occurrence.
76 */
77 (*spurious)++;
78 }
79}
80
81/* 43/*
82 * platform-specific code to shutdown a CPU 44 * platform-specific code to shutdown a CPU
83 * 45 *
@@ -85,20 +47,13 @@ static inline void zynq_platform_do_lowpower(unsigned int cpu, int *spurious)
85 */ 47 */
86void zynq_platform_cpu_die(unsigned int cpu) 48void zynq_platform_cpu_die(unsigned int cpu)
87{ 49{
88 int spurious = 0;
89
90 /*
91 * we're ready for shutdown now, so do it
92 */
93 zynq_cpu_enter_lowpower(); 50 zynq_cpu_enter_lowpower();
94 zynq_platform_do_lowpower(cpu, &spurious);
95 51
96 /* 52 /*
97 * bring this CPU back into the world of cache 53 * there is no power-control hardware on this platform, so all
98 * coherency, and then restore interrupts 54 * we can do is put the core into WFI; this is safe as the calling
55 * code will have already disabled interrupts
99 */ 56 */
100 zynq_cpu_leave_lowpower(); 57 for (;;)
101 58 cpu_do_idle();
102 if (spurious)
103 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
104} 59}
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 50d008d8f87f..1836d5a34606 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -14,32 +14,21 @@
14 * 02139, USA. 14 * 02139, USA.
15 */ 15 */
16 16
17#include <linux/export.h>
18#include <linux/io.h> 17#include <linux/io.h>
19#include <linux/fs.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_address.h> 18#include <linux/of_address.h>
25#include <linux/uaccess.h>
26#include <linux/platform_device.h>
27#include <linux/slab.h>
28#include <linux/string.h>
29#include <linux/clk/zynq.h> 19#include <linux/clk/zynq.h>
30#include "common.h" 20#include "common.h"
31 21
32#define SLCR_UNLOCK_MAGIC 0xDF0D 22/* register offsets */
33#define SLCR_UNLOCK 0x8 /* SCLR unlock register */ 23#define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */
34
35#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ 24#define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */
25#define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */
26#define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */
36 27
28#define SLCR_UNLOCK_MAGIC 0xDF0D
37#define SLCR_A9_CPU_CLKSTOP 0x10 29#define SLCR_A9_CPU_CLKSTOP 0x10
38#define SLCR_A9_CPU_RST 0x1 30#define SLCR_A9_CPU_RST 0x1
39 31
40#define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */
41#define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */
42
43void __iomem *zynq_slcr_base; 32void __iomem *zynq_slcr_base;
44 33
45/** 34/**
@@ -54,15 +43,15 @@ void zynq_slcr_system_reset(void)
54 * Note that this seems to require raw i/o 43 * Note that this seems to require raw i/o
55 * functions or there's a lockup? 44 * functions or there's a lockup?
56 */ 45 */
57 writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); 46 writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
58 47
59 /* 48 /*
60 * Clear 0x0F000000 bits of reboot status register to workaround 49 * Clear 0x0F000000 bits of reboot status register to workaround
61 * the FSBL not loading the bitstream after soft-reboot 50 * the FSBL not loading the bitstream after soft-reboot
62 * This is a temporary solution until we know more. 51 * This is a temporary solution until we know more.
63 */ 52 */
64 reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); 53 reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
65 writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); 54 writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
66 writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); 55 writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
67} 56}
68 57
@@ -72,11 +61,11 @@ void zynq_slcr_system_reset(void)
72 */ 61 */
73void zynq_slcr_cpu_start(int cpu) 62void zynq_slcr_cpu_start(int cpu)
74{ 63{
75 /* enable CPUn */ 64 u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
76 writel(SLCR_A9_CPU_CLKSTOP << cpu, 65 reg &= ~(SLCR_A9_CPU_RST << cpu);
77 zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); 66 writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
78 /* enable CLK for CPUn */ 67 reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
79 writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); 68 writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
80} 69}
81 70
82/** 71/**
@@ -85,9 +74,9 @@ void zynq_slcr_cpu_start(int cpu)
85 */ 74 */
86void zynq_slcr_cpu_stop(int cpu) 75void zynq_slcr_cpu_stop(int cpu)
87{ 76{
88 /* stop CLK and reset CPUn */ 77 u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
89 writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, 78 reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
90 zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); 79 writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
91} 80}
92 81
93/** 82/**
@@ -113,7 +102,7 @@ int __init zynq_slcr_init(void)
113 } 102 }
114 103
115 /* unlock the SLCR so that registers can be changed */ 104 /* unlock the SLCR so that registers can be changed */
116 writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); 105 writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
117 106
118 pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); 107 pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
119 108
diff --git a/arch/arm/mm/hugetlbpage.c b/arch/arm/mm/hugetlbpage.c
index 66781bf34077..54ee6163c181 100644
--- a/arch/arm/mm/hugetlbpage.c
+++ b/arch/arm/mm/hugetlbpage.c
@@ -56,3 +56,8 @@ int pmd_huge(pmd_t pmd)
56{ 56{
57 return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT); 57 return pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT);
58} 58}
59
60int pmd_huge_support(void)
61{
62 return 1;
63}
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 2958e74fc42c..febaee7ca57b 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -17,6 +17,7 @@
17#include <linux/nodemask.h> 17#include <linux/nodemask.h>
18#include <linux/initrd.h> 18#include <linux/initrd.h>
19#include <linux/of_fdt.h> 19#include <linux/of_fdt.h>
20#include <linux/of_reserved_mem.h>
20#include <linux/highmem.h> 21#include <linux/highmem.h>
21#include <linux/gfp.h> 22#include <linux/gfp.h>
22#include <linux/memblock.h> 23#include <linux/memblock.h>
@@ -77,7 +78,7 @@ static int __init parse_tag_initrd2(const struct tag *tag)
77__tagtable(ATAG_INITRD2, parse_tag_initrd2); 78__tagtable(ATAG_INITRD2, parse_tag_initrd2);
78 79
79#ifdef CONFIG_OF_FLATTREE 80#ifdef CONFIG_OF_FLATTREE
80void __init early_init_dt_setup_initrd_arch(unsigned long start, unsigned long end) 81void __init early_init_dt_setup_initrd_arch(u64 start, u64 end)
81{ 82{
82 phys_initrd_start = start; 83 phys_initrd_start = start;
83 phys_initrd_size = end - start; 84 phys_initrd_size = end - start;
@@ -207,7 +208,7 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
207 208
208#ifdef CONFIG_ZONE_DMA 209#ifdef CONFIG_ZONE_DMA
209 210
210unsigned long arm_dma_zone_size __read_mostly; 211phys_addr_t arm_dma_zone_size __read_mostly;
211EXPORT_SYMBOL(arm_dma_zone_size); 212EXPORT_SYMBOL(arm_dma_zone_size);
212 213
213/* 214/*
@@ -378,6 +379,8 @@ void __init arm_memblock_init(struct meminfo *mi,
378 if (mdesc->reserve) 379 if (mdesc->reserve)
379 mdesc->reserve(); 380 mdesc->reserve();
380 381
382 early_init_dt_scan_reserved_mem();
383
381 /* 384 /*
382 * reserve memory for DMA contigouos allocations, 385 * reserve memory for DMA contigouos allocations,
383 * must come from DMA area inside low memory 386 * must come from DMA area inside low memory
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index f82bae2171eb..436ea97074cd 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -106,7 +106,7 @@ config OMAP_32K_TIMER
106 This timer saves power compared to the OMAP_MPU_TIMER, and has 106 This timer saves power compared to the OMAP_MPU_TIMER, and has
107 support for no tick during idle. The 32KHz timer provides less 107 support for no tick during idle. The 32KHz timer provides less
108 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is 108 intra-tick resolution than OMAP_MPU_TIMER. The 32KHz timer is
109 currently only available for OMAP16XX, 24XX, 34XX and OMAP4/5. 109 currently only available for OMAP16XX, 24XX, 34XX, OMAP4/5 and DRA7XX.
110 110
111 On OMAP2PLUS this value is only used for CONFIG_HZ and 111 On OMAP2PLUS this value is only used for CONFIG_HZ and
112 CLOCK_TICK_RATE compile time calculation. 112 CLOCK_TICK_RATE compile time calculation.
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 4d463ca6821f..037660633fa4 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -2083,6 +2083,7 @@ static int omap_system_dma_probe(struct platform_device *pdev)
2083 dma_irq = platform_get_irq_byname(pdev, irq_name); 2083 dma_irq = platform_get_irq_byname(pdev, irq_name);
2084 if (dma_irq < 0) { 2084 if (dma_irq < 0) {
2085 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq); 2085 dev_err(&pdev->dev, "failed: request IRQ %d", dma_irq);
2086 ret = dma_irq;
2086 goto exit_dma_lch_fail; 2087 goto exit_dma_lch_fail;
2087 } 2088 }
2088 ret = setup_irq(dma_irq, &omap24xx_dma_irq); 2089 ret = setup_irq(dma_irq, &omap24xx_dma_irq);
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 8db0b981ca64..c492e1b3dfdb 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -47,7 +47,7 @@ static int __init orion_add_irq_domain(struct device_node *np,
47 do { 47 do {
48 base = of_iomap(np, i); 48 base = of_iomap(np, i);
49 if (base) { 49 if (base) {
50 orion_irq_init(i * 32, base); 50 orion_irq_init(i * 32, base + 0x04);
51 i++; 51 i++;
52 } 52 }
53 } while (base); 53 } while (base);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a5b5ff6e68d2..7dfba937d8fc 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -25,7 +25,6 @@ config PLAT_S5P
25 select S5P_GPIO_DRVSTR 25 select S5P_GPIO_DRVSTR
26 select SAMSUNG_CLKSRC if !COMMON_CLK 26 select SAMSUNG_CLKSRC if !COMMON_CLK
27 select SAMSUNG_GPIOLIB_4BIT 27 select SAMSUNG_GPIOLIB_4BIT
28 select SAMSUNG_IRQ_VIC_TIMER
29 help 28 help
30 Base platform code for Samsung's S5P series SoC. 29 Base platform code for Samsung's S5P series SoC.
31 30
@@ -79,14 +78,6 @@ config SAMSUNG_ATAGS
79 78
80if SAMSUNG_ATAGS 79if SAMSUNG_ATAGS
81 80
82# timer options
83
84config SAMSUNG_HRT
85 bool
86 select SAMSUNG_DEV_PWM
87 help
88 Use the High Resolution timer support
89
90# clock options 81# clock options
91 82
92config SAMSUNG_CLOCK 83config SAMSUNG_CLOCK
@@ -106,11 +97,6 @@ config S5P_CLOCK
106 97
107# options for IRQ support 98# options for IRQ support
108 99
109config SAMSUNG_IRQ_VIC_TIMER
110 bool
111 help
112 Internal configuration to build the VIC timer interrupt code.
113
114config S5P_IRQ 100config S5P_IRQ
115 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 101 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210)
116 help 102 help
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 199bbe304d02..498c7c23e9f4 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -12,15 +12,12 @@ obj- :=
12# Objects we always build independent of SoC choice 12# Objects we always build independent of SoC choice
13 13
14obj-y += init.o cpu.o 14obj-y += init.o cpu.o
15obj-$(CONFIG_SAMSUNG_HRT) += samsung-time.o
16 15
17obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o 16obj-$(CONFIG_SAMSUNG_CLOCK) += clock.o
18obj-$(CONFIG_SAMSUNG_CLOCK) += pwm-clock.o
19 17
20obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o 18obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o
21obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o 19obj-$(CONFIG_S5P_CLOCK) += s5p-clock.o
22 20
23obj-$(CONFIG_SAMSUNG_IRQ_VIC_TIMER) += irq-vic-timer.o
24obj-$(CONFIG_S5P_IRQ) += s5p-irq.o 21obj-$(CONFIG_S5P_IRQ) += s5p-irq.o
25obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o 22obj-$(CONFIG_S5P_EXT_INT) += s5p-irq-eint.o
26obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o 23obj-$(CONFIG_S5P_GPIO_INT) += s5p-irq-gpioint.o
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
index 5f197dcaf10c..d51f9565567c 100644
--- a/arch/arm/plat-samsung/dev-backlight.c
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -20,13 +20,18 @@
20#include <plat/gpio-cfg.h> 20#include <plat/gpio-cfg.h>
21#include <plat/backlight.h> 21#include <plat/backlight.h>
22 22
23struct samsung_bl_drvdata {
24 struct platform_pwm_backlight_data plat_data;
25 struct samsung_bl_gpio_info *gpio_info;
26};
27
23static int samsung_bl_init(struct device *dev) 28static int samsung_bl_init(struct device *dev)
24{ 29{
25 int ret = 0; 30 int ret = 0;
26 struct platform_device *timer_dev = 31 struct platform_pwm_backlight_data *pdata = dev->platform_data;
27 container_of(dev->parent, struct platform_device, dev); 32 struct samsung_bl_drvdata *drvdata = container_of(pdata,
28 struct samsung_bl_gpio_info *bl_gpio_info = 33 struct samsung_bl_drvdata, plat_data);
29 timer_dev->dev.platform_data; 34 struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
30 35
31 ret = gpio_request(bl_gpio_info->no, "Backlight"); 36 ret = gpio_request(bl_gpio_info->no, "Backlight");
32 if (ret) { 37 if (ret) {
@@ -42,10 +47,10 @@ static int samsung_bl_init(struct device *dev)
42 47
43static void samsung_bl_exit(struct device *dev) 48static void samsung_bl_exit(struct device *dev)
44{ 49{
45 struct platform_device *timer_dev = 50 struct platform_pwm_backlight_data *pdata = dev->platform_data;
46 container_of(dev->parent, struct platform_device, dev); 51 struct samsung_bl_drvdata *drvdata = container_of(pdata,
47 struct samsung_bl_gpio_info *bl_gpio_info = 52 struct samsung_bl_drvdata, plat_data);
48 timer_dev->dev.platform_data; 53 struct samsung_bl_gpio_info *bl_gpio_info = drvdata->gpio_info;
49 54
50 s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT); 55 s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT);
51 gpio_free(bl_gpio_info->no); 56 gpio_free(bl_gpio_info->no);
@@ -60,12 +65,14 @@ static void samsung_bl_exit(struct device *dev)
60 * for their specific boards 65 * for their specific boards
61 */ 66 */
62 67
63static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = { 68static struct samsung_bl_drvdata samsung_dfl_bl_data __initdata = {
64 .max_brightness = 255, 69 .plat_data = {
65 .dft_brightness = 255, 70 .max_brightness = 255,
66 .pwm_period_ns = 78770, 71 .dft_brightness = 255,
67 .init = samsung_bl_init, 72 .pwm_period_ns = 78770,
68 .exit = samsung_bl_exit, 73 .init = samsung_bl_init,
74 .exit = samsung_bl_exit,
75 },
69}; 76};
70 77
71static struct platform_device samsung_dfl_bl_device __initdata = { 78static struct platform_device samsung_dfl_bl_device __initdata = {
@@ -82,6 +89,7 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
82{ 89{
83 int ret = 0; 90 int ret = 0;
84 struct platform_device *samsung_bl_device; 91 struct platform_device *samsung_bl_device;
92 struct samsung_bl_drvdata *samsung_bl_drvdata;
85 struct platform_pwm_backlight_data *samsung_bl_data; 93 struct platform_pwm_backlight_data *samsung_bl_data;
86 94
87 samsung_bl_device = kmemdup(&samsung_dfl_bl_device, 95 samsung_bl_device = kmemdup(&samsung_dfl_bl_device,
@@ -91,17 +99,19 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
91 return; 99 return;
92 } 100 }
93 101
94 samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data, 102 samsung_bl_drvdata = kmemdup(&samsung_dfl_bl_data,
95 sizeof(struct platform_pwm_backlight_data), samsung_bl_device); 103 sizeof(samsung_dfl_bl_data), GFP_KERNEL);
96 if (!samsung_bl_data) { 104 if (!samsung_bl_drvdata) {
97 printk(KERN_ERR "%s: no memory for platform dev\n", __func__); 105 printk(KERN_ERR "%s: no memory for platform dev\n", __func__);
98 goto err_data; 106 goto err_data;
99 } 107 }
108 samsung_bl_device->dev.platform_data = &samsung_bl_drvdata->plat_data;
109 samsung_bl_drvdata->gpio_info = gpio_info;
110 samsung_bl_data = &samsung_bl_drvdata->plat_data;
100 111
101 /* Copy board specific data provided by user */ 112 /* Copy board specific data provided by user */
102 samsung_bl_data->pwm_id = bl_data->pwm_id; 113 samsung_bl_data->pwm_id = bl_data->pwm_id;
103 samsung_bl_device->dev.parent = 114 samsung_bl_device->dev.parent = &samsung_device_pwm.dev;
104 &s3c_device_timer[samsung_bl_data->pwm_id].dev;
105 115
106 if (bl_data->max_brightness) 116 if (bl_data->max_brightness)
107 samsung_bl_data->max_brightness = bl_data->max_brightness; 117 samsung_bl_data->max_brightness = bl_data->max_brightness;
@@ -122,17 +132,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
122 if (bl_data->check_fb) 132 if (bl_data->check_fb)
123 samsung_bl_data->check_fb = bl_data->check_fb; 133 samsung_bl_data->check_fb = bl_data->check_fb;
124 134
125 /* Keep the GPIO info for future use */
126 s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info;
127
128 /* Register the specific PWM timer dev for Backlight control */
129 ret = platform_device_register(
130 &s3c_device_timer[samsung_bl_data->pwm_id]);
131 if (ret) {
132 printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret);
133 goto err_plat_reg1;
134 }
135
136 /* Register the Backlight dev */ 135 /* Register the Backlight dev */
137 ret = platform_device_register(samsung_bl_device); 136 ret = platform_device_register(samsung_bl_device);
138 if (ret) { 137 if (ret) {
@@ -143,8 +142,6 @@ void __init samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
143 return; 142 return;
144 143
145err_plat_reg2: 144err_plat_reg2:
146 platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]);
147err_plat_reg1:
148 kfree(samsung_bl_data); 145 kfree(samsung_bl_data);
149err_data: 146err_data:
150 kfree(samsung_bl_device); 147 kfree(samsung_bl_device);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 0f9c3f431a5f..8ce0ac007eb9 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -58,6 +58,7 @@
58#include <plat/keypad.h> 58#include <plat/keypad.h>
59#include <linux/platform_data/mmc-s3cmci.h> 59#include <linux/platform_data/mmc-s3cmci.h>
60#include <linux/platform_data/mtd-nand-s3c2410.h> 60#include <linux/platform_data/mtd-nand-s3c2410.h>
61#include <plat/pwm-core.h>
61#include <plat/sdhci.h> 62#include <plat/sdhci.h>
62#include <linux/platform_data/touchscreen-s3c2410.h> 63#include <linux/platform_data/touchscreen-s3c2410.h>
63#include <linux/platform_data/usb-s3c2410_udc.h> 64#include <linux/platform_data/usb-s3c2410_udc.h>
@@ -1097,36 +1098,21 @@ arch_initcall(s5p_pmu_init);
1097/* PWM Timer */ 1098/* PWM Timer */
1098 1099
1099#ifdef CONFIG_SAMSUNG_DEV_PWM 1100#ifdef CONFIG_SAMSUNG_DEV_PWM
1101static struct resource samsung_pwm_resource[] = {
1102 DEFINE_RES_MEM(SAMSUNG_PA_TIMER, SZ_4K),
1103};
1100 1104
1101#define TIMER_RESOURCE_SIZE (1) 1105struct platform_device samsung_device_pwm = {
1102 1106 .name = "samsung-pwm",
1103#define TIMER_RESOURCE(_tmr, _irq) \ 1107 .id = -1,
1104 (struct resource [TIMER_RESOURCE_SIZE]) { \ 1108 .num_resources = ARRAY_SIZE(samsung_pwm_resource),
1105 [0] = { \ 1109 .resource = samsung_pwm_resource,
1106 .start = _irq, \
1107 .end = _irq, \
1108 .flags = IORESOURCE_IRQ \
1109 } \
1110 }
1111
1112#define DEFINE_S3C_TIMER(_tmr_no, _irq) \
1113 .name = "s3c24xx-pwm", \
1114 .id = _tmr_no, \
1115 .num_resources = TIMER_RESOURCE_SIZE, \
1116 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
1117
1118/*
1119 * since we already have an static mapping for the timer,
1120 * we do not bother setting any IO resource for the base.
1121 */
1122
1123struct platform_device s3c_device_timer[] = {
1124 [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
1125 [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
1126 [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
1127 [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
1128 [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
1129}; 1110};
1111
1112void __init samsung_pwm_set_platdata(struct samsung_pwm_variant *pd)
1113{
1114 samsung_device_pwm.dev.platform_data = pd;
1115}
1130#endif /* CONFIG_SAMSUNG_DEV_PWM */ 1116#endif /* CONFIG_SAMSUNG_DEV_PWM */
1131 1117
1132/* RTC */ 1118/* RTC */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index df45d6edc98d..63239f409807 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -145,10 +145,6 @@ extern int s3c2443_clkcon_enable_s(struct clk *clk, int enable);
145 145
146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable); 146extern int s3c64xx_sclk_ctrl(struct clk *clk, int enable);
147 147
148/* Init for pwm clock code */
149
150extern void s3c_pwmclk_init(void);
151
152/* Global watchdog clock used by arch_wtd_reset() callback */ 148/* Global watchdog clock used by arch_wtd_reset() callback */
153 149
154extern struct clk *s3c2410_wdtclk; 150extern struct clk *s3c2410_wdtclk;
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 87d501ff3328..0dc4ac4909b0 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -134,6 +134,7 @@ extern struct platform_device exynos4_device_spdif;
134 134
135extern struct platform_device samsung_asoc_idma; 135extern struct platform_device samsung_asoc_idma;
136extern struct platform_device samsung_device_keypad; 136extern struct platform_device samsung_device_keypad;
137extern struct platform_device samsung_device_pwm;
137 138
138/* s3c2440 specific devices */ 139/* s3c2440 specific devices */
139 140
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
deleted file mode 100644
index 5b9c42fd32d7..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/* arch/arm/plat-samsung/include/plat/irq-vic-timer.h
2 *
3 * Copyright (c) 2010 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for Samsung SoC IRQ VIC timer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/irqs.h b/arch/arm/plat-samsung/include/plat/irqs.h
index df46b776976a..039001c0ef05 100644
--- a/arch/arm/plat-samsung/include/plat/irqs.h
+++ b/arch/arm/plat-samsung/include/plat/irqs.h
@@ -44,15 +44,6 @@
44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x)) 44#define S5P_IRQ_VIC2(x) (S5P_VIC2_BASE + (x))
45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x)) 45#define S5P_IRQ_VIC3(x) (S5P_VIC3_BASE + (x))
46 46
47#define S5P_TIMER_IRQ(x) (IRQ_TIMER_BASE + (x))
48
49#define IRQ_TIMER0 S5P_TIMER_IRQ(0)
50#define IRQ_TIMER1 S5P_TIMER_IRQ(1)
51#define IRQ_TIMER2 S5P_TIMER_IRQ(2)
52#define IRQ_TIMER3 S5P_TIMER_IRQ(3)
53#define IRQ_TIMER4 S5P_TIMER_IRQ(4)
54#define IRQ_TIMER_COUNT (5)
55
56#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \ 47#define IRQ_EINT(x) ((x) < 16 ? ((x) + S5P_EINT_BASE1) \
57 : ((x) - 16 + S5P_EINT_BASE2)) 48 : ((x) - 16 + S5P_EINT_BASE2))
58 49
diff --git a/arch/arm/plat-samsung/include/plat/pwm-clock.h b/arch/arm/plat-samsung/include/plat/pwm-clock.h
deleted file mode 100644
index bf6a60eb6237..000000000000
--- a/arch/arm/plat-samsung/include/plat/pwm-clock.h
+++ /dev/null
@@ -1,81 +0,0 @@
1/* linux/arch/arm/plat-samsung/include/plat/pwm-clock.h
2 *
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright 2008 Openmoko, Inc.
7 * Copyright 2008 Simtec Electronics
8 * Ben Dooks <ben@simtec.co.uk>
9 * http://armlinux.simtec.co.uk/
10 *
11 * SAMSUNG - pwm clock and timer support
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16*/
17
18#ifndef __ASM_PLAT_PWM_CLOCK_H
19#define __ASM_PLAT_PWM_CLOCK_H __FILE__
20
21/**
22 * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
23 * @tcfg: The timer TCFG1 register bits shifted down to 0.
24 *
25 * Return true if the given configuration from TCFG1 is a TCLK instead
26 * any of the TDIV clocks.
27 */
28static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
29{
30 if (soc_is_s3c24xx())
31 return tcfg == S3C2410_TCFG1_MUX_TCLK;
32 else if (soc_is_s3c64xx() || soc_is_s5pc100())
33 return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
34 else if (soc_is_s5p6440() || soc_is_s5p6450())
35 return 0;
36 else
37 return tcfg == S3C64XX_TCFG1_MUX_TCLK;
38}
39
40/**
41 * tcfg_to_divisor() - convert tcfg1 setting to a divisor
42 * @tcfg1: The tcfg1 setting, shifted down.
43 *
44 * Get the divisor value for the given tcfg1 setting. We assume the
45 * caller has already checked to see if this is not a TCLK source.
46 */
47static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
48{
49 if (soc_is_s3c24xx())
50 return 1 << (tcfg1 + 1);
51 else
52 return 1 << tcfg1;
53}
54
55/**
56 * pwm_tdiv_has_div1() - does the tdiv setting have a /1
57 *
58 * Return true if we have a /1 in the tdiv setting.
59 */
60static inline unsigned int pwm_tdiv_has_div1(void)
61{
62 if (soc_is_s3c24xx())
63 return 0;
64 else
65 return 1;
66}
67
68/**
69 * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
70 * @div: The divisor to calculate the bit information for.
71 *
72 * Turn a divisor into the necessary bit field for TCFG1.
73 */
74static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
75{
76 if (soc_is_s3c24xx())
77 return ilog2(div) - 1;
78 else
79 return ilog2(div);
80}
81#endif /* __ASM_PLAT_PWM_CLOCK_H */
diff --git a/arch/arm/plat-samsung/include/plat/pwm-core.h b/arch/arm/plat-samsung/include/plat/pwm-core.h
new file mode 100644
index 000000000000..5bff1facb672
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/pwm-core.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2013 Tomasz Figa <tomasz.figa@gmail.com>
3 *
4 * Samsung PWM controller platform data helpers.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_PWM_CORE_H
12#define __ASM_ARCH_PWM_CORE_H __FILE__
13
14#include <clocksource/samsung_pwm.h>
15
16#ifdef CONFIG_SAMSUNG_DEV_PWM
17extern void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd);
18#else
19static inline void samsung_pwm_set_platdata(struct samsung_pwm_variant *pd) { }
20#endif
21
22#endif /* __ASM_ARCH_PWM_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-timer.h b/arch/arm/plat-samsung/include/plat/regs-timer.h
deleted file mode 100644
index d097d92f8cc7..000000000000
--- a/arch/arm/plat-samsung/include/plat/regs-timer.h
+++ /dev/null
@@ -1,124 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11*/
12
13#ifndef __ASM_ARCH_REGS_TIMER_H
14#define __ASM_ARCH_REGS_TIMER_H
15
16#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
17#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
18
19#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
20#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
21#define S3C2410_TCON S3C_TIMERREG(0x08)
22
23#define S3C64XX_TINT_CSTAT S3C_TIMERREG(0x44)
24
25#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
26#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
27#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
28#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
29#define S3C2410_TCFG_DEADZONE_SHIFT (16)
30
31#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
32#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
33#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
34#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
35#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
36#define S3C2410_TCFG1_MUX4_MASK (15<<16)
37#define S3C2410_TCFG1_MUX4_SHIFT (16)
38
39#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
40#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
41#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
42#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
43#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
44#define S3C2410_TCFG1_MUX3_MASK (15<<12)
45
46
47#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
48#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
49#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
50#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
51#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
52#define S3C2410_TCFG1_MUX2_MASK (15<<8)
53
54
55#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
56#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
57#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
58#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
59#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
60#define S3C2410_TCFG1_MUX1_MASK (15<<4)
61
62#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
63#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
64#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
65#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
66#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
67#define S3C2410_TCFG1_MUX0_MASK (15<<0)
68
69#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
70#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
71#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
72#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
73#define S3C2410_TCFG1_MUX_TCLK (4<<0)
74#define S3C2410_TCFG1_MUX_MASK (15<<0)
75
76#define S3C64XX_TCFG1_MUX_DIV1 (0<<0)
77#define S3C64XX_TCFG1_MUX_DIV2 (1<<0)
78#define S3C64XX_TCFG1_MUX_DIV4 (2<<0)
79#define S3C64XX_TCFG1_MUX_DIV8 (3<<0)
80#define S3C64XX_TCFG1_MUX_DIV16 (4<<0)
81#define S3C64XX_TCFG1_MUX_TCLK (5<<0) /* 3 sets of TCLK */
82#define S3C64XX_TCFG1_MUX_MASK (15<<0)
83
84#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
85
86/* for each timer, we have an count buffer, an compare buffer and
87 * an observation buffer
88*/
89
90/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
91
92#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
93#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
94#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
95
96#define S3C2410_TCON_T4RELOAD (1<<22)
97#define S3C2410_TCON_T4MANUALUPD (1<<21)
98#define S3C2410_TCON_T4START (1<<20)
99
100#define S3C2410_TCON_T3RELOAD (1<<19)
101#define S3C2410_TCON_T3INVERT (1<<18)
102#define S3C2410_TCON_T3MANUALUPD (1<<17)
103#define S3C2410_TCON_T3START (1<<16)
104
105#define S3C2410_TCON_T2RELOAD (1<<15)
106#define S3C2410_TCON_T2INVERT (1<<14)
107#define S3C2410_TCON_T2MANUALUPD (1<<13)
108#define S3C2410_TCON_T2START (1<<12)
109
110#define S3C2410_TCON_T1RELOAD (1<<11)
111#define S3C2410_TCON_T1INVERT (1<<10)
112#define S3C2410_TCON_T1MANUALUPD (1<<9)
113#define S3C2410_TCON_T1START (1<<8)
114
115#define S3C2410_TCON_T0DEADZONE (1<<4)
116#define S3C2410_TCON_T0RELOAD (1<<3)
117#define S3C2410_TCON_T0INVERT (1<<2)
118#define S3C2410_TCON_T0MANUALUPD (1<<1)
119#define S3C2410_TCON_T0START (1<<0)
120
121#endif /* __ASM_ARCH_REGS_TIMER_H */
122
123
124
diff --git a/arch/arm/plat-samsung/include/plat/samsung-time.h b/arch/arm/plat-samsung/include/plat/samsung-time.h
index 4cc99bb1f176..209464adef97 100644
--- a/arch/arm/plat-samsung/include/plat/samsung-time.h
+++ b/arch/arm/plat-samsung/include/plat/samsung-time.h
@@ -22,29 +22,6 @@ enum samsung_timer_mode {
22 SAMSUNG_PWM4, 22 SAMSUNG_PWM4,
23}; 23};
24 24
25struct samsung_timer_source {
26 unsigned int event_id;
27 unsigned int source_id;
28};
29
30/* Be able to sleep for atleast 4 seconds (usually more) */
31#define SAMSUNG_TIMER_MIN_RANGE 4
32
33#if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S5PC100)
34#define TCNT_MAX 0xffff
35#define TSCALER_DIV 25
36#define TDIV 50
37#define TSIZE 16
38#else
39#define TCNT_MAX 0xffffffff
40#define TSCALER_DIV 2
41#define TDIV 2
42#define TSIZE 32
43#endif
44
45#define NON_PERIODIC 0
46#define PERIODIC 1
47
48extern void __init samsung_set_timer_source(enum samsung_timer_mode event, 25extern void __init samsung_set_timer_source(enum samsung_timer_mode event,
49 enum samsung_timer_mode source); 26 enum samsung_timer_mode source);
50 27
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index ce1d0f785efd..bf650218b40e 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -260,44 +260,6 @@ static inline void s5pv210_default_sdhci3(void) { }
260 260
261#endif /* CONFIG_S5PV210_SETUP_SDHCI */ 261#endif /* CONFIG_S5PV210_SETUP_SDHCI */
262 262
263/* EXYNOS4 SDHCI setup */
264#ifdef CONFIG_EXYNOS4_SETUP_SDHCI
265static inline void exynos4_default_sdhci0(void)
266{
267#ifdef CONFIG_S3C_DEV_HSMMC
268 s3c_hsmmc0_def_platdata.cfg_gpio = exynos4_setup_sdhci0_cfg_gpio;
269#endif
270}
271
272static inline void exynos4_default_sdhci1(void)
273{
274#ifdef CONFIG_S3C_DEV_HSMMC1
275 s3c_hsmmc1_def_platdata.cfg_gpio = exynos4_setup_sdhci1_cfg_gpio;
276#endif
277}
278
279static inline void exynos4_default_sdhci2(void)
280{
281#ifdef CONFIG_S3C_DEV_HSMMC2
282 s3c_hsmmc2_def_platdata.cfg_gpio = exynos4_setup_sdhci2_cfg_gpio;
283#endif
284}
285
286static inline void exynos4_default_sdhci3(void)
287{
288#ifdef CONFIG_S3C_DEV_HSMMC3
289 s3c_hsmmc3_def_platdata.cfg_gpio = exynos4_setup_sdhci3_cfg_gpio;
290#endif
291}
292
293#else
294static inline void exynos4_default_sdhci0(void) { }
295static inline void exynos4_default_sdhci1(void) { }
296static inline void exynos4_default_sdhci2(void) { }
297static inline void exynos4_default_sdhci3(void) { }
298
299#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
300
301static inline void s3c_sdhci_setname(int id, char *name) 263static inline void s3c_sdhci_setname(int id, char *name)
302{ 264{
303 switch (id) { 265 switch (id) {
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
deleted file mode 100644
index 0fceb4273824..000000000000
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/* arch/arm/plat-samsung/irq-vic-timer.c
2 * originally part of arch/arm/plat-s3c64xx/irq.c
3 *
4 * Copyright 2008 Openmoko, Inc.
5 * Copyright 2008 Simtec Electronics
6 * Ben Dooks <ben@simtec.co.uk>
7 * http://armlinux.simtec.co.uk/
8 *
9 * S3C64XX - Interrupt handling
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/io.h>
21
22#include <mach/map.h>
23#include <mach/irqs.h>
24#include <plat/cpu.h>
25#include <plat/irq-vic-timer.h>
26#include <plat/regs-timer.h>
27
28static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
29{
30 struct irq_chip *chip = irq_get_chip(irq);
31 chained_irq_enter(chip, desc);
32 generic_handle_irq((int)desc->irq_data.handler_data);
33 chained_irq_exit(chip, desc);
34}
35
36/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
37static void s3c_irq_timer_ack(struct irq_data *d)
38{
39 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
40 u32 mask = (1 << 5) << (d->irq - gc->irq_base);
41
42 irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
43}
44
45/**
46 * s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
47 * @num: Number of timers to initialize
48 * @timer_irq: Base IRQ number to be used for the timers.
49 *
50 * Register the necessary IRQ chaining and support for the timer IRQs
51 * chained of the VIC.
52 */
53void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
54{
55 unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
56 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
57 struct irq_chip_generic *s3c_tgc;
58 struct irq_chip_type *ct;
59 unsigned int i;
60
61#ifdef CONFIG_ARCH_EXYNOS
62 if (soc_is_exynos5250()) {
63 pirq[0] = EXYNOS5_IRQ_TIMER0_VIC;
64 pirq[1] = EXYNOS5_IRQ_TIMER1_VIC;
65 pirq[2] = EXYNOS5_IRQ_TIMER2_VIC;
66 pirq[3] = EXYNOS5_IRQ_TIMER3_VIC;
67 pirq[4] = EXYNOS5_IRQ_TIMER4_VIC;
68 } else {
69 pirq[0] = EXYNOS4_IRQ_TIMER0_VIC;
70 pirq[1] = EXYNOS4_IRQ_TIMER1_VIC;
71 pirq[2] = EXYNOS4_IRQ_TIMER2_VIC;
72 pirq[3] = EXYNOS4_IRQ_TIMER3_VIC;
73 pirq[4] = EXYNOS4_IRQ_TIMER4_VIC;
74 }
75#endif
76 s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
77 S3C64XX_TINT_CSTAT, handle_level_irq);
78
79 if (!s3c_tgc) {
80 pr_err("%s: irq_alloc_generic_chip for IRQ %d failed\n",
81 __func__, timer_irq);
82 return;
83 }
84
85 ct = s3c_tgc->chip_types;
86 ct->chip.irq_mask = irq_gc_mask_clr_bit;
87 ct->chip.irq_unmask = irq_gc_mask_set_bit;
88 ct->chip.irq_ack = s3c_irq_timer_ack;
89 irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
90 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
91 /* Clear the upper bits of the mask_cache*/
92 s3c_tgc->mask_cache &= 0x1f;
93
94 for (i = 0; i < num; i++, timer_irq++) {
95 irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
96 irq_set_handler_data(pirq[i], (void *)timer_irq);
97 }
98}
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
deleted file mode 100644
index a35ff3bcffe4..000000000000
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ /dev/null
@@ -1,474 +0,0 @@
1/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/log2.h>
18#include <linux/clk.h>
19#include <linux/err.h>
20#include <linux/io.h>
21
22#include <mach/hardware.h>
23#include <mach/map.h>
24#include <asm/irq.h>
25
26#include <plat/clock.h>
27#include <plat/cpu.h>
28
29#include <plat/regs-timer.h>
30#include <plat/pwm-clock.h>
31
32/* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers.
34 *
35 * pclk ---- [ prescaler 0 ] -+---> timer 0
36 * +---> timer 1
37 *
38 * pclk ---- [ prescaler 1 ] -+---> timer 2
39 * +---> timer 3
40 * \---> timer 4
41 *
42 * Which are fed into the timers as so:
43 *
44 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
45 * [mux] -> timer 0
46 * tclk 0 ------------------------------/
47 *
48 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
49 * [mux] -> timer 1
50 * tclk 0 ------------------------------/
51 *
52 *
53 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
54 * [mux] -> timer 2
55 * tclk 1 ------------------------------/
56 *
57 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
58 * [mux] -> timer 3
59 * tclk 1 ------------------------------/
60 *
61 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
62 * [mux] -> timer 4
63 * tclk 1 ------------------------------/
64 *
65 * Since the mux and the divider are tied together in the
66 * same register space, it is impossible to set the parent
67 * and the rate at the same time. To avoid this, we add an
68 * intermediate 'prescaled-and-divided' clock to select
69 * as the parent for the timer input clock called tdiv.
70 *
71 * prescaled clk --> pwm-tdiv ---\
72 * [ mux ] --> timer X
73 * tclk -------------------------/
74*/
75
76static struct clk clk_timer_scaler[];
77
78static unsigned long clk_pwm_scaler_get_rate(struct clk *clk)
79{
80 unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
81
82 if (clk == &clk_timer_scaler[1]) {
83 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
84 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
85 } else {
86 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
87 }
88
89 return clk_get_rate(clk->parent) / (tcfg0 + 1);
90}
91
92static unsigned long clk_pwm_scaler_round_rate(struct clk *clk,
93 unsigned long rate)
94{
95 unsigned long parent_rate = clk_get_rate(clk->parent);
96 unsigned long divisor = parent_rate / rate;
97
98 if (divisor > 256)
99 divisor = 256;
100 else if (divisor < 2)
101 divisor = 2;
102
103 return parent_rate / divisor;
104}
105
106static int clk_pwm_scaler_set_rate(struct clk *clk, unsigned long rate)
107{
108 unsigned long round = clk_pwm_scaler_round_rate(clk, rate);
109 unsigned long tcfg0;
110 unsigned long divisor;
111 unsigned long flags;
112
113 divisor = clk_get_rate(clk->parent) / round;
114 divisor--;
115
116 local_irq_save(flags);
117 tcfg0 = __raw_readl(S3C2410_TCFG0);
118
119 if (clk == &clk_timer_scaler[1]) {
120 tcfg0 &= ~S3C2410_TCFG_PRESCALER1_MASK;
121 tcfg0 |= divisor << S3C2410_TCFG_PRESCALER1_SHIFT;
122 } else {
123 tcfg0 &= ~S3C2410_TCFG_PRESCALER0_MASK;
124 tcfg0 |= divisor;
125 }
126
127 __raw_writel(tcfg0, S3C2410_TCFG0);
128 local_irq_restore(flags);
129
130 return 0;
131}
132
133static struct clk_ops clk_pwm_scaler_ops = {
134 .get_rate = clk_pwm_scaler_get_rate,
135 .set_rate = clk_pwm_scaler_set_rate,
136 .round_rate = clk_pwm_scaler_round_rate,
137};
138
139static struct clk clk_timer_scaler[] = {
140 [0] = {
141 .name = "pwm-scaler0",
142 .id = -1,
143 .ops = &clk_pwm_scaler_ops,
144 },
145 [1] = {
146 .name = "pwm-scaler1",
147 .id = -1,
148 .ops = &clk_pwm_scaler_ops,
149 },
150};
151
152static struct clk clk_timer_tclk[] = {
153 [0] = {
154 .name = "pwm-tclk0",
155 .id = -1,
156 },
157 [1] = {
158 .name = "pwm-tclk1",
159 .id = -1,
160 },
161};
162
163struct pwm_tdiv_clk {
164 struct clk clk;
165 unsigned int divisor;
166};
167
168static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
169{
170 return container_of(clk, struct pwm_tdiv_clk, clk);
171}
172
173static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
174{
175 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
176 unsigned int divisor;
177
178 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
179 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
180
181 if (pwm_cfg_src_is_tclk(tcfg1))
182 divisor = to_tdiv(clk)->divisor;
183 else
184 divisor = tcfg_to_divisor(tcfg1);
185
186 return clk_get_rate(clk->parent) / divisor;
187}
188
189static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
190 unsigned long rate)
191{
192 unsigned long parent_rate;
193 unsigned long divisor;
194
195 parent_rate = clk_get_rate(clk->parent);
196 divisor = parent_rate / rate;
197
198 if (divisor <= 1 && pwm_tdiv_has_div1())
199 divisor = 1;
200 else if (divisor <= 2)
201 divisor = 2;
202 else if (divisor <= 4)
203 divisor = 4;
204 else if (divisor <= 8)
205 divisor = 8;
206 else
207 divisor = 16;
208
209 return parent_rate / divisor;
210}
211
212static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
213{
214 return pwm_tdiv_div_bits(divclk->divisor);
215}
216
217static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
218{
219 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
220 unsigned long bits = clk_pwm_tdiv_bits(divclk);
221 unsigned long flags;
222 unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
223
224 local_irq_save(flags);
225
226 tcfg1 = __raw_readl(S3C2410_TCFG1);
227 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
228 tcfg1 |= bits << shift;
229 __raw_writel(tcfg1, S3C2410_TCFG1);
230
231 local_irq_restore(flags);
232}
233
234static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
235{
236 struct pwm_tdiv_clk *divclk = to_tdiv(clk);
237 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
238 unsigned long parent_rate = clk_get_rate(clk->parent);
239 unsigned long divisor;
240
241 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
242 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
243
244 rate = clk_round_rate(clk, rate);
245 divisor = parent_rate / rate;
246
247 if (divisor > 16)
248 return -EINVAL;
249
250 divclk->divisor = divisor;
251
252 /* Update the current MUX settings if we are currently
253 * selected as the clock source for this clock. */
254
255 if (!pwm_cfg_src_is_tclk(tcfg1))
256 clk_pwm_tdiv_update(divclk);
257
258 return 0;
259}
260
261static struct clk_ops clk_tdiv_ops = {
262 .get_rate = clk_pwm_tdiv_get_rate,
263 .set_rate = clk_pwm_tdiv_set_rate,
264 .round_rate = clk_pwm_tdiv_round_rate,
265};
266
267static struct pwm_tdiv_clk clk_timer_tdiv[] = {
268 [0] = {
269 .clk = {
270 .name = "pwm-tdiv",
271 .devname = "s3c24xx-pwm.0",
272 .ops = &clk_tdiv_ops,
273 .parent = &clk_timer_scaler[0],
274 },
275 },
276 [1] = {
277 .clk = {
278 .name = "pwm-tdiv",
279 .devname = "s3c24xx-pwm.1",
280 .ops = &clk_tdiv_ops,
281 .parent = &clk_timer_scaler[0],
282 }
283 },
284 [2] = {
285 .clk = {
286 .name = "pwm-tdiv",
287 .devname = "s3c24xx-pwm.2",
288 .ops = &clk_tdiv_ops,
289 .parent = &clk_timer_scaler[1],
290 },
291 },
292 [3] = {
293 .clk = {
294 .name = "pwm-tdiv",
295 .devname = "s3c24xx-pwm.3",
296 .ops = &clk_tdiv_ops,
297 .parent = &clk_timer_scaler[1],
298 },
299 },
300 [4] = {
301 .clk = {
302 .name = "pwm-tdiv",
303 .devname = "s3c24xx-pwm.4",
304 .ops = &clk_tdiv_ops,
305 .parent = &clk_timer_scaler[1],
306 },
307 },
308};
309
310static int __init clk_pwm_tdiv_register(unsigned int id)
311{
312 struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
313 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
314
315 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
316 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
317
318 divclk->clk.id = id;
319 divclk->divisor = tcfg_to_divisor(tcfg1);
320
321 return s3c24xx_register_clock(&divclk->clk);
322}
323
324static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
325{
326 return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
327}
328
329static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
330{
331 return &clk_timer_tdiv[id].clk;
332}
333
334static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
335{
336 unsigned int id = clk->id;
337 unsigned long tcfg1;
338 unsigned long flags;
339 unsigned long bits;
340 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
341
342 unsigned long mux_tclk;
343
344 if (soc_is_s3c24xx())
345 mux_tclk = S3C2410_TCFG1_MUX_TCLK;
346 else if (soc_is_s5p6440() || soc_is_s5p6450())
347 mux_tclk = 0;
348 else
349 mux_tclk = S3C64XX_TCFG1_MUX_TCLK;
350
351 if (parent == s3c24xx_pwmclk_tclk(id))
352 bits = mux_tclk << shift;
353 else if (parent == s3c24xx_pwmclk_tdiv(id))
354 bits = clk_pwm_tdiv_bits(to_tdiv(parent)) << shift;
355 else
356 return -EINVAL;
357
358 clk->parent = parent;
359
360 local_irq_save(flags);
361
362 tcfg1 = __raw_readl(S3C2410_TCFG1);
363 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
364 __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
365
366 local_irq_restore(flags);
367
368 return 0;
369}
370
371static struct clk_ops clk_tin_ops = {
372 .set_parent = clk_pwm_tin_set_parent,
373};
374
375static struct clk clk_tin[] = {
376 [0] = {
377 .name = "pwm-tin",
378 .devname = "s3c24xx-pwm.0",
379 .id = 0,
380 .ops = &clk_tin_ops,
381 },
382 [1] = {
383 .name = "pwm-tin",
384 .devname = "s3c24xx-pwm.1",
385 .id = 1,
386 .ops = &clk_tin_ops,
387 },
388 [2] = {
389 .name = "pwm-tin",
390 .devname = "s3c24xx-pwm.2",
391 .id = 2,
392 .ops = &clk_tin_ops,
393 },
394 [3] = {
395 .name = "pwm-tin",
396 .devname = "s3c24xx-pwm.3",
397 .id = 3,
398 .ops = &clk_tin_ops,
399 },
400 [4] = {
401 .name = "pwm-tin",
402 .devname = "s3c24xx-pwm.4",
403 .id = 4,
404 .ops = &clk_tin_ops,
405 },
406};
407
408static __init int clk_pwm_tin_register(struct clk *pwm)
409{
410 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
411 unsigned int id = pwm->id;
412
413 struct clk *parent;
414 int ret;
415
416 ret = s3c24xx_register_clock(pwm);
417 if (ret < 0)
418 return ret;
419
420 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
421 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
422
423 if (pwm_cfg_src_is_tclk(tcfg1))
424 parent = s3c24xx_pwmclk_tclk(id);
425 else
426 parent = s3c24xx_pwmclk_tdiv(id);
427
428 return clk_set_parent(pwm, parent);
429}
430
431/**
432 * s3c_pwmclk_init() - initialise pwm clocks
433 *
434 * Initialise and register the clocks which provide the inputs for the
435 * pwm timer blocks.
436 *
437 * Note, this call is required by the time core, so must be called after
438 * the base clocks are added and before any of the initcalls are run.
439 */
440__init void s3c_pwmclk_init(void)
441{
442 struct clk *clk_timers;
443 unsigned int clk;
444 int ret;
445
446 clk_timers = clk_get(NULL, "timers");
447 if (IS_ERR(clk_timers)) {
448 printk(KERN_ERR "%s: no parent clock\n", __func__);
449 return;
450 }
451
452 for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++)
453 clk_timer_scaler[clk].parent = clk_timers;
454
455 s3c_register_clocks(clk_timer_scaler, ARRAY_SIZE(clk_timer_scaler));
456 s3c_register_clocks(clk_timer_tclk, ARRAY_SIZE(clk_timer_tclk));
457
458 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
459 ret = clk_pwm_tdiv_register(clk);
460
461 if (ret < 0) {
462 printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
463 return;
464 }
465 }
466
467 for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
468 ret = clk_pwm_tin_register(&clk_tin[clk]);
469 if (ret < 0) {
470 printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
471 return;
472 }
473 }
474}
diff --git a/arch/arm/plat-samsung/s5p-irq.c b/arch/arm/plat-samsung/s5p-irq.c
index ff1a76011b1e..ddfaca9c79d8 100644
--- a/arch/arm/plat-samsung/s5p-irq.c
+++ b/arch/arm/plat-samsung/s5p-irq.c
@@ -17,9 +17,7 @@
17 17
18#include <mach/irqs.h> 18#include <mach/irqs.h>
19#include <mach/map.h> 19#include <mach/map.h>
20#include <plat/regs-timer.h>
21#include <plat/cpu.h> 20#include <plat/cpu.h>
22#include <plat/irq-vic-timer.h>
23 21
24void __init s5p_init_irq(u32 *vic, u32 num_vic) 22void __init s5p_init_irq(u32 *vic, u32 num_vic)
25{ 23{
@@ -30,6 +28,4 @@ void __init s5p_init_irq(u32 *vic, u32 num_vic)
30 for (irq = 0; irq < num_vic; irq++) 28 for (irq = 0; irq < num_vic; irq++)
31 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0); 29 vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
32#endif 30#endif
33
34 s3c_init_vic_timer_irq(5, IRQ_TIMER0);
35} 31}
diff --git a/arch/arm/plat-samsung/samsung-time.c b/arch/arm/plat-samsung/samsung-time.c
deleted file mode 100644
index 2957075ca836..000000000000
--- a/arch/arm/plat-samsung/samsung-time.c
+++ /dev/null
@@ -1,394 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com/
4 *
5 * samsung - Common hr-timer support (s3c and s5p)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/interrupt.h>
13#include <linux/irq.h>
14#include <linux/err.h>
15#include <linux/clk.h>
16#include <linux/clockchips.h>
17#include <linux/platform_device.h>
18#include <linux/sched_clock.h>
19
20#include <asm/smp_twd.h>
21#include <asm/mach/time.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/map.h>
24
25#include <mach/map.h>
26#include <plat/devs.h>
27#include <plat/regs-timer.h>
28#include <plat/samsung-time.h>
29
30static struct clk *tin_event;
31static struct clk *tin_source;
32static struct clk *tdiv_event;
33static struct clk *tdiv_source;
34static struct clk *timerclk;
35static struct samsung_timer_source timer_source;
36static unsigned long clock_count_per_tick;
37static void samsung_timer_resume(void);
38
39static void samsung_time_stop(enum samsung_timer_mode mode)
40{
41 unsigned long tcon;
42
43 tcon = __raw_readl(S3C2410_TCON);
44
45 switch (mode) {
46 case SAMSUNG_PWM0:
47 tcon &= ~S3C2410_TCON_T0START;
48 break;
49
50 case SAMSUNG_PWM1:
51 tcon &= ~S3C2410_TCON_T1START;
52 break;
53
54 case SAMSUNG_PWM2:
55 tcon &= ~S3C2410_TCON_T2START;
56 break;
57
58 case SAMSUNG_PWM3:
59 tcon &= ~S3C2410_TCON_T3START;
60 break;
61
62 case SAMSUNG_PWM4:
63 tcon &= ~S3C2410_TCON_T4START;
64 break;
65
66 default:
67 printk(KERN_ERR "Invalid Timer %d\n", mode);
68 break;
69 }
70 __raw_writel(tcon, S3C2410_TCON);
71}
72
73static void samsung_time_setup(enum samsung_timer_mode mode, unsigned long tcnt)
74{
75 unsigned long tcon;
76
77 tcon = __raw_readl(S3C2410_TCON);
78
79 tcnt--;
80
81 switch (mode) {
82 case SAMSUNG_PWM0:
83 tcon &= ~(0x0f << 0);
84 tcon |= S3C2410_TCON_T0MANUALUPD;
85 break;
86
87 case SAMSUNG_PWM1:
88 tcon &= ~(0x0f << 8);
89 tcon |= S3C2410_TCON_T1MANUALUPD;
90 break;
91
92 case SAMSUNG_PWM2:
93 tcon &= ~(0x0f << 12);
94 tcon |= S3C2410_TCON_T2MANUALUPD;
95 break;
96
97 case SAMSUNG_PWM3:
98 tcon &= ~(0x0f << 16);
99 tcon |= S3C2410_TCON_T3MANUALUPD;
100 break;
101
102 case SAMSUNG_PWM4:
103 tcon &= ~(0x07 << 20);
104 tcon |= S3C2410_TCON_T4MANUALUPD;
105 break;
106
107 default:
108 printk(KERN_ERR "Invalid Timer %d\n", mode);
109 break;
110 }
111
112 __raw_writel(tcnt, S3C2410_TCNTB(mode));
113 __raw_writel(tcnt, S3C2410_TCMPB(mode));
114 __raw_writel(tcon, S3C2410_TCON);
115}
116
117static void samsung_time_start(enum samsung_timer_mode mode, bool periodic)
118{
119 unsigned long tcon;
120
121 tcon = __raw_readl(S3C2410_TCON);
122
123 switch (mode) {
124 case SAMSUNG_PWM0:
125 tcon |= S3C2410_TCON_T0START;
126 tcon &= ~S3C2410_TCON_T0MANUALUPD;
127
128 if (periodic)
129 tcon |= S3C2410_TCON_T0RELOAD;
130 else
131 tcon &= ~S3C2410_TCON_T0RELOAD;
132 break;
133
134 case SAMSUNG_PWM1:
135 tcon |= S3C2410_TCON_T1START;
136 tcon &= ~S3C2410_TCON_T1MANUALUPD;
137
138 if (periodic)
139 tcon |= S3C2410_TCON_T1RELOAD;
140 else
141 tcon &= ~S3C2410_TCON_T1RELOAD;
142 break;
143
144 case SAMSUNG_PWM2:
145 tcon |= S3C2410_TCON_T2START;
146 tcon &= ~S3C2410_TCON_T2MANUALUPD;
147
148 if (periodic)
149 tcon |= S3C2410_TCON_T2RELOAD;
150 else
151 tcon &= ~S3C2410_TCON_T2RELOAD;
152 break;
153
154 case SAMSUNG_PWM3:
155 tcon |= S3C2410_TCON_T3START;
156 tcon &= ~S3C2410_TCON_T3MANUALUPD;
157
158 if (periodic)
159 tcon |= S3C2410_TCON_T3RELOAD;
160 else
161 tcon &= ~S3C2410_TCON_T3RELOAD;
162 break;
163
164 case SAMSUNG_PWM4:
165 tcon |= S3C2410_TCON_T4START;
166 tcon &= ~S3C2410_TCON_T4MANUALUPD;
167
168 if (periodic)
169 tcon |= S3C2410_TCON_T4RELOAD;
170 else
171 tcon &= ~S3C2410_TCON_T4RELOAD;
172 break;
173
174 default:
175 printk(KERN_ERR "Invalid Timer %d\n", mode);
176 break;
177 }
178 __raw_writel(tcon, S3C2410_TCON);
179}
180
181static int samsung_set_next_event(unsigned long cycles,
182 struct clock_event_device *evt)
183{
184 samsung_time_setup(timer_source.event_id, cycles);
185 samsung_time_start(timer_source.event_id, NON_PERIODIC);
186
187 return 0;
188}
189
190static void samsung_set_mode(enum clock_event_mode mode,
191 struct clock_event_device *evt)
192{
193 samsung_time_stop(timer_source.event_id);
194
195 switch (mode) {
196 case CLOCK_EVT_MODE_PERIODIC:
197 samsung_time_setup(timer_source.event_id, clock_count_per_tick);
198 samsung_time_start(timer_source.event_id, PERIODIC);
199 break;
200
201 case CLOCK_EVT_MODE_ONESHOT:
202 break;
203
204 case CLOCK_EVT_MODE_UNUSED:
205 case CLOCK_EVT_MODE_SHUTDOWN:
206 break;
207
208 case CLOCK_EVT_MODE_RESUME:
209 samsung_timer_resume();
210 break;
211 }
212}
213
214static void samsung_timer_resume(void)
215{
216 /* event timer restart */
217 samsung_time_setup(timer_source.event_id, clock_count_per_tick);
218 samsung_time_start(timer_source.event_id, PERIODIC);
219
220 /* source timer restart */
221 samsung_time_setup(timer_source.source_id, TCNT_MAX);
222 samsung_time_start(timer_source.source_id, PERIODIC);
223}
224
225void __init samsung_set_timer_source(enum samsung_timer_mode event,
226 enum samsung_timer_mode source)
227{
228 s3c_device_timer[event].dev.bus = &platform_bus_type;
229 s3c_device_timer[source].dev.bus = &platform_bus_type;
230
231 timer_source.event_id = event;
232 timer_source.source_id = source;
233}
234
235static struct clock_event_device time_event_device = {
236 .name = "samsung_event_timer",
237 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
238 .rating = 200,
239 .set_next_event = samsung_set_next_event,
240 .set_mode = samsung_set_mode,
241};
242
243static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
244{
245 struct clock_event_device *evt = dev_id;
246
247 evt->event_handler(evt);
248
249 return IRQ_HANDLED;
250}
251
252static struct irqaction samsung_clock_event_irq = {
253 .name = "samsung_time_irq",
254 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
255 .handler = samsung_clock_event_isr,
256 .dev_id = &time_event_device,
257};
258
259static void __init samsung_clockevent_init(void)
260{
261 unsigned long pclk;
262 unsigned long clock_rate;
263 unsigned int irq_number;
264 struct clk *tscaler;
265
266 pclk = clk_get_rate(timerclk);
267
268 tscaler = clk_get_parent(tdiv_event);
269
270 clk_set_rate(tscaler, pclk / TSCALER_DIV);
271 clk_set_rate(tdiv_event, pclk / TDIV);
272 clk_set_parent(tin_event, tdiv_event);
273
274 clock_rate = clk_get_rate(tin_event);
275 clock_count_per_tick = clock_rate / HZ;
276
277 time_event_device.cpumask = cpumask_of(0);
278 clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
279
280 irq_number = timer_source.event_id + IRQ_TIMER0;
281 setup_irq(irq_number, &samsung_clock_event_irq);
282}
283
284static void __iomem *samsung_timer_reg(void)
285{
286 unsigned long offset = 0;
287
288 switch (timer_source.source_id) {
289 case SAMSUNG_PWM0:
290 case SAMSUNG_PWM1:
291 case SAMSUNG_PWM2:
292 case SAMSUNG_PWM3:
293 offset = (timer_source.source_id * 0x0c) + 0x14;
294 break;
295
296 case SAMSUNG_PWM4:
297 offset = 0x40;
298 break;
299
300 default:
301 printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
302 return NULL;
303 }
304
305 return S3C_TIMERREG(offset);
306}
307
308/*
309 * Override the global weak sched_clock symbol with this
310 * local implementation which uses the clocksource to get some
311 * better resolution when scheduling the kernel. We accept that
312 * this wraps around for now, since it is just a relative time
313 * stamp. (Inspired by U300 implementation.)
314 */
315static u32 notrace samsung_read_sched_clock(void)
316{
317 void __iomem *reg = samsung_timer_reg();
318
319 if (!reg)
320 return 0;
321
322 return ~__raw_readl(reg);
323}
324
325static void __init samsung_clocksource_init(void)
326{
327 unsigned long pclk;
328 unsigned long clock_rate;
329
330 pclk = clk_get_rate(timerclk);
331
332 clk_set_rate(tdiv_source, pclk / TDIV);
333 clk_set_parent(tin_source, tdiv_source);
334
335 clock_rate = clk_get_rate(tin_source);
336
337 samsung_time_setup(timer_source.source_id, TCNT_MAX);
338 samsung_time_start(timer_source.source_id, PERIODIC);
339
340 setup_sched_clock(samsung_read_sched_clock, TSIZE, clock_rate);
341
342 if (clocksource_mmio_init(samsung_timer_reg(), "samsung_clocksource_timer",
343 clock_rate, 250, TSIZE, clocksource_mmio_readl_down))
344 panic("samsung_clocksource_timer: can't register clocksource\n");
345}
346
347static void __init samsung_timer_resources(void)
348{
349
350 unsigned long event_id = timer_source.event_id;
351 unsigned long source_id = timer_source.source_id;
352 char devname[15];
353
354 timerclk = clk_get(NULL, "timers");
355 if (IS_ERR(timerclk))
356 panic("failed to get timers clock for timer");
357
358 clk_enable(timerclk);
359
360 sprintf(devname, "s3c24xx-pwm.%lu", event_id);
361 s3c_device_timer[event_id].id = event_id;
362 s3c_device_timer[event_id].dev.init_name = devname;
363
364 tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
365 if (IS_ERR(tin_event))
366 panic("failed to get pwm-tin clock for event timer");
367
368 tdiv_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tdiv");
369 if (IS_ERR(tdiv_event))
370 panic("failed to get pwm-tdiv clock for event timer");
371
372 clk_enable(tin_event);
373
374 sprintf(devname, "s3c24xx-pwm.%lu", source_id);
375 s3c_device_timer[source_id].id = source_id;
376 s3c_device_timer[source_id].dev.init_name = devname;
377
378 tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
379 if (IS_ERR(tin_source))
380 panic("failed to get pwm-tin clock for source timer");
381
382 tdiv_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tdiv");
383 if (IS_ERR(tdiv_source))
384 panic("failed to get pwm-tdiv clock for source timer");
385
386 clk_enable(tin_source);
387}
388
389void __init samsung_timer_init(void)
390{
391 samsung_timer_resources();
392 samsung_clockevent_init();
393 samsung_clocksource_init();
394}
diff --git a/arch/arm/xen/enlighten.c b/arch/arm/xen/enlighten.c
index 8a6295c86209..83e4f959ee47 100644
--- a/arch/arm/xen/enlighten.c
+++ b/arch/arm/xen/enlighten.c
@@ -21,6 +21,8 @@
21#include <linux/of.h> 21#include <linux/of.h>
22#include <linux/of_irq.h> 22#include <linux/of_irq.h>
23#include <linux/of_address.h> 23#include <linux/of_address.h>
24#include <linux/cpuidle.h>
25#include <linux/cpufreq.h>
24 26
25#include <linux/mm.h> 27#include <linux/mm.h>
26 28
@@ -267,18 +269,28 @@ static int __init xen_guest_init(void)
267 if (!xen_initial_domain()) 269 if (!xen_initial_domain())
268 xenbus_probe(NULL); 270 xenbus_probe(NULL);
269 271
272 /*
273 * Making sure board specific code will not set up ops for
274 * cpu idle and cpu freq.
275 */
276 disable_cpuidle();
277 disable_cpufreq();
278
270 return 0; 279 return 0;
271} 280}
272core_initcall(xen_guest_init); 281core_initcall(xen_guest_init);
273 282
274static int __init xen_pm_init(void) 283static int __init xen_pm_init(void)
275{ 284{
285 if (!xen_domain())
286 return -ENODEV;
287
276 pm_power_off = xen_power_off; 288 pm_power_off = xen_power_off;
277 arm_pm_restart = xen_restart; 289 arm_pm_restart = xen_restart;
278 290
279 return 0; 291 return 0;
280} 292}
281subsys_initcall(xen_pm_init); 293late_initcall(xen_pm_init);
282 294
283static irqreturn_t xen_arm_callback(int irq, void *arg) 295static irqreturn_t xen_arm_callback(int irq, void *arg)
284{ 296{
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-05 15:51:16 -0400