414 files changed, 11018 insertions, 4313 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 57eb6ef7f48d..5dbb9562742c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -260,6 +260,7 @@ config ARCH_INTEGRATOR
         select ICST
         select GENERIC_CLOCKEVENTS
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_FPGA_IRQ
         select NEED_MACH_IO_H
         select NEED_MACH_MEMORY_H
@@ -277,6 +278,7 @@ config ARCH_REALVIEW
         select GENERIC_CLOCKEVENTS
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
         select ARM_TIMER_SP804
         select GPIO_PL061 if GPIOLIB
@@ -295,6 +297,7 @@ config ARCH_VERSATILE
         select ARCH_WANT_OPTIONAL_GPIOLIB
         select NEED_MACH_IO_H if PCI
         select PLAT_VERSATILE
+        select PLAT_VERSATILE_CLOCK
         select PLAT_VERSATILE_CLCD
         select PLAT_VERSATILE_FPGA_IRQ
         select ARM_TIMER_SP804
@@ -307,7 +310,7 @@ config ARCH_VEXPRESS
         select ARM_AMBA
         select ARM_TIMER_SP804
         select CLKDEV_LOOKUP
-        select HAVE_MACH_CLKDEV
+        select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK
         select HAVE_PATA_PLATFORM
@@ -315,6 +318,7 @@ config ARCH_VEXPRESS
         select NO_IOPORT
         select PLAT_VERSATILE
         select PLAT_VERSATILE_CLCD
+        select REGULATOR_FIXED_VOLTAGE if REGULATOR
         help
           This enables support for the ARM Ltd Versatile Express boards.
 
@@ -567,6 +571,7 @@ config ARCH_LPC32XX
         select CLKDEV_LOOKUP
         select GENERIC_CLOCKEVENTS
         select USE_OF
+        select HAVE_PWM
         help
           Support for the NXP LPC32XX family of processors
 
@@ -914,7 +919,7 @@ config ARCH_NOMADIK
         select ARM_AMBA
         select ARM_VIC
         select CPU_ARM926T
-        select CLKDEV_LOOKUP
+        select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select PINCTRL
         select MIGHT_HAVE_CACHE_L2X0
@@ -937,6 +942,7 @@ config ARCH_DAVINCI
 
 config ARCH_OMAP
         bool "TI OMAP"
+        depends on MMU
         select HAVE_CLK
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_HAS_CPUFREQ
@@ -1022,8 +1028,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
 
 source "arch/arm/mach-ks8695/Kconfig"
 
-source "arch/arm/mach-lpc32xx/Kconfig"
-
 source "arch/arm/mach-msm/Kconfig"
 
 source "arch/arm/mach-mv78xx0/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 01a134141216..a03b5a7059e2 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -310,6 +310,32 @@ choice
                   The uncompressor code port configuration is now handled
                   by CONFIG_S3C_LOWLEVEL_UART_PORT.
 
+        config DEBUG_VEXPRESS_UART0_DETECT
+                bool "Autodetect UART0 on Versatile Express Cortex-A core tiles"
+                depends on ARCH_VEXPRESS && CPU_CP15_MMU
+                help
+                  This option enables a simple heuristic which tries to determine
+                  the motherboard's memory map variant (original or RS1) and then
+                  choose the relevant UART0 base address.
+
+                  Note that this will only work with standard A-class core tiles,
+                  and may fail with non-standard SMM or custom software models.
+
+        config DEBUG_VEXPRESS_UART0_CA9
+                bool "Use PL011 UART0 at 0x10009000 (V2P-CA9 core tile)"
+                depends on ARCH_VEXPRESS
+                help
+                  This option selects UART0 at 0x10009000. Except for custom models,
+                  this applies only to the V2P-CA9 tile.
+
+        config DEBUG_VEXPRESS_UART0_RS1
+                bool "Use PL011 UART0 at 0x1c090000 (RS1 complaint tiles)"
+                depends on ARCH_VEXPRESS
+                help
+                  This option selects UART0 at 0x1c090000. This applies to most
+                  of the tiles using the RS1 memory map, including all new A-class
+                  core tiles, FPGA-based SMMs and software models.
+
         config DEBUG_LL_UART_NONE
                 bool "No low-level debugging UART"
                 help
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
new file mode 100644
index 000000000000..29b9f15e7599
--- /dev/null
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -0,0 +1,113 @@
+/*
+ * aks-cdu.dts - Device Tree file for AK signal CDU
+ *
+ * Copyright (C) 2012 AK signal Brno a.s.
+ *               2012 Jiri Prchal <jiri.prchal@aksignal.cz>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "ge863-pro3.dtsi"
+
+/ {
+        chosen {
+                bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
+        };
+
+        ahb {
+                apb {
+                        usart0: serial@fffb0000 {
+                                status = "okay";
+                        };
+
+                        usart1: serial@fffb4000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                                };
+
+                        usart2: serial@fffb8000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                        };
+
+                        usart3: serial@fffd0000 {
+                                status = "okay";
+                                linux,rs485-enabled-at-boot-time;
+                                rs485-rts-delay = <0 0>;
+                        };
+
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 15 0>;
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        bootstrap@0 {
+                                label = "bootstrap";
+                                reg = <0x0 0x40000>;
+                        };
+
+                        uboot@40000 {
+                                label = "uboot";
+                                reg = <0x40000 0x80000>;
+                        };
+                        ubootenv@c0000 {
+                                label = "ubootenv";
+                                reg = <0xc0000 0x40000>;
+                        };
+                        kernel@100000 {
+                                label = "kernel";
+                                reg = <0x100000 0x400000>;
+                        };
+                        rootfs@500000 {
+                                label = "rootfs";
+                                reg = <0x500000 0x7b00000>;
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                red {
+                        gpios = <&pioC 10 0>;
+                        linux,default-trigger = "none";
+                };
+
+                green {
+                        gpios = <&pioA 5 1>;
+                        linux,default-trigger = "none";
+                        default-state = "on";
+                };
+
+                yellow {
+                        gpios = <&pioB 20 1>;
+                        linux,default-trigger = "none";
+                };
+
+                blue {
+                        gpios = <&pioB 21 1>;
+                        linux,default-trigger = "none";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
new file mode 100644
index 000000000000..a9af4db7234c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+        model = "TI AM335x BeagleBone";
+        compatible = "ti,am335x-bone", "ti,am33xx";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
new file mode 100644
index 000000000000..d6a97d9eff72
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "am33xx.dtsi"
+
+/ {
+        model = "TI AM335x EVM";
+        compatible = "ti,am335x-evm", "ti,am33xx";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
new file mode 100644
index 000000000000..59509c48d7e5
--- /dev/null
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -0,0 +1,158 @@
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "ti,am33xx";
+
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+                serial5 = &uart6;
+        };
+
+        cpus {
+                cpu@0 {
+                        compatible = "arm,cortex-a8";
+                };
+        };
+
+        /*
+         * The soc node represents the soc top level view. It is uses for IPs
+         * that are not memory mapped in the MPU view or for the MPU itself.
+         */
+        soc {
+                compatible = "ti,omap-infra";
+                mpu {
+                        compatible = "ti,omap3-mpu";
+                        ti,hwmods = "mpu";
+                };
+        };
+
+        /*
+         * XXX: Use a flat representation of the AM33XX interconnect.
+         * The real AM33XX interconnect network is quite complex.Since
+         * that will not bring real advantage to represent that in DT
+         * for the moment, just use a fake OCP bus entry to represent
+         * the whole bus hierarchy.
+         */
+        ocp {
+                compatible = "simple-bus";
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+                ti,hwmods = "l3_main";
+
+                intc: interrupt-controller@48200000 {
+                        compatible = "ti,omap2-intc";
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                        ti,intc-size = <128>;
+                        reg = <0x48200000 0x1000>;
+                };
+
+                gpio1: gpio@44e07000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio1";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio2: gpio@4804C000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio2";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio3: gpio@481AC000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio3";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                gpio4: gpio@481AE000 {
+                        compatible = "ti,omap4-gpio";
+                        ti,hwmods = "gpio4";
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <1>;
+                };
+
+                uart1: serial@44E09000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart1";
+                        clock-frequency = <48000000>;
+                };
+
+                uart2: serial@48022000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart2";
+                        clock-frequency = <48000000>;
+                };
+
+                uart3: serial@48024000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart3";
+                        clock-frequency = <48000000>;
+                };
+
+                uart4: serial@481A6000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart4";
+                        clock-frequency = <48000000>;
+                };
+
+                uart5: serial@481A8000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart5";
+                        clock-frequency = <48000000>;
+                };
+
+                uart6: serial@481AA000 {
+                        compatible = "ti,omap3-uart";
+                        ti,hwmods = "uart6";
+                        clock-frequency = <48000000>;
+                };
+
+                i2c1: i2c@44E0B000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c1";
+                };
+
+                i2c2: i2c@4802A000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c2";
+                };
+
+                i2c3: i2c@4819C000 {
+                        compatible = "ti,omap4-i2c";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        ti,hwmods = "i2c3";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/am3517-evm.dts b/arch/arm/boot/dts/am3517-evm.dts
new file mode 100644
index 000000000000..474f760ecadf
--- /dev/null
+++ b/arch/arm/boot/dts/am3517-evm.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap3.dtsi"
+
+/ {
+        model = "TI AM3517 EVM (AM3517/05)";
+        compatible = "ti,am3517-evm", "ti,omap3";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x10000000>; /* 256 MB */
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+};
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+};
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index f449efc9825f..66389c1c6f62 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -52,10 +52,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <29 30 31>;
                         };
 
                         ramc0: ramc@ffffea00 {
@@ -81,25 +82,25 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@fffa0000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffa0000 0x100>;
-                                interrupts = <17 4 18 4 19 4>;
+                                interrupts = <17 4 0 18 4 0 19 4 0>;
                         };
 
                         tcb1: timer@fffdc000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffdc000 0x100>;
-                                interrupts = <26 4 27 4 28 4>;
+                                interrupts = <26 4 0 27 4 0 28 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -108,7 +109,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,14 +127,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fffb0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb0000 0x200>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -142,7 +143,7 @@
                         usart1: serial@fffb4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb4000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -151,7 +152,7 @@
                         usart2: serial@fffb8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffb8000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -160,7 +161,7 @@
                         usart3: serial@fffd0000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd0000 0x200>;
-                                interrupts = <23 4>;
+                                interrupts = <23 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,7 +170,7 @@
                         usart4: serial@fffd4000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd4000 0x200>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -178,7 +179,7 @@
                         usart5: serial@fffd8000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffd8000 0x200>;
-                                interrupts = <25 4>;
+                                interrupts = <25 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -187,21 +188,21 @@
                         macb0: ethernet@fffc4000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffc4000 0x100>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 3>;
                                 status = "disabled";
                         };
 
                         usb1: gadget@fffa4000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfffa4000 0x4000>;
-                                interrupts = <10 4>;
+                                interrupts = <10 4 2>;
                                 status = "disabled";
                         };
 
                         adc0: adc@fffe0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffe0000 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xf>;
                                 atmel,adc-vref = <3300>;
@@ -253,7 +254,7 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x100000>;
-                        interrupts = <20 4>;
+                        interrupts = <20 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 0209913a65a2..b460d6ce9eb5 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -48,10 +48,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <30 31>;
                         };
 
                         pmc: pmc@fffffc00 {
@@ -68,13 +69,13 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <19 4>;
+                                interrupts = <19 4 0>;
                         };
 
                         rstc@fffffd00 {
@@ -90,7 +91,7 @@
                         pioA: gpio@fffff200 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff200 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -99,7 +100,7 @@
                         pioB: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -108,7 +109,7 @@
                         pioC: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioD: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,7 +127,7 @@
                         pioE: gpio@fffffa00 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -135,14 +136,14 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -151,7 +152,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -160,7 +161,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4>;
+                                interrupts = <9 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,14 +170,14 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 3>;
                                 status = "disabled";
                         };
 
                         usb1: gadget@fff78000 {
                                 compatible = "atmel,at91rm9200-udc";
                                 reg = <0xfff78000 0x4000>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 2>;
                                 status = "disabled";
                         };
                 };
@@ -200,7 +201,7 @@
                 usb0: ohci@00a00000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00a00000 0x100000>;
-                        interrupts = <29 4>;
+                        interrupts = <29 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 7dbccaf199f7..bafa8806fc17 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -53,10 +53,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <31>;
                         };
 
                         ramc0: ramc@ffffe400 {
@@ -78,7 +79,7 @@
                         pit: timer@fffffd30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffd30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
 
@@ -90,25 +91,25 @@
                         tcb0: timer@fff7c000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfff7c000 0x100>;
-                                interrupts = <18 4>;
+                                interrupts = <18 4 0>;
                         };
 
                         tcb1: timer@fffd4000 {
                                 compatible = "atmel,at91rm9200-tcb";
                                 reg = <0xfffd4000 0x100>;
-                                interrupts = <18 4>;
+                                interrupts = <18 4 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 0>;
                         };
 
                         pioA: gpio@fffff200 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff200 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -117,7 +118,7 @@
                         pioB: gpio@fffff400 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -126,7 +127,7 @@
                         pioC: gpio@fffff600 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <4 4>;
+                                interrupts = <4 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -135,7 +136,7 @@
                         pioD: gpio@fffff800 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -144,7 +145,7 @@
                         pioE: gpio@fffffa00 {
                                 compatible = "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -153,14 +154,14 @@
                         dbgu: serial@ffffee00 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@fff8c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff8c000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -169,7 +170,7 @@
                         usart1: serial@fff90000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff90000 0x200>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -178,7 +179,7 @@
                         usart2: serial@fff94000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff94000 0x200>;
-                                interrupts = <9 4>;
+                                interrupts = <9 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -187,7 +188,7 @@
                         usart3: serial@fff98000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfff98000 0x200>;
-                                interrupts = <10 4>;
+                                interrupts = <10 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -196,14 +197,14 @@
                         macb0: ethernet@fffbc000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xfffbc000 0x100>;
-                                interrupts = <25 4>;
+                                interrupts = <25 4 3>;
                                 status = "disabled";
                         };
 
                         adc0: adc@fffb0000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xfffb0000 0x100>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                                 atmel,adc-use-external-triggers;
                                 atmel,adc-channels-used = <0xff>;
                                 atmel,adc-vref = <3300>;
@@ -257,14 +258,14 @@
                 usb0: ohci@00700000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00800000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00800000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index cb84de791b5a..bfac0dfc332c 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -50,7 +50,7 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
@@ -74,7 +74,7 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         shdwc@fffffe10 {
@@ -85,25 +85,25 @@
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         dma: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -112,7 +112,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -121,7 +121,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -130,7 +130,7 @@
                         pioD: gpio@fffffa00 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -139,14 +139,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x4000>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -155,7 +155,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x4000>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -164,7 +164,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x4000>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -173,7 +173,7 @@
                         usart3: serial@f8028000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8028000 0x4000>;
-                                interrupts = <8 4>;
+                                interrupts = <8 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -201,7 +201,7 @@
                 usb0: ohci@00500000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00500000 0x00100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 6b3ef4339ae7..4a18c393b136 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -51,10 +51,11 @@
                         ranges;
 
                         aic: interrupt-controller@fffff000 {
-                                #interrupt-cells = <2>;
+                                #interrupt-cells = <3>;
                                 compatible = "atmel,at91rm9200-aic";
                                 interrupt-controller;
                                 reg = <0xfffff000 0x200>;
+                                atmel,external-irqs = <31>;
                         };
 
                         ramc0: ramc@ffffe800 {
@@ -80,37 +81,37 @@
                         pit: timer@fffffe30 {
                                 compatible = "atmel,at91sam9260-pit";
                                 reg = <0xfffffe30 0xf>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                         };
 
                         tcb0: timer@f8008000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf8008000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         tcb1: timer@f800c000 {
                                 compatible = "atmel,at91sam9x5-tcb";
                                 reg = <0xf800c000 0x100>;
-                                interrupts = <17 4>;
+                                interrupts = <17 4 0>;
                         };
 
                         dma0: dma-controller@ffffec00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffec00 0x200>;
-                                interrupts = <20 4>;
+                                interrupts = <20 4 0>;
                         };
 
                         dma1: dma-controller@ffffee00 {
                                 compatible = "atmel,at91sam9g45-dma";
                                 reg = <0xffffee00 0x200>;
-                                interrupts = <21 4>;
+                                interrupts = <21 4 0>;
                         };
 
                         pioA: gpio@fffff400 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff400 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -119,7 +120,7 @@
                         pioB: gpio@fffff600 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff600 0x100>;
-                                interrupts = <2 4>;
+                                interrupts = <2 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -128,7 +129,7 @@
                         pioC: gpio@fffff800 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffff800 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -137,7 +138,7 @@
                         pioD: gpio@fffffa00 {
                                 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
                                 reg = <0xfffffa00 0x100>;
-                                interrupts = <3 4>;
+                                interrupts = <3 4 1>;
                                 #gpio-cells = <2>;
                                 gpio-controller;
                                 interrupt-controller;
@@ -146,14 +147,14 @@
                         dbgu: serial@fffff200 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xfffff200 0x200>;
-                                interrupts = <1 4>;
+                                interrupts = <1 4 7>;
                                 status = "disabled";
                         };
 
                         usart0: serial@f801c000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf801c000 0x200>;
-                                interrupts = <5 4>;
+                                interrupts = <5 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -162,7 +163,7 @@
                         usart1: serial@f8020000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8020000 0x200>;
-                                interrupts = <6 4>;
+                                interrupts = <6 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -171,7 +172,7 @@
                         usart2: serial@f8024000 {
                                 compatible = "atmel,at91sam9260-usart";
                                 reg = <0xf8024000 0x200>;
-                                interrupts = <7 4>;
+                                interrupts = <7 4 5>;
                                 atmel,use-dma-rx;
                                 atmel,use-dma-tx;
                                 status = "disabled";
@@ -180,21 +181,21 @@
                         macb0: ethernet@f802c000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf802c000 0x100>;
-                                interrupts = <24 4>;
+                                interrupts = <24 4 3>;
                                 status = "disabled";
                         };
 
                         macb1: ethernet@f8030000 {
                                 compatible = "cdns,at32ap7000-macb", "cdns,macb";
                                 reg = <0xf8030000 0x100>;
-                                interrupts = <27 4>;
+                                interrupts = <27 4 3>;
                                 status = "disabled";
                         };
 
                         adc0: adc@f804c000 {
                                 compatible = "atmel,at91sam9260-adc";
                                 reg = <0xf804c000 0x100>;
-                                interrupts = <19 4>;
+                                interrupts = <19 4 0>;
                                 atmel,adc-use-external;
                                 atmel,adc-channels-used = <0xffff>;
                                 atmel,adc-vref = <3300>;
@@ -248,14 +249,14 @@
                 usb0: ohci@00600000 {
                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
                         reg = <0x00600000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
 
                 usb1: ehci@00700000 {
                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
                         reg = <0x00700000 0x100000>;
-                        interrupts = <22 4>;
+                        interrupts = <22 4 2>;
                         status = "disabled";
                 };
         };
diff --git a/arch/arm/boot/dts/db8500.dtsi b/arch/arm/boot/dts/db8500.dtsi
index 4ad5160018cb..3180a9c588b9 100644
--- a/arch/arm/boot/dts/db8500.dtsi
+++ b/arch/arm/boot/dts/db8500.dtsi
@@ -48,7 +48,7 @@
                 };
 
                 rtc@80154000 {
-                        compatible = "stericsson,db8500-rtc";
+                        compatible = "arm,rtc-pl031", "arm,primecell";
                         reg = <0x80154000 0x1000>;
                         interrupts = <0 18 0x4>;
                 };
@@ -60,7 +60,7 @@
                         interrupts = <0 119 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <0>;
@@ -73,7 +73,7 @@
                         interrupts = <0 120 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <1>;
@@ -86,7 +86,7 @@
                         interrupts = <0 121 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <2>;
@@ -99,7 +99,7 @@
                         interrupts = <0 122 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <3>;
@@ -112,7 +112,7 @@
                         interrupts = <0 123 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <4>;
@@ -125,7 +125,7 @@
                         interrupts = <0 124 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <5>;
@@ -138,7 +138,7 @@
                         interrupts = <0 125 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <6>;
@@ -151,7 +151,7 @@
                         interrupts = <0 126 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <7>;
@@ -164,7 +164,7 @@
                         interrupts = <0 127 0x4>;
                         interrupt-controller;
                         #interrupt-cells = <2>;
-                        supports-sleepmode;
+                        st,supports-sleepmode;
                         gpio-controller;
                         #gpio-cells = <2>;
                         gpio-bank = <8>;
@@ -206,62 +206,74 @@
 
                                 // DB8500_REGULATOR_VAPE
                                 db8500_vape_reg: db8500_vape {
+                                        regulator-compatible = "db8500_vape";
                                         regulator-name = "db8500-vape";
                                         regulator-always-on;
                                 };
 
                                 // DB8500_REGULATOR_VARM
                                 db8500_varm_reg: db8500_varm {
+                                        regulator-compatible = "db8500_varm";
                                         regulator-name = "db8500-varm";
                                 };
 
                                 // DB8500_REGULATOR_VMODEM
                                 db8500_vmodem_reg: db8500_vmodem {
+                                        regulator-compatible = "db8500_vmodem";
                                         regulator-name = "db8500-vmodem";
                                 };
 
                                 // DB8500_REGULATOR_VPLL
                                 db8500_vpll_reg: db8500_vpll {
+                                        regulator-compatible = "db8500_vpll";
                                         regulator-name = "db8500-vpll";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS1
                                 db8500_vsmps1_reg: db8500_vsmps1 {
+                                        regulator-compatible = "db8500_vsmps1";
                                         regulator-name = "db8500-vsmps1";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS2
                                 db8500_vsmps2_reg: db8500_vsmps2 {
+                                        regulator-compatible = "db8500_vsmps2";
                                         regulator-name = "db8500-vsmps2";
                                 };
 
                                 // DB8500_REGULATOR_VSMPS3
                                 db8500_vsmps3_reg: db8500_vsmps3 {
+                                        regulator-compatible = "db8500_vsmps3";
                                         regulator-name = "db8500-vsmps3";
                                 };
 
                                 // DB8500_REGULATOR_VRF1
                                 db8500_vrf1_reg: db8500_vrf1 {
+                                        regulator-compatible = "db8500_vrf1";
                                         regulator-name = "db8500-vrf1";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAMMDSP
                                 db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
+                                        regulator-compatible = "db8500_sva_mmdsp";
                                         regulator-name = "db8500-sva-mmdsp";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAMMDSPRET
                                 db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
+                                        regulator-compatible = "db8500_sva_mmdsp_ret";
                                         regulator-name = "db8500-sva-mmdsp-ret";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SVAPIPE
                                 db8500_sva_pipe_reg: db8500_sva_pipe {
+                                        regulator-compatible = "db8500_sva_pipe";
                                         regulator-name = "db8500_sva_pipe";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SIAMMDSP
                                 db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
+                                        regulator-compatible = "db8500_sia_mmdsp";
                                         regulator-name = "db8500_sia_mmdsp";
                                 };
 
@@ -272,38 +284,45 @@
 
                                 // DB8500_REGULATOR_SWITCH_SIAPIPE
                                 db8500_sia_pipe_reg: db8500_sia_pipe {
+                                        regulator-compatible = "db8500_sia_pipe";
                                         regulator-name = "db8500-sia-pipe";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_SGA
                                 db8500_sga_reg: db8500_sga {
+                                        regulator-compatible = "db8500_sga";
                                         regulator-name = "db8500-sga";
                                         vin-supply = <&db8500_vape_reg>;
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_B2R2_MCDE
                                 db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
+                                        regulator-compatible = "db8500_b2r2_mcde";
                                         regulator-name = "db8500-b2r2-mcde";
                                         vin-supply = <&db8500_vape_reg>;
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM12
                                 db8500_esram12_reg: db8500_esram12 {
+                                        regulator-compatible = "db8500_esram12";
                                         regulator-name = "db8500-esram12";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM12RET
                                 db8500_esram12_ret_reg: db8500_esram12_ret {
+                                        regulator-compatible = "db8500_esram12_ret";
                                         regulator-name = "db8500-esram12-ret";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM34
                                 db8500_esram34_reg: db8500_esram34 {
+                                        regulator-compatible = "db8500_esram34";
                                         regulator-name = "db8500-esram34";
                                 };
 
                                 // DB8500_REGULATOR_SWITCH_ESRAM34RET
                                 db8500_esram34_ret_reg: db8500_esram34_ret {
+                                        regulator-compatible = "db8500_esram34_ret";
                                         regulator-name = "db8500-esram34-ret";
                                 };
                         };
@@ -312,12 +331,70 @@
                                 compatible = "stericsson,ab8500";
                                 reg = <5>; /* mailbox 5 is i2c */
                                 interrupts = <0 40 0x4>;
+                                interrupt-controller;
+                                #interrupt-cells = <2>;
+
+                                ab8500-rtc {
+                                        compatible = "stericsson,ab8500-rtc";
+                                        interrupts = <17 0x4
+                                                      18 0x4>;
+                                        interrupt-names = "60S", "ALARM";
+                                };
+
+                                ab8500-gpadc {
+                                        compatible = "stericsson,ab8500-gpadc";
+                                        interrupts = <32 0x4
+                                                      39 0x4>;
+                                        interrupt-names = "HW_CONV_END", "SW_CONV_END";
+                                        vddadc-supply = <&ab8500_ldo_tvout_reg>;
+                                };
+
+                                ab8500-usb {
+                                        compatible = "stericsson,ab8500-usb";
+                                        interrupts = < 90 0x4
+                                                       96 0x4
+                                                       14 0x4
+                                                       15 0x4
+                                                       79 0x4
+                                                       74 0x4
+                                                       75 0x4>;
+                                        interrupt-names = "ID_WAKEUP_R",
+                                                          "ID_WAKEUP_F",
+                                                          "VBUS_DET_F",
+                                                          "VBUS_DET_R",
+                                                          "USB_LINK_STATUS",
+                                                          "USB_ADP_PROBE_PLUG",
+                                                          "USB_ADP_PROBE_UNPLUG";
+                                        vddulpivio18-supply = <&ab8500_ldo_initcore_reg>;
+                                        v-ape-supply = <&db8500_vape_reg>;
+                                        musb_1v8-supply = <&db8500_vsmps2_reg>;
+                                };
+
+                                ab8500-ponkey {
+                                        compatible = "stericsson,ab8500-ponkey";
+                                        interrupts = <6 0x4
+                                                      7 0x4>;
+                                        interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
+                                };
+
+                                ab8500-sysctrl {
+                                        compatible = "stericsson,ab8500-sysctrl";
+                                };
+
+                                ab8500-pwm {
+                                        compatible = "stericsson,ab8500-pwm";
+                                };
+
+                                ab8500-debugfs {
+                                        compatible = "stericsson,ab8500-debug";
+                                };
 
                                 ab8500-regulators {
                                         compatible = "stericsson,ab8500-regulator";
 
                                         // supplies to the display/camera
                                         ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
+                                                regulator-compatible = "ab8500_ldo_aux1";
                                                 regulator-name = "V-DISPLAY";
                                                 regulator-min-microvolt = <2500000>;
                                                 regulator-max-microvolt = <2900000>;
@@ -328,6 +405,7 @@
 
                                         // supplies to the on-board eMMC
                                         ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
+                                                regulator-compatible = "ab8500_ldo_aux2";
                                                 regulator-name = "V-eMMC1";
                                                 regulator-min-microvolt = <1100000>;
                                                 regulator-max-microvolt = <3300000>;
@@ -335,6 +413,7 @@
 
                                         // supply for VAUX3; SDcard slots
                                         ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
+                                                regulator-compatible = "ab8500_ldo_aux3";
                                                 regulator-name = "V-MMC-SD";
                                                 regulator-min-microvolt = <1100000>;
                                                 regulator-max-microvolt = <3300000>;
@@ -342,41 +421,49 @@
 
                                         // supply for v-intcore12; VINTCORE12 LDO
                                         ab8500_ldo_initcore_reg: ab8500_ldo_initcore {
+                                                regulator-compatible = "ab8500_ldo_initcore";
                                                 regulator-name = "V-INTCORE";
                                         };
 
                                         // supply for tvout; gpadc; TVOUT LDO
                                         ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
+                                                regulator-compatible = "ab8500_ldo_tvout";
                                                 regulator-name = "V-TVOUT";
                                         };
 
                                         // supply for ab8500-usb; USB LDO
                                         ab8500_ldo_usb_reg: ab8500_ldo_usb {
+                                                regulator-compatible = "ab8500_ldo_usb";
                                                 regulator-name = "dummy";
                                         };
 
                                         // supply for ab8500-vaudio; VAUDIO LDO
                                         ab8500_ldo_audio_reg: ab8500_ldo_audio {
+                                                regulator-compatible = "ab8500_ldo_audio";
                                                 regulator-name = "V-AUD";
                                         };
 
                                         // supply for v-anamic1 VAMic1-LDO
                                         ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
+                                                regulator-compatible = "ab8500_ldo_anamic1";
                                                 regulator-name = "V-AMIC1";
                                         };
 
                                         // supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
                                         ab8500_ldo_amamic2_reg: ab8500_ldo_amamic2 {
+                                                regulator-compatible = "ab8500_ldo_amamic2";
                                                 regulator-name = "V-AMIC2";
                                         };
 
                                         // supply for v-dmic; VDMIC LDO
                                         ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
+                                                regulator-compatible = "ab8500_ldo_dmic";
                                                 regulator-name = "V-DMIC";
                                         };
 
                                         // supply for U8500 CSI/DSI; VANA LDO
                                         ab8500_ldo_ana_reg: ab8500_ldo_ana {
+                                                regulator-compatible = "ab8500_ldo_ana";
                                                 regulator-name = "V-CSI/DSI";
                                         };
                                 };
diff --git a/arch/arm/boot/dts/ea3250.dts b/arch/arm/boot/dts/ea3250.dts
new file mode 100644
index 000000000000..d79b28d9c963
--- /dev/null
+++ b/arch/arm/boot/dts/ea3250.dts
@@ -0,0 +1,174 @@
+/*
+ * Embedded Artists LPC3250 board
+ *
+ * Copyright 2012 Roland Stigge <stigge@antcom.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "lpc32xx.dtsi"
+
+/ {
+        model = "Embedded Artists LPC3250 board based on NXP LPC3250";
+        compatible = "ea,ea3250", "nxp,lpc3250";
+        #address-cells = <1>;
+        #size-cells = <1>;
+
+        memory {
+                device_type = "memory";
+                reg = <0 0x4000000>;
+        };
+
+        ahb {
+                mac: ethernet@31060000 {
+                        phy-mode = "rmii";
+                        use-iram;
+                };
+
+                /* Here, choose exactly one from: ohci, usbd */
+                ohci@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+
+/*
+                usbd@31020000 {
+                        transceiver = <&isp1301>;
+                        status = "okay";
+                };
+*/
+
+                /* 128MB Flash via SLC NAND controller */
+                slc: flash@20020000 {
+                        status = "okay";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+
+                        nxp,wdr-clks = <14>;
+                        nxp,wwidth = <260000000>;
+                        nxp,whold = <104000000>;
+                        nxp,wsetup = <200000000>;
+                        nxp,rdr-clks = <14>;
+                        nxp,rwidth = <34666666>;
+                        nxp,rhold = <104000000>;
+                        nxp,rsetup = <200000000>;
+                        nand-on-flash-bbt;
+                        gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
+                        mtd0@00000000 {
+                                label = "ea3250-boot";
+                                reg = <0x00000000 0x00080000>;
+                                read-only;
+                        };
+
+                        mtd1@00080000 {
+                                label = "ea3250-uboot";
+                                reg = <0x00080000 0x000c0000>;
+                                read-only;
+                        };
+
+                        mtd2@00140000 {
+                                label = "ea3250-kernel";
+                                reg = <0x00140000 0x00400000>;
+                        };
+
+                        mtd3@00540000 {
+                                label = "ea3250-rootfs";
+                                reg = <0x00540000 0x07ac0000>;
+                        };
+                };
+
+                apb {
+                        uart5: serial@40090000 {
+                                status = "okay";
+                        };
+
+                        uart3: serial@40080000 {
+                                status = "okay";
+                        };
+
+                        uart6: serial@40098000 {
+                                status = "okay";
+                        };
+
+                        i2c1: i2c@400A0000 {
+                                clock-frequency = <100000>;
+
+                                eeprom@50 {
+                                        compatible = "at,24c256";
+                                        reg = <0x50>;
+                                };
+
+                                eeprom@57 {
+                                        compatible = "at,24c64";
+                                        reg = <0x57>;
+                                };
+
+                                uda1380: uda1380@18 {
+                                        compatible = "nxp,uda1380";
+                                        reg = <0x18>;
+                                        power-gpio = <&gpio 0x59 0>;
+                                        reset-gpio = <&gpio 0x51 0>;
+                                        dac-clk = "wspll";
+                                };
+
+                                pca9532: pca9532@60 {
+                                        compatible = "nxp,pca9532";
+                                        gpio-controller;
+                                        #gpio-cells = <2>;
+                                        reg = <0x60>;
+                                };
+                        };
+
+                        i2c2: i2c@400A8000 {
+                                clock-frequency = <100000>;
+                        };
+
+                        i2cusb: i2c@31020300 {
+                                clock-frequency = <100000>;
+
+                                isp1301: usb-transceiver@2d {
+                                        compatible = "nxp,isp1301";
+                                        reg = <0x2d>;
+                                };
+                        };
+
+                        sd@20098000 {
+                                wp-gpios = <&pca9532 5 0>;
+                                cd-gpios = <&pca9532 4 0>;
+                                cd-inverted;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                fab {
+                        uart1: serial@40014000 {
+                                status = "okay";
+                        };
+
+                        /* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
+                        adc@40048000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                autorepeat;
+                button@21 {
+                        label = "GPIO Key UP";
+                        linux,code = <103>;
+                        gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
new file mode 100644
index 000000000000..b7354e6506de
--- /dev/null
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -0,0 +1,41 @@
+/*
+ * evk-pro3.dts - Device Tree file for Telit EVK-PRO3 with Telit GE863-PRO3
+ *
+ * Copyright (C) 2012 Telit,
+ *               2012 Fabio Porcedda <fabio.porcedda@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/dts-v1/;
+
+/include/ "ge863-pro3.dtsi"
+
+/ {
+        model = "Telit EVK-PRO3 for Telit GE863-PRO3";
+        compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
+
+        ahb {
+                apb {
+                        macb0: ethernet@fffc4000 {
+                                phy-mode = "rmii";
+                                status = "okay";
+                        };
+
+                        usb1: gadget@fffa4000 {
+                                atmel,vbus-gpio = <&pioC 5 0>;
+                                status = "okay";
+                        };
+                };
+
+                usb0: ohci@00500000 {
+                        num-ports = <2>;
+                        status = "okay";
+                };
+        };
+
+        i2c@0 {
+                status = "okay";
+        };
+
+};
\ No newline at end of file
diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts
index b8c476384eef..0c49caa09978 100644
--- a/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/arch/arm/boot/dts/exynos4210-origen.dts
@@ -134,4 +134,16 @@
         i2c@138D0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@13920000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@13930000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@13940000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts
index 27afc8e535ca..1beccc8f14ff 100644
--- a/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -179,4 +179,42 @@
         i2c@138D0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@13920000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@13930000 {
+                status = "disabled";
+        };
+
+        spi_2: spi@13940000 {
+                gpios = <&gpc1 1 5 3 0>,
+                        <&gpc1 3 5 3 0>,
+                        <&gpc1 4 5 3 0>;
+
+                w25x80@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "w25x80";
+                        reg = <0>;
+                        spi-max-frequency = <1000000>;
+
+                        controller-data {
+                                cs-gpio = <&gpc1 2 1 0 3>;
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0x0 0x40000>;
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                label = "Kernel";
+                                reg = <0x40000 0xc0000>;
+                        };
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index a1dd2ee83753..02891fe876e4 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -25,6 +25,12 @@
         compatible = "samsung,exynos4210";
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+
         gic:interrupt-controller@10490000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -33,6 +39,17 @@
                 reg = <0x10490000 0x1000>, <0x10480000 0x100>;
         };
 
+        combiner:interrupt-controller@10440000 {
+                compatible = "samsung,exynos4210-combiner";
+                #interrupt-cells = <2>;
+                interrupt-controller;
+                reg = <0x10440000 0x1000>;
+                interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
+                             <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
+                             <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
+                             <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
+        };
+
         watchdog@10060000 {
                 compatible = "samsung,s3c2410-wdt";
                 reg = <0x10060000 0x100>;
@@ -147,6 +164,36 @@
                 interrupts = <0 65 0>;
         };
 
+        spi_0: spi@13920000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13920000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_1: spi@13930000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13930000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 7>; /* preliminary */
+                rx-dma-channel = <&pdma1 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_2: spi@13940000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x13940000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 9>; /* preliminary */
+                rx-dma-channel = <&pdma0 8>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 49945cc1bc7d..8a5e348793c7 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -71,4 +71,42 @@
         i2c@12CD0000 {
                 status = "disabled";
         };
+
+        spi_0: spi@12d20000 {
+                status = "disabled";
+        };
+
+        spi_1: spi@12d30000 {
+                gpios = <&gpa2 4 2 3 0>,
+                        <&gpa2 6 2 3 0>,
+                        <&gpa2 7 2 3 0>;
+
+                w25q80bw@0 {
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        compatible = "w25x80";
+                        reg = <0>;
+                        spi-max-frequency = <1000000>;
+
+                        controller-data {
+                                cs-gpio = <&gpa2 5 1 0 3>;
+                                samsung,spi-feedback-delay = <0>;
+                        };
+
+                        partition@0 {
+                                label = "U-Boot";
+                                reg = <0x0 0x40000>;
+                                read-only;
+                        };
+
+                        partition@40000 {
+                                label = "Kernel";
+                                reg = <0x40000 0xc0000>;
+                        };
+                };
+        };
+
+        spi_2: spi@12d40000 {
+                status = "disabled";
+        };
 };
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 4272b2949228..004aaa8d123c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -23,6 +23,12 @@
         compatible = "samsung,exynos5250";
         interrupt-parent = <&gic>;
 
+        aliases {
+                spi0 = &spi_0;
+                spi1 = &spi_1;
+                spi2 = &spi_2;
+        };
+
         gic:interrupt-controller@10481000 {
                 compatible = "arm,cortex-a9-gic";
                 #interrupt-cells = <3>;
@@ -146,6 +152,36 @@
                 #size-cells = <0>;
         };
 
+        spi_0: spi@12d20000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d20000 0x100>;
+                interrupts = <0 66 0>;
+                tx-dma-channel = <&pdma0 5>; /* preliminary */
+                rx-dma-channel = <&pdma0 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_1: spi@12d30000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d30000 0x100>;
+                interrupts = <0 67 0>;
+                tx-dma-channel = <&pdma1 5>; /* preliminary */
+                rx-dma-channel = <&pdma1 4>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
+        spi_2: spi@12d40000 {
+                compatible = "samsung,exynos4210-spi";
+                reg = <0x12d40000 0x100>;
+                interrupts = <0 68 0>;
+                tx-dma-channel = <&pdma0 7>; /* preliminary */
+                rx-dma-channel = <&pdma0 6>; /* preliminary */
+                #address-cells = <1>;
+                #size-cells = <0>;
+        };
+
         amba {
                 #address-cells = <1>;
                 #size-cells = <1>;
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
new file mode 100644
index 000000000000..17136fc7a516
--- /dev/null
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -0,0 +1,52 @@
+/*
+ * ge863_pro3.dtsi - Device Tree file for Telit GE863-PRO3
+ *
+ * Copyright (C) 2012 Telit,
+ *               2012 Fabio Porcedda <fabio.porcedda@gmail.com>
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+/include/ "at91sam9260.dtsi"
+
+/ {
+        clocks {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                ranges;
+
+                main_clock: clock@0 {
+                        compatible = "atmel,osc", "fixed-clock";
+                        clock-frequency = <6000000>;
+                };
+        };
+
+        ahb {
+                apb {
+                        dbgu: serial@fffff200 {
+                                status = "okay";
+                        };
+                };
+
+                nand0: nand@40000000 {
+                        nand-bus-width = <8>;
+                        nand-ecc-mode = "soft";
+                        nand-on-flash-bbt;
+                        status = "okay";
+
+                        boot@0 {
+                                label = "boot";
+                                reg = <0x0 0x7c0000>;
+                        };
+
+                        root@07c0000 {
+                                label = "root";
+                                reg = <0x7c0000 0x7840000>;
+                        };
+                };
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200 root=ubi0:rootfs ubi.mtd=1 rootfstype=ubifs";
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-evk.dts b/arch/arm/boot/dts/imx23-evk.dts
index 70bffa929b65..e3486f486b40 100644
--- a/arch/arm/boot/dts/imx23-evk.dts
+++ b/arch/arm/boot/dts/imx23-evk.dts
@@ -22,17 +22,60 @@
 
         apb@80000000 {
                 apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_pins_fixup>;
+                                status = "okay";
+                        };
+
                         ssp0: ssp@80010000 {
                                 compatible = "fsl,imx23-mmc";
                                 pinctrl-names = "default";
-                                pinctrl-0 = <&mmc0_8bit_pins_a &mmc0_pins_fixup>;
-                                bus-width = <8>;
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
                                 wp-gpios = <&gpio1 30 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1123 /* MX23_PAD_LCD_RESET__GPIO_1_18 */
+                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
+                                                0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a>;
+                                panel-enable-gpios = <&gpio1 18 0>;
                                 status = "okay";
                         };
                 };
 
                 apbx@80040000 {
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
                         duart: serial@80070000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
@@ -40,4 +83,23 @@
                         };
                 };
         };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio1 29 0>;
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx23-olinuxino.dts b/arch/arm/boot/dts/imx23-olinuxino.dts
new file mode 100644
index 000000000000..20912b1d8893
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-olinuxino.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx23.dtsi"
+
+/ {
+        model = "i.MX23 Olinuxino Low Cost Board";
+        compatible = "olimex,imx23-olinuxino", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23-stmp378x_devb.dts b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
new file mode 100644
index 000000000000..757a327ff3e8
--- /dev/null
+++ b/arch/arm/boot/dts/imx23-stmp378x_devb.dts
@@ -0,0 +1,78 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx23.dtsi"
+
+/ {
+        model = "Freescale STMP378x Development Board";
+        compatible = "fsl,stmp378x-devb", "fsl,imx23";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx23-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_pins_fixup>;
+                                bus-width = <4>;
+                                wp-gpios = <&gpio1 30 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11d3 /* MX23_PAD_PWM3__GPIO_1_29 */
+                                                0x11e3 /* MX23_PAD_PWM4__GPIO_1_30 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        auart0: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio1 29 0>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 8c5f9994f3fc..a874dbfb5ae6 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -18,6 +18,8 @@
                 gpio0 = &gpio0;
                 gpio1 = &gpio1;
                 gpio2 = &gpio2;
+                serial0 = &auart0;
+                serial1 = &auart1;
         };
 
         cpus {
@@ -57,13 +59,15 @@
                                 status = "disabled";
                         };
 
-                        bch@8000a000 {
-                                reg = <0x8000a000 2000>;
-                                status = "disabled";
-                        };
-
-                        gpmi@8000c000 {
-                                reg = <0x8000c000 2000>;
+                        gpmi-nand@8000c000 {
+                                compatible = "fsl,imx23-gpmi-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x8000c000 2000>, <0x8000a000 2000>;
+                                reg-names = "gpmi-nand", "bch";
+                                interrupts = <13>, <56>;
+                                interrupt-names = "gpmi-dma", "bch";
+                                fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
@@ -114,24 +118,151 @@
 
                                 duart_pins_a: duart@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x11a2 0x11b2>;
+                                        fsl,pinmux-ids = <
+                                                0x11a2 /* MX23_PAD_PWM0__DUART_RX */
+                                                0x11b2 /* MX23_PAD_PWM1__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart0_pins_a: auart0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x01c0 /* MX23_PAD_AUART1_RX__AUART1_RX */
+                                                0x01d0 /* MX23_PAD_AUART1_TX__AUART1_TX */
+                                                0x01a0 /* MX23_PAD_AUART1_CTS__AUART1_CTS */
+                                                0x01b0 /* MX23_PAD_AUART1_RTS__AUART1_RTS */
+                                        >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
 
+                                gpmi_pins_a: gpmi-nand@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0000 /* MX23_PAD_GPMI_D00__GPMI_D00 */
+                                                0x0010 /* MX23_PAD_GPMI_D01__GPMI_D01 */
+                                                0x0020 /* MX23_PAD_GPMI_D02__GPMI_D02 */
+                                                0x0030 /* MX23_PAD_GPMI_D03__GPMI_D03 */
+                                                0x0040 /* MX23_PAD_GPMI_D04__GPMI_D04 */
+                                                0x0050 /* MX23_PAD_GPMI_D05__GPMI_D05 */
+                                                0x0060 /* MX23_PAD_GPMI_D06__GPMI_D06 */
+                                                0x0070 /* MX23_PAD_GPMI_D07__GPMI_D07 */
+                                                0x0100 /* MX23_PAD_GPMI_CLE__GPMI_CLE */
+                                                0x0110 /* MX23_PAD_GPMI_ALE__GPMI_ALE */
+                                                0x0130 /* MX23_PAD_GPMI_RDY0__GPMI_RDY0 */
+                                                0x0140 /* MX23_PAD_GPMI_RDY1__GPMI_RDY1 */
+                                                0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
+                                                0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x21b0 /* MX23_PAD_GPMI_CE1N__GPMI_CE1N */
+                                                0x21c0 /* MX23_PAD_GPMI_CE0N__GPMI_CE0N */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_fixup: gpmi-pins-fixup {
+                                        fsl,pinmux-ids = <
+                                                0x0170 /* MX23_PAD_GPMI_WPN__GPMI_WPN */
+                                                0x0180 /* MX23_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x0190 /* MX23_PAD_GPMI_RDN__GPMI_RDN */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                };
+
+                                mmc0_4bit_pins_a: mmc0-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
+                                                0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
+                                                0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
+                                                0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
+                                                0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
                                 mmc0_8bit_pins_a: mmc0-8bit@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x2020 0x2030 0x2040
-                                                0x2050 0x0082 0x0092 0x00a2
-                                                0x00b2 0x2000 0x2010 0x2060>;
+                                        fsl,pinmux-ids = <
+                                                0x2020 /* MX23_PAD_SSP1_DATA0__SSP1_DATA0 */
+                                                0x2030 /* MX23_PAD_SSP1_DATA1__SSP1_DATA1 */
+                                                0x2040 /* MX23_PAD_SSP1_DATA2__SSP1_DATA2 */
+                                                0x2050 /* MX23_PAD_SSP1_DATA3__SSP1_DATA3 */
+                                                0x0082 /* MX23_PAD_GPMI_D08__SSP1_DATA4 */
+                                                0x0092 /* MX23_PAD_GPMI_D09__SSP1_DATA5 */
+                                                0x00a2 /* MX23_PAD_GPMI_D10__SSP1_DATA6 */
+                                                0x00b2 /* MX23_PAD_GPMI_D11__SSP1_DATA7 */
+                                                0x2000 /* MX23_PAD_SSP1_CMD__SSP1_CMD */
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
 
                                 mmc0_pins_fixup: mmc0-pins-fixup {
-                                        fsl,pinmux-ids = <0x2010 0x2060>;
+                                        fsl,pinmux-ids = <
+                                                0x2010 /* MX23_PAD_SSP1_DETECT__SSP1_DETECT */
+                                                0x2060 /* MX23_PAD_SSP1_SCK__SSP1_SCK */
+                                        >;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                pwm2_pins_a: pwm2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11c0 /* MX23_PAD_PWM2__PWM2 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_24bit_pins_a: lcdif-24bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX23_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX23_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX23_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX23_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX23_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX23_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX23_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX23_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX23_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX23_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX23_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX23_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX23_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX23_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX23_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX23_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX23_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX23_PAD_LCD_D17__LCD_D17 */
+                                                0x0081 /* MX23_PAD_GPMI_D08__LCD_D18 */
+                                                0x0091 /* MX23_PAD_GPMI_D09__LCD_D19 */
+                                                0x00a1 /* MX23_PAD_GPMI_D10__LCD_D20 */
+                                                0x00b1 /* MX23_PAD_GPMI_D11__LCD_D21 */
+                                                0x00c1 /* MX23_PAD_GPMI_D12__LCD_D22 */
+                                                0x00d1 /* MX23_PAD_GPMI_D13__LCD_D23 */
+                                                0x1160 /* MX23_PAD_LCD_DOTCK__LCD_DOTCK */
+                                                0x1170 /* MX23_PAD_LCD_ENABLE__LCD_ENABLE */
+                                                0x1180 /* MX23_PAD_LCD_HSYNC__LCD_HSYNC */
+                                                0x1190 /* MX23_PAD_LCD_VSYNC__LCD_VSYNC */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
                                 };
                         };
@@ -172,7 +303,9 @@
                         };
 
                         lcdif@80030000 {
+                                compatible = "fsl,imx23-lcdif";
                                 reg = <0x80030000 2000>;
+                                interrupts = <46 45>;
                                 status = "disabled";
                         };
 
@@ -242,12 +375,16 @@
                         };
 
                         rtc@8005c000 {
+                                compatible = "fsl,imx23-rtc", "fsl,stmp3xxx-rtc";
                                 reg = <0x8005c000 2000>;
-                                status = "disabled";
+                                interrupts = <22>;
                         };
 
-                        pwm@80064000 {
+                        pwm: pwm@80064000 {
+                                compatible = "fsl,imx23-pwm";
                                 reg = <0x80064000 2000>;
+                                #pwm-cells = <2>;
+                                fsl,pwm-number = <5>;
                                 status = "disabled";
                         };
 
@@ -257,12 +394,16 @@
                         };
 
                         auart0: serial@8006c000 {
+                                compatible = "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
+                                interrupts = <24 25 23>;
                                 status = "disabled";
                         };
 
                         auart1: serial@8006e000 {
+                                compatible = "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
+                                interrupts = <59 60 58>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/imx27-3ds.dts b/arch/arm/boot/dts/imx27-3ds.dts
new file mode 100644
index 000000000000..d3f8296e19e0
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-3ds.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx27.dtsi"
+
+/ {
+        model = "mx27_3ds";
+        compatible = "freescale,imx27-3ds", "fsl,imx27";
+
+        memory {
+                reg = <0x0 0x0>;
+        };
+
+        soc {
+                aipi@10000000 { /* aipi */
+
+                        wdog@10002000 {
+                                status = "okay";
+                        };
+
+                        uart@1000a000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+
+                        fec@1002b000 {
+                                status = "okay";
+                        };
+                };
+        };
+
+};
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 386c769c38d1..00bae3aad5ab 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -121,7 +121,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@10015100 {
@@ -131,7 +131,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@10015200 {
@@ -141,7 +141,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@10015300 {
@@ -151,7 +151,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio5: gpio@10015400 {
@@ -161,7 +161,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@10015500 {
@@ -171,7 +171,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         cspi3: cspi@10017000 {
diff --git a/arch/arm/boot/dts/imx28-apx4devkit.dts b/arch/arm/boot/dts/imx28-apx4devkit.dts
new file mode 100644
index 000000000000..b383417a558f
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-apx4devkit.dts
@@ -0,0 +1,198 @@
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Bluegiga APX4 Development Kit";
+        compatible = "bluegiga,apx4devkit", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x04000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+                                status = "okay";
+                        };
+
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        ssp2: ssp@80014000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc2_4bit_pins_apx4 &mmc2_sck_cfg_apx4>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0113 /* MX28_PAD_GPMI_CE1N__GPIO_0_17 */
+                                                0x0153 /* MX28_PAD_GPMI_RDY1__GPIO_0_21 */
+                                                0x2123 /* MX28_PAD_SSP2_MISO__GPIO_2_18 */
+                                                0x2131 /* MX28_PAD_SSP2_SS0__GPIO_2_19 */
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                                0x4143 /* MX28_PAD_JTAG_RTCK__GPIO_4_20 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_apx4: lcdif-apx4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                mmc2_4bit_pins_apx4: mmc2-4bit-apx4@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2041 /* MX28_PAD_SSP0_DATA4__SSP2_D0 */
+                                                0x2051 /* MX28_PAD_SSP0_DATA5__SSP2_D3 */
+                                                0x2061 /* MX28_PAD_SSP0_DATA6__SSP2_CMD */
+                                                0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
+                                                0x2141 /* MX28_PAD_SSP2_SS1__SSP2_D1 */
+                                                0x2151 /* MX28_PAD_SSP2_SS2__SSP2_D2 */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                mmc2_sck_cfg_apx4: mmc2-sck-cfg-apx4 {
+                                        fsl,pinmux-ids = <
+                                                0x2071 /* MX28_PAD_SSP0_DATA7__SSP2_SCK */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_apx4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        saif0: saif@80042000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif0_pins_a>;
+                                status = "okay";
+                        };
+
+                        saif1: saif@80046000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif1_pins_a>;
+                                fsl,saif-master = <&saif0>;
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                sgtl5000: codec@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_3p3v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+
+                                };
+
+                                pcf8563: rtc@51 {
+                                        compatible = "phg,pcf8563";
+                                        reg = <0x51>;
+                                };
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_2pins_a>;
+                                status = "okay";
+                        };
+
+                        auart2: serial@8006e000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart2_2pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "bluegiga,apx4devkit-sgtl5000",
+                             "fsl,mxs-audio-sgtl5000";
+                model = "apx4devkit-sgtl5000";
+                saif-controllers = <&saif0 &saif1>;
+                audio-codec = <&sgtl5000>;
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 28 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
new file mode 100644
index 000000000000..c03a577beca3
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2012 Free Electrons
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Crystalfontz CFA-10036 Board";
+        compatible = "crystalfontz,cfa10036", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a
+                                        &mmc0_cd_cfg &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_b>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                power {
+                        gpios = <&gpio3 4 1>;
+                        default-state = "on";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-evk.dts b/arch/arm/boot/dts/imx28-evk.dts
index ee520a529cb4..773c0e84d1fb 100644
--- a/arch/arm/boot/dts/imx28-evk.dts
+++ b/arch/arm/boot/dts/imx28-evk.dts
@@ -22,6 +22,13 @@
 
         apb@80000000 {
                 apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg
+                                             &gpmi_pins_evk>;
+                                status = "okay";
+                        };
+
                         ssp0: ssp@80010000 {
                                 compatible = "fsl,imx28-mmc";
                                 pinctrl-names = "default";
@@ -29,6 +36,7 @@
                                         &mmc0_cd_cfg &mmc0_sck_cfg>;
                                 bus-width = <8>;
                                 wp-gpios = <&gpio2 12 0>;
+                                vmmc-supply = <&reg_vddio_sd0>;
                                 status = "okay";
                         };
 
@@ -36,6 +44,72 @@
                                 compatible = "fsl,imx28-mmc";
                                 bus-width = <8>;
                                 wp-gpios = <&gpio0 28 0>;
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x20d3 /* MX28_PAD_SSP1_CMD__GPIO_2_13 */
+                                                0x20f3 /* MX28_PAD_SSP1_DATA3__GPIO_2_15 */
+                                                0x40d3 /* MX28_PAD_ENET0_RX_CLK__GPIO_4_13 */
+                                                0x20c3 /* MX28_PAD_SSP1_SCK__GPIO_2_12 */
+                                                0x31c3 /* MX28_PAD_PWM3__GPIO_3_28 */
+                                                0x31e3 /* MX28_PAD_LCD_RESET__GPIO_3_30 */
+                                                0x3053 /* MX28_PAD_AUART1_TX__GPIO_3_5 */
+                                                0x3083 /* MX28_PAD_AUART2_RX__GPIO_3_8 */
+                                                0x3093 /* MX28_PAD_AUART2_TX__GPIO_3_9 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_evk: gpmi-nand-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0110 /* MX28_PAD_GPMI_CE1N__GPMI_CE1N */
+                                                0x0150 /* MX28_PAD_GPMI_RDY1__GPMI_READY1 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_evk: lcdif-evk@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */
+                                                0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */
+                                                0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */
+                                                0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_evk>;
+                                panel-enable-gpios = <&gpio3 30 0>;
+                                status = "okay";
+                        };
+
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                status = "okay";
+                        };
+
+                        can1: can@80034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can1_pins_a>;
                                 status = "okay";
                         };
                 };
@@ -68,19 +142,58 @@
                                 };
                         };
 
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm2_pins_a>;
+                                status = "okay";
+                        };
+
                         duart: serial@80074000 {
                                 pinctrl-names = "default";
                                 pinctrl-0 = <&duart_pins_a>;
                                 status = "okay";
                         };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart3: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart3_pins_a>;
+                                status = "okay";
+                        };
+
+                        usbphy0: usbphy@8007c000 {
+                                status = "okay";
+                        };
+
+                        usbphy1: usbphy@8007e000 {
+                                status = "okay";
+                        };
                 };
         };
 
         ahb@80080000 {
+                usb0: usb@80080000 {
+                        vbus-supply = <&reg_usb0_vbus>;
+                        status = "okay";
+                };
+
+                usb1: usb@80090000 {
+                        vbus-supply = <&reg_usb1_vbus>;
+                        status = "okay";
+                };
+
                 mac0: ethernet@800f0000 {
                         phy-mode = "rmii";
                         pinctrl-names = "default";
                         pinctrl-0 = <&mac0_pins_a>;
+                        phy-supply = <&reg_fec_3v3>;
+                        phy-reset-gpios = <&gpio4 13 0>;
+                        phy-reset-duration = <100>;
                         status = "okay";
                 };
 
@@ -102,6 +215,40 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_vddio_sd0: vddio-sd0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "vddio-sd0";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio3 28 0>;
+                };
+
+                reg_fec_3v3: fec-3v3 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "fec-3v3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        gpio = <&gpio2 15 0>;
+                };
+
+                reg_usb0_vbus: usb0_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb0_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 9 0>;
+                        enable-active-high;
+                };
+
+                reg_usb1_vbus: usb1_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb1_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 8 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
@@ -111,4 +258,21 @@
                 saif-controllers = <&saif0 &saif1>;
                 audio-codec = <&sgtl5000>;
         };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio3 5 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 2 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
 };
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
new file mode 100644
index 000000000000..183a3fd2d859
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -0,0 +1,210 @@
+/*
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "DENX M28EVK";
+        compatible = "denx,m28evk", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        gpmi-nand@8000c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
+                                status = "okay";
+
+                                partition@0 {
+                                        label = "bootloader";
+                                        reg = <0x00000000 0x00300000>;
+                                        read-only;
+                                };
+
+                                partition@1 {
+                                        label = "environment";
+                                        reg = <0x00300000 0x00080000>;
+                                };
+
+                                partition@2 {
+                                        label = "redundant-environment";
+                                        reg = <0x00380000 0x00080000>;
+                                };
+
+                                partition@3 {
+                                        label = "kernel";
+                                        reg = <0x00400000 0x00400000>;
+                                };
+
+                                partition@4 {
+                                        label = "filesystem";
+                                        reg = <0x00800000 0x0f800000>;
+                                };
+                        };
+
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_8bit_pins_a
+                                             &mmc0_cd_cfg
+                                             &mmc0_sck_cfg>;
+                                bus-width = <8>;
+                                wp-gpios = <&gpio3 10 1>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x30a3 /* MX28_PAD_AUART2_CTS__GPIO_3_10 */
+                                                0x30b3 /* MX28_PAD_AUART2_RTS__GPIO_3_11 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_pins_m28: lcdif-m28@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x11e0 /* MX28_PAD_LCD_DOTCLK__LCD_DOTCLK */
+                                                0x11f0 /* MX28_PAD_LCD_ENABLE__LCD_ENABLE */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+
+                        lcdif@80030000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&lcdif_24bit_pins_a
+                                             &lcdif_pins_m28>;
+                                status = "okay";
+                        };
+
+                        can0: can@80032000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can0_pins_a>;
+                                status = "okay";
+                        };
+
+                        can1: can@80034000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&can1_pins_a>;
+                                status = "okay";
+                        };
+                };
+
+                apbx@80040000 {
+                        saif0: saif@80042000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif0_pins_a>;
+                                status = "okay";
+                        };
+
+                        saif1: saif@80046000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&saif1_pins_a>;
+                                fsl,saif-master = <&saif0>;
+                                status = "okay";
+                        };
+
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                sgtl5000: codec@0a {
+                                        compatible = "fsl,sgtl5000";
+                                        reg = <0x0a>;
+                                        VDDA-supply = <&reg_3p3v>;
+                                        VDDIO-supply = <&reg_3p3v>;
+
+                                };
+
+                                eeprom: eeprom@51 {
+                                        compatible = "atmel,24c128";
+                                        reg = <0x51>;
+                                        pagesize = <32>;
+                                };
+
+                                rtc: rtc@68 {
+                                        compatible = "stm,mt41t62";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_pins_a>;
+                                status = "okay";
+                        };
+
+                        auart0: serial@8006a000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart0_2pins_a>;
+                                status = "okay";
+                        };
+
+                        auart3: serial@80070000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart3_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        phy-reset-gpios = <&gpio3 11 0>;
+                        status = "okay";
+                };
+
+                mac1: ethernet@800f4000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac1_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        regulators {
+                compatible = "simple-bus";
+
+                reg_3p3v: 3p3v {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3P3V";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
+        };
+
+        sound {
+                compatible = "denx,m28evk-sgtl5000",
+                             "fsl,mxs-audio-sgtl5000";
+                model = "m28evk-sgtl5000";
+                saif-controllers = <&saif0 &saif1>;
+                audio-codec = <&sgtl5000>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
new file mode 100644
index 000000000000..62bf767409a6
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -0,0 +1,97 @@
+/dts-v1/;
+/include/ "imx28.dtsi"
+
+/ {
+        model = "Ka-Ro electronics TX28 module";
+        compatible = "karo,tx28", "fsl,imx28";
+
+        memory {
+                reg = <0x40000000 0x08000000>;
+        };
+
+        apb@80000000 {
+                apbh@80000000 {
+                        ssp0: ssp@80010000 {
+                                compatible = "fsl,imx28-mmc";
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&mmc0_4bit_pins_a
+                                             &mmc0_cd_cfg
+                                             &mmc0_sck_cfg>;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
+
+                        pinctrl@80018000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&hog_pins_a>;
+
+                                hog_pins_a: hog-gpios@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+                        };
+                };
+
+                apbx@80040000 {
+                        i2c0: i2c@80058000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&i2c0_pins_a>;
+                                status = "okay";
+
+                                ds1339: rtc@68 {
+                                        compatible = "mxim,ds1339";
+                                        reg = <0x68>;
+                                };
+                        };
+
+                        pwm: pwm@80064000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pwm0_pins_a>;
+                                status = "okay";
+                        };
+
+                        duart: serial@80074000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&duart_4pins_a>;
+                                status = "okay";
+                        };
+
+                        auart1: serial@8006c000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&auart1_pins_a>;
+                                status = "okay";
+                        };
+                };
+        };
+
+        ahb@80080000 {
+                mac0: ethernet@800f0000 {
+                        phy-mode = "rmii";
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&mac0_pins_a>;
+                        status = "okay";
+                };
+        };
+
+        leds {
+                compatible = "gpio-leds";
+
+                user {
+                        label = "Heartbeat";
+                        gpios = <&gpio4 10 0>;
+                        linux,default-trigger = "heartbeat";
+                };
+        };
+
+        backlight {
+                compatible = "pwm-backlight";
+                pwms = <&pwm 0 5000000>;
+                brightness-levels = <0 4 8 16 32 64 128 255>;
+                default-brightness-level = <6>;
+        };
+};
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 4634cb861a59..915db89e3644 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -22,6 +22,11 @@
                 gpio4 = &gpio4;
                 saif0 = &saif0;
                 saif1 = &saif1;
+                serial0 = &auart0;
+                serial1 = &auart1;
+                serial2 = &auart2;
+                serial3 = &auart3;
+                serial4 = &auart4;
         };
 
         cpus {
@@ -68,15 +73,15 @@
                                 status = "disabled";
                         };
 
-                        bch@8000a000 {
-                                reg = <0x8000a000 2000>;
-                                interrupts = <41>;
-                                status = "disabled";
-                        };
-
-                        gpmi@8000c000 {
-                                reg = <0x8000c000 2000>;
-                                interrupts = <42 88>;
+                        gpmi-nand@8000c000 {
+                                compatible = "fsl,imx28-gpmi-nand";
+                                #address-cells = <1>;
+                                #size-cells = <1>;
+                                reg = <0x8000c000 2000>, <0x8000a000 2000>;
+                                reg-names = "gpmi-nand", "bch";
+                                interrupts = <88>, <41>;
+                                interrupt-names = "gpmi-dma", "bch";
+                                fsl,gpmi-dma-channel = <4>;
                                 status = "disabled";
                         };
 
@@ -161,7 +166,150 @@
 
                                 duart_pins_a: duart@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x3102 0x3112>;
+                                        fsl,pinmux-ids = <
+                                                0x3102 /* MX28_PAD_PWM0__DUART_RX */
+                                                0x3112 /* MX28_PAD_PWM1__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                duart_pins_b: duart@1 {
+                                        reg = <1>;
+                                        fsl,pinmux-ids = <
+                                                0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+                                                0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                duart_4pins_a: duart-4pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */
+                                                0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */
+                                                0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */
+                                                0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_pins_a: gpmi-nand@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */
+                                                0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */
+                                                0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */
+                                                0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */
+                                                0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */
+                                                0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */
+                                                0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */
+                                                0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */
+                                                0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */
+                                                0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */
+                                                0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */
+                                                0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */
+                                                0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                gpmi_status_cfg: gpmi-status-cfg {
+                                        fsl,pinmux-ids = <
+                                                0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */
+                                                0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */
+                                                0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */
+                                        >;
+                                        fsl,drive-strength = <2>;
+                                };
+
+                                auart0_pins_a: auart0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+                                                0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+                                                0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */
+                                                0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart0_2pins_a: auart0-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */
+                                                0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart1_pins_a: auart1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+                                                0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+                                                0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */
+                                                0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart1_2pins_a: auart1-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */
+                                                0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart2_2pins_a: auart2-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */
+                                                0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart3_pins_a: auart3@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */
+                                                0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */
+                                                0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */
+                                                0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                auart3_2pins_a: auart3-2pins@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */
+                                                0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */
+                                        >;
                                         fsl,drive-strength = <0>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <0>;
@@ -169,9 +317,17 @@
 
                                 mac0_pins_a: mac0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x4000 0x4010 0x4020
-                                                0x4030 0x4040 0x4060 0x4070
-                                                0x4080 0x4100>;
+                                        fsl,pinmux-ids = <
+                                                0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */
+                                                0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */
+                                                0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */
+                                                0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */
+                                                0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */
+                                                0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */
+                                                0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */
+                                                0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */
+                                                0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -179,8 +335,14 @@
 
                                 mac1_pins_a: mac1@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x40f1 0x4091 0x40a1
-                                                0x40e1 0x40b1 0x40c1>;
+                                        fsl,pinmux-ids = <
+                                                0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */
+                                                0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */
+                                                0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */
+                                                0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */
+                                                0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */
+                                                0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -188,28 +350,61 @@
 
                                 mmc0_8bit_pins_a: mmc0-8bit@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x2000 0x2010 0x2020
-                                                0x2030 0x2040 0x2050 0x2060
-                                                0x2070 0x2080 0x2090 0x20a0>;
+                                        fsl,pinmux-ids = <
+                                                0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+                                                0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+                                                0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+                                                0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+                                                0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */
+                                                0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */
+                                                0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */
+                                                0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */
+                                                0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
+                                        fsl,drive-strength = <1>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <1>;
+                                };
+
+                                mmc0_4bit_pins_a: mmc0-4bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */
+                                                0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */
+                                                0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */
+                                                0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */
+                                                0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
 
                                 mmc0_cd_cfg: mmc0-cd-cfg {
-                                        fsl,pinmux-ids = <0x2090>;
+                                        fsl,pinmux-ids = <
+                                                0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */
+                                        >;
                                         fsl,pull-up = <0>;
                                 };
 
                                 mmc0_sck_cfg: mmc0-sck-cfg {
-                                        fsl,pinmux-ids = <0x20a0>;
+                                        fsl,pinmux-ids = <
+                                                0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,pull-up = <0>;
                                 };
 
                                 i2c0_pins_a: i2c0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x3180 0x3190>;
+                                        fsl,pinmux-ids = <
+                                                0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */
+                                                0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */
+                                        >;
                                         fsl,drive-strength = <1>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -217,8 +412,12 @@
 
                                 saif0_pins_a: saif0@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids =
-                                                <0x3140 0x3150 0x3160 0x3170>;
+                                        fsl,pinmux-ids = <
+                                                0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */
+                                                0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */
+                                                0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */
+                                                0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
@@ -226,11 +425,88 @@
 
                                 saif1_pins_a: saif1@0 {
                                         reg = <0>;
-                                        fsl,pinmux-ids = <0x31a0>;
+                                        fsl,pinmux-ids = <
+                                                0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */
+                                        >;
                                         fsl,drive-strength = <2>;
                                         fsl,voltage = <1>;
                                         fsl,pull-up = <1>;
                                 };
+
+                                pwm0_pins_a: pwm0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3100 /* MX28_PAD_PWM0__PWM_0 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                pwm2_pins_a: pwm2@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x3120 /* MX28_PAD_PWM2__PWM_2 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                lcdif_24bit_pins_a: lcdif-24bit@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */
+                                                0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */
+                                                0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */
+                                                0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */
+                                                0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */
+                                                0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */
+                                                0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */
+                                                0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */
+                                                0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */
+                                                0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */
+                                                0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */
+                                                0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */
+                                                0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */
+                                                0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */
+                                                0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */
+                                                0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */
+                                                0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */
+                                                0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */
+                                                0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */
+                                                0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */
+                                                0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */
+                                                0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */
+                                                0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */
+                                                0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                can0_pins_a: can0@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */
+                                                0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
+
+                                can1_pins_a: can1@0 {
+                                        reg = <0>;
+                                        fsl,pinmux-ids = <
+                                                0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */
+                                                0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */
+                                        >;
+                                        fsl,drive-strength = <0>;
+                                        fsl,voltage = <1>;
+                                        fsl,pull-up = <0>;
+                                };
                         };
 
                         digctl@8001c000 {
@@ -272,18 +548,21 @@
                         };
 
                         lcdif@80030000 {
+                                compatible = "fsl,imx28-lcdif";
                                 reg = <0x80030000 2000>;
                                 interrupts = <38 86>;
                                 status = "disabled";
                         };
 
                         can0: can@80032000 {
+                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80032000 2000>;
                                 interrupts = <8>;
                                 status = "disabled";
                         };
 
                         can1: can@80034000 {
+                                compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
                                 reg = <0x80034000 2000>;
                                 interrupts = <9>;
                                 status = "disabled";
@@ -370,9 +649,9 @@
                         };
 
                         rtc@80056000 {
+                                compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
                                 reg = <0x80056000 2000>;
-                                interrupts = <28 29>;
-                                status = "disabled";
+                                interrupts = <29>;
                         };
 
                         i2c0: i2c@80058000 {
@@ -393,8 +672,11 @@
                                 status = "disabled";
                         };
 
-                        pwm@80064000 {
+                        pwm: pwm@80064000 {
+                                compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
                                 reg = <0x80064000 2000>;
+                                #pwm-cells = <2>;
+                                fsl,pwm-number = <8>;
                                 status = "disabled";
                         };
 
@@ -404,30 +686,35 @@
                         };
 
                         auart0: serial@8006a000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006a000 0x2000>;
                                 interrupts = <112 70 71>;
                                 status = "disabled";
                         };
 
                         auart1: serial@8006c000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006c000 0x2000>;
                                 interrupts = <113 72 73>;
                                 status = "disabled";
                         };
 
                         auart2: serial@8006e000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x8006e000 0x2000>;
                                 interrupts = <114 74 75>;
                                 status = "disabled";
                         };
 
                         auart3: serial@80070000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80070000 0x2000>;
                                 interrupts = <115 76 77>;
                                 status = "disabled";
                         };
 
                         auart4: serial@80072000 {
+                                compatible = "fsl,imx28-auart", "fsl,imx23-auart";
                                 reg = <0x80072000 0x2000>;
                                 interrupts = <116 78 79>;
                                 status = "disabled";
@@ -441,11 +728,13 @@
                         };
 
                         usbphy0: usbphy@8007c000 {
+                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007c000 0x2000>;
                                 status = "disabled";
                         };
 
                         usbphy1: usbphy@8007e000 {
+                                compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x8007e000 0x2000>;
                                 status = "disabled";
                         };
@@ -459,13 +748,19 @@
                 reg = <0x80080000 0x80000>;
                 ranges;
 
-                usbctrl0: usbctrl@80080000 {
+                usb0: usb@80080000 {
+                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80080000 0x10000>;
+                        interrupts = <93>;
+                        fsl,usbphy = <&usbphy0>;
                         status = "disabled";
                 };
 
-                usbctrl1: usbctrl@80090000 {
+                usb1: usb@80090000 {
+                        compatible = "fsl,imx28-usb", "fsl,imx27-usb";
                         reg = <0x80090000 0x10000>;
+                        interrupts = <92>;
+                        fsl,usbphy = <&usbphy1>;
                         status = "disabled";
                 };
 
diff --git a/arch/arm/boot/dts/imx31-bug.dts b/arch/arm/boot/dts/imx31-bug.dts
new file mode 100644
index 000000000000..24731cb78e8e
--- /dev/null
+++ b/arch/arm/boot/dts/imx31-bug.dts
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+/include/ "imx31.dtsi"
+
+/ {
+        model = "Buglabs i.MX31 Bug 1.x";
+        compatible = "fsl,imx31-bug", "fsl,imx31";
+
+        memory {
+                reg = <0x80000000 0x8000000>; /* 128M */
+        };
+
+        soc {
+                aips@43f00000 { /* AIPS1 */
+                        uart5: serial@43fb4000 {
+                                fsl,uart-has-rtscts;
+                                status = "okay";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
new file mode 100644
index 000000000000..eef7099f3e3c
--- /dev/null
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -0,0 +1,88 @@
+/*
+ * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/include/ "skeleton.dtsi"
+
+/ {
+        aliases {
+                serial0 = &uart1;
+                serial1 = &uart2;
+                serial2 = &uart3;
+                serial3 = &uart4;
+                serial4 = &uart5;
+        };
+
+        avic: avic-interrupt-controller@60000000 {
+                compatible = "fsl,imx31-avic", "fsl,avic";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0x60000000 0x100000>;
+        };
+
+        soc {
+                #address-cells = <1>;
+                #size-cells = <1>;
+                compatible = "simple-bus";
+                interrupt-parent = <&avic>;
+                ranges;
+
+                aips@43f00000 { /* AIPS1 */
+                        compatible = "fsl,aips-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x43f00000 0x100000>;
+                        ranges;
+
+                        uart1: serial@43f90000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43f90000 0x4000>;
+                                interrupts = <45>;
+                                status = "disabled";
+                        };
+
+                        uart2: serial@43f94000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43f94000 0x4000>;
+                                interrupts = <32>;
+                                status = "disabled";
+                        };
+
+                        uart4: serial@43fb0000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43fb0000 0x4000>;
+                                interrupts = <46>;
+                                status = "disabled";
+                        };
+
+                        uart5: serial@43fb4000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x43fb4000 0x4000>;
+                                interrupts = <47>;
+                                status = "disabled";
+                        };
+                };
+
+                spba@50000000 {
+                        compatible = "fsl,spba-bus", "simple-bus";
+                        #address-cells = <1>;
+                        #size-cells = <1>;
+                        reg = <0x50000000 0x100000>;
+                        ranges;
+
+                        uart3: serial@5000c000 {
+                                compatible = "fsl,imx31-uart", "fsl,imx21-uart";
+                                reg = <0x5000c000 0x4000>;
+                                interrupts = <18>;
+                                status = "disabled";
+                        };
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bfa65abe8ef2..922adefdd291 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -133,7 +133,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@73f88000 {
@@ -143,7 +143,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@73f8c000 {
@@ -153,7 +153,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@73f90000 {
@@ -163,7 +163,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         wdog@73f98000 { /* WDOG1 */
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index e3e869470cd3..4e735edc78ed 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -135,7 +135,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@53f88000 {
@@ -145,7 +145,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@53f8c000 {
@@ -155,7 +155,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@53f90000 {
@@ -165,7 +165,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         wdog@53f98000 { /* WDOG1 */
@@ -203,7 +203,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@53fe0000 {
@@ -213,7 +213,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio7: gpio@53fe4000 {
@@ -223,7 +223,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         i2c@53fec000 { /* I2C3 */
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index db4c6096c562..d792581672cc 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -22,6 +22,12 @@
         };
 
         soc {
+                gpmi-nand@00112000 {
+                        pinctrl-names = "default";
+                        pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+                        status = "disabled"; /* gpmi nand conflicts with SD */
+                };
+
                 aips-bus@02100000 { /* AIPS2 */
                         ethernet@02188000 {
                                 phy-mode = "rgmii";
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index e0ec92973e7e..d42e851ceb97 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -27,6 +27,8 @@
                                 ecspi@02008000 { /* eCSPI1 */
                                         fsl,spi-num-chipselects = <1>;
                                         cs-gpios = <&gpio3 19 0>;
+                                        pinctrl-names = "default";
+                                        pinctrl-0 = <&pinctrl_ecspi1_1>;
                                         status = "okay";
 
                                         flash: m25p80@0 {
@@ -42,9 +44,31 @@
                                 };
                         };
 
+                        iomuxc@020e0000 {
+                                pinctrl-names = "default";
+                                pinctrl-0 = <&pinctrl_gpio_hog>;
+
+                                gpios {
+                                        pinctrl_gpio_hog: gpiohog {
+                                                fsl,pins = <
+                                                           144  0x80000000      /* MX6Q_PAD_EIM_D22__GPIO_3_22 */
+                                                           121  0x80000000      /* MX6Q_PAD_EIM_D19__GPIO_3_19 */
+                                                           >;
+                                        };
+                                };
+                        };
                 };
 
                 aips-bus@02100000 { /* AIPS2 */
+                        usb@02184000 { /* USB OTG */
+                                vbus-supply = <&reg_usb_otg_vbus>;
+                                status = "okay";
+                        };
+
+                        usb@02184200 { /* USB1 */
+                                status = "okay";
+                        };
+
                         ethernet@02188000 {
                                 phy-mode = "rgmii";
                                 phy-reset-gpios = <&gpio3 23 0>;
@@ -111,6 +135,15 @@
                         regulator-max-microvolt = <3300000>;
                         regulator-always-on;
                 };
+
+                reg_usb_otg_vbus: usb_otg_vbus {
+                        compatible = "regulator-fixed";
+                        regulator-name = "usb_otg_vbus";
+                        regulator-min-microvolt = <5000000>;
+                        regulator-max-microvolt = <5000000>;
+                        gpio = <&gpio3 22 0>;
+                        enable-active-high;
+                };
         };
 
         sound {
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 8c90cbac945f..c25d49584814 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -87,6 +87,23 @@
                 interrupt-parent = <&intc>;
                 ranges;
 
+                dma-apbh@00110000 {
+                        compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
+                        reg = <0x00110000 0x2000>;
+                };
+
+                gpmi-nand@00112000 {
+                       compatible = "fsl,imx6q-gpmi-nand";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
+                       reg-names = "gpmi-nand", "bch";
+                       interrupts = <0 13 0x04>, <0 15 0x04>;
+                       interrupt-names = "gpmi-dma", "bch";
+                       fsl,gpmi-dma-channel = <0>;
+                       status = "disabled";
+                };
+
                 timer@00a00600 {
                         compatible = "arm,cortex-a9-twd-timer";
                         reg = <0x00a00600 0x20>;
@@ -266,7 +283,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio2: gpio@020a0000 {
@@ -276,7 +293,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio3: gpio@020a4000 {
@@ -286,7 +303,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio4: gpio@020a8000 {
@@ -296,7 +313,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio5: gpio@020ac000 {
@@ -306,7 +323,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio6: gpio@020b0000 {
@@ -316,7 +333,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         gpio7: gpio@020b4000 {
@@ -326,7 +343,7 @@
                                 gpio-controller;
                                 #gpio-cells = <2>;
                                 interrupt-controller;
-                                #interrupt-cells = <1>;
+                                #interrupt-cells = <2>;
                         };
 
                         kpp@020b8000 {
@@ -444,12 +461,14 @@
                                 };
                         };
 
-                        usbphy@020c9000 { /* USBPHY1 */
+                        usbphy1: usbphy@020c9000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020c9000 0x1000>;
                                 interrupts = <0 44 0x04>;
                         };
 
-                        usbphy@020ca000 { /* USBPHY2 */
+                        usbphy2: usbphy@020ca000 {
+                                compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
                                 reg = <0x020ca000 0x1000>;
                                 interrupts = <0 45 0x04>;
                         };
@@ -495,6 +514,30 @@
                                         };
                                 };
 
+                                gpmi-nand {
+                                        pinctrl_gpmi_nand_1: gpmi-nand-1 {
+                                                fsl,pins = <1328 0xb0b1         /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
+                                                            1336 0xb0b1         /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
+                                                            1344 0xb0b1         /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
+                                                            1352 0xb000         /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
+                                                            1360 0xb0b1         /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
+                                                            1365 0xb0b1         /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
+                                                            1371 0xb0b1         /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
+                                                            1378 0xb0b1         /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
+                                                            1387 0xb0b1         /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
+                                                            1393 0xb0b1         /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
+                                                            1397 0xb0b1         /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
+                                                            1405 0xb0b1         /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
+                                                            1413 0xb0b1         /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
+                                                            1421 0xb0b1         /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
+                                                            1429 0xb0b1         /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
+                                                            1437 0xb0b1         /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
+                                                            1445 0xb0b1         /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
+                                                            1453 0xb0b1         /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
+                                                            1463 0x00b1>;       /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
+                                        };
+                                };
+
                                 i2c1 {
                                         pinctrl_i2c1_1: i2c1grp-1 {
                                                 fsl,pins = <137 0x4001b8b1      /* MX6Q_PAD_EIM_D21__I2C1_SCL */
@@ -538,6 +581,14 @@
                                                             1517 0x17059>;      /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
                                         };
                                 };
+
+                                ecspi1 {
+                                        pinctrl_ecspi1_1: ecspi1grp-1 {
+                                                fsl,pins = <101 0x100b1         /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
+                                                            109 0x100b1         /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
+                                                            94  0x100b1>;       /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
+                                        };
+                                };
                         };
 
                         dcic@020e4000 { /* DCIC1 */
@@ -573,6 +624,36 @@
                                 reg = <0x0217c000 0x4000>;
                         };
 
+                        usb@02184000 { /* USB OTG */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184000 0x200>;
+                                interrupts = <0 43 0x04>;
+                                fsl,usbphy = <&usbphy1>;
+                                status = "disabled";
+                        };
+
+                        usb@02184200 { /* USB1 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184200 0x200>;
+                                interrupts = <0 40 0x04>;
+                                fsl,usbphy = <&usbphy2>;
+                                status = "disabled";
+                        };
+
+                        usb@02184400 { /* USB2 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184400 0x200>;
+                                interrupts = <0 41 0x04>;
+                                status = "disabled";
+                        };
+
+                        usb@02184600 { /* USB3 */
+                                compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
+                                reg = <0x02184600 0x200>;
+                                interrupts = <0 42 0x04>;
+                                status = "disabled";
+                        };
+
                         ethernet@02188000 {
                                 compatible = "fsl,imx6q-fec";
                                 reg = <0x02188000 0x4000>;
diff --git a/arch/arm/boot/dts/lpc32xx.dtsi b/arch/arm/boot/dts/lpc32xx.dtsi
index 3f5dad801a98..e5ffe960dbf3 100644
--- a/arch/arm/boot/dts/lpc32xx.dtsi
+++ b/arch/arm/boot/dts/lpc32xx.dtsi
@@ -35,13 +35,14 @@
                 slc: flash@20020000 {
                         compatible = "nxp,lpc3220-slc";
                         reg = <0x20020000 0x1000>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
-                mlc: flash@200B0000 {
+                mlc: flash@200a8000 {
                         compatible = "nxp,lpc3220-mlc";
-                        reg = <0x200B0000 0x1000>;
-                        status = "disable";
+                        reg = <0x200a8000 0x11000>;
+                        interrupts = <11 0>;
+                        status = "disabled";
                 };
 
                 dma@31000000 {
@@ -57,21 +58,21 @@
                         compatible = "nxp,ohci-nxp", "usb-ohci";
                         reg = <0x31020000 0x300>;
                         interrupts = <0x3b 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 usbd@31020000 {
                         compatible = "nxp,lpc3220-udc";
                         reg = <0x31020000 0x300>;
                         interrupts = <0x3d 0>, <0x3e 0>, <0x3c 0>, <0x3a 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 clcd@31040000 {
                         compatible = "arm,pl110", "arm,primecell";
                         reg = <0x31040000 0x1000>;
                         interrupts = <0x0e 0>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 mac: ethernet@31060000 {
@@ -114,9 +115,10 @@
                         };
 
                         sd@20098000 {
-                                compatible = "arm,pl180", "arm,primecell";
+                                compatible = "arm,pl18x", "arm,primecell";
                                 reg = <0x20098000 0x1000>;
                                 interrupts = <0x0f 0>, <0x0d 0>;
+                                status = "disabled";
                         };
 
                         i2s1: i2s@2009C000 {
@@ -124,24 +126,42 @@
                                 reg = <0x2009C000 0x1000>;
                         };
 
+                        /* UART5 first since it is the default console, ttyS0 */
+                        uart5: serial@40090000 {
+                                /* actually, ns16550a w/ 64 byte fifos! */
+                                compatible = "nxp,lpc3220-uart";
+                                reg = <0x40090000 0x1000>;
+                                interrupts = <9 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
+                        };
+
                         uart3: serial@40080000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40080000 0x1000>;
+                                interrupts = <7 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         uart4: serial@40088000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40088000 0x1000>;
-                        };
-
-                        uart5: serial@40090000 {
-                                compatible = "nxp,serial";
-                                reg = <0x40090000 0x1000>;
+                                interrupts = <8 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         uart6: serial@40098000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-uart";
                                 reg = <0x40098000 0x1000>;
+                                interrupts = <10 0>;
+                                clock-frequency = <13000000>;
+                                reg-shift = <2>;
+                                status = "disabled";
                         };
 
                         i2c1: i2c@400A0000 {
@@ -192,18 +212,24 @@
                         };
 
                         uart1: serial@40014000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-hsuart";
                                 reg = <0x40014000 0x1000>;
+                                interrupts = <26 0>;
+                                status = "disabled";
                         };
 
                         uart2: serial@40018000 {
-                                compatible = "nxp,serial";
+                                compatible = "nxp,lpc3220-hsuart";
                                 reg = <0x40018000 0x1000>;
+                                interrupts = <25 0>;
+                                status = "disabled";
                         };
 
-                        uart7: serial@4001C000 {
-                                compatible = "nxp,serial";
-                                reg = <0x4001C000 0x1000>;
+                        uart7: serial@4001c000 {
+                                compatible = "nxp,lpc3220-hsuart";
+                                reg = <0x4001c000 0x1000>;
+                                interrupts = <24 0>;
+                                status = "disabled";
                         };
 
                         rtc@40024000 {
@@ -235,21 +261,28 @@
                                 compatible = "nxp,lpc3220-adc";
                                 reg = <0x40048000 0x1000>;
                                 interrupts = <0x27 0>;
-                                status = "disable";
+                                status = "disabled";
                         };
 
                         tsc@40048000 {
                                 compatible = "nxp,lpc3220-tsc";
                                 reg = <0x40048000 0x1000>;
                                 interrupts = <0x27 0>;
-                                status = "disable";
+                                status = "disabled";
                         };
 
                         key@40050000 {
                                 compatible = "nxp,lpc3220-key";
                                 reg = <0x40050000 0x1000>;
+                                interrupts = <54 0>;
+                                status = "disabled";
                         };
 
+                        pwm: pwm@4005C000 {
+                                compatible = "nxp,lpc3220-pwm";
+                                reg = <0x4005C000 0x8>;
+                                status = "disabled";
+                        };
                 };
         };
 };
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
new file mode 100644
index 000000000000..25b50b759dec
--- /dev/null
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap2.dtsi"
+
+/ {
+        model = "TI OMAP2420 H4 board";
+        compatible = "ti,omap2420-h4", "ti,omap2420", "ti,omap2";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x84000000>; /* 64 MB */
+        };
+};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index 5b4506c0a8c4..cdcb98c7e075 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -61,9 +61,9 @@
 };
 
 &mmc2 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
diff --git a/arch/arm/boot/dts/omap3-evm.dts b/arch/arm/boot/dts/omap3-evm.dts
index 2eee16ec59b4..f349ee9182ce 100644
--- a/arch/arm/boot/dts/omap3-evm.dts
+++ b/arch/arm/boot/dts/omap3-evm.dts
@@ -18,3 +18,31 @@
                 reg = <0x80000000 0x10000000>; /* 256 MB */
         };
 };
+
+&i2c1 {
+        clock-frequency = <2600000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                interrupts = <7>; /* SYS_NIRQ cascaded to intc */
+                interrupt-parent = <&intc>;
+        };
+};
+
+/include/ "twl4030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+
+        /*
+         * TVP5146 Video decoder-in for analog input support.
+         */
+        tvp5146@5c {
+                compatible = "ti,tvp5146m2";
+                reg = <0x5c>;
+        };
+};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 99474fa5fac4..810947198208 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -215,5 +215,10 @@
                         compatible = "ti,omap3-hsmmc";
                         ti,hwmods = "mmc3";
                 };
+
+                wdt2: wdt@48314000 {
+                        compatible = "ti,omap3-wdt";
+                        ti,hwmods = "wd_timer2";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/omap4-panda.dts b/arch/arm/boot/dts/omap4-panda.dts
index 1efe0c587985..9880c12877b3 100644
--- a/arch/arm/boot/dts/omap4-panda.dts
+++ b/arch/arm/boot/dts/omap4-panda.dts
@@ -32,6 +32,30 @@
                         linux,default-trigger = "mmc0";
                 };
         };
+
+        sound: sound {
+                compatible = "ti,abe-twl6040";
+                ti,model = "PandaBoard";
+
+                ti,mclk-freq = <38400000>;
+
+                ti,mcpdm = <&mcpdm>;
+
+                ti,twl6040 = <&twl6040>;
+
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "Ext Spk", "HFL",
+                        "Ext Spk", "HFR",
+                        "Line Out", "AUXL",
+                        "Line Out", "AUXR",
+                        "HSMIC", "Headset Mic",
+                        "Headset Mic", "Headset Mic Bias",
+                        "AFML", "Line In",
+                        "AFMR", "Line In";
+        };
 };
 
 &i2c1 {
@@ -43,6 +67,19 @@
                 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
+
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+        };
 };
 
 /include/ "twl6030.dtsi"
@@ -74,15 +111,15 @@
 };
 
 &mmc2 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc4 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc5 {
diff --git a/arch/arm/boot/dts/omap4-pandaES.dts b/arch/arm/boot/dts/omap4-pandaES.dts
new file mode 100644
index 000000000000..d4ba43a48d9b
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-pandaES.dts
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/include/ "omap4-panda.dts"
+
+/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
+&sound {
+        ti,model = "PandaBoardES";
+
+        /* Audio routing */
+        ti,audio-routing =
+                "Headset Stereophone", "HSOL",
+                "Headset Stereophone", "HSOR",
+                "Ext Spk", "HFL",
+                "Ext Spk", "HFR",
+                "Line Out", "AUXL",
+                "Line Out", "AUXR",
+                "AFML", "Line In",
+                "AFMR", "Line In";
+};
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index d08c4d137280..72216e932fc0 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -28,6 +28,14 @@
                 regulator-boot-on;
         };
 
+        vbat: fixedregulator@2 {
+                compatible = "regulator-fixed";
+                regulator-name = "VBAT";
+                regulator-min-microvolt = <3750000>;
+                regulator-max-microvolt = <3750000>;
+                regulator-boot-on;
+        };
+
         leds {
                 compatible = "gpio-leds";
                 debug0 {
@@ -70,6 +78,41 @@
                         gpios = <&gpio5 11 0>; /* 139 */
                 };
         };
+
+        sound {
+                compatible = "ti,abe-twl6040";
+                ti,model = "SDP4430";
+
+                ti,jack-detection = <1>;
+                ti,mclk-freq = <38400000>;
+
+                ti,mcpdm = <&mcpdm>;
+                ti,dmic = <&dmic>;
+
+                ti,twl6040 = <&twl6040>;
+
+                /* Audio routing */
+                ti,audio-routing =
+                        "Headset Stereophone", "HSOL",
+                        "Headset Stereophone", "HSOR",
+                        "Earphone Spk", "EP",
+                        "Ext Spk", "HFL",
+                        "Ext Spk", "HFR",
+                        "Line Out", "AUXL",
+                        "Line Out", "AUXR",
+                        "Vibrator", "VIBRAL",
+                        "Vibrator", "VIBRAR",
+                        "HSMIC", "Headset Mic",
+                        "Headset Mic", "Headset Mic Bias",
+                        "MAINMIC", "Main Handset Mic",
+                        "Main Handset Mic", "Main Mic Bias",
+                        "SUBMIC", "Sub Handset Mic",
+                        "Sub Handset Mic", "Main Mic Bias",
+                        "AFML", "Line In",
+                        "AFMR", "Line In",
+                        "DMic", "Digital Mic",
+                        "Digital Mic", "Digital Mic1 Bias";
+        };
 };
 
 &i2c1 {
@@ -81,6 +124,31 @@
                 interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
                 interrupt-parent = <&gic>;
         };
+
+        twl6040: twl@4b {
+                compatible = "ti,twl6040";
+                reg = <0x4b>;
+                /* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
+                interrupts = <0 119 4>; /* IRQ_SYS_2N cascaded to gic */
+                interrupt-parent = <&gic>;
+                ti,audpwron-gpio = <&gpio4 31 0>;  /* gpio line 127 */
+
+                vio-supply = <&v1v8>;
+                v2v1-supply = <&v2v1>;
+                enable-active-high;
+
+                /* regulators for vibra motor */
+                vddvibl-supply = <&vbat>;
+                vddvibr-supply = <&vbat>;
+
+                vibra {
+                        /* Vibra driver, motor resistance parameters */
+                        ti,vibldrv-res = <8>;
+                        ti,vibrdrv-res = <3>;
+                        ti,viblmotor-res = <10>;
+                        ti,vibrmotor-res = <10>;
+                };
+        };
 };
 
 /include/ "twl6030.dtsi"
@@ -147,11 +215,11 @@
 };
 
 &mmc3 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc4 {
-        status = "disable";
+        status = "disabled";
 };
 
 &mmc5 {
diff --git a/arch/arm/boot/dts/omap4-var_som.dts b/arch/arm/boot/dts/omap4-var_som.dts
new file mode 100644
index 000000000000..6601e6af6092
--- /dev/null
+++ b/arch/arm/boot/dts/omap4-var_som.dts
@@ -0,0 +1,96 @@
+/*
+ * Copyright (C) 2012 Variscite Ltd. - http://www.variscite.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+/include/ "omap4.dtsi"
+
+/ {
+        model = "Variscite OMAP4 SOM";
+        compatible = "var,omap4-var_som", "ti,omap4430", "ti,omap4";
+
+        memory {
+                device_type = "memory";
+                reg = <0x80000000 0x40000000>; /* 1 GB */
+        };
+
+        vdd_eth: fixedregulator@0 {
+                compatible = "regulator-fixed";
+                regulator-name = "VDD_ETH";
+                regulator-min-microvolt = <3300000>;
+                regulator-max-microvolt = <3300000>;
+                enable-active-high;
+                regulator-boot-on;
+        };
+};
+
+&i2c1 {
+        clock-frequency = <400000>;
+
+        twl: twl@48 {
+                reg = <0x48>;
+                /* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
+                interrupts = <0 7 4>; /* IRQ_SYS_1N cascaded to gic */
+                interrupt-parent = <&gic>;
+        };
+};
+
+/include/ "twl6030.dtsi"
+
+&i2c2 {
+        clock-frequency = <400000>;
+};
+
+&i2c3 {
+        clock-frequency = <400000>;
+
+        /*
+         * Temperature Sensor
+         * http://www.ti.com/lit/ds/symlink/tmp105.pdf
+         */
+        tmp105@49 {
+                compatible = "ti,tmp105";
+                reg = <0x49>;
+        };
+};
+
+&i2c4 {
+        clock-frequency = <400000>;
+};
+
+&mcspi1 {
+        eth@0 {
+                compatible = "ks8851";
+                spi-max-frequency = <24000000>;
+                reg = <0>;
+                interrupt-parent = <&gpio6>;
+                interrupts = <11>; /* gpio line 171 */
+                vdd-supply = <&vdd_eth>;
+        };
+};
+
+&mmc1 {
+        vmmc-supply = <&vmmc>;
+        ti,bus-width = <8>;
+        ti,non-removable;
+};
+
+&mmc2 {
+        status = "disabled";
+};
+
+&mmc3 {
+        status = "disabled";
+};
+
+&mmc4 {
+        status = "disabled";
+};
+
+&mmc5 {
+        ti,bus-width = <4>;
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 359c4979c8aa..04cbbcb6ff91 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -272,5 +272,28 @@
                         ti,hwmods = "mmc5";
                         ti,needs-special-reset;
                 };
+
+                wdt2: wdt@4a314000 {
+                        compatible = "ti,omap4-wdt", "ti,omap3-wdt";
+                        ti,hwmods = "wd_timer2";
+                };
+
+                mcpdm: mcpdm@40132000 {
+                        compatible = "ti,omap4-mcpdm";
+                        reg = <0x40132000 0x7f>, /* MPU private access */
+                              <0x49032000 0x7f>; /* L3 Interconnect */
+                        interrupts = <0 112 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "mcpdm";
+                };
+
+                dmic: dmic@4012e000 {
+                        compatible = "ti,omap4-dmic";
+                        reg = <0x4012e000 0x7f>, /* MPU private access */
+                              <0x4902e000 0x7f>; /* L3 Interconnect */
+                        interrupts = <0 114 0x4>;
+                        interrupt-parent = <&gic>;
+                        ti,hwmods = "dmic";
+                };
         };
 };
diff --git a/arch/arm/boot/dts/phy3250.dts b/arch/arm/boot/dts/phy3250.dts
index c4ff6d1a018b..802ec5b2fd00 100644
--- a/arch/arm/boot/dts/phy3250.dts
+++ b/arch/arm/boot/dts/phy3250.dts
@@ -54,6 +54,17 @@
                         #address-cells = <1>;
                         #size-cells = <1>;
 
+                        nxp,wdr-clks = <14>;
+                        nxp,wwidth = <40000000>;
+                        nxp,whold = <100000000>;
+                        nxp,wsetup = <100000000>;
+                        nxp,rdr-clks = <14>;
+                        nxp,rwidth = <40000000>;
+                        nxp,rhold = <66666666>;
+                        nxp,rsetup = <100000000>;
+                        nand-on-flash-bbt;
+                        gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
+
                         mtd0@00000000 {
                                 label = "phy3250-boot";
                                 reg = <0x00000000 0x00064000>;
@@ -83,6 +94,14 @@
                 };
 
                 apb {
+                        uart5: serial@40090000 {
+                                status = "okay";
+                        };
+
+                        uart3: serial@40080000 {
+                                status = "okay";
+                        };
+
                         i2c1: i2c@400A0000 {
                                 clock-frequency = <100000>;
 
@@ -114,16 +133,58 @@
                         };
 
                         ssp0: ssp@20084000 {
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+                                pl022,num-chipselects = <1>;
+                                cs-gpios = <&gpio 3 5 0>;
+
                                 eeprom: at25@0 {
+                                        pl022,hierarchy = <0>;
+                                        pl022,interface = <0>;
+                                        pl022,slave-tx-disable = <0>;
+                                        pl022,com-mode = <0>;
+                                        pl022,rx-level-trig = <1>;
+                                        pl022,tx-level-trig = <1>;
+                                        pl022,ctrl-len = <11>;
+                                        pl022,wait-state = <0>;
+                                        pl022,duplex = <0>;
+
+                                        at25,byte-len = <0x8000>;
+                                        at25,addr-mode = <2>;
+                                        at25,page-size = <64>;
+
                                         compatible = "atmel,at25";
+                                        reg = <0>;
+                                        spi-max-frequency = <5000000>;
                                 };
                         };
+
+                        sd@20098000 {
+                                wp-gpios = <&gpio 3 0 0>;
+                                cd-gpios = <&gpio 3 1 0>;
+                                cd-inverted;
+                                bus-width = <4>;
+                                status = "okay";
+                        };
                 };
 
                 fab {
+                        uart2: serial@40018000 {
+                                status = "okay";
+                        };
+
                         tsc@40048000 {
                                 status = "okay";
                         };
+
+                        key@40050000 {
+                                status = "okay";
+                                keypad,num-rows = <1>;
+                                keypad,num-columns = <1>;
+                                nxp,debounce-delay-ms = <3>;
+                                nxp,scan-delay-ms = <34>;
+                                linux,keymap = <0x00000002>;
+                        };
                 };
         };
 
diff --git a/arch/arm/boot/dts/snowball.dts b/arch/arm/boot/dts/snowball.dts
index ec3c33975110..7e334d4cae21 100644
--- a/arch/arm/boot/dts/snowball.dts
+++ b/arch/arm/boot/dts/snowball.dts
@@ -77,6 +77,8 @@
                 used-led {
                         label = "user_led";
                         gpios = <&gpio4 14 0x4>;
+                        default-state = "on";
+                        linux,default-trigger = "heartbeat";
                 };
         };
 
@@ -101,15 +103,30 @@
                         };
                 };
 
+                // External Micro SD slot
                 sdi@80126000 {
-                        status = "enabled";
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux3_reg>;
+
+                        #gpio-cells = <1>;
                         cd-gpios  = <&gpio6 26 0x4>; // 218
+                        cd-inverted;
+
+                        status = "okay";
                 };
 
+                // On-board eMMC
                 sdi@80114000 {
-                        status = "enabled";
+                        arm,primecell-periphid = <0x10480180>;
+                        max-frequency = <50000000>;
+                        bus-width = <8>;
+                        mmc-cap-mmc-highspeed;
                         vmmc-supply = <&ab8500_ldo_aux2_reg>;
+
+                        status = "okay";
                 };
 
                 uart@80120000 {
diff --git a/arch/arm/boot/dts/spear13xx.dtsi b/arch/arm/boot/dts/spear13xx.dtsi
index 10dcec7e7321..f7b84aced654 100644
--- a/arch/arm/boot/dts/spear13xx.dtsi
+++ b/arch/arm/boot/dts/spear13xx.dtsi
@@ -43,8 +43,8 @@
 
         pmu {
                 compatible = "arm,cortex-a9-pmu";
-                interrupts = <0 8 0x04
-                              0 9 0x04>;
+                interrupts = <0 6 0x04
+                              0 7 0x04>;
         };
 
         L2: l2-cache {
@@ -119,8 +119,8 @@
                 gmac0: eth@e2000000 {
                         compatible = "st,spear600-gmac";
                         reg = <0xe2000000 0x8000>;
-                        interrupts = <0 23 0x4
-                                      0 24 0x4>;
+                        interrupts = <0 33 0x4
+                                      0 34 0x4>;
                         interrupt-names = "macirq", "eth_wake_irq";
                         status = "disabled";
                 };
@@ -202,6 +202,7 @@
                         kbd@e0300000 {
                                 compatible = "st,spear300-kbd";
                                 reg = <0xe0300000 0x1000>;
+                                interrupts = <0 52 0x4>;
                                 status = "disabled";
                         };
 
@@ -224,7 +225,7 @@
                         serial@e0000000 {
                                 compatible = "arm,pl011", "arm,primecell";
                                 reg = <0xe0000000 0x1000>;
-                                interrupts = <0 36 0x4>;
+                                interrupts = <0 35 0x4>;
                                 status = "disabled";
                         };
 
diff --git a/arch/arm/boot/dts/spear320-evb.dts b/arch/arm/boot/dts/spear320-evb.dts
index c13fd1f3b09f..e4e912f95024 100644
--- a/arch/arm/boot/dts/spear320-evb.dts
+++ b/arch/arm/boot/dts/spear320-evb.dts
@@ -15,8 +15,8 @@
 /include/ "spear320.dtsi"
 
 / {
-        model = "ST SPEAr300 Evaluation Board";
-        compatible = "st,spear300-evb", "st,spear300";
+        model = "ST SPEAr320 Evaluation Board";
+        compatible = "st,spear320-evb", "st,spear320";
         #address-cells = <1>;
         #size-cells = <1>;
 
@@ -26,7 +26,7 @@
 
         ahb {
                 pinmux@b3000000 {
-                        st,pinmux-mode = <3>;
+                        st,pinmux-mode = <4>;
                         pinctrl-names = "default";
                         pinctrl-0 = <&state_default>;
 
diff --git a/arch/arm/boot/dts/spear600.dtsi b/arch/arm/boot/dts/spear600.dtsi
index 089f0a42c50e..a3c36e47d7ef 100644
--- a/arch/arm/boot/dts/spear600.dtsi
+++ b/arch/arm/boot/dts/spear600.dtsi
@@ -181,6 +181,7 @@
                         timer@f0000000 {
                                 compatible = "st,spear-timer";
                                 reg = <0xf0000000 0x400>;
+                                interrupt-parent = <&vic0>;
                                 interrupts = <16>;
                         };
                 };
diff --git a/arch/arm/boot/dts/tegra-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index 7de701365fce..f146dbf6f7f8 100644
--- a/arch/arm/boot/dts/tegra-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -307,7 +307,6 @@
                 cd-gpios = <&gpio 58 0>; /* gpio PH2 */
                 wp-gpios = <&gpio 59 0>; /* gpio PH3 */
                 power-gpios = <&gpio 70 0>; /* gpio PI6 */
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index bfeb117d5aea..684a9e1ff7e9 100644
--- a/arch/arm/boot/dts/tegra-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -301,7 +301,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts
index 89cb7f2acd92..85e621ab2968 100644
--- a/arch/arm/boot/dts/tegra-seaboard.dts
+++ b/arch/arm/boot/dts/tegra20-seaboard.dts
@@ -64,11 +64,6 @@
                                 nvidia,pins = "dap4";
                                 nvidia,function = "dap4";
                         };
-                        ddc {
-                                nvidia,pins = "ddc", "owc", "spdi", "spdo",
-                                        "uac";
-                                nvidia,function = "rsvd2";
-                        };
                         dta {
                                 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
                                 nvidia,function = "vi";
@@ -129,14 +124,14 @@
                                         "lspi", "lvp1", "lvs";
                                 nvidia,function = "displaya";
                         };
+                        owc {
+                                nvidia,pins = "owc", "spdi", "spdo", "uac";
+                                nvidia,function = "rsvd2";
+                        };
                         pmc {
                                 nvidia,pins = "pmc";
                                 nvidia,function = "pwr_on";
                         };
-                        pta {
-                                nvidia,pins = "pta";
-                                nvidia,function = "i2c2";
-                        };
                         rm {
                                 nvidia,pins = "rm";
                                 nvidia,function = "i2c1";
@@ -176,7 +171,7 @@
                         conf_ata {
                                 nvidia,pins = "ata", "atb", "atc", "atd",
                                         "cdev1", "cdev2", "dap1", "dap2",
-                                        "dap4", "dtf", "gma", "gmc", "gmd",
+                                        "dap4", "ddc", "dtf", "gma", "gmc", "gmd",
                                         "gme", "gpu", "gpu7", "i2cp", "irrx",
                                         "irtx", "pta", "rm", "sdc", "sdd",
                                         "slxd", "slxk", "spdi", "spdo", "uac",
@@ -185,7 +180,7 @@
                                 nvidia,tristate = <0>;
                         };
                         conf_ate {
-                                nvidia,pins = "ate", "csus", "dap3", "ddc",
+                                nvidia,pins = "ate", "csus", "dap3",
                                         "gpv", "owc", "slxc", "spib", "spid",
                                         "spie";
                                 nvidia,pull = <0>;
@@ -255,6 +250,39 @@
                                 nvidia,slew-rate-falling = <3>;
                         };
                 };
+
+                state_i2cmux_ddc: pinmux_i2cmux_ddc {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
+
+                state_i2cmux_pta: pinmux_i2cmux_pta {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "i2c2";
+                        };
+                };
+
+                state_i2cmux_idle: pinmux_i2cmux_idle {
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "rsvd4";
+                        };
+                        pta {
+                                nvidia,pins = "pta";
+                                nvidia,function = "rsvd4";
+                        };
+                };
         };
 
         i2s@70002800 {
@@ -303,12 +331,37 @@
         i2c@7000c400 {
                 status = "okay";
                 clock-frequency = <100000>;
+        };
+
+        i2cmux {
+                compatible = "i2c-mux-pinctrl";
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                i2c-parent = <&{/i2c@7000c400}>;
 
-                smart-battery@b {
-                        compatible = "ti,bq20z75", "smart-battery-1.1";
-                        reg = <0xb>;
-                        ti,i2c-retry-count = <2>;
-                        ti,poll-retry-count = <10>;
+                pinctrl-names = "ddc", "pta", "idle";
+                pinctrl-0 = <&state_i2cmux_ddc>;
+                pinctrl-1 = <&state_i2cmux_pta>;
+                pinctrl-2 = <&state_i2cmux_idle>;
+
+                i2c@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                };
+
+                i2c@1 {
+                        reg = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        smart-battery@b {
+                                compatible = "ti,bq20z75", "smart-battery-1.1";
+                                reg = <0xb>;
+                                ti,i2c-retry-count = <2>;
+                                ti,poll-retry-count = <10>;
+                        };
                 };
         };
 
@@ -334,7 +387,7 @@
                 };
         };
 
-        emc {
+        memory-controller@0x7000f400 {
                 emc-table@190000 {
                         reg = <190000>;
                         compatible = "nvidia,tegra20-emc-table";
@@ -397,7 +450,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts
index 9de5636023f6..9de5636023f6 100644
--- a/arch/arm/boot/dts/tegra-trimslice.dts
+++ b/arch/arm/boot/dts/tegra20-trimslice.dts
diff --git a/arch/arm/boot/dts/tegra-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts
index 445343b0fbdd..be90544e6b59 100644
--- a/arch/arm/boot/dts/tegra-ventana.dts
+++ b/arch/arm/boot/dts/tegra20-ventana.dts
@@ -314,7 +314,6 @@
 
         sdhci@c8000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra20-whistler.dts b/arch/arm/boot/dts/tegra20-whistler.dts
new file mode 100644
index 000000000000..6916310bf58f
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-whistler.dts
@@ -0,0 +1,301 @@
+/dts-v1/;
+
+/include/ "tegra20.dtsi"
+
+/ {
+        model = "NVIDIA Tegra2 Whistler evaluation board";
+        compatible = "nvidia,whistler", "nvidia,tegra20";
+
+        memory {
+                reg = <0x00000000 0x20000000>;
+        };
+
+        pinmux {
+                pinctrl-names = "default";
+                pinctrl-0 = <&state_default>;
+
+                state_default: pinmux {
+                        ata {
+                                nvidia,pins = "ata", "atb", "ate", "gma", "gmb",
+                                        "gmc", "gmd", "gpu";
+                                nvidia,function = "gmi";
+                        };
+                        atc {
+                                nvidia,pins = "atc", "atd";
+                                nvidia,function = "sdio4";
+                        };
+                        cdev1 {
+                                nvidia,pins = "cdev1";
+                                nvidia,function = "plla_out";
+                        };
+                        cdev2 {
+                                nvidia,pins = "cdev2";
+                                nvidia,function = "osc";
+                        };
+                        crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,function = "crt";
+                        };
+                        csus {
+                                nvidia,pins = "csus";
+                                nvidia,function = "vi_sensor_clk";
+                        };
+                        dap1 {
+                                nvidia,pins = "dap1";
+                                nvidia,function = "dap1";
+                        };
+                        dap2 {
+                                nvidia,pins = "dap2";
+                                nvidia,function = "dap2";
+                        };
+                        dap3 {
+                                nvidia,pins = "dap3";
+                                nvidia,function = "dap3";
+                        };
+                        dap4 {
+                                nvidia,pins = "dap4";
+                                nvidia,function = "dap4";
+                        };
+                        ddc {
+                                nvidia,pins = "ddc";
+                                nvidia,function = "i2c2";
+                        };
+                        dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd";
+                                nvidia,function = "vi";
+                        };
+                        dte {
+                                nvidia,pins = "dte";
+                                nvidia,function = "rsvd1";
+                        };
+                        dtf {
+                                nvidia,pins = "dtf";
+                                nvidia,function = "i2c3";
+                        };
+                        gme {
+                                nvidia,pins = "gme";
+                                nvidia,function = "dap5";
+                        };
+                        gpu7 {
+                                nvidia,pins = "gpu7";
+                                nvidia,function = "rtck";
+                        };
+                        gpv {
+                                nvidia,pins = "gpv";
+                                nvidia,function = "pcie";
+                        };
+                        hdint {
+                                nvidia,pins = "hdint", "pta";
+                                nvidia,function = "hdmi";
+                        };
+                        i2cp {
+                                nvidia,pins = "i2cp";
+                                nvidia,function = "i2cp";
+                        };
+                        irrx {
+                                nvidia,pins = "irrx", "irtx";
+                                nvidia,function = "uartb";
+                        };
+                        kbca {
+                                nvidia,pins = "kbca", "kbcc", "kbce", "kbcf";
+                                nvidia,function = "kbc";
+                        };
+                        kbcb {
+                                nvidia,pins = "kbcb", "kbcd";
+                                nvidia,function = "sdio2";
+                        };
+                        lcsn {
+                                nvidia,pins = "lcsn", "lsck", "lsda", "lsdi",
+                                        "spia", "spib", "spic";
+                                nvidia,function = "spi3";
+                        };
+                        ld0 {
+                                nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
+                                        "ld5", "ld6", "ld7", "ld8", "ld9",
+                                        "ld10", "ld11", "ld12", "ld13", "ld14",
+                                        "ld15", "ld16", "ld17", "ldc", "ldi",
+                                        "lhp0", "lhp1", "lhp2", "lhs", "lm0",
+                                        "lm1", "lpp", "lpw0", "lpw1", "lpw2",
+                                        "lsc0", "lsc1", "lspi", "lvp0", "lvp1",
+                                        "lvs";
+                                nvidia,function = "displaya";
+                        };
+                        owc {
+                                nvidia,pins = "owc", "uac";
+                                nvidia,function = "owr";
+                        };
+                        pmc {
+                                nvidia,pins = "pmc";
+                                nvidia,function = "pwr_on";
+                        };
+                        rm {
+                                nvidia,pins = "rm";
+                                nvidia,function = "i2c1";
+                        };
+                        sdb {
+                                nvidia,pins = "sdb", "sdc", "sdd", "slxa",
+                                        "slxc", "slxd", "slxk";
+                                nvidia,function = "sdio3";
+                        };
+                        sdio1 {
+                                nvidia,pins = "sdio1";
+                                nvidia,function = "sdio1";
+                        };
+                        spdi {
+                                nvidia,pins = "spdi", "spdo";
+                                nvidia,function = "rsvd2";
+                        };
+                        spid {
+                                nvidia,pins = "spid", "spie", "spig", "spih";
+                                nvidia,function = "spi2_alt";
+                        };
+                        spif {
+                                nvidia,pins = "spif";
+                                nvidia,function = "spi2";
+                        };
+                        uaa {
+                                nvidia,pins = "uaa", "uab";
+                                nvidia,function = "uarta";
+                        };
+                        uad {
+                                nvidia,pins = "uad";
+                                nvidia,function = "irda";
+                        };
+                        uca {
+                                nvidia,pins = "uca", "ucb";
+                                nvidia,function = "uartc";
+                        };
+                        uda {
+                                nvidia,pins = "uda";
+                                nvidia,function = "spi1";
+                        };
+                        conf_ata {
+                                nvidia,pins = "ata", "atb", "atc", "ddc", "gma",
+                                        "gmb", "gmc", "gmd", "irrx", "irtx",
+                                        "kbca", "kbcb", "kbcc", "kbcd", "kbce",
+                                        "kbcf", "sdc", "sdd", "spie", "spig",
+                                        "spih", "uaa", "uab", "uad", "uca",
+                                        "ucb";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_atd {
+                                nvidia,pins = "atd", "ate", "cdev1", "csus",
+                                        "dap1", "dap2", "dap3", "dap4", "dte",
+                                        "dtf", "gpu", "gpu7", "gpv", "i2cp",
+                                        "rm", "sdio1", "slxa", "slxc", "slxd",
+                                        "slxk", "spdi", "spdo", "uac", "uda";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_cdev2 {
+                                nvidia,pins = "cdev2", "spia", "spib";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ck32 {
+                                nvidia,pins = "ck32", "ddrc", "lc", "pmca",
+                                        "pmcb", "pmcc", "pmcd", "xm2c",
+                                        "xm2d";
+                                nvidia,pull = <0>;
+                        };
+                        conf_crtp {
+                                nvidia,pins = "crtp";
+                                nvidia,pull = <0>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_dta {
+                                nvidia,pins = "dta", "dtb", "dtc", "dtd",
+                                        "spid", "spif";
+                                nvidia,pull = <1>;
+                                nvidia,tristate = <0>;
+                        };
+                        conf_gme {
+                                nvidia,pins = "gme", "owc", "pta", "spic";
+                                nvidia,pull = <2>;
+                                nvidia,tristate = <1>;
+                        };
+                        conf_ld17_0 {
+                                nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
+                                        "ld23_22";
+                                nvidia,pull = <1>;
+                        };
+                        conf_ls {
+                                nvidia,pins = "ls", "pmce";
+                                nvidia,pull = <2>;
+                        };
+                        drive_dap1 {
+                                nvidia,pins = "drive_dap1";
+                                nvidia,high-speed-mode = <0>;
+                                nvidia,schmitt = <1>;
+                                nvidia,low-power-mode = <0>;
+                                nvidia,pull-down-strength = <0>;
+                                nvidia,pull-up-strength = <0>;
+                                nvidia,slew-rate-rising = <0>;
+                                nvidia,slew-rate-falling = <0>;
+                        };
+                };
+        };
+
+        i2s@70002800 {
+                status = "okay";
+        };
+
+        serial@70006000 {
+                status = "okay";
+                clock-frequency = <216000000>;
+        };
+
+        i2c@7000d000 {
+                status = "okay";
+                clock-frequency = <100000>;
+
+                codec: codec@1a {
+                        compatible = "wlf,wm8753";
+                        reg = <0x1a>;
+                };
+
+                tca6416: gpio@20 {
+                        compatible = "ti,tca6416";
+                        reg = <0x20>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                };
+        };
+
+        usb@c5000000 {
+                status = "okay";
+                nvidia,vbus-gpio = <&tca6416 0 0>; /* GPIO_PMU0 */
+        };
+
+        usb@c5008000 {
+                status = "okay";
+                nvidia,vbus-gpio = <&tca6416 1 0>; /* GPIO_PMU1 */
+        };
+
+        sdhci@c8000400 {
+                status = "okay";
+                wp-gpios = <&gpio 173 0>; /* gpio PV5 */
+                bus-width = <8>;
+        };
+
+        sdhci@c8000600 {
+                status = "okay";
+                bus-width = <8>;
+        };
+
+        sound {
+                compatible = "nvidia,tegra-audio-wm8753-whistler",
+                             "nvidia,tegra-audio-wm8753";
+                nvidia,model = "NVIDIA Tegra Whistler";
+
+                nvidia,audio-routing =
+                        "Headphone Jack", "LOUT1",
+                        "Headphone Jack", "ROUT1",
+                        "MIC2", "Mic Jack",
+                        "MIC2N", "Mic Jack";
+
+                nvidia,i2s-controller = <&tegra_i2s1>;
+                nvidia,audio-codec = <&codec>;
+        };
+};
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index c417d67e9027..9f1921634eb7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -72,7 +72,7 @@
                 reg = <0x70002800 0x200>;
                 interrupts = <0 13 0x04>;
                 nvidia,dma-request-selector = <&apbdma 2>;
-                status = "disable";
+                status = "disabled";
         };
 
         tegra_i2s2: i2s@70002a00 {
@@ -80,7 +80,7 @@
                 reg = <0x70002a00 0x200>;
                 interrupts = <0 3 0x04>;
                 nvidia,dma-request-selector = <&apbdma 1>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006000 {
@@ -88,7 +88,7 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006040 {
@@ -96,7 +96,7 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006200 {
@@ -104,7 +104,7 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006300 {
@@ -112,7 +112,7 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006400 {
@@ -120,7 +120,7 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 91 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c000 {
@@ -129,7 +129,7 @@
                 interrupts = <0 38 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c400 {
@@ -138,7 +138,7 @@
                 interrupts = <0 84 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c500 {
@@ -147,7 +147,7 @@
                 interrupts = <0 92 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000d000 {
@@ -156,7 +156,7 @@
                 interrupts = <0 53 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmc {
@@ -164,7 +164,7 @@
                 reg = <0x7000e400 0x400>;
         };
 
-        mc {
+        memory-controller@0x7000f000 {
                 compatible = "nvidia,tegra20-mc";
                 reg = <0x7000f000 0x024
                        0x7000f03c 0x3c4>;
@@ -177,7 +177,7 @@
                        0x58000000 0x02000000>;  /* GART aperture */
         };
 
-        emc {
+        memory-controller@0x7000f400 {
                 compatible = "nvidia,tegra20-emc";
                 reg = <0x7000f400 0x200>;
                 #address-cells = <1>;
@@ -190,7 +190,7 @@
                 interrupts = <0 20 0x04>;
                 phy_type = "utmi";
                 nvidia,has-legacy-mode;
-                status = "disable";
+                status = "disabled";
         };
 
         usb@c5004000 {
@@ -198,7 +198,7 @@
                 reg = <0xc5004000 0x4000>;
                 interrupts = <0 21 0x04>;
                 phy_type = "ulpi";
-                status = "disable";
+                status = "disabled";
         };
 
         usb@c5008000 {
@@ -206,35 +206,35 @@
                 reg = <0xc5008000 0x4000>;
                 interrupts = <0 97 0x04>;
                 phy_type = "utmi";
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000000 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000000 0x200>;
                 interrupts = <0 14 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000200 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000200 0x200>;
                 interrupts = <0 15 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000400 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000400 0x200>;
                 interrupts = <0 19 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@c8000600 {
                 compatible = "nvidia,tegra20-sdhci";
                 reg = <0xc8000600 0x200>;
                 interrupts = <0 31 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmu {
diff --git a/arch/arm/boot/dts/tegra-cardhu.dts b/arch/arm/boot/dts/tegra30-cardhu.dts
index 36321bceec46..c169bced131e 100644
--- a/arch/arm/boot/dts/tegra-cardhu.dts
+++ b/arch/arm/boot/dts/tegra30-cardhu.dts
@@ -144,7 +144,6 @@
 
         sdhci@78000600 {
                 status = "okay";
-                support-8bit;
                 bus-width = <8>;
         };
 
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index 2dcc09e784b5..da740191771f 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -82,7 +82,7 @@
                 reg = <0x70006000 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 36 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006040 {
@@ -90,7 +90,7 @@
                 reg = <0x70006040 0x40>;
                 reg-shift = <2>;
                 interrupts = <0 37 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006200 {
@@ -98,7 +98,7 @@
                 reg = <0x70006200 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 46 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006300 {
@@ -106,7 +106,7 @@
                 reg = <0x70006300 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 90 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         serial@70006400 {
@@ -114,7 +114,7 @@
                 reg = <0x70006400 0x100>;
                 reg-shift = <2>;
                 interrupts = <0 91 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c000 {
@@ -123,7 +123,7 @@
                 interrupts = <0 38 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c400 {
@@ -132,7 +132,7 @@
                 interrupts = <0 84 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c500 {
@@ -141,7 +141,7 @@
                 interrupts = <0 92 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000c700 {
@@ -150,7 +150,7 @@
                 interrupts = <0 120 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         i2c@7000d000 {
@@ -159,7 +159,7 @@
                 interrupts = <0 53 0x04>;
                 #address-cells = <1>;
                 #size-cells = <0>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmc {
@@ -167,7 +167,7 @@
                 reg = <0x7000e400 0x400>;
         };
 
-        mc {
+        memory-controller {
                 compatible = "nvidia,tegra30-mc";
                 reg = <0x7000f000 0x010
                        0x7000f03c 0x1b4
@@ -201,35 +201,35 @@
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080300 0x100>;
                         nvidia,ahub-cif-ids = <4 4>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s1: i2s@70080400 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080400 0x100>;
                         nvidia,ahub-cif-ids = <5 5>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s2: i2s@70080500 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080500 0x100>;
                         nvidia,ahub-cif-ids = <6 6>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s3: i2s@70080600 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080600 0x100>;
                         nvidia,ahub-cif-ids = <7 7>;
-                        status = "disable";
+                        status = "disabled";
                 };
 
                 tegra_i2s4: i2s@70080700 {
                         compatible = "nvidia,tegra30-i2s";
                         reg = <0x70080700 0x100>;
                         nvidia,ahub-cif-ids = <8 8>;
-                        status = "disable";
+                        status = "disabled";
                 };
         };
 
@@ -237,28 +237,28 @@
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000000 0x200>;
                 interrupts = <0 14 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000200 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000200 0x200>;
                 interrupts = <0 15 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000400 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000400 0x200>;
                 interrupts = <0 19 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         sdhci@78000600 {
                 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
                 reg = <0x78000600 0x200>;
                 interrupts = <0 31 0x04>;
-                status = "disable";
+                status = "disabled";
         };
 
         pmu {
diff --git a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
index 16076e2d0934..d8a827bd2bf3 100644
--- a/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m-rs1.dtsi
@@ -55,6 +55,8 @@
                         reg-io-width = <4>;
                         smsc,irq-active-high;
                         smsc,irq-push-pull;
+                        vdd33a-supply = <&v2m_fixed_3v3>;
+                        vddvario-supply = <&v2m_fixed_3v3>;
                 };
 
                 usb@2,03000000 {
@@ -157,6 +159,7 @@
                         v2m_timer23: timer@120000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x120000 0x1000>;
+                                interrupts = <3>;
                         };
 
                         /* DVI I2C bus */
@@ -197,5 +200,13 @@
                                 interrupts = <14>;
                         };
                 };
+
+                v2m_fixed_3v3: fixedregulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi
index a6c9c7c82d53..dba53fd026bb 100644
--- a/arch/arm/boot/dts/vexpress-v2m.dtsi
+++ b/arch/arm/boot/dts/vexpress-v2m.dtsi
@@ -54,6 +54,8 @@
                         reg-io-width = <4>;
                         smsc,irq-active-high;
                         smsc,irq-push-pull;
+                        vdd33a-supply = <&v2m_fixed_3v3>;
+                        vddvario-supply = <&v2m_fixed_3v3>;
                 };
 
                 usb@3,03000000 {
@@ -156,6 +158,7 @@
                         v2m_timer23: timer@12000 {
                                 compatible = "arm,sp804", "arm,primecell";
                                 reg = <0x12000 0x1000>;
+                                interrupts = <3>;
                         };
 
                         /* DVI I2C bus */
@@ -196,5 +199,13 @@
                                 interrupts = <14>;
                         };
                 };
+
+                v2m_fixed_3v3: fixedregulator@0 {
+                        compatible = "regulator-fixed";
+                        regulator-name = "3V3";
+                        regulator-min-microvolt = <3300000>;
+                        regulator-max-microvolt = <3300000>;
+                        regulator-always-on;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
index 7e1091d91af8..d12b34ca0568 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
@@ -14,8 +14,8 @@
         arm,hbi = <0x237>;
         compatible = "arm,vexpress,v2p-ca15,tc1", "arm,vexpress,v2p-ca15", "arm,vexpress";
         interrupt-parent = <&gic>;
-        #address-cells = <1>;
-        #size-cells = <1>;
+        #address-cells = <2>;
+        #size-cells = <2>;
 
         chosen { };
 
@@ -47,23 +47,23 @@
 
         memory@80000000 {
                 device_type = "memory";
-                reg = <0x80000000 0x40000000>;
+                reg = <0 0x80000000 0 0x40000000>;
         };
 
         hdlcd@2b000000 {
                 compatible = "arm,hdlcd";
-                reg = <0x2b000000 0x1000>;
+                reg = <0 0x2b000000 0 0x1000>;
                 interrupts = <0 85 4>;
         };
 
         memory-controller@2b0a0000 {
                 compatible = "arm,pl341", "arm,primecell";
-                reg = <0x2b0a0000 0x1000>;
+                reg = <0 0x2b0a0000 0 0x1000>;
         };
 
         wdt@2b060000 {
                 compatible = "arm,sp805", "arm,primecell";
-                reg = <0x2b060000 0x1000>;
+                reg = <0 0x2b060000 0 0x1000>;
                 interrupts = <98>;
         };
 
@@ -72,23 +72,23 @@
                 #interrupt-cells = <3>;
                 #address-cells = <0>;
                 interrupt-controller;
-                reg = <0x2c001000 0x1000>,
-                      <0x2c002000 0x1000>,
-                      <0x2c004000 0x2000>,
-                      <0x2c006000 0x2000>;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x1000>,
+                      <0 0x2c004000 0 0x2000>,
+                      <0 0x2c006000 0 0x2000>;
                 interrupts = <1 9 0xf04>;
         };
 
         memory-controller@7ffd0000 {
                 compatible = "arm,pl354", "arm,primecell";
-                reg = <0x7ffd0000 0x1000>;
+                reg = <0 0x7ffd0000 0 0x1000>;
                 interrupts = <0 86 4>,
                              <0 87 4>;
         };
 
         dma@7ffb0000 {
                 compatible = "arm,pl330", "arm,primecell";
-                reg = <0x7ffb0000 0x1000>;
+                reg = <0 0x7ffb0000 0 0x1000>;
                 interrupts = <0 92 4>,
                              <0 88 4>,
                              <0 89 4>,
@@ -111,12 +111,12 @@
         };
 
         motherboard {
-                ranges = <0 0 0x08000000 0x04000000>,
-                         <1 0 0x14000000 0x04000000>,
-                         <2 0 0x18000000 0x04000000>,
-                         <3 0 0x1c000000 0x04000000>,
-                         <4 0 0x0c000000 0x04000000>,
-                         <5 0 0x10000000 0x04000000>;
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
 
                 interrupt-map-mask = <0 0 63>;
                 interrupt-map = <0 0  0 &gic 0  0 4>,
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
new file mode 100644
index 000000000000..4890a81c5467
--- /dev/null
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -0,0 +1,188 @@
+/*
+ * ARM Ltd. Versatile Express
+ *
+ * CoreTile Express A15x2 A7x3
+ * Cortex-A15_A7 MPCore (V2P-CA15_A7)
+ *
+ * HBI-0249A
+ */
+
+/dts-v1/;
+
+/ {
+        model = "V2P-CA15_CA7";
+        arm,hbi = <0x249>;
+        compatible = "arm,vexpress,v2p-ca15_a7", "arm,vexpress";
+        interrupt-parent = <&gic>;
+        #address-cells = <2>;
+        #size-cells = <2>;
+
+        chosen { };
+
+        aliases {
+                serial0 = &v2m_serial0;
+                serial1 = &v2m_serial1;
+                serial2 = &v2m_serial2;
+                serial3 = &v2m_serial3;
+                i2c0 = &v2m_i2c_dvi;
+                i2c1 = &v2m_i2c_pcie;
+        };
+
+        cpus {
+                #address-cells = <1>;
+                #size-cells = <0>;
+
+                cpu0: cpu@0 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <0>;
+                };
+
+                cpu1: cpu@1 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a15";
+                        reg = <1>;
+                };
+
+/* A7s disabled till big.LITTLE patches are available...
+                cpu2: cpu@2 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x100>;
+                };
+
+                cpu3: cpu@3 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x101>;
+                };
+
+                cpu4: cpu@4 {
+                        device_type = "cpu";
+                        compatible = "arm,cortex-a7";
+                        reg = <0x102>;
+                };
+*/
+        };
+
+        memory@80000000 {
+                device_type = "memory";
+                reg = <0 0x80000000 0 0x40000000>;
+        };
+
+        wdt@2a490000 {
+                compatible = "arm,sp805", "arm,primecell";
+                reg = <0 0x2a490000 0 0x1000>;
+                interrupts = <98>;
+        };
+
+        hdlcd@2b000000 {
+                compatible = "arm,hdlcd";
+                reg = <0 0x2b000000 0 0x1000>;
+                interrupts = <0 85 4>;
+        };
+
+        memory-controller@2b0a0000 {
+                compatible = "arm,pl341", "arm,primecell";
+                reg = <0 0x2b0a0000 0 0x1000>;
+        };
+
+        gic: interrupt-controller@2c001000 {
+                compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+                #interrupt-cells = <3>;
+                #address-cells = <0>;
+                interrupt-controller;
+                reg = <0 0x2c001000 0 0x1000>,
+                      <0 0x2c002000 0 0x1000>,
+                      <0 0x2c004000 0 0x2000>,
+                      <0 0x2c006000 0 0x2000>;
+                interrupts = <1 9 0xf04>;
+        };
+
+        memory-controller@7ffd0000 {
+                compatible = "arm,pl354", "arm,primecell";
+                reg = <0 0x7ffd0000 0 0x1000>;
+                interrupts = <0 86 4>,
+                             <0 87 4>;
+        };
+
+        dma@7ff00000 {
+                compatible = "arm,pl330", "arm,primecell";
+                reg = <0 0x7ff00000 0 0x1000>;
+                interrupts = <0 92 4>,
+                             <0 88 4>,
+                             <0 89 4>,
+                             <0 90 4>,
+                             <0 91 4>;
+        };
+
+        timer {
+                compatible = "arm,armv7-timer";
+                interrupts = <1 13 0xf08>,
+                             <1 14 0xf08>,
+                             <1 11 0xf08>,
+                             <1 10 0xf08>;
+        };
+
+        pmu {
+                compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
+                interrupts = <0 68 4>,
+                             <0 69 4>;
+        };
+
+        motherboard {
+                ranges = <0 0 0 0x08000000 0x04000000>,
+                         <1 0 0 0x14000000 0x04000000>,
+                         <2 0 0 0x18000000 0x04000000>,
+                         <3 0 0 0x1c000000 0x04000000>,
+                         <4 0 0 0x0c000000 0x04000000>,
+                         <5 0 0 0x10000000 0x04000000>;
+
+                interrupt-map-mask = <0 0 63>;
+                interrupt-map = <0 0  0 &gic 0  0 4>,
+                                <0 0  1 &gic 0  1 4>,
+                                <0 0  2 &gic 0  2 4>,
+                                <0 0  3 &gic 0  3 4>,
+                                <0 0  4 &gic 0  4 4>,
+                                <0 0  5 &gic 0  5 4>,
+                                <0 0  6 &gic 0  6 4>,
+                                <0 0  7 &gic 0  7 4>,
+                                <0 0  8 &gic 0  8 4>,
+                                <0 0  9 &gic 0  9 4>,
+                                <0 0 10 &gic 0 10 4>,
+                                <0 0 11 &gic 0 11 4>,
+                                <0 0 12 &gic 0 12 4>,
+                                <0 0 13 &gic 0 13 4>,
+                                <0 0 14 &gic 0 14 4>,
+                                <0 0 15 &gic 0 15 4>,
+                                <0 0 16 &gic 0 16 4>,
+                                <0 0 17 &gic 0 17 4>,
+                                <0 0 18 &gic 0 18 4>,
+                                <0 0 19 &gic 0 19 4>,
+                                <0 0 20 &gic 0 20 4>,
+                                <0 0 21 &gic 0 21 4>,
+                                <0 0 22 &gic 0 22 4>,
+                                <0 0 23 &gic 0 23 4>,
+                                <0 0 24 &gic 0 24 4>,
+                                <0 0 25 &gic 0 25 4>,
+                                <0 0 26 &gic 0 26 4>,
+                                <0 0 27 &gic 0 27 4>,
+                                <0 0 28 &gic 0 28 4>,
+                                <0 0 29 &gic 0 29 4>,
+                                <0 0 30 &gic 0 30 4>,
+                                <0 0 31 &gic 0 31 4>,
+                                <0 0 32 &gic 0 32 4>,
+                                <0 0 33 &gic 0 33 4>,
+                                <0 0 34 &gic 0 34 4>,
+                                <0 0 35 &gic 0 35 4>,
+                                <0 0 36 &gic 0 36 4>,
+                                <0 0 37 &gic 0 37 4>,
+                                <0 0 38 &gic 0 38 4>,
+                                <0 0 39 &gic 0 39 4>,
+                                <0 0 40 &gic 0 40 4>,
+                                <0 0 41 &gic 0 41 4>,
+                                <0 0 42 &gic 0 42 4>;
+        };
+};
+
+/include/ "vexpress-v2m-rs1.dtsi"
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
index 4fa60547494a..eceed186a3c1 100644
--- a/arch/arm/configs/lpc32xx_defconfig
+++ b/arch/arm/configs/lpc32xx_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_IKCONFIG=y
 CONFIG_IKCONFIG_PROC=y
 CONFIG_LOG_BUF_SHIFT=16
@@ -16,8 +18,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_ARCH_LPC32XX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 CONFIG_ZBOOT_ROM_TEXT=0x0
@@ -52,13 +52,17 @@ CONFIG_MTD=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_MUSEUM_IDS=y
+CONFIG_MTD_NAND_SLC_LPC32XX=y
+CONFIG_MTD_NAND_MLC_LPC32XX=y
 CONFIG_BLK_DEV_LOOP=y
 CONFIG_BLK_DEV_CRYPTOLOOP=y
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_COUNT=1
 CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_EEPROM_AT24=y
 CONFIG_EEPROM_AT25=y
 CONFIG_SCSI=y
 CONFIG_BLK_DEV_SD=y
@@ -79,16 +83,22 @@ CONFIG_LPC_ENET=y
 # CONFIG_NET_VENDOR_STMICRO is not set
 CONFIG_SMSC_PHY=y
 # CONFIG_WLAN is not set
+CONFIG_INPUT_MATRIXKMAP=y
 # CONFIG_INPUT_MOUSEDEV_PSAUX is not set
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=240
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=320
 CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_LPC32XX=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_TOUCHSCREEN_LPC32XX=y
+CONFIG_SERIO_LIBPS2=y
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_HS_LPC32XX=y
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
@@ -96,7 +106,8 @@ CONFIG_I2C_PNX=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_DS620=y
+CONFIG_SENSORS_MAX6639=y
 CONFIG_WATCHDOG=y
 CONFIG_PNX4008_WATCHDOG=y
 CONFIG_FB=y
@@ -133,6 +144,8 @@ CONFIG_MMC=y
 CONFIG_MMC_ARMMMCI=y
 CONFIG_NEW_LEDS=y
 CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_PCA9532=y
+CONFIG_LEDS_PCA9532_GPIO=y
 CONFIG_LEDS_GPIO=y
 CONFIG_LEDS_TRIGGERS=y
 CONFIG_LEDS_TRIGGER_TIMER=y
@@ -146,10 +159,10 @@ CONFIG_RTC_DRV_DS1374=y
 CONFIG_RTC_DRV_PCF8563=y
 CONFIG_RTC_DRV_LPC32XX=y
 CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
 CONFIG_STAGING=y
-CONFIG_IIO=y
 CONFIG_LPC32XX_ADC=y
+CONFIG_MAX517=y
+CONFIG_IIO=y
 CONFIG_EXT2_FS=y
 CONFIG_AUTOFS4_FS=y
 CONFIG_MSDOS_FS=y
@@ -159,7 +172,6 @@ CONFIG_JFFS2_FS=y
 CONFIG_JFFS2_FS_WBUF_VERIFY=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_ASCII=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 9854ff4279e0..d3c29b377af9 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -176,7 +176,6 @@ CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
 CONFIG_USB_DEVICEFS=y
 CONFIG_USB_SUSPEND=y
 CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_WDM=y
 CONFIG_USB_STORAGE=y
 CONFIG_USB_LIBUSUAL=y
@@ -197,6 +196,7 @@ CONFIG_RTC_DRV_TWL4030=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
+CONFIG_EXT4_FS=y
 CONFIG_QUOTA=y
 CONFIG_QFMT_V2=y
 CONFIG_MSDOS_FS=y
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 8349d4e97e2b..16cedb42c0c3 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -40,13 +40,6 @@
 #include <asm/mach/irq.h>
 #include <asm/mach/time.h>
 
-/*
- * No architecture-specific irq_finish function defined in arm/arch/irqs.h.
- */
-#ifndef irq_finish
-#define irq_finish(irq) do { } while (0)
-#endif
-
 unsigned long irq_err_count;
 
 int arch_show_interrupts(struct seq_file *p, int prec)
@@ -85,9 +78,6 @@ void handle_IRQ(unsigned int irq, struct pt_regs *regs)
                 generic_handle_irq(irq);
         }
 
-        /* AT91 specific workaround */
-        irq_finish(irq);
-
         irq_exit();
         set_irq_regs(old_regs);
 }
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 19505c0a3f01..c8050b14e615 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -29,12 +29,16 @@ comment "Atmel AT91 Processor"
 config SOC_AT91SAM9
         bool
         select CPU_ARM926T
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select AT91_SAM9_TIME
         select AT91_SAM9_SMC
 
 config SOC_AT91RM9200
         bool "AT91RM9200"
         select CPU_ARM920T
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select GENERIC_CLOCKEVENTS
         select HAVE_AT91_DBGU0
 
@@ -140,6 +144,8 @@ config ARCH_AT91SAM9G45
 config ARCH_AT91X40
         bool "AT91x40"
         depends on !MMU
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
         select ARCH_USES_GETTIMEOFFSET
 
 endchoice
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 9e84fe4f2aaa..30bb7332e30b 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -15,7 +15,9 @@ endif
 
 # Keep dtb files sorted alphabetically for each SoC
 # sam9260
+dtb-$(CONFIG_MACH_AT91SAM_DT) += aks-cdu.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += ethernut5.dtb
+dtb-$(CONFIG_MACH_AT91SAM_DT) += evk-pro3.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += tny_a9260.dtb
 dtb-$(CONFIG_MACH_AT91SAM_DT) += usb_a9260.dtb
 # sam9263
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 26917687fc30..6f50c6722276 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -17,6 +17,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91rm9200.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_st.h>
 #include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index e6b7d0533dd7..01fb7325fecc 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -41,8 +41,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_UHP,
-                .end    = AT91RM9200_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -94,8 +94,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_UDP,
-                .end    = AT91RM9200_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -145,8 +145,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_EMAC,
-                .end    = AT91RM9200_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_MCI,
-                .end    = AT91RM9200_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -488,8 +488,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TWI,
-                .end    = AT91RM9200_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -532,8 +532,8 @@ static struct resource spi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SPI,
-                .end    = AT91RM9200_ID_SPI,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SPI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -598,18 +598,18 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TC0,
-                .end    = AT91RM9200_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91RM9200_ID_TC1,
-                .end    = AT91RM9200_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91RM9200_ID_TC2,
-                .end    = AT91RM9200_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -628,18 +628,18 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_TC3,
-                .end    = AT91RM9200_ID_TC3,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC3,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91RM9200_ID_TC4,
-                .end    = AT91RM9200_ID_TC4,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC4,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91RM9200_ID_TC5,
-                .end    = AT91RM9200_ID_TC5,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_TC5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -673,8 +673,8 @@ static struct resource rtc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -729,8 +729,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC0,
-                .end    = AT91RM9200_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -771,8 +771,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC1,
-                .end    = AT91RM9200_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -813,8 +813,8 @@ static struct resource ssc2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_SSC2,
-                .end    = AT91RM9200_ID_SSC2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_SSC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -897,8 +897,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -935,8 +935,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US0,
-                .end    = AT91RM9200_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -984,8 +984,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US1,
-                .end    = AT91RM9200_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1035,8 +1035,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US2,
-                .end    = AT91RM9200_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1078,8 +1078,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91RM9200_ID_US3,
-                .end    = AT91RM9200_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91RM9200_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 2b1e438ed878..30c7f26a4668 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -20,6 +20,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9260.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 0ded951f785a..7b9c2ba396ed 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_UHP,
-                .end    = AT91SAM9260_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_UDP,
-                .end    = AT91SAM9260_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -149,8 +149,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_EMAC,
-                .end    = AT91SAM9260_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -223,8 +223,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_MCI,
-                .end    = AT91SAM9260_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -305,8 +305,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_MCI,
-                .end    = AT91SAM9260_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -496,8 +496,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TWI,
-                .end    = AT91SAM9260_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -540,8 +540,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SPI0,
-                .end    = AT91SAM9260_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -566,8 +566,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SPI1,
-                .end    = AT91SAM9260_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -652,18 +652,18 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TC0,
-                .end    = AT91SAM9260_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9260_ID_TC1,
-                .end    = AT91SAM9260_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9260_ID_TC2,
-                .end    = AT91SAM9260_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -682,18 +682,18 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_TC3,
-                .end    = AT91SAM9260_ID_TC3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC3,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9260_ID_TC4,
-                .end    = AT91SAM9260_ID_TC4,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC4,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9260_ID_TC5,
-                .end    = AT91SAM9260_ID_TC5,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_TC5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -807,8 +807,8 @@ static struct resource ssc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_SSC,
-                .end    = AT91SAM9260_ID_SSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_SSC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -882,8 +882,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -920,8 +920,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US0,
-                .end    = AT91SAM9260_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -971,8 +971,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US1,
-                .end    = AT91SAM9260_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1014,8 +1014,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US2,
-                .end    = AT91SAM9260_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1057,8 +1057,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US3,
-                .end    = AT91SAM9260_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1100,8 +1100,8 @@ static struct resource uart4_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US4,
-                .end    = AT91SAM9260_ID_US4,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US4,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1138,8 +1138,8 @@ static struct resource uart5_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_US5,
-                .end    = AT91SAM9260_ID_US5,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_US5,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1357,8 +1357,8 @@ static struct resource adc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9260_ID_ADC,
-                .end    = AT91SAM9260_ID_ADC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9260_ID_ADC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index c77d503d09d1..f40762c5fede 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -19,6 +19,7 @@
 #include <asm/system_misc.h>
 #include <mach/cpu.h>
 #include <mach/at91sam9261.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 9295e90b08ff..8df5c1bdff92 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -45,8 +45,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_UHP,
-                .end    = AT91SAM9261_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -98,8 +98,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_UDP,
-                .end    = AT91SAM9261_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -148,8 +148,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_MCI,
-                .end    = AT91SAM9261_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -310,8 +310,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_TWI,
-                .end    = AT91SAM9261_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -354,8 +354,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SPI0,
-                .end    = AT91SAM9261_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -380,8 +380,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SPI1,
-                .end    = AT91SAM9261_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -468,8 +468,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_LCDC,
-                .end    = AT91SAM9261_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 #if defined(CONFIG_FB_INTSRAM)
@@ -566,18 +566,18 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_TC0,
-                .end    = AT91SAM9261_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9261_ID_TC1,
-                .end    = AT91SAM9261_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9261_ID_TC2,
-                .end    = AT91SAM9261_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -689,8 +689,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC0,
-                .end    = AT91SAM9261_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -731,8 +731,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC1,
-                .end    = AT91SAM9261_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -773,8 +773,8 @@ static struct resource ssc2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_SSC2,
-                .end    = AT91SAM9261_ID_SSC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_SSC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -857,8 +857,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -895,8 +895,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US0,
-                .end    = AT91SAM9261_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -938,8 +938,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US1,
-                .end    = AT91SAM9261_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -981,8 +981,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9261_ID_US2,
-                .end    = AT91SAM9261_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9261_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ed91c7e9f7c2..84b38105231e 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -18,6 +18,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9263.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 175e0009eaa9..eb6bbf86fb9f 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -44,8 +44,8 @@ static struct resource usbh_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_UHP,
-                .end    = AT91SAM9263_ID_UHP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UHP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -104,8 +104,8 @@ static struct resource udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_UDP,
-                .end    = AT91SAM9263_ID_UDP,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_UDP,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -155,8 +155,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_EMAC,
-                .end    = AT91SAM9263_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -229,8 +229,8 @@ static struct resource mmc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_MCI0,
-                .end    = AT91SAM9263_ID_MCI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -254,8 +254,8 @@ static struct resource mmc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_MCI1,
-                .end    = AT91SAM9263_ID_MCI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_MCI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -567,8 +567,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_TWI,
-                .end    = AT91SAM9263_ID_TWI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TWI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -611,8 +611,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SPI0,
-                .end    = AT91SAM9263_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -637,8 +637,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SPI1,
-                .end    = AT91SAM9263_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_AC97C,
-                .end    = AT91SAM9263_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -776,8 +776,8 @@ static struct resource can_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_CAN,
-                .end    = AT91SAM9263_ID_CAN,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_CAN,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -816,8 +816,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_LCDC,
-                .end    = AT91SAM9263_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -883,8 +883,8 @@ struct resource isi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_ISI,
-                .end    = AT91SAM9263_ID_ISI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_ISI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -940,8 +940,8 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_TCB,
-                .end    = AT91SAM9263_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1108,8 +1108,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_PWMC,
-                .end    = AT91SAM9263_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1161,8 +1161,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SSC0,
-                .end    = AT91SAM9263_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1203,8 +1203,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_SSC1,
-                .end    = AT91SAM9263_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1284,8 +1284,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1322,8 +1322,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US0,
-                .end    = AT91SAM9263_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1365,8 +1365,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US1,
-                .end    = AT91SAM9263_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1408,8 +1408,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9263_ID_US2,
-                .end    = AT91SAM9263_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9263_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam926x_time.c b/arch/arm/mach-at91/at91sam926x_time.c
index a94758b42737..ffc0957d7623 100644
--- a/arch/arm/mach-at91/at91sam926x_time.c
+++ b/arch/arm/mach-at91/at91sam926x_time.c
@@ -137,7 +137,7 @@ static struct irqaction at91sam926x_pit_irq = {
         .name           = "at91_tick",
         .flags          = IRQF_SHARED | IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
         .handler        = at91sam926x_pit_interrupt,
-        .irq            = AT91_ID_SYS,
+        .irq            = NR_IRQS_LEGACY + AT91_ID_SYS,
 };
 
 static void at91sam926x_pit_reset(void)
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 4792682d52b9..977127368a7d 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -18,6 +18,7 @@
 #include <asm/mach/map.h>
 #include <asm/system_misc.h>
 #include <mach/at91sam9g45.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 933fc9afe7d0..40fb79df2de0 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -53,8 +53,8 @@ static struct resource hdmac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_DMA,
-                .end    = AT91SAM9G45_ID_DMA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_DMA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -94,8 +94,8 @@ static struct resource usbh_ohci_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_UHPHS,
-                .end    = AT91SAM9G45_ID_UHPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -156,8 +156,8 @@ static struct resource usbh_ehci_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_UHPHS,
-                .end    = AT91SAM9G45_ID_UHPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UHPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -213,8 +213,8 @@ static struct resource usba_udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9G45_ID_UDPHS,
-                .end    = AT91SAM9G45_ID_UDPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_UDPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -296,8 +296,8 @@ static struct resource eth_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_EMAC,
-                .end    = AT91SAM9G45_ID_EMAC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_EMAC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -370,8 +370,8 @@ static struct resource mmc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_MCI0,
-                .end    = AT91SAM9G45_ID_MCI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -395,8 +395,8 @@ static struct resource mmc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_MCI1,
-                .end    = AT91SAM9G45_ID_MCI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_MCI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -645,8 +645,8 @@ static struct resource twi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TWI0,
-                .end    = AT91SAM9G45_ID_TWI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -665,8 +665,8 @@ static struct resource twi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TWI1,
-                .end    = AT91SAM9G45_ID_TWI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TWI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -720,8 +720,8 @@ static struct resource spi0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SPI0,
-                .end    = AT91SAM9G45_ID_SPI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -746,8 +746,8 @@ static struct resource spi1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SPI1,
-                .end    = AT91SAM9G45_ID_SPI1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SPI1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -834,8 +834,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_AC97C,
-                .end    = AT91SAM9G45_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -887,8 +887,8 @@ struct resource isi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_ISI,
-                .end    = AT91SAM9G45_ID_ISI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_ISI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -979,8 +979,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_LCDC,
-                .end    = AT91SAM9G45_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1054,8 +1054,8 @@ static struct resource tcb0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TCB,
-                .end    = AT91SAM9G45_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1075,8 +1075,8 @@ static struct resource tcb1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TCB,
-                .end    = AT91SAM9G45_ID_TCB,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TCB,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1110,8 +1110,8 @@ static struct resource rtc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1147,8 +1147,8 @@ static struct resource tsadcc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TSC,
-                .end    = AT91SAM9G45_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -1197,8 +1197,8 @@ static struct resource adc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_TSC,
-                .end    = AT91SAM9G45_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -1400,8 +1400,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_PWMC,
-                .end    = AT91SAM9G45_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1453,8 +1453,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SSC0,
-                .end    = AT91SAM9G45_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1495,8 +1495,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_SSC1,
-                .end    = AT91SAM9G45_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1575,8 +1575,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1613,8 +1613,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US0,
-                .end    = AT91SAM9G45_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1656,8 +1656,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US1,
-                .end    = AT91SAM9G45_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1699,8 +1699,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US2,
-                .end    = AT91SAM9G45_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1742,8 +1742,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9G45_ID_US3,
-                .end    = AT91SAM9G45_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9G45_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9rl.c b/arch/arm/mach-at91/at91sam9rl.c
index e420085a57ef..72ce50a50de5 100644
--- a/arch/arm/mach-at91/at91sam9rl.c
+++ b/arch/arm/mach-at91/at91sam9rl.c
@@ -19,6 +19,7 @@
 #include <mach/cpu.h>
 #include <mach/at91_dbgu.h>
 #include <mach/at91sam9rl.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
 
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 9c0b1481a9a7..f09fff932172 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -41,8 +41,8 @@ static struct resource hdmac_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_DMA,
-                .end    = AT91SAM9RL_ID_DMA,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_DMA,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -84,8 +84,8 @@ static struct resource usba_udc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_UDPHS,
-                .end    = AT91SAM9RL_ID_UDPHS,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_UDPHS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -172,8 +172,8 @@ static struct resource mmc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_MCI,
-                .end    = AT91SAM9RL_ID_MCI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_MCI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -339,8 +339,8 @@ static struct resource twi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TWI0,
-                .end    = AT91SAM9RL_ID_TWI0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TWI0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -383,8 +383,8 @@ static struct resource spi_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SPI,
-                .end    = AT91SAM9RL_ID_SPI,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SPI,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -452,8 +452,8 @@ static struct resource ac97_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_AC97C,
-                .end    = AT91SAM9RL_ID_AC97C,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_AC97C,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -507,8 +507,8 @@ static struct resource lcdc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_LCDC,
-                .end    = AT91SAM9RL_ID_LCDC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_LCDC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -574,18 +574,18 @@ static struct resource tcb_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TC0,
-                .end    = AT91SAM9RL_ID_TC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC0,
                 .flags  = IORESOURCE_IRQ,
         },
         [2] = {
-                .start  = AT91SAM9RL_ID_TC1,
-                .end    = AT91SAM9RL_ID_TC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC1,
                 .flags  = IORESOURCE_IRQ,
         },
         [3] = {
-                .start  = AT91SAM9RL_ID_TC2,
-                .end    = AT91SAM9RL_ID_TC2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TC2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -621,8 +621,8 @@ static struct resource tsadcc_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_TSC,
-                .end    = AT91SAM9RL_ID_TSC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_TSC,
                 .flags  = IORESOURCE_IRQ,
         }
 };
@@ -768,8 +768,8 @@ static struct resource pwm_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_PWMC,
-                .end    = AT91SAM9RL_ID_PWMC,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_PWMC,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -821,8 +821,8 @@ static struct resource ssc0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SSC0,
-                .end    = AT91SAM9RL_ID_SSC0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -863,8 +863,8 @@ static struct resource ssc1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_SSC1,
-                .end    = AT91SAM9RL_ID_SSC1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_SSC1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -943,8 +943,8 @@ static struct resource dbgu_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91_ID_SYS,
-                .end    = AT91_ID_SYS,
+                .start  = NR_IRQS_LEGACY + AT91_ID_SYS,
+                .end    = NR_IRQS_LEGACY + AT91_ID_SYS,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -981,8 +981,8 @@ static struct resource uart0_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US0,
-                .end    = AT91SAM9RL_ID_US0,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US0,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1032,8 +1032,8 @@ static struct resource uart1_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US1,
-                .end    = AT91SAM9RL_ID_US1,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US1,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1075,8 +1075,8 @@ static struct resource uart2_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US2,
-                .end    = AT91SAM9RL_ID_US2,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US2,
                 .flags  = IORESOURCE_IRQ,
         },
 };
@@ -1118,8 +1118,8 @@ static struct resource uart3_resources[] = {
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
-                .start  = AT91SAM9RL_ID_US3,
-                .end    = AT91SAM9RL_ID_US3,
+                .start  = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
+                .end    = NR_IRQS_LEGACY + AT91SAM9RL_ID_US3,
                 .flags  = IORESOURCE_IRQ,
         },
 };
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 1b144b4d3ce1..477cf9d06672 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -312,8 +312,6 @@ static void __init at91sam9x5_map_io(void)
 
 void __init at91sam9x5_initialize(void)
 {
-        at91_extern_irq = (1 << AT91SAM9X5_ID_IRQ0);
-
         /* Register GPIO subsystem (using DT) */
         at91_gpio_init(NULL, 0);
 }
@@ -321,47 +319,9 @@ void __init at91sam9x5_initialize(void)
 /* --------------------------------------------------------------------
  *  Interrupt initialization
  * -------------------------------------------------------------------- */
-/*
- * The default interrupt priority levels (0 = lowest, 7 = highest).
- */
-static unsigned int at91sam9x5_default_irq_priority[NR_AIC_IRQS] __initdata = {
-        7,      /* Advanced Interrupt Controller (FIQ) */
-        7,      /* System Peripherals */
-        1,      /* Parallel IO Controller A and B */
-        1,      /* Parallel IO Controller C and D */
-        4,      /* Soft Modem */
-        5,      /* USART 0 */
-        5,      /* USART 1 */
-        5,      /* USART 2 */
-        5,      /* USART 3 */
-        6,      /* Two-Wire Interface 0 */
-        6,      /* Two-Wire Interface 1 */
-        6,      /* Two-Wire Interface 2 */
-        0,      /* Multimedia Card Interface 0 */
-        5,      /* Serial Peripheral Interface 0 */
-        5,      /* Serial Peripheral Interface 1 */
-        5,      /* UART 0 */
-        5,      /* UART 1 */
-        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
-        0,      /* Pulse Width Modulation Controller */
-        0,      /* ADC Controller */
-        0,      /* DMA Controller 0 */
-        0,      /* DMA Controller 1 */
-        2,      /* USB Host High Speed port */
-        2,      /* USB Device High speed port */
-        3,      /* Ethernet MAC 0 */
-        3,      /* LDC Controller or Image Sensor Interface */
-        0,      /* Multimedia Card Interface 1 */
-        3,      /* Ethernet MAC 1 */
-        4,      /* Synchronous Serial Interface */
-        4,      /* CAN Controller 0 */
-        4,      /* CAN Controller 1 */
-        0,      /* Advanced Interrupt Controller (IRQ0) */
-};
 
 struct at91_init_soc __initdata at91sam9x5_soc = {
         .map_io = at91sam9x5_map_io,
-        .default_irq_priority = at91sam9x5_default_irq_priority,
         .register_clocks = at91sam9x5_register_clocks,
         .init = at91sam9x5_initialize,
 };
diff --git a/arch/arm/mach-at91/at91x40.c b/arch/arm/mach-at91/at91x40.c
index d62fe090d814..46090e642d8e 100644
--- a/arch/arm/mach-at91/at91x40.c
+++ b/arch/arm/mach-at91/at91x40.c
@@ -13,10 +13,12 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <asm/proc-fns.h>
 #include <asm/system_misc.h>
 #include <asm/mach/arch.h>
 #include <mach/at91x40.h>
+#include <mach/at91_aic.h>
 #include <mach/at91_st.h>
 #include <mach/timex.h>
 #include "generic.h"
diff --git a/arch/arm/mach-at91/board-1arm.c b/arch/arm/mach-at91/board-1arm.c
index 271f994314a4..22d8856094f1 100644
--- a/arch/arm/mach-at91/board-1arm.c
+++ b/arch/arm/mach-at91/board-1arm.c
@@ -36,6 +36,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -91,6 +92,7 @@ MACHINE_START(ONEARM, "Ajeco 1ARM single board computer")
         /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = onearm_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = onearm_board_init,
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index b7d8aa7b81e6..de7be1931817 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -44,6 +44,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -212,6 +213,7 @@ MACHINE_START(AFEB9260, "Custom afeb9260 board")
         /* Maintainer: Sergey Lapin <slapin@ossfans.org> */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = afeb9260_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = afeb9260_board_init,
diff --git a/arch/arm/mach-at91/board-cam60.c b/arch/arm/mach-at91/board-cam60.c
index 29d3ef0a50fb..477e708497bc 100644
--- a/arch/arm/mach-at91/board-cam60.c
+++ b/arch/arm/mach-at91/board-cam60.c
@@ -39,6 +39,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -188,6 +189,7 @@ MACHINE_START(CAM60, "KwikByte CAM60")
         /* Maintainer: KwikByte */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cam60_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cam60_board_init,
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 44328a6d4609..a5b002f32a61 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -36,6 +36,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -158,6 +159,7 @@ MACHINE_START(CARMEVA, "Carmeva")
         /* Maintainer: Conitec Datasystems */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = carmeva_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = carmeva_board_init,
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
index 69951ec7dbf3..ecbc13b594de 100644
--- a/arch/arm/mach-at91/board-cpu9krea.c
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -41,6 +41,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91sam9260_matrix.h>
 #include <mach/at91_matrix.h>
@@ -376,6 +377,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cpu9krea_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cpu9krea_board_init,
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
index 895cf2dba612..2e6d043c82f2 100644
--- a/arch/arm/mach-at91/board-cpuat91.c
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -37,6 +37,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -178,6 +179,7 @@ MACHINE_START(CPUAT91, "Eukrea")
         /* Maintainer: Eric Benard - EUKREA Electromatique */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = cpuat91_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = cpuat91_board_init,
diff --git a/arch/arm/mach-at91/board-csb337.c b/arch/arm/mach-at91/board-csb337.c
index cd813361cd26..462bc319cbc5 100644
--- a/arch/arm/mach-at91/board-csb337.c
+++ b/arch/arm/mach-at91/board-csb337.c
@@ -39,6 +39,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -252,6 +253,7 @@ MACHINE_START(CSB337, "Cogent CSB337")
         /* Maintainer: Bill Gatliff */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = csb337_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = csb337_board_init,
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 7c8b05a57d7f..872871ab1160 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -36,6 +36,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -133,6 +134,7 @@ MACHINE_START(CSB637, "Cogent CSB637")
         /* Maintainer: Bill Gatliff */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = csb637_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = csb637_board_init,
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
index a1fce05aa7a5..e8f45c4e0ea8 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt.c
@@ -16,6 +16,7 @@
 #include <linux/of_platform.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include <asm/setup.h>
 #include <asm/irq.h>
@@ -53,6 +54,7 @@ DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91_dt_initialize,
         .init_irq       = at91_dt_init_irq,
         .init_machine   = at91_dt_device_init,
diff --git a/arch/arm/mach-at91/board-eb01.c b/arch/arm/mach-at91/board-eb01.c
index d2023f27c652..01f66e99ece7 100644
--- a/arch/arm/mach-at91/board-eb01.c
+++ b/arch/arm/mach-at91/board-eb01.c
@@ -28,6 +28,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include "generic.h"
 
 static void __init at91eb01_init_irq(void)
@@ -43,6 +44,7 @@ static void __init at91eb01_init_early(void)
 MACHINE_START(AT91EB01, "Atmel AT91 EB01")
         /* Maintainer: Greg Ungerer <gerg@snapgear.com> */
         .timer          = &at91x40_timer,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = at91eb01_init_early,
         .init_irq       = at91eb01_init_irq,
 MACHINE_END
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index bd1017297989..d1e1f3fc0a47 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -36,6 +36,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -118,6 +119,7 @@ static void __init eb9200_board_init(void)
 MACHINE_START(ATEB9200, "Embest ATEB9200")
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = eb9200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = eb9200_board_init,
diff --git a/arch/arm/mach-at91/board-ecbat91.c b/arch/arm/mach-at91/board-ecbat91.c
index 89cc3726a9ce..9c24cb25707c 100644
--- a/arch/arm/mach-at91/board-ecbat91.c
+++ b/arch/arm/mach-at91/board-ecbat91.c
@@ -39,6 +39,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -170,6 +171,7 @@ MACHINE_START(ECBAT91, "emQbit's ECB_AT91")
         /* Maintainer: emQbit.com */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ecb_at91init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ecb_at91board_init,
diff --git a/arch/arm/mach-at91/board-eco920.c b/arch/arm/mach-at91/board-eco920.c
index 558546cf63f4..82bdfde3405f 100644
--- a/arch/arm/mach-at91/board-eco920.c
+++ b/arch/arm/mach-at91/board-eco920.c
@@ -25,6 +25,7 @@
 #include <asm/mach/map.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -132,6 +133,7 @@ MACHINE_START(ECO920, "eco920")
         /* Maintainer: Sascha Hauer */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = eco920_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = eco920_board_init,
diff --git a/arch/arm/mach-at91/board-flexibity.c b/arch/arm/mach-at91/board-flexibity.c
index 47658f78105d..6cc83a87d77c 100644
--- a/arch/arm/mach-at91/board-flexibity.c
+++ b/arch/arm/mach-at91/board-flexibity.c
@@ -34,6 +34,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include "generic.h"
 
@@ -160,6 +161,7 @@ MACHINE_START(FLEXIBITY, "Flexibity Connect")
         /* Maintainer: Maxim Osipov */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = flexibity_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = flexibity_board_init,
diff --git a/arch/arm/mach-at91/board-foxg20.c b/arch/arm/mach-at91/board-foxg20.c
index 33411e6ecb1f..69ab1247ef81 100644
--- a/arch/arm/mach-at91/board-foxg20.c
+++ b/arch/arm/mach-at91/board-foxg20.c
@@ -42,6 +42,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -262,6 +263,7 @@ MACHINE_START(ACMENETUSFOXG20, "Acme Systems srl FOX Board G20")
         /* Maintainer: Sergio Tanzilli */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = foxg20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = foxg20_board_init,
diff --git a/arch/arm/mach-at91/board-gsia18s.c b/arch/arm/mach-at91/board-gsia18s.c
index 3e0dfa643a86..a9d5e78118c5 100644
--- a/arch/arm/mach-at91/board-gsia18s.c
+++ b/arch/arm/mach-at91/board-gsia18s.c
@@ -31,6 +31,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/gsia18s.h>
 #include <mach/stamp9g20.h>
@@ -575,6 +576,7 @@ static void __init gsia18s_board_init(void)
 MACHINE_START(GSIA18S, "GS_IA18_S")
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = gsia18s_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = gsia18s_board_init,
diff --git a/arch/arm/mach-at91/board-kafa.c b/arch/arm/mach-at91/board-kafa.c
index f260657f32bc..64c1dbf88a07 100644
--- a/arch/arm/mach-at91/board-kafa.c
+++ b/arch/arm/mach-at91/board-kafa.c
@@ -35,6 +35,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/cpu.h>
 
 #include "generic.h"
@@ -93,6 +94,7 @@ MACHINE_START(KAFA, "Sperry-Sun KAFA")
         /* Maintainer: Sergei Sharonov */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = kafa_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = kafa_board_init,
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index ba39db5482b9..5d96cb85175f 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -37,6 +37,7 @@
 
 #include <mach/board.h>
 #include <mach/cpu.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -133,6 +134,7 @@ MACHINE_START(KB9200, "KB920x")
         /* Maintainer: KwikByte, Inc. */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = kb9202_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = kb9202_board_init,
diff --git a/arch/arm/mach-at91/board-neocore926.c b/arch/arm/mach-at91/board-neocore926.c
index d2f4cc161766..18103c5d993c 100644
--- a/arch/arm/mach-at91/board-neocore926.c
+++ b/arch/arm/mach-at91/board-neocore926.c
@@ -45,6 +45,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -378,6 +379,7 @@ MACHINE_START(NEOCORE926, "ADENEO NEOCORE 926")
         /* Maintainer: ADENEO */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = neocore926_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = neocore926_board_init,
diff --git a/arch/arm/mach-at91/board-pcontrol-g20.c b/arch/arm/mach-at91/board-pcontrol-g20.c
index 7fe638342421..9ca3e32c54cb 100644
--- a/arch/arm/mach-at91/board-pcontrol-g20.c
+++ b/arch/arm/mach-at91/board-pcontrol-g20.c
@@ -30,6 +30,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/stamp9g20.h>
 
@@ -218,6 +219,7 @@ MACHINE_START(PCONTROL_G20, "PControl G20")
         /* Maintainer: pgsellmann@portner-elektronik.at */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = pcontrol_g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = pcontrol_g20_board_init,
diff --git a/arch/arm/mach-at91/board-picotux200.c b/arch/arm/mach-at91/board-picotux200.c
index b45c0a5d5ca7..127065504508 100644
--- a/arch/arm/mach-at91/board-picotux200.c
+++ b/arch/arm/mach-at91/board-picotux200.c
@@ -38,6 +38,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -120,6 +121,7 @@ MACHINE_START(PICOTUX2XX, "picotux 200")
         /* Maintainer: Kleinhenz Elektronik GmbH */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = picotux200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = picotux200_board_init,
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
index 0c61bf0d272c..bf351e285422 100644
--- a/arch/arm/mach-at91/board-qil-a9260.c
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -41,6 +41,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -258,6 +259,7 @@ MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200dk.c b/arch/arm/mach-at91/board-rm9200dk.c
index afd7a4713766..cc2bf9796073 100644
--- a/arch/arm/mach-at91/board-rm9200dk.c
+++ b/arch/arm/mach-at91/board-rm9200dk.c
@@ -40,6 +40,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -223,6 +224,7 @@ MACHINE_START(AT91RM9200DK, "Atmel AT91RM9200-DK")
         /* Maintainer: SAN People/Atmel */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = dk_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = dk_board_init,
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 2b15b8adec4c..62e19e64c9d3 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -40,6 +40,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 
@@ -190,6 +191,7 @@ MACHINE_START(AT91RM9200EK, "Atmel AT91RM9200-EK")
         /* Maintainer: SAN People/Atmel */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-rsi-ews.c b/arch/arm/mach-at91/board-rsi-ews.c
index 24ab9be7510f..c3b43aefdb75 100644
--- a/arch/arm/mach-at91/board-rsi-ews.c
+++ b/arch/arm/mach-at91/board-rsi-ews.c
@@ -26,6 +26,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 
 #include <linux/gpio.h>
 
@@ -225,6 +226,7 @@ MACHINE_START(RSI_EWS, "RSI EWS")
         /* Maintainer: Josef Holzmayr <holzmayr@rsi-elektrotechnik.de> */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = rsi_ews_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = rsi_ews_board_init,
diff --git a/arch/arm/mach-at91/board-sam9-l9260.c b/arch/arm/mach-at91/board-sam9-l9260.c
index cdd21f2595d2..7bf6da70d7d5 100644
--- a/arch/arm/mach-at91/board-sam9-l9260.c
+++ b/arch/arm/mach-at91/board-sam9-l9260.c
@@ -38,6 +38,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -202,6 +203,7 @@ MACHINE_START(SAM9_L9260, "Olimex SAM9-L9260")
         /* Maintainer: Olimex */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9260ek.c b/arch/arm/mach-at91/board-sam9260ek.c
index 7b3c3913551a..889c1bf71eb5 100644
--- a/arch/arm/mach-at91/board-sam9260ek.c
+++ b/arch/arm/mach-at91/board-sam9260ek.c
@@ -42,6 +42,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -344,6 +345,7 @@ MACHINE_START(AT91SAM9260EK, "Atmel AT91SAM9260-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index 2736453821b0..2269be5fa384 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -46,6 +46,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -615,6 +616,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 983cb98d2465..82adf581afc2 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -45,6 +45,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -443,6 +444,7 @@ MACHINE_START(AT91SAM9263EK, "Atmel AT91SAM9263-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index 6860d3451100..4ea4ee00364b 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -44,6 +44,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/system_rev.h>
 
@@ -413,6 +414,7 @@ MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -422,6 +424,7 @@ MACHINE_START(AT91SAM9G20EK_2MMC, "Atmel AT91SAM9G20-EK 2 MMC Slot Mod")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
index 63163dc7df46..3d48ec154685 100644
--- a/arch/arm/mach-at91/board-sam9m10g45ek.c
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -43,6 +43,7 @@
 #include <asm/mach/irq.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 #include <mach/system_rev.h>
@@ -503,6 +504,7 @@ MACHINE_START(AT91SAM9M10G45EK, "Atmel AT91SAM9M10G45-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index be3239f13daa..e7dc3ead7045 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -31,6 +31,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -319,6 +320,7 @@ MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
         /* Maintainer: Atmel */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 9d446f1bb45f..a4e031a039fd 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -33,6 +33,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -178,6 +179,7 @@ static void __init snapper9260_board_init(void)
 MACHINE_START(SNAPPER_9260, "Bluewater Systems Snapper 9260/9G20 module")
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = snapper9260_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = snapper9260_board_init,
diff --git a/arch/arm/mach-at91/board-stamp9g20.c b/arch/arm/mach-at91/board-stamp9g20.c
index ee86f9d7ee72..29eae1626bf7 100644
--- a/arch/arm/mach-at91/board-stamp9g20.c
+++ b/arch/arm/mach-at91/board-stamp9g20.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 
 #include "sam9_smc.h"
@@ -287,6 +288,7 @@ MACHINE_START(PORTUXG20, "taskit PortuxG20")
         /* Maintainer: taskit GmbH */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = portuxg20_board_init,
@@ -296,6 +298,7 @@ MACHINE_START(STAMP9G20, "taskit Stamp9G20")
         /* Maintainer: taskit GmbH */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = stamp9g20_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = stamp9g20evb_board_init,
diff --git a/arch/arm/mach-at91/board-usb-a926x.c b/arch/arm/mach-at91/board-usb-a926x.c
index 95393fcaf199..c1476b9fe7b9 100644
--- a/arch/arm/mach-at91/board-usb-a926x.c
+++ b/arch/arm/mach-at91/board-usb-a926x.c
@@ -42,6 +42,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91sam9_smc.h>
 #include <mach/at91_shdwc.h>
 
@@ -358,6 +359,7 @@ MACHINE_START(USB_A9263, "CALAO USB_A9263")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -367,6 +369,7 @@ MACHINE_START(USB_A9260, "CALAO USB_A9260")
         /* Maintainer: calao-systems */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
@@ -376,6 +379,7 @@ MACHINE_START(USB_A9G20, "CALAO USB_A92G0")
         /* Maintainer: Jean-Christophe PLAGNIOL-VILLARD */
         .timer          = &at91sam926x_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = ek_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = ek_board_init,
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index d56665ea4b55..516d340549d8 100644
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -44,6 +44,7 @@
 
 #include <mach/hardware.h>
 #include <mach/board.h>
+#include <mach/at91_aic.h>
 #include <mach/at91rm9200_mc.h>
 #include <mach/at91_ramc.h>
 #include <mach/cpu.h>
@@ -590,6 +591,7 @@ MACHINE_START(YL9200, "uCdragon YL-9200")
         /* Maintainer: S.Birtles */
         .timer          = &at91rm9200_timer,
         .map_io         = at91_map_io,
+        .handle_irq     = at91_aic_handle_irq,
         .init_early     = yl9200_init_early,
         .init_irq       = at91_init_irq_default,
         .init_machine   = yl9200_board_init,
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index 0a60bf837037..f49650677653 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -29,6 +29,8 @@ extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
 extern int  __init at91_aic_of_init(struct device_node *node,
                                     struct device_node *parent);
+extern int  __init at91_aic5_of_init(struct device_node *node,
+                                    struct device_node *parent);
 
 
  /* Timer */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index 325837a264c9..be42cf0e74bd 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -26,6 +26,8 @@
 #include <linux/of_irq.h>
 #include <linux/of_gpio.h>
 
+#include <asm/mach/irq.h>
+
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
@@ -585,15 +587,14 @@ static struct irq_chip gpio_irqchip = {
 
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         struct irq_data *idata = irq_desc_get_irq_data(desc);
-        struct irq_chip *chip = irq_data_get_irq_chip(idata);
         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
         void __iomem    *pio = at91_gpio->regbase;
         unsigned long   isr;
         int             n;
 
-        /* temporarily mask (level sensitive) parent IRQ */
-        chip->irq_ack(idata);
+        chained_irq_enter(chip, desc);
         for (;;) {
                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
                  * When there none are pending, we're finished unless we need
@@ -614,7 +615,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
                 }
         }
-        chip->irq_unmask(idata);
+        chained_irq_exit(chip, desc);
         /* now it may re-trigger */
 }
 
diff --git a/arch/arm/mach-at91/include/mach/at91_aic.h b/arch/arm/mach-at91/include/mach/at91_aic.h
index 3045781c473f..eaea66197fa1 100644
--- a/arch/arm/mach-at91/include/mach/at91_aic.h
+++ b/arch/arm/mach-at91/include/mach/at91_aic.h
@@ -23,12 +23,23 @@ extern void __iomem *at91_aic_base;
         __raw_readl(at91_aic_base + field)
 
 #define at91_aic_write(field, value) \
-        __raw_writel(value, at91_aic_base + field);
+        __raw_writel(value, at91_aic_base + field)
 #else
 .extern at91_aic_base
 #endif
 
+/* Number of irq lines managed by AIC */
+#define NR_AIC_IRQS     32
+#define NR_AIC5_IRQS    128
+
+#define AT91_AIC5_SSR           0x0                     /* Source Select Register [AIC5] */
+#define         AT91_AIC5_INTSEL_MSK    (0x7f << 0)             /* Interrupt Line Selection Mask */
+
+#define AT91_AIC_IRQ_MIN_PRIORITY       0
+#define AT91_AIC_IRQ_MAX_PRIORITY       7
+
 #define AT91_AIC_SMR(n)         ((n) * 4)               /* Source Mode Registers 0-31 */
+#define AT91_AIC5_SMR           0x4                     /* Source Mode Register [AIC5] */
 #define         AT91_AIC_PRIOR          (7 << 0)                /* Priority Level */
 #define         AT91_AIC_SRCTYPE        (3 << 5)                /* Interrupt Source Type */
 #define                 AT91_AIC_SRCTYPE_LOW            (0 << 5)
@@ -37,29 +48,52 @@ extern void __iomem *at91_aic_base;
 #define                 AT91_AIC_SRCTYPE_RISING         (3 << 5)
 
 #define AT91_AIC_SVR(n)         (0x80 + ((n) * 4))      /* Source Vector Registers 0-31 */
+#define AT91_AIC5_SVR           0x8                     /* Source Vector Register [AIC5] */
 #define AT91_AIC_IVR            0x100                   /* Interrupt Vector Register */
+#define AT91_AIC5_IVR           0x10                    /* Interrupt Vector Register [AIC5] */
 #define AT91_AIC_FVR            0x104                   /* Fast Interrupt Vector Register */
+#define AT91_AIC5_FVR           0x14                    /* Fast Interrupt Vector Register [AIC5] */
 #define AT91_AIC_ISR            0x108                   /* Interrupt Status Register */
+#define AT91_AIC5_ISR           0x18                    /* Interrupt Status Register [AIC5] */
 #define         AT91_AIC_IRQID          (0x1f << 0)             /* Current Interrupt Identifier */
 
 #define AT91_AIC_IPR            0x10c                   /* Interrupt Pending Register */
+#define AT91_AIC5_IPR0          0x20                    /* Interrupt Pending Register 0 [AIC5] */
+#define AT91_AIC5_IPR1          0x24                    /* Interrupt Pending Register 1 [AIC5] */
+#define AT91_AIC5_IPR2          0x28                    /* Interrupt Pending Register 2 [AIC5] */
+#define AT91_AIC5_IPR3          0x2c                    /* Interrupt Pending Register 3 [AIC5] */
 #define AT91_AIC_IMR            0x110                   /* Interrupt Mask Register */
+#define AT91_AIC5_IMR           0x30                    /* Interrupt Mask Register [AIC5] */
 #define AT91_AIC_CISR           0x114                   /* Core Interrupt Status Register */
+#define AT91_AIC5_CISR          0x34                    /* Core Interrupt Status Register [AIC5] */
 #define         AT91_AIC_NFIQ           (1 << 0)                /* nFIQ Status */
 #define         AT91_AIC_NIRQ           (1 << 1)                /* nIRQ Status */
 
 #define AT91_AIC_IECR           0x120                   /* Interrupt Enable Command Register */
+#define AT91_AIC5_IECR          0x40                    /* Interrupt Enable Command Register [AIC5] */
 #define AT91_AIC_IDCR           0x124                   /* Interrupt Disable Command Register */
+#define AT91_AIC5_IDCR          0x44                    /* Interrupt Disable Command Register [AIC5] */
 #define AT91_AIC_ICCR           0x128                   /* Interrupt Clear Command Register */
+#define AT91_AIC5_ICCR          0x48                    /* Interrupt Clear Command Register [AIC5] */
 #define AT91_AIC_ISCR           0x12c                   /* Interrupt Set Command Register */
+#define AT91_AIC5_ISCR          0x4c                    /* Interrupt Set Command Register [AIC5] */
 #define AT91_AIC_EOICR          0x130                   /* End of Interrupt Command Register */
+#define AT91_AIC5_EOICR         0x38                    /* End of Interrupt Command Register [AIC5] */
 #define AT91_AIC_SPU            0x134                   /* Spurious Interrupt Vector Register */
+#define AT91_AIC5_SPU           0x3c                    /* Spurious Interrupt Vector Register [AIC5] */
 #define AT91_AIC_DCR            0x138                   /* Debug Control Register */
+#define AT91_AIC5_DCR           0x6c                    /* Debug Control Register [AIC5] */
 #define         AT91_AIC_DCR_PROT       (1 << 0)                /* Protection Mode */
 #define         AT91_AIC_DCR_GMSK       (1 << 1)                /* General Mask */
 
 #define AT91_AIC_FFER           0x140                   /* Fast Forcing Enable Register [SAM9 only] */
+#define AT91_AIC5_FFER          0x50                    /* Fast Forcing Enable Register [AIC5] */
 #define AT91_AIC_FFDR           0x144                   /* Fast Forcing Disable Register [SAM9 only] */
+#define AT91_AIC5_FFDR          0x54                    /* Fast Forcing Disable Register [AIC5] */
 #define AT91_AIC_FFSR           0x148                   /* Fast Forcing Status Register [SAM9 only] */
+#define AT91_AIC5_FFSR          0x58                    /* Fast Forcing Status Register [AIC5] */
+
+void at91_aic_handle_irq(struct pt_regs *regs);
+void at91_aic5_handle_irq(struct pt_regs *regs);
 
 #endif
diff --git a/arch/arm/mach-at91/include/mach/at91_spi.h b/arch/arm/mach-at91/include/mach/at91_spi.h
deleted file mode 100644
index 2f6ba0c5636e..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_spi.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_spi.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * Serial Peripheral Interface (SPI) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SPI_H
-#define AT91_SPI_H
-
-#define AT91_SPI_CR                     0x00            /* Control Register */
-#define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
-#define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
-#define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
-#define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_MR                     0x04            /* Mode Register */
-#define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
-#define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
-#define                 AT91_SPI_PS_FIXED       (0 << 1)
-#define                 AT91_SPI_PS_VARIABLE    (1 << 1)
-#define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
-#define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
-#define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
-#define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
-#define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
-#define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
-
-#define AT91_SPI_RDR            0x08                    /* Receive Data Register */
-#define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-
-#define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
-#define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
-#define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
-#define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
-
-#define AT91_SPI_SR             0x10                    /* Status Register */
-#define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
-#define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
-#define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
-#define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
-#define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
-#define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
-#define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
-#define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
-#define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
-#define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
-#define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
-
-#define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
-#define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
-#define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
-
-#define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
-#define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
-#define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
-#define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
-#define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
-#define                 AT91_SPI_BITS_8         (0 << 4)
-#define                 AT91_SPI_BITS_9         (1 << 4)
-#define                 AT91_SPI_BITS_10        (2 << 4)
-#define                 AT91_SPI_BITS_11        (3 << 4)
-#define                 AT91_SPI_BITS_12        (4 << 4)
-#define                 AT91_SPI_BITS_13        (5 << 4)
-#define                 AT91_SPI_BITS_14        (6 << 4)
-#define                 AT91_SPI_BITS_15        (7 << 4)
-#define                 AT91_SPI_BITS_16        (8 << 4)
-#define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
-#define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
-#define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_ssc.h b/arch/arm/mach-at91/include/mach/at91_ssc.h
deleted file mode 100644
index a81114c11c74..000000000000
--- a/arch/arm/mach-at91/include/mach/at91_ssc.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_ssc.h
- *
- * Copyright (C) SAN People
- *
- * Serial Synchronous Controller (SSC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_SSC_H
-#define AT91_SSC_H
-
-#define AT91_SSC_CR             0x00    /* Control Register */
-#define         AT91_SSC_RXEN           (1 <<  0)       /* Receive Enable */
-#define         AT91_SSC_RXDIS          (1 <<  1)       /* Receive Disable */
-#define         AT91_SSC_TXEN           (1 <<  8)       /* Transmit Enable */
-#define         AT91_SSC_TXDIS          (1 <<  9)       /* Transmit Disable */
-#define         AT91_SSC_SWRST          (1 << 15)       /* Software Reset */
-
-#define AT91_SSC_CMR            0x04    /* Clock Mode Register */
-#define         AT91_SSC_CMR_DIV        (0xfff << 0)    /* Clock Divider */
-
-#define AT91_SSC_RCMR           0x10    /* Receive Clock Mode Register */
-#define         AT91_SSC_CKS            (3    <<  0)    /* Clock Selection */
-#define                 AT91_SSC_CKS_DIV                (0 << 0)
-#define                 AT91_SSC_CKS_CLOCK              (1 << 0)
-#define                 AT91_SSC_CKS_PIN                (2 << 0)
-#define         AT91_SSC_CKO            (7    <<  2)    /* Clock Output Mode Selection */
-#define                 AT91_SSC_CKO_NONE               (0 << 2)
-#define                 AT91_SSC_CKO_CONTINUOUS         (1 << 2)
-#define         AT91_SSC_CKI            (1    <<  5)    /* Clock Inversion */
-#define                 AT91_SSC_CKI_FALLING            (0 << 5)
-#define                 AT91_SSC_CK_RISING              (1 << 5)
-#define         AT91_SSC_CKG            (1    <<  6)    /* Receive Clock Gating Selection [AT91SAM9261 only] */
-#define                 AT91_SSC_CKG_NONE               (0 << 6)
-#define                 AT91_SSC_CKG_RFLOW              (1 << 6)
-#define                 AT91_SSC_CKG_RFHIGH             (2 << 6)
-#define         AT91_SSC_START          (0xf  <<  8)    /* Start Selection */
-#define                 AT91_SSC_START_CONTINUOUS       (0 << 8)
-#define                 AT91_SSC_START_TX_RX            (1 << 8)
-#define                 AT91_SSC_START_LOW_RF           (2 << 8)
-#define                 AT91_SSC_START_HIGH_RF          (3 << 8)
-#define                 AT91_SSC_START_FALLING_RF       (4 << 8)
-#define                 AT91_SSC_START_RISING_RF        (5 << 8)
-#define                 AT91_SSC_START_LEVEL_RF         (6 << 8)
-#define                 AT91_SSC_START_EDGE_RF          (7 << 8)
-#define         AT91_SSC_STOP           (1    << 12)    /* Receive Stop Selection [AT91SAM9261 only] */
-#define         AT91_SSC_STTDLY         (0xff << 16)    /* Start Delay */
-#define         AT91_SSC_PERIOD         (0xff << 24)    /* Period Divider Selection */
-
-#define AT91_SSC_RFMR           0x14    /* Receive Frame Mode Register */
-#define         AT91_SSC_DATALEN        (0x1f <<  0)    /* Data Length */
-#define         AT91_SSC_LOOP           (1    <<  5)    /* Loop Mode */
-#define         AT91_SSC_MSBF           (1    <<  7)    /* Most Significant Bit First */
-#define         AT91_SSC_DATNB          (0xf  <<  8)    /* Data Number per Frame */
-#define         AT91_SSC_FSLEN          (0xf  << 16)    /* Frame Sync Length */
-#define         AT91_SSC_FSOS           (7    << 20)    /* Frame Sync Output Selection */
-#define                 AT91_SSC_FSOS_NONE              (0 << 20)
-#define                 AT91_SSC_FSOS_NEGATIVE          (1 << 20)
-#define                 AT91_SSC_FSOS_POSITIVE          (2 << 20)
-#define                 AT91_SSC_FSOS_LOW               (3 << 20)
-#define                 AT91_SSC_FSOS_HIGH              (4 << 20)
-#define                 AT91_SSC_FSOS_TOGGLE            (5 << 20)
-#define         AT91_SSC_FSEDGE         (1    << 24)    /* Frame Sync Edge Detection */
-#define                 AT91_SSC_FSEDGE_POSITIVE        (0 << 24)
-#define                 AT91_SSC_FSEDGE_NEGATIVE        (1 << 24)
-
-#define AT91_SSC_TCMR           0x18    /* Transmit Clock Mode Register */
-#define AT91_SSC_TFMR           0x1c    /* Transmit Fram Mode Register */
-#define         AT91_SSC_DATDEF         (1 <<  5)       /* Data Default Value */
-#define         AT91_SSC_FSDEN          (1 << 23)       /* Frame Sync Data Enable */
-
-#define AT91_SSC_RHR            0x20    /* Receive Holding Register */
-#define AT91_SSC_THR            0x24    /* Transmit Holding Register */
-#define AT91_SSC_RSHR           0x30    /* Receive Sync Holding Register */
-#define AT91_SSC_TSHR           0x34    /* Transmit Sync Holding Register */
-
-#define AT91_SSC_RC0R           0x38    /* Receive Compare 0 Register [AT91SAM9261 only] */
-#define AT91_SSC_RC1R           0x3c    /* Receive Compare 1 Register [AT91SAM9261 only] */
-
-#define AT91_SSC_SR             0x40    /* Status Register */
-#define         AT91_SSC_TXRDY          (1 <<  0)       /* Transmit Ready */
-#define         AT91_SSC_TXEMPTY        (1 <<  1)       /* Transmit Empty */
-#define         AT91_SSC_ENDTX          (1 <<  2)       /* End of Transmission */
-#define         AT91_SSC_TXBUFE         (1 <<  3)       /* Transmit Buffer Empty */
-#define         AT91_SSC_RXRDY          (1 <<  4)       /* Receive Ready */
-#define         AT91_SSC_OVRUN          (1 <<  5)       /* Receive Overrun */
-#define         AT91_SSC_ENDRX          (1 <<  6)       /* End of Reception */
-#define         AT91_SSC_RXBUFF         (1 <<  7)       /* Receive Buffer Full */
-#define         AT91_SSC_CP0            (1 <<  8)       /* Compare 0 [AT91SAM9261 only] */
-#define         AT91_SSC_CP1            (1 <<  9)       /* Compare 1 [AT91SAM9261 only] */
-#define         AT91_SSC_TXSYN          (1 << 10)       /* Transmit Sync */
-#define         AT91_SSC_RXSYN          (1 << 11)       /* Receive Sync */
-#define         AT91_SSC_TXENA          (1 << 16)       /* Transmit Enable */
-#define         AT91_SSC_RXENA          (1 << 17)       /* Receive Enable */
-
-#define AT91_SSC_IER            0x44    /* Interrupt Enable Register */
-#define AT91_SSC_IDR            0x48    /* Interrupt Disable Register */
-#define AT91_SSC_IMR            0x4c    /* Interrupt Mask Register */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/entry-macro.S b/arch/arm/mach-at91/include/mach/entry-macro.S
deleted file mode 100644
index 903bf205a333..000000000000
--- a/arch/arm/mach-at91/include/mach/entry-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/entry-macro.S
- *
- *  Copyright (C) 2003-2005 SAN People
- *
- * Low-level IRQ helper macros for AT91RM9200 platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/hardware.h>
-#include <mach/at91_aic.h>
-
-        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =at91_aic_base           @ base virtual address of AIC peripheral
-        ldr     \base, [\base]
-        .endm
-
-        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-        ldr     \irqnr, [\base, #AT91_AIC_IVR]          @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
-        ldr     \irqstat, [\base, #AT91_AIC_ISR]        @ read interrupt source number
-        teq     \irqstat, #0                            @ ISR is 0 when no current interrupt, or spurious interrupt
-        streq   \tmp, [\base, #AT91_AIC_EOICR]          @ not going to be handled further, then ACK it now.
-        .endm
-
diff --git a/arch/arm/mach-at91/include/mach/irqs.h b/arch/arm/mach-at91/include/mach/irqs.h
deleted file mode 100644
index ac8b7dfc85ef..000000000000
--- a/arch/arm/mach-at91/include/mach/irqs.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/irqs.h
- *
- *  Copyright (C) 2004 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include <linux/io.h>
-#include <mach/at91_aic.h>
-
-#define NR_AIC_IRQS 32
-
-
-/*
- * Acknowledge interrupt with AIC after interrupt has been handled.
- *   (by kernel/irq.c)
- */
-#define irq_finish(irq) do { at91_aic_write(AT91_AIC_EOICR, 0); } while (0)
-
-
-/*
- * IRQ interrupt symbols are the AT91xxx_ID_* symbols
- * for IRQs handled directly through the AIC, or else the AT91_PIN_*
- * symbols in gpio.h for ones handled indirectly as GPIOs.
- * We make provision for 5 banks of GPIO.
- */
-#define NR_IRQS         (NR_AIC_IRQS + (5 * 32))
-
-/* FIQ is AIC source 0. */
-#define FIQ_START AT91_ID_FIQ
-
-#endif
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index cfcfcbe36269..1e02c0e49dcc 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/module.h>
 #include <linux/mm.h>
+#include <linux/bitmap.h>
 #include <linux/types.h>
 #include <linux/irq.h>
 #include <linux/of.h>
@@ -30,38 +31,218 @@
 #include <linux/of_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/err.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <asm/irq.h>
 #include <asm/setup.h>
 
+#include <asm/exception.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/irq.h>
 #include <asm/mach/map.h>
 
+#include <mach/at91_aic.h>
+
 void __iomem *at91_aic_base;
 static struct irq_domain *at91_aic_domain;
 static struct device_node *at91_aic_np;
+static unsigned int n_irqs = NR_AIC_IRQS;
+static unsigned long at91_aic_caps = 0;
+
+/* AIC5 introduces a Source Select Register */
+#define AT91_AIC_CAP_AIC5       (1 << 0)
+#define has_aic5()              (at91_aic_caps & AT91_AIC_CAP_AIC5)
+
+#ifdef CONFIG_PM
+
+static unsigned long *wakeups;
+static unsigned long *backups;
+
+#define set_backup(bit) set_bit(bit, backups)
+#define clear_backup(bit) clear_bit(bit, backups)
+
+static int at91_aic_pm_init(void)
+{
+        backups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+        if (!backups)
+                return -ENOMEM;
+
+        wakeups = kzalloc(BITS_TO_LONGS(n_irqs) * sizeof(*backups), GFP_KERNEL);
+        if (!wakeups) {
+                kfree(backups);
+                return -ENOMEM;
+        }
+
+        return 0;
+}
+
+static int at91_aic_set_wake(struct irq_data *d, unsigned value)
+{
+        if (unlikely(d->hwirq >= n_irqs))
+                return -EINVAL;
+
+        if (value)
+                set_bit(d->hwirq, wakeups);
+        else
+                clear_bit(d->hwirq, wakeups);
+
+        return 0;
+}
+
+void at91_irq_suspend(void)
+{
+        int i = 0, bit;
+
+        if (has_aic5()) {
+                /* disable enabled irqs */
+                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IDCR, 1);
+                        i = bit;
+                }
+                /* enable wakeup irqs */
+                i = 0;
+                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IECR, 1);
+                        i = bit;
+                }
+        } else {
+                at91_aic_write(AT91_AIC_IDCR, *backups);
+                at91_aic_write(AT91_AIC_IECR, *wakeups);
+        }
+}
+
+void at91_irq_resume(void)
+{
+        int i = 0, bit;
+
+        if (has_aic5()) {
+                /* disable wakeup irqs */
+                while ((bit = find_next_bit(wakeups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IDCR, 1);
+                        i = bit;
+                }
+                /* enable irqs disabled for suspend */
+                i = 0;
+                while ((bit = find_next_bit(backups, n_irqs, i)) < n_irqs) {
+                        at91_aic_write(AT91_AIC5_SSR,
+                                       bit & AT91_AIC5_INTSEL_MSK);
+                        at91_aic_write(AT91_AIC5_IECR, 1);
+                        i = bit;
+                }
+        } else {
+                at91_aic_write(AT91_AIC_IDCR, *wakeups);
+                at91_aic_write(AT91_AIC_IECR, *backups);
+        }
+}
+
+#else
+static inline int at91_aic_pm_init(void)
+{
+        return 0;
+}
+
+#define set_backup(bit)
+#define clear_backup(bit)
+#define at91_aic_set_wake       NULL
+
+#endif /* CONFIG_PM */
+
+asmlinkage void __exception_irq_entry
+at91_aic_handle_irq(struct pt_regs *regs)
+{
+        u32 irqnr;
+        u32 irqstat;
+
+        irqnr = at91_aic_read(AT91_AIC_IVR);
+        irqstat = at91_aic_read(AT91_AIC_ISR);
+
+        /*
+         * ISR value is 0 when there is no current interrupt or when there is
+         * a spurious interrupt
+         */
+        if (!irqstat)
+                at91_aic_write(AT91_AIC_EOICR, 0);
+        else
+                handle_IRQ(irqnr, regs);
+}
+
+asmlinkage void __exception_irq_entry
+at91_aic5_handle_irq(struct pt_regs *regs)
+{
+        u32 irqnr;
+        u32 irqstat;
+
+        irqnr = at91_aic_read(AT91_AIC5_IVR);
+        irqstat = at91_aic_read(AT91_AIC5_ISR);
+
+        if (!irqstat)
+                at91_aic_write(AT91_AIC5_EOICR, 0);
+        else
+                handle_IRQ(irqnr, regs);
+}
 
 static void at91_aic_mask_irq(struct irq_data *d)
 {
         /* Disable interrupt on AIC */
         at91_aic_write(AT91_AIC_IDCR, 1 << d->hwirq);
+        /* Update ISR cache */
+        clear_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_mask_irq(struct irq_data *d)
+{
+        /* Disable interrupt on AIC5 */
+        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+        at91_aic_write(AT91_AIC5_IDCR, 1);
+        /* Update ISR cache */
+        clear_backup(d->hwirq);
 }
 
 static void at91_aic_unmask_irq(struct irq_data *d)
 {
         /* Enable interrupt on AIC */
         at91_aic_write(AT91_AIC_IECR, 1 << d->hwirq);
+        /* Update ISR cache */
+        set_backup(d->hwirq);
+}
+
+static void __maybe_unused at91_aic5_unmask_irq(struct irq_data *d)
+{
+        /* Enable interrupt on AIC5 */
+        at91_aic_write(AT91_AIC5_SSR, d->hwirq & AT91_AIC5_INTSEL_MSK);
+        at91_aic_write(AT91_AIC5_IECR, 1);
+        /* Update ISR cache */
+        set_backup(d->hwirq);
 }
 
-unsigned int at91_extern_irq;
+static void at91_aic_eoi(struct irq_data *d)
+{
+        /*
+         * Mark end-of-interrupt on AIC, the controller doesn't care about
+         * the value written. Moreover it's a write-only register.
+         */
+        at91_aic_write(AT91_AIC_EOICR, 0);
+}
+
+static void __maybe_unused at91_aic5_eoi(struct irq_data *d)
+{
+        at91_aic_write(AT91_AIC5_EOICR, 0);
+}
 
-#define is_extern_irq(hwirq) ((1 << (hwirq)) & at91_extern_irq)
+unsigned long *at91_extern_irq;
 
-static int at91_aic_set_type(struct irq_data *d, unsigned type)
+#define is_extern_irq(hwirq) test_bit(hwirq, at91_extern_irq)
+
+static int at91_aic_compute_srctype(struct irq_data *d, unsigned type)
 {
-        unsigned int smr, srctype;
+        int srctype;
 
         switch (type) {
         case IRQ_TYPE_LEVEL_HIGH:
@@ -74,65 +255,51 @@ static int at91_aic_set_type(struct irq_data *d, unsigned type)
                 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_LOW;
                 else
-                        return -EINVAL;
+                        srctype = -EINVAL;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
                 if ((d->hwirq == AT91_ID_FIQ) || is_extern_irq(d->hwirq))               /* only supported on external interrupts */
                         srctype = AT91_AIC_SRCTYPE_FALLING;
                 else
-                        return -EINVAL;
+                        srctype = -EINVAL;
                 break;
         default:
-                return -EINVAL;
+                srctype = -EINVAL;
         }
 
-        smr = at91_aic_read(AT91_AIC_SMR(d->hwirq)) & ~AT91_AIC_SRCTYPE;
-        at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
-        return 0;
+        return srctype;
 }
 
-#ifdef CONFIG_PM
-
-static u32 wakeups;
-static u32 backups;
-
-static int at91_aic_set_wake(struct irq_data *d, unsigned value)
+static int at91_aic_set_type(struct irq_data *d, unsigned type)
 {
-        if (unlikely(d->hwirq >= NR_AIC_IRQS))
-                return -EINVAL;
-
-        if (value)
-                wakeups |= (1 << d->hwirq);
-        else
-                wakeups &= ~(1 << d->hwirq);
+        unsigned int smr;
+        int srctype;
+
+        srctype = at91_aic_compute_srctype(d, type);
+        if (srctype < 0)
+                return srctype;
+
+        if (has_aic5()) {
+                at91_aic_write(AT91_AIC5_SSR,
+                               d->hwirq & AT91_AIC5_INTSEL_MSK);
+                smr = at91_aic_read(AT91_AIC5_SMR) & ~AT91_AIC_SRCTYPE;
+                at91_aic_write(AT91_AIC5_SMR, smr | srctype);
+        } else {
+                smr = at91_aic_read(AT91_AIC_SMR(d->hwirq))
+                      & ~AT91_AIC_SRCTYPE;
+                at91_aic_write(AT91_AIC_SMR(d->hwirq), smr | srctype);
+        }
 
         return 0;
 }
 
-void at91_irq_suspend(void)
-{
-        backups = at91_aic_read(AT91_AIC_IMR);
-        at91_aic_write(AT91_AIC_IDCR, backups);
-        at91_aic_write(AT91_AIC_IECR, wakeups);
-}
-
-void at91_irq_resume(void)
-{
-        at91_aic_write(AT91_AIC_IDCR, wakeups);
-        at91_aic_write(AT91_AIC_IECR, backups);
-}
-
-#else
-#define at91_aic_set_wake       NULL
-#endif
-
 static struct irq_chip at91_aic_chip = {
         .name           = "AIC",
-        .irq_ack        = at91_aic_mask_irq,
         .irq_mask       = at91_aic_mask_irq,
         .irq_unmask     = at91_aic_unmask_irq,
         .irq_set_type   = at91_aic_set_type,
         .irq_set_wake   = at91_aic_set_wake,
+        .irq_eoi        = at91_aic_eoi,
 };
 
 static void __init at91_aic_hw_init(unsigned int spu_vector)
@@ -161,41 +328,172 @@ static void __init at91_aic_hw_init(unsigned int spu_vector)
         at91_aic_write(AT91_AIC_ICCR, 0xFFFFFFFF);
 }
 
+static void __init __maybe_unused at91_aic5_hw_init(unsigned int spu_vector)
+{
+        int i;
+
+        /*
+         * Perform 8 End Of Interrupt Command to make sure AIC
+         * will not Lock out nIRQ
+         */
+        for (i = 0; i < 8; i++)
+                at91_aic_write(AT91_AIC5_EOICR, 0);
+
+        /*
+         * Spurious Interrupt ID in Spurious Vector Register.
+         * When there is no current interrupt, the IRQ Vector Register
+         * reads the value stored in AIC_SPU
+         */
+        at91_aic_write(AT91_AIC5_SPU, spu_vector);
+
+        /* No debugging in AIC: Debug (Protect) Control Register */
+        at91_aic_write(AT91_AIC5_DCR, 0);
+
+        /* Disable and clear all interrupts initially */
+        for (i = 0; i < n_irqs; i++) {
+                at91_aic_write(AT91_AIC5_SSR, i & AT91_AIC5_INTSEL_MSK);
+                at91_aic_write(AT91_AIC5_IDCR, 1);
+                at91_aic_write(AT91_AIC5_ICCR, 1);
+        }
+}
+
 #if defined(CONFIG_OF)
+static unsigned int *at91_aic_irq_priorities;
+
 static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
                                                         irq_hw_number_t hw)
 {
         /* Put virq number in Source Vector Register */
         at91_aic_write(AT91_AIC_SVR(hw), virq);
 
-        /* Active Low interrupt, without priority */
-        at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);
+        /* Active Low interrupt, with priority */
+        at91_aic_write(AT91_AIC_SMR(hw),
+                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
 
-        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
         set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
 
         return 0;
 }
 
+static int at91_aic5_irq_map(struct irq_domain *h, unsigned int virq,
+                irq_hw_number_t hw)
+{
+        at91_aic_write(AT91_AIC5_SSR, hw & AT91_AIC5_INTSEL_MSK);
+
+        /* Put virq number in Source Vector Register */
+        at91_aic_write(AT91_AIC5_SVR, virq);
+
+        /* Active Low interrupt, with priority */
+        at91_aic_write(AT91_AIC5_SMR,
+                       AT91_AIC_SRCTYPE_LOW | at91_aic_irq_priorities[hw]);
+
+        irq_set_chip_and_handler(virq, &at91_aic_chip, handle_fasteoi_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static int at91_aic_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
+                                const u32 *intspec, unsigned int intsize,
+                                irq_hw_number_t *out_hwirq, unsigned int *out_type)
+{
+        if (WARN_ON(intsize < 3))
+                return -EINVAL;
+        if (WARN_ON(intspec[0] >= n_irqs))
+                return -EINVAL;
+        if (WARN_ON((intspec[2] < AT91_AIC_IRQ_MIN_PRIORITY)
+                    || (intspec[2] > AT91_AIC_IRQ_MAX_PRIORITY)))
+                return -EINVAL;
+
+        *out_hwirq = intspec[0];
+        *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
+        at91_aic_irq_priorities[*out_hwirq] = intspec[2];
+
+        return 0;
+}
+
 static struct irq_domain_ops at91_aic_irq_ops = {
         .map    = at91_aic_irq_map,
-        .xlate  = irq_domain_xlate_twocell,
+        .xlate  = at91_aic_irq_domain_xlate,
 };
 
-int __init at91_aic_of_init(struct device_node *node,
-                                     struct device_node *parent)
+int __init at91_aic_of_common_init(struct device_node *node,
+                                    struct device_node *parent)
 {
+        struct property *prop;
+        const __be32 *p;
+        u32 val;
+
+        at91_extern_irq = kzalloc(BITS_TO_LONGS(n_irqs)
+                                  * sizeof(*at91_extern_irq), GFP_KERNEL);
+        if (!at91_extern_irq)
+                return -ENOMEM;
+
+        if (at91_aic_pm_init()) {
+                kfree(at91_extern_irq);
+                return -ENOMEM;
+        }
+
+        at91_aic_irq_priorities = kzalloc(n_irqs
+                                          * sizeof(*at91_aic_irq_priorities),
+                                          GFP_KERNEL);
+        if (!at91_aic_irq_priorities)
+                return -ENOMEM;
+
         at91_aic_base = of_iomap(node, 0);
         at91_aic_np = node;
 
-        at91_aic_domain = irq_domain_add_linear(at91_aic_np, NR_AIC_IRQS,
+        at91_aic_domain = irq_domain_add_linear(at91_aic_np, n_irqs,
                                                 &at91_aic_irq_ops, NULL);
         if (!at91_aic_domain)
                 panic("Unable to add AIC irq domain (DT)\n");
 
+        of_property_for_each_u32(node, "atmel,external-irqs", prop, p, val) {
+                if (val >= n_irqs)
+                        pr_warn("AIC: external irq %d >= %d skip it\n",
+                                val, n_irqs);
+                else
+                        set_bit(val, at91_extern_irq);
+        }
+
         irq_set_default_host(at91_aic_domain);
 
-        at91_aic_hw_init(NR_AIC_IRQS);
+        return 0;
+}
+
+int __init at91_aic_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        int err;
+
+        err = at91_aic_of_common_init(node, parent);
+        if (err)
+                return err;
+
+        at91_aic_hw_init(n_irqs);
+
+        return 0;
+}
+
+int __init at91_aic5_of_init(struct device_node *node,
+                                     struct device_node *parent)
+{
+        int err;
+
+        at91_aic_caps |= AT91_AIC_CAP_AIC5;
+        n_irqs = NR_AIC5_IRQS;
+        at91_aic_chip.irq_ack           = at91_aic5_mask_irq;
+        at91_aic_chip.irq_mask          = at91_aic5_mask_irq;
+        at91_aic_chip.irq_unmask        = at91_aic5_unmask_irq;
+        at91_aic_chip.irq_eoi           = at91_aic5_eoi;
+        at91_aic_irq_ops.map            = at91_aic5_irq_map;
+
+        err = at91_aic_of_common_init(node, parent);
+        if (err)
+                return err;
+
+        at91_aic5_hw_init(n_irqs);
 
         return 0;
 }
@@ -204,22 +502,25 @@ int __init at91_aic_of_init(struct device_node *node,
 /*
  * Initialize the AIC interrupt controller.
  */
-void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
+void __init at91_aic_init(unsigned int *priority)
 {
         unsigned int i;
         int irq_base;
 
+        if (at91_aic_pm_init())
+                panic("Unable to allocate bit maps\n");
+
         at91_aic_base = ioremap(AT91_AIC, 512);
         if (!at91_aic_base)
                 panic("Unable to ioremap AIC registers\n");
 
         /* Add irq domain for AIC */
-        irq_base = irq_alloc_descs(-1, 0, NR_AIC_IRQS, 0);
+        irq_base = irq_alloc_descs(-1, 0, n_irqs, 0);
         if (irq_base < 0) {
                 WARN(1, "Cannot allocate irq_descs, assuming pre-allocated\n");
                 irq_base = 0;
         }
-        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, NR_AIC_IRQS,
+        at91_aic_domain = irq_domain_add_legacy(at91_aic_np, n_irqs,
                                                 irq_base, 0,
                                                 &irq_domain_simple_ops, NULL);
 
@@ -232,15 +533,14 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
          * The IVR is used by macro get_irqnr_and_base to read and verify.
          * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
          */
-        for (i = 0; i < NR_AIC_IRQS; i++) {
+        for (i = 0; i < n_irqs; i++) {
                 /* Put hardware irq number in Source Vector Register: */
-                at91_aic_write(AT91_AIC_SVR(i), i);
+                at91_aic_write(AT91_AIC_SVR(i), NR_IRQS_LEGACY + i);
                 /* Active Low interrupt, with the specified priority */
                 at91_aic_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
-
-                irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
+                irq_set_chip_and_handler(NR_IRQS_LEGACY + i, &at91_aic_chip, handle_fasteoi_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
-        at91_aic_hw_init(NR_AIC_IRQS);
+        at91_aic_hw_init(n_irqs);
 }
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 1bfaad628731..2c2d86505a54 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -25,6 +25,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
 
+#include <mach/at91_aic.h>
 #include <mach/at91_pmc.h>
 #include <mach/cpu.h>
 
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c
index c965fd8eb31a..f15293bd7974 100644
--- a/arch/arm/mach-clps711x/common.c
+++ b/arch/arm/mach-clps711x/common.c
@@ -26,7 +26,6 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/sched.h>
-#include <linux/timex.h>
 
 #include <asm/sizes.h>
 #include <mach/hardware.h>
@@ -188,7 +187,6 @@ static struct irqaction clps711x_timer_irq = {
 
 static void __init clps711x_timer_init(void)
 {
-        struct timespec tv;
         unsigned int syscon;
 
         syscon = clps_readl(SYSCON1);
@@ -198,10 +196,6 @@ static void __init clps711x_timer_init(void)
         clps_writel(LATCH-1, TC2D); /* 512kHz / 100Hz - 1 */
 
         setup_irq(IRQ_TC2OI, &clps711x_timer_irq);
-
-        tv.tv_nsec = 0;
-        tv.tv_sec = clps_readl(RTCDR);
-        do_settimeofday(&tv);
 }
 
 struct sys_timer clps711x_timer = {
diff --git a/arch/arm/mach-clps711x/include/mach/memory.h b/arch/arm/mach-clps711x/include/mach/memory.h
index 3a032a67725c..fc0e028d9405 100644
--- a/arch/arm/mach-clps711x/include/mach/memory.h
+++ b/arch/arm/mach-clps711x/include/mach/memory.h
@@ -25,26 +25,6 @@
  */
 #define PLAT_PHYS_OFFSET        UL(0xc0000000)
 
-#if !defined(CONFIG_ARCH_CDB89712) && !defined (CONFIG_ARCH_AUTCPU12)
-
-#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
-#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
-#define __pfn_to_bus(x)         (__pfn_to_phys(x) - PHYS_OFFSET)
-#define __bus_to_pfn(x)         __phys_to_pfn((x) + PHYS_OFFSET)
-
-#endif
-
-
-/*
- * Like the SA1100, the EDB7211 has a large gap between physical RAM
- * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
- * discontiguous physical memory.  In 2.4, we can use the standard
- * Linux NUMA support.
- *
- * This is not necessary for EP7211 implementations with only one used
- * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
- */
-
 /*
  * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
  * uses only one of the two banks (bank #1).  However, even within
@@ -54,23 +34,6 @@
  * them, so we use 24 for the node max shift to get 16MB node sizes.
  */
 
-/*
- * Because of the wide memory address space between physical RAM banks on the 
- * SA1100, it's much more convenient to use Linux's NUMA support to implement
- * our memory map representation.  Assuming all memory nodes have equal access 
- * characteristics, we then have generic discontiguous memory support.
- *
- * Of course, all this isn't mandatory for SA1100 implementations with only
- * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
- *
- * The nodes are matched with the physical memory bank addresses which are 
- * incidentally the same as virtual addresses.
- * 
- *      node 0:  0xc0000000 - 0xc7ffffff
- *      node 1:  0xc8000000 - 0xcfffffff
- *      node 2:  0xd0000000 - 0xd7ffffff
- *      node 3:  0xd8000000 - 0xdfffffff
- */
 #define SECTION_SIZE_BITS       24
 #define MAX_PHYSMEM_BITS        32
 
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 42ee8f33eafb..f266d90b9efc 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -86,17 +86,7 @@ static void __init p720t_map_io(void)
         iotable_init(p720t_io_desc, ARRAY_SIZE(p720t_io_desc));
 }
 
-MACHINE_START(P720T, "ARM-Prospector720T")
-        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
-        .atag_offset    = 0x100,
-        .fixup          = fixup_p720t,
-        .map_io         = p720t_map_io,
-        .init_irq       = clps711x_init_irq,
-        .timer          = &clps711x_timer,
-        .restart        = clps711x_restart,
-MACHINE_END
-
-static int p720t_hw_init(void)
+static void __init p720t_init_early(void)
 {
         /*
          * Power down as much as possible in case we don't
@@ -111,13 +101,19 @@ static int p720t_hw_init(void)
         PLD_CODEC = 0;
         PLD_TCH   = 0;
         PLD_SPI   = 0;
-#ifndef CONFIG_DEBUG_LL
-        PLD_COM2  = 0;
-        PLD_COM1  = 0;
-#endif
-
-        return 0;
+        if (!IS_ENABLED(CONFIG_DEBUG_LL)) {
+                PLD_COM2 = 0;
+                PLD_COM1 = 0;
+        }
 }
 
-__initcall(p720t_hw_init);
-
+MACHINE_START(P720T, "ARM-Prospector720T")
+        /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
+        .atag_offset    = 0x100,
+        .fixup          = fixup_p720t,
+        .init_early     = p720t_init_early,
+        .map_io         = p720t_map_io,
+        .init_irq       = clps711x_init_irq,
+        .timer          = &clps711x_timer,
+        .restart        = clps711x_restart,
+MACHINE_END
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 32d837d8eab9..2ce1ef07c13d 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -4,6 +4,7 @@ config AINTC
         bool
 
 config CP_INTC
+        select IRQ_DOMAIN
         bool
 
 config ARCH_DAVINCI_DMx
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index 2db78bd5c835..2227effcb0e9 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD)	+= board-omapl138-hawk.o
 obj-$(CONFIG_CPU_FREQ)                  += cpufreq.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_SUSPEND)                   += pm.o sleep.o
+obj-$(CONFIG_HAVE_CLK)                  += pm_domain.o
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index f83152d643c5..006dae8dfe44 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -9,9 +9,14 @@
  * kind, whether express or implied.
  */
 
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/irqdomain.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
 
 #include <mach/common.h>
 #include <mach/cp_intc.h>
@@ -28,7 +33,7 @@ static inline void cp_intc_write(unsigned long value, unsigned offset)
 
 static void cp_intc_ack_irq(struct irq_data *d)
 {
-        cp_intc_write(d->irq, CP_INTC_SYS_STAT_IDX_CLR);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_STAT_IDX_CLR);
 }
 
 /* Disable interrupt */
@@ -36,20 +41,20 @@ static void cp_intc_mask_irq(struct irq_data *d)
 {
         /* XXX don't know why we need to disable nIRQ here... */
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_CLR);
-        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_CLR);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_CLR);
         cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET);
 }
 
 /* Enable interrupt */
 static void cp_intc_unmask_irq(struct irq_data *d)
 {
-        cp_intc_write(d->irq, CP_INTC_SYS_ENABLE_IDX_SET);
+        cp_intc_write(d->hwirq, CP_INTC_SYS_ENABLE_IDX_SET);
 }
 
 static int cp_intc_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        unsigned reg            = BIT_WORD(d->irq);
-        unsigned mask           = BIT_MASK(d->irq);
+        unsigned reg            = BIT_WORD(d->hwirq);
+        unsigned mask           = BIT_MASK(d->hwirq);
         unsigned polarity       = cp_intc_read(CP_INTC_SYS_POLARITY(reg));
         unsigned type           = cp_intc_read(CP_INTC_SYS_TYPE(reg));
 
@@ -99,18 +104,43 @@ static struct irq_chip cp_intc_irq_chip = {
         .irq_set_wake   = cp_intc_set_wake,
 };
 
-void __init cp_intc_init(void)
+static struct irq_domain *cp_intc_domain;
+
+static int cp_intc_host_map(struct irq_domain *h, unsigned int virq,
+                          irq_hw_number_t hw)
 {
-        unsigned long num_irq   = davinci_soc_info.intc_irq_num;
+        pr_debug("cp_intc_host_map(%d, 0x%lx)\n", virq, hw);
+
+        irq_set_chip(virq, &cp_intc_irq_chip);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+        irq_set_handler(virq, handle_edge_irq);
+        return 0;
+}
+
+static const struct irq_domain_ops cp_intc_host_ops = {
+        .map = cp_intc_host_map,
+        .xlate = irq_domain_xlate_onetwocell,
+};
+
+int __init cp_intc_of_init(struct device_node *node, struct device_node *parent)
+{
+        u32 num_irq             = davinci_soc_info.intc_irq_num;
         u8 *irq_prio            = davinci_soc_info.intc_irq_prios;
         u32 *host_map           = davinci_soc_info.intc_host_map;
         unsigned num_reg        = BITS_TO_LONGS(num_irq);
-        int i;
+        int i, irq_base;
 
         davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC;
-        davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+        if (node) {
+                davinci_intc_base = of_iomap(node, 0);
+                if (of_property_read_u32(node, "ti,intc-size", &num_irq))
+                        pr_warn("unable to get intc-size, default to %d\n",
+                                num_irq);
+        } else {
+                davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K);
+        }
         if (WARN_ON(!davinci_intc_base))
-                return;
+                return -EINVAL;
 
         cp_intc_write(0, CP_INTC_GLOBAL_ENABLE);
 
@@ -165,13 +195,28 @@ void __init cp_intc_init(void)
                 for (i = 0; host_map[i] != -1; i++)
                         cp_intc_write(host_map[i], CP_INTC_HOST_MAP(i));
 
-        /* Set up genirq dispatching for cp_intc */
-        for (i = 0; i < num_irq; i++) {
-                irq_set_chip(i, &cp_intc_irq_chip);
-                set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                irq_set_handler(i, handle_edge_irq);
+        irq_base = irq_alloc_descs(-1, 0, num_irq, 0);
+        if (irq_base < 0) {
+                pr_warn("Couldn't allocate IRQ numbers\n");
+                irq_base = 0;
+        }
+
+        /* create a legacy host */
+        cp_intc_domain = irq_domain_add_legacy(node, num_irq,
+                                        irq_base, 0, &cp_intc_host_ops, NULL);
+
+        if (!cp_intc_domain) {
+                pr_err("cp_intc: failed to allocate irq host!\n");
+                return -EINVAL;
         }
 
         /* Enable global interrupt */
         cp_intc_write(1, CP_INTC_GLOBAL_ENABLE);
+
+        return 0;
+}
+
+void __init cp_intc_init(void)
+{
+        cp_intc_of_init(NULL, NULL);
 }
diff --git a/arch/arm/mach-davinci/include/mach/cp_intc.h b/arch/arm/mach-davinci/include/mach/cp_intc.h
index 4e8190eed673..d13d8dfa2b0d 100644
--- a/arch/arm/mach-davinci/include/mach/cp_intc.h
+++ b/arch/arm/mach-davinci/include/mach/cp_intc.h
@@ -52,5 +52,6 @@
 #define CP_INTC_VECTOR_ADDR(n)          (0x2000 + (n << 2))
 
 void __init cp_intc_init(void);
+int __init cp_intc_of_init(struct device_node *, struct device_node *);
 
 #endif  /* __ASM_HARDWARE_CP_INTC_H */
diff --git a/arch/arm/mach-davinci/include/mach/dm365.h b/arch/arm/mach-davinci/include/mach/dm365.h
deleted file mode 100644
index b9bf3d6a4423..000000000000
--- a/arch/arm/mach-davinci/include/mach/dm365.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
deleted file mode 100644
index b9bf3d6a4423..000000000000
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ /dev/null
@@ -1 +0,0 @@
-/* empty, remove once unused */
diff --git a/arch/arm/mach-davinci/include/mach/entry-macro.S b/arch/arm/mach-davinci/include/mach/entry-macro.S
index 768b3c060214..cf5f573eb5fd 100644
--- a/arch/arm/mach-davinci/include/mach/entry-macro.S
+++ b/arch/arm/mach-davinci/include/mach/entry-macro.S
@@ -30,12 +30,10 @@
 #endif
 #if defined(CONFIG_CP_INTC)
 1001:           ldr \irqnr, [\base, #0x80] /* get irq number */
+                mov \tmp, \irqnr, lsr #31
                 and \irqnr, \irqnr, #0xff  /* irq is in bits 0-9 */
-                mov \tmp, \irqnr, lsr #3
-                and \tmp, \tmp, #0xfc
-                add \tmp, \tmp, #0x280 /* get the register offset */
-                ldr \irqstat, [\base, \tmp] /* get the intc status */
-                cmp \irqstat, #0x0
+                and \tmp, \tmp, #0x1
+                cmp \tmp, #0x1
 #endif
 1002:
                 .endm
diff --git a/arch/arm/mach-davinci/pm_domain.c b/arch/arm/mach-davinci/pm_domain.c
new file mode 100644
index 000000000000..00946e23c1ee
--- /dev/null
+++ b/arch/arm/mach-davinci/pm_domain.c
@@ -0,0 +1,64 @@
+/*
+ * Runtime PM support code for DaVinci
+ *
+ * Author: Kevin Hilman
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/init.h>
+#include <linux/pm_runtime.h>
+#include <linux/pm_clock.h>
+#include <linux/platform_device.h>
+
+#ifdef CONFIG_PM_RUNTIME
+static int davinci_pm_runtime_suspend(struct device *dev)
+{
+        int ret;
+
+        dev_dbg(dev, "%s\n", __func__);
+
+        ret = pm_generic_runtime_suspend(dev);
+        if (ret)
+                return ret;
+
+        ret = pm_clk_suspend(dev);
+        if (ret) {
+                pm_generic_runtime_resume(dev);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int davinci_pm_runtime_resume(struct device *dev)
+{
+        dev_dbg(dev, "%s\n", __func__);
+
+        pm_clk_resume(dev);
+        return pm_generic_runtime_resume(dev);
+}
+#endif
+
+static struct dev_pm_domain davinci_pm_domain = {
+        .ops = {
+                SET_RUNTIME_PM_OPS(davinci_pm_runtime_suspend,
+                                   davinci_pm_runtime_resume, NULL)
+                USE_PLATFORM_PM_SLEEP_OPS
+        },
+};
+
+static struct pm_clk_notifier_block platform_bus_notifier = {
+        .pm_domain = &davinci_pm_domain,
+};
+
+static int __init davinci_pm_runtime_init(void)
+{
+        pm_clk_add_notifier(&platform_bus_type, &platform_bus_notifier);
+
+        return 0;
+}
+core_initcall(davinci_pm_runtime_init);
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 4dd07a0e3604..4afe52aaaff3 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -797,6 +797,102 @@ static struct platform_device ep93xx_wdt_device = {
         .resource       = ep93xx_wdt_resources,
 };
 
+/*************************************************************************
+ * EP93xx IDE
+ *************************************************************************/
+static struct resource ep93xx_ide_resources[] = {
+        DEFINE_RES_MEM(EP93XX_IDE_PHYS_BASE, 0x38),
+        DEFINE_RES_IRQ(IRQ_EP93XX_EXT3),
+};
+
+static struct platform_device ep93xx_ide_device = {
+        .name           = "ep93xx-ide",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &ep93xx_ide_device.dev.coherent_dma_mask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .num_resources  = ARRAY_SIZE(ep93xx_ide_resources),
+        .resource       = ep93xx_ide_resources,
+};
+
+void __init ep93xx_register_ide(void)
+{
+        platform_device_register(&ep93xx_ide_device);
+}
+
+int ep93xx_ide_acquire_gpio(struct platform_device *pdev)
+{
+        int err;
+        int i;
+
+        err = gpio_request(EP93XX_GPIO_LINE_EGPIO2, dev_name(&pdev->dev));
+        if (err)
+                return err;
+        err = gpio_request(EP93XX_GPIO_LINE_EGPIO15, dev_name(&pdev->dev));
+        if (err)
+                goto fail_egpio15;
+        for (i = 2; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_E(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_e;
+        }
+        for (i = 4; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_G(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_g;
+        }
+        for (i = 0; i < 8; i++) {
+                err = gpio_request(EP93XX_GPIO_LINE_H(i), dev_name(&pdev->dev));
+                if (err)
+                        goto fail_gpio_h;
+        }
+
+        /* GPIO ports E[7:2], G[7:4] and H used by IDE */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
+                                 EP93XX_SYSCON_DEVCFG_GONIDE |
+                                 EP93XX_SYSCON_DEVCFG_HONIDE);
+        return 0;
+
+fail_gpio_h:
+        for (--i; i >= 0; --i)
+                gpio_free(EP93XX_GPIO_LINE_H(i));
+        i = 8;
+fail_gpio_g:
+        for (--i; i >= 4; --i)
+                gpio_free(EP93XX_GPIO_LINE_G(i));
+        i = 8;
+fail_gpio_e:
+        for (--i; i >= 2; --i)
+                gpio_free(EP93XX_GPIO_LINE_E(i));
+        gpio_free(EP93XX_GPIO_LINE_EGPIO15);
+fail_egpio15:
+        gpio_free(EP93XX_GPIO_LINE_EGPIO2);
+        return err;
+}
+EXPORT_SYMBOL(ep93xx_ide_acquire_gpio);
+
+void ep93xx_ide_release_gpio(struct platform_device *pdev)
+{
+        int i;
+
+        for (i = 2; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_E(i));
+        for (i = 4; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_G(i));
+        for (i = 0; i < 8; i++)
+                gpio_free(EP93XX_GPIO_LINE_H(i));
+        gpio_free(EP93XX_GPIO_LINE_EGPIO15);
+        gpio_free(EP93XX_GPIO_LINE_EGPIO2);
+
+
+        /* GPIO ports E[7:2], G[7:4] and H used by GPIO */
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_EONIDE |
+                               EP93XX_SYSCON_DEVCFG_GONIDE |
+                               EP93XX_SYSCON_DEVCFG_HONIDE);
+}
+EXPORT_SYMBOL(ep93xx_ide_release_gpio);
+
 void __init ep93xx_init_devices(void)
 {
         /* Disallow access to MaverickCrunch initially */
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index d74c5cddb98b..337ab7cf4c16 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -91,8 +91,8 @@ static void __init edb93xx_register_i2c(void)
                 ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
                                     edb93xxa_i2c_board_info,
                                     ARRAY_SIZE(edb93xxa_i2c_board_info));
-        } else if (machine_is_edb9307() || machine_is_edb9312() ||
-                   machine_is_edb9315()) {
+        } else if (machine_is_edb9302() || machine_is_edb9307()
+                || machine_is_edb9312() || machine_is_edb9315()) {
                 ep93xx_register_i2c(&edb93xx_i2c_gpio_data,
                                     edb93xx_i2c_board_info,
                                     ARRAY_SIZE(edb93xx_i2c_board_info));
@@ -233,6 +233,29 @@ static void __init edb93xx_register_fb(void)
 }
 
 
+/*************************************************************************
+ * EDB93xx IDE
+ *************************************************************************/
+static int __init edb93xx_has_ide(void)
+{
+        /*
+         * Although EDB9312 and EDB9315 do have IDE capability, they have
+         * INTRQ line wired as pull-up, which makes using IDE interface
+         * problematic.
+         */
+        return machine_is_edb9312() || machine_is_edb9315() ||
+               machine_is_edb9315a();
+}
+
+static void __init edb93xx_register_ide(void)
+{
+        if (!edb93xx_has_ide())
+                return;
+
+        ep93xx_register_ide();
+}
+
+
 static void __init edb93xx_init_machine(void)
 {
         ep93xx_init_devices();
@@ -243,6 +266,7 @@ static void __init edb93xx_init_machine(void)
         edb93xx_register_i2s();
         edb93xx_register_pwm();
         edb93xx_register_fb();
+        edb93xx_register_ide();
 }
 
 
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 1ecb040d98bf..33a5122c6dc8 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -48,6 +48,9 @@ void ep93xx_register_i2s(void);
 int ep93xx_i2s_acquire(void);
 void ep93xx_i2s_release(void);
 void ep93xx_register_ac97(void);
+void ep93xx_register_ide(void);
+int ep93xx_ide_acquire_gpio(struct platform_device *pdev);
+void ep93xx_ide_release_gpio(struct platform_device *pdev);
 
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index 979fba722926..7bf7ff8beae7 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -69,6 +69,7 @@
 
 #define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
 
+#define EP93XX_IDE_PHYS_BASE            EP93XX_AHB_PHYS(0x000a0000)
 #define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
 
 #define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index bcb7db453145..26fe9de35ecb 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -586,17 +586,17 @@ static struct clk exynos4_init_clocks_off[] = {
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 16),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
                 .enable         = exynos4_clk_ip_peril_ctrl,
                 .ctrlbit        = (1 << 18),
         }, {
@@ -1242,40 +1242,67 @@ static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
         .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 };
 
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.0",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.1",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.2",
+        },
+        .sources = &exynos4_clkset_group,
+        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
 static struct clksrc_clk exynos4_clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos4_clk_mdout_spi0.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 16),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
 };
 
 static struct clksrc_clk exynos4_clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos4_clk_mdout_spi1.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 20),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
 };
 
 static struct clksrc_clk exynos4_clk_sclk_spi2 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos4_clk_mdout_spi2.clk,
                 .enable         = exynos4_clksrc_mask_peril1_ctrl,
                 .ctrlbit        = (1 << 24),
         },
-        .sources = &exynos4_clkset_group,
-        .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
-        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+        .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
 };
 
 /* Clock initialization code */
@@ -1331,7 +1358,9 @@ static struct clksrc_clk *exynos4_clksrc_cdev[] = {
         &exynos4_clk_sclk_spi0,
         &exynos4_clk_sclk_spi1,
         &exynos4_clk_sclk_spi2,
-
+        &exynos4_clk_mdout_spi0,
+        &exynos4_clk_mdout_spi1,
+        &exynos4_clk_mdout_spi2,
 };
 
 static struct clk_lookup exynos4_clk_lookup[] = {
@@ -1347,9 +1376,9 @@ static struct clk_lookup exynos4_clk_lookup[] = {
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
 };
 
 static int xtal_rate;
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index fefa336be2b4..774533c67066 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -131,6 +131,11 @@ static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
         return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
 }
 
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+        return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
 static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
 {
         return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
@@ -741,6 +746,24 @@ static struct clk exynos5_init_clocks_off[] = {
                 .enable         = exynos5_clk_ip_peric_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 16),
+        }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 17),
+        }, {
+                .name           = "spi",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos5_clk_aclk_66.clk,
+                .enable         = exynos5_clk_ip_peric_ctrl,
+                .ctrlbit        = (1 << 18),
+        }, {
                 .name           = SYSMMU_CLOCK_NAME,
                 .devname        = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
                 .enable         = &exynos5_clk_ip_mfc_ctrl,
@@ -1034,6 +1057,69 @@ static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
         .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
 };
 
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.0",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.1",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+        .clk    = {
+                .name           = "mdout_spi",
+                .devname        = "exynos4210-spi.2",
+        },
+        .sources = &exynos5_clkset_group,
+        .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.0",
+                .parent         = &exynos5_clk_mdout_spi0.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 16),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.1",
+                .parent         = &exynos5_clk_mdout_spi1.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 20),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+        .clk    = {
+                .name           = "sclk_spi",
+                .devname        = "exynos4210-spi.2",
+                .parent         = &exynos5_clk_mdout_spi2.clk,
+                .enable         = exynos5_clksrc_mask_peric1_ctrl,
+                .ctrlbit        = (1 << 24),
+        },
+        .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
 static struct clksrc_clk exynos5_clksrcs[] = {
         {
                 .clk    = {
@@ -1148,6 +1234,12 @@ static struct clksrc_clk *exynos5_sysclks[] = {
         &exynos5_clk_dout_mmc4,
         &exynos5_clk_aclk_acp,
         &exynos5_clk_pclk_acp,
+        &exynos5_clk_sclk_spi0,
+        &exynos5_clk_sclk_spi1,
+        &exynos5_clk_sclk_spi2,
+        &exynos5_clk_mdout_spi0,
+        &exynos5_clk_mdout_spi1,
+        &exynos5_clk_mdout_spi2,
 };
 
 static struct clk *exynos5_clk_cdev[] = {
@@ -1176,6 +1268,9 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
         CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
         CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+        CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+        CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 742edd3bbec3..4eb39cdf75ea 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -540,7 +540,8 @@ static struct irq_domain_ops combiner_irq_domain_ops = {
         .map    = combiner_irq_domain_map,
 };
 
-void __init combiner_init(void __iomem *combiner_base, struct device_node *np)
+static void __init combiner_init(void __iomem *combiner_base,
+                                 struct device_node *np)
 {
         int i, irq, irq_base;
         unsigned int max_nr, nr_irq;
@@ -712,31 +713,6 @@ static int __init exynos4_l2x0_cache_init(void)
 early_initcall(exynos4_l2x0_cache_init);
 #endif
 
-static int __init exynos5_l2_cache_init(void)
-{
-        unsigned int val;
-
-        if (!soc_is_exynos5250())
-                return 0;
-
-        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
-                     "bic %0, %0, #(1 << 2)\n"  /* cache disable */
-                     "mcr p15, 0, %0, c1, c0, 0\n"
-                     "mrc p15, 1, %0, c9, c0, 2\n"
-                     : "=r"(val));
-
-        val |= (1 << 9) | (1 << 5) | (2 << 6) | (2 << 0);
-
-        asm volatile("mcr p15, 1, %0, c9, c0, 2\n" : : "r"(val));
-        asm volatile("mrc p15, 0, %0, c1, c0, 0\n"
-                     "orr %0, %0, #(1 << 2)\n"  /* cache enable */
-                     "mcr p15, 0, %0, c1, c0, 0\n"
-                     : : "r"(val));
-
-        return 0;
-}
-early_initcall(exynos5_l2_cache_init);
-
 static int __init exynos_init(void)
 {
         printk(KERN_INFO "EXYNOS: Initializing architecture\n");
diff --git a/arch/arm/mach-exynos/include/mach/irqs.h b/arch/arm/mach-exynos/include/mach/irqs.h
index 7a4b4789eb72..35bced6f9092 100644
--- a/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/arch/arm/mach-exynos/include/mach/irqs.h
@@ -195,6 +195,10 @@
 #define IRQ_IIC6                        EXYNOS4_IRQ_IIC6
 #define IRQ_IIC7                        EXYNOS4_IRQ_IIC7
 
+#define IRQ_SPI0                        EXYNOS4_IRQ_SPI0
+#define IRQ_SPI1                        EXYNOS4_IRQ_SPI1
+#define IRQ_SPI2                        EXYNOS4_IRQ_SPI2
+
 #define IRQ_USB_HOST                    EXYNOS4_IRQ_USB_HOST
 #define IRQ_OTG                         EXYNOS4_IRQ_USB_HSOTG
 
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index ca4aa89aa46b..c72b675b3e4b 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -154,6 +154,9 @@
 #define EXYNOS4_PA_SPI0                 0x13920000
 #define EXYNOS4_PA_SPI1                 0x13930000
 #define EXYNOS4_PA_SPI2                 0x13940000
+#define EXYNOS5_PA_SPI0                 0x12D20000
+#define EXYNOS5_PA_SPI1                 0x12D30000
+#define EXYNOS5_PA_SPI2                 0x12D40000
 
 #define EXYNOS4_PA_GPIO1                0x11400000
 #define EXYNOS4_PA_GPIO2                0x11000000
diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index 43a99e6f56ab..d4e392b811a3 100644
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -232,6 +232,11 @@
 
 #define EXYNOS5_USB_CFG                                         S5P_PMUREG(0x0230)
 
+#define EXYNOS5_AUTO_WDTRESET_DISABLE                           S5P_PMUREG(0x0408)
+#define EXYNOS5_MASK_WDTRESET_REQUEST                           S5P_PMUREG(0x040C)
+
+#define EXYNOS5_SYS_WDTRESET                                    (1 << 20)
+
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG                           S5P_PMUREG(0x1000)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG             S5P_PMUREG(0x1004)
 #define EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG           S5P_PMUREG(0x1008)
diff --git a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
index c337cf3a71bf..07277735252e 100644
--- a/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
+++ b/arch/arm/mach-exynos/include/mach/regs-usb-phy.h
@@ -35,11 +35,21 @@
 #define PHY1_COMMON_ON_N                (1 << 7)
 #define PHY0_COMMON_ON_N                (1 << 4)
 #define PHY0_ID_PULLUP                  (1 << 2)
-#define CLKSEL_MASK                     (0x3 << 0)
-#define CLKSEL_SHIFT                    (0)
-#define CLKSEL_48M                      (0x0 << 0)
-#define CLKSEL_12M                      (0x2 << 0)
-#define CLKSEL_24M                      (0x3 << 0)
+
+#define EXYNOS4_CLKSEL_SHIFT            (0)
+
+#define EXYNOS4210_CLKSEL_MASK          (0x3 << 0)
+#define EXYNOS4210_CLKSEL_48M           (0x0 << 0)
+#define EXYNOS4210_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4210_CLKSEL_24M           (0x3 << 0)
+
+#define EXYNOS4X12_CLKSEL_MASK          (0x7 << 0)
+#define EXYNOS4X12_CLKSEL_9600K         (0x0 << 0)
+#define EXYNOS4X12_CLKSEL_10M           (0x1 << 0)
+#define EXYNOS4X12_CLKSEL_12M           (0x2 << 0)
+#define EXYNOS4X12_CLKSEL_19200K        (0x3 << 0)
+#define EXYNOS4X12_CLKSEL_20M           (0x4 << 0)
+#define EXYNOS4X12_CLKSEL_24M           (0x5 << 0)
 
 #define EXYNOS4_RSTCON                  EXYNOS4_HSOTG_PHYREG(0x08)
 #define HOST_LINK_PORT_SWRST_MASK       (0xf << 6)
diff --git a/arch/arm/mach-exynos/include/mach/spi-clocks.h b/arch/arm/mach-exynos/include/mach/spi-clocks.h
deleted file mode 100644
index c71a5fba6a84..000000000000
--- a/arch/arm/mach-exynos/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/spi-clocks.h
- *
- * Copyright (C) 2011 Samsung Electronics Co. Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_SPI_CLKS_H
-#define __ASM_ARCH_SPI_CLKS_H __FILE__
-
-/* Must source from SCLK_SPI */
-#define EXYNOS_SPI_SRCCLK_SCLK          0
-
-#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-exynos/mach-exynos4-dt.c b/arch/arm/mach-exynos/mach-exynos4-dt.c
index e7e9743543ac..b2b5d5faa748 100644
--- a/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -55,6 +55,12 @@ static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
                                 "exynos4-sdhci.3", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
                                 "s3c2440-i2c.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
+                                "exynos4210-spi.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
+                                "exynos4210-spi.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
+                                "exynos4210-spi.2", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
         {},
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index 7b1e11a228cc..ef770bc2318f 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -47,6 +47,12 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
                                 "s3c2440-i2c.0", NULL),
         OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
                                 "s3c2440-i2c.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
+                                "exynos4210-spi.0", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
+                                "exynos4210-spi.1", NULL),
+        OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
+                                "exynos4210-spi.2", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
         OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index 656f8fc9addd..f3b328d0aff6 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-cfg.h>
 #include <plat/iic.h>
 #include <plat/mfc.h>
-#include <plat/pd.h>
 #include <plat/fimc-core.h>
 #include <plat/camport.h>
 #include <plat/mipi_csis.h>
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index f5572be9d7bf..873c708fd340 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -38,7 +38,6 @@
 #include <plat/clock.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
-#include <plat/pd.h>
 #include <plat/fb.h>
 #include <plat/mfc.h>
 
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index 262e9e446a96..5fb209c4a594 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -34,7 +34,6 @@
 #include <plat/keypad.h>
 #include <plat/sdhci.h>
 #include <plat/iic.h>
-#include <plat/pd.h>
 #include <plat/gpio-cfg.h>
 #include <plat/backlight.h>
 #include <plat/mfc.h>
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index cd92fa86ba41..68719f57dcea 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -39,7 +39,6 @@
 #include <plat/fb.h>
 #include <plat/mfc.h>
 #include <plat/sdhci.h>
-#include <plat/pd.h>
 #include <plat/regs-fb-v4.h>
 #include <plat/fimc-core.h>
 #include <plat/s5p-time.h>
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index e9fafcf163de..373c3c00d24c 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -119,7 +119,9 @@ static __init void exynos_pm_add_dev_to_genpd(struct platform_device *pdev,
                                                 struct exynos_pm_domain *pd)
 {
         if (pdev->dev.bus) {
-                if (pm_genpd_add_device(&pd->pd, &pdev->dev))
+                if (!pm_genpd_add_device(&pd->pd, &pdev->dev))
+                        pm_genpd_dev_need_restore(&pdev->dev, true);
+                else
                         pr_info("%s: error in adding %s device to %s power"
                                 "domain\n", __func__, dev_name(&pdev->dev),
                                 pd->name);
@@ -151,9 +153,12 @@ static __init int exynos4_pm_init_power_domain(void)
         if (of_have_populated_dt())
                 return exynos_pm_dt_parse_domains();
 
-        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++)
-                pm_genpd_init(&exynos4_pm_domains[idx]->pd, NULL,
-                                exynos4_pm_domains[idx]->is_off);
+        for (idx = 0; idx < ARRAY_SIZE(exynos4_pm_domains); idx++) {
+                struct exynos_pm_domain *pd = exynos4_pm_domains[idx];
+                int on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN;
+
+                pm_genpd_init(&pd->pd, NULL, !on);
+        }
 
 #ifdef CONFIG_S5P_DEV_FIMD0
         exynos_pm_add_dev_to_genpd(&s5p_device_fimd0, &exynos4_pd_lcd0);
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 4aacb66f7161..3a48c852be6c 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -315,7 +315,7 @@ static struct exynos_pmu_conf exynos5250_pmu_config[] = {
         { PMU_TABLE_END,},
 };
 
-void __iomem *exynos5_list_both_cnt_feed[] = {
+static void __iomem *exynos5_list_both_cnt_feed[] = {
         EXYNOS5_ARM_CORE0_OPTION,
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_ARM_COMMON_OPTION,
@@ -329,7 +329,7 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
         EXYNOS5_TOP_PWR_SYSMEM_OPTION,
 };
 
-void __iomem *exynos5_list_diable_wfi_wfe[] = {
+static void __iomem *exynos5_list_diable_wfi_wfe[] = {
         EXYNOS5_ARM_CORE1_OPTION,
         EXYNOS5_FSYS_ARM_OPTION,
         EXYNOS5_ISP_ARM_OPTION,
@@ -390,6 +390,8 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode)
 
 static int __init exynos_pmu_init(void)
 {
+        unsigned int value;
+
         exynos_pmu_config = exynos4210_pmu_config;
 
         if (soc_is_exynos4210()) {
@@ -399,6 +401,18 @@ static int __init exynos_pmu_init(void)
                 exynos_pmu_config = exynos4x12_pmu_config;
                 pr_info("EXYNOS4x12 PMU Initialize\n");
         } else if (soc_is_exynos5250()) {
+                /*
+                 * When SYS_WDTRESET is set, watchdog timer reset request
+                 * is ignored by power management unit.
+                 */
+                value = __raw_readl(EXYNOS5_AUTO_WDTRESET_DISABLE);
+                value &= ~EXYNOS5_SYS_WDTRESET;
+                __raw_writel(value, EXYNOS5_AUTO_WDTRESET_DISABLE);
+
+                value = __raw_readl(EXYNOS5_MASK_WDTRESET_REQUEST);
+                value &= ~EXYNOS5_SYS_WDTRESET;
+                __raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
+
                 exynos_pmu_config = exynos5250_pmu_config;
                 pr_info("EXYNOS5250 PMU Initialize\n");
         } else {
diff --git a/arch/arm/mach-exynos/setup-spi.c b/arch/arm/mach-exynos/setup-spi.c
index 833ff40ee0e8..4999829d1c6e 100644
--- a/arch/arm/mach-exynos/setup-spi.c
+++ b/arch/arm/mach-exynos/setup-spi.c
@@ -9,21 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(0), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(EXYNOS4_GPB(0), S3C_GPIO_PULL_UP);
@@ -34,15 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPB(4), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(EXYNOS4_GPB(4), S3C_GPIO_PULL_UP);
@@ -53,15 +34,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .clk_from_cmu   = true,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(EXYNOS4_GPC1(1), S3C_GPIO_SFN(5));
         s3c_gpio_setpull(EXYNOS4_GPC1(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1af0a7f44e00..b81cc569a8dd 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -31,27 +31,55 @@ static void exynos4210_usb_phy_clkset(struct platform_device *pdev)
         struct clk *xusbxti_clk;
         u32 phyclk;
 
-        /* set clock frequency for PLL */
-        phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
-
         xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
         if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
-                switch (clk_get_rate(xusbxti_clk)) {
-                case 12 * MHZ:
-                        phyclk |= CLKSEL_12M;
-                        break;
-                case 24 * MHZ:
-                        phyclk |= CLKSEL_24M;
-                        break;
-                default:
-                case 48 * MHZ:
-                        /* default reference clock */
-                        break;
+                if (soc_is_exynos4210()) {
+                        /* set clock frequency for PLL */
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4210_CLKSEL_MASK;
+
+                        switch (clk_get_rate(xusbxti_clk)) {
+                        case 12 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_12M;
+                                break;
+                        case 48 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_48M;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                phyclk |= EXYNOS4210_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
+                } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+                        /* set clock frequency for PLL */
+                        phyclk = readl(EXYNOS4_PHYCLK) & ~EXYNOS4X12_CLKSEL_MASK;
+
+                        switch (clk_get_rate(xusbxti_clk)) {
+                        case 9600 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_9600K;
+                                break;
+                        case 10 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_10M;
+                                break;
+                        case 12 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_12M;
+                                break;
+                        case 19200 * KHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_19200K;
+                                break;
+                        case 20 * MHZ:
+                                phyclk |= EXYNOS4X12_CLKSEL_20M;
+                                break;
+                        default:
+                        case 24 * MHZ:
+                                /* default reference clock */
+                                phyclk |= EXYNOS4X12_CLKSEL_24M;
+                                break;
+                        }
+                        writel(phyclk, EXYNOS4_PHYCLK);
                 }
                 clk_put(xusbxti_clk);
         }
-
-        writel(phyclk, EXYNOS4_PHYCLK);
 }
 
 static int exynos4210_usb_phy0_init(struct platform_device *pdev)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index eff4db5de0dd..7616101a35f0 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -52,6 +52,7 @@ config SOC_IMX25
         select ARCH_MX25
         select COMMON_CLK
         select CPU_ARM926T
+        select HAVE_CAN_FLEXCAN if CAN
         select ARCH_MXC_IOMUX_V3
         select MXC_AVIC
 
@@ -73,12 +74,13 @@ config SOC_IMX31
 
 config SOC_IMX35
         bool
-        select CPU_V6
+        select CPU_V6K
         select ARCH_MXC_IOMUX_V3
         select COMMON_CLK
         select HAVE_EPIT
         select MXC_AVIC
         select SMP_ON_UP if SMP
+        select HAVE_CAN_FLEXCAN if CAN
 
 config SOC_IMX5
         select CPU_V7
@@ -105,6 +107,7 @@ config	SOC_IMX53
         select SOC_IMX5
         select ARCH_MX5
         select ARCH_MX53
+        select HAVE_CAN_FLEXCAN if CAN
 
 if ARCH_IMX_V4_V5
 
@@ -158,7 +161,6 @@ config MACH_MX25_3DS
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select IMX_HAVE_PLATFORM_IMXDI_RTC
         select IMX_HAVE_PLATFORM_IMX_I2C
-        select IMX_HAVE_PLATFORM_IMX_SSI
         select IMX_HAVE_PLATFORM_IMX_FB
         select IMX_HAVE_PLATFORM_IMX_KEYPAD
         select IMX_HAVE_PLATFORM_IMX_UART
@@ -557,6 +559,14 @@ config MACH_BUG
           Include support for BUGBase 1.3 platform. This includes specific
           configurations for the board and its peripherals.
 
+config MACH_IMX31_DT
+        bool "Support i.MX31 platforms from device tree"
+        select SOC_IMX31
+        select USE_OF
+        help
+          Include support for Freescale i.MX31 based platforms
+          using the device tree for discovery.
+
 comment "MX35 platforms:"
 
 config MACH_PCM043
@@ -589,6 +599,7 @@ config MACH_MX35_3DS
         select IMX_HAVE_PLATFORM_IPU_CORE
         select IMX_HAVE_PLATFORM_MXC_EHCI
         select IMX_HAVE_PLATFORM_MXC_NAND
+        select IMX_HAVE_PLATFORM_MXC_RTC
         select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
         help
           Include support for MX35PDK platform. This includes specific
@@ -826,10 +837,12 @@ config SOC_IMX6Q
         select COMMON_CLK
         select CPU_V7
         select HAVE_ARM_SCU
+        select HAVE_CAN_FLEXCAN if CAN
         select HAVE_IMX_GPC
         select HAVE_IMX_MMDC
         select HAVE_IMX_SRC
         select HAVE_SMP
+        select MFD_ANATOP
         select PINCTRL
         select PINCTRL_IMX6Q
         select USE_OF
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index ff29421414f2..07f7c226e4cf 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_MACH_QONG) += mach-qong.o
 obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
 obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
 obj-$(CONFIG_MACH_BUG) += mach-bug.o
+obj-$(CONFIG_MACH_IMX31_DT) += imx31-dt.o
 
 # i.MX35 based machines
 obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index c9a06d800f8e..f87a48fc74e1 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -20,6 +20,7 @@
 #include <linux/clkdev.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/of.h>
 
 #include <mach/hardware.h>
 #include <mach/mx31.h>
@@ -179,3 +180,21 @@ int __init mx31_clocks_init(unsigned long fref)
 
         return 0;
 }
+
+#ifdef CONFIG_OF
+int __init mx31_clocks_init_dt(void)
+{
+        struct device_node *np;
+        u32 fref = 26000000; /* default */
+
+        for_each_compatible_node(np, NULL, "fixed-clock") {
+                if (!of_device_is_compatible(np, "fsl,imx-osc26m"))
+                        continue;
+
+                if (!of_property_read_u32(np, "clock-frequency", &fref))
+                        break;
+        }
+
+        return mx31_clocks_init(fref);
+}
+#endif
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index e1a17ac7b3b4..ea89520b6e22 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -147,12 +147,12 @@ enum mx6q_clks {
         esai, gpt_ipg, gpt_ipg_per, gpu2d_core, gpu3d_core, hdmi_iahb,
         hdmi_isfr, i2c1, i2c2, i2c3, iim, enfc, ipu1, ipu1_di0, ipu1_di1, ipu2,
         ipu2_di0, ldb_di0, ldb_di1, ipu2_di1, hsi_tx, mlb, mmdc_ch0_axi,
-        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4,
+        mmdc_ch1_axi, ocram, openvg_axi, pcie_axi, pwm1, pwm2, pwm3, pwm4, per1_bch,
         gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
         ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
         usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
         pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
-        ssi2_ipg, ssi3_ipg, rom,
+        ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2,
         clk_max
 };
 
@@ -198,6 +198,9 @@ int __init mx6q_clocks_init(void)
         clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,       "pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);
         clk[pll8_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,      "pll8_enet",    "osc", base + 0xe0, 0x182000, 0x3);
 
+        clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
+        clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
+
         /*                                name              parent_name        reg       idx */
         clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
         clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
@@ -318,7 +321,7 @@ int __init mx6q_clocks_init(void)
         clk[ahb]               = imx_clk_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
 
         /*                                name             parent_name          reg         shift */
-        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "ahb",               base + 0x68, 4);
+        clk[apbh_dma]     = imx_clk_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
         clk[asrc]         = imx_clk_gate2("asrc",          "asrc_podf",         base + 0x68, 6);
         clk[can1_ipg]     = imx_clk_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
         clk[can1_serial]  = imx_clk_gate2("can1_serial",   "can_root",          base + 0x68, 16);
@@ -357,6 +360,7 @@ int __init mx6q_clocks_init(void)
         clk[ocram]        = imx_clk_gate2("ocram",         "ahb",               base + 0x74, 28);
         clk[openvg_axi]   = imx_clk_gate2("openvg_axi",    "axi",               base + 0x74, 30);
         clk[pcie_axi]     = imx_clk_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
+        clk[per1_bch]     = imx_clk_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
         clk[pwm1]         = imx_clk_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
         clk[pwm2]         = imx_clk_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
         clk[pwm3]         = imx_clk_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
@@ -388,12 +392,21 @@ int __init mx6q_clocks_init(void)
                         pr_err("i.MX6q clk %d: register failed with %ld\n",
                                 i, PTR_ERR(clk[i]));
 
-        clk_register_clkdev(clk[mmdc_ch0_axi], NULL, "mmdc_ch0_axi");
-        clk_register_clkdev(clk[mmdc_ch1_axi], NULL, "mmdc_ch1_axi");
         clk_register_clkdev(clk[gpt_ipg], "ipg", "imx-gpt.0");
         clk_register_clkdev(clk[gpt_ipg_per], "per", "imx-gpt.0");
         clk_register_clkdev(clk[twd], NULL, "smp_twd");
-        clk_register_clkdev(clk[usboh3], NULL, "usboh3");
+        clk_register_clkdev(clk[apbh_dma], NULL, "110000.dma-apbh");
+        clk_register_clkdev(clk[per1_bch], "per1_bch", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_bch_apb], "gpmi_bch_apb", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_bch], "gpmi_bch", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_apb], "gpmi_apb", "112000.gpmi-nand");
+        clk_register_clkdev(clk[gpmi_io], "gpmi_io", "112000.gpmi-nand");
+        clk_register_clkdev(clk[usboh3], NULL, "2184000.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184200.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184400.usb");
+        clk_register_clkdev(clk[usboh3], NULL, "2184600.usb");
+        clk_register_clkdev(clk[usbphy1], NULL, "20c9000.usbphy");
+        clk_register_clkdev(clk[usbphy2], NULL, "20ca000.usbphy");
         clk_register_clkdev(clk[uart_serial], "per", "2020000.serial");
         clk_register_clkdev(clk[uart_ipg], "ipg", "2020000.serial");
         clk_register_clkdev(clk[uart_serial], "per", "21e8000.serial");
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 2628e0c474dc..93ece55f75df 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -14,7 +14,7 @@ extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
         imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
-#define imx21_add_imx2_wdt(pdata)       \
+#define imx21_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx21_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx21_imx_fb_data;
@@ -50,7 +50,7 @@ extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
         imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
-#define imx21_add_mxc_w1(pdata) \
+#define imx21_add_mxc_w1()      \
         imx_add_mxc_w1(&imx21_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx21_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index efa0761c508d..f8e03dd1f116 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -24,11 +24,11 @@ extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
 
 extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
-#define imx25_add_imxdi_rtc(pdata)      \
+#define imx25_add_imxdi_rtc()   \
         imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
 
 extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
-#define imx25_add_imx2_wdt(pdata)       \
+#define imx25_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx25_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx25_imx_fb_data;
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 28537a5d9048..436c5720fe6a 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -18,7 +18,7 @@ extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
-#define imx27_add_imx2_wdt(pdata)       \
+#define imx27_add_imx2_wdt()    \
         imx_add_imx2_wdt(&imx27_imx2_wdt_data)
 
 extern const struct imx_imx_fb_data imx27_imx_fb_data;
@@ -50,7 +50,7 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
 extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
 #define imx27_add_mx2_camera(pdata)     \
         imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
-#define imx27_add_mx2_emmaprp(pdata)    \
+#define imx27_add_mx2_emmaprp() \
         imx_add_mx2_emmaprp(&imx27_mx2_camera_data)
 
 extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
@@ -69,7 +69,7 @@ extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
         imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
-#define imx27_add_mxc_w1(pdata) \
+#define imx27_add_mxc_w1()      \
         imx_add_mxc_w1(&imx27_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx27_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
index 488e241a6db6..13f533d0aa5c 100644
--- a/arch/arm/mach-imx/devices-imx31.h
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -14,7 +14,7 @@ extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
         imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
 
 extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
-#define imx31_add_imx2_wdt(pdata)       \
+#define imx31_add_imx2_wdt()       \
         imx_add_imx2_wdt(&imx31_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
@@ -65,11 +65,11 @@ extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
         imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
 
 extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
-#define imx31_add_mxc_rtc(pdata)        \
+#define imx31_add_mxc_rtc()     \
         imx_add_mxc_rtc(&imx31_mxc_rtc_data)
 
 extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
-#define imx31_add_mxc_w1(pdata) \
+#define imx31_add_mxc_w1()      \
         imx_add_mxc_w1(&imx31_mxc_w1_data)
 
 extern const struct imx_spi_imx_data imx31_cspi_data[];
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
index 7b99ef0bb501..4815be1ee675 100644
--- a/arch/arm/mach-imx/devices-imx35.h
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -24,7 +24,7 @@ extern const struct imx_flexcan_data imx35_flexcan_data[];
 #define imx35_add_flexcan1(pdata)       imx35_add_flexcan(1, pdata)
 
 extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
-#define imx35_add_imx2_wdt(pdata)       \
+#define imx35_add_imx2_wdt()       \
         imx_add_imx2_wdt(&imx35_imx2_wdt_data)
 
 extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
@@ -68,8 +68,12 @@ extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
 #define imx35_add_mxc_nand(pdata)       \
         imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
 
+extern const struct imx_mxc_rtc_data imx35_mxc_rtc_data;
+#define imx35_add_mxc_rtc()     \
+        imx_add_mxc_rtc(&imx35_mxc_rtc_data)
+
 extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
-#define imx35_add_mxc_w1(pdata) \
+#define imx35_add_mxc_w1()      \
         imx_add_mxc_w1(&imx35_mxc_w1_data)
 
 extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
diff --git a/arch/arm/mach-imx/devices-imx51.h b/arch/arm/mach-imx/devices-imx51.h
index af488bc0e225..9f1718725195 100644
--- a/arch/arm/mach-imx/devices-imx51.h
+++ b/arch/arm/mach-imx/devices-imx51.h
@@ -55,7 +55,7 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[];
         imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
 
 extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
-#define imx51_add_imx2_wdt(id, pdata)   \
+#define imx51_add_imx2_wdt(id)  \
         imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
 
 extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
diff --git a/arch/arm/mach-imx/devices-imx53.h b/arch/arm/mach-imx/devices-imx53.h
index 6e1e5d1f8c3a..77e0db96c448 100644
--- a/arch/arm/mach-imx/devices-imx53.h
+++ b/arch/arm/mach-imx/devices-imx53.h
@@ -30,7 +30,7 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
         imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
 
 extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
-#define imx53_add_imx2_wdt(id, pdata)   \
+#define imx53_add_imx2_wdt(id)  \
         imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
 
 extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
diff --git a/arch/arm/mach-imx/ehci-imx25.c b/arch/arm/mach-imx/ehci-imx25.c
index 865daf0b09e9..05bb41d99728 100644
--- a/arch/arm/mach-imx/ehci-imx25.c
+++ b/arch/arm/mach-imx/ehci-imx25.c
@@ -24,14 +24,18 @@
 #define MX25_OTG_SIC_SHIFT      29
 #define MX25_OTG_SIC_MASK       (0x3 << MX25_OTG_SIC_SHIFT)
 #define MX25_OTG_PM_BIT         (1 << 24)
+#define MX25_OTG_PP_BIT         (1 << 11)
+#define MX25_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX25_H1_SIC_SHIFT       21
 #define MX25_H1_SIC_MASK        (0x3 << MX25_H1_SIC_SHIFT)
+#define MX25_H1_PP_BIT          (1 << 18)
 #define MX25_H1_PM_BIT          (1 << 8)
 #define MX25_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX25_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX25_H1_TLL_BIT         (1 << 5)
 #define MX25_H1_USBTE_BIT       (1 << 4)
+#define MX25_H1_OCPOL_BIT       (1 << 2)
 
 int mx25_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -41,21 +45,35 @@ int mx25_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT);
+                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
+                        MX25_OTG_OCPOL_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_OTG_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX25_OTG_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX25_OTG_OCPOL_BIT;
+
                 break;
         case 1: /* H1 port */
-                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_TLL_BIT |
-                        MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
+                v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
+                        MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT | MX25_H1_USBTE_BIT |
+                        MX25_H1_IPPUE_DOWN_BIT | MX25_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX25_H1_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX25_H1_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX25_H1_OCPOL_BIT;
+
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX25_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
index 001ec3971f5d..73574c30cf50 100644
--- a/arch/arm/mach-imx/ehci-imx35.c
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -24,14 +24,18 @@
 #define MX35_OTG_SIC_SHIFT      29
 #define MX35_OTG_SIC_MASK       (0x3 << MX35_OTG_SIC_SHIFT)
 #define MX35_OTG_PM_BIT         (1 << 24)
+#define MX35_OTG_PP_BIT         (1 << 11)
+#define MX35_OTG_OCPOL_BIT      (1 << 3)
 
 #define MX35_H1_SIC_SHIFT       21
 #define MX35_H1_SIC_MASK        (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PP_BIT          (1 << 18)
 #define MX35_H1_PM_BIT          (1 << 8)
 #define MX35_H1_IPPUE_UP_BIT    (1 << 7)
 #define MX35_H1_IPPUE_DOWN_BIT  (1 << 6)
 #define MX35_H1_TLL_BIT         (1 << 5)
 #define MX35_H1_USBTE_BIT       (1 << 4)
+#define MX35_H1_OCPOL_BIT       (1 << 2)
 
 int mx35_initialize_usb_hw(int port, unsigned int flags)
 {
@@ -41,21 +45,35 @@ int mx35_initialize_usb_hw(int port, unsigned int flags)
 
         switch (port) {
         case 0: /* OTG port */
-                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
+                        MX35_OTG_OCPOL_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_OTG_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX35_OTG_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX35_OTG_OCPOL_BIT;
+
                 break;
         case 1: /* H1 port */
-                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
-                        MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+                v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
+                        MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT | MX35_H1_USBTE_BIT |
+                        MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
                 v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
 
                 if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
                         v |= MX35_H1_PM_BIT;
 
+                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                        v |= MX35_H1_PP_BIT;
+
+                if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
+                        v |= MX35_H1_OCPOL_BIT;
+
                 if (!(flags & MXC_EHCI_TTL_ENABLED))
                         v |= MX35_H1_TLL_BIT;
 
diff --git a/arch/arm/mach-imx/ehci-imx5.c b/arch/arm/mach-imx/ehci-imx5.c
index c17fa131728b..a6a4afb0ad62 100644
--- a/arch/arm/mach-imx/ehci-imx5.c
+++ b/arch/arm/mach-imx/ehci-imx5.c
@@ -28,11 +28,14 @@
 #define MXC_OTG_UCTRL_OPM_BIT           (1 << 24)       /* OTG power mask */
 #define MXC_H1_UCTRL_H1UIE_BIT          (1 << 12)       /* Host1 ULPI interrupt enable */
 #define MXC_H1_UCTRL_H1WIE_BIT          (1 << 11)       /* HOST1 wakeup intr enable */
-#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)               /* HOST1 power mask */
+#define MXC_H1_UCTRL_H1PM_BIT           (1 <<  8)       /* HOST1 power mask */
 
 /* USB_PHY_CTRL_FUNC */
+#define MXC_OTG_PHYCTRL_OC_POL_BIT      (1 << 9)        /* OTG Polarity of Overcurrent */
 #define MXC_OTG_PHYCTRL_OC_DIS_BIT      (1 << 8)        /* OTG Disable Overcurrent Event */
+#define MXC_H1_OC_POL_BIT               (1 << 6)        /* UH1 Polarity of Overcurrent */
 #define MXC_H1_OC_DIS_BIT               (1 << 5)        /* UH1 Disable Overcurrent Event */
+#define MXC_OTG_PHYCTRL_PWR_POL_BIT     (1 << 3)        /* OTG Power Pin Polarity */
 
 /* USBH2CTRL */
 #define MXC_H2_UCTRL_H2UIE_BIT          (1 << 8)
@@ -80,13 +83,21 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 if (flags & MXC_EHCI_INTERNAL_PHY) {
                         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
+                        if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+                                v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
+                        else
+                                v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
                         if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
-                                /* OC/USBPWR is not used */
-                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
-                        } else {
                                 /* OC/USBPWR is used */
                                 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
+                        } else {
+                                /* OC/USBPWR is not used */
+                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
                         }
+                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
+                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
+                        else
+                                v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
                         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                         v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -95,9 +106,9 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                         else
                                 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
                         if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                                v |= MXC_OTG_UCTRL_OPM_BIT;
-                        else
                                 v &= ~MXC_OTG_UCTRL_OPM_BIT;
+                        else
+                                v |= MXC_OTG_UCTRL_OPM_BIT;
                         __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
                 }
                 break;
@@ -113,12 +124,16 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 }
 
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
+                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask unused*/
                 else
                         v |= MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
                 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
 
                 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
+                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
+                        v |= MXC_H1_OC_POL_BIT;
+                else
+                        v &= ~MXC_H1_OC_POL_BIT;
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                         v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
                 else
@@ -142,7 +157,7 @@ int mx51_initialize_usb_hw(int port, unsigned int flags)
                 }
 
                 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
-                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
+                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask unused*/
                 else
                         v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
                 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index eee0cc8d92a4..52efe4d5149b 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -75,7 +75,7 @@ static struct sys_timer imx27_timer = {
         .init = imx27_timer_init,
 };
 
-static const char *imx27_dt_board_compat[] __initdata = {
+static const char * const imx27_dt_board_compat[] __initconst = {
         "fsl,imx27",
         NULL
 };
diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c
new file mode 100644
index 000000000000..a68ba207b2b7
--- /dev/null
+++ b/arch/arm/mach-imx/imx31-dt.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2012 Sascha Hauer, Pengutronix
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <mach/common.h>
+#include <mach/mx31.h>
+
+static const struct of_dev_auxdata imx31_auxdata_lookup[] __initconst = {
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART1_BASE_ADDR,
+                        "imx21-uart.0", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART2_BASE_ADDR,
+                        "imx21-uart.1", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART3_BASE_ADDR,
+                        "imx21-uart.2", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART4_BASE_ADDR,
+                        "imx21-uart.3", NULL),
+        OF_DEV_AUXDATA("fsl,imx31-uart", MX31_UART5_BASE_ADDR,
+                        "imx21-uart.4", NULL),
+        { /* sentinel */ }
+};
+
+static void __init imx31_dt_init(void)
+{
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             imx31_auxdata_lookup, NULL);
+}
+
+static void __init imx31_timer_init(void)
+{
+        mx31_clocks_init_dt();
+}
+
+static struct sys_timer imx31_timer = {
+        .init = imx31_timer_init,
+};
+
+static const char *imx31_dt_board_compat[] __initdata = {
+        "fsl,imx31",
+        NULL
+};
+
+DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)")
+        .map_io         = mx31_map_io,
+        .init_early     = imx31_init_early,
+        .init_irq       = mx31_init_irq,
+        .handle_irq     = imx31_handle_irq,
+        .timer          = &imx31_timer,
+        .init_machine   = imx31_dt_init,
+        .dt_compat      = imx31_dt_board_compat,
+        .restart        = mxc_restart,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index d085aea08709..9a3b06e688c5 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -233,18 +233,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx27_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx27_otg_mode);
 
@@ -266,8 +266,8 @@ static void __init eukrea_cpuimx27_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 
 #if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
         /* SDHC2 can be used for Wifi */
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 6450303f1a7a..1634e54ffed5 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -141,18 +141,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx35_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx35_otg_mode);
 
@@ -167,7 +167,7 @@ static void __init eukrea_cpuimx35_init(void)
                         ARRAY_SIZE(eukrea_cpuimx35_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 1e09de50cbcd..e78b40b41462 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -217,18 +217,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .portsc = MXC_EHCI_MODE_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx51sd_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx51sd_otg_mode);
 
@@ -292,7 +292,7 @@ static void __init eukrea_cpuimx51sd_init(void)
 
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 
         gpio_request(ETH_RST, "eth_rst");
         gpio_set_value(ETH_RST, 1);
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index d1e04e676e33..017bbb70ea41 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -109,18 +109,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .workaround     = FLS_USB2_WORKAROUND_ENGCM09152,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init eukrea_cpuimx25_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", eukrea_cpuimx25_otg_mode);
 
@@ -134,9 +134,9 @@ static void __init eukrea_cpuimx25_init(void)
 
         imx25_add_imx_uart0(&uart_pdata);
         imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
-        imx25_add_imxdi_rtc(NULL);
+        imx25_add_imxdi_rtc();
         imx25_add_fec(&mx25_fec_pdata);
-        imx25_add_imx2_wdt(NULL);
+        imx25_add_imx2_wdt();
 
         i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
                                 ARRAY_SIZE(eukrea_cpuimx25_i2c_devices));
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index c9d350c5dcc8..7381387a8905 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -57,7 +57,7 @@ static void __init mx27ipcam_init(void)
 
         imx27_add_imx_uart0(NULL);
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt(NULL);
+        imx27_add_imx2_wdt();
 }
 
 static void __init mx27ipcam_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b47e98b7d539..140f55010630 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -24,6 +24,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <linux/mfd/anatop.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -113,6 +114,45 @@ static void __init imx6q_sabrelite_init(void)
         imx6q_sabrelite_cko1_setup();
 }
 
+static void __init imx6q_usb_init(void)
+{
+        struct device_node *np;
+        struct platform_device *pdev = NULL;
+        struct anatop *adata = NULL;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
+        if (np)
+                pdev = of_find_device_by_node(np);
+        if (pdev)
+                adata = platform_get_drvdata(pdev);
+        if (!adata) {
+                if (np)
+                        of_node_put(np);
+                return;
+        }
+
+#define HW_ANADIG_USB1_CHRG_DETECT              0x000001b0
+#define HW_ANADIG_USB2_CHRG_DETECT              0x00000210
+
+#define BM_ANADIG_USB_CHRG_DETECT_EN_B          0x00100000
+#define BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B    0x00080000
+
+        /*
+         * The external charger detector needs to be disabled,
+         * or the signal at DP will be poor
+         */
+        anatop_write_reg(adata, HW_ANADIG_USB1_CHRG_DETECT,
+                        BM_ANADIG_USB_CHRG_DETECT_EN_B
+                        | BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                        ~0);
+        anatop_write_reg(adata, HW_ANADIG_USB2_CHRG_DETECT,
+                        BM_ANADIG_USB_CHRG_DETECT_EN_B |
+                        BM_ANADIG_USB_CHRG_DETECT_CHK_CHRG_B,
+                        ~0);
+
+        of_node_put(np);
+}
+
 static void __init imx6q_init_machine(void)
 {
         /*
@@ -127,6 +167,7 @@ static void __init imx6q_init_machine(void)
         of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
 
         imx6q_pm_init();
+        imx6q_usb_init();
 }
 
 static void __init imx6q_map_io(void)
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index f26734298aa6..ce247fd1269a 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -237,9 +237,9 @@ static void __init mx25pdk_init(void)
         imx25_add_fsl_usb2_udc(&otg_device_pdata);
         imx25_add_mxc_ehci_hs(&usbh2_pdata);
         imx25_add_mxc_nand(&mx25pdk_nand_board_info);
-        imx25_add_imxdi_rtc(NULL);
+        imx25_add_imxdi_rtc();
         imx25_add_imx_fb(&mx25pdk_fb_pdata);
-        imx25_add_imx2_wdt(NULL);
+        imx25_add_imx2_wdt();
 
         mx25pdk_fec_reset();
         imx25_add_fec(&mx25_fec_pdata);
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index c6d385c52257..ce9a5c26290c 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -241,18 +241,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx27_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx27_3ds_otg_mode);
 
@@ -480,7 +480,7 @@ static void __init mx27pdk_init(void)
         imx27_add_fec(NULL);
         imx27_add_imx_keypad(&mx27_3ds_keymap_data);
         imx27_add_mxc_mmc(0, &sdhc1_pdata);
-        imx27_add_imx2_wdt(NULL);
+        imx27_add_imx2_wdt();
         otg_phy_init();
 
         if (otg_mode_host) {
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 0228d2e07fe0..7936bb32264d 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -310,7 +310,7 @@ static void __init mx27ads_board_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_mxc_w1(NULL);
+        imx27_add_mxc_w1();
 }
 
 static void __init mx27ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 4eafdf275ea2..928e1dcbc6a7 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -671,18 +671,18 @@ static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx31_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx31_3ds_otg_mode);
 
@@ -739,7 +739,7 @@ static void __init mx31_3ds_init(void)
         if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
                 printk(KERN_WARNING "Init of the debug board failed, all "
                                     "devices on the debug board are unusable.\n");
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
         imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
         imx31_add_mxc_mmc(0, &sdhc1_pdata);
 
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index 016791f038b0..63e84e67b990 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -544,7 +544,7 @@ static void __init mx31moboard_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
         gpio_led_register_device(-1, &mx31moboard_led_pdata);
 
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
 
         imx31_add_imx_uart0(&uart0_pdata);
         imx31_add_imx_uart4(&uart4_pdata);
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 28aa19476de7..69018e5c52de 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -540,18 +540,18 @@ static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
         .portsc         = MXC_EHCI_MODE_SERIAL,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init mx35_3ds_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", mx35_3ds_otg_mode);
 
@@ -571,7 +571,8 @@ static void __init mx35_3ds_init(void)
         mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
+        imx35_add_mxc_rtc();
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx35_add_imx_uart0(&uart_pdata);
diff --git a/arch/arm/mach-imx/mach-mx51_3ds.c b/arch/arm/mach-imx/mach-mx51_3ds.c
index 3c5b163923f6..2edb563b968d 100644
--- a/arch/arm/mach-imx/mach-mx51_3ds.c
+++ b/arch/arm/mach-imx/mach-mx51_3ds.c
@@ -154,7 +154,7 @@ static void __init mx51_3ds_init(void)
 
         imx51_add_sdhci_esdhc_imx(0, NULL);
         imx51_add_imx_keypad(&mx51_3ds_map_data);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 }
 
 static void __init mx51_3ds_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index dde397014d4b..7b31cbde8775 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -307,18 +307,18 @@ static const struct mxc_usbh_platform_data usbh1_config __initconst = {
         .portsc = MXC_EHCI_MODE_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init babbage_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", babbage_otg_mode);
 
@@ -411,7 +411,7 @@ static void __init mx51_babbage_init(void)
         spi_register_board_info(mx51_babbage_spi_board_info,
                 ARRAY_SIZE(mx51_babbage_spi_board_info));
         imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
-        imx51_add_imx2_wdt(0, NULL);
+        imx51_add_imx2_wdt(0);
 }
 
 static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 05641980dc5e..4a7593a953e2 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -243,7 +243,7 @@ static void __init mx53_ard_board_init(void)
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
         imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
         imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
         imx_add_gpio_keys(&ard_button_data);
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
index 5a72188b9cdb..a1060b26fb23 100644
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ b/arch/arm/mach-imx/mach-mx53_evk.c
@@ -154,7 +154,7 @@ static void __init mx53_evk_board_init(void)
         spi_register_board_info(mx53_evk_spi_board_info,
                 ARRAY_SIZE(mx53_evk_spi_board_info));
         imx53_add_ecspi(0, &mx53_evk_spi_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         gpio_led_register_device(-1, &mx53evk_leds_data);
 }
 
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
index 37f67cac15a4..388c415d6b62 100644
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ b/arch/arm/mach-imx/mach-mx53_loco.c
@@ -283,7 +283,7 @@ static void __init mx53_loco_board_init(void)
         imx53_add_imx_uart(0, NULL);
         mx53_loco_fec_reset();
         imx53_add_fec(&mx53_loco_fec_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
 
         ret = gpio_request_one(LOCO_ACCEL_EN, GPIOF_OUT_INIT_HIGH, "accel_en");
         if (ret)
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
index 8e972c5c3e13..f297df7ccb39 100644
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ b/arch/arm/mach-imx/mach-mx53_smd.c
@@ -138,7 +138,7 @@ static void __init mx53_smd_board_init(void)
         mx53_smd_init_uart();
         mx53_smd_fec_reset();
         imx53_add_fec(&mx53_smd_fec_data);
-        imx53_add_imx2_wdt(0, NULL);
+        imx53_add_imx2_wdt(0);
         imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
         imx53_add_sdhci_esdhc_imx(0, NULL);
         imx53_add_sdhci_esdhc_imx(1, NULL);
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 541152e450c4..d37ed25003b2 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -298,18 +298,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pca100_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pca100_otg_mode);
 
@@ -408,8 +408,8 @@ static void __init pca100_init(void)
         imx27_add_imx_fb(&pca100_fb_data);
 
         imx27_add_fec(NULL);
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 }
 
 static void __init pca100_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index 0a40004154f2..cd48712a6f50 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -557,18 +557,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_ULPI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pcm037_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pcm037_otg_mode);
 
@@ -619,13 +619,13 @@ static void __init pcm037_init(void)
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
 
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
         imx31_add_imx_uart0(&uart_pdata);
         /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
         imx31_add_imx_uart1(&uart_pdata);
         imx31_add_imx_uart2(&uart_pdata);
 
-        imx31_add_mxc_w1(NULL);
+        imx31_add_mxc_w1();
 
         /* LAN9217 IRQ pin */
         ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 2f3debe2a113..3fbb89d74fcc 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -332,8 +332,8 @@ static void __init pcm038_init(void)
 
         imx27_add_fec(NULL);
         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-        imx27_add_imx2_wdt(NULL);
-        imx27_add_mxc_w1(NULL);
+        imx27_add_imx2_wdt();
+        imx27_add_mxc_w1();
 
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
         pcm970_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 73585f55cca0..1f20f222375e 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -330,18 +330,18 @@ static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
         .phy_mode       = FSL_USB2_PHY_UTMI,
 };
 
-static int otg_mode_host;
+static bool otg_mode_host __initdata;
 
 static int __init pcm043_otg_mode(char *options)
 {
         if (!strcmp(options, "host"))
-                otg_mode_host = 1;
+                otg_mode_host = true;
         else if (!strcmp(options, "device"))
-                otg_mode_host = 0;
+                otg_mode_host = false;
         else
                 pr_info("otg_mode neither \"host\" nor \"device\". "
                         "Defaulting to device\n");
-        return 0;
+        return 1;
 }
 __setup("otg_mode=", pcm043_otg_mode);
 
@@ -363,7 +363,7 @@ static void __init pcm043_init(void)
 
         imx35_add_fec(NULL);
         platform_add_devices(devices, ARRAY_SIZE(devices));
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
 
         imx35_add_imx_uart0(&uart_pdata);
         imx35_add_mxc_nand(&pcm037_nand_board_info);
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 260621055b6b..a13087b11a6e 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -252,7 +252,7 @@ static void __init qong_init(void)
         mxc_init_imx_uart();
         qong_init_nor_mtd();
         qong_init_fpga();
-        imx31_add_imx2_wdt(NULL);
+        imx31_add_imx2_wdt();
 }
 
 static void __init qong_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
index add8c69c6c1a..b26209d4bcef 100644
--- a/arch/arm/mach-imx/mach-vpr200.c
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -272,7 +272,7 @@ static void __init vpr200_board_init(void)
         mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
 
         imx35_add_fec(NULL);
-        imx35_add_imx2_wdt(NULL);
+        imx35_add_imx2_wdt();
         imx_add_gpio_keys(&vpr200_gpio_keys_data);
 
         platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index bf0fb87946ba..fa60ef6ac7ff 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -191,6 +191,6 @@ void __init mx31lite_db_init(void)
         imx31_add_mxc_mmc(0, &mmc_pdata);
         imx31_add_spi_imx0(&spi0_pdata);
         gpio_led_register_device(-1, &litekit_led_platform_data);
-        imx31_add_imx2_wdt(NULL);
-        imx31_add_mxc_rtc(NULL);
+        imx31_add_imx2_wdt();
+        imx31_add_mxc_rtc();
 }
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index e0b3eee83834..000000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if ARCH_LPC32XX
-
-menu "Individual UART enable selections"
-
-config ARCH_LPC32XX_UART3_SELECT
-        bool "Add support for standard UART3"
-        help
-         Adds support for standard UART 3 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART4_SELECT
-        bool "Add support for standard UART4"
-        help
-         Adds support for standard UART 4 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART5_SELECT
-        bool "Add support for standard UART5"
-        default y
-        help
-         Adds support for standard UART 5 when the 8250 serial support
-         is enabled.
-
-config ARCH_LPC32XX_UART6_SELECT
-        bool "Add support for standard UART6"
-        help
-         Adds support for standard UART 6 when the 8250 serial support
-         is enabled.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-lpc32xx/Makefile.boot b/arch/arm/mach-lpc32xx/Makefile.boot
index 2cfe0ee635c5..697323b5f92d 100644
--- a/arch/arm/mach-lpc32xx/Makefile.boot
+++ b/arch/arm/mach-lpc32xx/Makefile.boot
@@ -2,3 +2,4 @@
 params_phys-y   := 0x80000100
 initrd_phys-y   := 0x82000000
 
+dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f6a3ffec1f4b..f48c2e961b84 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -607,6 +607,19 @@ static struct clk clk_dma = {
         .get_rate       = local_return_parent_rate,
 };
 
+static struct clk clk_pwm = {
+        .parent         = &clk_pclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_PWM_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN |
+                          LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK |
+                          LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(1) |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK |
+                          LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(1),
+        .get_rate       = local_return_parent_rate,
+};
+
 static struct clk clk_uart3 = {
         .parent         = &clk_pclk,
         .enable         = local_onoff_enable,
@@ -691,10 +704,21 @@ static struct clk clk_nand = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
         .get_rate       = local_return_parent_rate,
 };
 
+static struct clk clk_nand_mlc = {
+        .parent         = &clk_hclk,
+        .enable         = local_onoff_enable,
+        .enable_reg     = LPC32XX_CLKPWR_NAND_CLK_CTRL,
+        .enable_mask    = LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN |
+                          LPC32XX_CLKPWR_NANDCLK_DMA_INT |
+                          LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC,
+        .get_rate       = local_return_parent_rate,
+};
+
 static struct clk clk_i2s0 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
@@ -707,7 +731,8 @@ static struct clk clk_i2s1 = {
         .parent         = &clk_hclk,
         .enable         = local_onoff_enable,
         .enable_reg     = LPC32XX_CLKPWR_I2S_CLK_CTRL,
-        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN,
+        .enable_mask    = LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN |
+                          LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA,
         .get_rate       = local_return_parent_rate,
 };
 
@@ -727,14 +752,77 @@ static struct clk clk_rtc = {
         .get_rate       = local_return_parent_rate,
 };
 
+static int local_usb_enable(struct clk *clk, int enable)
+{
+        u32 tmp;
+
+        if (enable) {
+                /* Set up I2C pull levels */
+                tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
+                tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE;
+                __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
+        }
+
+        return local_onoff_enable(clk, enable);
+}
+
 static struct clk clk_usbd = {
         .parent         = &clk_usbpll,
-        .enable         = local_onoff_enable,
+        .enable         = local_usb_enable,
         .enable_reg     = LPC32XX_CLKPWR_USB_CTRL,
         .enable_mask    = LPC32XX_CLKPWR_USBCTRL_HCLK_EN,
         .get_rate       = local_return_parent_rate,
 };
 
+#define OTG_ALWAYS_MASK         (LPC32XX_USB_OTG_OTG_CLOCK_ON | \
+                                 LPC32XX_USB_OTG_I2C_CLOCK_ON)
+
+static int local_usb_otg_enable(struct clk *clk, int enable)
+{
+        int to = 1000;
+
+        if (enable) {
+                __raw_writel(clk->enable_mask, clk->enable_reg);
+
+                while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
+                        clk->enable_mask) != clk->enable_mask) && (to > 0))
+                        to--;
+        } else {
+                __raw_writel(OTG_ALWAYS_MASK, clk->enable_reg);
+
+                while (((__raw_readl(LPC32XX_USB_OTG_CLK_STAT) &
+                        OTG_ALWAYS_MASK) != OTG_ALWAYS_MASK) && (to > 0))
+                        to--;
+        }
+
+        if (to)
+                return 0;
+        else
+                return -1;
+}
+
+static struct clk clk_usb_otg_dev = {
+        .parent         = &clk_usbpll,
+        .enable         = local_usb_otg_enable,
+        .enable_reg     = LPC32XX_USB_OTG_CLK_CTRL,
+        .enable_mask    = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
+                          LPC32XX_USB_OTG_OTG_CLOCK_ON |
+                          LPC32XX_USB_OTG_DEV_CLOCK_ON |
+                          LPC32XX_USB_OTG_I2C_CLOCK_ON,
+        .get_rate       = local_return_parent_rate,
+};
+
+static struct clk clk_usb_otg_host = {
+        .parent         = &clk_usbpll,
+        .enable         = local_usb_otg_enable,
+        .enable_reg     = LPC32XX_USB_OTG_CLK_CTRL,
+        .enable_mask    = LPC32XX_USB_OTG_AHB_M_CLOCK_ON |
+                          LPC32XX_USB_OTG_OTG_CLOCK_ON |
+                          LPC32XX_USB_OTG_HOST_CLOCK_ON |
+                          LPC32XX_USB_OTG_I2C_CLOCK_ON,
+        .get_rate       = local_return_parent_rate,
+};
+
 static int tsc_onoff_enable(struct clk *clk, int enable)
 {
         u32 tmp;
@@ -800,11 +888,17 @@ static int mmc_onoff_enable(struct clk *clk, int enable)
         u32 tmp;
 
         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
-                ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+                ~(LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS |
+                  LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS);
 
         /* If rate is 0, disable clock */
         if (enable != 0)
-                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
+                tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_EN |
+                        LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN;
 
         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 
@@ -853,7 +947,7 @@ static unsigned long mmc_round_rate(struct clk *clk, unsigned long rate)
 
 static int mmc_set_rate(struct clk *clk, unsigned long rate)
 {
-        u32 oldclk, tmp;
+        u32 tmp;
         unsigned long prate, div, crate = mmc_round_rate(clk, rate);
 
         prate = clk->parent->get_rate(clk->parent);
@@ -861,16 +955,12 @@ static int mmc_set_rate(struct clk *clk, unsigned long rate)
         div = prate / crate;
 
         /* The MMC clock must be on when accessing an MMC register */
-        oldclk = __raw_readl(LPC32XX_CLKPWR_MS_CTRL);
-        __raw_writel(oldclk | LPC32XX_CLKPWR_MSCARD_SDCARD_EN,
-                LPC32XX_CLKPWR_MS_CTRL);
         tmp = __raw_readl(LPC32XX_CLKPWR_MS_CTRL) &
                 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
-        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div);
+        tmp |= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div) |
+                LPC32XX_CLKPWR_MSCARD_SDCARD_EN;
         __raw_writel(tmp, LPC32XX_CLKPWR_MS_CTRL);
 
-        __raw_writel(oldclk, LPC32XX_CLKPWR_MS_CTRL);
-
         return 0;
 }
 
@@ -1111,6 +1201,7 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT(NULL, "vfp9_ck", &clk_vfp9),
         CLKDEV_INIT("pl08xdmac", NULL, &clk_dma),
         CLKDEV_INIT("4003c000.watchdog", NULL, &clk_wdt),
+        CLKDEV_INIT("4005c000.pwm", NULL, &clk_pwm),
         CLKDEV_INIT(NULL, "uart3_ck", &clk_uart3),
         CLKDEV_INIT(NULL, "uart4_ck", &clk_uart4),
         CLKDEV_INIT(NULL, "uart5_ck", &clk_uart5),
@@ -1120,8 +1211,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("31020300.i2c", NULL, &clk_i2c2),
         CLKDEV_INIT("dev:ssp0", NULL, &clk_ssp0),
         CLKDEV_INIT("dev:ssp1", NULL, &clk_ssp1),
-        CLKDEV_INIT("lpc32xx_keys.0", NULL, &clk_kscan),
-        CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand),
+        CLKDEV_INIT("40050000.key", NULL, &clk_kscan),
+        CLKDEV_INIT("20020000.flash", NULL, &clk_nand),
+        CLKDEV_INIT("200a8000.flash", NULL, &clk_nand_mlc),
         CLKDEV_INIT("40048000.adc", NULL, &clk_adc),
         CLKDEV_INIT(NULL, "i2s0_ck", &clk_i2s0),
         CLKDEV_INIT(NULL, "i2s1_ck", &clk_i2s1),
@@ -1130,6 +1222,9 @@ static struct clk_lookup lookups[] = {
         CLKDEV_INIT("31060000.ethernet", NULL, &clk_net),
         CLKDEV_INIT("dev:clcd", NULL, &clk_lcd),
         CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd),
+        CLKDEV_INIT("31020000.ohci", "ck_usbd", &clk_usbd),
+        CLKDEV_INIT("31020000.usbd", "ck_usb_otg", &clk_usb_otg_dev),
+        CLKDEV_INIT("31020000.ohci", "ck_usb_otg", &clk_usb_otg_host),
         CLKDEV_INIT("lpc32xx_rtc", NULL, &clk_rtc),
 };
 
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 5c96057b6d78..a48dc2dec485 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -26,6 +26,7 @@
 #include <linux/io.h>
 
 #include <asm/mach/map.h>
+#include <asm/system_info.h>
 
 #include <mach/hardware.h>
 #include <mach/platform.h>
@@ -224,7 +225,7 @@ void lpc23xx_restart(char mode, const char *cmd)
                 ;
 }
 
-static int __init lpc32xx_display_uid(void)
+static int __init lpc32xx_check_uid(void)
 {
         u32 uid[4];
 
@@ -233,6 +234,11 @@ static int __init lpc32xx_display_uid(void)
         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
                 uid[3], uid[2], uid[1], uid[0]);
 
+        if (!system_serial_low && !system_serial_high) {
+                system_serial_low = uid[0];
+                system_serial_high = uid[1];
+        }
+
         return 1;
 }
-arch_initcall(lpc32xx_display_uid);
+arch_initcall(lpc32xx_check_uid);
diff --git a/arch/arm/mach-lpc32xx/include/mach/gpio.h b/arch/arm/mach-lpc32xx/include/mach/gpio.h
index 2ba6ca412bef..0052e7a76179 100644
--- a/arch/arm/mach-lpc32xx/include/mach/gpio.h
+++ b/arch/arm/mach-lpc32xx/include/mach/gpio.h
@@ -3,6 +3,4 @@
 
 #include "gpio-lpc32xx.h"
 
-#define ARCH_NR_GPIOS (LPC32XX_GPO_P3_GRP + LPC32XX_GPO_P3_MAX)
-
 #endif /* __MACH_GPIO_H */
diff --git a/arch/arm/mach-lpc32xx/include/mach/platform.h b/arch/arm/mach-lpc32xx/include/mach/platform.h
index c584f5bb164f..acc4aabf1c7b 100644
--- a/arch/arm/mach-lpc32xx/include/mach/platform.h
+++ b/arch/arm/mach-lpc32xx/include/mach/platform.h
@@ -694,4 +694,18 @@
 #define LPC32XX_GPIO_P2_MUX_CLR                 _GPREG(0x02C)
 #define LPC32XX_GPIO_P2_MUX_STATE               _GPREG(0x030)
 
+/*
+ * USB Otg Registers
+ */
+#define _OTGREG(x)                      io_p2v(LPC32XX_USB_OTG_BASE + (x))
+#define LPC32XX_USB_OTG_CLK_CTRL        _OTGREG(0xFF4)
+#define LPC32XX_USB_OTG_CLK_STAT        _OTGREG(0xFF8)
+
+/* USB OTG CLK CTRL bit defines */
+#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON  _BIT(4)
+#define LPC32XX_USB_OTG_OTG_CLOCK_ON    _BIT(3)
+#define LPC32XX_USB_OTG_I2C_CLOCK_ON    _BIT(2)
+#define LPC32XX_USB_OTG_DEV_CLOCK_ON    _BIT(1)
+#define LPC32XX_USB_OTG_HOST_CLOCK_ON   _BIT(0)
+
 #endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 540106cdb9ec..b07dcc90829d 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -30,12 +30,13 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
 #include <linux/amba/pl022.h>
+#include <linux/amba/pl08x.h>
+#include <linux/amba/mmci.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/clk.h>
-#include <linux/amba/pl08x.h>
 
 #include <asm/setup.h>
 #include <asm/mach-types.h>
@@ -50,9 +51,9 @@
 /*
  * Mapped GPIOLIB GPIOs
  */
-#define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
-#define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
-#define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define LCD_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
+#define BKL_POWER_GPIO          LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
+#define MMC_PWR_ENABLE_GPIO     LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 5)
 
 /*
  * AMBA LCD controller
@@ -158,24 +159,6 @@ static struct clcd_board lpc32xx_clcd_data = {
 /*
  * AMBA SSP (SPI)
  */
-static void phy3250_spi_cs_set(u32 control)
-{
-        gpio_set_value(SPI0_CS_GPIO, (int) control);
-}
-
-static struct pl022_config_chip spi0_chip_info = {
-        .com_mode               = INTERRUPT_TRANSFER,
-        .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
-        .hierarchy              = SSP_MASTER,
-        .slave_tx_disable       = 0,
-        .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
-        .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
-        .ctrl_len               = SSP_BITS_8,
-        .wait_state             = SSP_MWIRE_WAIT_ZERO,
-        .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
-        .cs_control             = phy3250_spi_cs_set,
-};
-
 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
         .bus_id                 = 0,
         .num_chipselect         = 1,
@@ -188,45 +171,56 @@ static struct pl022_ssp_controller lpc32xx_ssp1_data = {
         .enable_dma             = 0,
 };
 
-/* AT25 driver registration */
-static int __init phy3250_spi_board_register(void)
+static struct pl08x_channel_data pl08x_slave_channels[] = {
+        {
+                .bus_id = "nand-slc",
+                .min_signal = 1, /* SLC NAND Flash */
+                .max_signal = 1,
+                .periph_buses = PL08X_AHB1,
+        },
+        {
+                .bus_id = "nand-mlc",
+                .min_signal = 12, /* MLC NAND Flash */
+                .max_signal = 12,
+                .periph_buses = PL08X_AHB1,
+        },
+};
+
+static int pl08x_get_signal(const struct pl08x_channel_data *cd)
+{
+        return cd->min_signal;
+}
+
+static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
 {
-#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
-        static struct spi_board_info info[] = {
-                {
-                        .modalias = "spidev",
-                        .max_speed_hz = 5000000,
-                        .bus_num = 0,
-                        .chip_select = 0,
-                        .controller_data = &spi0_chip_info,
-                },
-        };
-
-#else
-        static struct spi_eeprom eeprom = {
-                .name = "at25256a",
-                .byte_len = 0x8000,
-                .page_size = 64,
-                .flags = EE_ADDR2,
-        };
-
-        static struct spi_board_info info[] = {
-                {
-                        .modalias = "at25",
-                        .max_speed_hz = 5000000,
-                        .bus_num = 0,
-                        .chip_select = 0,
-                        .mode = SPI_MODE_0,
-                        .platform_data = &eeprom,
-                        .controller_data = &spi0_chip_info,
-                },
-        };
-#endif
-        return spi_register_board_info(info, ARRAY_SIZE(info));
 }
-arch_initcall(phy3250_spi_board_register);
 
 static struct pl08x_platform_data pl08x_pd = {
+        .slave_channels = &pl08x_slave_channels[0],
+        .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
+        .get_signal = pl08x_get_signal,
+        .put_signal = pl08x_put_signal,
+        .lli_buses = PL08X_AHB1,
+        .mem_buses = PL08X_AHB1,
+};
+
+static int mmc_handle_ios(struct device *dev, struct mmc_ios *ios)
+{
+        /* Only on and off are supported */
+        if (ios->power_mode == MMC_POWER_OFF)
+                gpio_set_value(MMC_PWR_ENABLE_GPIO, 0);
+        else
+                gpio_set_value(MMC_PWR_ENABLE_GPIO, 1);
+        return 0;
+}
+
+static struct mmci_platform_data lpc32xx_mmci_data = {
+        .ocr_mask       = MMC_VDD_30_31 | MMC_VDD_31_32 |
+                          MMC_VDD_32_33 | MMC_VDD_33_34,
+        .ios_handler    = mmc_handle_ios,
+        .dma_filter     = NULL,
+        /* No DMA for now since AMBA PL080 dmaengine driver only does scatter
+         * gather, and the MMCI driver doesn't do it this way */
 };
 
 static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
@@ -234,6 +228,8 @@ static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
         OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
         OF_DEV_AUXDATA("arm,pl110", 0x31040000, "dev:clcd", &lpc32xx_clcd_data),
         OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
+        OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
+                       &lpc32xx_mmci_data),
         { }
 };
 
@@ -241,10 +237,6 @@ static void __init lpc3250_machine_init(void)
 {
         u32 tmp;
 
-        /* Setup SLC NAND controller muxing */
-        __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
-                LPC32XX_CLKPWR_NAND_CLK_CTRL);
-
         /* Setup LCD muxing to RGB565 */
         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
@@ -252,47 +244,8 @@ static void __init lpc3250_machine_init(void)
         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 
-        /* Set up USB power */
-        tmp = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
-        tmp |= LPC32XX_CLKPWR_USBCTRL_HCLK_EN |
-                LPC32XX_CLKPWR_USBCTRL_USBI2C_EN;
-        __raw_writel(tmp, LPC32XX_CLKPWR_USB_CTRL);
-
-        /* Set up I2C pull levels */
-        tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
-        tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
-                LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
-        __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
-
-        /* Disable IrDA pulsing support on UART6 */
-        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
-        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
-        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
-        /* Enable DMA for I2S1 channel */
-        tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
-        tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
-        __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
-
         lpc32xx_serial_init();
 
-        /*
-         * AMBA peripheral clocks need to be enabled prior to AMBA device
-         * detection or a data fault will occur, so enable the clocks
-         * here.
-         */
-        tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
-                LPC32XX_CLKPWR_LCDCLK_CTRL);
-
-        tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
-                LPC32XX_CLKPWR_SSP_CLK_CTRL);
-
-        tmp = __raw_readl(LPC32XX_CLKPWR_DMA_CLK_CTRL);
-        __raw_writel((tmp | LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN),
-                     LPC32XX_CLKPWR_DMA_CLK_CTRL);
-
         /* Test clock needed for UDA1380 initial init */
         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
@@ -302,12 +255,10 @@ static void __init lpc3250_machine_init(void)
                              lpc32xx_auxdata_lookup, NULL);
 
         /* Register GPIOs used on this board */
-        if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
-                printk(KERN_ERR "Error requesting gpio %u",
-                        SPI0_CS_GPIO);
-        else if (gpio_direction_output(SPI0_CS_GPIO, 1))
-                printk(KERN_ERR "Error setting gpio %u to output",
-                        SPI0_CS_GPIO);
+        if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
+                pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
+        else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
+                pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
 }
 
 static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
index f2735281616a..05621a29fba2 100644
--- a/arch/arm/mach-lpc32xx/serial.c
+++ b/arch/arm/mach-lpc32xx/serial.c
@@ -31,59 +31,6 @@
 
 #define LPC32XX_SUART_FIFO_SIZE 64
 
-/* Standard 8250/16550 compatible serial ports */
-static struct plat_serial8250_port serial_std_platform_data[] = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART5_BASE),
-                .mapbase        = LPC32XX_UART5_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR5,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART3_BASE),
-                .mapbase        = LPC32XX_UART3_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR3,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART4_BASE),
-                .mapbase        = LPC32XX_UART4_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR4,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
-        {
-                .membase        = io_p2v(LPC32XX_UART6_BASE),
-                .mapbase        = LPC32XX_UART6_BASE,
-                .irq            = IRQ_LPC32XX_UART_IIR6,
-                .uartclk        = LPC32XX_MAIN_OSC_FREQ,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM32,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART |
-                                        UPF_SKIP_TEST,
-        },
-#endif
-        { },
-};
-
 struct uartinit {
         char *uart_ck_name;
         u32 ck_mode_mask;
@@ -92,7 +39,6 @@ struct uartinit {
 };
 
 static struct uartinit uartinit_data[] __initdata = {
-#ifdef CONFIG_ARCH_LPC32XX_UART5_SELECT
         {
                 .uart_ck_name = "uart5_ck",
                 .ck_mode_mask =
@@ -100,8 +46,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
                 .mapbase = LPC32XX_UART5_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
         {
                 .uart_ck_name = "uart3_ck",
                 .ck_mode_mask =
@@ -109,8 +53,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
                 .mapbase = LPC32XX_UART3_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
         {
                 .uart_ck_name = "uart4_ck",
                 .ck_mode_mask =
@@ -118,8 +60,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
                 .mapbase = LPC32XX_UART4_BASE,
         },
-#endif
-#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
         {
                 .uart_ck_name = "uart6_ck",
                 .ck_mode_mask =
@@ -127,19 +67,6 @@ static struct uartinit uartinit_data[] __initdata = {
                 .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
                 .mapbase = LPC32XX_UART6_BASE,
         },
-#endif
-};
-
-static struct platform_device serial_std_platform_device = {
-        .name                   = "serial8250",
-        .id                     = 0,
-        .dev                    = {
-                .platform_data  = serial_std_platform_data,
-        },
-};
-
-static struct platform_device *lpc32xx_serial_devs[] __initdata = {
-        &serial_std_platform_device,
 };
 
 void __init lpc32xx_serial_init(void)
@@ -156,15 +83,8 @@ void __init lpc32xx_serial_init(void)
                 clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
                 if (!IS_ERR(clk)) {
                         clk_enable(clk);
-                        serial_std_platform_data[i].uartclk =
-                                clk_get_rate(clk);
                 }
 
-                /* Fall back on main osc rate if clock rate return fails */
-                if (serial_std_platform_data[i].uartclk == 0)
-                        serial_std_platform_data[i].uartclk =
-                                LPC32XX_MAIN_OSC_FREQ;
-
                 /* Setup UART clock modes for all UARTs, disable autoclock */
                 clkmodes |= uartinit_data[i].ck_mode_mask;
 
@@ -189,7 +109,7 @@ void __init lpc32xx_serial_init(void)
         __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
         for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
                 /* Force a flush of the RX FIFOs to work around a HW bug */
-                puart = serial_std_platform_data[i].mapbase;
+                puart = uartinit_data[i].mapbase;
                 __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
                 __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
                 j = LPC32XX_SUART_FIFO_SIZE;
@@ -198,11 +118,13 @@ void __init lpc32xx_serial_init(void)
                 __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
         }
 
+        /* Disable IrDA pulsing support on UART6 */
+        tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
+        tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
+        __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
+
         /* Disable UART5->USB transparent mode or USB won't work */
         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
         tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
-        platform_add_devices(lpc32xx_serial_devs,
-                ARRAY_SIZE(lpc32xx_serial_devs));
 }
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 91cf0625819c..ccdf83b17cf1 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -16,6 +16,7 @@ config SOC_IMX28
         bool
         select ARM_AMBA
         select CPU_ARM926T
+        select HAVE_CAN_FLEXCAN if CAN
         select HAVE_PWM
         select PINCTRL_IMX28
 
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
index 07b11fe6453f..4582999cf080 100644
--- a/arch/arm/mach-mxs/Makefile.boot
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -1 +1,10 @@
 zreladdr-y += 0x40008000
+
+dtb-y += imx23-evk.dtb \
+         imx23-olinuxino.dtb \
+         imx23-stmp378x_devb.dtb \
+         imx28-apx4devkit.dtb \
+         imx28-cfa10036.dtb \
+         imx28-evk.dtb \
+         imx28-m28evk.dtb \
+         imx28-tx28.dtb \
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
index 9acdd6387047..9ee5cede3d42 100644
--- a/arch/arm/mach-mxs/devices-mx23.h
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -10,7 +10,7 @@
  */
 #include <mach/mx23.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 #include <linux/amba/bus.h>
 
 static inline int mx23_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index 84b2960df117..fcab431060f4 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -10,7 +10,7 @@
  */
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 #include <linux/amba/bus.h>
 
 static inline int mx28_add_duart(void)
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
index 5a75b7180f74..76b53f73418e 100644
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -10,7 +10,7 @@
 #include <mach/mx23.h>
 #include <mach/mx28.h>
 #include <mach/devices-common.h>
-#include <mach/mxsfb.h>
+#include <linux/mxsfb.h>
 
 #ifdef CONFIG_SOC_IMX23
 struct platform_device *__init mx23_add_mxsfb(
diff --git a/arch/arm/mach-mxs/include/mach/mxsfb.h b/arch/arm/mach-mxs/include/mach/mxsfb.h
deleted file mode 100644
index e4d79791515e..000000000000
--- a/arch/arm/mach-mxs/include/mach/mxsfb.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __MACH_FB_H
-#define __MACH_FB_H
-
-#include <linux/fb.h>
-
-#define STMLCDIF_8BIT 1 /** pixel data bus to the display is of 8 bit width */
-#define STMLCDIF_16BIT 0 /** pixel data bus to the display is of 16 bit width */
-#define STMLCDIF_18BIT 2 /** pixel data bus to the display is of 18 bit width */
-#define STMLCDIF_24BIT 3 /** pixel data bus to the display is of 24 bit width */
-
-#define FB_SYNC_DATA_ENABLE_HIGH_ACT    (1 << 6)
-#define FB_SYNC_DOTCLK_FAILING_ACT      (1 << 7) /* failing/negtive edge sampling */
-
-struct mxsfb_platform_data {
-        struct fb_videomode *mode_list;
-        unsigned mode_count;
-
-        unsigned default_bpp;
-
-        unsigned dotclk_delay;  /* refer manual HW_LCDIF_VDCTRL4 register */
-        unsigned ld_intf_width; /* refer STMLCDIF_* macros */
-
-        unsigned fb_size;       /* Size of the video memory. If zero a
-                                 * default will be used
-                                 */
-        unsigned long fb_phys;  /* physical address for the video memory. If
-                                 * zero the framebuffer memory will be dynamically
-                                 * allocated. If specified,fb_size must also be specified.
-                                 * fb_phys must be unused by Linux.
-                                 */
-};
-
-#endif /* __MACH_FB_H */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 8cac94b33020..648bdd05d38b 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -16,12 +16,95 @@
 #include <linux/init.h>
 #include <linux/init.h>
 #include <linux/irqdomain.h>
+#include <linux/micrel_phy.h>
+#include <linux/mxsfb.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
+#include <linux/phy.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 #include <mach/common.h>
 
+static struct fb_videomode mx23evk_video_modes[] = {
+        {
+                .name           = "Samsung-LMS430HF02",
+                .refresh        = 60,
+                .xres           = 480,
+                .yres           = 272,
+                .pixclock       = 108096, /* picosecond (9.2 MHz) */
+                .left_margin    = 15,
+                .right_margin   = 8,
+                .upper_margin   = 12,
+                .lower_margin   = 4,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct fb_videomode mx28evk_video_modes[] = {
+        {
+                .name           = "Seiko-43WVF1G",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 29851, /* picosecond (33.5 MHz) */
+                .left_margin    = 89,
+                .right_margin   = 164,
+                .upper_margin   = 23,
+                .lower_margin   = 10,
+                .hsync_len      = 10,
+                .vsync_len      = 10,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct fb_videomode m28evk_video_modes[] = {
+        {
+                .name           = "Ampire AM-800480R2TMQW-T01H",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 30066, /* picosecond (33.26 MHz) */
+                .left_margin    = 0,
+                .right_margin   = 256,
+                .upper_margin   = 0,
+                .lower_margin   = 45,
+                .hsync_len      = 1,
+                .vsync_len      = 1,
+                .sync           = FB_SYNC_DATA_ENABLE_HIGH_ACT,
+        },
+};
+
+static struct fb_videomode apx4devkit_video_modes[] = {
+        {
+                .name           = "HannStar PJ70112A",
+                .refresh        = 60,
+                .xres           = 800,
+                .yres           = 480,
+                .pixclock       = 33333, /* picosecond (30.00 MHz) */
+                .left_margin    = 88,
+                .right_margin   = 40,
+                .upper_margin   = 32,
+                .lower_margin   = 13,
+                .hsync_len      = 48,
+                .vsync_len      = 3,
+                .sync           = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT |
+                                  FB_SYNC_DATA_ENABLE_HIGH_ACT |
+                                  FB_SYNC_DOTCLK_FAILING_ACT,
+        },
+};
+
+static struct mxsfb_platform_data mxsfb_pdata __initdata;
+
+static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("fsl,imx23-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        OF_DEV_AUXDATA("fsl,imx28-lcdif", 0x80030000, NULL, &mxsfb_pdata),
+        { /* sentinel */ }
+};
+
 static int __init mxs_icoll_add_irq_domain(struct device_node *np,
                                 struct device_node *interrupt_parent)
 {
@@ -71,33 +154,155 @@ static struct sys_timer imx28_timer = {
         .init = imx28_timer_init,
 };
 
-static void __init imx28_evk_init(void)
+enum mac_oui {
+        OUI_FSL,
+        OUI_DENX,
+};
+
+static void __init update_fec_mac_prop(enum mac_oui oui)
+{
+        struct device_node *np, *from = NULL;
+        struct property *oldmac, *newmac;
+        const u32 *ocotp = mxs_get_ocotp();
+        u8 *macaddr;
+        u32 val;
+        int i;
+
+        for (i = 0; i < 2; i++) {
+                np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
+                if (!np)
+                        return;
+                from = np;
+
+                newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
+                if (!newmac)
+                        return;
+                newmac->value = newmac + 1;
+                newmac->length = 6;
+
+                newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
+                if (!newmac->name) {
+                        kfree(newmac);
+                        return;
+                }
+
+                /*
+                 * OCOTP only stores the last 4 octets for each mac address,
+                 * so hard-code OUI here.
+                 */
+                macaddr = newmac->value;
+                switch (oui) {
+                case OUI_FSL:
+                        macaddr[0] = 0x00;
+                        macaddr[1] = 0x04;
+                        macaddr[2] = 0x9f;
+                        break;
+                case OUI_DENX:
+                        macaddr[0] = 0xc0;
+                        macaddr[1] = 0xe5;
+                        macaddr[2] = 0x4e;
+                        break;
+                }
+                val = ocotp[i];
+                macaddr[3] = (val >> 16) & 0xff;
+                macaddr[4] = (val >> 8) & 0xff;
+                macaddr[5] = (val >> 0) & 0xff;
+
+                oldmac = of_find_property(np, newmac->name, NULL);
+                if (oldmac)
+                        prom_update_property(np, newmac, oldmac);
+                else
+                        prom_add_property(np, newmac);
+        }
+}
+
+static void __init imx23_evk_init(void)
+{
+        mxsfb_pdata.mode_list = mx23evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(mx23evk_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
+static inline void enable_clk_enet_out(void)
 {
-        struct clk *clk;
+        struct clk *clk = clk_get_sys("enet_out", NULL);
 
-        /* Enable fec phy clock */
-        clk = clk_get_sys("enet_out", NULL);
         if (!IS_ERR(clk))
                 clk_prepare_enable(clk);
 }
 
+static void __init imx28_evk_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_FSL);
+
+        mxsfb_pdata.mode_list = mx28evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(mx28evk_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
+static void __init m28evk_init(void)
+{
+        enable_clk_enet_out();
+        update_fec_mac_prop(OUI_DENX);
+
+        mxsfb_pdata.mode_list = m28evk_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(m28evk_video_modes);
+        mxsfb_pdata.default_bpp = 16;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_18BIT;
+}
+
+static int apx4devkit_phy_fixup(struct phy_device *phy)
+{
+        phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
+        return 0;
+}
+
+static void __init apx4devkit_init(void)
+{
+        enable_clk_enet_out();
+
+        if (IS_BUILTIN(CONFIG_PHYLIB))
+                phy_register_fixup_for_uid(PHY_ID_KS8051, MICREL_PHY_ID_MASK,
+                                           apx4devkit_phy_fixup);
+
+        mxsfb_pdata.mode_list = apx4devkit_video_modes;
+        mxsfb_pdata.mode_count = ARRAY_SIZE(apx4devkit_video_modes);
+        mxsfb_pdata.default_bpp = 32;
+        mxsfb_pdata.ld_intf_width = STMLCDIF_24BIT;
+}
+
 static void __init mxs_machine_init(void)
 {
         if (of_machine_is_compatible("fsl,imx28-evk"))
                 imx28_evk_init();
+        else if (of_machine_is_compatible("fsl,imx23-evk"))
+                imx23_evk_init();
+        else if (of_machine_is_compatible("denx,m28evk"))
+                m28evk_init();
+        else if (of_machine_is_compatible("bluegiga,apx4devkit"))
+                apx4devkit_init();
 
         of_platform_populate(NULL, of_default_bus_match_table,
-                                NULL, NULL);
+                             mxs_auxdata_lookup, NULL);
 }
 
 static const char *imx23_dt_compat[] __initdata = {
         "fsl,imx23-evk",
+        "fsl,stmp378x_devb"
+        "olimex,imx23-olinuxino",
         "fsl,imx23",
         NULL,
 };
 
 static const char *imx28_dt_compat[] __initdata = {
+        "bluegiga,apx4devkit",
+        "crystalfontz,cfa10036",
+        "denx,m28evk",
         "fsl,imx28-evk",
+        "karo,tx28",
         "fsl,imx28",
         NULL,
 };
diff --git a/arch/arm/mach-mxs/module-tx28.c b/arch/arm/mach-mxs/module-tx28.c
index 9a7b08b2a925..0f71f82101cc 100644
--- a/arch/arm/mach-mxs/module-tx28.c
+++ b/arch/arm/mach-mxs/module-tx28.c
@@ -11,7 +11,7 @@
 #include <linux/gpio.h>
 
 #include <mach/iomux-mx28.h>
-#include "../devices-mx28.h"
+#include "devices-mx28.h"
 
 #include "module-tx28.h"
 
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
index a6bbd1a7b4e7..a42c9a33d3bf 100644
--- a/arch/arm/mach-nomadik/Makefile
+++ b/arch/arm/mach-nomadik/Makefile
@@ -7,8 +7,6 @@
 
 # Object file lists.
 
-obj-y                   += clock.o
-
 # Cpu revision
 obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
 
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 2e8d3e176bc7..f4535a7dadf5 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -14,12 +14,14 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/mmci.h>
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>
 #include <linux/mtd/onenand.h>
 #include <linux/mtd/partitions.h>
+#include <linux/i2c.h>
 #include <linux/io.h>
 #include <asm/hardware/vic.h>
 #include <asm/sizes.h>
@@ -185,16 +187,28 @@ static void __init nhk8815_onenand_init(void)
 #endif
 }
 
-static AMBA_APB_DEVICE(uart0, "uart0", 0, NOMADIK_UART0_BASE,
-        { IRQ_UART0 }, NULL);
+static struct mmci_platform_data mmcsd_plat_data = {
+        .ocr_mask = MMC_VDD_29_30,
+        .f_max = 48000000,
+        .gpio_wp = -1,
+        .gpio_cd = 111,
+        .cd_invert = true,
+        .capabilities = MMC_CAP_MMC_HIGHSPEED |
+        MMC_CAP_SD_HIGHSPEED | MMC_CAP_4_BIT_DATA,
+};
 
-static AMBA_APB_DEVICE(uart1, "uart1", 0, NOMADIK_UART1_BASE,
-        { IRQ_UART1 }, NULL);
+static int __init nhk8815_mmcsd_init(void)
+{
+        int ret;
 
-static struct amba_device *amba_devs[] __initdata = {
-        &uart0_device,
-        &uart1_device,
-};
+        ret = gpio_request(112, "card detect bias");
+        if (ret)
+                return ret;
+        gpio_direction_output(112, 0);
+        amba_apb_device_add(NULL, "mmci", NOMADIK_SDI_BASE, SZ_4K, IRQ_SDMMC, 0, &mmcsd_plat_data, 0x10180180);
+        return 0;
+}
+module_init(nhk8815_mmcsd_init);
 
 static struct resource nhk8815_eth_resources[] = {
         {
@@ -253,17 +267,46 @@ static struct sys_timer nomadik_timer = {
         .init   = nomadik_timer_init,
 };
 
+static struct i2c_board_info __initdata nhk8815_i2c0_devices[] = {
+        {
+                I2C_BOARD_INFO("stw4811", 0x2d),
+        },
+};
+
+static struct i2c_board_info __initdata nhk8815_i2c1_devices[] = {
+        {
+                I2C_BOARD_INFO("camera", 0x10),
+        },
+        {
+                I2C_BOARD_INFO("stw5095", 0x1a),
+        },
+        {
+                I2C_BOARD_INFO("lis3lv02dl", 0x1d),
+        },
+};
+
+static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
+        {
+                I2C_BOARD_INFO("stw4811-usb", 0x2d),
+        },
+};
+
 static void __init nhk8815_platform_init(void)
 {
-        int i;
-
         cpu8815_platform_init();
         nhk8815_onenand_init();
         platform_add_devices(nhk8815_platform_devices,
                              ARRAY_SIZE(nhk8815_platform_devices));
 
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
+        amba_apb_device_add(NULL, "uart0", NOMADIK_UART0_BASE, SZ_4K, IRQ_UART0, 0, NULL, 0);
+        amba_apb_device_add(NULL, "uart1", NOMADIK_UART1_BASE, SZ_4K, IRQ_UART1, 0, NULL, 0);
+
+        i2c_register_board_info(0, nhk8815_i2c0_devices,
+                                ARRAY_SIZE(nhk8815_i2c0_devices));
+        i2c_register_board_info(1, nhk8815_i2c1_devices,
+                                ARRAY_SIZE(nhk8815_i2c1_devices));
+        i2c_register_board_info(2, nhk8815_i2c2_devices,
+                                ARRAY_SIZE(nhk8815_i2c2_devices));
 }
 
 MACHINE_START(NOMADIK, "NHK8815")
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
deleted file mode 100644
index 48a59f24e10c..000000000000
--- a/arch/arm/mach-nomadik/clock.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- *  linux/arch/arm/mach-nomadik/clock.c
- *
- *  Copyright (C) 2009 Alessandro Rubini
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include "clock.h"
-
-/*
- * The nomadik board uses generic clocks, but the serial pl011 file
- * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
-        return clk->rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* enable and disable do nothing */
-int clk_enable(struct clk *clk)
-{
-        return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
-}
-EXPORT_SYMBOL(clk_disable);
-
-static struct clk clk_24 = {
-        .rate = 2400000,
-};
-
-static struct clk clk_48 = {
-        .rate = 48 * 1000 * 1000,
-};
-
-/*
- * Catch-all default clock to satisfy drivers using the clk API.  We don't
- * model the actual hardware clocks yet.
- */
-static struct clk clk_default;
-
-#define CLK(_clk, dev)                          \
-        {                                       \
-                .clk            = _clk,         \
-                .dev_id         = dev,          \
-        }
-
-static struct clk_lookup lookups[] = {
-        {
-                .con_id         = "apb_pclk",
-                .clk            = &clk_default,
-        },
-        CLK(&clk_24, "mtu0"),
-        CLK(&clk_24, "mtu1"),
-        CLK(&clk_48, "uart0"),
-        CLK(&clk_48, "uart1"),
-        CLK(&clk_default, "gpio.0"),
-        CLK(&clk_default, "gpio.1"),
-        CLK(&clk_default, "gpio.2"),
-        CLK(&clk_default, "gpio.3"),
-        CLK(&clk_default, "rng"),
-};
-
-int __init clk_init(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-        return 0;
-}
diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h
deleted file mode 100644
index 78da2e7c3985..000000000000
--- a/arch/arm/mach-nomadik/clock.h
+++ /dev/null
@@ -1,15 +0,0 @@
-
-/*
- *  linux/arch/arm/mach-nomadik/clock.h
- *
- *  Copyright (C) 2009 Alessandro Rubini
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-struct clk {
-        unsigned long           rate;
-};
-
-int __init clk_init(void);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
index 27f43a46985e..6fd8e46567a4 100644
--- a/arch/arm/mach-nomadik/cpu-8815.c
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -22,6 +22,10 @@
 #include <linux/amba/bus.h>
 #include <linux/platform_device.h>
 #include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/irq.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_data/clk-nomadik.h>
 
 #include <plat/gpio-nomadik.h>
 #include <mach/hardware.h>
@@ -32,91 +36,63 @@
 #include <asm/cacheflush.h>
 #include <asm/hardware/cache-l2x0.h>
 
-#include "clock.h"
 #include "cpu-8815.h"
 
-#define __MEM_4K_RESOURCE(x) \
-        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
-
 /* The 8815 has 4 GPIO blocks, let's register them immediately */
-
-#define GPIO_RESOURCE(block)                                            \
-        {                                                               \
-                .start  = NOMADIK_GPIO##block##_BASE,                   \
-                .end    = NOMADIK_GPIO##block##_BASE + SZ_4K - 1,       \
-                .flags  = IORESOURCE_MEM,                               \
-        },                                                              \
-        {                                                               \
-                .start  = IRQ_GPIO##block,                              \
-                .end    = IRQ_GPIO##block,                              \
-                .flags  = IORESOURCE_IRQ,                               \
-        }
-
-#define GPIO_DEVICE(block)                                              \
-        {                                                               \
-                .name           = "gpio",                               \
-                .id             = block,                                \
-                .num_resources  = 2,                                    \
-                .resource       = &cpu8815_gpio_resources[block * 2],   \
-                .dev = {                                                \
-                        .platform_data = &cpu8815_gpio[block],          \
-                },                                                      \
-        }
-
-static struct nmk_gpio_platform_data cpu8815_gpio[] = {
-        {
-                .name = "GPIO-0-31",
-                .first_gpio = 0,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(0),
-        }, {
-                .name = "GPIO-32-63",
-                .first_gpio = 32,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(32),
-        }, {
-                .name = "GPIO-64-95",
-                .first_gpio = 64,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(64),
-        }, {
-                .name = "GPIO-96-127", /* 124..127 not routed to pin */
-                .first_gpio = 96,
-                .first_irq = NOMADIK_GPIO_TO_IRQ(96),
-        }
+static resource_size_t __initdata cpu8815_gpio_base[] = {
+        NOMADIK_GPIO0_BASE,
+        NOMADIK_GPIO1_BASE,
+        NOMADIK_GPIO2_BASE,
+        NOMADIK_GPIO3_BASE,
 };
 
-static struct resource cpu8815_gpio_resources[] = {
-        GPIO_RESOURCE(0),
-        GPIO_RESOURCE(1),
-        GPIO_RESOURCE(2),
-        GPIO_RESOURCE(3),
-};
-
-static struct platform_device cpu8815_platform_gpio[] = {
-        GPIO_DEVICE(0),
-        GPIO_DEVICE(1),
-        GPIO_DEVICE(2),
-        GPIO_DEVICE(3),
-};
+static struct platform_device *
+cpu8815_add_gpio(int id, resource_size_t addr, int irq,
+                 struct nmk_gpio_platform_data *pdata)
+{
+        struct resource resources[] = {
+                {
+                        .start  = addr,
+                        .end    = addr + 127,
+                        .flags  = IORESOURCE_MEM,
+                },
+                {
+                        .start  = irq,
+                        .end    = irq,
+                        .flags  = IORESOURCE_IRQ,
+                }
+        };
+
+        return platform_device_register_resndata(NULL, "gpio", id,
+                                resources, ARRAY_SIZE(resources),
+                                pdata, sizeof(*pdata));
+}
 
-static AMBA_APB_DEVICE(cpu8815_amba_rng, "rng", 0, NOMADIK_RNG_BASE, { }, NULL);
+void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
+                       struct nmk_gpio_platform_data *pdata)
+{
+        int first = 0;
+        int i;
 
-static struct platform_device *platform_devs[] __initdata = {
-        cpu8815_platform_gpio + 0,
-        cpu8815_platform_gpio + 1,
-        cpu8815_platform_gpio + 2,
-        cpu8815_platform_gpio + 3,
-};
+        for (i = 0; i < num; i++, first += 32, irq++) {
+                pdata->first_gpio = first;
+                pdata->first_irq = NOMADIK_GPIO_TO_IRQ(first);
+                pdata->num_gpio = 32;
 
-static struct amba_device *amba_devs[] __initdata = {
-        &cpu8815_amba_rng_device
-};
+                cpu8815_add_gpio(i, base[i], irq, pdata);
+        }
+}
 
 static int __init cpu8815_init(void)
 {
-        int i;
-
-        platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
-        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
-                amba_device_register(amba_devs[i], &iomem_resource);
+        struct nmk_gpio_platform_data pdata = {
+                /* No custom data yet */
+        };
+
+        cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
+                          IRQ_GPIO0, &pdata);
+        amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
+        amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
         return 0;
 }
 arch_initcall(cpu8815_init);
@@ -147,7 +123,7 @@ void __init cpu8815_init_irq(void)
          * Init clocks here so that they are available for system timer
          * initialization.
          */
-        clk_init();
+        nomadik_clk_init();
 }
 
 /*
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
index 0fc2f6f1cc97..6d14454d4609 100644
--- a/arch/arm/mach-nomadik/i2c-8815nhk.c
+++ b/arch/arm/mach-nomadik/i2c-8815nhk.c
@@ -5,6 +5,7 @@
 #include <linux/i2c-gpio.h>
 #include <linux/platform_device.h>
 #include <plat/gpio-nomadik.h>
+#include <plat/pincfg.h>
 
 /*
  * There are two busses in the 8815NHK.
@@ -12,19 +13,27 @@
  * use bit-bang through GPIO by now, to keep things simple
  */
 
+/* I2C0 connected to the STw4811 power management chip */
 static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
         /* keep defaults for timeouts; pins are push-pull bidirectional */
         .scl_pin = 62,
         .sda_pin = 63,
 };
 
+/* I2C1 connected to various sensors */
 static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
         /* keep defaults for timeouts; pins are push-pull bidirectional */
         .scl_pin = 53,
         .sda_pin = 54,
 };
 
-/* first bus: GPIO XX and YY */
+/* I2C2 connected to the USB portions of the STw4811 only */
+static struct i2c_gpio_platform_data nhk8815_i2c_data2 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 73,
+        .sda_pin = 74,
+};
+
 static struct platform_device nhk8815_i2c_dev0 = {
         .name   = "i2c-gpio",
         .id     = 0,
@@ -32,7 +41,7 @@ static struct platform_device nhk8815_i2c_dev0 = {
                 .platform_data = &nhk8815_i2c_data0,
         },
 };
-/* second bus: GPIO XX and YY */
+
 static struct platform_device nhk8815_i2c_dev1 = {
         .name   = "i2c-gpio",
         .id     = 1,
@@ -41,15 +50,29 @@ static struct platform_device nhk8815_i2c_dev1 = {
         },
 };
 
+static struct platform_device nhk8815_i2c_dev2 = {
+        .name   = "i2c-gpio",
+        .id     = 2,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data2,
+        },
+};
+
+static pin_cfg_t cpu8815_pins_i2c[] = {
+        PIN_CFG_INPUT(62, GPIO, PULLUP),
+        PIN_CFG_INPUT(63, GPIO, PULLUP),
+        PIN_CFG_INPUT(53, GPIO, PULLUP),
+        PIN_CFG_INPUT(54, GPIO, PULLUP),
+        PIN_CFG_INPUT(73, GPIO, PULLUP),
+        PIN_CFG_INPUT(74, GPIO, PULLUP),
+};
+
 static int __init nhk8815_i2c_init(void)
 {
-        nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO);
-        nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO);
+        nmk_config_pins(cpu8815_pins_i2c, ARRAY_SIZE(cpu8815_pins_i2c));
         platform_device_register(&nhk8815_i2c_dev0);
-
-        nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO);
-        nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO);
         platform_device_register(&nhk8815_i2c_dev1);
+        platform_device_register(&nhk8815_i2c_dev2);
 
         return 0;
 }
@@ -58,6 +81,7 @@ static void __exit nhk8815_i2c_exit(void)
 {
         platform_device_unregister(&nhk8815_i2c_dev0);
         platform_device_unregister(&nhk8815_i2c_dev1);
+        platform_device_unregister(&nhk8815_i2c_dev2);
         return;
 }
 
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
index 8faabc560398..a118e615f865 100644
--- a/arch/arm/mach-nomadik/include/mach/irqs.h
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -22,56 +22,56 @@
 
 #include <mach/hardware.h>
 
-#define IRQ_VIC_START           0       /* first VIC interrupt is 0 */
+#define IRQ_VIC_START           1       /* first VIC interrupt is 1 */
 
 /*
  * Interrupt numbers generic for all Nomadik Chip cuts
  */
-#define IRQ_WATCHDOG                    0
-#define IRQ_SOFTINT                     1
-#define IRQ_CRYPTO                      2
-#define IRQ_OWM                         3
-#define IRQ_MTU0                        4
-#define IRQ_MTU1                        5
-#define IRQ_GPIO0                       6
-#define IRQ_GPIO1                       7
-#define IRQ_GPIO2                       8
-#define IRQ_GPIO3                       9
-#define IRQ_RTC_RTT                     10
-#define IRQ_SSP                         11
-#define IRQ_UART0                       12
-#define IRQ_DMA1                        13
-#define IRQ_CLCD_MDIF                   14
-#define IRQ_DMA0                        15
-#define IRQ_PWRFAIL                     16
-#define IRQ_UART1                       17
-#define IRQ_FIRDA                       18
-#define IRQ_MSP0                        19
-#define IRQ_I2C0                        20
-#define IRQ_I2C1                        21
-#define IRQ_SDMMC                       22
-#define IRQ_USBOTG                      23
-#define IRQ_SVA_IT0                     24
-#define IRQ_SVA_IT1                     25
-#define IRQ_SAA_IT0                     26
-#define IRQ_SAA_IT1                     27
-#define IRQ_UART2                       28
-#define IRQ_MSP2                        31
-#define IRQ_L2CC                        48
-#define IRQ_HPI                         49
-#define IRQ_SKE                         50
-#define IRQ_KP                          51
-#define IRQ_MEMST                       54
-#define IRQ_SGA_IT                      58
-#define IRQ_USBM                        60
-#define IRQ_MSP1                        62
+#define IRQ_WATCHDOG                    1
+#define IRQ_SOFTINT                     2
+#define IRQ_CRYPTO                      3
+#define IRQ_OWM                         4
+#define IRQ_MTU0                        5
+#define IRQ_MTU1                        6
+#define IRQ_GPIO0                       7
+#define IRQ_GPIO1                       8
+#define IRQ_GPIO2                       9
+#define IRQ_GPIO3                       10
+#define IRQ_RTC_RTT                     11
+#define IRQ_SSP                         12
+#define IRQ_UART0                       13
+#define IRQ_DMA1                        14
+#define IRQ_CLCD_MDIF                   15
+#define IRQ_DMA0                        16
+#define IRQ_PWRFAIL                     17
+#define IRQ_UART1                       18
+#define IRQ_FIRDA                       19
+#define IRQ_MSP0                        20
+#define IRQ_I2C0                        21
+#define IRQ_I2C1                        22
+#define IRQ_SDMMC                       23
+#define IRQ_USBOTG                      24
+#define IRQ_SVA_IT0                     25
+#define IRQ_SVA_IT1                     26
+#define IRQ_SAA_IT0                     27
+#define IRQ_SAA_IT1                     28
+#define IRQ_UART2                       29
+#define IRQ_MSP2                        30
+#define IRQ_L2CC                        49
+#define IRQ_HPI                         50
+#define IRQ_SKE                         51
+#define IRQ_KP                          52
+#define IRQ_MEMST                       55
+#define IRQ_SGA_IT                      59
+#define IRQ_USBM                        61
+#define IRQ_MSP1                        63
 
-#define NOMADIK_SOC_NR_IRQS             64
+#define NOMADIK_GPIO_OFFSET             (IRQ_VIC_START+64)
 
 /* After chip-specific IRQ numbers we have the GPIO ones */
 #define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
-#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_SOC_NR_IRQS)
-#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_SOC_NR_IRQS)
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_GPIO_OFFSET)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_GPIO_OFFSET)
 #define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
 
 /* Following two are used by entry_macro.S, to access our dual-vic */
@@ -79,4 +79,3 @@
 #define VIC_REG_IRQSR1          0x20
 
 #endif /* __ASM_ARCH_IRQS_H */
-
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index f2f8a5847018..c53469802c03 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -37,12 +37,12 @@
 #include <plat/board-ams-delta.h>
 #include <plat/keypad.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 
 #include <mach/hardware.h>
 #include <mach/ams-delta-fiq.h>
 #include <mach/camera.h>
+#include <mach/usb.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index e75e2d55a2d7..6ec385e2b98e 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -23,8 +23,10 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
+
+#include <mach/usb.h>
+
 #include "common.h"
 
 /* assume no Mini-AB port */
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index a28e989a63f4..44a4ab195fbc 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -40,11 +40,11 @@
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/irda.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/flash.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 #include "board-h2.h"
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index 108a8640fc6f..86cb5a04a404 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -40,13 +40,13 @@
 
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/dma.h>
 #include <plat/flash.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/usb.h>
 
 #include "common.h"
 #include "board-h3.h"
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 118a9d4a4c54..b3f6e943e661 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -44,10 +44,10 @@
 #include <plat/omap7xx.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
-#include <plat/usb.h>
 #include <plat/mmc.h>
 
 #include <mach/irqs.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 7970223a559d..f21c2966daad 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -35,11 +35,11 @@
 #include <plat/flash.h>
 #include <plat/fpga.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
 #include <plat/keypad.h>
 #include <plat/mmc.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "iomap.h"
 #include "common.h"
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 7212ae97f44a..4007a372481b 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -26,7 +26,6 @@
 #include <asm/mach/map.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/lcd_mipid.h>
@@ -34,6 +33,7 @@
 #include <plat/clock.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index da8d872d3d1c..8784705edb60 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -45,11 +45,11 @@
 #include <asm/mach/map.h>
 
 #include <plat/flash.h>
-#include <plat/usb.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 949b62a73693..26bcb9defcdc 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -35,7 +35,6 @@
 
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/dma.h>
 #include <plat/board.h>
@@ -43,6 +42,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index 7f1e1cf2bf46..4d099446dfa8 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -35,7 +35,6 @@
 #include <plat/led.h>
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/board.h>
@@ -43,6 +42,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 3c71c6bace2c..cc71a26723ef 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -37,7 +37,6 @@
 
 #include <plat/flash.h>
 #include <plat/mux.h>
-#include <plat/usb.h>
 #include <plat/dma.h>
 #include <plat/tc.h>
 #include <plat/board.h>
@@ -45,6 +44,7 @@
 #include <plat/keypad.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 3b7b82b13684..8c665bd16ac2 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -37,13 +37,13 @@
 #include <plat/mux.h>
 #include <plat/dma.h>
 #include <plat/irda.h>
-#include <plat/usb.h>
 #include <plat/tc.h>
 #include <plat/board.h>
 #include <plat/keypad.h>
 #include <plat/board-sx1.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index afd67f0ec495..3497769eb353 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -35,9 +35,10 @@
 #include <plat/flash.h>
 #include <plat/mux.h>
 #include <plat/tc.h>
-#include <plat/usb.h>
+#include <plat/board.h>
 
 #include <mach/hardware.h>
+#include <mach/usb.h>
 
 #include "common.h"
 
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index c6ce93f71d08..c007d80dfb62 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -25,10 +25,11 @@
 #include <plat/clock.h>
 #include <plat/cpu.h>
 #include <plat/clkdev_omap.h>
+#include <plat/board.h>
 #include <plat/sram.h>  /* for omap_sram_reprogram_clock() */
-#include <plat/usb.h>   /* for OTG_BASE */
 
 #include <mach/hardware.h>
+#include <mach/usb.h>   /* for OTG_BASE */
 
 #include "iomap.h"
 #include "clock.h"
diff --git a/arch/arm/mach-omap1/include/mach/usb.h b/arch/arm/mach-omap1/include/mach/usb.h
new file mode 100644
index 000000000000..753cd5ce6949
--- /dev/null
+++ b/arch/arm/mach-omap1/include/mach/usb.h
@@ -0,0 +1,165 @@
+/*
+ * FIXME correct answer depends on hmc_mode,
+ * as does (on omap1) any nonzero value for config->otg port number
+ */
+#ifdef  CONFIG_USB_GADGET_OMAP
+#define is_usb0_device(config)  1
+#else
+#define is_usb0_device(config)  0
+#endif
+
+struct omap_usb_config {
+        /* Configure drivers according to the connectors on your board:
+         *  - "A" connector (rectagular)
+         *      ... for host/OHCI use, set "register_host".
+         *  - "B" connector (squarish) or "Mini-B"
+         *      ... for device/gadget use, set "register_dev".
+         *  - "Mini-AB" connector (very similar to Mini-B)
+         *      ... for OTG use as device OR host, initialize "otg"
+         */
+        unsigned        register_host:1;
+        unsigned        register_dev:1;
+        u8              otg;    /* port number, 1-based:  usb1 == 2 */
+
+        u8              hmc_mode;
+
+        /* implicitly true if otg:  host supports remote wakeup? */
+        u8              rwc;
+
+        /* signaling pins used to talk to transceiver on usbN:
+         *  0 == usbN unused
+         *  2 == usb0-only, using internal transceiver
+         *  3 == 3 wire bidirectional
+         *  4 == 4 wire bidirectional
+         *  6 == 6 wire unidirectional (or TLL)
+         */
+        u8              pins[3];
+
+        struct platform_device *udc_device;
+        struct platform_device *ohci_device;
+        struct platform_device *otg_device;
+
+        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
+        u32 (*usb1_init)(unsigned nwires);
+        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
+
+        int (*ocpi_enable)(void);
+};
+
+void omap_otg_init(struct omap_usb_config *config);
+
+#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
+void omap1_usb_init(struct omap_usb_config *pdata);
+#else
+static inline void omap1_usb_init(struct omap_usb_config *pdata)
+{
+}
+#endif
+
+#define OMAP1_OTG_BASE                  0xfffb0400
+#define OMAP1_UDC_BASE                  0xfffb4000
+#define OMAP1_OHCI_BASE                 0xfffba000
+
+#define OMAP2_OHCI_BASE                 0x4805e000
+#define OMAP2_UDC_BASE                  0x4805e200
+#define OMAP2_OTG_BASE                  0x4805e300
+#define OTG_BASE                        OMAP1_OTG_BASE
+#define UDC_BASE                        OMAP1_UDC_BASE
+#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REV                         (OTG_BASE + 0x00)
+#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
+#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
+#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
+#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
+#       define   OTG_IDLE_EN            (1 << 15)
+#       define   HST_IDLE_EN            (1 << 14)
+#       define   DEV_IDLE_EN            (1 << 13)
+#       define   OTG_RESET_DONE         (1 << 2)
+#       define   OTG_SOFT_RESET         (1 << 1)
+#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
+#       define   OTG_EN                 (1 << 31)
+#       define   USBX_SYNCHRO           (1 << 30)
+#       define   OTG_MST16              (1 << 29)
+#       define   SRP_GPDATA             (1 << 28)
+#       define   SRP_GPDVBUS            (1 << 27)
+#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
+#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
+#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
+#       define   SRP_DPW                (1 << 14)
+#       define   SRP_DATA               (1 << 13)
+#       define   SRP_VBUS               (1 << 12)
+#       define   OTG_PADEN              (1 << 10)
+#       define   HMC_PADEN              (1 << 9)
+#       define   UHOST_EN               (1 << 8)
+#       define   HMC_TLLSPEED           (1 << 7)
+#       define   HMC_TLLATTACH          (1 << 6)
+#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
+#define OTG_CTRL                        (OTG_BASE + 0x0c)
+#       define   OTG_USB2_EN            (1 << 29)
+#       define   OTG_USB2_DP            (1 << 28)
+#       define   OTG_USB2_DM            (1 << 27)
+#       define   OTG_USB1_EN            (1 << 26)
+#       define   OTG_USB1_DP            (1 << 25)
+#       define   OTG_USB1_DM            (1 << 24)
+#       define   OTG_USB0_EN            (1 << 23)
+#       define   OTG_USB0_DP            (1 << 22)
+#       define   OTG_USB0_DM            (1 << 21)
+#       define   OTG_ASESSVLD           (1 << 20)
+#       define   OTG_BSESSEND           (1 << 19)
+#       define   OTG_BSESSVLD           (1 << 18)
+#       define   OTG_VBUSVLD            (1 << 17)
+#       define   OTG_ID                 (1 << 16)
+#       define   OTG_DRIVER_SEL         (1 << 15)
+#       define   OTG_A_SETB_HNPEN       (1 << 12)
+#       define   OTG_A_BUSREQ           (1 << 11)
+#       define   OTG_B_HNPEN            (1 << 9)
+#       define   OTG_B_BUSREQ           (1 << 8)
+#       define   OTG_BUSDROP            (1 << 7)
+#       define   OTG_PULLDOWN           (1 << 5)
+#       define   OTG_PULLUP             (1 << 4)
+#       define   OTG_DRV_VBUS           (1 << 3)
+#       define   OTG_PD_VBUS            (1 << 2)
+#       define   OTG_PU_VBUS            (1 << 1)
+#       define   OTG_PU_ID              (1 << 0)
+#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
+#       define   DRIVER_SWITCH          (1 << 15)
+#       define   A_VBUS_ERR             (1 << 13)
+#       define   A_REQ_TMROUT           (1 << 12)
+#       define   A_SRP_DETECT           (1 << 11)
+#       define   B_HNP_FAIL             (1 << 10)
+#       define   B_SRP_TMROUT           (1 << 9)
+#       define   B_SRP_DONE             (1 << 8)
+#       define   B_SRP_STARTED          (1 << 7)
+#       define   OPRT_CHG               (1 << 0)
+#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
+        // same bits as in IRQ_EN
+#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
+#       define   OTGVPD                 (1 << 14)
+#       define   OTGVPU                 (1 << 13)
+#       define   OTGPUID                (1 << 12)
+#       define   USB2VDR                (1 << 10)
+#       define   USB2PDEN               (1 << 9)
+#       define   USB2PUEN               (1 << 8)
+#       define   USB1VDR                (1 << 6)
+#       define   USB1PDEN               (1 << 5)
+#       define   USB1PUEN               (1 << 4)
+#       define   USB0VDR                (1 << 2)
+#       define   USB0PDEN               (1 << 1)
+#       define   USB0PUEN               (1 << 0)
+#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
+#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
+
+/*-------------------------------------------------------------------------*/
+
+/* OMAP1 */
+#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
+#       define  CONF_USB2_UNI_R         (1 << 8)
+#       define  CONF_USB1_UNI_R         (1 << 7)
+#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
+#       define  CONF_USB0_ISOLATE_R     (1 << 3)
+#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
+#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
diff --git a/arch/arm/mach-omap1/usb.c b/arch/arm/mach-omap1/usb.c
index e61afd922766..65f88176fba8 100644
--- a/arch/arm/mach-omap1/usb.c
+++ b/arch/arm/mach-omap1/usb.c
@@ -27,7 +27,8 @@
 #include <asm/irq.h>
 
 #include <plat/mux.h>
-#include <plat/usb.h>
+
+#include <mach/usb.h>
 
 #include "common.h"
 
@@ -55,6 +56,119 @@
 #define INT_USB_IRQ_HGEN        INT_USB_HHC_1
 #define INT_USB_IRQ_OTG         IH2_BASE + 8
 
+#ifdef  CONFIG_ARCH_OMAP_OTG
+
+void __init
+omap_otg_init(struct omap_usb_config *config)
+{
+        u32             syscon;
+        int             alt_pingroup = 0;
+
+        /* NOTE:  no bus or clock setup (yet?) */
+
+        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
+        if (!(syscon & OTG_RESET_DONE))
+                pr_debug("USB resets not complete?\n");
+
+        //omap_writew(0, OTG_IRQ_EN);
+
+        /* pin muxing and transceiver pinouts */
+        if (config->pins[0] > 2)        /* alt pingroup 2 */
+                alt_pingroup = 1;
+        syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
+        syscon |= config->usb1_init(config->pins[1]);
+        syscon |= config->usb2_init(config->pins[2], alt_pingroup);
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
+
+        syscon = config->hmc_mode;
+        syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
+#ifdef  CONFIG_USB_OTG
+        if (config->otg)
+                syscon |= OTG_EN;
+#endif
+        if (cpu_class_is_omap1())
+                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+                         omap_readl(USB_TRANSCEIVER_CTRL));
+        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
+        omap_writel(syscon, OTG_SYSCON_2);
+
+        printk("USB: hmc %d", config->hmc_mode);
+        if (!alt_pingroup)
+                printk(", usb2 alt %d wires", config->pins[2]);
+        else if (config->pins[0])
+                printk(", usb0 %d wires%s", config->pins[0],
+                        is_usb0_device(config) ? " (dev)" : "");
+        if (config->pins[1])
+                printk(", usb1 %d wires", config->pins[1]);
+        if (!alt_pingroup && config->pins[2])
+                printk(", usb2 %d wires", config->pins[2]);
+        if (config->otg)
+                printk(", Mini-AB on usb%d", config->otg - 1);
+        printk("\n");
+
+        if (cpu_class_is_omap1()) {
+                u16 w;
+
+                /* leave USB clocks/controllers off until needed */
+                w = omap_readw(ULPD_SOFT_REQ);
+                w &= ~SOFT_USB_CLK_REQ;
+                omap_writew(w, ULPD_SOFT_REQ);
+
+                w = omap_readw(ULPD_CLOCK_CTRL);
+                w &= ~USB_MCLK_EN;
+                w |= DIS_USB_PVCI_CLK;
+                omap_writew(w, ULPD_CLOCK_CTRL);
+        }
+        syscon = omap_readl(OTG_SYSCON_1);
+        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
+
+#ifdef  CONFIG_USB_GADGET_OMAP
+        if (config->otg || config->register_dev) {
+                struct platform_device *udc_device = config->udc_device;
+                int status;
+
+                syscon &= ~DEV_IDLE_EN;
+                udc_device->dev.platform_data = config;
+                status = platform_device_register(udc_device);
+                if (status)
+                        pr_debug("can't register UDC device, %d\n", status);
+        }
+#endif
+
+#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+        if (config->otg || config->register_host) {
+                struct platform_device *ohci_device = config->ohci_device;
+                int status;
+
+                syscon &= ~HST_IDLE_EN;
+                ohci_device->dev.platform_data = config;
+                status = platform_device_register(ohci_device);
+                if (status)
+                        pr_debug("can't register OHCI device, %d\n", status);
+        }
+#endif
+
+#ifdef  CONFIG_USB_OTG
+        if (config->otg) {
+                struct platform_device *otg_device = config->otg_device;
+                int status;
+
+                syscon &= ~OTG_IDLE_EN;
+                otg_device->dev.platform_data = config;
+                status = platform_device_register(otg_device);
+                if (status)
+                        pr_debug("can't register OTG device, %d\n", status);
+        }
+#endif
+        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
+        omap_writel(syscon, OTG_SYSCON_1);
+}
+
+#else
+void omap_otg_init(struct omap_usb_config *config) {}
+#endif
+
 #ifdef  CONFIG_USB_GADGET_OMAP
 
 static struct resource udc_resources[] = {
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4cf5142f22cc..184469517f15 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -35,6 +35,7 @@ config ARCH_OMAP3
         select CPU_V7
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARCH_HAS_OPP
+        select PM_RUNTIME if CPU_IDLE
         select PM_OPP if PM
         select ARM_CPU_SUSPEND if PM
         select MULTI_IRQ_HANDLER
@@ -52,6 +53,7 @@ config ARCH_OMAP4
         select PL310_ERRATA_727915
         select ARM_ERRATA_720789
         select ARCH_HAS_OPP
+        select PM_RUNTIME if CPU_IDLE
         select PM_OPP if PM
         select USB_ARCH_HAS_EHCI if USB_SUPPORT
         select ARM_CPU_SUSPEND if PM
@@ -64,19 +66,16 @@ config SOC_OMAP2420
         depends on ARCH_OMAP2
         default y
         select OMAP_DM_TIMER
-        select ARCH_OMAP_OTG
 
 config SOC_OMAP2430
         bool "OMAP2430 support"
         depends on ARCH_OMAP2
         default y
-        select ARCH_OMAP_OTG
 
 config SOC_OMAP3430
         bool "OMAP3430 support"
         depends on ARCH_OMAP3
         default y
-        select ARCH_OMAP_OTG
 
 config SOC_TI81XX
         bool "TI81XX support"
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index fa742f3c2629..821794fd03d6 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -66,9 +66,7 @@ ifeq ($(CONFIG_PM),y)
 obj-$(CONFIG_ARCH_OMAP2)                += pm24xx.o
 obj-$(CONFIG_ARCH_OMAP2)                += sleep24xx.o
 obj-$(CONFIG_ARCH_OMAP3)                += pm34xx.o sleep34xx.o
-obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
 obj-$(CONFIG_PM_DEBUG)                  += pm-debug.o
 obj-$(CONFIG_OMAP_SMARTREFLEX)          += sr_device.o smartreflex.o
 obj-$(CONFIG_OMAP_SMARTREFLEX_CLASS3)   += smartreflex-class3.o
@@ -82,6 +80,11 @@ endif
 
 endif
 
+ifeq ($(CONFIG_CPU_IDLE),y)
+obj-$(CONFIG_ARCH_OMAP3)                += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4)                += cpuidle44xx.o
+endif
+
 # PRCM
 obj-y                                   += prm_common.o
 obj-$(CONFIG_ARCH_OMAP2)                += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
@@ -90,6 +93,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= vc3xxx_data.o vp3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += prcm.o cminst44xx.o cm44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += prcm_mpu44xx.o prminst44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += vc44xx_data.o vp44xx_data.o prm44xx.o
+obj-$(CONFIG_SOC_AM33XX)                += prcm.o prm33xx.o cm33xx.o
 
 # OMAP voltage domains
 voltagedomain-common                    := voltage.o vc.o vp.o
@@ -99,6 +103,7 @@ obj-$(CONFIG_ARCH_OMAP3)		+= $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP3)                += voltagedomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(voltagedomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += voltagedomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += voltagedomains33xx_data.o
 
 # OMAP powerdomain framework
 powerdomain-common                      += powerdomain.o powerdomain-common.o
@@ -113,10 +118,11 @@ obj-$(CONFIG_ARCH_OMAP3)		+= powerdomains2xxx_3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(powerdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += powerdomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += powerdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += powerdomains33xx_data.o
 
 # PRCM clockdomain control
 clockdomain-common                      += clockdomain.o
-clockdomain-common                      += clockdomains_common_data.o
 obj-$(CONFIG_ARCH_OMAP2)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomain2xxx_3xxx.o
 obj-$(CONFIG_ARCH_OMAP2)                += clockdomains2xxx_3xxx_data.o
@@ -129,6 +135,8 @@ obj-$(CONFIG_ARCH_OMAP3)		+= clockdomains3xxx_data.o
 obj-$(CONFIG_ARCH_OMAP4)                += $(clockdomain-common)
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomain44xx.o
 obj-$(CONFIG_ARCH_OMAP4)                += clockdomains44xx_data.o
+obj-$(CONFIG_SOC_AM33XX)                += clockdomain33xx.o
+obj-$(CONFIG_SOC_AM33XX)                += clockdomains33xx_data.o
 
 # Clock framework
 obj-$(CONFIG_ARCH_OMAP2)                += $(clock-common) clock2xxx.o
@@ -244,9 +252,6 @@ obj-y					+= $(omap-flash-y) $(omap-flash-m)
 omap-hsmmc-$(CONFIG_MMC_OMAP_HS)        := hsmmc.o
 obj-y                                   += $(omap-hsmmc-m) $(omap-hsmmc-y)
 
-
-usbfs-$(CONFIG_ARCH_OMAP_OTG)           := usb-fs.o
-obj-y                                   += $(usbfs-m) $(usbfs-y)
 obj-y                                   += usb-musb.o
 obj-y                                   += omap_phy_internal.o
 
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index 447682c4e11c..2c90ac686686 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -15,27 +15,13 @@
  * General Public License for more details.
  */
 
-#include <linux/clk.h>
+#include <linux/err.h>
 #include <linux/davinci_emac.h>
-#include <linux/platform_device.h>
-#include <plat/irqs.h>
+#include <asm/system.h>
+#include <plat/omap_device.h>
 #include <mach/am35xx.h>
-
 #include "control.h"
-
-static struct mdio_platform_data am35xx_emac_mdio_pdata;
-
-static struct resource am35xx_emac_mdio_resources[] = {
-        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE + AM35XX_EMAC_MDIO_OFFSET, SZ_4K),
-};
-
-static struct platform_device am35xx_emac_mdio_device = {
-        .name           = "davinci_mdio",
-        .id             = 0,
-        .num_resources  = ARRAY_SIZE(am35xx_emac_mdio_resources),
-        .resource       = am35xx_emac_mdio_resources,
-        .dev.platform_data = &am35xx_emac_mdio_pdata,
-};
+#include "am35xx-emac.h"
 
 static void am35xx_enable_emac_int(void)
 {
@@ -69,41 +55,57 @@ static struct emac_platform_data am35xx_emac_pdata = {
         .interrupt_disable      = am35xx_disable_emac_int,
 };
 
-static struct resource am35xx_emac_resources[] = {
-        DEFINE_RES_MEM(AM35XX_IPSS_EMAC_BASE, 0x30000),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RXTHRESH_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_RX_PULSE_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_TX_PULSE_IRQ),
-        DEFINE_RES_IRQ(INT_35XX_EMAC_C0_MISC_PULSE_IRQ),
-};
+static struct mdio_platform_data am35xx_mdio_pdata;
 
-static struct platform_device am35xx_emac_device = {
-        .name           = "davinci_emac",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(am35xx_emac_resources),
-        .resource       = am35xx_emac_resources,
-        .dev            = {
-                .platform_data  = &am35xx_emac_pdata,
-        },
-};
+static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
+                void *pdata, int pdata_len)
+{
+        struct platform_device *pdev;
+
+        pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len,
+                                 NULL, 0, false);
+        if (IS_ERR(pdev)) {
+                WARN(1, "Can't build omap_device for %s:%s.\n",
+                     oh->class->name, oh->name);
+                return PTR_ERR(pdev);
+        }
+
+        return 0;
+}
 
 void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
 {
+        struct omap_hwmod *oh;
         u32 v;
-        int err;
+        int ret;
 
-        am35xx_emac_pdata.rmii_en = rmii_en;
-        am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
-        err = platform_device_register(&am35xx_emac_device);
-        if (err) {
-                pr_err("AM35x: failed registering EMAC device: %d\n", err);
+        oh = omap_hwmod_lookup("davinci_mdio");
+        if (!oh) {
+                pr_err("Could not find davinci_mdio hwmod\n");
+                return;
+        }
+
+        am35xx_mdio_pdata.bus_freq = mdio_bus_freq;
+
+        ret = omap_davinci_emac_dev_init(oh, &am35xx_mdio_pdata,
+                                         sizeof(am35xx_mdio_pdata));
+        if (ret) {
+                pr_err("Could not build davinci_mdio hwmod device\n");
                 return;
         }
 
-        err = platform_device_register(&am35xx_emac_mdio_device);
-        if (err) {
-                pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
-                platform_device_unregister(&am35xx_emac_device);
+        oh = omap_hwmod_lookup("davinci_emac");
+        if (!oh) {
+                pr_err("Could not find davinci_emac hwmod\n");
+                return;
+        }
+
+        am35xx_emac_pdata.rmii_en = rmii_en;
+
+        ret = omap_davinci_emac_dev_init(oh, &am35xx_emac_pdata,
+                                         sizeof(am35xx_emac_pdata));
+        if (ret) {
+                pr_err("Could not build davinci_emac hwmod device\n");
                 return;
         }
 
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 99ca6bad5c30..9511584fdc4f 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -218,9 +218,6 @@ static struct twl4030_gpio_platform_data sdp2430_gpio_data = {
 };
 
 static struct twl4030_platform_data sdp2430_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .gpio           = &sdp2430_gpio_data,
         .vmmc1          = &sdp2430_vmmc1,
@@ -254,16 +251,6 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
         {}      /* Terminator */
 };
 
-static struct omap_usb_config sdp2430_usb_config __initdata = {
-        .otg            = 1,
-#ifdef  CONFIG_USB_GADGET_OMAP
-        .hmc_mode       = 0x0,
-#elif   defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        .hmc_mode       = 0x1,
-#endif
-        .pins[0]        = 3,
-};
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -280,7 +267,6 @@ static void __init omap_2430sdp_init(void)
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         omap_hsmmc_init(mmc);
-        omap2_usbfs_init(&sdp2430_usb_config);
 
         omap_mux_init_signal("usb0hs_stp", OMAP_PULL_ENA | OMAP_PULL_UP);
         usb_musb_init(NULL);
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 502c31e123be..519bcd3079e8 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -35,7 +35,6 @@
 #include <asm/mach/flash.h>
 
 #include <plat/led.h>
-#include <plat/usb.h>
 #include <plat/board.h>
 #include "common.h"
 #include <plat/gpmc.h>
@@ -253,13 +252,6 @@ out:
         clk_put(gpmc_fck);
 }
 
-static struct omap_usb_config apollon_usb_config __initdata = {
-        .register_dev   = 1,
-        .hmc_mode       = 0x14, /* 0:dev 1:host1 2:disable */
-
-        .pins[0]        = 6,
-};
-
 static struct panel_generic_dpi_data apollon_panel_data = {
         .name                   = "apollon",
 };
@@ -297,15 +289,6 @@ static void __init apollon_led_init(void)
         gpio_request_array(apollon_gpio_leds, ARRAY_SIZE(apollon_gpio_leds));
 }
 
-static void __init apollon_usb_init(void)
-{
-        /* USB device */
-        /* DEVICE_SUSPEND */
-        omap_mux_init_signal("mcbsp2_clkx.gpio_12", 0);
-        gpio_request_one(12, GPIOF_OUT_INIT_LOW, "USB suspend");
-        omap2_usbfs_init(&apollon_usb_config);
-}
-
 #ifdef CONFIG_OMAP_MUX
 static struct omap_board_mux board_mux[] __initdata = {
         { .reg_offset = OMAP_MUX_TERMINATOR },
@@ -321,7 +304,6 @@ static void __init omap_apollon_init(void)
         apollon_init_smc91x();
         apollon_led_init();
         apollon_flash_init();
-        apollon_usb_init();
 
         /* REVISIT: where's the correct place */
         omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 202934657867..2f2abfb82d84 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -112,6 +112,24 @@ DT_MACHINE_START(OMAP3_DT, "Generic OMAP3 (Flattened Device Tree)")
 MACHINE_END
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+static const char *am33xx_boards_compat[] __initdata = {
+        "ti,am33xx",
+        NULL,
+};
+
+DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
+        .reserve        = omap_reserve,
+        .map_io         = am33xx_map_io,
+        .init_early     = am33xx_init_early,
+        .init_irq       = omap_init_irq,
+        .handle_irq     = omap3_intc_handle_irq,
+        .init_machine   = omap_generic_init,
+        .timer          = &omap3_am33xx_timer,
+        .dt_compat      = am33xx_boards_compat,
+MACHINE_END
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 static const char *omap4_boards_compat[] __initdata = {
         "ti,omap4",
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 876becf8205a..ace20482e3e1 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -32,7 +32,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <plat/usb.h>
 #include <plat/board.h>
 #include "common.h"
 #include <plat/menelaus.h>
@@ -329,17 +328,6 @@ static void __init h4_init_flash(void)
         h4_flash_resource.end   = base + SZ_64M - 1;
 }
 
-static struct omap_usb_config h4_usb_config __initdata = {
-        /* S1.10 OFF -- usb "download port"
-         * usb0 switched to Mini-B port and isp1105 transceiver;
-         * S2.POS3 = ON, S2.POS4 = OFF ... to enable battery charging
-         */
-        .register_dev   = 1,
-        .pins[0]        = 3,
-/*      .hmc_mode       = 0x14,*/       /* 0:dev 1:host 2:disable */
-        .hmc_mode       = 0x00,         /* 0:dev|otg 1:disable 2:disable */
-};
-
 static struct at24_platform_data m24c01 = {
         .byte_len       = SZ_1K / 8,
         .page_size      = 16,
@@ -381,7 +369,6 @@ static void __init omap_h4_init(void)
                         ARRAY_SIZE(h4_i2c_board_info));
 
         platform_add_devices(h4_devices, ARRAY_SIZE(h4_devices));
-        omap2_usbfs_init(&h4_usb_config);
         omap_serial_init();
         omap_sdrc_init(NULL, NULL);
         h4_init_flash();
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 580fd17208da..6202fc76e490 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -433,7 +433,7 @@ static struct platform_device *omap3_beagle_devices[] __initdata = {
 
 static const struct usbhs_omap_board_data usbhs_bdata __initconst = {
 
-        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+        .port_mode[0] = OMAP_USBHS_PORT_MODE_UNUSED,
         .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
         .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 932e1778aff9..fca93d1afd43 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -93,9 +93,6 @@ static struct twl4030_usb_data omap3logic_usb_data = {
 
 
 static struct twl4030_platform_data omap3logic_twldata = {
-        .irq_base       = TWL4030_IRQ_BASE,
-        .irq_end        = TWL4030_IRQ_END,
-
         /* platform_data for children goes here */
         .gpio           = &omap3logic_gpio_data,
         .vmmc1          = &omap3logic_vmmc1,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 861767ed1a3a..002745181ad6 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1774,8 +1774,6 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_242X),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_242X),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
@@ -1784,8 +1782,6 @@ static struct omap_clk omap2420_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_242X),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 5577810dbc26..cacabb070e22 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1858,11 +1858,6 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
         CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_243X),
-        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_243X),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
         /* internal analog sources */
         CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
@@ -1871,11 +1866,6 @@ static struct omap_clk omap2430_clks[] = {
         /* internal prcm root sources */
         CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
         CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.3",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.4",     "prcm_fck",     &func_96m_ck,   CK_243X),
-        CLK("omap-mcbsp.5",     "prcm_fck",     &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
         CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
         CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 0d814620b69c..51f7430f6d3f 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -2490,13 +2490,13 @@ static struct clk uart4_fck = {
 };
 
 static struct clk uart4_fck_am35xx = {
-        .name           = "uart4_fck",
-        .ops            = &clkops_omap2_dflt_wait,
-        .parent         = &per_48m_fck,
-        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
-        .enable_bit     = OMAP3430_EN_UART4_SHIFT,
-        .clkdm_name     = "core_l4_clkdm",
-        .recalc         = &followparent_recalc,
+        .name           = "uart4_fck",
+        .ops            = &clkops_omap2_dflt_wait,
+        .parent         = &core_48m_fck,
+        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
+        .enable_bit     = AM35XX_EN_UART4_SHIFT,
+        .clkdm_name     = "core_l4_clkdm",
+        .recalc         = &followparent_recalc,
 };
 
 static struct clk gpt2_fck = {
@@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = {
 };
 
 /*
- * The UART1/2 functional clock acts as the functional
- * clock for UART4. No separate fclk control available.
+ * The UART1/2 functional clock acts as the functional clock for
+ * UART4. No separate fclk control available.  XXX Well now we have a
+ * uart4_fck that is apparently used as the UART4 functional clock,
+ * but it also seems that uart1_fck or uart2_fck are still needed, at
+ * least for UART4 softresets to complete.  This really needs
+ * clarification.
  */
 static struct clk uart4_ick_am35xx = {
         .name           = "uart4_ick",
@@ -3236,11 +3240,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
         CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
         CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
-        CLK("omap-mcbsp.1",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.2",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.3",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.4",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
-        CLK("omap-mcbsp.5",     "pad_fck",      &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
         CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
         CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
@@ -3307,8 +3306,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap-mcbsp.1",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
-        CLK("omap-mcbsp.5",     "prcm_fck",     &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3413,9 +3410,6 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
         CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
-        CLK("omap-mcbsp.2",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
-        CLK("omap-mcbsp.3",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
-        CLK("omap-mcbsp.4",     "prcm_fck",     &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
         CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
         CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
@@ -3474,12 +3468,12 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
-        CLK("davinci_emac",     NULL,   &emac_ick,      CK_AM35XX),
+        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK("musb-am35x",       "ick",          &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK("musb-am35x",       "fck",          &hsotgusb_fck_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
+        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
         CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index f7b58609bad8..5601dc13785e 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -31,12 +31,16 @@
  *
  * CLKDM_NO_AUTODEPS: Prevent "autodeps" from being added/removed from this
  *     clockdomain.  (Currently, this applies to OMAP3 clockdomains only.)
+ * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
+ *     active whenever the MPU is active.  True for interconnects and
+ *     the WKUP clockdomains.
  */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
 #define CLKDM_CAN_ENABLE_AUTO                   (1 << 2)
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
+#define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -195,6 +199,7 @@ int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
 extern void __init omap242x_clockdomains_init(void);
 extern void __init omap243x_clockdomains_init(void);
 extern void __init omap3xxx_clockdomains_init(void);
+extern void __init am33xx_clockdomains_init(void);
 extern void __init omap44xx_clockdomains_init(void);
 extern void _clkdm_add_autodeps(struct clockdomain *clkdm);
 extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
@@ -202,11 +207,10 @@ extern void _clkdm_del_autodeps(struct clockdomain *clkdm);
 extern struct clkdm_ops omap2_clkdm_operations;
 extern struct clkdm_ops omap3_clkdm_operations;
 extern struct clkdm_ops omap4_clkdm_operations;
+extern struct clkdm_ops am33xx_clkdm_operations;
 
 extern struct clkdm_dep gfx_24xx_wkdeps[];
 extern struct clkdm_dep dsp_24xx_wkdeps[];
 extern struct clockdomain wkup_common_clkdm;
-extern struct clockdomain prm_common_clkdm;
-extern struct clockdomain cm_common_clkdm;
 
 #endif
diff --git a/arch/arm/mach-omap2/clockdomain33xx.c b/arch/arm/mach-omap2/clockdomain33xx.c
new file mode 100644
index 000000000000..aca6388fad76
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomain33xx.c
@@ -0,0 +1,74 @@
+/*
+ * AM33XX clockdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Derived from mach-omap2/clockdomain44xx.c written by Rajendra Nayak
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+
+#include "clockdomain.h"
+#include "cm33xx.h"
+
+
+static int am33xx_clkdm_sleep(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_sleep(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static int am33xx_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_force_wakeup(clkdm->cm_inst, clkdm->clkdm_offs);
+        return 0;
+}
+
+static void am33xx_clkdm_allow_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_enable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static void am33xx_clkdm_deny_idle(struct clockdomain *clkdm)
+{
+        am33xx_cm_clkdm_disable_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+}
+
+static int am33xx_clkdm_clk_enable(struct clockdomain *clkdm)
+{
+        if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+                return am33xx_clkdm_wakeup(clkdm);
+
+        return 0;
+}
+
+static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm)
+{
+        bool hwsup = false;
+
+        hwsup = am33xx_cm_is_clkdm_in_hwsup(clkdm->cm_inst, clkdm->clkdm_offs);
+
+        if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+                am33xx_clkdm_sleep(clkdm);
+
+        return 0;
+}
+
+struct clkdm_ops am33xx_clkdm_operations = {
+        .clkdm_sleep            = am33xx_clkdm_sleep,
+        .clkdm_wakeup           = am33xx_clkdm_wakeup,
+        .clkdm_allow_idle       = am33xx_clkdm_allow_idle,
+        .clkdm_deny_idle        = am33xx_clkdm_deny_idle,
+        .clkdm_clk_enable       = am33xx_clkdm_clk_enable,
+        .clkdm_clk_disable      = am33xx_clkdm_clk_disable,
+};
diff --git a/arch/arm/mach-omap2/clockdomains2420_data.c b/arch/arm/mach-omap2/clockdomains2420_data.c
index 0ab8e46d5b2b..5c741852fac0 100644
--- a/arch/arm/mach-omap2/clockdomains2420_data.c
+++ b/arch/arm/mach-omap2/clockdomains2420_data.c
@@ -131,8 +131,6 @@ static struct clockdomain dss_2420_clkdm = {
 
 static struct clockdomain *clockdomains_omap242x[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
         &mpu_2420_clkdm,
         &iva1_2420_clkdm,
         &dsp_2420_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains2430_data.c b/arch/arm/mach-omap2/clockdomains2430_data.c
index 3645ed044890..f09617555e15 100644
--- a/arch/arm/mach-omap2/clockdomains2430_data.c
+++ b/arch/arm/mach-omap2/clockdomains2430_data.c
@@ -157,8 +157,6 @@ static struct clockdomain dss_2430_clkdm = {
 
 static struct clockdomain *clockdomains_omap243x[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
         &mpu_2430_clkdm,
         &mdm_clkdm,
         &dsp_2430_clkdm,
diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
index 839145e1cfbe..4972219653ce 100644
--- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c
@@ -88,4 +88,5 @@ struct clockdomain wkup_common_clkdm = {
         .name           = "wkup_clkdm",
         .pwrdm          = { .name = "wkup_pwrdm" },
         .dep_bit        = OMAP_EN_WKUP_SHIFT,
+        .flags          = CLKDM_ACTIVE_WITH_MPU,
 };
diff --git a/arch/arm/mach-omap2/clockdomains33xx_data.c b/arch/arm/mach-omap2/clockdomains33xx_data.c
new file mode 100644
index 000000000000..32c90fd9eba2
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains33xx_data.c
@@ -0,0 +1,196 @@
+/*
+ * AM33XX Clock Domain data.
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+
+#include "clockdomain.h"
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-33xx.h"
+
+static struct clockdomain l4ls_am33xx_clkdm = {
+        .name           = "l4ls_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3s_am33xx_clkdm = {
+        .name           = "l3s_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4fw_am33xx_clkdm = {
+        .name           = "l4fw_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_am33xx_clkdm = {
+        .name           = "l3_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4hs_am33xx_clkdm = {
+        .name           = "l4hs_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain ocpwp_l3_am33xx_clkdm = {
+        .name           = "ocpwp_l3_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain pruss_ocp_am33xx_clkdm = {
+        .name           = "pruss_ocp_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain cpsw_125mhz_am33xx_clkdm = {
+        .name           = "cpsw_125mhz_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain lcdc_am33xx_clkdm = {
+        .name           = "lcdc_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain clk_24mhz_am33xx_clkdm = {
+        .name           = "clk_24mhz_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .cm_inst        = AM33XX_CM_PER_MOD,
+        .clkdm_offs     = AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_am33xx_clkdm = {
+        .name           = "l4_wkup_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_WKUP_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l3_aon_am33xx_clkdm = {
+        .name           = "l3_aon_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_wkup_aon_am33xx_clkdm = {
+        .name           = "l4_wkup_aon_clkdm",
+        .pwrdm          = { .name = "wkup_pwrdm" },
+        .cm_inst        = AM33XX_CM_WKUP_MOD,
+        .clkdm_offs     = AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain mpu_am33xx_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .cm_inst        = AM33XX_CM_MPU_MOD,
+        .clkdm_offs     = AM33XX_CM_MPU_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_rtc_am33xx_clkdm = {
+        .name           = "l4_rtc_clkdm",
+        .pwrdm          = { .name = "rtc_pwrdm" },
+        .cm_inst        = AM33XX_CM_RTC_MOD,
+        .clkdm_offs     = AM33XX_CM_RTC_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l3_am33xx_clkdm = {
+        .name           = "gfx_l3_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .cm_inst        = AM33XX_CM_GFX_MOD,
+        .clkdm_offs     = AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain gfx_l4ls_gfx_am33xx_clkdm = {
+        .name           = "gfx_l4ls_gfx_clkdm",
+        .pwrdm          = { .name = "gfx_pwrdm" },
+        .cm_inst        = AM33XX_CM_GFX_MOD,
+        .clkdm_offs     = AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain l4_cefuse_am33xx_clkdm = {
+        .name           = "l4_cefuse_clkdm",
+        .pwrdm          = { .name = "cefuse_pwrdm" },
+        .cm_inst        = AM33XX_CM_CEFUSE_MOD,
+        .clkdm_offs     = AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET,
+        .flags          = CLKDM_CAN_SWSUP,
+};
+
+static struct clockdomain *clockdomains_am33xx[] __initdata = {
+        &l4ls_am33xx_clkdm,
+        &l3s_am33xx_clkdm,
+        &l4fw_am33xx_clkdm,
+        &l3_am33xx_clkdm,
+        &l4hs_am33xx_clkdm,
+        &ocpwp_l3_am33xx_clkdm,
+        &pruss_ocp_am33xx_clkdm,
+        &cpsw_125mhz_am33xx_clkdm,
+        &lcdc_am33xx_clkdm,
+        &clk_24mhz_am33xx_clkdm,
+        &l4_wkup_am33xx_clkdm,
+        &l3_aon_am33xx_clkdm,
+        &l4_wkup_aon_am33xx_clkdm,
+        &mpu_am33xx_clkdm,
+        &l4_rtc_am33xx_clkdm,
+        &gfx_l3_am33xx_clkdm,
+        &gfx_l4ls_gfx_am33xx_clkdm,
+        &l4_cefuse_am33xx_clkdm,
+        NULL,
+};
+
+void __init am33xx_clockdomains_init(void)
+{
+        clkdm_register_platform_funcs(&am33xx_clkdm_operations);
+        clkdm_register_clkdms(clockdomains_am33xx);
+        clkdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 6038adb97710..56089c49142a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -59,6 +59,12 @@ static struct clkdm_dep gfx_sgx_3xxx_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep gfx_sgx_am35x_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 static struct clkdm_dep per_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -69,6 +75,14 @@ static struct clkdm_dep per_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep per_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 static struct clkdm_dep usbhost_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -79,6 +93,14 @@ static struct clkdm_dep usbhost_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep usbhost_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 static struct clkdm_dep mpu_3xxx_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -89,6 +111,14 @@ static struct clkdm_dep mpu_3xxx_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep mpu_am35x_wkdeps[] = {
+        { .clkdm_name = "core_l3_clkdm" },
+        { .clkdm_name = "core_l4_clkdm" },
+        { .clkdm_name = "dss_clkdm" },
+        { .clkdm_name = "per_clkdm" },
+        { NULL },
+};
+
 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 static struct clkdm_dep iva2_wkdeps[] = {
         { .clkdm_name = "core_l3_clkdm" },
@@ -116,6 +146,12 @@ static struct clkdm_dep dss_wkdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep dss_am35x_wkdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { .clkdm_name = "wkup_clkdm" },
+        { NULL },
+};
+
 /* 3430: PM_WKDEP_NEON: MPU */
 static struct clkdm_dep neon_wkdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -131,6 +167,11 @@ static struct clkdm_dep dss_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep dss_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 static struct clkdm_dep per_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -138,6 +179,11 @@ static struct clkdm_dep per_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep per_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 static struct clkdm_dep usbhost_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -145,6 +191,11 @@ static struct clkdm_dep usbhost_sleepdeps[] = {
         { NULL },
 };
 
+static struct clkdm_dep usbhost_am35x_sleepdeps[] = {
+        { .clkdm_name = "mpu_clkdm" },
+        { NULL },
+};
+
 /* 3430: CM_SLEEPDEP_CAM: MPU */
 static struct clkdm_dep cam_sleepdeps[] = {
         { .clkdm_name = "mpu_clkdm" },
@@ -175,6 +226,15 @@ static struct clockdomain mpu_3xxx_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 };
 
+static struct clockdomain mpu_am35x_clkdm = {
+        .name           = "mpu_clkdm",
+        .pwrdm          = { .name = "mpu_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
+        .dep_bit        = OMAP3430_EN_MPU_SHIFT,
+        .wkdep_srcs     = mpu_am35x_wkdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
+};
+
 static struct clockdomain neon_clkdm = {
         .name           = "neon_clkdm",
         .pwrdm          = { .name = "neon_pwrdm" },
@@ -210,6 +270,15 @@ static struct clockdomain sgx_clkdm = {
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 };
 
+static struct clockdomain sgx_am35x_clkdm = {
+        .name           = "sgx_clkdm",
+        .pwrdm          = { .name = "sgx_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = gfx_sgx_am35x_wkdeps,
+        .sleepdep_srcs  = gfx_sgx_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
+};
+
 /*
  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
  * then that information was removed from the 34xx ES2+ TRM.  It is
@@ -261,6 +330,16 @@ static struct clockdomain dss_3xxx_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 };
 
+static struct clockdomain dss_am35x_clkdm = {
+        .name           = "dss_clkdm",
+        .pwrdm          = { .name = "dss_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
+        .wkdep_srcs     = dss_am35x_wkdeps,
+        .sleepdep_srcs  = dss_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
+};
+
 static struct clockdomain cam_clkdm = {
         .name           = "cam_clkdm",
         .pwrdm          = { .name = "cam_pwrdm" },
@@ -279,6 +358,15 @@ static struct clockdomain usbhost_clkdm = {
         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 };
 
+static struct clockdomain usbhost_am35x_clkdm = {
+        .name           = "usbhost_clkdm",
+        .pwrdm          = { .name = "core_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .wkdep_srcs     = usbhost_am35x_wkdeps,
+        .sleepdep_srcs  = usbhost_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
+};
+
 static struct clockdomain per_clkdm = {
         .name           = "per_clkdm",
         .pwrdm          = { .name = "per_pwrdm" },
@@ -289,6 +377,16 @@ static struct clockdomain per_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
+static struct clockdomain per_am35x_clkdm = {
+        .name           = "per_clkdm",
+        .pwrdm          = { .name = "per_pwrdm" },
+        .flags          = CLKDM_CAN_HWSUP_SWSUP,
+        .dep_bit        = OMAP3430_EN_PER_SHIFT,
+        .wkdep_srcs     = per_am35x_wkdeps,
+        .sleepdep_srcs  = per_am35x_sleepdeps,
+        .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
+};
+
 /*
  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
  * switched of even if sdti is in use
@@ -341,31 +439,42 @@ static struct clkdm_autodep clkdm_autodeps[] = {
         }
 };
 
+static struct clkdm_autodep clkdm_am35x_autodeps[] = {
+        {
+                .clkdm = { .name = "mpu_clkdm" },
+        },
+        {
+                .clkdm = { .name = NULL },
+        }
+};
+
 /*
  *
  */
 
-static struct clockdomain *clockdomains_omap3430_common[] __initdata = {
+static struct clockdomain *clockdomains_common[] __initdata = {
         &wkup_common_clkdm,
-        &cm_common_clkdm,
-        &prm_common_clkdm,
-        &mpu_3xxx_clkdm,
         &neon_clkdm,
-        &iva2_clkdm,
-        &d2d_clkdm,
         &core_l3_3xxx_clkdm,
         &core_l4_3xxx_clkdm,
-        &dss_3xxx_clkdm,
-        &cam_clkdm,
-        &per_clkdm,
         &emu_clkdm,
         &dpll1_clkdm,
-        &dpll2_clkdm,
         &dpll3_clkdm,
         &dpll4_clkdm,
         NULL
 };
 
+static struct clockdomain *clockdomains_omap3430[] __initdata = {
+        &mpu_3xxx_clkdm,
+        &iva2_clkdm,
+        &d2d_clkdm,
+        &dss_3xxx_clkdm,
+        &cam_clkdm,
+        &per_clkdm,
+        &dpll2_clkdm,
+        NULL
+};
+
 static struct clockdomain *clockdomains_omap3430es1[] __initdata = {
         &gfx_3430es1_clkdm,
         NULL,
@@ -378,21 +487,41 @@ static struct clockdomain *clockdomains_omap3430es2plus[] __initdata = {
         NULL,
 };
 
+static struct clockdomain *clockdomains_am35x[] __initdata = {
+        &mpu_am35x_clkdm,
+        &sgx_am35x_clkdm,
+        &dss_am35x_clkdm,
+        &per_am35x_clkdm,
+        &usbhost_am35x_clkdm,
+        &dpll5_clkdm,
+        NULL
+};
+
 void __init omap3xxx_clockdomains_init(void)
 {
         struct clockdomain **sc;
+        unsigned int rev;
 
         if (!cpu_is_omap34xx())
                 return;
 
         clkdm_register_platform_funcs(&omap3_clkdm_operations);
-        clkdm_register_clkdms(clockdomains_omap3430_common);
+        clkdm_register_clkdms(clockdomains_common);
 
-        sc = (omap_rev() == OMAP3430_REV_ES1_0) ? clockdomains_omap3430es1 :
-                clockdomains_omap3430es2plus;
+        rev = omap_rev();
 
-        clkdm_register_clkdms(sc);
+        if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
+                clkdm_register_clkdms(clockdomains_am35x);
+                clkdm_register_autodeps(clkdm_am35x_autodeps);
+        } else {
+                clkdm_register_clkdms(clockdomains_omap3430);
+
+                sc = (rev == OMAP3430_REV_ES1_0) ?
+                        clockdomains_omap3430es1 : clockdomains_omap3430es2plus;
+
+                clkdm_register_clkdms(sc);
+                clkdm_register_autodeps(clkdm_autodeps);
+        }
 
-        clkdm_register_autodeps(clkdm_autodeps);
         clkdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index c53425847493..63d60a773d3b 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -381,7 +381,7 @@ static struct clockdomain l4_wkup_44xx_clkdm = {
         .cm_inst          = OMAP4430_PRM_WKUP_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS,
         .dep_bit          = OMAP4430_L4WKUP_STATDEP_SHIFT,
-        .flags            = CLKDM_CAN_HWSUP,
+        .flags            = CLKDM_CAN_HWSUP | CLKDM_ACTIVE_WITH_MPU,
 };
 
 static struct clockdomain emu_sys_44xx_clkdm = {
@@ -430,8 +430,6 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
         &l4_wkup_44xx_clkdm,
         &emu_sys_44xx_clkdm,
         &l3_dma_44xx_clkdm,
-        &prm_common_clkdm,
-        &cm_common_clkdm,
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains_common_data.c b/arch/arm/mach-omap2/clockdomains_common_data.c
deleted file mode 100644
index 615b1f04967d..000000000000
--- a/arch/arm/mach-omap2/clockdomains_common_data.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * OMAP2+-common clockdomain data
- *
- * Copyright (C) 2008-2012 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
- *
- * Paul Walmsley, Jouni Högander
- */
-
-#include <linux/kernel.h>
-#include <linux/io.h>
-
-#include "clockdomain.h"
-
-/* These are implicit clockdomains - they are never defined as such in TRM */
-struct clockdomain prm_common_clkdm = {
-        .name           = "prm_clkdm",
-        .pwrdm          = { .name = "wkup_pwrdm" },
-};
-
-struct clockdomain cm_common_clkdm = {
-        .name           = "cm_clkdm",
-        .pwrdm          = { .name = "core_pwrdm" },
-};
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
new file mode 100644
index 000000000000..532027ee3d8d
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -0,0 +1,687 @@
+/*
+ * AM33XX Power Management register bits
+ *
+ * This file is automatically generated from the AM33XX hardware databases.
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_33XX_H
+
+/*
+ * Used by CM_AUTOIDLE_DPLL_CORE, CM_AUTOIDLE_DPLL_DDR, CM_AUTOIDLE_DPLL_DISP,
+ * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
+ */
+#define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
+
+/* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
+
+/* Used by CM_PER_CPSW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
+
+/* Used by CM_GFX_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
+
+/* Used by CM_PER_PRUSS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
+
+/* Used by CM_PER_L3S_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
+
+/* Used by CM_L3_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
+
+/* Used by CM_PER_L4FW_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
+
+/* Used by CM_PER_L4HS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
+
+/* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
+
+/* Used by CM_CEFUSE_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
+
+/* Used by CM_L4_WKUP_AON_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
+
+/* Used by CM_PER_LCDC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
+
+/* Used by CM_PER_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
+
+/* Used by CM_MPU_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
+
+/* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
+
+/* Used by CM_RTC_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
+
+/* Used by CM_PER_L4LS_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
+
+/* Used by CM_WKUP_CLKSTCTRL */
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2DIV_SHIFT                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
+
+/* Used by CM_CLKOUT_CTRL */
+#define AM33XX_CLKOUT2SOURCE_SHIFT                      0
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+
+/*
+ * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
+ * CLKSEL_TIMER3_CLK, CLKSEL_TIMER4_CLK, CLKSEL_TIMER5_CLK, CLKSEL_TIMER6_CLK,
+ * CLKSEL_TIMER7_CLK
+ */
+#define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_MASK                              (0x01 << 0)
+
+/*
+ * Renamed from CLKSEL Used by CLKSEL_PRUSS_OCP_CLK, CLKSEL_WDT1_CLK,
+ * CM_CPTS_RFT_CLKSEL
+ */
+#define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
+
+#define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
+
+/* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
+#define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
+
+/* Used by CLKSEL_GFX_FCLK */
+#define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
+
+/*
+ * Used by CM_MPU_CLKSTCTRL, CM_RTC_CLKSTCTRL, CM_PER_CLK_24MHZ_CLKSTCTRL,
+ * CM_PER_CPSW_CLKSTCTRL, CM_PER_PRUSS_CLKSTCTRL, CM_PER_L3S_CLKSTCTRL,
+ * CM_PER_L3_CLKSTCTRL, CM_PER_L4FW_CLKSTCTRL, CM_PER_L4HS_CLKSTCTRL,
+ * CM_PER_L4LS_CLKSTCTRL, CM_PER_LCDC_CLKSTCTRL, CM_PER_OCPWP_L3_CLKSTCTRL,
+ * CM_L3_AON_CLKSTCTRL, CM_L4_WKUP_AON_CLKSTCTRL, CM_WKUP_CLKSTCTRL,
+ * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
+ */
+#define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
+
+/*
+ * Used by CM_SSC_DELTAMSTEP_DPLL_CORE, CM_SSC_DELTAMSTEP_DPLL_DDR,
+ * CM_SSC_DELTAMSTEP_DPLL_DISP, CM_SSC_DELTAMSTEP_DPLL_MPU,
+ * CM_SSC_DELTAMSTEP_DPLL_PER
+ */
+#define AM33XX_DELTAMSTEP_SHIFT                         0
+#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+
+/* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
+#define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
+
+/* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+
+/* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
+
+/* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
+
+#define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
+
+/* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_DIV_0_7_SHIFT                       0
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
+
+/*
+ * Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP,
+ * CM_CLKSEL_DPLL_MPU
+ */
+#define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
+
+/* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU
+ */
+#define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
+
+/* Used by CM_CLKSEL_DPLL_PERIPH */
+#define AM33XX_DPLL_SD_DIV_SHIFT                        24
+#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
+
+/*
+ * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
+ * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ */
+#define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL,
+ * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_MASK                              (0x3 << 16)
+#define AM33XX_IDLEST_VAL                               0x3
+
+/* Used by CM_MAC_CLKSEL */
+#define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+
+/*
+ * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
+ * CM_SSC_MODFREQDIV_DPLL_DISP, CM_SSC_MODFREQDIV_DPLL_MPU,
+ * CM_SSC_MODFREQDIV_DPLL_PER
+ */
+#define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
+ * CM_PER_AES1_CLKCTRL, CM_PER_CLKDIV32K_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL,
+ * CM_PER_DCAN0_CLKCTRL, CM_PER_DCAN1_CLKCTRL, CM_PER_DES_CLKCTRL,
+ * CM_PER_ELM_CLKCTRL, CM_PER_EMIF_CLKCTRL, CM_PER_EMIF_FW_CLKCTRL,
+ * CM_PER_EPWMSS0_CLKCTRL, CM_PER_EPWMSS1_CLKCTRL, CM_PER_EPWMSS2_CLKCTRL,
+ * CM_PER_GPIO1_CLKCTRL, CM_PER_GPIO2_CLKCTRL, CM_PER_GPIO3_CLKCTRL,
+ * CM_PER_GPIO4_CLKCTRL, CM_PER_GPIO5_CLKCTRL, CM_PER_GPIO6_CLKCTRL,
+ * CM_PER_GPMC_CLKCTRL, CM_PER_I2C1_CLKCTRL, CM_PER_I2C2_CLKCTRL,
+ * CM_PER_PRUSS_CLKCTRL, CM_PER_IEEE5000_CLKCTRL, CM_PER_L3_CLKCTRL,
+ * CM_PER_L3_INSTR_CLKCTRL, CM_PER_L4FW_CLKCTRL, CM_PER_L4HS_CLKCTRL,
+ * CM_PER_L4LS_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MAILBOX0_CLKCTRL,
+ * CM_PER_MAILBOX1_CLKCTRL, CM_PER_MCASP0_CLKCTRL, CM_PER_MCASP1_CLKCTRL,
+ * CM_PER_MCASP2_CLKCTRL, CM_PER_MLB_CLKCTRL, CM_PER_MMC0_CLKCTRL,
+ * CM_PER_MMC1_CLKCTRL, CM_PER_MMC2_CLKCTRL, CM_PER_MSTR_EXPS_CLKCTRL,
+ * CM_PER_OCMCRAM_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_PKA_CLKCTRL, CM_PER_RNG_CLKCTRL, CM_PER_SHA0_CLKCTRL,
+ * CM_PER_SLV_EXPS_CLKCTRL, CM_PER_SPARE0_CLKCTRL, CM_PER_SPARE1_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_SPI0_CLKCTRL, CM_PER_SPI1_CLKCTRL,
+ * CM_PER_SPI2_CLKCTRL, CM_PER_SPI3_CLKCTRL, CM_PER_SPINLOCK_CLKCTRL,
+ * CM_PER_TIMER2_CLKCTRL, CM_PER_TIMER3_CLKCTRL, CM_PER_TIMER4_CLKCTRL,
+ * CM_PER_TIMER5_CLKCTRL, CM_PER_TIMER6_CLKCTRL, CM_PER_TIMER7_CLKCTRL,
+ * CM_PER_TPCC_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_UART1_CLKCTRL, CM_PER_UART2_CLKCTRL,
+ * CM_PER_UART3_CLKCTRL, CM_PER_UART4_CLKCTRL, CM_PER_UART5_CLKCTRL,
+ * CM_PER_USB0_CLKCTRL, CM_WKUP_ADC_TSC_CLKCTRL, CM_WKUP_CONTROL_CLKCTRL,
+ * CM_WKUP_DEBUGSS_CLKCTRL, CM_WKUP_GPIO0_CLKCTRL, CM_WKUP_I2C0_CLKCTRL,
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SMARTREFLEX0_CLKCTRL,
+ * CM_WKUP_SMARTREFLEX1_CLKCTRL, CM_WKUP_TIMER0_CLKCTRL,
+ * CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_UART0_CLKCTRL, CM_WKUP_WDT0_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL,
+ * CM_GFX_GFX_CLKCTRL, CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL,
+ * CM_CEFUSE_CEFUSE_CLKCTRL
+ */
+#define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
+
+/* Used by CM_WKUP_GPIO0_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
+
+/* Used by CM_PER_GPIO1_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO2_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO3_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO4_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO5_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
+
+/* Used by CM_PER_GPIO6_CLKCTRL */
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
+
+/*
+ * Used by CM_MPU_MPU_CLKCTRL, CM_PER_CPGMAC0_CLKCTRL, CM_PER_PRUSS_CLKCTRL,
+ * CM_PER_IEEE5000_CLKCTRL, CM_PER_LCDC_CLKCTRL, CM_PER_MLB_CLKCTRL,
+ * CM_PER_MSTR_EXPS_CLKCTRL, CM_PER_OCPWP_CLKCTRL, CM_PER_PCIE_CLKCTRL,
+ * CM_PER_SPARE_CLKCTRL, CM_PER_TPTC0_CLKCTRL, CM_PER_TPTC1_CLKCTRL,
+ * CM_PER_TPTC2_CLKCTRL, CM_PER_USB0_CLKCTRL, CM_WKUP_DEBUGSS_CLKCTRL,
+ * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
+ */
+#define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_MASK                              (1 << 18)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
+
+/* Used by CM_CLKDCOLDO_DPLL_PER */
+#define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
+
+/*
+ * Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU,
+ * CM_DIV_M2_DPLL_PER
+ */
+#define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
+
+/* Used by CM_DIV_M4_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
+
+/* Used by CM_DIV_M5_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
+
+/* Used by CM_DIV_M6_DPLL_CORE */
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
+
+/*
+ * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
+ * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
+ */
+#define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+
+/* Used by CM_WKUP_DEBUGSS_CLKCTRL */
+#define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+
+/* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
+#endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 8083a8cdc55f..766338fe4d34 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -169,8 +169,6 @@
 /* AM35XX specific CM_ICLKEN1_CORE bits */
 #define AM35XX_EN_IPSS_MASK                             (1 << 4)
 #define AM35XX_EN_IPSS_SHIFT                            4
-#define AM35XX_EN_UART4_MASK                            (1 << 23)
-#define AM35XX_EN_UART4_SHIFT                           23
 
 /* CM_ICLKEN2_CORE */
 #define OMAP3430_EN_PKA_MASK                            (1 << 4)
@@ -207,6 +205,8 @@
 #define OMAP3430_ST_DES2_MASK                           (1 << 26)
 #define OMAP3430_ST_MSPRO_SHIFT                         23
 #define OMAP3430_ST_MSPRO_MASK                          (1 << 23)
+#define AM35XX_ST_UART4_SHIFT                           23
+#define AM35XX_ST_UART4_MASK                            (1 << 23)
 #define OMAP3430_ST_HDQ_SHIFT                           22
 #define OMAP3430_ST_HDQ_MASK                            (1 << 22)
 #define OMAP3430ES1_ST_FAC_SHIFT                        8
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
new file mode 100644
index 000000000000..13f56eafef03
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -0,0 +1,313 @@
+/*
+ * AM33XX CM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Reference taken from from OMAP4 cminst44xx.c
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "cm.h"
+#include "cm33xx.h"
+#include "cm-regbits-34xx.h"
+#include "cm-regbits-33xx.h"
+#include "prm33xx.h"
+
+/*
+ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ *
+ *   0x0 func:     Module is fully functional, including OCP
+ *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
+ *                 abortion
+ *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
+ *                 using separate functional clock
+ *   0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+#define CLKCTRL_IDLEST_FUNCTIONAL               0x0
+#define CLKCTRL_IDLEST_INTRANSITION             0x1
+#define CLKCTRL_IDLEST_INTERFACE_IDLE           0x2
+#define CLKCTRL_IDLEST_DISABLED                 0x3
+
+/* Private functions */
+
+/* Read a register in a CM instance */
+static inline u32 am33xx_cm_read_reg(s16 inst, u16 idx)
+{
+        return __raw_readl(cm_base + inst + idx);
+}
+
+/* Write into a register in a CM */
+static inline void am33xx_cm_write_reg(u32 val, s16 inst, u16 idx)
+{
+        __raw_writel(val, cm_base + inst + idx);
+}
+
+/* Read-modify-write a register in CM */
+static inline u32 am33xx_cm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, idx);
+        v &= ~mask;
+        v |= bits;
+        am33xx_cm_write_reg(v, inst, idx);
+
+        return v;
+}
+
+static inline u32 am33xx_cm_set_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+        return am33xx_cm_rmw_reg_bits(bits, bits, inst, idx);
+}
+
+static inline u32 am33xx_cm_clear_reg_bits(u32 bits, s16 inst, s16 idx)
+{
+        return am33xx_cm_rmw_reg_bits(bits, 0x0, inst, idx);
+}
+
+static inline u32 am33xx_cm_read_reg_bits(u16 inst, s16 idx, u32 mask)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, idx);
+        v &= mask;
+        v >>= __ffs(mask);
+
+        return v;
+}
+
+/**
+ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ * bit 0.
+ */
+static u32 _clkctrl_idlest(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= AM33XX_IDLEST_MASK;
+        v >>= AM33XX_IDLEST_SHIFT;
+        return v;
+}
+
+/**
+ * _is_module_ready - can module registers be accessed without causing an abort?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ */
+static bool _is_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = _clkctrl_idlest(inst, cdoffs, clkctrl_offs);
+
+        return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+                v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+}
+
+/**
+ * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
+ * @c: CLKTRCTRL register bitfield (LSB = bit 0, i.e., unshifted)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * @c must be the unshifted value for CLKTRCTRL - i.e., this function
+ * will handle the shift itself.
+ */
+static void _clktrctrl_write(u8 c, s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, cdoffs);
+        v &= ~AM33XX_CLKTRCTRL_MASK;
+        v |= c << AM33XX_CLKTRCTRL_SHIFT;
+        am33xx_cm_write_reg(v, inst, cdoffs);
+}
+
+/* Public functions */
+
+/**
+ * am33xx_cm_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Returns true if the clockdomain referred to by (@inst, @cdoffs)
+ * is in hardware-supervised idle mode, or 0 otherwise.
+ */
+bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, cdoffs);
+        v &= AM33XX_CLKTRCTRL_MASK;
+        v >>= AM33XX_CLKTRCTRL_SHIFT;
+
+        return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? true : false;
+}
+
+/**
+ * am33xx_cm_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * hardware-supervised idle mode.  No return value.
+ */
+void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into
+ * software-supervised idle mode, i.e., controlled manually by the
+ * Linux OMAP clockdomain code.  No return value.
+ */
+void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_force_sleep - try to put a clockdomain into idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Put a clockdomain referred to by (@inst, @cdoffs) into idle
+ * No return value.
+ */
+void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, inst, cdoffs);
+}
+
+/**
+ * am33xx_cm_clkdm_force_wakeup - try to take a clockdomain out of idle
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ *
+ * Take a clockdomain referred to by (@inst, @cdoffs) out of idle,
+ * waking it up.  No return value.
+ */
+void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs)
+{
+        _clktrctrl_write(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, inst, cdoffs);
+}
+
+/*
+ *
+ */
+
+/**
+ * am33xx_cm_wait_module_ready - wait for a module to be in 'func' state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be functional. If the idle state is in any
+ * the non functional state (trans, idle or disabled), module and thus the
+ * sysconfig cannot be accessed and will probably lead to an "imprecise
+ * external abort"
+ */
+int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        int i = 0;
+
+        if (!clkctrl_offs)
+                return 0;
+
+        omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
+                          MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cm_wait_module_idle - wait for a module to be in 'disabled'
+ * state
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ * like reset assertion or parent clock de-activation must wait the
+ * module to be fully disabled.
+ */
+int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        int i = 0;
+
+        if (!clkctrl_offs)
+                return 0;
+
+        omap_test_timeout((_clkctrl_idlest(inst, cdoffs, clkctrl_offs) ==
+                                CLKCTRL_IDLEST_DISABLED),
+                                MAX_MODULE_READY_TIME, i);
+
+        return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * am33xx_cm_module_enable - Enable the modulemode inside CLKCTRL
+ * @mode: Module mode (SW or HW)
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= ~AM33XX_MODULEMODE_MASK;
+        v |= mode << AM33XX_MODULEMODE_SHIFT;
+        am33xx_cm_write_reg(v, inst, clkctrl_offs);
+}
+
+/**
+ * am33xx_cm_module_disable - Disable the module inside CLKCTRL
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void am33xx_cm_module_disable(u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_cm_read_reg(inst, clkctrl_offs);
+        v &= ~AM33XX_MODULEMODE_MASK;
+        am33xx_cm_write_reg(v, inst, clkctrl_offs);
+}
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
new file mode 100644
index 000000000000..5fa0b62e1a79
--- /dev/null
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -0,0 +1,420 @@
+/*
+ * AM33XX CM offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ * Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
+
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include "common.h"
+
+#include "cm.h"
+#include "cm-regbits-33xx.h"
+#include "cm33xx.h"
+
+/* CM base address */
+#define AM33XX_CM_BASE          0x44e00000
+
+#define AM33XX_CM_REGADDR(inst, reg)                            \
+        AM33XX_L4_WK_IO_ADDRESS(AM33XX_CM_BASE + (inst) + (reg))
+
+/* CM instances */
+#define AM33XX_CM_PER_MOD               0x0000
+#define AM33XX_CM_WKUP_MOD              0x0400
+#define AM33XX_CM_DPLL_MOD              0x0500
+#define AM33XX_CM_MPU_MOD               0x0600
+#define AM33XX_CM_DEVICE_MOD            0x0700
+#define AM33XX_CM_RTC_MOD               0x0800
+#define AM33XX_CM_GFX_MOD               0x0900
+#define AM33XX_CM_CEFUSE_MOD            0x0A00
+
+/* CM */
+
+/* CM.PER_CM register offsets */
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET             0x0000
+#define AM33XX_CM_PER_L4LS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000)
+#define AM33XX_CM_PER_L3S_CLKSTCTRL_OFFSET              0x0004
+#define AM33XX_CM_PER_L3S_CLKSTCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0004)
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL_OFFSET             0x0008
+#define AM33XX_CM_PER_L4FW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008)
+#define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET               0x000c
+#define AM33XX_CM_PER_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c)
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET            0x0014
+#define AM33XX_CM_PER_CPGMAC0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014)
+#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET               0x0018
+#define AM33XX_CM_PER_LCDC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018)
+#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET               0x001c
+#define AM33XX_CM_PER_USB0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c)
+#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET                0x0020
+#define AM33XX_CM_PER_MLB_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020)
+#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET              0x0024
+#define AM33XX_CM_PER_TPTC0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024)
+#define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET               0x0028
+#define AM33XX_CM_PER_EMIF_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028)
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET            0x002c
+#define AM33XX_CM_PER_OCMCRAM_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c)
+#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET               0x0030
+#define AM33XX_CM_PER_GPMC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030)
+#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET             0x0034
+#define AM33XX_CM_PER_MCASP0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034)
+#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET              0x0038
+#define AM33XX_CM_PER_UART5_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038)
+#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET               0x003c
+#define AM33XX_CM_PER_MMC0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c)
+#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET                0x0040
+#define AM33XX_CM_PER_ELM_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040)
+#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET               0x0044
+#define AM33XX_CM_PER_I2C2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044)
+#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET               0x0048
+#define AM33XX_CM_PER_I2C1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048)
+#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET               0x004c
+#define AM33XX_CM_PER_SPI0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c)
+#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET               0x0050
+#define AM33XX_CM_PER_SPI1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050)
+#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET               0x0054
+#define AM33XX_CM_PER_SPI2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054)
+#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET               0x0058
+#define AM33XX_CM_PER_SPI3_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058)
+#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET               0x0060
+#define AM33XX_CM_PER_L4LS_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060)
+#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET               0x0064
+#define AM33XX_CM_PER_L4FW_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064)
+#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET             0x0068
+#define AM33XX_CM_PER_MCASP1_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068)
+#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET              0x006c
+#define AM33XX_CM_PER_UART1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c)
+#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET              0x0070
+#define AM33XX_CM_PER_UART2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070)
+#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET              0x0074
+#define AM33XX_CM_PER_UART3_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074)
+#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET              0x0078
+#define AM33XX_CM_PER_UART4_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078)
+#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET             0x007c
+#define AM33XX_CM_PER_TIMER7_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c)
+#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET             0x0080
+#define AM33XX_CM_PER_TIMER2_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080)
+#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET             0x0084
+#define AM33XX_CM_PER_TIMER3_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084)
+#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET             0x0088
+#define AM33XX_CM_PER_TIMER4_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088)
+#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET             0x008c
+#define AM33XX_CM_PER_MCASP2_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c)
+#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET                0x0090
+#define AM33XX_CM_PER_RNG_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090)
+#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET               0x0094
+#define AM33XX_CM_PER_AES0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094)
+#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET               0x0098
+#define AM33XX_CM_PER_AES1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098)
+#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET                0x009c
+#define AM33XX_CM_PER_DES_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c)
+#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET               0x00a0
+#define AM33XX_CM_PER_SHA0_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0)
+#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET                0x00a4
+#define AM33XX_CM_PER_PKA_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4)
+#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET              0x00a8
+#define AM33XX_CM_PER_GPIO6_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8)
+#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET              0x00ac
+#define AM33XX_CM_PER_GPIO1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac)
+#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET              0x00b0
+#define AM33XX_CM_PER_GPIO2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0)
+#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET              0x00b4
+#define AM33XX_CM_PER_GPIO3_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4)
+#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET              0x00b8
+#define AM33XX_CM_PER_GPIO4_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8)
+#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET               0x00bc
+#define AM33XX_CM_PER_TPCC_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc)
+#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET              0x00c0
+#define AM33XX_CM_PER_DCAN0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0)
+#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET              0x00c4
+#define AM33XX_CM_PER_DCAN1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4)
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET            0x00cc
+#define AM33XX_CM_PER_EPWMSS1_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc)
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET            0x00d0
+#define AM33XX_CM_PER_EMIF_FW_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0)
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET            0x00d4
+#define AM33XX_CM_PER_EPWMSS0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4)
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET            0x00d8
+#define AM33XX_CM_PER_EPWMSS2_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8)
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET           0x00dc
+#define AM33XX_CM_PER_L3_INSTR_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc)
+#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET                 0x00e0
+#define AM33XX_CM_PER_L3_CLKCTRL                        AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0)
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET           0x00e4
+#define AM33XX_CM_PER_IEEE5000_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4)
+#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET              0x00e8
+#define AM33XX_CM_PER_PRUSS_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8)
+#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET             0x00ec
+#define AM33XX_CM_PER_TIMER5_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec)
+#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET             0x00f0
+#define AM33XX_CM_PER_TIMER6_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0)
+#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET               0x00f4
+#define AM33XX_CM_PER_MMC1_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4)
+#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET               0x00f8
+#define AM33XX_CM_PER_MMC2_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8)
+#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET              0x00fc
+#define AM33XX_CM_PER_TPTC1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc)
+#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET              0x0100
+#define AM33XX_CM_PER_TPTC2_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100)
+#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET              0x0104
+#define AM33XX_CM_PER_GPIO5_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104)
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET           0x010c
+#define AM33XX_CM_PER_SPINLOCK_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c)
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET           0x0110
+#define AM33XX_CM_PER_MAILBOX0_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110)
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET             0x011c
+#define AM33XX_CM_PER_L4HS_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c)
+#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET               0x0120
+#define AM33XX_CM_PER_L4HS_CLKCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120)
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET          0x0124
+#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124)
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET           0x0128
+#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128)
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET         0x012c
+#define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL                AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c)
+#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET              0x0130
+#define AM33XX_CM_PER_OCPWP_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130)
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET           0x0134
+#define AM33XX_CM_PER_MAILBOX1_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134)
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET            0x0140
+#define AM33XX_CM_PER_PRUSS_CLKSTCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140)
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET             0x0144
+#define AM33XX_CM_PER_CPSW_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144)
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET             0x0148
+#define AM33XX_CM_PER_LCDC_CLKSTCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148)
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET          0x014c
+#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c)
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET        0x0150
+#define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL               AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150)
+
+/* CM.WKUP_CM register offsets */
+#define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET                 0x0000
+#define AM33XX_CM_WKUP_CLKSTCTRL                        AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000)
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET           0x0004
+#define AM33XX_CM_WKUP_CONTROL_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004)
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET             0x0008
+#define AM33XX_CM_WKUP_GPIO0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008)
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET            0x000c
+#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c)
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET            0x0010
+#define AM33XX_CM_WKUP_TIMER0_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010)
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET           0x0014
+#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014)
+#define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET               0x0018
+#define AM33XX_CM_L3_AON_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018)
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET              0x001c
+#define AM33XX_CM_AUTOIDLE_DPLL_MPU                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c)
+#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET                0x0020
+#define AM33XX_CM_IDLEST_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET        0x0024
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET        0x0028
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028)
+#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET                0x002c
+#define AM33XX_CM_CLKSEL_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c)
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET              0x0030
+#define AM33XX_CM_AUTOIDLE_DPLL_DDR                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030)
+#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET                0x0034
+#define AM33XX_CM_IDLEST_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET        0x0038
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET        0x003c
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c)
+#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET                0x0040
+#define AM33XX_CM_CLKSEL_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040)
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET             0x0044
+#define AM33XX_CM_AUTOIDLE_DPLL_DISP                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044)
+#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET               0x0048
+#define AM33XX_CM_IDLEST_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET       0x004c
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET       0x0050
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050)
+#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET               0x0054
+#define AM33XX_CM_CLKSEL_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054)
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET             0x0058
+#define AM33XX_CM_AUTOIDLE_DPLL_CORE                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058)
+#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET               0x005c
+#define AM33XX_CM_IDLEST_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET       0x0060
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET       0x0064
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE              AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064)
+#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET               0x0068
+#define AM33XX_CM_CLKSEL_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068)
+#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET              0x006c
+#define AM33XX_CM_AUTOIDLE_DPLL_PER                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c)
+#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET                0x0070
+#define AM33XX_CM_IDLEST_DPLL_PER                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070)
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET        0x0074
+#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074)
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET        0x0078
+#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER               AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078)
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET             0x007c
+#define AM33XX_CM_CLKDCOLDO_DPLL_PER                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c)
+#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET               0x0080
+#define AM33XX_CM_DIV_M4_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080)
+#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET               0x0084
+#define AM33XX_CM_DIV_M5_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084)
+#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET               0x0088
+#define AM33XX_CM_CLKMODE_DPLL_MPU                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088)
+#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET               0x008c
+#define AM33XX_CM_CLKMODE_DPLL_PER                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c)
+#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET              0x0090
+#define AM33XX_CM_CLKMODE_DPLL_CORE                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090)
+#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET               0x0094
+#define AM33XX_CM_CLKMODE_DPLL_DDR                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094)
+#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET              0x0098
+#define AM33XX_CM_CLKMODE_DPLL_DISP                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098)
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET             0x009c
+#define AM33XX_CM_CLKSEL_DPLL_PERIPH                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c)
+#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET                0x00a0
+#define AM33XX_CM_DIV_M2_DPLL_DDR                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0)
+#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET               0x00a4
+#define AM33XX_CM_DIV_M2_DPLL_DISP                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4)
+#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET                0x00a8
+#define AM33XX_CM_DIV_M2_DPLL_MPU                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8)
+#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET                0x00ac
+#define AM33XX_CM_DIV_M2_DPLL_PER                       AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac)
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET           0x00b0
+#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0)
+#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET             0x00b4
+#define AM33XX_CM_WKUP_UART0_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4)
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET              0x00b8
+#define AM33XX_CM_WKUP_I2C0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8)
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET           0x00bc
+#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL                  AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc)
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET      0x00c0
+#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL             AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0)
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET            0x00c4
+#define AM33XX_CM_WKUP_TIMER1_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4)
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET      0x00c8
+#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL             AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8)
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET          0x00cc
+#define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc)
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET              0x00d0
+#define AM33XX_CM_WKUP_WDT0_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0)
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET              0x00d4
+#define AM33XX_CM_WKUP_WDT1_CLKCTRL                     AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4)
+#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET               0x00d8
+#define AM33XX_CM_DIV_M6_DPLL_CORE                      AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8)
+
+/* CM.DPLL_CM register offsets */
+#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET                 0x0004
+#define AM33XX_CLKSEL_TIMER7_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004)
+#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET                 0x0008
+#define AM33XX_CLKSEL_TIMER2_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008)
+#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET                 0x000c
+#define AM33XX_CLKSEL_TIMER3_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c)
+#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET                 0x0010
+#define AM33XX_CLKSEL_TIMER4_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010)
+#define AM33XX_CM_MAC_CLKSEL_OFFSET                     0x0014
+#define AM33XX_CM_MAC_CLKSEL                            AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014)
+#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET                 0x0018
+#define AM33XX_CLKSEL_TIMER5_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018)
+#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET                 0x001c
+#define AM33XX_CLKSEL_TIMER6_CLK                        AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c)
+#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET                0x0020
+#define AM33XX_CM_CPTS_RFT_CLKSEL                       AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020)
+#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET               0x0028
+#define AM33XX_CLKSEL_TIMER1MS_CLK                      AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028)
+#define AM33XX_CLKSEL_GFX_FCLK_OFFSET                   0x002c
+#define AM33XX_CLKSEL_GFX_FCLK                          AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c)
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET              0x0030
+#define AM33XX_CLKSEL_PRUSS_OCP_CLK                     AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030)
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET             0x0034
+#define AM33XX_CLKSEL_LCDC_PIXEL_CLK                    AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034)
+#define AM33XX_CLKSEL_WDT1_CLK_OFFSET                   0x0038
+#define AM33XX_CLKSEL_WDT1_CLK                          AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038)
+#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET                0x003c
+#define AM33XX_CLKSEL_GPIO0_DBCLK                       AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c)
+
+/* CM.MPU_CM register offsets */
+#define AM33XX_CM_MPU_CLKSTCTRL_OFFSET                  0x0000
+#define AM33XX_CM_MPU_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000)
+#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET                0x0004
+#define AM33XX_CM_MPU_MPU_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004)
+
+/* CM.DEVICE_CM register offsets */
+#define AM33XX_CM_CLKOUT_CTRL_OFFSET                    0x0000
+#define AM33XX_CM_CLKOUT_CTRL                           AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000)
+
+/* CM.RTC_CM register offsets */
+#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET                0x0000
+#define AM33XX_CM_RTC_RTC_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000)
+#define AM33XX_CM_RTC_CLKSTCTRL_OFFSET                  0x0004
+#define AM33XX_CM_RTC_CLKSTCTRL                         AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004)
+
+/* CM.GFX_CM register offsets */
+#define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET               0x0000
+#define AM33XX_CM_GFX_L3_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000)
+#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET                0x0004
+#define AM33XX_CM_GFX_GFX_CLKCTRL                       AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004)
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET             0x0008
+#define AM33XX_CM_GFX_BITBLT_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008)
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET      0x000c
+#define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1             AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c)
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET             0x0010
+#define AM33XX_CM_GFX_MMUCFG_CLKCTRL                    AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010)
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET            0x0014
+#define AM33XX_CM_GFX_MMUDATA_CLKCTRL                   AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014)
+
+/* CM.CEFUSE_CM register offsets */
+#define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET               0x0000
+#define AM33XX_CM_CEFUSE_CLKSTCTRL                      AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000)
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET          0x0020
+#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL                 AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
+
+
+extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_sleep(s16 inst, u16 cdoffs);
+extern void am33xx_cm_clkdm_force_wakeup(s16 inst, u16 cdoffs);
+
+#ifdef CONFIG_SOC_AM33XX
+extern int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+extern int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs);
+#else
+static inline int am33xx_cm_wait_module_idle(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+        return 0;
+}
+static inline void am33xx_cm_module_enable(u8 mode, u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+}
+static inline void am33xx_cm_module_disable(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+}
+static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
+                                        u16 clkctrl_offs)
+{
+        return 0;
+}
+#endif
+
+#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 1706ebcec08d..c1875862679f 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -63,28 +63,30 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
         struct spi_board_info *spi_bi = &ads7846_spi_board_info;
         int err;
 
-        if (board_pdata && board_pdata->get_pendown_state) {
-                err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
-                if (err) {
-                        pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
-                        return;
-                }
-                gpio_export(gpio_pendown, 0);
-
-                if (gpio_debounce)
-                        gpio_set_debounce(gpio_pendown, gpio_debounce);
+        err = gpio_request_one(gpio_pendown, GPIOF_IN, "TSPenDown");
+        if (err) {
+                pr_err("Couldn't obtain gpio for TSPenDown: %d\n", err);
+                return;
         }
 
+        if (gpio_debounce)
+                gpio_set_debounce(gpio_pendown, gpio_debounce);
+
         spi_bi->bus_num = bus_num;
         spi_bi->irq     = gpio_to_irq(gpio_pendown);
 
         if (board_pdata) {
                 board_pdata->gpio_pendown = gpio_pendown;
                 spi_bi->platform_data = board_pdata;
+                if (board_pdata->get_pendown_state)
+                        gpio_export(gpio_pendown, 0);
         } else {
                 ads7846_config.gpio_pendown = gpio_pendown;
         }
 
+        if (!board_pdata || (board_pdata && !board_pdata->get_pendown_state))
+                gpio_free(gpio_pendown);
+
         spi_register_board_info(&ads7846_spi_board_info, 1);
 }
 #else
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index be9dfd1abe60..5d99c1b2cb48 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -120,6 +120,7 @@ extern void omap2_init_common_infrastructure(void);
 extern struct sys_timer omap2_timer;
 extern struct sys_timer omap3_timer;
 extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap3_am33xx_timer;
 extern struct sys_timer omap4_timer;
 
 void omap2420_init_early(void);
@@ -128,8 +129,10 @@ void omap3430_init_early(void);
 void omap35xx_init_early(void);
 void omap3630_init_early(void);
 void omap3_init_early(void);    /* Do not use this one */
+void am33xx_init_early(void);
 void am35xx_init_early(void);
 void ti81xx_init_early(void);
+void am33xx_init_early(void);
 void omap4430_init_early(void);
 void omap3_init_late(void);     /* Do not use this one */
 void omap4430_init_late(void);
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index 08e674bb0417..3223b81e7532 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -241,6 +241,49 @@ void omap3_ctrl_write_boot_mode(u8 bootmode)
 
 #endif
 
+/**
+ * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor
+ * @bootaddr: physical address of the boot loader
+ *
+ * Set boot address for the boot loader of a supported processor
+ * when a power ON sequence occurs.
+ */
+void omap_ctrl_write_dsp_boot_addr(u32 bootaddr)
+{
+        u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR :
+                     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR :
+                     cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR :
+                     0;
+
+        if (!offset) {
+                pr_err("%s: unsupported omap type\n", __func__);
+                return;
+        }
+
+        omap_ctrl_writel(bootaddr, offset);
+}
+
+/**
+ * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor
+ * @bootmode: 8-bit value to pass to some boot code
+ *
+ * Sets boot mode for the boot loader of a supported processor
+ * when a power ON sequence occurs.
+ */
+void omap_ctrl_write_dsp_boot_mode(u8 bootmode)
+{
+        u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD :
+                     cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD :
+                     0;
+
+        if (!offset) {
+                pr_err("%s: unsupported omap type\n", __func__);
+                return;
+        }
+
+        omap_ctrl_writel(bootmode, offset);
+}
+
 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 /*
  * Clears the scratchpad contents in case of cold boot-
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index a406fd045ce1..5baf305386e9 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -21,6 +21,8 @@
 #include <mach/ctrl_module_pad_core_44xx.h>
 #include <mach/ctrl_module_pad_wkup_44xx.h>
 
+#include <plat/am33xx.h>
+
 #ifndef __ASSEMBLY__
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -28,6 +30,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                        \
+                AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #else
 #define OMAP242X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
@@ -35,6 +39,8 @@
                 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
 #define OMAP343X_CTRL_REGADDR(reg)                                      \
                 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
+#define AM33XX_CTRL_REGADDR(reg)                                        \
+                AM33XX_L4_WK_IO_ADDRESS(AM33XX_SCM_BASE + (reg))
 #endif /* __ASSEMBLY__ */
 
 /*
@@ -312,15 +318,15 @@
                                                 OMAP343X_SCRATCHPAD + reg)
 
 /* AM35XX_CONTROL_IPSS_CLK_CTRL bits */
-#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
-#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
-#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
-#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
-#define AM35XX_USBOTG_FCLK_SHIFT        8
-#define AM35XX_CPGMAC_FCLK_SHIFT        9
-#define AM35XX_VPFE_FCLK_SHIFT          10
-
-/*AM35XX CONTROL_LVL_INTR_CLEAR bits*/
+#define AM35XX_USBOTG_VBUSP_CLK_SHIFT   0
+#define AM35XX_CPGMAC_VBUSP_CLK_SHIFT   1
+#define AM35XX_VPFE_VBUSP_CLK_SHIFT     2
+#define AM35XX_HECC_VBUSP_CLK_SHIFT     3
+#define AM35XX_USBOTG_FCLK_SHIFT        8
+#define AM35XX_CPGMAC_FCLK_SHIFT        9
+#define AM35XX_VPFE_FCLK_SHIFT          10
+
+/* AM35XX CONTROL_LVL_INTR_CLEAR bits */
 #define AM35XX_CPGMAC_C0_MISC_PULSE_CLR BIT(0)
 #define AM35XX_CPGMAC_C0_RX_PULSE_CLR   BIT(1)
 #define AM35XX_CPGMAC_C0_RX_THRESH_CLR  BIT(2)
@@ -330,21 +336,22 @@
 #define AM35XX_VPFE_CCDC_VD1_INT_CLR    BIT(6)
 #define AM35XX_VPFE_CCDC_VD2_INT_CLR    BIT(7)
 
-/*AM35XX CONTROL_IP_SW_RESET bits*/
+/* AM35XX CONTROL_IP_SW_RESET bits */
 #define AM35XX_USBOTGSS_SW_RST          BIT(0)
 #define AM35XX_CPGMACSS_SW_RST          BIT(1)
 #define AM35XX_VPFE_VBUSP_SW_RST        BIT(2)
 #define AM35XX_HECC_SW_RST              BIT(3)
 #define AM35XX_VPFE_PCLK_SW_RST         BIT(4)
 
-/*
- * CONTROL AM33XX STATUS register
- */
+/* AM33XX CONTROL_STATUS register */
 #define AM33XX_CONTROL_STATUS           0x040
+#define AM33XX_CONTROL_SEC_CLK_CTRL     0x1bc
 
-/*
- * CONTROL OMAP STATUS register to identify OMAP3 features
- */
+/* AM33XX CONTROL_STATUS bitfields (partial) */
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
+
+/* CONTROL OMAP STATUS register to identify OMAP3 features */
 #define OMAP3_CONTROL_OMAP_STATUS       0x044c
 
 #define OMAP3_SGX_SHIFT                 13
@@ -397,6 +404,8 @@ extern u32 omap3_arm_context[128];
 extern void omap3_control_save_context(void);
 extern void omap3_control_restore_context(void);
 extern void omap3_ctrl_write_boot_mode(u8 bootmode);
+extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr);
+extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode);
 extern void omap3630_ctrl_disable_rta(void);
 extern int omap3_ctrl_save_padconf(void);
 #else
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index 207bc1c7759f..31344528eb54 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -36,8 +36,6 @@
 #include "control.h"
 #include "common.h"
 
-#ifdef CONFIG_CPU_IDLE
-
 /* Mach specific information to be recorded in the C-state driver_data */
 struct omap3_idle_statedata {
         u32 mpu_state;
@@ -379,9 +377,3 @@ int __init omap3_idle_init(void)
 
         return 0;
 }
-#else
-int __init omap3_idle_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index be1617ca84bd..02d15bbd4e35 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -22,8 +22,6 @@
 #include "pm.h"
 #include "prm.h"
 
-#ifdef CONFIG_CPU_IDLE
-
 /* Machine specific information */
 struct omap4_idle_statedata {
         u32 cpu_state;
@@ -199,9 +197,3 @@ int __init omap4_idle_init(void)
 
         return 0;
 }
-#else
-int __init omap4_idle_init(void)
-{
-        return 0;
-}
-#endif /* CONFIG_CPU_IDLE */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 7b4b9327e543..527c0046064d 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -772,7 +772,7 @@ static int __init omap_init_wdt(void)
         char *oh_name = "wd_timer2";
         char *dev_name = "omap_wdt";
 
-        if (!cpu_class_is_omap2())
+        if (!cpu_class_is_omap2() || of_have_populated_dt())
                 return 0;
 
         oh = omap_hwmod_lookup(oh_name);
diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c
index 88ffa1e645cd..a636ebc16b39 100644
--- a/arch/arm/mach-omap2/dsp.c
+++ b/arch/arm/mach-omap2/dsp.c
@@ -23,6 +23,7 @@
 
 #include <asm/memblock.h>
 
+#include "control.h"
 #include "cm2xxx_3xxx.h"
 #include "prm2xxx_3xxx.h"
 #ifdef CONFIG_BRIDGE_DVFS
@@ -46,6 +47,9 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = {
         .dsp_cm_read = omap2_cm_read_mod_reg,
         .dsp_cm_write = omap2_cm_write_mod_reg,
         .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits,
+
+        .set_bootaddr = omap_ctrl_write_dsp_boot_addr,
+        .set_bootmode = omap_ctrl_write_dsp_boot_mode,
 };
 
 static phys_addr_t omap_dsp_phys_mempool_base;
diff --git a/arch/arm/mach-omap2/include/mach/am35xx.h b/arch/arm/mach-omap2/include/mach/am35xx.h
index f1e13d1ca5e7..95594495fcf6 100644
--- a/arch/arm/mach-omap2/include/mach/am35xx.h
+++ b/arch/arm/mach-omap2/include/mach/am35xx.h
@@ -36,6 +36,8 @@
 #define AM35XX_EMAC_CNTRL_MOD_OFFSET    (0x0)
 #define AM35XX_EMAC_CNTRL_RAM_OFFSET    (0x20000)
 #define AM35XX_EMAC_MDIO_OFFSET         (0x30000)
+#define AM35XX_IPSS_MDIO_BASE           (AM35XX_IPSS_EMAC_BASE + \
+                                                AM35XX_EMAC_MDIO_OFFSET)
 #define AM35XX_EMAC_CNTRL_RAM_SIZE      (0x2000)
 #define AM35XX_EMAC_RAM_ADDR            (AM3517_EMAC_BASE + \
                                                 AM3517_EMAC_CNTRL_RAM_OFFSET)
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
index 2f7ac70a20d8..01970824e0e5 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_core_44xx.h
@@ -42,6 +42,7 @@
 #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1              0x0268
 #define OMAP4_CTRL_MODULE_CORE_STATUS                           0x02c4
 #define OMAP4_CTRL_MODULE_CORE_DEV_CONF                         0x0300
+#define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR                     0x0304
 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL          0x0314
 #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL          0x0318
 #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL         0x0320
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index cdfc2a1f0e75..d7f844a99a7b 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -72,6 +72,8 @@ omap_uart_lsr:	.word	0
                 beq     82f                     @ configure UART2
                 cmp     \rp, #TI81XXUART3       @ ti81Xx UART offsets different
                 beq     83f                     @ configure UART3
+                cmp     \rp, #AM33XXUART1       @ AM33XX UART offsets different
+                beq     84f                     @ configure UART1
                 cmp     \rp, #ZOOM_UART         @ only on zoom2/3
                 beq     95f                     @ configure ZOOM_UART
 
@@ -100,7 +102,9 @@ omap_uart_lsr:	.word	0
                 b       98f
 83:             mov     \rp, #UART_OFFSET(TI81XX_UART3_BASE)
                 b       98f
-
+84:             ldr     \rp, =AM33XX_UART1_BASE
+                and     \rp, \rp, #0x00ffffff
+                b       97f
 95:             ldr     \rp, =ZOOM_UART_BASE
                 str     \rp, [\tmp, #0]         @ omap_uart_phys
                 ldr     \rp, =ZOOM_UART_VIRT
@@ -109,6 +113,17 @@ omap_uart_lsr:	.word	0
                 str     \rp, [\tmp, #8]         @ omap_uart_lsr
                 b       10b
 
+                /* AM33XX: Store both phys and virt address for the uart */
+97:             add     \rp, \rp, #0x44000000   @ phys base
+                str     \rp, [\tmp, #0]         @ omap_uart_phys
+                sub     \rp, \rp, #0x44000000   @ phys base
+                add     \rp, \rp, #0xf9000000   @ virt base
+                str     \rp, [\tmp, #4]         @ omap_uart_virt
+                mov     \rp, #(UART_LSR << OMAP_PORT_SHIFT)
+                str     \rp, [\tmp, #8]         @ omap_uart_lsr
+
+                b       10b
+
                 /* Store both phys and virt address for the uart */
 98:             add     \rp, \rp, #0x48000000   @ phys base
                 str     \rp, [\tmp, #0]         @ omap_uart_phys
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 8d014ba04abc..cb6c11cd8df9 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -477,6 +477,19 @@ void __init ti81xx_init_late(void)
 }
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+void __init am33xx_init_early(void)
+{
+        omap2_set_globals_am33xx();
+        omap3xxx_check_revision();
+        ti81xx_check_features();
+        omap_common_init_early();
+        am33xx_voltagedomains_init();
+        am33xx_powerdomains_init();
+        am33xx_clockdomains_init();
+}
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 void __init omap4430_init_early(void)
 {
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 6038a8c84b74..a9c26b12cad2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -262,7 +262,7 @@ int __init omap_intc_of_init(struct device_node *node,
                              struct device_node *parent)
 {
         struct resource res;
-        u32 nr_irqs = 96;
+        u32 nr_irq = 96;
 
         if (WARN_ON(!node))
                 return -ENODEV;
@@ -272,15 +272,15 @@ int __init omap_intc_of_init(struct device_node *node,
                 return -EINVAL;
         }
 
-        if (of_property_read_u32(node, "ti,intc-size", &nr_irqs))
-                pr_warn("unable to get intc-size, default to %d\n", nr_irqs);
+        if (of_property_read_u32(node, "ti,intc-size", &nr_irq))
+                pr_warn("unable to get intc-size, default to %d\n", nr_irq);
 
-        omap_init_irq(res.start, nr_irqs, of_node_get(node));
+        omap_init_irq(res.start, nr_irq, of_node_get(node));
 
         return 0;
 }
 
-#ifdef CONFIG_ARCH_OMAP3
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM33XX)
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
 void omap_intc_save_context(void)
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 19b8b6774862..6875be837d9f 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -83,8 +83,6 @@ static int omap2_mbox_startup(struct omap_mbox *mbox)
         l = mbox_read_reg(MAILBOX_REVISION);
         pr_debug("omap mailbox rev %d.%d\n", (l & 0xf0) >> 4, (l & 0x0f));
 
-        omap2_mbox_enable_irq(mbox, IRQ_RX);
-
         return 0;
 }
 
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index ac49384d0285..1be8bcb52e93 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -73,19 +73,17 @@ static struct iommu_device omap4_devices[] = {
                         .da_end = 0xFFFFF000,
                 },
         },
-#if defined(CONFIG_MPU_TESLA_IOMMU)
         {
                 .base = OMAP4_MMU2_BASE,
-                .irq = INT_44XX_DSP_MMU,
+                .irq = OMAP44XX_IRQ_TESLA_MMU,
                 .pdata = {
                         .name = "tesla",
                         .nr_tlb_entries = 32,
-                        .clk_name = "tesla_ick",
+                        .clk_name = "dsp_fck",
                         .da_start = 0x0,
                         .da_end = 0xFFFFF000,
                 },
         },
-#endif
 };
 #define NR_OMAP4_IOMMU_DEVICES ARRAY_SIZE(omap4_devices)
 static struct platform_device *omap4_iommu_pdev[NR_OMAP4_IOMMU_DEVICES];
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 773193670ea2..bdc1ec2edb4d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -166,6 +166,31 @@
  */
 #define LINKS_PER_OCP_IF                2
 
+/**
+ * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations
+ * @enable_module: function to enable a module (via MODULEMODE)
+ * @disable_module: function to disable a module (via MODULEMODE)
+ *
+ * XXX Eventually this functionality will be hidden inside the PRM/CM
+ * device drivers.  Until then, this should avoid huge blocks of cpu_is_*()
+ * conditionals in this code.
+ */
+struct omap_hwmod_soc_ops {
+        void (*enable_module)(struct omap_hwmod *oh);
+        int (*disable_module)(struct omap_hwmod *oh);
+        int (*wait_target_ready)(struct omap_hwmod *oh);
+        int (*assert_hardreset)(struct omap_hwmod *oh,
+                                struct omap_hwmod_rst_info *ohri);
+        int (*deassert_hardreset)(struct omap_hwmod *oh,
+                                  struct omap_hwmod_rst_info *ohri);
+        int (*is_hardreset_asserted)(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri);
+        int (*init_clkdm)(struct omap_hwmod *oh);
+};
+
+/* soc_ops: adapts the omap_hwmod code to the currently-booted SoC */
+static struct omap_hwmod_soc_ops soc_ops;
+
 /* omap_hwmod_list contains all registered struct omap_hwmods */
 static LIST_HEAD(omap_hwmod_list);
 
@@ -186,6 +211,9 @@ static struct omap_hwmod_link *linkspace;
  */
 static unsigned short free_ls, max_ls, ls_supp;
 
+/* inited: set to true once the hwmod code is initialized */
+static bool inited;
+
 /* Private functions */
 
 /**
@@ -771,23 +799,19 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
 }
 
 /**
- * _enable_module - enable CLKCTRL modulemode on OMAP4
+ * _omap4_enable_module - enable CLKCTRL modulemode on OMAP4
  * @oh: struct omap_hwmod *
  *
  * Enables the PRCM module mode related to the hwmod @oh.
  * No return value.
  */
-static void _enable_module(struct omap_hwmod *oh)
+static void _omap4_enable_module(struct omap_hwmod *oh)
 {
-        /* The module mode does not exist prior OMAP4 */
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return;
-
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return;
 
-        pr_debug("omap_hwmod: %s: _enable_module: %d\n",
-                 oh->name, oh->prcm.omap4.modulemode);
+        pr_debug("omap_hwmod: %s: %s: %d\n",
+                 oh->name, __func__, oh->prcm.omap4.modulemode);
 
         omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
                                    oh->clkdm->prcm_partition,
@@ -807,10 +831,7 @@ static void _enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!cpu_is_omap44xx())
-                return 0;
-
-        if (!oh)
+        if (!oh || !oh->clkdm)
                 return -EINVAL;
 
         if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
@@ -1124,15 +1145,18 @@ static struct omap_hwmod_addr_space * __init _find_mpu_rt_addr_space(struct omap
  * _enable_sysc - try to bring a module out of idle via OCP_SYSCONFIG
  * @oh: struct omap_hwmod *
  *
- * If module is marked as SWSUP_SIDLE, force the module out of slave
- * idle; otherwise, configure it for smart-idle.  If module is marked
- * as SWSUP_MSUSPEND, force the module out of master standby;
- * otherwise, configure it for smart-standby.  No return value.
+ * Ensure that the OCP_SYSCONFIG register for the IP block represented
+ * by @oh is set to indicate to the PRCM that the IP block is active.
+ * Usually this means placing the module into smart-idle mode and
+ * smart-standby, but if there is a bug in the automatic idle handling
+ * for the IP block, it may need to be placed into the force-idle or
+ * no-idle variants of these modes.  No return value.
  */
 static void _enable_sysc(struct omap_hwmod *oh)
 {
         u8 idlemode, sf;
         u32 v;
+        bool clkdm_act;
 
         if (!oh->class->sysc)
                 return;
@@ -1141,8 +1165,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
         sf = oh->class->sysc->sysc_flags;
 
         if (sf & SYSC_HAS_SIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
-                        HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+                clkdm_act = ((oh->clkdm &&
+                              oh->clkdm->flags & CLKDM_ACTIVE_WITH_MPU) ||
+                             (oh->_clk && oh->_clk->clkdm &&
+                              oh->_clk->clkdm->flags & CLKDM_ACTIVE_WITH_MPU));
+                if (clkdm_act && !(oh->class->sysc->idlemodes &
+                                   (SIDLE_SMART | SIDLE_SMART_WKUP)))
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
+                                HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
                 _set_slave_idlemode(oh, idlemode, &v);
         }
 
@@ -1208,8 +1240,13 @@ static void _idle_sysc(struct omap_hwmod *oh)
         sf = oh->class->sysc->sysc_flags;
 
         if (sf & SYSC_HAS_SIDLEMODE) {
-                idlemode = (oh->flags & HWMOD_SWSUP_SIDLE) ?
-                        HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+                /* XXX What about HWMOD_IDLEMODE_SMART_WKUP? */
+                if (oh->flags & HWMOD_SWSUP_SIDLE ||
+                    !(oh->class->sysc->idlemodes &
+                      (SIDLE_SMART | SIDLE_SMART_WKUP)))
+                        idlemode = HWMOD_IDLEMODE_FORCE;
+                else
+                        idlemode = HWMOD_IDLEMODE_SMART;
                 _set_slave_idlemode(oh, idlemode, &v);
         }
 
@@ -1285,24 +1322,20 @@ static struct omap_hwmod *_lookup(const char *name)
 
         return oh;
 }
+
 /**
  * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
  * @oh: struct omap_hwmod *
  *
  * Convert a clockdomain name stored in a struct omap_hwmod into a
  * clockdomain pointer, and save it into the struct omap_hwmod.
- * return -EINVAL if clkdm_name does not exist or if the lookup failed.
+ * Return -EINVAL if the clkdm_name lookup failed.
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+        if (!oh->clkdm_name)
                 return 0;
 
-        if (!oh->clkdm_name) {
-                pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
-                return -EINVAL;
-        }
-
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
                 pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
@@ -1338,7 +1371,8 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
         ret |= _init_main_clk(oh);
         ret |= _init_interface_clks(oh);
         ret |= _init_opt_clks(oh);
-        ret |= _init_clkdm(oh);
+        if (soc_ops.init_clkdm)
+                ret |= soc_ops.init_clkdm(oh);
 
         if (!ret)
                 oh->_state = _HWMOD_STATE_CLKS_INITED;
@@ -1349,53 +1383,6 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
 }
 
 /**
- * _wait_target_ready - wait for a module to leave slave idle
- * @oh: struct omap_hwmod *
- *
- * Wait for a module @oh to leave slave idle.  Returns 0 if the module
- * does not have an IDLEST bit or if the module successfully leaves
- * slave idle; otherwise, pass along the return value of the
- * appropriate *_cm*_wait_module_ready() function.
- */
-static int _wait_target_ready(struct omap_hwmod *oh)
-{
-        struct omap_hwmod_ocp_if *os;
-        int ret;
-
-        if (!oh)
-                return -EINVAL;
-
-        if (oh->flags & HWMOD_NO_IDLEST)
-                return 0;
-
-        os = _find_mpu_rt_port(oh);
-        if (!os)
-                return 0;
-
-        /* XXX check module SIDLEMODE */
-
-        /* XXX check clock enable states */
-
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                ret = omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
-                                                 oh->prcm.omap2.idlest_reg_id,
-                                                 oh->prcm.omap2.idlest_idle_bit);
-        } else if (cpu_is_omap44xx()) {
-                if (!oh->clkdm)
-                        return -EINVAL;
-
-                ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
-                                                     oh->clkdm->cm_inst,
-                                                     oh->clkdm->clkdm_offs,
-                                                     oh->prcm.omap4.clkctrl_offs);
-        } else {
-                BUG();
-        };
-
-        return ret;
-}
-
-/**
  * _lookup_hardreset - fill register bit info for this hwmod/reset line
  * @oh: struct omap_hwmod *
  * @name: name of the reset line in the context of this hwmod
@@ -1431,32 +1418,31 @@ static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to lookup and assert
  *
- * Some IP like dsp, ipu or iva contain processor that require
- * an HW reset line to be assert / deassert in order to enable fully
- * the IP.
+ * Some IP like dsp, ipu or iva contain processor that require an HW
+ * reset line to be assert / deassert in order to enable fully the IP.
+ * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
+ * asserting the hardreset line on the currently-booted SoC, or passes
+ * along the return value from _lookup_hardreset() or the SoC's
+ * assert_hardreset code.
  */
 static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret;
+        u8 ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.assert_hardreset)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
-                return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
-                                                  ohri.rst_shift);
-        else if (cpu_is_omap44xx())
-                return omap4_prminst_assert_hardreset(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        else
-                return -EINVAL;
+        ret = soc_ops.assert_hardreset(oh, &ohri);
+
+        return ret;
 }
 
 /**
@@ -1465,38 +1451,29 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to look up and deassert
  *
- * Some IP like dsp, ipu or iva contain processor that require
- * an HW reset line to be assert / deassert in order to enable fully
- * the IP.
+ * Some IP like dsp, ipu or iva contain processor that require an HW
+ * reset line to be assert / deassert in order to enable fully the IP.
+ * Returns -EINVAL if @oh is null, -ENOSYS if we have no way of
+ * deasserting the hardreset line on the currently-booted SoC, or passes
+ * along the return value from _lookup_hardreset() or the SoC's
+ * deassert_hardreset code.
  */
 static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        int ret;
+        int ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.deassert_hardreset)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                ret = omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
-                                                   ohri.rst_shift,
-                                                   ohri.st_shift);
-        } else if (cpu_is_omap44xx()) {
-                if (ohri.st_shift)
-                        pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
-                               oh->name, name);
-                ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        } else {
-                return -EINVAL;
-        }
-
+        ret = soc_ops.deassert_hardreset(oh, &ohri);
         if (ret == -EBUSY)
                 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
@@ -1509,31 +1486,28 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
  * @oh: struct omap_hwmod *
  * @name: name of the reset line to look up and read
  *
- * Return the state of the reset line.
+ * Return the state of the reset line.  Returns -EINVAL if @oh is
+ * null, -ENOSYS if we have no way of reading the hardreset line
+ * status on the currently-booted SoC, or passes along the return
+ * value from _lookup_hardreset() or the SoC's is_hardreset_asserted
+ * code.
  */
 static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
-        u8 ret;
+        u8 ret = -EINVAL;
 
         if (!oh)
                 return -EINVAL;
 
+        if (!soc_ops.is_hardreset_asserted)
+                return -ENOSYS;
+
         ret = _lookup_hardreset(oh, name, &ohri);
         if (IS_ERR_VALUE(ret))
                 return ret;
 
-        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
-                return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
-                                                       ohri.st_shift);
-        } else if (cpu_is_omap44xx()) {
-                return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
-                                  oh->clkdm->pwrdm.ptr->prcm_partition,
-                                  oh->clkdm->pwrdm.ptr->prcm_offs,
-                                  oh->prcm.omap4.rstctrl_offs);
-        } else {
-                return -EINVAL;
-        }
+        return soc_ops.is_hardreset_asserted(oh, &ohri);
 }
 
 /**
@@ -1571,10 +1545,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
 {
         int v;
 
-        /* The module mode does not exist prior OMAP4 */
-        if (!cpu_is_omap44xx())
-                return -EINVAL;
-
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return -EINVAL;
 
@@ -1814,9 +1784,11 @@ static int _enable(struct omap_hwmod *oh)
         }
 
         _enable_clocks(oh);
-        _enable_module(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
 
-        r = _wait_target_ready(oh);
+        r = (soc_ops.wait_target_ready) ? soc_ops.wait_target_ready(oh) :
+                -EINVAL;
         if (!r) {
                 /*
                  * Set the clockdomain to HW_AUTO only if the target is ready,
@@ -1870,7 +1842,8 @@ static int _idle(struct omap_hwmod *oh)
                 _idle_sysc(oh);
         _del_initiator_dep(oh, mpu_oh);
 
-        _omap4_disable_module(oh);
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
 
         /*
          * The module must be in idle mode before disabling any parents
@@ -1975,7 +1948,8 @@ static int _shutdown(struct omap_hwmod *oh)
         if (oh->_state == _HWMOD_STATE_ENABLED) {
                 _del_initiator_dep(oh, mpu_oh);
                 /* XXX what about the other system initiators here? dma, dsp */
-                _omap4_disable_module(oh);
+                if (soc_ops.disable_module)
+                        soc_ops.disable_module(oh);
                 _disable_clocks(oh);
                 if (oh->clkdm)
                         clkdm_hwmod_disable(oh->clkdm, oh);
@@ -2431,6 +2405,194 @@ static int __init _alloc_linkspace(struct omap_hwmod_ocp_if **ois)
         return 0;
 }
 
+/* Static functions intended only for use in soc_ops field function pointers */
+
+/**
+ * _omap2_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap2_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status, enabled clocks */
+
+        return omap2_cm_wait_module_ready(oh->prcm.omap2.module_offs,
+                                          oh->prcm.omap2.idlest_reg_id,
+                                          oh->prcm.omap2.idlest_idle_bit);
+}
+
+/**
+ * _omap4_wait_target_ready - wait for a module to leave slave idle
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to leave slave idle.  Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully leaves
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_ready() function.
+ */
+static int _omap4_wait_target_ready(struct omap_hwmod *oh)
+{
+        if (!oh || !oh->clkdm)
+                return -EINVAL;
+
+        if (oh->flags & HWMOD_NO_IDLEST)
+                return 0;
+
+        if (!_find_mpu_rt_port(oh))
+                return 0;
+
+        /* XXX check module SIDLEMODE, hardreset status */
+
+        return omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+                                              oh->clkdm->cm_inst,
+                                              oh->clkdm->clkdm_offs,
+                                              oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _omap2_assert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_assert_hardreset() with parameters extracted from
+ * the hwmod @oh and the hardreset line data @ohri.  Only intended for
+ * use as an soc_ops function pointer.  Passes along the return value
+ * from omap2_prm_assert_hardreset().  XXX This function is scheduled
+ * for removal when the PRM code is moved into drivers/.
+ */
+static int _omap2_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
+                                          ohri->rst_shift);
+}
+
+/**
+ * _omap2_deassert_hardreset - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_deassert_hardreset() with parameters extracted from
+ * the hwmod @oh and the hardreset line data @ohri.  Only intended for
+ * use as an soc_ops function pointer.  Passes along the return value
+ * from omap2_prm_deassert_hardreset().  XXX This function is
+ * scheduled for removal when the PRM code is moved into drivers/.
+ */
+static int _omap2_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_deassert_hardreset(oh->prcm.omap2.module_offs,
+                                            ohri->rst_shift,
+                                            ohri->st_shift);
+}
+
+/**
+ * _omap2_is_hardreset_asserted - call OMAP2 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap2_prm_is_hardreset_asserted() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap2_prm_is_hardreset_asserted().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap2_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
+                                               ohri->st_shift);
+}
+
+/**
+ * _omap4_assert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to assert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_assert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap4_prminst_assert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap4_assert_hardreset(struct omap_hwmod *oh,
+                                   struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        return omap4_prminst_assert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _omap4_deassert_hardreset - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to deassert hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_deassert_hardreset() with parameters extracted
+ * from the hwmod @oh and the hardreset line data @ohri.  Only
+ * intended for use as an soc_ops function pointer.  Passes along the
+ * return value from omap4_prminst_deassert_hardreset().  XXX This
+ * function is scheduled for removal when the PRM code is moved into
+ * drivers/.
+ */
+static int _omap4_deassert_hardreset(struct omap_hwmod *oh,
+                                     struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        if (ohri->st_shift)
+                pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
+                       oh->name, ohri->name);
+        return omap4_prminst_deassert_hardreset(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
+/**
+ * _omap4_is_hardreset_asserted - call OMAP4 PRM hardreset fn with hwmod args
+ * @oh: struct omap_hwmod * to test hardreset
+ * @ohri: hardreset line data
+ *
+ * Call omap4_prminst_is_hardreset_asserted() with parameters
+ * extracted from the hwmod @oh and the hardreset line data @ohri.
+ * Only intended for use as an soc_ops function pointer.  Passes along
+ * the return value from omap4_prminst_is_hardreset_asserted().  XXX
+ * This function is scheduled for removal when the PRM code is moved
+ * into drivers/.
+ */
+static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh,
+                                        struct omap_hwmod_rst_info *ohri)
+{
+        if (!oh->clkdm)
+                return -EINVAL;
+
+        return omap4_prminst_is_hardreset_asserted(ohri->rst_shift,
+                                oh->clkdm->pwrdm.ptr->prcm_partition,
+                                oh->clkdm->pwrdm.ptr->prcm_offs,
+                                oh->prcm.omap4.rstctrl_offs);
+}
+
 /* Public functions */
 
 u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs)
@@ -2563,12 +2725,18 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
  *
  * Intended to be called early in boot before the clock framework is
  * initialized.  If @ois is not null, will register all omap_hwmods
- * listed in @ois that are valid for this chip.  Returns 0.
+ * listed in @ois that are valid for this chip.  Returns -EINVAL if
+ * omap_hwmod_init() hasn't been called before calling this function,
+ * -ENOMEM if the link memory area can't be allocated, or 0 upon
+ * success.
  */
 int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois)
 {
         int r, i;
 
+        if (!inited)
+                return -EINVAL;
+
         if (!ois)
                 return 0;
 
@@ -3401,3 +3569,32 @@ int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx)
 
         return 0;
 }
+
+/**
+ * omap_hwmod_init - initialize the hwmod code
+ *
+ * Sets up some function pointers needed by the hwmod code to operate on the
+ * currently-booted SoC.  Intended to be called once during kernel init
+ * before any hwmods are registered.  No return value.
+ */
+void __init omap_hwmod_init(void)
+{
+        if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
+                soc_ops.wait_target_ready = _omap2_wait_target_ready;
+                soc_ops.assert_hardreset = _omap2_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap2_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap2_is_hardreset_asserted;
+        } else if (cpu_is_omap44xx()) {
+                soc_ops.enable_module = _omap4_enable_module;
+                soc_ops.disable_module = _omap4_disable_module;
+                soc_ops.wait_target_ready = _omap4_wait_target_ready;
+                soc_ops.assert_hardreset = _omap4_assert_hardreset;
+                soc_ops.deassert_hardreset = _omap4_deassert_hardreset;
+                soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted;
+                soc_ops.init_clkdm = _init_clkdm;
+        } else {
+                WARN(1, "omap_hwmod: unknown SoC type\n");
+        }
+
+        inited = true;
+}
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a7640d1b215e..50cfab61b0e2 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -192,6 +192,11 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
         .name = "mcbsp",
 };
 
+static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "func_96m_ck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
         { .name = "tx", .irq = 59 },
@@ -214,6 +219,8 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp2 */
@@ -238,6 +245,8 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 static struct omap_hwmod_class_sysconfig omap2420_msdi_sysc = {
@@ -585,5 +594,6 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap2420_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4d7264981230..58b5bc196d32 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -296,6 +296,11 @@ static struct omap_hwmod_class omap2430_mcbsp_hwmod_class = {
         .rev  = MCBSP_CONFIG_TYPE2,
 };
 
+static struct omap_hwmod_opt_clk mcbsp_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "func_96m_ck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
         { .name = "tx",         .irq = 59 },
@@ -320,6 +325,8 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp2 */
@@ -345,6 +352,8 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp3 */
@@ -370,6 +379,8 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp4 */
@@ -401,6 +412,8 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* mcbsp5 */
@@ -432,6 +445,8 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp_opt_clks),
 };
 
 /* MMC/SD/SDIO common */
@@ -938,5 +953,6 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap2430_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap2430_hwmod_ocp_ifs);
 }
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 0ea53bcc7d18..cdb9637aab19 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -519,11 +519,27 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
 
 static struct omap_hwmod_irq_info am35xx_uart4_mpu_irqs[] = {
         { .irq = INT_35XX_UART4_IRQ, },
+        { .irq = -1 }
 };
 
 static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
         { .name = "rx", .dma_req = AM35XX_DMA_UART4_RX, },
         { .name = "tx", .dma_req = AM35XX_DMA_UART4_TX, },
+        { .dma_req = -1 }
+};
+
+/*
+ * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
+ * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
+ * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
+ * should not be needed.  The functional clock structure of the AM35xx
+ * UART4 is extremely unclear and opaque; it is unclear what the role
+ * of uart1/2_fck is for the UART4.  Any clarification from either
+ * empirical testing or the AM3505/3517 hardware designers would be
+ * most welcome.
+ */
+static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
+        { .role = "softreset_uart1_fck", .clk = "uart1_fck" },
 };
 
 static struct omap_hwmod am35xx_uart4_hwmod = {
@@ -535,11 +551,14 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
                 .omap2 = {
                         .module_offs = CORE_MOD,
                         .prcm_reg_id = 1,
-                        .module_bit = OMAP3430_EN_UART4_SHIFT,
+                        .module_bit = AM35XX_EN_UART4_SHIFT,
                         .idlest_reg_id = 1,
-                        .idlest_idle_bit = OMAP3430_EN_UART4_SHIFT,
+                        .idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
                 },
         },
+        .opt_clks       = am35xx_uart4_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(am35xx_uart4_opt_clks),
+        .flags          = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
         .class          = &omap2_uart_class,
 };
 
@@ -1066,6 +1085,17 @@ static struct omap_hwmod_class omap3xxx_mcbsp_hwmod_class = {
         .rev  = MCBSP_CONFIG_TYPE3,
 };
 
+/* McBSP functional clock mapping */
+static struct omap_hwmod_opt_clk mcbsp15_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "core_96m_fck" },
+};
+
+static struct omap_hwmod_opt_clk mcbsp234_opt_clks[] = {
+        { .role = "pad_fck", .clk = "mcbsp_clks" },
+        { .role = "prcm_fck", .clk = "per_96m_fck" },
+};
+
 /* mcbsp1 */
 static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
         { .name = "common", .irq = 16 },
@@ -1089,6 +1119,8 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp15_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 };
 
 /* mcbsp2 */
@@ -1118,6 +1150,8 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
         .dev_attr       = &omap34xx_mcbsp2_dev_attr,
 };
 
@@ -1148,6 +1182,8 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
         .dev_attr       = &omap34xx_mcbsp3_dev_attr,
 };
 
@@ -1180,6 +1216,8 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp234_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp234_opt_clks),
 };
 
 /* mcbsp5 */
@@ -1211,6 +1249,8 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
                 },
         },
+        .opt_clks       = mcbsp15_opt_clks,
+        .opt_clks_cnt   = ARRAY_SIZE(mcbsp15_opt_clks),
 };
 
 /* 'mcbsp sidetone' class */
@@ -1630,25 +1670,20 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
 
 /* usb_otg_hs */
 static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
-
         { .name = "mc", .irq = 71 },
         { .irq = -1 }
 };
 
 static struct omap_hwmod_class am35xx_usbotg_class = {
         .name = "am35xx_usbotg",
-        .sysc = NULL,
 };
 
 static struct omap_hwmod am35xx_usbhsotg_hwmod = {
         .name           = "am35x_otg_hs",
         .mpu_irqs       = am35xx_usbhsotg_mpu_irqs,
-        .main_clk       = NULL,
-        .prcm = {
-                .omap2 = {
-                },
-        },
+        .main_clk       = "hsotgusb_fck",
         .class          = &am35xx_usbotg_class,
+        .flags          = HWMOD_NO_IDLEST,
 };
 
 /* MMC/SD/SDIO common */
@@ -2089,9 +2124,10 @@ static struct omap_hwmod_ocp_if omap3xxx_usbhsotg__l3 = {
 static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
         .master         = &am35xx_usbhsotg_hwmod,
         .slave          = &omap3xxx_l3_main_hwmod,
-        .clk            = "core_l3_ick",
+        .clk            = "hsotgusb_ick",
         .user           = OCP_USER_MPU,
 };
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -2235,6 +2271,7 @@ static struct omap_hwmod_addr_space am35xx_uart4_addr_space[] = {
                 .pa_end         = OMAP3_UART4_AM35XX_BASE + SZ_1K - 1,
                 .flags          = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
         },
+        { }
 };
 
 static struct omap_hwmod_ocp_if am35xx_l4_core__uart4 = {
@@ -2385,7 +2422,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
 static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
         .master         = &omap3xxx_l4_core_hwmod,
         .slave          = &am35xx_usbhsotg_hwmod,
-        .clk            = "l4_ick",
+        .clk            = "hsotgusb_ick",
         .addr           = am35xx_usbhsotg_addrs,
         .user           = OCP_USER_MPU,
 };
@@ -3130,6 +3167,107 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* am35xx has Davinci MDIO & EMAC */
+static struct omap_hwmod_class am35xx_mdio_class = {
+        .name = "davinci_mdio",
+};
+
+static struct omap_hwmod am35xx_mdio_hwmod = {
+        .name           = "davinci_mdio",
+        .class          = &am35xx_mdio_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L3 directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_mdio__l3 = {
+        .master         = &am35xx_mdio_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "emac_fck",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am35xx_mdio_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_MDIO_BASE,
+                .pa_end         = AM35XX_IPSS_MDIO_BASE + SZ_4K - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> davinci mdio  */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_l4_core__mdio = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_mdio_hwmod,
+        .clk            = "emac_fck",
+        .addr           = am35xx_mdio_addrs,
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_irq_info am35xx_emac_mpu_irqs[] = {
+        { .name = "rxthresh",   .irq = INT_35XX_EMAC_C0_RXTHRESH_IRQ },
+        { .name = "rx_pulse",   .irq = INT_35XX_EMAC_C0_RX_PULSE_IRQ },
+        { .name = "tx_pulse",   .irq = INT_35XX_EMAC_C0_TX_PULSE_IRQ },
+        { .name = "misc_pulse", .irq = INT_35XX_EMAC_C0_MISC_PULSE_IRQ },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_class am35xx_emac_class = {
+        .name = "davinci_emac",
+};
+
+static struct omap_hwmod am35xx_emac_hwmod = {
+        .name           = "davinci_emac",
+        .mpu_irqs       = am35xx_emac_mpu_irqs,
+        .class          = &am35xx_emac_class,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+/* l3_core -> davinci emac interface */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L3 directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_emac__l3 = {
+        .master         = &am35xx_emac_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "emac_ick",
+        .user           = OCP_USER_MPU,
+};
+
+static struct omap_hwmod_addr_space am35xx_emac_addrs[] = {
+        {
+                .pa_start       = AM35XX_IPSS_EMAC_BASE,
+                .pa_end         = AM35XX_IPSS_EMAC_BASE + 0x30000 - 1,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> davinci emac  */
+/*
+ * XXX Should be connected to an IPSS hwmod, not the L4_CORE directly;
+ * but this will probably require some additional hwmod core support,
+ * so is left as a future to-do item.
+ */
+static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &am35xx_emac_hwmod,
+        .clk            = "emac_ick",
+        .addr           = am35xx_emac_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
@@ -3258,6 +3396,10 @@ static struct omap_hwmod_ocp_if *am35xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__usb_tll_hs,
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
+        &am35xx_mdio__l3,
+        &am35xx_l4_core__mdio,
+        &am35xx_emac__l3,
+        &am35xx_l4_core__emac,
         NULL
 };
 
@@ -3275,6 +3417,8 @@ int __init omap3xxx_hwmod_init(void)
         struct omap_hwmod_ocp_if **h = NULL;
         unsigned int rev;
 
+        omap_hwmod_init();
+
         /* Register hwmod links common to all OMAP3 */
         r = omap_hwmod_register_links(omap3xxx_hwmod_ocp_ifs);
         if (r < 0)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index dfe9bc4d7b80..5c2ce7e77838 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2544,14 +2544,12 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
         .name           = "cm_core_aon",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "cm_clkdm",
 };
 
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
         .name           = "cm_core",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "cm_clkdm",
 };
 
 /* prm */
@@ -2568,7 +2566,6 @@ static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
 static struct omap_hwmod omap44xx_prm_hwmod = {
         .name           = "prm",
         .class          = &omap44xx_prcm_hwmod_class,
-        .clkdm_name     = "prm_clkdm",
         .mpu_irqs       = omap44xx_prm_irqs,
         .rst_lines      = omap44xx_prm_resets,
         .rst_lines_cnt  = ARRAY_SIZE(omap44xx_prm_resets),
@@ -6142,6 +6139,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
 
 int __init omap44xx_hwmod_init(void)
 {
+        omap_hwmod_init();
         return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
 }
 
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index de6d46451746..d8f6dbf45d16 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -53,7 +53,7 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
         omap_table_init = 1;
 
         /* Lets now register with OPP library */
-        for (i = 0; i < opp_def_size; i++) {
+        for (i = 0; i < opp_def_size; i++, opp_def++) {
                 struct omap_hwmod *oh;
                 struct device *dev;
 
@@ -86,7 +86,6 @@ int __init omap_init_opp_table(struct omap_opp_def *opp_def,
                                         __func__, opp_def->freq,
                                         opp_def->hwmod_name, i, r);
                 }
-                opp_def++;
         }
 
         return 0;
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 78564895e914..ab04d3bba2e7 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -15,12 +15,25 @@
 
 #include "powerdomain.h"
 
+#ifdef CONFIG_CPU_IDLE
+extern int __init omap3_idle_init(void);
+extern int __init omap4_idle_init(void);
+#else
+static inline int omap3_idle_init(void)
+{
+        return 0;
+}
+
+static inline int omap4_idle_init(void)
+{
+        return 0;
+}
+#endif
+
 extern void *omap3_secure_ram_storage;
 extern void omap3_pm_off_mode_enable(int);
 extern void omap_sram_idle(void);
 extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state);
-extern int omap3_idle_init(void);
-extern int omap4_idle_init(void);
 extern int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused);
 extern int (*omap_pm_suspend)(void);
 
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 3a595e899724..9b463c987508 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -581,10 +581,13 @@ static void __init prcm_setup_regs(void)
                           OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
 
         /* Don't attach IVA interrupts */
-        omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
-        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
-        omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
-        omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
+        if (omap3_has_iva()) {
+                omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
+                omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
+                omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD,
+                                        OMAP3430_PM_IVAGRPSEL);
+        }
 
         /* Clear any pending 'reset' flags */
         omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
@@ -598,7 +601,9 @@ static void __init prcm_setup_regs(void)
         /* Clear any pending PRCM interrupts */
         omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
 
-        omap3_iva_idle();
+        if (omap3_has_iva())
+                omap3_iva_idle();
+
         omap3_d2d_idle();
 }
 
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index 8f88d65c46ea..a8a95184243d 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -67,9 +67,9 @@
 
 /*
  * Maximum number of clockdomains that can be associated with a powerdomain.
- * CORE powerdomain on OMAP4 is the worst case
+ * PER powerdomain on AM33XX is the worst case
  */
-#define PWRDM_MAX_CLKDMS        9
+#define PWRDM_MAX_CLKDMS        11
 
 /* XXX A completely arbitrary number. What is reasonable here? */
 #define PWRDM_TRANSITION_BAILOUT 100000
@@ -92,6 +92,15 @@ struct powerdomain;
  * @pwrdm_clkdms: Clockdomains in this powerdomain
  * @node: list_head linking all powerdomains
  * @voltdm_node: list_head linking all powerdomains in a voltagedomain
+ * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
+ * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
+ * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
+ *      in @pwrstctrl_offs
+ * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
+ * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
+ * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
+ * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
+ *      in @pwrstctrl_offs
  * @state:
  * @state_counter:
  * @timer:
@@ -121,6 +130,14 @@ struct powerdomain {
         unsigned ret_logic_off_counter;
         unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
 
+        const u8 pwrstctrl_offs;
+        const u8 pwrstst_offs;
+        const u32 logicretstate_mask;
+        const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
+        const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
+
 #ifdef CONFIG_PM_DEBUG
         s64 timer;
         s64 state_timer[PWRDM_MAX_PWRSTS];
@@ -222,10 +239,12 @@ bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
 extern void omap242x_powerdomains_init(void);
 extern void omap243x_powerdomains_init(void);
 extern void omap3xxx_powerdomains_init(void);
+extern void am33xx_powerdomains_init(void);
 extern void omap44xx_powerdomains_init(void);
 
 extern struct pwrdm_ops omap2_pwrdm_operations;
 extern struct pwrdm_ops omap3_pwrdm_operations;
+extern struct pwrdm_ops am33xx_pwrdm_operations;
 extern struct pwrdm_ops omap4_pwrdm_operations;
 
 /* Common Internal functions used across OMAP rev's */
diff --git a/arch/arm/mach-omap2/powerdomain33xx.c b/arch/arm/mach-omap2/powerdomain33xx.c
new file mode 100644
index 000000000000..67c5663899b6
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomain33xx.c
@@ -0,0 +1,229 @@
+/*
+ * AM33XX Powerdomain control
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Derived from mach-omap2/powerdomain44xx.c written by Rajendra Nayak
+ * <rnayak@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+
+#include <plat/prcm.h>
+
+#include "powerdomain.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+
+static int am33xx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        am33xx_prm_rmw_reg_bits(OMAP_POWERSTATE_MASK,
+                                (pwrst << OMAP_POWERSTATE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs,  pwrdm->pwrstctrl_offs);
+        v &= OMAP_POWERSTATE_MASK;
+        v >>= OMAP_POWERSTATE_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= OMAP_POWERSTATEST_MASK;
+        v >>= OMAP_POWERSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LASTPOWERSTATEENTERED_MASK;
+        v >>= AM33XX_LASTPOWERSTATEENTERED_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LOWPOWERSTATECHANGE_MASK,
+                                (1 << AM33XX_LOWPOWERSTATECHANGE_SHIFT),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm)
+{
+        am33xx_prm_rmw_reg_bits(AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                AM33XX_LASTPOWERSTATEENTERED_MASK,
+                                pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        return 0;
+}
+
+static int am33xx_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= AM33XX_LOGICSTATEST_MASK;
+        v >>= AM33XX_LOGICSTATEST_SHIFT;
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
+{
+        u32 v, m;
+
+        m = pwrdm->logicretstate_mask;
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank,
+                u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_on_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank,
+                                        u8 pwrst)
+{
+        u32 m;
+
+        m = pwrdm->mem_ret_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        am33xx_prm_rmw_reg_bits(m, (pwrst << __ffs(m)),
+                                pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+
+        return 0;
+}
+
+static int am33xx_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_pwrst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
+{
+        u32 m, v;
+
+        m = pwrdm->mem_retst_mask[bank];
+        if (!m)
+                return -EINVAL;
+
+        v = am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstctrl_offs);
+        v &= m;
+        v >>= __ffs(m);
+
+        return v;
+}
+
+static int am33xx_pwrdm_wait_transition(struct powerdomain *pwrdm)
+{
+        u32 c = 0;
+
+        /*
+         * REVISIT: pwrdm_wait_transition() may be better implemented
+         * via a callback and a periodic timer check -- how long do we expect
+         * powerdomain transitions to take?
+         */
+
+        /* XXX Is this udelay() value meaningful? */
+        while ((am33xx_prm_read_reg(pwrdm->prcm_offs, pwrdm->pwrstst_offs)
+                        & OMAP_INTRANSITION_MASK) &&
+                        (c++ < PWRDM_TRANSITION_BAILOUT))
+                udelay(1);
+
+        if (c > PWRDM_TRANSITION_BAILOUT) {
+                pr_err("powerdomain: %s: waited too long to complete transition\n",
+                       pwrdm->name);
+                return -EAGAIN;
+        }
+
+        pr_debug("powerdomain: completed transition in %d loops\n", c);
+
+        return 0;
+}
+
+struct pwrdm_ops am33xx_pwrdm_operations = {
+        .pwrdm_set_next_pwrst           = am33xx_pwrdm_set_next_pwrst,
+        .pwrdm_read_next_pwrst          = am33xx_pwrdm_read_next_pwrst,
+        .pwrdm_read_pwrst               = am33xx_pwrdm_read_pwrst,
+        .pwrdm_read_prev_pwrst          = am33xx_pwrdm_read_prev_pwrst,
+        .pwrdm_set_logic_retst          = am33xx_pwrdm_set_logic_retst,
+        .pwrdm_read_logic_pwrst         = am33xx_pwrdm_read_logic_pwrst,
+        .pwrdm_read_logic_retst         = am33xx_pwrdm_read_logic_retst,
+        .pwrdm_clear_all_prev_pwrst     = am33xx_pwrdm_clear_all_prev_pwrst,
+        .pwrdm_set_lowpwrstchange       = am33xx_pwrdm_set_lowpwrstchange,
+        .pwrdm_read_mem_pwrst           = am33xx_pwrdm_read_mem_pwrst,
+        .pwrdm_read_mem_retst           = am33xx_pwrdm_read_mem_retst,
+        .pwrdm_set_mem_onst             = am33xx_pwrdm_set_mem_onst,
+        .pwrdm_set_mem_retst            = am33xx_pwrdm_set_mem_retst,
+        .pwrdm_wait_transition          = am33xx_pwrdm_wait_transition,
+};
diff --git a/arch/arm/mach-omap2/powerdomains33xx_data.c b/arch/arm/mach-omap2/powerdomains33xx_data.c
new file mode 100644
index 000000000000..869adb82569e
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains33xx_data.c
@@ -0,0 +1,185 @@
+/*
+ * AM33XX Power domain data
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "powerdomain.h"
+#include "prcm-common.h"
+#include "prm-regbits-33xx.h"
+#include "prm33xx.h"
+
+static struct powerdomain gfx_33xx_pwrdm = {
+        .name                   = "gfx_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_GFX_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_GFX_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_GFX_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 1,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_GFX_MEM_ONSTATE_MASK,  /* gfx_mem */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_GFX_MEM_STATEST_MASK,  /* gfx_mem */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_GFX_MEM_RETSTATE_MASK, /* gfx_mem */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* gfx_mem */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* gfx_mem */
+        },
+};
+
+static struct powerdomain rtc_33xx_pwrdm = {
+        .name                   = "rtc_pwrdm",
+        .voltdm                 = { .name = "rtc" },
+        .prcm_offs              = AM33XX_PRM_RTC_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_RTC_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_RTC_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_ON,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+};
+
+static struct powerdomain wkup_33xx_pwrdm = {
+        .name                   = "wkup_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_WKUP_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_WKUP_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_WKUP_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_ON,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_3_3_MASK,
+};
+
+static struct powerdomain per_33xx_pwrdm = {
+        .name                   = "per_pwrdm",
+        .voltdm                 = { .name = "core" },
+        .prcm_offs              = AM33XX_PRM_PER_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_PER_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_PER_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 3,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_3_3_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_PRUSS_MEM_ONSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_ONSTATE_MASK,  /* per_mem */
+                [2]             = AM33XX_RAM_MEM_ONSTATE_MASK,  /* ram_mem */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
+                [2]             = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_PRUSS_MEM_STATEST_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_STATEST_MASK,  /* per_mem */
+                [2]             = AM33XX_RAM_MEM_STATEST_MASK,  /* ram_mem */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_PRUSS_MEM_RETSTATE_MASK, /* pruss_mem */
+                [1]             = AM33XX_PER_MEM_RETSTATE_MASK, /* per_mem */
+                [2]             = AM33XX_RAM_MEM_RETSTATE_MASK, /* ram_mem */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* pruss_mem */
+                [1]             = PWRSTS_OFF_RET,       /* per_mem */
+                [2]             = PWRSTS_OFF_RET,       /* ram_mem */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* pruss_mem */
+                [1]             = PWRSTS_ON,            /* per_mem */
+                [2]             = PWRSTS_ON,            /* ram_mem */
+        },
+};
+
+static struct powerdomain mpu_33xx_pwrdm = {
+        .name                   = "mpu_pwrdm",
+        .voltdm                 = { .name = "mpu" },
+        .prcm_offs              = AM33XX_PRM_MPU_MOD,
+        .pwrstctrl_offs         = AM33XX_PM_MPU_PWRSTCTRL_OFFSET,
+        .pwrstst_offs           = AM33XX_PM_MPU_PWRSTST_OFFSET,
+        .pwrsts                 = PWRSTS_OFF_RET_ON,
+        .pwrsts_logic_ret       = PWRSTS_OFF_RET,
+        .flags                  = PWRDM_HAS_LOWPOWERSTATECHANGE,
+        .banks                  = 3,
+        .logicretstate_mask     = AM33XX_LOGICRETSTATE_MASK,
+        .mem_on_mask            = {
+                [0]             = AM33XX_MPU_L1_ONSTATE_MASK,   /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_ONSTATE_MASK,   /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_ONSTATE_MASK,  /* mpu_ram */
+        },
+        .mem_ret_mask           = {
+                [0]             = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
+        },
+        .mem_pwrst_mask         = {
+                [0]             = AM33XX_MPU_L1_STATEST_MASK,   /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_STATEST_MASK,   /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_STATEST_MASK,  /* mpu_ram */
+        },
+        .mem_retst_mask         = {
+                [0]             = AM33XX_MPU_L1_RETSTATE_MASK,  /* mpu_l1 */
+                [1]             = AM33XX_MPU_L2_RETSTATE_MASK,  /* mpu_l2 */
+                [2]             = AM33XX_MPU_RAM_RETSTATE_MASK, /* mpu_ram */
+        },
+        .pwrsts_mem_ret         = {
+                [0]             = PWRSTS_OFF_RET,       /* mpu_l1 */
+                [1]             = PWRSTS_OFF_RET,       /* mpu_l2 */
+                [2]             = PWRSTS_OFF_RET,       /* mpu_ram */
+        },
+        .pwrsts_mem_on          = {
+                [0]             = PWRSTS_ON,            /* mpu_l1 */
+                [1]             = PWRSTS_ON,            /* mpu_l2 */
+                [2]             = PWRSTS_ON,            /* mpu_ram */
+        },
+};
+
+static struct powerdomain cefuse_33xx_pwrdm = {
+        .name           = "cefuse_pwrdm",
+        .voltdm         = { .name = "core" },
+        .prcm_offs      = AM33XX_PRM_CEFUSE_MOD,
+        .pwrstctrl_offs = AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET,
+        .pwrstst_offs   = AM33XX_PM_CEFUSE_PWRSTST_OFFSET,
+        .pwrsts         = PWRSTS_OFF_ON,
+};
+
+static struct powerdomain *powerdomains_am33xx[] __initdata = {
+        &gfx_33xx_pwrdm,
+        &rtc_33xx_pwrdm,
+        &wkup_33xx_pwrdm,
+        &per_33xx_pwrdm,
+        &mpu_33xx_pwrdm,
+        &cefuse_33xx_pwrdm,
+        NULL,
+};
+
+void __init am33xx_powerdomains_init(void)
+{
+        pwrdm_register_platform_funcs(&am33xx_pwrdm_operations);
+        pwrdm_register_pwrdms(powerdomains_am33xx);
+        pwrdm_complete_init();
+}
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index fb0a0a6869d1..bb883e463078 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -71,6 +71,22 @@ static struct powerdomain mpu_3xxx_pwrdm = {
         .voltdm           = { .name = "mpu_iva" },
 };
 
+static struct powerdomain mpu_am35x_pwrdm = {
+        .name             = "mpu_pwrdm",
+        .prcm_offs        = MPU_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .flags            = PWRDM_HAS_MPU_QUIRK,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON,
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,
+        },
+        .voltdm           = { .name = "mpu_iva" },
+};
+
 /*
  * The USBTLL Save-and-Restore mechanism is broken on
  * 3430s up to ES3.0 and 3630ES1.0. Hence this feature
@@ -120,6 +136,23 @@ static struct powerdomain core_3xxx_es3_1_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain core_am35x_pwrdm = {
+        .name             = "core_pwrdm",
+        .prcm_offs        = CORE_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 2,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON,         /* MEM1RETSTATE */
+                [1] = PWRSTS_ON,         /* MEM2RETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON, /* MEM1ONSTATE */
+                [1] = PWRSTS_ON, /* MEM2ONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain dss_pwrdm = {
         .name             = "dss_pwrdm",
         .prcm_offs        = OMAP3430_DSS_MOD,
@@ -135,6 +168,21 @@ static struct powerdomain dss_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain dss_am35x_pwrdm = {
+        .name             = "dss_pwrdm",
+        .prcm_offs        = OMAP3430_DSS_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 /*
  * Although the 34XX TRM Rev K Table 4-371 notes that retention is a
  * possible SGX powerstate, the SGX device itself does not support
@@ -156,6 +204,21 @@ static struct powerdomain sgx_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain sgx_am35x_pwrdm = {
+        .name             = "sgx_pwrdm",
+        .prcm_offs        = OMAP3430ES2_SGX_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain cam_pwrdm = {
         .name             = "cam_pwrdm",
         .prcm_offs        = OMAP3430_CAM_MOD,
@@ -186,6 +249,21 @@ static struct powerdomain per_pwrdm = {
         .voltdm           = { .name = "core" },
 };
 
+static struct powerdomain per_am35x_pwrdm = {
+        .name             = "per_pwrdm",
+        .prcm_offs        = OMAP3430_PER_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .banks            = 1,
+        .pwrsts_mem_ret   = {
+                [0] = PWRSTS_ON, /* MEMRETSTATE */
+        },
+        .pwrsts_mem_on    = {
+                [0] = PWRSTS_ON,  /* MEMONSTATE */
+        },
+        .voltdm           = { .name = "core" },
+};
+
 static struct powerdomain emu_pwrdm = {
         .name           = "emu_pwrdm",
         .prcm_offs      = OMAP3430_EMU_MOD,
@@ -200,6 +278,14 @@ static struct powerdomain neon_pwrdm = {
         .voltdm           = { .name = "mpu_iva" },
 };
 
+static struct powerdomain neon_am35x_pwrdm = {
+        .name             = "neon_pwrdm",
+        .prcm_offs        = OMAP3430_NEON_MOD,
+        .pwrsts           = PWRSTS_ON,
+        .pwrsts_logic_ret = PWRSTS_ON,
+        .voltdm           = { .name = "mpu_iva" },
+};
+
 static struct powerdomain usbhost_pwrdm = {
         .name             = "usbhost_pwrdm",
         .prcm_offs        = OMAP3430ES2_USBHOST_MOD,
@@ -293,6 +379,22 @@ static struct powerdomain *powerdomains_omap3430es3_1plus[] __initdata = {
         NULL
 };
 
+static struct powerdomain *powerdomains_am35x[] __initdata = {
+        &wkup_omap2_pwrdm,
+        &mpu_am35x_pwrdm,
+        &neon_am35x_pwrdm,
+        &core_am35x_pwrdm,
+        &sgx_am35x_pwrdm,
+        &dss_am35x_pwrdm,
+        &per_am35x_pwrdm,
+        &emu_pwrdm,
+        &dpll1_pwrdm,
+        &dpll3_pwrdm,
+        &dpll4_pwrdm,
+        &dpll5_pwrdm,
+        NULL
+};
+
 void __init omap3xxx_powerdomains_init(void)
 {
         unsigned int rev;
@@ -301,21 +403,34 @@ void __init omap3xxx_powerdomains_init(void)
                 return;
 
         pwrdm_register_platform_funcs(&omap3_pwrdm_operations);
-        pwrdm_register_pwrdms(powerdomains_omap3430_common);
 
         rev = omap_rev();
 
-        if (rev == OMAP3430_REV_ES1_0)
-                pwrdm_register_pwrdms(powerdomains_omap3430es1);
-        else if (rev == OMAP3430_REV_ES2_0 || rev == OMAP3430_REV_ES2_1 ||
-                 rev == OMAP3430_REV_ES3_0 || rev == OMAP3630_REV_ES1_0)
-                pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
-        else if (rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2 ||
-                 rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1 ||
-                 rev == OMAP3630_REV_ES1_1 || rev == OMAP3630_REV_ES1_2)
-                pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
-        else
-                WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+        if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
+                pwrdm_register_pwrdms(powerdomains_am35x);
+        } else {
+                pwrdm_register_pwrdms(powerdomains_omap3430_common);
+
+                switch (rev) {
+                case OMAP3430_REV_ES1_0:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es1);
+                        break;
+                case OMAP3430_REV_ES2_0:
+                case OMAP3430_REV_ES2_1:
+                case OMAP3430_REV_ES3_0:
+                case OMAP3630_REV_ES1_0:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es2_es3_0);
+                        break;
+                case OMAP3430_REV_ES3_1:
+                case OMAP3430_REV_ES3_1_2:
+                case OMAP3630_REV_ES1_1:
+                case OMAP3630_REV_ES1_2:
+                        pwrdm_register_pwrdms(powerdomains_omap3430es3_1plus);
+                        break;
+                default:
+                        WARN(1, "OMAP3 powerdomain init: unknown chip type\n");
+                }
+        }
 
         pwrdm_complete_init();
 }
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index 6da3ba483ad1..cc1398e8b469 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -203,8 +203,8 @@
 #define OMAP3430_EN_MMC2_SHIFT                          25
 #define OMAP3430_EN_MMC1_MASK                           (1 << 24)
 #define OMAP3430_EN_MMC1_SHIFT                          24
-#define OMAP3430_EN_UART4_MASK                          (1 << 23)
-#define OMAP3430_EN_UART4_SHIFT                         23
+#define AM35XX_EN_UART4_MASK                            (1 << 23)
+#define AM35XX_EN_UART4_SHIFT                           23
 #define OMAP3430_EN_MCSPI4_MASK                         (1 << 21)
 #define OMAP3430_EN_MCSPI4_SHIFT                        21
 #define OMAP3430_EN_MCSPI3_MASK                         (1 << 20)
diff --git a/arch/arm/mach-omap2/prm-regbits-33xx.h b/arch/arm/mach-omap2/prm-regbits-33xx.h
new file mode 100644
index 000000000000..0221b5c20e87
--- /dev/null
+++ b/arch/arm/mach-omap2/prm-regbits-33xx.h
@@ -0,0 +1,357 @@
+/*
+ * AM33XX PRM_XXX register bits
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_33XX_H
+
+#include "prm.h"
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_ACT_EXPORT_SHIFT                  1
+#define AM33XX_ABBOFF_ACT_EXPORT_MASK                   (1 << 1)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ABBOFF_SLEEP_EXPORT_SHIFT                2
+#define AM33XX_ABBOFF_SLEEP_EXPORT_MASK                 (1 << 2)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_AIPOFF_SHIFT                             8
+#define AM33XX_AIPOFF_MASK                              (1 << 8)
+
+/* Used by PM_WKUP_PWRSTST */
+#define AM33XX_DEBUGSS_MEM_STATEST_SHIFT                17
+#define AM33XX_DEBUGSS_MEM_STATEST_MASK                 (0x3 << 17)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_DISABLE_RTA_EXPORT_SHIFT                 0
+#define AM33XX_DISABLE_RTA_EXPORT_MASK                  (1 << 0)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_CORE_RECAL_EN_SHIFT                 12
+#define AM33XX_DPLL_CORE_RECAL_EN_MASK                  (1 << 12)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_CORE_RECAL_ST_SHIFT                 12
+#define AM33XX_DPLL_CORE_RECAL_ST_MASK                  (1 << 12)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DDR_RECAL_EN_SHIFT                  14
+#define AM33XX_DPLL_DDR_RECAL_EN_MASK                   (1 << 14)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DDR_RECAL_ST_SHIFT                  14
+#define AM33XX_DPLL_DDR_RECAL_ST_MASK                   (1 << 14)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_DISP_RECAL_EN_SHIFT                 15
+#define AM33XX_DPLL_DISP_RECAL_EN_MASK                  (1 << 15)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_DISP_RECAL_ST_SHIFT                 13
+#define AM33XX_DPLL_DISP_RECAL_ST_MASK                  (1 << 13)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_MPU_RECAL_EN_SHIFT                  11
+#define AM33XX_DPLL_MPU_RECAL_EN_MASK                   (1 << 11)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_MPU_RECAL_ST_SHIFT                  11
+#define AM33XX_DPLL_MPU_RECAL_ST_MASK                   (1 << 11)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_DPLL_PER_RECAL_EN_SHIFT                  13
+#define AM33XX_DPLL_PER_RECAL_EN_MASK                   (1 << 13)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_DPLL_PER_RECAL_ST_SHIFT                  15
+#define AM33XX_DPLL_PER_RECAL_ST_MASK                   (1 << 15)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_EMULATION_M3_RST_SHIFT                   6
+#define AM33XX_EMULATION_M3_RST_MASK                    (1 << 6)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_EMULATION_MPU_RST_SHIFT                  5
+#define AM33XX_EMULATION_MPU_RST_MASK                   (1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC1_EXPORT_SHIFT                     3
+#define AM33XX_ENFUNC1_EXPORT_MASK                      (1 << 3)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC3_EXPORT_SHIFT                     5
+#define AM33XX_ENFUNC3_EXPORT_MASK                      (1 << 5)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC4_SHIFT                            6
+#define AM33XX_ENFUNC4_MASK                             (1 << 6)
+
+/* Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_MPU_SETUP */
+#define AM33XX_ENFUNC5_SHIFT                            7
+#define AM33XX_ENFUNC5_MASK                             (1 << 7)
+
+/* Used by PRM_RSTST */
+#define AM33XX_EXTERNAL_WARM_RST_SHIFT                  5
+#define AM33XX_EXTERNAL_WARM_RST_MASK                   (1 << 5)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_FORCEWKUP_EN_SHIFT                       10
+#define AM33XX_FORCEWKUP_EN_MASK                        (1 << 10)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_FORCEWKUP_ST_SHIFT                       10
+#define AM33XX_FORCEWKUP_ST_MASK                        (1 << 10)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_ONSTATE_SHIFT                    17
+#define AM33XX_GFX_MEM_ONSTATE_MASK                     (0x3 << 17)
+
+/* Used by PM_GFX_PWRSTCTRL */
+#define AM33XX_GFX_MEM_RETSTATE_SHIFT                   6
+#define AM33XX_GFX_MEM_RETSTATE_MASK                    (1 << 6)
+
+/* Used by PM_GFX_PWRSTST */
+#define AM33XX_GFX_MEM_STATEST_SHIFT                    4
+#define AM33XX_GFX_MEM_STATEST_MASK                     (0x3 << 4)
+
+/* Used by RM_GFX_RSTCTRL, RM_GFX_RSTST */
+#define AM33XX_GFX_RST_SHIFT                            0
+#define AM33XX_GFX_RST_MASK                             (1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_COLD_RST_SHIFT                    0
+#define AM33XX_GLOBAL_COLD_RST_MASK                     (1 << 0)
+
+/* Used by PRM_RSTST */
+#define AM33XX_GLOBAL_WARM_SW_RST_SHIFT                 1
+#define AM33XX_GLOBAL_WARM_SW_RST_MASK                  (1 << 1)
+
+/* Used by RM_WKUP_RSTST */
+#define AM33XX_ICECRUSHER_M3_RST_SHIFT                  7
+#define AM33XX_ICECRUSHER_M3_RST_MASK                   (1 << 7)
+
+/* Used by RM_MPU_RSTST */
+#define AM33XX_ICECRUSHER_MPU_RST_SHIFT                 6
+#define AM33XX_ICECRUSHER_MPU_RST_MASK                  (1 << 6)
+
+/* Used by PRM_RSTST */
+#define AM33XX_ICEPICK_RST_SHIFT                        9
+#define AM33XX_ICEPICK_RST_MASK                         (1 << 9)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PRUSS_LRST_SHIFT                         1
+#define AM33XX_PRUSS_LRST_MASK                          (1 << 1)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_ONSTATE_SHIFT                  5
+#define AM33XX_PRUSS_MEM_ONSTATE_MASK                   (0x3 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PRUSS_MEM_RETSTATE_SHIFT                 7
+#define AM33XX_PRUSS_MEM_RETSTATE_MASK                  (1 << 7)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PRUSS_MEM_STATEST_SHIFT                  23
+#define AM33XX_PRUSS_MEM_STATEST_MASK                   (0x3 << 23)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_INTRANSITION_SHIFT                       20
+#define AM33XX_INTRANSITION_MASK                        (1 << 20)
+
+/* Used by PM_CEFUSE_PWRSTST */
+#define AM33XX_LASTPOWERSTATEENTERED_SHIFT              24
+#define AM33XX_LASTPOWERSTATEENTERED_MASK               (0x3 << 24)
+
+/* Used by PM_GFX_PWRSTCTRL, PM_MPU_PWRSTCTRL, PM_RTC_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_SHIFT                      2
+#define AM33XX_LOGICRETSTATE_MASK                       (1 << 2)
+
+/* Renamed from LOGICRETSTATE Used by PM_PER_PWRSTCTRL, PM_WKUP_PWRSTCTRL */
+#define AM33XX_LOGICRETSTATE_3_3_SHIFT                  3
+#define AM33XX_LOGICRETSTATE_3_3_MASK                   (1 << 3)
+
+/*
+ * Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST,
+ * PM_WKUP_PWRSTST, PM_RTC_PWRSTST
+ */
+#define AM33XX_LOGICSTATEST_SHIFT                       2
+#define AM33XX_LOGICSTATEST_MASK                        (1 << 2)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL, PM_WKUP_PWRSTCTRL, PM_RTC_PWRSTCTRL
+ */
+#define AM33XX_LOWPOWERSTATECHANGE_SHIFT                4
+#define AM33XX_LOWPOWERSTATECHANGE_MASK                 (1 << 4)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_ONSTATE_SHIFT                     18
+#define AM33XX_MPU_L1_ONSTATE_MASK                      (0x3 << 18)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L1_RETSTATE_SHIFT                    22
+#define AM33XX_MPU_L1_RETSTATE_MASK                     (1 << 22)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L1_STATEST_SHIFT                     6
+#define AM33XX_MPU_L1_STATEST_MASK                      (0x3 << 6)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_ONSTATE_SHIFT                     20
+#define AM33XX_MPU_L2_ONSTATE_MASK                      (0x3 << 20)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_L2_RETSTATE_SHIFT                    23
+#define AM33XX_MPU_L2_RETSTATE_MASK                     (1 << 23)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_L2_STATEST_SHIFT                     8
+#define AM33XX_MPU_L2_STATEST_MASK                      (0x3 << 8)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_ONSTATE_SHIFT                    16
+#define AM33XX_MPU_RAM_ONSTATE_MASK                     (0x3 << 16)
+
+/* Used by PM_MPU_PWRSTCTRL */
+#define AM33XX_MPU_RAM_RETSTATE_SHIFT                   24
+#define AM33XX_MPU_RAM_RETSTATE_MASK                    (1 << 24)
+
+/* Used by PM_MPU_PWRSTST */
+#define AM33XX_MPU_RAM_STATEST_SHIFT                    4
+#define AM33XX_MPU_RAM_STATEST_MASK                     (0x3 << 4)
+
+/* Used by PRM_RSTST */
+#define AM33XX_MPU_SECURITY_VIOL_RST_SHIFT              2
+#define AM33XX_MPU_SECURITY_VIOL_RST_MASK               (1 << 2)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_PCHARGECNT_VALUE_SHIFT                   0
+#define AM33XX_PCHARGECNT_VALUE_MASK                    (0x3f << 0)
+
+/* Used by RM_PER_RSTCTRL */
+#define AM33XX_PCI_LRST_SHIFT                           0
+#define AM33XX_PCI_LRST_MASK                            (1 << 0)
+
+/* Renamed from PCI_LRST Used by RM_PER_RSTST */
+#define AM33XX_PCI_LRST_5_5_SHIFT                       5
+#define AM33XX_PCI_LRST_5_5_MASK                        (1 << 5)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_ONSTATE_SHIFT                    25
+#define AM33XX_PER_MEM_ONSTATE_MASK                     (0x3 << 25)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_PER_MEM_RETSTATE_SHIFT                   29
+#define AM33XX_PER_MEM_RETSTATE_MASK                    (1 << 29)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_PER_MEM_STATEST_SHIFT                    17
+#define AM33XX_PER_MEM_STATEST_MASK                     (0x3 << 17)
+
+/*
+ * Used by PM_GFX_PWRSTCTRL, PM_CEFUSE_PWRSTCTRL, PM_PER_PWRSTCTRL,
+ * PM_MPU_PWRSTCTRL
+ */
+#define AM33XX_POWERSTATE_SHIFT                         0
+#define AM33XX_POWERSTATE_MASK                          (0x3 << 0)
+
+/* Used by PM_GFX_PWRSTST, PM_CEFUSE_PWRSTST, PM_PER_PWRSTST, PM_MPU_PWRSTST */
+#define AM33XX_POWERSTATEST_SHIFT                       0
+#define AM33XX_POWERSTATEST_MASK                        (0x3 << 0)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_ONSTATE_SHIFT                    30
+#define AM33XX_RAM_MEM_ONSTATE_MASK                     (0x3 << 30)
+
+/* Used by PM_PER_PWRSTCTRL */
+#define AM33XX_RAM_MEM_RETSTATE_SHIFT                   27
+#define AM33XX_RAM_MEM_RETSTATE_MASK                    (1 << 27)
+
+/* Used by PM_PER_PWRSTST */
+#define AM33XX_RAM_MEM_STATEST_SHIFT                    21
+#define AM33XX_RAM_MEM_STATEST_MASK                     (0x3 << 21)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_RETMODE_ENABLE_SHIFT                     0
+#define AM33XX_RETMODE_ENABLE_MASK                      (1 << 0)
+
+/* Used by REVISION_PRM */
+#define AM33XX_REV_SHIFT                                0
+#define AM33XX_REV_MASK                                 (0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME1_SHIFT                           0
+#define AM33XX_RSTTIME1_MASK                            (0xff << 0)
+
+/* Used by PRM_RSTTIME */
+#define AM33XX_RSTTIME2_SHIFT                           8
+#define AM33XX_RSTTIME2_MASK                            (0x1f << 8)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_COLD_SW_SHIFT                 1
+#define AM33XX_RST_GLOBAL_COLD_SW_MASK                  (1 << 1)
+
+/* Used by PRM_RSTCTRL */
+#define AM33XX_RST_GLOBAL_WARM_SW_SHIFT                 0
+#define AM33XX_RST_GLOBAL_WARM_SW_MASK                  (1 << 0)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_SLPCNT_VALUE_SHIFT                       16
+#define AM33XX_SLPCNT_VALUE_MASK                        (0xff << 16)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAMLDO_STATUS_SHIFT                     8
+#define AM33XX_SRAMLDO_STATUS_MASK                      (1 << 8)
+
+/* Used by PRM_LDO_SRAM_CORE_CTRL, PRM_LDO_SRAM_MPU_CTRL */
+#define AM33XX_SRAM_IN_TRANSITION_SHIFT                 9
+#define AM33XX_SRAM_IN_TRANSITION_MASK                  (1 << 9)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_STARTUP_COUNT_SHIFT                      24
+#define AM33XX_STARTUP_COUNT_MASK                       (0xff << 24)
+
+/* Used by PRM_IRQENABLE_M3, PRM_IRQENABLE_MPU */
+#define AM33XX_TRANSITION_EN_SHIFT                      8
+#define AM33XX_TRANSITION_EN_MASK                       (1 << 8)
+
+/* Used by PRM_IRQSTATUS_M3, PRM_IRQSTATUS_MPU */
+#define AM33XX_TRANSITION_ST_SHIFT                      8
+#define AM33XX_TRANSITION_ST_MASK                       (1 << 8)
+
+/* Used by PRM_SRAM_COUNT */
+#define AM33XX_VSETUPCNT_VALUE_SHIFT                    8
+#define AM33XX_VSETUPCNT_VALUE_MASK                     (0xff << 8)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT0_RST_SHIFT                           3
+#define AM33XX_WDT0_RST_MASK                            (1 << 3)
+
+/* Used by PRM_RSTST */
+#define AM33XX_WDT1_RST_SHIFT                           4
+#define AM33XX_WDT1_RST_MASK                            (1 << 4)
+
+/* Used by RM_WKUP_RSTCTRL */
+#define AM33XX_WKUP_M3_LRST_SHIFT                       3
+#define AM33XX_WKUP_M3_LRST_MASK                        (1 << 3)
+
+/* Renamed from WKUP_M3_LRST Used by RM_WKUP_RSTST */
+#define AM33XX_WKUP_M3_LRST_5_5_SHIFT                   5
+#define AM33XX_WKUP_M3_LRST_5_5_MASK                    (1 << 5)
+
+#endif
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
new file mode 100644
index 000000000000..e7dbb6cf1255
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -0,0 +1,135 @@
+/*
+ * AM33XX PRM functions
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <plat/common.h>
+
+#include "common.h"
+#include "prm33xx.h"
+#include "prm-regbits-33xx.h"
+
+/* Read a register in a PRM instance */
+u32 am33xx_prm_read_reg(s16 inst, u16 idx)
+{
+        return __raw_readl(prm_base + inst + idx);
+}
+
+/* Write into a register in a PRM instance */
+void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx)
+{
+        __raw_writel(val, prm_base + inst + idx);
+}
+
+/* Read-modify-write a register in PRM. Caller must lock */
+u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(inst, idx);
+        v &= ~mask;
+        v |= bits;
+        am33xx_prm_write_reg(v, inst, idx);
+
+        return v;
+}
+
+/**
+ * am33xx_prm_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @shift: register bit shift corresponding to the reset line to check
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_offs: RM_RSTCTRL register address offset for this module
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+        u32 v;
+
+        v = am33xx_prm_read_reg(inst, rstctrl_offs);
+        v &= 1 << shift;
+        v >>= shift;
+
+        return v;
+}
+
+/**
+ * am33xx_prm_assert_hardreset - assert the HW reset line of a submodule
+ * @shift: register bit shift corresponding to the reset line to assert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * place the submodule into reset.  Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
+{
+        u32 mask = 1 << shift;
+
+        am33xx_prm_rmw_reg_bits(mask, mask, inst, rstctrl_offs);
+
+        return 0;
+}
+
+/**
+ * am33xx_prm_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @shift: register bit shift corresponding to the reset line to deassert
+ * @inst: CM instance register offset (*_INST macro)
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @rstst_reg: RM_RSTST register address for this module
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP.  These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block.  This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning.  Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+                u16 rstctrl_offs, u16 rstst_offs)
+{
+        int c;
+        u32 mask = 1 << shift;
+
+        /* Check the current status to avoid  de-asserting the line twice */
+        if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
+                return -EEXIST;
+
+        /* Clear the reset status by writing 1 to the status bit */
+        am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
+        /* de-assert the reset control line */
+        am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
+        /* wait the status to be set */
+
+        omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst,
+                                                           rstst_offs),
+                          MAX_MODULE_HARDRESET_WAIT, c);
+
+        return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
new file mode 100644
index 000000000000..3f25c563a821
--- /dev/null
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -0,0 +1,129 @@
+/*
+ * AM33XX PRM instance offset macros
+ *
+ * Copyright (C) 2011-2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+#define __ARCH_ARM_MACH_OMAP2_PRM33XX_H
+
+#include "prcm-common.h"
+#include "prm.h"
+
+#define AM33XX_PRM_BASE               0x44E00000
+
+#define AM33XX_PRM_REGADDR(inst, reg)                         \
+        AM33XX_L4_WK_IO_ADDRESS(AM33XX_PRM_BASE + (inst) + (reg))
+
+
+/* PRM instances */
+#define AM33XX_PRM_OCP_SOCKET_MOD       0x0B00
+#define AM33XX_PRM_PER_MOD              0x0C00
+#define AM33XX_PRM_WKUP_MOD             0x0D00
+#define AM33XX_PRM_MPU_MOD              0x0E00
+#define AM33XX_PRM_DEVICE_MOD           0x0F00
+#define AM33XX_PRM_RTC_MOD              0x1000
+#define AM33XX_PRM_GFX_MOD              0x1100
+#define AM33XX_PRM_CEFUSE_MOD           0x1200
+
+/* PRM */
+
+/* PRM.OCP_SOCKET_PRM register offsets */
+#define AM33XX_REVISION_PRM_OFFSET              0x0000
+#define AM33XX_REVISION_PRM                     AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000)
+#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET         0x0004
+#define AM33XX_PRM_IRQSTATUS_MPU                AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004)
+#define AM33XX_PRM_IRQENABLE_MPU_OFFSET         0x0008
+#define AM33XX_PRM_IRQENABLE_MPU                AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008)
+#define AM33XX_PRM_IRQSTATUS_M3_OFFSET          0x000c
+#define AM33XX_PRM_IRQSTATUS_M3                 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c)
+#define AM33XX_PRM_IRQENABLE_M3_OFFSET          0x0010
+#define AM33XX_PRM_IRQENABLE_M3                 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010)
+
+/* PRM.PER_PRM register offsets */
+#define AM33XX_RM_PER_RSTCTRL_OFFSET            0x0000
+#define AM33XX_RM_PER_RSTCTRL                   AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000)
+#define AM33XX_RM_PER_RSTST_OFFSET              0x0004
+#define AM33XX_RM_PER_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0004)
+#define AM33XX_PM_PER_PWRSTST_OFFSET            0x0008
+#define AM33XX_PM_PER_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008)
+#define AM33XX_PM_PER_PWRSTCTRL_OFFSET          0x000c
+#define AM33XX_PM_PER_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c)
+
+/* PRM.WKUP_PRM register offsets */
+#define AM33XX_RM_WKUP_RSTCTRL_OFFSET           0x0000
+#define AM33XX_RM_WKUP_RSTCTRL                  AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000)
+#define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET         0x0004
+#define AM33XX_PM_WKUP_PWRSTCTRL                AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004)
+#define AM33XX_PM_WKUP_PWRSTST_OFFSET           0x0008
+#define AM33XX_PM_WKUP_PWRSTST                  AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008)
+#define AM33XX_RM_WKUP_RSTST_OFFSET             0x000c
+#define AM33XX_RM_WKUP_RSTST                    AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c)
+
+/* PRM.MPU_PRM register offsets */
+#define AM33XX_PM_MPU_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_MPU_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000)
+#define AM33XX_PM_MPU_PWRSTST_OFFSET            0x0004
+#define AM33XX_PM_MPU_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004)
+#define AM33XX_RM_MPU_RSTST_OFFSET              0x0008
+#define AM33XX_RM_MPU_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008)
+
+/* PRM.DEVICE_PRM register offsets */
+#define AM33XX_PRM_RSTCTRL_OFFSET               0x0000
+#define AM33XX_PRM_RSTCTRL                      AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000)
+#define AM33XX_PRM_RSTTIME_OFFSET               0x0004
+#define AM33XX_PRM_RSTTIME                      AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004)
+#define AM33XX_PRM_RSTST_OFFSET                 0x0008
+#define AM33XX_PRM_RSTST                        AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008)
+#define AM33XX_PRM_SRAM_COUNT_OFFSET            0x000c
+#define AM33XX_PRM_SRAM_COUNT                   AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c)
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET   0x0010
+#define AM33XX_PRM_LDO_SRAM_CORE_SETUP          AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010)
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET    0x0014
+#define AM33XX_PRM_LDO_SRAM_CORE_CTRL           AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014)
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET    0x0018
+#define AM33XX_PRM_LDO_SRAM_MPU_SETUP           AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018)
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET     0x001c
+#define AM33XX_PRM_LDO_SRAM_MPU_CTRL            AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c)
+
+/* PRM.RTC_PRM register offsets */
+#define AM33XX_PM_RTC_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_RTC_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0000)
+#define AM33XX_PM_RTC_PWRSTST_OFFSET            0x0004
+#define AM33XX_PM_RTC_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_RTC_MOD, 0x0004)
+
+/* PRM.GFX_PRM register offsets */
+#define AM33XX_PM_GFX_PWRSTCTRL_OFFSET          0x0000
+#define AM33XX_PM_GFX_PWRSTCTRL                 AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000)
+#define AM33XX_RM_GFX_RSTCTRL_OFFSET            0x0004
+#define AM33XX_RM_GFX_RSTCTRL                   AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004)
+#define AM33XX_PM_GFX_PWRSTST_OFFSET            0x0010
+#define AM33XX_PM_GFX_PWRSTST                   AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010)
+#define AM33XX_RM_GFX_RSTST_OFFSET              0x0014
+#define AM33XX_RM_GFX_RSTST                     AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014)
+
+/* PRM.CEFUSE_PRM register offsets */
+#define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET       0x0000
+#define AM33XX_PM_CEFUSE_PWRSTCTRL              AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0000)
+#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET         0x0004
+#define AM33XX_PM_CEFUSE_PWRSTST                AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
+
+extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
+extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
+extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
+extern void am33xx_prm_global_warm_sw_reset(void);
+extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
+                u16 rstctrl_offs);
+extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
+extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
+                u16 rstctrl_offs, u16 rstst_offs);
+#endif
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index dfe00ddb5c60..534d732caa1e 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -85,7 +85,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
         unsigned long priority_pending[OMAP_PRCM_MAX_NR_PENDING_REG];
         struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int virtirq;
-        int nr_irqs = prcm_irq_setup->nr_regs * 32;
+        int nr_irq = prcm_irq_setup->nr_regs * 32;
 
         /*
          * If we are suspended, mask all interrupts from PRCM level,
@@ -110,7 +110,7 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
                 prcm_irq_setup->read_pending_irqs(pending);
 
                 /* No bit set, then all IRQs are handled */
-                if (find_first_bit(pending, nr_irqs) >= nr_irqs)
+                if (find_first_bit(pending, nr_irq) >= nr_irq)
                         break;
 
                 omap_prcm_events_filter_priority(pending, priority_pending);
@@ -121,11 +121,11 @@ static void omap_prcm_irq_handler(unsigned int irq, struct irq_desc *desc)
                  */
 
                 /* Serve priority events first */
-                for_each_set_bit(virtirq, priority_pending, nr_irqs)
+                for_each_set_bit(virtirq, priority_pending, nr_irq)
                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
 
                 /* Serve normal events next */
-                for_each_set_bit(virtirq, pending, nr_irqs)
+                for_each_set_bit(virtirq, pending, nr_irq)
                         generic_handle_irq(prcm_irq_setup->base_irq + virtirq);
         }
         if (chip->irq_ack)
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 8fe75a81e12d..b5b5d92acd9d 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -364,6 +364,11 @@ OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
 OMAP_SYS_TIMER(3_secure)
 #endif
 
+#ifdef CONFIG_SOC_AM33XX
+OMAP_SYS_TIMER_INIT(3_am33xx, 1, OMAP4_MPU_SOURCE, 2, OMAP4_MPU_SOURCE)
+OMAP_SYS_TIMER(3_am33xx)
+#endif
+
 #ifdef CONFIG_ARCH_OMAP4
 #ifdef CONFIG_LOCAL_TIMERS
 static DEFINE_TWD_LOCAL_TIMER(twd_local_timer,
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 43a979075338..3882f3c7608c 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -49,6 +49,7 @@ static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
         },
 };
 
+#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
 static int twl_set_voltage(void *data, int target_uV)
 {
         struct voltagedomain *voltdm = (struct voltagedomain *)data;
@@ -60,6 +61,7 @@ static int twl_get_voltage(void *data)
         struct voltagedomain *voltdm = (struct voltagedomain *)data;
         return voltdm_get_voltage(voltdm);
 }
+#endif
 
 void __init omap_pmic_init(int bus, u32 clkrate,
                            const char *pmic_type, int pmic_irq,
@@ -213,10 +215,6 @@ static struct twl_regulator_driver_data omap3_vdd2_drvdata = {
 void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
-        if (!pmic_data->irq_base)
-                pmic_data->irq_base = TWL4030_IRQ_BASE;
-        if (!pmic_data->irq_end)
-                pmic_data->irq_end = TWL4030_IRQ_END;
         if (!pmic_data->vdd1) {
                 omap3_vdd1.driver_data = &omap3_vdd1_drvdata;
                 omap3_vdd1_drvdata.data = voltdm_lookup("mpu_iva");
@@ -481,11 +479,6 @@ static struct regulator_init_data omap4_v2v1_idata = {
 void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
                                   u32 pdata_flags, u32 regulators_flags)
 {
-        if (!pmic_data->irq_base)
-                pmic_data->irq_base = TWL6030_IRQ_BASE;
-        if (!pmic_data->irq_end)
-                pmic_data->irq_end = TWL6030_IRQ_END;
-
         if (!pmic_data->vdd1) {
                 omap4_vdd1.driver_data = &omap4_vdd1_drvdata;
                 omap4_vdd1_drvdata.data = voltdm_lookup("mpu");
diff --git a/arch/arm/mach-omap2/usb-fs.c b/arch/arm/mach-omap2/usb-fs.c
deleted file mode 100644
index 1481078763b8..000000000000
--- a/arch/arm/mach-omap2/usb-fs.c
+++ /dev/null
@@ -1,359 +0,0 @@
-/*
- * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-
-#include <asm/irq.h>
-
-#include <plat/usb.h>
-#include <plat/board.h>
-
-#include "control.h"
-#include "mux.h"
-
-#define INT_USB_IRQ_GEN         INT_24XX_USB_IRQ_GEN
-#define INT_USB_IRQ_NISO        INT_24XX_USB_IRQ_NISO
-#define INT_USB_IRQ_ISO         INT_24XX_USB_IRQ_ISO
-#define INT_USB_IRQ_HGEN        INT_24XX_USB_IRQ_HGEN
-#define INT_USB_IRQ_OTG         INT_24XX_USB_IRQ_OTG
-
-#if defined(CONFIG_ARCH_OMAP2)
-
-#ifdef  CONFIG_USB_GADGET_OMAP
-
-static struct resource udc_resources[] = {
-        /* order is significant! */
-        {               /* registers */
-                .start          = UDC_BASE,
-                .end            = UDC_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {            /* general IRQ */
-                .start          = INT_USB_IRQ_GEN,
-                .flags          = IORESOURCE_IRQ,
-        }, {            /* PIO IRQ */
-                .start          = INT_USB_IRQ_NISO,
-                .flags          = IORESOURCE_IRQ,
-        }, {            /* SOF IRQ */
-                .start          = INT_USB_IRQ_ISO,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static u64 udc_dmamask = ~(u32)0;
-
-static struct platform_device udc_device = {
-        .name           = "omap_udc",
-        .id             = -1,
-        .dev = {
-                .dma_mask               = &udc_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(udc_resources),
-        .resource       = udc_resources,
-};
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-        pdata->udc_device = &udc_device;
-}
-
-#else
-
-static inline void udc_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32)0;
-
-static struct resource ohci_resources[] = {
-        {
-                .start  = OMAP_OHCI_BASE,
-                .end    = OMAP_OHCI_BASE + 0xff,
-                .flags  = IORESOURCE_MEM,
-        },
-        {
-                .start  = INT_USB_IRQ_HGEN,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device ohci_device = {
-        .name                   = "ohci",
-        .id                     = -1,
-        .dev = {
-                .dma_mask               = &ohci_dmamask,
-                .coherent_dma_mask      = 0xffffffff,
-        },
-        .num_resources  = ARRAY_SIZE(ohci_resources),
-        .resource               = ohci_resources,
-};
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-        pdata->ohci_device = &ohci_device;
-}
-
-#else
-
-static inline void ohci_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-#if     defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)
-
-static struct resource otg_resources[] = {
-        /* order is significant! */
-        {
-                .start          = OTG_BASE,
-                .end            = OTG_BASE + 0xff,
-                .flags          = IORESOURCE_MEM,
-        }, {
-                .start          = INT_USB_IRQ_OTG,
-                .flags          = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device otg_device = {
-        .name           = "omap_otg",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(otg_resources),
-        .resource       = otg_resources,
-};
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-        pdata->otg_device = &otg_device;
-}
-
-#else
-
-static inline void otg_device_init(struct omap_usb_config *pdata)
-{
-}
-
-#endif
-
-static void omap2_usb_devconf_clear(u8 port, u32 mask)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r &= ~USBTXWRMODEI(port, mask);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb_devconf_set(u8 port, u32 mask)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r |= USBTXWRMODEI(port, mask);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_disable_5pinbitll(void)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static void omap2_usb2_enable_5pinunitll(void)
-{
-        u32 r;
-
-        r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
-        r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
-        omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
-}
-
-static u32 __init omap2_usb0_init(unsigned nwires, unsigned is_device)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb_devconf_clear(0, USB_BIDIR_TLL);
-
-        if (nwires == 0)
-                return 0;
-
-        if (is_device)
-                omap_mux_init_signal("usb0_puen", 0);
-
-        omap_mux_init_signal("usb0_dat", 0);
-        omap_mux_init_signal("usb0_txen", 0);
-        omap_mux_init_signal("usb0_se0", 0);
-        if (nwires != 3)
-                omap_mux_init_signal("usb0_rcv", 0);
-
-        switch (nwires) {
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(0, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(0, USB_BIDIR);
-                break;
-        case 6:
-                syscon1 = 3;
-                omap_mux_init_signal("usb0_vp", 0);
-                omap_mux_init_signal("usb0_vm", 0);
-                omap2_usb_devconf_set(0, USB_UNIDIR);
-                break;
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        0, nwires);
-        }
-
-        return syscon1 << 16;
-}
-
-static u32 __init omap2_usb1_init(unsigned nwires)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
-
-        if (nwires == 0)
-                return 0;
-
-        /* NOTE:  board-specific code must set up pin muxing for usb1,
-         * since each signal could come out on either of two balls.
-         */
-
-        switch (nwires) {
-        case 2:
-                /* NOTE: board-specific code must override this setting if
-                 * this TLL link is not using DP/DM
-                 */
-                syscon1 = 1;
-                omap2_usb_devconf_set(1, USB_BIDIR_TLL);
-                break;
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(1, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(1, USB_BIDIR);
-                break;
-        case 6:
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        1, nwires);
-        }
-
-        return syscon1 << 20;
-}
-
-static u32 __init omap2_usb2_init(unsigned nwires, unsigned alt_pingroup)
-{
-        u32     syscon1 = 0;
-
-        omap2_usb2_disable_5pinbitll();
-        alt_pingroup = 0;
-
-        /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */
-        if (alt_pingroup || nwires == 0)
-                return 0;
-
-        omap_mux_init_signal("usb2_dat", 0);
-        omap_mux_init_signal("usb2_se0", 0);
-        if (nwires > 2)
-                omap_mux_init_signal("usb2_txen", 0);
-        if (nwires > 3)
-                omap_mux_init_signal("usb2_rcv", 0);
-
-        switch (nwires) {
-        case 2:
-                /* NOTE: board-specific code must override this setting if
-                 * this TLL link is not using DP/DM
-                 */
-                syscon1 = 1;
-                omap2_usb_devconf_set(2, USB_BIDIR_TLL);
-                break;
-        case 3:
-                syscon1 = 2;
-                omap2_usb_devconf_set(2, USB_BIDIR);
-                break;
-        case 4:
-                syscon1 = 1;
-                omap2_usb_devconf_set(2, USB_BIDIR);
-                break;
-        case 5:
-                /* NOTE: board-specific code must mux this setting depending
-                 * on TLL link using DP/DM.  Something must also
-                 * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED}
-                 * 2420: hdq_sio.usb2_tllse0 or vlynq_rx0.usb2_tllse0
-                 * 2430: hdq_sio.usb2_tllse0 or sdmmc2_dat0.usb2_tllse0
-                 */
-
-                syscon1 = 3;
-                omap2_usb2_enable_5pinunitll();
-                break;
-        case 6:
-        default:
-                printk(KERN_ERR "illegal usb%d %d-wire transceiver\n",
-                        2, nwires);
-        }
-
-        return syscon1 << 24;
-}
-
-void __init omap2_usbfs_init(struct omap_usb_config *pdata)
-{
-        struct clk *ick;
-
-        if (!cpu_is_omap24xx())
-                return;
-
-        ick = clk_get(NULL, "usb_l4_ick");
-        if (IS_ERR(ick))
-                return;
-
-        clk_enable(ick);
-        pdata->usb0_init = omap2_usb0_init;
-        pdata->usb1_init = omap2_usb1_init;
-        pdata->usb2_init = omap2_usb2_init;
-        udc_device_init(pdata);
-        ohci_device_init(pdata);
-        otg_device_init(pdata);
-        omap_otg_init(pdata);
-        clk_disable(ick);
-        clk_put(ick);
-}
-
-#endif
diff --git a/arch/arm/mach-omap2/voltage.h b/arch/arm/mach-omap2/voltage.h
index 16a1b092cf36..a7c43c1042be 100644
--- a/arch/arm/mach-omap2/voltage.h
+++ b/arch/arm/mach-omap2/voltage.h
@@ -156,6 +156,7 @@ int omap_voltage_late_init(void);
 
 extern void omap2xxx_voltagedomains_init(void);
 extern void omap3xxx_voltagedomains_init(void);
+extern void am33xx_voltagedomains_init(void);
 extern void omap44xx_voltagedomains_init(void);
 
 struct voltagedomain *voltdm_lookup(const char *name);
diff --git a/arch/arm/mach-omap2/voltagedomains33xx_data.c b/arch/arm/mach-omap2/voltagedomains33xx_data.c
new file mode 100644
index 000000000000..965458dc0cb9
--- /dev/null
+++ b/arch/arm/mach-omap2/voltagedomains33xx_data.c
@@ -0,0 +1,43 @@
+/*
+ * AM33XX voltage domain data
+ *
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "voltage.h"
+
+static struct voltagedomain am33xx_voltdm_mpu = {
+        .name           = "mpu",
+};
+
+static struct voltagedomain am33xx_voltdm_core = {
+        .name           = "core",
+};
+
+static struct voltagedomain am33xx_voltdm_rtc = {
+        .name           = "rtc",
+};
+
+static struct voltagedomain *voltagedomains_am33xx[] __initdata = {
+        &am33xx_voltdm_mpu,
+        &am33xx_voltdm_core,
+        &am33xx_voltdm_rtc,
+        NULL,
+};
+
+void __init am33xx_voltagedomains_init(void)
+{
+        voltdm_init(voltagedomains_am33xx);
+}
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 8702ecfaab30..14a81c2317a4 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -144,7 +144,8 @@ static struct clk_lookup s3c2416_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &hsspi_mux.clk),
+        /* s3c2443-spi.0 is used on s3c2416 and s3c2450 as well */
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &hsspi_mux.clk),
 };
 
 void __init s3c2416_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2440.c b/arch/arm/mach-s3c24xx/clock-s3c2440.c
index 414364eb426c..cb2883d553b5 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2440.c
@@ -106,7 +106,7 @@ static struct clk s3c2440_clk_cam_upll = {
 static struct clk s3c2440_clk_ac97 = {
         .name           = "ac97",
         .enable         = s3c2410_clkcon_enable,
-        .ctrlbit        = S3C2440_CLKCON_CAMERA,
+        .ctrlbit        = S3C2440_CLKCON_AC97,
 };
 
 static unsigned long  s3c2440_fclk_n_getrate(struct clk *clk)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index a4c5a520d994..7f689ce1be61 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -181,7 +181,7 @@ static struct clk *clks[] __initdata = {
 
 static struct clk_lookup s3c2443_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_hsspi.clk),
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk),
 };
 
 void __init s3c2443_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c24xx/common-s3c2443.c b/arch/arm/mach-s3c24xx/common-s3c2443.c
index aeeb2be283fa..aeb4a24ff3ed 100644
--- a/arch/arm/mach-s3c24xx/common-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/common-s3c2443.c
@@ -559,7 +559,7 @@ static struct clk hsmmc1_clk = {
 
 static struct clk hsspi_clk = {
         .name           = "spi",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s3c2443-spi.0",
         .parent         = &clk_p,
         .enable         = s3c2443_clkcon_enable_p,
         .ctrlbit        = S3C2443_PCLKCON_HSSPI,
@@ -633,7 +633,7 @@ static struct clk_lookup s3c2443_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &hsspi_clk),
+        CLKDEV_INIT("s3c2443-spi.0", "spi_busclk0", &hsspi_clk),
 };
 
 void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 084604be6ad1..87e75a250d5e 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -182,19 +182,21 @@ static struct platform_device __initdata *smdk_devs[] = {
         &smdk_led7,
 };
 
+static const struct gpio smdk_led_gpios[] = {
+        { S3C2410_GPF(4), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(5), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(6), GPIOF_OUT_INIT_HIGH, NULL },
+        { S3C2410_GPF(7), GPIOF_OUT_INIT_HIGH, NULL },
+};
+
 void __init smdk_machine_init(void)
 {
         /* Configure the LEDs (even if we have no LED support)*/
 
-        s3c_gpio_cfgpin(S3C2410_GPF(4), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(5), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(6), S3C2410_GPIO_OUTPUT);
-        s3c_gpio_cfgpin(S3C2410_GPF(7), S3C2410_GPIO_OUTPUT);
-
-        s3c2410_gpio_setpin(S3C2410_GPF(4), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(5), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(6), 1);
-        s3c2410_gpio_setpin(S3C2410_GPF(7), 1);
+        int ret = gpio_request_array(smdk_led_gpios,
+                                     ARRAY_SIZE(smdk_led_gpios));
+        if (!WARN_ON(ret < 0))
+                gpio_free_array(smdk_led_gpios, ARRAY_SIZE(smdk_led_gpios));
 
         if (machine_is_smdk2443())
                 smdk_nand_info.twrph0 = 50;
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 56cdd34cce41..0c9e9a785ef6 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -41,7 +41,6 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 
-#include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 #include <plat/regs-serial.h>
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h b/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
deleted file mode 100644
index 4c38b39b741d..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/bast-pmu.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/bast-pmu.h
- *
- * Copyright (c) 2003-2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *      Vincent Sanders <vince@simtec.co.uk>
- *
- * Machine BAST - Power Management chip
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_BASTPMU_H
-#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
-
-#define BASTPMU_REG_IDENT       (0x00)
-#define BASTPMU_REG_VERSION     (0x01)
-#define BASTPMU_REG_DDCCTRL     (0x02)
-#define BASTPMU_REG_POWER       (0x03)
-#define BASTPMU_REG_RESET       (0x04)
-#define BASTPMU_REG_GWO         (0x05)
-#define BASTPMU_REG_WOL         (0x06)
-#define BASTPMU_REG_WOR         (0x07)
-#define BASTPMU_REG_UID         (0x09)
-
-#define BASTPMU_EEPROM          (0xC0)
-
-#define BASTPMU_EEP_UID         (BASTPMU_EEPROM + 0)
-#define BASTPMU_EEP_WOL         (BASTPMU_EEPROM + 8)
-#define BASTPMU_EEP_WOR         (BASTPMU_EEPROM + 9)
-
-#define BASTPMU_IDENT_0         0x53
-#define BASTPMU_IDENT_1         0x42
-#define BASTPMU_IDENT_2         0x50
-#define BASTPMU_IDENT_3         0x4d
-
-#define BASTPMU_RESET_GUARD     (0x55)
-
-#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
index 019ea86057f6..3890a05948fb 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gpio-nrs.h
@@ -93,26 +93,5 @@ enum s3c_gpio_number {
 #define S3C2410_GPL(_nr)        (S3C2410_GPIO_L_START + (_nr))
 #define S3C2410_GPM(_nr)        (S3C2410_GPIO_M_START + (_nr))
 
-/* compatibility until drivers can be modified */
-
-#define S3C2410_GPA0    S3C2410_GPA(0)
-#define S3C2410_GPA1    S3C2410_GPA(1)
-#define S3C2410_GPA3    S3C2410_GPA(3)
-#define S3C2410_GPA7    S3C2410_GPA(7)
-
-#define S3C2410_GPE0    S3C2410_GPE(0)
-#define S3C2410_GPE1    S3C2410_GPE(1)
-#define S3C2410_GPE2    S3C2410_GPE(2)
-#define S3C2410_GPE3    S3C2410_GPE(3)
-#define S3C2410_GPE4    S3C2410_GPE(4)
-#define S3C2410_GPE5    S3C2410_GPE(5)
-#define S3C2410_GPE6    S3C2410_GPE(6)
-#define S3C2410_GPE7    S3C2410_GPE(7)
-#define S3C2410_GPE8    S3C2410_GPE(8)
-#define S3C2410_GPE9    S3C2410_GPE(9)
-#define S3C2410_GPE10   S3C2410_GPE(10)
-
-#define S3C2410_GPH10   S3C2410_GPH(10)
-
 #endif /* __MACH_GPIONRS_H */
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/gta02.h b/arch/arm/mach-s3c24xx/include/mach/gta02.h
index 3a56a229cac6..217393482153 100644
--- a/arch/arm/mach-s3c24xx/include/mach/gta02.h
+++ b/arch/arm/mach-s3c24xx/include/mach/gta02.h
@@ -3,82 +3,13 @@
 
 #include <mach/regs-gpio.h>
 
-/* Different hardware revisions, passed in ATAG_REVISION by u-boot */
-#define GTA02v1_SYSTEM_REV      0x00000310
-#define GTA02v2_SYSTEM_REV      0x00000320
-#define GTA02v3_SYSTEM_REV      0x00000330
-#define GTA02v4_SYSTEM_REV      0x00000340
-#define GTA02v5_SYSTEM_REV      0x00000350
-/* since A7 is basically same as A6, we use A6 PCB ID */
-#define GTA02v6_SYSTEM_REV      0x00000360
-
-#define GTA02_GPIO_n3DL_GSM     S3C2410_GPA(13) /* v1 + v2 + v3 only */
-
-#define GTA02_GPIO_PWR_LED1     S3C2410_GPB(0)
-#define GTA02_GPIO_PWR_LED2     S3C2410_GPB(1)
 #define GTA02_GPIO_AUX_LED      S3C2410_GPB(2)
-#define GTA02_GPIO_VIBRATOR_ON  S3C2410_GPB(3)
-#define GTA02_GPIO_MODEM_RST    S3C2410_GPB(5)
-#define GTA02_GPIO_BT_EN        S3C2410_GPB(6)
-#define GTA02_GPIO_MODEM_ON     S3C2410_GPB(7)
-#define GTA02_GPIO_EXTINT8      S3C2410_GPB(8)
 #define GTA02_GPIO_USB_PULLUP   S3C2410_GPB(9)
-
-#define GTA02_GPIO_PIO5         S3C2410_GPC(5)  /* v3 + v4 only */
-
-#define GTA02v3_GPIO_nG1_CS     S3C2410_GPD(12) /* v3 + v4 only */
-#define GTA02v3_GPIO_nG2_CS     S3C2410_GPD(13) /* v3 + v4 only */
-#define GTA02v5_GPIO_HDQ        S3C2410_GPD(14)   /* v5 + */
-
-#define GTA02_GPIO_nG1_INT      S3C2410_GPF(0)
-#define GTA02_GPIO_IO1          S3C2410_GPF(1)
-#define GTA02_GPIO_PIO_2        S3C2410_GPF(2)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_JACK_INSERT  S3C2410_GPF(4)
-#define GTA02_GPIO_WLAN_GPIO1   S3C2410_GPF(5)  /* v2 + v3 + v4 only */
 #define GTA02_GPIO_AUX_KEY      S3C2410_GPF(6)
 #define GTA02_GPIO_HOLD_KEY     S3C2410_GPF(7)
-
-#define GTA02_GPIO_3D_IRQ       S3C2410_GPG(4)
-#define GTA02v2_GPIO_nG2_INT    S3C2410_GPG(8)  /* v2 + v3 + v4 only */
-#define GTA02v3_GPIO_nUSB_OC    S3C2410_GPG(9)  /* v3 + v4 only */
-#define GTA02v3_GPIO_nUSB_FLT   S3C2410_GPG(10) /* v3 + v4 only */
-#define GTA02v3_GPIO_nGSM_OC    S3C2410_GPG(11) /* v3 + v4 only */
-
 #define GTA02_GPIO_AMP_SHUT     S3C2410_GPJ(1)  /* v2 + v3 + v4 only */
-#define GTA02v1_GPIO_WLAN_GPIO10        S3C2410_GPJ(2)
 #define GTA02_GPIO_HP_IN        S3C2410_GPJ(2)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_INT0         S3C2410_GPJ(3)  /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nGSM_EN      S3C2410_GPJ(4)
-#define GTA02_GPIO_3D_RESET     S3C2410_GPJ(5)
-#define GTA02_GPIO_nDL_GSM      S3C2410_GPJ(6)  /* v4 + v5 only */
-#define GTA02_GPIO_WLAN_GPIO0   S3C2410_GPJ(7)
-#define GTA02v1_GPIO_BAT_ID     S3C2410_GPJ(8)
-#define GTA02_GPIO_KEEPACT      S3C2410_GPJ(8)
-#define GTA02v1_GPIO_HP_IN      S3C2410_GPJ(10)
-#define GTA02_CHIP_PWD          S3C2410_GPJ(11) /* v2 + v3 + v4 only */
-#define GTA02_GPIO_nWLAN_RESET  S3C2410_GPJ(12) /* v2 + v3 + v4 only */
 
-#define GTA02_IRQ_GSENSOR_1     IRQ_EINT0
-#define GTA02_IRQ_MODEM         IRQ_EINT1
-#define GTA02_IRQ_PIO_2         IRQ_EINT2       /* v2 + v3 + v4 only */
-#define GTA02_IRQ_nJACK_INSERT  IRQ_EINT4
-#define GTA02_IRQ_WLAN_GPIO1    IRQ_EINT5
-#define GTA02_IRQ_AUX           IRQ_EINT6
-#define GTA02_IRQ_nHOLD         IRQ_EINT7
 #define GTA02_IRQ_PCF50633      IRQ_EINT9
-#define GTA02_IRQ_3D            IRQ_EINT12
-#define GTA02_IRQ_GSENSOR_2     IRQ_EINT16      /* v2 + v3 + v4 only */
-#define GTA02v3_IRQ_nUSB_OC     IRQ_EINT17      /* v3 + v4 only */
-#define GTA02v3_IRQ_nUSB_FLT    IRQ_EINT18      /* v3 + v4 only */
-#define GTA02v3_IRQ_nGSM_OC     IRQ_EINT19      /* v3 + v4 only */
-
-/* returns 00 000 on GTA02 A5 and earlier, A6 returns 01 001 */
-#define GTA02_PCB_ID1_0         S3C2410_GPC(13)
-#define GTA02_PCB_ID1_1         S3C2410_GPC(15)
-#define GTA02_PCB_ID1_2         S3C2410_GPD(0)
-#define GTA02_PCB_ID2_0         S3C2410_GPD(3)
-#define GTA02_PCB_ID2_1         S3C2410_GPD(4)
-
-int gta02_get_pcb_revision(void);
 
 #endif /* _GTA02_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
index cac1ad6b582c..a11a638bd599 100644
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c24xx/include/mach/regs-gpio.h
@@ -302,7 +302,7 @@
 /* S3C2410:
  * Port G consists of 8 GPIO/IRQ/Special function
  *
- * GPGCON has 2 bits for each of the input pins on port F
+ * GPGCON has 2 bits for each of the input pins on port G
  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  *
  * pull up works like all other ports.
@@ -366,7 +366,7 @@
 
 /* Port H consists of11 GPIO/serial/Misc pins
  *
- * GPGCON has 2 bits for each of the input pins on port F
+ * GPHCON has 2 bits for each of the input pins on port H
  *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
  *
  * pull up works like all other ports.
@@ -427,6 +427,19 @@
  * for the 2412/2413 from the 2410/2440/2442
 */
 
+/*
+ * Port J consists of 13 GPIO/Camera pins. GPJCON has 2 bits
+ * for each of the pins on port J.
+ *   00 - input, 01 output, 10 - camera
+ *
+ * Pull up works like all other ports.
+ */
+
+#define S3C2413_GPJCON     S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT     S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP      S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON  S3C2410_GPIOREG(0x8C)
+
 /* S3C2443 and above */
 #define S3C2440_GPJCON     S3C2410_GPIOREG(0xD0)
 #define S3C2440_GPJDAT     S3C2410_GPIOREG(0xD4)
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h b/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
deleted file mode 100644
index 19575e061114..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-gpioj.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-gpioj.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2440 GPIO J register definitions
-*/
-
-
-#ifndef __ASM_ARCH_REGS_GPIOJ_H
-#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
-
-/* Port J consists of 13 GPIO/Camera pins
- *
- * GPJCON has 2 bits for each of the input pins on port F
- *   00 = 0 input, 1 output, 2 Camera
- *
- * pull up works like all other ports.
-*/
-
-#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
-#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
-#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
-#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
-
-#define S3C2440_GPJ0_OUTP       (0x01 << 0)
-#define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
-
-#define S3C2440_GPJ1_OUTP       (0x01 << 2)
-#define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
-
-#define S3C2440_GPJ2_OUTP       (0x01 << 4)
-#define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
-
-#define S3C2440_GPJ3_OUTP       (0x01 << 6)
-#define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
-
-#define S3C2440_GPJ4_OUTP       (0x01 << 8)
-#define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
-
-#define S3C2440_GPJ5_OUTP       (0x01 << 10)
-#define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
-
-#define S3C2440_GPJ6_OUTP       (0x01 << 12)
-#define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
-
-#define S3C2440_GPJ7_OUTP       (0x01 << 14)
-#define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
-
-#define S3C2440_GPJ8_OUTP       (0x01 << 16)
-#define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
-
-#define S3C2440_GPJ9_OUTP       (0x01 << 18)
-#define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
-
-#define S3C2440_GPJ10_OUTP      (0x01 << 20)
-#define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
-
-#define S3C2440_GPJ11_OUTP      (0x01 << 22)
-#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
-
-#define S3C2440_GPJ12_OUTP      (0x01 << 24)
-#define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
-
-#endif  /* __ASM_ARCH_REGS_GPIOJ_H */
-
diff --git a/arch/arm/mach-s3c24xx/mach-gta02.c b/arch/arm/mach-s3c24xx/mach-gta02.c
index 0f29f64a3eeb..92e1f93a6bca 100644
--- a/arch/arm/mach-s3c24xx/mach-gta02.c
+++ b/arch/arm/mach-s3c24xx/mach-gta02.c
@@ -71,7 +71,6 @@
 
 #include <mach/regs-irq.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/fb.h>
 
 #include <plat/usb-control.h>
diff --git a/arch/arm/mach-s3c24xx/mach-mini2440.c b/arch/arm/mach-s3c24xx/mach-mini2440.c
index f092b188ab70..bd6d2525debe 100644
--- a/arch/arm/mach-s3c24xx/mach-mini2440.c
+++ b/arch/arm/mach-s3c24xx/mach-mini2440.c
@@ -634,8 +634,8 @@ static void __init mini2440_init(void)
         s3c_gpio_cfgpin(S3C2410_GPC(0), S3C2410_GPC0_LEND);
 
         /* Turn the backlight early on */
-        WARN_ON(gpio_request(S3C2410_GPG(4), "backlight"));
-        gpio_direction_output(S3C2410_GPG(4), 1);
+        WARN_ON(gpio_request_one(S3C2410_GPG(4), GPIOF_OUT_INIT_HIGH, NULL));
+        gpio_free(S3C2410_GPG(4));
 
         /* remove pullup on optional PWM backlight -- unused on 3.5 and 7"s */
         s3c_gpio_setpull(S3C2410_GPB(1), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index b868dddcb836..678bbca2b5e5 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -47,7 +47,6 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <mach/regs-gpio.h>
 #include <mach/leds-gpio.h>
 #include <mach/regs-lcd.h>
 #include <plat/regs-serial.h>
@@ -325,8 +324,9 @@ static void __init qt2410_machine_init(void)
         }
         s3c24xx_fb_set_platdata(&qt2410_fb_info);
 
-        s3c_gpio_cfgpin(S3C2410_GPB(0), S3C2410_GPIO_OUTPUT);
-        s3c2410_gpio_setpin(S3C2410_GPB(0), 1);
+        /* set initial state of the LED GPIO */
+        WARN_ON(gpio_request_one(S3C2410_GPB(0), GPIOF_OUT_INIT_HIGH, NULL));
+        gpio_free(S3C2410_GPB(0));
 
         s3c24xx_udc_set_platdata(&qt2410_udc_cfg);
         s3c_i2c0_set_platdata(NULL);
diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
index a6762aae4727..7ee73f27f207 100644
--- a/arch/arm/mach-s3c24xx/mach-rx1950.c
+++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
@@ -42,7 +42,6 @@
 #include <asm/mach-types.h>
 
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-lcd.h>
 #include <mach/h1940.h>
 #include <mach/fb.h>
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2410.c b/arch/arm/mach-s3c24xx/pm-s3c2410.c
index 03f706dd6009..949ae05e07c5 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2410.c
@@ -77,8 +77,10 @@ static void s3c2410_pm_prepare(void)
                 __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
         }
 
-        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
+        if (machine_is_aml_m5900()) {
+                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
+                gpio_free(S3C2410_GPF(2));
+        }
 
         if (machine_is_rx1950()) {
                 /* According to S3C2442 user's manual, page 7-17,
@@ -103,8 +105,10 @@ static void s3c2410_pm_resume(void)
         tmp &= S3C2410_GSTATUS2_OFFRESET;
         __raw_writel(tmp, S3C2410_GSTATUS2);
 
-        if ( machine_is_aml_m5900() )
-                s3c2410_gpio_setpin(S3C2410_GPF(2), 0);
+        if (machine_is_aml_m5900()) {
+                gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
+                gpio_free(S3C2410_GPF(2));
+        }
 }
 
 struct syscore_ops s3c2410_pm_syscore_ops = {
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index d04588506ec4..c60f67a75aff 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -26,7 +26,6 @@
 #include <asm/irq.h>
 
 #include <mach/regs-power.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-dsc.h>
 
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index d4bc7f960bbb..6c5f4031ff0c 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -39,7 +39,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-power.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-dsc.h>
 #include <plat/regs-spi.h>
 #include <mach/regs-s3c2412.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index 6f74118f60c6..b0b60a1154d6 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -36,7 +36,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
-#include <mach/regs-gpioj.h>
 #include <mach/regs-dsc.h>
 
 #include <plat/s3c2410.h>
diff --git a/arch/arm/mach-s3c24xx/setup-spi.c b/arch/arm/mach-s3c24xx/setup-spi.c
index 5712c85f39b1..3d47e023ce94 100644
--- a/arch/arm/mach-s3c24xx/setup-spi.c
+++ b/arch/arm/mach-s3c24xx/setup-spi.c
@@ -13,20 +13,12 @@
 #include <linux/platform_device.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #include <mach/hardware.h>
 #include <mach/regs-gpio.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-        .high_speed     = 1,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *pdev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         /* enable hsspi bit in misccr */
         s3c2410_modify_misccr(S3C2416_MISCCR_HSSPI_EN2, 1);
diff --git a/arch/arm/mach-s3c24xx/setup-ts.c b/arch/arm/mach-s3c24xx/setup-ts.c
index ed2638663675..4e11affce3a8 100644
--- a/arch/arm/mach-s3c24xx/setup-ts.c
+++ b/arch/arm/mach-s3c24xx/setup-ts.c
@@ -16,7 +16,6 @@
 struct platform_device; /* don't need the contents */
 
 #include <mach/hardware.h>
-#include <mach/regs-gpio.h>
 
 /**
  * s3c24xx_ts_cfg_gpio - configure gpio for s3c2410 systems
@@ -27,8 +26,5 @@ struct platform_device; /* don't need the contents */
  */
 void s3c24xx_ts_cfg_gpio(struct platform_device *dev)
 {
-        s3c2410_gpio_cfgpin(S3C2410_GPG(12), S3C2410_GPG12_XMON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPG13_nXPON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPG14_YMON);
-        s3c2410_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPG15_nYPON);
+        s3c_gpio_cfgpin_range(S3C2410_GPG(12), 4, S3C_GPIO_SFN(3));
 }
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index 52f079a691cb..28041e83dc82 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -178,13 +178,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = S3C_CLKCON_PCLK_KEYPAD,
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s3c6410-spi.0",
                 .parent         = &clk_p,
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI0,
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s3c6410-spi.1",
                 .parent         = &clk_p,
                 .enable         = s3c64xx_pclk_ctrl,
                 .ctrlbit        = S3C_CLKCON_PCLK_SPI1,
@@ -331,7 +331,7 @@ static struct clk init_clocks_off[] = {
 
 static struct clk clk_48m_spi0 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s3c6410-spi.0",
         .parent         = &clk_48m,
         .enable         = s3c64xx_sclk_ctrl,
         .ctrlbit        = S3C_CLKCON_SCLK_SPI0_48,
@@ -339,7 +339,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.1",
+        .devname        = "s3c6410-spi.1",
         .parent         = &clk_48m,
         .enable         = s3c64xx_sclk_ctrl,
         .ctrlbit        = S3C_CLKCON_SCLK_SPI1_48,
@@ -802,7 +802,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "spi-bus",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s3c6410-spi.0",
                 .ctrlbit        = S3C_CLKCON_SCLK_SPI0,
                 .enable         = s3c64xx_sclk_ctrl,
         },
@@ -814,7 +814,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "spi-bus",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s3c6410-spi.1",
                 .ctrlbit        = S3C_CLKCON_SCLK_SPI1,
                 .enable         = s3c64xx_sclk_ctrl,
         },
@@ -858,10 +858,10 @@ static struct clk_lookup s3c64xx_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_48m_spi0),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_48m_spi1),
+        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s3c6410-spi.0", "spi_busclk2", &clk_48m_spi0),
+        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s3c6410-spi.1", "spi_busclk2", &clk_48m_spi1),
 };
 
 #define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index fe1a98cf0e4c..57b1ff4b2d7c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,6 +21,7 @@
  */
 enum dma_ch {
         /* DMA0/SDMA0 */
+        DMACH_DT_PROP = -1, /* not yet supported, do not use */
         DMACH_UART0 = 0,
         DMACH_UART0_SRC2,
         DMACH_UART1,
diff --git a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h b/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
deleted file mode 100644
index 9d0c43b4b687..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s3c64xx/include/mach/spi-clocks.h
- *
- * Copyright (C) 2009 Samsung Electronics Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S3C64XX_PLAT_SPI_CLKS_H
-#define __S3C64XX_PLAT_SPI_CLKS_H __FILE__
-
-#define S3C64XX_SPI_SRCCLK_PCLK         0
-#define S3C64XX_SPI_SRCCLK_SPIBUS       1
-#define S3C64XX_SPI_SRCCLK_48M          2
-
-#endif /* __S3C64XX_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index d0c352d861f8..6dd4fae33a82 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -799,7 +799,7 @@ static void __init crag6410_machine_init(void)
         i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
 
         samsung_keypad_set_platdata(&crag6410_keypad_data);
-        s3c64xx_spi0_set_platdata(&s3c64xx_spi0_pdata, 0, 1);
+        s3c64xx_spi0_set_platdata(NULL, 0, 1);
 
         platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
 
diff --git a/arch/arm/mach-s3c64xx/setup-spi.c b/arch/arm/mach-s3c64xx/setup-spi.c
index d9592ad7a825..4dc53450d715 100644
--- a/arch/arm/mach-s3c64xx/setup-spi.c
+++ b/arch/arm/mach-s3c64xx/setup-spi.c
@@ -9,19 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S3C64XX_GPC(0), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -30,13 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S3C64XX_GPC(4), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index ee1e8e7f5631..000445596ec4 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -227,13 +227,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 22),
@@ -467,7 +467,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .ctrlbit        = (1 << 20),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -479,7 +479,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .ctrlbit        = (1 << 21),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -519,8 +519,8 @@ static struct clk_lookup s5p6440_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index dae6a13f43bb..f3e0ef3d27c9 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -236,13 +236,13 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 17),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 21),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .parent         = &clk_pclk_low.clk,
                 .enable         = s5p64x0_pclk_ctrl,
                 .ctrlbit        = (1 << 22),
@@ -528,7 +528,7 @@ static struct clksrc_clk clk_sclk_uclk = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5p64x0-spi.0",
                 .ctrlbit        = (1 << 20),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -540,7 +540,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5p64x0-spi.1",
                 .ctrlbit        = (1 << 21),
                 .enable         = s5p64x0_sclk_ctrl,
         },
@@ -562,8 +562,8 @@ static struct clk_lookup s5p6450_clk_lookup[] = {
         CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
         CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
         CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
index 2ee5dc069b37..9c4ce085f585 100644
--- a/arch/arm/mach-s5p64x0/dma.c
+++ b/arch/arm/mach-s5p64x0/dma.c
@@ -36,8 +36,6 @@
 #include <plat/devs.h>
 #include <plat/irqs.h>
 
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
 static u8 s5p6440_pdma_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
diff --git a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h b/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
deleted file mode 100644
index 170a20a9643a..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* linux/arch/arm/mach-s5p64x0/include/mach/spi-clocks.h
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_SPI_CLKS_H
-#define __ASM_ARCH_SPI_CLKS_H __FILE__
-
-#define S5P64X0_SPI_SRCCLK_PCLK         0
-#define S5P64X0_SPI_SRCCLK_SCLK         1
-
-#endif /* __ASM_ARCH_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
index e9b841240352..7664356720ca 100644
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ b/arch/arm/mach-s5p64x0/setup-spi.c
@@ -9,21 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/cpu.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         if (soc_is_s5p6450())
                 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
@@ -36,13 +25,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         if (soc_is_s5p6450())
                 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 16eca4ea2010..926219791f0d 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -564,19 +564,19 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pc100-spi.0",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pc100-spi.1",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pc100-spi.2",
                 .parent         = &clk_div_d1_bus.clk,
                 .enable         = s5pc100_d1_4_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -702,7 +702,7 @@ static struct clk clk_hsmmc0 = {
 
 static struct clk clk_48m_spi0 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.0",
+        .devname        = "s5pc100-spi.0",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 7),
@@ -710,7 +710,7 @@ static struct clk clk_48m_spi0 = {
 
 static struct clk clk_48m_spi1 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.1",
+        .devname        = "s5pc100-spi.1",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 8),
@@ -718,7 +718,7 @@ static struct clk clk_48m_spi1 = {
 
 static struct clk clk_48m_spi2 = {
         .name           = "spi_48m",
-        .devname        = "s3c64xx-spi.2",
+        .devname        = "s5pc100-spi.2",
         .parent         = &clk_mout_48m.clk,
         .enable         = s5pc100_sclk0_ctrl,
         .ctrlbit        = (1 << 9),
@@ -1085,7 +1085,7 @@ static struct clksrc_clk clk_sclk_mmc2 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pc100-spi.0",
                 .ctrlbit        = (1 << 4),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1097,7 +1097,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pc100-spi.1",
                 .ctrlbit        = (1 << 5),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1109,7 +1109,7 @@ static struct clksrc_clk clk_sclk_spi1 = {
 static struct clksrc_clk clk_sclk_spi2 = {
         .clk    = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pc100-spi.2",
                 .ctrlbit        = (1 << 6),
                 .enable         = s5pc100_sclk0_ctrl,
         },
@@ -1315,12 +1315,12 @@ static struct clk_lookup s5pc100_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2),
-        CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
+        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
+        CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
+        CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
+        CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
 };
 
 void __init s5pc100_register_clocks(void)
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
index afd8db2d5991..b1418409709e 100644
--- a/arch/arm/mach-s5pc100/dma.c
+++ b/arch/arm/mach-s5pc100/dma.c
@@ -33,8 +33,6 @@
 #include <mach/irqs.h>
 #include <mach/dma.h>
 
-static u64 dma_dmamask = DMA_BIT_MASK(32);
-
 static u8 pdma0_peri[] = {
         DMACH_UART0_RX,
         DMACH_UART0_TX,
diff --git a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h b/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
deleted file mode 100644
index 65e426370bb2..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s5pc100/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5PC100_PLAT_SPI_CLKS_H
-#define __S5PC100_PLAT_SPI_CLKS_H __FILE__
-
-#define S5PC100_SPI_SRCCLK_PCLK         0
-#define S5PC100_SPI_SRCCLK_48M          1
-#define S5PC100_SPI_SRCCLK_SPIBUS       2
-
-#endif /* __S5PC100_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
index 431a6f747caa..183567961de1 100644
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ b/arch/arm/mach-s5pc100/setup-spi.c
@@ -9,20 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -31,14 +21,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
                                 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
@@ -47,14 +30,7 @@ int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI2
-struct s3c64xx_spi_info s3c64xx_spi2_pdata __initdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 13,
-        .high_speed     = 1,
-        .tx_st_done     = 21,
-};
-
-int s3c64xx_spi2_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi2_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
         s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 09609d50961d..fcdf52dbcc49 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -445,19 +445,19 @@ static struct clk init_clocks_off[] = {
                 .ctrlbit        = (1 << 11),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pv210-spi.0",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<12),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pv210-spi.1",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<13),
         }, {
                 .name           = "spi",
-                .devname        = "s3c64xx-spi.2",
+                .devname        = "s5pv210-spi.2",
                 .parent         = &clk_pclk_psys.clk,
                 .enable         = s5pv210_clk_ip3_ctrl,
                 .ctrlbit        = (1<<14),
@@ -1035,7 +1035,7 @@ static struct clksrc_clk clk_sclk_mmc3 = {
 static struct clksrc_clk clk_sclk_spi0 = {
         .clk            = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.0",
+                .devname        = "s5pv210-spi.0",
                 .enable         = s5pv210_clk_mask0_ctrl,
                 .ctrlbit        = (1 << 16),
         },
@@ -1047,7 +1047,7 @@ static struct clksrc_clk clk_sclk_spi0 = {
 static struct clksrc_clk clk_sclk_spi1 = {
         .clk            = {
                 .name           = "sclk_spi",
-                .devname        = "s3c64xx-spi.1",
+                .devname        = "s5pv210-spi.1",
                 .enable         = s5pv210_clk_mask0_ctrl,
                 .ctrlbit        = (1 << 17),
         },
@@ -1331,8 +1331,8 @@ static struct clk_lookup s5pv210_clk_lookup[] = {
         CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
         CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk),
         CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
-        CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
-        CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
+        CLKDEV_INIT("s5pv210-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
+        CLKDEV_INIT("s5pv210-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
 };
 
 void __init s5pv210_register_clocks(void)
diff --git a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h b/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
deleted file mode 100644
index 02acded5f73d..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/include/mach/spi-clocks.h
- *
- * Copyright (C) 2010 Samsung Electronics Co. Ltd.
- *      Jaswinder Singh <jassi.brar@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __S5PV210_PLAT_SPI_CLKS_H
-#define __S5PV210_PLAT_SPI_CLKS_H __FILE__
-
-#define S5PV210_SPI_SRCCLK_PCLK         0
-#define S5PV210_SPI_SRCCLK_SCLK         1
-
-#endif /* __S5PV210_PLAT_SPI_CLKS_H */
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c
index f43c5048a37d..81aecc162f82 100644
--- a/arch/arm/mach-s5pv210/setup-spi.c
+++ b/arch/arm/mach-s5pv210/setup-spi.c
@@ -9,20 +9,10 @@
  */
 
 #include <linux/gpio.h>
-#include <linux/platform_device.h>
-
 #include <plat/gpio-cfg.h>
-#include <plat/s3c64xx-spi.h>
 
 #ifdef CONFIG_S3C64XX_DEV_SPI0
-struct s3c64xx_spi_info s3c64xx_spi0_pdata = {
-        .fifo_lvl_mask  = 0x1ff,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi0_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PV210_GPB(0), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5PV210_GPB(0), S3C_GPIO_PULL_UP);
@@ -33,14 +23,7 @@ int s3c64xx_spi0_cfg_gpio(struct platform_device *dev)
 #endif
 
 #ifdef CONFIG_S3C64XX_DEV_SPI1
-struct s3c64xx_spi_info s3c64xx_spi1_pdata = {
-        .fifo_lvl_mask  = 0x7f,
-        .rx_lvl_offset  = 15,
-        .high_speed     = 1,
-        .tx_st_done     = 25,
-};
-
-int s3c64xx_spi1_cfg_gpio(struct platform_device *dev)
+int s3c64xx_spi1_cfg_gpio(void)
 {
         s3c_gpio_cfgpin(S5PV210_GPB(4), S3C_GPIO_SFN(2));
         s3c_gpio_setpull(S5PV210_GPB(4), S3C_GPIO_PULL_UP);
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index e859fcdb3d58..fde0d23121dc 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -22,8 +22,13 @@
 #include <mach/common.h>
 #include <mach/emev2.h>
 
+#ifdef CONFIG_ARCH_SH73A0
 #define is_sh73a0() (machine_is_ag5evm() || machine_is_kota2() || \
                         of_machine_is_compatible("renesas,sh73a0"))
+#else
+#define is_sh73a0() (0)
+#endif
+
 #define is_r8a7779() machine_is_marzen()
 
 #ifdef CONFIG_ARCH_EMEV2
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index 0f41bd1c47c3..66db5f13af84 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -87,7 +87,7 @@ void __init spear3xx_map_io(void)
 
 static void __init spear3xx_timer_init(void)
 {
-        char pclk_name[] = "pll3_48m_clk";
+        char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
         spear3xx_clk_init();
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 2e2e3596583e..9af67d003c62 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -423,7 +423,7 @@ void __init spear6xx_map_io(void)
 
 static void __init spear6xx_timer_init(void)
 {
-        char pclk_name[] = "pll3_48m_clk";
+        char pclk_name[] = "pll3_clk";
         struct clk *gpt_clk, *pclk;
 
         spear6xx_clk_init();
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 6a113a9bb87a..7c407393cd07 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -63,7 +63,6 @@ comment "Tegra board type"
 config MACH_HARMONY
        bool "Harmony board"
        depends on ARCH_TEGRA_2x_SOC
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Harmony development platform
 
@@ -71,7 +70,6 @@ config MACH_KAEN
        bool "Kaen board"
        depends on ARCH_TEGRA_2x_SOC
        select MACH_SEABOARD
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for the Kaen version of Seaboard
 
@@ -84,7 +82,6 @@ config MACH_PAZ00
 config MACH_SEABOARD
        bool "Seaboard board"
        depends on ARCH_TEGRA_2x_SOC
-       select MACH_HAS_SND_SOC_TEGRA_WM8903 if SND_SOC
        help
          Support for nVidia Seaboard development platform. It will
          also be included for some of the derivative boards that
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 2eb4445ddb14..90aae34245cd 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,9 +8,10 @@ obj-y                                   += timer.o
 obj-y                                   += fuse.o
 obj-y                                   += pmc.o
 obj-y                                   += flowctrl.o
+obj-y                                   += powergate.o
+obj-y                                   += apbio.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_CPU_IDLE)                  += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += powergate.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_clocks.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
 obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
@@ -18,7 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC)		+= tegra30_clocks.o
 obj-$(CONFIG_SMP)                       += platsmp.o headsmp.o
 obj-$(CONFIG_SMP)                       += reset.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
-obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o apbio.o
+obj-$(CONFIG_TEGRA_SYSTEM_DMA)          += dma.o
 obj-$(CONFIG_CPU_FREQ)                  += cpu-tegra.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 obj-$(CONFIG_USB_SUPPORT)               += usb_phy.o
diff --git a/arch/arm/mach-tegra/Makefile.boot b/arch/arm/mach-tegra/Makefile.boot
index 9a82094092d7..435f00ca3c58 100644
--- a/arch/arm/mach-tegra/Makefile.boot
+++ b/arch/arm/mach-tegra/Makefile.boot
@@ -2,9 +2,10 @@ zreladdr-$(CONFIG_ARCH_TEGRA_2x_SOC)	+= 0x00008000
 params_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00000100
 initrd_phys-$(CONFIG_ARCH_TEGRA_2x_SOC) := 0x00800000
 
-dtb-$(CONFIG_MACH_HARMONY) += tegra-harmony.dtb
-dtb-$(CONFIG_MACH_PAZ00) += tegra-paz00.dtb
-dtb-$(CONFIG_MACH_SEABOARD) += tegra-seaboard.dtb
-dtb-$(CONFIG_MACH_TRIMSLICE) += tegra-trimslice.dtb
-dtb-$(CONFIG_MACH_VENTANA) += tegra-ventana.dtb
-dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra-cardhu.dtb
+dtb-$(CONFIG_MACH_HARMONY) += tegra20-harmony.dtb
+dtb-$(CONFIG_MACH_PAZ00) += tegra20-paz00.dtb
+dtb-$(CONFIG_MACH_SEABOARD) += tegra20-seaboard.dtb
+dtb-$(CONFIG_MACH_TRIMSLICE) += tegra20-trimslice.dtb
+dtb-$(CONFIG_MACH_VENTANA) += tegra20-ventana.dtb
+dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20-whistler.dtb
+dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30-cardhu.dtb
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index e75451e517bd..dc0fe389be56 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -15,6 +15,9 @@
 
 #include <linux/kernel.h>
 #include <linux/io.h>
+#include <mach/iomap.h>
+#include <linux/of.h>
+#include <linux/dmaengine.h>
 #include <linux/dma-mapping.h>
 #include <linux/spinlock.h>
 #include <linux/completion.h>
@@ -22,17 +25,21 @@
 #include <linux/mutex.h>
 
 #include <mach/dma.h>
-#include <mach/iomap.h>
 
 #include "apbio.h"
 
+#if defined(CONFIG_TEGRA_SYSTEM_DMA) || defined(CONFIG_TEGRA20_APB_DMA)
 static DEFINE_MUTEX(tegra_apb_dma_lock);
-
-static struct tegra_dma_channel *tegra_apb_dma;
 static u32 *tegra_apb_bb;
 static dma_addr_t tegra_apb_bb_phys;
 static DECLARE_COMPLETION(tegra_apb_wait);
 
+static u32 tegra_apb_readl_direct(unsigned long offset);
+static void tegra_apb_writel_direct(u32 value, unsigned long offset);
+
+#if defined(CONFIG_TEGRA_SYSTEM_DMA)
+static struct tegra_dma_channel *tegra_apb_dma;
+
 bool tegra_apb_init(void)
 {
         struct tegra_dma_channel *ch;
@@ -72,13 +79,13 @@ static void apb_dma_complete(struct tegra_dma_req *req)
         complete(&tegra_apb_wait);
 }
 
-u32 tegra_apb_readl(unsigned long offset)
+static u32 tegra_apb_readl_using_dma(unsigned long offset)
 {
         struct tegra_dma_req req;
         int ret;
 
         if (!tegra_apb_dma && !tegra_apb_init())
-                return readl(IO_TO_VIRT(offset));
+                return tegra_apb_readl_direct(offset);
 
         mutex_lock(&tegra_apb_dma_lock);
         req.complete = apb_dma_complete;
@@ -108,13 +115,13 @@ u32 tegra_apb_readl(unsigned long offset)
         return *((u32 *)tegra_apb_bb);
 }
 
-void tegra_apb_writel(u32 value, unsigned long offset)
+static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
 {
         struct tegra_dma_req req;
         int ret;
 
         if (!tegra_apb_dma && !tegra_apb_init()) {
-                writel(value, IO_TO_VIRT(offset));
+                tegra_apb_writel_direct(value, offset);
                 return;
         }
 
@@ -143,3 +150,176 @@ void tegra_apb_writel(u32 value, unsigned long offset)
 
         mutex_unlock(&tegra_apb_dma_lock);
 }
+
+#else
+static struct dma_chan *tegra_apb_dma_chan;
+static struct dma_slave_config dma_sconfig;
+
+bool tegra_apb_dma_init(void)
+{
+        dma_cap_mask_t mask;
+
+        mutex_lock(&tegra_apb_dma_lock);
+
+        /* Check to see if we raced to setup */
+        if (tegra_apb_dma_chan)
+                goto skip_init;
+
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
+        tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL);
+        if (!tegra_apb_dma_chan) {
+                /*
+                 * This is common until the device is probed, so don't
+                 * shout about it.
+                 */
+                pr_debug("%s: can not allocate dma channel\n", __func__);
+                goto err_dma_alloc;
+        }
+
+        tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32),
+                &tegra_apb_bb_phys, GFP_KERNEL);
+        if (!tegra_apb_bb) {
+                pr_err("%s: can not allocate bounce buffer\n", __func__);
+                goto err_buff_alloc;
+        }
+
+        dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
+        dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
+        dma_sconfig.src_maxburst = 1;
+        dma_sconfig.dst_maxburst = 1;
+
+skip_init:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return true;
+
+err_buff_alloc:
+        dma_release_channel(tegra_apb_dma_chan);
+        tegra_apb_dma_chan = NULL;
+
+err_dma_alloc:
+        mutex_unlock(&tegra_apb_dma_lock);
+        return false;
+}
+
+static void apb_dma_complete(void *args)
+{
+        complete(&tegra_apb_wait);
+}
+
+static int do_dma_transfer(unsigned long apb_add,
+                enum dma_transfer_direction dir)
+{
+        struct dma_async_tx_descriptor *dma_desc;
+        int ret;
+
+        if (dir == DMA_DEV_TO_MEM)
+                dma_sconfig.src_addr = apb_add;
+        else
+                dma_sconfig.dst_addr = apb_add;
+
+        ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig);
+        if (ret)
+                return ret;
+
+        dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan,
+                        tegra_apb_bb_phys, sizeof(u32), dir,
+                        DMA_PREP_INTERRUPT |  DMA_CTRL_ACK);
+        if (!dma_desc)
+                return -EINVAL;
+
+        dma_desc->callback = apb_dma_complete;
+        dma_desc->callback_param = NULL;
+
+        INIT_COMPLETION(tegra_apb_wait);
+
+        dmaengine_submit(dma_desc);
+        dma_async_issue_pending(tegra_apb_dma_chan);
+        ret = wait_for_completion_timeout(&tegra_apb_wait,
+                msecs_to_jiffies(50));
+
+        if (WARN(ret == 0, "apb read dma timed out")) {
+                dmaengine_terminate_all(tegra_apb_dma_chan);
+                return -EFAULT;
+        }
+        return 0;
+}
+
+static u32 tegra_apb_readl_using_dma(unsigned long offset)
+{
+        int ret;
+
+        if (!tegra_apb_dma_chan && !tegra_apb_dma_init())
+                return tegra_apb_readl_direct(offset);
+
+        mutex_lock(&tegra_apb_dma_lock);
+        ret = do_dma_transfer(offset, DMA_DEV_TO_MEM);
+        if (ret < 0) {
+                pr_err("error in reading offset 0x%08lx using dma\n", offset);
+                *(u32 *)tegra_apb_bb = 0;
+        }
+        mutex_unlock(&tegra_apb_dma_lock);
+        return *((u32 *)tegra_apb_bb);
+}
+
+static void tegra_apb_writel_using_dma(u32 value, unsigned long offset)
+{
+        int ret;
+
+        if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) {
+                tegra_apb_writel_direct(value, offset);
+                return;
+        }
+
+        mutex_lock(&tegra_apb_dma_lock);
+        *((u32 *)tegra_apb_bb) = value;
+        ret = do_dma_transfer(offset, DMA_MEM_TO_DEV);
+        if (ret < 0)
+                pr_err("error in writing offset 0x%08lx using dma\n", offset);
+        mutex_unlock(&tegra_apb_dma_lock);
+}
+#endif
+#else
+#define tegra_apb_readl_using_dma tegra_apb_readl_direct
+#define tegra_apb_writel_using_dma tegra_apb_writel_direct
+#endif
+
+typedef u32 (*apbio_read_fptr)(unsigned long offset);
+typedef void (*apbio_write_fptr)(u32 value, unsigned long offset);
+
+static apbio_read_fptr apbio_read;
+static apbio_write_fptr apbio_write;
+
+static u32 tegra_apb_readl_direct(unsigned long offset)
+{
+        return readl(IO_TO_VIRT(offset));
+}
+
+static void tegra_apb_writel_direct(u32 value, unsigned long offset)
+{
+        writel(value, IO_TO_VIRT(offset));
+}
+
+void tegra_apb_io_init(void)
+{
+        /* Need to use dma only when it is Tegra20 based platform */
+        if (of_machine_is_compatible("nvidia,tegra20") ||
+                        !of_have_populated_dt()) {
+                apbio_read = tegra_apb_readl_using_dma;
+                apbio_write = tegra_apb_writel_using_dma;
+        } else {
+                apbio_read = tegra_apb_readl_direct;
+                apbio_write = tegra_apb_writel_direct;
+        }
+}
+
+u32 tegra_apb_readl(unsigned long offset)
+{
+        return apbio_read(offset);
+}
+
+void tegra_apb_writel(u32 value, unsigned long offset)
+{
+        apbio_write(value, offset);
+}
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h
index 8b49e8c89a64..f05d71c303c7 100644
--- a/arch/arm/mach-tegra/apbio.h
+++ b/arch/arm/mach-tegra/apbio.h
@@ -16,24 +16,7 @@
 #ifndef __MACH_TEGRA_APBIO_H
 #define __MACH_TEGRA_APBIO_H
 
-#ifdef CONFIG_TEGRA_SYSTEM_DMA
-
+void tegra_apb_io_init(void);
 u32 tegra_apb_readl(unsigned long offset);
 void tegra_apb_writel(u32 value, unsigned long offset);
-
-#else
-#include <asm/io.h>
-#include <mach/io.h>
-
-static inline u32 tegra_apb_readl(unsigned long offset)
-{
-        return readl(IO_TO_VIRT(offset));
-}
-
-static inline void tegra_apb_writel(u32 value, unsigned long offset)
-{
-        writel(value, IO_TO_VIRT(offset));
-}
-#endif
-
 #endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 204a5c8b0b57..96fef6bcc651 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -33,6 +33,7 @@
 #include "clock.h"
 #include "fuse.h"
 #include "pmc.h"
+#include "apbio.h"
 
 /*
  * Storage for debug-macro.S's state.
@@ -127,6 +128,7 @@ static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
 void __init tegra20_init_early(void)
 {
+        tegra_apb_io_init();
         tegra_init_fuse();
         tegra2_init_clocks();
         tegra_clk_init_from_table(tegra20_clk_init_table);
@@ -138,6 +140,7 @@ void __init tegra20_init_early(void)
 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
 void __init tegra30_init_early(void)
 {
+        tegra_apb_io_init();
         tegra_init_fuse();
         tegra30_init_clocks();
         tegra_clk_init_from_table(tegra30_clk_init_table);
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index d83a8c0296f5..566e2f88899b 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -27,9 +27,9 @@
 #include <linux/cpuidle.h>
 #include <linux/hrtimer.h>
 
-#include <mach/iomap.h>
+#include <asm/proc-fns.h>
 
-extern void tegra_cpu_wfi(void);
+#include <mach/iomap.h>
 
 static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
                                 struct cpuidle_driver *drv, int index);
@@ -64,7 +64,7 @@ static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
 
         enter = ktime_get();
 
-        tegra_cpu_wfi();
+        cpu_do_idle();
 
         exit = ktime_sub(ktime_get(), enter);
         us = ktime_to_us(exit);
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index 5b20197bae7f..d29b156a8011 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -62,32 +62,3 @@
         movw    \reg, #:lower16:\val
         movt    \reg, #:upper16:\val
 .endm
-
-/*
- * tegra_cpu_wfi
- *
- * puts current CPU in clock-gated wfi using the flow controller
- *
- * corrupts r0-r3
- * must be called with MMU on
- */
-
-ENTRY(tegra_cpu_wfi)
-        cpu_id  r0
-        cpu_to_halt_reg r1, r0
-        cpu_to_csr_reg r2, r0
-        mov32   r0, TEGRA_FLOW_CTRL_VIRT
-        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        str     r3, [r0, r2]    @ clear event & interrupt status
-        mov     r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
-        str     r3, [r0, r1]    @ put flow controller in wait irq mode
-        dsb
-        wfi
-        mov     r3, #0
-        str     r3, [r0, r1]    @ clear flow controller halt status
-        mov     r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
-        str     r3, [r0, r2]    @ clear event & interrupt status
-        dsb
-        mov     pc, lr
-ENDPROC(tegra_cpu_wfi)
-
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 53d3d46dec12..c013bbf79cac 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -41,6 +41,7 @@ config MACH_HREFV60
 config MACH_SNOWBALL
         bool "U8500 Snowball platform"
         select MACH_MOP500
+        select LEDS_GPIO
         help
           Include support for the snowball development platform.
 
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 920251cf834c..18ff781cfbe4 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -80,7 +80,7 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi0_data = {
+struct mmci_platform_data mop500_sdi0_data = {
         .ios_handler    = mop500_sdi0_ios_handler,
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
@@ -227,7 +227,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
 };
 #endif
 
-static struct mmci_platform_data mop500_sdi4_data = {
+struct mmci_platform_data mop500_sdi4_data = {
         .ocr_mask       = MMC_VDD_29_30,
         .f_max          = 50000000,
         .capabilities   = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 1509a3cb5833..84461fa2a3ba 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -58,7 +58,7 @@
 static struct gpio_led snowball_led_array[] = {
         {
                 .name = "user_led",
-                .default_trigger = "none",
+                .default_trigger = "heartbeat",
                 .gpio = 142,
         },
 };
@@ -331,43 +331,12 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         },
 };
 
-#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm)    \
-static struct nmk_i2c_controller u8500_i2c##id##_data = { \
-        /*                              \
-         * slave data setup time, which is      \
-         * 250 ns,100ns,10ns which is 14,6,2    \
-         * respectively for a 48 Mhz    \
-         * i2c clock                    \
-         */                             \
-        .slsu           = _slsu,        \
-        /* Tx FIFO threshold */         \
-        .tft            = _tft,         \
-        /* Rx FIFO threshold */         \
-        .rft            = _rft,         \
-        /* std. mode operation */       \
-        .clk_freq       = clk,          \
-        /* Slave response timeout(ms) */\
-        .timeout        = t_out,        \
-        .sm             = _sm,          \
-}
-
-/*
- * The board uses 4 i2c controllers, initialize all of
- * them with slave data setup time of 250 ns,
- * Tx & Rx FIFO threshold values as 8 and standard
- * mode of operation
- */
-U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
-
 static void __init mop500_i2c_init(struct device *parent)
 {
-        db8500_add_i2c0(parent, &u8500_i2c0_data);
-        db8500_add_i2c1(parent, &u8500_i2c1_data);
-        db8500_add_i2c2(parent, &u8500_i2c2_data);
-        db8500_add_i2c3(parent, &u8500_i2c3_data);
+        db8500_add_i2c0(parent, NULL);
+        db8500_add_i2c1(parent, NULL);
+        db8500_add_i2c2(parent, NULL);
+        db8500_add_i2c3(parent, NULL);
 }
 
 static struct gpio_keys_button mop500_gpio_keys[] = {
@@ -625,11 +594,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
         &ab8500_device,
 };
 
-static struct platform_device *snowball_of_platform_devs[] __initdata = {
-        &snowball_led_dev,
-        &snowball_key_dev,
-};
-
 static void __init mop500_init_machine(void)
 {
         struct device *parent = NULL;
@@ -769,6 +733,11 @@ MACHINE_END
 
 #ifdef CONFIG_MACH_UX500_DT
 
+static struct platform_device *snowball_of_platform_devs[] __initdata = {
+        &snowball_led_dev,
+        &snowball_key_dev,
+};
+
 struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         /* Requires DMA and call-back bindings. */
         OF_DEV_AUXDATA("arm,pl011", 0x80120000, "uart0", &uart0_plat),
@@ -776,6 +745,8 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("arm,pl011", 0x80007000, "uart2", &uart2_plat),
         /* Requires DMA bindings. */
         OF_DEV_AUXDATA("arm,pl022", 0x80002000, "ssp0",  &ssp0_plat),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80126000, "sdi0",  &mop500_sdi0_data),
+        OF_DEV_AUXDATA("arm,pl18x", 0x80114000, "sdi4",  &mop500_sdi4_data),
         /* Requires clock name bindings. */
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e000, "gpio.0", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8012e080, "gpio.1", NULL),
@@ -786,6 +757,13 @@ struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e000, "gpio.6", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0x8011e080, "gpio.7", NULL),
         OF_DEV_AUXDATA("st,nomadik-gpio", 0xa03fe000, "gpio.8", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80004000, "nmk-i2c.0", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80122000, "nmk-i2c.1", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80128000, "nmk-i2c.2", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x80110000, "nmk-i2c.3", NULL),
+        OF_DEV_AUXDATA("st,nomadik-i2c", 0x8012a000, "nmk-i2c.4", NULL),
+        /* Requires device name bindings. */
+        OF_DEV_AUXDATA("stericsson,nmk_pinctrl", 0, "pinctrl-db8500", NULL),
         {},
 };
 
@@ -818,8 +796,6 @@ static void __init u8500_init_machine(void)
 
         for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
                 mop500_platform_devs[i]->dev.parent = parent;
-        for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
-                snowball_platform_devs[i]->dev.parent = parent;
 
         /* automatically probe child nodes of db8500 device */
         of_platform_populate(NULL, u8500_local_bus_nodes, u8500_auxdata_lookup, parent);
@@ -838,18 +814,6 @@ static void __init u8500_init_machine(void)
 
                 mop500_uib_init();
 
-        } else if (of_machine_is_compatible("calaosystems,snowball-a9500")) {
-                /*
-                 * Devices to be DT:ed:
-                 *   snowball_led_dev   = todo
-                 *   snowball_key_dev   = todo
-                 *   snowball_sbnet_dev = done
-                 *   ab8500_device      = done
-                 */
-                platform_add_devices(snowball_of_platform_devs,
-                                ARRAY_SIZE(snowball_of_platform_devs));
-
-                snowball_sdi_init(parent);
         } else if (of_machine_is_compatible("st-ericsson,hrefv60+")) {
                 /*
                  * The HREFv60 board removed a GPIO expander and routed
@@ -871,7 +835,6 @@ static void __init u8500_init_machine(void)
 
                 mop500_uib_init();
         }
-        mop500_i2c_init(parent);
 
         /* This board has full regulator constraints */
         regulator_has_full_constraints();
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 2f87b25a908a..b5bfc1a78b1a 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -9,6 +9,7 @@
 
 /* For NOMADIK_NR_GPIO */
 #include <mach/irqs.h>
+#include <linux/amba/mmci.h>
 
 /* Snowball specific GPIO assignments, this board has no GPIO expander */
 #define SNOWBALL_ACCEL_INT1_GPIO        163
@@ -78,6 +79,8 @@
 
 struct device;
 struct i2c_board_info;
+extern struct mmci_platform_data mop500_sdi0_data;
+extern struct mmci_platform_data mop500_sdi4_data;
 
 extern void mop500_sdi_init(struct device *parent);
 extern void snowball_sdi_init(struct device *parent);
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 33275eb4c689..c8dd94f606dc 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -139,7 +139,6 @@ static struct platform_device *platform_devs[] __initdata = {
 
 static struct platform_device *of_platform_devs[] __initdata = {
         &u8500_dma40_device,
-        &db8500_pmu_device,
 };
 
 static resource_size_t __initdata db8500_gpio_base[] = {
@@ -237,7 +236,6 @@ struct device * __init u8500_of_init_devices(void)
 
         parent = db8500_soc_device_init();
 
-        db8500_add_rtc(parent);
         db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
 
         platform_device_register_data(parent,
@@ -249,7 +247,7 @@ struct device * __init u8500_of_init_devices(void)
         /*
          * Devices to be DT:ed:
          *   u8500_dma40_device  = todo
-         *   db8500_pmu_device   = todo
+         *   db8500_pmu_device   = done
          *   db8500_prcmu_device = done
          */
         platform_add_devices(of_platform_devs, ARRAY_SIZE(of_platform_devs));
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 741e71feca78..66e7f00884ab 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -63,8 +63,10 @@ static void __init ux500_timer_init(void)
 
         /* TODO: Once MTU has been DT:ed place code above into else. */
         if (of_have_populated_dt()) {
+#ifdef CONFIG_OF
                 np = of_find_matching_node(NULL, prcmu_timer_of_match);
                 if (!np)
+#endif
                         goto dt_fail;
 
                 tmp_base = of_iomap(np, 0);
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig
index cf8730d35e70..fc3730f01650 100644
--- a/arch/arm/mach-vexpress/Kconfig
+++ b/arch/arm/mach-vexpress/Kconfig
@@ -2,7 +2,8 @@ menu "Versatile Express platform type"
         depends on ARCH_VEXPRESS
 
 config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
-        bool
+        bool "Enable A5 and A9 only errata work-arounds"
+        default y
         select ARM_ERRATA_720789
         select ARM_ERRATA_751472
         select PL310_ERRATA_753970 if CACHE_PL310
@@ -14,7 +15,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
 
 config ARCH_VEXPRESS_CA9X4
         bool "Versatile Express Cortex-A9x4 tile"
-        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
         select CPU_V7
         select HAVE_SMP
@@ -22,7 +22,6 @@ config ARCH_VEXPRESS_CA9X4
 
 config ARCH_VEXPRESS_DT
         bool "Device Tree support for Versatile Express platforms"
-        select ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA
         select ARM_GIC
         select ARM_PATCH_PHYS_VIRT
         select AUTO_ZRELADDR
diff --git a/arch/arm/mach-vexpress/Makefile.boot b/arch/arm/mach-vexpress/Makefile.boot
index 909f85ebf5f4..318d308dfb93 100644
--- a/arch/arm/mach-vexpress/Makefile.boot
+++ b/arch/arm/mach-vexpress/Makefile.boot
@@ -6,4 +6,5 @@ initrd_phys-y	:= 0x60800000
 
 dtb-$(CONFIG_ARCH_VEXPRESS_DT)  += vexpress-v2p-ca5s.dtb \
                                    vexpress-v2p-ca9.dtb \
-                                   vexpress-v2p-ca15-tc1.dtb
+                                   vexpress-v2p-ca15-tc1.dtb \
+                                   vexpress-v2p-ca15_a7.dtb
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index c65cc3b462a5..61c492403b05 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -66,8 +66,15 @@ static void __init ct_ca9x4_init_irq(void)
 
 static void ct_ca9x4_clcd_enable(struct clcd_fb *fb)
 {
-        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE_DB1, 0);
-        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE_DB1, 2);
+        u32 site = v2m_get_master_site();
+
+        /*
+         * Old firmware was using the "site" component of the command
+         * to control the DVI muxer (while it should be always 0 ie. MB).
+         * Newer firmware uses the data register. Keep both for compatibility.
+         */
+        v2m_cfg_write(SYS_CFG_MUXFPGA | SYS_CFG_SITE(site), site);
+        v2m_cfg_write(SYS_CFG_DVIMODE | SYS_CFG_SITE(SYS_CFG_SITE_MB), 2);
 }
 
 static int ct_ca9x4_clcd_setup(struct clcd_fb *fb)
@@ -105,43 +112,11 @@ static struct amba_device *ct_ca9x4_amba_devs[] __initdata = {
 };
 
 
-static long ct_round(struct clk *clk, unsigned long rate)
-{
-        return rate;
-}
-
-static int ct_set(struct clk *clk, unsigned long rate)
-{
-        return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_DB1 | 1, rate);
-}
-
-static const struct clk_ops osc1_clk_ops = {
-        .round  = ct_round,
-        .set    = ct_set,
-};
-
-static struct clk osc1_clk = {
-        .ops    = &osc1_clk_ops,
-        .rate   = 24000000,
-};
-
-static struct clk ct_sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk_lookup lookups[] = {
-        {       /* CLCD */
-                .dev_id         = "ct:clcd",
-                .clk            = &osc1_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "ct-timer0",
-                .clk            = &ct_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "ct-timer1",
-                .clk            = &ct_sp804_clk,
-        },
+static struct v2m_osc ct_osc1 = {
+        .osc = 1,
+        .rate_min = 10000000,
+        .rate_max = 80000000,
+        .rate_default = 23750000,
 };
 
 static struct resource pmu_resources[] = {
@@ -174,14 +149,10 @@ static struct platform_device pmu_device = {
         .resource       = pmu_resources,
 };
 
-static void __init ct_ca9x4_init_early(void)
-{
-        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-}
-
 static void __init ct_ca9x4_init(void)
 {
         int i;
+        struct clk *clk;
 
 #ifdef CONFIG_CACHE_L2X0
         void __iomem *l2x0_base = ioremap(CT_CA9X4_L2CC, SZ_4K);
@@ -193,6 +164,10 @@ static void __init ct_ca9x4_init(void)
         l2x0_init(l2x0_base, 0x00400000, 0xfe0fffff);
 #endif
 
+        ct_osc1.site = v2m_get_master_site();
+        clk = v2m_osc_register("ct:osc1", &ct_osc1);
+        clk_register_clkdev(clk, NULL, "ct:clcd");
+
         for (i = 0; i < ARRAY_SIZE(ct_ca9x4_amba_devs); i++)
                 amba_device_register(ct_ca9x4_amba_devs[i], &iomem_resource);
 
@@ -234,7 +209,6 @@ struct ct_desc ct_ca9x4_desc __initdata = {
         .id             = V2M_CT_ID_CA9,
         .name           = "CA9x4",
         .map_io         = ct_ca9x4_map_io,
-        .init_early     = ct_ca9x4_init_early,
         .init_irq       = ct_ca9x4_init_irq,
         .init_tile      = ct_ca9x4_init,
 #ifdef CONFIG_SMP
diff --git a/arch/arm/mach-vexpress/include/mach/clkdev.h b/arch/arm/mach-vexpress/include/mach/clkdev.h
deleted file mode 100644
index 3f8307d73cad..000000000000
--- a/arch/arm/mach-vexpress/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#include <plat/clock.h>
-
-struct clk {
-        const struct clk_ops    *ops;
-        unsigned long           rate;
-        const struct icst_params *params;
-};
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index fa8224794e0b..9f509f55d078 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -18,6 +18,8 @@
 
 #define DEBUG_LL_VIRT_BASE              0xf8000000
 
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
+
                 .macro  addruart,rp,rv,tmp
 
                 @ Make an educated guess regarding the memory map:
@@ -41,3 +43,42 @@
                 .endm
 
 #include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+
+                .macro  addruart,rp,rv,tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET
+                orr     \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orr     \rp, \rp, #DEBUG_LL_PHYS_BASE
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+
+                .macro  addruart,rp,rv,tmp
+                mov     \rp, #DEBUG_LL_UART_OFFSET_RS1
+                orr     \rv, \rp, #DEBUG_LL_VIRT_BASE
+                orr     \rp, \rp, #DEBUG_LL_PHYS_BASE_RS1
+                .endm
+
+#include <asm/hardware/debug-pl01x.S>
+
+#else /* CONFIG_DEBUG_LL_UART_NONE */
+
+                .macro  addruart, rp, rv, tmp
+                /* Safe dummy values */
+                mov     \rp, #0
+                mov     \rv, #DEBUG_LL_VIRT_BASE
+                .endm
+
+                .macro  senduart,rd,rx
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+                .endm
+
+#endif
diff --git a/arch/arm/mach-vexpress/include/mach/motherboard.h b/arch/arm/mach-vexpress/include/mach/motherboard.h
index 31a92890893d..1e388c7bf4d7 100644
--- a/arch/arm/mach-vexpress/include/mach/motherboard.h
+++ b/arch/arm/mach-vexpress/include/mach/motherboard.h
@@ -1,6 +1,8 @@
 #ifndef __MACH_MOTHERBOARD_H
 #define __MACH_MOTHERBOARD_H
 
+#include <linux/clk-provider.h>
+
 /*
  * Physical addresses, offset from V2M_PA_CS0-3
  */
@@ -104,9 +106,10 @@
 #define SYS_CFG_REBOOT          (9 << 20)
 #define SYS_CFG_DVIMODE         (11 << 20)
 #define SYS_CFG_POWER           (12 << 20)
-#define SYS_CFG_SITE_MB         (0 << 16)
-#define SYS_CFG_SITE_DB1        (1 << 16)
-#define SYS_CFG_SITE_DB2        (2 << 16)
+#define SYS_CFG_SITE(n)         ((n) << 16)
+#define SYS_CFG_SITE_MB         0
+#define SYS_CFG_SITE_DB1        1
+#define SYS_CFG_SITE_DB2        2
 #define SYS_CFG_STACK(n)        ((n) << 12)
 
 #define SYS_CFG_ERR             (1 << 1)
@@ -122,6 +125,8 @@ void v2m_flags_set(u32 data);
 #define SYS_MISC_MASTERSITE     (1 << 14)
 #define SYS_PROCIDx_HBI_MASK    0xfff
 
+int v2m_get_master_site(void);
+
 /*
  * Core tile IDs
  */
@@ -144,4 +149,21 @@ struct ct_desc {
 
 extern struct ct_desc *ct_desc;
 
+/*
+ * OSC clock provider
+ */
+struct v2m_osc {
+        struct clk_hw hw;
+        u8 site; /* 0 = motherboard, 1 = site 1, 2 = site 2 */
+        u8 stack; /* board stack position */
+        u16 osc;
+        unsigned long rate_min;
+        unsigned long rate_max;
+        unsigned long rate_default;
+};
+
+#define to_v2m_osc(osc) container_of(osc, struct v2m_osc, hw)
+
+struct clk *v2m_osc_register(const char *name, struct v2m_osc *osc);
+
 #endif
diff --git a/arch/arm/mach-vexpress/include/mach/uncompress.h b/arch/arm/mach-vexpress/include/mach/uncompress.h
index 7dab5596b868..1e472eb0bbdc 100644
--- a/arch/arm/mach-vexpress/include/mach/uncompress.h
+++ b/arch/arm/mach-vexpress/include/mach/uncompress.h
@@ -27,6 +27,7 @@
 
 static unsigned long get_uart_base(void)
 {
+#if defined(CONFIG_DEBUG_VEXPRESS_UART0_DETECT)
         unsigned long mpcore_periph;
 
         /*
@@ -42,6 +43,13 @@ static unsigned long get_uart_base(void)
                 return UART_BASE;
         else
                 return UART_BASE_RS1;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_CA9)
+        return UART_BASE;
+#elif defined(CONFIG_DEBUG_VEXPRESS_UART0_RS1)
+        return UART_BASE_RS1;
+#else
+        return 0;
+#endif
 }
 
 /*
@@ -51,6 +59,9 @@ static inline void putc(int c)
 {
         unsigned long base = get_uart_base();
 
+        if (!base)
+                return;
+
         while (AMBA_UART_FR(base) & (1 << 5))
                 barrier();
 
@@ -61,6 +72,9 @@ static inline void flush(void)
 {
         unsigned long base = get_uart_base();
 
+        if (!base)
+                return;
+
         while (AMBA_UART_FR(base) & (1 << 3))
                 barrier();
 }
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index fde26adaef32..37608f22ee31 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -16,7 +16,10 @@
 #include <linux/spinlock.h>
 #include <linux/usb/isp1760.h>
 #include <linux/clkdev.h>
+#include <linux/clk-provider.h>
 #include <linux/mtd/physmap.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
 
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
@@ -81,16 +84,6 @@ static void __init v2m_sp804_init(void __iomem *base, unsigned int irq)
         sp804_clockevents_init(base + TIMER_1_BASE, irq, "v2m-timer0");
 }
 
-static void __init v2m_timer_init(void)
-{
-        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
-        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
-}
-
-static struct sys_timer v2m_timer = {
-        .init   = v2m_timer_init,
-};
-
 
 static DEFINE_SPINLOCK(v2m_cfg_lock);
 
@@ -147,6 +140,13 @@ void __init v2m_flags_set(u32 data)
         writel(data, v2m_sysreg_base + V2M_SYS_FLAGSSET);
 }
 
+int v2m_get_master_site(void)
+{
+        u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
+
+        return misc & SYS_MISC_MASTERSITE ? SYS_CFG_SITE_DB2 : SYS_CFG_SITE_DB1;
+}
+
 
 static struct resource v2m_pcie_i2c_resource = {
         .start  = V2M_SERIAL_BUS_PCI,
@@ -201,6 +201,11 @@ static struct platform_device v2m_eth_device = {
         .dev.platform_data = &v2m_eth_config,
 };
 
+static struct regulator_consumer_supply v2m_eth_supplies[] = {
+        REGULATOR_SUPPLY("vddvario", "smsc911x"),
+        REGULATOR_SUPPLY("vdd33a", "smsc911x"),
+};
+
 static struct resource v2m_usb_resources[] = {
         {
                 .start  = V2M_ISP1761,
@@ -319,98 +324,145 @@ static struct amba_device *v2m_amba_devs[] __initdata = {
 };
 
 
-static long v2m_osc_round(struct clk *clk, unsigned long rate)
+static unsigned long v2m_osc_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        return !parent_rate ? osc->rate_default : parent_rate;
+}
+
+static long v2m_osc_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate)
 {
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        if (WARN_ON(rate < osc->rate_min))
+                rate = osc->rate_min;
+
+        if (WARN_ON(rate > osc->rate_max))
+                rate = osc->rate_max;
+
         return rate;
 }
 
-static int v2m_osc1_set(struct clk *clk, unsigned long rate)
+static int v2m_osc_set_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate)
 {
-        return v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE_MB | 1, rate);
+        struct v2m_osc *osc = to_v2m_osc(hw);
+
+        v2m_cfg_write(SYS_CFG_OSC | SYS_CFG_SITE(osc->site) |
+                        SYS_CFG_STACK(osc->stack) | osc->osc, rate);
+
+        return 0;
 }
 
-static const struct clk_ops osc1_clk_ops = {
-        .round  = v2m_osc_round,
-        .set    = v2m_osc1_set,
-};
-
-static struct clk osc1_clk = {
-        .ops    = &osc1_clk_ops,
-        .rate   = 24000000,
-};
-
-static struct clk osc2_clk = {
-        .rate   = 24000000,
-};
-
-static struct clk v2m_sp804_clk = {
-        .rate   = 1000000,
-};
-
-static struct clk v2m_ref_clk = {
-        .rate   = 32768,
-};
-
-static struct clk dummy_apb_pclk;
-
-static struct clk_lookup v2m_lookups[] = {
-        {       /* AMBA bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* UART0 */
-                .dev_id         = "mb:uart0",
-                .clk            = &osc2_clk,
-        }, {    /* UART1 */
-                .dev_id         = "mb:uart1",
-                .clk            = &osc2_clk,
-        }, {    /* UART2 */
-                .dev_id         = "mb:uart2",
-                .clk            = &osc2_clk,
-        }, {    /* UART3 */
-                .dev_id         = "mb:uart3",
-                .clk            = &osc2_clk,
-        }, {    /* KMI0 */
-                .dev_id         = "mb:kmi0",
-                .clk            = &osc2_clk,
-        }, {    /* KMI1 */
-                .dev_id         = "mb:kmi1",
-                .clk            = &osc2_clk,
-        }, {    /* MMC0 */
-                .dev_id         = "mb:mmci",
-                .clk            = &osc2_clk,
-        }, {    /* CLCD */
-                .dev_id         = "mb:clcd",
-                .clk            = &osc1_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "mb:wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer0",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer1",
-                .clk            = &v2m_sp804_clk,
-        },
+static struct clk_ops v2m_osc_ops = {
+        .recalc_rate = v2m_osc_recalc_rate,
+        .round_rate = v2m_osc_round_rate,
+        .set_rate = v2m_osc_set_rate,
+};
+
+struct clk * __init v2m_osc_register(const char *name, struct v2m_osc *osc)
+{
+        struct clk_init_data init;
+
+        WARN_ON(osc->site > 2);
+        WARN_ON(osc->stack > 15);
+        WARN_ON(osc->osc > 4095);
+
+        init.name = name;
+        init.ops = &v2m_osc_ops;
+        init.flags = CLK_IS_ROOT;
+        init.num_parents = 0;
+
+        osc->hw.init = &init;
+
+        return clk_register(NULL, &osc->hw);
+}
+
+static struct v2m_osc v2m_mb_osc1 = {
+        .site = SYS_CFG_SITE_MB,
+        .osc = 1,
+        .rate_min = 23750000,
+        .rate_max = 63500000,
+        .rate_default = 23750000,
+};
+
+static const char *v2m_ref_clk_periphs[] __initconst = {
+        "mb:wdt",   "1000f000.wdt",  "1c0f0000.wdt",    /* SP805 WDT */
+};
+
+static const char *v2m_osc1_periphs[] __initconst = {
+        "mb:clcd",  "1001f000.clcd", "1c1f0000.clcd",   /* PL111 CLCD */
+};
+
+static const char *v2m_osc2_periphs[] __initconst = {
+        "mb:mmci",  "10005000.mmci", "1c050000.mmci",   /* PL180 MMCI */
+        "mb:kmi0",  "10006000.kmi",  "1c060000.kmi",    /* PL050 KMI0 */
+        "mb:kmi1",  "10007000.kmi",  "1c070000.kmi",    /* PL050 KMI1 */
+        "mb:uart0", "10009000.uart", "1c090000.uart",   /* PL011 UART0 */
+        "mb:uart1", "1000a000.uart", "1c0a0000.uart",   /* PL011 UART1 */
+        "mb:uart2", "1000b000.uart", "1c0b0000.uart",   /* PL011 UART2 */
+        "mb:uart3", "1000c000.uart", "1c0c0000.uart",   /* PL011 UART3 */
+};
+
+static void __init v2m_clk_init(void)
+{
+        struct clk *clk;
+        int i;
+
+        clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
+                        CLK_IS_ROOT, 0);
+        WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
+
+        clk = clk_register_fixed_rate(NULL, "mb:ref_clk", NULL,
+                        CLK_IS_ROOT, 32768);
+        for (i = 0; i < ARRAY_SIZE(v2m_ref_clk_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_ref_clk_periphs[i]));
+
+        clk = clk_register_fixed_rate(NULL, "mb:sp804_clk", NULL,
+                        CLK_IS_ROOT, 1000000);
+        WARN_ON(clk_register_clkdev(clk, "v2m-timer0", "sp804"));
+        WARN_ON(clk_register_clkdev(clk, "v2m-timer1", "sp804"));
+
+        clk = v2m_osc_register("mb:osc1", &v2m_mb_osc1);
+        for (i = 0; i < ARRAY_SIZE(v2m_osc1_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc1_periphs[i]));
+
+        clk = clk_register_fixed_rate(NULL, "mb:osc2", NULL,
+                        CLK_IS_ROOT, 24000000);
+        for (i = 0; i < ARRAY_SIZE(v2m_osc2_periphs); i++)
+                WARN_ON(clk_register_clkdev(clk, NULL, v2m_osc2_periphs[i]));
+}
+
+static void __init v2m_timer_init(void)
+{
+        v2m_sysctl_init(ioremap(V2M_SYSCTL, SZ_4K));
+        v2m_clk_init();
+        v2m_sp804_init(ioremap(V2M_TIMER01, SZ_4K), IRQ_V2M_TIMER0);
+}
+
+static struct sys_timer v2m_timer = {
+        .init   = v2m_timer_init,
 };
 
 static void __init v2m_init_early(void)
 {
-        ct_desc->init_early();
-        clkdev_add_table(v2m_lookups, ARRAY_SIZE(v2m_lookups));
+        if (ct_desc->init_early)
+                ct_desc->init_early();
         versatile_sched_clock_init(v2m_sysreg_base + V2M_SYS_24MHZ, 24000000);
 }
 
 static void v2m_power_off(void)
 {
-        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE_MB, 0))
+        if (v2m_cfg_write(SYS_CFG_SHUTDOWN | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
                 printk(KERN_EMERG "Unable to shutdown\n");
 }
 
 static void v2m_restart(char str, const char *cmd)
 {
-        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
+        if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE(SYS_CFG_SITE_MB), 0))
                 printk(KERN_EMERG "Unable to reboot\n");
 }
 
@@ -458,6 +510,9 @@ static void __init v2m_init(void)
 {
         int i;
 
+        regulator_register_fixed(0, v2m_eth_supplies,
+                        ARRAY_SIZE(v2m_eth_supplies));
+
         platform_device_register(&v2m_pcie_i2c_device);
         platform_device_register(&v2m_ddc_i2c_device);
         platform_device_register(&v2m_flash_device);
@@ -522,77 +577,6 @@ void __init v2m_dt_map_io(void)
 #endif
 }
 
-static struct clk_lookup v2m_dt_lookups[] = {
-        {       /* AMBA bus clock */
-                .con_id         = "apb_pclk",
-                .clk            = &dummy_apb_pclk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer0",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* SP804 timers */
-                .dev_id         = "sp804",
-                .con_id         = "v2m-timer1",
-                .clk            = &v2m_sp804_clk,
-        }, {    /* PL180 MMCI */
-                .dev_id         = "mb:mmci", /* 10005000.mmci */
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI0 */
-                .dev_id         = "10006000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI1 */
-                .dev_id         = "10007000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART0 */
-                .dev_id         = "10009000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART1 */
-                .dev_id         = "1000a000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART2 */
-                .dev_id         = "1000b000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART3 */
-                .dev_id         = "1000c000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "1000f000.wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* PL111 CLCD */
-                .dev_id         = "1001f000.clcd",
-                .clk            = &osc1_clk,
-        },
-        /* RS1 memory map */
-        {       /* PL180 MMCI */
-                .dev_id         = "mb:mmci", /* 1c050000.mmci */
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI0 */
-                .dev_id         = "1c060000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL050 KMI1 */
-                .dev_id         = "1c070000.kmi",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART0 */
-                .dev_id         = "1c090000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART1 */
-                .dev_id         = "1c0a0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART2 */
-                .dev_id         = "1c0b0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* PL011 UART3 */
-                .dev_id         = "1c0c0000.uart",
-                .clk            = &osc2_clk,
-        }, {    /* SP805 WDT */
-                .dev_id         = "1c0f0000.wdt",
-                .clk            = &v2m_ref_clk,
-        }, {    /* PL111 CLCD */
-                .dev_id         = "1c1f0000.clcd",
-                .clk            = &osc1_clk,
-        },
-};
-
 void __init v2m_dt_init_early(void)
 {
         struct device_node *node;
@@ -605,8 +589,8 @@ void __init v2m_dt_init_early(void)
 
         /* Confirm board type against DT property, if available */
         if (of_property_read_u32(allnodes, "arm,hbi", &dt_hbi) == 0) {
-                u32 misc = readl(v2m_sysreg_base + V2M_SYS_MISC);
-                u32 id = readl(v2m_sysreg_base + (misc & SYS_MISC_MASTERSITE ?
+                int site = v2m_get_master_site();
+                u32 id = readl(v2m_sysreg_base + (site == SYS_CFG_SITE_DB2 ?
                                 V2M_SYS_PROCID1 : V2M_SYS_PROCID0));
                 u32 hbi = id & SYS_PROCIDx_HBI_MASK;
 
@@ -614,8 +598,6 @@ void __init v2m_dt_init_early(void)
                         pr_warning("vexpress: DT HBI (%x) is not matching "
                                         "hardware (%x)!\n", dt_hbi, hbi);
         }
-
-        clkdev_add_table(v2m_dt_lookups, ARRAY_SIZE(v2m_dt_lookups));
 }
 
 static  struct of_device_id vexpress_irq_match[] __initdata = {
@@ -637,6 +619,8 @@ static void __init v2m_dt_timer_init(void)
         node = of_find_compatible_node(NULL, NULL, "arm,sp810");
         v2m_sysctl_init(of_iomap(node, 0));
 
+        v2m_clk_init();
+
         err = of_property_read_string(of_aliases, "arm,v2m_timer", &path);
         if (WARN_ON(err))
                 return;
diff --git a/arch/arm/mach-vt8500/Makefile b/arch/arm/mach-vt8500/Makefile
index 81aedb7c893c..54e69973f39b 100644
--- a/arch/arm/mach-vt8500/Makefile
+++ b/arch/arm/mach-vt8500/Makefile
@@ -1,4 +1,4 @@
-obj-y += devices.o gpio.o irq.o timer.o
+obj-y += devices.o gpio.o irq.o timer.o restart.o
 
 obj-$(CONFIG_VTWM_VERSION_VT8500) += devices-vt8500.o
 obj-$(CONFIG_VTWM_VERSION_WM8505) += devices-wm8505.o
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
index a464c7584411..f9fbeb2d10e9 100644
--- a/arch/arm/mach-vt8500/bv07.c
+++ b/arch/arm/mach-vt8500/bv07.c
@@ -23,6 +23,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/restart.h>
 
 #include "devices.h"
 
@@ -62,6 +63,7 @@ void __init bv07_init(void)
         else
                 printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
 
+        wmt_setup_restart();
         vt8500_set_resources();
         platform_add_devices(devices, ARRAY_SIZE(devices));
         vt8500_gpio_init();
@@ -69,6 +71,7 @@ void __init bv07_init(void)
 
 MACHINE_START(BV07, "Benign BV07 Mini Netbook")
         .atag_offset    = 0x100,
+        .restart        = wmt_restart,
         .reserve        = vt8500_reserve_mem,
         .map_io         = vt8500_map_io,
         .init_irq       = vt8500_init_irq,
diff --git a/arch/arm/mach-vt8500/include/mach/restart.h b/arch/arm/mach-vt8500/include/mach/restart.h
new file mode 100644
index 000000000000..89f9b787d2a0
--- /dev/null
+++ b/arch/arm/mach-vt8500/include/mach/restart.h
@@ -0,0 +1,17 @@
+/* linux/arch/arm/mach-vt8500/restart.h
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+void wmt_setup_restart(void);
+void wmt_restart(char mode, const char *cmd);
diff --git a/arch/arm/mach-vt8500/include/mach/system.h b/arch/arm/mach-vt8500/include/mach/system.h
deleted file mode 100644
index 58fa8010ee61..000000000000
--- a/arch/arm/mach-vt8500/include/mach/system.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-vt8500/include/mach/system.h
- *
- */
-#include <asm/io.h>
-
-/* PM Software Reset request register */
-#define VT8500_PMSR_VIRT        0xf8130060
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-        writel(1, VT8500_PMSR_VIRT);
-}
diff --git a/arch/arm/mach-vt8500/restart.c b/arch/arm/mach-vt8500/restart.c
new file mode 100644
index 000000000000..497e89a5e130
--- /dev/null
+++ b/arch/arm/mach-vt8500/restart.c
@@ -0,0 +1,54 @@
+/* linux/arch/arm/mach-vt8500/restart.c
+ *
+ * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <asm/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define LEGACY_PMC_BASE         0xD8130000
+#define WMT_PRIZM_PMSR_REG      0x60
+
+static void __iomem *pmc_base;
+
+void wmt_setup_restart(void)
+{
+        struct device_node *np;
+
+        /*
+         * Check if Power Mgmt Controller node is present in device tree. If no
+         * device tree node, use the legacy PMSR value (valid for all current
+         * SoCs).
+         */
+        np = of_find_compatible_node(NULL, NULL, "wmt,prizm-pmc");
+        if (np) {
+                pmc_base = of_iomap(np, 0);
+
+                if (!pmc_base)
+                        pr_err("%s:of_iomap(pmc) failed\n", __func__);
+
+                of_node_put(np);
+        } else {
+                pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
+                if (!pmc_base) {
+                        pr_err("%s:ioremap(rstc) failed\n", __func__);
+                        return;
+                }
+        }
+}
+
+void wmt_restart(char mode, const char *cmd)
+{
+        if (pmc_base)
+                writel(1, pmc_base + WMT_PRIZM_PMSR_REG);
+}
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
index cf910a956080..db19886caf7c 100644
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ b/arch/arm/mach-vt8500/wm8505_7in.c
@@ -23,6 +23,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <mach/restart.h>
 
 #include "devices.h"
 
@@ -61,7 +62,7 @@ void __init wm8505_7in_init(void)
                 pm_power_off = &vt8500_power_off;
         else
                 printk(KERN_ERR "PMC Hibernation register could not be remapped, not enabling power off!\n");
-
+        wmt_setup_restart();
         wm8505_set_resources();
         platform_add_devices(devices, ARRAY_SIZE(devices));
         vt8500_gpio_init();
@@ -69,6 +70,7 @@ void __init wm8505_7in_init(void)
 
 MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
         .atag_offset    = 0x100,
+        .restart        = wmt_restart,
         .reserve        = wm8505_reserve_mem,
         .map_io         = wm8505_map_io,
         .init_irq       = wm8505_init_irq,
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 4044abcf6f9d..655878bcc96d 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -1091,7 +1091,7 @@ error:
         while (--i)
                 if (pages[i])
                         __free_pages(pages[i], 0);
-        if (array_size < PAGE_SIZE)
+        if (array_size <= PAGE_SIZE)
                 kfree(pages);
         else
                 vfree(pages);
@@ -1106,7 +1106,7 @@ static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t s
         for (i = 0; i < count; i++)
                 if (pages[i])
                         __free_pages(pages[i], 0);
-        if (array_size < PAGE_SIZE)
+        if (array_size <= PAGE_SIZE)
                 kfree(pages);
         else
                 vfree(pages);
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
index 16d0ec4df5f6..a5c9ad5721c2 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
@@ -20,6 +20,11 @@ const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
         imx_mxc_rtc_data_entry_single(MX31);
 #endif /* ifdef CONFIG_SOC_IMX31 */
 
+#ifdef CONFIG_SOC_IMX35
+const struct imx_mxc_rtc_data imx35_mxc_rtc_data __initconst =
+        imx_mxc_rtc_data_entry_single(MX35);
+#endif /* ifdef CONFIG_SOC_IMX35 */
+
 struct platform_device *__init imx_add_mxc_rtc(
                 const struct imx_mxc_rtc_data *data)
 {
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814a..7cfcc44537f0 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -67,6 +67,7 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
 extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
                         unsigned long ckih1, unsigned long ckih2);
 extern int mx27_clocks_init_dt(void);
+extern int mx31_clocks_init_dt(void);
 extern int mx51_clocks_init_dt(void);
 extern int mx53_clocks_init_dt(void);
 extern int mx6q_clocks_init(void);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 36c8989d9de6..2623e7a2e190 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -107,11 +107,13 @@
 #define MX51_PAD_EIM_D25__UART2_CTS             IOMUX_PAD(0x414, 0x080, 4, __NA_, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D25__UART3_RXD             IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D25__USBOTG_DATA1          IOMUX_PAD(0x414, 0x080, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D25__GPT_CMPOUT1           IOMUX_PAD(0x414, 0x080, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__EIM_D26               IOMUX_PAD(0x418, 0x084, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__KEY_COL7              IOMUX_PAD(0x418, 0x084, 1, 0x9cc, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART2_RTS             IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D26__UART3_TXD             IOMUX_PAD(0x418, 0x084, 3, __NA_, 0, MX51_UART_PAD_CTRL)
 #define MX51_PAD_EIM_D26__USBOTG_DATA2          IOMUX_PAD(0x418, 0x084, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_EIM_D26__GPT_CMPOUT2           IOMUX_PAD(0x418, 0x084, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__AUD6_RXC              IOMUX_PAD(0x41c, 0x088, 5, 0x8f4, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__EIM_D27               IOMUX_PAD(0x41c, 0x088, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_D27__GPIO2_9               IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL)
@@ -228,6 +230,7 @@
 #define MX51_PAD_EIM_CRE__EIM_CRE               IOMUX_PAD(0x4a0, 0x100, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_EIM_CRE__GPIO3_2               IOMUX_PAD(0x4a0, 0x100, 1, 0x97c, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_DRAM_CS1__DRAM_CS1             IOMUX_PAD(0x4d0, 0x104, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DRAM_CS1__CCM_CLKO             IOMUX_PAD(0x4d0, 0x104, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__GPIO3_3            IOMUX_PAD(0x4e4, 0x108, 3, 0x980, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__NANDF_WE_B         IOMUX_PAD(0x4e4, 0x108, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_WE_B__PATA_DIOW          IOMUX_PAD(0x4e4, 0x108, 1, __NA_, 0, NO_PAD_CTRL)
@@ -256,12 +259,14 @@
 #define MX51_PAD_NANDF_RB1__GPIO3_9             IOMUX_PAD(0x4fc, 0x120, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__NANDF_RB1           IOMUX_PAD(0x4fc, 0x120, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__PATA_IORDY          IOMUX_PAD(0x4fc, 0x120, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB1__GPT_CMPOUT2         IOMUX_PAD(0x4fc, 0x120, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__SD4_CMD             IOMUX_PAD(0x4fc, 0x120, 0x15, __NA_, 0, MX51_SDHCI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__DISP2_WAIT          IOMUX_PAD(0x500, 0x124, 5, 0x9a8, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, __NA_, 0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__FEC_COL             IOMUX_PAD(0x500, 0x124, 1, 0x94c, 0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB2__GPIO3_10            IOMUX_PAD(0x500, 0x124, 3, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__NANDF_RB2           IOMUX_PAD(0x500, 0x124, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__GPT_CMPOUT3         IOMUX_PAD(0x500, 0x124, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__USBH3_H3_DP         IOMUX_PAD(0x500, 0x124, 0x17, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__USBH3_NXT           IOMUX_PAD(0x500, 0x124, 6, 0xa20, 0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__DISP1_WAIT          IOMUX_PAD(0x504, 0x128, 5, __NA_, 0, NO_PAD_CTRL)
@@ -637,7 +642,9 @@
 #define MX51_PAD_DISP1_DAT23__DISP2_DAT17       IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DISP1_DAT23__DISP2_SER_CS      IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI1_PIN3__DI1_PIN3             IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_DISP_CLK__DI1_DISP_CLK     IOMUX_PAD(0x730, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI1_PIN2__DI1_PIN2             IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_DI1_PIN15__DI1_PIN15           IOMUX_PAD(0x738, __NA_, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP2__DISP1_SER_CLK          IOMUX_PAD(0x740, 0x338, 0, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP2__DISP2_WAIT             IOMUX_PAD(0x740, 0x338, 2, 0x9a8, 1, NO_PAD_CTRL)
 #define MX51_PAD_DI_GP3__CSI1_DATA_EN           IOMUX_PAD(0x744, 0x33c, 3, 0x9a0, 1, NO_PAD_CTRL)
@@ -780,6 +787,8 @@
 #define MX51_PAD_GPIO1_2__PWM1_PWMO             IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__GPIO1_3               IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__I2C2_SDA              IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x9bc, 3, MX51_I2C_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__CCM_CLKO2             IOMUX_PAD(0x7d8, 0x3d0, 5, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_3__GPT_CLKIN             IOMUX_PAD(0x7d8, 0x3d0, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PLL2_BYP              IOMUX_PAD(0x7d8, 0x3d0, 7, 0x910, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_3__PWM2_PWMO             IOMUX_PAD(0x7d8, 0x3d0, 1, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ     IOMUX_PAD(0x7fc, 0x3d4, 0, __NA_, 0, NO_PAD_CTRL)
@@ -788,13 +797,16 @@
 #define MX51_PAD_GPIO1_4__EIM_RDY               IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__GPIO1_4               IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_4__WDOG1_WDOG_B          IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_4__GPT_CAPIN1            IOMUX_PAD(0x804, 0x3d8, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__CSI2_MCLK             IOMUX_PAD(0x808, 0x3dc, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__DISP2_PIN16           IOMUX_PAD(0x808, 0x3dc, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__GPIO1_5               IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_5__WDOG2_WDOG_B          IOMUX_PAD(0x808, 0x3dc, 2, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_5__CCM_CLKO              IOMUX_PAD(0x808, 0x3dc, 5, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__DISP2_PIN17           IOMUX_PAD(0x80c, 0x3e0, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__GPIO1_6               IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_6__REF_EN_B              IOMUX_PAD(0x80c, 0x3e0, 3, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_6__GPT_CAPIN2            IOMUX_PAD(0x80c, 0x3e0, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__CCM_OUT_0             IOMUX_PAD(0x810, 0x3e4, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__GPIO1_7               IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_7__SD2_WP                IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
@@ -803,11 +815,13 @@
 #define MX51_PAD_GPIO1_8__GPIO1_8               IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__SD2_CD                IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL)
 #define MX51_PAD_GPIO1_8__USBH3_PWR             IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_8__CCM_CLKO2             IOMUX_PAD(0x814, 0x3e8, 4, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__CCM_OUT_1             IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_D1_CS           IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__DISP2_SER_CS          IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__GPIO1_9               IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, MX51_GPIO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__SD2_LCTL              IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL)
 #define MX51_PAD_GPIO1_9__USBH3_OC              IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL)
+#define MX51_PAD_GPIO1_9__CCM_CLKO              IOMUX_PAD(0x818, 0x3ec, 4, __NA_, 0, NO_PAD_CTRL)
 
 #endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 9ffd1bbe615f..7eb9d1329671 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -20,13 +20,15 @@
 #define MXC_EHCI_INTERFACE_MASK         (0xf)
 
 #define MXC_EHCI_POWER_PINS_ENABLED     (1 << 5)
-#define MXC_EHCI_TTL_ENABLED            (1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY           (1 << 7)
-#define MXC_EHCI_IPPUE_DOWN             (1 << 8)
-#define MXC_EHCI_IPPUE_UP               (1 << 9)
-#define MXC_EHCI_WAKEUP_ENABLED (1 << 10)
-#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 11)
+#define MXC_EHCI_PWR_PIN_ACTIVE_HIGH    (1 << 6)
+#define MXC_EHCI_OC_PIN_ACTIVE_LOW      (1 << 7)
+#define MXC_EHCI_TTL_ENABLED            (1 << 8)
+
+#define MXC_EHCI_INTERNAL_PHY           (1 << 9)
+#define MXC_EHCI_IPPUE_DOWN             (1 << 10)
+#define MXC_EHCI_IPPUE_UP               (1 << 11)
+#define MXC_EHCI_WAKEUP_ENABLED         (1 << 12)
+#define MXC_EHCI_ITC_NO_THRESHOLD       (1 << 13)
 
 #define MXC_USBCTRL_OFFSET              0
 #define MXC_USB_PHY_CTR_FUNC_OFFSET     0x8
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index ed8605f01155..6d87532871cd 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -4,7 +4,7 @@
 
 # Common support
 obj-y := common.o sram.o clock.o devices.o dma.o mux.o \
-         usb.o fb.o counter_32k.o
+         fb.o counter_32k.o
 obj-m :=
 obj-n :=
 obj-  :=
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index cb16ade437cb..7fe626761e53 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -573,22 +573,25 @@ EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
 
 static inline void omap_enable_channel_irq(int lch)
 {
-        u32 status;
-
         /* Clear CSR */
         if (cpu_class_is_omap1())
-                status = p->dma_read(CSR, lch);
-        else if (cpu_class_is_omap2())
+                p->dma_read(CSR, lch);
+        else
                 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 
         /* Enable some nice interrupts. */
         p->dma_write(dma_chan[lch].enabled_irqs, CICR, lch);
 }
 
-static void omap_disable_channel_irq(int lch)
+static inline void omap_disable_channel_irq(int lch)
 {
-        if (cpu_class_is_omap2())
-                p->dma_write(0, CICR, lch);
+        /* disable channel interrupts */
+        p->dma_write(0, CICR, lch);
+        /* Clear CSR */
+        if (cpu_class_is_omap1())
+                p->dma_read(CSR, lch);
+        else
+                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
 }
 
 void omap_enable_dma_irq(int lch, u16 bits)
@@ -632,14 +635,14 @@ static inline void disable_lnk(int lch)
         l = p->dma_read(CLNK_CTRL, lch);
 
         /* Disable interrupts */
+        omap_disable_channel_irq(lch);
+
         if (cpu_class_is_omap1()) {
-                p->dma_write(0, CICR, lch);
                 /* Set the STOP_LNK bit */
                 l |= 1 << 14;
         }
 
         if (cpu_class_is_omap2()) {
-                omap_disable_channel_irq(lch);
                 /* Clear the ENABLE_LNK bit */
                 l &= ~(1 << 15);
         }
@@ -657,6 +660,9 @@ static inline void omap2_enable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Enable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val |= 1 << lch;
         p->dma_write(val, IRQENABLE_L0, lch);
@@ -672,9 +678,12 @@ static inline void omap2_disable_irq_lch(int lch)
                 return;
 
         spin_lock_irqsave(&dma_chan_lock, flags);
+        /* Disable interrupt */
         val = p->dma_read(IRQENABLE_L0, lch);
         val &= ~(1 << lch);
         p->dma_write(val, IRQENABLE_L0, lch);
+        /* clear IRQ STATUS */
+        p->dma_write(1 << lch, IRQSTATUS_L0, lch);
         spin_unlock_irqrestore(&dma_chan_lock, flags);
 }
 
@@ -745,11 +754,8 @@ int omap_request_dma(int dev_id, const char *dev_name,
         }
 
         if (cpu_class_is_omap2()) {
-                omap2_enable_irq_lch(free_ch);
                 omap_enable_channel_irq(free_ch);
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch);
-                p->dma_write(1 << free_ch, IRQSTATUS_L0, 0);
+                omap2_enable_irq_lch(free_ch);
         }
 
         *dma_ch_out = free_ch;
@@ -768,27 +774,19 @@ void omap_free_dma(int lch)
                 return;
         }
 
-        if (cpu_class_is_omap1()) {
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
-        }
-
-        if (cpu_class_is_omap2()) {
+        /* Disable interrupt for logical channel */
+        if (cpu_class_is_omap2())
                 omap2_disable_irq_lch(lch);
 
-                /* Clear the CSR register and IRQ status register */
-                p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch);
-                p->dma_write(1 << lch, IRQSTATUS_L0, lch);
+        /* Disable all DMA interrupts for the channel. */
+        omap_disable_channel_irq(lch);
 
-                /* Disable all DMA interrupts for the channel. */
-                p->dma_write(0, CICR, lch);
+        /* Make sure the DMA transfer is stopped. */
+        p->dma_write(0, CCR, lch);
 
-                /* Make sure the DMA transfer is stopped. */
-                p->dma_write(0, CCR, lch);
+        /* Clear registers */
+        if (cpu_class_is_omap2())
                 omap_clear_dma(lch);
-        }
 
         spin_lock_irqsave(&dma_chan_lock, flags);
         dma_chan[lch].dev_id = -1;
@@ -943,8 +941,7 @@ void omap_stop_dma(int lch)
         u32 l;
 
         /* Disable all interrupts on the channel */
-        if (cpu_class_is_omap1())
-                p->dma_write(0, CICR, lch);
+        omap_disable_channel_irq(lch);
 
         l = p->dma_read(CCR, lch);
         if (IS_DMA_ERRATA(DMA_ERRATA_i541) &&
diff --git a/arch/arm/plat-omap/include/plat/board.h b/arch/arm/plat-omap/include/plat/board.h
index 4814c5b65306..e62f20a5c0af 100644
--- a/arch/arm/plat-omap/include/plat/board.h
+++ b/arch/arm/plat-omap/include/plat/board.h
@@ -57,44 +57,6 @@ struct omap_camera_sensor_config {
         int (*power_off)(void * data);
 };
 
-struct omap_usb_config {
-        /* Configure drivers according to the connectors on your board:
-         *  - "A" connector (rectagular)
-         *      ... for host/OHCI use, set "register_host".
-         *  - "B" connector (squarish) or "Mini-B"
-         *      ... for device/gadget use, set "register_dev".
-         *  - "Mini-AB" connector (very similar to Mini-B)
-         *      ... for OTG use as device OR host, initialize "otg"
-         */
-        unsigned        register_host:1;
-        unsigned        register_dev:1;
-        u8              otg;    /* port number, 1-based:  usb1 == 2 */
-
-        u8              hmc_mode;
-
-        /* implicitly true if otg:  host supports remote wakeup? */
-        u8              rwc;
-
-        /* signaling pins used to talk to transceiver on usbN:
-         *  0 == usbN unused
-         *  2 == usb0-only, using internal transceiver
-         *  3 == 3 wire bidirectional
-         *  4 == 4 wire bidirectional
-         *  6 == 6 wire unidirectional (or TLL)
-         */
-        u8              pins[3];
-
-        struct platform_device *udc_device;
-        struct platform_device *ohci_device;
-        struct platform_device *otg_device;
-
-        u32 (*usb0_init)(unsigned nwires, unsigned is_device);
-        u32 (*usb1_init)(unsigned nwires);
-        u32 (*usb2_init)(unsigned nwires, unsigned alt_pingroup);
-
-        int (*ocpi_enable)(void);
-};
-
 struct omap_lcd_config {
         char panel_name[16];
         char ctrl_name[16];
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index d0ef57c1d71b..656b9862279e 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -156,7 +156,6 @@ struct dpll_data {
         u8                      min_divider;
         u16                     max_divider;
         u8                      modes;
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
         void __iomem            *autoidle_reg;
         void __iomem            *idlest_reg;
         u32                     autoidle_mask;
@@ -167,7 +166,6 @@ struct dpll_data {
         u8                      auto_recal_bit;
         u8                      recal_en_bit;
         u8                      recal_st_bit;
-#  endif
         u8                      flags;
 };
 
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index de6c0a08f461..430081ac0c47 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -238,9 +238,7 @@ IS_AM_SUBCLASS(335x, 0x335)
 /*
  * Macros to detect individual cpu types.
  * These are only rarely needed.
- * cpu_is_omap330():    True for OMAP330
- * cpu_is_omap730():    True for OMAP730
- * cpu_is_omap850():    True for OMAP850
+ * cpu_is_omap310():    True for OMAP310
  * cpu_is_omap1510():   True for OMAP1510
  * cpu_is_omap1610():   True for OMAP1610
  * cpu_is_omap1611():   True for OMAP1611
@@ -262,8 +260,6 @@ static inline int is_omap ##type (void)			\
 }
 
 IS_OMAP_TYPE(310, 0x0310)
-IS_OMAP_TYPE(730, 0x0730)
-IS_OMAP_TYPE(850, 0x0850)
 IS_OMAP_TYPE(1510, 0x1510)
 IS_OMAP_TYPE(1610, 0x1610)
 IS_OMAP_TYPE(1611, 0x1611)
@@ -277,8 +273,6 @@ IS_OMAP_TYPE(2430, 0x2430)
 IS_OMAP_TYPE(3430, 0x3430)
 
 #define cpu_is_omap310()                0
-#define cpu_is_omap730()                0
-#define cpu_is_omap850()                0
 #define cpu_is_omap1510()               0
 #define cpu_is_omap1610()               0
 #define cpu_is_omap5912()               0
@@ -294,19 +288,9 @@ IS_OMAP_TYPE(3430, 0x3430)
 
 /*
  * Whether we have MULTI_OMAP1 or not, we still need to distinguish
- * between 730 vs 850, 330 vs. 1510 and 1611B/5912 vs. 1710.
+ * between 310 vs. 1510 and 1611B/5912 vs. 1710.
  */
 
-#if defined(CONFIG_ARCH_OMAP730)
-# undef  cpu_is_omap730
-# define cpu_is_omap730()               is_omap730()
-#endif
-
-#if defined(CONFIG_ARCH_OMAP850)
-# undef  cpu_is_omap850
-# define cpu_is_omap850()               is_omap850()
-#endif
-
 #if defined(CONFIG_ARCH_OMAP15XX)
 # undef  cpu_is_omap310
 # undef  cpu_is_omap1510
diff --git a/arch/arm/plat-omap/include/plat/dsp.h b/arch/arm/plat-omap/include/plat/dsp.h
index 9c604b390f9f..5927709b1908 100644
--- a/arch/arm/plat-omap/include/plat/dsp.h
+++ b/arch/arm/plat-omap/include/plat/dsp.h
@@ -18,6 +18,9 @@ struct omap_dsp_platform_data {
         u32 (*dsp_cm_read)(s16 , u16);
         u32 (*dsp_cm_rmw_bits)(u32, u32, s16, s16);
 
+        void (*set_bootaddr)(u32);
+        void (*set_bootmode)(u8);
+
         phys_addr_t phys_mempool_base;
         phys_addr_t phys_mempool_size;
 };
diff --git a/arch/arm/plat-omap/include/plat/mux.h b/arch/arm/plat-omap/include/plat/mux.h
index aeba71796ad9..323948959200 100644
--- a/arch/arm/plat-omap/include/plat/mux.h
+++ b/arch/arm/plat-omap/include/plat/mux.h
@@ -99,7 +99,7 @@
 
 /*
  * OMAP730/850 has a slightly different config for the pin mux.
- * - config regs are the OMAP7XX_IO_CONF_x regs (see omap730.h) regs and
+ * - config regs are the OMAP7XX_IO_CONF_x regs (see omap7xx.h) regs and
  *   not the FUNC_MUX_CTRL_x regs from hardware.h
  * - for pull-up/down, only has one enable bit which is is in the same register
  *   as mux config
diff --git a/arch/arm/plat-omap/include/plat/omap730.h b/arch/arm/plat-omap/include/plat/omap730.h
deleted file mode 100644
index 14272bc1a6fd..000000000000
--- a/arch/arm/plat-omap/include/plat/omap730.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap730.h
- *
- * Hardware definitions for TI OMAP730 processor.
- *
- * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP730_H
-#define __ASM_ARCH_OMAP730_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP730_DSP_BASE        0xE0000000
-#define OMAP730_DSP_SIZE        0x50000
-#define OMAP730_DSP_START       0xE0000000
-
-#define OMAP730_DSPREG_BASE     0xE1000000
-#define OMAP730_DSPREG_SIZE     SZ_128K
-#define OMAP730_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_CONFIG_BASE     0xfffe1000
-#define OMAP730_IO_CONF_0       0xfffe1070
-#define OMAP730_IO_CONF_1       0xfffe1074
-#define OMAP730_IO_CONF_2       0xfffe1078
-#define OMAP730_IO_CONF_3       0xfffe107c
-#define OMAP730_IO_CONF_4       0xfffe1080
-#define OMAP730_IO_CONF_5       0xfffe1084
-#define OMAP730_IO_CONF_6       0xfffe1088
-#define OMAP730_IO_CONF_7       0xfffe108c
-#define OMAP730_IO_CONF_8       0xfffe1090
-#define OMAP730_IO_CONF_9       0xfffe1094
-#define OMAP730_IO_CONF_10      0xfffe1098
-#define OMAP730_IO_CONF_11      0xfffe109c
-#define OMAP730_IO_CONF_12      0xfffe10a0
-#define OMAP730_IO_CONF_13      0xfffe10a4
-
-#define OMAP730_MODE_1          0xfffe1010
-#define OMAP730_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP730_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_FLASH_CFG_0     0xfffecc10
-#define OMAP730_FLASH_ACFG_0    0xfffecc50
-#define OMAP730_FLASH_CFG_1     0xfffecc14
-#define OMAP730_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_ICR_BASE        0xfffbb800
-#define OMAP730_DSP_M_CTL       0xfffbb804
-#define OMAP730_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP730 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP730_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap850.h b/arch/arm/plat-omap/include/plat/omap850.h
deleted file mode 100644
index c33f67981712..000000000000
--- a/arch/arm/plat-omap/include/plat/omap850.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/* arch/arm/plat-omap/include/mach/omap850.h
- *
- * Hardware definitions for TI OMAP850 processor.
- *
- * Derived from omap730.h by Zebediah C. McClure <zmc@lurian.net>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the  GNU General Public License along
- * with this program; if not, write  to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_ARCH_OMAP850_H
-#define __ASM_ARCH_OMAP850_H
-
-/*
- * ----------------------------------------------------------------------------
- * Base addresses
- * ----------------------------------------------------------------------------
- */
-
-/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
-
-#define OMAP850_DSP_BASE        0xE0000000
-#define OMAP850_DSP_SIZE        0x50000
-#define OMAP850_DSP_START       0xE0000000
-
-#define OMAP850_DSPREG_BASE     0xE1000000
-#define OMAP850_DSPREG_SIZE     SZ_128K
-#define OMAP850_DSPREG_START    0xE1000000
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 specific configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_CONFIG_BASE     0xfffe1000
-#define OMAP850_IO_CONF_0       0xfffe1070
-#define OMAP850_IO_CONF_1       0xfffe1074
-#define OMAP850_IO_CONF_2       0xfffe1078
-#define OMAP850_IO_CONF_3       0xfffe107c
-#define OMAP850_IO_CONF_4       0xfffe1080
-#define OMAP850_IO_CONF_5       0xfffe1084
-#define OMAP850_IO_CONF_6       0xfffe1088
-#define OMAP850_IO_CONF_7       0xfffe108c
-#define OMAP850_IO_CONF_8       0xfffe1090
-#define OMAP850_IO_CONF_9       0xfffe1094
-#define OMAP850_IO_CONF_10      0xfffe1098
-#define OMAP850_IO_CONF_11      0xfffe109c
-#define OMAP850_IO_CONF_12      0xfffe10a0
-#define OMAP850_IO_CONF_13      0xfffe10a4
-
-#define OMAP850_MODE_1          0xfffe1010
-#define OMAP850_MODE_2          0xfffe1014
-
-/* CSMI specials: in terms of base + offset */
-#define OMAP850_MODE2_OFFSET    0x14
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 traffic controller configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_FLASH_CFG_0     0xfffecc10
-#define OMAP850_FLASH_ACFG_0    0xfffecc50
-#define OMAP850_FLASH_CFG_1     0xfffecc14
-#define OMAP850_FLASH_ACFG_1    0xfffecc54
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 DSP control registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_ICR_BASE        0xfffbb800
-#define OMAP850_DSP_M_CTL       0xfffbb804
-#define OMAP850_DSP_MMU_BASE    0xfffed200
-
-/*
- * ----------------------------------------------------------------------------
- * OMAP850 PCC_UPLD configuration registers
- * ----------------------------------------------------------------------------
- */
-#define OMAP850_PCC_UPLD_CTRL_BASE      (0xfffe0900)
-#define OMAP850_PCC_UPLD_CTRL           (OMAP850_PCC_UPLD_CTRL_BASE + 0x00)
-
-#endif /*  __ASM_ARCH_OMAP850_H */
-
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index c835b7194ff5..a8ecc53b3670 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -629,6 +629,8 @@ int omap_hwmod_no_setup_reset(struct omap_hwmod *oh);
 
 int omap_hwmod_pad_route_irq(struct omap_hwmod *oh, int pad_idx, int irq_idx);
 
+extern void __init omap_hwmod_init(void);
+
 /*
  * Chip variant-specific hwmod init routines - XXX should be converted
  * to use initcalls once the initial boot ordering is straightened out
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index b073e5f2b190..28e2d250c2fd 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -60,6 +60,9 @@
 /* AM3505/3517 UART4 */
 #define AM35XX_UART4_BASE       0x4809E000      /* Only on AM3505/3517 */
 
+/* AM33XX serial port */
+#define AM33XX_UART1_BASE       0x44E09000
+
 /* External port on Zoom2/3 */
 #define ZOOM_UART_BASE          0x10000000
 #define ZOOM_UART_VIRT          0xfa400000
@@ -93,6 +96,7 @@
 #define TI81XXUART1             81
 #define TI81XXUART2             82
 #define TI81XXUART3             83
+#define AM33XXUART1             84
 #define ZOOM_UART               95              /* Only on zoom2/3 */
 
 /* This is only used by 8250.c for omap1510 */
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index cc3f11ba7a99..ac4323390213 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -103,6 +103,10 @@ static inline void flush(void)
         _DEBUG_LL_ENTRY(mach, TI81XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
                 TI81XXUART##p)
 
+#define DEBUG_LL_AM33XX(p, mach)                                        \
+        _DEBUG_LL_ENTRY(mach, AM33XX_UART##p##_BASE, OMAP_PORT_SHIFT,   \
+                AM33XXUART##p)
+
 static inline void __arch_decomp_setup(unsigned long arch_id)
 {
         int port = 0;
@@ -183,6 +187,8 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
                 /* TI8148 base boards using UART1 */
                 DEBUG_LL_TI81XX(1, ti8148evm);
 
+                /* AM33XX base boards using UART1 */
+                DEBUG_LL_AM33XX(1, am335xevm);
         } while (0);
 }
 
diff --git a/arch/arm/plat-omap/include/plat/usb.h b/arch/arm/plat-omap/include/plat/usb.h
index 762eeb0626c1..548a4c8d63df 100644
--- a/arch/arm/plat-omap/include/plat/usb.h
+++ b/arch/arm/plat-omap/include/plat/usb.h
@@ -44,6 +44,8 @@ struct usbhs_omap_board_data {
         struct regulator                *regulator[OMAP3_HS_USB_PORTS];
 };
 
+#ifdef CONFIG_ARCH_OMAP2PLUS
+
 struct ehci_hcd_omap_platform_data {
         enum usbhs_omap_port_mode       port_mode[OMAP3_HS_USB_PORTS];
         int                             reset_gpio_port[OMAP3_HS_USB_PORTS];
@@ -64,26 +66,6 @@ struct usbhs_omap_platform_data {
 };
 /*-------------------------------------------------------------------------*/
 
-#define OMAP1_OTG_BASE                  0xfffb0400
-#define OMAP1_UDC_BASE                  0xfffb4000
-#define OMAP1_OHCI_BASE                 0xfffba000
-
-#define OMAP2_OHCI_BASE                 0x4805e000
-#define OMAP2_UDC_BASE                  0x4805e200
-#define OMAP2_OTG_BASE                  0x4805e300
-
-#ifdef CONFIG_ARCH_OMAP1
-
-#define OTG_BASE                        OMAP1_OTG_BASE
-#define UDC_BASE                        OMAP1_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP1_OHCI_BASE
-
-#else
-
-#define OTG_BASE                        OMAP2_OTG_BASE
-#define UDC_BASE                        OMAP2_UDC_BASE
-#define OMAP_OHCI_BASE                  OMAP2_OHCI_BASE
-
 struct omap_musb_board_data {
         u8      interface_type;
         u8      mode;
@@ -107,44 +89,6 @@ extern int omap4430_phy_init(struct device *dev);
 extern int omap4430_phy_exit(struct device *dev);
 extern int omap4430_phy_suspend(struct device *dev, int suspend);
 
-/*
- * NOTE: Please update omap USB drivers to use ioremap + read/write
- */
-
-#define OMAP2_L4_IO_OFFSET      0xb2000000
-#define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET)
-
-static inline u8 omap_readb(u32 pa)
-{
-        return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u16 omap_readw(u32 pa)
-{
-        return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline u32 omap_readl(u32 pa)
-{
-        return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writeb(u8 v, u32 pa)
-{
-        __raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-
-static inline void omap_writew(u16 v, u32 pa)
-{
-        __raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
-static inline void omap_writel(u32 v, u32 pa)
-{
-        __raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
-}
-
 #endif
 
 extern void am35x_musb_reset(void);
@@ -153,142 +97,6 @@ extern void am35x_musb_clear_irq(void);
 extern void am35x_set_mode(u8 musb_mode);
 extern void ti81xx_musb_phy_power(u8 on);
 
-/*
- * FIXME correct answer depends on hmc_mode,
- * as does (on omap1) any nonzero value for config->otg port number
- */
-#ifdef  CONFIG_USB_GADGET_OMAP
-#define is_usb0_device(config)  1
-#else
-#define is_usb0_device(config)  0
-#endif
-
-void omap_otg_init(struct omap_usb_config *config);
-
-#if defined(CONFIG_USB) || defined(CONFIG_USB_MODULE)
-void omap1_usb_init(struct omap_usb_config *pdata);
-#else
-static inline void omap1_usb_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-#if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP_OTG_MODULE)
-void omap2_usbfs_init(struct omap_usb_config *pdata);
-#else
-static inline void omap2_usbfs_init(struct omap_usb_config *pdata)
-{
-}
-#endif
-
-/*-------------------------------------------------------------------------*/
-
-/*
- * OTG and transceiver registers, for OMAPs starting with ARM926
- */
-#define OTG_REV                         (OTG_BASE + 0x00)
-#define OTG_SYSCON_1                    (OTG_BASE + 0x04)
-#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
-#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
-#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
-#       define   OTG_IDLE_EN            (1 << 15)
-#       define   HST_IDLE_EN            (1 << 14)
-#       define   DEV_IDLE_EN            (1 << 13)
-#       define   OTG_RESET_DONE         (1 << 2)
-#       define   OTG_SOFT_RESET         (1 << 1)
-#define OTG_SYSCON_2                    (OTG_BASE + 0x08)
-#       define   OTG_EN                 (1 << 31)
-#       define   USBX_SYNCHRO           (1 << 30)
-#       define   OTG_MST16              (1 << 29)
-#       define   SRP_GPDATA             (1 << 28)
-#       define   SRP_GPDVBUS            (1 << 27)
-#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
-#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
-#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
-#       define   SRP_DPW                (1 << 14)
-#       define   SRP_DATA               (1 << 13)
-#       define   SRP_VBUS               (1 << 12)
-#       define   OTG_PADEN              (1 << 10)
-#       define   HMC_PADEN              (1 << 9)
-#       define   UHOST_EN               (1 << 8)
-#       define   HMC_TLLSPEED           (1 << 7)
-#       define   HMC_TLLATTACH          (1 << 6)
-#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
-#define OTG_CTRL                        (OTG_BASE + 0x0c)
-#       define   OTG_USB2_EN            (1 << 29)
-#       define   OTG_USB2_DP            (1 << 28)
-#       define   OTG_USB2_DM            (1 << 27)
-#       define   OTG_USB1_EN            (1 << 26)
-#       define   OTG_USB1_DP            (1 << 25)
-#       define   OTG_USB1_DM            (1 << 24)
-#       define   OTG_USB0_EN            (1 << 23)
-#       define   OTG_USB0_DP            (1 << 22)
-#       define   OTG_USB0_DM            (1 << 21)
-#       define   OTG_ASESSVLD           (1 << 20)
-#       define   OTG_BSESSEND           (1 << 19)
-#       define   OTG_BSESSVLD           (1 << 18)
-#       define   OTG_VBUSVLD            (1 << 17)
-#       define   OTG_ID                 (1 << 16)
-#       define   OTG_DRIVER_SEL         (1 << 15)
-#       define   OTG_A_SETB_HNPEN       (1 << 12)
-#       define   OTG_A_BUSREQ           (1 << 11)
-#       define   OTG_B_HNPEN            (1 << 9)
-#       define   OTG_B_BUSREQ           (1 << 8)
-#       define   OTG_BUSDROP            (1 << 7)
-#       define   OTG_PULLDOWN           (1 << 5)
-#       define   OTG_PULLUP             (1 << 4)
-#       define   OTG_DRV_VBUS           (1 << 3)
-#       define   OTG_PD_VBUS            (1 << 2)
-#       define   OTG_PU_VBUS            (1 << 1)
-#       define   OTG_PU_ID              (1 << 0)
-#define OTG_IRQ_EN                      (OTG_BASE + 0x10)       /* 16-bit */
-#       define   DRIVER_SWITCH          (1 << 15)
-#       define   A_VBUS_ERR             (1 << 13)
-#       define   A_REQ_TMROUT           (1 << 12)
-#       define   A_SRP_DETECT           (1 << 11)
-#       define   B_HNP_FAIL             (1 << 10)
-#       define   B_SRP_TMROUT           (1 << 9)
-#       define   B_SRP_DONE             (1 << 8)
-#       define   B_SRP_STARTED          (1 << 7)
-#       define   OPRT_CHG               (1 << 0)
-#define OTG_IRQ_SRC                     (OTG_BASE + 0x14)       /* 16-bit */
-        // same bits as in IRQ_EN
-#define OTG_OUTCTRL                     (OTG_BASE + 0x18)       /* 16-bit */
-#       define   OTGVPD                 (1 << 14)
-#       define   OTGVPU                 (1 << 13)
-#       define   OTGPUID                (1 << 12)
-#       define   USB2VDR                (1 << 10)
-#       define   USB2PDEN               (1 << 9)
-#       define   USB2PUEN               (1 << 8)
-#       define   USB1VDR                (1 << 6)
-#       define   USB1PDEN               (1 << 5)
-#       define   USB1PUEN               (1 << 4)
-#       define   USB0VDR                (1 << 2)
-#       define   USB0PDEN               (1 << 1)
-#       define   USB0PUEN               (1 << 0)
-#define OTG_TEST                        (OTG_BASE + 0x20)       /* 16-bit */
-#define OTG_VENDOR_CODE                 (OTG_BASE + 0xfc)       /* 16-bit */
-
-/*-------------------------------------------------------------------------*/
-
-/* OMAP1 */
-#define USB_TRANSCEIVER_CTRL            (0xfffe1000 + 0x0064)
-#       define  CONF_USB2_UNI_R         (1 << 8)
-#       define  CONF_USB1_UNI_R         (1 << 7)
-#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
-#       define  CONF_USB0_ISOLATE_R     (1 << 3)
-#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
-#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
-
-/* OMAP2 */
-#       define  USB_UNIDIR                      0x0
-#       define  USB_UNIDIR_TLL                  0x1
-#       define  USB_BIDIR                       0x2
-#       define  USB_BIDIR_TLL                   0x3
-#       define  USBTXWRMODEI(port, x)   ((x) << (22 - (port * 2)))
-#       define  USBT2TLL5PI             (1 << 17)
-#       define  USB0PUENACTLOI          (1 << 16)
-#       define  USBSTANDBYCTRL          (1 << 15)
 /* AM35x */
 /* USB 2.0 PHY Control */
 #define CONF2_PHY_GPIOMODE      (1 << 23)
diff --git a/arch/arm/plat-omap/mailbox.c b/arch/arm/plat-omap/mailbox.c
index ad32621aa52e..5e13c3884aa4 100644
--- a/arch/arm/plat-omap/mailbox.c
+++ b/arch/arm/plat-omap/mailbox.c
@@ -282,6 +282,8 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
                 }
                 mbox->rxq = mq;
                 mq->mbox = mbox;
+
+                omap_mbox_enable_irq(mbox, IRQ_RX);
         }
         mutex_unlock(&mbox_configured_lock);
         return 0;
@@ -305,6 +307,7 @@ static void omap_mbox_fini(struct omap_mbox *mbox)
         mutex_lock(&mbox_configured_lock);
 
         if (!--mbox->use_count) {
+                omap_mbox_disable_irq(mbox, IRQ_RX);
                 free_irq(mbox->irq, mbox);
                 tasklet_kill(&mbox->txq->tasklet);
                 flush_work_sync(&mbox->rxq->work);
@@ -338,13 +341,15 @@ struct omap_mbox *omap_mbox_get(const char *name, struct notifier_block *nb)
         if (!mbox)
                 return ERR_PTR(-ENOENT);
 
-        ret = omap_mbox_startup(mbox);
-        if (ret)
-                return ERR_PTR(-ENODEV);
-
         if (nb)
                 blocking_notifier_chain_register(&mbox->notifier, nb);
 
+        ret = omap_mbox_startup(mbox);
+        if (ret) {
+                blocking_notifier_chain_unregister(&mbox->notifier, nb);
+                return ERR_PTR(-ENODEV);
+        }
+
         return mbox;
 }
 EXPORT_SYMBOL(omap_mbox_get);
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
deleted file mode 100644
index daa0327381b5..000000000000
--- a/arch/arm/plat-omap/usb.c
+++ /dev/null
@@ -1,145 +0,0 @@
- /*
- * arch/arm/plat-omap/usb.c -- platform level USB initialization
- *
- * Copyright (C) 2004 Texas Instruments, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#undef  DEBUG
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <plat/usb.h>
-#include <plat/board.h>
-
-#include <mach/hardware.h>
-
-#ifdef  CONFIG_ARCH_OMAP_OTG
-
-void __init
-omap_otg_init(struct omap_usb_config *config)
-{
-        u32             syscon;
-        int             alt_pingroup = 0;
-
-        /* NOTE:  no bus or clock setup (yet?) */
-
-        syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
-        if (!(syscon & OTG_RESET_DONE))
-                pr_debug("USB resets not complete?\n");
-
-        //omap_writew(0, OTG_IRQ_EN);
-
-        /* pin muxing and transceiver pinouts */
-        if (config->pins[0] > 2)        /* alt pingroup 2 */
-                alt_pingroup = 1;
-        syscon |= config->usb0_init(config->pins[0], is_usb0_device(config));
-        syscon |= config->usb1_init(config->pins[1]);
-        syscon |= config->usb2_init(config->pins[2], alt_pingroup);
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-
-        syscon = config->hmc_mode;
-        syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
-#ifdef  CONFIG_USB_OTG
-        if (config->otg)
-                syscon |= OTG_EN;
-#endif
-        if (cpu_class_is_omap1())
-                pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
-                         omap_readl(USB_TRANSCEIVER_CTRL));
-        pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
-        omap_writel(syscon, OTG_SYSCON_2);
-
-        printk("USB: hmc %d", config->hmc_mode);
-        if (!alt_pingroup)
-                printk(", usb2 alt %d wires", config->pins[2]);
-        else if (config->pins[0])
-                printk(", usb0 %d wires%s", config->pins[0],
-                        is_usb0_device(config) ? " (dev)" : "");
-        if (config->pins[1])
-                printk(", usb1 %d wires", config->pins[1]);
-        if (!alt_pingroup && config->pins[2])
-                printk(", usb2 %d wires", config->pins[2]);
-        if (config->otg)
-                printk(", Mini-AB on usb%d", config->otg - 1);
-        printk("\n");
-
-        if (cpu_class_is_omap1()) {
-                u16 w;
-
-                /* leave USB clocks/controllers off until needed */
-                w = omap_readw(ULPD_SOFT_REQ);
-                w &= ~SOFT_USB_CLK_REQ;
-                omap_writew(w, ULPD_SOFT_REQ);
-
-                w = omap_readw(ULPD_CLOCK_CTRL);
-                w &= ~USB_MCLK_EN;
-                w |= DIS_USB_PVCI_CLK;
-                omap_writew(w, ULPD_CLOCK_CTRL);
-        }
-        syscon = omap_readl(OTG_SYSCON_1);
-        syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
-
-#ifdef  CONFIG_USB_GADGET_OMAP
-        if (config->otg || config->register_dev) {
-                struct platform_device *udc_device = config->udc_device;
-                int status;
-
-                syscon &= ~DEV_IDLE_EN;
-                udc_device->dev.platform_data = config;
-                status = platform_device_register(udc_device);
-                if (status)
-                        pr_debug("can't register UDC device, %d\n", status);
-        }
-#endif
-
-#if     defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
-        if (config->otg || config->register_host) {
-                struct platform_device *ohci_device = config->ohci_device;
-                int status;
-
-                syscon &= ~HST_IDLE_EN;
-                ohci_device->dev.platform_data = config;
-                status = platform_device_register(ohci_device);
-                if (status)
-                        pr_debug("can't register OHCI device, %d\n", status);
-        }
-#endif
-
-#ifdef  CONFIG_USB_OTG
-        if (config->otg) {
-                struct platform_device *otg_device = config->otg_device;
-                int status;
-
-                syscon &= ~OTG_IDLE_EN;
-                otg_device->dev.platform_data = config;
-                status = platform_device_register(otg_device);
-                if (status)
-                        pr_debug("can't register OTG device, %d\n", status);
-        }
-#endif
-        pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
-        omap_writel(syscon, OTG_SYSCON_1);
-}
-
-#else
-void omap_otg_init(struct omap_usb_config *config) {}
-#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a2fae4ea0936..7aca31c1df1f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -78,6 +78,10 @@ config S5P_HRT
 
 # clock options
 
+config SAMSUNG_CLOCK
+        bool
+        default y if !COMMON_CLK
+
 config SAMSUNG_CLKSRC
         bool
         help
@@ -491,14 +495,6 @@ config S5P_SLEEP
           Internal config node to apply common S5P sleep management code.
           Can be selected by S5P and newer SoCs with similar sleep procedure.
 
-comment "Power Domain"
-
-config SAMSUNG_PD
-        bool "Samsung Power Domain"
-        depends on PM_RUNTIME
-        help
-          Say Y here if you want to control Power Domain by Runtime PM.
-
 config DEBUG_S3C_UART
         depends on PLAT_SAMSUNG
         int
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 860b2db4db15..b78717496677 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -15,8 +15,8 @@ obj-y				+= init.o cpu.o
 obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET)   += time.o
 obj-$(CONFIG_S5P_HRT)           += s5p-time.o
 
-obj-y                           += clock.o
-obj-y                           += pwm-clock.o
+obj-$(CONFIG_SAMSUNG_CLOCK)     += clock.o
+obj-$(CONFIG_SAMSUNG_CLOCK)     += pwm-clock.o
 
 obj-$(CONFIG_SAMSUNG_CLKSRC)    += clock-clksrc.o
 obj-$(CONFIG_S5P_CLOCK)         += s5p-clock.o
@@ -60,10 +60,6 @@ obj-$(CONFIG_SAMSUNG_WAKEMASK)	+= wakeup-mask.o
 obj-$(CONFIG_S5P_PM)            += s5p-pm.o s5p-irq-pm.o
 obj-$(CONFIG_S5P_SLEEP)         += s5p-sleep.o
 
-# PD support
-
-obj-$(CONFIG_SAMSUNG_PD)        += pd.o
-
 # PWM support
 
 obj-$(CONFIG_HAVE_PWM)          += pwm.o
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 33ecd0c9f0c3..b1e05ccff3ac 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -157,11 +157,13 @@ int s3c_adc_start(struct s3c_adc_client *client,
                 return -EINVAL;
         }
 
-        if (client->is_ts && adc->ts_pend)
-                return -EAGAIN;
-
         spin_lock_irqsave(&adc->lock, flags);
 
+        if (client->is_ts && adc->ts_pend) {
+                spin_unlock_irqrestore(&adc->lock, flags);
+                return -EAGAIN;
+        }
+
         client->channel = channel;
         client->nr_samples = nr_samples;
 
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index 1d214cb9d770..74e31ce35538 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -126,7 +126,8 @@ struct platform_device s3c_device_adc = {
 #ifdef CONFIG_CPU_S3C2440
 static struct resource s3c_camif_resource[] = {
         [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
-        [1] = DEFINE_RES_IRQ(IRQ_CAM),
+        [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
+        [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
 };
 
 struct platform_device s3c_device_camif = {
@@ -1512,7 +1513,7 @@ static struct resource s3c64xx_spi0_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi0 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 0,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi0_resource),
         .resource       = s3c64xx_spi0_resource,
@@ -1522,13 +1523,10 @@ struct platform_device s3c64xx_device_spi0 = {
         },
 };
 
-void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
+        struct s3c64xx_spi_info pd;
 
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
@@ -1536,12 +1534,11 @@ void __init s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi0_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi0);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI0 */
 
@@ -1554,7 +1551,7 @@ static struct resource s3c64xx_spi1_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi1 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 1,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi1_resource),
         .resource       = s3c64xx_spi1_resource,
@@ -1564,26 +1561,20 @@ struct platform_device s3c64xx_device_spi1 = {
         },
 };
 
-void __init s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
-
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
                 pr_err("%s: Invalid SPI configuration\n", __func__);
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi1_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi1);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI1 */
 
@@ -1596,7 +1587,7 @@ static struct resource s3c64xx_spi2_resource[] = {
 };
 
 struct platform_device s3c64xx_device_spi2 = {
-        .name           = "s3c64xx-spi",
+        .name           = "s3c6410-spi",
         .id             = 2,
         .num_resources  = ARRAY_SIZE(s3c64xx_spi2_resource),
         .resource       = s3c64xx_spi2_resource,
@@ -1606,13 +1597,10 @@ struct platform_device s3c64xx_device_spi2 = {
         },
 };
 
-void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs)
+void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs)
 {
-        if (!pd) {
-                pr_err("%s:Need to pass platform data\n", __func__);
-                return;
-        }
+        struct s3c64xx_spi_info pd;
 
         /* Reject invalid configuration */
         if (!num_cs || src_clk_nr < 0) {
@@ -1620,11 +1608,10 @@ void __init s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
                 return;
         }
 
-        pd->num_cs = num_cs;
-        pd->src_clk_nr = src_clk_nr;
-        if (!pd->cfg_gpio)
-                pd->cfg_gpio = s3c64xx_spi2_cfg_gpio;
+        pd.num_cs = num_cs;
+        pd.src_clk_nr = src_clk_nr;
+        pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
 
-        s3c_set_platdata(pd, sizeof(*pd), &s3c64xx_device_spi2);
+        s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
 }
 #endif /* CONFIG_S3C64XX_DEV_SPI2 */
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index eb9f4f534006..c38d75489240 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -19,72 +19,79 @@
 #include <mach/dma.h>
 
 static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
-                                struct samsung_dma_info *info)
+                                struct samsung_dma_req *param)
 {
-        struct dma_chan *chan;
         dma_cap_mask_t mask;
-        struct dma_slave_config slave_config;
         void *filter_param;
 
         dma_cap_zero(mask);
-        dma_cap_set(info->cap, mask);
+        dma_cap_set(param->cap, mask);
 
         /*
          * If a dma channel property of a device node from device tree is
          * specified, use that as the fliter parameter.
          */
-        filter_param = (dma_ch == DMACH_DT_PROP) ? (void *)info->dt_dmach_prop :
-                                (void *)dma_ch;
-        chan = dma_request_channel(mask, pl330_filter, filter_param);
+        filter_param = (dma_ch == DMACH_DT_PROP) ?
+                (void *)param->dt_dmach_prop : (void *)dma_ch;
+        return (unsigned)dma_request_channel(mask, pl330_filter, filter_param);
+}
+
+static int samsung_dmadev_release(unsigned ch, void *param)
+{
+        dma_release_channel((struct dma_chan *)ch);
 
-        if (info->direction == DMA_DEV_TO_MEM) {
+        return 0;
+}
+
+static int samsung_dmadev_config(unsigned ch,
+                                struct samsung_dma_config *param)
+{
+        struct dma_chan *chan = (struct dma_chan *)ch;
+        struct dma_slave_config slave_config;
+
+        if (param->direction == DMA_DEV_TO_MEM) {
                 memset(&slave_config, 0, sizeof(struct dma_slave_config));
-                slave_config.direction = info->direction;
-                slave_config.src_addr = info->fifo;
-                slave_config.src_addr_width = info->width;
+                slave_config.direction = param->direction;
+                slave_config.src_addr = param->fifo;
+                slave_config.src_addr_width = param->width;
                 slave_config.src_maxburst = 1;
                 dmaengine_slave_config(chan, &slave_config);
-        } else if (info->direction == DMA_MEM_TO_DEV) {
+        } else if (param->direction == DMA_MEM_TO_DEV) {
                 memset(&slave_config, 0, sizeof(struct dma_slave_config));
-                slave_config.direction = info->direction;
-                slave_config.dst_addr = info->fifo;
-                slave_config.dst_addr_width = info->width;
+                slave_config.direction = param->direction;
+                slave_config.dst_addr = param->fifo;
+                slave_config.dst_addr_width = param->width;
                 slave_config.dst_maxburst = 1;
                 dmaengine_slave_config(chan, &slave_config);
+        } else {
+                pr_warn("unsupported direction\n");
+                return -EINVAL;
         }
 
-        return (unsigned)chan;
-}
-
-static int samsung_dmadev_release(unsigned ch,
-                        struct s3c2410_dma_client *client)
-{
-        dma_release_channel((struct dma_chan *)ch);
-
         return 0;
 }
 
 static int samsung_dmadev_prepare(unsigned ch,
-                        struct samsung_dma_prep_info *info)
+                        struct samsung_dma_prep *param)
 {
         struct scatterlist sg;
         struct dma_chan *chan = (struct dma_chan *)ch;
         struct dma_async_tx_descriptor *desc;
 
-        switch (info->cap) {
+        switch (param->cap) {
         case DMA_SLAVE:
                 sg_init_table(&sg, 1);
-                sg_dma_len(&sg) = info->len;
-                sg_set_page(&sg, pfn_to_page(PFN_DOWN(info->buf)),
-                            info->len, offset_in_page(info->buf));
-                sg_dma_address(&sg) = info->buf;
+                sg_dma_len(&sg) = param->len;
+                sg_set_page(&sg, pfn_to_page(PFN_DOWN(param->buf)),
+                            param->len, offset_in_page(param->buf));
+                sg_dma_address(&sg) = param->buf;
 
                 desc = dmaengine_prep_slave_sg(chan,
-                        &sg, 1, info->direction, DMA_PREP_INTERRUPT);
+                        &sg, 1, param->direction, DMA_PREP_INTERRUPT);
                 break;
         case DMA_CYCLIC:
-                desc = dmaengine_prep_dma_cyclic(chan,
-                        info->buf, info->len, info->period, info->direction);
+                desc = dmaengine_prep_dma_cyclic(chan, param->buf,
+                        param->len, param->period, param->direction);
                 break;
         default:
                 dev_err(&chan->dev->device, "unsupported format\n");
@@ -96,8 +103,8 @@ static int samsung_dmadev_prepare(unsigned ch,
                 return -EFAULT;
         }
 
-        desc->callback = info->fp;
-        desc->callback_param = info->fp_param;
+        desc->callback = param->fp;
+        desc->callback_param = param->fp_param;
 
         dmaengine_submit((struct dma_async_tx_descriptor *)desc);
 
@@ -119,6 +126,7 @@ static inline int samsung_dmadev_flush(unsigned ch)
 static struct samsung_dma_ops dmadev_ops = {
         .request        = samsung_dmadev_request,
         .release        = samsung_dmadev_release,
+        .config         = samsung_dmadev_config,
         .prepare        = samsung_dmadev_prepare,
         .trigger        = samsung_dmadev_trigger,
         .started        = NULL,
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 0721293fad63..ace4451b7651 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -132,6 +132,10 @@ IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
 
 #define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
 
+#ifndef KHZ
+#define KHZ (1000)
+#endif
+
 #ifndef MHZ
 #define MHZ (1000*1000)
 #endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index 61ca2f356c52..5da4b4f38f40 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -131,7 +131,6 @@ extern struct platform_device exynos4_device_ohci;
 extern struct platform_device exynos4_device_pcm0;
 extern struct platform_device exynos4_device_pcm1;
 extern struct platform_device exynos4_device_pcm2;
-extern struct platform_device exynos4_device_pd[];
 extern struct platform_device exynos4_device_spdif;
 
 extern struct platform_device exynos_device_drm;
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 71a6827c7706..f5144cdd3001 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -16,7 +16,13 @@
 #include <linux/dmaengine.h>
 #include <mach/dma.h>
 
-struct samsung_dma_prep_info {
+struct samsung_dma_req {
+        enum dma_transaction_type cap;
+        struct property *dt_dmach_prop;
+        struct s3c2410_dma_client *client;
+};
+
+struct samsung_dma_prep {
         enum dma_transaction_type cap;
         enum dma_transfer_direction direction;
         dma_addr_t buf;
@@ -26,19 +32,17 @@ struct samsung_dma_prep_info {
         void *fp_param;
 };
 
-struct samsung_dma_info {
-        enum dma_transaction_type cap;
+struct samsung_dma_config {
         enum dma_transfer_direction direction;
         enum dma_slave_buswidth width;
         dma_addr_t fifo;
-        struct s3c2410_dma_client *client;
-        struct property *dt_dmach_prop;
 };
 
 struct samsung_dma_ops {
-        unsigned (*request)(enum dma_ch ch, struct samsung_dma_info *info);
-        int (*release)(unsigned ch, struct s3c2410_dma_client *client);
-        int (*prepare)(unsigned ch, struct samsung_dma_prep_info *info);
+        unsigned (*request)(enum dma_ch ch, struct samsung_dma_req *param);
+        int (*release)(unsigned ch, void *param);
+        int (*config)(unsigned ch, struct samsung_dma_config *param);
+        int (*prepare)(unsigned ch, struct samsung_dma_prep *param);
         int (*trigger)(unsigned ch);
         int (*started)(unsigned ch);
         int (*flush)(unsigned ch);
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 536002ff2ab8..b885322717a1 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -43,7 +43,6 @@ struct s3c_fb_pd_win {
  * @setup_gpio: Setup the external GPIO pins to the right state to transfer
  *              the data from the display system to the connected display
  *              device.
- * @default_win: default window layer number to be used for UI layer.
  * @vidcon0: The base vidcon0 values to control the panel data format.
  * @vidcon1: The base vidcon1 values to control the panel data output.
  * @vtiming: Video timing when connected to a RGB type panel.
diff --git a/arch/arm/plat-samsung/include/plat/pd.h b/arch/arm/plat-samsung/include/plat/pd.h
deleted file mode 100644
index abb4bc32716a..000000000000
--- a/arch/arm/plat-samsung/include/plat/pd.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/pd.h
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_SAMSUNG_PD_H
-#define __ASM_PLAT_SAMSUNG_PD_H __FILE__
-
-struct samsung_pd_info {
-        int (*enable)(struct device *dev);
-        int (*disable)(struct device *dev);
-        void __iomem *base;
-};
-
-enum exynos4_pd_block {
-        PD_MFC,
-        PD_G3D,
-        PD_LCD0,
-        PD_LCD1,
-        PD_TV,
-        PD_CAM,
-        PD_GPS
-};
-
-#endif /* __ASM_PLAT_SAMSUNG_PD_H */
diff --git a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
index fa95e9a00972..ceba18d23a5a 100644
--- a/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
+++ b/arch/arm/plat-samsung/include/plat/s3c64xx-spi.h
@@ -18,7 +18,6 @@ struct platform_device;
  * @fb_delay: Slave specific feedback delay.
  *            Refer to FB_CLK_SEL register definition in SPI chapter.
  * @line: Custom 'identity' of the CS line.
- * @set_level: CS line control.
  *
  * This is per SPI-Slave Chipselect information.
  * Allocate and initialize one in machine init code and make the
@@ -27,57 +26,41 @@ struct platform_device;
 struct s3c64xx_spi_csinfo {
         u8 fb_delay;
         unsigned line;
-        void (*set_level)(unsigned line_id, int lvl);
 };
 
 /**
  * struct s3c64xx_spi_info - SPI Controller defining structure
  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
- * @clk_from_cmu: If the SPI clock/prescalar control block is present
- *     by the platform's clock-management-unit and not in SPI controller.
  * @num_cs: Number of CS this controller emulates.
  * @cfg_gpio: Configure pins for this SPI controller.
- * @fifo_lvl_mask: All tx fifo_lvl fields start at offset-6
- * @rx_lvl_offset: Depends on tx fifo_lvl field and bus number
- * @high_speed: If the controller supports HIGH_SPEED_EN bit
- * @tx_st_done: Depends on tx fifo_lvl field
  */
 struct s3c64xx_spi_info {
         int src_clk_nr;
-        bool clk_from_cmu;
-
         int num_cs;
-
-        int (*cfg_gpio)(struct platform_device *pdev);
-
-        /* Following two fields are for future compatibility */
-        int fifo_lvl_mask;
-        int rx_lvl_offset;
-        int high_speed;
-        int tx_st_done;
+        int (*cfg_gpio)(void);
 };
 
 /**
  * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
  *                              initialization code.
- * @pd: SPI platform data to set.
+ * @cfg_gpio: Pointer to gpio setup function.
  * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
  * @num_cs: Number of elements in the 'cs' array.
  *
  * Call this from machine init code for each SPI Controller that
  * has some chips attached to it.
  */
-extern void s3c64xx_spi0_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi1_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
-extern void s3c64xx_spi2_set_platdata(struct s3c64xx_spi_info *pd,
-                                      int src_clk_nr, int num_cs);
+extern void s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
+extern void s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
+extern void s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
+                                                int num_cs);
 
 /* defined by architecture to configure gpio */
-extern int s3c64xx_spi0_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi1_cfg_gpio(struct platform_device *dev);
-extern int s3c64xx_spi2_cfg_gpio(struct platform_device *dev);
+extern int s3c64xx_spi0_cfg_gpio(void);
+extern int s3c64xx_spi1_cfg_gpio(void);
+extern int s3c64xx_spi2_cfg_gpio(void);
 
 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
 extern struct s3c64xx_spi_info s3c64xx_spi1_pdata;
diff --git a/arch/arm/plat-samsung/pd.c b/arch/arm/plat-samsung/pd.c
deleted file mode 100644
index 312b510d86b7..000000000000
--- a/arch/arm/plat-samsung/pd.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/* linux/arch/arm/plat-samsung/pd.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- *              http://www.samsung.com
- *
- * Samsung Power domain support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/init.h>
-#include <linux/export.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <linux/pm_runtime.h>
-
-#include <plat/pd.h>
-
-static int samsung_pd_probe(struct platform_device *pdev)
-{
-        struct samsung_pd_info *pdata = pdev->dev.platform_data;
-        struct device *dev = &pdev->dev;
-
-        if (!pdata) {
-                dev_err(dev, "no device data specified\n");
-                return -ENOENT;
-        }
-
-        pm_runtime_set_active(dev);
-        pm_runtime_enable(dev);
-
-        dev_info(dev, "power domain registered\n");
-        return 0;
-}
-
-static int __devexit samsung_pd_remove(struct platform_device *pdev)
-{
-        struct device *dev = &pdev->dev;
-
-        pm_runtime_disable(dev);
-        return 0;
-}
-
-static int samsung_pd_runtime_suspend(struct device *dev)
-{
-        struct samsung_pd_info *pdata = dev->platform_data;
-        int ret = 0;
-
-        if (pdata->disable)
-                ret = pdata->disable(dev);
-
-        dev_dbg(dev, "suspended\n");
-        return ret;
-}
-
-static int samsung_pd_runtime_resume(struct device *dev)
-{
-        struct samsung_pd_info *pdata = dev->platform_data;
-        int ret = 0;
-
-        if (pdata->enable)
-                ret = pdata->enable(dev);
-
-        dev_dbg(dev, "resumed\n");
-        return ret;
-}
-
-static const struct dev_pm_ops samsung_pd_pm_ops = {
-        .runtime_suspend        = samsung_pd_runtime_suspend,
-        .runtime_resume         = samsung_pd_runtime_resume,
-};
-
-static struct platform_driver samsung_pd_driver = {
-        .driver         = {
-                .name           = "samsung-pd",
-                .owner          = THIS_MODULE,
-                .pm             = &samsung_pd_pm_ops,
-        },
-        .probe          = samsung_pd_probe,
-        .remove         = __devexit_p(samsung_pd_remove),
-};
-
-static int __init samsung_pd_init(void)
-{
-        int ret;
-
-        ret = platform_driver_register(&samsung_pd_driver);
-        if (ret)
-                printk(KERN_ERR "%s: failed to add PD driver\n", __func__);
-
-        return ret;
-}
-arch_initcall(samsung_pd_init);
diff --git a/arch/arm/plat-samsung/pwm.c b/arch/arm/plat-samsung/pwm.c
index c559d8438c70..d3583050fb05 100644
--- a/arch/arm/plat-samsung/pwm.c
+++ b/arch/arm/plat-samsung/pwm.c
@@ -36,7 +36,6 @@ struct pwm_device {
         unsigned int             duty_ns;
 
         unsigned char            tcon_base;
-        unsigned char            running;
         unsigned char            use_count;
         unsigned char            pwm_id;
 };
@@ -116,7 +115,6 @@ int pwm_enable(struct pwm_device *pwm)
 
         local_irq_restore(flags);
 
-        pwm->running = 1;
         return 0;
 }
 
@@ -134,8 +132,6 @@ void pwm_disable(struct pwm_device *pwm)
         __raw_writel(tcon, S3C2410_TCON);
 
         local_irq_restore(flags);
-
-        pwm->running = 0;
 }
 
 EXPORT_SYMBOL(pwm_disable);
diff --git a/arch/arm/plat-samsung/s3c-dma-ops.c b/arch/arm/plat-samsung/s3c-dma-ops.c
index 781494912827..f99448c48d30 100644
--- a/arch/arm/plat-samsung/s3c-dma-ops.c
+++ b/arch/arm/plat-samsung/s3c-dma-ops.c
@@ -36,30 +36,26 @@ static void s3c_dma_cb(struct s3c2410_dma_chan *channel, void *param,
 }
 
 static unsigned s3c_dma_request(enum dma_ch dma_ch,
-                                 struct samsung_dma_info *info)
+                                        struct samsung_dma_req *param)
 {
         struct cb_data *data;
 
-        if (s3c2410_dma_request(dma_ch, info->client, NULL) < 0) {
-                s3c2410_dma_free(dma_ch, info->client);
+        if (s3c2410_dma_request(dma_ch, param->client, NULL) < 0) {
+                s3c2410_dma_free(dma_ch, param->client);
                 return 0;
         }
 
+        if (param->cap == DMA_CYCLIC)
+                s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
+
         data = kzalloc(sizeof(struct cb_data), GFP_KERNEL);
         data->ch = dma_ch;
         list_add_tail(&data->node, &dma_list);
 
-        s3c2410_dma_devconfig(dma_ch, info->direction, info->fifo);
-
-        if (info->cap == DMA_CYCLIC)
-                s3c2410_dma_setflags(dma_ch, S3C2410_DMAF_CIRCULAR);
-
-        s3c2410_dma_config(dma_ch, info->width);
-
         return (unsigned)dma_ch;
 }
 
-static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client)
+static int s3c_dma_release(unsigned ch, void *param)
 {
         struct cb_data *data;
 
@@ -68,16 +64,24 @@ static int s3c_dma_release(unsigned ch, struct s3c2410_dma_client *client)
                         break;
         list_del(&data->node);
 
-        s3c2410_dma_free(ch, client);
+        s3c2410_dma_free(ch, param);
         kfree(data);
 
         return 0;
 }
 
-static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info)
+static int s3c_dma_config(unsigned ch, struct samsung_dma_config *param)
+{
+        s3c2410_dma_devconfig(ch, param->direction, param->fifo);
+        s3c2410_dma_config(ch, param->width);
+
+        return 0;
+}
+
+static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep *param)
 {
         struct cb_data *data;
-        int len = (info->cap == DMA_CYCLIC) ? info->period : info->len;
+        int len = (param->cap == DMA_CYCLIC) ? param->period : param->len;
 
         list_for_each_entry(data, &dma_list, node)
                 if (data->ch == ch)
@@ -85,11 +89,11 @@ static int s3c_dma_prepare(unsigned ch, struct samsung_dma_prep_info *info)
 
         if (!data->fp) {
                 s3c2410_dma_set_buffdone_fn(ch, s3c_dma_cb);
-                data->fp = info->fp;
-                data->fp_param = info->fp_param;
+                data->fp = param->fp;
+                data->fp_param = param->fp_param;
         }
 
-        s3c2410_dma_enqueue(ch, (void *)data, info->buf, len);
+        s3c2410_dma_enqueue(ch, (void *)data, param->buf, len);
 
         return 0;
 }
@@ -117,6 +121,7 @@ static inline int s3c_dma_stop(unsigned ch)
 static struct samsung_dma_ops s3c_dma_ops = {
         .request        = s3c_dma_request,
         .release        = s3c_dma_release,
+        .config         = s3c_dma_config,
         .prepare        = s3c_dma_prepare,
         .trigger        = s3c_dma_trigger,
         .started        = s3c_dma_started,
diff --git a/arch/arm/plat-samsung/s5p-clock.c b/arch/arm/plat-samsung/s5p-clock.c
index 031a61899bef..48a159911037 100644
--- a/arch/arm/plat-samsung/s5p-clock.c
+++ b/arch/arm/plat-samsung/s5p-clock.c
@@ -37,6 +37,7 @@ struct clk clk_ext_xtal_mux = {
 struct clk clk_xusbxti = {
         .name           = "xusbxti",
         .id             = -1,
+        .rate           = 24000000,
 };
 
 struct clk s5p_clk_27m = {
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig
index 81ee7cc34457..8d5c10a5084d 100644
--- a/arch/arm/plat-versatile/Kconfig
+++ b/arch/arm/plat-versatile/Kconfig
@@ -1,5 +1,8 @@
 if PLAT_VERSATILE
 
+config PLAT_VERSATILE_CLOCK
+        bool
+
 config PLAT_VERSATILE_CLCD
         bool
 
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile
index a5cb1945bdcc..272769a8a7d6 100644
--- a/arch/arm/plat-versatile/Makefile
+++ b/arch/arm/plat-versatile/Makefile
@@ -1,4 +1,4 @@
-obj-y   := clock.o
+obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
 obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
 obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
 obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o