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-rw-r--r--arch/arm/Kconfig77
-rw-r--r--arch/arm/Makefile7
-rw-r--r--arch/arm/boot/compressed/head.S4
-rw-r--r--arch/arm/common/Makefile1
-rw-r--r--arch/arm/common/dmabounce.c3
-rw-r--r--arch/arm/common/rtctime.c434
-rw-r--r--arch/arm/configs/at91cap9adk_defconfig82
-rw-r--r--arch/arm/configs/at91rm9200dk_defconfig1
-rw-r--r--arch/arm/configs/at91rm9200ek_defconfig1
-rw-r--r--arch/arm/configs/at91sam9260ek_defconfig1
-rw-r--r--arch/arm/configs/at91sam9261ek_defconfig1
-rw-r--r--arch/arm/configs/at91sam9263ek_defconfig1
-rw-r--r--arch/arm/configs/at91sam9g20ek_defconfig1168
-rw-r--r--arch/arm/configs/at91sam9rlek_defconfig1
-rw-r--r--arch/arm/configs/ateb9200_defconfig1
-rw-r--r--arch/arm/configs/cm_x270_defconfig1
-rw-r--r--arch/arm/configs/collie_defconfig1
-rw-r--r--arch/arm/configs/corgi_defconfig1
-rw-r--r--arch/arm/configs/ecbat91_defconfig1
-rw-r--r--arch/arm/configs/em_x270_defconfig1
-rw-r--r--arch/arm/configs/ep93xx_defconfig1
-rw-r--r--arch/arm/configs/eseries_pxa_defconfig1
-rw-r--r--arch/arm/configs/iop13xx_defconfig1
-rw-r--r--arch/arm/configs/iop32x_defconfig1
-rw-r--r--arch/arm/configs/iop33x_defconfig1
-rw-r--r--arch/arm/configs/ixp2000_defconfig1
-rw-r--r--arch/arm/configs/ixp23xx_defconfig1
-rw-r--r--arch/arm/configs/ixp4xx_defconfig9
-rw-r--r--arch/arm/configs/kafa_defconfig1
-rw-r--r--arch/arm/configs/kb9202_defconfig1
-rw-r--r--arch/arm/configs/kirkwood_defconfig1426
-rw-r--r--arch/arm/configs/ks8695_defconfig1
-rw-r--r--arch/arm/configs/loki_defconfig1147
-rw-r--r--arch/arm/configs/lpd270_defconfig1
-rw-r--r--arch/arm/configs/lpd7a404_defconfig1
-rw-r--r--arch/arm/configs/mv78xx0_defconfig1445
-rw-r--r--arch/arm/configs/netx_defconfig1
-rw-r--r--arch/arm/configs/onearm_defconfig1
-rw-r--r--arch/arm/configs/orion5x_defconfig319
-rw-r--r--arch/arm/configs/picotux200_defconfig1
-rw-r--r--arch/arm/configs/pnx4008_defconfig1
-rw-r--r--arch/arm/configs/qil-a9260_defconfig1256
-rw-r--r--arch/arm/configs/realview-smp_defconfig1
-rw-r--r--arch/arm/configs/realview_defconfig1
-rw-r--r--arch/arm/configs/rpc_defconfig1
-rw-r--r--arch/arm/configs/s3c2410_defconfig1043
-rw-r--r--arch/arm/configs/sam9_l9260_defconfig1
-rw-r--r--arch/arm/configs/spitz_defconfig1
-rw-r--r--arch/arm/configs/tct_hammer_defconfig1
-rw-r--r--arch/arm/configs/trizeps4_defconfig1
-rw-r--r--arch/arm/configs/usb-a9260_defconfig1142
-rw-r--r--arch/arm/configs/usb-a9263_defconfig1134
-rw-r--r--arch/arm/configs/versatile_defconfig1
-rw-r--r--arch/arm/kernel/atags.c83
-rw-r--r--arch/arm/kernel/ecard.c13
-rw-r--r--arch/arm/kernel/ecard.h13
-rw-r--r--arch/arm/kernel/process.c4
-rw-r--r--arch/arm/kernel/stacktrace.c34
-rw-r--r--arch/arm/kernel/time.c120
-rw-r--r--arch/arm/lib/copy_template.S12
-rw-r--r--arch/arm/lib/memmove.S14
-rw-r--r--arch/arm/lib/memset.S46
-rw-r--r--arch/arm/lib/memzero.S44
-rw-r--r--arch/arm/mach-at91/Kconfig56
-rw-r--r--arch/arm/mach-at91/Makefile8
-rw-r--r--arch/arm/mach-at91/at91cap9_devices.c99
-rw-r--r--arch/arm/mach-at91/at91sam9260.c16
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c44
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c12
-rw-r--r--arch/arm/mach-at91/at91sam9263_devices.c4
-rw-r--r--arch/arm/mach-at91/at91sam9rl_devices.c107
-rw-r--r--arch/arm/mach-at91/board-cap9adk.c9
-rw-r--r--arch/arm/mach-at91/board-carmeva.c23
-rw-r--r--arch/arm/mach-at91/board-csb637.c4
-rw-r--r--arch/arm/mach-at91/board-dk.c25
-rw-r--r--arch/arm/mach-at91/board-eb9200.c26
-rw-r--r--arch/arm/mach-at91/board-ek.c25
-rw-r--r--arch/arm/mach-at91/board-kb9202.c29
-rw-r--r--arch/arm/mach-at91/board-qil-a9260.c255
-rw-r--r--arch/arm/mach-at91/board-sam9g20ek.c218
-rw-r--r--arch/arm/mach-at91/board-sam9rlek.c10
-rw-r--r--arch/arm/mach-at91/board-usb-a9260.c215
-rw-r--r--arch/arm/mach-at91/board-usb-a9263.c230
-rwxr-xr-xarch/arm/mach-at91/board-yl-9200.c853
-rw-r--r--arch/arm/mach-at91/clock.c64
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mach-ep93xx/clock.c5
-rw-r--r--arch/arm/mach-footbridge/Makefile2
-rw-r--r--arch/arm/mach-footbridge/co285.c39
-rw-r--r--arch/arm/mach-footbridge/common.c21
-rw-r--r--arch/arm/mach-footbridge/ebsa285-leds.c2
-rw-r--r--arch/arm/mach-footbridge/time.c3
-rw-r--r--arch/arm/mach-imx/dma.c13
-rw-r--r--arch/arm/mach-integrator/Makefile2
-rw-r--r--arch/arm/mach-integrator/time.c223
-rw-r--r--arch/arm/mach-ixp4xx/Kconfig9
-rw-r--r--arch/arm/mach-ixp4xx/Makefile2
-rw-r--r--arch/arm/mach-ixp4xx/fsg-pci.c71
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c276
-rw-r--r--arch/arm/mach-kirkwood/Kconfig25
-rw-r--r--arch/arm/mach-kirkwood/Makefile5
-rw-r--r--arch/arm/mach-kirkwood/Makefile.boot3
-rw-r--r--arch/arm/mach-kirkwood/addr-map.c139
-rw-r--r--arch/arm/mach-kirkwood/common.c331
-rw-r--r--arch/arm/mach-kirkwood/common.h42
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c68
-rw-r--r--arch/arm/mach-kirkwood/irq.c22
-rw-r--r--arch/arm/mach-kirkwood/pcie.c180
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c69
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c113
-rw-r--r--arch/arm/mach-loki/Kconfig13
-rw-r--r--arch/arm/mach-loki/Makefile3
-rw-r--r--arch/arm/mach-loki/Makefile.boot3
-rw-r--r--arch/arm/mach-loki/addr-map.c121
-rw-r--r--arch/arm/mach-loki/common.c305
-rw-r--r--arch/arm/mach-loki/common.h36
-rw-r--r--arch/arm/mach-loki/irq.c21
-rw-r--r--arch/arm/mach-loki/lb88rc8480-setup.c100
-rw-r--r--arch/arm/mach-mv78xx0/Kconfig13
-rw-r--r--arch/arm/mach-mv78xx0/Makefile2
-rw-r--r--arch/arm/mach-mv78xx0/Makefile.boot3
-rw-r--r--arch/arm/mach-mv78xx0/addr-map.c156
-rw-r--r--arch/arm/mach-mv78xx0/common.c754
-rw-r--r--arch/arm/mach-mv78xx0/common.h49
-rw-r--r--arch/arm/mach-mv78xx0/db78x00-bp-setup.c94
-rw-r--r--arch/arm/mach-mv78xx0/irq.c22
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c312
-rw-r--r--arch/arm/mach-omap1/Makefile4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c17
-rw-r--r--arch/arm/mach-omap1/board-osk.c18
-rw-r--r--arch/arm/mach-omap1/fpga.c10
-rw-r--r--arch/arm/mach-omap1/mcbsp.c280
-rw-r--r--arch/arm/mach-omap1/pm.c7
-rw-r--r--arch/arm/mach-omap1/sram.S (renamed from arch/arm/plat-omap/sram-fn.S)6
-rw-r--r--arch/arm/mach-omap2/Makefile8
-rw-r--r--arch/arm/mach-omap2/clock.c201
-rw-r--r--arch/arm/mach-omap2/clock.h6
-rw-r--r--arch/arm/mach-omap2/clock24xx.c12
-rw-r--r--arch/arm/mach-omap2/clock24xx.h47
-rw-r--r--arch/arm/mach-omap2/clock34xx.c299
-rw-r--r--arch/arm/mach-omap2/clock34xx.h147
-rw-r--r--arch/arm/mach-omap2/cm-regbits-34xx.h18
-rw-r--r--arch/arm/mach-omap2/cm.h15
-rw-r--r--arch/arm/mach-omap2/control.c24
-rw-r--r--arch/arm/mach-omap2/gpmc.c2
-rw-r--r--arch/arm/mach-omap2/id.c195
-rw-r--r--arch/arm/mach-omap2/mcbsp.c208
-rw-r--r--arch/arm/mach-omap2/memory.c11
-rw-r--r--arch/arm/mach-omap2/mux.c2
-rw-r--r--arch/arm/mach-omap2/pm.c7
-rw-r--r--arch/arm/mach-omap2/prcm-common.h1
-rw-r--r--arch/arm/mach-omap2/prcm.c98
-rw-r--r--arch/arm/mach-omap2/prm.h30
-rw-r--r--arch/arm/mach-omap2/sdrc.h10
-rw-r--r--arch/arm/mach-omap2/sram242x.S (renamed from arch/arm/mach-omap2/sram-fn.S)105
-rw-r--r--arch/arm/mach-omap2/sram243x.S321
-rw-r--r--arch/arm/mach-omap2/timer-gp.c9
-rw-r--r--arch/arm/mach-orion5x/Kconfig48
-rw-r--r--arch/arm/mach-orion5x/Makefile12
-rw-r--r--arch/arm/mach-orion5x/addr-map.c45
-rw-r--r--arch/arm/mach-orion5x/common.c307
-rw-r--r--arch/arm/mach-orion5x/common.h38
-rw-r--r--arch/arm/mach-orion5x/db88f5281-setup.c82
-rw-r--r--arch/arm/mach-orion5x/dns323-setup.c125
-rw-r--r--arch/arm/mach-orion5x/gpio.c47
-rw-r--r--arch/arm/mach-orion5x/irq.c18
-rw-r--r--arch/arm/mach-orion5x/kurobox_pro-setup.c224
-rw-r--r--arch/arm/mach-orion5x/mpp.c163
-rw-r--r--arch/arm/mach-orion5x/mpp.h74
-rw-r--r--arch/arm/mach-orion5x/mss2-setup.c270
-rw-r--r--arch/arm/mach-orion5x/mv2120-setup.c239
-rw-r--r--arch/arm/mach-orion5x/pci.c86
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c161
-rw-r--r--arch/arm/mach-orion5x/rd88f5181l-ge-setup.c172
-rw-r--r--arch/arm/mach-orion5x/rd88f5182-setup.c79
-rw-r--r--arch/arm/mach-orion5x/ts209-setup.c299
-rw-r--r--arch/arm/mach-orion5x/ts409-setup.c273
-rw-r--r--arch/arm/mach-orion5x/ts78xx-setup.c277
-rw-r--r--arch/arm/mach-orion5x/tsx09-common.c133
-rw-r--r--arch/arm/mach-orion5x/tsx09-common.h20
-rw-r--r--arch/arm/mach-orion5x/wnr854t-setup.c164
-rw-r--r--arch/arm/mach-orion5x/wrt350n-v2-setup.c173
-rw-r--r--arch/arm/mach-realview/platsmp.c2
-rw-r--r--arch/arm/mach-s3c2410/Kconfig21
-rw-r--r--arch/arm/mach-s3c2410/Makefile8
-rw-r--r--arch/arm/mach-s3c2410/bast-ide.c112
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c59
-rw-r--r--arch/arm/mach-s3c2410/mach-n30.c474
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c72
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.c86
-rw-r--r--arch/arm/mach-s3c2410/nor-simtec.h14
-rw-r--r--arch/arm/mach-s3c2412/Kconfig10
-rw-r--r--arch/arm/mach-s3c2412/Makefile1
-rw-r--r--arch/arm/mach-s3c2412/clock.c13
-rw-r--r--arch/arm/mach-s3c2412/mach-jive.c687
-rw-r--r--arch/arm/mach-s3c2440/Kconfig6
-rw-r--r--arch/arm/mach-s3c2440/Makefile1
-rw-r--r--arch/arm/mach-s3c2440/mach-anubis.c41
-rw-r--r--arch/arm/mach-s3c2440/mach-at2440evb.c198
-rw-r--r--arch/arm/mach-s3c2440/mach-osiris.c15
-rw-r--r--arch/arm/mach-s3c2443/clock.c91
-rw-r--r--arch/arm/mm/Kconfig21
-rw-r--r--arch/arm/mm/Makefile2
-rw-r--r--arch/arm/mm/cache-feroceon-l2.c318
-rw-r--r--arch/arm/mm/fault-armv.c4
-rw-r--r--arch/arm/mm/flush.c2
-rw-r--r--arch/arm/mm/proc-feroceon.S242
-rw-r--r--arch/arm/plat-omap/Makefile2
-rw-r--r--arch/arm/plat-omap/clock.c128
-rw-r--r--arch/arm/plat-omap/common.c59
-rw-r--r--arch/arm/plat-omap/devices.c48
-rw-r--r--arch/arm/plat-omap/dma.c766
-rw-r--r--arch/arm/plat-omap/dmtimer.c212
-rw-r--r--arch/arm/plat-omap/mcbsp.c767
-rw-r--r--arch/arm/plat-omap/sram.c211
-rw-r--r--arch/arm/plat-omap/usb.c131
-rw-r--r--arch/arm/plat-orion/irq.c3
-rw-r--r--arch/arm/plat-orion/pcie.c6
-rw-r--r--arch/arm/plat-orion/time.c6
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig8
-rw-r--r--arch/arm/plat-s3c24xx/Makefile3
-rw-r--r--arch/arm/plat-s3c24xx/devs.c100
-rw-r--r--arch/arm/plat-s3c24xx/gpiolib.c259
-rw-r--r--arch/arm/plat-s3c24xx/pwm-clock.c437
-rw-r--r--arch/arm/plat-s3c24xx/pwm.c402
-rw-r--r--arch/arm/tools/mach-types126
226 files changed, 24786 insertions, 4157 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 63ef7cf852a7..b92925c70172 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -84,6 +84,11 @@ config STACKTRACE_SUPPORT
84 bool 84 bool
85 default y 85 default y
86 86
87config HAVE_LATENCYTOP_SUPPORT
88 bool
89 depends on !SMP
90 default y
91
87config LOCKDEP_SUPPORT 92config LOCKDEP_SUPPORT
88 bool 93 bool
89 default y 94 default y
@@ -147,6 +152,10 @@ config FIQ
147config ARCH_MTD_XIP 152config ARCH_MTD_XIP
148 bool 153 bool
149 154
155config GENERIC_HARDIRQS_NO__DO_IRQ
156 bool
157 def_bool y
158
150if OPROFILE 159if OPROFILE
151 160
152config OPROFILE_ARMV6 161config OPROFILE_ARMV6
@@ -232,13 +241,6 @@ config ARCH_CLPS711X
232 help 241 help
233 Support for Cirrus Logic 711x/721x based boards. 242 Support for Cirrus Logic 711x/721x based boards.
234 243
235config ARCH_CO285
236 bool "Co-EBSA285"
237 select FOOTBRIDGE
238 select FOOTBRIDGE_ADDIN
239 help
240 Support for Intel's EBSA285 companion chip.
241
242config ARCH_EBSA110 244config ARCH_EBSA110
243 bool "EBSA-110" 245 bool "EBSA-110"
244 select ISA 246 select ISA
@@ -351,6 +353,16 @@ config ARCH_L7200
351 If you have any questions or comments about the Linux kernel port 353 If you have any questions or comments about the Linux kernel port
352 to this board, send e-mail to <sjhill@cotw.com>. 354 to this board, send e-mail to <sjhill@cotw.com>.
353 355
356config ARCH_KIRKWOOD
357 bool "Marvell Kirkwood"
358 select PCI
359 select GENERIC_TIME
360 select GENERIC_CLOCKEVENTS
361 select PLAT_ORION
362 help
363 Support for the following Marvell Kirkwood series SoCs:
364 88F6180, 88F6192 and 88F6281.
365
354config ARCH_KS8695 366config ARCH_KS8695
355 bool "Micrel/Kendin KS8695" 367 bool "Micrel/Kendin KS8695"
356 select GENERIC_GPIO 368 select GENERIC_GPIO
@@ -369,6 +381,24 @@ config ARCH_NS9XXX
369 381
370 <http://www.digi.com/products/microprocessors/index.jsp> 382 <http://www.digi.com/products/microprocessors/index.jsp>
371 383
384config ARCH_LOKI
385 bool "Marvell Loki (88RC8480)"
386 select GENERIC_TIME
387 select GENERIC_CLOCKEVENTS
388 select PLAT_ORION
389 help
390 Support for the Marvell Loki (88RC8480) SoC.
391
392config ARCH_MV78XX0
393 bool "Marvell MV78xx0"
394 select PCI
395 select GENERIC_TIME
396 select GENERIC_CLOCKEVENTS
397 select PLAT_ORION
398 help
399 Support for the following Marvell MV78xx0 series SoCs:
400 MV781x0, MV782x0.
401
372config ARCH_MXC 402config ARCH_MXC
373 bool "Freescale MXC/iMX-based" 403 bool "Freescale MXC/iMX-based"
374 select ARCH_MTD_XIP 404 select ARCH_MTD_XIP
@@ -385,7 +415,8 @@ config ARCH_ORION5X
385 select PLAT_ORION 415 select PLAT_ORION
386 help 416 help
387 Support for the following Marvell Orion 5x series SoCs: 417 Support for the following Marvell Orion 5x series SoCs:
388 Orion-1 (5181), Orion-NAS (5182), Orion-2 (5281.) 418 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
419 Orion-2 (5281).
389 420
390config ARCH_PNX4008 421config ARCH_PNX4008
391 bool "Philips Nexperia PNX4008 Mobile" 422 bool "Philips Nexperia PNX4008 Mobile"
@@ -410,6 +441,7 @@ config ARCH_RPC
410 select FIQ 441 select FIQ
411 select TIMER_ACORN 442 select TIMER_ACORN
412 select ARCH_MAY_HAVE_PC_FDC 443 select ARCH_MAY_HAVE_PC_FDC
444 select HAVE_PATA_PLATFORM
413 select ISA_DMA_API 445 select ISA_DMA_API
414 select NO_IOPORT 446 select NO_IOPORT
415 help 447 help
@@ -506,6 +538,10 @@ source "arch/arm/mach-ixp2000/Kconfig"
506 538
507source "arch/arm/mach-ixp23xx/Kconfig" 539source "arch/arm/mach-ixp23xx/Kconfig"
508 540
541source "arch/arm/mach-loki/Kconfig"
542
543source "arch/arm/mach-mv78xx0/Kconfig"
544
509source "arch/arm/mach-pxa/Kconfig" 545source "arch/arm/mach-pxa/Kconfig"
510 546
511source "arch/arm/mach-sa1100/Kconfig" 547source "arch/arm/mach-sa1100/Kconfig"
@@ -518,6 +554,8 @@ source "arch/arm/mach-omap2/Kconfig"
518 554
519source "arch/arm/mach-orion5x/Kconfig" 555source "arch/arm/mach-orion5x/Kconfig"
520 556
557source "arch/arm/mach-kirkwood/Kconfig"
558
521source "arch/arm/plat-s3c24xx/Kconfig" 559source "arch/arm/plat-s3c24xx/Kconfig"
522source "arch/arm/plat-s3c/Kconfig" 560source "arch/arm/plat-s3c/Kconfig"
523 561
@@ -707,27 +745,6 @@ config PREEMPT
707 Say Y here if you are building a kernel for a desktop, embedded 745 Say Y here if you are building a kernel for a desktop, embedded
708 or real-time system. Say N if you are unsure. 746 or real-time system. Say N if you are unsure.
709 747
710config NO_IDLE_HZ
711 bool "Dynamic tick timer"
712 depends on !GENERIC_CLOCKEVENTS
713 help
714 Select this option if you want to disable continuous timer ticks
715 and have them programmed to occur as required. This option saves
716 power as the system can remain in idle state for longer.
717
718 By default dynamic tick is disabled during the boot, and can be
719 manually enabled with:
720
721 echo 1 > /sys/devices/system/timer/timer0/dyn_tick
722
723 Alternatively, if you want dynamic tick automatically enabled
724 during boot, pass "dyntick=enable" via the kernel command string.
725
726 Please note that dynamic tick may affect the accuracy of
727 timekeeping on some platforms depending on the implementation.
728 Currently at least OMAP, PXA2xx and SA11x0 platforms are known
729 to have accurate timekeeping with dynamic tick.
730
731config HZ 748config HZ
732 int 749 int
733 default 128 if ARCH_L7200 750 default 128 if ARCH_L7200
@@ -793,7 +810,7 @@ source "mm/Kconfig"
793 810
794config LEDS 811config LEDS
795 bool "Timer and CPU usage LEDs" 812 bool "Timer and CPU usage LEDs"
796 depends on ARCH_CDB89712 || ARCH_CO285 || ARCH_EBSA110 || \ 813 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
797 ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \ 814 ARCH_EBSA285 || ARCH_IMX || ARCH_INTEGRATOR || \
798 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \ 815 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
799 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \ 816 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e72db27e0ba0..91fac81833e8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -100,8 +100,6 @@ textofs-y := 0x00008000
100 incdir-$(CONFIG_ARCH_CLPS7500) := cl7500 100 incdir-$(CONFIG_ARCH_CLPS7500) := cl7500
101 machine-$(CONFIG_FOOTBRIDGE) := footbridge 101 machine-$(CONFIG_FOOTBRIDGE) := footbridge
102 incdir-$(CONFIG_FOOTBRIDGE) := ebsa285 102 incdir-$(CONFIG_FOOTBRIDGE) := ebsa285
103 machine-$(CONFIG_ARCH_CO285) := footbridge
104 incdir-$(CONFIG_ARCH_CO285) := ebsa285
105 machine-$(CONFIG_ARCH_SHARK) := shark 103 machine-$(CONFIG_ARCH_SHARK) := shark
106 machine-$(CONFIG_ARCH_SA1100) := sa1100 104 machine-$(CONFIG_ARCH_SA1100) := sa1100
107ifeq ($(CONFIG_ARCH_SA1100),y) 105ifeq ($(CONFIG_ARCH_SA1100),y)
@@ -135,11 +133,14 @@ endif
135 machine-$(CONFIG_ARCH_NETX) := netx 133 machine-$(CONFIG_ARCH_NETX) := netx
136 machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx 134 machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
137 machine-$(CONFIG_ARCH_DAVINCI) := davinci 135 machine-$(CONFIG_ARCH_DAVINCI) := davinci
136 machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
138 machine-$(CONFIG_ARCH_KS8695) := ks8695 137 machine-$(CONFIG_ARCH_KS8695) := ks8695
139 incdir-$(CONFIG_ARCH_MXC) := mxc 138 incdir-$(CONFIG_ARCH_MXC) := mxc
140 machine-$(CONFIG_ARCH_MX3) := mx3 139 machine-$(CONFIG_ARCH_MX3) := mx3
141 machine-$(CONFIG_ARCH_ORION5X) := orion5x 140 machine-$(CONFIG_ARCH_ORION5X) := orion5x
142 machine-$(CONFIG_ARCH_MSM7X00A) := msm 141 machine-$(CONFIG_ARCH_MSM7X00A) := msm
142 machine-$(CONFIG_ARCH_LOKI) := loki
143 machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
143 144
144ifeq ($(CONFIG_ARCH_EBSA110),y) 145ifeq ($(CONFIG_ARCH_EBSA110),y)
145# This is what happens if you forget the IOCS16 line. 146# This is what happens if you forget the IOCS16 line.
@@ -190,8 +191,6 @@ core-$(CONFIG_PLAT_S3C24XX) += arch/arm/plat-s3c24xx/
190core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/ 191core-$(CONFIG_ARCH_MXC) += arch/arm/plat-mxc/
191 192
192drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/ 193drivers-$(CONFIG_OPROFILE) += arch/arm/oprofile/
193drivers-$(CONFIG_ARCH_CLPS7500) += drivers/acorn/char/
194drivers-$(CONFIG_ARCH_L7200) += drivers/acorn/char/
195 194
196libs-y := arch/arm/lib/ $(libs-y) 195libs-y := arch/arm/lib/ $(libs-y)
197 196
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 3c2c8f2a1dc4..de41daeab5e9 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -623,8 +623,8 @@ proc_types:
623 b __armv4_mmu_cache_off 623 b __armv4_mmu_cache_off
624 b __armv4_mmu_cache_flush 624 b __armv4_mmu_cache_flush
625 625
626 .word 0x56055310 @ Feroceon 626 .word 0x56050000 @ Feroceon
627 .word 0xfffffff0 627 .word 0xff0f0000
628 b __armv4_mmu_cache_on 628 b __armv4_mmu_cache_on
629 b __armv4_mmu_cache_off 629 b __armv4_mmu_cache_off
630 b __armv5tej_mmu_cache_flush 630 b __armv5tej_mmu_cache_flush
diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
index 3d0b9fa42f84..325e4b6a6afb 100644
--- a/arch/arm/common/Makefile
+++ b/arch/arm/common/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the linux kernel. 2# Makefile for the linux kernel.
3# 3#
4 4
5obj-y += rtctime.o
6obj-$(CONFIG_ARM_GIC) += gic.o 5obj-$(CONFIG_ARM_GIC) += gic.o
7obj-$(CONFIG_ARM_VIC) += vic.o 6obj-$(CONFIG_ARM_VIC) += vic.o
8obj-$(CONFIG_ICST525) += icst525.o 7obj-$(CONFIG_ICST525) += icst525.o
diff --git a/arch/arm/common/dmabounce.c b/arch/arm/common/dmabounce.c
index 52fc6a883281..2744673314b4 100644
--- a/arch/arm/common/dmabounce.c
+++ b/arch/arm/common/dmabounce.c
@@ -650,7 +650,8 @@ EXPORT_SYMBOL(dma_map_sg);
650EXPORT_SYMBOL(dma_unmap_sg); 650EXPORT_SYMBOL(dma_unmap_sg);
651EXPORT_SYMBOL(dma_sync_single_for_cpu); 651EXPORT_SYMBOL(dma_sync_single_for_cpu);
652EXPORT_SYMBOL(dma_sync_single_for_device); 652EXPORT_SYMBOL(dma_sync_single_for_device);
653EXPORT_SYMBOL(dma_sync_sg); 653EXPORT_SYMBOL(dma_sync_sg_for_cpu);
654EXPORT_SYMBOL(dma_sync_sg_for_device);
654EXPORT_SYMBOL(dmabounce_register_dev); 655EXPORT_SYMBOL(dmabounce_register_dev);
655EXPORT_SYMBOL(dmabounce_unregister_dev); 656EXPORT_SYMBOL(dmabounce_unregister_dev);
656 657
diff --git a/arch/arm/common/rtctime.c b/arch/arm/common/rtctime.c
deleted file mode 100644
index aa8f7739c822..000000000000
--- a/arch/arm/common/rtctime.c
+++ /dev/null
@@ -1,434 +0,0 @@
1/*
2 * linux/arch/arm/common/rtctime.c
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd.
5 * Based on sa1100-rtc.c, Nils Faerber, CIH, Nicolas Pitre.
6 * Based on rtc.c by Paul Gortmaker
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/time.h>
15#include <linux/rtc.h>
16#include <linux/poll.h>
17#include <linux/proc_fs.h>
18#include <linux/miscdevice.h>
19#include <linux/spinlock.h>
20#include <linux/capability.h>
21#include <linux/device.h>
22#include <linux/mutex.h>
23
24#include <asm/rtc.h>
25
26static DECLARE_WAIT_QUEUE_HEAD(rtc_wait);
27static struct fasync_struct *rtc_async_queue;
28
29/*
30 * rtc_lock protects rtc_irq_data
31 */
32static DEFINE_SPINLOCK(rtc_lock);
33static unsigned long rtc_irq_data;
34
35/*
36 * rtc_sem protects rtc_inuse and rtc_ops
37 */
38static DEFINE_MUTEX(rtc_mutex);
39static unsigned long rtc_inuse;
40static struct rtc_ops *rtc_ops;
41
42#define rtc_epoch 1900UL
43
44/*
45 * Calculate the next alarm time given the requested alarm time mask
46 * and the current time.
47 */
48void rtc_next_alarm_time(struct rtc_time *next, struct rtc_time *now, struct rtc_time *alrm)
49{
50 unsigned long next_time;
51 unsigned long now_time;
52
53 next->tm_year = now->tm_year;
54 next->tm_mon = now->tm_mon;
55 next->tm_mday = now->tm_mday;
56 next->tm_hour = alrm->tm_hour;
57 next->tm_min = alrm->tm_min;
58 next->tm_sec = alrm->tm_sec;
59
60 rtc_tm_to_time(now, &now_time);
61 rtc_tm_to_time(next, &next_time);
62
63 if (next_time < now_time) {
64 /* Advance one day */
65 next_time += 60 * 60 * 24;
66 rtc_time_to_tm(next_time, next);
67 }
68}
69EXPORT_SYMBOL(rtc_next_alarm_time);
70
71static inline int rtc_arm_read_time(struct rtc_ops *ops, struct rtc_time *tm)
72{
73 memset(tm, 0, sizeof(struct rtc_time));
74 return ops->read_time(tm);
75}
76
77static inline int rtc_arm_set_time(struct rtc_ops *ops, struct rtc_time *tm)
78{
79 int ret;
80
81 ret = rtc_valid_tm(tm);
82 if (ret == 0)
83 ret = ops->set_time(tm);
84
85 return ret;
86}
87
88static inline int rtc_arm_read_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
89{
90 int ret = -EINVAL;
91 if (ops->read_alarm) {
92 memset(alrm, 0, sizeof(struct rtc_wkalrm));
93 ret = ops->read_alarm(alrm);
94 }
95 return ret;
96}
97
98static inline int rtc_arm_set_alarm(struct rtc_ops *ops, struct rtc_wkalrm *alrm)
99{
100 int ret = -EINVAL;
101 if (ops->set_alarm)
102 ret = ops->set_alarm(alrm);
103 return ret;
104}
105
106void rtc_update(unsigned long num, unsigned long events)
107{
108 spin_lock(&rtc_lock);
109 rtc_irq_data = (rtc_irq_data + (num << 8)) | events;
110 spin_unlock(&rtc_lock);
111
112 wake_up_interruptible(&rtc_wait);
113 kill_fasync(&rtc_async_queue, SIGIO, POLL_IN);
114}
115EXPORT_SYMBOL(rtc_update);
116
117
118static ssize_t
119rtc_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
120{
121 DECLARE_WAITQUEUE(wait, current);
122 unsigned long data;
123 ssize_t ret;
124
125 if (count < sizeof(unsigned long))
126 return -EINVAL;
127
128 add_wait_queue(&rtc_wait, &wait);
129 do {
130 __set_current_state(TASK_INTERRUPTIBLE);
131
132 spin_lock_irq(&rtc_lock);
133 data = rtc_irq_data;
134 rtc_irq_data = 0;
135 spin_unlock_irq(&rtc_lock);
136
137 if (data != 0) {
138 ret = 0;
139 break;
140 }
141 if (file->f_flags & O_NONBLOCK) {
142 ret = -EAGAIN;
143 break;
144 }
145 if (signal_pending(current)) {
146 ret = -ERESTARTSYS;
147 break;
148 }
149 schedule();
150 } while (1);
151 set_current_state(TASK_RUNNING);
152 remove_wait_queue(&rtc_wait, &wait);
153
154 if (ret == 0) {
155 ret = put_user(data, (unsigned long __user *)buf);
156 if (ret == 0)
157 ret = sizeof(unsigned long);
158 }
159 return ret;
160}
161
162static unsigned int rtc_poll(struct file *file, poll_table *wait)
163{
164 unsigned long data;
165
166 poll_wait(file, &rtc_wait, wait);
167
168 spin_lock_irq(&rtc_lock);
169 data = rtc_irq_data;
170 spin_unlock_irq(&rtc_lock);
171
172 return data != 0 ? POLLIN | POLLRDNORM : 0;
173}
174
175static int rtc_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
176 unsigned long arg)
177{
178 struct rtc_ops *ops = file->private_data;
179 struct rtc_time tm;
180 struct rtc_wkalrm alrm;
181 void __user *uarg = (void __user *)arg;
182 int ret = -EINVAL;
183
184 switch (cmd) {
185 case RTC_ALM_READ:
186 ret = rtc_arm_read_alarm(ops, &alrm);
187 if (ret)
188 break;
189 ret = copy_to_user(uarg, &alrm.time, sizeof(tm));
190 if (ret)
191 ret = -EFAULT;
192 break;
193
194 case RTC_ALM_SET:
195 ret = copy_from_user(&alrm.time, uarg, sizeof(tm));
196 if (ret) {
197 ret = -EFAULT;
198 break;
199 }
200 alrm.enabled = 0;
201 alrm.pending = 0;
202 alrm.time.tm_mday = -1;
203 alrm.time.tm_mon = -1;
204 alrm.time.tm_year = -1;
205 alrm.time.tm_wday = -1;
206 alrm.time.tm_yday = -1;
207 alrm.time.tm_isdst = -1;
208 ret = rtc_arm_set_alarm(ops, &alrm);
209 break;
210
211 case RTC_RD_TIME:
212 ret = rtc_arm_read_time(ops, &tm);
213 if (ret)
214 break;
215 ret = copy_to_user(uarg, &tm, sizeof(tm));
216 if (ret)
217 ret = -EFAULT;
218 break;
219
220 case RTC_SET_TIME:
221 if (!capable(CAP_SYS_TIME)) {
222 ret = -EACCES;
223 break;
224 }
225 ret = copy_from_user(&tm, uarg, sizeof(tm));
226 if (ret) {
227 ret = -EFAULT;
228 break;
229 }
230 ret = rtc_arm_set_time(ops, &tm);
231 break;
232
233 case RTC_EPOCH_SET:
234#ifndef rtc_epoch
235 /*
236 * There were no RTC clocks before 1900.
237 */
238 if (arg < 1900) {
239 ret = -EINVAL;
240 break;
241 }
242 if (!capable(CAP_SYS_TIME)) {
243 ret = -EACCES;
244 break;
245 }
246 rtc_epoch = arg;
247 ret = 0;
248#endif
249 break;
250
251 case RTC_EPOCH_READ:
252 ret = put_user(rtc_epoch, (unsigned long __user *)uarg);
253 break;
254
255 case RTC_WKALM_SET:
256 ret = copy_from_user(&alrm, uarg, sizeof(alrm));
257 if (ret) {
258 ret = -EFAULT;
259 break;
260 }
261 ret = rtc_arm_set_alarm(ops, &alrm);
262 break;
263
264 case RTC_WKALM_RD:
265 ret = rtc_arm_read_alarm(ops, &alrm);
266 if (ret)
267 break;
268 ret = copy_to_user(uarg, &alrm, sizeof(alrm));
269 if (ret)
270 ret = -EFAULT;
271 break;
272
273 default:
274 if (ops->ioctl)
275 ret = ops->ioctl(cmd, arg);
276 break;
277 }
278 return ret;
279}
280
281static int rtc_open(struct inode *inode, struct file *file)
282{
283 int ret;
284
285 mutex_lock(&rtc_mutex);
286
287 if (rtc_inuse) {
288 ret = -EBUSY;
289 } else if (!rtc_ops || !try_module_get(rtc_ops->owner)) {
290 ret = -ENODEV;
291 } else {
292 file->private_data = rtc_ops;
293
294 ret = rtc_ops->open ? rtc_ops->open() : 0;
295 if (ret == 0) {
296 spin_lock_irq(&rtc_lock);
297 rtc_irq_data = 0;
298 spin_unlock_irq(&rtc_lock);
299
300 rtc_inuse = 1;
301 }
302 }
303 mutex_unlock(&rtc_mutex);
304
305 return ret;
306}
307
308static int rtc_release(struct inode *inode, struct file *file)
309{
310 struct rtc_ops *ops = file->private_data;
311
312 if (ops->release)
313 ops->release();
314
315 spin_lock_irq(&rtc_lock);
316 rtc_irq_data = 0;
317 spin_unlock_irq(&rtc_lock);
318
319 module_put(rtc_ops->owner);
320 rtc_inuse = 0;
321
322 return 0;
323}
324
325static int rtc_fasync(int fd, struct file *file, int on)
326{
327 return fasync_helper(fd, file, on, &rtc_async_queue);
328}
329
330static const struct file_operations rtc_fops = {
331 .owner = THIS_MODULE,
332 .llseek = no_llseek,
333 .read = rtc_read,
334 .poll = rtc_poll,
335 .ioctl = rtc_ioctl,
336 .open = rtc_open,
337 .release = rtc_release,
338 .fasync = rtc_fasync,
339};
340
341static struct miscdevice rtc_miscdev = {
342 .minor = RTC_MINOR,
343 .name = "rtc",
344 .fops = &rtc_fops,
345};
346
347
348static int rtc_read_proc(char *page, char **start, off_t off, int count, int *eof, void *data)
349{
350 struct rtc_ops *ops = data;
351 struct rtc_wkalrm alrm;
352 struct rtc_time tm;
353 char *p = page;
354
355 if (rtc_arm_read_time(ops, &tm) == 0) {
356 p += sprintf(p,
357 "rtc_time\t: %02d:%02d:%02d\n"
358 "rtc_date\t: %04d-%02d-%02d\n"
359 "rtc_epoch\t: %04lu\n",
360 tm.tm_hour, tm.tm_min, tm.tm_sec,
361 tm.tm_year + 1900, tm.tm_mon + 1, tm.tm_mday,
362 rtc_epoch);
363 }
364
365 if (rtc_arm_read_alarm(ops, &alrm) == 0) {
366 p += sprintf(p, "alrm_time\t: ");
367 if ((unsigned int)alrm.time.tm_hour <= 24)
368 p += sprintf(p, "%02d:", alrm.time.tm_hour);
369 else
370 p += sprintf(p, "**:");
371 if ((unsigned int)alrm.time.tm_min <= 59)
372 p += sprintf(p, "%02d:", alrm.time.tm_min);
373 else
374 p += sprintf(p, "**:");
375 if ((unsigned int)alrm.time.tm_sec <= 59)
376 p += sprintf(p, "%02d\n", alrm.time.tm_sec);
377 else
378 p += sprintf(p, "**\n");
379
380 p += sprintf(p, "alrm_date\t: ");
381 if ((unsigned int)alrm.time.tm_year <= 200)
382 p += sprintf(p, "%04d-", alrm.time.tm_year + 1900);
383 else
384 p += sprintf(p, "****-");
385 if ((unsigned int)alrm.time.tm_mon <= 11)
386 p += sprintf(p, "%02d-", alrm.time.tm_mon + 1);
387 else
388 p += sprintf(p, "**-");
389 if ((unsigned int)alrm.time.tm_mday <= 31)
390 p += sprintf(p, "%02d\n", alrm.time.tm_mday);
391 else
392 p += sprintf(p, "**\n");
393 p += sprintf(p, "alrm_wakeup\t: %s\n",
394 alrm.enabled ? "yes" : "no");
395 p += sprintf(p, "alrm_pending\t: %s\n",
396 alrm.pending ? "yes" : "no");
397 }
398
399 if (ops->proc)
400 p += ops->proc(p);
401
402 return p - page;
403}
404
405int register_rtc(struct rtc_ops *ops)
406{
407 int ret = -EBUSY;
408
409 mutex_lock(&rtc_mutex);
410 if (rtc_ops == NULL) {
411 rtc_ops = ops;
412
413 ret = misc_register(&rtc_miscdev);
414 if (ret == 0)
415 create_proc_read_entry("driver/rtc", 0, NULL,
416 rtc_read_proc, ops);
417 }
418 mutex_unlock(&rtc_mutex);
419
420 return ret;
421}
422EXPORT_SYMBOL(register_rtc);
423
424void unregister_rtc(struct rtc_ops *rtc)
425{
426 mutex_lock(&rtc_mutex);
427 if (rtc == rtc_ops) {
428 remove_proc_entry("driver/rtc", NULL);
429 misc_deregister(&rtc_miscdev);
430 rtc_ops = NULL;
431 }
432 mutex_unlock(&rtc_mutex);
433}
434EXPORT_SYMBOL(unregister_rtc);
diff --git a/arch/arm/configs/at91cap9adk_defconfig b/arch/arm/configs/at91cap9adk_defconfig
index e32e73648129..be2b2f38fd94 100644
--- a/arch/arm/configs/at91cap9adk_defconfig
+++ b/arch/arm/configs/at91cap9adk_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
213# 213#
214# CONFIG_TICK_ONESHOT is not set 214# CONFIG_TICK_ONESHOT is not set
215# CONFIG_PREEMPT is not set 215# CONFIG_PREEMPT is not set
216# CONFIG_NO_IDLE_HZ is not set
217CONFIG_HZ=100 216CONFIG_HZ=100
218CONFIG_AEABI=y 217CONFIG_AEABI=y
219CONFIG_OABI_COMPAT=y 218CONFIG_OABI_COMPAT=y
@@ -907,7 +906,32 @@ CONFIG_USB_MON=y
907# 906#
908# USB Gadget Support 907# USB Gadget Support
909# 908#
910# CONFIG_USB_GADGET is not set 909CONFIG_USB_GADGET=y
910# CONFIG_USB_GADGET_DEBUG is not set
911# CONFIG_USB_GADGET_DEBUG_FILES is not set
912CONFIG_USB_GADGET_SELECTED=y
913# CONFIG_USB_GADGET_AMD5536UDC is not set
914CONFIG_USB_GADGET_ATMEL_USBA=y
915CONFIG_USB_ATMEL_USBA=y
916# CONFIG_USB_GADGET_FSL_USB2 is not set
917# CONFIG_USB_GADGET_NET2280 is not set
918# CONFIG_USB_GADGET_PXA2XX is not set
919# CONFIG_USB_GADGET_M66592 is not set
920# CONFIG_USB_GADGET_GOKU is not set
921# CONFIG_USB_GADGET_LH7A40X is not set
922# CONFIG_USB_GADGET_OMAP is not set
923# CONFIG_USB_GADGET_S3C2410 is not set
924# CONFIG_USB_GADGET_AT91 is not set
925# CONFIG_USB_GADGET_DUMMY_HCD is not set
926CONFIG_USB_GADGET_DUALSPEED=y
927# CONFIG_USB_ZERO is not set
928CONFIG_USB_ETH=m
929CONFIG_USB_ETH_RNDIS=y
930# CONFIG_USB_GADGETFS is not set
931CONFIG_USB_FILE_STORAGE=m
932# CONFIG_USB_FILE_STORAGE_TEST is not set
933# CONFIG_USB_G_SERIAL is not set
934# CONFIG_USB_MIDI_GADGET is not set
911CONFIG_MMC=y 935CONFIG_MMC=y
912# CONFIG_MMC_DEBUG is not set 936# CONFIG_MMC_DEBUG is not set
913# CONFIG_MMC_UNSAFE_RESUME is not set 937# CONFIG_MMC_UNSAFE_RESUME is not set
@@ -926,7 +950,59 @@ CONFIG_MMC_AT91=y
926# CONFIG_MMC_SPI is not set 950# CONFIG_MMC_SPI is not set
927# CONFIG_NEW_LEDS is not set 951# CONFIG_NEW_LEDS is not set
928CONFIG_RTC_LIB=y 952CONFIG_RTC_LIB=y
929# CONFIG_RTC_CLASS is not set 953CONFIG_RTC_CLASS=y
954CONFIG_RTC_HCTOSYS=y
955CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
956# CONFIG_RTC_DEBUG is not set
957
958#
959# RTC interfaces
960#
961CONFIG_RTC_INTF_SYSFS=y
962CONFIG_RTC_INTF_PROC=y
963CONFIG_RTC_INTF_DEV=y
964# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
965# CONFIG_RTC_DRV_TEST is not set
966
967#
968# I2C RTC drivers
969#
970# CONFIG_RTC_DRV_DS1307 is not set
971# CONFIG_RTC_DRV_DS1374 is not set
972# CONFIG_RTC_DRV_DS1672 is not set
973# CONFIG_RTC_DRV_MAX6900 is not set
974# CONFIG_RTC_DRV_RS5C372 is not set
975# CONFIG_RTC_DRV_ISL1208 is not set
976# CONFIG_RTC_DRV_X1205 is not set
977# CONFIG_RTC_DRV_PCF8563 is not set
978# CONFIG_RTC_DRV_PCF8583 is not set
979# CONFIG_RTC_DRV_M41T80 is not set
980
981#
982# SPI RTC drivers
983#
984# CONFIG_RTC_DRV_MAX6902 is not set
985# CONFIG_RTC_DRV_R9701 is not set
986# CONFIG_RTC_DRV_RS5C348 is not set
987
988#
989# Platform RTC drivers
990#
991# CONFIG_RTC_DRV_CMOS is not set
992# CONFIG_RTC_DRV_DS1511 is not set
993# CONFIG_RTC_DRV_DS1553 is not set
994# CONFIG_RTC_DRV_DS1742 is not set
995# CONFIG_RTC_DRV_STK17TA8 is not set
996# CONFIG_RTC_DRV_M48T86 is not set
997# CONFIG_RTC_DRV_M48T59 is not set
998# CONFIG_RTC_DRV_V3020 is not set
999
1000#
1001# on-CPU RTC drivers
1002#
1003CONFIG_RTC_DRV_AT91SAM9=y
1004CONFIG_RTC_DRV_AT91SAM9_RTT=0
1005CONFIG_RTC_DRV_AT91SAM9_GPBR=0
930 1006
931# 1007#
932# File systems 1008# File systems
diff --git a/arch/arm/configs/at91rm9200dk_defconfig b/arch/arm/configs/at91rm9200dk_defconfig
index 2dbbbc3d4ac3..868fb7b9530b 100644
--- a/arch/arm/configs/at91rm9200dk_defconfig
+++ b/arch/arm/configs/at91rm9200dk_defconfig
@@ -169,7 +169,6 @@ CONFIG_AT91_CF=y
169# Kernel Features 169# Kernel Features
170# 170#
171# CONFIG_PREEMPT is not set 171# CONFIG_PREEMPT is not set
172# CONFIG_NO_IDLE_HZ is not set
173# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 172# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
174CONFIG_SELECT_MEMORY_MODEL=y 173CONFIG_SELECT_MEMORY_MODEL=y
175CONFIG_FLATMEM_MANUAL=y 174CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91rm9200ek_defconfig b/arch/arm/configs/at91rm9200ek_defconfig
index 6e994f7820c6..de43fc675616 100644
--- a/arch/arm/configs/at91rm9200ek_defconfig
+++ b/arch/arm/configs/at91rm9200ek_defconfig
@@ -160,7 +160,6 @@ CONFIG_ISA_DMA_API=y
160# Kernel Features 160# Kernel Features
161# 161#
162# CONFIG_PREEMPT is not set 162# CONFIG_PREEMPT is not set
163# CONFIG_NO_IDLE_HZ is not set
164# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 163# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
165CONFIG_SELECT_MEMORY_MODEL=y 164CONFIG_SELECT_MEMORY_MODEL=y
166CONFIG_FLATMEM_MANUAL=y 165CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/at91sam9260ek_defconfig b/arch/arm/configs/at91sam9260ek_defconfig
index f659c938473f..2011adfa6758 100644
--- a/arch/arm/configs/at91sam9260ek_defconfig
+++ b/arch/arm/configs/at91sam9260ek_defconfig
@@ -220,7 +220,6 @@ CONFIG_CPU_CP15_MMU=y
220# 220#
221# CONFIG_TICK_ONESHOT is not set 221# CONFIG_TICK_ONESHOT is not set
222# CONFIG_PREEMPT is not set 222# CONFIG_PREEMPT is not set
223# CONFIG_NO_IDLE_HZ is not set
224CONFIG_HZ=100 223CONFIG_HZ=100
225# CONFIG_AEABI is not set 224# CONFIG_AEABI is not set
226# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 225# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9261ek_defconfig b/arch/arm/configs/at91sam9261ek_defconfig
index 3802e85f7483..4049768962d2 100644
--- a/arch/arm/configs/at91sam9261ek_defconfig
+++ b/arch/arm/configs/at91sam9261ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
213# 213#
214# CONFIG_TICK_ONESHOT is not set 214# CONFIG_TICK_ONESHOT is not set
215# CONFIG_PREEMPT is not set 215# CONFIG_PREEMPT is not set
216# CONFIG_NO_IDLE_HZ is not set
217CONFIG_HZ=100 216CONFIG_HZ=100
218# CONFIG_AEABI is not set 217# CONFIG_AEABI is not set
219# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 218# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9263ek_defconfig b/arch/arm/configs/at91sam9263ek_defconfig
index 32a0d74e0c89..fa1c5aecb5a8 100644
--- a/arch/arm/configs/at91sam9263ek_defconfig
+++ b/arch/arm/configs/at91sam9263ek_defconfig
@@ -213,7 +213,6 @@ CONFIG_CPU_CP15_MMU=y
213# 213#
214# CONFIG_TICK_ONESHOT is not set 214# CONFIG_TICK_ONESHOT is not set
215# CONFIG_PREEMPT is not set 215# CONFIG_PREEMPT is not set
216# CONFIG_NO_IDLE_HZ is not set
217CONFIG_HZ=100 216CONFIG_HZ=100
218# CONFIG_AEABI is not set 217# CONFIG_AEABI is not set
219# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 218# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/at91sam9g20ek_defconfig b/arch/arm/configs/at91sam9g20ek_defconfig
new file mode 100644
index 000000000000..c06863847364
--- /dev/null
+++ b/arch/arm/configs/at91sam9g20ek_defconfig
@@ -0,0 +1,1168 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24
4# Tue Jun 10 15:51:52 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35# CONFIG_LOCALVERSION_AUTO is not set
36# CONFIG_SWAP is not set
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48# CONFIG_FAIR_GROUP_SCHED is not set
49CONFIG_SYSFS_DEPRECATED=y
50# CONFIG_RELAY is not set
51CONFIG_BLK_DEV_INITRD=y
52CONFIG_INITRAMFS_SOURCE=""
53CONFIG_CC_OPTIMIZE_FOR_SIZE=y
54CONFIG_SYSCTL=y
55# CONFIG_EMBEDDED is not set
56CONFIG_UID16=y
57CONFIG_SYSCTL_SYSCALL=y
58CONFIG_KALLSYMS=y
59# CONFIG_KALLSYMS_EXTRA_PASS is not set
60CONFIG_HOTPLUG=y
61CONFIG_PRINTK=y
62CONFIG_BUG=y
63CONFIG_ELF_CORE=y
64CONFIG_BASE_FULL=y
65CONFIG_FUTEX=y
66CONFIG_ANON_INODES=y
67CONFIG_EPOLL=y
68CONFIG_SIGNALFD=y
69CONFIG_EVENTFD=y
70CONFIG_SHMEM=y
71CONFIG_VM_EVENT_COUNTERS=y
72CONFIG_SLAB=y
73# CONFIG_SLUB is not set
74# CONFIG_SLOB is not set
75CONFIG_SLABINFO=y
76CONFIG_RT_MUTEXES=y
77# CONFIG_TINY_SHMEM is not set
78CONFIG_BASE_SMALL=0
79CONFIG_MODULES=y
80CONFIG_MODULE_UNLOAD=y
81# CONFIG_MODULE_FORCE_UNLOAD is not set
82# CONFIG_MODVERSIONS is not set
83# CONFIG_MODULE_SRCVERSION_ALL is not set
84CONFIG_KMOD=y
85CONFIG_BLOCK=y
86# CONFIG_LBD is not set
87# CONFIG_BLK_DEV_IO_TRACE is not set
88# CONFIG_LSF is not set
89# CONFIG_BLK_DEV_BSG is not set
90
91#
92# IO Schedulers
93#
94CONFIG_IOSCHED_NOOP=y
95CONFIG_IOSCHED_AS=y
96# CONFIG_IOSCHED_DEADLINE is not set
97# CONFIG_IOSCHED_CFQ is not set
98CONFIG_DEFAULT_AS=y
99# CONFIG_DEFAULT_DEADLINE is not set
100# CONFIG_DEFAULT_CFQ is not set
101# CONFIG_DEFAULT_NOOP is not set
102CONFIG_DEFAULT_IOSCHED="anticipatory"
103
104#
105# System Type
106#
107# CONFIG_ARCH_AAEC2000 is not set
108# CONFIG_ARCH_INTEGRATOR is not set
109# CONFIG_ARCH_REALVIEW is not set
110# CONFIG_ARCH_VERSATILE is not set
111CONFIG_ARCH_AT91=y
112# CONFIG_ARCH_CLPS7500 is not set
113# CONFIG_ARCH_CLPS711X is not set
114# CONFIG_ARCH_CO285 is not set
115# CONFIG_ARCH_EBSA110 is not set
116# CONFIG_ARCH_EP93XX is not set
117# CONFIG_ARCH_FOOTBRIDGE is not set
118# CONFIG_ARCH_NETX is not set
119# CONFIG_ARCH_H720X is not set
120# CONFIG_ARCH_IMX is not set
121# CONFIG_ARCH_IOP13XX is not set
122# CONFIG_ARCH_IOP32X is not set
123# CONFIG_ARCH_IOP33X is not set
124# CONFIG_ARCH_IXP23XX is not set
125# CONFIG_ARCH_IXP2000 is not set
126# CONFIG_ARCH_IXP4XX is not set
127# CONFIG_ARCH_L7200 is not set
128# CONFIG_ARCH_KS8695 is not set
129# CONFIG_ARCH_NS9XXX is not set
130# CONFIG_ARCH_MXC is not set
131# CONFIG_ARCH_PNX4008 is not set
132# CONFIG_ARCH_PXA is not set
133# CONFIG_ARCH_RPC is not set
134# CONFIG_ARCH_SA1100 is not set
135# CONFIG_ARCH_S3C2410 is not set
136# CONFIG_ARCH_SHARK is not set
137# CONFIG_ARCH_LH7A40X is not set
138# CONFIG_ARCH_DAVINCI is not set
139# CONFIG_ARCH_OMAP is not set
140
141#
142# Boot options
143#
144
145#
146# Power management
147#
148
149#
150# Atmel AT91 System-on-Chip
151#
152# CONFIG_ARCH_AT91RM9200 is not set
153# CONFIG_ARCH_AT91SAM9260 is not set
154# CONFIG_ARCH_AT91SAM9261 is not set
155# CONFIG_ARCH_AT91SAM9263 is not set
156# CONFIG_ARCH_AT91SAM9RL is not set
157CONFIG_ARCH_AT91SAM9G20=y
158# CONFIG_ARCH_AT91CAP9 is not set
159# CONFIG_ARCH_AT91X40 is not set
160CONFIG_AT91_PMC_UNIT=y
161
162#
163# AT91SAM9G20 Board Type
164#
165CONFIG_MACH_AT91SAM9G20EK=y
166
167#
168# AT91 Board Options
169#
170# CONFIG_MTD_AT91_DATAFLASH_CARD is not set
171# CONFIG_MTD_NAND_AT91_BUSWIDTH_16 is not set
172
173#
174# AT91 Feature Selections
175#
176CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
177# CONFIG_AT91_SLOW_CLOCK is not set
178CONFIG_AT91_TIMER_HZ=100
179CONFIG_AT91_EARLY_DBGU=y
180# CONFIG_AT91_EARLY_USART0 is not set
181# CONFIG_AT91_EARLY_USART1 is not set
182# CONFIG_AT91_EARLY_USART2 is not set
183# CONFIG_AT91_EARLY_USART3 is not set
184# CONFIG_AT91_EARLY_USART4 is not set
185# CONFIG_AT91_EARLY_USART5 is not set
186
187#
188# Processor Type
189#
190CONFIG_CPU_32=y
191CONFIG_CPU_ARM926T=y
192CONFIG_CPU_32v5=y
193CONFIG_CPU_ABRT_EV5TJ=y
194CONFIG_CPU_CACHE_VIVT=y
195CONFIG_CPU_COPY_V4WB=y
196CONFIG_CPU_TLB_V4WBI=y
197CONFIG_CPU_CP15=y
198CONFIG_CPU_CP15_MMU=y
199
200#
201# Processor Features
202#
203# CONFIG_ARM_THUMB is not set
204# CONFIG_CPU_ICACHE_DISABLE is not set
205# CONFIG_CPU_DCACHE_DISABLE is not set
206# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
207# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
208# CONFIG_OUTER_CACHE is not set
209
210#
211# Bus support
212#
213# CONFIG_PCI_SYSCALL is not set
214# CONFIG_ARCH_SUPPORTS_MSI is not set
215# CONFIG_PCCARD is not set
216
217#
218# Kernel Features
219#
220# CONFIG_TICK_ONESHOT is not set
221# CONFIG_NO_HZ is not set
222# CONFIG_HIGH_RES_TIMERS is not set
223CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
224# CONFIG_PREEMPT is not set
225CONFIG_HZ=100
226CONFIG_AEABI=y
227CONFIG_OABI_COMPAT=y
228# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
229CONFIG_SELECT_MEMORY_MODEL=y
230CONFIG_FLATMEM_MANUAL=y
231# CONFIG_DISCONTIGMEM_MANUAL is not set
232# CONFIG_SPARSEMEM_MANUAL is not set
233CONFIG_FLATMEM=y
234CONFIG_FLAT_NODE_MEM_MAP=y
235# CONFIG_SPARSEMEM_STATIC is not set
236# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
237CONFIG_SPLIT_PTLOCK_CPUS=4096
238# CONFIG_RESOURCES_64BIT is not set
239CONFIG_ZONE_DMA_FLAG=1
240CONFIG_BOUNCE=y
241CONFIG_VIRT_TO_BUS=y
242CONFIG_LEDS=y
243CONFIG_LEDS_CPU=y
244CONFIG_ALIGNMENT_TRAP=y
245
246#
247# Boot options
248#
249CONFIG_ZBOOT_ROM_TEXT=0x0
250CONFIG_ZBOOT_ROM_BSS=0x0
251CONFIG_CMDLINE="mem=64M console=ttyS0,115200 initrd=0x21100000,3145728 root=/dev/ram0 rw"
252# CONFIG_XIP_KERNEL is not set
253# CONFIG_KEXEC is not set
254
255#
256# Floating point emulation
257#
258
259#
260# At least one emulation must be selected
261#
262CONFIG_FPE_NWFPE=y
263# CONFIG_FPE_NWFPE_XP is not set
264# CONFIG_FPE_FASTFPE is not set
265# CONFIG_VFP is not set
266
267#
268# Userspace binary formats
269#
270CONFIG_BINFMT_ELF=y
271# CONFIG_BINFMT_AOUT is not set
272# CONFIG_BINFMT_MISC is not set
273
274#
275# Power management options
276#
277CONFIG_PM=y
278# CONFIG_PM_LEGACY is not set
279# CONFIG_PM_DEBUG is not set
280CONFIG_PM_SLEEP=y
281CONFIG_SUSPEND_UP_POSSIBLE=y
282CONFIG_SUSPEND=y
283# CONFIG_APM_EMULATION is not set
284
285#
286# Networking
287#
288CONFIG_NET=y
289
290#
291# Networking options
292#
293CONFIG_PACKET=y
294# CONFIG_PACKET_MMAP is not set
295CONFIG_UNIX=y
296# CONFIG_NET_KEY is not set
297CONFIG_INET=y
298# CONFIG_IP_MULTICAST is not set
299# CONFIG_IP_ADVANCED_ROUTER is not set
300CONFIG_IP_FIB_HASH=y
301CONFIG_IP_PNP=y
302# CONFIG_IP_PNP_DHCP is not set
303CONFIG_IP_PNP_BOOTP=y
304# CONFIG_IP_PNP_RARP is not set
305# CONFIG_NET_IPIP is not set
306# CONFIG_NET_IPGRE is not set
307# CONFIG_ARPD is not set
308# CONFIG_SYN_COOKIES is not set
309# CONFIG_INET_AH is not set
310# CONFIG_INET_ESP is not set
311# CONFIG_INET_IPCOMP is not set
312# CONFIG_INET_XFRM_TUNNEL is not set
313# CONFIG_INET_TUNNEL is not set
314# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
315# CONFIG_INET_XFRM_MODE_TUNNEL is not set
316# CONFIG_INET_XFRM_MODE_BEET is not set
317# CONFIG_INET_LRO is not set
318CONFIG_INET_DIAG=y
319CONFIG_INET_TCP_DIAG=y
320# CONFIG_TCP_CONG_ADVANCED is not set
321CONFIG_TCP_CONG_CUBIC=y
322CONFIG_DEFAULT_TCP_CONG="cubic"
323# CONFIG_TCP_MD5SIG is not set
324# CONFIG_IPV6 is not set
325# CONFIG_INET6_XFRM_TUNNEL is not set
326# CONFIG_INET6_TUNNEL is not set
327# CONFIG_NETWORK_SECMARK is not set
328# CONFIG_NETFILTER is not set
329# CONFIG_IP_DCCP is not set
330# CONFIG_IP_SCTP is not set
331# CONFIG_TIPC is not set
332# CONFIG_ATM is not set
333# CONFIG_BRIDGE is not set
334# CONFIG_VLAN_8021Q is not set
335# CONFIG_DECNET is not set
336# CONFIG_LLC2 is not set
337# CONFIG_IPX is not set
338# CONFIG_ATALK is not set
339# CONFIG_X25 is not set
340# CONFIG_LAPB is not set
341# CONFIG_ECONET is not set
342# CONFIG_WAN_ROUTER is not set
343# CONFIG_NET_SCHED is not set
344
345#
346# Network testing
347#
348# CONFIG_NET_PKTGEN is not set
349# CONFIG_HAMRADIO is not set
350# CONFIG_IRDA is not set
351# CONFIG_BT is not set
352# CONFIG_AF_RXRPC is not set
353
354#
355# Wireless
356#
357# CONFIG_CFG80211 is not set
358# CONFIG_WIRELESS_EXT is not set
359# CONFIG_MAC80211 is not set
360# CONFIG_IEEE80211 is not set
361# CONFIG_RFKILL is not set
362# CONFIG_NET_9P is not set
363
364#
365# Device Drivers
366#
367
368#
369# Generic Driver Options
370#
371CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
372CONFIG_STANDALONE=y
373CONFIG_PREVENT_FIRMWARE_BUILD=y
374# CONFIG_FW_LOADER is not set
375# CONFIG_SYS_HYPERVISOR is not set
376# CONFIG_CONNECTOR is not set
377CONFIG_MTD=y
378# CONFIG_MTD_DEBUG is not set
379CONFIG_MTD_CONCAT=y
380CONFIG_MTD_PARTITIONS=y
381# CONFIG_MTD_REDBOOT_PARTS is not set
382CONFIG_MTD_CMDLINE_PARTS=y
383# CONFIG_MTD_AFS_PARTS is not set
384
385#
386# User Modules And Translation Layers
387#
388CONFIG_MTD_CHAR=y
389CONFIG_MTD_BLKDEVS=y
390CONFIG_MTD_BLOCK=y
391# CONFIG_FTL is not set
392# CONFIG_NFTL is not set
393# CONFIG_INFTL is not set
394# CONFIG_RFD_FTL is not set
395# CONFIG_SSFDC is not set
396# CONFIG_MTD_OOPS is not set
397
398#
399# RAM/ROM/Flash chip drivers
400#
401# CONFIG_MTD_CFI is not set
402# CONFIG_MTD_JEDECPROBE is not set
403CONFIG_MTD_MAP_BANK_WIDTH_1=y
404CONFIG_MTD_MAP_BANK_WIDTH_2=y
405CONFIG_MTD_MAP_BANK_WIDTH_4=y
406# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
407# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
408# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
409CONFIG_MTD_CFI_I1=y
410CONFIG_MTD_CFI_I2=y
411# CONFIG_MTD_CFI_I4 is not set
412# CONFIG_MTD_CFI_I8 is not set
413# CONFIG_MTD_RAM is not set
414# CONFIG_MTD_ROM is not set
415# CONFIG_MTD_ABSENT is not set
416
417#
418# Mapping drivers for chip access
419#
420# CONFIG_MTD_COMPLEX_MAPPINGS is not set
421# CONFIG_MTD_PLATRAM is not set
422
423#
424# Self-contained MTD device drivers
425#
426CONFIG_MTD_DATAFLASH=y
427# CONFIG_MTD_M25P80 is not set
428# CONFIG_MTD_SLRAM is not set
429# CONFIG_MTD_PHRAM is not set
430# CONFIG_MTD_MTDRAM is not set
431# CONFIG_MTD_BLOCK2MTD is not set
432
433#
434# Disk-On-Chip Device Drivers
435#
436# CONFIG_MTD_DOC2000 is not set
437# CONFIG_MTD_DOC2001 is not set
438# CONFIG_MTD_DOC2001PLUS is not set
439CONFIG_MTD_NAND=y
440# CONFIG_MTD_NAND_VERIFY_WRITE is not set
441# CONFIG_MTD_NAND_ECC_SMC is not set
442# CONFIG_MTD_NAND_MUSEUM_IDS is not set
443CONFIG_MTD_NAND_IDS=y
444# CONFIG_MTD_NAND_DISKONCHIP is not set
445CONFIG_MTD_NAND_AT91=y
446CONFIG_MTD_NAND_AT91_ECC_SOFT=y
447# CONFIG_MTD_NAND_AT91_ECC_HW is not set
448# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
449# CONFIG_MTD_NAND_NANDSIM is not set
450# CONFIG_MTD_NAND_PLATFORM is not set
451# CONFIG_MTD_ALAUDA is not set
452# CONFIG_MTD_ONENAND is not set
453
454#
455# UBI - Unsorted block images
456#
457# CONFIG_MTD_UBI is not set
458# CONFIG_PARPORT is not set
459CONFIG_BLK_DEV=y
460# CONFIG_BLK_DEV_COW_COMMON is not set
461CONFIG_BLK_DEV_LOOP=y
462# CONFIG_BLK_DEV_CRYPTOLOOP is not set
463# CONFIG_BLK_DEV_NBD is not set
464# CONFIG_BLK_DEV_UB is not set
465CONFIG_BLK_DEV_RAM=y
466CONFIG_BLK_DEV_RAM_COUNT=16
467CONFIG_BLK_DEV_RAM_SIZE=8192
468CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
469# CONFIG_CDROM_PKTCDVD is not set
470# CONFIG_ATA_OVER_ETH is not set
471CONFIG_MISC_DEVICES=y
472CONFIG_ATMEL_PWM=y
473# CONFIG_EEPROM_93CX6 is not set
474CONFIG_ATMEL_SSC=y
475
476#
477# SCSI device support
478#
479# CONFIG_RAID_ATTRS is not set
480CONFIG_SCSI=y
481CONFIG_SCSI_DMA=y
482# CONFIG_SCSI_TGT is not set
483# CONFIG_SCSI_NETLINK is not set
484CONFIG_SCSI_PROC_FS=y
485
486#
487# SCSI support type (disk, tape, CD-ROM)
488#
489CONFIG_BLK_DEV_SD=y
490# CONFIG_CHR_DEV_ST is not set
491# CONFIG_CHR_DEV_OSST is not set
492# CONFIG_BLK_DEV_SR is not set
493# CONFIG_CHR_DEV_SG is not set
494# CONFIG_CHR_DEV_SCH is not set
495
496#
497# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
498#
499CONFIG_SCSI_MULTI_LUN=y
500# CONFIG_SCSI_CONSTANTS is not set
501# CONFIG_SCSI_LOGGING is not set
502# CONFIG_SCSI_SCAN_ASYNC is not set
503CONFIG_SCSI_WAIT_SCAN=m
504
505#
506# SCSI Transports
507#
508# CONFIG_SCSI_SPI_ATTRS is not set
509# CONFIG_SCSI_FC_ATTRS is not set
510# CONFIG_SCSI_ISCSI_ATTRS is not set
511# CONFIG_SCSI_SAS_LIBSAS is not set
512# CONFIG_SCSI_SRP_ATTRS is not set
513# CONFIG_SCSI_LOWLEVEL is not set
514# CONFIG_ATA is not set
515# CONFIG_MD is not set
516CONFIG_NETDEVICES=y
517# CONFIG_NETDEVICES_MULTIQUEUE is not set
518# CONFIG_DUMMY is not set
519# CONFIG_BONDING is not set
520# CONFIG_MACVLAN is not set
521# CONFIG_EQUALIZER is not set
522# CONFIG_TUN is not set
523# CONFIG_VETH is not set
524CONFIG_PHYLIB=y
525
526#
527# MII PHY device drivers
528#
529# CONFIG_MARVELL_PHY is not set
530# CONFIG_DAVICOM_PHY is not set
531# CONFIG_QSEMI_PHY is not set
532# CONFIG_LXT_PHY is not set
533# CONFIG_CICADA_PHY is not set
534# CONFIG_VITESSE_PHY is not set
535# CONFIG_SMSC_PHY is not set
536# CONFIG_BROADCOM_PHY is not set
537# CONFIG_ICPLUS_PHY is not set
538# CONFIG_FIXED_PHY is not set
539# CONFIG_MDIO_BITBANG is not set
540CONFIG_NET_ETHERNET=y
541CONFIG_MII=y
542CONFIG_MACB=y
543# CONFIG_AX88796 is not set
544# CONFIG_SMC91X is not set
545# CONFIG_DM9000 is not set
546# CONFIG_IBM_NEW_EMAC_ZMII is not set
547# CONFIG_IBM_NEW_EMAC_RGMII is not set
548# CONFIG_IBM_NEW_EMAC_TAH is not set
549# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
550# CONFIG_B44 is not set
551# CONFIG_NETDEV_1000 is not set
552# CONFIG_NETDEV_10000 is not set
553
554#
555# Wireless LAN
556#
557# CONFIG_WLAN_PRE80211 is not set
558# CONFIG_WLAN_80211 is not set
559
560#
561# USB Network Adapters
562#
563# CONFIG_USB_CATC is not set
564# CONFIG_USB_KAWETH is not set
565# CONFIG_USB_PEGASUS is not set
566# CONFIG_USB_RTL8150 is not set
567# CONFIG_USB_USBNET is not set
568# CONFIG_WAN is not set
569# CONFIG_PPP is not set
570# CONFIG_SLIP is not set
571# CONFIG_SHAPER is not set
572# CONFIG_NETCONSOLE is not set
573# CONFIG_NETPOLL is not set
574# CONFIG_NET_POLL_CONTROLLER is not set
575# CONFIG_ISDN is not set
576
577#
578# Input device support
579#
580CONFIG_INPUT=y
581# CONFIG_INPUT_FF_MEMLESS is not set
582# CONFIG_INPUT_POLLDEV is not set
583
584#
585# Userland interfaces
586#
587CONFIG_INPUT_MOUSEDEV=y
588# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
589CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
590CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
591# CONFIG_INPUT_JOYDEV is not set
592CONFIG_INPUT_EVDEV=y
593# CONFIG_INPUT_EVBUG is not set
594
595#
596# Input Device Drivers
597#
598CONFIG_INPUT_KEYBOARD=y
599# CONFIG_KEYBOARD_ATKBD is not set
600# CONFIG_KEYBOARD_SUNKBD is not set
601# CONFIG_KEYBOARD_LKKBD is not set
602# CONFIG_KEYBOARD_XTKBD is not set
603# CONFIG_KEYBOARD_NEWTON is not set
604# CONFIG_KEYBOARD_STOWAWAY is not set
605CONFIG_KEYBOARD_GPIO=y
606# CONFIG_INPUT_MOUSE is not set
607# CONFIG_INPUT_JOYSTICK is not set
608# CONFIG_INPUT_TABLET is not set
609# CONFIG_INPUT_TOUCHSCREEN is not set
610# CONFIG_INPUT_MISC is not set
611
612#
613# Hardware I/O ports
614#
615CONFIG_SERIO=y
616CONFIG_SERIO_SERPORT=y
617# CONFIG_SERIO_RAW is not set
618# CONFIG_GAMEPORT is not set
619
620#
621# Character devices
622#
623CONFIG_VT=y
624CONFIG_VT_CONSOLE=y
625CONFIG_HW_CONSOLE=y
626# CONFIG_VT_HW_CONSOLE_BINDING is not set
627# CONFIG_SERIAL_NONSTANDARD is not set
628
629#
630# Serial drivers
631#
632# CONFIG_SERIAL_8250 is not set
633
634#
635# Non-8250 serial port support
636#
637CONFIG_SERIAL_ATMEL=y
638CONFIG_SERIAL_ATMEL_CONSOLE=y
639# CONFIG_SERIAL_ATMEL_TTYAT is not set
640CONFIG_SERIAL_CORE=y
641CONFIG_SERIAL_CORE_CONSOLE=y
642CONFIG_UNIX98_PTYS=y
643CONFIG_LEGACY_PTYS=y
644CONFIG_LEGACY_PTY_COUNT=16
645# CONFIG_IPMI_HANDLER is not set
646CONFIG_HW_RANDOM=y
647# CONFIG_NVRAM is not set
648# CONFIG_R3964 is not set
649# CONFIG_RAW_DRIVER is not set
650# CONFIG_TCG_TPM is not set
651# CONFIG_I2C is not set
652
653#
654# SPI support
655#
656CONFIG_SPI=y
657CONFIG_SPI_MASTER=y
658
659#
660# SPI Master Controller Drivers
661#
662CONFIG_SPI_ATMEL=y
663# CONFIG_SPI_BITBANG is not set
664
665#
666# SPI Protocol Masters
667#
668# CONFIG_SPI_AT25 is not set
669CONFIG_SPI_SPIDEV=y
670# CONFIG_SPI_TLE62X0 is not set
671# CONFIG_W1 is not set
672# CONFIG_POWER_SUPPLY is not set
673# CONFIG_HWMON is not set
674# CONFIG_WATCHDOG is not set
675
676#
677# Sonics Silicon Backplane
678#
679CONFIG_SSB_POSSIBLE=y
680# CONFIG_SSB is not set
681
682#
683# Multifunction device drivers
684#
685# CONFIG_MFD_SM501 is not set
686
687#
688# Multimedia devices
689#
690# CONFIG_VIDEO_DEV is not set
691# CONFIG_DVB_CORE is not set
692# CONFIG_DAB is not set
693
694#
695# Graphics support
696#
697# CONFIG_VGASTATE is not set
698# CONFIG_VIDEO_OUTPUT_CONTROL is not set
699# CONFIG_FB is not set
700# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
701
702#
703# Display device support
704#
705# CONFIG_DISPLAY_SUPPORT is not set
706
707#
708# Console display driver support
709#
710# CONFIG_VGA_CONSOLE is not set
711CONFIG_DUMMY_CONSOLE=y
712
713#
714# Sound
715#
716CONFIG_SOUND=y
717
718#
719# Advanced Linux Sound Architecture
720#
721CONFIG_SND=y
722CONFIG_SND_TIMER=y
723CONFIG_SND_PCM=y
724CONFIG_SND_SEQUENCER=y
725# CONFIG_SND_SEQ_DUMMY is not set
726CONFIG_SND_OSSEMUL=y
727CONFIG_SND_MIXER_OSS=y
728CONFIG_SND_PCM_OSS=y
729CONFIG_SND_PCM_OSS_PLUGINS=y
730CONFIG_SND_SEQUENCER_OSS=y
731# CONFIG_SND_DYNAMIC_MINORS is not set
732CONFIG_SND_SUPPORT_OLD_API=y
733# CONFIG_SND_VERBOSE_PROCFS is not set
734# CONFIG_SND_VERBOSE_PRINTK is not set
735# CONFIG_SND_DEBUG is not set
736
737#
738# Generic devices
739#
740# CONFIG_SND_DUMMY is not set
741# CONFIG_SND_VIRMIDI is not set
742# CONFIG_SND_MTPAV is not set
743# CONFIG_SND_SERIAL_U16550 is not set
744# CONFIG_SND_MPU401 is not set
745
746#
747# ALSA ARM devices
748#
749# CONFIG_SND_AT91_AC97 is not set
750
751#
752# SPI devices
753#
754CONFIG_SND_AT73C213=y
755CONFIG_SND_AT73C213_TARGET_BITRATE=48000
756
757#
758# USB devices
759#
760# CONFIG_SND_USB_AUDIO is not set
761# CONFIG_SND_USB_CAIAQ is not set
762
763#
764# System on Chip audio support
765#
766# CONFIG_SND_SOC is not set
767
768#
769# SoC Audio support for SuperH
770#
771
772#
773# Open Sound System
774#
775# CONFIG_SOUND_PRIME is not set
776CONFIG_HID_SUPPORT=y
777CONFIG_HID=y
778# CONFIG_HID_DEBUG is not set
779# CONFIG_HIDRAW is not set
780
781#
782# USB Input Devices
783#
784CONFIG_USB_HID=y
785# CONFIG_USB_HIDINPUT_POWERBOOK is not set
786# CONFIG_HID_FF is not set
787# CONFIG_USB_HIDDEV is not set
788CONFIG_USB_SUPPORT=y
789CONFIG_USB_ARCH_HAS_HCD=y
790CONFIG_USB_ARCH_HAS_OHCI=y
791# CONFIG_USB_ARCH_HAS_EHCI is not set
792CONFIG_USB=y
793# CONFIG_USB_DEBUG is not set
794
795#
796# Miscellaneous USB options
797#
798CONFIG_USB_DEVICEFS=y
799# CONFIG_USB_DEVICE_CLASS is not set
800# CONFIG_USB_DYNAMIC_MINORS is not set
801# CONFIG_USB_SUSPEND is not set
802# CONFIG_USB_PERSIST is not set
803# CONFIG_USB_OTG is not set
804
805#
806# USB Host Controller Drivers
807#
808# CONFIG_USB_ISP116X_HCD is not set
809CONFIG_USB_OHCI_HCD=y
810# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
811# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
812CONFIG_USB_OHCI_LITTLE_ENDIAN=y
813# CONFIG_USB_SL811_HCD is not set
814# CONFIG_USB_R8A66597_HCD is not set
815
816#
817# USB Device Class drivers
818#
819# CONFIG_USB_ACM is not set
820# CONFIG_USB_PRINTER is not set
821
822#
823# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
824#
825
826#
827# may also be needed; see USB_STORAGE Help for more information
828#
829CONFIG_USB_STORAGE=y
830# CONFIG_USB_STORAGE_DEBUG is not set
831# CONFIG_USB_STORAGE_DATAFAB is not set
832# CONFIG_USB_STORAGE_FREECOM is not set
833# CONFIG_USB_STORAGE_ISD200 is not set
834# CONFIG_USB_STORAGE_DPCM is not set
835# CONFIG_USB_STORAGE_USBAT is not set
836# CONFIG_USB_STORAGE_SDDR09 is not set
837# CONFIG_USB_STORAGE_SDDR55 is not set
838# CONFIG_USB_STORAGE_JUMPSHOT is not set
839# CONFIG_USB_STORAGE_ALAUDA is not set
840# CONFIG_USB_STORAGE_KARMA is not set
841# CONFIG_USB_LIBUSUAL is not set
842
843#
844# USB Imaging devices
845#
846# CONFIG_USB_MDC800 is not set
847# CONFIG_USB_MICROTEK is not set
848CONFIG_USB_MON=y
849
850#
851# USB port drivers
852#
853
854#
855# USB Serial Converter support
856#
857# CONFIG_USB_SERIAL is not set
858
859#
860# USB Miscellaneous drivers
861#
862# CONFIG_USB_EMI62 is not set
863# CONFIG_USB_EMI26 is not set
864# CONFIG_USB_ADUTUX is not set
865# CONFIG_USB_AUERSWALD is not set
866# CONFIG_USB_RIO500 is not set
867# CONFIG_USB_LEGOTOWER is not set
868# CONFIG_USB_LCD is not set
869# CONFIG_USB_BERRY_CHARGE is not set
870# CONFIG_USB_LED is not set
871# CONFIG_USB_CYPRESS_CY7C63 is not set
872# CONFIG_USB_CYTHERM is not set
873# CONFIG_USB_PHIDGET is not set
874# CONFIG_USB_IDMOUSE is not set
875# CONFIG_USB_FTDI_ELAN is not set
876# CONFIG_USB_APPLEDISPLAY is not set
877# CONFIG_USB_LD is not set
878# CONFIG_USB_TRANCEVIBRATOR is not set
879# CONFIG_USB_IOWARRIOR is not set
880# CONFIG_USB_TEST is not set
881
882#
883# USB DSL modem support
884#
885
886#
887# USB Gadget Support
888#
889CONFIG_USB_GADGET=y
890# CONFIG_USB_GADGET_DEBUG_FILES is not set
891CONFIG_USB_GADGET_SELECTED=y
892# CONFIG_USB_GADGET_AMD5536UDC is not set
893# CONFIG_USB_GADGET_ATMEL_USBA is not set
894# CONFIG_USB_GADGET_FSL_USB2 is not set
895# CONFIG_USB_GADGET_NET2280 is not set
896# CONFIG_USB_GADGET_PXA2XX is not set
897# CONFIG_USB_GADGET_M66592 is not set
898# CONFIG_USB_GADGET_GOKU is not set
899# CONFIG_USB_GADGET_LH7A40X is not set
900# CONFIG_USB_GADGET_OMAP is not set
901# CONFIG_USB_GADGET_S3C2410 is not set
902CONFIG_USB_GADGET_AT91=y
903CONFIG_USB_AT91=y
904# CONFIG_USB_GADGET_DUMMY_HCD is not set
905# CONFIG_USB_GADGET_DUALSPEED is not set
906CONFIG_USB_ZERO=m
907# CONFIG_USB_ETH is not set
908CONFIG_USB_GADGETFS=m
909CONFIG_USB_FILE_STORAGE=m
910# CONFIG_USB_FILE_STORAGE_TEST is not set
911CONFIG_USB_G_SERIAL=m
912# CONFIG_USB_MIDI_GADGET is not set
913CONFIG_MMC=y
914# CONFIG_MMC_DEBUG is not set
915# CONFIG_MMC_UNSAFE_RESUME is not set
916
917#
918# MMC/SD Card Drivers
919#
920CONFIG_MMC_BLOCK=y
921CONFIG_MMC_BLOCK_BOUNCE=y
922# CONFIG_SDIO_UART is not set
923
924#
925# MMC/SD Host Controller Drivers
926#
927CONFIG_MMC_AT91=y
928# CONFIG_MMC_SPI is not set
929CONFIG_NEW_LEDS=y
930CONFIG_LEDS_CLASS=y
931
932#
933# LED drivers
934#
935CONFIG_LEDS_ATMEL_PWM=y
936CONFIG_LEDS_GPIO=y
937
938#
939# LED Triggers
940#
941CONFIG_LEDS_TRIGGERS=y
942CONFIG_LEDS_TRIGGER_TIMER=y
943CONFIG_LEDS_TRIGGER_HEARTBEAT=y
944CONFIG_RTC_LIB=y
945CONFIG_RTC_CLASS=y
946CONFIG_RTC_HCTOSYS=y
947CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
948# CONFIG_RTC_DEBUG is not set
949
950#
951# RTC interfaces
952#
953CONFIG_RTC_INTF_SYSFS=y
954CONFIG_RTC_INTF_PROC=y
955CONFIG_RTC_INTF_DEV=y
956# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
957# CONFIG_RTC_DRV_TEST is not set
958
959#
960# SPI RTC drivers
961#
962# CONFIG_RTC_DRV_RS5C348 is not set
963# CONFIG_RTC_DRV_MAX6902 is not set
964
965#
966# Platform RTC drivers
967#
968# CONFIG_RTC_DRV_CMOS is not set
969# CONFIG_RTC_DRV_DS1553 is not set
970# CONFIG_RTC_DRV_STK17TA8 is not set
971# CONFIG_RTC_DRV_DS1742 is not set
972# CONFIG_RTC_DRV_M48T86 is not set
973# CONFIG_RTC_DRV_M48T59 is not set
974# CONFIG_RTC_DRV_V3020 is not set
975
976#
977# on-CPU RTC drivers
978#
979CONFIG_RTC_DRV_AT91SAM9=y
980CONFIG_RTC_DRV_AT91SAM9_RTT=0
981CONFIG_RTC_DRV_AT91SAM9_GPBR=0
982
983#
984# File systems
985#
986CONFIG_EXT2_FS=y
987# CONFIG_EXT2_FS_XATTR is not set
988# CONFIG_EXT2_FS_XIP is not set
989# CONFIG_EXT3_FS is not set
990# CONFIG_EXT4DEV_FS is not set
991# CONFIG_REISERFS_FS is not set
992# CONFIG_JFS_FS is not set
993# CONFIG_FS_POSIX_ACL is not set
994# CONFIG_XFS_FS is not set
995# CONFIG_GFS2_FS is not set
996# CONFIG_OCFS2_FS is not set
997# CONFIG_MINIX_FS is not set
998# CONFIG_ROMFS_FS is not set
999CONFIG_INOTIFY=y
1000CONFIG_INOTIFY_USER=y
1001# CONFIG_QUOTA is not set
1002CONFIG_DNOTIFY=y
1003# CONFIG_AUTOFS_FS is not set
1004# CONFIG_AUTOFS4_FS is not set
1005# CONFIG_FUSE_FS is not set
1006
1007#
1008# CD-ROM/DVD Filesystems
1009#
1010# CONFIG_ISO9660_FS is not set
1011# CONFIG_UDF_FS is not set
1012
1013#
1014# DOS/FAT/NT Filesystems
1015#
1016CONFIG_FAT_FS=y
1017CONFIG_MSDOS_FS=y
1018CONFIG_VFAT_FS=y
1019CONFIG_FAT_DEFAULT_CODEPAGE=437
1020CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1021# CONFIG_NTFS_FS is not set
1022
1023#
1024# Pseudo filesystems
1025#
1026CONFIG_PROC_FS=y
1027CONFIG_PROC_SYSCTL=y
1028CONFIG_SYSFS=y
1029CONFIG_TMPFS=y
1030# CONFIG_TMPFS_POSIX_ACL is not set
1031# CONFIG_HUGETLB_PAGE is not set
1032# CONFIG_CONFIGFS_FS is not set
1033
1034#
1035# Miscellaneous filesystems
1036#
1037# CONFIG_ADFS_FS is not set
1038# CONFIG_AFFS_FS is not set
1039# CONFIG_HFS_FS is not set
1040# CONFIG_HFSPLUS_FS is not set
1041# CONFIG_BEFS_FS is not set
1042# CONFIG_BFS_FS is not set
1043# CONFIG_EFS_FS is not set
1044CONFIG_JFFS2_FS=y
1045CONFIG_JFFS2_FS_DEBUG=0
1046CONFIG_JFFS2_FS_WRITEBUFFER=y
1047# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1048CONFIG_JFFS2_SUMMARY=y
1049# CONFIG_JFFS2_FS_XATTR is not set
1050# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1051CONFIG_JFFS2_ZLIB=y
1052# CONFIG_JFFS2_LZO is not set
1053CONFIG_JFFS2_RTIME=y
1054# CONFIG_JFFS2_RUBIN is not set
1055CONFIG_CRAMFS=y
1056# CONFIG_VXFS_FS is not set
1057# CONFIG_HPFS_FS is not set
1058# CONFIG_QNX4FS_FS is not set
1059# CONFIG_SYSV_FS is not set
1060# CONFIG_UFS_FS is not set
1061CONFIG_NETWORK_FILESYSTEMS=y
1062CONFIG_NFS_FS=y
1063CONFIG_NFS_V3=y
1064# CONFIG_NFS_V3_ACL is not set
1065# CONFIG_NFS_V4 is not set
1066# CONFIG_NFS_DIRECTIO is not set
1067# CONFIG_NFSD is not set
1068CONFIG_ROOT_NFS=y
1069CONFIG_LOCKD=y
1070CONFIG_LOCKD_V4=y
1071CONFIG_NFS_COMMON=y
1072CONFIG_SUNRPC=y
1073# CONFIG_SUNRPC_BIND34 is not set
1074# CONFIG_RPCSEC_GSS_KRB5 is not set
1075# CONFIG_RPCSEC_GSS_SPKM3 is not set
1076# CONFIG_SMB_FS is not set
1077# CONFIG_CIFS is not set
1078# CONFIG_NCP_FS is not set
1079# CONFIG_CODA_FS is not set
1080# CONFIG_AFS_FS is not set
1081
1082#
1083# Partition Types
1084#
1085# CONFIG_PARTITION_ADVANCED is not set
1086CONFIG_MSDOS_PARTITION=y
1087CONFIG_NLS=y
1088CONFIG_NLS_DEFAULT="iso8859-1"
1089CONFIG_NLS_CODEPAGE_437=y
1090# CONFIG_NLS_CODEPAGE_737 is not set
1091# CONFIG_NLS_CODEPAGE_775 is not set
1092CONFIG_NLS_CODEPAGE_850=y
1093# CONFIG_NLS_CODEPAGE_852 is not set
1094# CONFIG_NLS_CODEPAGE_855 is not set
1095# CONFIG_NLS_CODEPAGE_857 is not set
1096# CONFIG_NLS_CODEPAGE_860 is not set
1097# CONFIG_NLS_CODEPAGE_861 is not set
1098# CONFIG_NLS_CODEPAGE_862 is not set
1099# CONFIG_NLS_CODEPAGE_863 is not set
1100# CONFIG_NLS_CODEPAGE_864 is not set
1101# CONFIG_NLS_CODEPAGE_865 is not set
1102# CONFIG_NLS_CODEPAGE_866 is not set
1103# CONFIG_NLS_CODEPAGE_869 is not set
1104# CONFIG_NLS_CODEPAGE_936 is not set
1105# CONFIG_NLS_CODEPAGE_950 is not set
1106# CONFIG_NLS_CODEPAGE_932 is not set
1107# CONFIG_NLS_CODEPAGE_949 is not set
1108# CONFIG_NLS_CODEPAGE_874 is not set
1109# CONFIG_NLS_ISO8859_8 is not set
1110# CONFIG_NLS_CODEPAGE_1250 is not set
1111# CONFIG_NLS_CODEPAGE_1251 is not set
1112# CONFIG_NLS_ASCII is not set
1113CONFIG_NLS_ISO8859_1=y
1114# CONFIG_NLS_ISO8859_2 is not set
1115# CONFIG_NLS_ISO8859_3 is not set
1116# CONFIG_NLS_ISO8859_4 is not set
1117# CONFIG_NLS_ISO8859_5 is not set
1118# CONFIG_NLS_ISO8859_6 is not set
1119# CONFIG_NLS_ISO8859_7 is not set
1120# CONFIG_NLS_ISO8859_9 is not set
1121# CONFIG_NLS_ISO8859_13 is not set
1122# CONFIG_NLS_ISO8859_14 is not set
1123CONFIG_NLS_ISO8859_15=y
1124# CONFIG_NLS_KOI8_R is not set
1125# CONFIG_NLS_KOI8_U is not set
1126CONFIG_NLS_UTF8=y
1127# CONFIG_DLM is not set
1128# CONFIG_INSTRUMENTATION is not set
1129
1130#
1131# Kernel hacking
1132#
1133# CONFIG_PRINTK_TIME is not set
1134# CONFIG_ENABLE_WARN_DEPRECATED is not set
1135CONFIG_ENABLE_MUST_CHECK=y
1136# CONFIG_MAGIC_SYSRQ is not set
1137# CONFIG_UNUSED_SYMBOLS is not set
1138# CONFIG_DEBUG_FS is not set
1139# CONFIG_HEADERS_CHECK is not set
1140# CONFIG_DEBUG_KERNEL is not set
1141CONFIG_DEBUG_BUGVERBOSE=y
1142CONFIG_FRAME_POINTER=y
1143# CONFIG_SAMPLES is not set
1144# CONFIG_DEBUG_USER is not set
1145
1146#
1147# Security options
1148#
1149# CONFIG_KEYS is not set
1150# CONFIG_SECURITY is not set
1151# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1152# CONFIG_CRYPTO is not set
1153
1154#
1155# Library routines
1156#
1157CONFIG_BITREVERSE=y
1158# CONFIG_CRC_CCITT is not set
1159# CONFIG_CRC16 is not set
1160# CONFIG_CRC_ITU_T is not set
1161CONFIG_CRC32=y
1162# CONFIG_CRC7 is not set
1163# CONFIG_LIBCRC32C is not set
1164CONFIG_ZLIB_INFLATE=y
1165CONFIG_ZLIB_DEFLATE=y
1166CONFIG_PLIST=y
1167CONFIG_HAS_IOMEM=y
1168CONFIG_HAS_IOPORT=y
diff --git a/arch/arm/configs/at91sam9rlek_defconfig b/arch/arm/configs/at91sam9rlek_defconfig
index 98e6746d02be..d8ec5f9ca6ec 100644
--- a/arch/arm/configs/at91sam9rlek_defconfig
+++ b/arch/arm/configs/at91sam9rlek_defconfig
@@ -211,7 +211,6 @@ CONFIG_CPU_CP15_MMU=y
211# 211#
212# CONFIG_TICK_ONESHOT is not set 212# CONFIG_TICK_ONESHOT is not set
213# CONFIG_PREEMPT is not set 213# CONFIG_PREEMPT is not set
214# CONFIG_NO_IDLE_HZ is not set
215CONFIG_HZ=100 214CONFIG_HZ=100
216# CONFIG_AEABI is not set 215# CONFIG_AEABI is not set
217# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 216# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ateb9200_defconfig b/arch/arm/configs/ateb9200_defconfig
index d846a492e5ce..85c80f723d8e 100644
--- a/arch/arm/configs/ateb9200_defconfig
+++ b/arch/arm/configs/ateb9200_defconfig
@@ -171,7 +171,6 @@ CONFIG_AT91_CF=m
171# Kernel Features 171# Kernel Features
172# 172#
173CONFIG_PREEMPT=y 173CONFIG_PREEMPT=y
174CONFIG_NO_IDLE_HZ=y
175CONFIG_HZ=100 174CONFIG_HZ=100
176# CONFIG_AEABI is not set 175# CONFIG_AEABI is not set
177# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 176# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/cm_x270_defconfig b/arch/arm/configs/cm_x270_defconfig
index 5cab08397ae7..33b201c3b309 100644
--- a/arch/arm/configs/cm_x270_defconfig
+++ b/arch/arm/configs/cm_x270_defconfig
@@ -194,7 +194,6 @@ CONFIG_PCI_HOST_ITE8152=y
194# 194#
195# CONFIG_TICK_ONESHOT is not set 195# CONFIG_TICK_ONESHOT is not set
196# CONFIG_PREEMPT is not set 196# CONFIG_PREEMPT is not set
197# CONFIG_NO_IDLE_HZ is not set
198CONFIG_HZ=100 197CONFIG_HZ=100
199# CONFIG_AEABI is not set 198# CONFIG_AEABI is not set
200# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 199# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
index 4264e273202d..f7622e658163 100644
--- a/arch/arm/configs/collie_defconfig
+++ b/arch/arm/configs/collie_defconfig
@@ -166,7 +166,6 @@ CONFIG_PCMCIA_SA1100=y
166# Kernel Features 166# Kernel Features
167# 167#
168# CONFIG_PREEMPT is not set 168# CONFIG_PREEMPT is not set
169# CONFIG_NO_IDLE_HZ is not set
170CONFIG_HZ=100 169CONFIG_HZ=100
171# CONFIG_AEABI is not set 170# CONFIG_AEABI is not set
172CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 171CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig
index e8980a9bb893..9b8748a8d9dd 100644
--- a/arch/arm/configs/corgi_defconfig
+++ b/arch/arm/configs/corgi_defconfig
@@ -165,7 +165,6 @@ CONFIG_PCMCIA_PXA2XX=y
165# Kernel Features 165# Kernel Features
166# 166#
167CONFIG_PREEMPT=y 167CONFIG_PREEMPT=y
168# CONFIG_NO_IDLE_HZ is not set
169# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 168# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
170CONFIG_SELECT_MEMORY_MODEL=y 169CONFIG_SELECT_MEMORY_MODEL=y
171CONFIG_FLATMEM_MANUAL=y 170CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/ecbat91_defconfig b/arch/arm/configs/ecbat91_defconfig
index 90ed214e3673..cfeb817ad21a 100644
--- a/arch/arm/configs/ecbat91_defconfig
+++ b/arch/arm/configs/ecbat91_defconfig
@@ -230,7 +230,6 @@ CONFIG_AT91_CF=y
230# 230#
231# CONFIG_TICK_ONESHOT is not set 231# CONFIG_TICK_ONESHOT is not set
232CONFIG_PREEMPT=y 232CONFIG_PREEMPT=y
233# CONFIG_NO_IDLE_HZ is not set
234CONFIG_HZ=100 233CONFIG_HZ=100
235# CONFIG_AEABI is not set 234# CONFIG_AEABI is not set
236# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 235# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/em_x270_defconfig b/arch/arm/configs/em_x270_defconfig
index 6bea0901bdf0..d3114c23603b 100644
--- a/arch/arm/configs/em_x270_defconfig
+++ b/arch/arm/configs/em_x270_defconfig
@@ -197,7 +197,6 @@ CONFIG_XSCALE_PMU=y
197# 197#
198# CONFIG_TICK_ONESHOT is not set 198# CONFIG_TICK_ONESHOT is not set
199# CONFIG_PREEMPT is not set 199# CONFIG_PREEMPT is not set
200# CONFIG_NO_IDLE_HZ is not set
201CONFIG_HZ=100 200CONFIG_HZ=100
202CONFIG_AEABI=y 201CONFIG_AEABI=y
203CONFIG_OABI_COMPAT=y 202CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
index 24a701ab33e5..21aa013793c6 100644
--- a/arch/arm/configs/ep93xx_defconfig
+++ b/arch/arm/configs/ep93xx_defconfig
@@ -184,7 +184,6 @@ CONFIG_ARM_AMBA=y
184# Kernel Features 184# Kernel Features
185# 185#
186# CONFIG_PREEMPT is not set 186# CONFIG_PREEMPT is not set
187# CONFIG_NO_IDLE_HZ is not set
188CONFIG_HZ=100 187CONFIG_HZ=100
189# CONFIG_AEABI is not set 188# CONFIG_AEABI is not set
190# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 189# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig
index ed487b90dbed..493ecee24f94 100644
--- a/arch/arm/configs/eseries_pxa_defconfig
+++ b/arch/arm/configs/eseries_pxa_defconfig
@@ -251,7 +251,6 @@ CONFIG_PCMCIA_PXA2XX=m
251# Kernel Features 251# Kernel Features
252# 252#
253# CONFIG_PREEMPT is not set 253# CONFIG_PREEMPT is not set
254# CONFIG_NO_IDLE_HZ is not set
255CONFIG_HZ=100 254CONFIG_HZ=100
256CONFIG_AEABI=y 255CONFIG_AEABI=y
257CONFIG_OABI_COMPAT=y 256CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/iop13xx_defconfig b/arch/arm/configs/iop13xx_defconfig
index 988b4d13e76f..482e57061053 100644
--- a/arch/arm/configs/iop13xx_defconfig
+++ b/arch/arm/configs/iop13xx_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
197# 197#
198# CONFIG_TICK_ONESHOT is not set 198# CONFIG_TICK_ONESHOT is not set
199# CONFIG_PREEMPT is not set 199# CONFIG_PREEMPT is not set
200# CONFIG_NO_IDLE_HZ is not set
201CONFIG_HZ=100 200CONFIG_HZ=100
202# CONFIG_AEABI is not set 201# CONFIG_AEABI is not set
203# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 202# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig
index 83f40d4041a6..8612f58e1056 100644
--- a/arch/arm/configs/iop32x_defconfig
+++ b/arch/arm/configs/iop32x_defconfig
@@ -201,7 +201,6 @@ CONFIG_PCI_LEGACY=y
201# 201#
202# CONFIG_TICK_ONESHOT is not set 202# CONFIG_TICK_ONESHOT is not set
203# CONFIG_PREEMPT is not set 203# CONFIG_PREEMPT is not set
204# CONFIG_NO_IDLE_HZ is not set
205CONFIG_HZ=100 204CONFIG_HZ=100
206# CONFIG_AEABI is not set 205# CONFIG_AEABI is not set
207# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 206# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/iop33x_defconfig b/arch/arm/configs/iop33x_defconfig
index 917afb5ccfac..8b0098d19d08 100644
--- a/arch/arm/configs/iop33x_defconfig
+++ b/arch/arm/configs/iop33x_defconfig
@@ -197,7 +197,6 @@ CONFIG_PCI_LEGACY=y
197# 197#
198# CONFIG_TICK_ONESHOT is not set 198# CONFIG_TICK_ONESHOT is not set
199# CONFIG_PREEMPT is not set 199# CONFIG_PREEMPT is not set
200# CONFIG_NO_IDLE_HZ is not set
201CONFIG_HZ=100 200CONFIG_HZ=100
202# CONFIG_AEABI is not set 201# CONFIG_AEABI is not set
203# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 202# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp2000_defconfig b/arch/arm/configs/ixp2000_defconfig
index f8f9793b526f..84680db6c615 100644
--- a/arch/arm/configs/ixp2000_defconfig
+++ b/arch/arm/configs/ixp2000_defconfig
@@ -184,7 +184,6 @@ CONFIG_PCI=y
184# Kernel Features 184# Kernel Features
185# 185#
186# CONFIG_PREEMPT is not set 186# CONFIG_PREEMPT is not set
187# CONFIG_NO_IDLE_HZ is not set
188CONFIG_HZ=100 187CONFIG_HZ=100
189# CONFIG_AEABI is not set 188# CONFIG_AEABI is not set
190# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 189# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp23xx_defconfig b/arch/arm/configs/ixp23xx_defconfig
index 27cf022dd807..4a2f7b2372db 100644
--- a/arch/arm/configs/ixp23xx_defconfig
+++ b/arch/arm/configs/ixp23xx_defconfig
@@ -180,7 +180,6 @@ CONFIG_PCI=y
180# Kernel Features 180# Kernel Features
181# 181#
182# CONFIG_PREEMPT is not set 182# CONFIG_PREEMPT is not set
183# CONFIG_NO_IDLE_HZ is not set
184CONFIG_HZ=100 183CONFIG_HZ=100
185# CONFIG_AEABI is not set 184# CONFIG_AEABI is not set
186# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 185# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
index efa0485d2f7e..fc14932e3abd 100644
--- a/arch/arm/configs/ixp4xx_defconfig
+++ b/arch/arm/configs/ixp4xx_defconfig
@@ -165,6 +165,7 @@ CONFIG_ARCH_PRPMC1100=y
165CONFIG_MACH_NAS100D=y 165CONFIG_MACH_NAS100D=y
166CONFIG_MACH_DSMG600=y 166CONFIG_MACH_DSMG600=y
167CONFIG_ARCH_IXDP4XX=y 167CONFIG_ARCH_IXDP4XX=y
168CONFIG_MACH_FSG=y
168CONFIG_CPU_IXP46X=y 169CONFIG_CPU_IXP46X=y
169CONFIG_CPU_IXP43X=y 170CONFIG_CPU_IXP43X=y
170CONFIG_MACH_GTWX5715=y 171CONFIG_MACH_GTWX5715=y
@@ -770,7 +771,7 @@ CONFIG_ATA=y
770# CONFIG_SATA_SIL24 is not set 771# CONFIG_SATA_SIL24 is not set
771# CONFIG_SATA_SIS is not set 772# CONFIG_SATA_SIS is not set
772# CONFIG_SATA_ULI is not set 773# CONFIG_SATA_ULI is not set
773# CONFIG_SATA_VIA is not set 774CONFIG_SATA_VIA=y
774# CONFIG_SATA_VITESSE is not set 775# CONFIG_SATA_VITESSE is not set
775# CONFIG_SATA_INIC162X is not set 776# CONFIG_SATA_INIC162X is not set
776# CONFIG_PATA_ALI is not set 777# CONFIG_PATA_ALI is not set
@@ -1143,7 +1144,7 @@ CONFIG_HWMON=y
1143# CONFIG_SENSORS_VIA686A is not set 1144# CONFIG_SENSORS_VIA686A is not set
1144# CONFIG_SENSORS_VT1211 is not set 1145# CONFIG_SENSORS_VT1211 is not set
1145# CONFIG_SENSORS_VT8231 is not set 1146# CONFIG_SENSORS_VT8231 is not set
1146# CONFIG_SENSORS_W83781D is not set 1147CONFIG_SENSORS_W83781D=y
1147# CONFIG_SENSORS_W83791D is not set 1148# CONFIG_SENSORS_W83791D is not set
1148# CONFIG_SENSORS_W83792D is not set 1149# CONFIG_SENSORS_W83792D is not set
1149# CONFIG_SENSORS_W83793 is not set 1150# CONFIG_SENSORS_W83793 is not set
@@ -1334,8 +1335,8 @@ CONFIG_LEDS_CLASS=y
1334# 1335#
1335# LED drivers 1336# LED drivers
1336# 1337#
1337# CONFIG_LEDS_IXP4XX is not set
1338CONFIG_LEDS_GPIO=y 1338CONFIG_LEDS_GPIO=y
1339CONFIG_LEDS_FSG=y
1339 1340
1340# 1341#
1341# LED Triggers 1342# LED Triggers
@@ -1367,7 +1368,7 @@ CONFIG_RTC_INTF_DEV=y
1367# CONFIG_RTC_DRV_DS1672 is not set 1368# CONFIG_RTC_DRV_DS1672 is not set
1368# CONFIG_RTC_DRV_MAX6900 is not set 1369# CONFIG_RTC_DRV_MAX6900 is not set
1369# CONFIG_RTC_DRV_RS5C372 is not set 1370# CONFIG_RTC_DRV_RS5C372 is not set
1370# CONFIG_RTC_DRV_ISL1208 is not set 1371CONFIG_RTC_DRV_ISL1208=y
1371CONFIG_RTC_DRV_X1205=y 1372CONFIG_RTC_DRV_X1205=y
1372CONFIG_RTC_DRV_PCF8563=y 1373CONFIG_RTC_DRV_PCF8563=y
1373# CONFIG_RTC_DRV_PCF8583 is not set 1374# CONFIG_RTC_DRV_PCF8583 is not set
diff --git a/arch/arm/configs/kafa_defconfig b/arch/arm/configs/kafa_defconfig
index ae51a40db6f9..6dd95a2c8d5d 100644
--- a/arch/arm/configs/kafa_defconfig
+++ b/arch/arm/configs/kafa_defconfig
@@ -162,7 +162,6 @@ CONFIG_CPU_TLB_V4WBI=y
162# Kernel Features 162# Kernel Features
163# 163#
164CONFIG_PREEMPT=y 164CONFIG_PREEMPT=y
165# CONFIG_NO_IDLE_HZ is not set
166CONFIG_HZ=100 165CONFIG_HZ=100
167# CONFIG_AEABI is not set 166# CONFIG_AEABI is not set
168# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 167# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/kb9202_defconfig b/arch/arm/configs/kb9202_defconfig
index c16537d9d67a..8e74c66f239d 100644
--- a/arch/arm/configs/kb9202_defconfig
+++ b/arch/arm/configs/kb9202_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
126# 126#
127# Kernel Features 127# Kernel Features
128# 128#
129# CONFIG_NO_IDLE_HZ is not set
130# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 129# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
131CONFIG_FLATMEM=y 130CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 131CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
new file mode 100644
index 000000000000..e3357ba10f1f
--- /dev/null
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -0,0 +1,1426 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5
4# Sun Jun 22 15:51:25 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set
50# CONFIG_SYSFS_DEPRECATED_V2 is not set
51# CONFIG_RELAY is not set
52# CONFIG_NAMESPACES is not set
53# CONFIG_BLK_DEV_INITRD is not set
54CONFIG_CC_OPTIMIZE_FOR_SIZE=y
55CONFIG_SYSCTL=y
56CONFIG_EMBEDDED=y
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_SYSCTL_SYSCALL_CHECK=y
60CONFIG_KALLSYMS=y
61# CONFIG_KALLSYMS_ALL is not set
62# CONFIG_KALLSYMS_EXTRA_PASS is not set
63CONFIG_HOTPLUG=y
64CONFIG_PRINTK=y
65CONFIG_BUG=y
66CONFIG_ELF_CORE=y
67CONFIG_COMPAT_BRK=y
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_TIMERFD=y
74CONFIG_EVENTFD=y
75CONFIG_SHMEM=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80CONFIG_PROFILING=y
81# CONFIG_MARKERS is not set
82CONFIG_OPROFILE=y
83CONFIG_HAVE_OPROFILE=y
84CONFIG_KPROBES=y
85CONFIG_KRETPROBES=y
86CONFIG_HAVE_KPROBES=y
87CONFIG_HAVE_KRETPROBES=y
88# CONFIG_HAVE_DMA_ATTRS is not set
89CONFIG_PROC_PAGE_MONITOR=y
90CONFIG_SLABINFO=y
91CONFIG_RT_MUTEXES=y
92# CONFIG_TINY_SHMEM is not set
93CONFIG_BASE_SMALL=0
94CONFIG_MODULES=y
95# CONFIG_MODULE_FORCE_LOAD is not set
96CONFIG_MODULE_UNLOAD=y
97# CONFIG_MODULE_FORCE_UNLOAD is not set
98# CONFIG_MODVERSIONS is not set
99# CONFIG_MODULE_SRCVERSION_ALL is not set
100# CONFIG_KMOD is not set
101CONFIG_BLOCK=y
102# CONFIG_LBD is not set
103# CONFIG_BLK_DEV_IO_TRACE is not set
104# CONFIG_LSF is not set
105# CONFIG_BLK_DEV_BSG is not set
106
107#
108# IO Schedulers
109#
110CONFIG_IOSCHED_NOOP=y
111CONFIG_IOSCHED_AS=y
112CONFIG_IOSCHED_DEADLINE=y
113CONFIG_IOSCHED_CFQ=y
114# CONFIG_DEFAULT_AS is not set
115# CONFIG_DEFAULT_DEADLINE is not set
116CONFIG_DEFAULT_CFQ=y
117# CONFIG_DEFAULT_NOOP is not set
118CONFIG_DEFAULT_IOSCHED="cfq"
119CONFIG_CLASSIC_RCU=y
120
121#
122# System Type
123#
124# CONFIG_ARCH_AAEC2000 is not set
125# CONFIG_ARCH_INTEGRATOR is not set
126# CONFIG_ARCH_REALVIEW is not set
127# CONFIG_ARCH_VERSATILE is not set
128# CONFIG_ARCH_AT91 is not set
129# CONFIG_ARCH_CLPS7500 is not set
130# CONFIG_ARCH_CLPS711X is not set
131# CONFIG_ARCH_CO285 is not set
132# CONFIG_ARCH_EBSA110 is not set
133# CONFIG_ARCH_EP93XX is not set
134# CONFIG_ARCH_FOOTBRIDGE is not set
135# CONFIG_ARCH_NETX is not set
136# CONFIG_ARCH_H720X is not set
137# CONFIG_ARCH_IMX is not set
138# CONFIG_ARCH_IOP13XX is not set
139# CONFIG_ARCH_IOP32X is not set
140# CONFIG_ARCH_IOP33X is not set
141# CONFIG_ARCH_IXP23XX is not set
142# CONFIG_ARCH_IXP2000 is not set
143# CONFIG_ARCH_IXP4XX is not set
144# CONFIG_ARCH_L7200 is not set
145CONFIG_ARCH_KIRKWOOD=y
146# CONFIG_ARCH_KS8695 is not set
147# CONFIG_ARCH_NS9XXX is not set
148# CONFIG_ARCH_LOKI is not set
149# CONFIG_ARCH_MV78XX0 is not set
150# CONFIG_ARCH_MXC is not set
151# CONFIG_ARCH_ORION5X is not set
152# CONFIG_ARCH_PNX4008 is not set
153# CONFIG_ARCH_PXA is not set
154# CONFIG_ARCH_RPC is not set
155# CONFIG_ARCH_SA1100 is not set
156# CONFIG_ARCH_S3C2410 is not set
157# CONFIG_ARCH_SHARK is not set
158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set
160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
162
163#
164# Marvell Kirkwood Implementations
165#
166CONFIG_MACH_DB88F6281_BP=y
167CONFIG_MACH_RD88F6192_NAS=y
168CONFIG_MACH_RD88F6281=y
169
170#
171# Boot options
172#
173
174#
175# Power management
176#
177CONFIG_PLAT_ORION=y
178
179#
180# Processor Type
181#
182CONFIG_CPU_32=y
183CONFIG_CPU_FEROCEON=y
184# CONFIG_CPU_FEROCEON_OLD_ID is not set
185CONFIG_CPU_32v5=y
186CONFIG_CPU_ABRT_EV5T=y
187CONFIG_CPU_PABRT_NOIFAR=y
188CONFIG_CPU_CACHE_VIVT=y
189CONFIG_CPU_COPY_FEROCEON=y
190CONFIG_CPU_TLB_FEROCEON=y
191CONFIG_CPU_CP15=y
192CONFIG_CPU_CP15_MMU=y
193
194#
195# Processor Features
196#
197CONFIG_ARM_THUMB=y
198# CONFIG_CPU_ICACHE_DISABLE is not set
199# CONFIG_CPU_DCACHE_DISABLE is not set
200CONFIG_OUTER_CACHE=y
201CONFIG_CACHE_FEROCEON_L2=y
202
203#
204# Bus support
205#
206CONFIG_PCI=y
207CONFIG_PCI_SYSCALL=y
208# CONFIG_ARCH_SUPPORTS_MSI is not set
209CONFIG_PCI_LEGACY=y
210# CONFIG_PCI_DEBUG is not set
211# CONFIG_PCCARD is not set
212
213#
214# Kernel Features
215#
216CONFIG_TICK_ONESHOT=y
217CONFIG_NO_HZ=y
218CONFIG_HIGH_RES_TIMERS=y
219CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
220CONFIG_PREEMPT=y
221CONFIG_HZ=100
222CONFIG_AEABI=y
223# CONFIG_OABI_COMPAT is not set
224# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
225CONFIG_SELECT_MEMORY_MODEL=y
226CONFIG_FLATMEM_MANUAL=y
227# CONFIG_DISCONTIGMEM_MANUAL is not set
228# CONFIG_SPARSEMEM_MANUAL is not set
229CONFIG_FLATMEM=y
230CONFIG_FLAT_NODE_MEM_MAP=y
231# CONFIG_SPARSEMEM_STATIC is not set
232# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
233CONFIG_PAGEFLAGS_EXTENDED=y
234CONFIG_SPLIT_PTLOCK_CPUS=4096
235# CONFIG_RESOURCES_64BIT is not set
236CONFIG_ZONE_DMA_FLAG=1
237CONFIG_BOUNCE=y
238CONFIG_VIRT_TO_BUS=y
239CONFIG_ALIGNMENT_TRAP=y
240
241#
242# Boot options
243#
244CONFIG_ZBOOT_ROM_TEXT=0x0
245CONFIG_ZBOOT_ROM_BSS=0x0
246CONFIG_CMDLINE=""
247# CONFIG_XIP_KERNEL is not set
248# CONFIG_KEXEC is not set
249
250#
251# Floating point emulation
252#
253
254#
255# At least one emulation must be selected
256#
257# CONFIG_VFP is not set
258
259#
260# Userspace binary formats
261#
262CONFIG_BINFMT_ELF=y
263# CONFIG_BINFMT_AOUT is not set
264# CONFIG_BINFMT_MISC is not set
265
266#
267# Power management options
268#
269# CONFIG_PM is not set
270CONFIG_ARCH_SUSPEND_POSSIBLE=y
271
272#
273# Networking
274#
275CONFIG_NET=y
276
277#
278# Networking options
279#
280CONFIG_PACKET=y
281CONFIG_PACKET_MMAP=y
282CONFIG_UNIX=y
283CONFIG_XFRM=y
284# CONFIG_XFRM_USER is not set
285# CONFIG_XFRM_SUB_POLICY is not set
286# CONFIG_XFRM_MIGRATE is not set
287# CONFIG_XFRM_STATISTICS is not set
288# CONFIG_NET_KEY is not set
289CONFIG_INET=y
290CONFIG_IP_MULTICAST=y
291# CONFIG_IP_ADVANCED_ROUTER is not set
292CONFIG_IP_FIB_HASH=y
293CONFIG_IP_PNP=y
294CONFIG_IP_PNP_DHCP=y
295CONFIG_IP_PNP_BOOTP=y
296# CONFIG_IP_PNP_RARP is not set
297# CONFIG_NET_IPIP is not set
298# CONFIG_NET_IPGRE is not set
299# CONFIG_IP_MROUTE is not set
300# CONFIG_ARPD is not set
301# CONFIG_SYN_COOKIES is not set
302# CONFIG_INET_AH is not set
303# CONFIG_INET_ESP is not set
304# CONFIG_INET_IPCOMP is not set
305# CONFIG_INET_XFRM_TUNNEL is not set
306# CONFIG_INET_TUNNEL is not set
307CONFIG_INET_XFRM_MODE_TRANSPORT=y
308CONFIG_INET_XFRM_MODE_TUNNEL=y
309CONFIG_INET_XFRM_MODE_BEET=y
310# CONFIG_INET_LRO is not set
311CONFIG_INET_DIAG=y
312CONFIG_INET_TCP_DIAG=y
313# CONFIG_TCP_CONG_ADVANCED is not set
314CONFIG_TCP_CONG_CUBIC=y
315CONFIG_DEFAULT_TCP_CONG="cubic"
316# CONFIG_TCP_MD5SIG is not set
317# CONFIG_IPV6 is not set
318# CONFIG_NETWORK_SECMARK is not set
319# CONFIG_NETFILTER is not set
320# CONFIG_IP_DCCP is not set
321# CONFIG_IP_SCTP is not set
322# CONFIG_TIPC is not set
323# CONFIG_ATM is not set
324# CONFIG_BRIDGE is not set
325# CONFIG_VLAN_8021Q is not set
326# CONFIG_DECNET is not set
327# CONFIG_LLC2 is not set
328# CONFIG_IPX is not set
329# CONFIG_ATALK is not set
330# CONFIG_X25 is not set
331# CONFIG_LAPB is not set
332# CONFIG_ECONET is not set
333# CONFIG_WAN_ROUTER is not set
334# CONFIG_NET_SCHED is not set
335
336#
337# Network testing
338#
339CONFIG_NET_PKTGEN=m
340# CONFIG_NET_TCPPROBE is not set
341# CONFIG_HAMRADIO is not set
342# CONFIG_CAN is not set
343# CONFIG_IRDA is not set
344# CONFIG_BT is not set
345# CONFIG_AF_RXRPC is not set
346
347#
348# Wireless
349#
350# CONFIG_CFG80211 is not set
351CONFIG_WIRELESS_EXT=y
352# CONFIG_MAC80211 is not set
353# CONFIG_IEEE80211 is not set
354# CONFIG_RFKILL is not set
355# CONFIG_NET_9P is not set
356
357#
358# Device Drivers
359#
360
361#
362# Generic Driver Options
363#
364CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
365CONFIG_STANDALONE=y
366CONFIG_PREVENT_FIRMWARE_BUILD=y
367CONFIG_FW_LOADER=y
368# CONFIG_DEBUG_DRIVER is not set
369# CONFIG_DEBUG_DEVRES is not set
370# CONFIG_SYS_HYPERVISOR is not set
371# CONFIG_CONNECTOR is not set
372CONFIG_MTD=y
373# CONFIG_MTD_DEBUG is not set
374# CONFIG_MTD_CONCAT is not set
375CONFIG_MTD_PARTITIONS=y
376# CONFIG_MTD_REDBOOT_PARTS is not set
377CONFIG_MTD_CMDLINE_PARTS=y
378# CONFIG_MTD_AFS_PARTS is not set
379# CONFIG_MTD_AR7_PARTS is not set
380
381#
382# User Modules And Translation Layers
383#
384CONFIG_MTD_CHAR=y
385CONFIG_MTD_BLKDEVS=y
386CONFIG_MTD_BLOCK=y
387# CONFIG_FTL is not set
388# CONFIG_NFTL is not set
389# CONFIG_INFTL is not set
390# CONFIG_RFD_FTL is not set
391# CONFIG_SSFDC is not set
392# CONFIG_MTD_OOPS is not set
393
394#
395# RAM/ROM/Flash chip drivers
396#
397CONFIG_MTD_CFI=y
398CONFIG_MTD_JEDECPROBE=y
399CONFIG_MTD_GEN_PROBE=y
400CONFIG_MTD_CFI_ADV_OPTIONS=y
401CONFIG_MTD_CFI_NOSWAP=y
402# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
403# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
404CONFIG_MTD_CFI_GEOMETRY=y
405CONFIG_MTD_MAP_BANK_WIDTH_1=y
406CONFIG_MTD_MAP_BANK_WIDTH_2=y
407# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
408# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
409# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
410# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
411CONFIG_MTD_CFI_I1=y
412CONFIG_MTD_CFI_I2=y
413# CONFIG_MTD_CFI_I4 is not set
414# CONFIG_MTD_CFI_I8 is not set
415# CONFIG_MTD_OTP is not set
416CONFIG_MTD_CFI_INTELEXT=y
417# CONFIG_MTD_CFI_AMDSTD is not set
418CONFIG_MTD_CFI_STAA=y
419CONFIG_MTD_CFI_UTIL=y
420# CONFIG_MTD_RAM is not set
421# CONFIG_MTD_ROM is not set
422# CONFIG_MTD_ABSENT is not set
423
424#
425# Mapping drivers for chip access
426#
427# CONFIG_MTD_COMPLEX_MAPPINGS is not set
428CONFIG_MTD_PHYSMAP=y
429CONFIG_MTD_PHYSMAP_START=0x0
430CONFIG_MTD_PHYSMAP_LEN=0x0
431CONFIG_MTD_PHYSMAP_BANKWIDTH=0
432# CONFIG_MTD_ARM_INTEGRATOR is not set
433# CONFIG_MTD_IMPA7 is not set
434# CONFIG_MTD_INTEL_VR_NOR is not set
435# CONFIG_MTD_PLATRAM is not set
436
437#
438# Self-contained MTD device drivers
439#
440# CONFIG_MTD_PMC551 is not set
441# CONFIG_MTD_DATAFLASH is not set
442CONFIG_MTD_M25P80=y
443CONFIG_M25PXX_USE_FAST_READ=y
444# CONFIG_MTD_SLRAM is not set
445# CONFIG_MTD_PHRAM is not set
446# CONFIG_MTD_MTDRAM is not set
447# CONFIG_MTD_BLOCK2MTD is not set
448
449#
450# Disk-On-Chip Device Drivers
451#
452# CONFIG_MTD_DOC2000 is not set
453# CONFIG_MTD_DOC2001 is not set
454# CONFIG_MTD_DOC2001PLUS is not set
455CONFIG_MTD_NAND=y
456CONFIG_MTD_NAND_VERIFY_WRITE=y
457# CONFIG_MTD_NAND_ECC_SMC is not set
458# CONFIG_MTD_NAND_MUSEUM_IDS is not set
459CONFIG_MTD_NAND_IDS=y
460# CONFIG_MTD_NAND_DISKONCHIP is not set
461# CONFIG_MTD_NAND_CAFE is not set
462# CONFIG_MTD_NAND_NANDSIM is not set
463# CONFIG_MTD_NAND_PLATFORM is not set
464# CONFIG_MTD_ALAUDA is not set
465CONFIG_MTD_NAND_ORION=y
466# CONFIG_MTD_ONENAND is not set
467
468#
469# UBI - Unsorted block images
470#
471# CONFIG_MTD_UBI is not set
472# CONFIG_PARPORT is not set
473CONFIG_BLK_DEV=y
474# CONFIG_BLK_CPQ_DA is not set
475# CONFIG_BLK_CPQ_CISS_DA is not set
476# CONFIG_BLK_DEV_DAC960 is not set
477# CONFIG_BLK_DEV_UMEM is not set
478# CONFIG_BLK_DEV_COW_COMMON is not set
479CONFIG_BLK_DEV_LOOP=y
480# CONFIG_BLK_DEV_CRYPTOLOOP is not set
481# CONFIG_BLK_DEV_NBD is not set
482# CONFIG_BLK_DEV_SX8 is not set
483# CONFIG_BLK_DEV_UB is not set
484# CONFIG_BLK_DEV_RAM is not set
485# CONFIG_CDROM_PKTCDVD is not set
486# CONFIG_ATA_OVER_ETH is not set
487# CONFIG_MISC_DEVICES is not set
488CONFIG_HAVE_IDE=y
489# CONFIG_IDE is not set
490
491#
492# SCSI device support
493#
494# CONFIG_RAID_ATTRS is not set
495CONFIG_SCSI=y
496CONFIG_SCSI_DMA=y
497# CONFIG_SCSI_TGT is not set
498# CONFIG_SCSI_NETLINK is not set
499# CONFIG_SCSI_PROC_FS is not set
500
501#
502# SCSI support type (disk, tape, CD-ROM)
503#
504CONFIG_BLK_DEV_SD=y
505# CONFIG_CHR_DEV_ST is not set
506# CONFIG_CHR_DEV_OSST is not set
507CONFIG_BLK_DEV_SR=m
508# CONFIG_BLK_DEV_SR_VENDOR is not set
509CONFIG_CHR_DEV_SG=m
510# CONFIG_CHR_DEV_SCH is not set
511
512#
513# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
514#
515# CONFIG_SCSI_MULTI_LUN is not set
516# CONFIG_SCSI_CONSTANTS is not set
517# CONFIG_SCSI_LOGGING is not set
518# CONFIG_SCSI_SCAN_ASYNC is not set
519CONFIG_SCSI_WAIT_SCAN=m
520
521#
522# SCSI Transports
523#
524# CONFIG_SCSI_SPI_ATTRS is not set
525# CONFIG_SCSI_FC_ATTRS is not set
526# CONFIG_SCSI_ISCSI_ATTRS is not set
527# CONFIG_SCSI_SAS_LIBSAS is not set
528# CONFIG_SCSI_SRP_ATTRS is not set
529CONFIG_SCSI_LOWLEVEL=y
530# CONFIG_ISCSI_TCP is not set
531# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
532# CONFIG_SCSI_3W_9XXX is not set
533# CONFIG_SCSI_ACARD is not set
534# CONFIG_SCSI_AACRAID is not set
535# CONFIG_SCSI_AIC7XXX is not set
536# CONFIG_SCSI_AIC7XXX_OLD is not set
537# CONFIG_SCSI_AIC79XX is not set
538# CONFIG_SCSI_AIC94XX is not set
539# CONFIG_SCSI_DPT_I2O is not set
540# CONFIG_SCSI_ADVANSYS is not set
541# CONFIG_SCSI_ARCMSR is not set
542# CONFIG_MEGARAID_NEWGEN is not set
543# CONFIG_MEGARAID_LEGACY is not set
544# CONFIG_MEGARAID_SAS is not set
545# CONFIG_SCSI_HPTIOP is not set
546# CONFIG_SCSI_DMX3191D is not set
547# CONFIG_SCSI_FUTURE_DOMAIN is not set
548# CONFIG_SCSI_IPS is not set
549# CONFIG_SCSI_INITIO is not set
550# CONFIG_SCSI_INIA100 is not set
551# CONFIG_SCSI_MVSAS is not set
552# CONFIG_SCSI_STEX is not set
553# CONFIG_SCSI_SYM53C8XX_2 is not set
554# CONFIG_SCSI_IPR is not set
555# CONFIG_SCSI_QLOGIC_1280 is not set
556# CONFIG_SCSI_QLA_FC is not set
557# CONFIG_SCSI_QLA_ISCSI is not set
558# CONFIG_SCSI_LPFC is not set
559# CONFIG_SCSI_DC395x is not set
560# CONFIG_SCSI_DC390T is not set
561# CONFIG_SCSI_NSP32 is not set
562# CONFIG_SCSI_DEBUG is not set
563# CONFIG_SCSI_SRP is not set
564CONFIG_ATA=y
565# CONFIG_ATA_NONSTANDARD is not set
566CONFIG_SATA_PMP=y
567# CONFIG_SATA_AHCI is not set
568# CONFIG_SATA_SIL24 is not set
569CONFIG_ATA_SFF=y
570# CONFIG_SATA_SVW is not set
571# CONFIG_ATA_PIIX is not set
572CONFIG_SATA_MV=y
573# CONFIG_SATA_NV is not set
574# CONFIG_PDC_ADMA is not set
575# CONFIG_SATA_QSTOR is not set
576# CONFIG_SATA_PROMISE is not set
577# CONFIG_SATA_SX4 is not set
578# CONFIG_SATA_SIL is not set
579# CONFIG_SATA_SIS is not set
580# CONFIG_SATA_ULI is not set
581# CONFIG_SATA_VIA is not set
582# CONFIG_SATA_VITESSE is not set
583# CONFIG_SATA_INIC162X is not set
584# CONFIG_PATA_ALI is not set
585# CONFIG_PATA_AMD is not set
586# CONFIG_PATA_ARTOP is not set
587# CONFIG_PATA_ATIIXP is not set
588# CONFIG_PATA_CMD640_PCI is not set
589# CONFIG_PATA_CMD64X is not set
590# CONFIG_PATA_CS5520 is not set
591# CONFIG_PATA_CS5530 is not set
592# CONFIG_PATA_CYPRESS is not set
593# CONFIG_PATA_EFAR is not set
594# CONFIG_ATA_GENERIC is not set
595# CONFIG_PATA_HPT366 is not set
596# CONFIG_PATA_HPT37X is not set
597# CONFIG_PATA_HPT3X2N is not set
598# CONFIG_PATA_HPT3X3 is not set
599# CONFIG_PATA_IT821X is not set
600# CONFIG_PATA_IT8213 is not set
601# CONFIG_PATA_JMICRON is not set
602# CONFIG_PATA_TRIFLEX is not set
603# CONFIG_PATA_MARVELL is not set
604# CONFIG_PATA_MPIIX is not set
605# CONFIG_PATA_OLDPIIX is not set
606# CONFIG_PATA_NETCELL is not set
607# CONFIG_PATA_NINJA32 is not set
608# CONFIG_PATA_NS87410 is not set
609# CONFIG_PATA_NS87415 is not set
610# CONFIG_PATA_OPTI is not set
611# CONFIG_PATA_OPTIDMA is not set
612# CONFIG_PATA_PDC_OLD is not set
613# CONFIG_PATA_RADISYS is not set
614# CONFIG_PATA_RZ1000 is not set
615# CONFIG_PATA_SC1200 is not set
616# CONFIG_PATA_SERVERWORKS is not set
617# CONFIG_PATA_PDC2027X is not set
618# CONFIG_PATA_SIL680 is not set
619# CONFIG_PATA_SIS is not set
620# CONFIG_PATA_VIA is not set
621# CONFIG_PATA_WINBOND is not set
622# CONFIG_PATA_PLATFORM is not set
623# CONFIG_PATA_SCH is not set
624# CONFIG_MD is not set
625# CONFIG_FUSION is not set
626
627#
628# IEEE 1394 (FireWire) support
629#
630# CONFIG_FIREWIRE is not set
631# CONFIG_IEEE1394 is not set
632# CONFIG_I2O is not set
633CONFIG_NETDEVICES=y
634# CONFIG_NETDEVICES_MULTIQUEUE is not set
635# CONFIG_DUMMY is not set
636# CONFIG_BONDING is not set
637# CONFIG_MACVLAN is not set
638# CONFIG_EQUALIZER is not set
639# CONFIG_TUN is not set
640# CONFIG_VETH is not set
641# CONFIG_ARCNET is not set
642# CONFIG_PHYLIB is not set
643CONFIG_NET_ETHERNET=y
644CONFIG_MII=y
645# CONFIG_AX88796 is not set
646# CONFIG_HAPPYMEAL is not set
647# CONFIG_SUNGEM is not set
648# CONFIG_CASSINI is not set
649# CONFIG_NET_VENDOR_3COM is not set
650# CONFIG_SMC91X is not set
651# CONFIG_DM9000 is not set
652# CONFIG_ENC28J60 is not set
653# CONFIG_NET_TULIP is not set
654# CONFIG_HP100 is not set
655# CONFIG_IBM_NEW_EMAC_ZMII is not set
656# CONFIG_IBM_NEW_EMAC_RGMII is not set
657# CONFIG_IBM_NEW_EMAC_TAH is not set
658# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
659CONFIG_NET_PCI=y
660# CONFIG_PCNET32 is not set
661# CONFIG_AMD8111_ETH is not set
662# CONFIG_ADAPTEC_STARFIRE is not set
663# CONFIG_B44 is not set
664# CONFIG_FORCEDETH is not set
665# CONFIG_EEPRO100 is not set
666# CONFIG_E100 is not set
667# CONFIG_FEALNX is not set
668# CONFIG_NATSEMI is not set
669# CONFIG_NE2K_PCI is not set
670# CONFIG_8139CP is not set
671# CONFIG_8139TOO is not set
672# CONFIG_R6040 is not set
673# CONFIG_SIS900 is not set
674# CONFIG_EPIC100 is not set
675# CONFIG_SUNDANCE is not set
676# CONFIG_TLAN is not set
677# CONFIG_VIA_RHINE is not set
678# CONFIG_SC92031 is not set
679CONFIG_NETDEV_1000=y
680# CONFIG_ACENIC is not set
681# CONFIG_DL2K is not set
682CONFIG_E1000=y
683CONFIG_E1000_NAPI=y
684# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
685# CONFIG_E1000E is not set
686# CONFIG_E1000E_ENABLED is not set
687# CONFIG_IP1000 is not set
688# CONFIG_IGB is not set
689# CONFIG_NS83820 is not set
690# CONFIG_HAMACHI is not set
691# CONFIG_YELLOWFIN is not set
692# CONFIG_R8169 is not set
693# CONFIG_SIS190 is not set
694# CONFIG_SKGE is not set
695# CONFIG_SKY2 is not set
696# CONFIG_VIA_VELOCITY is not set
697# CONFIG_TIGON3 is not set
698# CONFIG_BNX2 is not set
699CONFIG_MV643XX_ETH=y
700# CONFIG_QLA3XXX is not set
701# CONFIG_ATL1 is not set
702# CONFIG_NETDEV_10000 is not set
703# CONFIG_TR is not set
704
705#
706# Wireless LAN
707#
708# CONFIG_WLAN_PRE80211 is not set
709# CONFIG_WLAN_80211 is not set
710# CONFIG_IWLWIFI_LEDS is not set
711
712#
713# USB Network Adapters
714#
715# CONFIG_USB_CATC is not set
716# CONFIG_USB_KAWETH is not set
717# CONFIG_USB_PEGASUS is not set
718# CONFIG_USB_RTL8150 is not set
719# CONFIG_USB_USBNET is not set
720# CONFIG_WAN is not set
721# CONFIG_FDDI is not set
722# CONFIG_HIPPI is not set
723# CONFIG_PPP is not set
724# CONFIG_SLIP is not set
725# CONFIG_NET_FC is not set
726# CONFIG_NETCONSOLE is not set
727# CONFIG_NETPOLL is not set
728# CONFIG_NET_POLL_CONTROLLER is not set
729# CONFIG_ISDN is not set
730
731#
732# Input device support
733#
734CONFIG_INPUT=y
735# CONFIG_INPUT_FF_MEMLESS is not set
736# CONFIG_INPUT_POLLDEV is not set
737
738#
739# Userland interfaces
740#
741CONFIG_INPUT_MOUSEDEV=y
742CONFIG_INPUT_MOUSEDEV_PSAUX=y
743CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
744CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
745# CONFIG_INPUT_JOYDEV is not set
746# CONFIG_INPUT_EVDEV is not set
747# CONFIG_INPUT_EVBUG is not set
748
749#
750# Input Device Drivers
751#
752# CONFIG_INPUT_KEYBOARD is not set
753# CONFIG_INPUT_MOUSE is not set
754# CONFIG_INPUT_JOYSTICK is not set
755# CONFIG_INPUT_TABLET is not set
756# CONFIG_INPUT_TOUCHSCREEN is not set
757# CONFIG_INPUT_MISC is not set
758
759#
760# Hardware I/O ports
761#
762# CONFIG_SERIO is not set
763# CONFIG_GAMEPORT is not set
764
765#
766# Character devices
767#
768# CONFIG_VT is not set
769# CONFIG_DEVKMEM is not set
770# CONFIG_SERIAL_NONSTANDARD is not set
771# CONFIG_NOZOMI is not set
772
773#
774# Serial drivers
775#
776CONFIG_SERIAL_8250=y
777CONFIG_SERIAL_8250_CONSOLE=y
778# CONFIG_SERIAL_8250_PCI is not set
779CONFIG_SERIAL_8250_NR_UARTS=4
780CONFIG_SERIAL_8250_RUNTIME_UARTS=2
781# CONFIG_SERIAL_8250_EXTENDED is not set
782
783#
784# Non-8250 serial port support
785#
786CONFIG_SERIAL_CORE=y
787CONFIG_SERIAL_CORE_CONSOLE=y
788# CONFIG_SERIAL_JSM is not set
789CONFIG_UNIX98_PTYS=y
790CONFIG_LEGACY_PTYS=y
791CONFIG_LEGACY_PTY_COUNT=16
792# CONFIG_IPMI_HANDLER is not set
793# CONFIG_HW_RANDOM is not set
794# CONFIG_NVRAM is not set
795# CONFIG_R3964 is not set
796# CONFIG_APPLICOM is not set
797# CONFIG_RAW_DRIVER is not set
798# CONFIG_TCG_TPM is not set
799CONFIG_DEVPORT=y
800CONFIG_I2C=y
801CONFIG_I2C_BOARDINFO=y
802CONFIG_I2C_CHARDEV=y
803
804#
805# I2C Hardware Bus support
806#
807# CONFIG_I2C_ALI1535 is not set
808# CONFIG_I2C_ALI1563 is not set
809# CONFIG_I2C_ALI15X3 is not set
810# CONFIG_I2C_AMD756 is not set
811# CONFIG_I2C_AMD8111 is not set
812# CONFIG_I2C_GPIO is not set
813# CONFIG_I2C_I801 is not set
814# CONFIG_I2C_I810 is not set
815# CONFIG_I2C_PIIX4 is not set
816# CONFIG_I2C_NFORCE2 is not set
817# CONFIG_I2C_OCORES is not set
818# CONFIG_I2C_PARPORT_LIGHT is not set
819# CONFIG_I2C_PROSAVAGE is not set
820# CONFIG_I2C_SAVAGE4 is not set
821# CONFIG_I2C_SIMTEC is not set
822# CONFIG_I2C_SIS5595 is not set
823# CONFIG_I2C_SIS630 is not set
824# CONFIG_I2C_SIS96X is not set
825# CONFIG_I2C_TAOS_EVM is not set
826# CONFIG_I2C_STUB is not set
827# CONFIG_I2C_TINY_USB is not set
828# CONFIG_I2C_VIA is not set
829# CONFIG_I2C_VIAPRO is not set
830# CONFIG_I2C_VOODOO3 is not set
831# CONFIG_I2C_PCA_PLATFORM is not set
832CONFIG_I2C_MV64XXX=y
833
834#
835# Miscellaneous I2C Chip support
836#
837# CONFIG_DS1682 is not set
838# CONFIG_SENSORS_EEPROM is not set
839# CONFIG_SENSORS_PCF8574 is not set
840# CONFIG_PCF8575 is not set
841# CONFIG_SENSORS_PCF8591 is not set
842# CONFIG_SENSORS_MAX6875 is not set
843# CONFIG_SENSORS_TSL2550 is not set
844# CONFIG_I2C_DEBUG_CORE is not set
845# CONFIG_I2C_DEBUG_ALGO is not set
846# CONFIG_I2C_DEBUG_BUS is not set
847# CONFIG_I2C_DEBUG_CHIP is not set
848CONFIG_SPI=y
849# CONFIG_SPI_DEBUG is not set
850CONFIG_SPI_MASTER=y
851
852#
853# SPI Master Controller Drivers
854#
855# CONFIG_SPI_BITBANG is not set
856CONFIG_SPI_ORION=y
857
858#
859# SPI Protocol Masters
860#
861# CONFIG_SPI_AT25 is not set
862# CONFIG_SPI_SPIDEV is not set
863# CONFIG_SPI_TLE62X0 is not set
864# CONFIG_W1 is not set
865# CONFIG_POWER_SUPPLY is not set
866# CONFIG_HWMON is not set
867# CONFIG_WATCHDOG is not set
868
869#
870# Sonics Silicon Backplane
871#
872CONFIG_SSB_POSSIBLE=y
873# CONFIG_SSB is not set
874
875#
876# Multifunction device drivers
877#
878# CONFIG_MFD_SM501 is not set
879# CONFIG_MFD_ASIC3 is not set
880# CONFIG_HTC_PASIC3 is not set
881
882#
883# Multimedia devices
884#
885
886#
887# Multimedia core support
888#
889# CONFIG_VIDEO_DEV is not set
890# CONFIG_DVB_CORE is not set
891# CONFIG_VIDEO_MEDIA is not set
892
893#
894# Multimedia drivers
895#
896# CONFIG_DAB is not set
897
898#
899# Graphics support
900#
901# CONFIG_DRM is not set
902# CONFIG_VGASTATE is not set
903# CONFIG_VIDEO_OUTPUT_CONTROL is not set
904# CONFIG_FB is not set
905# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
906
907#
908# Display device support
909#
910# CONFIG_DISPLAY_SUPPORT is not set
911
912#
913# Sound
914#
915# CONFIG_SOUND is not set
916CONFIG_HID_SUPPORT=y
917CONFIG_HID=y
918# CONFIG_HID_DEBUG is not set
919# CONFIG_HIDRAW is not set
920
921#
922# USB Input Devices
923#
924CONFIG_USB_HID=y
925# CONFIG_USB_HIDINPUT_POWERBOOK is not set
926# CONFIG_HID_FF is not set
927# CONFIG_USB_HIDDEV is not set
928CONFIG_USB_SUPPORT=y
929CONFIG_USB_ARCH_HAS_HCD=y
930CONFIG_USB_ARCH_HAS_OHCI=y
931CONFIG_USB_ARCH_HAS_EHCI=y
932CONFIG_USB=y
933# CONFIG_USB_DEBUG is not set
934# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
935
936#
937# Miscellaneous USB options
938#
939CONFIG_USB_DEVICEFS=y
940CONFIG_USB_DEVICE_CLASS=y
941# CONFIG_USB_DYNAMIC_MINORS is not set
942# CONFIG_USB_OTG is not set
943# CONFIG_USB_OTG_WHITELIST is not set
944# CONFIG_USB_OTG_BLACKLIST_HUB is not set
945
946#
947# USB Host Controller Drivers
948#
949# CONFIG_USB_C67X00_HCD is not set
950CONFIG_USB_EHCI_HCD=y
951CONFIG_USB_EHCI_ROOT_HUB_TT=y
952CONFIG_USB_EHCI_TT_NEWSCHED=y
953# CONFIG_USB_ISP116X_HCD is not set
954# CONFIG_USB_ISP1760_HCD is not set
955# CONFIG_USB_OHCI_HCD is not set
956# CONFIG_USB_UHCI_HCD is not set
957# CONFIG_USB_SL811_HCD is not set
958# CONFIG_USB_R8A66597_HCD is not set
959
960#
961# USB Device Class drivers
962#
963# CONFIG_USB_ACM is not set
964CONFIG_USB_PRINTER=y
965# CONFIG_USB_WDM is not set
966
967#
968# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
969#
970
971#
972# may also be needed; see USB_STORAGE Help for more information
973#
974CONFIG_USB_STORAGE=y
975# CONFIG_USB_STORAGE_DEBUG is not set
976CONFIG_USB_STORAGE_DATAFAB=y
977CONFIG_USB_STORAGE_FREECOM=y
978# CONFIG_USB_STORAGE_ISD200 is not set
979CONFIG_USB_STORAGE_DPCM=y
980# CONFIG_USB_STORAGE_USBAT is not set
981CONFIG_USB_STORAGE_SDDR09=y
982CONFIG_USB_STORAGE_SDDR55=y
983CONFIG_USB_STORAGE_JUMPSHOT=y
984# CONFIG_USB_STORAGE_ALAUDA is not set
985# CONFIG_USB_STORAGE_ONETOUCH is not set
986# CONFIG_USB_STORAGE_KARMA is not set
987# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
988# CONFIG_USB_LIBUSUAL is not set
989
990#
991# USB Imaging devices
992#
993# CONFIG_USB_MDC800 is not set
994# CONFIG_USB_MICROTEK is not set
995# CONFIG_USB_MON is not set
996
997#
998# USB port drivers
999#
1000# CONFIG_USB_SERIAL is not set
1001
1002#
1003# USB Miscellaneous drivers
1004#
1005# CONFIG_USB_EMI62 is not set
1006# CONFIG_USB_EMI26 is not set
1007# CONFIG_USB_ADUTUX is not set
1008# CONFIG_USB_AUERSWALD is not set
1009# CONFIG_USB_RIO500 is not set
1010# CONFIG_USB_LEGOTOWER is not set
1011# CONFIG_USB_LCD is not set
1012# CONFIG_USB_BERRY_CHARGE is not set
1013# CONFIG_USB_LED is not set
1014# CONFIG_USB_CYPRESS_CY7C63 is not set
1015# CONFIG_USB_CYTHERM is not set
1016# CONFIG_USB_PHIDGET is not set
1017# CONFIG_USB_IDMOUSE is not set
1018# CONFIG_USB_FTDI_ELAN is not set
1019# CONFIG_USB_APPLEDISPLAY is not set
1020# CONFIG_USB_SISUSBVGA is not set
1021# CONFIG_USB_LD is not set
1022# CONFIG_USB_TRANCEVIBRATOR is not set
1023# CONFIG_USB_IOWARRIOR is not set
1024# CONFIG_USB_TEST is not set
1025# CONFIG_USB_ISIGHTFW is not set
1026# CONFIG_USB_GADGET is not set
1027# CONFIG_MMC is not set
1028CONFIG_NEW_LEDS=y
1029# CONFIG_LEDS_CLASS is not set
1030
1031#
1032# LED drivers
1033#
1034
1035#
1036# LED Triggers
1037#
1038# CONFIG_LEDS_TRIGGERS is not set
1039CONFIG_RTC_LIB=y
1040CONFIG_RTC_CLASS=y
1041# CONFIG_RTC_DEBUG is not set
1042
1043#
1044# RTC interfaces
1045#
1046CONFIG_RTC_INTF_SYSFS=y
1047CONFIG_RTC_INTF_PROC=y
1048CONFIG_RTC_INTF_DEV=y
1049# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1050# CONFIG_RTC_DRV_TEST is not set
1051
1052#
1053# I2C RTC drivers
1054#
1055# CONFIG_RTC_DRV_DS1307 is not set
1056# CONFIG_RTC_DRV_DS1374 is not set
1057# CONFIG_RTC_DRV_DS1672 is not set
1058# CONFIG_RTC_DRV_MAX6900 is not set
1059CONFIG_RTC_DRV_MV=y
1060# CONFIG_RTC_DRV_RS5C372 is not set
1061# CONFIG_RTC_DRV_ISL1208 is not set
1062# CONFIG_RTC_DRV_X1205 is not set
1063# CONFIG_RTC_DRV_PCF8563 is not set
1064# CONFIG_RTC_DRV_PCF8583 is not set
1065# CONFIG_RTC_DRV_M41T80 is not set
1066# CONFIG_RTC_DRV_S35390A is not set
1067
1068#
1069# SPI RTC drivers
1070#
1071# CONFIG_RTC_DRV_MAX6902 is not set
1072# CONFIG_RTC_DRV_R9701 is not set
1073# CONFIG_RTC_DRV_RS5C348 is not set
1074
1075#
1076# Platform RTC drivers
1077#
1078# CONFIG_RTC_DRV_CMOS is not set
1079# CONFIG_RTC_DRV_DS1511 is not set
1080# CONFIG_RTC_DRV_DS1553 is not set
1081# CONFIG_RTC_DRV_DS1742 is not set
1082# CONFIG_RTC_DRV_STK17TA8 is not set
1083# CONFIG_RTC_DRV_M48T86 is not set
1084# CONFIG_RTC_DRV_M48T59 is not set
1085# CONFIG_RTC_DRV_V3020 is not set
1086
1087#
1088# on-CPU RTC drivers
1089#
1090CONFIG_DMADEVICES=y
1091
1092#
1093# DMA Devices
1094#
1095CONFIG_MV_XOR=y
1096CONFIG_DMA_ENGINE=y
1097
1098#
1099# DMA Clients
1100#
1101# CONFIG_NET_DMA is not set
1102# CONFIG_UIO is not set
1103
1104#
1105# File systems
1106#
1107CONFIG_EXT2_FS=y
1108# CONFIG_EXT2_FS_XATTR is not set
1109# CONFIG_EXT2_FS_XIP is not set
1110CONFIG_EXT3_FS=y
1111# CONFIG_EXT3_FS_XATTR is not set
1112# CONFIG_EXT4DEV_FS is not set
1113CONFIG_JBD=y
1114# CONFIG_REISERFS_FS is not set
1115# CONFIG_JFS_FS is not set
1116# CONFIG_FS_POSIX_ACL is not set
1117CONFIG_XFS_FS=y
1118# CONFIG_XFS_QUOTA is not set
1119# CONFIG_XFS_POSIX_ACL is not set
1120# CONFIG_XFS_RT is not set
1121# CONFIG_XFS_DEBUG is not set
1122# CONFIG_OCFS2_FS is not set
1123CONFIG_DNOTIFY=y
1124CONFIG_INOTIFY=y
1125CONFIG_INOTIFY_USER=y
1126# CONFIG_QUOTA is not set
1127# CONFIG_AUTOFS_FS is not set
1128# CONFIG_AUTOFS4_FS is not set
1129# CONFIG_FUSE_FS is not set
1130
1131#
1132# CD-ROM/DVD Filesystems
1133#
1134CONFIG_ISO9660_FS=y
1135CONFIG_JOLIET=y
1136# CONFIG_ZISOFS is not set
1137CONFIG_UDF_FS=m
1138CONFIG_UDF_NLS=y
1139
1140#
1141# DOS/FAT/NT Filesystems
1142#
1143CONFIG_FAT_FS=y
1144CONFIG_MSDOS_FS=y
1145CONFIG_VFAT_FS=y
1146CONFIG_FAT_DEFAULT_CODEPAGE=437
1147CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1148# CONFIG_NTFS_FS is not set
1149
1150#
1151# Pseudo filesystems
1152#
1153CONFIG_PROC_FS=y
1154CONFIG_PROC_SYSCTL=y
1155CONFIG_SYSFS=y
1156CONFIG_TMPFS=y
1157# CONFIG_TMPFS_POSIX_ACL is not set
1158# CONFIG_HUGETLB_PAGE is not set
1159# CONFIG_CONFIGFS_FS is not set
1160
1161#
1162# Miscellaneous filesystems
1163#
1164# CONFIG_ADFS_FS is not set
1165# CONFIG_AFFS_FS is not set
1166# CONFIG_HFS_FS is not set
1167# CONFIG_HFSPLUS_FS is not set
1168# CONFIG_BEFS_FS is not set
1169# CONFIG_BFS_FS is not set
1170# CONFIG_EFS_FS is not set
1171CONFIG_JFFS2_FS=y
1172CONFIG_JFFS2_FS_DEBUG=0
1173CONFIG_JFFS2_FS_WRITEBUFFER=y
1174# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1175# CONFIG_JFFS2_SUMMARY is not set
1176# CONFIG_JFFS2_FS_XATTR is not set
1177# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1178CONFIG_JFFS2_ZLIB=y
1179# CONFIG_JFFS2_LZO is not set
1180CONFIG_JFFS2_RTIME=y
1181# CONFIG_JFFS2_RUBIN is not set
1182CONFIG_CRAMFS=y
1183# CONFIG_VXFS_FS is not set
1184# CONFIG_MINIX_FS is not set
1185# CONFIG_HPFS_FS is not set
1186# CONFIG_QNX4FS_FS is not set
1187# CONFIG_ROMFS_FS is not set
1188# CONFIG_SYSV_FS is not set
1189# CONFIG_UFS_FS is not set
1190CONFIG_NETWORK_FILESYSTEMS=y
1191CONFIG_NFS_FS=y
1192CONFIG_NFS_V3=y
1193# CONFIG_NFS_V3_ACL is not set
1194# CONFIG_NFS_V4 is not set
1195# CONFIG_NFSD is not set
1196CONFIG_ROOT_NFS=y
1197CONFIG_LOCKD=y
1198CONFIG_LOCKD_V4=y
1199CONFIG_NFS_COMMON=y
1200CONFIG_SUNRPC=y
1201# CONFIG_SUNRPC_BIND34 is not set
1202# CONFIG_RPCSEC_GSS_KRB5 is not set
1203# CONFIG_RPCSEC_GSS_SPKM3 is not set
1204# CONFIG_SMB_FS is not set
1205# CONFIG_CIFS is not set
1206# CONFIG_NCP_FS is not set
1207# CONFIG_CODA_FS is not set
1208# CONFIG_AFS_FS is not set
1209
1210#
1211# Partition Types
1212#
1213CONFIG_PARTITION_ADVANCED=y
1214# CONFIG_ACORN_PARTITION is not set
1215# CONFIG_OSF_PARTITION is not set
1216# CONFIG_AMIGA_PARTITION is not set
1217# CONFIG_ATARI_PARTITION is not set
1218# CONFIG_MAC_PARTITION is not set
1219CONFIG_MSDOS_PARTITION=y
1220# CONFIG_BSD_DISKLABEL is not set
1221# CONFIG_MINIX_SUBPARTITION is not set
1222# CONFIG_SOLARIS_X86_PARTITION is not set
1223# CONFIG_UNIXWARE_DISKLABEL is not set
1224# CONFIG_LDM_PARTITION is not set
1225# CONFIG_SGI_PARTITION is not set
1226# CONFIG_ULTRIX_PARTITION is not set
1227# CONFIG_SUN_PARTITION is not set
1228# CONFIG_KARMA_PARTITION is not set
1229# CONFIG_EFI_PARTITION is not set
1230# CONFIG_SYSV68_PARTITION is not set
1231CONFIG_NLS=y
1232CONFIG_NLS_DEFAULT="iso8859-1"
1233CONFIG_NLS_CODEPAGE_437=y
1234# CONFIG_NLS_CODEPAGE_737 is not set
1235# CONFIG_NLS_CODEPAGE_775 is not set
1236CONFIG_NLS_CODEPAGE_850=y
1237# CONFIG_NLS_CODEPAGE_852 is not set
1238# CONFIG_NLS_CODEPAGE_855 is not set
1239# CONFIG_NLS_CODEPAGE_857 is not set
1240# CONFIG_NLS_CODEPAGE_860 is not set
1241# CONFIG_NLS_CODEPAGE_861 is not set
1242# CONFIG_NLS_CODEPAGE_862 is not set
1243# CONFIG_NLS_CODEPAGE_863 is not set
1244# CONFIG_NLS_CODEPAGE_864 is not set
1245# CONFIG_NLS_CODEPAGE_865 is not set
1246# CONFIG_NLS_CODEPAGE_866 is not set
1247# CONFIG_NLS_CODEPAGE_869 is not set
1248# CONFIG_NLS_CODEPAGE_936 is not set
1249# CONFIG_NLS_CODEPAGE_950 is not set
1250# CONFIG_NLS_CODEPAGE_932 is not set
1251# CONFIG_NLS_CODEPAGE_949 is not set
1252# CONFIG_NLS_CODEPAGE_874 is not set
1253# CONFIG_NLS_ISO8859_8 is not set
1254# CONFIG_NLS_CODEPAGE_1250 is not set
1255# CONFIG_NLS_CODEPAGE_1251 is not set
1256# CONFIG_NLS_ASCII is not set
1257CONFIG_NLS_ISO8859_1=y
1258CONFIG_NLS_ISO8859_2=y
1259# CONFIG_NLS_ISO8859_3 is not set
1260# CONFIG_NLS_ISO8859_4 is not set
1261# CONFIG_NLS_ISO8859_5 is not set
1262# CONFIG_NLS_ISO8859_6 is not set
1263# CONFIG_NLS_ISO8859_7 is not set
1264# CONFIG_NLS_ISO8859_9 is not set
1265# CONFIG_NLS_ISO8859_13 is not set
1266# CONFIG_NLS_ISO8859_14 is not set
1267# CONFIG_NLS_ISO8859_15 is not set
1268# CONFIG_NLS_KOI8_R is not set
1269# CONFIG_NLS_KOI8_U is not set
1270CONFIG_NLS_UTF8=y
1271# CONFIG_DLM is not set
1272
1273#
1274# Kernel hacking
1275#
1276# CONFIG_PRINTK_TIME is not set
1277CONFIG_ENABLE_WARN_DEPRECATED=y
1278CONFIG_ENABLE_MUST_CHECK=y
1279CONFIG_FRAME_WARN=1024
1280CONFIG_MAGIC_SYSRQ=y
1281# CONFIG_UNUSED_SYMBOLS is not set
1282# CONFIG_DEBUG_FS is not set
1283# CONFIG_HEADERS_CHECK is not set
1284CONFIG_DEBUG_KERNEL=y
1285# CONFIG_DEBUG_SHIRQ is not set
1286CONFIG_DETECT_SOFTLOCKUP=y
1287# CONFIG_SCHED_DEBUG is not set
1288# CONFIG_SCHEDSTATS is not set
1289# CONFIG_TIMER_STATS is not set
1290# CONFIG_DEBUG_OBJECTS is not set
1291# CONFIG_DEBUG_SLAB is not set
1292# CONFIG_DEBUG_PREEMPT is not set
1293# CONFIG_DEBUG_RT_MUTEXES is not set
1294# CONFIG_RT_MUTEX_TESTER is not set
1295# CONFIG_DEBUG_SPINLOCK is not set
1296# CONFIG_DEBUG_MUTEXES is not set
1297# CONFIG_DEBUG_LOCK_ALLOC is not set
1298# CONFIG_PROVE_LOCKING is not set
1299# CONFIG_LOCK_STAT is not set
1300# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1301# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1302# CONFIG_DEBUG_KOBJECT is not set
1303# CONFIG_DEBUG_BUGVERBOSE is not set
1304CONFIG_DEBUG_INFO=y
1305# CONFIG_DEBUG_VM is not set
1306# CONFIG_DEBUG_WRITECOUNT is not set
1307# CONFIG_DEBUG_LIST is not set
1308# CONFIG_DEBUG_SG is not set
1309CONFIG_FRAME_POINTER=y
1310# CONFIG_BOOT_PRINTK_DELAY is not set
1311# CONFIG_RCU_TORTURE_TEST is not set
1312# CONFIG_KPROBES_SANITY_TEST is not set
1313# CONFIG_BACKTRACE_SELF_TEST is not set
1314# CONFIG_LKDTM is not set
1315# CONFIG_FAULT_INJECTION is not set
1316# CONFIG_LATENCYTOP is not set
1317# CONFIG_SAMPLES is not set
1318CONFIG_DEBUG_USER=y
1319CONFIG_DEBUG_ERRORS=y
1320# CONFIG_DEBUG_STACK_USAGE is not set
1321CONFIG_DEBUG_LL=y
1322# CONFIG_DEBUG_ICEDCC is not set
1323
1324#
1325# Security options
1326#
1327# CONFIG_KEYS is not set
1328# CONFIG_SECURITY is not set
1329# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1330CONFIG_ASYNC_CORE=y
1331CONFIG_CRYPTO=y
1332
1333#
1334# Crypto core or helper
1335#
1336CONFIG_CRYPTO_ALGAPI=m
1337CONFIG_CRYPTO_BLKCIPHER=m
1338CONFIG_CRYPTO_MANAGER=m
1339# CONFIG_CRYPTO_GF128MUL is not set
1340# CONFIG_CRYPTO_NULL is not set
1341# CONFIG_CRYPTO_CRYPTD is not set
1342# CONFIG_CRYPTO_AUTHENC is not set
1343# CONFIG_CRYPTO_TEST is not set
1344
1345#
1346# Authenticated Encryption with Associated Data
1347#
1348# CONFIG_CRYPTO_CCM is not set
1349# CONFIG_CRYPTO_GCM is not set
1350# CONFIG_CRYPTO_SEQIV is not set
1351
1352#
1353# Block modes
1354#
1355CONFIG_CRYPTO_CBC=m
1356# CONFIG_CRYPTO_CTR is not set
1357# CONFIG_CRYPTO_CTS is not set
1358CONFIG_CRYPTO_ECB=m
1359# CONFIG_CRYPTO_LRW is not set
1360CONFIG_CRYPTO_PCBC=m
1361# CONFIG_CRYPTO_XTS is not set
1362
1363#
1364# Hash modes
1365#
1366# CONFIG_CRYPTO_HMAC is not set
1367# CONFIG_CRYPTO_XCBC is not set
1368
1369#
1370# Digest
1371#
1372# CONFIG_CRYPTO_CRC32C is not set
1373# CONFIG_CRYPTO_MD4 is not set
1374# CONFIG_CRYPTO_MD5 is not set
1375# CONFIG_CRYPTO_MICHAEL_MIC is not set
1376# CONFIG_CRYPTO_SHA1 is not set
1377# CONFIG_CRYPTO_SHA256 is not set
1378# CONFIG_CRYPTO_SHA512 is not set
1379# CONFIG_CRYPTO_TGR192 is not set
1380# CONFIG_CRYPTO_WP512 is not set
1381
1382#
1383# Ciphers
1384#
1385# CONFIG_CRYPTO_AES is not set
1386# CONFIG_CRYPTO_ANUBIS is not set
1387# CONFIG_CRYPTO_ARC4 is not set
1388# CONFIG_CRYPTO_BLOWFISH is not set
1389# CONFIG_CRYPTO_CAMELLIA is not set
1390# CONFIG_CRYPTO_CAST5 is not set
1391# CONFIG_CRYPTO_CAST6 is not set
1392# CONFIG_CRYPTO_DES is not set
1393# CONFIG_CRYPTO_FCRYPT is not set
1394# CONFIG_CRYPTO_KHAZAD is not set
1395# CONFIG_CRYPTO_SALSA20 is not set
1396# CONFIG_CRYPTO_SEED is not set
1397# CONFIG_CRYPTO_SERPENT is not set
1398# CONFIG_CRYPTO_TEA is not set
1399# CONFIG_CRYPTO_TWOFISH is not set
1400
1401#
1402# Compression
1403#
1404# CONFIG_CRYPTO_DEFLATE is not set
1405# CONFIG_CRYPTO_LZO is not set
1406CONFIG_CRYPTO_HW=y
1407# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1408
1409#
1410# Library routines
1411#
1412CONFIG_BITREVERSE=y
1413# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1414# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1415CONFIG_CRC_CCITT=y
1416CONFIG_CRC16=y
1417CONFIG_CRC_ITU_T=m
1418CONFIG_CRC32=y
1419# CONFIG_CRC7 is not set
1420CONFIG_LIBCRC32C=y
1421CONFIG_ZLIB_INFLATE=y
1422CONFIG_ZLIB_DEFLATE=y
1423CONFIG_PLIST=y
1424CONFIG_HAS_IOMEM=y
1425CONFIG_HAS_IOPORT=y
1426CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/ks8695_defconfig b/arch/arm/configs/ks8695_defconfig
index 8ab21a0719e9..6077f2cb88e4 100644
--- a/arch/arm/configs/ks8695_defconfig
+++ b/arch/arm/configs/ks8695_defconfig
@@ -174,7 +174,6 @@ CONFIG_PCCARD_NONSTATIC=y
174# Kernel Features 174# Kernel Features
175# 175#
176# CONFIG_PREEMPT is not set 176# CONFIG_PREEMPT is not set
177# CONFIG_NO_IDLE_HZ is not set
178CONFIG_HZ=100 177CONFIG_HZ=100
179# CONFIG_AEABI is not set 178# CONFIG_AEABI is not set
180# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 179# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig
new file mode 100644
index 000000000000..17da7c3b3d53
--- /dev/null
+++ b/arch/arm/configs/loki_defconfig
@@ -0,0 +1,1147 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5
4# Fri Jun 13 03:07:49 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8# CONFIG_GENERIC_GPIO is not set
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set
50# CONFIG_SYSFS_DEPRECATED_V2 is not set
51# CONFIG_RELAY is not set
52# CONFIG_NAMESPACES is not set
53# CONFIG_BLK_DEV_INITRD is not set
54CONFIG_CC_OPTIMIZE_FOR_SIZE=y
55CONFIG_SYSCTL=y
56CONFIG_EMBEDDED=y
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_SYSCTL_SYSCALL_CHECK=y
60CONFIG_KALLSYMS=y
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_COMPAT_BRK=y
67CONFIG_BASE_FULL=y
68CONFIG_FUTEX=y
69CONFIG_ANON_INODES=y
70CONFIG_EPOLL=y
71CONFIG_SIGNALFD=y
72CONFIG_TIMERFD=y
73CONFIG_EVENTFD=y
74CONFIG_SHMEM=y
75CONFIG_VM_EVENT_COUNTERS=y
76CONFIG_SLAB=y
77# CONFIG_SLUB is not set
78# CONFIG_SLOB is not set
79# CONFIG_PROFILING is not set
80# CONFIG_MARKERS is not set
81CONFIG_HAVE_OPROFILE=y
82# CONFIG_KPROBES is not set
83CONFIG_HAVE_KPROBES=y
84CONFIG_HAVE_KRETPROBES=y
85# CONFIG_HAVE_DMA_ATTRS is not set
86CONFIG_PROC_PAGE_MONITOR=y
87CONFIG_SLABINFO=y
88CONFIG_RT_MUTEXES=y
89# CONFIG_TINY_SHMEM is not set
90CONFIG_BASE_SMALL=0
91CONFIG_MODULES=y
92# CONFIG_MODULE_FORCE_LOAD is not set
93CONFIG_MODULE_UNLOAD=y
94# CONFIG_MODULE_FORCE_UNLOAD is not set
95# CONFIG_MODVERSIONS is not set
96# CONFIG_MODULE_SRCVERSION_ALL is not set
97# CONFIG_KMOD is not set
98CONFIG_BLOCK=y
99# CONFIG_LBD is not set
100# CONFIG_BLK_DEV_IO_TRACE is not set
101# CONFIG_LSF is not set
102# CONFIG_BLK_DEV_BSG is not set
103
104#
105# IO Schedulers
106#
107CONFIG_IOSCHED_NOOP=y
108CONFIG_IOSCHED_AS=y
109CONFIG_IOSCHED_DEADLINE=y
110CONFIG_IOSCHED_CFQ=y
111# CONFIG_DEFAULT_AS is not set
112# CONFIG_DEFAULT_DEADLINE is not set
113CONFIG_DEFAULT_CFQ=y
114# CONFIG_DEFAULT_NOOP is not set
115CONFIG_DEFAULT_IOSCHED="cfq"
116CONFIG_CLASSIC_RCU=y
117
118#
119# System Type
120#
121# CONFIG_ARCH_AAEC2000 is not set
122# CONFIG_ARCH_INTEGRATOR is not set
123# CONFIG_ARCH_REALVIEW is not set
124# CONFIG_ARCH_VERSATILE is not set
125# CONFIG_ARCH_AT91 is not set
126# CONFIG_ARCH_CLPS7500 is not set
127# CONFIG_ARCH_CLPS711X is not set
128# CONFIG_ARCH_CO285 is not set
129# CONFIG_ARCH_EBSA110 is not set
130# CONFIG_ARCH_EP93XX is not set
131# CONFIG_ARCH_FOOTBRIDGE is not set
132# CONFIG_ARCH_NETX is not set
133# CONFIG_ARCH_H720X is not set
134# CONFIG_ARCH_IMX is not set
135# CONFIG_ARCH_IOP13XX is not set
136# CONFIG_ARCH_IOP32X is not set
137# CONFIG_ARCH_IOP33X is not set
138# CONFIG_ARCH_IXP23XX is not set
139# CONFIG_ARCH_IXP2000 is not set
140# CONFIG_ARCH_IXP4XX is not set
141# CONFIG_ARCH_L7200 is not set
142# CONFIG_ARCH_KIRKWOOD is not set
143# CONFIG_ARCH_KS8695 is not set
144# CONFIG_ARCH_NS9XXX is not set
145CONFIG_ARCH_LOKI=y
146# CONFIG_ARCH_MV78XX0 is not set
147# CONFIG_ARCH_MXC is not set
148# CONFIG_ARCH_ORION5X is not set
149# CONFIG_ARCH_PNX4008 is not set
150# CONFIG_ARCH_PXA is not set
151# CONFIG_ARCH_RPC is not set
152# CONFIG_ARCH_SA1100 is not set
153# CONFIG_ARCH_S3C2410 is not set
154# CONFIG_ARCH_SHARK is not set
155# CONFIG_ARCH_LH7A40X is not set
156# CONFIG_ARCH_DAVINCI is not set
157# CONFIG_ARCH_OMAP is not set
158# CONFIG_ARCH_MSM7X00A is not set
159
160#
161# Marvell Loki (88RC8480) Implementations
162#
163CONFIG_MACH_LB88RC8480=y
164
165#
166# Boot options
167#
168
169#
170# Power management
171#
172CONFIG_PLAT_ORION=y
173
174#
175# Processor Type
176#
177CONFIG_CPU_32=y
178CONFIG_CPU_FEROCEON=y
179# CONFIG_CPU_FEROCEON_OLD_ID is not set
180CONFIG_CPU_32v5=y
181CONFIG_CPU_ABRT_EV5T=y
182CONFIG_CPU_PABRT_NOIFAR=y
183CONFIG_CPU_CACHE_VIVT=y
184CONFIG_CPU_COPY_FEROCEON=y
185CONFIG_CPU_TLB_FEROCEON=y
186CONFIG_CPU_CP15=y
187CONFIG_CPU_CP15_MMU=y
188
189#
190# Processor Features
191#
192CONFIG_ARM_THUMB=y
193# CONFIG_CPU_ICACHE_DISABLE is not set
194# CONFIG_CPU_DCACHE_DISABLE is not set
195# CONFIG_OUTER_CACHE is not set
196
197#
198# Bus support
199#
200# CONFIG_PCI_SYSCALL is not set
201# CONFIG_ARCH_SUPPORTS_MSI is not set
202# CONFIG_PCCARD is not set
203
204#
205# Kernel Features
206#
207CONFIG_TICK_ONESHOT=y
208CONFIG_NO_HZ=y
209CONFIG_HIGH_RES_TIMERS=y
210CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
211CONFIG_PREEMPT=y
212CONFIG_HZ=100
213CONFIG_AEABI=y
214CONFIG_OABI_COMPAT=y
215# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
216CONFIG_SELECT_MEMORY_MODEL=y
217CONFIG_FLATMEM_MANUAL=y
218# CONFIG_DISCONTIGMEM_MANUAL is not set
219# CONFIG_SPARSEMEM_MANUAL is not set
220CONFIG_FLATMEM=y
221CONFIG_FLAT_NODE_MEM_MAP=y
222# CONFIG_SPARSEMEM_STATIC is not set
223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
224CONFIG_PAGEFLAGS_EXTENDED=y
225CONFIG_SPLIT_PTLOCK_CPUS=4096
226# CONFIG_RESOURCES_64BIT is not set
227CONFIG_ZONE_DMA_FLAG=1
228CONFIG_BOUNCE=y
229CONFIG_VIRT_TO_BUS=y
230CONFIG_ALIGNMENT_TRAP=y
231
232#
233# Boot options
234#
235CONFIG_ZBOOT_ROM_TEXT=0x0
236CONFIG_ZBOOT_ROM_BSS=0x0
237CONFIG_CMDLINE=""
238# CONFIG_XIP_KERNEL is not set
239# CONFIG_KEXEC is not set
240
241#
242# Floating point emulation
243#
244
245#
246# At least one emulation must be selected
247#
248# CONFIG_FPE_NWFPE is not set
249# CONFIG_FPE_FASTFPE is not set
250# CONFIG_VFP is not set
251
252#
253# Userspace binary formats
254#
255CONFIG_BINFMT_ELF=y
256# CONFIG_BINFMT_AOUT is not set
257# CONFIG_BINFMT_MISC is not set
258
259#
260# Power management options
261#
262# CONFIG_PM is not set
263CONFIG_ARCH_SUSPEND_POSSIBLE=y
264
265#
266# Networking
267#
268CONFIG_NET=y
269
270#
271# Networking options
272#
273CONFIG_PACKET=y
274CONFIG_PACKET_MMAP=y
275CONFIG_UNIX=y
276CONFIG_XFRM=y
277# CONFIG_XFRM_USER is not set
278# CONFIG_XFRM_SUB_POLICY is not set
279# CONFIG_XFRM_MIGRATE is not set
280# CONFIG_XFRM_STATISTICS is not set
281# CONFIG_NET_KEY is not set
282CONFIG_INET=y
283CONFIG_IP_MULTICAST=y
284# CONFIG_IP_ADVANCED_ROUTER is not set
285CONFIG_IP_FIB_HASH=y
286CONFIG_IP_PNP=y
287CONFIG_IP_PNP_DHCP=y
288CONFIG_IP_PNP_BOOTP=y
289# CONFIG_IP_PNP_RARP is not set
290# CONFIG_NET_IPIP is not set
291# CONFIG_NET_IPGRE is not set
292# CONFIG_IP_MROUTE is not set
293# CONFIG_ARPD is not set
294# CONFIG_SYN_COOKIES is not set
295# CONFIG_INET_AH is not set
296# CONFIG_INET_ESP is not set
297# CONFIG_INET_IPCOMP is not set
298# CONFIG_INET_XFRM_TUNNEL is not set
299# CONFIG_INET_TUNNEL is not set
300CONFIG_INET_XFRM_MODE_TRANSPORT=y
301CONFIG_INET_XFRM_MODE_TUNNEL=y
302CONFIG_INET_XFRM_MODE_BEET=y
303# CONFIG_INET_LRO is not set
304CONFIG_INET_DIAG=y
305CONFIG_INET_TCP_DIAG=y
306# CONFIG_TCP_CONG_ADVANCED is not set
307CONFIG_TCP_CONG_CUBIC=y
308CONFIG_DEFAULT_TCP_CONG="cubic"
309# CONFIG_TCP_MD5SIG is not set
310# CONFIG_IPV6 is not set
311# CONFIG_NETWORK_SECMARK is not set
312# CONFIG_NETFILTER is not set
313# CONFIG_IP_DCCP is not set
314# CONFIG_IP_SCTP is not set
315# CONFIG_TIPC is not set
316# CONFIG_ATM is not set
317# CONFIG_BRIDGE is not set
318# CONFIG_VLAN_8021Q is not set
319# CONFIG_DECNET is not set
320# CONFIG_LLC2 is not set
321# CONFIG_IPX is not set
322# CONFIG_ATALK is not set
323# CONFIG_X25 is not set
324# CONFIG_LAPB is not set
325# CONFIG_ECONET is not set
326# CONFIG_WAN_ROUTER is not set
327# CONFIG_NET_SCHED is not set
328
329#
330# Network testing
331#
332CONFIG_NET_PKTGEN=m
333# CONFIG_HAMRADIO is not set
334# CONFIG_CAN is not set
335# CONFIG_IRDA is not set
336# CONFIG_BT is not set
337# CONFIG_AF_RXRPC is not set
338
339#
340# Wireless
341#
342# CONFIG_CFG80211 is not set
343CONFIG_WIRELESS_EXT=y
344# CONFIG_MAC80211 is not set
345# CONFIG_IEEE80211 is not set
346# CONFIG_RFKILL is not set
347# CONFIG_NET_9P is not set
348
349#
350# Device Drivers
351#
352
353#
354# Generic Driver Options
355#
356CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
357CONFIG_STANDALONE=y
358CONFIG_PREVENT_FIRMWARE_BUILD=y
359CONFIG_FW_LOADER=y
360# CONFIG_SYS_HYPERVISOR is not set
361# CONFIG_CONNECTOR is not set
362CONFIG_MTD=y
363# CONFIG_MTD_DEBUG is not set
364# CONFIG_MTD_CONCAT is not set
365CONFIG_MTD_PARTITIONS=y
366# CONFIG_MTD_REDBOOT_PARTS is not set
367CONFIG_MTD_CMDLINE_PARTS=y
368# CONFIG_MTD_AFS_PARTS is not set
369# CONFIG_MTD_AR7_PARTS is not set
370
371#
372# User Modules And Translation Layers
373#
374CONFIG_MTD_CHAR=y
375CONFIG_MTD_BLKDEVS=y
376CONFIG_MTD_BLOCK=y
377CONFIG_FTL=y
378CONFIG_NFTL=y
379# CONFIG_NFTL_RW is not set
380# CONFIG_INFTL is not set
381# CONFIG_RFD_FTL is not set
382# CONFIG_SSFDC is not set
383# CONFIG_MTD_OOPS is not set
384
385#
386# RAM/ROM/Flash chip drivers
387#
388CONFIG_MTD_CFI=y
389CONFIG_MTD_JEDECPROBE=y
390CONFIG_MTD_GEN_PROBE=y
391CONFIG_MTD_CFI_ADV_OPTIONS=y
392CONFIG_MTD_CFI_NOSWAP=y
393# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
394# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
395CONFIG_MTD_CFI_GEOMETRY=y
396CONFIG_MTD_MAP_BANK_WIDTH_1=y
397CONFIG_MTD_MAP_BANK_WIDTH_2=y
398CONFIG_MTD_MAP_BANK_WIDTH_4=y
399# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
400# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
401# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
402CONFIG_MTD_CFI_I1=y
403CONFIG_MTD_CFI_I2=y
404CONFIG_MTD_CFI_I4=y
405# CONFIG_MTD_CFI_I8 is not set
406# CONFIG_MTD_OTP is not set
407CONFIG_MTD_CFI_INTELEXT=y
408CONFIG_MTD_CFI_AMDSTD=y
409CONFIG_MTD_CFI_STAA=y
410CONFIG_MTD_CFI_UTIL=y
411# CONFIG_MTD_RAM is not set
412# CONFIG_MTD_ROM is not set
413# CONFIG_MTD_ABSENT is not set
414
415#
416# Mapping drivers for chip access
417#
418# CONFIG_MTD_COMPLEX_MAPPINGS is not set
419CONFIG_MTD_PHYSMAP=y
420CONFIG_MTD_PHYSMAP_START=0x0
421CONFIG_MTD_PHYSMAP_LEN=0x0
422CONFIG_MTD_PHYSMAP_BANKWIDTH=0
423# CONFIG_MTD_ARM_INTEGRATOR is not set
424# CONFIG_MTD_IMPA7 is not set
425# CONFIG_MTD_PLATRAM is not set
426
427#
428# Self-contained MTD device drivers
429#
430# CONFIG_MTD_DATAFLASH is not set
431CONFIG_MTD_M25P80=y
432CONFIG_M25PXX_USE_FAST_READ=y
433# CONFIG_MTD_SLRAM is not set
434# CONFIG_MTD_PHRAM is not set
435# CONFIG_MTD_MTDRAM is not set
436# CONFIG_MTD_BLOCK2MTD is not set
437
438#
439# Disk-On-Chip Device Drivers
440#
441# CONFIG_MTD_DOC2000 is not set
442# CONFIG_MTD_DOC2001 is not set
443# CONFIG_MTD_DOC2001PLUS is not set
444CONFIG_MTD_NAND=y
445CONFIG_MTD_NAND_VERIFY_WRITE=y
446# CONFIG_MTD_NAND_ECC_SMC is not set
447# CONFIG_MTD_NAND_MUSEUM_IDS is not set
448CONFIG_MTD_NAND_IDS=y
449# CONFIG_MTD_NAND_DISKONCHIP is not set
450# CONFIG_MTD_NAND_NANDSIM is not set
451# CONFIG_MTD_NAND_PLATFORM is not set
452# CONFIG_MTD_ALAUDA is not set
453CONFIG_MTD_NAND_ORION=y
454# CONFIG_MTD_ONENAND is not set
455
456#
457# UBI - Unsorted block images
458#
459# CONFIG_MTD_UBI is not set
460# CONFIG_PARPORT is not set
461CONFIG_BLK_DEV=y
462# CONFIG_BLK_DEV_COW_COMMON is not set
463CONFIG_BLK_DEV_LOOP=y
464# CONFIG_BLK_DEV_CRYPTOLOOP is not set
465# CONFIG_BLK_DEV_NBD is not set
466# CONFIG_BLK_DEV_UB is not set
467# CONFIG_BLK_DEV_RAM is not set
468# CONFIG_CDROM_PKTCDVD is not set
469# CONFIG_ATA_OVER_ETH is not set
470# CONFIG_MISC_DEVICES is not set
471CONFIG_HAVE_IDE=y
472# CONFIG_IDE is not set
473
474#
475# SCSI device support
476#
477# CONFIG_RAID_ATTRS is not set
478CONFIG_SCSI=y
479CONFIG_SCSI_DMA=y
480# CONFIG_SCSI_TGT is not set
481# CONFIG_SCSI_NETLINK is not set
482# CONFIG_SCSI_PROC_FS is not set
483
484#
485# SCSI support type (disk, tape, CD-ROM)
486#
487CONFIG_BLK_DEV_SD=y
488# CONFIG_CHR_DEV_ST is not set
489# CONFIG_CHR_DEV_OSST is not set
490CONFIG_BLK_DEV_SR=m
491# CONFIG_BLK_DEV_SR_VENDOR is not set
492CONFIG_CHR_DEV_SG=m
493# CONFIG_CHR_DEV_SCH is not set
494
495#
496# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
497#
498# CONFIG_SCSI_MULTI_LUN is not set
499# CONFIG_SCSI_CONSTANTS is not set
500# CONFIG_SCSI_LOGGING is not set
501# CONFIG_SCSI_SCAN_ASYNC is not set
502CONFIG_SCSI_WAIT_SCAN=m
503
504#
505# SCSI Transports
506#
507# CONFIG_SCSI_SPI_ATTRS is not set
508# CONFIG_SCSI_FC_ATTRS is not set
509# CONFIG_SCSI_ISCSI_ATTRS is not set
510# CONFIG_SCSI_SAS_LIBSAS is not set
511# CONFIG_SCSI_SRP_ATTRS is not set
512CONFIG_SCSI_LOWLEVEL=y
513# CONFIG_ISCSI_TCP is not set
514# CONFIG_SCSI_DEBUG is not set
515CONFIG_ATA=y
516# CONFIG_ATA_NONSTANDARD is not set
517CONFIG_SATA_PMP=y
518CONFIG_ATA_SFF=y
519CONFIG_SATA_MV=y
520# CONFIG_PATA_PLATFORM is not set
521# CONFIG_MD is not set
522CONFIG_NETDEVICES=y
523# CONFIG_NETDEVICES_MULTIQUEUE is not set
524# CONFIG_DUMMY is not set
525# CONFIG_BONDING is not set
526# CONFIG_MACVLAN is not set
527# CONFIG_EQUALIZER is not set
528# CONFIG_TUN is not set
529# CONFIG_VETH is not set
530# CONFIG_PHYLIB is not set
531CONFIG_NET_ETHERNET=y
532CONFIG_MII=y
533# CONFIG_AX88796 is not set
534# CONFIG_SMC91X is not set
535# CONFIG_DM9000 is not set
536# CONFIG_ENC28J60 is not set
537# CONFIG_IBM_NEW_EMAC_ZMII is not set
538# CONFIG_IBM_NEW_EMAC_RGMII is not set
539# CONFIG_IBM_NEW_EMAC_TAH is not set
540# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
541# CONFIG_B44 is not set
542CONFIG_NETDEV_1000=y
543# CONFIG_E1000E_ENABLED is not set
544CONFIG_MV643XX_ETH=y
545# CONFIG_NETDEV_10000 is not set
546
547#
548# Wireless LAN
549#
550# CONFIG_WLAN_PRE80211 is not set
551# CONFIG_WLAN_80211 is not set
552# CONFIG_IWLWIFI_LEDS is not set
553
554#
555# USB Network Adapters
556#
557# CONFIG_USB_CATC is not set
558# CONFIG_USB_KAWETH is not set
559# CONFIG_USB_PEGASUS is not set
560# CONFIG_USB_RTL8150 is not set
561# CONFIG_USB_USBNET is not set
562# CONFIG_WAN is not set
563# CONFIG_PPP is not set
564# CONFIG_SLIP is not set
565# CONFIG_NETCONSOLE is not set
566# CONFIG_NETPOLL is not set
567# CONFIG_NET_POLL_CONTROLLER is not set
568# CONFIG_ISDN is not set
569
570#
571# Input device support
572#
573CONFIG_INPUT=y
574# CONFIG_INPUT_FF_MEMLESS is not set
575# CONFIG_INPUT_POLLDEV is not set
576
577#
578# Userland interfaces
579#
580CONFIG_INPUT_MOUSEDEV=y
581CONFIG_INPUT_MOUSEDEV_PSAUX=y
582CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
583CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
584# CONFIG_INPUT_JOYDEV is not set
585# CONFIG_INPUT_EVDEV is not set
586# CONFIG_INPUT_EVBUG is not set
587
588#
589# Input Device Drivers
590#
591# CONFIG_INPUT_KEYBOARD is not set
592# CONFIG_INPUT_MOUSE is not set
593# CONFIG_INPUT_JOYSTICK is not set
594# CONFIG_INPUT_TABLET is not set
595# CONFIG_INPUT_TOUCHSCREEN is not set
596# CONFIG_INPUT_MISC is not set
597
598#
599# Hardware I/O ports
600#
601# CONFIG_SERIO is not set
602# CONFIG_GAMEPORT is not set
603
604#
605# Character devices
606#
607CONFIG_VT=y
608CONFIG_VT_CONSOLE=y
609CONFIG_HW_CONSOLE=y
610# CONFIG_VT_HW_CONSOLE_BINDING is not set
611CONFIG_DEVKMEM=y
612# CONFIG_SERIAL_NONSTANDARD is not set
613
614#
615# Serial drivers
616#
617CONFIG_SERIAL_8250=y
618CONFIG_SERIAL_8250_CONSOLE=y
619CONFIG_SERIAL_8250_NR_UARTS=4
620CONFIG_SERIAL_8250_RUNTIME_UARTS=2
621# CONFIG_SERIAL_8250_EXTENDED is not set
622
623#
624# Non-8250 serial port support
625#
626CONFIG_SERIAL_CORE=y
627CONFIG_SERIAL_CORE_CONSOLE=y
628CONFIG_UNIX98_PTYS=y
629CONFIG_LEGACY_PTYS=y
630CONFIG_LEGACY_PTY_COUNT=16
631# CONFIG_IPMI_HANDLER is not set
632CONFIG_HW_RANDOM=m
633# CONFIG_NVRAM is not set
634# CONFIG_R3964 is not set
635# CONFIG_RAW_DRIVER is not set
636# CONFIG_TCG_TPM is not set
637CONFIG_I2C=y
638CONFIG_I2C_BOARDINFO=y
639CONFIG_I2C_CHARDEV=y
640
641#
642# I2C Hardware Bus support
643#
644# CONFIG_I2C_OCORES is not set
645# CONFIG_I2C_PARPORT_LIGHT is not set
646# CONFIG_I2C_SIMTEC is not set
647# CONFIG_I2C_TAOS_EVM is not set
648# CONFIG_I2C_STUB is not set
649# CONFIG_I2C_TINY_USB is not set
650# CONFIG_I2C_PCA_PLATFORM is not set
651CONFIG_I2C_MV64XXX=y
652
653#
654# Miscellaneous I2C Chip support
655#
656# CONFIG_DS1682 is not set
657# CONFIG_SENSORS_EEPROM is not set
658# CONFIG_SENSORS_PCF8574 is not set
659# CONFIG_PCF8575 is not set
660# CONFIG_SENSORS_PCF8591 is not set
661# CONFIG_SENSORS_MAX6875 is not set
662# CONFIG_SENSORS_TSL2550 is not set
663# CONFIG_I2C_DEBUG_CORE is not set
664# CONFIG_I2C_DEBUG_ALGO is not set
665# CONFIG_I2C_DEBUG_BUS is not set
666# CONFIG_I2C_DEBUG_CHIP is not set
667CONFIG_SPI=y
668CONFIG_SPI_MASTER=y
669
670#
671# SPI Master Controller Drivers
672#
673# CONFIG_SPI_BITBANG is not set
674
675#
676# SPI Protocol Masters
677#
678# CONFIG_SPI_AT25 is not set
679# CONFIG_SPI_SPIDEV is not set
680# CONFIG_SPI_TLE62X0 is not set
681# CONFIG_W1 is not set
682# CONFIG_POWER_SUPPLY is not set
683# CONFIG_HWMON is not set
684# CONFIG_WATCHDOG is not set
685
686#
687# Sonics Silicon Backplane
688#
689CONFIG_SSB_POSSIBLE=y
690# CONFIG_SSB is not set
691
692#
693# Multifunction device drivers
694#
695# CONFIG_MFD_SM501 is not set
696# CONFIG_MFD_ASIC3 is not set
697# CONFIG_HTC_PASIC3 is not set
698
699#
700# Multimedia devices
701#
702
703#
704# Multimedia core support
705#
706# CONFIG_VIDEO_DEV is not set
707# CONFIG_DVB_CORE is not set
708# CONFIG_VIDEO_MEDIA is not set
709
710#
711# Multimedia drivers
712#
713# CONFIG_DAB is not set
714
715#
716# Graphics support
717#
718# CONFIG_VGASTATE is not set
719# CONFIG_VIDEO_OUTPUT_CONTROL is not set
720# CONFIG_FB is not set
721# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
722
723#
724# Display device support
725#
726# CONFIG_DISPLAY_SUPPORT is not set
727
728#
729# Console display driver support
730#
731# CONFIG_VGA_CONSOLE is not set
732CONFIG_DUMMY_CONSOLE=y
733
734#
735# Sound
736#
737# CONFIG_SOUND is not set
738CONFIG_HID_SUPPORT=y
739CONFIG_HID=y
740# CONFIG_HID_DEBUG is not set
741# CONFIG_HIDRAW is not set
742
743#
744# USB Input Devices
745#
746CONFIG_USB_HID=y
747# CONFIG_USB_HIDINPUT_POWERBOOK is not set
748# CONFIG_HID_FF is not set
749# CONFIG_USB_HIDDEV is not set
750CONFIG_USB_SUPPORT=y
751CONFIG_USB_ARCH_HAS_HCD=y
752# CONFIG_USB_ARCH_HAS_OHCI is not set
753# CONFIG_USB_ARCH_HAS_EHCI is not set
754CONFIG_USB=y
755# CONFIG_USB_DEBUG is not set
756# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
757
758#
759# Miscellaneous USB options
760#
761CONFIG_USB_DEVICEFS=y
762CONFIG_USB_DEVICE_CLASS=y
763# CONFIG_USB_DYNAMIC_MINORS is not set
764# CONFIG_USB_OTG is not set
765# CONFIG_USB_OTG_WHITELIST is not set
766# CONFIG_USB_OTG_BLACKLIST_HUB is not set
767
768#
769# USB Host Controller Drivers
770#
771# CONFIG_USB_C67X00_HCD is not set
772# CONFIG_USB_ISP116X_HCD is not set
773# CONFIG_USB_ISP1760_HCD is not set
774# CONFIG_USB_SL811_HCD is not set
775# CONFIG_USB_R8A66597_HCD is not set
776
777#
778# USB Device Class drivers
779#
780# CONFIG_USB_ACM is not set
781CONFIG_USB_PRINTER=y
782# CONFIG_USB_WDM is not set
783
784#
785# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
786#
787
788#
789# may also be needed; see USB_STORAGE Help for more information
790#
791CONFIG_USB_STORAGE=y
792# CONFIG_USB_STORAGE_DEBUG is not set
793CONFIG_USB_STORAGE_DATAFAB=y
794CONFIG_USB_STORAGE_FREECOM=y
795# CONFIG_USB_STORAGE_ISD200 is not set
796CONFIG_USB_STORAGE_DPCM=y
797# CONFIG_USB_STORAGE_USBAT is not set
798CONFIG_USB_STORAGE_SDDR09=y
799CONFIG_USB_STORAGE_SDDR55=y
800CONFIG_USB_STORAGE_JUMPSHOT=y
801# CONFIG_USB_STORAGE_ALAUDA is not set
802# CONFIG_USB_STORAGE_ONETOUCH is not set
803# CONFIG_USB_STORAGE_KARMA is not set
804# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
805# CONFIG_USB_LIBUSUAL is not set
806
807#
808# USB Imaging devices
809#
810# CONFIG_USB_MDC800 is not set
811# CONFIG_USB_MICROTEK is not set
812# CONFIG_USB_MON is not set
813
814#
815# USB port drivers
816#
817# CONFIG_USB_SERIAL is not set
818
819#
820# USB Miscellaneous drivers
821#
822# CONFIG_USB_EMI62 is not set
823# CONFIG_USB_EMI26 is not set
824# CONFIG_USB_ADUTUX is not set
825# CONFIG_USB_AUERSWALD is not set
826# CONFIG_USB_RIO500 is not set
827# CONFIG_USB_LEGOTOWER is not set
828# CONFIG_USB_LCD is not set
829# CONFIG_USB_BERRY_CHARGE is not set
830# CONFIG_USB_LED is not set
831# CONFIG_USB_CYPRESS_CY7C63 is not set
832# CONFIG_USB_CYTHERM is not set
833# CONFIG_USB_PHIDGET is not set
834# CONFIG_USB_IDMOUSE is not set
835# CONFIG_USB_FTDI_ELAN is not set
836# CONFIG_USB_APPLEDISPLAY is not set
837# CONFIG_USB_LD is not set
838# CONFIG_USB_TRANCEVIBRATOR is not set
839# CONFIG_USB_IOWARRIOR is not set
840# CONFIG_USB_TEST is not set
841# CONFIG_USB_ISIGHTFW is not set
842# CONFIG_USB_GADGET is not set
843# CONFIG_MMC is not set
844CONFIG_NEW_LEDS=y
845# CONFIG_LEDS_CLASS is not set
846
847#
848# LED drivers
849#
850
851#
852# LED Triggers
853#
854# CONFIG_LEDS_TRIGGERS is not set
855CONFIG_RTC_LIB=y
856# CONFIG_RTC_CLASS is not set
857# CONFIG_UIO is not set
858
859#
860# File systems
861#
862CONFIG_EXT2_FS=y
863# CONFIG_EXT2_FS_XATTR is not set
864# CONFIG_EXT2_FS_XIP is not set
865CONFIG_EXT3_FS=y
866# CONFIG_EXT3_FS_XATTR is not set
867# CONFIG_EXT4DEV_FS is not set
868CONFIG_JBD=y
869# CONFIG_REISERFS_FS is not set
870# CONFIG_JFS_FS is not set
871# CONFIG_FS_POSIX_ACL is not set
872CONFIG_XFS_FS=y
873# CONFIG_XFS_QUOTA is not set
874# CONFIG_XFS_POSIX_ACL is not set
875# CONFIG_XFS_RT is not set
876# CONFIG_XFS_DEBUG is not set
877# CONFIG_OCFS2_FS is not set
878CONFIG_DNOTIFY=y
879CONFIG_INOTIFY=y
880CONFIG_INOTIFY_USER=y
881# CONFIG_QUOTA is not set
882# CONFIG_AUTOFS_FS is not set
883# CONFIG_AUTOFS4_FS is not set
884# CONFIG_FUSE_FS is not set
885
886#
887# CD-ROM/DVD Filesystems
888#
889CONFIG_ISO9660_FS=y
890# CONFIG_JOLIET is not set
891# CONFIG_ZISOFS is not set
892CONFIG_UDF_FS=m
893CONFIG_UDF_NLS=y
894
895#
896# DOS/FAT/NT Filesystems
897#
898CONFIG_FAT_FS=y
899CONFIG_MSDOS_FS=y
900CONFIG_VFAT_FS=y
901CONFIG_FAT_DEFAULT_CODEPAGE=437
902CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
903# CONFIG_NTFS_FS is not set
904
905#
906# Pseudo filesystems
907#
908CONFIG_PROC_FS=y
909CONFIG_PROC_SYSCTL=y
910CONFIG_SYSFS=y
911CONFIG_TMPFS=y
912# CONFIG_TMPFS_POSIX_ACL is not set
913# CONFIG_HUGETLB_PAGE is not set
914# CONFIG_CONFIGFS_FS is not set
915
916#
917# Miscellaneous filesystems
918#
919# CONFIG_ADFS_FS is not set
920# CONFIG_AFFS_FS is not set
921# CONFIG_HFS_FS is not set
922# CONFIG_HFSPLUS_FS is not set
923# CONFIG_BEFS_FS is not set
924# CONFIG_BFS_FS is not set
925# CONFIG_EFS_FS is not set
926CONFIG_JFFS2_FS=y
927CONFIG_JFFS2_FS_DEBUG=0
928CONFIG_JFFS2_FS_WRITEBUFFER=y
929# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
930# CONFIG_JFFS2_SUMMARY is not set
931# CONFIG_JFFS2_FS_XATTR is not set
932# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
933CONFIG_JFFS2_ZLIB=y
934# CONFIG_JFFS2_LZO is not set
935CONFIG_JFFS2_RTIME=y
936# CONFIG_JFFS2_RUBIN is not set
937CONFIG_CRAMFS=y
938# CONFIG_VXFS_FS is not set
939# CONFIG_MINIX_FS is not set
940# CONFIG_HPFS_FS is not set
941# CONFIG_QNX4FS_FS is not set
942# CONFIG_ROMFS_FS is not set
943# CONFIG_SYSV_FS is not set
944# CONFIG_UFS_FS is not set
945CONFIG_NETWORK_FILESYSTEMS=y
946CONFIG_NFS_FS=y
947CONFIG_NFS_V3=y
948# CONFIG_NFS_V3_ACL is not set
949# CONFIG_NFS_V4 is not set
950# CONFIG_NFSD is not set
951CONFIG_ROOT_NFS=y
952CONFIG_LOCKD=y
953CONFIG_LOCKD_V4=y
954CONFIG_NFS_COMMON=y
955CONFIG_SUNRPC=y
956# CONFIG_SUNRPC_BIND34 is not set
957# CONFIG_RPCSEC_GSS_KRB5 is not set
958# CONFIG_RPCSEC_GSS_SPKM3 is not set
959# CONFIG_SMB_FS is not set
960# CONFIG_CIFS is not set
961# CONFIG_NCP_FS is not set
962# CONFIG_CODA_FS is not set
963# CONFIG_AFS_FS is not set
964
965#
966# Partition Types
967#
968CONFIG_PARTITION_ADVANCED=y
969# CONFIG_ACORN_PARTITION is not set
970# CONFIG_OSF_PARTITION is not set
971# CONFIG_AMIGA_PARTITION is not set
972# CONFIG_ATARI_PARTITION is not set
973# CONFIG_MAC_PARTITION is not set
974CONFIG_MSDOS_PARTITION=y
975CONFIG_BSD_DISKLABEL=y
976CONFIG_MINIX_SUBPARTITION=y
977CONFIG_SOLARIS_X86_PARTITION=y
978CONFIG_UNIXWARE_DISKLABEL=y
979CONFIG_LDM_PARTITION=y
980CONFIG_LDM_DEBUG=y
981# CONFIG_SGI_PARTITION is not set
982# CONFIG_ULTRIX_PARTITION is not set
983CONFIG_SUN_PARTITION=y
984# CONFIG_KARMA_PARTITION is not set
985# CONFIG_EFI_PARTITION is not set
986# CONFIG_SYSV68_PARTITION is not set
987CONFIG_NLS=y
988CONFIG_NLS_DEFAULT="iso8859-1"
989CONFIG_NLS_CODEPAGE_437=y
990# CONFIG_NLS_CODEPAGE_737 is not set
991# CONFIG_NLS_CODEPAGE_775 is not set
992CONFIG_NLS_CODEPAGE_850=y
993# CONFIG_NLS_CODEPAGE_852 is not set
994# CONFIG_NLS_CODEPAGE_855 is not set
995# CONFIG_NLS_CODEPAGE_857 is not set
996# CONFIG_NLS_CODEPAGE_860 is not set
997# CONFIG_NLS_CODEPAGE_861 is not set
998# CONFIG_NLS_CODEPAGE_862 is not set
999# CONFIG_NLS_CODEPAGE_863 is not set
1000# CONFIG_NLS_CODEPAGE_864 is not set
1001# CONFIG_NLS_CODEPAGE_865 is not set
1002# CONFIG_NLS_CODEPAGE_866 is not set
1003# CONFIG_NLS_CODEPAGE_869 is not set
1004# CONFIG_NLS_CODEPAGE_936 is not set
1005# CONFIG_NLS_CODEPAGE_950 is not set
1006# CONFIG_NLS_CODEPAGE_932 is not set
1007# CONFIG_NLS_CODEPAGE_949 is not set
1008# CONFIG_NLS_CODEPAGE_874 is not set
1009# CONFIG_NLS_ISO8859_8 is not set
1010# CONFIG_NLS_CODEPAGE_1250 is not set
1011# CONFIG_NLS_CODEPAGE_1251 is not set
1012# CONFIG_NLS_ASCII is not set
1013CONFIG_NLS_ISO8859_1=y
1014CONFIG_NLS_ISO8859_2=y
1015# CONFIG_NLS_ISO8859_3 is not set
1016# CONFIG_NLS_ISO8859_4 is not set
1017# CONFIG_NLS_ISO8859_5 is not set
1018# CONFIG_NLS_ISO8859_6 is not set
1019# CONFIG_NLS_ISO8859_7 is not set
1020# CONFIG_NLS_ISO8859_9 is not set
1021# CONFIG_NLS_ISO8859_13 is not set
1022# CONFIG_NLS_ISO8859_14 is not set
1023# CONFIG_NLS_ISO8859_15 is not set
1024# CONFIG_NLS_KOI8_R is not set
1025# CONFIG_NLS_KOI8_U is not set
1026# CONFIG_NLS_UTF8 is not set
1027# CONFIG_DLM is not set
1028
1029#
1030# Kernel hacking
1031#
1032# CONFIG_PRINTK_TIME is not set
1033CONFIG_ENABLE_WARN_DEPRECATED=y
1034CONFIG_ENABLE_MUST_CHECK=y
1035CONFIG_FRAME_WARN=1024
1036CONFIG_MAGIC_SYSRQ=y
1037# CONFIG_UNUSED_SYMBOLS is not set
1038# CONFIG_DEBUG_FS is not set
1039# CONFIG_HEADERS_CHECK is not set
1040# CONFIG_DEBUG_KERNEL is not set
1041# CONFIG_DEBUG_BUGVERBOSE is not set
1042CONFIG_FRAME_POINTER=y
1043# CONFIG_LATENCYTOP is not set
1044# CONFIG_SAMPLES is not set
1045CONFIG_DEBUG_USER=y
1046
1047#
1048# Security options
1049#
1050# CONFIG_KEYS is not set
1051# CONFIG_SECURITY is not set
1052# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1053CONFIG_CRYPTO=y
1054
1055#
1056# Crypto core or helper
1057#
1058CONFIG_CRYPTO_ALGAPI=m
1059CONFIG_CRYPTO_BLKCIPHER=m
1060CONFIG_CRYPTO_MANAGER=m
1061# CONFIG_CRYPTO_GF128MUL is not set
1062# CONFIG_CRYPTO_NULL is not set
1063# CONFIG_CRYPTO_CRYPTD is not set
1064# CONFIG_CRYPTO_AUTHENC is not set
1065# CONFIG_CRYPTO_TEST is not set
1066
1067#
1068# Authenticated Encryption with Associated Data
1069#
1070# CONFIG_CRYPTO_CCM is not set
1071# CONFIG_CRYPTO_GCM is not set
1072# CONFIG_CRYPTO_SEQIV is not set
1073
1074#
1075# Block modes
1076#
1077CONFIG_CRYPTO_CBC=m
1078# CONFIG_CRYPTO_CTR is not set
1079# CONFIG_CRYPTO_CTS is not set
1080CONFIG_CRYPTO_ECB=m
1081# CONFIG_CRYPTO_LRW is not set
1082CONFIG_CRYPTO_PCBC=m
1083# CONFIG_CRYPTO_XTS is not set
1084
1085#
1086# Hash modes
1087#
1088# CONFIG_CRYPTO_HMAC is not set
1089# CONFIG_CRYPTO_XCBC is not set
1090
1091#
1092# Digest
1093#
1094# CONFIG_CRYPTO_CRC32C is not set
1095# CONFIG_CRYPTO_MD4 is not set
1096# CONFIG_CRYPTO_MD5 is not set
1097# CONFIG_CRYPTO_MICHAEL_MIC is not set
1098# CONFIG_CRYPTO_SHA1 is not set
1099# CONFIG_CRYPTO_SHA256 is not set
1100# CONFIG_CRYPTO_SHA512 is not set
1101# CONFIG_CRYPTO_TGR192 is not set
1102# CONFIG_CRYPTO_WP512 is not set
1103
1104#
1105# Ciphers
1106#
1107# CONFIG_CRYPTO_AES is not set
1108# CONFIG_CRYPTO_ANUBIS is not set
1109# CONFIG_CRYPTO_ARC4 is not set
1110# CONFIG_CRYPTO_BLOWFISH is not set
1111# CONFIG_CRYPTO_CAMELLIA is not set
1112# CONFIG_CRYPTO_CAST5 is not set
1113# CONFIG_CRYPTO_CAST6 is not set
1114# CONFIG_CRYPTO_DES is not set
1115# CONFIG_CRYPTO_FCRYPT is not set
1116# CONFIG_CRYPTO_KHAZAD is not set
1117# CONFIG_CRYPTO_SALSA20 is not set
1118# CONFIG_CRYPTO_SEED is not set
1119# CONFIG_CRYPTO_SERPENT is not set
1120# CONFIG_CRYPTO_TEA is not set
1121# CONFIG_CRYPTO_TWOFISH is not set
1122
1123#
1124# Compression
1125#
1126# CONFIG_CRYPTO_DEFLATE is not set
1127# CONFIG_CRYPTO_LZO is not set
1128CONFIG_CRYPTO_HW=y
1129
1130#
1131# Library routines
1132#
1133CONFIG_BITREVERSE=y
1134# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1135# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1136CONFIG_CRC_CCITT=y
1137CONFIG_CRC16=y
1138CONFIG_CRC_ITU_T=m
1139CONFIG_CRC32=y
1140# CONFIG_CRC7 is not set
1141CONFIG_LIBCRC32C=y
1142CONFIG_ZLIB_INFLATE=y
1143CONFIG_ZLIB_DEFLATE=y
1144CONFIG_PLIST=y
1145CONFIG_HAS_IOMEM=y
1146CONFIG_HAS_IOPORT=y
1147CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig
index a3bf5833b87a..1a38d8e3fe66 100644
--- a/arch/arm/configs/lpd270_defconfig
+++ b/arch/arm/configs/lpd270_defconfig
@@ -173,7 +173,6 @@ CONFIG_XSCALE_PMU=y
173# Kernel Features 173# Kernel Features
174# 174#
175# CONFIG_PREEMPT is not set 175# CONFIG_PREEMPT is not set
176# CONFIG_NO_IDLE_HZ is not set
177CONFIG_HZ=100 176CONFIG_HZ=100
178# CONFIG_AEABI is not set 177# CONFIG_AEABI is not set
179# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 178# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 46a0f7fe1fa5..7a2e932da1c6 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -148,7 +148,6 @@ CONFIG_ARM_AMBA=y
148# Kernel Features 148# Kernel Features
149# 149#
150CONFIG_PREEMPT=y 150CONFIG_PREEMPT=y
151# CONFIG_NO_IDLE_HZ is not set
152# CONFIG_AEABI is not set 151# CONFIG_AEABI is not set
153CONFIG_ARCH_DISCONTIGMEM_ENABLE=y 152CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
154CONFIG_SELECT_MEMORY_MODEL=y 153CONFIG_SELECT_MEMORY_MODEL=y
diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
new file mode 100644
index 000000000000..d38ebf8721a4
--- /dev/null
+++ b/arch/arm/configs/mv78xx0_defconfig
@@ -0,0 +1,1445 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.26-rc5
4# Fri Jun 13 02:57:32 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8# CONFIG_GENERIC_GPIO is not set
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_HAVE_LATENCYTOP_SUPPORT=y
16CONFIG_LOCKDEP_SUPPORT=y
17CONFIG_TRACE_IRQFLAGS_SUPPORT=y
18CONFIG_HARDIRQS_SW_RESEND=y
19CONFIG_GENERIC_IRQ_PROBE=y
20CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U32 is not set
22# CONFIG_ARCH_HAS_ILOG2_U64 is not set
23CONFIG_GENERIC_HWEIGHT=y
24CONFIG_GENERIC_CALIBRATE_DELAY=y
25CONFIG_ARCH_SUPPORTS_AOUT=y
26CONFIG_ZONE_DMA=y
27CONFIG_VECTORS_BASE=0xffff0000
28CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
29
30#
31# General setup
32#
33CONFIG_EXPERIMENTAL=y
34CONFIG_BROKEN_ON_SMP=y
35CONFIG_LOCK_KERNEL=y
36CONFIG_INIT_ENV_ARG_LIMIT=32
37CONFIG_LOCALVERSION=""
38CONFIG_LOCALVERSION_AUTO=y
39CONFIG_SWAP=y
40CONFIG_SYSVIPC=y
41CONFIG_SYSVIPC_SYSCTL=y
42# CONFIG_POSIX_MQUEUE is not set
43# CONFIG_BSD_PROCESS_ACCT is not set
44# CONFIG_TASKSTATS is not set
45# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set
49# CONFIG_GROUP_SCHED is not set
50CONFIG_SYSFS_DEPRECATED=y
51CONFIG_SYSFS_DEPRECATED_V2=y
52# CONFIG_RELAY is not set
53# CONFIG_NAMESPACES is not set
54# CONFIG_BLK_DEV_INITRD is not set
55CONFIG_CC_OPTIMIZE_FOR_SIZE=y
56CONFIG_SYSCTL=y
57CONFIG_EMBEDDED=y
58CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y
60CONFIG_SYSCTL_SYSCALL_CHECK=y
61CONFIG_KALLSYMS=y
62CONFIG_KALLSYMS_ALL=y
63# CONFIG_KALLSYMS_EXTRA_PASS is not set
64CONFIG_HOTPLUG=y
65CONFIG_PRINTK=y
66CONFIG_BUG=y
67CONFIG_ELF_CORE=y
68CONFIG_COMPAT_BRK=y
69CONFIG_BASE_FULL=y
70CONFIG_FUTEX=y
71CONFIG_ANON_INODES=y
72CONFIG_EPOLL=y
73CONFIG_SIGNALFD=y
74CONFIG_TIMERFD=y
75CONFIG_EVENTFD=y
76CONFIG_SHMEM=y
77CONFIG_VM_EVENT_COUNTERS=y
78# CONFIG_SLUB_DEBUG is not set
79# CONFIG_SLAB is not set
80CONFIG_SLUB=y
81# CONFIG_SLOB is not set
82CONFIG_PROFILING=y
83# CONFIG_MARKERS is not set
84CONFIG_OPROFILE=y
85CONFIG_HAVE_OPROFILE=y
86CONFIG_KPROBES=y
87CONFIG_KRETPROBES=y
88CONFIG_HAVE_KPROBES=y
89CONFIG_HAVE_KRETPROBES=y
90# CONFIG_HAVE_DMA_ATTRS is not set
91CONFIG_PROC_PAGE_MONITOR=y
92CONFIG_RT_MUTEXES=y
93# CONFIG_TINY_SHMEM is not set
94CONFIG_BASE_SMALL=0
95CONFIG_MODULES=y
96# CONFIG_MODULE_FORCE_LOAD is not set
97CONFIG_MODULE_UNLOAD=y
98# CONFIG_MODULE_FORCE_UNLOAD is not set
99# CONFIG_MODVERSIONS is not set
100# CONFIG_MODULE_SRCVERSION_ALL is not set
101# CONFIG_KMOD is not set
102CONFIG_BLOCK=y
103# CONFIG_LBD is not set
104# CONFIG_BLK_DEV_IO_TRACE is not set
105# CONFIG_LSF is not set
106# CONFIG_BLK_DEV_BSG is not set
107
108#
109# IO Schedulers
110#
111CONFIG_IOSCHED_NOOP=y
112CONFIG_IOSCHED_AS=y
113CONFIG_IOSCHED_DEADLINE=y
114CONFIG_IOSCHED_CFQ=y
115# CONFIG_DEFAULT_AS is not set
116# CONFIG_DEFAULT_DEADLINE is not set
117CONFIG_DEFAULT_CFQ=y
118# CONFIG_DEFAULT_NOOP is not set
119CONFIG_DEFAULT_IOSCHED="cfq"
120CONFIG_CLASSIC_RCU=y
121
122#
123# System Type
124#
125# CONFIG_ARCH_AAEC2000 is not set
126# CONFIG_ARCH_INTEGRATOR is not set
127# CONFIG_ARCH_REALVIEW is not set
128# CONFIG_ARCH_VERSATILE is not set
129# CONFIG_ARCH_AT91 is not set
130# CONFIG_ARCH_CLPS7500 is not set
131# CONFIG_ARCH_CLPS711X is not set
132# CONFIG_ARCH_CO285 is not set
133# CONFIG_ARCH_EBSA110 is not set
134# CONFIG_ARCH_EP93XX is not set
135# CONFIG_ARCH_FOOTBRIDGE is not set
136# CONFIG_ARCH_NETX is not set
137# CONFIG_ARCH_H720X is not set
138# CONFIG_ARCH_IMX is not set
139# CONFIG_ARCH_IOP13XX is not set
140# CONFIG_ARCH_IOP32X is not set
141# CONFIG_ARCH_IOP33X is not set
142# CONFIG_ARCH_IXP23XX is not set
143# CONFIG_ARCH_IXP2000 is not set
144# CONFIG_ARCH_IXP4XX is not set
145# CONFIG_ARCH_L7200 is not set
146# CONFIG_ARCH_KIRKWOOD is not set
147# CONFIG_ARCH_KS8695 is not set
148# CONFIG_ARCH_NS9XXX is not set
149# CONFIG_ARCH_LOKI is not set
150CONFIG_ARCH_MV78XX0=y
151# CONFIG_ARCH_MXC is not set
152# CONFIG_ARCH_ORION5X is not set
153# CONFIG_ARCH_PNX4008 is not set
154# CONFIG_ARCH_PXA is not set
155# CONFIG_ARCH_RPC is not set
156# CONFIG_ARCH_SA1100 is not set
157# CONFIG_ARCH_S3C2410 is not set
158# CONFIG_ARCH_SHARK is not set
159# CONFIG_ARCH_LH7A40X is not set
160# CONFIG_ARCH_DAVINCI is not set
161# CONFIG_ARCH_OMAP is not set
162# CONFIG_ARCH_MSM7X00A is not set
163
164#
165# Marvell MV78xx0 Implementations
166#
167CONFIG_MACH_DB78X00_BP=y
168
169#
170# Boot options
171#
172
173#
174# Power management
175#
176CONFIG_PLAT_ORION=y
177
178#
179# Processor Type
180#
181CONFIG_CPU_32=y
182CONFIG_CPU_FEROCEON=y
183CONFIG_CPU_FEROCEON_OLD_ID=y
184CONFIG_CPU_32v5=y
185CONFIG_CPU_ABRT_EV5T=y
186CONFIG_CPU_PABRT_NOIFAR=y
187CONFIG_CPU_CACHE_VIVT=y
188CONFIG_CPU_COPY_FEROCEON=y
189CONFIG_CPU_TLB_FEROCEON=y
190CONFIG_CPU_CP15=y
191CONFIG_CPU_CP15_MMU=y
192
193#
194# Processor Features
195#
196CONFIG_ARM_THUMB=y
197# CONFIG_CPU_ICACHE_DISABLE is not set
198# CONFIG_CPU_DCACHE_DISABLE is not set
199CONFIG_OUTER_CACHE=y
200CONFIG_CACHE_FEROCEON_L2=y
201
202#
203# Bus support
204#
205CONFIG_PCI=y
206CONFIG_PCI_SYSCALL=y
207# CONFIG_ARCH_SUPPORTS_MSI is not set
208CONFIG_PCI_LEGACY=y
209# CONFIG_PCI_DEBUG is not set
210# CONFIG_PCCARD is not set
211
212#
213# Kernel Features
214#
215CONFIG_TICK_ONESHOT=y
216CONFIG_NO_HZ=y
217CONFIG_HIGH_RES_TIMERS=y
218CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
219CONFIG_PREEMPT=y
220CONFIG_HZ=100
221CONFIG_AEABI=y
222CONFIG_OABI_COMPAT=y
223# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
224CONFIG_SELECT_MEMORY_MODEL=y
225CONFIG_FLATMEM_MANUAL=y
226# CONFIG_DISCONTIGMEM_MANUAL is not set
227# CONFIG_SPARSEMEM_MANUAL is not set
228CONFIG_FLATMEM=y
229CONFIG_FLAT_NODE_MEM_MAP=y
230# CONFIG_SPARSEMEM_STATIC is not set
231# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
232CONFIG_PAGEFLAGS_EXTENDED=y
233CONFIG_SPLIT_PTLOCK_CPUS=4096
234# CONFIG_RESOURCES_64BIT is not set
235CONFIG_ZONE_DMA_FLAG=1
236CONFIG_BOUNCE=y
237CONFIG_VIRT_TO_BUS=y
238CONFIG_ALIGNMENT_TRAP=y
239
240#
241# Boot options
242#
243CONFIG_ZBOOT_ROM_TEXT=0x0
244CONFIG_ZBOOT_ROM_BSS=0x0
245CONFIG_CMDLINE=""
246# CONFIG_XIP_KERNEL is not set
247# CONFIG_KEXEC is not set
248
249#
250# Floating point emulation
251#
252
253#
254# At least one emulation must be selected
255#
256CONFIG_FPE_NWFPE=y
257# CONFIG_FPE_NWFPE_XP is not set
258# CONFIG_FPE_FASTFPE is not set
259CONFIG_VFP=y
260
261#
262# Userspace binary formats
263#
264CONFIG_BINFMT_ELF=y
265# CONFIG_BINFMT_AOUT is not set
266# CONFIG_BINFMT_MISC is not set
267
268#
269# Power management options
270#
271# CONFIG_PM is not set
272CONFIG_ARCH_SUSPEND_POSSIBLE=y
273
274#
275# Networking
276#
277CONFIG_NET=y
278
279#
280# Networking options
281#
282CONFIG_PACKET=y
283CONFIG_PACKET_MMAP=y
284CONFIG_UNIX=y
285CONFIG_XFRM=y
286# CONFIG_XFRM_USER is not set
287# CONFIG_XFRM_SUB_POLICY is not set
288# CONFIG_XFRM_MIGRATE is not set
289# CONFIG_XFRM_STATISTICS is not set
290# CONFIG_NET_KEY is not set
291CONFIG_INET=y
292CONFIG_IP_MULTICAST=y
293# CONFIG_IP_ADVANCED_ROUTER is not set
294CONFIG_IP_FIB_HASH=y
295CONFIG_IP_PNP=y
296CONFIG_IP_PNP_DHCP=y
297CONFIG_IP_PNP_BOOTP=y
298# CONFIG_IP_PNP_RARP is not set
299# CONFIG_NET_IPIP is not set
300# CONFIG_NET_IPGRE is not set
301# CONFIG_IP_MROUTE is not set
302# CONFIG_ARPD is not set
303# CONFIG_SYN_COOKIES is not set
304# CONFIG_INET_AH is not set
305# CONFIG_INET_ESP is not set
306# CONFIG_INET_IPCOMP is not set
307# CONFIG_INET_XFRM_TUNNEL is not set
308# CONFIG_INET_TUNNEL is not set
309CONFIG_INET_XFRM_MODE_TRANSPORT=y
310CONFIG_INET_XFRM_MODE_TUNNEL=y
311CONFIG_INET_XFRM_MODE_BEET=y
312# CONFIG_INET_LRO is not set
313CONFIG_INET_DIAG=y
314CONFIG_INET_TCP_DIAG=y
315# CONFIG_TCP_CONG_ADVANCED is not set
316CONFIG_TCP_CONG_CUBIC=y
317CONFIG_DEFAULT_TCP_CONG="cubic"
318# CONFIG_TCP_MD5SIG is not set
319# CONFIG_IPV6 is not set
320# CONFIG_NETWORK_SECMARK is not set
321# CONFIG_NETFILTER is not set
322# CONFIG_IP_DCCP is not set
323# CONFIG_IP_SCTP is not set
324# CONFIG_TIPC is not set
325# CONFIG_ATM is not set
326# CONFIG_BRIDGE is not set
327# CONFIG_VLAN_8021Q is not set
328# CONFIG_DECNET is not set
329# CONFIG_LLC2 is not set
330# CONFIG_IPX is not set
331# CONFIG_ATALK is not set
332# CONFIG_X25 is not set
333# CONFIG_LAPB is not set
334# CONFIG_ECONET is not set
335# CONFIG_WAN_ROUTER is not set
336# CONFIG_NET_SCHED is not set
337
338#
339# Network testing
340#
341CONFIG_NET_PKTGEN=m
342# CONFIG_NET_TCPPROBE is not set
343# CONFIG_HAMRADIO is not set
344# CONFIG_CAN is not set
345# CONFIG_IRDA is not set
346# CONFIG_BT is not set
347# CONFIG_AF_RXRPC is not set
348
349#
350# Wireless
351#
352# CONFIG_CFG80211 is not set
353CONFIG_WIRELESS_EXT=y
354# CONFIG_MAC80211 is not set
355# CONFIG_IEEE80211 is not set
356# CONFIG_RFKILL is not set
357# CONFIG_NET_9P is not set
358
359#
360# Device Drivers
361#
362
363#
364# Generic Driver Options
365#
366CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
367CONFIG_STANDALONE=y
368CONFIG_PREVENT_FIRMWARE_BUILD=y
369CONFIG_FW_LOADER=y
370# CONFIG_DEBUG_DRIVER is not set
371# CONFIG_DEBUG_DEVRES is not set
372# CONFIG_SYS_HYPERVISOR is not set
373# CONFIG_CONNECTOR is not set
374CONFIG_MTD=y
375# CONFIG_MTD_DEBUG is not set
376# CONFIG_MTD_CONCAT is not set
377CONFIG_MTD_PARTITIONS=y
378# CONFIG_MTD_REDBOOT_PARTS is not set
379CONFIG_MTD_CMDLINE_PARTS=y
380# CONFIG_MTD_AFS_PARTS is not set
381# CONFIG_MTD_AR7_PARTS is not set
382
383#
384# User Modules And Translation Layers
385#
386CONFIG_MTD_CHAR=y
387CONFIG_MTD_BLKDEVS=y
388CONFIG_MTD_BLOCK=y
389# CONFIG_FTL is not set
390# CONFIG_NFTL is not set
391# CONFIG_INFTL is not set
392# CONFIG_RFD_FTL is not set
393# CONFIG_SSFDC is not set
394# CONFIG_MTD_OOPS is not set
395
396#
397# RAM/ROM/Flash chip drivers
398#
399CONFIG_MTD_CFI=y
400CONFIG_MTD_JEDECPROBE=y
401CONFIG_MTD_GEN_PROBE=y
402CONFIG_MTD_CFI_ADV_OPTIONS=y
403CONFIG_MTD_CFI_NOSWAP=y
404# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
405# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
406CONFIG_MTD_CFI_GEOMETRY=y
407CONFIG_MTD_MAP_BANK_WIDTH_1=y
408CONFIG_MTD_MAP_BANK_WIDTH_2=y
409CONFIG_MTD_MAP_BANK_WIDTH_4=y
410# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
411# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
412# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
413CONFIG_MTD_CFI_I1=y
414CONFIG_MTD_CFI_I2=y
415# CONFIG_MTD_CFI_I4 is not set
416# CONFIG_MTD_CFI_I8 is not set
417# CONFIG_MTD_OTP is not set
418CONFIG_MTD_CFI_INTELEXT=y
419CONFIG_MTD_CFI_AMDSTD=y
420# CONFIG_MTD_CFI_STAA is not set
421CONFIG_MTD_CFI_UTIL=y
422# CONFIG_MTD_RAM is not set
423# CONFIG_MTD_ROM is not set
424# CONFIG_MTD_ABSENT is not set
425
426#
427# Mapping drivers for chip access
428#
429# CONFIG_MTD_COMPLEX_MAPPINGS is not set
430CONFIG_MTD_PHYSMAP=y
431CONFIG_MTD_PHYSMAP_START=0x0
432CONFIG_MTD_PHYSMAP_LEN=0x0
433CONFIG_MTD_PHYSMAP_BANKWIDTH=0
434# CONFIG_MTD_ARM_INTEGRATOR is not set
435# CONFIG_MTD_IMPA7 is not set
436# CONFIG_MTD_INTEL_VR_NOR is not set
437# CONFIG_MTD_PLATRAM is not set
438
439#
440# Self-contained MTD device drivers
441#
442# CONFIG_MTD_PMC551 is not set
443# CONFIG_MTD_SLRAM is not set
444# CONFIG_MTD_PHRAM is not set
445# CONFIG_MTD_MTDRAM is not set
446# CONFIG_MTD_BLOCK2MTD is not set
447
448#
449# Disk-On-Chip Device Drivers
450#
451# CONFIG_MTD_DOC2000 is not set
452# CONFIG_MTD_DOC2001 is not set
453# CONFIG_MTD_DOC2001PLUS is not set
454CONFIG_MTD_NAND=y
455CONFIG_MTD_NAND_VERIFY_WRITE=y
456# CONFIG_MTD_NAND_ECC_SMC is not set
457# CONFIG_MTD_NAND_MUSEUM_IDS is not set
458CONFIG_MTD_NAND_IDS=y
459# CONFIG_MTD_NAND_DISKONCHIP is not set
460# CONFIG_MTD_NAND_CAFE is not set
461# CONFIG_MTD_NAND_NANDSIM is not set
462# CONFIG_MTD_NAND_PLATFORM is not set
463# CONFIG_MTD_ALAUDA is not set
464CONFIG_MTD_NAND_ORION=y
465# CONFIG_MTD_ONENAND is not set
466
467#
468# UBI - Unsorted block images
469#
470# CONFIG_MTD_UBI is not set
471# CONFIG_PARPORT is not set
472CONFIG_BLK_DEV=y
473# CONFIG_BLK_CPQ_DA is not set
474# CONFIG_BLK_CPQ_CISS_DA is not set
475# CONFIG_BLK_DEV_DAC960 is not set
476# CONFIG_BLK_DEV_UMEM is not set
477# CONFIG_BLK_DEV_COW_COMMON is not set
478CONFIG_BLK_DEV_LOOP=y
479# CONFIG_BLK_DEV_CRYPTOLOOP is not set
480# CONFIG_BLK_DEV_NBD is not set
481# CONFIG_BLK_DEV_SX8 is not set
482# CONFIG_BLK_DEV_UB is not set
483# CONFIG_BLK_DEV_RAM is not set
484# CONFIG_CDROM_PKTCDVD is not set
485# CONFIG_ATA_OVER_ETH is not set
486CONFIG_MISC_DEVICES=y
487# CONFIG_PHANTOM is not set
488# CONFIG_EEPROM_93CX6 is not set
489# CONFIG_SGI_IOC4 is not set
490# CONFIG_TIFM_CORE is not set
491# CONFIG_ENCLOSURE_SERVICES is not set
492CONFIG_HAVE_IDE=y
493# CONFIG_IDE is not set
494
495#
496# SCSI device support
497#
498# CONFIG_RAID_ATTRS is not set
499CONFIG_SCSI=y
500CONFIG_SCSI_DMA=y
501# CONFIG_SCSI_TGT is not set
502# CONFIG_SCSI_NETLINK is not set
503# CONFIG_SCSI_PROC_FS is not set
504
505#
506# SCSI support type (disk, tape, CD-ROM)
507#
508CONFIG_BLK_DEV_SD=y
509# CONFIG_CHR_DEV_ST is not set
510# CONFIG_CHR_DEV_OSST is not set
511CONFIG_BLK_DEV_SR=m
512# CONFIG_BLK_DEV_SR_VENDOR is not set
513CONFIG_CHR_DEV_SG=m
514# CONFIG_CHR_DEV_SCH is not set
515
516#
517# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
518#
519# CONFIG_SCSI_MULTI_LUN is not set
520# CONFIG_SCSI_CONSTANTS is not set
521# CONFIG_SCSI_LOGGING is not set
522# CONFIG_SCSI_SCAN_ASYNC is not set
523CONFIG_SCSI_WAIT_SCAN=m
524
525#
526# SCSI Transports
527#
528# CONFIG_SCSI_SPI_ATTRS is not set
529# CONFIG_SCSI_FC_ATTRS is not set
530# CONFIG_SCSI_ISCSI_ATTRS is not set
531# CONFIG_SCSI_SAS_LIBSAS is not set
532# CONFIG_SCSI_SRP_ATTRS is not set
533CONFIG_SCSI_LOWLEVEL=y
534# CONFIG_ISCSI_TCP is not set
535# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
536# CONFIG_SCSI_3W_9XXX is not set
537# CONFIG_SCSI_ACARD is not set
538# CONFIG_SCSI_AACRAID is not set
539# CONFIG_SCSI_AIC7XXX is not set
540# CONFIG_SCSI_AIC7XXX_OLD is not set
541# CONFIG_SCSI_AIC79XX is not set
542# CONFIG_SCSI_AIC94XX is not set
543# CONFIG_SCSI_DPT_I2O is not set
544# CONFIG_SCSI_ADVANSYS is not set
545# CONFIG_SCSI_ARCMSR is not set
546# CONFIG_MEGARAID_NEWGEN is not set
547# CONFIG_MEGARAID_LEGACY is not set
548# CONFIG_MEGARAID_SAS is not set
549# CONFIG_SCSI_HPTIOP is not set
550# CONFIG_SCSI_DMX3191D is not set
551# CONFIG_SCSI_FUTURE_DOMAIN is not set
552# CONFIG_SCSI_IPS is not set
553# CONFIG_SCSI_INITIO is not set
554# CONFIG_SCSI_INIA100 is not set
555# CONFIG_SCSI_MVSAS is not set
556# CONFIG_SCSI_STEX is not set
557# CONFIG_SCSI_SYM53C8XX_2 is not set
558# CONFIG_SCSI_IPR is not set
559# CONFIG_SCSI_QLOGIC_1280 is not set
560# CONFIG_SCSI_QLA_FC is not set
561# CONFIG_SCSI_QLA_ISCSI is not set
562# CONFIG_SCSI_LPFC is not set
563# CONFIG_SCSI_DC395x is not set
564# CONFIG_SCSI_DC390T is not set
565# CONFIG_SCSI_NSP32 is not set
566# CONFIG_SCSI_DEBUG is not set
567# CONFIG_SCSI_SRP is not set
568CONFIG_ATA=y
569# CONFIG_ATA_NONSTANDARD is not set
570CONFIG_SATA_PMP=y
571# CONFIG_SATA_AHCI is not set
572# CONFIG_SATA_SIL24 is not set
573CONFIG_ATA_SFF=y
574# CONFIG_SATA_SVW is not set
575# CONFIG_ATA_PIIX is not set
576CONFIG_SATA_MV=y
577# CONFIG_SATA_NV is not set
578# CONFIG_PDC_ADMA is not set
579# CONFIG_SATA_QSTOR is not set
580# CONFIG_SATA_PROMISE is not set
581# CONFIG_SATA_SX4 is not set
582# CONFIG_SATA_SIL is not set
583# CONFIG_SATA_SIS is not set
584# CONFIG_SATA_ULI is not set
585# CONFIG_SATA_VIA is not set
586# CONFIG_SATA_VITESSE is not set
587# CONFIG_SATA_INIC162X is not set
588# CONFIG_PATA_ALI is not set
589# CONFIG_PATA_AMD is not set
590# CONFIG_PATA_ARTOP is not set
591# CONFIG_PATA_ATIIXP is not set
592# CONFIG_PATA_CMD640_PCI is not set
593# CONFIG_PATA_CMD64X is not set
594# CONFIG_PATA_CS5520 is not set
595# CONFIG_PATA_CS5530 is not set
596# CONFIG_PATA_CYPRESS is not set
597# CONFIG_PATA_EFAR is not set
598# CONFIG_ATA_GENERIC is not set
599# CONFIG_PATA_HPT366 is not set
600# CONFIG_PATA_HPT37X is not set
601# CONFIG_PATA_HPT3X2N is not set
602# CONFIG_PATA_HPT3X3 is not set
603# CONFIG_PATA_IT821X is not set
604# CONFIG_PATA_IT8213 is not set
605# CONFIG_PATA_JMICRON is not set
606# CONFIG_PATA_TRIFLEX is not set
607# CONFIG_PATA_MARVELL is not set
608# CONFIG_PATA_MPIIX is not set
609# CONFIG_PATA_OLDPIIX is not set
610# CONFIG_PATA_NETCELL is not set
611# CONFIG_PATA_NINJA32 is not set
612# CONFIG_PATA_NS87410 is not set
613# CONFIG_PATA_NS87415 is not set
614# CONFIG_PATA_OPTI is not set
615# CONFIG_PATA_OPTIDMA is not set
616# CONFIG_PATA_PDC_OLD is not set
617# CONFIG_PATA_RADISYS is not set
618# CONFIG_PATA_RZ1000 is not set
619# CONFIG_PATA_SC1200 is not set
620# CONFIG_PATA_SERVERWORKS is not set
621# CONFIG_PATA_PDC2027X is not set
622# CONFIG_PATA_SIL680 is not set
623# CONFIG_PATA_SIS is not set
624# CONFIG_PATA_VIA is not set
625# CONFIG_PATA_WINBOND is not set
626# CONFIG_PATA_PLATFORM is not set
627# CONFIG_PATA_SCH is not set
628# CONFIG_MD is not set
629# CONFIG_FUSION is not set
630
631#
632# IEEE 1394 (FireWire) support
633#
634# CONFIG_FIREWIRE is not set
635# CONFIG_IEEE1394 is not set
636# CONFIG_I2O is not set
637CONFIG_NETDEVICES=y
638# CONFIG_NETDEVICES_MULTIQUEUE is not set
639# CONFIG_DUMMY is not set
640# CONFIG_BONDING is not set
641# CONFIG_MACVLAN is not set
642# CONFIG_EQUALIZER is not set
643# CONFIG_TUN is not set
644# CONFIG_VETH is not set
645# CONFIG_ARCNET is not set
646# CONFIG_PHYLIB is not set
647CONFIG_NET_ETHERNET=y
648CONFIG_MII=y
649# CONFIG_AX88796 is not set
650# CONFIG_HAPPYMEAL is not set
651# CONFIG_SUNGEM is not set
652# CONFIG_CASSINI is not set
653# CONFIG_NET_VENDOR_3COM is not set
654# CONFIG_SMC91X is not set
655# CONFIG_DM9000 is not set
656# CONFIG_NET_TULIP is not set
657# CONFIG_HP100 is not set
658# CONFIG_IBM_NEW_EMAC_ZMII is not set
659# CONFIG_IBM_NEW_EMAC_RGMII is not set
660# CONFIG_IBM_NEW_EMAC_TAH is not set
661# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
662CONFIG_NET_PCI=y
663# CONFIG_PCNET32 is not set
664# CONFIG_AMD8111_ETH is not set
665# CONFIG_ADAPTEC_STARFIRE is not set
666# CONFIG_B44 is not set
667# CONFIG_FORCEDETH is not set
668# CONFIG_EEPRO100 is not set
669# CONFIG_E100 is not set
670# CONFIG_FEALNX is not set
671# CONFIG_NATSEMI is not set
672# CONFIG_NE2K_PCI is not set
673# CONFIG_8139CP is not set
674# CONFIG_8139TOO is not set
675# CONFIG_R6040 is not set
676# CONFIG_SIS900 is not set
677# CONFIG_EPIC100 is not set
678# CONFIG_SUNDANCE is not set
679# CONFIG_TLAN is not set
680# CONFIG_VIA_RHINE is not set
681# CONFIG_SC92031 is not set
682CONFIG_NETDEV_1000=y
683# CONFIG_ACENIC is not set
684# CONFIG_DL2K is not set
685# CONFIG_E1000 is not set
686# CONFIG_E1000E is not set
687# CONFIG_E1000E_ENABLED is not set
688# CONFIG_IP1000 is not set
689# CONFIG_IGB is not set
690# CONFIG_NS83820 is not set
691# CONFIG_HAMACHI is not set
692# CONFIG_YELLOWFIN is not set
693# CONFIG_R8169 is not set
694# CONFIG_SIS190 is not set
695# CONFIG_SKGE is not set
696# CONFIG_SKY2 is not set
697# CONFIG_VIA_VELOCITY is not set
698# CONFIG_TIGON3 is not set
699# CONFIG_BNX2 is not set
700CONFIG_MV643XX_ETH=y
701# CONFIG_QLA3XXX is not set
702# CONFIG_ATL1 is not set
703# CONFIG_NETDEV_10000 is not set
704# CONFIG_TR is not set
705
706#
707# Wireless LAN
708#
709# CONFIG_WLAN_PRE80211 is not set
710# CONFIG_WLAN_80211 is not set
711# CONFIG_IWLWIFI_LEDS is not set
712
713#
714# USB Network Adapters
715#
716# CONFIG_USB_CATC is not set
717# CONFIG_USB_KAWETH is not set
718# CONFIG_USB_PEGASUS is not set
719# CONFIG_USB_RTL8150 is not set
720# CONFIG_USB_USBNET is not set
721# CONFIG_WAN is not set
722# CONFIG_FDDI is not set
723# CONFIG_HIPPI is not set
724# CONFIG_PPP is not set
725# CONFIG_SLIP is not set
726# CONFIG_NET_FC is not set
727# CONFIG_NETCONSOLE is not set
728# CONFIG_NETPOLL is not set
729# CONFIG_NET_POLL_CONTROLLER is not set
730# CONFIG_ISDN is not set
731
732#
733# Input device support
734#
735CONFIG_INPUT=y
736# CONFIG_INPUT_FF_MEMLESS is not set
737# CONFIG_INPUT_POLLDEV is not set
738
739#
740# Userland interfaces
741#
742# CONFIG_INPUT_MOUSEDEV is not set
743# CONFIG_INPUT_JOYDEV is not set
744CONFIG_INPUT_EVDEV=y
745# CONFIG_INPUT_EVBUG is not set
746
747#
748# Input Device Drivers
749#
750# CONFIG_INPUT_KEYBOARD is not set
751# CONFIG_INPUT_MOUSE is not set
752# CONFIG_INPUT_JOYSTICK is not set
753# CONFIG_INPUT_TABLET is not set
754# CONFIG_INPUT_TOUCHSCREEN is not set
755# CONFIG_INPUT_MISC is not set
756
757#
758# Hardware I/O ports
759#
760# CONFIG_SERIO is not set
761# CONFIG_GAMEPORT is not set
762
763#
764# Character devices
765#
766# CONFIG_VT is not set
767CONFIG_DEVKMEM=y
768# CONFIG_SERIAL_NONSTANDARD is not set
769# CONFIG_NOZOMI is not set
770
771#
772# Serial drivers
773#
774CONFIG_SERIAL_8250=y
775CONFIG_SERIAL_8250_CONSOLE=y
776# CONFIG_SERIAL_8250_PCI is not set
777CONFIG_SERIAL_8250_NR_UARTS=4
778CONFIG_SERIAL_8250_RUNTIME_UARTS=2
779# CONFIG_SERIAL_8250_EXTENDED is not set
780
781#
782# Non-8250 serial port support
783#
784CONFIG_SERIAL_CORE=y
785CONFIG_SERIAL_CORE_CONSOLE=y
786# CONFIG_SERIAL_JSM is not set
787CONFIG_UNIX98_PTYS=y
788CONFIG_LEGACY_PTYS=y
789CONFIG_LEGACY_PTY_COUNT=16
790# CONFIG_IPMI_HANDLER is not set
791# CONFIG_HW_RANDOM is not set
792# CONFIG_NVRAM is not set
793# CONFIG_R3964 is not set
794# CONFIG_APPLICOM is not set
795# CONFIG_RAW_DRIVER is not set
796# CONFIG_TCG_TPM is not set
797CONFIG_DEVPORT=y
798CONFIG_I2C=y
799CONFIG_I2C_BOARDINFO=y
800CONFIG_I2C_CHARDEV=y
801
802#
803# I2C Hardware Bus support
804#
805# CONFIG_I2C_ALI1535 is not set
806# CONFIG_I2C_ALI1563 is not set
807# CONFIG_I2C_ALI15X3 is not set
808# CONFIG_I2C_AMD756 is not set
809# CONFIG_I2C_AMD8111 is not set
810# CONFIG_I2C_I801 is not set
811# CONFIG_I2C_I810 is not set
812# CONFIG_I2C_PIIX4 is not set
813# CONFIG_I2C_NFORCE2 is not set
814# CONFIG_I2C_OCORES is not set
815# CONFIG_I2C_PARPORT_LIGHT is not set
816# CONFIG_I2C_PROSAVAGE is not set
817# CONFIG_I2C_SAVAGE4 is not set
818# CONFIG_I2C_SIMTEC is not set
819# CONFIG_I2C_SIS5595 is not set
820# CONFIG_I2C_SIS630 is not set
821# CONFIG_I2C_SIS96X is not set
822# CONFIG_I2C_TAOS_EVM is not set
823# CONFIG_I2C_STUB is not set
824# CONFIG_I2C_TINY_USB is not set
825# CONFIG_I2C_VIA is not set
826# CONFIG_I2C_VIAPRO is not set
827# CONFIG_I2C_VOODOO3 is not set
828# CONFIG_I2C_PCA_PLATFORM is not set
829CONFIG_I2C_MV64XXX=y
830
831#
832# Miscellaneous I2C Chip support
833#
834# CONFIG_DS1682 is not set
835# CONFIG_SENSORS_EEPROM is not set
836# CONFIG_SENSORS_PCF8574 is not set
837# CONFIG_PCF8575 is not set
838# CONFIG_SENSORS_PCF8591 is not set
839# CONFIG_SENSORS_MAX6875 is not set
840# CONFIG_SENSORS_TSL2550 is not set
841# CONFIG_I2C_DEBUG_CORE is not set
842# CONFIG_I2C_DEBUG_ALGO is not set
843# CONFIG_I2C_DEBUG_BUS is not set
844# CONFIG_I2C_DEBUG_CHIP is not set
845# CONFIG_SPI is not set
846# CONFIG_W1 is not set
847# CONFIG_POWER_SUPPLY is not set
848CONFIG_HWMON=y
849# CONFIG_HWMON_VID is not set
850# CONFIG_SENSORS_AD7418 is not set
851# CONFIG_SENSORS_ADM1021 is not set
852# CONFIG_SENSORS_ADM1025 is not set
853# CONFIG_SENSORS_ADM1026 is not set
854# CONFIG_SENSORS_ADM1029 is not set
855# CONFIG_SENSORS_ADM1031 is not set
856# CONFIG_SENSORS_ADM9240 is not set
857# CONFIG_SENSORS_ADT7470 is not set
858# CONFIG_SENSORS_ADT7473 is not set
859# CONFIG_SENSORS_ATXP1 is not set
860# CONFIG_SENSORS_DS1621 is not set
861# CONFIG_SENSORS_I5K_AMB is not set
862# CONFIG_SENSORS_F71805F is not set
863# CONFIG_SENSORS_F71882FG is not set
864# CONFIG_SENSORS_F75375S is not set
865# CONFIG_SENSORS_GL518SM is not set
866# CONFIG_SENSORS_GL520SM is not set
867# CONFIG_SENSORS_IT87 is not set
868# CONFIG_SENSORS_LM63 is not set
869# CONFIG_SENSORS_LM75 is not set
870# CONFIG_SENSORS_LM77 is not set
871# CONFIG_SENSORS_LM78 is not set
872# CONFIG_SENSORS_LM80 is not set
873# CONFIG_SENSORS_LM83 is not set
874# CONFIG_SENSORS_LM85 is not set
875# CONFIG_SENSORS_LM87 is not set
876# CONFIG_SENSORS_LM90 is not set
877# CONFIG_SENSORS_LM92 is not set
878# CONFIG_SENSORS_LM93 is not set
879# CONFIG_SENSORS_MAX1619 is not set
880# CONFIG_SENSORS_MAX6650 is not set
881# CONFIG_SENSORS_PC87360 is not set
882# CONFIG_SENSORS_PC87427 is not set
883# CONFIG_SENSORS_SIS5595 is not set
884# CONFIG_SENSORS_DME1737 is not set
885# CONFIG_SENSORS_SMSC47M1 is not set
886# CONFIG_SENSORS_SMSC47M192 is not set
887# CONFIG_SENSORS_SMSC47B397 is not set
888# CONFIG_SENSORS_ADS7828 is not set
889# CONFIG_SENSORS_THMC50 is not set
890# CONFIG_SENSORS_VIA686A is not set
891# CONFIG_SENSORS_VT1211 is not set
892# CONFIG_SENSORS_VT8231 is not set
893# CONFIG_SENSORS_W83781D is not set
894# CONFIG_SENSORS_W83791D is not set
895# CONFIG_SENSORS_W83792D is not set
896# CONFIG_SENSORS_W83793 is not set
897# CONFIG_SENSORS_W83L785TS is not set
898# CONFIG_SENSORS_W83L786NG is not set
899# CONFIG_SENSORS_W83627HF is not set
900# CONFIG_SENSORS_W83627EHF is not set
901# CONFIG_HWMON_DEBUG_CHIP is not set
902# CONFIG_WATCHDOG is not set
903
904#
905# Sonics Silicon Backplane
906#
907CONFIG_SSB_POSSIBLE=y
908# CONFIG_SSB is not set
909
910#
911# Multifunction device drivers
912#
913# CONFIG_MFD_SM501 is not set
914# CONFIG_MFD_ASIC3 is not set
915# CONFIG_HTC_PASIC3 is not set
916
917#
918# Multimedia devices
919#
920
921#
922# Multimedia core support
923#
924# CONFIG_VIDEO_DEV is not set
925# CONFIG_DVB_CORE is not set
926# CONFIG_VIDEO_MEDIA is not set
927
928#
929# Multimedia drivers
930#
931# CONFIG_DAB is not set
932
933#
934# Graphics support
935#
936# CONFIG_DRM is not set
937# CONFIG_VGASTATE is not set
938# CONFIG_VIDEO_OUTPUT_CONTROL is not set
939# CONFIG_FB is not set
940# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
941
942#
943# Display device support
944#
945# CONFIG_DISPLAY_SUPPORT is not set
946
947#
948# Sound
949#
950# CONFIG_SOUND is not set
951CONFIG_HID_SUPPORT=y
952CONFIG_HID=y
953# CONFIG_HID_DEBUG is not set
954# CONFIG_HIDRAW is not set
955
956#
957# USB Input Devices
958#
959CONFIG_USB_HID=y
960# CONFIG_USB_HIDINPUT_POWERBOOK is not set
961# CONFIG_HID_FF is not set
962# CONFIG_USB_HIDDEV is not set
963CONFIG_USB_SUPPORT=y
964CONFIG_USB_ARCH_HAS_HCD=y
965CONFIG_USB_ARCH_HAS_OHCI=y
966CONFIG_USB_ARCH_HAS_EHCI=y
967CONFIG_USB=y
968# CONFIG_USB_DEBUG is not set
969# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
970
971#
972# Miscellaneous USB options
973#
974CONFIG_USB_DEVICEFS=y
975CONFIG_USB_DEVICE_CLASS=y
976# CONFIG_USB_DYNAMIC_MINORS is not set
977# CONFIG_USB_OTG is not set
978# CONFIG_USB_OTG_WHITELIST is not set
979# CONFIG_USB_OTG_BLACKLIST_HUB is not set
980
981#
982# USB Host Controller Drivers
983#
984# CONFIG_USB_C67X00_HCD is not set
985CONFIG_USB_EHCI_HCD=y
986CONFIG_USB_EHCI_ROOT_HUB_TT=y
987CONFIG_USB_EHCI_TT_NEWSCHED=y
988# CONFIG_USB_ISP116X_HCD is not set
989# CONFIG_USB_ISP1760_HCD is not set
990# CONFIG_USB_OHCI_HCD is not set
991# CONFIG_USB_UHCI_HCD is not set
992# CONFIG_USB_SL811_HCD is not set
993# CONFIG_USB_R8A66597_HCD is not set
994
995#
996# USB Device Class drivers
997#
998# CONFIG_USB_ACM is not set
999CONFIG_USB_PRINTER=y
1000# CONFIG_USB_WDM is not set
1001
1002#
1003# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1004#
1005
1006#
1007# may also be needed; see USB_STORAGE Help for more information
1008#
1009CONFIG_USB_STORAGE=y
1010# CONFIG_USB_STORAGE_DEBUG is not set
1011CONFIG_USB_STORAGE_DATAFAB=y
1012CONFIG_USB_STORAGE_FREECOM=y
1013# CONFIG_USB_STORAGE_ISD200 is not set
1014CONFIG_USB_STORAGE_DPCM=y
1015# CONFIG_USB_STORAGE_USBAT is not set
1016CONFIG_USB_STORAGE_SDDR09=y
1017CONFIG_USB_STORAGE_SDDR55=y
1018CONFIG_USB_STORAGE_JUMPSHOT=y
1019# CONFIG_USB_STORAGE_ALAUDA is not set
1020# CONFIG_USB_STORAGE_ONETOUCH is not set
1021# CONFIG_USB_STORAGE_KARMA is not set
1022# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1023# CONFIG_USB_LIBUSUAL is not set
1024
1025#
1026# USB Imaging devices
1027#
1028# CONFIG_USB_MDC800 is not set
1029# CONFIG_USB_MICROTEK is not set
1030# CONFIG_USB_MON is not set
1031
1032#
1033# USB port drivers
1034#
1035# CONFIG_USB_SERIAL is not set
1036
1037#
1038# USB Miscellaneous drivers
1039#
1040# CONFIG_USB_EMI62 is not set
1041# CONFIG_USB_EMI26 is not set
1042# CONFIG_USB_ADUTUX is not set
1043# CONFIG_USB_AUERSWALD is not set
1044# CONFIG_USB_RIO500 is not set
1045# CONFIG_USB_LEGOTOWER is not set
1046# CONFIG_USB_LCD is not set
1047# CONFIG_USB_BERRY_CHARGE is not set
1048# CONFIG_USB_LED is not set
1049# CONFIG_USB_CYPRESS_CY7C63 is not set
1050# CONFIG_USB_CYTHERM is not set
1051# CONFIG_USB_PHIDGET is not set
1052# CONFIG_USB_IDMOUSE is not set
1053# CONFIG_USB_FTDI_ELAN is not set
1054# CONFIG_USB_APPLEDISPLAY is not set
1055# CONFIG_USB_SISUSBVGA is not set
1056# CONFIG_USB_LD is not set
1057# CONFIG_USB_TRANCEVIBRATOR is not set
1058# CONFIG_USB_IOWARRIOR is not set
1059# CONFIG_USB_TEST is not set
1060# CONFIG_USB_ISIGHTFW is not set
1061# CONFIG_USB_GADGET is not set
1062# CONFIG_MMC is not set
1063CONFIG_NEW_LEDS=y
1064CONFIG_LEDS_CLASS=y
1065
1066#
1067# LED drivers
1068#
1069
1070#
1071# LED Triggers
1072#
1073CONFIG_LEDS_TRIGGERS=y
1074CONFIG_LEDS_TRIGGER_TIMER=y
1075CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1076# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1077CONFIG_RTC_LIB=y
1078CONFIG_RTC_CLASS=y
1079CONFIG_RTC_HCTOSYS=y
1080CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
1081# CONFIG_RTC_DEBUG is not set
1082
1083#
1084# RTC interfaces
1085#
1086CONFIG_RTC_INTF_SYSFS=y
1087CONFIG_RTC_INTF_PROC=y
1088CONFIG_RTC_INTF_DEV=y
1089# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1090# CONFIG_RTC_DRV_TEST is not set
1091
1092#
1093# I2C RTC drivers
1094#
1095CONFIG_RTC_DRV_DS1307=y
1096# CONFIG_RTC_DRV_DS1374 is not set
1097# CONFIG_RTC_DRV_DS1672 is not set
1098# CONFIG_RTC_DRV_MAX6900 is not set
1099CONFIG_RTC_DRV_RS5C372=y
1100# CONFIG_RTC_DRV_ISL1208 is not set
1101# CONFIG_RTC_DRV_X1205 is not set
1102# CONFIG_RTC_DRV_PCF8563 is not set
1103# CONFIG_RTC_DRV_PCF8583 is not set
1104CONFIG_RTC_DRV_M41T80=y
1105# CONFIG_RTC_DRV_M41T80_WDT is not set
1106# CONFIG_RTC_DRV_S35390A is not set
1107
1108#
1109# SPI RTC drivers
1110#
1111
1112#
1113# Platform RTC drivers
1114#
1115# CONFIG_RTC_DRV_CMOS is not set
1116# CONFIG_RTC_DRV_DS1511 is not set
1117# CONFIG_RTC_DRV_DS1553 is not set
1118# CONFIG_RTC_DRV_DS1742 is not set
1119# CONFIG_RTC_DRV_STK17TA8 is not set
1120# CONFIG_RTC_DRV_M48T86 is not set
1121# CONFIG_RTC_DRV_M48T59 is not set
1122# CONFIG_RTC_DRV_V3020 is not set
1123
1124#
1125# on-CPU RTC drivers
1126#
1127# CONFIG_UIO is not set
1128
1129#
1130# File systems
1131#
1132CONFIG_EXT2_FS=y
1133# CONFIG_EXT2_FS_XATTR is not set
1134# CONFIG_EXT2_FS_XIP is not set
1135CONFIG_EXT3_FS=y
1136# CONFIG_EXT3_FS_XATTR is not set
1137# CONFIG_EXT4DEV_FS is not set
1138CONFIG_JBD=y
1139# CONFIG_REISERFS_FS is not set
1140# CONFIG_JFS_FS is not set
1141# CONFIG_FS_POSIX_ACL is not set
1142# CONFIG_XFS_FS is not set
1143# CONFIG_OCFS2_FS is not set
1144CONFIG_DNOTIFY=y
1145CONFIG_INOTIFY=y
1146CONFIG_INOTIFY_USER=y
1147# CONFIG_QUOTA is not set
1148# CONFIG_AUTOFS_FS is not set
1149# CONFIG_AUTOFS4_FS is not set
1150# CONFIG_FUSE_FS is not set
1151
1152#
1153# CD-ROM/DVD Filesystems
1154#
1155CONFIG_ISO9660_FS=m
1156CONFIG_JOLIET=y
1157# CONFIG_ZISOFS is not set
1158CONFIG_UDF_FS=m
1159CONFIG_UDF_NLS=y
1160
1161#
1162# DOS/FAT/NT Filesystems
1163#
1164CONFIG_FAT_FS=y
1165CONFIG_MSDOS_FS=y
1166CONFIG_VFAT_FS=y
1167CONFIG_FAT_DEFAULT_CODEPAGE=437
1168CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1169# CONFIG_NTFS_FS is not set
1170
1171#
1172# Pseudo filesystems
1173#
1174CONFIG_PROC_FS=y
1175CONFIG_PROC_SYSCTL=y
1176CONFIG_SYSFS=y
1177CONFIG_TMPFS=y
1178# CONFIG_TMPFS_POSIX_ACL is not set
1179# CONFIG_HUGETLB_PAGE is not set
1180# CONFIG_CONFIGFS_FS is not set
1181
1182#
1183# Miscellaneous filesystems
1184#
1185# CONFIG_ADFS_FS is not set
1186# CONFIG_AFFS_FS is not set
1187# CONFIG_HFS_FS is not set
1188# CONFIG_HFSPLUS_FS is not set
1189# CONFIG_BEFS_FS is not set
1190# CONFIG_BFS_FS is not set
1191# CONFIG_EFS_FS is not set
1192CONFIG_JFFS2_FS=y
1193CONFIG_JFFS2_FS_DEBUG=0
1194CONFIG_JFFS2_FS_WRITEBUFFER=y
1195# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1196# CONFIG_JFFS2_SUMMARY is not set
1197# CONFIG_JFFS2_FS_XATTR is not set
1198# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1199CONFIG_JFFS2_ZLIB=y
1200# CONFIG_JFFS2_LZO is not set
1201CONFIG_JFFS2_RTIME=y
1202# CONFIG_JFFS2_RUBIN is not set
1203CONFIG_CRAMFS=y
1204# CONFIG_VXFS_FS is not set
1205# CONFIG_MINIX_FS is not set
1206# CONFIG_HPFS_FS is not set
1207# CONFIG_QNX4FS_FS is not set
1208# CONFIG_ROMFS_FS is not set
1209# CONFIG_SYSV_FS is not set
1210# CONFIG_UFS_FS is not set
1211CONFIG_NETWORK_FILESYSTEMS=y
1212CONFIG_NFS_FS=y
1213CONFIG_NFS_V3=y
1214# CONFIG_NFS_V3_ACL is not set
1215# CONFIG_NFS_V4 is not set
1216# CONFIG_NFSD is not set
1217CONFIG_ROOT_NFS=y
1218CONFIG_LOCKD=y
1219CONFIG_LOCKD_V4=y
1220CONFIG_NFS_COMMON=y
1221CONFIG_SUNRPC=y
1222# CONFIG_SUNRPC_BIND34 is not set
1223# CONFIG_RPCSEC_GSS_KRB5 is not set
1224# CONFIG_RPCSEC_GSS_SPKM3 is not set
1225# CONFIG_SMB_FS is not set
1226# CONFIG_CIFS is not set
1227# CONFIG_NCP_FS is not set
1228# CONFIG_CODA_FS is not set
1229# CONFIG_AFS_FS is not set
1230
1231#
1232# Partition Types
1233#
1234CONFIG_PARTITION_ADVANCED=y
1235# CONFIG_ACORN_PARTITION is not set
1236# CONFIG_OSF_PARTITION is not set
1237# CONFIG_AMIGA_PARTITION is not set
1238# CONFIG_ATARI_PARTITION is not set
1239# CONFIG_MAC_PARTITION is not set
1240CONFIG_MSDOS_PARTITION=y
1241CONFIG_BSD_DISKLABEL=y
1242# CONFIG_MINIX_SUBPARTITION is not set
1243# CONFIG_SOLARIS_X86_PARTITION is not set
1244# CONFIG_UNIXWARE_DISKLABEL is not set
1245# CONFIG_LDM_PARTITION is not set
1246# CONFIG_SGI_PARTITION is not set
1247# CONFIG_ULTRIX_PARTITION is not set
1248# CONFIG_SUN_PARTITION is not set
1249# CONFIG_KARMA_PARTITION is not set
1250# CONFIG_EFI_PARTITION is not set
1251# CONFIG_SYSV68_PARTITION is not set
1252CONFIG_NLS=y
1253CONFIG_NLS_DEFAULT="iso8859-1"
1254CONFIG_NLS_CODEPAGE_437=y
1255# CONFIG_NLS_CODEPAGE_737 is not set
1256# CONFIG_NLS_CODEPAGE_775 is not set
1257CONFIG_NLS_CODEPAGE_850=y
1258# CONFIG_NLS_CODEPAGE_852 is not set
1259# CONFIG_NLS_CODEPAGE_855 is not set
1260# CONFIG_NLS_CODEPAGE_857 is not set
1261# CONFIG_NLS_CODEPAGE_860 is not set
1262# CONFIG_NLS_CODEPAGE_861 is not set
1263# CONFIG_NLS_CODEPAGE_862 is not set
1264# CONFIG_NLS_CODEPAGE_863 is not set
1265# CONFIG_NLS_CODEPAGE_864 is not set
1266# CONFIG_NLS_CODEPAGE_865 is not set
1267# CONFIG_NLS_CODEPAGE_866 is not set
1268# CONFIG_NLS_CODEPAGE_869 is not set
1269# CONFIG_NLS_CODEPAGE_936 is not set
1270# CONFIG_NLS_CODEPAGE_950 is not set
1271# CONFIG_NLS_CODEPAGE_932 is not set
1272# CONFIG_NLS_CODEPAGE_949 is not set
1273# CONFIG_NLS_CODEPAGE_874 is not set
1274# CONFIG_NLS_ISO8859_8 is not set
1275# CONFIG_NLS_CODEPAGE_1250 is not set
1276# CONFIG_NLS_CODEPAGE_1251 is not set
1277# CONFIG_NLS_ASCII is not set
1278CONFIG_NLS_ISO8859_1=y
1279CONFIG_NLS_ISO8859_2=y
1280# CONFIG_NLS_ISO8859_3 is not set
1281# CONFIG_NLS_ISO8859_4 is not set
1282# CONFIG_NLS_ISO8859_5 is not set
1283# CONFIG_NLS_ISO8859_6 is not set
1284# CONFIG_NLS_ISO8859_7 is not set
1285# CONFIG_NLS_ISO8859_9 is not set
1286# CONFIG_NLS_ISO8859_13 is not set
1287# CONFIG_NLS_ISO8859_14 is not set
1288# CONFIG_NLS_ISO8859_15 is not set
1289# CONFIG_NLS_KOI8_R is not set
1290# CONFIG_NLS_KOI8_U is not set
1291# CONFIG_NLS_UTF8 is not set
1292# CONFIG_DLM is not set
1293
1294#
1295# Kernel hacking
1296#
1297# CONFIG_PRINTK_TIME is not set
1298CONFIG_ENABLE_WARN_DEPRECATED=y
1299CONFIG_ENABLE_MUST_CHECK=y
1300CONFIG_FRAME_WARN=1024
1301CONFIG_MAGIC_SYSRQ=y
1302# CONFIG_UNUSED_SYMBOLS is not set
1303# CONFIG_DEBUG_FS is not set
1304# CONFIG_HEADERS_CHECK is not set
1305CONFIG_DEBUG_KERNEL=y
1306# CONFIG_DEBUG_SHIRQ is not set
1307CONFIG_DETECT_SOFTLOCKUP=y
1308CONFIG_SCHED_DEBUG=y
1309CONFIG_SCHEDSTATS=y
1310# CONFIG_TIMER_STATS is not set
1311# CONFIG_DEBUG_OBJECTS is not set
1312CONFIG_DEBUG_PREEMPT=y
1313# CONFIG_DEBUG_RT_MUTEXES is not set
1314# CONFIG_RT_MUTEX_TESTER is not set
1315# CONFIG_DEBUG_SPINLOCK is not set
1316# CONFIG_DEBUG_MUTEXES is not set
1317# CONFIG_DEBUG_LOCK_ALLOC is not set
1318# CONFIG_PROVE_LOCKING is not set
1319# CONFIG_LOCK_STAT is not set
1320# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1321# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1322# CONFIG_DEBUG_KOBJECT is not set
1323# CONFIG_DEBUG_BUGVERBOSE is not set
1324CONFIG_DEBUG_INFO=y
1325# CONFIG_DEBUG_VM is not set
1326# CONFIG_DEBUG_WRITECOUNT is not set
1327# CONFIG_DEBUG_LIST is not set
1328# CONFIG_DEBUG_SG is not set
1329CONFIG_FRAME_POINTER=y
1330# CONFIG_BOOT_PRINTK_DELAY is not set
1331# CONFIG_RCU_TORTURE_TEST is not set
1332# CONFIG_KPROBES_SANITY_TEST is not set
1333# CONFIG_BACKTRACE_SELF_TEST is not set
1334# CONFIG_LKDTM is not set
1335# CONFIG_FAULT_INJECTION is not set
1336# CONFIG_LATENCYTOP is not set
1337# CONFIG_SAMPLES is not set
1338CONFIG_DEBUG_USER=y
1339CONFIG_DEBUG_ERRORS=y
1340# CONFIG_DEBUG_STACK_USAGE is not set
1341CONFIG_DEBUG_LL=y
1342# CONFIG_DEBUG_ICEDCC is not set
1343
1344#
1345# Security options
1346#
1347# CONFIG_KEYS is not set
1348# CONFIG_SECURITY is not set
1349# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1350CONFIG_CRYPTO=y
1351
1352#
1353# Crypto core or helper
1354#
1355CONFIG_CRYPTO_ALGAPI=m
1356CONFIG_CRYPTO_BLKCIPHER=m
1357CONFIG_CRYPTO_MANAGER=m
1358# CONFIG_CRYPTO_GF128MUL is not set
1359# CONFIG_CRYPTO_NULL is not set
1360# CONFIG_CRYPTO_CRYPTD is not set
1361# CONFIG_CRYPTO_AUTHENC is not set
1362# CONFIG_CRYPTO_TEST is not set
1363
1364#
1365# Authenticated Encryption with Associated Data
1366#
1367# CONFIG_CRYPTO_CCM is not set
1368# CONFIG_CRYPTO_GCM is not set
1369# CONFIG_CRYPTO_SEQIV is not set
1370
1371#
1372# Block modes
1373#
1374CONFIG_CRYPTO_CBC=m
1375# CONFIG_CRYPTO_CTR is not set
1376# CONFIG_CRYPTO_CTS is not set
1377CONFIG_CRYPTO_ECB=m
1378# CONFIG_CRYPTO_LRW is not set
1379CONFIG_CRYPTO_PCBC=m
1380# CONFIG_CRYPTO_XTS is not set
1381
1382#
1383# Hash modes
1384#
1385# CONFIG_CRYPTO_HMAC is not set
1386# CONFIG_CRYPTO_XCBC is not set
1387
1388#
1389# Digest
1390#
1391# CONFIG_CRYPTO_CRC32C is not set
1392# CONFIG_CRYPTO_MD4 is not set
1393# CONFIG_CRYPTO_MD5 is not set
1394# CONFIG_CRYPTO_MICHAEL_MIC is not set
1395# CONFIG_CRYPTO_SHA1 is not set
1396# CONFIG_CRYPTO_SHA256 is not set
1397# CONFIG_CRYPTO_SHA512 is not set
1398# CONFIG_CRYPTO_TGR192 is not set
1399# CONFIG_CRYPTO_WP512 is not set
1400
1401#
1402# Ciphers
1403#
1404# CONFIG_CRYPTO_AES is not set
1405# CONFIG_CRYPTO_ANUBIS is not set
1406# CONFIG_CRYPTO_ARC4 is not set
1407# CONFIG_CRYPTO_BLOWFISH is not set
1408# CONFIG_CRYPTO_CAMELLIA is not set
1409# CONFIG_CRYPTO_CAST5 is not set
1410# CONFIG_CRYPTO_CAST6 is not set
1411# CONFIG_CRYPTO_DES is not set
1412# CONFIG_CRYPTO_FCRYPT is not set
1413# CONFIG_CRYPTO_KHAZAD is not set
1414# CONFIG_CRYPTO_SALSA20 is not set
1415# CONFIG_CRYPTO_SEED is not set
1416# CONFIG_CRYPTO_SERPENT is not set
1417# CONFIG_CRYPTO_TEA is not set
1418# CONFIG_CRYPTO_TWOFISH is not set
1419
1420#
1421# Compression
1422#
1423# CONFIG_CRYPTO_DEFLATE is not set
1424# CONFIG_CRYPTO_LZO is not set
1425CONFIG_CRYPTO_HW=y
1426# CONFIG_CRYPTO_DEV_HIFN_795X is not set
1427
1428#
1429# Library routines
1430#
1431CONFIG_BITREVERSE=y
1432# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1433# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1434# CONFIG_CRC_CCITT is not set
1435# CONFIG_CRC16 is not set
1436CONFIG_CRC_ITU_T=m
1437CONFIG_CRC32=y
1438# CONFIG_CRC7 is not set
1439# CONFIG_LIBCRC32C is not set
1440CONFIG_ZLIB_INFLATE=y
1441CONFIG_ZLIB_DEFLATE=y
1442CONFIG_PLIST=y
1443CONFIG_HAS_IOMEM=y
1444CONFIG_HAS_IOPORT=y
1445CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/netx_defconfig b/arch/arm/configs/netx_defconfig
index 57f32f39d0ff..0884f2370c3a 100644
--- a/arch/arm/configs/netx_defconfig
+++ b/arch/arm/configs/netx_defconfig
@@ -154,7 +154,6 @@ CONFIG_ARM_AMBA=y
154# Kernel Features 154# Kernel Features
155# 155#
156CONFIG_PREEMPT=y 156CONFIG_PREEMPT=y
157# CONFIG_NO_IDLE_HZ is not set
158CONFIG_HZ=100 157CONFIG_HZ=100
159# CONFIG_AEABI is not set 158# CONFIG_AEABI is not set
160# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 159# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/onearm_defconfig b/arch/arm/configs/onearm_defconfig
index 650a248613e5..418ca2febbe3 100644
--- a/arch/arm/configs/onearm_defconfig
+++ b/arch/arm/configs/onearm_defconfig
@@ -202,7 +202,6 @@ CONFIG_AT91_CF=y
202# Kernel Features 202# Kernel Features
203# 203#
204# CONFIG_PREEMPT is not set 204# CONFIG_PREEMPT is not set
205# CONFIG_NO_IDLE_HZ is not set
206CONFIG_HZ=100 205CONFIG_HZ=100
207# CONFIG_AEABI is not set 206# CONFIG_AEABI is not set
208# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 207# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
index 52cd99bd52fb..9578b5d9f9c7 100644
--- a/arch/arm/configs/orion5x_defconfig
+++ b/arch/arm/configs/orion5x_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24 3# Linux kernel version: 2.6.26-rc4
4# Thu Feb 7 14:10:30 2008 4# Mon Jun 2 23:54:48 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -21,6 +21,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set 21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y 22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
24CONFIG_ZONE_DMA=y 25CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
@@ -40,24 +41,24 @@ CONFIG_SYSVIPC_SYSCTL=y
40# CONFIG_POSIX_MQUEUE is not set 41# CONFIG_POSIX_MQUEUE is not set
41# CONFIG_BSD_PROCESS_ACCT is not set 42# CONFIG_BSD_PROCESS_ACCT is not set
42# CONFIG_TASKSTATS is not set 43# CONFIG_TASKSTATS is not set
43# CONFIG_USER_NS is not set
44# CONFIG_PID_NS is not set
45# CONFIG_AUDIT is not set 44# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set 45# CONFIG_IKCONFIG is not set
47CONFIG_LOG_BUF_SHIFT=14 46CONFIG_LOG_BUF_SHIFT=14
48# CONFIG_CGROUPS is not set 47# CONFIG_CGROUPS is not set
49CONFIG_FAIR_GROUP_SCHED=y 48# CONFIG_GROUP_SCHED is not set
50CONFIG_FAIR_USER_SCHED=y
51# CONFIG_FAIR_CGROUP_SCHED is not set
52CONFIG_SYSFS_DEPRECATED=y 49CONFIG_SYSFS_DEPRECATED=y
50CONFIG_SYSFS_DEPRECATED_V2=y
53# CONFIG_RELAY is not set 51# CONFIG_RELAY is not set
52# CONFIG_NAMESPACES is not set
54# CONFIG_BLK_DEV_INITRD is not set 53# CONFIG_BLK_DEV_INITRD is not set
55CONFIG_CC_OPTIMIZE_FOR_SIZE=y 54CONFIG_CC_OPTIMIZE_FOR_SIZE=y
56CONFIG_SYSCTL=y 55CONFIG_SYSCTL=y
57CONFIG_EMBEDDED=y 56CONFIG_EMBEDDED=y
58CONFIG_UID16=y 57CONFIG_UID16=y
59CONFIG_SYSCTL_SYSCALL=y 58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_SYSCTL_SYSCALL_CHECK=y
60CONFIG_KALLSYMS=y 60CONFIG_KALLSYMS=y
61CONFIG_KALLSYMS_ALL=y
61# CONFIG_KALLSYMS_EXTRA_PASS is not set 62# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y 63CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y 64CONFIG_PRINTK=y
@@ -73,20 +74,25 @@ CONFIG_TIMERFD=y
73CONFIG_EVENTFD=y 74CONFIG_EVENTFD=y
74CONFIG_SHMEM=y 75CONFIG_SHMEM=y
75CONFIG_VM_EVENT_COUNTERS=y 76CONFIG_VM_EVENT_COUNTERS=y
76CONFIG_SLAB=y 77# CONFIG_SLUB_DEBUG is not set
77# CONFIG_SLUB is not set 78# CONFIG_SLAB is not set
79CONFIG_SLUB=y
78# CONFIG_SLOB is not set 80# CONFIG_SLOB is not set
79# CONFIG_PROFILING is not set 81CONFIG_PROFILING=y
80# CONFIG_MARKERS is not set 82# CONFIG_MARKERS is not set
83CONFIG_OPROFILE=y
81CONFIG_HAVE_OPROFILE=y 84CONFIG_HAVE_OPROFILE=y
82# CONFIG_KPROBES is not set 85CONFIG_KPROBES=y
86CONFIG_KRETPROBES=y
83CONFIG_HAVE_KPROBES=y 87CONFIG_HAVE_KPROBES=y
88CONFIG_HAVE_KRETPROBES=y
89# CONFIG_HAVE_DMA_ATTRS is not set
84CONFIG_PROC_PAGE_MONITOR=y 90CONFIG_PROC_PAGE_MONITOR=y
85CONFIG_SLABINFO=y
86CONFIG_RT_MUTEXES=y 91CONFIG_RT_MUTEXES=y
87# CONFIG_TINY_SHMEM is not set 92# CONFIG_TINY_SHMEM is not set
88CONFIG_BASE_SMALL=0 93CONFIG_BASE_SMALL=0
89CONFIG_MODULES=y 94CONFIG_MODULES=y
95# CONFIG_MODULE_FORCE_LOAD is not set
90CONFIG_MODULE_UNLOAD=y 96CONFIG_MODULE_UNLOAD=y
91# CONFIG_MODULE_FORCE_UNLOAD is not set 97# CONFIG_MODULE_FORCE_UNLOAD is not set
92# CONFIG_MODVERSIONS is not set 98# CONFIG_MODVERSIONS is not set
@@ -111,7 +117,6 @@ CONFIG_DEFAULT_CFQ=y
111# CONFIG_DEFAULT_NOOP is not set 117# CONFIG_DEFAULT_NOOP is not set
112CONFIG_DEFAULT_IOSCHED="cfq" 118CONFIG_DEFAULT_IOSCHED="cfq"
113CONFIG_CLASSIC_RCU=y 119CONFIG_CLASSIC_RCU=y
114# CONFIG_PREEMPT_RCU is not set
115 120
116# 121#
117# System Type 122# System Type
@@ -160,6 +165,15 @@ CONFIG_MACH_RD88F5182=y
160CONFIG_MACH_KUROBOX_PRO=y 165CONFIG_MACH_KUROBOX_PRO=y
161CONFIG_MACH_DNS323=y 166CONFIG_MACH_DNS323=y
162CONFIG_MACH_TS209=y 167CONFIG_MACH_TS209=y
168CONFIG_MACH_LINKSTATION_PRO=y
169CONFIG_MACH_TS409=y
170CONFIG_MACH_WRT350N_V2=y
171CONFIG_MACH_TS78XX=y
172CONFIG_MACH_MV2120=y
173CONFIG_MACH_MSS2=y
174CONFIG_MACH_WNR854T=y
175CONFIG_MACH_RD88F5181L_GE=y
176CONFIG_MACH_RD88F5181L_FXO=y
163 177
164# 178#
165# Boot options 179# Boot options
@@ -168,6 +182,7 @@ CONFIG_MACH_TS209=y
168# 182#
169# Power management 183# Power management
170# 184#
185CONFIG_PLAT_ORION=y
171 186
172# 187#
173# Processor Type 188# Processor Type
@@ -177,8 +192,9 @@ CONFIG_CPU_FEROCEON=y
177CONFIG_CPU_FEROCEON_OLD_ID=y 192CONFIG_CPU_FEROCEON_OLD_ID=y
178CONFIG_CPU_32v5=y 193CONFIG_CPU_32v5=y
179CONFIG_CPU_ABRT_EV5T=y 194CONFIG_CPU_ABRT_EV5T=y
195CONFIG_CPU_PABRT_NOIFAR=y
180CONFIG_CPU_CACHE_VIVT=y 196CONFIG_CPU_CACHE_VIVT=y
181CONFIG_CPU_COPY_V4WB=y 197CONFIG_CPU_COPY_FEROCEON=y
182CONFIG_CPU_TLB_V4WBI=y 198CONFIG_CPU_TLB_V4WBI=y
183CONFIG_CPU_CP15=y 199CONFIG_CPU_CP15=y
184CONFIG_CPU_CP15_MMU=y 200CONFIG_CPU_CP15_MMU=y
@@ -189,7 +205,6 @@ CONFIG_CPU_CP15_MMU=y
189CONFIG_ARM_THUMB=y 205CONFIG_ARM_THUMB=y
190# CONFIG_CPU_ICACHE_DISABLE is not set 206# CONFIG_CPU_ICACHE_DISABLE is not set
191# CONFIG_CPU_DCACHE_DISABLE is not set 207# CONFIG_CPU_DCACHE_DISABLE is not set
192# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
193# CONFIG_OUTER_CACHE is not set 208# CONFIG_OUTER_CACHE is not set
194 209
195# 210#
@@ -199,6 +214,7 @@ CONFIG_PCI=y
199CONFIG_PCI_SYSCALL=y 214CONFIG_PCI_SYSCALL=y
200# CONFIG_ARCH_SUPPORTS_MSI is not set 215# CONFIG_ARCH_SUPPORTS_MSI is not set
201CONFIG_PCI_LEGACY=y 216CONFIG_PCI_LEGACY=y
217# CONFIG_PCI_DEBUG is not set
202# CONFIG_PCCARD is not set 218# CONFIG_PCCARD is not set
203 219
204# 220#
@@ -221,6 +237,7 @@ CONFIG_FLATMEM=y
221CONFIG_FLAT_NODE_MEM_MAP=y 237CONFIG_FLAT_NODE_MEM_MAP=y
222# CONFIG_SPARSEMEM_STATIC is not set 238# CONFIG_SPARSEMEM_STATIC is not set
223# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set 239# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
240CONFIG_PAGEFLAGS_EXTENDED=y
224CONFIG_SPLIT_PTLOCK_CPUS=4096 241CONFIG_SPLIT_PTLOCK_CPUS=4096
225# CONFIG_RESOURCES_64BIT is not set 242# CONFIG_RESOURCES_64BIT is not set
226CONFIG_ZONE_DMA_FLAG=1 243CONFIG_ZONE_DMA_FLAG=1
@@ -238,7 +255,6 @@ CONFIG_ZBOOT_ROM_BSS=0x0
238CONFIG_CMDLINE="" 255CONFIG_CMDLINE=""
239# CONFIG_XIP_KERNEL is not set 256# CONFIG_XIP_KERNEL is not set
240# CONFIG_KEXEC is not set 257# CONFIG_KEXEC is not set
241# CONFIG_ATAGS_PROC is not set
242 258
243# 259#
244# Floating point emulation 260# Floating point emulation
@@ -311,8 +327,6 @@ CONFIG_TCP_CONG_CUBIC=y
311CONFIG_DEFAULT_TCP_CONG="cubic" 327CONFIG_DEFAULT_TCP_CONG="cubic"
312# CONFIG_TCP_MD5SIG is not set 328# CONFIG_TCP_MD5SIG is not set
313# CONFIG_IPV6 is not set 329# CONFIG_IPV6 is not set
314# CONFIG_INET6_XFRM_TUNNEL is not set
315# CONFIG_INET6_TUNNEL is not set
316# CONFIG_NETWORK_SECMARK is not set 330# CONFIG_NETWORK_SECMARK is not set
317# CONFIG_NETFILTER is not set 331# CONFIG_NETFILTER is not set
318# CONFIG_IP_DCCP is not set 332# CONFIG_IP_DCCP is not set
@@ -335,6 +349,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
335# Network testing 349# Network testing
336# 350#
337CONFIG_NET_PKTGEN=m 351CONFIG_NET_PKTGEN=m
352# CONFIG_NET_TCPPROBE is not set
338# CONFIG_HAMRADIO is not set 353# CONFIG_HAMRADIO is not set
339# CONFIG_CAN is not set 354# CONFIG_CAN is not set
340# CONFIG_IRDA is not set 355# CONFIG_IRDA is not set
@@ -362,6 +377,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
362CONFIG_STANDALONE=y 377CONFIG_STANDALONE=y
363CONFIG_PREVENT_FIRMWARE_BUILD=y 378CONFIG_PREVENT_FIRMWARE_BUILD=y
364CONFIG_FW_LOADER=y 379CONFIG_FW_LOADER=y
380# CONFIG_DEBUG_DRIVER is not set
381# CONFIG_DEBUG_DEVRES is not set
365# CONFIG_SYS_HYPERVISOR is not set 382# CONFIG_SYS_HYPERVISOR is not set
366# CONFIG_CONNECTOR is not set 383# CONFIG_CONNECTOR is not set
367CONFIG_MTD=y 384CONFIG_MTD=y
@@ -371,6 +388,7 @@ CONFIG_MTD_PARTITIONS=y
371# CONFIG_MTD_REDBOOT_PARTS is not set 388# CONFIG_MTD_REDBOOT_PARTS is not set
372CONFIG_MTD_CMDLINE_PARTS=y 389CONFIG_MTD_CMDLINE_PARTS=y
373# CONFIG_MTD_AFS_PARTS is not set 390# CONFIG_MTD_AFS_PARTS is not set
391# CONFIG_MTD_AR7_PARTS is not set
374 392
375# 393#
376# User Modules And Translation Layers 394# User Modules And Translation Layers
@@ -378,9 +396,8 @@ CONFIG_MTD_CMDLINE_PARTS=y
378CONFIG_MTD_CHAR=y 396CONFIG_MTD_CHAR=y
379CONFIG_MTD_BLKDEVS=y 397CONFIG_MTD_BLKDEVS=y
380CONFIG_MTD_BLOCK=y 398CONFIG_MTD_BLOCK=y
381CONFIG_FTL=y 399# CONFIG_FTL is not set
382CONFIG_NFTL=y 400# CONFIG_NFTL is not set
383# CONFIG_NFTL_RW is not set
384# CONFIG_INFTL is not set 401# CONFIG_INFTL is not set
385# CONFIG_RFD_FTL is not set 402# CONFIG_RFD_FTL is not set
386# CONFIG_SSFDC is not set 403# CONFIG_SSFDC is not set
@@ -405,12 +422,12 @@ CONFIG_MTD_MAP_BANK_WIDTH_4=y
405# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set 422# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
406CONFIG_MTD_CFI_I1=y 423CONFIG_MTD_CFI_I1=y
407CONFIG_MTD_CFI_I2=y 424CONFIG_MTD_CFI_I2=y
408CONFIG_MTD_CFI_I4=y 425# CONFIG_MTD_CFI_I4 is not set
409# CONFIG_MTD_CFI_I8 is not set 426# CONFIG_MTD_CFI_I8 is not set
410# CONFIG_MTD_OTP is not set 427# CONFIG_MTD_OTP is not set
411CONFIG_MTD_CFI_INTELEXT=y 428CONFIG_MTD_CFI_INTELEXT=y
412CONFIG_MTD_CFI_AMDSTD=y 429CONFIG_MTD_CFI_AMDSTD=y
413CONFIG_MTD_CFI_STAA=y 430# CONFIG_MTD_CFI_STAA is not set
414CONFIG_MTD_CFI_UTIL=y 431CONFIG_MTD_CFI_UTIL=y
415# CONFIG_MTD_RAM is not set 432# CONFIG_MTD_RAM is not set
416# CONFIG_MTD_ROM is not set 433# CONFIG_MTD_ROM is not set
@@ -481,6 +498,9 @@ CONFIG_MISC_DEVICES=y
481# CONFIG_EEPROM_93CX6 is not set 498# CONFIG_EEPROM_93CX6 is not set
482# CONFIG_SGI_IOC4 is not set 499# CONFIG_SGI_IOC4 is not set
483# CONFIG_TIFM_CORE is not set 500# CONFIG_TIFM_CORE is not set
501# CONFIG_ENCLOSURE_SERVICES is not set
502CONFIG_HAVE_IDE=y
503# CONFIG_IDE is not set
484 504
485# 505#
486# SCSI device support 506# SCSI device support
@@ -542,6 +562,7 @@ CONFIG_SCSI_LOWLEVEL=y
542# CONFIG_SCSI_IPS is not set 562# CONFIG_SCSI_IPS is not set
543# CONFIG_SCSI_INITIO is not set 563# CONFIG_SCSI_INITIO is not set
544# CONFIG_SCSI_INIA100 is not set 564# CONFIG_SCSI_INIA100 is not set
565# CONFIG_SCSI_MVSAS is not set
545# CONFIG_SCSI_STEX is not set 566# CONFIG_SCSI_STEX is not set
546# CONFIG_SCSI_SYM53C8XX_2 is not set 567# CONFIG_SCSI_SYM53C8XX_2 is not set
547# CONFIG_SCSI_IPR is not set 568# CONFIG_SCSI_IPR is not set
@@ -556,7 +577,10 @@ CONFIG_SCSI_LOWLEVEL=y
556# CONFIG_SCSI_SRP is not set 577# CONFIG_SCSI_SRP is not set
557CONFIG_ATA=y 578CONFIG_ATA=y
558# CONFIG_ATA_NONSTANDARD is not set 579# CONFIG_ATA_NONSTANDARD is not set
580CONFIG_SATA_PMP=y
559# CONFIG_SATA_AHCI is not set 581# CONFIG_SATA_AHCI is not set
582# CONFIG_SATA_SIL24 is not set
583CONFIG_ATA_SFF=y
560# CONFIG_SATA_SVW is not set 584# CONFIG_SATA_SVW is not set
561# CONFIG_ATA_PIIX is not set 585# CONFIG_ATA_PIIX is not set
562CONFIG_SATA_MV=y 586CONFIG_SATA_MV=y
@@ -566,7 +590,6 @@ CONFIG_SATA_MV=y
566# CONFIG_SATA_PROMISE is not set 590# CONFIG_SATA_PROMISE is not set
567# CONFIG_SATA_SX4 is not set 591# CONFIG_SATA_SX4 is not set
568# CONFIG_SATA_SIL is not set 592# CONFIG_SATA_SIL is not set
569# CONFIG_SATA_SIL24 is not set
570# CONFIG_SATA_SIS is not set 593# CONFIG_SATA_SIS is not set
571# CONFIG_SATA_ULI is not set 594# CONFIG_SATA_ULI is not set
572# CONFIG_SATA_VIA is not set 595# CONFIG_SATA_VIA is not set
@@ -611,6 +634,7 @@ CONFIG_SATA_MV=y
611# CONFIG_PATA_VIA is not set 634# CONFIG_PATA_VIA is not set
612# CONFIG_PATA_WINBOND is not set 635# CONFIG_PATA_WINBOND is not set
613# CONFIG_PATA_PLATFORM is not set 636# CONFIG_PATA_PLATFORM is not set
637# CONFIG_PATA_SCH is not set
614# CONFIG_MD is not set 638# CONFIG_MD is not set
615# CONFIG_FUSION is not set 639# CONFIG_FUSION is not set
616 640
@@ -652,7 +676,7 @@ CONFIG_NET_PCI=y
652# CONFIG_B44 is not set 676# CONFIG_B44 is not set
653# CONFIG_FORCEDETH is not set 677# CONFIG_FORCEDETH is not set
654# CONFIG_EEPRO100 is not set 678# CONFIG_EEPRO100 is not set
655CONFIG_E100=y 679# CONFIG_E100 is not set
656# CONFIG_FEALNX is not set 680# CONFIG_FEALNX is not set
657# CONFIG_NATSEMI is not set 681# CONFIG_NATSEMI is not set
658# CONFIG_NE2K_PCI is not set 682# CONFIG_NE2K_PCI is not set
@@ -668,9 +692,7 @@ CONFIG_E100=y
668CONFIG_NETDEV_1000=y 692CONFIG_NETDEV_1000=y
669# CONFIG_ACENIC is not set 693# CONFIG_ACENIC is not set
670# CONFIG_DL2K is not set 694# CONFIG_DL2K is not set
671CONFIG_E1000=y 695# CONFIG_E1000 is not set
672CONFIG_E1000_NAPI=y
673# CONFIG_E1000_DISABLE_PACKET_SPLIT is not set
674# CONFIG_E1000E is not set 696# CONFIG_E1000E is not set
675# CONFIG_E1000E_ENABLED is not set 697# CONFIG_E1000E_ENABLED is not set
676# CONFIG_IP1000 is not set 698# CONFIG_IP1000 is not set
@@ -680,27 +702,15 @@ CONFIG_E1000_NAPI=y
680# CONFIG_YELLOWFIN is not set 702# CONFIG_YELLOWFIN is not set
681# CONFIG_R8169 is not set 703# CONFIG_R8169 is not set
682# CONFIG_SIS190 is not set 704# CONFIG_SIS190 is not set
683CONFIG_SKGE=y 705# CONFIG_SKGE is not set
684CONFIG_SKY2=y 706# CONFIG_SKY2 is not set
685# CONFIG_SK98LIN is not set
686# CONFIG_VIA_VELOCITY is not set 707# CONFIG_VIA_VELOCITY is not set
687CONFIG_TIGON3=y 708# CONFIG_TIGON3 is not set
688# CONFIG_BNX2 is not set 709# CONFIG_BNX2 is not set
689CONFIG_MV643XX_ETH=y 710CONFIG_MV643XX_ETH=y
690# CONFIG_QLA3XXX is not set 711# CONFIG_QLA3XXX is not set
691# CONFIG_ATL1 is not set 712# CONFIG_ATL1 is not set
692CONFIG_NETDEV_10000=y 713# CONFIG_NETDEV_10000 is not set
693# CONFIG_CHELSIO_T1 is not set
694# CONFIG_CHELSIO_T3 is not set
695# CONFIG_IXGBE is not set
696# CONFIG_IXGB is not set
697# CONFIG_S2IO is not set
698# CONFIG_MYRI10GE is not set
699# CONFIG_NETXEN_NIC is not set
700# CONFIG_NIU is not set
701# CONFIG_MLX4_CORE is not set
702# CONFIG_TEHUTI is not set
703# CONFIG_BNX2X is not set
704# CONFIG_TR is not set 714# CONFIG_TR is not set
705 715
706# 716#
@@ -708,6 +718,7 @@ CONFIG_NETDEV_10000=y
708# 718#
709# CONFIG_WLAN_PRE80211 is not set 719# CONFIG_WLAN_PRE80211 is not set
710# CONFIG_WLAN_80211 is not set 720# CONFIG_WLAN_80211 is not set
721# CONFIG_IWLWIFI_LEDS is not set
711 722
712# 723#
713# USB Network Adapters 724# USB Network Adapters
@@ -738,12 +749,9 @@ CONFIG_INPUT=y
738# 749#
739# Userland interfaces 750# Userland interfaces
740# 751#
741CONFIG_INPUT_MOUSEDEV=y 752# CONFIG_INPUT_MOUSEDEV is not set
742CONFIG_INPUT_MOUSEDEV_PSAUX=y
743CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
744CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
745# CONFIG_INPUT_JOYDEV is not set 753# CONFIG_INPUT_JOYDEV is not set
746# CONFIG_INPUT_EVDEV is not set 754CONFIG_INPUT_EVDEV=y
747# CONFIG_INPUT_EVBUG is not set 755# CONFIG_INPUT_EVBUG is not set
748 756
749# 757#
@@ -765,10 +773,8 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
765# 773#
766# Character devices 774# Character devices
767# 775#
768CONFIG_VT=y 776# CONFIG_VT is not set
769CONFIG_VT_CONSOLE=y 777CONFIG_DEVKMEM=y
770CONFIG_HW_CONSOLE=y
771# CONFIG_VT_HW_CONSOLE_BINDING is not set
772# CONFIG_SERIAL_NONSTANDARD is not set 778# CONFIG_SERIAL_NONSTANDARD is not set
773# CONFIG_NOZOMI is not set 779# CONFIG_NOZOMI is not set
774 780
@@ -777,7 +783,7 @@ CONFIG_HW_CONSOLE=y
777# 783#
778CONFIG_SERIAL_8250=y 784CONFIG_SERIAL_8250=y
779CONFIG_SERIAL_8250_CONSOLE=y 785CONFIG_SERIAL_8250_CONSOLE=y
780CONFIG_SERIAL_8250_PCI=y 786# CONFIG_SERIAL_8250_PCI is not set
781CONFIG_SERIAL_8250_NR_UARTS=4 787CONFIG_SERIAL_8250_NR_UARTS=4
782CONFIG_SERIAL_8250_RUNTIME_UARTS=2 788CONFIG_SERIAL_8250_RUNTIME_UARTS=2
783# CONFIG_SERIAL_8250_EXTENDED is not set 789# CONFIG_SERIAL_8250_EXTENDED is not set
@@ -792,7 +798,7 @@ CONFIG_UNIX98_PTYS=y
792CONFIG_LEGACY_PTYS=y 798CONFIG_LEGACY_PTYS=y
793CONFIG_LEGACY_PTY_COUNT=16 799CONFIG_LEGACY_PTY_COUNT=16
794# CONFIG_IPMI_HANDLER is not set 800# CONFIG_IPMI_HANDLER is not set
795CONFIG_HW_RANDOM=m 801# CONFIG_HW_RANDOM is not set
796# CONFIG_NVRAM is not set 802# CONFIG_NVRAM is not set
797# CONFIG_R3964 is not set 803# CONFIG_R3964 is not set
798# CONFIG_APPLICOM is not set 804# CONFIG_APPLICOM is not set
@@ -804,13 +810,6 @@ CONFIG_I2C_BOARDINFO=y
804CONFIG_I2C_CHARDEV=y 810CONFIG_I2C_CHARDEV=y
805 811
806# 812#
807# I2C Algorithms
808#
809# CONFIG_I2C_ALGOBIT is not set
810# CONFIG_I2C_ALGOPCF is not set
811# CONFIG_I2C_ALGOPCA is not set
812
813#
814# I2C Hardware Bus support 813# I2C Hardware Bus support
815# 814#
816# CONFIG_I2C_ALI1535 is not set 815# CONFIG_I2C_ALI1535 is not set
@@ -837,6 +836,7 @@ CONFIG_I2C_CHARDEV=y
837# CONFIG_I2C_VIA is not set 836# CONFIG_I2C_VIA is not set
838# CONFIG_I2C_VIAPRO is not set 837# CONFIG_I2C_VIAPRO is not set
839# CONFIG_I2C_VOODOO3 is not set 838# CONFIG_I2C_VOODOO3 is not set
839# CONFIG_I2C_PCA_PLATFORM is not set
840CONFIG_I2C_MV64XXX=y 840CONFIG_I2C_MV64XXX=y
841 841
842# 842#
@@ -847,19 +847,13 @@ CONFIG_I2C_MV64XXX=y
847# CONFIG_SENSORS_PCF8574 is not set 847# CONFIG_SENSORS_PCF8574 is not set
848# CONFIG_PCF8575 is not set 848# CONFIG_PCF8575 is not set
849# CONFIG_SENSORS_PCF8591 is not set 849# CONFIG_SENSORS_PCF8591 is not set
850# CONFIG_TPS65010 is not set
851# CONFIG_SENSORS_MAX6875 is not set 850# CONFIG_SENSORS_MAX6875 is not set
852# CONFIG_SENSORS_TSL2550 is not set 851# CONFIG_SENSORS_TSL2550 is not set
853# CONFIG_I2C_DEBUG_CORE is not set 852# CONFIG_I2C_DEBUG_CORE is not set
854# CONFIG_I2C_DEBUG_ALGO is not set 853# CONFIG_I2C_DEBUG_ALGO is not set
855# CONFIG_I2C_DEBUG_BUS is not set 854# CONFIG_I2C_DEBUG_BUS is not set
856# CONFIG_I2C_DEBUG_CHIP is not set 855# CONFIG_I2C_DEBUG_CHIP is not set
857
858#
859# SPI support
860#
861# CONFIG_SPI is not set 856# CONFIG_SPI is not set
862# CONFIG_SPI_MASTER is not set
863# CONFIG_W1 is not set 857# CONFIG_W1 is not set
864# CONFIG_POWER_SUPPLY is not set 858# CONFIG_POWER_SUPPLY is not set
865CONFIG_HWMON=y 859CONFIG_HWMON=y
@@ -872,6 +866,7 @@ CONFIG_HWMON=y
872# CONFIG_SENSORS_ADM1031 is not set 866# CONFIG_SENSORS_ADM1031 is not set
873# CONFIG_SENSORS_ADM9240 is not set 867# CONFIG_SENSORS_ADM9240 is not set
874# CONFIG_SENSORS_ADT7470 is not set 868# CONFIG_SENSORS_ADT7470 is not set
869# CONFIG_SENSORS_ADT7473 is not set
875# CONFIG_SENSORS_ATXP1 is not set 870# CONFIG_SENSORS_ATXP1 is not set
876# CONFIG_SENSORS_DS1621 is not set 871# CONFIG_SENSORS_DS1621 is not set
877# CONFIG_SENSORS_I5K_AMB is not set 872# CONFIG_SENSORS_I5K_AMB is not set
@@ -901,6 +896,7 @@ CONFIG_HWMON=y
901# CONFIG_SENSORS_SMSC47M1 is not set 896# CONFIG_SENSORS_SMSC47M1 is not set
902# CONFIG_SENSORS_SMSC47M192 is not set 897# CONFIG_SENSORS_SMSC47M192 is not set
903# CONFIG_SENSORS_SMSC47B397 is not set 898# CONFIG_SENSORS_SMSC47B397 is not set
899# CONFIG_SENSORS_ADS7828 is not set
904# CONFIG_SENSORS_THMC50 is not set 900# CONFIG_SENSORS_THMC50 is not set
905# CONFIG_SENSORS_VIA686A is not set 901# CONFIG_SENSORS_VIA686A is not set
906# CONFIG_SENSORS_VT1211 is not set 902# CONFIG_SENSORS_VT1211 is not set
@@ -910,6 +906,7 @@ CONFIG_HWMON=y
910# CONFIG_SENSORS_W83792D is not set 906# CONFIG_SENSORS_W83792D is not set
911# CONFIG_SENSORS_W83793 is not set 907# CONFIG_SENSORS_W83793 is not set
912# CONFIG_SENSORS_W83L785TS is not set 908# CONFIG_SENSORS_W83L785TS is not set
909# CONFIG_SENSORS_W83L786NG is not set
913# CONFIG_SENSORS_W83627HF is not set 910# CONFIG_SENSORS_W83627HF is not set
914# CONFIG_SENSORS_W83627EHF is not set 911# CONFIG_SENSORS_W83627EHF is not set
915# CONFIG_HWMON_DEBUG_CHIP is not set 912# CONFIG_HWMON_DEBUG_CHIP is not set
@@ -925,14 +922,24 @@ CONFIG_SSB_POSSIBLE=y
925# Multifunction device drivers 922# Multifunction device drivers
926# 923#
927# CONFIG_MFD_SM501 is not set 924# CONFIG_MFD_SM501 is not set
925# CONFIG_MFD_ASIC3 is not set
926# CONFIG_HTC_PASIC3 is not set
928 927
929# 928#
930# Multimedia devices 929# Multimedia devices
931# 930#
931
932#
933# Multimedia core support
934#
932# CONFIG_VIDEO_DEV is not set 935# CONFIG_VIDEO_DEV is not set
933# CONFIG_DVB_CORE is not set 936# CONFIG_DVB_CORE is not set
934CONFIG_DAB=y 937# CONFIG_VIDEO_MEDIA is not set
935# CONFIG_USB_DABUSB is not set 938
939#
940# Multimedia drivers
941#
942# CONFIG_DAB is not set
936 943
937# 944#
938# Graphics support 945# Graphics support
@@ -949,12 +956,6 @@ CONFIG_DAB=y
949# CONFIG_DISPLAY_SUPPORT is not set 956# CONFIG_DISPLAY_SUPPORT is not set
950 957
951# 958#
952# Console display driver support
953#
954# CONFIG_VGA_CONSOLE is not set
955CONFIG_DUMMY_CONSOLE=y
956
957#
958# Sound 959# Sound
959# 960#
960# CONFIG_SOUND is not set 961# CONFIG_SOUND is not set
@@ -985,14 +986,18 @@ CONFIG_USB_DEVICEFS=y
985CONFIG_USB_DEVICE_CLASS=y 986CONFIG_USB_DEVICE_CLASS=y
986# CONFIG_USB_DYNAMIC_MINORS is not set 987# CONFIG_USB_DYNAMIC_MINORS is not set
987# CONFIG_USB_OTG is not set 988# CONFIG_USB_OTG is not set
989# CONFIG_USB_OTG_WHITELIST is not set
990# CONFIG_USB_OTG_BLACKLIST_HUB is not set
988 991
989# 992#
990# USB Host Controller Drivers 993# USB Host Controller Drivers
991# 994#
995# CONFIG_USB_C67X00_HCD is not set
992CONFIG_USB_EHCI_HCD=y 996CONFIG_USB_EHCI_HCD=y
993CONFIG_USB_EHCI_ROOT_HUB_TT=y 997CONFIG_USB_EHCI_ROOT_HUB_TT=y
994CONFIG_USB_EHCI_TT_NEWSCHED=y 998CONFIG_USB_EHCI_TT_NEWSCHED=y
995# CONFIG_USB_ISP116X_HCD is not set 999# CONFIG_USB_ISP116X_HCD is not set
1000# CONFIG_USB_ISP1760_HCD is not set
996# CONFIG_USB_OHCI_HCD is not set 1001# CONFIG_USB_OHCI_HCD is not set
997# CONFIG_USB_UHCI_HCD is not set 1002# CONFIG_USB_UHCI_HCD is not set
998# CONFIG_USB_SL811_HCD is not set 1003# CONFIG_USB_SL811_HCD is not set
@@ -1003,6 +1008,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
1003# 1008#
1004# CONFIG_USB_ACM is not set 1009# CONFIG_USB_ACM is not set
1005CONFIG_USB_PRINTER=y 1010CONFIG_USB_PRINTER=y
1011# CONFIG_USB_WDM is not set
1006 1012
1007# 1013#
1008# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1014# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1022,7 +1028,9 @@ CONFIG_USB_STORAGE_SDDR09=y
1022CONFIG_USB_STORAGE_SDDR55=y 1028CONFIG_USB_STORAGE_SDDR55=y
1023CONFIG_USB_STORAGE_JUMPSHOT=y 1029CONFIG_USB_STORAGE_JUMPSHOT=y
1024# CONFIG_USB_STORAGE_ALAUDA is not set 1030# CONFIG_USB_STORAGE_ALAUDA is not set
1031# CONFIG_USB_STORAGE_ONETOUCH is not set
1025# CONFIG_USB_STORAGE_KARMA is not set 1032# CONFIG_USB_STORAGE_KARMA is not set
1033# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1026# CONFIG_USB_LIBUSUAL is not set 1034# CONFIG_USB_LIBUSUAL is not set
1027 1035
1028# 1036#
@@ -1060,6 +1068,7 @@ CONFIG_USB_STORAGE_JUMPSHOT=y
1060# CONFIG_USB_TRANCEVIBRATOR is not set 1068# CONFIG_USB_TRANCEVIBRATOR is not set
1061# CONFIG_USB_IOWARRIOR is not set 1069# CONFIG_USB_IOWARRIOR is not set
1062# CONFIG_USB_TEST is not set 1070# CONFIG_USB_TEST is not set
1071# CONFIG_USB_ISIGHTFW is not set
1063# CONFIG_USB_GADGET is not set 1072# CONFIG_USB_GADGET is not set
1064# CONFIG_MMC is not set 1073# CONFIG_MMC is not set
1065CONFIG_NEW_LEDS=y 1074CONFIG_NEW_LEDS=y
@@ -1068,7 +1077,7 @@ CONFIG_LEDS_CLASS=y
1068# 1077#
1069# LED drivers 1078# LED drivers
1070# 1079#
1071# CONFIG_LEDS_GPIO is not set 1080CONFIG_LEDS_GPIO=y
1072 1081
1073# 1082#
1074# LED Triggers 1083# LED Triggers
@@ -1076,6 +1085,7 @@ CONFIG_LEDS_CLASS=y
1076CONFIG_LEDS_TRIGGERS=y 1085CONFIG_LEDS_TRIGGERS=y
1077CONFIG_LEDS_TRIGGER_TIMER=y 1086CONFIG_LEDS_TRIGGER_TIMER=y
1078CONFIG_LEDS_TRIGGER_HEARTBEAT=y 1087CONFIG_LEDS_TRIGGER_HEARTBEAT=y
1088CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
1079CONFIG_RTC_LIB=y 1089CONFIG_RTC_LIB=y
1080CONFIG_RTC_CLASS=y 1090CONFIG_RTC_CLASS=y
1081CONFIG_RTC_HCTOSYS=y 1091CONFIG_RTC_HCTOSYS=y
@@ -1105,6 +1115,7 @@ CONFIG_RTC_DRV_RS5C372=y
1105# CONFIG_RTC_DRV_PCF8583 is not set 1115# CONFIG_RTC_DRV_PCF8583 is not set
1106CONFIG_RTC_DRV_M41T80=y 1116CONFIG_RTC_DRV_M41T80=y
1107# CONFIG_RTC_DRV_M41T80_WDT is not set 1117# CONFIG_RTC_DRV_M41T80_WDT is not set
1118# CONFIG_RTC_DRV_S35390A is not set
1108 1119
1109# 1120#
1110# SPI RTC drivers 1121# SPI RTC drivers
@@ -1125,6 +1136,7 @@ CONFIG_RTC_DRV_M41T80=y
1125# 1136#
1126# on-CPU RTC drivers 1137# on-CPU RTC drivers
1127# 1138#
1139# CONFIG_UIO is not set
1128 1140
1129# 1141#
1130# File systems 1142# File systems
@@ -1140,14 +1152,11 @@ CONFIG_JBD=y
1140# CONFIG_JFS_FS is not set 1152# CONFIG_JFS_FS is not set
1141# CONFIG_FS_POSIX_ACL is not set 1153# CONFIG_FS_POSIX_ACL is not set
1142# CONFIG_XFS_FS is not set 1154# CONFIG_XFS_FS is not set
1143# CONFIG_GFS2_FS is not set
1144# CONFIG_OCFS2_FS is not set 1155# CONFIG_OCFS2_FS is not set
1145# CONFIG_MINIX_FS is not set 1156CONFIG_DNOTIFY=y
1146# CONFIG_ROMFS_FS is not set
1147CONFIG_INOTIFY=y 1157CONFIG_INOTIFY=y
1148CONFIG_INOTIFY_USER=y 1158CONFIG_INOTIFY_USER=y
1149# CONFIG_QUOTA is not set 1159# CONFIG_QUOTA is not set
1150CONFIG_DNOTIFY=y
1151# CONFIG_AUTOFS_FS is not set 1160# CONFIG_AUTOFS_FS is not set
1152# CONFIG_AUTOFS4_FS is not set 1161# CONFIG_AUTOFS4_FS is not set
1153# CONFIG_FUSE_FS is not set 1162# CONFIG_FUSE_FS is not set
@@ -1155,8 +1164,8 @@ CONFIG_DNOTIFY=y
1155# 1164#
1156# CD-ROM/DVD Filesystems 1165# CD-ROM/DVD Filesystems
1157# 1166#
1158CONFIG_ISO9660_FS=y 1167CONFIG_ISO9660_FS=m
1159# CONFIG_JOLIET is not set 1168CONFIG_JOLIET=y
1160# CONFIG_ZISOFS is not set 1169# CONFIG_ZISOFS is not set
1161CONFIG_UDF_FS=m 1170CONFIG_UDF_FS=m
1162CONFIG_UDF_NLS=y 1171CONFIG_UDF_NLS=y
@@ -1205,8 +1214,10 @@ CONFIG_JFFS2_RTIME=y
1205# CONFIG_JFFS2_RUBIN is not set 1214# CONFIG_JFFS2_RUBIN is not set
1206CONFIG_CRAMFS=y 1215CONFIG_CRAMFS=y
1207# CONFIG_VXFS_FS is not set 1216# CONFIG_VXFS_FS is not set
1217# CONFIG_MINIX_FS is not set
1208# CONFIG_HPFS_FS is not set 1218# CONFIG_HPFS_FS is not set
1209# CONFIG_QNX4FS_FS is not set 1219# CONFIG_QNX4FS_FS is not set
1220# CONFIG_ROMFS_FS is not set
1210# CONFIG_SYSV_FS is not set 1221# CONFIG_SYSV_FS is not set
1211# CONFIG_UFS_FS is not set 1222# CONFIG_UFS_FS is not set
1212CONFIG_NETWORK_FILESYSTEMS=y 1223CONFIG_NETWORK_FILESYSTEMS=y
@@ -1214,7 +1225,6 @@ CONFIG_NFS_FS=y
1214CONFIG_NFS_V3=y 1225CONFIG_NFS_V3=y
1215# CONFIG_NFS_V3_ACL is not set 1226# CONFIG_NFS_V3_ACL is not set
1216# CONFIG_NFS_V4 is not set 1227# CONFIG_NFS_V4 is not set
1217# CONFIG_NFS_DIRECTIO is not set
1218# CONFIG_NFSD is not set 1228# CONFIG_NFSD is not set
1219CONFIG_ROOT_NFS=y 1229CONFIG_ROOT_NFS=y
1220CONFIG_LOCKD=y 1230CONFIG_LOCKD=y
@@ -1241,14 +1251,13 @@ CONFIG_PARTITION_ADVANCED=y
1241# CONFIG_MAC_PARTITION is not set 1251# CONFIG_MAC_PARTITION is not set
1242CONFIG_MSDOS_PARTITION=y 1252CONFIG_MSDOS_PARTITION=y
1243CONFIG_BSD_DISKLABEL=y 1253CONFIG_BSD_DISKLABEL=y
1244CONFIG_MINIX_SUBPARTITION=y 1254# CONFIG_MINIX_SUBPARTITION is not set
1245CONFIG_SOLARIS_X86_PARTITION=y 1255# CONFIG_SOLARIS_X86_PARTITION is not set
1246CONFIG_UNIXWARE_DISKLABEL=y 1256# CONFIG_UNIXWARE_DISKLABEL is not set
1247CONFIG_LDM_PARTITION=y 1257# CONFIG_LDM_PARTITION is not set
1248CONFIG_LDM_DEBUG=y
1249# CONFIG_SGI_PARTITION is not set 1258# CONFIG_SGI_PARTITION is not set
1250# CONFIG_ULTRIX_PARTITION is not set 1259# CONFIG_ULTRIX_PARTITION is not set
1251CONFIG_SUN_PARTITION=y 1260# CONFIG_SUN_PARTITION is not set
1252# CONFIG_KARMA_PARTITION is not set 1261# CONFIG_KARMA_PARTITION is not set
1253# CONFIG_EFI_PARTITION is not set 1262# CONFIG_EFI_PARTITION is not set
1254# CONFIG_SYSV68_PARTITION is not set 1263# CONFIG_SYSV68_PARTITION is not set
@@ -1300,15 +1309,48 @@ CONFIG_NLS_ISO8859_2=y
1300# CONFIG_PRINTK_TIME is not set 1309# CONFIG_PRINTK_TIME is not set
1301CONFIG_ENABLE_WARN_DEPRECATED=y 1310CONFIG_ENABLE_WARN_DEPRECATED=y
1302CONFIG_ENABLE_MUST_CHECK=y 1311CONFIG_ENABLE_MUST_CHECK=y
1303# CONFIG_MAGIC_SYSRQ is not set 1312CONFIG_FRAME_WARN=1024
1313CONFIG_MAGIC_SYSRQ=y
1304# CONFIG_UNUSED_SYMBOLS is not set 1314# CONFIG_UNUSED_SYMBOLS is not set
1305# CONFIG_DEBUG_FS is not set 1315# CONFIG_DEBUG_FS is not set
1306# CONFIG_HEADERS_CHECK is not set 1316# CONFIG_HEADERS_CHECK is not set
1307# CONFIG_DEBUG_KERNEL is not set 1317CONFIG_DEBUG_KERNEL=y
1318# CONFIG_DEBUG_SHIRQ is not set
1319CONFIG_DETECT_SOFTLOCKUP=y
1320CONFIG_SCHED_DEBUG=y
1321CONFIG_SCHEDSTATS=y
1322# CONFIG_TIMER_STATS is not set
1323# CONFIG_DEBUG_OBJECTS is not set
1324CONFIG_DEBUG_PREEMPT=y
1325# CONFIG_DEBUG_RT_MUTEXES is not set
1326# CONFIG_RT_MUTEX_TESTER is not set
1327# CONFIG_DEBUG_SPINLOCK is not set
1328# CONFIG_DEBUG_MUTEXES is not set
1329# CONFIG_DEBUG_LOCK_ALLOC is not set
1330# CONFIG_PROVE_LOCKING is not set
1331# CONFIG_LOCK_STAT is not set
1332# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1333# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1334# CONFIG_DEBUG_KOBJECT is not set
1308# CONFIG_DEBUG_BUGVERBOSE is not set 1335# CONFIG_DEBUG_BUGVERBOSE is not set
1336CONFIG_DEBUG_INFO=y
1337# CONFIG_DEBUG_VM is not set
1338# CONFIG_DEBUG_WRITECOUNT is not set
1339# CONFIG_DEBUG_LIST is not set
1340# CONFIG_DEBUG_SG is not set
1309CONFIG_FRAME_POINTER=y 1341CONFIG_FRAME_POINTER=y
1342# CONFIG_BOOT_PRINTK_DELAY is not set
1343# CONFIG_RCU_TORTURE_TEST is not set
1344# CONFIG_KPROBES_SANITY_TEST is not set
1345# CONFIG_BACKTRACE_SELF_TEST is not set
1346# CONFIG_LKDTM is not set
1347# CONFIG_FAULT_INJECTION is not set
1310# CONFIG_SAMPLES is not set 1348# CONFIG_SAMPLES is not set
1311CONFIG_DEBUG_USER=y 1349CONFIG_DEBUG_USER=y
1350CONFIG_DEBUG_ERRORS=y
1351# CONFIG_DEBUG_STACK_USAGE is not set
1352CONFIG_DEBUG_LL=y
1353# CONFIG_DEBUG_ICEDCC is not set
1312 1354
1313# 1355#
1314# Security options 1356# Security options
@@ -1317,50 +1359,79 @@ CONFIG_DEBUG_USER=y
1317# CONFIG_SECURITY is not set 1359# CONFIG_SECURITY is not set
1318# CONFIG_SECURITY_FILE_CAPABILITIES is not set 1360# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1319CONFIG_CRYPTO=y 1361CONFIG_CRYPTO=y
1362
1363#
1364# Crypto core or helper
1365#
1320CONFIG_CRYPTO_ALGAPI=m 1366CONFIG_CRYPTO_ALGAPI=m
1321CONFIG_CRYPTO_BLKCIPHER=m 1367CONFIG_CRYPTO_BLKCIPHER=m
1322# CONFIG_CRYPTO_SEQIV is not set
1323CONFIG_CRYPTO_MANAGER=m 1368CONFIG_CRYPTO_MANAGER=m
1369# CONFIG_CRYPTO_GF128MUL is not set
1370# CONFIG_CRYPTO_NULL is not set
1371# CONFIG_CRYPTO_CRYPTD is not set
1372# CONFIG_CRYPTO_AUTHENC is not set
1373# CONFIG_CRYPTO_TEST is not set
1374
1375#
1376# Authenticated Encryption with Associated Data
1377#
1378# CONFIG_CRYPTO_CCM is not set
1379# CONFIG_CRYPTO_GCM is not set
1380# CONFIG_CRYPTO_SEQIV is not set
1381
1382#
1383# Block modes
1384#
1385CONFIG_CRYPTO_CBC=m
1386# CONFIG_CRYPTO_CTR is not set
1387# CONFIG_CRYPTO_CTS is not set
1388CONFIG_CRYPTO_ECB=m
1389# CONFIG_CRYPTO_LRW is not set
1390CONFIG_CRYPTO_PCBC=m
1391# CONFIG_CRYPTO_XTS is not set
1392
1393#
1394# Hash modes
1395#
1324# CONFIG_CRYPTO_HMAC is not set 1396# CONFIG_CRYPTO_HMAC is not set
1325# CONFIG_CRYPTO_XCBC is not set 1397# CONFIG_CRYPTO_XCBC is not set
1326# CONFIG_CRYPTO_NULL is not set 1398
1399#
1400# Digest
1401#
1402# CONFIG_CRYPTO_CRC32C is not set
1327# CONFIG_CRYPTO_MD4 is not set 1403# CONFIG_CRYPTO_MD4 is not set
1328# CONFIG_CRYPTO_MD5 is not set 1404# CONFIG_CRYPTO_MD5 is not set
1405# CONFIG_CRYPTO_MICHAEL_MIC is not set
1329# CONFIG_CRYPTO_SHA1 is not set 1406# CONFIG_CRYPTO_SHA1 is not set
1330# CONFIG_CRYPTO_SHA256 is not set 1407# CONFIG_CRYPTO_SHA256 is not set
1331# CONFIG_CRYPTO_SHA512 is not set 1408# CONFIG_CRYPTO_SHA512 is not set
1332# CONFIG_CRYPTO_WP512 is not set
1333# CONFIG_CRYPTO_TGR192 is not set 1409# CONFIG_CRYPTO_TGR192 is not set
1334# CONFIG_CRYPTO_GF128MUL is not set 1410# CONFIG_CRYPTO_WP512 is not set
1335CONFIG_CRYPTO_ECB=m 1411
1336CONFIG_CRYPTO_CBC=m 1412#
1337CONFIG_CRYPTO_PCBC=m 1413# Ciphers
1338# CONFIG_CRYPTO_LRW is not set 1414#
1339# CONFIG_CRYPTO_XTS is not set
1340# CONFIG_CRYPTO_CTR is not set
1341# CONFIG_CRYPTO_GCM is not set
1342# CONFIG_CRYPTO_CCM is not set
1343# CONFIG_CRYPTO_CRYPTD is not set
1344# CONFIG_CRYPTO_DES is not set
1345# CONFIG_CRYPTO_FCRYPT is not set
1346# CONFIG_CRYPTO_BLOWFISH is not set
1347# CONFIG_CRYPTO_TWOFISH is not set
1348# CONFIG_CRYPTO_SERPENT is not set
1349# CONFIG_CRYPTO_AES is not set 1415# CONFIG_CRYPTO_AES is not set
1416# CONFIG_CRYPTO_ANUBIS is not set
1417# CONFIG_CRYPTO_ARC4 is not set
1418# CONFIG_CRYPTO_BLOWFISH is not set
1419# CONFIG_CRYPTO_CAMELLIA is not set
1350# CONFIG_CRYPTO_CAST5 is not set 1420# CONFIG_CRYPTO_CAST5 is not set
1351# CONFIG_CRYPTO_CAST6 is not set 1421# CONFIG_CRYPTO_CAST6 is not set
1352# CONFIG_CRYPTO_TEA is not set 1422# CONFIG_CRYPTO_DES is not set
1353# CONFIG_CRYPTO_ARC4 is not set 1423# CONFIG_CRYPTO_FCRYPT is not set
1354# CONFIG_CRYPTO_KHAZAD is not set 1424# CONFIG_CRYPTO_KHAZAD is not set
1355# CONFIG_CRYPTO_ANUBIS is not set
1356# CONFIG_CRYPTO_SEED is not set
1357# CONFIG_CRYPTO_SALSA20 is not set 1425# CONFIG_CRYPTO_SALSA20 is not set
1426# CONFIG_CRYPTO_SEED is not set
1427# CONFIG_CRYPTO_SERPENT is not set
1428# CONFIG_CRYPTO_TEA is not set
1429# CONFIG_CRYPTO_TWOFISH is not set
1430
1431#
1432# Compression
1433#
1358# CONFIG_CRYPTO_DEFLATE is not set 1434# CONFIG_CRYPTO_DEFLATE is not set
1359# CONFIG_CRYPTO_MICHAEL_MIC is not set
1360# CONFIG_CRYPTO_CRC32C is not set
1361# CONFIG_CRYPTO_CAMELLIA is not set
1362# CONFIG_CRYPTO_TEST is not set
1363# CONFIG_CRYPTO_AUTHENC is not set
1364# CONFIG_CRYPTO_LZO is not set 1435# CONFIG_CRYPTO_LZO is not set
1365CONFIG_CRYPTO_HW=y 1436CONFIG_CRYPTO_HW=y
1366# CONFIG_CRYPTO_DEV_HIFN_795X is not set 1437# CONFIG_CRYPTO_DEV_HIFN_795X is not set
@@ -1369,12 +1440,14 @@ CONFIG_CRYPTO_HW=y
1369# Library routines 1440# Library routines
1370# 1441#
1371CONFIG_BITREVERSE=y 1442CONFIG_BITREVERSE=y
1372CONFIG_CRC_CCITT=y 1443# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1373CONFIG_CRC16=y 1444# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1374# CONFIG_CRC_ITU_T is not set 1445# CONFIG_CRC_CCITT is not set
1446# CONFIG_CRC16 is not set
1447CONFIG_CRC_ITU_T=m
1375CONFIG_CRC32=y 1448CONFIG_CRC32=y
1376# CONFIG_CRC7 is not set 1449# CONFIG_CRC7 is not set
1377CONFIG_LIBCRC32C=y 1450# CONFIG_LIBCRC32C is not set
1378CONFIG_ZLIB_INFLATE=y 1451CONFIG_ZLIB_INFLATE=y
1379CONFIG_ZLIB_DEFLATE=y 1452CONFIG_ZLIB_DEFLATE=y
1380CONFIG_PLIST=y 1453CONFIG_PLIST=y
diff --git a/arch/arm/configs/picotux200_defconfig b/arch/arm/configs/picotux200_defconfig
index 95a22f512805..14826f0dabde 100644
--- a/arch/arm/configs/picotux200_defconfig
+++ b/arch/arm/configs/picotux200_defconfig
@@ -201,7 +201,6 @@ CONFIG_ARM_THUMB=y
201# Kernel Features 201# Kernel Features
202# 202#
203# CONFIG_PREEMPT is not set 203# CONFIG_PREEMPT is not set
204CONFIG_NO_IDLE_HZ=y
205CONFIG_HZ=100 204CONFIG_HZ=100
206CONFIG_AEABI=y 205CONFIG_AEABI=y
207CONFIG_OABI_COMPAT=y 206CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
index b5e11aa2e290..811b8f60d19d 100644
--- a/arch/arm/configs/pnx4008_defconfig
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_THUMB=y
151# Kernel Features 151# Kernel Features
152# 152#
153CONFIG_PREEMPT=y 153CONFIG_PREEMPT=y
154# CONFIG_NO_IDLE_HZ is not set
155CONFIG_HZ=100 154CONFIG_HZ=100
156# CONFIG_AEABI is not set 155# CONFIG_AEABI is not set
157# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 156# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/qil-a9260_defconfig b/arch/arm/configs/qil-a9260_defconfig
new file mode 100644
index 000000000000..ef903bed061e
--- /dev/null
+++ b/arch/arm/configs/qil-a9260_defconfig
@@ -0,0 +1,1256 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24
4# Tue Apr 15 12:28:38 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35# CONFIG_LOCALVERSION_AUTO is not set
36# CONFIG_SWAP is not set
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48CONFIG_FAIR_GROUP_SCHED=y
49CONFIG_FAIR_USER_SCHED=y
50# CONFIG_FAIR_CGROUP_SCHED is not set
51# CONFIG_SYSFS_DEPRECATED is not set
52# CONFIG_RELAY is not set
53# CONFIG_BLK_DEV_INITRD is not set
54# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
55CONFIG_SYSCTL=y
56# CONFIG_EMBEDDED is not set
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_KALLSYMS=y
60# CONFIG_KALLSYMS_ALL is not set
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_EVENTFD=y
72CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y
75# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set
77CONFIG_SLABINFO=y
78CONFIG_RT_MUTEXES=y
79# CONFIG_TINY_SHMEM is not set
80CONFIG_BASE_SMALL=0
81CONFIG_MODULES=y
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97CONFIG_IOSCHED_AS=y
98# CONFIG_IOSCHED_DEADLINE is not set
99# CONFIG_IOSCHED_CFQ is not set
100CONFIG_DEFAULT_AS=y
101# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set
103# CONFIG_DEFAULT_NOOP is not set
104CONFIG_DEFAULT_IOSCHED="anticipatory"
105
106#
107# System Type
108#
109# CONFIG_ARCH_AAEC2000 is not set
110# CONFIG_ARCH_INTEGRATOR is not set
111# CONFIG_ARCH_REALVIEW is not set
112# CONFIG_ARCH_VERSATILE is not set
113CONFIG_ARCH_AT91=y
114# CONFIG_ARCH_CLPS7500 is not set
115# CONFIG_ARCH_CLPS711X is not set
116# CONFIG_ARCH_CO285 is not set
117# CONFIG_ARCH_EBSA110 is not set
118# CONFIG_ARCH_EP93XX is not set
119# CONFIG_ARCH_FOOTBRIDGE is not set
120# CONFIG_ARCH_NETX is not set
121# CONFIG_ARCH_H720X is not set
122# CONFIG_ARCH_IMX is not set
123# CONFIG_ARCH_IOP13XX is not set
124# CONFIG_ARCH_IOP32X is not set
125# CONFIG_ARCH_IOP33X is not set
126# CONFIG_ARCH_IXP23XX is not set
127# CONFIG_ARCH_IXP2000 is not set
128# CONFIG_ARCH_IXP4XX is not set
129# CONFIG_ARCH_L7200 is not set
130# CONFIG_ARCH_KS8695 is not set
131# CONFIG_ARCH_NS9XXX is not set
132# CONFIG_ARCH_MXC is not set
133# CONFIG_ARCH_PNX4008 is not set
134# CONFIG_ARCH_PXA is not set
135# CONFIG_ARCH_RPC is not set
136# CONFIG_ARCH_SA1100 is not set
137# CONFIG_ARCH_S3C2410 is not set
138# CONFIG_ARCH_SHARK is not set
139# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set
141# CONFIG_ARCH_OMAP is not set
142
143#
144# Boot options
145#
146
147#
148# Power management
149#
150
151#
152# Atmel AT91 System-on-Chip
153#
154# CONFIG_ARCH_AT91RM9200 is not set
155CONFIG_ARCH_AT91SAM9260=y
156# CONFIG_ARCH_AT91SAM9261 is not set
157# CONFIG_ARCH_AT91SAM9263 is not set
158# CONFIG_ARCH_AT91SAM9RL is not set
159# CONFIG_ARCH_AT91CAP9 is not set
160# CONFIG_ARCH_AT91X40 is not set
161CONFIG_AT91_PMC_UNIT=y
162
163#
164# AT91SAM9260 Variants
165#
166# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
167
168#
169# AT91SAM9260 / AT91SAM9XE Board Type
170#
171# CONFIG_MACH_AT91SAM9260EK is not set
172# CONFIG_MACH_CAM60 is not set
173# CONFIG_MACH_SAM9_L9260 is not set
174# CONFIG_MACH_USB_A9260 is not set
175CONFIG_MACH_QIL_A9260=y
176
177#
178# AT91 Board Options
179#
180
181#
182# AT91 Feature Selections
183#
184# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
185CONFIG_AT91_SLOW_CLOCK=y
186CONFIG_AT91_TIMER_HZ=100
187# CONFIG_AT91_EARLY_DBGU is not set
188CONFIG_AT91_EARLY_USART0=y
189# CONFIG_AT91_EARLY_USART1 is not set
190# CONFIG_AT91_EARLY_USART2 is not set
191# CONFIG_AT91_EARLY_USART3 is not set
192# CONFIG_AT91_EARLY_USART4 is not set
193# CONFIG_AT91_EARLY_USART5 is not set
194
195#
196# Processor Type
197#
198CONFIG_CPU_32=y
199CONFIG_CPU_ARM926T=y
200CONFIG_CPU_32v5=y
201CONFIG_CPU_ABRT_EV5TJ=y
202CONFIG_CPU_CACHE_VIVT=y
203CONFIG_CPU_COPY_V4WB=y
204CONFIG_CPU_TLB_V4WBI=y
205CONFIG_CPU_CP15=y
206CONFIG_CPU_CP15_MMU=y
207
208#
209# Processor Features
210#
211# CONFIG_ARM_THUMB is not set
212# CONFIG_CPU_ICACHE_DISABLE is not set
213# CONFIG_CPU_DCACHE_DISABLE is not set
214# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
215# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
216# CONFIG_OUTER_CACHE is not set
217
218#
219# Bus support
220#
221# CONFIG_PCI_SYSCALL is not set
222# CONFIG_ARCH_SUPPORTS_MSI is not set
223# CONFIG_PCCARD is not set
224
225#
226# Kernel Features
227#
228# CONFIG_TICK_ONESHOT is not set
229# CONFIG_NO_HZ is not set
230# CONFIG_HIGH_RES_TIMERS is not set
231CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
232# CONFIG_PREEMPT is not set
233CONFIG_HZ=100
234CONFIG_AEABI=y
235CONFIG_OABI_COMPAT=y
236# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
237CONFIG_SELECT_MEMORY_MODEL=y
238CONFIG_FLATMEM_MANUAL=y
239# CONFIG_DISCONTIGMEM_MANUAL is not set
240# CONFIG_SPARSEMEM_MANUAL is not set
241CONFIG_FLATMEM=y
242CONFIG_FLAT_NODE_MEM_MAP=y
243# CONFIG_SPARSEMEM_STATIC is not set
244# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
245CONFIG_SPLIT_PTLOCK_CPUS=4096
246# CONFIG_RESOURCES_64BIT is not set
247CONFIG_ZONE_DMA_FLAG=1
248CONFIG_BOUNCE=y
249CONFIG_VIRT_TO_BUS=y
250# CONFIG_LEDS is not set
251CONFIG_ALIGNMENT_TRAP=y
252
253#
254# Boot options
255#
256CONFIG_ZBOOT_ROM_TEXT=0x0
257CONFIG_ZBOOT_ROM_BSS=0x0
258CONFIG_CMDLINE="mem=64M console=ttyS1,115200"
259# CONFIG_XIP_KERNEL is not set
260# CONFIG_KEXEC is not set
261
262#
263# Floating point emulation
264#
265
266#
267# At least one emulation must be selected
268#
269CONFIG_FPE_NWFPE=y
270# CONFIG_FPE_NWFPE_XP is not set
271# CONFIG_FPE_FASTFPE is not set
272# CONFIG_VFP is not set
273
274#
275# Userspace binary formats
276#
277CONFIG_BINFMT_ELF=y
278# CONFIG_BINFMT_AOUT is not set
279# CONFIG_BINFMT_MISC is not set
280
281#
282# Power management options
283#
284CONFIG_PM=y
285# CONFIG_PM_LEGACY is not set
286# CONFIG_PM_DEBUG is not set
287CONFIG_PM_SLEEP=y
288CONFIG_SUSPEND_UP_POSSIBLE=y
289CONFIG_SUSPEND=y
290# CONFIG_APM_EMULATION is not set
291
292#
293# Networking
294#
295CONFIG_NET=y
296
297#
298# Networking options
299#
300CONFIG_PACKET=y
301# CONFIG_PACKET_MMAP is not set
302CONFIG_UNIX=y
303# CONFIG_NET_KEY is not set
304CONFIG_INET=y
305CONFIG_IP_MULTICAST=y
306CONFIG_IP_ADVANCED_ROUTER=y
307CONFIG_ASK_IP_FIB_HASH=y
308# CONFIG_IP_FIB_TRIE is not set
309CONFIG_IP_FIB_HASH=y
310# CONFIG_IP_MULTIPLE_TABLES is not set
311# CONFIG_IP_ROUTE_MULTIPATH is not set
312CONFIG_IP_ROUTE_VERBOSE=y
313CONFIG_IP_PNP=y
314# CONFIG_IP_PNP_DHCP is not set
315CONFIG_IP_PNP_BOOTP=y
316CONFIG_IP_PNP_RARP=y
317# CONFIG_NET_IPIP is not set
318# CONFIG_NET_IPGRE is not set
319CONFIG_IP_MROUTE=y
320CONFIG_IP_PIMSM_V1=y
321CONFIG_IP_PIMSM_V2=y
322# CONFIG_ARPD is not set
323# CONFIG_SYN_COOKIES is not set
324# CONFIG_INET_AH is not set
325# CONFIG_INET_ESP is not set
326# CONFIG_INET_IPCOMP is not set
327# CONFIG_INET_XFRM_TUNNEL is not set
328# CONFIG_INET_TUNNEL is not set
329# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
330# CONFIG_INET_XFRM_MODE_TUNNEL is not set
331# CONFIG_INET_XFRM_MODE_BEET is not set
332# CONFIG_INET_LRO is not set
333# CONFIG_INET_DIAG is not set
334# CONFIG_TCP_CONG_ADVANCED is not set
335CONFIG_TCP_CONG_CUBIC=y
336CONFIG_DEFAULT_TCP_CONG="cubic"
337# CONFIG_TCP_MD5SIG is not set
338# CONFIG_IPV6 is not set
339# CONFIG_INET6_XFRM_TUNNEL is not set
340# CONFIG_INET6_TUNNEL is not set
341# CONFIG_NETWORK_SECMARK is not set
342# CONFIG_NETFILTER is not set
343# CONFIG_IP_DCCP is not set
344# CONFIG_IP_SCTP is not set
345# CONFIG_TIPC is not set
346# CONFIG_ATM is not set
347# CONFIG_BRIDGE is not set
348# CONFIG_VLAN_8021Q is not set
349# CONFIG_DECNET is not set
350# CONFIG_LLC2 is not set
351# CONFIG_IPX is not set
352# CONFIG_ATALK is not set
353# CONFIG_X25 is not set
354# CONFIG_LAPB is not set
355# CONFIG_ECONET is not set
356# CONFIG_WAN_ROUTER is not set
357# CONFIG_NET_SCHED is not set
358
359#
360# Network testing
361#
362# CONFIG_NET_PKTGEN is not set
363# CONFIG_HAMRADIO is not set
364# CONFIG_IRDA is not set
365# CONFIG_BT is not set
366# CONFIG_AF_RXRPC is not set
367
368#
369# Wireless
370#
371# CONFIG_CFG80211 is not set
372# CONFIG_WIRELESS_EXT is not set
373# CONFIG_MAC80211 is not set
374# CONFIG_IEEE80211 is not set
375# CONFIG_RFKILL is not set
376# CONFIG_NET_9P is not set
377
378#
379# Device Drivers
380#
381
382#
383# Generic Driver Options
384#
385CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
386CONFIG_STANDALONE=y
387CONFIG_PREVENT_FIRMWARE_BUILD=y
388# CONFIG_FW_LOADER is not set
389# CONFIG_DEBUG_DRIVER is not set
390# CONFIG_DEBUG_DEVRES is not set
391# CONFIG_SYS_HYPERVISOR is not set
392# CONFIG_CONNECTOR is not set
393CONFIG_MTD=y
394# CONFIG_MTD_DEBUG is not set
395# CONFIG_MTD_CONCAT is not set
396CONFIG_MTD_PARTITIONS=y
397# CONFIG_MTD_REDBOOT_PARTS is not set
398CONFIG_MTD_CMDLINE_PARTS=y
399# CONFIG_MTD_AFS_PARTS is not set
400
401#
402# User Modules And Translation Layers
403#
404CONFIG_MTD_CHAR=y
405CONFIG_MTD_BLKDEVS=y
406CONFIG_MTD_BLOCK=y
407# CONFIG_FTL is not set
408# CONFIG_NFTL is not set
409# CONFIG_INFTL is not set
410# CONFIG_RFD_FTL is not set
411# CONFIG_SSFDC is not set
412# CONFIG_MTD_OOPS is not set
413
414#
415# RAM/ROM/Flash chip drivers
416#
417# CONFIG_MTD_CFI is not set
418# CONFIG_MTD_JEDECPROBE is not set
419CONFIG_MTD_MAP_BANK_WIDTH_1=y
420CONFIG_MTD_MAP_BANK_WIDTH_2=y
421CONFIG_MTD_MAP_BANK_WIDTH_4=y
422# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
423# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
424# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
425CONFIG_MTD_CFI_I1=y
426CONFIG_MTD_CFI_I2=y
427# CONFIG_MTD_CFI_I4 is not set
428# CONFIG_MTD_CFI_I8 is not set
429# CONFIG_MTD_RAM is not set
430# CONFIG_MTD_ROM is not set
431# CONFIG_MTD_ABSENT is not set
432
433#
434# Mapping drivers for chip access
435#
436# CONFIG_MTD_COMPLEX_MAPPINGS is not set
437# CONFIG_MTD_PLATRAM is not set
438
439#
440# Self-contained MTD device drivers
441#
442CONFIG_MTD_DATAFLASH=y
443# CONFIG_MTD_M25P80 is not set
444# CONFIG_MTD_SLRAM is not set
445# CONFIG_MTD_PHRAM is not set
446# CONFIG_MTD_MTDRAM is not set
447# CONFIG_MTD_BLOCK2MTD is not set
448
449#
450# Disk-On-Chip Device Drivers
451#
452# CONFIG_MTD_DOC2000 is not set
453# CONFIG_MTD_DOC2001 is not set
454# CONFIG_MTD_DOC2001PLUS is not set
455CONFIG_MTD_NAND=y
456# CONFIG_MTD_NAND_VERIFY_WRITE is not set
457# CONFIG_MTD_NAND_ECC_SMC is not set
458# CONFIG_MTD_NAND_MUSEUM_IDS is not set
459CONFIG_MTD_NAND_IDS=y
460# CONFIG_MTD_NAND_DISKONCHIP is not set
461CONFIG_MTD_NAND_AT91=y
462CONFIG_MTD_NAND_AT91_ECC_SOFT=y
463# CONFIG_MTD_NAND_AT91_ECC_HW is not set
464# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
465# CONFIG_MTD_NAND_NANDSIM is not set
466# CONFIG_MTD_NAND_PLATFORM is not set
467# CONFIG_MTD_ALAUDA is not set
468# CONFIG_MTD_ONENAND is not set
469
470#
471# UBI - Unsorted block images
472#
473# CONFIG_MTD_UBI is not set
474# CONFIG_PARPORT is not set
475CONFIG_BLK_DEV=y
476# CONFIG_BLK_DEV_COW_COMMON is not set
477CONFIG_BLK_DEV_LOOP=y
478# CONFIG_BLK_DEV_CRYPTOLOOP is not set
479# CONFIG_BLK_DEV_NBD is not set
480# CONFIG_BLK_DEV_UB is not set
481# CONFIG_BLK_DEV_RAM is not set
482# CONFIG_CDROM_PKTCDVD is not set
483# CONFIG_ATA_OVER_ETH is not set
484# CONFIG_MISC_DEVICES is not set
485
486#
487# SCSI device support
488#
489# CONFIG_RAID_ATTRS is not set
490CONFIG_SCSI=y
491CONFIG_SCSI_DMA=y
492# CONFIG_SCSI_TGT is not set
493# CONFIG_SCSI_NETLINK is not set
494CONFIG_SCSI_PROC_FS=y
495
496#
497# SCSI support type (disk, tape, CD-ROM)
498#
499CONFIG_BLK_DEV_SD=y
500# CONFIG_CHR_DEV_ST is not set
501# CONFIG_CHR_DEV_OSST is not set
502# CONFIG_BLK_DEV_SR is not set
503# CONFIG_CHR_DEV_SG is not set
504# CONFIG_CHR_DEV_SCH is not set
505
506#
507# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
508#
509CONFIG_SCSI_MULTI_LUN=y
510# CONFIG_SCSI_CONSTANTS is not set
511# CONFIG_SCSI_LOGGING is not set
512# CONFIG_SCSI_SCAN_ASYNC is not set
513CONFIG_SCSI_WAIT_SCAN=m
514
515#
516# SCSI Transports
517#
518# CONFIG_SCSI_SPI_ATTRS is not set
519# CONFIG_SCSI_FC_ATTRS is not set
520# CONFIG_SCSI_ISCSI_ATTRS is not set
521# CONFIG_SCSI_SAS_LIBSAS is not set
522# CONFIG_SCSI_SRP_ATTRS is not set
523CONFIG_SCSI_LOWLEVEL=y
524# CONFIG_ISCSI_TCP is not set
525# CONFIG_SCSI_DEBUG is not set
526# CONFIG_ATA is not set
527# CONFIG_MD is not set
528CONFIG_NETDEVICES=y
529# CONFIG_NETDEVICES_MULTIQUEUE is not set
530# CONFIG_DUMMY is not set
531# CONFIG_BONDING is not set
532# CONFIG_MACVLAN is not set
533# CONFIG_EQUALIZER is not set
534# CONFIG_TUN is not set
535# CONFIG_VETH is not set
536CONFIG_PHYLIB=y
537
538#
539# MII PHY device drivers
540#
541# CONFIG_MARVELL_PHY is not set
542# CONFIG_DAVICOM_PHY is not set
543# CONFIG_QSEMI_PHY is not set
544# CONFIG_LXT_PHY is not set
545# CONFIG_CICADA_PHY is not set
546# CONFIG_VITESSE_PHY is not set
547# CONFIG_SMSC_PHY is not set
548# CONFIG_BROADCOM_PHY is not set
549# CONFIG_ICPLUS_PHY is not set
550# CONFIG_FIXED_PHY is not set
551# CONFIG_MDIO_BITBANG is not set
552CONFIG_NET_ETHERNET=y
553CONFIG_MII=y
554CONFIG_MACB=y
555# CONFIG_AX88796 is not set
556# CONFIG_SMC91X is not set
557# CONFIG_DM9000 is not set
558# CONFIG_IBM_NEW_EMAC_ZMII is not set
559# CONFIG_IBM_NEW_EMAC_RGMII is not set
560# CONFIG_IBM_NEW_EMAC_TAH is not set
561# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
562# CONFIG_B44 is not set
563CONFIG_NETDEV_1000=y
564CONFIG_NETDEV_10000=y
565
566#
567# Wireless LAN
568#
569# CONFIG_WLAN_PRE80211 is not set
570# CONFIG_WLAN_80211 is not set
571
572#
573# USB Network Adapters
574#
575# CONFIG_USB_CATC is not set
576# CONFIG_USB_KAWETH is not set
577# CONFIG_USB_PEGASUS is not set
578# CONFIG_USB_RTL8150 is not set
579# CONFIG_USB_USBNET is not set
580# CONFIG_WAN is not set
581# CONFIG_PPP is not set
582# CONFIG_SLIP is not set
583# CONFIG_SHAPER is not set
584# CONFIG_NETCONSOLE is not set
585# CONFIG_NETPOLL is not set
586# CONFIG_NET_POLL_CONTROLLER is not set
587# CONFIG_ISDN is not set
588
589#
590# Input device support
591#
592CONFIG_INPUT=y
593# CONFIG_INPUT_FF_MEMLESS is not set
594# CONFIG_INPUT_POLLDEV is not set
595
596#
597# Userland interfaces
598#
599CONFIG_INPUT_MOUSEDEV=y
600# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
601CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
602CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
603# CONFIG_INPUT_JOYDEV is not set
604CONFIG_INPUT_EVDEV=y
605CONFIG_INPUT_EVBUG=y
606
607#
608# Input Device Drivers
609#
610CONFIG_INPUT_KEYBOARD=y
611# CONFIG_KEYBOARD_ATKBD is not set
612# CONFIG_KEYBOARD_SUNKBD is not set
613# CONFIG_KEYBOARD_LKKBD is not set
614# CONFIG_KEYBOARD_XTKBD is not set
615# CONFIG_KEYBOARD_NEWTON is not set
616# CONFIG_KEYBOARD_STOWAWAY is not set
617CONFIG_KEYBOARD_GPIO=y
618# CONFIG_INPUT_MOUSE is not set
619# CONFIG_INPUT_JOYSTICK is not set
620# CONFIG_INPUT_TABLET is not set
621# CONFIG_INPUT_TOUCHSCREEN is not set
622# CONFIG_INPUT_MISC is not set
623
624#
625# Hardware I/O ports
626#
627# CONFIG_SERIO is not set
628# CONFIG_GAMEPORT is not set
629
630#
631# Character devices
632#
633CONFIG_VT=y
634CONFIG_VT_CONSOLE=y
635CONFIG_HW_CONSOLE=y
636# CONFIG_VT_HW_CONSOLE_BINDING is not set
637# CONFIG_SERIAL_NONSTANDARD is not set
638
639#
640# Serial drivers
641#
642# CONFIG_SERIAL_8250 is not set
643
644#
645# Non-8250 serial port support
646#
647CONFIG_SERIAL_ATMEL=y
648CONFIG_SERIAL_ATMEL_CONSOLE=y
649# CONFIG_SERIAL_ATMEL_TTYAT is not set
650CONFIG_SERIAL_CORE=y
651CONFIG_SERIAL_CORE_CONSOLE=y
652CONFIG_UNIX98_PTYS=y
653CONFIG_LEGACY_PTYS=y
654CONFIG_LEGACY_PTY_COUNT=256
655# CONFIG_IPMI_HANDLER is not set
656CONFIG_HW_RANDOM=y
657# CONFIG_NVRAM is not set
658# CONFIG_R3964 is not set
659# CONFIG_RAW_DRIVER is not set
660# CONFIG_TCG_TPM is not set
661CONFIG_I2C=y
662CONFIG_I2C_BOARDINFO=y
663CONFIG_I2C_CHARDEV=y
664
665#
666# I2C Algorithms
667#
668# CONFIG_I2C_ALGOBIT is not set
669# CONFIG_I2C_ALGOPCF is not set
670# CONFIG_I2C_ALGOPCA is not set
671
672#
673# I2C Hardware Bus support
674#
675# CONFIG_I2C_GPIO is not set
676# CONFIG_I2C_OCORES is not set
677# CONFIG_I2C_PARPORT_LIGHT is not set
678# CONFIG_I2C_SIMTEC is not set
679# CONFIG_I2C_TAOS_EVM is not set
680# CONFIG_I2C_STUB is not set
681# CONFIG_I2C_TINY_USB is not set
682# CONFIG_I2C_PCA is not set
683
684#
685# Miscellaneous I2C Chip support
686#
687# CONFIG_SENSORS_DS1337 is not set
688# CONFIG_SENSORS_DS1374 is not set
689# CONFIG_DS1682 is not set
690# CONFIG_SENSORS_EEPROM is not set
691# CONFIG_SENSORS_PCF8574 is not set
692# CONFIG_SENSORS_PCA9539 is not set
693# CONFIG_SENSORS_PCF8591 is not set
694# CONFIG_SENSORS_MAX6875 is not set
695# CONFIG_SENSORS_TSL2550 is not set
696# CONFIG_I2C_DEBUG_CORE is not set
697# CONFIG_I2C_DEBUG_ALGO is not set
698# CONFIG_I2C_DEBUG_BUS is not set
699# CONFIG_I2C_DEBUG_CHIP is not set
700
701#
702# SPI support
703#
704CONFIG_SPI=y
705# CONFIG_SPI_DEBUG is not set
706CONFIG_SPI_MASTER=y
707
708#
709# SPI Master Controller Drivers
710#
711CONFIG_SPI_ATMEL=y
712# CONFIG_SPI_BITBANG is not set
713
714#
715# SPI Protocol Masters
716#
717# CONFIG_SPI_AT25 is not set
718# CONFIG_SPI_SPIDEV is not set
719# CONFIG_SPI_TLE62X0 is not set
720# CONFIG_W1 is not set
721# CONFIG_POWER_SUPPLY is not set
722# CONFIG_HWMON is not set
723CONFIG_WATCHDOG=y
724CONFIG_WATCHDOG_NOWAYOUT=y
725
726#
727# Watchdog Device Drivers
728#
729# CONFIG_SOFT_WATCHDOG is not set
730# CONFIG_AT91SAM9_WATCHDOG is not set
731
732#
733# USB-based Watchdog Cards
734#
735# CONFIG_USBPCWATCHDOG is not set
736
737#
738# Sonics Silicon Backplane
739#
740CONFIG_SSB_POSSIBLE=y
741# CONFIG_SSB is not set
742
743#
744# Multifunction device drivers
745#
746# CONFIG_MFD_SM501 is not set
747
748#
749# Multimedia devices
750#
751# CONFIG_VIDEO_DEV is not set
752# CONFIG_DVB_CORE is not set
753# CONFIG_DAB is not set
754
755#
756# Graphics support
757#
758# CONFIG_VGASTATE is not set
759# CONFIG_VIDEO_OUTPUT_CONTROL is not set
760# CONFIG_FB is not set
761# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
762
763#
764# Display device support
765#
766# CONFIG_DISPLAY_SUPPORT is not set
767
768#
769# Console display driver support
770#
771# CONFIG_VGA_CONSOLE is not set
772CONFIG_DUMMY_CONSOLE=y
773
774#
775# Sound
776#
777# CONFIG_SOUND is not set
778CONFIG_HID_SUPPORT=y
779CONFIG_HID=y
780# CONFIG_HID_DEBUG is not set
781# CONFIG_HIDRAW is not set
782
783#
784# USB Input Devices
785#
786# CONFIG_USB_HID is not set
787
788#
789# USB HID Boot Protocol drivers
790#
791# CONFIG_USB_KBD is not set
792# CONFIG_USB_MOUSE is not set
793CONFIG_USB_SUPPORT=y
794CONFIG_USB_ARCH_HAS_HCD=y
795CONFIG_USB_ARCH_HAS_OHCI=y
796# CONFIG_USB_ARCH_HAS_EHCI is not set
797CONFIG_USB=y
798# CONFIG_USB_DEBUG is not set
799
800#
801# Miscellaneous USB options
802#
803CONFIG_USB_DEVICEFS=y
804CONFIG_USB_DEVICE_CLASS=y
805# CONFIG_USB_DYNAMIC_MINORS is not set
806# CONFIG_USB_SUSPEND is not set
807# CONFIG_USB_PERSIST is not set
808# CONFIG_USB_OTG is not set
809
810#
811# USB Host Controller Drivers
812#
813# CONFIG_USB_ISP116X_HCD is not set
814CONFIG_USB_OHCI_HCD=y
815# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
816# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
817CONFIG_USB_OHCI_LITTLE_ENDIAN=y
818# CONFIG_USB_SL811_HCD is not set
819# CONFIG_USB_R8A66597_HCD is not set
820
821#
822# USB Device Class drivers
823#
824# CONFIG_USB_ACM is not set
825# CONFIG_USB_PRINTER is not set
826
827#
828# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
829#
830
831#
832# may also be needed; see USB_STORAGE Help for more information
833#
834CONFIG_USB_STORAGE=y
835# CONFIG_USB_STORAGE_DEBUG is not set
836# CONFIG_USB_STORAGE_DATAFAB is not set
837# CONFIG_USB_STORAGE_FREECOM is not set
838# CONFIG_USB_STORAGE_ISD200 is not set
839# CONFIG_USB_STORAGE_DPCM is not set
840# CONFIG_USB_STORAGE_USBAT is not set
841# CONFIG_USB_STORAGE_SDDR09 is not set
842# CONFIG_USB_STORAGE_SDDR55 is not set
843# CONFIG_USB_STORAGE_JUMPSHOT is not set
844# CONFIG_USB_STORAGE_ALAUDA is not set
845# CONFIG_USB_STORAGE_KARMA is not set
846# CONFIG_USB_LIBUSUAL is not set
847
848#
849# USB Imaging devices
850#
851# CONFIG_USB_MDC800 is not set
852# CONFIG_USB_MICROTEK is not set
853CONFIG_USB_MON=y
854
855#
856# USB port drivers
857#
858
859#
860# USB Serial Converter support
861#
862# CONFIG_USB_SERIAL is not set
863
864#
865# USB Miscellaneous drivers
866#
867# CONFIG_USB_EMI62 is not set
868# CONFIG_USB_EMI26 is not set
869# CONFIG_USB_ADUTUX is not set
870# CONFIG_USB_AUERSWALD is not set
871# CONFIG_USB_RIO500 is not set
872# CONFIG_USB_LEGOTOWER is not set
873# CONFIG_USB_LCD is not set
874# CONFIG_USB_BERRY_CHARGE is not set
875# CONFIG_USB_LED is not set
876# CONFIG_USB_CYPRESS_CY7C63 is not set
877# CONFIG_USB_CYTHERM is not set
878# CONFIG_USB_PHIDGET is not set
879# CONFIG_USB_IDMOUSE is not set
880# CONFIG_USB_FTDI_ELAN is not set
881# CONFIG_USB_APPLEDISPLAY is not set
882# CONFIG_USB_LD is not set
883# CONFIG_USB_TRANCEVIBRATOR is not set
884# CONFIG_USB_IOWARRIOR is not set
885# CONFIG_USB_TEST is not set
886
887#
888# USB DSL modem support
889#
890
891#
892# USB Gadget Support
893#
894CONFIG_USB_GADGET=y
895# CONFIG_USB_GADGET_DEBUG is not set
896# CONFIG_USB_GADGET_DEBUG_FILES is not set
897CONFIG_USB_GADGET_SELECTED=y
898# CONFIG_USB_GADGET_AMD5536UDC is not set
899# CONFIG_USB_GADGET_ATMEL_USBA is not set
900# CONFIG_USB_GADGET_FSL_USB2 is not set
901# CONFIG_USB_GADGET_NET2280 is not set
902# CONFIG_USB_GADGET_PXA2XX is not set
903# CONFIG_USB_GADGET_M66592 is not set
904# CONFIG_USB_GADGET_GOKU is not set
905# CONFIG_USB_GADGET_LH7A40X is not set
906# CONFIG_USB_GADGET_OMAP is not set
907# CONFIG_USB_GADGET_S3C2410 is not set
908CONFIG_USB_GADGET_AT91=y
909CONFIG_USB_AT91=y
910# CONFIG_USB_GADGET_DUMMY_HCD is not set
911# CONFIG_USB_GADGET_DUALSPEED is not set
912# CONFIG_USB_ZERO is not set
913CONFIG_USB_ETH=y
914CONFIG_USB_ETH_RNDIS=y
915# CONFIG_USB_GADGETFS is not set
916# CONFIG_USB_FILE_STORAGE is not set
917# CONFIG_USB_G_SERIAL is not set
918# CONFIG_USB_MIDI_GADGET is not set
919CONFIG_MMC=y
920# CONFIG_MMC_DEBUG is not set
921# CONFIG_MMC_UNSAFE_RESUME is not set
922
923#
924# MMC/SD Card Drivers
925#
926CONFIG_MMC_BLOCK=y
927CONFIG_MMC_BLOCK_BOUNCE=y
928# CONFIG_SDIO_UART is not set
929
930#
931# MMC/SD Host Controller Drivers
932#
933CONFIG_MMC_AT91=y
934# CONFIG_MMC_SPI is not set
935CONFIG_NEW_LEDS=y
936CONFIG_LEDS_CLASS=y
937
938#
939# LED drivers
940#
941CONFIG_LEDS_GPIO=y
942
943#
944# LED Triggers
945#
946CONFIG_LEDS_TRIGGERS=y
947# CONFIG_LEDS_TRIGGER_TIMER is not set
948CONFIG_LEDS_TRIGGER_HEARTBEAT=y
949CONFIG_RTC_LIB=y
950CONFIG_RTC_CLASS=y
951CONFIG_RTC_HCTOSYS=y
952CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
953# CONFIG_RTC_DEBUG is not set
954
955#
956# RTC interfaces
957#
958CONFIG_RTC_INTF_SYSFS=y
959CONFIG_RTC_INTF_PROC=y
960CONFIG_RTC_INTF_DEV=y
961# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
962# CONFIG_RTC_DRV_TEST is not set
963
964#
965# I2C RTC drivers
966#
967# CONFIG_RTC_DRV_DS1307 is not set
968# CONFIG_RTC_DRV_DS1374 is not set
969# CONFIG_RTC_DRV_DS1672 is not set
970# CONFIG_RTC_DRV_MAX6900 is not set
971# CONFIG_RTC_DRV_RS5C372 is not set
972# CONFIG_RTC_DRV_ISL1208 is not set
973# CONFIG_RTC_DRV_X1205 is not set
974# CONFIG_RTC_DRV_PCF8563 is not set
975# CONFIG_RTC_DRV_PCF8583 is not set
976# CONFIG_RTC_DRV_M41T80 is not set
977
978#
979# SPI RTC drivers
980#
981# CONFIG_RTC_DRV_RS5C348 is not set
982# CONFIG_RTC_DRV_MAX6902 is not set
983CONFIG_RTC_DRV_M41T94=y
984
985#
986# Platform RTC drivers
987#
988# CONFIG_RTC_DRV_CMOS is not set
989# CONFIG_RTC_DRV_DS1553 is not set
990# CONFIG_RTC_DRV_STK17TA8 is not set
991# CONFIG_RTC_DRV_DS1742 is not set
992# CONFIG_RTC_DRV_M48T86 is not set
993# CONFIG_RTC_DRV_M48T59 is not set
994# CONFIG_RTC_DRV_V3020 is not set
995
996#
997# on-CPU RTC drivers
998#
999# CONFIG_RTC_DRV_AT91SAM9 is not set
1000
1001#
1002# File systems
1003#
1004CONFIG_EXT2_FS=y
1005# CONFIG_EXT2_FS_XATTR is not set
1006# CONFIG_EXT2_FS_XIP is not set
1007# CONFIG_EXT3_FS is not set
1008# CONFIG_EXT4DEV_FS is not set
1009# CONFIG_REISERFS_FS is not set
1010# CONFIG_JFS_FS is not set
1011CONFIG_FS_POSIX_ACL=y
1012# CONFIG_XFS_FS is not set
1013# CONFIG_GFS2_FS is not set
1014# CONFIG_OCFS2_FS is not set
1015# CONFIG_MINIX_FS is not set
1016# CONFIG_ROMFS_FS is not set
1017CONFIG_INOTIFY=y
1018CONFIG_INOTIFY_USER=y
1019# CONFIG_QUOTA is not set
1020CONFIG_DNOTIFY=y
1021# CONFIG_AUTOFS_FS is not set
1022# CONFIG_AUTOFS4_FS is not set
1023CONFIG_FUSE_FS=m
1024
1025#
1026# CD-ROM/DVD Filesystems
1027#
1028# CONFIG_ISO9660_FS is not set
1029# CONFIG_UDF_FS is not set
1030
1031#
1032# DOS/FAT/NT Filesystems
1033#
1034CONFIG_FAT_FS=y
1035# CONFIG_MSDOS_FS is not set
1036CONFIG_VFAT_FS=y
1037CONFIG_FAT_DEFAULT_CODEPAGE=437
1038CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1039# CONFIG_NTFS_FS is not set
1040
1041#
1042# Pseudo filesystems
1043#
1044CONFIG_PROC_FS=y
1045CONFIG_PROC_SYSCTL=y
1046CONFIG_SYSFS=y
1047CONFIG_TMPFS=y
1048# CONFIG_TMPFS_POSIX_ACL is not set
1049# CONFIG_HUGETLB_PAGE is not set
1050# CONFIG_CONFIGFS_FS is not set
1051
1052#
1053# Miscellaneous filesystems
1054#
1055# CONFIG_ADFS_FS is not set
1056# CONFIG_AFFS_FS is not set
1057# CONFIG_HFS_FS is not set
1058# CONFIG_HFSPLUS_FS is not set
1059# CONFIG_BEFS_FS is not set
1060# CONFIG_BFS_FS is not set
1061# CONFIG_EFS_FS is not set
1062CONFIG_JFFS2_FS=y
1063CONFIG_JFFS2_FS_DEBUG=0
1064CONFIG_JFFS2_FS_WRITEBUFFER=y
1065# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1066# CONFIG_JFFS2_SUMMARY is not set
1067# CONFIG_JFFS2_FS_XATTR is not set
1068# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1069CONFIG_JFFS2_ZLIB=y
1070# CONFIG_JFFS2_LZO is not set
1071CONFIG_JFFS2_RTIME=y
1072# CONFIG_JFFS2_RUBIN is not set
1073# CONFIG_CRAMFS is not set
1074# CONFIG_VXFS_FS is not set
1075# CONFIG_HPFS_FS is not set
1076# CONFIG_QNX4FS_FS is not set
1077# CONFIG_SYSV_FS is not set
1078# CONFIG_UFS_FS is not set
1079CONFIG_NETWORK_FILESYSTEMS=y
1080CONFIG_NFS_FS=y
1081CONFIG_NFS_V3=y
1082CONFIG_NFS_V3_ACL=y
1083CONFIG_NFS_V4=y
1084# CONFIG_NFS_DIRECTIO is not set
1085# CONFIG_NFSD is not set
1086CONFIG_ROOT_NFS=y
1087CONFIG_LOCKD=y
1088CONFIG_LOCKD_V4=y
1089CONFIG_NFS_ACL_SUPPORT=y
1090CONFIG_NFS_COMMON=y
1091CONFIG_SUNRPC=y
1092CONFIG_SUNRPC_GSS=y
1093# CONFIG_SUNRPC_BIND34 is not set
1094CONFIG_RPCSEC_GSS_KRB5=y
1095# CONFIG_RPCSEC_GSS_SPKM3 is not set
1096# CONFIG_SMB_FS is not set
1097# CONFIG_CIFS is not set
1098# CONFIG_NCP_FS is not set
1099# CONFIG_CODA_FS is not set
1100# CONFIG_AFS_FS is not set
1101
1102#
1103# Partition Types
1104#
1105# CONFIG_PARTITION_ADVANCED is not set
1106CONFIG_MSDOS_PARTITION=y
1107CONFIG_NLS=y
1108CONFIG_NLS_DEFAULT="iso8859-1"
1109CONFIG_NLS_CODEPAGE_437=y
1110# CONFIG_NLS_CODEPAGE_737 is not set
1111# CONFIG_NLS_CODEPAGE_775 is not set
1112CONFIG_NLS_CODEPAGE_850=y
1113# CONFIG_NLS_CODEPAGE_852 is not set
1114# CONFIG_NLS_CODEPAGE_855 is not set
1115# CONFIG_NLS_CODEPAGE_857 is not set
1116# CONFIG_NLS_CODEPAGE_860 is not set
1117# CONFIG_NLS_CODEPAGE_861 is not set
1118# CONFIG_NLS_CODEPAGE_862 is not set
1119# CONFIG_NLS_CODEPAGE_863 is not set
1120# CONFIG_NLS_CODEPAGE_864 is not set
1121# CONFIG_NLS_CODEPAGE_865 is not set
1122# CONFIG_NLS_CODEPAGE_866 is not set
1123# CONFIG_NLS_CODEPAGE_869 is not set
1124# CONFIG_NLS_CODEPAGE_936 is not set
1125# CONFIG_NLS_CODEPAGE_950 is not set
1126# CONFIG_NLS_CODEPAGE_932 is not set
1127# CONFIG_NLS_CODEPAGE_949 is not set
1128# CONFIG_NLS_CODEPAGE_874 is not set
1129# CONFIG_NLS_ISO8859_8 is not set
1130# CONFIG_NLS_CODEPAGE_1250 is not set
1131# CONFIG_NLS_CODEPAGE_1251 is not set
1132# CONFIG_NLS_ASCII is not set
1133CONFIG_NLS_ISO8859_1=y
1134# CONFIG_NLS_ISO8859_2 is not set
1135# CONFIG_NLS_ISO8859_3 is not set
1136# CONFIG_NLS_ISO8859_4 is not set
1137# CONFIG_NLS_ISO8859_5 is not set
1138# CONFIG_NLS_ISO8859_6 is not set
1139# CONFIG_NLS_ISO8859_7 is not set
1140# CONFIG_NLS_ISO8859_9 is not set
1141# CONFIG_NLS_ISO8859_13 is not set
1142# CONFIG_NLS_ISO8859_14 is not set
1143# CONFIG_NLS_ISO8859_15 is not set
1144# CONFIG_NLS_KOI8_R is not set
1145# CONFIG_NLS_KOI8_U is not set
1146# CONFIG_NLS_UTF8 is not set
1147# CONFIG_DLM is not set
1148# CONFIG_INSTRUMENTATION is not set
1149
1150#
1151# Kernel hacking
1152#
1153# CONFIG_PRINTK_TIME is not set
1154CONFIG_ENABLE_WARN_DEPRECATED=y
1155CONFIG_ENABLE_MUST_CHECK=y
1156# CONFIG_MAGIC_SYSRQ is not set
1157# CONFIG_UNUSED_SYMBOLS is not set
1158# CONFIG_DEBUG_FS is not set
1159# CONFIG_HEADERS_CHECK is not set
1160CONFIG_DEBUG_KERNEL=y
1161# CONFIG_DEBUG_SHIRQ is not set
1162CONFIG_DETECT_SOFTLOCKUP=y
1163CONFIG_SCHED_DEBUG=y
1164# CONFIG_SCHEDSTATS is not set
1165# CONFIG_TIMER_STATS is not set
1166# CONFIG_DEBUG_SLAB is not set
1167# CONFIG_DEBUG_RT_MUTEXES is not set
1168# CONFIG_RT_MUTEX_TESTER is not set
1169# CONFIG_DEBUG_SPINLOCK is not set
1170# CONFIG_DEBUG_MUTEXES is not set
1171# CONFIG_DEBUG_LOCK_ALLOC is not set
1172# CONFIG_PROVE_LOCKING is not set
1173# CONFIG_LOCK_STAT is not set
1174# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1175# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1176# CONFIG_DEBUG_KOBJECT is not set
1177CONFIG_DEBUG_BUGVERBOSE=y
1178# CONFIG_DEBUG_INFO is not set
1179# CONFIG_DEBUG_VM is not set
1180# CONFIG_DEBUG_LIST is not set
1181# CONFIG_DEBUG_SG is not set
1182CONFIG_FRAME_POINTER=y
1183CONFIG_FORCED_INLINING=y
1184# CONFIG_BOOT_PRINTK_DELAY is not set
1185# CONFIG_RCU_TORTURE_TEST is not set
1186# CONFIG_FAULT_INJECTION is not set
1187# CONFIG_SAMPLES is not set
1188CONFIG_DEBUG_USER=y
1189# CONFIG_DEBUG_ERRORS is not set
1190CONFIG_DEBUG_LL=y
1191# CONFIG_DEBUG_ICEDCC is not set
1192
1193#
1194# Security options
1195#
1196# CONFIG_KEYS is not set
1197# CONFIG_SECURITY is not set
1198# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1199CONFIG_CRYPTO=y
1200CONFIG_CRYPTO_ALGAPI=y
1201CONFIG_CRYPTO_BLKCIPHER=y
1202CONFIG_CRYPTO_MANAGER=y
1203# CONFIG_CRYPTO_HMAC is not set
1204# CONFIG_CRYPTO_XCBC is not set
1205# CONFIG_CRYPTO_NULL is not set
1206# CONFIG_CRYPTO_MD4 is not set
1207CONFIG_CRYPTO_MD5=y
1208# CONFIG_CRYPTO_SHA1 is not set
1209# CONFIG_CRYPTO_SHA256 is not set
1210# CONFIG_CRYPTO_SHA512 is not set
1211# CONFIG_CRYPTO_WP512 is not set
1212# CONFIG_CRYPTO_TGR192 is not set
1213# CONFIG_CRYPTO_GF128MUL is not set
1214# CONFIG_CRYPTO_ECB is not set
1215CONFIG_CRYPTO_CBC=y
1216# CONFIG_CRYPTO_PCBC is not set
1217# CONFIG_CRYPTO_LRW is not set
1218# CONFIG_CRYPTO_XTS is not set
1219# CONFIG_CRYPTO_CRYPTD is not set
1220CONFIG_CRYPTO_DES=y
1221# CONFIG_CRYPTO_FCRYPT is not set
1222# CONFIG_CRYPTO_BLOWFISH is not set
1223# CONFIG_CRYPTO_TWOFISH is not set
1224# CONFIG_CRYPTO_SERPENT is not set
1225# CONFIG_CRYPTO_AES is not set
1226# CONFIG_CRYPTO_CAST5 is not set
1227# CONFIG_CRYPTO_CAST6 is not set
1228# CONFIG_CRYPTO_TEA is not set
1229# CONFIG_CRYPTO_ARC4 is not set
1230# CONFIG_CRYPTO_KHAZAD is not set
1231# CONFIG_CRYPTO_ANUBIS is not set
1232# CONFIG_CRYPTO_SEED is not set
1233# CONFIG_CRYPTO_DEFLATE is not set
1234# CONFIG_CRYPTO_MICHAEL_MIC is not set
1235# CONFIG_CRYPTO_CRC32C is not set
1236# CONFIG_CRYPTO_CAMELLIA is not set
1237# CONFIG_CRYPTO_TEST is not set
1238# CONFIG_CRYPTO_AUTHENC is not set
1239# CONFIG_CRYPTO_HW is not set
1240
1241#
1242# Library routines
1243#
1244CONFIG_BITREVERSE=y
1245# CONFIG_CRC_CCITT is not set
1246# CONFIG_CRC16 is not set
1247# CONFIG_CRC_ITU_T is not set
1248CONFIG_CRC32=y
1249# CONFIG_CRC7 is not set
1250# CONFIG_LIBCRC32C is not set
1251CONFIG_ZLIB_INFLATE=y
1252CONFIG_ZLIB_DEFLATE=y
1253CONFIG_PLIST=y
1254CONFIG_HAS_IOMEM=y
1255CONFIG_HAS_IOPORT=y
1256CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index fc39ba1a89f3..0c09b23167ec 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -177,7 +177,6 @@ CONFIG_NR_CPUS=4
177CONFIG_HOTPLUG_CPU=y 177CONFIG_HOTPLUG_CPU=y
178CONFIG_LOCAL_TIMERS=y 178CONFIG_LOCAL_TIMERS=y
179# CONFIG_PREEMPT is not set 179# CONFIG_PREEMPT is not set
180# CONFIG_NO_IDLE_HZ is not set
181CONFIG_HZ=100 180CONFIG_HZ=100
182# CONFIG_AEABI is not set 181# CONFIG_AEABI is not set
183# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 182# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index accbf529ce5b..907e54344dad 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -126,7 +126,6 @@ CONFIG_ISA_DMA_API=y
126# 126#
127# Kernel Features 127# Kernel Features
128# 128#
129# CONFIG_NO_IDLE_HZ is not set
130# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 129# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
131CONFIG_FLATMEM=y 130CONFIG_FLATMEM=y
132CONFIG_FLAT_NODE_MEM_MAP=y 131CONFIG_FLAT_NODE_MEM_MAP=y
diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
index 5ddecb9ddf01..f62d1817d2c6 100644
--- a/arch/arm/configs/rpc_defconfig
+++ b/arch/arm/configs/rpc_defconfig
@@ -190,7 +190,6 @@ CONFIG_ISA_DMA_API=y
190# 190#
191# CONFIG_TICK_ONESHOT is not set 191# CONFIG_TICK_ONESHOT is not set
192# CONFIG_PREEMPT is not set 192# CONFIG_PREEMPT is not set
193# CONFIG_NO_IDLE_HZ is not set
194CONFIG_HZ=100 193CONFIG_HZ=100
195# CONFIG_AEABI is not set 194# CONFIG_AEABI is not set
196# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 195# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig
index f8a1645b3d4a..35faaea8623e 100644
--- a/arch/arm/configs/s3c2410_defconfig
+++ b/arch/arm/configs/s3c2410_defconfig
@@ -1,15 +1,18 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.21-rc6 3# Linux kernel version: 2.6.26-rc8
4# Mon Apr 9 10:12:58 2007 4# Mon Jul 7 16:59:23 2008
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y 7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y 8CONFIG_GENERIC_GPIO=y
9# CONFIG_GENERIC_TIME is not set 9# CONFIG_GENERIC_TIME is not set
10# CONFIG_GENERIC_CLOCKEVENTS is not set
10CONFIG_MMU=y 11CONFIG_MMU=y
11CONFIG_NO_IOPORT=y 12CONFIG_NO_IOPORT=y
12CONFIG_GENERIC_HARDIRQS=y 13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
13CONFIG_TRACE_IRQFLAGS_SUPPORT=y 16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
14CONFIG_HARDIRQS_SW_RESEND=y 17CONFIG_HARDIRQS_SW_RESEND=y
15CONFIG_GENERIC_IRQ_PROBE=y 18CONFIG_GENERIC_IRQ_PROBE=y
@@ -18,34 +21,39 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y
18# CONFIG_ARCH_HAS_ILOG2_U64 is not set 21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
19CONFIG_GENERIC_HWEIGHT=y 22CONFIG_GENERIC_HWEIGHT=y
20CONFIG_GENERIC_CALIBRATE_DELAY=y 23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ARCH_SUPPORTS_AOUT=y
21CONFIG_ZONE_DMA=y 25CONFIG_ZONE_DMA=y
22CONFIG_VECTORS_BASE=0xffff0000 26CONFIG_VECTORS_BASE=0xffff0000
23CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" 27CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
24 28
25# 29#
26# Code maturity level options 30# General setup
27# 31#
28CONFIG_EXPERIMENTAL=y 32CONFIG_EXPERIMENTAL=y
29CONFIG_BROKEN_ON_SMP=y 33CONFIG_BROKEN_ON_SMP=y
30CONFIG_INIT_ENV_ARG_LIMIT=32 34CONFIG_INIT_ENV_ARG_LIMIT=32
31
32#
33# General setup
34#
35CONFIG_LOCALVERSION="" 35CONFIG_LOCALVERSION=""
36CONFIG_LOCALVERSION_AUTO=y 36CONFIG_LOCALVERSION_AUTO=y
37CONFIG_SWAP=y 37CONFIG_SWAP=y
38CONFIG_SYSVIPC=y 38CONFIG_SYSVIPC=y
39# CONFIG_IPC_NS is not set
40CONFIG_SYSVIPC_SYSCTL=y 39CONFIG_SYSVIPC_SYSCTL=y
41# CONFIG_POSIX_MQUEUE is not set 40# CONFIG_POSIX_MQUEUE is not set
42# CONFIG_BSD_PROCESS_ACCT is not set 41# CONFIG_BSD_PROCESS_ACCT is not set
43# CONFIG_TASKSTATS is not set 42# CONFIG_TASKSTATS is not set
44# CONFIG_UTS_NS is not set
45# CONFIG_AUDIT is not set 43# CONFIG_AUDIT is not set
46# CONFIG_IKCONFIG is not set 44CONFIG_IKCONFIG=m
45CONFIG_IKCONFIG_PROC=y
46CONFIG_LOG_BUF_SHIFT=16
47# CONFIG_CGROUPS is not set
48# CONFIG_GROUP_SCHED is not set
47CONFIG_SYSFS_DEPRECATED=y 49CONFIG_SYSFS_DEPRECATED=y
50CONFIG_SYSFS_DEPRECATED_V2=y
48# CONFIG_RELAY is not set 51# CONFIG_RELAY is not set
52CONFIG_NAMESPACES=y
53# CONFIG_UTS_NS is not set
54# CONFIG_IPC_NS is not set
55# CONFIG_USER_NS is not set
56# CONFIG_PID_NS is not set
49CONFIG_BLK_DEV_INITRD=y 57CONFIG_BLK_DEV_INITRD=y
50CONFIG_INITRAMFS_SOURCE="" 58CONFIG_INITRAMFS_SOURCE=""
51CONFIG_CC_OPTIMIZE_FOR_SIZE=y 59CONFIG_CC_OPTIMIZE_FOR_SIZE=y
@@ -53,6 +61,7 @@ CONFIG_SYSCTL=y
53# CONFIG_EMBEDDED is not set 61# CONFIG_EMBEDDED is not set
54CONFIG_UID16=y 62CONFIG_UID16=y
55CONFIG_SYSCTL_SYSCALL=y 63CONFIG_SYSCTL_SYSCALL=y
64CONFIG_SYSCTL_SYSCALL_CHECK=y
56CONFIG_KALLSYMS=y 65CONFIG_KALLSYMS=y
57# CONFIG_KALLSYMS_ALL is not set 66# CONFIG_KALLSYMS_ALL is not set
58# CONFIG_KALLSYMS_EXTRA_PASS is not set 67# CONFIG_KALLSYMS_EXTRA_PASS is not set
@@ -60,34 +69,43 @@ CONFIG_HOTPLUG=y
60CONFIG_PRINTK=y 69CONFIG_PRINTK=y
61CONFIG_BUG=y 70CONFIG_BUG=y
62CONFIG_ELF_CORE=y 71CONFIG_ELF_CORE=y
72CONFIG_COMPAT_BRK=y
63CONFIG_BASE_FULL=y 73CONFIG_BASE_FULL=y
64CONFIG_FUTEX=y 74CONFIG_FUTEX=y
75CONFIG_ANON_INODES=y
65CONFIG_EPOLL=y 76CONFIG_EPOLL=y
77CONFIG_SIGNALFD=y
78CONFIG_TIMERFD=y
79CONFIG_EVENTFD=y
66CONFIG_SHMEM=y 80CONFIG_SHMEM=y
67CONFIG_SLAB=y
68CONFIG_VM_EVENT_COUNTERS=y 81CONFIG_VM_EVENT_COUNTERS=y
82CONFIG_SLAB=y
83# CONFIG_SLUB is not set
84# CONFIG_SLOB is not set
85# CONFIG_PROFILING is not set
86# CONFIG_MARKERS is not set
87CONFIG_HAVE_OPROFILE=y
88# CONFIG_KPROBES is not set
89CONFIG_HAVE_KPROBES=y
90CONFIG_HAVE_KRETPROBES=y
91# CONFIG_HAVE_DMA_ATTRS is not set
92CONFIG_PROC_PAGE_MONITOR=y
93CONFIG_SLABINFO=y
69CONFIG_RT_MUTEXES=y 94CONFIG_RT_MUTEXES=y
70# CONFIG_TINY_SHMEM is not set 95# CONFIG_TINY_SHMEM is not set
71CONFIG_BASE_SMALL=0 96CONFIG_BASE_SMALL=0
72# CONFIG_SLOB is not set
73
74#
75# Loadable module support
76#
77CONFIG_MODULES=y 97CONFIG_MODULES=y
98# CONFIG_MODULE_FORCE_LOAD is not set
78CONFIG_MODULE_UNLOAD=y 99CONFIG_MODULE_UNLOAD=y
79# CONFIG_MODULE_FORCE_UNLOAD is not set 100# CONFIG_MODULE_FORCE_UNLOAD is not set
80# CONFIG_MODVERSIONS is not set 101# CONFIG_MODVERSIONS is not set
81# CONFIG_MODULE_SRCVERSION_ALL is not set 102# CONFIG_MODULE_SRCVERSION_ALL is not set
82CONFIG_KMOD=y 103CONFIG_KMOD=y
83
84#
85# Block layer
86#
87CONFIG_BLOCK=y 104CONFIG_BLOCK=y
88# CONFIG_LBD is not set 105# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set 106# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set 107# CONFIG_LSF is not set
108# CONFIG_BLK_DEV_BSG is not set
91 109
92# 110#
93# IO Schedulers 111# IO Schedulers
@@ -101,6 +119,7 @@ CONFIG_DEFAULT_AS=y
101# CONFIG_DEFAULT_CFQ is not set 119# CONFIG_DEFAULT_CFQ is not set
102# CONFIG_DEFAULT_NOOP is not set 120# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="anticipatory" 121CONFIG_DEFAULT_IOSCHED="anticipatory"
122CONFIG_CLASSIC_RCU=y
104 123
105# 124#
106# System Type 125# System Type
@@ -119,14 +138,17 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
119# CONFIG_ARCH_NETX is not set 138# CONFIG_ARCH_NETX is not set
120# CONFIG_ARCH_H720X is not set 139# CONFIG_ARCH_H720X is not set
121# CONFIG_ARCH_IMX is not set 140# CONFIG_ARCH_IMX is not set
141# CONFIG_ARCH_IOP13XX is not set
122# CONFIG_ARCH_IOP32X is not set 142# CONFIG_ARCH_IOP32X is not set
123# CONFIG_ARCH_IOP33X is not set 143# CONFIG_ARCH_IOP33X is not set
124# CONFIG_ARCH_IOP13XX is not set
125# CONFIG_ARCH_IXP4XX is not set
126# CONFIG_ARCH_IXP2000 is not set
127# CONFIG_ARCH_IXP23XX is not set 144# CONFIG_ARCH_IXP23XX is not set
145# CONFIG_ARCH_IXP2000 is not set
146# CONFIG_ARCH_IXP4XX is not set
128# CONFIG_ARCH_L7200 is not set 147# CONFIG_ARCH_L7200 is not set
148# CONFIG_ARCH_KS8695 is not set
129# CONFIG_ARCH_NS9XXX is not set 149# CONFIG_ARCH_NS9XXX is not set
150# CONFIG_ARCH_MXC is not set
151# CONFIG_ARCH_ORION5X is not set
130# CONFIG_ARCH_PNX4008 is not set 152# CONFIG_ARCH_PNX4008 is not set
131# CONFIG_ARCH_PXA is not set 153# CONFIG_ARCH_PXA is not set
132# CONFIG_ARCH_RPC is not set 154# CONFIG_ARCH_RPC is not set
@@ -134,18 +156,32 @@ CONFIG_DEFAULT_IOSCHED="anticipatory"
134CONFIG_ARCH_S3C2410=y 156CONFIG_ARCH_S3C2410=y
135# CONFIG_ARCH_SHARK is not set 157# CONFIG_ARCH_SHARK is not set
136# CONFIG_ARCH_LH7A40X is not set 158# CONFIG_ARCH_LH7A40X is not set
159# CONFIG_ARCH_DAVINCI is not set
137# CONFIG_ARCH_OMAP is not set 160# CONFIG_ARCH_OMAP is not set
161# CONFIG_ARCH_MSM7X00A is not set
138CONFIG_PLAT_S3C24XX=y 162CONFIG_PLAT_S3C24XX=y
139CONFIG_CPU_S3C244X=y 163CONFIG_CPU_S3C244X=y
164# CONFIG_S3C24XX_PWM is not set
140CONFIG_PM_SIMTEC=y 165CONFIG_PM_SIMTEC=y
166CONFIG_S3C2410_DMA=y
167# CONFIG_S3C2410_DMA_DEBUG is not set
168CONFIG_MACH_SMDK=y
169CONFIG_PLAT_S3C=y
170CONFIG_CPU_LLSERIAL_S3C2410=y
171CONFIG_CPU_LLSERIAL_S3C2440=y
172
173#
174# Boot options
175#
141# CONFIG_S3C_BOOT_WATCHDOG is not set 176# CONFIG_S3C_BOOT_WATCHDOG is not set
142# CONFIG_S3C_BOOT_ERROR_RESET is not set 177# CONFIG_S3C_BOOT_ERROR_RESET is not set
178
179#
180# Power management
181#
143# CONFIG_S3C2410_PM_DEBUG is not set 182# CONFIG_S3C2410_PM_DEBUG is not set
144# CONFIG_S3C2410_PM_CHECK is not set 183# CONFIG_S3C2410_PM_CHECK is not set
145CONFIG_S3C_LOWLEVEL_UART_PORT=0 184CONFIG_S3C_LOWLEVEL_UART_PORT=0
146CONFIG_S3C2410_DMA=y
147# CONFIG_S3C2410_DMA_DEBUG is not set
148CONFIG_MACH_SMDK=y
149 185
150# 186#
151# S3C2400 Machines 187# S3C2400 Machines
@@ -155,6 +191,8 @@ CONFIG_CPU_S3C2410_DMA=y
155CONFIG_S3C2410_PM=y 191CONFIG_S3C2410_PM=y
156CONFIG_S3C2410_GPIO=y 192CONFIG_S3C2410_GPIO=y
157CONFIG_S3C2410_CLOCK=y 193CONFIG_S3C2410_CLOCK=y
194CONFIG_SIMTEC_NOR=y
195CONFIG_MACH_BAST_IDE=y
158 196
159# 197#
160# S3C2410 Machines 198# S3C2410 Machines
@@ -167,6 +205,7 @@ CONFIG_ARCH_BAST=y
167CONFIG_MACH_OTOM=y 205CONFIG_MACH_OTOM=y
168CONFIG_MACH_AML_M5900=y 206CONFIG_MACH_AML_M5900=y
169CONFIG_BAST_PC104_IRQ=y 207CONFIG_BAST_PC104_IRQ=y
208# CONFIG_MACH_TCT_HAMMER is not set
170CONFIG_MACH_VR1000=y 209CONFIG_MACH_VR1000=y
171CONFIG_MACH_QT2410=y 210CONFIG_MACH_QT2410=y
172CONFIG_CPU_S3C2412=y 211CONFIG_CPU_S3C2412=y
@@ -176,8 +215,10 @@ CONFIG_S3C2412_PM=y
176# 215#
177# S3C2412 Machines 216# S3C2412 Machines
178# 217#
218# CONFIG_MACH_JIVE is not set
179CONFIG_MACH_SMDK2413=y 219CONFIG_MACH_SMDK2413=y
180CONFIG_MACH_S3C2413=y 220CONFIG_MACH_S3C2413=y
221# CONFIG_MACH_SMDK2412 is not set
181CONFIG_MACH_VSTMS=y 222CONFIG_MACH_VSTMS=y
182CONFIG_CPU_S3C2440=y 223CONFIG_CPU_S3C2440=y
183CONFIG_S3C2440_DMA=y 224CONFIG_S3C2440_DMA=y
@@ -191,6 +232,7 @@ CONFIG_MACH_RX3715=y
191CONFIG_ARCH_S3C2440=y 232CONFIG_ARCH_S3C2440=y
192CONFIG_MACH_NEXCODER_2440=y 233CONFIG_MACH_NEXCODER_2440=y
193CONFIG_SMDK2440_CPU2440=y 234CONFIG_SMDK2440_CPU2440=y
235# CONFIG_MACH_AT2440EVB is not set
194CONFIG_CPU_S3C2442=y 236CONFIG_CPU_S3C2442=y
195 237
196# 238#
@@ -215,6 +257,7 @@ CONFIG_CPU_32v4T=y
215CONFIG_CPU_32v5=y 257CONFIG_CPU_32v5=y
216CONFIG_CPU_ABRT_EV4T=y 258CONFIG_CPU_ABRT_EV4T=y
217CONFIG_CPU_ABRT_EV5TJ=y 259CONFIG_CPU_ABRT_EV5TJ=y
260CONFIG_CPU_PABRT_NOIFAR=y
218CONFIG_CPU_CACHE_V4WT=y 261CONFIG_CPU_CACHE_V4WT=y
219CONFIG_CPU_CACHE_VIVT=y 262CONFIG_CPU_CACHE_VIVT=y
220CONFIG_CPU_COPY_V4WB=y 263CONFIG_CPU_COPY_V4WB=y
@@ -236,17 +279,15 @@ CONFIG_CPU_CP15_MMU=y
236# Bus support 279# Bus support
237# 280#
238CONFIG_ISA=y 281CONFIG_ISA=y
239 282# CONFIG_PCI_SYSCALL is not set
240# 283# CONFIG_ARCH_SUPPORTS_MSI is not set
241# PCCARD (PCMCIA/CardBus) support
242#
243# CONFIG_PCCARD is not set 284# CONFIG_PCCARD is not set
244 285
245# 286#
246# Kernel Features 287# Kernel Features
247# 288#
289# CONFIG_TICK_ONESHOT is not set
248# CONFIG_PREEMPT is not set 290# CONFIG_PREEMPT is not set
249# CONFIG_NO_IDLE_HZ is not set
250CONFIG_HZ=200 291CONFIG_HZ=200
251# CONFIG_AEABI is not set 292# CONFIG_AEABI is not set
252# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 293# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
@@ -257,9 +298,13 @@ CONFIG_FLATMEM_MANUAL=y
257CONFIG_FLATMEM=y 298CONFIG_FLATMEM=y
258CONFIG_FLAT_NODE_MEM_MAP=y 299CONFIG_FLAT_NODE_MEM_MAP=y
259# CONFIG_SPARSEMEM_STATIC is not set 300# CONFIG_SPARSEMEM_STATIC is not set
301# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
302CONFIG_PAGEFLAGS_EXTENDED=y
260CONFIG_SPLIT_PTLOCK_CPUS=4096 303CONFIG_SPLIT_PTLOCK_CPUS=4096
261# CONFIG_RESOURCES_64BIT is not set 304# CONFIG_RESOURCES_64BIT is not set
262CONFIG_ZONE_DMA_FLAG=1 305CONFIG_ZONE_DMA_FLAG=1
306CONFIG_BOUNCE=y
307CONFIG_VIRT_TO_BUS=y
263CONFIG_ALIGNMENT_TRAP=y 308CONFIG_ALIGNMENT_TRAP=y
264 309
265# 310#
@@ -279,7 +324,7 @@ CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0"
279# At least one emulation must be selected 324# At least one emulation must be selected
280# 325#
281CONFIG_FPE_NWFPE=y 326CONFIG_FPE_NWFPE=y
282# CONFIG_FPE_NWFPE_XP is not set 327CONFIG_FPE_NWFPE_XP=y
283# CONFIG_FPE_FASTFPE is not set 328# CONFIG_FPE_FASTFPE is not set
284# CONFIG_VFP is not set 329# CONFIG_VFP is not set
285 330
@@ -295,10 +340,12 @@ CONFIG_BINFMT_AOUT=y
295# Power management options 340# Power management options
296# 341#
297CONFIG_PM=y 342CONFIG_PM=y
298# CONFIG_PM_LEGACY is not set
299# CONFIG_PM_DEBUG is not set 343# CONFIG_PM_DEBUG is not set
300# CONFIG_PM_SYSFS_DEPRECATED is not set 344CONFIG_PM_SLEEP=y
301# CONFIG_APM_EMULATION is not set 345CONFIG_SUSPEND=y
346CONFIG_SUSPEND_FREEZER=y
347CONFIG_APM_EMULATION=m
348CONFIG_ARCH_SUSPEND_POSSIBLE=y
302 349
303# 350#
304# Networking 351# Networking
@@ -308,59 +355,67 @@ CONFIG_NET=y
308# 355#
309# Networking options 356# Networking options
310# 357#
311# CONFIG_NETDEBUG is not set 358CONFIG_PACKET=y
312# CONFIG_PACKET is not set 359# CONFIG_PACKET_MMAP is not set
313CONFIG_UNIX=y 360CONFIG_UNIX=y
314CONFIG_XFRM=y 361CONFIG_XFRM=y
315# CONFIG_XFRM_USER is not set 362# CONFIG_XFRM_USER is not set
316# CONFIG_XFRM_SUB_POLICY is not set 363# CONFIG_XFRM_SUB_POLICY is not set
317# CONFIG_XFRM_MIGRATE is not set 364# CONFIG_XFRM_MIGRATE is not set
365# CONFIG_XFRM_STATISTICS is not set
318# CONFIG_NET_KEY is not set 366# CONFIG_NET_KEY is not set
319CONFIG_INET=y 367CONFIG_INET=y
320# CONFIG_IP_MULTICAST is not set 368CONFIG_IP_MULTICAST=y
321# CONFIG_IP_ADVANCED_ROUTER is not set 369# CONFIG_IP_ADVANCED_ROUTER is not set
322CONFIG_IP_FIB_HASH=y 370CONFIG_IP_FIB_HASH=y
323CONFIG_IP_PNP=y 371CONFIG_IP_PNP=y
324# CONFIG_IP_PNP_DHCP is not set 372CONFIG_IP_PNP_DHCP=y
325CONFIG_IP_PNP_BOOTP=y 373CONFIG_IP_PNP_BOOTP=y
326# CONFIG_IP_PNP_RARP is not set 374# CONFIG_IP_PNP_RARP is not set
327# CONFIG_NET_IPIP is not set 375# CONFIG_NET_IPIP is not set
328# CONFIG_NET_IPGRE is not set 376# CONFIG_NET_IPGRE is not set
377# CONFIG_IP_MROUTE is not set
329# CONFIG_ARPD is not set 378# CONFIG_ARPD is not set
330# CONFIG_SYN_COOKIES is not set 379# CONFIG_SYN_COOKIES is not set
331# CONFIG_INET_AH is not set 380# CONFIG_INET_AH is not set
332# CONFIG_INET_ESP is not set 381# CONFIG_INET_ESP is not set
333# CONFIG_INET_IPCOMP is not set 382# CONFIG_INET_IPCOMP is not set
334# CONFIG_INET_XFRM_TUNNEL is not set 383# CONFIG_INET_XFRM_TUNNEL is not set
335# CONFIG_INET_TUNNEL is not set 384CONFIG_INET_TUNNEL=m
336CONFIG_INET_XFRM_MODE_TRANSPORT=y 385CONFIG_INET_XFRM_MODE_TRANSPORT=y
337CONFIG_INET_XFRM_MODE_TUNNEL=y 386CONFIG_INET_XFRM_MODE_TUNNEL=y
338CONFIG_INET_XFRM_MODE_BEET=y 387CONFIG_INET_XFRM_MODE_BEET=y
388# CONFIG_INET_LRO is not set
339CONFIG_INET_DIAG=y 389CONFIG_INET_DIAG=y
340CONFIG_INET_TCP_DIAG=y 390CONFIG_INET_TCP_DIAG=y
341# CONFIG_TCP_CONG_ADVANCED is not set 391# CONFIG_TCP_CONG_ADVANCED is not set
342CONFIG_TCP_CONG_CUBIC=y 392CONFIG_TCP_CONG_CUBIC=y
343CONFIG_DEFAULT_TCP_CONG="cubic" 393CONFIG_DEFAULT_TCP_CONG="cubic"
344# CONFIG_TCP_MD5SIG is not set 394# CONFIG_TCP_MD5SIG is not set
345# CONFIG_IPV6 is not set 395CONFIG_IPV6=m
346# CONFIG_INET6_XFRM_TUNNEL is not set 396CONFIG_IPV6_PRIVACY=y
347# CONFIG_INET6_TUNNEL is not set 397CONFIG_IPV6_ROUTER_PREF=y
398# CONFIG_IPV6_ROUTE_INFO is not set
399# CONFIG_IPV6_OPTIMISTIC_DAD is not set
400CONFIG_INET6_AH=m
401CONFIG_INET6_ESP=m
402CONFIG_INET6_IPCOMP=m
403CONFIG_IPV6_MIP6=m
404CONFIG_INET6_XFRM_TUNNEL=m
405CONFIG_INET6_TUNNEL=m
406CONFIG_INET6_XFRM_MODE_TRANSPORT=m
407CONFIG_INET6_XFRM_MODE_TUNNEL=m
408CONFIG_INET6_XFRM_MODE_BEET=m
409CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
410CONFIG_IPV6_SIT=m
411CONFIG_IPV6_NDISC_NODETYPE=y
412CONFIG_IPV6_TUNNEL=m
413# CONFIG_IPV6_MULTIPLE_TABLES is not set
414# CONFIG_IPV6_MROUTE is not set
348# CONFIG_NETWORK_SECMARK is not set 415# CONFIG_NETWORK_SECMARK is not set
349# CONFIG_NETFILTER is not set 416# CONFIG_NETFILTER is not set
350
351#
352# DCCP Configuration (EXPERIMENTAL)
353#
354# CONFIG_IP_DCCP is not set 417# CONFIG_IP_DCCP is not set
355
356#
357# SCTP Configuration (EXPERIMENTAL)
358#
359# CONFIG_IP_SCTP is not set 418# CONFIG_IP_SCTP is not set
360
361#
362# TIPC Configuration (EXPERIMENTAL)
363#
364# CONFIG_TIPC is not set 419# CONFIG_TIPC is not set
365# CONFIG_ATM is not set 420# CONFIG_ATM is not set
366# CONFIG_BRIDGE is not set 421# CONFIG_BRIDGE is not set
@@ -373,20 +428,71 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
373# CONFIG_LAPB is not set 428# CONFIG_LAPB is not set
374# CONFIG_ECONET is not set 429# CONFIG_ECONET is not set
375# CONFIG_WAN_ROUTER is not set 430# CONFIG_WAN_ROUTER is not set
376
377#
378# QoS and/or fair queueing
379#
380# CONFIG_NET_SCHED is not set 431# CONFIG_NET_SCHED is not set
432CONFIG_NET_SCH_FIFO=y
381 433
382# 434#
383# Network testing 435# Network testing
384# 436#
385# CONFIG_NET_PKTGEN is not set 437# CONFIG_NET_PKTGEN is not set
386# CONFIG_HAMRADIO is not set 438# CONFIG_HAMRADIO is not set
439# CONFIG_CAN is not set
387# CONFIG_IRDA is not set 440# CONFIG_IRDA is not set
388# CONFIG_BT is not set 441CONFIG_BT=m
442CONFIG_BT_L2CAP=m
443CONFIG_BT_SCO=m
444CONFIG_BT_RFCOMM=m
445CONFIG_BT_RFCOMM_TTY=y
446CONFIG_BT_BNEP=m
447CONFIG_BT_BNEP_MC_FILTER=y
448CONFIG_BT_BNEP_PROTO_FILTER=y
449CONFIG_BT_HIDP=m
450
451#
452# Bluetooth device drivers
453#
454CONFIG_BT_HCIUSB=m
455CONFIG_BT_HCIUSB_SCO=y
456CONFIG_BT_HCIUART=m
457CONFIG_BT_HCIUART_H4=y
458CONFIG_BT_HCIUART_BCSP=y
459CONFIG_BT_HCIUART_LL=y
460CONFIG_BT_HCIBCM203X=m
461CONFIG_BT_HCIBPA10X=m
462CONFIG_BT_HCIBFUSB=m
463CONFIG_BT_HCIVHCI=m
464# CONFIG_AF_RXRPC is not set
465
466#
467# Wireless
468#
469CONFIG_CFG80211=m
470CONFIG_NL80211=y
471CONFIG_WIRELESS_EXT=y
472CONFIG_MAC80211=m
473
474#
475# Rate control algorithm selection
476#
477CONFIG_MAC80211_RC_DEFAULT_PID=y
478# CONFIG_MAC80211_RC_DEFAULT_NONE is not set
479
480#
481# Selecting 'y' for an algorithm will
482#
483
484#
485# build the algorithm into mac80211.
486#
487CONFIG_MAC80211_RC_DEFAULT="pid"
488CONFIG_MAC80211_RC_PID=y
489CONFIG_MAC80211_MESH=y
490CONFIG_MAC80211_LEDS=y
491# CONFIG_MAC80211_DEBUG_PACKET_ALIGNMENT is not set
492# CONFIG_MAC80211_DEBUG is not set
389# CONFIG_IEEE80211 is not set 493# CONFIG_IEEE80211 is not set
494# CONFIG_RFKILL is not set
495# CONFIG_NET_9P is not set
390 496
391# 497#
392# Device Drivers 498# Device Drivers
@@ -395,21 +501,14 @@ CONFIG_DEFAULT_TCP_CONG="cubic"
395# 501#
396# Generic Driver Options 502# Generic Driver Options
397# 503#
504CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
398CONFIG_STANDALONE=y 505CONFIG_STANDALONE=y
399CONFIG_PREVENT_FIRMWARE_BUILD=y 506CONFIG_PREVENT_FIRMWARE_BUILD=y
400# CONFIG_FW_LOADER is not set 507CONFIG_FW_LOADER=m
401# CONFIG_DEBUG_DRIVER is not set 508# CONFIG_DEBUG_DRIVER is not set
402# CONFIG_DEBUG_DEVRES is not set 509# CONFIG_DEBUG_DEVRES is not set
403# CONFIG_SYS_HYPERVISOR is not set 510# CONFIG_SYS_HYPERVISOR is not set
404
405#
406# Connector - unified userspace <-> kernelspace linker
407#
408# CONFIG_CONNECTOR is not set 511# CONFIG_CONNECTOR is not set
409
410#
411# Memory Technology Devices (MTD)
412#
413CONFIG_MTD=y 512CONFIG_MTD=y
414# CONFIG_MTD_DEBUG is not set 513# CONFIG_MTD_DEBUG is not set
415# CONFIG_MTD_CONCAT is not set 514# CONFIG_MTD_CONCAT is not set
@@ -420,6 +519,7 @@ CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y
420# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set 519# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
421CONFIG_MTD_CMDLINE_PARTS=y 520CONFIG_MTD_CMDLINE_PARTS=y
422# CONFIG_MTD_AFS_PARTS is not set 521# CONFIG_MTD_AFS_PARTS is not set
522# CONFIG_MTD_AR7_PARTS is not set
423 523
424# 524#
425# User Modules And Translation Layers 525# User Modules And Translation Layers
@@ -432,6 +532,7 @@ CONFIG_MTD_BLOCK=y
432# CONFIG_INFTL is not set 532# CONFIG_INFTL is not set
433# CONFIG_RFD_FTL is not set 533# CONFIG_RFD_FTL is not set
434# CONFIG_SSFDC is not set 534# CONFIG_SSFDC is not set
535# CONFIG_MTD_OOPS is not set
435 536
436# 537#
437# RAM/ROM/Flash chip drivers 538# RAM/ROM/Flash chip drivers
@@ -457,7 +558,6 @@ CONFIG_MTD_CFI_UTIL=y
457# CONFIG_MTD_RAM is not set 558# CONFIG_MTD_RAM is not set
458CONFIG_MTD_ROM=y 559CONFIG_MTD_ROM=y
459# CONFIG_MTD_ABSENT is not set 560# CONFIG_MTD_ABSENT is not set
460# CONFIG_MTD_OBSOLETE_CHIPS is not set
461 561
462# 562#
463# Mapping drivers for chip access 563# Mapping drivers for chip access
@@ -486,13 +586,10 @@ CONFIG_MTD_BAST_MAXSIZE=4
486# CONFIG_MTD_DOC2000 is not set 586# CONFIG_MTD_DOC2000 is not set
487# CONFIG_MTD_DOC2001 is not set 587# CONFIG_MTD_DOC2001 is not set
488# CONFIG_MTD_DOC2001PLUS is not set 588# CONFIG_MTD_DOC2001PLUS is not set
489
490#
491# NAND Flash Device Drivers
492#
493CONFIG_MTD_NAND=y 589CONFIG_MTD_NAND=y
494# CONFIG_MTD_NAND_VERIFY_WRITE is not set 590# CONFIG_MTD_NAND_VERIFY_WRITE is not set
495# CONFIG_MTD_NAND_ECC_SMC is not set 591# CONFIG_MTD_NAND_ECC_SMC is not set
592# CONFIG_MTD_NAND_MUSEUM_IDS is not set
496CONFIG_MTD_NAND_IDS=y 593CONFIG_MTD_NAND_IDS=y
497CONFIG_MTD_NAND_S3C2410=y 594CONFIG_MTD_NAND_S3C2410=y
498# CONFIG_MTD_NAND_S3C2410_DEBUG is not set 595# CONFIG_MTD_NAND_S3C2410_DEBUG is not set
@@ -500,30 +597,25 @@ CONFIG_MTD_NAND_S3C2410=y
500# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set 597# CONFIG_MTD_NAND_S3C2410_CLKSTOP is not set
501# CONFIG_MTD_NAND_DISKONCHIP is not set 598# CONFIG_MTD_NAND_DISKONCHIP is not set
502# CONFIG_MTD_NAND_NANDSIM is not set 599# CONFIG_MTD_NAND_NANDSIM is not set
503 600# CONFIG_MTD_NAND_PLATFORM is not set
504# 601# CONFIG_MTD_ALAUDA is not set
505# OneNAND Flash Device Drivers
506#
507# CONFIG_MTD_ONENAND is not set 602# CONFIG_MTD_ONENAND is not set
508 603
509# 604#
510# Parallel port support 605# UBI - Unsorted block images
511# 606#
607# CONFIG_MTD_UBI is not set
512CONFIG_PARPORT=y 608CONFIG_PARPORT=y
513# CONFIG_PARPORT_PC is not set 609CONFIG_PARPORT_PC=m
610# CONFIG_PARPORT_PC_FIFO is not set
611# CONFIG_PARPORT_PC_SUPERIO is not set
514# CONFIG_PARPORT_GSC is not set 612# CONFIG_PARPORT_GSC is not set
515# CONFIG_PARPORT_AX88796 is not set 613CONFIG_PARPORT_AX88796=m
516CONFIG_PARPORT_1284=y 614CONFIG_PARPORT_1284=y
517 615CONFIG_PARPORT_NOT_PC=y
518#
519# Plug and Play support
520#
521# CONFIG_PNP is not set 616# CONFIG_PNP is not set
522# CONFIG_PNPACPI is not set 617CONFIG_BLK_DEV=y
523 618# CONFIG_PARIDE is not set
524#
525# Block devices
526#
527# CONFIG_BLK_DEV_COW_COMMON is not set 619# CONFIG_BLK_DEV_COW_COMMON is not set
528CONFIG_BLK_DEV_LOOP=y 620CONFIG_BLK_DEV_LOOP=y
529# CONFIG_BLK_DEV_CRYPTOLOOP is not set 621# CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -532,34 +624,34 @@ CONFIG_BLK_DEV_NBD=m
532CONFIG_BLK_DEV_RAM=y 624CONFIG_BLK_DEV_RAM=y
533CONFIG_BLK_DEV_RAM_COUNT=16 625CONFIG_BLK_DEV_RAM_COUNT=16
534CONFIG_BLK_DEV_RAM_SIZE=4096 626CONFIG_BLK_DEV_RAM_SIZE=4096
535CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 627# CONFIG_BLK_DEV_XIP is not set
536# CONFIG_CDROM_PKTCDVD is not set 628# CONFIG_CDROM_PKTCDVD is not set
537CONFIG_ATA_OVER_ETH=m 629CONFIG_ATA_OVER_ETH=m
538 630CONFIG_MISC_DEVICES=y
539# 631# CONFIG_EEPROM_93CX6 is not set
540# ATA/ATAPI/MFM/RLL support 632# CONFIG_ENCLOSURE_SERVICES is not set
541# 633CONFIG_HAVE_IDE=y
542CONFIG_IDE=y 634CONFIG_IDE=y
543CONFIG_BLK_DEV_IDE=y 635CONFIG_BLK_DEV_IDE=y
544 636
545# 637#
546# Please see Documentation/ide.txt for help/info on IDE drives 638# Please see Documentation/ide/ide.txt for help/info on IDE drives
547# 639#
548# CONFIG_BLK_DEV_IDE_SATA is not set 640# CONFIG_BLK_DEV_IDE_SATA is not set
549CONFIG_BLK_DEV_IDEDISK=y 641CONFIG_BLK_DEV_IDEDISK=y
550# CONFIG_IDEDISK_MULTI_MODE is not set 642# CONFIG_IDEDISK_MULTI_MODE is not set
551CONFIG_BLK_DEV_IDECD=y 643CONFIG_BLK_DEV_IDECD=y
644CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y
552CONFIG_BLK_DEV_IDETAPE=m 645CONFIG_BLK_DEV_IDETAPE=m
553CONFIG_BLK_DEV_IDEFLOPPY=m 646CONFIG_BLK_DEV_IDEFLOPPY=m
647# CONFIG_BLK_DEV_IDESCSI is not set
554# CONFIG_IDE_TASK_IOCTL is not set 648# CONFIG_IDE_TASK_IOCTL is not set
649CONFIG_IDE_PROC_FS=y
555 650
556# 651#
557# IDE chipset support/bugfixes 652# IDE chipset support/bugfixes
558# 653#
559CONFIG_IDE_GENERIC=y 654# CONFIG_BLK_DEV_PLATFORM is not set
560# CONFIG_IDE_ARM is not set
561CONFIG_BLK_DEV_IDE_BAST=y
562# CONFIG_IDE_CHIPSETS is not set
563# CONFIG_BLK_DEV_IDEDMA is not set 655# CONFIG_BLK_DEV_IDEDMA is not set
564# CONFIG_BLK_DEV_HD is not set 656# CONFIG_BLK_DEV_HD is not set
565 657
@@ -567,101 +659,119 @@ CONFIG_BLK_DEV_IDE_BAST=y
567# SCSI device support 659# SCSI device support
568# 660#
569# CONFIG_RAID_ATTRS is not set 661# CONFIG_RAID_ATTRS is not set
570# CONFIG_SCSI is not set 662CONFIG_SCSI=y
663CONFIG_SCSI_DMA=y
664CONFIG_SCSI_TGT=m
571# CONFIG_SCSI_NETLINK is not set 665# CONFIG_SCSI_NETLINK is not set
572 666CONFIG_SCSI_PROC_FS=y
573# 667
574# Serial ATA (prod) and Parallel ATA (experimental) drivers 668#
575# 669# SCSI support type (disk, tape, CD-ROM)
670#
671CONFIG_BLK_DEV_SD=y
672CONFIG_CHR_DEV_ST=m
673# CONFIG_CHR_DEV_OSST is not set
674CONFIG_BLK_DEV_SR=m
675CONFIG_BLK_DEV_SR_VENDOR=y
676CONFIG_CHR_DEV_SG=y
677CONFIG_CHR_DEV_SCH=m
678
679#
680# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
681#
682CONFIG_SCSI_MULTI_LUN=y
683CONFIG_SCSI_CONSTANTS=y
684# CONFIG_SCSI_LOGGING is not set
685CONFIG_SCSI_SCAN_ASYNC=y
686CONFIG_SCSI_WAIT_SCAN=m
687
688#
689# SCSI Transports
690#
691# CONFIG_SCSI_SPI_ATTRS is not set
692# CONFIG_SCSI_FC_ATTRS is not set
693# CONFIG_SCSI_ISCSI_ATTRS is not set
694# CONFIG_SCSI_SAS_LIBSAS is not set
695# CONFIG_SCSI_SRP_ATTRS is not set
696CONFIG_SCSI_LOWLEVEL=y
697# CONFIG_ISCSI_TCP is not set
698# CONFIG_SCSI_AHA152X is not set
699# CONFIG_SCSI_AIC7XXX_OLD is not set
700# CONFIG_SCSI_ADVANSYS is not set
701# CONFIG_SCSI_IN2000 is not set
702# CONFIG_SCSI_DTC3280 is not set
703# CONFIG_SCSI_FUTURE_DOMAIN is not set
704# CONFIG_SCSI_GENERIC_NCR5380 is not set
705# CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set
706# CONFIG_SCSI_PPA is not set
707# CONFIG_SCSI_IMM is not set
708# CONFIG_SCSI_NCR53C406A is not set
709# CONFIG_SCSI_PAS16 is not set
710# CONFIG_SCSI_QLOGIC_FAS is not set
711# CONFIG_SCSI_SYM53C416 is not set
712# CONFIG_SCSI_T128 is not set
713# CONFIG_SCSI_DEBUG is not set
576# CONFIG_ATA is not set 714# CONFIG_ATA is not set
577 715CONFIG_HAVE_PATA_PLATFORM=y
578#
579# Multi-device support (RAID and LVM)
580#
581# CONFIG_MD is not set 716# CONFIG_MD is not set
582
583#
584# Fusion MPT device support
585#
586# CONFIG_FUSION is not set
587
588#
589# IEEE 1394 (FireWire) support
590#
591
592#
593# I2O device support
594#
595
596#
597# Network device support
598#
599CONFIG_NETDEVICES=y 717CONFIG_NETDEVICES=y
718# CONFIG_NETDEVICES_MULTIQUEUE is not set
600# CONFIG_DUMMY is not set 719# CONFIG_DUMMY is not set
601# CONFIG_BONDING is not set 720# CONFIG_BONDING is not set
721# CONFIG_MACVLAN is not set
602# CONFIG_EQUALIZER is not set 722# CONFIG_EQUALIZER is not set
603# CONFIG_TUN is not set 723# CONFIG_TUN is not set
604 724# CONFIG_VETH is not set
605#
606# ARCnet devices
607#
608# CONFIG_ARCNET is not set 725# CONFIG_ARCNET is not set
609
610#
611# PHY device support
612#
613# CONFIG_PHYLIB is not set 726# CONFIG_PHYLIB is not set
614
615#
616# Ethernet (10 or 100Mbit)
617#
618CONFIG_NET_ETHERNET=y 727CONFIG_NET_ETHERNET=y
619CONFIG_MII=y 728CONFIG_MII=y
729# CONFIG_AX88796 is not set
620# CONFIG_NET_VENDOR_3COM is not set 730# CONFIG_NET_VENDOR_3COM is not set
621# CONFIG_NET_VENDOR_SMC is not set 731# CONFIG_NET_VENDOR_SMC is not set
622# CONFIG_SMC91X is not set 732# CONFIG_SMC91X is not set
623CONFIG_DM9000=y 733CONFIG_DM9000=y
734# CONFIG_ENC28J60 is not set
735CONFIG_DM9000_DEBUGLEVEL=4
624# CONFIG_NET_VENDOR_RACAL is not set 736# CONFIG_NET_VENDOR_RACAL is not set
625# CONFIG_AT1700 is not set 737# CONFIG_AT1700 is not set
626# CONFIG_DEPCA is not set 738# CONFIG_DEPCA is not set
627# CONFIG_HP100 is not set 739# CONFIG_HP100 is not set
628# CONFIG_NET_ISA is not set 740# CONFIG_NET_ISA is not set
741# CONFIG_IBM_NEW_EMAC_ZMII is not set
742# CONFIG_IBM_NEW_EMAC_RGMII is not set
743# CONFIG_IBM_NEW_EMAC_TAH is not set
744# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
629# CONFIG_NET_PCI is not set 745# CONFIG_NET_PCI is not set
746# CONFIG_B44 is not set
630# CONFIG_NET_POCKET is not set 747# CONFIG_NET_POCKET is not set
631 748CONFIG_NETDEV_1000=y
632# 749# CONFIG_E1000E_ENABLED is not set
633# Ethernet (1000 Mbit) 750CONFIG_NETDEV_10000=y
634#
635
636#
637# Ethernet (10000 Mbit)
638#
639
640#
641# Token Ring devices
642#
643# CONFIG_TR is not set 751# CONFIG_TR is not set
644 752
645# 753#
646# Wireless LAN (non-hamradio) 754# Wireless LAN
647# 755#
648# CONFIG_NET_RADIO is not set 756# CONFIG_WLAN_PRE80211 is not set
757# CONFIG_WLAN_80211 is not set
758# CONFIG_IWLWIFI_LEDS is not set
649 759
650# 760#
651# Wan interfaces 761# USB Network Adapters
652# 762#
763# CONFIG_USB_CATC is not set
764# CONFIG_USB_KAWETH is not set
765# CONFIG_USB_PEGASUS is not set
766# CONFIG_USB_RTL8150 is not set
767# CONFIG_USB_USBNET is not set
653# CONFIG_WAN is not set 768# CONFIG_WAN is not set
654# CONFIG_PLIP is not set 769# CONFIG_PLIP is not set
655# CONFIG_PPP is not set 770# CONFIG_PPP is not set
656# CONFIG_SLIP is not set 771# CONFIG_SLIP is not set
657# CONFIG_SHAPER is not set
658# CONFIG_NETCONSOLE is not set 772# CONFIG_NETCONSOLE is not set
659# CONFIG_NETPOLL is not set 773# CONFIG_NETPOLL is not set
660# CONFIG_NET_POLL_CONTROLLER is not set 774# CONFIG_NET_POLL_CONTROLLER is not set
661
662#
663# ISDN subsystem
664#
665# CONFIG_ISDN is not set 775# CONFIG_ISDN is not set
666 776
667# 777#
@@ -669,6 +779,7 @@ CONFIG_DM9000=y
669# 779#
670CONFIG_INPUT=y 780CONFIG_INPUT=y
671# CONFIG_INPUT_FF_MEMLESS is not set 781# CONFIG_INPUT_FF_MEMLESS is not set
782# CONFIG_INPUT_POLLDEV is not set
672 783
673# 784#
674# Userland interfaces 785# Userland interfaces
@@ -678,7 +789,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y
678CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 789CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
679CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 790CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
680# CONFIG_INPUT_JOYDEV is not set 791# CONFIG_INPUT_JOYDEV is not set
681# CONFIG_INPUT_TSDEV is not set
682# CONFIG_INPUT_EVDEV is not set 792# CONFIG_INPUT_EVDEV is not set
683# CONFIG_INPUT_EVBUG is not set 793# CONFIG_INPUT_EVBUG is not set
684 794
@@ -695,12 +805,21 @@ CONFIG_KEYBOARD_ATKBD=y
695# CONFIG_KEYBOARD_GPIO is not set 805# CONFIG_KEYBOARD_GPIO is not set
696CONFIG_INPUT_MOUSE=y 806CONFIG_INPUT_MOUSE=y
697CONFIG_MOUSE_PS2=y 807CONFIG_MOUSE_PS2=y
808CONFIG_MOUSE_PS2_ALPS=y
809CONFIG_MOUSE_PS2_LOGIPS2PP=y
810CONFIG_MOUSE_PS2_SYNAPTICS=y
811CONFIG_MOUSE_PS2_LIFEBOOK=y
812CONFIG_MOUSE_PS2_TRACKPOINT=y
813# CONFIG_MOUSE_PS2_TOUCHKIT is not set
698# CONFIG_MOUSE_SERIAL is not set 814# CONFIG_MOUSE_SERIAL is not set
815# CONFIG_MOUSE_APPLETOUCH is not set
699# CONFIG_MOUSE_INPORT is not set 816# CONFIG_MOUSE_INPORT is not set
700# CONFIG_MOUSE_LOGIBM is not set 817# CONFIG_MOUSE_LOGIBM is not set
701# CONFIG_MOUSE_PC110PAD is not set 818# CONFIG_MOUSE_PC110PAD is not set
702# CONFIG_MOUSE_VSXXXAA is not set 819# CONFIG_MOUSE_VSXXXAA is not set
820# CONFIG_MOUSE_GPIO is not set
703# CONFIG_INPUT_JOYSTICK is not set 821# CONFIG_INPUT_JOYSTICK is not set
822# CONFIG_INPUT_TABLET is not set
704# CONFIG_INPUT_TOUCHSCREEN is not set 823# CONFIG_INPUT_TOUCHSCREEN is not set
705# CONFIG_INPUT_MISC is not set 824# CONFIG_INPUT_MISC is not set
706 825
@@ -721,6 +840,7 @@ CONFIG_VT=y
721CONFIG_VT_CONSOLE=y 840CONFIG_VT_CONSOLE=y
722CONFIG_HW_CONSOLE=y 841CONFIG_HW_CONSOLE=y
723# CONFIG_VT_HW_CONSOLE_BINDING is not set 842# CONFIG_VT_HW_CONSOLE_BINDING is not set
843CONFIG_DEVKMEM=y
724CONFIG_SERIAL_NONSTANDARD=y 844CONFIG_SERIAL_NONSTANDARD=y
725# CONFIG_COMPUTONE is not set 845# CONFIG_COMPUTONE is not set
726# CONFIG_ROCKETPORT is not set 846# CONFIG_ROCKETPORT is not set
@@ -728,8 +848,6 @@ CONFIG_SERIAL_NONSTANDARD=y
728# CONFIG_DIGIEPCA is not set 848# CONFIG_DIGIEPCA is not set
729# CONFIG_MOXA_INTELLIO is not set 849# CONFIG_MOXA_INTELLIO is not set
730# CONFIG_MOXA_SMARTIO is not set 850# CONFIG_MOXA_SMARTIO is not set
731# CONFIG_MOXA_SMARTIO_NEW is not set
732# CONFIG_SYNCLINKMP is not set
733# CONFIG_N_HDLC is not set 851# CONFIG_N_HDLC is not set
734# CONFIG_RISCOM8 is not set 852# CONFIG_RISCOM8 is not set
735# CONFIG_SPECIALIX is not set 853# CONFIG_SPECIALIX is not set
@@ -758,8 +876,12 @@ CONFIG_SERIAL_8250_SHARE_IRQ=y
758# 876#
759# Non-8250 serial port support 877# Non-8250 serial port support
760# 878#
879CONFIG_SERIAL_SAMSUNG=y
880# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
881CONFIG_SERIAL_SAMSUNG_CONSOLE=y
761CONFIG_SERIAL_S3C2410=y 882CONFIG_SERIAL_S3C2410=y
762CONFIG_SERIAL_S3C2410_CONSOLE=y 883CONFIG_SERIAL_S3C2412=y
884CONFIG_SERIAL_S3C2440=y
763CONFIG_SERIAL_CORE=y 885CONFIG_SERIAL_CORE=y
764CONFIG_SERIAL_CORE_CONSOLE=y 886CONFIG_SERIAL_CORE_CONSOLE=y
765CONFIG_UNIX98_PTYS=y 887CONFIG_UNIX98_PTYS=y
@@ -768,89 +890,50 @@ CONFIG_LEGACY_PTY_COUNT=256
768CONFIG_PRINTER=y 890CONFIG_PRINTER=y
769# CONFIG_LP_CONSOLE is not set 891# CONFIG_LP_CONSOLE is not set
770CONFIG_PPDEV=y 892CONFIG_PPDEV=y
771# CONFIG_TIPAR is not set
772
773#
774# IPMI
775#
776# CONFIG_IPMI_HANDLER is not set 893# CONFIG_IPMI_HANDLER is not set
777
778#
779# Watchdog Cards
780#
781CONFIG_WATCHDOG=y
782# CONFIG_WATCHDOG_NOWAYOUT is not set
783
784#
785# Watchdog Device Drivers
786#
787# CONFIG_SOFT_WATCHDOG is not set
788CONFIG_S3C2410_WATCHDOG=y
789
790#
791# ISA-based Watchdog Cards
792#
793# CONFIG_PCWATCHDOG is not set
794# CONFIG_MIXCOMWD is not set
795# CONFIG_WDT is not set
796
797#
798# USB-based Watchdog Cards
799#
800# CONFIG_USBPCWATCHDOG is not set
801CONFIG_HW_RANDOM=y 894CONFIG_HW_RANDOM=y
802# CONFIG_NVRAM is not set 895# CONFIG_NVRAM is not set
803# CONFIG_DTLK is not set 896# CONFIG_DTLK is not set
804# CONFIG_R3964 is not set 897# CONFIG_R3964 is not set
805# CONFIG_RAW_DRIVER is not set 898# CONFIG_RAW_DRIVER is not set
806
807#
808# TPM devices
809#
810# CONFIG_TCG_TPM is not set 899# CONFIG_TCG_TPM is not set
811 900CONFIG_DEVPORT=y
812#
813# I2C support
814#
815CONFIG_I2C=y 901CONFIG_I2C=y
902CONFIG_I2C_BOARDINFO=y
816CONFIG_I2C_CHARDEV=m 903CONFIG_I2C_CHARDEV=m
817 904CONFIG_I2C_ALGOBIT=y
818#
819# I2C Algorithms
820#
821CONFIG_I2C_ALGOBIT=m
822# CONFIG_I2C_ALGOPCF is not set
823# CONFIG_I2C_ALGOPCA is not set
824 905
825# 906#
826# I2C Hardware Bus support 907# I2C Hardware Bus support
827# 908#
828# CONFIG_I2C_ELEKTOR is not set 909# CONFIG_I2C_ELEKTOR is not set
910# CONFIG_I2C_GPIO is not set
829# CONFIG_I2C_OCORES is not set 911# CONFIG_I2C_OCORES is not set
830# CONFIG_I2C_PARPORT is not set 912# CONFIG_I2C_PARPORT is not set
831# CONFIG_I2C_PARPORT_LIGHT is not set 913# CONFIG_I2C_PARPORT_LIGHT is not set
832CONFIG_I2C_S3C2410=y 914CONFIG_I2C_S3C2410=y
915CONFIG_I2C_SIMTEC=y
916# CONFIG_I2C_TAOS_EVM is not set
833# CONFIG_I2C_STUB is not set 917# CONFIG_I2C_STUB is not set
918# CONFIG_I2C_TINY_USB is not set
834# CONFIG_I2C_PCA_ISA is not set 919# CONFIG_I2C_PCA_ISA is not set
920# CONFIG_I2C_PCA_PLATFORM is not set
835 921
836# 922#
837# Miscellaneous I2C Chip support 923# Miscellaneous I2C Chip support
838# 924#
839# CONFIG_SENSORS_DS1337 is not set 925# CONFIG_DS1682 is not set
840# CONFIG_SENSORS_DS1374 is not set
841CONFIG_SENSORS_EEPROM=m 926CONFIG_SENSORS_EEPROM=m
842# CONFIG_SENSORS_PCF8574 is not set 927# CONFIG_SENSORS_PCF8574 is not set
843# CONFIG_SENSORS_PCA9539 is not set 928# CONFIG_PCF8575 is not set
844# CONFIG_SENSORS_PCF8591 is not set 929# CONFIG_SENSORS_PCF8591 is not set
930# CONFIG_TPS65010 is not set
845# CONFIG_SENSORS_MAX6875 is not set 931# CONFIG_SENSORS_MAX6875 is not set
932# CONFIG_SENSORS_TSL2550 is not set
846# CONFIG_I2C_DEBUG_CORE is not set 933# CONFIG_I2C_DEBUG_CORE is not set
847# CONFIG_I2C_DEBUG_ALGO is not set 934# CONFIG_I2C_DEBUG_ALGO is not set
848# CONFIG_I2C_DEBUG_BUS is not set 935# CONFIG_I2C_DEBUG_BUS is not set
849# CONFIG_I2C_DEBUG_CHIP is not set 936# CONFIG_I2C_DEBUG_CHIP is not set
850
851#
852# SPI support
853#
854CONFIG_SPI=y 937CONFIG_SPI=y
855# CONFIG_SPI_DEBUG is not set 938# CONFIG_SPI_DEBUG is not set
856CONFIG_SPI_MASTER=y 939CONFIG_SPI_MASTER=y
@@ -860,6 +943,7 @@ CONFIG_SPI_MASTER=y
860# 943#
861CONFIG_SPI_BITBANG=m 944CONFIG_SPI_BITBANG=m
862# CONFIG_SPI_BUTTERFLY is not set 945# CONFIG_SPI_BUTTERFLY is not set
946# CONFIG_SPI_LM70_LLP is not set
863CONFIG_SPI_S3C24XX=m 947CONFIG_SPI_S3C24XX=m
864CONFIG_SPI_S3C24XX_GPIO=m 948CONFIG_SPI_S3C24XX_GPIO=m
865 949
@@ -867,30 +951,43 @@ CONFIG_SPI_S3C24XX_GPIO=m
867# SPI Protocol Masters 951# SPI Protocol Masters
868# 952#
869# CONFIG_SPI_AT25 is not set 953# CONFIG_SPI_AT25 is not set
954# CONFIG_SPI_SPIDEV is not set
955# CONFIG_SPI_TLE62X0 is not set
956CONFIG_HAVE_GPIO_LIB=y
870 957
871# 958#
872# Dallas's 1-wire bus 959# GPIO Support
873# 960#
874# CONFIG_W1 is not set 961# CONFIG_DEBUG_GPIO is not set
875 962
876# 963#
877# Hardware Monitoring support 964# I2C GPIO expanders:
965#
966# CONFIG_GPIO_PCA953X is not set
967# CONFIG_GPIO_PCF857X is not set
968
878# 969#
970# SPI GPIO expanders:
971#
972# CONFIG_GPIO_MCP23S08 is not set
973# CONFIG_W1 is not set
974# CONFIG_POWER_SUPPLY is not set
879CONFIG_HWMON=y 975CONFIG_HWMON=y
880CONFIG_HWMON_VID=m 976CONFIG_HWMON_VID=m
881# CONFIG_SENSORS_ABITUGURU is not set 977# CONFIG_SENSORS_AD7418 is not set
882# CONFIG_SENSORS_ADM1021 is not set 978# CONFIG_SENSORS_ADM1021 is not set
883# CONFIG_SENSORS_ADM1025 is not set 979# CONFIG_SENSORS_ADM1025 is not set
884# CONFIG_SENSORS_ADM1026 is not set 980# CONFIG_SENSORS_ADM1026 is not set
885# CONFIG_SENSORS_ADM1029 is not set 981# CONFIG_SENSORS_ADM1029 is not set
886# CONFIG_SENSORS_ADM1031 is not set 982# CONFIG_SENSORS_ADM1031 is not set
887# CONFIG_SENSORS_ADM9240 is not set 983# CONFIG_SENSORS_ADM9240 is not set
888# CONFIG_SENSORS_ASB100 is not set 984# CONFIG_SENSORS_ADT7470 is not set
985# CONFIG_SENSORS_ADT7473 is not set
889# CONFIG_SENSORS_ATXP1 is not set 986# CONFIG_SENSORS_ATXP1 is not set
890# CONFIG_SENSORS_DS1621 is not set 987# CONFIG_SENSORS_DS1621 is not set
891# CONFIG_SENSORS_F71805F is not set 988# CONFIG_SENSORS_F71805F is not set
892# CONFIG_SENSORS_FSCHER is not set 989# CONFIG_SENSORS_F71882FG is not set
893# CONFIG_SENSORS_FSCPOS is not set 990# CONFIG_SENSORS_F75375S is not set
894# CONFIG_SENSORS_GL518SM is not set 991# CONFIG_SENSORS_GL518SM is not set
895# CONFIG_SENSORS_GL520SM is not set 992# CONFIG_SENSORS_GL520SM is not set
896# CONFIG_SENSORS_IT87 is not set 993# CONFIG_SENSORS_IT87 is not set
@@ -905,72 +1002,95 @@ CONFIG_SENSORS_LM85=m
905# CONFIG_SENSORS_LM87 is not set 1002# CONFIG_SENSORS_LM87 is not set
906# CONFIG_SENSORS_LM90 is not set 1003# CONFIG_SENSORS_LM90 is not set
907# CONFIG_SENSORS_LM92 is not set 1004# CONFIG_SENSORS_LM92 is not set
1005# CONFIG_SENSORS_LM93 is not set
908# CONFIG_SENSORS_MAX1619 is not set 1006# CONFIG_SENSORS_MAX1619 is not set
1007# CONFIG_SENSORS_MAX6650 is not set
909# CONFIG_SENSORS_PC87360 is not set 1008# CONFIG_SENSORS_PC87360 is not set
910# CONFIG_SENSORS_PC87427 is not set 1009# CONFIG_SENSORS_PC87427 is not set
1010# CONFIG_SENSORS_DME1737 is not set
911# CONFIG_SENSORS_SMSC47M1 is not set 1011# CONFIG_SENSORS_SMSC47M1 is not set
912# CONFIG_SENSORS_SMSC47M192 is not set 1012# CONFIG_SENSORS_SMSC47M192 is not set
913# CONFIG_SENSORS_SMSC47B397 is not set 1013# CONFIG_SENSORS_SMSC47B397 is not set
1014# CONFIG_SENSORS_ADS7828 is not set
1015# CONFIG_SENSORS_THMC50 is not set
914# CONFIG_SENSORS_VT1211 is not set 1016# CONFIG_SENSORS_VT1211 is not set
915# CONFIG_SENSORS_W83781D is not set 1017# CONFIG_SENSORS_W83781D is not set
916# CONFIG_SENSORS_W83791D is not set 1018# CONFIG_SENSORS_W83791D is not set
917# CONFIG_SENSORS_W83792D is not set 1019# CONFIG_SENSORS_W83792D is not set
918# CONFIG_SENSORS_W83793 is not set 1020# CONFIG_SENSORS_W83793 is not set
919# CONFIG_SENSORS_W83L785TS is not set 1021# CONFIG_SENSORS_W83L785TS is not set
1022# CONFIG_SENSORS_W83L786NG is not set
920# CONFIG_SENSORS_W83627HF is not set 1023# CONFIG_SENSORS_W83627HF is not set
921# CONFIG_SENSORS_W83627EHF is not set 1024# CONFIG_SENSORS_W83627EHF is not set
922# CONFIG_HWMON_DEBUG_CHIP is not set 1025# CONFIG_HWMON_DEBUG_CHIP is not set
1026CONFIG_WATCHDOG=y
1027# CONFIG_WATCHDOG_NOWAYOUT is not set
923 1028
924# 1029#
925# Misc devices 1030# Watchdog Device Drivers
926# 1031#
1032# CONFIG_SOFT_WATCHDOG is not set
1033CONFIG_S3C2410_WATCHDOG=y
927 1034
928# 1035#
929# Multifunction device drivers 1036# ISA-based Watchdog Cards
930# 1037#
931# CONFIG_MFD_SM501 is not set 1038# CONFIG_PCWATCHDOG is not set
1039# CONFIG_MIXCOMWD is not set
1040# CONFIG_WDT is not set
932 1041
933# 1042#
934# LED devices 1043# USB-based Watchdog Cards
935# 1044#
936CONFIG_NEW_LEDS=y 1045# CONFIG_USBPCWATCHDOG is not set
937CONFIG_LEDS_CLASS=m
938 1046
939# 1047#
940# LED drivers 1048# Sonics Silicon Backplane
941# 1049#
942CONFIG_LEDS_S3C24XX=m 1050CONFIG_SSB_POSSIBLE=y
943CONFIG_LEDS_H1940=m 1051# CONFIG_SSB is not set
944 1052
945# 1053#
946# LED Triggers 1054# Multifunction device drivers
947# 1055#
948CONFIG_LEDS_TRIGGERS=y 1056CONFIG_MFD_SM501=y
949CONFIG_LEDS_TRIGGER_TIMER=m 1057# CONFIG_MFD_ASIC3 is not set
950# CONFIG_LEDS_TRIGGER_IDE_DISK is not set 1058# CONFIG_HTC_EGPIO is not set
951CONFIG_LEDS_TRIGGER_HEARTBEAT=m 1059# CONFIG_HTC_PASIC3 is not set
952 1060
953# 1061#
954# Multimedia devices 1062# Multimedia devices
955# 1063#
1064
1065#
1066# Multimedia core support
1067#
956# CONFIG_VIDEO_DEV is not set 1068# CONFIG_VIDEO_DEV is not set
1069# CONFIG_DVB_CORE is not set
1070# CONFIG_VIDEO_MEDIA is not set
957 1071
958# 1072#
959# Digital Video Broadcasting Devices 1073# Multimedia drivers
960# 1074#
961# CONFIG_DVB is not set 1075# CONFIG_DAB is not set
962# CONFIG_USB_DABUSB is not set
963 1076
964# 1077#
965# Graphics support 1078# Graphics support
966# 1079#
967# CONFIG_BACKLIGHT_LCD_SUPPORT is not set 1080# CONFIG_VGASTATE is not set
1081# CONFIG_VIDEO_OUTPUT_CONTROL is not set
968CONFIG_FB=y 1082CONFIG_FB=y
969CONFIG_FIRMWARE_EDID=y 1083CONFIG_FIRMWARE_EDID=y
970# CONFIG_FB_DDC is not set 1084# CONFIG_FB_DDC is not set
971CONFIG_FB_CFB_FILLRECT=y 1085CONFIG_FB_CFB_FILLRECT=y
972CONFIG_FB_CFB_COPYAREA=y 1086CONFIG_FB_CFB_COPYAREA=y
973CONFIG_FB_CFB_IMAGEBLIT=y 1087CONFIG_FB_CFB_IMAGEBLIT=y
1088# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
1089# CONFIG_FB_SYS_FILLRECT is not set
1090# CONFIG_FB_SYS_COPYAREA is not set
1091# CONFIG_FB_SYS_IMAGEBLIT is not set
1092# CONFIG_FB_FOREIGN_ENDIAN is not set
1093# CONFIG_FB_SYS_FOPS is not set
974# CONFIG_FB_SVGALIB is not set 1094# CONFIG_FB_SVGALIB is not set
975# CONFIG_FB_MACMODES is not set 1095# CONFIG_FB_MACMODES is not set
976# CONFIG_FB_BACKLIGHT is not set 1096# CONFIG_FB_BACKLIGHT is not set
@@ -978,12 +1098,19 @@ CONFIG_FB_MODE_HELPERS=y
978# CONFIG_FB_TILEBLITTING is not set 1098# CONFIG_FB_TILEBLITTING is not set
979 1099
980# 1100#
981# Frambuffer hardware drivers 1101# Frame buffer hardware drivers
982# 1102#
983# CONFIG_FB_S1D13XXX is not set 1103# CONFIG_FB_S1D13XXX is not set
984CONFIG_FB_S3C2410=y 1104CONFIG_FB_S3C2410=y
985# CONFIG_FB_S3C2410_DEBUG is not set 1105# CONFIG_FB_S3C2410_DEBUG is not set
1106CONFIG_FB_SM501=y
986# CONFIG_FB_VIRTUAL is not set 1107# CONFIG_FB_VIRTUAL is not set
1108# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
1109
1110#
1111# Display device support
1112#
1113# CONFIG_DISPLAY_SUPPORT is not set
987 1114
988# 1115#
989# Console display driver support 1116# Console display driver support
@@ -992,40 +1119,45 @@ CONFIG_FB_S3C2410=y
992# CONFIG_MDA_CONSOLE is not set 1119# CONFIG_MDA_CONSOLE is not set
993CONFIG_DUMMY_CONSOLE=y 1120CONFIG_DUMMY_CONSOLE=y
994CONFIG_FRAMEBUFFER_CONSOLE=y 1121CONFIG_FRAMEBUFFER_CONSOLE=y
1122# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set
995# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set 1123# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
996# CONFIG_FONTS is not set 1124# CONFIG_FONTS is not set
997CONFIG_FONT_8x8=y 1125CONFIG_FONT_8x8=y
998CONFIG_FONT_8x16=y 1126CONFIG_FONT_8x16=y
999
1000#
1001# Logo configuration
1002#
1003# CONFIG_LOGO is not set 1127# CONFIG_LOGO is not set
1004 1128
1005# 1129#
1006# Sound 1130# Sound
1007# 1131#
1008# CONFIG_SOUND is not set 1132# CONFIG_SOUND is not set
1133CONFIG_HID_SUPPORT=y
1134CONFIG_HID=y
1135# CONFIG_HID_DEBUG is not set
1136# CONFIG_HIDRAW is not set
1009 1137
1010# 1138#
1011# HID Devices 1139# USB Input Devices
1012# 1140#
1013CONFIG_HID=y 1141# CONFIG_USB_HID is not set
1014# CONFIG_HID_DEBUG is not set
1015 1142
1016# 1143#
1017# USB support 1144# USB HID Boot Protocol drivers
1018# 1145#
1146# CONFIG_USB_KBD is not set
1147# CONFIG_USB_MOUSE is not set
1148CONFIG_USB_SUPPORT=y
1019CONFIG_USB_ARCH_HAS_HCD=y 1149CONFIG_USB_ARCH_HAS_HCD=y
1020CONFIG_USB_ARCH_HAS_OHCI=y 1150CONFIG_USB_ARCH_HAS_OHCI=y
1021# CONFIG_USB_ARCH_HAS_EHCI is not set 1151# CONFIG_USB_ARCH_HAS_EHCI is not set
1022CONFIG_USB=y 1152CONFIG_USB=y
1023# CONFIG_USB_DEBUG is not set 1153# CONFIG_USB_DEBUG is not set
1154# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
1024 1155
1025# 1156#
1026# Miscellaneous USB options 1157# Miscellaneous USB options
1027# 1158#
1028CONFIG_USB_DEVICEFS=y 1159CONFIG_USB_DEVICEFS=y
1160CONFIG_USB_DEVICE_CLASS=y
1029# CONFIG_USB_DYNAMIC_MINORS is not set 1161# CONFIG_USB_DYNAMIC_MINORS is not set
1030# CONFIG_USB_SUSPEND is not set 1162# CONFIG_USB_SUSPEND is not set
1031# CONFIG_USB_OTG is not set 1163# CONFIG_USB_OTG is not set
@@ -1033,18 +1165,22 @@ CONFIG_USB_DEVICEFS=y
1033# 1165#
1034# USB Host Controller Drivers 1166# USB Host Controller Drivers
1035# 1167#
1168# CONFIG_USB_C67X00_HCD is not set
1036# CONFIG_USB_ISP116X_HCD is not set 1169# CONFIG_USB_ISP116X_HCD is not set
1170# CONFIG_USB_ISP1760_HCD is not set
1037CONFIG_USB_OHCI_HCD=y 1171CONFIG_USB_OHCI_HCD=y
1038# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set 1172# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
1039# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set 1173# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
1040CONFIG_USB_OHCI_LITTLE_ENDIAN=y 1174CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1041# CONFIG_USB_SL811_HCD is not set 1175# CONFIG_USB_SL811_HCD is not set
1176# CONFIG_USB_R8A66597_HCD is not set
1042 1177
1043# 1178#
1044# USB Device Class drivers 1179# USB Device Class drivers
1045# 1180#
1046# CONFIG_USB_ACM is not set 1181CONFIG_USB_ACM=m
1047# CONFIG_USB_PRINTER is not set 1182CONFIG_USB_PRINTER=m
1183CONFIG_USB_WDM=m
1048 1184
1049# 1185#
1050# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' 1186# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
@@ -1053,57 +1189,78 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
1053# 1189#
1054# may also be needed; see USB_STORAGE Help for more information 1190# may also be needed; see USB_STORAGE Help for more information
1055# 1191#
1056# CONFIG_USB_LIBUSUAL is not set 1192CONFIG_USB_STORAGE=m
1057 1193# CONFIG_USB_STORAGE_DEBUG is not set
1058# 1194# CONFIG_USB_STORAGE_DATAFAB is not set
1059# USB Input Devices 1195# CONFIG_USB_STORAGE_FREECOM is not set
1060# 1196# CONFIG_USB_STORAGE_ISD200 is not set
1061# CONFIG_USB_HID is not set 1197# CONFIG_USB_STORAGE_DPCM is not set
1062 1198# CONFIG_USB_STORAGE_USBAT is not set
1063# 1199# CONFIG_USB_STORAGE_SDDR09 is not set
1064# USB HID Boot Protocol drivers 1200# CONFIG_USB_STORAGE_SDDR55 is not set
1065# 1201# CONFIG_USB_STORAGE_JUMPSHOT is not set
1066# CONFIG_USB_KBD is not set 1202# CONFIG_USB_STORAGE_ALAUDA is not set
1067# CONFIG_USB_MOUSE is not set 1203# CONFIG_USB_STORAGE_ONETOUCH is not set
1068# CONFIG_USB_AIPTEK is not set 1204# CONFIG_USB_STORAGE_KARMA is not set
1069# CONFIG_USB_WACOM is not set 1205# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
1070# CONFIG_USB_ACECAD is not set 1206CONFIG_USB_LIBUSUAL=y
1071# CONFIG_USB_KBTAB is not set
1072# CONFIG_USB_POWERMATE is not set
1073# CONFIG_USB_TOUCHSCREEN is not set
1074# CONFIG_USB_YEALINK is not set
1075# CONFIG_USB_XPAD is not set
1076# CONFIG_USB_ATI_REMOTE is not set
1077# CONFIG_USB_ATI_REMOTE2 is not set
1078# CONFIG_USB_KEYSPAN_REMOTE is not set
1079# CONFIG_USB_APPLETOUCH is not set
1080# CONFIG_USB_GTCO is not set
1081 1207
1082# 1208#
1083# USB Imaging devices 1209# USB Imaging devices
1084# 1210#
1085# CONFIG_USB_MDC800 is not set 1211# CONFIG_USB_MDC800 is not set
1086 1212# CONFIG_USB_MICROTEK is not set
1087#
1088# USB Network Adapters
1089#
1090# CONFIG_USB_CATC is not set
1091# CONFIG_USB_KAWETH is not set
1092# CONFIG_USB_PEGASUS is not set
1093# CONFIG_USB_RTL8150 is not set
1094# CONFIG_USB_USBNET_MII is not set
1095# CONFIG_USB_USBNET is not set
1096CONFIG_USB_MON=y 1213CONFIG_USB_MON=y
1097 1214
1098# 1215#
1099# USB port drivers 1216# USB port drivers
1100# 1217#
1101# CONFIG_USB_USS720 is not set 1218# CONFIG_USB_USS720 is not set
1102 1219CONFIG_USB_SERIAL=y
1103# 1220# CONFIG_USB_SERIAL_CONSOLE is not set
1104# USB Serial Converter support 1221# CONFIG_USB_EZUSB is not set
1105# 1222CONFIG_USB_SERIAL_GENERIC=y
1106# CONFIG_USB_SERIAL is not set 1223# CONFIG_USB_SERIAL_AIRCABLE is not set
1224# CONFIG_USB_SERIAL_AIRPRIME is not set
1225# CONFIG_USB_SERIAL_ARK3116 is not set
1226# CONFIG_USB_SERIAL_BELKIN is not set
1227# CONFIG_USB_SERIAL_CH341 is not set
1228# CONFIG_USB_SERIAL_WHITEHEAT is not set
1229# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
1230# CONFIG_USB_SERIAL_CP2101 is not set
1231# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
1232# CONFIG_USB_SERIAL_EMPEG is not set
1233CONFIG_USB_SERIAL_FTDI_SIO=y
1234# CONFIG_USB_SERIAL_FUNSOFT is not set
1235# CONFIG_USB_SERIAL_VISOR is not set
1236# CONFIG_USB_SERIAL_IPAQ is not set
1237# CONFIG_USB_SERIAL_IR is not set
1238# CONFIG_USB_SERIAL_EDGEPORT is not set
1239# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
1240# CONFIG_USB_SERIAL_GARMIN is not set
1241# CONFIG_USB_SERIAL_IPW is not set
1242# CONFIG_USB_SERIAL_IUU is not set
1243# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
1244# CONFIG_USB_SERIAL_KEYSPAN is not set
1245# CONFIG_USB_SERIAL_KLSI is not set
1246# CONFIG_USB_SERIAL_KOBIL_SCT is not set
1247# CONFIG_USB_SERIAL_MCT_U232 is not set
1248# CONFIG_USB_SERIAL_MOS7720 is not set
1249# CONFIG_USB_SERIAL_MOS7840 is not set
1250# CONFIG_USB_SERIAL_MOTOROLA is not set
1251CONFIG_USB_SERIAL_NAVMAN=m
1252CONFIG_USB_SERIAL_PL2303=y
1253# CONFIG_USB_SERIAL_OTI6858 is not set
1254# CONFIG_USB_SERIAL_SPCP8X5 is not set
1255# CONFIG_USB_SERIAL_HP4X is not set
1256# CONFIG_USB_SERIAL_SAFE is not set
1257# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
1258# CONFIG_USB_SERIAL_TI is not set
1259# CONFIG_USB_SERIAL_CYBERJACK is not set
1260# CONFIG_USB_SERIAL_XIRCOM is not set
1261CONFIG_USB_SERIAL_OPTION=m
1262# CONFIG_USB_SERIAL_OMNINET is not set
1263# CONFIG_USB_SERIAL_DEBUG is not set
1107 1264
1108# 1265#
1109# USB Miscellaneous drivers 1266# USB Miscellaneous drivers
@@ -1116,35 +1273,38 @@ CONFIG_USB_MON=y
1116# CONFIG_USB_LEGOTOWER is not set 1273# CONFIG_USB_LEGOTOWER is not set
1117# CONFIG_USB_LCD is not set 1274# CONFIG_USB_LCD is not set
1118# CONFIG_USB_BERRY_CHARGE is not set 1275# CONFIG_USB_BERRY_CHARGE is not set
1119# CONFIG_USB_LED is not set 1276CONFIG_USB_LED=m
1120# CONFIG_USB_CYPRESS_CY7C63 is not set 1277# CONFIG_USB_CYPRESS_CY7C63 is not set
1121# CONFIG_USB_CYTHERM is not set 1278# CONFIG_USB_CYTHERM is not set
1122# CONFIG_USB_PHIDGET is not set 1279# CONFIG_USB_PHIDGET is not set
1123# CONFIG_USB_IDMOUSE is not set 1280# CONFIG_USB_IDMOUSE is not set
1124# CONFIG_USB_FTDI_ELAN is not set 1281# CONFIG_USB_FTDI_ELAN is not set
1125# CONFIG_USB_APPLEDISPLAY is not set 1282# CONFIG_USB_APPLEDISPLAY is not set
1126# CONFIG_USB_LD is not set 1283CONFIG_USB_LD=m
1127# CONFIG_USB_TRANCEVIBRATOR is not set 1284# CONFIG_USB_TRANCEVIBRATOR is not set
1128# CONFIG_USB_IOWARRIOR is not set 1285# CONFIG_USB_IOWARRIOR is not set
1129# CONFIG_USB_TEST is not set 1286# CONFIG_USB_TEST is not set
1130 1287# CONFIG_USB_ISIGHTFW is not set
1131#
1132# USB DSL modem support
1133#
1134
1135#
1136# USB Gadget Support
1137#
1138# CONFIG_USB_GADGET is not set 1288# CONFIG_USB_GADGET is not set
1289# CONFIG_MMC is not set
1290CONFIG_NEW_LEDS=y
1291CONFIG_LEDS_CLASS=m
1139 1292
1140# 1293#
1141# MMC/SD Card support 1294# LED drivers
1142# 1295#
1143# CONFIG_MMC is not set 1296CONFIG_LEDS_S3C24XX=m
1297CONFIG_LEDS_H1940=m
1298# CONFIG_LEDS_GPIO is not set
1144 1299
1145# 1300#
1146# Real Time Clock 1301# LED Triggers
1147# 1302#
1303CONFIG_LEDS_TRIGGERS=y
1304CONFIG_LEDS_TRIGGER_TIMER=m
1305# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
1306CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1307# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set
1148CONFIG_RTC_LIB=y 1308CONFIG_RTC_LIB=y
1149CONFIG_RTC_CLASS=y 1309CONFIG_RTC_CLASS=y
1150CONFIG_RTC_HCTOSYS=y 1310CONFIG_RTC_HCTOSYS=y
@@ -1158,61 +1318,86 @@ CONFIG_RTC_INTF_SYSFS=y
1158CONFIG_RTC_INTF_PROC=y 1318CONFIG_RTC_INTF_PROC=y
1159CONFIG_RTC_INTF_DEV=y 1319CONFIG_RTC_INTF_DEV=y
1160# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set 1320# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
1321# CONFIG_RTC_DRV_TEST is not set
1161 1322
1162# 1323#
1163# RTC drivers 1324# I2C RTC drivers
1164# 1325#
1165# CONFIG_RTC_DRV_CMOS is not set
1166# CONFIG_RTC_DRV_X1205 is not set
1167# CONFIG_RTC_DRV_DS1307 is not set 1326# CONFIG_RTC_DRV_DS1307 is not set
1168# CONFIG_RTC_DRV_DS1553 is not set 1327# CONFIG_RTC_DRV_DS1374 is not set
1169# CONFIG_RTC_DRV_ISL1208 is not set
1170# CONFIG_RTC_DRV_DS1672 is not set 1328# CONFIG_RTC_DRV_DS1672 is not set
1171# CONFIG_RTC_DRV_DS1742 is not set 1329# CONFIG_RTC_DRV_MAX6900 is not set
1330# CONFIG_RTC_DRV_RS5C372 is not set
1331# CONFIG_RTC_DRV_ISL1208 is not set
1332# CONFIG_RTC_DRV_X1205 is not set
1172# CONFIG_RTC_DRV_PCF8563 is not set 1333# CONFIG_RTC_DRV_PCF8563 is not set
1334# CONFIG_RTC_DRV_PCF8583 is not set
1335# CONFIG_RTC_DRV_M41T80 is not set
1336# CONFIG_RTC_DRV_S35390A is not set
1337# CONFIG_RTC_DRV_FM3130 is not set
1338
1339#
1340# SPI RTC drivers
1341#
1342# CONFIG_RTC_DRV_MAX6902 is not set
1343# CONFIG_RTC_DRV_R9701 is not set
1173# CONFIG_RTC_DRV_RS5C348 is not set 1344# CONFIG_RTC_DRV_RS5C348 is not set
1174# CONFIG_RTC_DRV_RS5C372 is not set 1345
1175CONFIG_RTC_DRV_S3C=y 1346#
1347# Platform RTC drivers
1348#
1349# CONFIG_RTC_DRV_CMOS is not set
1350# CONFIG_RTC_DRV_DS1511 is not set
1351# CONFIG_RTC_DRV_DS1553 is not set
1352# CONFIG_RTC_DRV_DS1742 is not set
1353# CONFIG_RTC_DRV_STK17TA8 is not set
1176# CONFIG_RTC_DRV_M48T86 is not set 1354# CONFIG_RTC_DRV_M48T86 is not set
1177# CONFIG_RTC_DRV_TEST is not set 1355# CONFIG_RTC_DRV_M48T59 is not set
1178# CONFIG_RTC_DRV_MAX6902 is not set
1179# CONFIG_RTC_DRV_V3020 is not set 1356# CONFIG_RTC_DRV_V3020 is not set
1180 1357
1181# 1358#
1359# on-CPU RTC drivers
1360#
1361CONFIG_RTC_DRV_S3C=y
1362# CONFIG_UIO is not set
1363
1364#
1182# File systems 1365# File systems
1183# 1366#
1184CONFIG_EXT2_FS=y 1367CONFIG_EXT2_FS=y
1185# CONFIG_EXT2_FS_XATTR is not set 1368CONFIG_EXT2_FS_XATTR=y
1369CONFIG_EXT2_FS_POSIX_ACL=y
1370CONFIG_EXT2_FS_SECURITY=y
1186# CONFIG_EXT2_FS_XIP is not set 1371# CONFIG_EXT2_FS_XIP is not set
1187CONFIG_EXT3_FS=y 1372CONFIG_EXT3_FS=y
1188CONFIG_EXT3_FS_XATTR=y 1373CONFIG_EXT3_FS_XATTR=y
1189# CONFIG_EXT3_FS_POSIX_ACL is not set 1374CONFIG_EXT3_FS_POSIX_ACL=y
1190# CONFIG_EXT3_FS_SECURITY is not set 1375# CONFIG_EXT3_FS_SECURITY is not set
1191# CONFIG_EXT4DEV_FS is not set 1376# CONFIG_EXT4DEV_FS is not set
1192CONFIG_JBD=y 1377CONFIG_JBD=y
1193# CONFIG_JBD_DEBUG is not set
1194CONFIG_FS_MBCACHE=y 1378CONFIG_FS_MBCACHE=y
1195# CONFIG_REISERFS_FS is not set 1379# CONFIG_REISERFS_FS is not set
1196# CONFIG_JFS_FS is not set 1380# CONFIG_JFS_FS is not set
1197# CONFIG_FS_POSIX_ACL is not set 1381CONFIG_FS_POSIX_ACL=y
1198# CONFIG_XFS_FS is not set 1382# CONFIG_XFS_FS is not set
1199# CONFIG_GFS2_FS is not set
1200# CONFIG_OCFS2_FS is not set 1383# CONFIG_OCFS2_FS is not set
1201# CONFIG_MINIX_FS is not set 1384CONFIG_DNOTIFY=y
1202CONFIG_ROMFS_FS=y
1203CONFIG_INOTIFY=y 1385CONFIG_INOTIFY=y
1204CONFIG_INOTIFY_USER=y 1386CONFIG_INOTIFY_USER=y
1205# CONFIG_QUOTA is not set 1387# CONFIG_QUOTA is not set
1206CONFIG_DNOTIFY=y
1207# CONFIG_AUTOFS_FS is not set 1388# CONFIG_AUTOFS_FS is not set
1208# CONFIG_AUTOFS4_FS is not set 1389# CONFIG_AUTOFS4_FS is not set
1209# CONFIG_FUSE_FS is not set 1390# CONFIG_FUSE_FS is not set
1391CONFIG_GENERIC_ACL=y
1210 1392
1211# 1393#
1212# CD-ROM/DVD Filesystems 1394# CD-ROM/DVD Filesystems
1213# 1395#
1214# CONFIG_ISO9660_FS is not set 1396CONFIG_ISO9660_FS=y
1215# CONFIG_UDF_FS is not set 1397CONFIG_JOLIET=y
1398# CONFIG_ZISOFS is not set
1399CONFIG_UDF_FS=m
1400CONFIG_UDF_NLS=y
1216 1401
1217# 1402#
1218# DOS/FAT/NT Filesystems 1403# DOS/FAT/NT Filesystems
@@ -1222,7 +1407,9 @@ CONFIG_MSDOS_FS=y
1222CONFIG_VFAT_FS=y 1407CONFIG_VFAT_FS=y
1223CONFIG_FAT_DEFAULT_CODEPAGE=437 1408CONFIG_FAT_DEFAULT_CODEPAGE=437
1224CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" 1409CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1225# CONFIG_NTFS_FS is not set 1410CONFIG_NTFS_FS=m
1411# CONFIG_NTFS_DEBUG is not set
1412# CONFIG_NTFS_RW is not set
1226 1413
1227# 1414#
1228# Pseudo filesystems 1415# Pseudo filesystems
@@ -1230,10 +1417,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1230CONFIG_PROC_FS=y 1417CONFIG_PROC_FS=y
1231CONFIG_PROC_SYSCTL=y 1418CONFIG_PROC_SYSCTL=y
1232CONFIG_SYSFS=y 1419CONFIG_SYSFS=y
1233# CONFIG_TMPFS is not set 1420CONFIG_TMPFS=y
1421CONFIG_TMPFS_POSIX_ACL=y
1234# CONFIG_HUGETLB_PAGE is not set 1422# CONFIG_HUGETLB_PAGE is not set
1235CONFIG_RAMFS=y 1423CONFIG_CONFIGFS_FS=m
1236# CONFIG_CONFIGFS_FS is not set
1237 1424
1238# 1425#
1239# Miscellaneous filesystems 1426# Miscellaneous filesystems
@@ -1248,31 +1435,32 @@ CONFIG_RAMFS=y
1248CONFIG_JFFS2_FS=y 1435CONFIG_JFFS2_FS=y
1249CONFIG_JFFS2_FS_DEBUG=0 1436CONFIG_JFFS2_FS_DEBUG=0
1250CONFIG_JFFS2_FS_WRITEBUFFER=y 1437CONFIG_JFFS2_FS_WRITEBUFFER=y
1251# CONFIG_JFFS2_SUMMARY is not set 1438# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
1439CONFIG_JFFS2_SUMMARY=y
1252# CONFIG_JFFS2_FS_XATTR is not set 1440# CONFIG_JFFS2_FS_XATTR is not set
1253# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 1441# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1254CONFIG_JFFS2_ZLIB=y 1442CONFIG_JFFS2_ZLIB=y
1443# CONFIG_JFFS2_LZO is not set
1255CONFIG_JFFS2_RTIME=y 1444CONFIG_JFFS2_RTIME=y
1256# CONFIG_JFFS2_RUBIN is not set 1445# CONFIG_JFFS2_RUBIN is not set
1257CONFIG_CRAMFS=y 1446CONFIG_CRAMFS=y
1258# CONFIG_VXFS_FS is not set 1447# CONFIG_VXFS_FS is not set
1448# CONFIG_MINIX_FS is not set
1259# CONFIG_HPFS_FS is not set 1449# CONFIG_HPFS_FS is not set
1260# CONFIG_QNX4FS_FS is not set 1450# CONFIG_QNX4FS_FS is not set
1451CONFIG_ROMFS_FS=y
1261# CONFIG_SYSV_FS is not set 1452# CONFIG_SYSV_FS is not set
1262# CONFIG_UFS_FS is not set 1453# CONFIG_UFS_FS is not set
1263 1454CONFIG_NETWORK_FILESYSTEMS=y
1264#
1265# Network File Systems
1266#
1267CONFIG_NFS_FS=y 1455CONFIG_NFS_FS=y
1268# CONFIG_NFS_V3 is not set 1456# CONFIG_NFS_V3 is not set
1269# CONFIG_NFS_V4 is not set 1457# CONFIG_NFS_V4 is not set
1270# CONFIG_NFS_DIRECTIO is not set
1271# CONFIG_NFSD is not set 1458# CONFIG_NFSD is not set
1272CONFIG_ROOT_NFS=y 1459CONFIG_ROOT_NFS=y
1273CONFIG_LOCKD=y 1460CONFIG_LOCKD=y
1274CONFIG_NFS_COMMON=y 1461CONFIG_NFS_COMMON=y
1275CONFIG_SUNRPC=y 1462CONFIG_SUNRPC=y
1463# CONFIG_SUNRPC_BIND34 is not set
1276# CONFIG_RPCSEC_GSS_KRB5 is not set 1464# CONFIG_RPCSEC_GSS_KRB5 is not set
1277# CONFIG_RPCSEC_GSS_SPKM3 is not set 1465# CONFIG_RPCSEC_GSS_SPKM3 is not set
1278# CONFIG_SMB_FS is not set 1466# CONFIG_SMB_FS is not set
@@ -1280,7 +1468,6 @@ CONFIG_SUNRPC=y
1280# CONFIG_NCP_FS is not set 1468# CONFIG_NCP_FS is not set
1281# CONFIG_CODA_FS is not set 1469# CONFIG_CODA_FS is not set
1282# CONFIG_AFS_FS is not set 1470# CONFIG_AFS_FS is not set
1283# CONFIG_9P_FS is not set
1284 1471
1285# 1472#
1286# Partition Types 1473# Partition Types
@@ -1302,94 +1489,93 @@ CONFIG_SOLARIS_X86_PARTITION=y
1302# CONFIG_SUN_PARTITION is not set 1489# CONFIG_SUN_PARTITION is not set
1303# CONFIG_KARMA_PARTITION is not set 1490# CONFIG_KARMA_PARTITION is not set
1304# CONFIG_EFI_PARTITION is not set 1491# CONFIG_EFI_PARTITION is not set
1305 1492# CONFIG_SYSV68_PARTITION is not set
1306#
1307# Native Language Support
1308#
1309CONFIG_NLS=y 1493CONFIG_NLS=y
1310CONFIG_NLS_DEFAULT="iso8859-1" 1494CONFIG_NLS_DEFAULT="iso8859-1"
1311# CONFIG_NLS_CODEPAGE_437 is not set 1495CONFIG_NLS_CODEPAGE_437=y
1312# CONFIG_NLS_CODEPAGE_737 is not set 1496CONFIG_NLS_CODEPAGE_737=m
1313# CONFIG_NLS_CODEPAGE_775 is not set 1497CONFIG_NLS_CODEPAGE_775=m
1314# CONFIG_NLS_CODEPAGE_850 is not set 1498CONFIG_NLS_CODEPAGE_850=y
1315# CONFIG_NLS_CODEPAGE_852 is not set 1499CONFIG_NLS_CODEPAGE_852=m
1316# CONFIG_NLS_CODEPAGE_855 is not set 1500CONFIG_NLS_CODEPAGE_855=m
1317# CONFIG_NLS_CODEPAGE_857 is not set 1501CONFIG_NLS_CODEPAGE_857=m
1318# CONFIG_NLS_CODEPAGE_860 is not set 1502CONFIG_NLS_CODEPAGE_860=m
1319# CONFIG_NLS_CODEPAGE_861 is not set 1503CONFIG_NLS_CODEPAGE_861=m
1320# CONFIG_NLS_CODEPAGE_862 is not set 1504CONFIG_NLS_CODEPAGE_862=m
1321# CONFIG_NLS_CODEPAGE_863 is not set 1505CONFIG_NLS_CODEPAGE_863=m
1322# CONFIG_NLS_CODEPAGE_864 is not set 1506CONFIG_NLS_CODEPAGE_864=m
1323# CONFIG_NLS_CODEPAGE_865 is not set 1507CONFIG_NLS_CODEPAGE_865=m
1324# CONFIG_NLS_CODEPAGE_866 is not set 1508CONFIG_NLS_CODEPAGE_866=m
1325# CONFIG_NLS_CODEPAGE_869 is not set 1509CONFIG_NLS_CODEPAGE_869=m
1326# CONFIG_NLS_CODEPAGE_936 is not set 1510CONFIG_NLS_CODEPAGE_936=m
1327# CONFIG_NLS_CODEPAGE_950 is not set 1511CONFIG_NLS_CODEPAGE_950=m
1328# CONFIG_NLS_CODEPAGE_932 is not set 1512CONFIG_NLS_CODEPAGE_932=m
1329# CONFIG_NLS_CODEPAGE_949 is not set 1513CONFIG_NLS_CODEPAGE_949=m
1330# CONFIG_NLS_CODEPAGE_874 is not set 1514CONFIG_NLS_CODEPAGE_874=m
1331# CONFIG_NLS_ISO8859_8 is not set 1515CONFIG_NLS_ISO8859_8=m
1332# CONFIG_NLS_CODEPAGE_1250 is not set 1516CONFIG_NLS_CODEPAGE_1250=m
1333# CONFIG_NLS_CODEPAGE_1251 is not set 1517CONFIG_NLS_CODEPAGE_1251=m
1334# CONFIG_NLS_ASCII is not set 1518CONFIG_NLS_ASCII=y
1335# CONFIG_NLS_ISO8859_1 is not set 1519CONFIG_NLS_ISO8859_1=y
1336# CONFIG_NLS_ISO8859_2 is not set 1520CONFIG_NLS_ISO8859_2=m
1337# CONFIG_NLS_ISO8859_3 is not set 1521CONFIG_NLS_ISO8859_3=m
1338# CONFIG_NLS_ISO8859_4 is not set 1522CONFIG_NLS_ISO8859_4=m
1339# CONFIG_NLS_ISO8859_5 is not set 1523CONFIG_NLS_ISO8859_5=m
1340# CONFIG_NLS_ISO8859_6 is not set 1524CONFIG_NLS_ISO8859_6=m
1341# CONFIG_NLS_ISO8859_7 is not set 1525CONFIG_NLS_ISO8859_7=m
1342# CONFIG_NLS_ISO8859_9 is not set 1526CONFIG_NLS_ISO8859_9=m
1343# CONFIG_NLS_ISO8859_13 is not set 1527CONFIG_NLS_ISO8859_13=m
1344# CONFIG_NLS_ISO8859_14 is not set 1528CONFIG_NLS_ISO8859_14=m
1345# CONFIG_NLS_ISO8859_15 is not set 1529CONFIG_NLS_ISO8859_15=m
1346# CONFIG_NLS_KOI8_R is not set 1530CONFIG_NLS_KOI8_R=m
1347# CONFIG_NLS_KOI8_U is not set 1531CONFIG_NLS_KOI8_U=m
1348# CONFIG_NLS_UTF8 is not set 1532CONFIG_NLS_UTF8=m
1349
1350#
1351# Distributed Lock Manager
1352#
1353# CONFIG_DLM is not set 1533# CONFIG_DLM is not set
1354 1534
1355# 1535#
1356# Profiling support
1357#
1358# CONFIG_PROFILING is not set
1359
1360#
1361# Kernel hacking 1536# Kernel hacking
1362# 1537#
1363# CONFIG_PRINTK_TIME is not set 1538# CONFIG_PRINTK_TIME is not set
1539CONFIG_ENABLE_WARN_DEPRECATED=y
1364CONFIG_ENABLE_MUST_CHECK=y 1540CONFIG_ENABLE_MUST_CHECK=y
1541CONFIG_FRAME_WARN=1024
1365CONFIG_MAGIC_SYSRQ=y 1542CONFIG_MAGIC_SYSRQ=y
1366# CONFIG_UNUSED_SYMBOLS is not set 1543# CONFIG_UNUSED_SYMBOLS is not set
1367# CONFIG_DEBUG_FS is not set 1544# CONFIG_DEBUG_FS is not set
1368# CONFIG_HEADERS_CHECK is not set 1545# CONFIG_HEADERS_CHECK is not set
1369CONFIG_DEBUG_KERNEL=y 1546CONFIG_DEBUG_KERNEL=y
1370# CONFIG_DEBUG_SHIRQ is not set 1547# CONFIG_DEBUG_SHIRQ is not set
1371CONFIG_LOG_BUF_SHIFT=16
1372CONFIG_DETECT_SOFTLOCKUP=y 1548CONFIG_DETECT_SOFTLOCKUP=y
1549CONFIG_SCHED_DEBUG=y
1373# CONFIG_SCHEDSTATS is not set 1550# CONFIG_SCHEDSTATS is not set
1374# CONFIG_TIMER_STATS is not set 1551# CONFIG_TIMER_STATS is not set
1552# CONFIG_DEBUG_OBJECTS is not set
1375# CONFIG_DEBUG_SLAB is not set 1553# CONFIG_DEBUG_SLAB is not set
1376# CONFIG_DEBUG_RT_MUTEXES is not set 1554# CONFIG_DEBUG_RT_MUTEXES is not set
1377# CONFIG_RT_MUTEX_TESTER is not set 1555# CONFIG_RT_MUTEX_TESTER is not set
1378# CONFIG_DEBUG_SPINLOCK is not set 1556# CONFIG_DEBUG_SPINLOCK is not set
1379CONFIG_DEBUG_MUTEXES=y 1557CONFIG_DEBUG_MUTEXES=y
1558# CONFIG_DEBUG_LOCK_ALLOC is not set
1559# CONFIG_PROVE_LOCKING is not set
1560# CONFIG_LOCK_STAT is not set
1380# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1561# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1381# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set 1562# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1382# CONFIG_DEBUG_KOBJECT is not set 1563# CONFIG_DEBUG_KOBJECT is not set
1383CONFIG_DEBUG_BUGVERBOSE=y 1564CONFIG_DEBUG_BUGVERBOSE=y
1384CONFIG_DEBUG_INFO=y 1565CONFIG_DEBUG_INFO=y
1385# CONFIG_DEBUG_VM is not set 1566# CONFIG_DEBUG_VM is not set
1567# CONFIG_DEBUG_WRITECOUNT is not set
1386# CONFIG_DEBUG_LIST is not set 1568# CONFIG_DEBUG_LIST is not set
1569# CONFIG_DEBUG_SG is not set
1387CONFIG_FRAME_POINTER=y 1570CONFIG_FRAME_POINTER=y
1388CONFIG_FORCED_INLINING=y 1571# CONFIG_BOOT_PRINTK_DELAY is not set
1389# CONFIG_RCU_TORTURE_TEST is not set 1572# CONFIG_RCU_TORTURE_TEST is not set
1573# CONFIG_BACKTRACE_SELF_TEST is not set
1390# CONFIG_FAULT_INJECTION is not set 1574# CONFIG_FAULT_INJECTION is not set
1575# CONFIG_SAMPLES is not set
1391CONFIG_DEBUG_USER=y 1576CONFIG_DEBUG_USER=y
1392# CONFIG_DEBUG_ERRORS is not set 1577CONFIG_DEBUG_ERRORS=y
1578# CONFIG_DEBUG_STACK_USAGE is not set
1393CONFIG_DEBUG_LL=y 1579CONFIG_DEBUG_LL=y
1394# CONFIG_DEBUG_ICEDCC is not set 1580# CONFIG_DEBUG_ICEDCC is not set
1395CONFIG_DEBUG_S3C_PORT=y 1581CONFIG_DEBUG_S3C_PORT=y
@@ -1400,21 +1586,100 @@ CONFIG_DEBUG_S3C_UART=0
1400# 1586#
1401# CONFIG_KEYS is not set 1587# CONFIG_KEYS is not set
1402# CONFIG_SECURITY is not set 1588# CONFIG_SECURITY is not set
1589# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1590CONFIG_CRYPTO=y
1591
1592#
1593# Crypto core or helper
1594#
1595CONFIG_CRYPTO_ALGAPI=m
1596CONFIG_CRYPTO_AEAD=m
1597CONFIG_CRYPTO_BLKCIPHER=m
1598CONFIG_CRYPTO_HASH=m
1599CONFIG_CRYPTO_MANAGER=m
1600# CONFIG_CRYPTO_GF128MUL is not set
1601# CONFIG_CRYPTO_NULL is not set
1602# CONFIG_CRYPTO_CRYPTD is not set
1603CONFIG_CRYPTO_AUTHENC=m
1604# CONFIG_CRYPTO_TEST is not set
1605
1606#
1607# Authenticated Encryption with Associated Data
1608#
1609# CONFIG_CRYPTO_CCM is not set
1610# CONFIG_CRYPTO_GCM is not set
1611# CONFIG_CRYPTO_SEQIV is not set
1612
1613#
1614# Block modes
1615#
1616CONFIG_CRYPTO_CBC=m
1617# CONFIG_CRYPTO_CTR is not set
1618# CONFIG_CRYPTO_CTS is not set
1619CONFIG_CRYPTO_ECB=m
1620# CONFIG_CRYPTO_LRW is not set
1621# CONFIG_CRYPTO_PCBC is not set
1622# CONFIG_CRYPTO_XTS is not set
1623
1624#
1625# Hash modes
1626#
1627CONFIG_CRYPTO_HMAC=m
1628# CONFIG_CRYPTO_XCBC is not set
1629
1630#
1631# Digest
1632#
1633# CONFIG_CRYPTO_CRC32C is not set
1634# CONFIG_CRYPTO_MD4 is not set
1635CONFIG_CRYPTO_MD5=m
1636# CONFIG_CRYPTO_MICHAEL_MIC is not set
1637CONFIG_CRYPTO_SHA1=m
1638# CONFIG_CRYPTO_SHA256 is not set
1639# CONFIG_CRYPTO_SHA512 is not set
1640# CONFIG_CRYPTO_TGR192 is not set
1641# CONFIG_CRYPTO_WP512 is not set
1642
1643#
1644# Ciphers
1645#
1646CONFIG_CRYPTO_AES=m
1647# CONFIG_CRYPTO_ANUBIS is not set
1648CONFIG_CRYPTO_ARC4=m
1649# CONFIG_CRYPTO_BLOWFISH is not set
1650# CONFIG_CRYPTO_CAMELLIA is not set
1651# CONFIG_CRYPTO_CAST5 is not set
1652# CONFIG_CRYPTO_CAST6 is not set
1653CONFIG_CRYPTO_DES=m
1654# CONFIG_CRYPTO_FCRYPT is not set
1655# CONFIG_CRYPTO_KHAZAD is not set
1656# CONFIG_CRYPTO_SALSA20 is not set
1657# CONFIG_CRYPTO_SEED is not set
1658# CONFIG_CRYPTO_SERPENT is not set
1659# CONFIG_CRYPTO_TEA is not set
1660# CONFIG_CRYPTO_TWOFISH is not set
1403 1661
1404# 1662#
1405# Cryptographic options 1663# Compression
1406# 1664#
1407# CONFIG_CRYPTO is not set 1665CONFIG_CRYPTO_DEFLATE=m
1666# CONFIG_CRYPTO_LZO is not set
1667CONFIG_CRYPTO_HW=y
1408 1668
1409# 1669#
1410# Library routines 1670# Library routines
1411# 1671#
1412CONFIG_BITREVERSE=y 1672CONFIG_BITREVERSE=y
1673# CONFIG_GENERIC_FIND_FIRST_BIT is not set
1674# CONFIG_GENERIC_FIND_NEXT_BIT is not set
1413# CONFIG_CRC_CCITT is not set 1675# CONFIG_CRC_CCITT is not set
1414# CONFIG_CRC16 is not set 1676# CONFIG_CRC16 is not set
1677CONFIG_CRC_ITU_T=m
1415CONFIG_CRC32=y 1678CONFIG_CRC32=y
1679# CONFIG_CRC7 is not set
1416# CONFIG_LIBCRC32C is not set 1680# CONFIG_LIBCRC32C is not set
1417CONFIG_ZLIB_INFLATE=y 1681CONFIG_ZLIB_INFLATE=y
1418CONFIG_ZLIB_DEFLATE=y 1682CONFIG_ZLIB_DEFLATE=y
1419CONFIG_PLIST=y 1683CONFIG_PLIST=y
1420CONFIG_HAS_IOMEM=y 1684CONFIG_HAS_IOMEM=y
1685CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/sam9_l9260_defconfig b/arch/arm/configs/sam9_l9260_defconfig
index 484dc9739dfc..8688362bcf7b 100644
--- a/arch/arm/configs/sam9_l9260_defconfig
+++ b/arch/arm/configs/sam9_l9260_defconfig
@@ -211,7 +211,6 @@ CONFIG_ARM_THUMB=y
211# 211#
212# CONFIG_TICK_ONESHOT is not set 212# CONFIG_TICK_ONESHOT is not set
213CONFIG_PREEMPT=y 213CONFIG_PREEMPT=y
214# CONFIG_NO_IDLE_HZ is not set
215CONFIG_HZ=100 214CONFIG_HZ=100
216# CONFIG_AEABI is not set 215# CONFIG_AEABI is not set
217# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 216# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
index aa7a01179500..7d59fb1f1cea 100644
--- a/arch/arm/configs/spitz_defconfig
+++ b/arch/arm/configs/spitz_defconfig
@@ -164,7 +164,6 @@ CONFIG_PCMCIA_PXA2XX=y
164# Kernel Features 164# Kernel Features
165# 165#
166CONFIG_PREEMPT=y 166CONFIG_PREEMPT=y
167# CONFIG_NO_IDLE_HZ is not set
168# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 167# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
169CONFIG_SELECT_MEMORY_MODEL=y 168CONFIG_SELECT_MEMORY_MODEL=y
170CONFIG_FLATMEM_MANUAL=y 169CONFIG_FLATMEM_MANUAL=y
diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig
index 576b8339f0d6..07dfb98df4f0 100644
--- a/arch/arm/configs/tct_hammer_defconfig
+++ b/arch/arm/configs/tct_hammer_defconfig
@@ -247,7 +247,6 @@ CONFIG_ARM_THUMB=y
247# 247#
248# CONFIG_TICK_ONESHOT is not set 248# CONFIG_TICK_ONESHOT is not set
249# CONFIG_PREEMPT is not set 249# CONFIG_PREEMPT is not set
250# CONFIG_NO_IDLE_HZ is not set
251CONFIG_HZ=200 250CONFIG_HZ=200
252# CONFIG_AEABI is not set 251# CONFIG_AEABI is not set
253# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 252# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig
index 6db6392806f9..8b7a431a8bfc 100644
--- a/arch/arm/configs/trizeps4_defconfig
+++ b/arch/arm/configs/trizeps4_defconfig
@@ -195,7 +195,6 @@ CONFIG_PCMCIA_PXA2XX=y
195# Kernel Features 195# Kernel Features
196# 196#
197CONFIG_PREEMPT=y 197CONFIG_PREEMPT=y
198# CONFIG_NO_IDLE_HZ is not set
199CONFIG_HZ=100 198CONFIG_HZ=100
200CONFIG_AEABI=y 199CONFIG_AEABI=y
201CONFIG_OABI_COMPAT=y 200CONFIG_OABI_COMPAT=y
diff --git a/arch/arm/configs/usb-a9260_defconfig b/arch/arm/configs/usb-a9260_defconfig
new file mode 100644
index 000000000000..3680bd2df26d
--- /dev/null
+++ b/arch/arm/configs/usb-a9260_defconfig
@@ -0,0 +1,1142 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24
4# Tue Apr 15 11:39:35 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35# CONFIG_LOCALVERSION_AUTO is not set
36# CONFIG_SWAP is not set
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48CONFIG_FAIR_GROUP_SCHED=y
49CONFIG_FAIR_USER_SCHED=y
50# CONFIG_FAIR_CGROUP_SCHED is not set
51# CONFIG_SYSFS_DEPRECATED is not set
52# CONFIG_RELAY is not set
53# CONFIG_BLK_DEV_INITRD is not set
54# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
55CONFIG_SYSCTL=y
56# CONFIG_EMBEDDED is not set
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_KALLSYMS=y
60# CONFIG_KALLSYMS_ALL is not set
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_EVENTFD=y
72CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y
75# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set
77CONFIG_SLABINFO=y
78CONFIG_RT_MUTEXES=y
79# CONFIG_TINY_SHMEM is not set
80CONFIG_BASE_SMALL=0
81CONFIG_MODULES=y
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97CONFIG_IOSCHED_AS=y
98# CONFIG_IOSCHED_DEADLINE is not set
99# CONFIG_IOSCHED_CFQ is not set
100CONFIG_DEFAULT_AS=y
101# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set
103# CONFIG_DEFAULT_NOOP is not set
104CONFIG_DEFAULT_IOSCHED="anticipatory"
105
106#
107# System Type
108#
109# CONFIG_ARCH_AAEC2000 is not set
110# CONFIG_ARCH_INTEGRATOR is not set
111# CONFIG_ARCH_REALVIEW is not set
112# CONFIG_ARCH_VERSATILE is not set
113CONFIG_ARCH_AT91=y
114# CONFIG_ARCH_CLPS7500 is not set
115# CONFIG_ARCH_CLPS711X is not set
116# CONFIG_ARCH_CO285 is not set
117# CONFIG_ARCH_EBSA110 is not set
118# CONFIG_ARCH_EP93XX is not set
119# CONFIG_ARCH_FOOTBRIDGE is not set
120# CONFIG_ARCH_NETX is not set
121# CONFIG_ARCH_H720X is not set
122# CONFIG_ARCH_IMX is not set
123# CONFIG_ARCH_IOP13XX is not set
124# CONFIG_ARCH_IOP32X is not set
125# CONFIG_ARCH_IOP33X is not set
126# CONFIG_ARCH_IXP23XX is not set
127# CONFIG_ARCH_IXP2000 is not set
128# CONFIG_ARCH_IXP4XX is not set
129# CONFIG_ARCH_L7200 is not set
130# CONFIG_ARCH_KS8695 is not set
131# CONFIG_ARCH_NS9XXX is not set
132# CONFIG_ARCH_MXC is not set
133# CONFIG_ARCH_PNX4008 is not set
134# CONFIG_ARCH_PXA is not set
135# CONFIG_ARCH_RPC is not set
136# CONFIG_ARCH_SA1100 is not set
137# CONFIG_ARCH_S3C2410 is not set
138# CONFIG_ARCH_SHARK is not set
139# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set
141# CONFIG_ARCH_OMAP is not set
142
143#
144# Boot options
145#
146
147#
148# Power management
149#
150
151#
152# Atmel AT91 System-on-Chip
153#
154# CONFIG_ARCH_AT91RM9200 is not set
155CONFIG_ARCH_AT91SAM9260=y
156# CONFIG_ARCH_AT91SAM9261 is not set
157# CONFIG_ARCH_AT91SAM9263 is not set
158# CONFIG_ARCH_AT91SAM9RL is not set
159# CONFIG_ARCH_AT91CAP9 is not set
160# CONFIG_ARCH_AT91X40 is not set
161CONFIG_AT91_PMC_UNIT=y
162
163#
164# AT91SAM9260 Variants
165#
166# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
167
168#
169# AT91SAM9260 / AT91SAM9XE Board Type
170#
171# CONFIG_MACH_AT91SAM9260EK is not set
172# CONFIG_MACH_CAM60 is not set
173# CONFIG_MACH_SAM9_L9260 is not set
174CONFIG_MACH_USB_A9260=y
175# CONFIG_MACH_QIL_A9260 is not set
176
177#
178# AT91 Board Options
179#
180
181#
182# AT91 Feature Selections
183#
184# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
185CONFIG_AT91_SLOW_CLOCK=y
186CONFIG_AT91_TIMER_HZ=100
187CONFIG_AT91_EARLY_DBGU=y
188# CONFIG_AT91_EARLY_USART0 is not set
189# CONFIG_AT91_EARLY_USART1 is not set
190# CONFIG_AT91_EARLY_USART2 is not set
191# CONFIG_AT91_EARLY_USART3 is not set
192# CONFIG_AT91_EARLY_USART4 is not set
193# CONFIG_AT91_EARLY_USART5 is not set
194
195#
196# Processor Type
197#
198CONFIG_CPU_32=y
199CONFIG_CPU_ARM926T=y
200CONFIG_CPU_32v5=y
201CONFIG_CPU_ABRT_EV5TJ=y
202CONFIG_CPU_CACHE_VIVT=y
203CONFIG_CPU_COPY_V4WB=y
204CONFIG_CPU_TLB_V4WBI=y
205CONFIG_CPU_CP15=y
206CONFIG_CPU_CP15_MMU=y
207
208#
209# Processor Features
210#
211# CONFIG_ARM_THUMB is not set
212# CONFIG_CPU_ICACHE_DISABLE is not set
213# CONFIG_CPU_DCACHE_DISABLE is not set
214# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
215# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
216# CONFIG_OUTER_CACHE is not set
217
218#
219# Bus support
220#
221# CONFIG_PCI_SYSCALL is not set
222# CONFIG_ARCH_SUPPORTS_MSI is not set
223# CONFIG_PCCARD is not set
224
225#
226# Kernel Features
227#
228# CONFIG_TICK_ONESHOT is not set
229# CONFIG_NO_HZ is not set
230# CONFIG_HIGH_RES_TIMERS is not set
231CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
232# CONFIG_PREEMPT is not set
233CONFIG_HZ=100
234CONFIG_AEABI=y
235CONFIG_OABI_COMPAT=y
236# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
237CONFIG_SELECT_MEMORY_MODEL=y
238CONFIG_FLATMEM_MANUAL=y
239# CONFIG_DISCONTIGMEM_MANUAL is not set
240# CONFIG_SPARSEMEM_MANUAL is not set
241CONFIG_FLATMEM=y
242CONFIG_FLAT_NODE_MEM_MAP=y
243# CONFIG_SPARSEMEM_STATIC is not set
244# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
245CONFIG_SPLIT_PTLOCK_CPUS=4096
246# CONFIG_RESOURCES_64BIT is not set
247CONFIG_ZONE_DMA_FLAG=1
248CONFIG_BOUNCE=y
249CONFIG_VIRT_TO_BUS=y
250# CONFIG_LEDS is not set
251CONFIG_ALIGNMENT_TRAP=y
252
253#
254# Boot options
255#
256CONFIG_ZBOOT_ROM_TEXT=0x0
257CONFIG_ZBOOT_ROM_BSS=0x0
258CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
259# CONFIG_XIP_KERNEL is not set
260# CONFIG_KEXEC is not set
261
262#
263# Floating point emulation
264#
265
266#
267# At least one emulation must be selected
268#
269CONFIG_FPE_NWFPE=y
270# CONFIG_FPE_NWFPE_XP is not set
271# CONFIG_FPE_FASTFPE is not set
272# CONFIG_VFP is not set
273
274#
275# Userspace binary formats
276#
277CONFIG_BINFMT_ELF=y
278# CONFIG_BINFMT_AOUT is not set
279# CONFIG_BINFMT_MISC is not set
280
281#
282# Power management options
283#
284CONFIG_PM=y
285# CONFIG_PM_LEGACY is not set
286# CONFIG_PM_DEBUG is not set
287CONFIG_PM_SLEEP=y
288CONFIG_SUSPEND_UP_POSSIBLE=y
289CONFIG_SUSPEND=y
290# CONFIG_APM_EMULATION is not set
291
292#
293# Networking
294#
295CONFIG_NET=y
296
297#
298# Networking options
299#
300CONFIG_PACKET=y
301# CONFIG_PACKET_MMAP is not set
302CONFIG_UNIX=y
303# CONFIG_NET_KEY is not set
304CONFIG_INET=y
305CONFIG_IP_MULTICAST=y
306CONFIG_IP_ADVANCED_ROUTER=y
307CONFIG_ASK_IP_FIB_HASH=y
308# CONFIG_IP_FIB_TRIE is not set
309CONFIG_IP_FIB_HASH=y
310# CONFIG_IP_MULTIPLE_TABLES is not set
311# CONFIG_IP_ROUTE_MULTIPATH is not set
312CONFIG_IP_ROUTE_VERBOSE=y
313CONFIG_IP_PNP=y
314# CONFIG_IP_PNP_DHCP is not set
315CONFIG_IP_PNP_BOOTP=y
316CONFIG_IP_PNP_RARP=y
317# CONFIG_NET_IPIP is not set
318# CONFIG_NET_IPGRE is not set
319CONFIG_IP_MROUTE=y
320CONFIG_IP_PIMSM_V1=y
321CONFIG_IP_PIMSM_V2=y
322# CONFIG_ARPD is not set
323# CONFIG_SYN_COOKIES is not set
324# CONFIG_INET_AH is not set
325# CONFIG_INET_ESP is not set
326# CONFIG_INET_IPCOMP is not set
327# CONFIG_INET_XFRM_TUNNEL is not set
328# CONFIG_INET_TUNNEL is not set
329# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
330# CONFIG_INET_XFRM_MODE_TUNNEL is not set
331# CONFIG_INET_XFRM_MODE_BEET is not set
332# CONFIG_INET_LRO is not set
333# CONFIG_INET_DIAG is not set
334# CONFIG_TCP_CONG_ADVANCED is not set
335CONFIG_TCP_CONG_CUBIC=y
336CONFIG_DEFAULT_TCP_CONG="cubic"
337# CONFIG_TCP_MD5SIG is not set
338# CONFIG_IPV6 is not set
339# CONFIG_INET6_XFRM_TUNNEL is not set
340# CONFIG_INET6_TUNNEL is not set
341# CONFIG_NETWORK_SECMARK is not set
342# CONFIG_NETFILTER is not set
343# CONFIG_IP_DCCP is not set
344# CONFIG_IP_SCTP is not set
345# CONFIG_TIPC is not set
346# CONFIG_ATM is not set
347# CONFIG_BRIDGE is not set
348# CONFIG_VLAN_8021Q is not set
349# CONFIG_DECNET is not set
350# CONFIG_LLC2 is not set
351# CONFIG_IPX is not set
352# CONFIG_ATALK is not set
353# CONFIG_X25 is not set
354# CONFIG_LAPB is not set
355# CONFIG_ECONET is not set
356# CONFIG_WAN_ROUTER is not set
357# CONFIG_NET_SCHED is not set
358
359#
360# Network testing
361#
362# CONFIG_NET_PKTGEN is not set
363# CONFIG_HAMRADIO is not set
364# CONFIG_IRDA is not set
365# CONFIG_BT is not set
366# CONFIG_AF_RXRPC is not set
367
368#
369# Wireless
370#
371# CONFIG_CFG80211 is not set
372# CONFIG_WIRELESS_EXT is not set
373# CONFIG_MAC80211 is not set
374# CONFIG_IEEE80211 is not set
375# CONFIG_RFKILL is not set
376# CONFIG_NET_9P is not set
377
378#
379# Device Drivers
380#
381
382#
383# Generic Driver Options
384#
385CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
386CONFIG_STANDALONE=y
387CONFIG_PREVENT_FIRMWARE_BUILD=y
388# CONFIG_FW_LOADER is not set
389# CONFIG_DEBUG_DRIVER is not set
390# CONFIG_DEBUG_DEVRES is not set
391# CONFIG_SYS_HYPERVISOR is not set
392# CONFIG_CONNECTOR is not set
393CONFIG_MTD=y
394# CONFIG_MTD_DEBUG is not set
395# CONFIG_MTD_CONCAT is not set
396CONFIG_MTD_PARTITIONS=y
397# CONFIG_MTD_REDBOOT_PARTS is not set
398CONFIG_MTD_CMDLINE_PARTS=y
399# CONFIG_MTD_AFS_PARTS is not set
400
401#
402# User Modules And Translation Layers
403#
404CONFIG_MTD_CHAR=y
405CONFIG_MTD_BLKDEVS=y
406CONFIG_MTD_BLOCK=y
407# CONFIG_FTL is not set
408# CONFIG_NFTL is not set
409# CONFIG_INFTL is not set
410# CONFIG_RFD_FTL is not set
411# CONFIG_SSFDC is not set
412# CONFIG_MTD_OOPS is not set
413
414#
415# RAM/ROM/Flash chip drivers
416#
417# CONFIG_MTD_CFI is not set
418# CONFIG_MTD_JEDECPROBE is not set
419CONFIG_MTD_MAP_BANK_WIDTH_1=y
420CONFIG_MTD_MAP_BANK_WIDTH_2=y
421CONFIG_MTD_MAP_BANK_WIDTH_4=y
422# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
423# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
424# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
425CONFIG_MTD_CFI_I1=y
426CONFIG_MTD_CFI_I2=y
427# CONFIG_MTD_CFI_I4 is not set
428# CONFIG_MTD_CFI_I8 is not set
429# CONFIG_MTD_RAM is not set
430# CONFIG_MTD_ROM is not set
431# CONFIG_MTD_ABSENT is not set
432
433#
434# Mapping drivers for chip access
435#
436# CONFIG_MTD_COMPLEX_MAPPINGS is not set
437# CONFIG_MTD_PLATRAM is not set
438
439#
440# Self-contained MTD device drivers
441#
442CONFIG_MTD_DATAFLASH=y
443# CONFIG_MTD_M25P80 is not set
444# CONFIG_MTD_SLRAM is not set
445# CONFIG_MTD_PHRAM is not set
446# CONFIG_MTD_MTDRAM is not set
447# CONFIG_MTD_BLOCK2MTD is not set
448
449#
450# Disk-On-Chip Device Drivers
451#
452# CONFIG_MTD_DOC2000 is not set
453# CONFIG_MTD_DOC2001 is not set
454# CONFIG_MTD_DOC2001PLUS is not set
455CONFIG_MTD_NAND=y
456# CONFIG_MTD_NAND_VERIFY_WRITE is not set
457# CONFIG_MTD_NAND_ECC_SMC is not set
458# CONFIG_MTD_NAND_MUSEUM_IDS is not set
459CONFIG_MTD_NAND_IDS=y
460# CONFIG_MTD_NAND_DISKONCHIP is not set
461CONFIG_MTD_NAND_AT91=y
462CONFIG_MTD_NAND_AT91_ECC_SOFT=y
463# CONFIG_MTD_NAND_AT91_ECC_HW is not set
464# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
465# CONFIG_MTD_NAND_NANDSIM is not set
466# CONFIG_MTD_NAND_PLATFORM is not set
467# CONFIG_MTD_ALAUDA is not set
468# CONFIG_MTD_ONENAND is not set
469
470#
471# UBI - Unsorted block images
472#
473# CONFIG_MTD_UBI is not set
474# CONFIG_PARPORT is not set
475CONFIG_BLK_DEV=y
476# CONFIG_BLK_DEV_COW_COMMON is not set
477CONFIG_BLK_DEV_LOOP=y
478# CONFIG_BLK_DEV_CRYPTOLOOP is not set
479# CONFIG_BLK_DEV_NBD is not set
480# CONFIG_BLK_DEV_UB is not set
481# CONFIG_BLK_DEV_RAM is not set
482# CONFIG_CDROM_PKTCDVD is not set
483# CONFIG_ATA_OVER_ETH is not set
484# CONFIG_MISC_DEVICES is not set
485
486#
487# SCSI device support
488#
489# CONFIG_RAID_ATTRS is not set
490CONFIG_SCSI=y
491CONFIG_SCSI_DMA=y
492# CONFIG_SCSI_TGT is not set
493# CONFIG_SCSI_NETLINK is not set
494CONFIG_SCSI_PROC_FS=y
495
496#
497# SCSI support type (disk, tape, CD-ROM)
498#
499CONFIG_BLK_DEV_SD=y
500# CONFIG_CHR_DEV_ST is not set
501# CONFIG_CHR_DEV_OSST is not set
502# CONFIG_BLK_DEV_SR is not set
503# CONFIG_CHR_DEV_SG is not set
504# CONFIG_CHR_DEV_SCH is not set
505
506#
507# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
508#
509CONFIG_SCSI_MULTI_LUN=y
510# CONFIG_SCSI_CONSTANTS is not set
511# CONFIG_SCSI_LOGGING is not set
512# CONFIG_SCSI_SCAN_ASYNC is not set
513CONFIG_SCSI_WAIT_SCAN=m
514
515#
516# SCSI Transports
517#
518# CONFIG_SCSI_SPI_ATTRS is not set
519# CONFIG_SCSI_FC_ATTRS is not set
520# CONFIG_SCSI_ISCSI_ATTRS is not set
521# CONFIG_SCSI_SAS_LIBSAS is not set
522# CONFIG_SCSI_SRP_ATTRS is not set
523CONFIG_SCSI_LOWLEVEL=y
524# CONFIG_ISCSI_TCP is not set
525# CONFIG_SCSI_DEBUG is not set
526# CONFIG_ATA is not set
527# CONFIG_MD is not set
528CONFIG_NETDEVICES=y
529# CONFIG_NETDEVICES_MULTIQUEUE is not set
530# CONFIG_DUMMY is not set
531# CONFIG_BONDING is not set
532# CONFIG_MACVLAN is not set
533# CONFIG_EQUALIZER is not set
534# CONFIG_TUN is not set
535# CONFIG_VETH is not set
536CONFIG_PHYLIB=y
537
538#
539# MII PHY device drivers
540#
541# CONFIG_MARVELL_PHY is not set
542# CONFIG_DAVICOM_PHY is not set
543# CONFIG_QSEMI_PHY is not set
544# CONFIG_LXT_PHY is not set
545# CONFIG_CICADA_PHY is not set
546# CONFIG_VITESSE_PHY is not set
547# CONFIG_SMSC_PHY is not set
548# CONFIG_BROADCOM_PHY is not set
549# CONFIG_ICPLUS_PHY is not set
550# CONFIG_FIXED_PHY is not set
551# CONFIG_MDIO_BITBANG is not set
552CONFIG_NET_ETHERNET=y
553CONFIG_MII=y
554CONFIG_MACB=y
555# CONFIG_AX88796 is not set
556# CONFIG_SMC91X is not set
557# CONFIG_DM9000 is not set
558# CONFIG_IBM_NEW_EMAC_ZMII is not set
559# CONFIG_IBM_NEW_EMAC_RGMII is not set
560# CONFIG_IBM_NEW_EMAC_TAH is not set
561# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
562# CONFIG_B44 is not set
563CONFIG_NETDEV_1000=y
564CONFIG_NETDEV_10000=y
565
566#
567# Wireless LAN
568#
569# CONFIG_WLAN_PRE80211 is not set
570# CONFIG_WLAN_80211 is not set
571
572#
573# USB Network Adapters
574#
575# CONFIG_USB_CATC is not set
576# CONFIG_USB_KAWETH is not set
577# CONFIG_USB_PEGASUS is not set
578# CONFIG_USB_RTL8150 is not set
579# CONFIG_USB_USBNET is not set
580# CONFIG_WAN is not set
581# CONFIG_PPP is not set
582# CONFIG_SLIP is not set
583# CONFIG_SHAPER is not set
584# CONFIG_NETCONSOLE is not set
585# CONFIG_NETPOLL is not set
586# CONFIG_NET_POLL_CONTROLLER is not set
587# CONFIG_ISDN is not set
588
589#
590# Input device support
591#
592CONFIG_INPUT=y
593# CONFIG_INPUT_FF_MEMLESS is not set
594# CONFIG_INPUT_POLLDEV is not set
595
596#
597# Userland interfaces
598#
599CONFIG_INPUT_MOUSEDEV=y
600# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
601CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
602CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
603# CONFIG_INPUT_JOYDEV is not set
604CONFIG_INPUT_EVDEV=y
605CONFIG_INPUT_EVBUG=y
606
607#
608# Input Device Drivers
609#
610CONFIG_INPUT_KEYBOARD=y
611# CONFIG_KEYBOARD_ATKBD is not set
612# CONFIG_KEYBOARD_SUNKBD is not set
613# CONFIG_KEYBOARD_LKKBD is not set
614# CONFIG_KEYBOARD_XTKBD is not set
615# CONFIG_KEYBOARD_NEWTON is not set
616# CONFIG_KEYBOARD_STOWAWAY is not set
617CONFIG_KEYBOARD_GPIO=y
618# CONFIG_INPUT_MOUSE is not set
619# CONFIG_INPUT_JOYSTICK is not set
620# CONFIG_INPUT_TABLET is not set
621# CONFIG_INPUT_TOUCHSCREEN is not set
622# CONFIG_INPUT_MISC is not set
623
624#
625# Hardware I/O ports
626#
627# CONFIG_SERIO is not set
628# CONFIG_GAMEPORT is not set
629
630#
631# Character devices
632#
633CONFIG_VT=y
634CONFIG_VT_CONSOLE=y
635CONFIG_HW_CONSOLE=y
636# CONFIG_VT_HW_CONSOLE_BINDING is not set
637# CONFIG_SERIAL_NONSTANDARD is not set
638
639#
640# Serial drivers
641#
642# CONFIG_SERIAL_8250 is not set
643
644#
645# Non-8250 serial port support
646#
647CONFIG_SERIAL_ATMEL=y
648CONFIG_SERIAL_ATMEL_CONSOLE=y
649# CONFIG_SERIAL_ATMEL_TTYAT is not set
650CONFIG_SERIAL_CORE=y
651CONFIG_SERIAL_CORE_CONSOLE=y
652CONFIG_UNIX98_PTYS=y
653CONFIG_LEGACY_PTYS=y
654CONFIG_LEGACY_PTY_COUNT=256
655# CONFIG_IPMI_HANDLER is not set
656CONFIG_HW_RANDOM=y
657# CONFIG_NVRAM is not set
658# CONFIG_R3964 is not set
659# CONFIG_RAW_DRIVER is not set
660# CONFIG_TCG_TPM is not set
661# CONFIG_I2C is not set
662
663#
664# SPI support
665#
666CONFIG_SPI=y
667# CONFIG_SPI_DEBUG is not set
668CONFIG_SPI_MASTER=y
669
670#
671# SPI Master Controller Drivers
672#
673CONFIG_SPI_ATMEL=y
674# CONFIG_SPI_BITBANG is not set
675
676#
677# SPI Protocol Masters
678#
679# CONFIG_SPI_AT25 is not set
680# CONFIG_SPI_SPIDEV is not set
681# CONFIG_SPI_TLE62X0 is not set
682# CONFIG_W1 is not set
683# CONFIG_POWER_SUPPLY is not set
684# CONFIG_HWMON is not set
685# CONFIG_WATCHDOG is not set
686
687#
688# Sonics Silicon Backplane
689#
690CONFIG_SSB_POSSIBLE=y
691# CONFIG_SSB is not set
692
693#
694# Multifunction device drivers
695#
696# CONFIG_MFD_SM501 is not set
697
698#
699# Multimedia devices
700#
701# CONFIG_VIDEO_DEV is not set
702# CONFIG_DVB_CORE is not set
703# CONFIG_DAB is not set
704
705#
706# Graphics support
707#
708# CONFIG_VGASTATE is not set
709# CONFIG_VIDEO_OUTPUT_CONTROL is not set
710# CONFIG_FB is not set
711# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
712
713#
714# Display device support
715#
716# CONFIG_DISPLAY_SUPPORT is not set
717
718#
719# Console display driver support
720#
721# CONFIG_VGA_CONSOLE is not set
722CONFIG_DUMMY_CONSOLE=y
723
724#
725# Sound
726#
727# CONFIG_SOUND is not set
728CONFIG_HID_SUPPORT=y
729CONFIG_HID=y
730# CONFIG_HID_DEBUG is not set
731# CONFIG_HIDRAW is not set
732
733#
734# USB Input Devices
735#
736# CONFIG_USB_HID is not set
737
738#
739# USB HID Boot Protocol drivers
740#
741# CONFIG_USB_KBD is not set
742# CONFIG_USB_MOUSE is not set
743CONFIG_USB_SUPPORT=y
744CONFIG_USB_ARCH_HAS_HCD=y
745CONFIG_USB_ARCH_HAS_OHCI=y
746# CONFIG_USB_ARCH_HAS_EHCI is not set
747CONFIG_USB=y
748# CONFIG_USB_DEBUG is not set
749
750#
751# Miscellaneous USB options
752#
753CONFIG_USB_DEVICEFS=y
754CONFIG_USB_DEVICE_CLASS=y
755# CONFIG_USB_DYNAMIC_MINORS is not set
756# CONFIG_USB_SUSPEND is not set
757# CONFIG_USB_PERSIST is not set
758# CONFIG_USB_OTG is not set
759
760#
761# USB Host Controller Drivers
762#
763# CONFIG_USB_ISP116X_HCD is not set
764CONFIG_USB_OHCI_HCD=y
765# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
766# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
767CONFIG_USB_OHCI_LITTLE_ENDIAN=y
768# CONFIG_USB_SL811_HCD is not set
769# CONFIG_USB_R8A66597_HCD is not set
770
771#
772# USB Device Class drivers
773#
774# CONFIG_USB_ACM is not set
775# CONFIG_USB_PRINTER is not set
776
777#
778# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
779#
780
781#
782# may also be needed; see USB_STORAGE Help for more information
783#
784CONFIG_USB_STORAGE=y
785# CONFIG_USB_STORAGE_DEBUG is not set
786# CONFIG_USB_STORAGE_DATAFAB is not set
787# CONFIG_USB_STORAGE_FREECOM is not set
788# CONFIG_USB_STORAGE_ISD200 is not set
789# CONFIG_USB_STORAGE_DPCM is not set
790# CONFIG_USB_STORAGE_USBAT is not set
791# CONFIG_USB_STORAGE_SDDR09 is not set
792# CONFIG_USB_STORAGE_SDDR55 is not set
793# CONFIG_USB_STORAGE_JUMPSHOT is not set
794# CONFIG_USB_STORAGE_ALAUDA is not set
795# CONFIG_USB_STORAGE_KARMA is not set
796# CONFIG_USB_LIBUSUAL is not set
797
798#
799# USB Imaging devices
800#
801# CONFIG_USB_MDC800 is not set
802# CONFIG_USB_MICROTEK is not set
803CONFIG_USB_MON=y
804
805#
806# USB port drivers
807#
808
809#
810# USB Serial Converter support
811#
812# CONFIG_USB_SERIAL is not set
813
814#
815# USB Miscellaneous drivers
816#
817# CONFIG_USB_EMI62 is not set
818# CONFIG_USB_EMI26 is not set
819# CONFIG_USB_ADUTUX is not set
820# CONFIG_USB_AUERSWALD is not set
821# CONFIG_USB_RIO500 is not set
822# CONFIG_USB_LEGOTOWER is not set
823# CONFIG_USB_LCD is not set
824# CONFIG_USB_BERRY_CHARGE is not set
825# CONFIG_USB_LED is not set
826# CONFIG_USB_CYPRESS_CY7C63 is not set
827# CONFIG_USB_CYTHERM is not set
828# CONFIG_USB_PHIDGET is not set
829# CONFIG_USB_IDMOUSE is not set
830# CONFIG_USB_FTDI_ELAN is not set
831# CONFIG_USB_APPLEDISPLAY is not set
832# CONFIG_USB_LD is not set
833# CONFIG_USB_TRANCEVIBRATOR is not set
834# CONFIG_USB_IOWARRIOR is not set
835# CONFIG_USB_TEST is not set
836
837#
838# USB DSL modem support
839#
840
841#
842# USB Gadget Support
843#
844CONFIG_USB_GADGET=y
845# CONFIG_USB_GADGET_DEBUG is not set
846# CONFIG_USB_GADGET_DEBUG_FILES is not set
847CONFIG_USB_GADGET_SELECTED=y
848# CONFIG_USB_GADGET_AMD5536UDC is not set
849# CONFIG_USB_GADGET_ATMEL_USBA is not set
850# CONFIG_USB_GADGET_FSL_USB2 is not set
851# CONFIG_USB_GADGET_NET2280 is not set
852# CONFIG_USB_GADGET_PXA2XX is not set
853# CONFIG_USB_GADGET_M66592 is not set
854# CONFIG_USB_GADGET_GOKU is not set
855# CONFIG_USB_GADGET_LH7A40X is not set
856# CONFIG_USB_GADGET_OMAP is not set
857# CONFIG_USB_GADGET_S3C2410 is not set
858CONFIG_USB_GADGET_AT91=y
859CONFIG_USB_AT91=y
860# CONFIG_USB_GADGET_DUMMY_HCD is not set
861# CONFIG_USB_GADGET_DUALSPEED is not set
862# CONFIG_USB_ZERO is not set
863CONFIG_USB_ETH=y
864CONFIG_USB_ETH_RNDIS=y
865# CONFIG_USB_GADGETFS is not set
866# CONFIG_USB_FILE_STORAGE is not set
867# CONFIG_USB_G_SERIAL is not set
868# CONFIG_USB_MIDI_GADGET is not set
869# CONFIG_MMC is not set
870CONFIG_NEW_LEDS=y
871CONFIG_LEDS_CLASS=y
872
873#
874# LED drivers
875#
876CONFIG_LEDS_GPIO=y
877
878#
879# LED Triggers
880#
881CONFIG_LEDS_TRIGGERS=y
882# CONFIG_LEDS_TRIGGER_TIMER is not set
883CONFIG_LEDS_TRIGGER_HEARTBEAT=y
884CONFIG_RTC_LIB=y
885# CONFIG_RTC_CLASS is not set
886
887#
888# File systems
889#
890CONFIG_EXT2_FS=y
891# CONFIG_EXT2_FS_XATTR is not set
892# CONFIG_EXT2_FS_XIP is not set
893# CONFIG_EXT3_FS is not set
894# CONFIG_EXT4DEV_FS is not set
895# CONFIG_REISERFS_FS is not set
896# CONFIG_JFS_FS is not set
897CONFIG_FS_POSIX_ACL=y
898# CONFIG_XFS_FS is not set
899# CONFIG_GFS2_FS is not set
900# CONFIG_OCFS2_FS is not set
901# CONFIG_MINIX_FS is not set
902# CONFIG_ROMFS_FS is not set
903CONFIG_INOTIFY=y
904CONFIG_INOTIFY_USER=y
905# CONFIG_QUOTA is not set
906CONFIG_DNOTIFY=y
907# CONFIG_AUTOFS_FS is not set
908# CONFIG_AUTOFS4_FS is not set
909CONFIG_FUSE_FS=m
910
911#
912# CD-ROM/DVD Filesystems
913#
914# CONFIG_ISO9660_FS is not set
915# CONFIG_UDF_FS is not set
916
917#
918# DOS/FAT/NT Filesystems
919#
920CONFIG_FAT_FS=y
921# CONFIG_MSDOS_FS is not set
922CONFIG_VFAT_FS=y
923CONFIG_FAT_DEFAULT_CODEPAGE=437
924CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
925# CONFIG_NTFS_FS is not set
926
927#
928# Pseudo filesystems
929#
930CONFIG_PROC_FS=y
931CONFIG_PROC_SYSCTL=y
932CONFIG_SYSFS=y
933CONFIG_TMPFS=y
934# CONFIG_TMPFS_POSIX_ACL is not set
935# CONFIG_HUGETLB_PAGE is not set
936# CONFIG_CONFIGFS_FS is not set
937
938#
939# Miscellaneous filesystems
940#
941# CONFIG_ADFS_FS is not set
942# CONFIG_AFFS_FS is not set
943# CONFIG_HFS_FS is not set
944# CONFIG_HFSPLUS_FS is not set
945# CONFIG_BEFS_FS is not set
946# CONFIG_BFS_FS is not set
947# CONFIG_EFS_FS is not set
948CONFIG_JFFS2_FS=y
949CONFIG_JFFS2_FS_DEBUG=0
950CONFIG_JFFS2_FS_WRITEBUFFER=y
951# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
952# CONFIG_JFFS2_SUMMARY is not set
953# CONFIG_JFFS2_FS_XATTR is not set
954# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
955CONFIG_JFFS2_ZLIB=y
956# CONFIG_JFFS2_LZO is not set
957CONFIG_JFFS2_RTIME=y
958# CONFIG_JFFS2_RUBIN is not set
959# CONFIG_CRAMFS is not set
960# CONFIG_VXFS_FS is not set
961# CONFIG_HPFS_FS is not set
962# CONFIG_QNX4FS_FS is not set
963# CONFIG_SYSV_FS is not set
964# CONFIG_UFS_FS is not set
965CONFIG_NETWORK_FILESYSTEMS=y
966CONFIG_NFS_FS=y
967CONFIG_NFS_V3=y
968CONFIG_NFS_V3_ACL=y
969CONFIG_NFS_V4=y
970# CONFIG_NFS_DIRECTIO is not set
971# CONFIG_NFSD is not set
972CONFIG_ROOT_NFS=y
973CONFIG_LOCKD=y
974CONFIG_LOCKD_V4=y
975CONFIG_NFS_ACL_SUPPORT=y
976CONFIG_NFS_COMMON=y
977CONFIG_SUNRPC=y
978CONFIG_SUNRPC_GSS=y
979# CONFIG_SUNRPC_BIND34 is not set
980CONFIG_RPCSEC_GSS_KRB5=y
981# CONFIG_RPCSEC_GSS_SPKM3 is not set
982# CONFIG_SMB_FS is not set
983# CONFIG_CIFS is not set
984# CONFIG_NCP_FS is not set
985# CONFIG_CODA_FS is not set
986# CONFIG_AFS_FS is not set
987
988#
989# Partition Types
990#
991# CONFIG_PARTITION_ADVANCED is not set
992CONFIG_MSDOS_PARTITION=y
993CONFIG_NLS=y
994CONFIG_NLS_DEFAULT="iso8859-1"
995CONFIG_NLS_CODEPAGE_437=y
996# CONFIG_NLS_CODEPAGE_737 is not set
997# CONFIG_NLS_CODEPAGE_775 is not set
998CONFIG_NLS_CODEPAGE_850=y
999# CONFIG_NLS_CODEPAGE_852 is not set
1000# CONFIG_NLS_CODEPAGE_855 is not set
1001# CONFIG_NLS_CODEPAGE_857 is not set
1002# CONFIG_NLS_CODEPAGE_860 is not set
1003# CONFIG_NLS_CODEPAGE_861 is not set
1004# CONFIG_NLS_CODEPAGE_862 is not set
1005# CONFIG_NLS_CODEPAGE_863 is not set
1006# CONFIG_NLS_CODEPAGE_864 is not set
1007# CONFIG_NLS_CODEPAGE_865 is not set
1008# CONFIG_NLS_CODEPAGE_866 is not set
1009# CONFIG_NLS_CODEPAGE_869 is not set
1010# CONFIG_NLS_CODEPAGE_936 is not set
1011# CONFIG_NLS_CODEPAGE_950 is not set
1012# CONFIG_NLS_CODEPAGE_932 is not set
1013# CONFIG_NLS_CODEPAGE_949 is not set
1014# CONFIG_NLS_CODEPAGE_874 is not set
1015# CONFIG_NLS_ISO8859_8 is not set
1016# CONFIG_NLS_CODEPAGE_1250 is not set
1017# CONFIG_NLS_CODEPAGE_1251 is not set
1018# CONFIG_NLS_ASCII is not set
1019CONFIG_NLS_ISO8859_1=y
1020# CONFIG_NLS_ISO8859_2 is not set
1021# CONFIG_NLS_ISO8859_3 is not set
1022# CONFIG_NLS_ISO8859_4 is not set
1023# CONFIG_NLS_ISO8859_5 is not set
1024# CONFIG_NLS_ISO8859_6 is not set
1025# CONFIG_NLS_ISO8859_7 is not set
1026# CONFIG_NLS_ISO8859_9 is not set
1027# CONFIG_NLS_ISO8859_13 is not set
1028# CONFIG_NLS_ISO8859_14 is not set
1029# CONFIG_NLS_ISO8859_15 is not set
1030# CONFIG_NLS_KOI8_R is not set
1031# CONFIG_NLS_KOI8_U is not set
1032# CONFIG_NLS_UTF8 is not set
1033# CONFIG_DLM is not set
1034# CONFIG_INSTRUMENTATION is not set
1035
1036#
1037# Kernel hacking
1038#
1039# CONFIG_PRINTK_TIME is not set
1040CONFIG_ENABLE_WARN_DEPRECATED=y
1041CONFIG_ENABLE_MUST_CHECK=y
1042# CONFIG_MAGIC_SYSRQ is not set
1043# CONFIG_UNUSED_SYMBOLS is not set
1044# CONFIG_DEBUG_FS is not set
1045# CONFIG_HEADERS_CHECK is not set
1046CONFIG_DEBUG_KERNEL=y
1047# CONFIG_DEBUG_SHIRQ is not set
1048CONFIG_DETECT_SOFTLOCKUP=y
1049CONFIG_SCHED_DEBUG=y
1050# CONFIG_SCHEDSTATS is not set
1051# CONFIG_TIMER_STATS is not set
1052# CONFIG_DEBUG_SLAB is not set
1053# CONFIG_DEBUG_RT_MUTEXES is not set
1054# CONFIG_RT_MUTEX_TESTER is not set
1055# CONFIG_DEBUG_SPINLOCK is not set
1056# CONFIG_DEBUG_MUTEXES is not set
1057# CONFIG_DEBUG_LOCK_ALLOC is not set
1058# CONFIG_PROVE_LOCKING is not set
1059# CONFIG_LOCK_STAT is not set
1060# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1061# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1062# CONFIG_DEBUG_KOBJECT is not set
1063CONFIG_DEBUG_BUGVERBOSE=y
1064# CONFIG_DEBUG_INFO is not set
1065# CONFIG_DEBUG_VM is not set
1066# CONFIG_DEBUG_LIST is not set
1067# CONFIG_DEBUG_SG is not set
1068CONFIG_FRAME_POINTER=y
1069CONFIG_FORCED_INLINING=y
1070# CONFIG_BOOT_PRINTK_DELAY is not set
1071# CONFIG_RCU_TORTURE_TEST is not set
1072# CONFIG_FAULT_INJECTION is not set
1073# CONFIG_SAMPLES is not set
1074CONFIG_DEBUG_USER=y
1075# CONFIG_DEBUG_ERRORS is not set
1076CONFIG_DEBUG_LL=y
1077# CONFIG_DEBUG_ICEDCC is not set
1078
1079#
1080# Security options
1081#
1082# CONFIG_KEYS is not set
1083# CONFIG_SECURITY is not set
1084# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1085CONFIG_CRYPTO=y
1086CONFIG_CRYPTO_ALGAPI=y
1087CONFIG_CRYPTO_BLKCIPHER=y
1088CONFIG_CRYPTO_MANAGER=y
1089# CONFIG_CRYPTO_HMAC is not set
1090# CONFIG_CRYPTO_XCBC is not set
1091# CONFIG_CRYPTO_NULL is not set
1092# CONFIG_CRYPTO_MD4 is not set
1093CONFIG_CRYPTO_MD5=y
1094# CONFIG_CRYPTO_SHA1 is not set
1095# CONFIG_CRYPTO_SHA256 is not set
1096# CONFIG_CRYPTO_SHA512 is not set
1097# CONFIG_CRYPTO_WP512 is not set
1098# CONFIG_CRYPTO_TGR192 is not set
1099# CONFIG_CRYPTO_GF128MUL is not set
1100# CONFIG_CRYPTO_ECB is not set
1101CONFIG_CRYPTO_CBC=y
1102# CONFIG_CRYPTO_PCBC is not set
1103# CONFIG_CRYPTO_LRW is not set
1104# CONFIG_CRYPTO_XTS is not set
1105# CONFIG_CRYPTO_CRYPTD is not set
1106CONFIG_CRYPTO_DES=y
1107# CONFIG_CRYPTO_FCRYPT is not set
1108# CONFIG_CRYPTO_BLOWFISH is not set
1109# CONFIG_CRYPTO_TWOFISH is not set
1110# CONFIG_CRYPTO_SERPENT is not set
1111# CONFIG_CRYPTO_AES is not set
1112# CONFIG_CRYPTO_CAST5 is not set
1113# CONFIG_CRYPTO_CAST6 is not set
1114# CONFIG_CRYPTO_TEA is not set
1115# CONFIG_CRYPTO_ARC4 is not set
1116# CONFIG_CRYPTO_KHAZAD is not set
1117# CONFIG_CRYPTO_ANUBIS is not set
1118# CONFIG_CRYPTO_SEED is not set
1119# CONFIG_CRYPTO_DEFLATE is not set
1120# CONFIG_CRYPTO_MICHAEL_MIC is not set
1121# CONFIG_CRYPTO_CRC32C is not set
1122# CONFIG_CRYPTO_CAMELLIA is not set
1123# CONFIG_CRYPTO_TEST is not set
1124# CONFIG_CRYPTO_AUTHENC is not set
1125# CONFIG_CRYPTO_HW is not set
1126
1127#
1128# Library routines
1129#
1130CONFIG_BITREVERSE=y
1131# CONFIG_CRC_CCITT is not set
1132# CONFIG_CRC16 is not set
1133# CONFIG_CRC_ITU_T is not set
1134CONFIG_CRC32=y
1135# CONFIG_CRC7 is not set
1136# CONFIG_LIBCRC32C is not set
1137CONFIG_ZLIB_INFLATE=y
1138CONFIG_ZLIB_DEFLATE=y
1139CONFIG_PLIST=y
1140CONFIG_HAS_IOMEM=y
1141CONFIG_HAS_IOPORT=y
1142CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/usb-a9263_defconfig b/arch/arm/configs/usb-a9263_defconfig
new file mode 100644
index 000000000000..48d455bc7363
--- /dev/null
+++ b/arch/arm/configs/usb-a9263_defconfig
@@ -0,0 +1,1134 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.24
4# Tue Apr 15 11:15:19 2008
5#
6CONFIG_ARM=y
7CONFIG_SYS_SUPPORTS_APM_EMULATION=y
8CONFIG_GENERIC_GPIO=y
9CONFIG_GENERIC_TIME=y
10CONFIG_GENERIC_CLOCKEVENTS=y
11CONFIG_MMU=y
12# CONFIG_NO_IOPORT is not set
13CONFIG_GENERIC_HARDIRQS=y
14CONFIG_STACKTRACE_SUPPORT=y
15CONFIG_LOCKDEP_SUPPORT=y
16CONFIG_TRACE_IRQFLAGS_SUPPORT=y
17CONFIG_HARDIRQS_SW_RESEND=y
18CONFIG_GENERIC_IRQ_PROBE=y
19CONFIG_RWSEM_GENERIC_SPINLOCK=y
20# CONFIG_ARCH_HAS_ILOG2_U32 is not set
21# CONFIG_ARCH_HAS_ILOG2_U64 is not set
22CONFIG_GENERIC_HWEIGHT=y
23CONFIG_GENERIC_CALIBRATE_DELAY=y
24CONFIG_ZONE_DMA=y
25CONFIG_VECTORS_BASE=0xffff0000
26CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
27
28#
29# General setup
30#
31CONFIG_EXPERIMENTAL=y
32CONFIG_BROKEN_ON_SMP=y
33CONFIG_INIT_ENV_ARG_LIMIT=32
34CONFIG_LOCALVERSION=""
35# CONFIG_LOCALVERSION_AUTO is not set
36# CONFIG_SWAP is not set
37CONFIG_SYSVIPC=y
38CONFIG_SYSVIPC_SYSCTL=y
39# CONFIG_POSIX_MQUEUE is not set
40# CONFIG_BSD_PROCESS_ACCT is not set
41# CONFIG_TASKSTATS is not set
42# CONFIG_USER_NS is not set
43# CONFIG_PID_NS is not set
44# CONFIG_AUDIT is not set
45# CONFIG_IKCONFIG is not set
46CONFIG_LOG_BUF_SHIFT=14
47# CONFIG_CGROUPS is not set
48CONFIG_FAIR_GROUP_SCHED=y
49CONFIG_FAIR_USER_SCHED=y
50# CONFIG_FAIR_CGROUP_SCHED is not set
51# CONFIG_SYSFS_DEPRECATED is not set
52# CONFIG_RELAY is not set
53# CONFIG_BLK_DEV_INITRD is not set
54# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
55CONFIG_SYSCTL=y
56# CONFIG_EMBEDDED is not set
57CONFIG_UID16=y
58CONFIG_SYSCTL_SYSCALL=y
59CONFIG_KALLSYMS=y
60# CONFIG_KALLSYMS_ALL is not set
61# CONFIG_KALLSYMS_EXTRA_PASS is not set
62CONFIG_HOTPLUG=y
63CONFIG_PRINTK=y
64CONFIG_BUG=y
65CONFIG_ELF_CORE=y
66CONFIG_BASE_FULL=y
67CONFIG_FUTEX=y
68CONFIG_ANON_INODES=y
69CONFIG_EPOLL=y
70CONFIG_SIGNALFD=y
71CONFIG_EVENTFD=y
72CONFIG_SHMEM=y
73CONFIG_VM_EVENT_COUNTERS=y
74CONFIG_SLAB=y
75# CONFIG_SLUB is not set
76# CONFIG_SLOB is not set
77CONFIG_SLABINFO=y
78CONFIG_RT_MUTEXES=y
79# CONFIG_TINY_SHMEM is not set
80CONFIG_BASE_SMALL=0
81CONFIG_MODULES=y
82CONFIG_MODULE_UNLOAD=y
83# CONFIG_MODULE_FORCE_UNLOAD is not set
84# CONFIG_MODVERSIONS is not set
85# CONFIG_MODULE_SRCVERSION_ALL is not set
86CONFIG_KMOD=y
87CONFIG_BLOCK=y
88# CONFIG_LBD is not set
89# CONFIG_BLK_DEV_IO_TRACE is not set
90# CONFIG_LSF is not set
91# CONFIG_BLK_DEV_BSG is not set
92
93#
94# IO Schedulers
95#
96CONFIG_IOSCHED_NOOP=y
97CONFIG_IOSCHED_AS=y
98# CONFIG_IOSCHED_DEADLINE is not set
99# CONFIG_IOSCHED_CFQ is not set
100CONFIG_DEFAULT_AS=y
101# CONFIG_DEFAULT_DEADLINE is not set
102# CONFIG_DEFAULT_CFQ is not set
103# CONFIG_DEFAULT_NOOP is not set
104CONFIG_DEFAULT_IOSCHED="anticipatory"
105
106#
107# System Type
108#
109# CONFIG_ARCH_AAEC2000 is not set
110# CONFIG_ARCH_INTEGRATOR is not set
111# CONFIG_ARCH_REALVIEW is not set
112# CONFIG_ARCH_VERSATILE is not set
113CONFIG_ARCH_AT91=y
114# CONFIG_ARCH_CLPS7500 is not set
115# CONFIG_ARCH_CLPS711X is not set
116# CONFIG_ARCH_CO285 is not set
117# CONFIG_ARCH_EBSA110 is not set
118# CONFIG_ARCH_EP93XX is not set
119# CONFIG_ARCH_FOOTBRIDGE is not set
120# CONFIG_ARCH_NETX is not set
121# CONFIG_ARCH_H720X is not set
122# CONFIG_ARCH_IMX is not set
123# CONFIG_ARCH_IOP13XX is not set
124# CONFIG_ARCH_IOP32X is not set
125# CONFIG_ARCH_IOP33X is not set
126# CONFIG_ARCH_IXP23XX is not set
127# CONFIG_ARCH_IXP2000 is not set
128# CONFIG_ARCH_IXP4XX is not set
129# CONFIG_ARCH_L7200 is not set
130# CONFIG_ARCH_KS8695 is not set
131# CONFIG_ARCH_NS9XXX is not set
132# CONFIG_ARCH_MXC is not set
133# CONFIG_ARCH_PNX4008 is not set
134# CONFIG_ARCH_PXA is not set
135# CONFIG_ARCH_RPC is not set
136# CONFIG_ARCH_SA1100 is not set
137# CONFIG_ARCH_S3C2410 is not set
138# CONFIG_ARCH_SHARK is not set
139# CONFIG_ARCH_LH7A40X is not set
140# CONFIG_ARCH_DAVINCI is not set
141# CONFIG_ARCH_OMAP is not set
142
143#
144# Boot options
145#
146
147#
148# Power management
149#
150
151#
152# Atmel AT91 System-on-Chip
153#
154# CONFIG_ARCH_AT91RM9200 is not set
155# CONFIG_ARCH_AT91SAM9260 is not set
156# CONFIG_ARCH_AT91SAM9261 is not set
157CONFIG_ARCH_AT91SAM9263=y
158# CONFIG_ARCH_AT91SAM9RL is not set
159# CONFIG_ARCH_AT91CAP9 is not set
160# CONFIG_ARCH_AT91X40 is not set
161CONFIG_AT91_PMC_UNIT=y
162
163#
164# AT91SAM9263 Board Type
165#
166# CONFIG_MACH_AT91SAM9263EK is not set
167CONFIG_MACH_USB_A9263=y
168
169#
170# AT91 Board Options
171#
172
173#
174# AT91 Feature Selections
175#
176# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
177CONFIG_AT91_SLOW_CLOCK=y
178CONFIG_AT91_TIMER_HZ=100
179CONFIG_AT91_EARLY_DBGU=y
180# CONFIG_AT91_EARLY_USART0 is not set
181# CONFIG_AT91_EARLY_USART1 is not set
182# CONFIG_AT91_EARLY_USART2 is not set
183# CONFIG_AT91_EARLY_USART3 is not set
184# CONFIG_AT91_EARLY_USART4 is not set
185# CONFIG_AT91_EARLY_USART5 is not set
186
187#
188# Processor Type
189#
190CONFIG_CPU_32=y
191CONFIG_CPU_ARM926T=y
192CONFIG_CPU_32v5=y
193CONFIG_CPU_ABRT_EV5TJ=y
194CONFIG_CPU_CACHE_VIVT=y
195CONFIG_CPU_COPY_V4WB=y
196CONFIG_CPU_TLB_V4WBI=y
197CONFIG_CPU_CP15=y
198CONFIG_CPU_CP15_MMU=y
199
200#
201# Processor Features
202#
203# CONFIG_ARM_THUMB is not set
204# CONFIG_CPU_ICACHE_DISABLE is not set
205# CONFIG_CPU_DCACHE_DISABLE is not set
206# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
207# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
208# CONFIG_OUTER_CACHE is not set
209
210#
211# Bus support
212#
213# CONFIG_PCI_SYSCALL is not set
214# CONFIG_ARCH_SUPPORTS_MSI is not set
215# CONFIG_PCCARD is not set
216
217#
218# Kernel Features
219#
220# CONFIG_TICK_ONESHOT is not set
221# CONFIG_NO_HZ is not set
222# CONFIG_HIGH_RES_TIMERS is not set
223CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
224# CONFIG_PREEMPT is not set
225CONFIG_HZ=100
226CONFIG_AEABI=y
227CONFIG_OABI_COMPAT=y
228# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
229CONFIG_SELECT_MEMORY_MODEL=y
230CONFIG_FLATMEM_MANUAL=y
231# CONFIG_DISCONTIGMEM_MANUAL is not set
232# CONFIG_SPARSEMEM_MANUAL is not set
233CONFIG_FLATMEM=y
234CONFIG_FLAT_NODE_MEM_MAP=y
235# CONFIG_SPARSEMEM_STATIC is not set
236# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
237CONFIG_SPLIT_PTLOCK_CPUS=4096
238# CONFIG_RESOURCES_64BIT is not set
239CONFIG_ZONE_DMA_FLAG=1
240CONFIG_BOUNCE=y
241CONFIG_VIRT_TO_BUS=y
242# CONFIG_LEDS is not set
243CONFIG_ALIGNMENT_TRAP=y
244
245#
246# Boot options
247#
248CONFIG_ZBOOT_ROM_TEXT=0x0
249CONFIG_ZBOOT_ROM_BSS=0x0
250CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
251# CONFIG_XIP_KERNEL is not set
252# CONFIG_KEXEC is not set
253
254#
255# Floating point emulation
256#
257
258#
259# At least one emulation must be selected
260#
261CONFIG_FPE_NWFPE=y
262# CONFIG_FPE_NWFPE_XP is not set
263# CONFIG_FPE_FASTFPE is not set
264# CONFIG_VFP is not set
265
266#
267# Userspace binary formats
268#
269CONFIG_BINFMT_ELF=y
270# CONFIG_BINFMT_AOUT is not set
271# CONFIG_BINFMT_MISC is not set
272
273#
274# Power management options
275#
276CONFIG_PM=y
277# CONFIG_PM_LEGACY is not set
278# CONFIG_PM_DEBUG is not set
279CONFIG_PM_SLEEP=y
280CONFIG_SUSPEND_UP_POSSIBLE=y
281CONFIG_SUSPEND=y
282# CONFIG_APM_EMULATION is not set
283
284#
285# Networking
286#
287CONFIG_NET=y
288
289#
290# Networking options
291#
292CONFIG_PACKET=y
293# CONFIG_PACKET_MMAP is not set
294CONFIG_UNIX=y
295# CONFIG_NET_KEY is not set
296CONFIG_INET=y
297CONFIG_IP_MULTICAST=y
298CONFIG_IP_ADVANCED_ROUTER=y
299CONFIG_ASK_IP_FIB_HASH=y
300# CONFIG_IP_FIB_TRIE is not set
301CONFIG_IP_FIB_HASH=y
302# CONFIG_IP_MULTIPLE_TABLES is not set
303# CONFIG_IP_ROUTE_MULTIPATH is not set
304CONFIG_IP_ROUTE_VERBOSE=y
305CONFIG_IP_PNP=y
306# CONFIG_IP_PNP_DHCP is not set
307CONFIG_IP_PNP_BOOTP=y
308CONFIG_IP_PNP_RARP=y
309# CONFIG_NET_IPIP is not set
310# CONFIG_NET_IPGRE is not set
311CONFIG_IP_MROUTE=y
312CONFIG_IP_PIMSM_V1=y
313CONFIG_IP_PIMSM_V2=y
314# CONFIG_ARPD is not set
315# CONFIG_SYN_COOKIES is not set
316# CONFIG_INET_AH is not set
317# CONFIG_INET_ESP is not set
318# CONFIG_INET_IPCOMP is not set
319# CONFIG_INET_XFRM_TUNNEL is not set
320# CONFIG_INET_TUNNEL is not set
321# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
322# CONFIG_INET_XFRM_MODE_TUNNEL is not set
323# CONFIG_INET_XFRM_MODE_BEET is not set
324# CONFIG_INET_LRO is not set
325# CONFIG_INET_DIAG is not set
326# CONFIG_TCP_CONG_ADVANCED is not set
327CONFIG_TCP_CONG_CUBIC=y
328CONFIG_DEFAULT_TCP_CONG="cubic"
329# CONFIG_TCP_MD5SIG is not set
330# CONFIG_IPV6 is not set
331# CONFIG_INET6_XFRM_TUNNEL is not set
332# CONFIG_INET6_TUNNEL is not set
333# CONFIG_NETWORK_SECMARK is not set
334# CONFIG_NETFILTER is not set
335# CONFIG_IP_DCCP is not set
336# CONFIG_IP_SCTP is not set
337# CONFIG_TIPC is not set
338# CONFIG_ATM is not set
339# CONFIG_BRIDGE is not set
340# CONFIG_VLAN_8021Q is not set
341# CONFIG_DECNET is not set
342# CONFIG_LLC2 is not set
343# CONFIG_IPX is not set
344# CONFIG_ATALK is not set
345# CONFIG_X25 is not set
346# CONFIG_LAPB is not set
347# CONFIG_ECONET is not set
348# CONFIG_WAN_ROUTER is not set
349# CONFIG_NET_SCHED is not set
350
351#
352# Network testing
353#
354# CONFIG_NET_PKTGEN is not set
355# CONFIG_HAMRADIO is not set
356# CONFIG_IRDA is not set
357# CONFIG_BT is not set
358# CONFIG_AF_RXRPC is not set
359
360#
361# Wireless
362#
363# CONFIG_CFG80211 is not set
364# CONFIG_WIRELESS_EXT is not set
365# CONFIG_MAC80211 is not set
366# CONFIG_IEEE80211 is not set
367# CONFIG_RFKILL is not set
368# CONFIG_NET_9P is not set
369
370#
371# Device Drivers
372#
373
374#
375# Generic Driver Options
376#
377CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
378CONFIG_STANDALONE=y
379CONFIG_PREVENT_FIRMWARE_BUILD=y
380# CONFIG_FW_LOADER is not set
381# CONFIG_DEBUG_DRIVER is not set
382# CONFIG_DEBUG_DEVRES is not set
383# CONFIG_SYS_HYPERVISOR is not set
384# CONFIG_CONNECTOR is not set
385CONFIG_MTD=y
386# CONFIG_MTD_DEBUG is not set
387# CONFIG_MTD_CONCAT is not set
388CONFIG_MTD_PARTITIONS=y
389# CONFIG_MTD_REDBOOT_PARTS is not set
390CONFIG_MTD_CMDLINE_PARTS=y
391# CONFIG_MTD_AFS_PARTS is not set
392
393#
394# User Modules And Translation Layers
395#
396CONFIG_MTD_CHAR=y
397CONFIG_MTD_BLKDEVS=y
398CONFIG_MTD_BLOCK=y
399# CONFIG_FTL is not set
400# CONFIG_NFTL is not set
401# CONFIG_INFTL is not set
402# CONFIG_RFD_FTL is not set
403# CONFIG_SSFDC is not set
404# CONFIG_MTD_OOPS is not set
405
406#
407# RAM/ROM/Flash chip drivers
408#
409# CONFIG_MTD_CFI is not set
410# CONFIG_MTD_JEDECPROBE is not set
411CONFIG_MTD_MAP_BANK_WIDTH_1=y
412CONFIG_MTD_MAP_BANK_WIDTH_2=y
413CONFIG_MTD_MAP_BANK_WIDTH_4=y
414# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
415# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
416# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
417CONFIG_MTD_CFI_I1=y
418CONFIG_MTD_CFI_I2=y
419# CONFIG_MTD_CFI_I4 is not set
420# CONFIG_MTD_CFI_I8 is not set
421# CONFIG_MTD_RAM is not set
422# CONFIG_MTD_ROM is not set
423# CONFIG_MTD_ABSENT is not set
424
425#
426# Mapping drivers for chip access
427#
428# CONFIG_MTD_COMPLEX_MAPPINGS is not set
429# CONFIG_MTD_PLATRAM is not set
430
431#
432# Self-contained MTD device drivers
433#
434CONFIG_MTD_DATAFLASH=y
435# CONFIG_MTD_M25P80 is not set
436# CONFIG_MTD_SLRAM is not set
437# CONFIG_MTD_PHRAM is not set
438# CONFIG_MTD_MTDRAM is not set
439# CONFIG_MTD_BLOCK2MTD is not set
440
441#
442# Disk-On-Chip Device Drivers
443#
444# CONFIG_MTD_DOC2000 is not set
445# CONFIG_MTD_DOC2001 is not set
446# CONFIG_MTD_DOC2001PLUS is not set
447CONFIG_MTD_NAND=y
448# CONFIG_MTD_NAND_VERIFY_WRITE is not set
449# CONFIG_MTD_NAND_ECC_SMC is not set
450# CONFIG_MTD_NAND_MUSEUM_IDS is not set
451CONFIG_MTD_NAND_IDS=y
452# CONFIG_MTD_NAND_DISKONCHIP is not set
453CONFIG_MTD_NAND_AT91=y
454CONFIG_MTD_NAND_AT91_ECC_SOFT=y
455# CONFIG_MTD_NAND_AT91_ECC_HW is not set
456# CONFIG_MTD_NAND_AT91_ECC_NONE is not set
457# CONFIG_MTD_NAND_NANDSIM is not set
458# CONFIG_MTD_NAND_PLATFORM is not set
459# CONFIG_MTD_ALAUDA is not set
460# CONFIG_MTD_ONENAND is not set
461
462#
463# UBI - Unsorted block images
464#
465# CONFIG_MTD_UBI is not set
466# CONFIG_PARPORT is not set
467CONFIG_BLK_DEV=y
468# CONFIG_BLK_DEV_COW_COMMON is not set
469CONFIG_BLK_DEV_LOOP=y
470# CONFIG_BLK_DEV_CRYPTOLOOP is not set
471# CONFIG_BLK_DEV_NBD is not set
472# CONFIG_BLK_DEV_UB is not set
473# CONFIG_BLK_DEV_RAM is not set
474# CONFIG_CDROM_PKTCDVD is not set
475# CONFIG_ATA_OVER_ETH is not set
476# CONFIG_MISC_DEVICES is not set
477
478#
479# SCSI device support
480#
481# CONFIG_RAID_ATTRS is not set
482CONFIG_SCSI=y
483CONFIG_SCSI_DMA=y
484# CONFIG_SCSI_TGT is not set
485# CONFIG_SCSI_NETLINK is not set
486CONFIG_SCSI_PROC_FS=y
487
488#
489# SCSI support type (disk, tape, CD-ROM)
490#
491CONFIG_BLK_DEV_SD=y
492# CONFIG_CHR_DEV_ST is not set
493# CONFIG_CHR_DEV_OSST is not set
494# CONFIG_BLK_DEV_SR is not set
495# CONFIG_CHR_DEV_SG is not set
496# CONFIG_CHR_DEV_SCH is not set
497
498#
499# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
500#
501CONFIG_SCSI_MULTI_LUN=y
502# CONFIG_SCSI_CONSTANTS is not set
503# CONFIG_SCSI_LOGGING is not set
504# CONFIG_SCSI_SCAN_ASYNC is not set
505CONFIG_SCSI_WAIT_SCAN=m
506
507#
508# SCSI Transports
509#
510# CONFIG_SCSI_SPI_ATTRS is not set
511# CONFIG_SCSI_FC_ATTRS is not set
512# CONFIG_SCSI_ISCSI_ATTRS is not set
513# CONFIG_SCSI_SAS_LIBSAS is not set
514# CONFIG_SCSI_SRP_ATTRS is not set
515CONFIG_SCSI_LOWLEVEL=y
516# CONFIG_ISCSI_TCP is not set
517# CONFIG_SCSI_DEBUG is not set
518# CONFIG_ATA is not set
519# CONFIG_MD is not set
520CONFIG_NETDEVICES=y
521# CONFIG_NETDEVICES_MULTIQUEUE is not set
522# CONFIG_DUMMY is not set
523# CONFIG_BONDING is not set
524# CONFIG_MACVLAN is not set
525# CONFIG_EQUALIZER is not set
526# CONFIG_TUN is not set
527# CONFIG_VETH is not set
528CONFIG_PHYLIB=y
529
530#
531# MII PHY device drivers
532#
533# CONFIG_MARVELL_PHY is not set
534# CONFIG_DAVICOM_PHY is not set
535# CONFIG_QSEMI_PHY is not set
536# CONFIG_LXT_PHY is not set
537# CONFIG_CICADA_PHY is not set
538# CONFIG_VITESSE_PHY is not set
539# CONFIG_SMSC_PHY is not set
540# CONFIG_BROADCOM_PHY is not set
541# CONFIG_ICPLUS_PHY is not set
542# CONFIG_FIXED_PHY is not set
543# CONFIG_MDIO_BITBANG is not set
544CONFIG_NET_ETHERNET=y
545CONFIG_MII=y
546CONFIG_MACB=y
547# CONFIG_AX88796 is not set
548# CONFIG_SMC91X is not set
549# CONFIG_DM9000 is not set
550# CONFIG_IBM_NEW_EMAC_ZMII is not set
551# CONFIG_IBM_NEW_EMAC_RGMII is not set
552# CONFIG_IBM_NEW_EMAC_TAH is not set
553# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
554# CONFIG_B44 is not set
555CONFIG_NETDEV_1000=y
556CONFIG_NETDEV_10000=y
557
558#
559# Wireless LAN
560#
561# CONFIG_WLAN_PRE80211 is not set
562# CONFIG_WLAN_80211 is not set
563
564#
565# USB Network Adapters
566#
567# CONFIG_USB_CATC is not set
568# CONFIG_USB_KAWETH is not set
569# CONFIG_USB_PEGASUS is not set
570# CONFIG_USB_RTL8150 is not set
571# CONFIG_USB_USBNET is not set
572# CONFIG_WAN is not set
573# CONFIG_PPP is not set
574# CONFIG_SLIP is not set
575# CONFIG_SHAPER is not set
576# CONFIG_NETCONSOLE is not set
577# CONFIG_NETPOLL is not set
578# CONFIG_NET_POLL_CONTROLLER is not set
579# CONFIG_ISDN is not set
580
581#
582# Input device support
583#
584CONFIG_INPUT=y
585# CONFIG_INPUT_FF_MEMLESS is not set
586# CONFIG_INPUT_POLLDEV is not set
587
588#
589# Userland interfaces
590#
591CONFIG_INPUT_MOUSEDEV=y
592# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
593CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
594CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
595# CONFIG_INPUT_JOYDEV is not set
596CONFIG_INPUT_EVDEV=y
597CONFIG_INPUT_EVBUG=y
598
599#
600# Input Device Drivers
601#
602CONFIG_INPUT_KEYBOARD=y
603# CONFIG_KEYBOARD_ATKBD is not set
604# CONFIG_KEYBOARD_SUNKBD is not set
605# CONFIG_KEYBOARD_LKKBD is not set
606# CONFIG_KEYBOARD_XTKBD is not set
607# CONFIG_KEYBOARD_NEWTON is not set
608# CONFIG_KEYBOARD_STOWAWAY is not set
609CONFIG_KEYBOARD_GPIO=y
610# CONFIG_INPUT_MOUSE is not set
611# CONFIG_INPUT_JOYSTICK is not set
612# CONFIG_INPUT_TABLET is not set
613# CONFIG_INPUT_TOUCHSCREEN is not set
614# CONFIG_INPUT_MISC is not set
615
616#
617# Hardware I/O ports
618#
619# CONFIG_SERIO is not set
620# CONFIG_GAMEPORT is not set
621
622#
623# Character devices
624#
625CONFIG_VT=y
626CONFIG_VT_CONSOLE=y
627CONFIG_HW_CONSOLE=y
628# CONFIG_VT_HW_CONSOLE_BINDING is not set
629# CONFIG_SERIAL_NONSTANDARD is not set
630
631#
632# Serial drivers
633#
634# CONFIG_SERIAL_8250 is not set
635
636#
637# Non-8250 serial port support
638#
639CONFIG_SERIAL_ATMEL=y
640CONFIG_SERIAL_ATMEL_CONSOLE=y
641# CONFIG_SERIAL_ATMEL_TTYAT is not set
642CONFIG_SERIAL_CORE=y
643CONFIG_SERIAL_CORE_CONSOLE=y
644CONFIG_UNIX98_PTYS=y
645CONFIG_LEGACY_PTYS=y
646CONFIG_LEGACY_PTY_COUNT=256
647# CONFIG_IPMI_HANDLER is not set
648CONFIG_HW_RANDOM=y
649# CONFIG_NVRAM is not set
650# CONFIG_R3964 is not set
651# CONFIG_RAW_DRIVER is not set
652# CONFIG_TCG_TPM is not set
653# CONFIG_I2C is not set
654
655#
656# SPI support
657#
658CONFIG_SPI=y
659# CONFIG_SPI_DEBUG is not set
660CONFIG_SPI_MASTER=y
661
662#
663# SPI Master Controller Drivers
664#
665CONFIG_SPI_ATMEL=y
666# CONFIG_SPI_BITBANG is not set
667
668#
669# SPI Protocol Masters
670#
671# CONFIG_SPI_AT25 is not set
672# CONFIG_SPI_SPIDEV is not set
673# CONFIG_SPI_TLE62X0 is not set
674# CONFIG_W1 is not set
675# CONFIG_POWER_SUPPLY is not set
676# CONFIG_HWMON is not set
677# CONFIG_WATCHDOG is not set
678
679#
680# Sonics Silicon Backplane
681#
682CONFIG_SSB_POSSIBLE=y
683# CONFIG_SSB is not set
684
685#
686# Multifunction device drivers
687#
688# CONFIG_MFD_SM501 is not set
689
690#
691# Multimedia devices
692#
693# CONFIG_VIDEO_DEV is not set
694# CONFIG_DVB_CORE is not set
695# CONFIG_DAB is not set
696
697#
698# Graphics support
699#
700# CONFIG_VGASTATE is not set
701# CONFIG_VIDEO_OUTPUT_CONTROL is not set
702# CONFIG_FB is not set
703# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
704
705#
706# Display device support
707#
708# CONFIG_DISPLAY_SUPPORT is not set
709
710#
711# Console display driver support
712#
713# CONFIG_VGA_CONSOLE is not set
714CONFIG_DUMMY_CONSOLE=y
715
716#
717# Sound
718#
719# CONFIG_SOUND is not set
720CONFIG_HID_SUPPORT=y
721CONFIG_HID=y
722# CONFIG_HID_DEBUG is not set
723# CONFIG_HIDRAW is not set
724
725#
726# USB Input Devices
727#
728# CONFIG_USB_HID is not set
729
730#
731# USB HID Boot Protocol drivers
732#
733# CONFIG_USB_KBD is not set
734# CONFIG_USB_MOUSE is not set
735CONFIG_USB_SUPPORT=y
736CONFIG_USB_ARCH_HAS_HCD=y
737CONFIG_USB_ARCH_HAS_OHCI=y
738# CONFIG_USB_ARCH_HAS_EHCI is not set
739CONFIG_USB=y
740# CONFIG_USB_DEBUG is not set
741
742#
743# Miscellaneous USB options
744#
745CONFIG_USB_DEVICEFS=y
746CONFIG_USB_DEVICE_CLASS=y
747# CONFIG_USB_DYNAMIC_MINORS is not set
748# CONFIG_USB_SUSPEND is not set
749# CONFIG_USB_PERSIST is not set
750# CONFIG_USB_OTG is not set
751
752#
753# USB Host Controller Drivers
754#
755# CONFIG_USB_ISP116X_HCD is not set
756CONFIG_USB_OHCI_HCD=y
757# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
758# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
759CONFIG_USB_OHCI_LITTLE_ENDIAN=y
760# CONFIG_USB_SL811_HCD is not set
761# CONFIG_USB_R8A66597_HCD is not set
762
763#
764# USB Device Class drivers
765#
766# CONFIG_USB_ACM is not set
767# CONFIG_USB_PRINTER is not set
768
769#
770# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
771#
772
773#
774# may also be needed; see USB_STORAGE Help for more information
775#
776CONFIG_USB_STORAGE=y
777# CONFIG_USB_STORAGE_DEBUG is not set
778# CONFIG_USB_STORAGE_DATAFAB is not set
779# CONFIG_USB_STORAGE_FREECOM is not set
780# CONFIG_USB_STORAGE_ISD200 is not set
781# CONFIG_USB_STORAGE_DPCM is not set
782# CONFIG_USB_STORAGE_USBAT is not set
783# CONFIG_USB_STORAGE_SDDR09 is not set
784# CONFIG_USB_STORAGE_SDDR55 is not set
785# CONFIG_USB_STORAGE_JUMPSHOT is not set
786# CONFIG_USB_STORAGE_ALAUDA is not set
787# CONFIG_USB_STORAGE_KARMA is not set
788# CONFIG_USB_LIBUSUAL is not set
789
790#
791# USB Imaging devices
792#
793# CONFIG_USB_MDC800 is not set
794# CONFIG_USB_MICROTEK is not set
795CONFIG_USB_MON=y
796
797#
798# USB port drivers
799#
800
801#
802# USB Serial Converter support
803#
804# CONFIG_USB_SERIAL is not set
805
806#
807# USB Miscellaneous drivers
808#
809# CONFIG_USB_EMI62 is not set
810# CONFIG_USB_EMI26 is not set
811# CONFIG_USB_ADUTUX is not set
812# CONFIG_USB_AUERSWALD is not set
813# CONFIG_USB_RIO500 is not set
814# CONFIG_USB_LEGOTOWER is not set
815# CONFIG_USB_LCD is not set
816# CONFIG_USB_BERRY_CHARGE is not set
817# CONFIG_USB_LED is not set
818# CONFIG_USB_CYPRESS_CY7C63 is not set
819# CONFIG_USB_CYTHERM is not set
820# CONFIG_USB_PHIDGET is not set
821# CONFIG_USB_IDMOUSE is not set
822# CONFIG_USB_FTDI_ELAN is not set
823# CONFIG_USB_APPLEDISPLAY is not set
824# CONFIG_USB_LD is not set
825# CONFIG_USB_TRANCEVIBRATOR is not set
826# CONFIG_USB_IOWARRIOR is not set
827# CONFIG_USB_TEST is not set
828
829#
830# USB DSL modem support
831#
832
833#
834# USB Gadget Support
835#
836CONFIG_USB_GADGET=y
837# CONFIG_USB_GADGET_DEBUG is not set
838# CONFIG_USB_GADGET_DEBUG_FILES is not set
839CONFIG_USB_GADGET_SELECTED=y
840# CONFIG_USB_GADGET_AMD5536UDC is not set
841# CONFIG_USB_GADGET_ATMEL_USBA is not set
842# CONFIG_USB_GADGET_FSL_USB2 is not set
843# CONFIG_USB_GADGET_NET2280 is not set
844# CONFIG_USB_GADGET_PXA2XX is not set
845# CONFIG_USB_GADGET_M66592 is not set
846# CONFIG_USB_GADGET_GOKU is not set
847# CONFIG_USB_GADGET_LH7A40X is not set
848# CONFIG_USB_GADGET_OMAP is not set
849# CONFIG_USB_GADGET_S3C2410 is not set
850CONFIG_USB_GADGET_AT91=y
851CONFIG_USB_AT91=y
852# CONFIG_USB_GADGET_DUMMY_HCD is not set
853# CONFIG_USB_GADGET_DUALSPEED is not set
854# CONFIG_USB_ZERO is not set
855CONFIG_USB_ETH=y
856CONFIG_USB_ETH_RNDIS=y
857# CONFIG_USB_GADGETFS is not set
858# CONFIG_USB_FILE_STORAGE is not set
859# CONFIG_USB_G_SERIAL is not set
860# CONFIG_USB_MIDI_GADGET is not set
861# CONFIG_MMC is not set
862CONFIG_NEW_LEDS=y
863CONFIG_LEDS_CLASS=y
864
865#
866# LED drivers
867#
868CONFIG_LEDS_GPIO=y
869
870#
871# LED Triggers
872#
873CONFIG_LEDS_TRIGGERS=y
874# CONFIG_LEDS_TRIGGER_TIMER is not set
875CONFIG_LEDS_TRIGGER_HEARTBEAT=y
876CONFIG_RTC_LIB=y
877# CONFIG_RTC_CLASS is not set
878
879#
880# File systems
881#
882CONFIG_EXT2_FS=y
883# CONFIG_EXT2_FS_XATTR is not set
884# CONFIG_EXT2_FS_XIP is not set
885# CONFIG_EXT3_FS is not set
886# CONFIG_EXT4DEV_FS is not set
887# CONFIG_REISERFS_FS is not set
888# CONFIG_JFS_FS is not set
889CONFIG_FS_POSIX_ACL=y
890# CONFIG_XFS_FS is not set
891# CONFIG_GFS2_FS is not set
892# CONFIG_OCFS2_FS is not set
893# CONFIG_MINIX_FS is not set
894# CONFIG_ROMFS_FS is not set
895CONFIG_INOTIFY=y
896CONFIG_INOTIFY_USER=y
897# CONFIG_QUOTA is not set
898CONFIG_DNOTIFY=y
899# CONFIG_AUTOFS_FS is not set
900# CONFIG_AUTOFS4_FS is not set
901CONFIG_FUSE_FS=m
902
903#
904# CD-ROM/DVD Filesystems
905#
906# CONFIG_ISO9660_FS is not set
907# CONFIG_UDF_FS is not set
908
909#
910# DOS/FAT/NT Filesystems
911#
912CONFIG_FAT_FS=y
913# CONFIG_MSDOS_FS is not set
914CONFIG_VFAT_FS=y
915CONFIG_FAT_DEFAULT_CODEPAGE=437
916CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
917# CONFIG_NTFS_FS is not set
918
919#
920# Pseudo filesystems
921#
922CONFIG_PROC_FS=y
923CONFIG_PROC_SYSCTL=y
924CONFIG_SYSFS=y
925CONFIG_TMPFS=y
926# CONFIG_TMPFS_POSIX_ACL is not set
927# CONFIG_HUGETLB_PAGE is not set
928# CONFIG_CONFIGFS_FS is not set
929
930#
931# Miscellaneous filesystems
932#
933# CONFIG_ADFS_FS is not set
934# CONFIG_AFFS_FS is not set
935# CONFIG_HFS_FS is not set
936# CONFIG_HFSPLUS_FS is not set
937# CONFIG_BEFS_FS is not set
938# CONFIG_BFS_FS is not set
939# CONFIG_EFS_FS is not set
940CONFIG_JFFS2_FS=y
941CONFIG_JFFS2_FS_DEBUG=0
942CONFIG_JFFS2_FS_WRITEBUFFER=y
943# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
944# CONFIG_JFFS2_SUMMARY is not set
945# CONFIG_JFFS2_FS_XATTR is not set
946# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
947CONFIG_JFFS2_ZLIB=y
948# CONFIG_JFFS2_LZO is not set
949CONFIG_JFFS2_RTIME=y
950# CONFIG_JFFS2_RUBIN is not set
951# CONFIG_CRAMFS is not set
952# CONFIG_VXFS_FS is not set
953# CONFIG_HPFS_FS is not set
954# CONFIG_QNX4FS_FS is not set
955# CONFIG_SYSV_FS is not set
956# CONFIG_UFS_FS is not set
957CONFIG_NETWORK_FILESYSTEMS=y
958CONFIG_NFS_FS=y
959CONFIG_NFS_V3=y
960CONFIG_NFS_V3_ACL=y
961CONFIG_NFS_V4=y
962# CONFIG_NFS_DIRECTIO is not set
963# CONFIG_NFSD is not set
964CONFIG_ROOT_NFS=y
965CONFIG_LOCKD=y
966CONFIG_LOCKD_V4=y
967CONFIG_NFS_ACL_SUPPORT=y
968CONFIG_NFS_COMMON=y
969CONFIG_SUNRPC=y
970CONFIG_SUNRPC_GSS=y
971# CONFIG_SUNRPC_BIND34 is not set
972CONFIG_RPCSEC_GSS_KRB5=y
973# CONFIG_RPCSEC_GSS_SPKM3 is not set
974# CONFIG_SMB_FS is not set
975# CONFIG_CIFS is not set
976# CONFIG_NCP_FS is not set
977# CONFIG_CODA_FS is not set
978# CONFIG_AFS_FS is not set
979
980#
981# Partition Types
982#
983# CONFIG_PARTITION_ADVANCED is not set
984CONFIG_MSDOS_PARTITION=y
985CONFIG_NLS=y
986CONFIG_NLS_DEFAULT="iso8859-1"
987CONFIG_NLS_CODEPAGE_437=y
988# CONFIG_NLS_CODEPAGE_737 is not set
989# CONFIG_NLS_CODEPAGE_775 is not set
990CONFIG_NLS_CODEPAGE_850=y
991# CONFIG_NLS_CODEPAGE_852 is not set
992# CONFIG_NLS_CODEPAGE_855 is not set
993# CONFIG_NLS_CODEPAGE_857 is not set
994# CONFIG_NLS_CODEPAGE_860 is not set
995# CONFIG_NLS_CODEPAGE_861 is not set
996# CONFIG_NLS_CODEPAGE_862 is not set
997# CONFIG_NLS_CODEPAGE_863 is not set
998# CONFIG_NLS_CODEPAGE_864 is not set
999# CONFIG_NLS_CODEPAGE_865 is not set
1000# CONFIG_NLS_CODEPAGE_866 is not set
1001# CONFIG_NLS_CODEPAGE_869 is not set
1002# CONFIG_NLS_CODEPAGE_936 is not set
1003# CONFIG_NLS_CODEPAGE_950 is not set
1004# CONFIG_NLS_CODEPAGE_932 is not set
1005# CONFIG_NLS_CODEPAGE_949 is not set
1006# CONFIG_NLS_CODEPAGE_874 is not set
1007# CONFIG_NLS_ISO8859_8 is not set
1008# CONFIG_NLS_CODEPAGE_1250 is not set
1009# CONFIG_NLS_CODEPAGE_1251 is not set
1010# CONFIG_NLS_ASCII is not set
1011CONFIG_NLS_ISO8859_1=y
1012# CONFIG_NLS_ISO8859_2 is not set
1013# CONFIG_NLS_ISO8859_3 is not set
1014# CONFIG_NLS_ISO8859_4 is not set
1015# CONFIG_NLS_ISO8859_5 is not set
1016# CONFIG_NLS_ISO8859_6 is not set
1017# CONFIG_NLS_ISO8859_7 is not set
1018# CONFIG_NLS_ISO8859_9 is not set
1019# CONFIG_NLS_ISO8859_13 is not set
1020# CONFIG_NLS_ISO8859_14 is not set
1021# CONFIG_NLS_ISO8859_15 is not set
1022# CONFIG_NLS_KOI8_R is not set
1023# CONFIG_NLS_KOI8_U is not set
1024# CONFIG_NLS_UTF8 is not set
1025# CONFIG_DLM is not set
1026# CONFIG_INSTRUMENTATION is not set
1027
1028#
1029# Kernel hacking
1030#
1031# CONFIG_PRINTK_TIME is not set
1032CONFIG_ENABLE_WARN_DEPRECATED=y
1033CONFIG_ENABLE_MUST_CHECK=y
1034# CONFIG_MAGIC_SYSRQ is not set
1035# CONFIG_UNUSED_SYMBOLS is not set
1036# CONFIG_DEBUG_FS is not set
1037# CONFIG_HEADERS_CHECK is not set
1038CONFIG_DEBUG_KERNEL=y
1039# CONFIG_DEBUG_SHIRQ is not set
1040CONFIG_DETECT_SOFTLOCKUP=y
1041CONFIG_SCHED_DEBUG=y
1042# CONFIG_SCHEDSTATS is not set
1043# CONFIG_TIMER_STATS is not set
1044# CONFIG_DEBUG_SLAB is not set
1045# CONFIG_DEBUG_RT_MUTEXES is not set
1046# CONFIG_RT_MUTEX_TESTER is not set
1047# CONFIG_DEBUG_SPINLOCK is not set
1048# CONFIG_DEBUG_MUTEXES is not set
1049# CONFIG_DEBUG_LOCK_ALLOC is not set
1050# CONFIG_PROVE_LOCKING is not set
1051# CONFIG_LOCK_STAT is not set
1052# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
1053# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
1054# CONFIG_DEBUG_KOBJECT is not set
1055CONFIG_DEBUG_BUGVERBOSE=y
1056# CONFIG_DEBUG_INFO is not set
1057# CONFIG_DEBUG_VM is not set
1058# CONFIG_DEBUG_LIST is not set
1059# CONFIG_DEBUG_SG is not set
1060CONFIG_FRAME_POINTER=y
1061CONFIG_FORCED_INLINING=y
1062# CONFIG_BOOT_PRINTK_DELAY is not set
1063# CONFIG_RCU_TORTURE_TEST is not set
1064# CONFIG_FAULT_INJECTION is not set
1065# CONFIG_SAMPLES is not set
1066CONFIG_DEBUG_USER=y
1067# CONFIG_DEBUG_ERRORS is not set
1068CONFIG_DEBUG_LL=y
1069# CONFIG_DEBUG_ICEDCC is not set
1070
1071#
1072# Security options
1073#
1074# CONFIG_KEYS is not set
1075# CONFIG_SECURITY is not set
1076# CONFIG_SECURITY_FILE_CAPABILITIES is not set
1077CONFIG_CRYPTO=y
1078CONFIG_CRYPTO_ALGAPI=y
1079CONFIG_CRYPTO_BLKCIPHER=y
1080CONFIG_CRYPTO_MANAGER=y
1081# CONFIG_CRYPTO_HMAC is not set
1082# CONFIG_CRYPTO_XCBC is not set
1083# CONFIG_CRYPTO_NULL is not set
1084# CONFIG_CRYPTO_MD4 is not set
1085CONFIG_CRYPTO_MD5=y
1086# CONFIG_CRYPTO_SHA1 is not set
1087# CONFIG_CRYPTO_SHA256 is not set
1088# CONFIG_CRYPTO_SHA512 is not set
1089# CONFIG_CRYPTO_WP512 is not set
1090# CONFIG_CRYPTO_TGR192 is not set
1091# CONFIG_CRYPTO_GF128MUL is not set
1092# CONFIG_CRYPTO_ECB is not set
1093CONFIG_CRYPTO_CBC=y
1094# CONFIG_CRYPTO_PCBC is not set
1095# CONFIG_CRYPTO_LRW is not set
1096# CONFIG_CRYPTO_XTS is not set
1097# CONFIG_CRYPTO_CRYPTD is not set
1098CONFIG_CRYPTO_DES=y
1099# CONFIG_CRYPTO_FCRYPT is not set
1100# CONFIG_CRYPTO_BLOWFISH is not set
1101# CONFIG_CRYPTO_TWOFISH is not set
1102# CONFIG_CRYPTO_SERPENT is not set
1103# CONFIG_CRYPTO_AES is not set
1104# CONFIG_CRYPTO_CAST5 is not set
1105# CONFIG_CRYPTO_CAST6 is not set
1106# CONFIG_CRYPTO_TEA is not set
1107# CONFIG_CRYPTO_ARC4 is not set
1108# CONFIG_CRYPTO_KHAZAD is not set
1109# CONFIG_CRYPTO_ANUBIS is not set
1110# CONFIG_CRYPTO_SEED is not set
1111# CONFIG_CRYPTO_DEFLATE is not set
1112# CONFIG_CRYPTO_MICHAEL_MIC is not set
1113# CONFIG_CRYPTO_CRC32C is not set
1114# CONFIG_CRYPTO_CAMELLIA is not set
1115# CONFIG_CRYPTO_TEST is not set
1116# CONFIG_CRYPTO_AUTHENC is not set
1117# CONFIG_CRYPTO_HW is not set
1118
1119#
1120# Library routines
1121#
1122CONFIG_BITREVERSE=y
1123# CONFIG_CRC_CCITT is not set
1124# CONFIG_CRC16 is not set
1125# CONFIG_CRC_ITU_T is not set
1126CONFIG_CRC32=y
1127# CONFIG_CRC7 is not set
1128# CONFIG_LIBCRC32C is not set
1129CONFIG_ZLIB_INFLATE=y
1130CONFIG_ZLIB_DEFLATE=y
1131CONFIG_PLIST=y
1132CONFIG_HAS_IOMEM=y
1133CONFIG_HAS_IOPORT=y
1134CONFIG_HAS_DMA=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 48dca69addae..8355f88f7292 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -151,7 +151,6 @@ CONFIG_ARM_AMBA=y
151# Kernel Features 151# Kernel Features
152# 152#
153# CONFIG_PREEMPT is not set 153# CONFIG_PREEMPT is not set
154# CONFIG_NO_IDLE_HZ is not set
155CONFIG_HZ=100 154CONFIG_HZ=100
156# CONFIG_AEABI is not set 155# CONFIG_AEABI is not set
157# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set 156# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
diff --git a/arch/arm/kernel/atags.c b/arch/arm/kernel/atags.c
index 64c420805e6f..42a1a1415fa6 100644
--- a/arch/arm/kernel/atags.c
+++ b/arch/arm/kernel/atags.c
@@ -1,5 +1,4 @@
1#include <linux/slab.h> 1#include <linux/slab.h>
2#include <linux/kexec.h>
3#include <linux/proc_fs.h> 2#include <linux/proc_fs.h>
4#include <asm/setup.h> 3#include <asm/setup.h>
5#include <asm/types.h> 4#include <asm/types.h>
@@ -7,9 +6,8 @@
7 6
8struct buffer { 7struct buffer {
9 size_t size; 8 size_t size;
10 char *data; 9 char data[];
11}; 10};
12static struct buffer tags_buffer;
13 11
14static int 12static int
15read_buffer(char* page, char** start, off_t off, int count, 13read_buffer(char* page, char** start, off_t off, int count,
@@ -29,58 +27,57 @@ read_buffer(char* page, char** start, off_t off, int count,
29 return count; 27 return count;
30} 28}
31 29
32 30#define BOOT_PARAMS_SIZE 1536
33static int 31static char __initdata atags_copy[BOOT_PARAMS_SIZE];
34create_proc_entries(void)
35{
36 struct proc_dir_entry* tags_entry;
37
38 tags_entry = create_proc_read_entry("atags", 0400, NULL, read_buffer, &tags_buffer);
39 if (!tags_entry)
40 return -ENOMEM;
41
42 return 0;
43}
44
45
46static char __initdata atags_copy_buf[KEXEC_BOOT_PARAMS_SIZE];
47static char __initdata *atags_copy;
48 32
49void __init save_atags(const struct tag *tags) 33void __init save_atags(const struct tag *tags)
50{ 34{
51 atags_copy = atags_copy_buf; 35 memcpy(atags_copy, tags, sizeof(atags_copy));
52 memcpy(atags_copy, tags, KEXEC_BOOT_PARAMS_SIZE);
53} 36}
54 37
55
56static int __init init_atags_procfs(void) 38static int __init init_atags_procfs(void)
57{ 39{
58 struct tag *tag; 40 /*
59 int error; 41 * This cannot go into save_atags() because kmalloc and proc don't work
42 * yet when it is called.
43 */
44 struct proc_dir_entry *tags_entry;
45 struct tag *tag = (struct tag *)atags_copy;
46 struct buffer *b;
47 size_t size;
60 48
61 if (!atags_copy) { 49 if (tag->hdr.tag != ATAG_CORE) {
62 printk(KERN_WARNING "Exporting ATAGs: No saved tags found\n"); 50 printk(KERN_INFO "No ATAGs?");
63 return -EIO; 51 return -EINVAL;
64 } 52 }
65 53
66 for (tag = (struct tag *) atags_copy; tag->hdr.size; tag = tag_next(tag)) 54 for (; tag->hdr.size; tag = tag_next(tag))
67 ; 55 ;
68 56
69 tags_buffer.size = ((char *) tag - atags_copy) + sizeof(tag->hdr); 57 /* include the terminating ATAG_NONE */
70 tags_buffer.data = kmalloc(tags_buffer.size, GFP_KERNEL); 58 size = (char *)tag - atags_copy + sizeof(struct tag_header);
71 if (tags_buffer.data == NULL)
72 return -ENOMEM;
73 memcpy(tags_buffer.data, atags_copy, tags_buffer.size);
74
75 error = create_proc_entries();
76 if (error) {
77 printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
78 kfree(tags_buffer.data);
79 tags_buffer.size = 0;
80 tags_buffer.data = NULL;
81 }
82 59
83 return error; 60 WARN_ON(tag->hdr.tag != ATAG_NONE);
84} 61
62 b = kmalloc(sizeof(*b) + size, GFP_KERNEL);
63 if (!b)
64 goto nomem;
85 65
66 b->size = size;
67 memcpy(b->data, atags_copy, size);
68
69 tags_entry = create_proc_read_entry("atags", 0400,
70 NULL, read_buffer, b);
71
72 if (!tags_entry)
73 goto nomem;
74
75 return 0;
76
77nomem:
78 kfree(b);
79 printk(KERN_ERR "Exporting ATAGs: not enough memory\n");
80
81 return -ENOMEM;
82}
86arch_initcall(init_atags_procfs); 83arch_initcall(init_atags_procfs);
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index a53c0aba5c14..8bfd299bfe77 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -680,7 +680,7 @@ static int __init ecard_probeirqhw(void)
680#define IO_EC_MEMC8_BASE 0 680#define IO_EC_MEMC8_BASE 0
681#endif 681#endif
682 682
683unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed) 683static unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed)
684{ 684{
685 unsigned long address = 0; 685 unsigned long address = 0;
686 int slot = ec->slot_no; 686 int slot = ec->slot_no;
@@ -1002,7 +1002,7 @@ ecard_probe(int slot, card_type_t type)
1002 } 1002 }
1003 1003
1004 rc = -ENODEV; 1004 rc = -ENODEV;
1005 if ((ec->podaddr = ecard_address(ec, type, ECARD_SYNC)) == 0) 1005 if ((ec->podaddr = __ecard_address(ec, type, ECARD_SYNC)) == 0)
1006 goto nodev; 1006 goto nodev;
1007 1007
1008 cid.r_zero = 1; 1008 cid.r_zero = 1;
@@ -1141,10 +1141,10 @@ static int ecard_drv_probe(struct device *dev)
1141 1141
1142 id = ecard_match_device(drv->id_table, ec); 1142 id = ecard_match_device(drv->id_table, ec);
1143 1143
1144 ecard_claim(ec); 1144 ec->claimed = 1;
1145 ret = drv->probe(ec, id); 1145 ret = drv->probe(ec, id);
1146 if (ret) 1146 if (ret)
1147 ecard_release(ec); 1147 ec->claimed = 0;
1148 return ret; 1148 return ret;
1149} 1149}
1150 1150
@@ -1154,7 +1154,7 @@ static int ecard_drv_remove(struct device *dev)
1154 struct ecard_driver *drv = ECARD_DRV(dev->driver); 1154 struct ecard_driver *drv = ECARD_DRV(dev->driver);
1155 1155
1156 drv->remove(ec); 1156 drv->remove(ec);
1157 ecard_release(ec); 1157 ec->claimed = 0;
1158 1158
1159 /* 1159 /*
1160 * Restore the default operations. We ensure that the 1160 * Restore the default operations. We ensure that the
@@ -1182,7 +1182,7 @@ static void ecard_drv_shutdown(struct device *dev)
1182 if (dev->driver) { 1182 if (dev->driver) {
1183 if (drv->shutdown) 1183 if (drv->shutdown)
1184 drv->shutdown(ec); 1184 drv->shutdown(ec);
1185 ecard_release(ec); 1185 ec->claimed = 0;
1186 } 1186 }
1187 1187
1188 /* 1188 /*
@@ -1239,7 +1239,6 @@ static int ecard_bus_init(void)
1239postcore_initcall(ecard_bus_init); 1239postcore_initcall(ecard_bus_init);
1240 1240
1241EXPORT_SYMBOL(ecard_readchunk); 1241EXPORT_SYMBOL(ecard_readchunk);
1242EXPORT_SYMBOL(__ecard_address);
1243EXPORT_SYMBOL(ecard_register_driver); 1242EXPORT_SYMBOL(ecard_register_driver);
1244EXPORT_SYMBOL(ecard_remove_driver); 1243EXPORT_SYMBOL(ecard_remove_driver);
1245EXPORT_SYMBOL(ecard_bus_type); 1244EXPORT_SYMBOL(ecard_bus_type);
diff --git a/arch/arm/kernel/ecard.h b/arch/arm/kernel/ecard.h
index d7c2dacf935d..4642d436be2a 100644
--- a/arch/arm/kernel/ecard.h
+++ b/arch/arm/kernel/ecard.h
@@ -54,3 +54,16 @@ struct ex_chunk_dir {
54#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16)) 54#define c_len(x) ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
55#define c_start(x) ((x)->r_start) 55#define c_start(x) ((x)->r_start)
56}; 56};
57
58typedef enum ecard_type { /* Cards address space */
59 ECARD_IOC,
60 ECARD_MEMC,
61 ECARD_EASI
62} card_type_t;
63
64typedef enum { /* Speed for ECARD_IOC space */
65 ECARD_SLOW = 0,
66 ECARD_MEDIUM = 1,
67 ECARD_FAST = 2,
68 ECARD_SYNC = 3
69} card_speed_t;
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 46bf2ede6128..199b3680118b 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -133,10 +133,8 @@ static void default_idle(void)
133 cpu_relax(); 133 cpu_relax();
134 else { 134 else {
135 local_irq_disable(); 135 local_irq_disable();
136 if (!need_resched()) { 136 if (!need_resched())
137 timer_dyn_reprogram();
138 arch_idle(); 137 arch_idle();
139 }
140 local_irq_enable(); 138 local_irq_enable();
141 } 139 }
142} 140}
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index ae31deb2d065..90e0c35ae60d 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -36,6 +36,7 @@ EXPORT_SYMBOL(walk_stackframe);
36#ifdef CONFIG_STACKTRACE 36#ifdef CONFIG_STACKTRACE
37struct stack_trace_data { 37struct stack_trace_data {
38 struct stack_trace *trace; 38 struct stack_trace *trace;
39 unsigned int no_sched_functions;
39 unsigned int skip; 40 unsigned int skip;
40}; 41};
41 42
@@ -43,27 +44,52 @@ static int save_trace(struct stackframe *frame, void *d)
43{ 44{
44 struct stack_trace_data *data = d; 45 struct stack_trace_data *data = d;
45 struct stack_trace *trace = data->trace; 46 struct stack_trace *trace = data->trace;
47 unsigned long addr = frame->lr;
46 48
49 if (data->no_sched_functions && in_sched_functions(addr))
50 return 0;
47 if (data->skip) { 51 if (data->skip) {
48 data->skip--; 52 data->skip--;
49 return 0; 53 return 0;
50 } 54 }
51 55
52 trace->entries[trace->nr_entries++] = frame->lr; 56 trace->entries[trace->nr_entries++] = addr;
53 57
54 return trace->nr_entries >= trace->max_entries; 58 return trace->nr_entries >= trace->max_entries;
55} 59}
56 60
57void save_stack_trace(struct stack_trace *trace) 61void save_stack_trace_tsk(struct task_struct *tsk, struct stack_trace *trace)
58{ 62{
59 struct stack_trace_data data; 63 struct stack_trace_data data;
60 unsigned long fp, base; 64 unsigned long fp, base;
61 65
62 data.trace = trace; 66 data.trace = trace;
63 data.skip = trace->skip; 67 data.skip = trace->skip;
64 base = (unsigned long)task_stack_page(current); 68 base = (unsigned long)task_stack_page(tsk);
65 asm("mov %0, fp" : "=r" (fp)); 69
70 if (tsk != current) {
71#ifdef CONFIG_SMP
72 /*
73 * What guarantees do we have here that 'tsk'
74 * is not running on another CPU?
75 */
76 BUG();
77#else
78 data.no_sched_functions = 1;
79 fp = thread_saved_fp(tsk);
80#endif
81 } else {
82 data.no_sched_functions = 0;
83 asm("mov %0, fp" : "=r" (fp));
84 }
66 85
67 walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data); 86 walk_stackframe(fp, base, base + THREAD_SIZE, save_trace, &data);
87 if (trace->nr_entries < trace->max_entries)
88 trace->entries[trace->nr_entries++] = ULONG_MAX;
89}
90
91void save_stack_trace(struct stack_trace *trace)
92{
93 save_stack_trace_tsk(current, trace);
68} 94}
69#endif 95#endif
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index b5867eca1d0b..cc5145b28e7f 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -365,108 +365,6 @@ static struct sysdev_class timer_sysclass = {
365 .resume = timer_resume, 365 .resume = timer_resume,
366}; 366};
367 367
368#ifdef CONFIG_NO_IDLE_HZ
369static int timer_dyn_tick_enable(void)
370{
371 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
372 unsigned long flags;
373 int ret = -ENODEV;
374
375 if (dyn_tick) {
376 spin_lock_irqsave(&dyn_tick->lock, flags);
377 ret = 0;
378 if (!(dyn_tick->state & DYN_TICK_ENABLED)) {
379 ret = dyn_tick->enable();
380
381 if (ret == 0)
382 dyn_tick->state |= DYN_TICK_ENABLED;
383 }
384 spin_unlock_irqrestore(&dyn_tick->lock, flags);
385 }
386
387 return ret;
388}
389
390static int timer_dyn_tick_disable(void)
391{
392 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
393 unsigned long flags;
394 int ret = -ENODEV;
395
396 if (dyn_tick) {
397 spin_lock_irqsave(&dyn_tick->lock, flags);
398 ret = 0;
399 if (dyn_tick->state & DYN_TICK_ENABLED) {
400 ret = dyn_tick->disable();
401
402 if (ret == 0)
403 dyn_tick->state &= ~DYN_TICK_ENABLED;
404 }
405 spin_unlock_irqrestore(&dyn_tick->lock, flags);
406 }
407
408 return ret;
409}
410
411/*
412 * Reprogram the system timer for at least the calculated time interval.
413 * This function should be called from the idle thread with IRQs disabled,
414 * immediately before sleeping.
415 */
416void timer_dyn_reprogram(void)
417{
418 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
419 unsigned long next, seq, flags;
420
421 if (!dyn_tick)
422 return;
423
424 spin_lock_irqsave(&dyn_tick->lock, flags);
425 if (dyn_tick->state & DYN_TICK_ENABLED) {
426 next = next_timer_interrupt();
427 do {
428 seq = read_seqbegin(&xtime_lock);
429 dyn_tick->reprogram(next - jiffies);
430 } while (read_seqretry(&xtime_lock, seq));
431 }
432 spin_unlock_irqrestore(&dyn_tick->lock, flags);
433}
434
435static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
436{
437 return sprintf(buf, "%i\n",
438 (system_timer->dyn_tick->state & DYN_TICK_ENABLED) >> 1);
439}
440
441static ssize_t timer_set_dyn_tick(struct sys_device *dev, const char *buf,
442 size_t count)
443{
444 unsigned int enable = simple_strtoul(buf, NULL, 2);
445
446 if (enable)
447 timer_dyn_tick_enable();
448 else
449 timer_dyn_tick_disable();
450
451 return count;
452}
453static SYSDEV_ATTR(dyn_tick, 0644, timer_show_dyn_tick, timer_set_dyn_tick);
454
455/*
456 * dyntick=enable|disable
457 */
458static char dyntick_str[4] __initdata = "";
459
460static int __init dyntick_setup(char *str)
461{
462 if (str)
463 strlcpy(dyntick_str, str, sizeof(dyntick_str));
464 return 1;
465}
466
467__setup("dyntick=", dyntick_setup);
468#endif
469
470static int __init timer_init_sysfs(void) 368static int __init timer_init_sysfs(void)
471{ 369{
472 int ret = sysdev_class_register(&timer_sysclass); 370 int ret = sysdev_class_register(&timer_sysclass);
@@ -475,19 +373,6 @@ static int __init timer_init_sysfs(void)
475 ret = sysdev_register(&system_timer->dev); 373 ret = sysdev_register(&system_timer->dev);
476 } 374 }
477 375
478#ifdef CONFIG_NO_IDLE_HZ
479 if (ret == 0 && system_timer->dyn_tick) {
480 ret = sysdev_create_file(&system_timer->dev, &attr_dyn_tick);
481
482 /*
483 * Turn on dynamic tick after calibrate delay
484 * for correct bogomips
485 */
486 if (ret == 0 && dyntick_str[0] == 'e')
487 ret = timer_dyn_tick_enable();
488 }
489#endif
490
491 return ret; 376 return ret;
492} 377}
493 378
@@ -500,10 +385,5 @@ void __init time_init(void)
500 system_timer->offset = dummy_gettimeoffset; 385 system_timer->offset = dummy_gettimeoffset;
501#endif 386#endif
502 system_timer->init(); 387 system_timer->init();
503
504#ifdef CONFIG_NO_IDLE_HZ
505 if (system_timer->dyn_tick)
506 spin_lock_init(&system_timer->dyn_tick->lock);
507#endif
508} 388}
509 389
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index cab355c0c1f7..139cce646055 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -13,14 +13,6 @@
13 */ 13 */
14 14
15/* 15/*
16 * This can be used to enable code to cacheline align the source pointer.
17 * Experiments on tested architectures (StrongARM and XScale) didn't show
18 * this a worthwhile thing to do. That might be different in the future.
19 */
20//#define CALGN(code...) code
21#define CALGN(code...)
22
23/*
24 * Theory of operation 16 * Theory of operation
25 * ------------------- 17 * -------------------
26 * 18 *
@@ -82,7 +74,7 @@
82 stmfd sp!, {r5 - r8} 74 stmfd sp!, {r5 - r8}
83 blt 5f 75 blt 5f
84 76
85 CALGN( ands ip, r1, #31 ) 77 CALGN( ands ip, r0, #31 )
86 CALGN( rsb r3, ip, #32 ) 78 CALGN( rsb r3, ip, #32 )
87 CALGN( sbcnes r4, r3, r2 ) @ C is always set here 79 CALGN( sbcnes r4, r3, r2 ) @ C is always set here
88 CALGN( bcs 2f ) 80 CALGN( bcs 2f )
@@ -168,7 +160,7 @@
168 subs r2, r2, #28 160 subs r2, r2, #28
169 blt 14f 161 blt 14f
170 162
171 CALGN( ands ip, r1, #31 ) 163 CALGN( ands ip, r0, #31 )
172 CALGN( rsb ip, ip, #32 ) 164 CALGN( rsb ip, ip, #32 )
173 CALGN( sbcnes r4, ip, r2 ) @ C is always set here 165 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
174 CALGN( subcc r2, r2, ip ) 166 CALGN( subcc r2, r2, ip )
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index ef7fddc14ac9..2e301b7bd8f1 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -13,14 +13,6 @@
13#include <linux/linkage.h> 13#include <linux/linkage.h>
14#include <asm/assembler.h> 14#include <asm/assembler.h>
15 15
16/*
17 * This can be used to enable code to cacheline align the source pointer.
18 * Experiments on tested architectures (StrongARM and XScale) didn't show
19 * this a worthwhile thing to do. That might be different in the future.
20 */
21//#define CALGN(code...) code
22#define CALGN(code...)
23
24 .text 16 .text
25 17
26/* 18/*
@@ -55,11 +47,12 @@ ENTRY(memmove)
55 stmfd sp!, {r5 - r8} 47 stmfd sp!, {r5 - r8}
56 blt 5f 48 blt 5f
57 49
58 CALGN( ands ip, r1, #31 ) 50 CALGN( ands ip, r0, #31 )
59 CALGN( sbcnes r4, ip, r2 ) @ C is always set here 51 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
60 CALGN( bcs 2f ) 52 CALGN( bcs 2f )
61 CALGN( adr r4, 6f ) 53 CALGN( adr r4, 6f )
62 CALGN( subs r2, r2, ip ) @ C is set here 54 CALGN( subs r2, r2, ip ) @ C is set here
55 CALGN( rsb ip, ip, #32 )
63 CALGN( add pc, r4, ip ) 56 CALGN( add pc, r4, ip )
64 57
65 PLD( pld [r1, #-4] ) 58 PLD( pld [r1, #-4] )
@@ -138,8 +131,7 @@ ENTRY(memmove)
138 subs r2, r2, #28 131 subs r2, r2, #28
139 blt 14f 132 blt 14f
140 133
141 CALGN( ands ip, r1, #31 ) 134 CALGN( ands ip, r0, #31 )
142 CALGN( rsb ip, ip, #32 )
143 CALGN( sbcnes r4, ip, r2 ) @ C is always set here 135 CALGN( sbcnes r4, ip, r2 ) @ C is always set here
144 CALGN( subcc r2, r2, ip ) 136 CALGN( subcc r2, r2, ip )
145 CALGN( bcc 15f ) 137 CALGN( bcc 15f )
diff --git a/arch/arm/lib/memset.S b/arch/arm/lib/memset.S
index 95b110b07a89..b477d4ac88ef 100644
--- a/arch/arm/lib/memset.S
+++ b/arch/arm/lib/memset.S
@@ -39,6 +39,9 @@ ENTRY(memset)
39 mov r3, r1 39 mov r3, r1
40 cmp r2, #16 40 cmp r2, #16
41 blt 4f 41 blt 4f
42
43#if ! CALGN(1)+0
44
42/* 45/*
43 * We need an extra register for this loop - save the return address and 46 * We need an extra register for this loop - save the return address and
44 * use the LR 47 * use the LR
@@ -64,6 +67,49 @@ ENTRY(memset)
64 stmneia r0!, {r1, r3, ip, lr} 67 stmneia r0!, {r1, r3, ip, lr}
65 ldr lr, [sp], #4 68 ldr lr, [sp], #4
66 69
70#else
71
72/*
73 * This version aligns the destination pointer in order to write
74 * whole cache lines at once.
75 */
76
77 stmfd sp!, {r4-r7, lr}
78 mov r4, r1
79 mov r5, r1
80 mov r6, r1
81 mov r7, r1
82 mov ip, r1
83 mov lr, r1
84
85 cmp r2, #96
86 tstgt r0, #31
87 ble 3f
88
89 and ip, r0, #31
90 rsb ip, ip, #32
91 sub r2, r2, ip
92 movs ip, ip, lsl #(32 - 4)
93 stmcsia r0!, {r4, r5, r6, r7}
94 stmmiia r0!, {r4, r5}
95 tst ip, #(1 << 30)
96 mov ip, r1
97 strne r1, [r0], #4
98
993: subs r2, r2, #64
100 stmgeia r0!, {r1, r3-r7, ip, lr}
101 stmgeia r0!, {r1, r3-r7, ip, lr}
102 bgt 3b
103 ldmeqfd sp!, {r4-r7, pc}
104
105 tst r2, #32
106 stmneia r0!, {r1, r3-r7, ip, lr}
107 tst r2, #16
108 stmneia r0!, {r4-r7}
109 ldmfd sp!, {r4-r7, lr}
110
111#endif
112
674: tst r2, #8 1134: tst r2, #8
68 stmneia r0!, {r1, r3} 114 stmneia r0!, {r1, r3}
69 tst r2, #4 115 tst r2, #4
diff --git a/arch/arm/lib/memzero.S b/arch/arm/lib/memzero.S
index abf2508e8221..b8f79d80ee9b 100644
--- a/arch/arm/lib/memzero.S
+++ b/arch/arm/lib/memzero.S
@@ -39,6 +39,9 @@ ENTRY(__memzero)
39 */ 39 */
40 cmp r1, #16 @ 1 we can skip this chunk if we 40 cmp r1, #16 @ 1 we can skip this chunk if we
41 blt 4f @ 1 have < 16 bytes 41 blt 4f @ 1 have < 16 bytes
42
43#if ! CALGN(1)+0
44
42/* 45/*
43 * We need an extra register for this loop - save the return address and 46 * We need an extra register for this loop - save the return address and
44 * use the LR 47 * use the LR
@@ -64,6 +67,47 @@ ENTRY(__memzero)
64 stmneia r0!, {r2, r3, ip, lr} @ 4 67 stmneia r0!, {r2, r3, ip, lr} @ 4
65 ldr lr, [sp], #4 @ 1 68 ldr lr, [sp], #4 @ 1
66 69
70#else
71
72/*
73 * This version aligns the destination pointer in order to write
74 * whole cache lines at once.
75 */
76
77 stmfd sp!, {r4-r7, lr}
78 mov r4, r2
79 mov r5, r2
80 mov r6, r2
81 mov r7, r2
82 mov ip, r2
83 mov lr, r2
84
85 cmp r1, #96
86 andgts ip, r0, #31
87 ble 3f
88
89 rsb ip, ip, #32
90 sub r1, r1, ip
91 movs ip, ip, lsl #(32 - 4)
92 stmcsia r0!, {r4, r5, r6, r7}
93 stmmiia r0!, {r4, r5}
94 movs ip, ip, lsl #2
95 strcs r2, [r0], #4
96
973: subs r1, r1, #64
98 stmgeia r0!, {r2-r7, ip, lr}
99 stmgeia r0!, {r2-r7, ip, lr}
100 bgt 3b
101 ldmeqfd sp!, {r4-r7, pc}
102
103 tst r1, #32
104 stmneia r0!, {r2-r7, ip, lr}
105 tst r1, #16
106 stmneia r0!, {r4-r7}
107 ldmfd sp!, {r4-r7, lr}
108
109#endif
110
674: tst r1, #8 @ 1 8 bytes or more? 1114: tst r1, #8 @ 1 8 bytes or more?
68 stmneia r0!, {r2, r3} @ 2 112 stmneia r0!, {r2, r3} @ 2
69 tst r1, #4 @ 1 4 bytes or more? 113 tst r1, #4 @ 1 4 bytes or more?
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 0fc07b6db749..5bad6b9b00d7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,6 +30,11 @@ config ARCH_AT91SAM9RL
30 select GENERIC_TIME 30 select GENERIC_TIME
31 select GENERIC_CLOCKEVENTS 31 select GENERIC_CLOCKEVENTS
32 32
33config ARCH_AT91SAM9G20
34 bool "AT91SAM9G20"
35 select GENERIC_TIME
36 select GENERIC_CLOCKEVENTS
37
33config ARCH_AT91CAP9 38config ARCH_AT91CAP9
34 bool "AT91CAP9" 39 bool "AT91CAP9"
35 select GENERIC_TIME 40 select GENERIC_TIME
@@ -126,6 +131,12 @@ config MACH_ECBAT91
126 Select this if you are using emQbit's ECB_AT91 board. 131 Select this if you are using emQbit's ECB_AT91 board.
127 <http://wiki.emqbit.com/free-ecb-at91> 132 <http://wiki.emqbit.com/free-ecb-at91>
128 133
134config MACH_YL9200
135 bool "ucDragon YL-9200"
136 depends on ARCH_AT91RM9200
137 help
138 Select this if you are using the ucDragon YL-9200 board.
139
129endif 140endif
130 141
131# ---------------------------------------------------------- 142# ----------------------------------------------------------
@@ -164,6 +175,20 @@ config MACH_SAM9_L9260
164 Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260. 175 Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
165 <http://www.olimex.com/dev/sam9-L9260.html> 176 <http://www.olimex.com/dev/sam9-L9260.html>
166 177
178config MACH_USB_A9260
179 bool "CALAO USB-A9260"
180 depends on ARCH_AT91SAM9260
181 help
182 Select this if you are using a Calao Systems USB-A9260.
183 <http://www.calao-systems.com>
184
185config MACH_QIL_A9260
186 bool "CALAO QIL-A9260 board"
187 depends on ARCH_AT91SAM9260
188 help
189 Select this if you are using a Calao Systems QIL-A9260 Board.
190 <http://www.calao-systems.com>
191
167endif 192endif
168 193
169# ---------------------------------------------------------- 194# ----------------------------------------------------------
@@ -194,6 +219,13 @@ config MACH_AT91SAM9263EK
194 Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit. 219 Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
195 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057> 220 <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
196 221
222config MACH_USB_A9263
223 bool "CALAO USB-A9263"
224 depends on ARCH_AT91SAM9263
225 help
226 Select this if you are using a Calao Systems USB-A9263.
227 <http://www.calao-systems.com>
228
197endif 229endif
198 230
199# ---------------------------------------------------------- 231# ----------------------------------------------------------
@@ -212,6 +244,20 @@ endif
212 244
213# ---------------------------------------------------------- 245# ----------------------------------------------------------
214 246
247if ARCH_AT91SAM9G20
248
249comment "AT91SAM9G20 Board Type"
250
251config MACH_AT91SAM9G20EK
252 bool "Atmel AT91SAM9G20-EK Evaluation Kit"
253 depends on ARCH_AT91SAM9G20
254 help
255 Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
256
257endif
258
259# ----------------------------------------------------------
260
215if ARCH_AT91CAP9 261if ARCH_AT91CAP9
216 262
217comment "AT91CAP9 Board Type" 263comment "AT91CAP9 Board Type"
@@ -247,13 +293,13 @@ comment "AT91 Board Options"
247 293
248config MTD_AT91_DATAFLASH_CARD 294config MTD_AT91_DATAFLASH_CARD
249 bool "Enable DataFlash Card support" 295 bool "Enable DataFlash Card support"
250 depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK || MACH_SAM9_L9260 || MACH_ECBAT91) 296 depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK)
251 help 297 help
252 Enable support for the DataFlash card. 298 Enable support for the DataFlash card.
253 299
254config MTD_NAND_AT91_BUSWIDTH_16 300config MTD_NAND_AT91_BUSWIDTH_16
255 bool "Enable 16-bit data bus interface to NAND flash" 301 bool "Enable 16-bit data bus interface to NAND flash"
256 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91CAP9ADK) 302 depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
257 help 303 help
258 On AT91SAM926x boards both types of NAND flash can be present 304 On AT91SAM926x boards both types of NAND flash can be present
259 (8 and 16 bit data bus width). 305 (8 and 16 bit data bus width).
@@ -302,15 +348,15 @@ config AT91_EARLY_USART2
302 348
303config AT91_EARLY_USART3 349config AT91_EARLY_USART3
304 bool "USART3" 350 bool "USART3"
305 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260) 351 depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
306 352
307config AT91_EARLY_USART4 353config AT91_EARLY_USART4
308 bool "USART4" 354 bool "USART4"
309 depends on ARCH_AT91SAM9260 355 depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
310 356
311config AT91_EARLY_USART5 357config AT91_EARLY_USART5
312 bool "USART5" 358 bool "USART5"
313 depends on ARCH_AT91SAM9260 359 depends on ARCH_AT91SAM9260 || ARCH_AT91SAM9G20
314 360
315endchoice 361endchoice
316 362
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 8d9bc0153b18..7d641f97516b 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_d
15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o 15obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o
16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o 16obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o
17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o 17obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o
18obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o
18obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o 19obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o
19obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o 20obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o
20 21
@@ -30,21 +31,28 @@ obj-$(CONFIG_MACH_ATEB9200) += board-eb9200.o
30obj-$(CONFIG_MACH_KAFA) += board-kafa.o 31obj-$(CONFIG_MACH_KAFA) += board-kafa.o
31obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o 32obj-$(CONFIG_MACH_PICOTUX2XX) += board-picotux200.o
32obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o 33obj-$(CONFIG_MACH_ECBAT91) += board-ecbat91.o
34obj-$(CONFIG_MACH_YL9200) += board-yl-9200.o
33 35
34# AT91SAM9260 board-specific support 36# AT91SAM9260 board-specific support
35obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o 37obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
36obj-$(CONFIG_MACH_CAM60) += board-cam60.o 38obj-$(CONFIG_MACH_CAM60) += board-cam60.o
37obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o 39obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o
40obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o
41obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o
38 42
39# AT91SAM9261 board-specific support 43# AT91SAM9261 board-specific support
40obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o 44obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
41 45
42# AT91SAM9263 board-specific support 46# AT91SAM9263 board-specific support
43obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o 47obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
48obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o
44 49
45# AT91SAM9RL board-specific support 50# AT91SAM9RL board-specific support
46obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o 51obj-$(CONFIG_MACH_AT91SAM9RLEK) += board-sam9rlek.o
47 52
53# AT91SAM9G20 board-specific support
54obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
55
48# AT91CAP9 board-specific support 56# AT91CAP9 board-specific support
49obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 57obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
50 58
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index be526746e01e..747b9dedab88 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -84,6 +84,105 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
84 84
85 85
86/* -------------------------------------------------------------------- 86/* --------------------------------------------------------------------
87 * USB HS Device (Gadget)
88 * -------------------------------------------------------------------- */
89
90#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
91
92static struct resource usba_udc_resources[] = {
93 [0] = {
94 .start = AT91CAP9_UDPHS_FIFO,
95 .end = AT91CAP9_UDPHS_FIFO + SZ_512K - 1,
96 .flags = IORESOURCE_MEM,
97 },
98 [1] = {
99 .start = AT91CAP9_BASE_UDPHS,
100 .end = AT91CAP9_BASE_UDPHS + SZ_1K - 1,
101 .flags = IORESOURCE_MEM,
102 },
103 [2] = {
104 .start = AT91CAP9_ID_UDPHS,
105 .end = AT91CAP9_ID_UDPHS,
106 .flags = IORESOURCE_IRQ,
107 },
108};
109
110#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
111 [idx] = { \
112 .name = nam, \
113 .index = idx, \
114 .fifo_size = maxpkt, \
115 .nr_banks = maxbk, \
116 .can_dma = dma, \
117 .can_isoc = isoc, \
118 }
119
120static struct usba_ep_data usba_udc_ep[] = {
121 EP("ep0", 0, 64, 1, 0, 0),
122 EP("ep1", 1, 1024, 3, 1, 1),
123 EP("ep2", 2, 1024, 3, 1, 1),
124 EP("ep3", 3, 1024, 2, 1, 1),
125 EP("ep4", 4, 1024, 2, 1, 1),
126 EP("ep5", 5, 1024, 2, 1, 0),
127 EP("ep6", 6, 1024, 2, 1, 0),
128 EP("ep7", 7, 1024, 2, 0, 0),
129};
130
131#undef EP
132
133/*
134 * pdata doesn't have room for any endpoints, so we need to
135 * append room for the ones we need right after it.
136 */
137static struct {
138 struct usba_platform_data pdata;
139 struct usba_ep_data ep[8];
140} usba_udc_data;
141
142static struct platform_device at91_usba_udc_device = {
143 .name = "atmel_usba_udc",
144 .id = -1,
145 .dev = {
146 .platform_data = &usba_udc_data.pdata,
147 },
148 .resource = usba_udc_resources,
149 .num_resources = ARRAY_SIZE(usba_udc_resources),
150};
151
152void __init at91_add_device_usba(struct usba_platform_data *data)
153{
154 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
155 AT91_MATRIX_UDPHS_BYPASS_LOCK);
156
157 /*
158 * Invalid pins are 0 on AT91, but the usba driver is shared
159 * with AVR32, which use negative values instead. Once/if
160 * gpio_is_valid() is ported to AT91, revisit this code.
161 */
162 usba_udc_data.pdata.vbus_pin = -EINVAL;
163 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
164 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
165
166 if (data && data->vbus_pin > 0) {
167 at91_set_gpio_input(data->vbus_pin, 0);
168 at91_set_deglitch(data->vbus_pin, 1);
169 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
170 }
171
172 /* Pullup pin is handled internally by USB device peripheral */
173
174 /* Clocks */
175 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
176 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
177
178 platform_device_register(&at91_usba_udc_device);
179}
180#else
181void __init at91_add_device_usba(struct usba_platform_data *data) {}
182#endif
183
184
185/* --------------------------------------------------------------------
87 * Ethernet 186 * Ethernet
88 * -------------------------------------------------------------------- */ 187 * -------------------------------------------------------------------- */
89 188
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index ee26550cdc21..380f12a12200 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -47,6 +47,20 @@ static struct map_desc at91sam9260_sram_desc[] __initdata = {
47 } 47 }
48}; 48};
49 49
50static struct map_desc at91sam9g20_sram_desc[] __initdata = {
51 {
52 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE,
53 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM0_BASE),
54 .length = AT91SAM9G20_SRAM0_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = AT91_IO_VIRT_BASE - AT91SAM9G20_SRAM0_SIZE - AT91SAM9G20_SRAM1_SIZE,
58 .pfn = __phys_to_pfn(AT91SAM9G20_SRAM1_BASE),
59 .length = AT91SAM9G20_SRAM1_SIZE,
60 .type = MT_DEVICE,
61 }
62};
63
50static struct map_desc at91sam9xe_sram_desc[] __initdata = { 64static struct map_desc at91sam9xe_sram_desc[] __initdata = {
51 { 65 {
52 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE), 66 .pfn = __phys_to_pfn(AT91SAM9XE_SRAM_BASE),
@@ -307,6 +321,8 @@ void __init at91sam9260_initialize(unsigned long main_clock)
307 321
308 if (cpu_is_at91sam9xe()) 322 if (cpu_is_at91sam9xe())
309 at91sam9xe_initialize(); 323 at91sam9xe_initialize();
324 else if (cpu_is_at91sam9g20())
325 iotable_init(at91sam9g20_sram_desc, ARRAY_SIZE(at91sam9g20_sram_desc));
310 else 326 else
311 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc)); 327 iotable_init(at91sam9260_sram_desc, ARRAY_SIZE(at91sam9260_sram_desc));
312 328
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 393a32aefce5..86cba4ac29b1 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -18,6 +18,7 @@
18 18
19#include <asm/arch/board.h> 19#include <asm/arch/board.h>
20#include <asm/arch/gpio.h> 20#include <asm/arch/gpio.h>
21#include <asm/arch/cpu.h>
21#include <asm/arch/at91sam9260.h> 22#include <asm/arch/at91sam9260.h>
22#include <asm/arch/at91sam9260_matrix.h> 23#include <asm/arch/at91sam9260_matrix.h>
23#include <asm/arch/at91sam9_smc.h> 24#include <asm/arch/at91sam9_smc.h>
@@ -320,20 +321,41 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
320 csa = at91_sys_read(AT91_MATRIX_EBICSA); 321 csa = at91_sys_read(AT91_MATRIX_EBICSA);
321 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 322 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
322 323
323 /* set the bus interface characteristics */ 324 if (cpu_is_at91sam9260()) {
324 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) 325 /* Timing for sam9260 */
325 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 326 /* set the bus interface characteristics */
327 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
328 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
326 329
327 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) 330 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
328 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 331 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
329 332
330 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); 333 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
331 334
332 if (data->bus_width_16) 335 if (data->bus_width_16)
333 mode = AT91_SMC_DBW_16; 336 mode = AT91_SMC_DBW_16;
334 else 337 else
335 mode = AT91_SMC_DBW_8; 338 mode = AT91_SMC_DBW_8;
336 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2)); 339 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
340 }
341
342 if (cpu_is_at91sam9g20()) {
343 /* Timing for sam9g20 */
344 /* set the bus interface characteristics */
345 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0)
346 | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
347
348 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4)
349 | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
350
351 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
352
353 if (data->bus_width_16)
354 mode = AT91_SMC_DBW_16;
355 else
356 mode = AT91_SMC_DBW_8;
357 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(3));
358 }
337 359
338 /* enable pin */ 360 /* enable pin */
339 if (data->enable_pin) 361 if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 0babb645b83c..ec1891375dfb 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -232,19 +232,19 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
232 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 232 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
233 233
234 /* set the bus interface characteristics */ 234 /* set the bus interface characteristics */
235 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) 235 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
236 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 236 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
237 237
238 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) 238 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
239 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); 239 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
240 240
241 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); 241 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
242 242
243 if (data->bus_width_16) 243 if (data->bus_width_16)
244 mode = AT91_SMC_DBW_16; 244 mode = AT91_SMC_DBW_16;
245 else 245 else
246 mode = AT91_SMC_DBW_8; 246 mode = AT91_SMC_DBW_8;
247 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); 247 at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
248 248
249 /* enable pin */ 249 /* enable pin */
250 if (data->enable_pin) 250 if (data->enable_pin)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 719667e25c98..8a81f76f0200 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -391,8 +391,8 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
391 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); 391 at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
392 392
393 /* set the bus interface characteristics */ 393 /* set the bus interface characteristics */
394 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) 394 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
395 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 395 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
396 396
397 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) 397 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
398 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); 398 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
diff --git a/arch/arm/mach-at91/at91sam9rl_devices.c b/arch/arm/mach-at91/at91sam9rl_devices.c
index 450db304936f..ae28101e7542 100644
--- a/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -26,6 +26,101 @@
26 26
27 27
28/* -------------------------------------------------------------------- 28/* --------------------------------------------------------------------
29 * USB HS Device (Gadget)
30 * -------------------------------------------------------------------- */
31
32#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
33
34static struct resource usba_udc_resources[] = {
35 [0] = {
36 .start = AT91SAM9RL_UDPHS_FIFO,
37 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
38 .flags = IORESOURCE_MEM,
39 },
40 [1] = {
41 .start = AT91SAM9RL_BASE_UDPHS,
42 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [2] = {
46 .start = AT91SAM9RL_ID_UDPHS,
47 .end = AT91SAM9RL_ID_UDPHS,
48 .flags = IORESOURCE_IRQ,
49 },
50};
51
52#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
53 [idx] = { \
54 .name = nam, \
55 .index = idx, \
56 .fifo_size = maxpkt, \
57 .nr_banks = maxbk, \
58 .can_dma = dma, \
59 .can_isoc = isoc, \
60 }
61
62static struct usba_ep_data usba_udc_ep[] __initdata = {
63 EP("ep0", 0, 64, 1, 0, 0),
64 EP("ep1", 1, 1024, 2, 1, 1),
65 EP("ep2", 2, 1024, 2, 1, 1),
66 EP("ep3", 3, 1024, 3, 1, 0),
67 EP("ep4", 4, 1024, 3, 1, 0),
68 EP("ep5", 5, 1024, 3, 1, 1),
69 EP("ep6", 6, 1024, 3, 1, 1),
70};
71
72#undef EP
73
74/*
75 * pdata doesn't have room for any endpoints, so we need to
76 * append room for the ones we need right after it.
77 */
78static struct {
79 struct usba_platform_data pdata;
80 struct usba_ep_data ep[7];
81} usba_udc_data;
82
83static struct platform_device at91_usba_udc_device = {
84 .name = "atmel_usba_udc",
85 .id = -1,
86 .dev = {
87 .platform_data = &usba_udc_data.pdata,
88 },
89 .resource = usba_udc_resources,
90 .num_resources = ARRAY_SIZE(usba_udc_resources),
91};
92
93void __init at91_add_device_usba(struct usba_platform_data *data)
94{
95 /*
96 * Invalid pins are 0 on AT91, but the usba driver is shared
97 * with AVR32, which use negative values instead. Once/if
98 * gpio_is_valid() is ported to AT91, revisit this code.
99 */
100 usba_udc_data.pdata.vbus_pin = -EINVAL;
101 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
102 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
103
104 if (data && data->vbus_pin > 0) {
105 at91_set_gpio_input(data->vbus_pin, 0);
106 at91_set_deglitch(data->vbus_pin, 1);
107 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
108 }
109
110 /* Pullup pin is handled internally by USB device peripheral */
111
112 /* Clocks */
113 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
114 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
115
116 platform_device_register(&at91_usba_udc_device);
117}
118#else
119void __init at91_add_device_usba(struct usba_platform_data *data) {}
120#endif
121
122
123/* --------------------------------------------------------------------
29 * MMC / SD 124 * MMC / SD
30 * -------------------------------------------------------------------- */ 125 * -------------------------------------------------------------------- */
31 126
@@ -138,15 +233,15 @@ void __init at91_add_device_nand(struct at91_nand_data *data)
138 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); 233 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
139 234
140 /* set the bus interface characteristics */ 235 /* set the bus interface characteristics */
141 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) 236 at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0)
142 | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); 237 | AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
143 238
144 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5) 239 at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
145 | AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5)); 240 | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
146 241
147 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7)); 242 at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
148 243
149 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1)); 244 at91_sys_write(AT91_SMC_MODE(3), AT91_SMC_DBW_8 | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
150 245
151 /* enable pin */ 246 /* enable pin */
152 if (data->enable_pin) 247 if (data->enable_pin)
diff --git a/arch/arm/mach-at91/board-cap9adk.c b/arch/arm/mach-at91/board-cap9adk.c
index e5512d1ff217..8a2a958639db 100644
--- a/arch/arm/mach-at91/board-cap9adk.c
+++ b/arch/arm/mach-at91/board-cap9adk.c
@@ -78,6 +78,12 @@ static struct at91_usbh_data __initdata cap9adk_usbh_data = {
78 .ports = 2, 78 .ports = 2,
79}; 79};
80 80
81/*
82 * USB HS Device port
83 */
84static struct usba_platform_data __initdata cap9adk_usba_udc_data = {
85 .vbus_pin = AT91_PIN_PB31,
86};
81 87
82/* 88/*
83 * ADS7846 Touchscreen 89 * ADS7846 Touchscreen
@@ -326,6 +332,9 @@ static void __init cap9adk_board_init(void)
326 /* USB Host */ 332 /* USB Host */
327 set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH); 333 set_irq_type(AT91CAP9_ID_UHP, IRQT_HIGH);
328 at91_add_device_usbh(&cap9adk_usbh_data); 334 at91_add_device_usbh(&cap9adk_usbh_data);
335 /* USB HS */
336 set_irq_type(AT91CAP9_ID_UDPHS, IRQT_HIGH);
337 at91_add_device_usba(&cap9adk_usba_udc_data);
329 /* SPI */ 338 /* SPI */
330 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices)); 339 at91_add_device_spi(cap9adk_spi_devices, ARRAY_SIZE(cap9adk_spi_devices));
331 /* Touchscreen */ 340 /* Touchscreen */
diff --git a/arch/arm/mach-at91/board-carmeva.c b/arch/arm/mach-at91/board-carmeva.c
index 0f0878294a67..9854fc3dd1f2 100644
--- a/arch/arm/mach-at91/board-carmeva.c
+++ b/arch/arm/mach-at91/board-carmeva.c
@@ -40,24 +40,21 @@
40#include "generic.h" 40#include "generic.h"
41 41
42 42
43/*
44 * Serial port configuration.
45 * 0 .. 3 = USART0 .. USART3
46 * 4 = DBGU
47 */
48static struct at91_uart_config __initdata carmeva_uart_config = {
49 .console_tty = 0, /* ttyS0 */
50 .nr_tty = 2,
51 .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
52};
53
54static void __init carmeva_map_io(void) 43static void __init carmeva_map_io(void)
55{ 44{
56 /* Initialize processor: 20.000 MHz crystal */ 45 /* Initialize processor: 20.000 MHz crystal */
57 at91rm9200_initialize(20000000, AT91RM9200_BGA); 46 at91rm9200_initialize(20000000, AT91RM9200_BGA);
58 47
59 /* Setup the serial ports and console */ 48 /* DBGU on ttyS0. (Rx & Tx only) */
60 at91_init_serial(&carmeva_uart_config); 49 at91_register_uart(0, 0, 0);
50
51 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
52 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
53 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
54 | ATMEL_UART_RI);
55
56 /* set serial console to ttyS0 (ie, DBGU) */
57 at91_set_serial_console(0);
61} 58}
62 59
63static void __init carmeva_init_irq(void) 60static void __init carmeva_init_irq(void)
diff --git a/arch/arm/mach-at91/board-csb637.c b/arch/arm/mach-at91/board-csb637.c
index 419fd19b620b..bb1a5474ddab 100644
--- a/arch/arm/mach-at91/board-csb637.c
+++ b/arch/arm/mach-at91/board-csb637.c
@@ -45,10 +45,10 @@ static void __init csb637_map_io(void)
45 /* Initialize processor: 3.6864 MHz crystal */ 45 /* Initialize processor: 3.6864 MHz crystal */
46 at91rm9200_initialize(3686400, AT91RM9200_BGA); 46 at91rm9200_initialize(3686400, AT91RM9200_BGA);
47 47
48 /* DBGU on ttyS0 */ 48 /* DBGU on ttyS0. (Rx & Tx only) */
49 at91_register_uart(0, 0, 0); 49 at91_register_uart(0, 0, 0);
50 50
51 /* make console=ttyS0 the default */ 51 /* make console=ttyS0 (ie, DBGU) the default */
52 at91_set_serial_console(0); 52 at91_set_serial_console(0);
53} 53}
54 54
diff --git a/arch/arm/mach-at91/board-dk.c b/arch/arm/mach-at91/board-dk.c
index c1a813c7169b..dab958d25926 100644
--- a/arch/arm/mach-at91/board-dk.c
+++ b/arch/arm/mach-at91/board-dk.c
@@ -45,17 +45,6 @@
45#include "generic.h" 45#include "generic.h"
46 46
47 47
48/*
49 * Serial port configuration.
50 * 0 .. 3 = USART0 .. USART3
51 * 4 = DBGU
52 */
53static struct at91_uart_config __initdata dk_uart_config = {
54 .console_tty = 0, /* ttyS0 */
55 .nr_tty = 2,
56 .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
57};
58
59static void __init dk_map_io(void) 48static void __init dk_map_io(void)
60{ 49{
61 /* Initialize processor: 18.432 MHz crystal */ 50 /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init dk_map_io(void)
64 /* Setup the LEDs */ 53 /* Setup the LEDs */
65 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2); 54 at91_init_leds(AT91_PIN_PB2, AT91_PIN_PB2);
66 55
67 /* Setup the serial ports and console */ 56 /* DBGU on ttyS0. (Rx & Tx only) */
68 at91_init_serial(&dk_uart_config); 57 at91_register_uart(0, 0, 0);
58
59 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
60 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
61 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
62 | ATMEL_UART_RI);
63
64 /* set serial console to ttyS0 (ie, DBGU) */
65 at91_set_serial_console(0);
69} 66}
70 67
71static void __init dk_init_irq(void) 68static void __init dk_init_irq(void)
@@ -163,7 +160,7 @@ static struct at91_nand_data __initdata dk_nand_data = {
163#define DK_FLASH_SIZE 0x200000 160#define DK_FLASH_SIZE 0x200000
164 161
165static struct physmap_flash_data dk_flash_data = { 162static struct physmap_flash_data dk_flash_data = {
166 .width = 2, 163 .width = 2,
167}; 164};
168 165
169static struct resource dk_flash_resource = { 166static struct resource dk_flash_resource = {
diff --git a/arch/arm/mach-at91/board-eb9200.c b/arch/arm/mach-at91/board-eb9200.c
index af1a1d8ecc30..3fe054e0056b 100644
--- a/arch/arm/mach-at91/board-eb9200.c
+++ b/arch/arm/mach-at91/board-eb9200.c
@@ -40,24 +40,24 @@
40#include "generic.h" 40#include "generic.h"
41 41
42 42
43/*
44 * Serial port configuration.
45 * 0 .. 3 = USART0 .. USART3
46 * 4 = DBGU
47 */
48static struct at91_uart_config __initdata eb9200_uart_config = {
49 .console_tty = 0, /* ttyS0 */
50 .nr_tty = 2,
51 .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
52};
53
54static void __init eb9200_map_io(void) 43static void __init eb9200_map_io(void)
55{ 44{
56 /* Initialize processor: 18.432 MHz crystal */ 45 /* Initialize processor: 18.432 MHz crystal */
57 at91rm9200_initialize(18432000, AT91RM9200_BGA); 46 at91rm9200_initialize(18432000, AT91RM9200_BGA);
58 47
59 /* Setup the serial ports and console */ 48 /* DBGU on ttyS0. (Rx & Tx only) */
60 at91_init_serial(&eb9200_uart_config); 49 at91_register_uart(0, 0, 0);
50
51 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
52 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
53 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
54 | ATMEL_UART_RI);
55
56 /* USART2 on ttyS2. (Rx, Tx) - IRDA */
57 at91_register_uart(AT91RM9200_ID_US2, 2, 0);
58
59 /* set serial console to ttyS0 (ie, DBGU) */
60 at91_set_serial_console(0);
61} 61}
62 62
63static void __init eb9200_init_irq(void) 63static void __init eb9200_init_irq(void)
diff --git a/arch/arm/mach-at91/board-ek.c b/arch/arm/mach-at91/board-ek.c
index 0574e50a30dd..74aa4325eab3 100644
--- a/arch/arm/mach-at91/board-ek.c
+++ b/arch/arm/mach-at91/board-ek.c
@@ -45,17 +45,6 @@
45#include "generic.h" 45#include "generic.h"
46 46
47 47
48/*
49 * Serial port configuration.
50 * 0 .. 3 = USART0 .. USART3
51 * 4 = DBGU
52 */
53static struct at91_uart_config __initdata ek_uart_config = {
54 .console_tty = 0, /* ttyS0 */
55 .nr_tty = 2,
56 .tty_map = { 4, 1, -1, -1, -1 } /* ttyS0, ..., ttyS4 */
57};
58
59static void __init ek_map_io(void) 48static void __init ek_map_io(void)
60{ 49{
61 /* Initialize processor: 18.432 MHz crystal */ 50 /* Initialize processor: 18.432 MHz crystal */
@@ -64,8 +53,16 @@ static void __init ek_map_io(void)
64 /* Setup the LEDs */ 53 /* Setup the LEDs */
65 at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2); 54 at91_init_leds(AT91_PIN_PB1, AT91_PIN_PB2);
66 55
67 /* Setup the serial ports and console */ 56 /* DBGU on ttyS0. (Rx & Tx only) */
68 at91_init_serial(&ek_uart_config); 57 at91_register_uart(0, 0, 0);
58
59 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
60 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
61 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
62 | ATMEL_UART_RI);
63
64 /* set serial console to ttyS0 (ie, DBGU) */
65 at91_set_serial_console(0);
69} 66}
70 67
71static void __init ek_init_irq(void) 68static void __init ek_init_irq(void)
@@ -122,7 +119,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
122#define EK_FLASH_SIZE 0x200000 119#define EK_FLASH_SIZE 0x200000
123 120
124static struct physmap_flash_data ek_flash_data = { 121static struct physmap_flash_data ek_flash_data = {
125 .width = 2, 122 .width = 2,
126}; 123};
127 124
128static struct resource ek_flash_resource = { 125static struct resource ek_flash_resource = {
diff --git a/arch/arm/mach-at91/board-kb9202.c b/arch/arm/mach-at91/board-kb9202.c
index 4b39b9cda75b..cb065febd95e 100644
--- a/arch/arm/mach-at91/board-kb9202.c
+++ b/arch/arm/mach-at91/board-kb9202.c
@@ -37,19 +37,10 @@
37#include <asm/arch/board.h> 37#include <asm/arch/board.h>
38#include <asm/arch/gpio.h> 38#include <asm/arch/gpio.h>
39 39
40#include "generic.h" 40#include <asm/arch/at91rm9200_mc.h>
41 41
42#include "generic.h"
42 43
43/*
44 * Serial port configuration.
45 * 0 .. 3 = USART0 .. USART3
46 * 4 = DBGU
47 */
48static struct at91_uart_config __initdata kb9202_uart_config = {
49 .console_tty = 0, /* ttyS0 */
50 .nr_tty = 3,
51 .tty_map = { 4, 0, 1, -1, -1 } /* ttyS0, ..., ttyS4 */
52};
53 44
54static void __init kb9202_map_io(void) 45static void __init kb9202_map_io(void)
55{ 46{
@@ -59,8 +50,20 @@ static void __init kb9202_map_io(void)
59 /* Set up the LEDs */ 50 /* Set up the LEDs */
60 at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18); 51 at91_init_leds(AT91_PIN_PC19, AT91_PIN_PC18);
61 52
62 /* Setup the serial ports and console */ 53 /* DBGU on ttyS0. (Rx & Tx only) */
63 at91_init_serial(&kb9202_uart_config); 54 at91_register_uart(0, 0, 0);
55
56 /* USART0 on ttyS1 (Rx & Tx only) */
57 at91_register_uart(AT91RM9200_ID_US0, 1, 0);
58
59 /* USART1 on ttyS2 (Rx & Tx only) - IRDA (optional) */
60 at91_register_uart(AT91RM9200_ID_US1, 2, 0);
61
62 /* USART3 on ttyS3 (Rx, Tx, CTS, RTS) - RS485 (optional) */
63 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
64
65 /* set serial console to ttyS0 (ie, DBGU) */
66 at91_set_serial_console(0);
64} 67}
65 68
66static void __init kb9202_init_irq(void) 69static void __init kb9202_init_irq(void)
diff --git a/arch/arm/mach-at91/board-qil-a9260.c b/arch/arm/mach-at91/board-qil-a9260.c
new file mode 100644
index 000000000000..99b4ec3818d6
--- /dev/null
+++ b/arch/arm/mach-at91/board-qil-a9260.c
@@ -0,0 +1,255 @@
1/*
2 * linux/arch/arm/mach-at91/board-qil-a9260.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <linux/clk.h>
32
33#include <asm/hardware.h>
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <asm/arch/board.h>
43#include <asm/arch/gpio.h>
44#include <asm/arch/at91_shdwc.h>
45
46#include "generic.h"
47
48
49static void __init ek_map_io(void)
50{
51 /* Initialize processor: 12.000 MHz crystal */
52 at91sam9260_initialize(12000000);
53
54 /* DGBU on ttyS0. (Rx & Tx only) */
55 at91_register_uart(0, 0, 0);
56
57 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
58 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
59 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
60 | ATMEL_UART_RI);
61
62 /* USART1 on ttyS2. (Rx, Tx, CTS, RTS) */
63 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
64
65 /* USART2 on ttyS3. (Rx, Tx, CTS, RTS) */
66 at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS | ATMEL_UART_RTS);
67
68 /* set serial console to ttyS1 (ie, USART0) */
69 at91_set_serial_console(1);
70
71}
72
73static void __init ek_init_irq(void)
74{
75 at91sam9260_init_interrupts(NULL);
76}
77
78
79/*
80 * USB Host port
81 */
82static struct at91_usbh_data __initdata ek_usbh_data = {
83 .ports = 2,
84};
85
86/*
87 * USB Device port
88 */
89static struct at91_udc_data __initdata ek_udc_data = {
90 .vbus_pin = AT91_PIN_PC5,
91 .pullup_pin = 0, /* pull-up driven by UDC */
92};
93
94/*
95 * SPI devices.
96 */
97static struct spi_board_info ek_spi_devices[] = {
98#if defined(CONFIG_RTC_DRV_M41T94)
99 { /* M41T94 RTC */
100 .modalias = "m41t94",
101 .chip_select = 0,
102 .max_speed_hz = 1 * 1000 * 1000,
103 .bus_num = 0,
104 }
105#endif
106};
107
108/*
109 * MACB Ethernet device
110 */
111static struct at91_eth_data __initdata ek_macb_data = {
112 .phy_irq_pin = AT91_PIN_PA31,
113 .is_rmii = 1,
114};
115
116/*
117 * NAND flash
118 */
119static struct mtd_partition __initdata ek_nand_partition[] = {
120 {
121 .name = "Uboot & Kernel",
122 .offset = 0x00000000,
123 .size = 16 * 1024 * 1024,
124 },
125 {
126 .name = "Root FS",
127 .offset = 0x01000000,
128 .size = 120 * 1024 * 1024,
129 },
130 {
131 .name = "FS",
132 .offset = 0x08800000,
133 .size = 120 * 1024 * 1024,
134 },
135};
136
137static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
138{
139 *num_partitions = ARRAY_SIZE(ek_nand_partition);
140 return ek_nand_partition;
141}
142
143static struct at91_nand_data __initdata ek_nand_data = {
144 .ale = 21,
145 .cle = 22,
146// .det_pin = ... not connected
147 .rdy_pin = AT91_PIN_PC13,
148 .enable_pin = AT91_PIN_PC14,
149 .partition_info = nand_partitions,
150#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
151 .bus_width_16 = 1,
152#else
153 .bus_width_16 = 0,
154#endif
155};
156
157/*
158 * MCI (SD/MMC)
159 */
160static struct at91_mmc_data __initdata ek_mmc_data = {
161 .slot_b = 0,
162 .wire4 = 1,
163// .det_pin = ... not connected
164// .wp_pin = ... not connected
165// .vcc_pin = ... not connected
166};
167
168/*
169 * GPIO Buttons
170 */
171#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
172static struct gpio_keys_button ek_buttons[] = {
173 { /* USER PUSH BUTTON */
174 .code = KEY_ENTER,
175 .gpio = AT91_PIN_PB10,
176 .active_low = 1,
177 .desc = "user_pb",
178 .wakeup = 1,
179 }
180};
181
182static struct gpio_keys_platform_data ek_button_data = {
183 .buttons = ek_buttons,
184 .nbuttons = ARRAY_SIZE(ek_buttons),
185};
186
187static struct platform_device ek_button_device = {
188 .name = "gpio-keys",
189 .id = -1,
190 .num_resources = 0,
191 .dev = {
192 .platform_data = &ek_button_data,
193 }
194};
195
196static void __init ek_add_device_buttons(void)
197{
198 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
199 at91_set_deglitch(AT91_PIN_PB10, 1);
200
201 platform_device_register(&ek_button_device);
202}
203#else
204static void __init ek_add_device_buttons(void) {}
205#endif
206
207/*
208 * LEDs
209 */
210static struct gpio_led ek_leds[] = {
211 { /* user_led (green) */
212 .name = "user_led",
213 .gpio = AT91_PIN_PB21,
214 .active_low = 0,
215 .default_trigger = "heartbeat",
216 }
217};
218
219static void __init ek_board_init(void)
220{
221 /* Serial */
222 at91_add_device_serial();
223 /* USB Host */
224 at91_add_device_usbh(&ek_usbh_data);
225 /* USB Device */
226 at91_add_device_udc(&ek_udc_data);
227 /* SPI */
228 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
229 /* NAND */
230 at91_add_device_nand(&ek_nand_data);
231 /* I2C */
232 at91_add_device_i2c(NULL, 0);
233 /* Ethernet */
234 at91_add_device_eth(&ek_macb_data);
235 /* MMC */
236 at91_add_device_mmc(0, &ek_mmc_data);
237 /* Push Buttons */
238 ek_add_device_buttons();
239 /* LEDs */
240 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
241 /* shutdown controller, wakeup button (5 msec low) */
242 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
243 | AT91_SHDW_RTTWKEN);
244}
245
246MACHINE_START(QIL_A9260, "CALAO QIL_A9260")
247 /* Maintainer: calao-systems */
248 .phys_io = AT91_BASE_SYS,
249 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
250 .boot_params = AT91_SDRAM_BASE + 0x100,
251 .timer = &at91sam926x_timer,
252 .map_io = ek_map_io,
253 .init_irq = ek_init_irq,
254 .init_machine = ek_board_init,
255MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
new file mode 100644
index 000000000000..45617c201240
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -0,0 +1,218 @@
1/*
2 * Copyright (C) 2005 SAN People
3 * Copyright (C) 2008 Atmel
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#include <linux/types.h>
21#include <linux/init.h>
22#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/spi/spi.h>
26#include <linux/spi/at73c213.h>
27#include <linux/clk.h>
28
29#include <asm/hardware.h>
30#include <asm/setup.h>
31#include <asm/mach-types.h>
32#include <asm/irq.h>
33
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <asm/arch/board.h>
39#include <asm/arch/gpio.h>
40
41#include "generic.h"
42
43
44static void __init ek_map_io(void)
45{
46 /* Initialize processor: 18.432 MHz crystal */
47 at91sam9260_initialize(18432000);
48
49 /* DGBU on ttyS0. (Rx & Tx only) */
50 at91_register_uart(0, 0, 0);
51
52 /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
53 at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
54 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
55 | ATMEL_UART_RI);
56
57 /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
58 at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
59
60 /* set serial console to ttyS0 (ie, DBGU) */
61 at91_set_serial_console(0);
62}
63
64static void __init ek_init_irq(void)
65{
66 at91sam9260_init_interrupts(NULL);
67}
68
69
70/*
71 * USB Host port
72 */
73static struct at91_usbh_data __initdata ek_usbh_data = {
74 .ports = 2,
75};
76
77/*
78 * USB Device port
79 */
80static struct at91_udc_data __initdata ek_udc_data = {
81 .vbus_pin = AT91_PIN_PC5,
82 .pullup_pin = 0, /* pull-up driven by UDC */
83};
84
85
86/*
87 * SPI devices.
88 */
89static struct spi_board_info ek_spi_devices[] = {
90#if !defined(CONFIG_MMC_AT91)
91 { /* DataFlash chip */
92 .modalias = "mtd_dataflash",
93 .chip_select = 1,
94 .max_speed_hz = 15 * 1000 * 1000,
95 .bus_num = 0,
96 },
97#if defined(CONFIG_MTD_AT91_DATAFLASH_CARD)
98 { /* DataFlash card */
99 .modalias = "mtd_dataflash",
100 .chip_select = 0,
101 .max_speed_hz = 15 * 1000 * 1000,
102 .bus_num = 0,
103 },
104#endif
105#endif
106};
107
108
109/*
110 * MACB Ethernet device
111 */
112static struct at91_eth_data __initdata ek_macb_data = {
113 .phy_irq_pin = AT91_PIN_PA7,
114 .is_rmii = 1,
115};
116
117
118/*
119 * NAND flash
120 */
121static struct mtd_partition __initdata ek_nand_partition[] = {
122 {
123 .name = "Bootstrap",
124 .offset = 0,
125 .size = 4 * 1024 * 1024,
126 },
127 {
128 .name = "Partition 1",
129 .offset = 4 * 1024 * 1024,
130 .size = 60 * 1024 * 1024,
131 },
132 {
133 .name = "Partition 2",
134 .offset = 64 * 1024 * 1024,
135 .size = MTDPART_SIZ_FULL,
136 },
137};
138
139static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
140{
141 *num_partitions = ARRAY_SIZE(ek_nand_partition);
142 return ek_nand_partition;
143}
144
145/* det_pin is not connected */
146static struct at91_nand_data __initdata ek_nand_data = {
147 .ale = 21,
148 .cle = 22,
149 .rdy_pin = AT91_PIN_PC13,
150 .enable_pin = AT91_PIN_PC14,
151 .partition_info = nand_partitions,
152#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
153 .bus_width_16 = 1,
154#else
155 .bus_width_16 = 0,
156#endif
157};
158
159
160/*
161 * MCI (SD/MMC)
162 * det_pin, wp_pin and vcc_pin are not connected
163 */
164static struct at91_mmc_data __initdata ek_mmc_data = {
165 .slot_b = 1,
166 .wire4 = 1,
167};
168
169
170/*
171 * LEDs
172 */
173static struct gpio_led ek_leds[] = {
174 { /* "bottom" led, green, userled1 to be defined */
175 .name = "ds5",
176 .gpio = AT91_PIN_PA6,
177 .active_low = 1,
178 .default_trigger = "none",
179 },
180 { /* "power" led, yellow */
181 .name = "ds1",
182 .gpio = AT91_PIN_PA9,
183 .default_trigger = "heartbeat",
184 }
185};
186
187static void __init ek_board_init(void)
188{
189 /* Serial */
190 at91_add_device_serial();
191 /* USB Host */
192 at91_add_device_usbh(&ek_usbh_data);
193 /* USB Device */
194 at91_add_device_udc(&ek_udc_data);
195 /* SPI */
196 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
197 /* NAND */
198 at91_add_device_nand(&ek_nand_data);
199 /* Ethernet */
200 at91_add_device_eth(&ek_macb_data);
201 /* MMC */
202 at91_add_device_mmc(0, &ek_mmc_data);
203 /* I2C */
204 at91_add_device_i2c(NULL, 0);
205 /* LEDs */
206 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
207}
208
209MACHINE_START(AT91SAM9G20EK, "Atmel AT91SAM9G20-EK")
210 /* Maintainer: Atmel */
211 .phys_io = AT91_BASE_SYS,
212 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
213 .boot_params = AT91_SDRAM_BASE + 0x100,
214 .timer = &at91sam926x_timer,
215 .map_io = ek_map_io,
216 .init_irq = ek_init_irq,
217 .init_machine = ek_board_init,
218MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index ffc0597aee8d..b6a70fc735c3 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -56,6 +56,14 @@ static void __init ek_init_irq(void)
56 56
57 57
58/* 58/*
59 * USB HS Device port
60 */
61static struct usba_platform_data __initdata ek_usba_udc_data = {
62 .vbus_pin = AT91_PIN_PA8,
63};
64
65
66/*
59 * MCI (SD/MMC) 67 * MCI (SD/MMC)
60 */ 68 */
61static struct at91_mmc_data __initdata ek_mmc_data = { 69static struct at91_mmc_data __initdata ek_mmc_data = {
@@ -175,6 +183,8 @@ static void __init ek_board_init(void)
175{ 183{
176 /* Serial */ 184 /* Serial */
177 at91_add_device_serial(); 185 at91_add_device_serial();
186 /* USB HS */
187 at91_add_device_usba(&ek_usba_udc_data);
178 /* I2C */ 188 /* I2C */
179 at91_add_device_i2c(NULL, 0); 189 at91_add_device_i2c(NULL, 0);
180 /* NAND */ 190 /* NAND */
diff --git a/arch/arm/mach-at91/board-usb-a9260.c b/arch/arm/mach-at91/board-usb-a9260.c
new file mode 100644
index 000000000000..837aedf8ffeb
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9260.c
@@ -0,0 +1,215 @@
1/*
2 * linux/arch/arm/mach-at91/board-usb-a9260.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2006 Atmel
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31#include <linux/clk.h>
32
33#include <asm/hardware.h>
34#include <asm/setup.h>
35#include <asm/mach-types.h>
36#include <asm/irq.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/map.h>
40#include <asm/mach/irq.h>
41
42#include <asm/arch/board.h>
43#include <asm/arch/gpio.h>
44#include <asm/arch/at91_shdwc.h>
45
46#include "generic.h"
47
48
49static void __init ek_map_io(void)
50{
51 /* Initialize processor: 12.000 MHz crystal */
52 at91sam9260_initialize(12000000);
53
54 /* DGBU on ttyS0. (Rx & Tx only) */
55 at91_register_uart(0, 0, 0);
56
57 /* set serial console to ttyS0 (ie, DBGU) */
58 at91_set_serial_console(0);
59}
60
61static void __init ek_init_irq(void)
62{
63 at91sam9260_init_interrupts(NULL);
64}
65
66
67/*
68 * USB Host port
69 */
70static struct at91_usbh_data __initdata ek_usbh_data = {
71 .ports = 2,
72};
73
74/*
75 * USB Device port
76 */
77static struct at91_udc_data __initdata ek_udc_data = {
78 .vbus_pin = AT91_PIN_PC5,
79 .pullup_pin = 0, /* pull-up driven by UDC */
80};
81
82/*
83 * MACB Ethernet device
84 */
85static struct at91_eth_data __initdata ek_macb_data = {
86 .phy_irq_pin = AT91_PIN_PA31,
87 .is_rmii = 1,
88};
89
90/*
91 * NAND flash
92 */
93static struct mtd_partition __initdata ek_nand_partition[] = {
94 {
95 .name = "Uboot & Kernel",
96 .offset = 0x00000000,
97 .size = 16 * 1024 * 1024,
98 },
99 {
100 .name = "Root FS",
101 .offset = 0x01000000,
102 .size = 120 * 1024 * 1024,
103 },
104 {
105 .name = "FS",
106 .offset = 0x08800000,
107 .size = 120 * 1024 * 1024,
108 }
109};
110
111static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
112{
113 *num_partitions = ARRAY_SIZE(ek_nand_partition);
114 return ek_nand_partition;
115}
116
117static struct at91_nand_data __initdata ek_nand_data = {
118 .ale = 21,
119 .cle = 22,
120// .det_pin = ... not connected
121 .rdy_pin = AT91_PIN_PC13,
122 .enable_pin = AT91_PIN_PC14,
123 .partition_info = nand_partitions,
124#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
125 .bus_width_16 = 1,
126#else
127 .bus_width_16 = 0,
128#endif
129};
130
131/*
132 * GPIO Buttons
133 */
134
135#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
136static struct gpio_keys_button ek_buttons[] = {
137 { /* USER PUSH BUTTON */
138 .code = KEY_ENTER,
139 .gpio = AT91_PIN_PB10,
140 .active_low = 1,
141 .desc = "user_pb",
142 .wakeup = 1,
143 }
144};
145
146static struct gpio_keys_platform_data ek_button_data = {
147 .buttons = ek_buttons,
148 .nbuttons = ARRAY_SIZE(ek_buttons),
149};
150
151static struct platform_device ek_button_device = {
152 .name = "gpio-keys",
153 .id = -1,
154 .num_resources = 0,
155 .dev = {
156 .platform_data = &ek_button_data,
157 }
158};
159
160static void __init ek_add_device_buttons(void)
161{
162 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
163 at91_set_deglitch(AT91_PIN_PB10, 1);
164
165 platform_device_register(&ek_button_device);
166}
167#else
168static void __init ek_add_device_buttons(void) {}
169#endif
170
171/*
172 * LEDs
173 */
174static struct gpio_led ek_leds[] = {
175 { /* user_led (green) */
176 .name = "user_led",
177 .gpio = AT91_PIN_PB21,
178 .active_low = 0,
179 .default_trigger = "heartbeat",
180 }
181};
182
183static void __init ek_board_init(void)
184{
185 /* Serial */
186 at91_add_device_serial();
187 /* USB Host */
188 at91_add_device_usbh(&ek_usbh_data);
189 /* USB Device */
190 at91_add_device_udc(&ek_udc_data);
191 /* NAND */
192 at91_add_device_nand(&ek_nand_data);
193 /* I2C */
194 at91_add_device_i2c(NULL, 0);
195 /* Ethernet */
196 at91_add_device_eth(&ek_macb_data);
197 /* Push Buttons */
198 ek_add_device_buttons();
199 /* LEDs */
200 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
201 /* shutdown controller, wakeup button (5 msec low) */
202 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
203 | AT91_SHDW_RTTWKEN);
204}
205
206MACHINE_START(USB_A9260, "CALAO USB_A9260")
207 /* Maintainer: calao-systems */
208 .phys_io = AT91_BASE_SYS,
209 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
210 .boot_params = AT91_SDRAM_BASE + 0x100,
211 .timer = &at91sam926x_timer,
212 .map_io = ek_map_io,
213 .init_irq = ek_init_irq,
214 .init_machine = ek_board_init,
215MACHINE_END
diff --git a/arch/arm/mach-at91/board-usb-a9263.c b/arch/arm/mach-at91/board-usb-a9263.c
new file mode 100644
index 000000000000..95800d32bd49
--- /dev/null
+++ b/arch/arm/mach-at91/board-usb-a9263.c
@@ -0,0 +1,230 @@
1/*
2 * linux/arch/arm/mach-at91/board-usb-a9263.c
3 *
4 * Copyright (C) 2005 SAN People
5 * Copyright (C) 2007 Atmel Corporation.
6 * Copyright (C) 2007 Calao-systems
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/mm.h>
26#include <linux/module.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29#include <linux/gpio_keys.h>
30#include <linux/input.h>
31
32#include <asm/hardware.h>
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/irq.h>
36
37#include <asm/mach/arch.h>
38#include <asm/mach/map.h>
39#include <asm/mach/irq.h>
40
41#include <asm/arch/board.h>
42#include <asm/arch/gpio.h>
43#include <asm/arch/at91_shdwc.h>
44
45#include "generic.h"
46
47
48static void __init ek_map_io(void)
49{
50 /* Initialize processor: 12.00 MHz crystal */
51 at91sam9263_initialize(12000000);
52
53 /* DGBU on ttyS0. (Rx & Tx only) */
54 at91_register_uart(0, 0, 0);
55
56 /* set serial console to ttyS0 (ie, DBGU) */
57 at91_set_serial_console(0);
58}
59
60static void __init ek_init_irq(void)
61{
62 at91sam9263_init_interrupts(NULL);
63}
64
65
66/*
67 * USB Host port
68 */
69static struct at91_usbh_data __initdata ek_usbh_data = {
70 .ports = 2,
71};
72
73/*
74 * USB Device port
75 */
76static struct at91_udc_data __initdata ek_udc_data = {
77 .vbus_pin = AT91_PIN_PB11,
78 .pullup_pin = 0, /* pull-up driven by UDC */
79};
80
81/*
82 * SPI devices.
83 */
84static struct spi_board_info ek_spi_devices[] = {
85#if !defined(CONFIG_MMC_AT91)
86 { /* DataFlash chip */
87 .modalias = "mtd_dataflash",
88 .chip_select = 0,
89 .max_speed_hz = 15 * 1000 * 1000,
90 .bus_num = 0,
91 }
92#endif
93};
94
95/*
96 * MACB Ethernet device
97 */
98static struct at91_eth_data __initdata ek_macb_data = {
99 .phy_irq_pin = AT91_PIN_PE31,
100 .is_rmii = 1,
101};
102
103/*
104 * NAND flash
105 */
106static struct mtd_partition __initdata ek_nand_partition[] = {
107 {
108 .name = "Linux Kernel",
109 .offset = 0x00000000,
110 .size = 16 * 1024 * 1024,
111 },
112 {
113 .name = "Root FS",
114 .offset = 0x01000000,
115 .size = 120 * 1024 * 1024,
116 },
117 {
118 .name = "FS",
119 .offset = 0x08800000,
120 .size = 120 * 1024 * 1024,
121 }
122};
123
124static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
125{
126 *num_partitions = ARRAY_SIZE(ek_nand_partition);
127 return ek_nand_partition;
128}
129
130static struct at91_nand_data __initdata ek_nand_data = {
131 .ale = 21,
132 .cle = 22,
133// .det_pin = ... not connected
134 .rdy_pin = AT91_PIN_PA22,
135 .enable_pin = AT91_PIN_PD15,
136 .partition_info = nand_partitions,
137#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
138 .bus_width_16 = 1,
139#else
140 .bus_width_16 = 0,
141#endif
142};
143
144/*
145 * GPIO Buttons
146 */
147#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
148static struct gpio_keys_button ek_buttons[] = {
149 { /* USER PUSH BUTTON */
150 .code = KEY_ENTER,
151 .gpio = AT91_PIN_PB10,
152 .active_low = 1,
153 .desc = "user_pb",
154 .wakeup = 1,
155 }
156};
157
158static struct gpio_keys_platform_data ek_button_data = {
159 .buttons = ek_buttons,
160 .nbuttons = ARRAY_SIZE(ek_buttons),
161};
162
163static struct platform_device ek_button_device = {
164 .name = "gpio-keys",
165 .id = -1,
166 .num_resources = 0,
167 .dev = {
168 .platform_data = &ek_button_data,
169 }
170};
171
172static void __init ek_add_device_buttons(void)
173{
174 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* user push button, pull up enabled */
175 at91_set_deglitch(AT91_PIN_PB10, 1);
176
177 platform_device_register(&ek_button_device);
178}
179#else
180static void __init ek_add_device_buttons(void) {}
181#endif
182
183/*
184 * LEDs
185 */
186static struct gpio_led ek_leds[] = {
187 { /* user_led (green) */
188 .name = "user_led",
189 .gpio = AT91_PIN_PB21,
190 .active_low = 1,
191 .default_trigger = "heartbeat",
192 }
193};
194
195
196static void __init ek_board_init(void)
197{
198 /* Serial */
199 at91_add_device_serial();
200 /* USB Host */
201 at91_add_device_usbh(&ek_usbh_data);
202 /* USB Device */
203 at91_add_device_udc(&ek_udc_data);
204 /* SPI */
205 at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
206 /* Ethernet */
207 at91_add_device_eth(&ek_macb_data);
208 /* NAND */
209 at91_add_device_nand(&ek_nand_data);
210 /* I2C */
211 at91_add_device_i2c(NULL, 0);
212 /* Push Buttons */
213 ek_add_device_buttons();
214 /* LEDs */
215 at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
216 /* shutdown controller, wakeup button (5 msec low) */
217 at91_sys_write(AT91_SHDW_MR, AT91_SHDW_CPTWK0_(10) | AT91_SHDW_WKMODE0_LOW
218 | AT91_SHDW_RTTWKEN);
219}
220
221MACHINE_START(USB_A9263, "CALAO USB_A9263")
222 /* Maintainer: calao-systems */
223 .phys_io = AT91_BASE_SYS,
224 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
225 .boot_params = AT91_SDRAM_BASE + 0x100,
226 .timer = &at91sam926x_timer,
227 .map_io = ek_map_io,
228 .init_irq = ek_init_irq,
229 .init_machine = ek_board_init,
230MACHINE_END
diff --git a/arch/arm/mach-at91/board-yl-9200.c b/arch/arm/mach-at91/board-yl-9200.c
index b5717108991d..7079050ab88d 100755
--- a/arch/arm/mach-at91/board-yl-9200.c
+++ b/arch/arm/mach-at91/board-yl-9200.c
@@ -1,11 +1,10 @@
1/* 1/*
2 * linux/arch/arm/mach-at91/board-yl-9200.c 2 * linux/arch/arm/mach-at91/board-yl-9200.c
3 * 3 *
4 * Adapted from: 4 * Adapted from various board files in arch/arm/mach-at91
5 *various board files in 5 *
6 * /arch/arm/mach-at91 6 * Modifications for YL-9200 platform:
7 * modifications to convert to YL-9200 platform 7 * Copyright (C) 2007 S. Birtles
8 * Copyright (C) 2007 S.Birtles
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License as published by
@@ -26,13 +25,14 @@
26#include <linux/init.h> 25#include <linux/init.h>
27#include <linux/mm.h> 26#include <linux/mm.h>
28#include <linux/module.h> 27#include <linux/module.h>
28#include <linux/dma-mapping.h>
29#include <linux/platform_device.h> 29#include <linux/platform_device.h>
30#include <linux/spi/spi.h> 30#include <linux/spi/spi.h>
31/*#include <linux/can_bus/candata.h>*/
32#include <linux/spi/ads7846.h> 31#include <linux/spi/ads7846.h>
33#include <linux/mtd/physmap.h> 32#include <linux/mtd/physmap.h>
33#include <linux/gpio_keys.h>
34#include <linux/input.h>
34 35
35/*#include <sound/gpio_sounder.h>*/
36#include <asm/hardware.h> 36#include <asm/hardware.h>
37#include <asm/setup.h> 37#include <asm/setup.h>
38#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -45,179 +45,108 @@
45#include <asm/arch/board.h> 45#include <asm/arch/board.h>
46#include <asm/arch/gpio.h> 46#include <asm/arch/gpio.h>
47#include <asm/arch/at91rm9200_mc.h> 47#include <asm/arch/at91rm9200_mc.h>
48#include <linux/gpio_keys.h>
49#include <linux/input.h>
50 48
51#include "generic.h" 49#include "generic.h"
52#include <asm/arch/at91_pio.h>
53 50
54#define YL_9200_FLASH_BASE AT91_CHIPSELECT_0
55#define YL_9200_FLASH_SIZE 0x800000
56 51
57/* 52static void __init yl9200_map_io(void)
58 * Serial port configuration. 53{
59 * 0 .. 3 = USART0 .. USART3 54 /* Initialize processor: 18.432 MHz crystal */
60 * 4 = DBGU 55 at91rm9200_initialize(18432000, AT91RM9200_PQFP);
61 *atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL
62 *atmel_usart.1: ttyS1 at MMIO 0xfffc0000 (irq = 6) is a ATMEL_SERIAL
63 *atmel_usart.2: ttyS2 at MMIO 0xfffc4000 (irq = 7) is a ATMEL_SERIAL
64 *atmel_usart.3: ttyS3 at MMIO 0xfffc8000 (irq = 8) is a ATMEL_SERIAL
65 *atmel_usart.4: ttyS4 at MMIO 0xfffcc000 (irq = 9) is a ATMEL_SERIAL
66 * on the YL-9200 we are sitting at the following
67 *ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL
68 *ttyS1 at MMIO 0xfefc4000 (irq = 7) is a AT91_SERIAL
69 */
70 56
71/* extern void __init yl_9200_add_device_sounder(struct gpio_sounder *sounders, int nr);*/ 57 /* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */
58 at91_init_leds(AT91_PIN_PB16, AT91_PIN_PB17);
72 59
73static struct at91_uart_config __initdata yl_9200_uart_config = { 60 /* DBGU on ttyS0. (Rx & Tx only) */
74 .console_tty = 0, /* ttyS0 */ 61 at91_register_uart(0, 0, 0);
75 .nr_tty = 3,
76 .tty_map = { 4, 1, 0, -1, -1 } /* ttyS0, ..., ttyS4 */
77};
78 62
79static void __init yl_9200_map_io(void) 63 /* USART1 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
80{ 64 at91_register_uart(AT91RM9200_ID_US1, 1, ATMEL_UART_CTS | ATMEL_UART_RTS
81 /* Initialize processor: 18.432 MHz crystal */ 65 | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD
82 /*Also initialises register clocks & gpio*/ 66 | ATMEL_UART_RI);
83 at91rm9200_initialize(18432000, AT91RM9200_PQFP); /*we have a 3 bank system*/
84 67
85 /* Setup the serial ports and console */ 68 /* USART0 on ttyS2. (Rx & Tx only to JP3) */
86 at91_init_serial(&yl_9200_uart_config); 69 at91_register_uart(AT91RM9200_ID_US0, 2, 0);
87 70
88 /* Setup the LEDs D2=PB17,D3=PB16 */ 71 /* USART3 on ttyS3. (Rx, Tx, RTS - RS485 interface) */
89 at91_init_leds(AT91_PIN_PB16,AT91_PIN_PB17); /*cpu-led,timer-led*/ 72 at91_register_uart(AT91RM9200_ID_US3, 3, ATMEL_UART_RTS);
73
74 /* set serial console to ttyS0 (ie, DBGU) */
75 at91_set_serial_console(0);
90} 76}
91 77
92static void __init yl_9200_init_irq(void) 78static void __init yl9200_init_irq(void)
93{ 79{
94 at91rm9200_init_interrupts(NULL); 80 at91rm9200_init_interrupts(NULL);
95} 81}
96 82
97static struct at91_eth_data __initdata yl_9200_eth_data = {
98 .phy_irq_pin = AT91_PIN_PB28,
99 .is_rmii = 1,
100};
101 83
102static struct at91_usbh_data __initdata yl_9200_usbh_data = { 84/*
103 .ports = 1, /* this should be 1 not 2 for the Yl9200*/ 85 * LEDs
86 */
87static struct gpio_led yl9200_leds[] = {
88 { /* D2 */
89 .name = "led2",
90 .gpio = AT91_PIN_PB17,
91 .active_low = 1,
92 .default_trigger = "timer",
93 },
94 { /* D3 */
95 .name = "led3",
96 .gpio = AT91_PIN_PB16,
97 .active_low = 1,
98 .default_trigger = "heartbeat",
99 },
100 { /* D4 */
101 .name = "led4",
102 .gpio = AT91_PIN_PB15,
103 .active_low = 1,
104 },
105 { /* D5 */
106 .name = "led5",
107 .gpio = AT91_PIN_PB8,
108 .active_low = 1,
109 }
104}; 110};
105 111
106static struct at91_udc_data __initdata yl_9200_udc_data = {
107/*on sheet 7 Schemitic rev 1.0*/
108 .pullup_pin = AT91_PIN_PC4,
109 .vbus_pin= AT91_PIN_PC5,
110 .pullup_active_low = 1, /*ACTIVE LOW!! due to PNP transistor on page 7*/
111
112};
113/* 112/*
114static struct at91_cf_data __initdata yl_9200_cf_data = { 113 * Ethernet
115TODO S.BIRTLES 114 */
116 .det_pin = AT91_PIN_xxx, 115static struct at91_eth_data __initdata yl9200_eth_data = {
117 .rst_pin = AT91_PIN_xxx, 116 .phy_irq_pin = AT91_PIN_PB28,
118 .irq_pin = ... not connected 117 .is_rmii = 1,
119 .vcc_pin = ... always powered
120
121}; 118};
122*/
123static struct at91_mmc_data __initdata yl_9200_mmc_data = {
124 .det_pin = AT91_PIN_PB9, /*THIS LOOKS CORRECT SHEET7*/
125/* .wp_pin = ... not connected SHEET7*/
126 .slot_b = 0,
127 .wire4 = 1,
128 119
120/*
121 * USB Host
122 */
123static struct at91_usbh_data __initdata yl9200_usbh_data = {
124 .ports = 1, /* PQFP version of AT91RM9200 */
129}; 125};
130 126
131/* -------------------------------------------------------------------- 127/*
132 * Touch screen 128 * USB Device
133 * -------------------------------------------------------------------- */ 129 */
134#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 130static struct at91_udc_data __initdata yl9200_udc_data = {
135static int ads7843_pendown_state(void) 131 .pullup_pin = AT91_PIN_PC4,
136{ 132 .vbus_pin = AT91_PIN_PC5,
137 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */ 133 .pullup_active_low = 1, /* Active Low due to PNP transistor (pg 7) */
138}
139
140static void __init at91_init_device_ts(void)
141{
142/*IMPORTANT NOTE THE SPI INTERFACE IS ALREADY CONFIGURED BY XXX_DEVICES.C
143THAT IS TO SAY THAT MISO,MOSI,SPCK AND CS are already configured
144we only need to enable the other datapins which are:
145PB10/RK1 BUSY
146*/
147/* Touchscreen BUSY signal , pin,use pullup ( TODO not currently used in the ADS7843/6.c driver)*/
148at91_set_gpio_input(AT91_PIN_PB10, 1);
149}
150
151#else
152static void __init at91_init_device_ts(void) {}
153#endif
154
155static struct ads7846_platform_data ads_info = {
156 .model = 7843,
157 .x_min = 150,
158 .x_max = 3830,
159 .y_min = 190,
160 .y_max = 3830,
161 .vref_delay_usecs = 100,
162/* for a 8" touch screen*/
163 //.x_plate_ohms = 603, //= 450, S.Birtles TODO
164 //.y_plate_ohms = 332, //= 250, S.Birtles TODO
165/*for a 10.4" touch screen*/
166 //.x_plate_ohms =611,
167 //.y_plate_ohms =325,
168
169 .x_plate_ohms = 576,
170 .y_plate_ohms = 366,
171 //
172 .pressure_max = 15000, /*generally nonsense on the 7843*/
173 /*number of times to send query to chip in a given run 0 equals one time (do not set to 0!! ,there is a bug in ADS 7846 code)*/
174 .debounce_max = 1,
175 .debounce_rep = 0,
176 .debounce_tol = (~0),
177 .get_pendown_state = ads7843_pendown_state,
178};
179 134
180/*static struct canbus_platform_data can_info = {
181 .model = 2510,
182}; 135};
183*/
184
185static struct spi_board_info yl_9200_spi_devices[] = {
186/*this sticks it at:
187 /sys/devices/platform/atmel_spi.0/spi0.0
188 /sys/bus/platform/devices/
189Documentation/spi IIRC*/
190 136
191#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) 137/*
192 /*(this IS correct 04-NOV-2007)*/ 138 * MMC
193 { 139 */
194 .modalias = "ads7846", /* because the driver is called ads7846*/ 140static struct at91_mmc_data __initdata yl9200_mmc_data = {
195 .chip_select = 0, /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */ 141 .det_pin = AT91_PIN_PB9,
196/*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select*/ 142 // .wp_pin = ... not connected
197 /*.controller_data =AT91_PIN_PA3 ,*/ 143 .wire4 = 1,
198 .max_speed_hz = 5000*26, /*(4700 * 26)-125000 * 26, (max sample rate @ 3V) * (cmd + data + overhead) */
199 .bus_num = 0,
200 .platform_data = &ads_info,
201 .irq = AT91_PIN_PB11,
202 },
203#endif
204/*we need to put our CAN driver data here!!*/
205/*THIS IS ALL DUMMY DATA*/
206/* {
207 .modalias = "mcp2510", //DUMMY for MCP2510 chip
208 .chip_select = 1,*/ /*THIS MUST BE AN INDEX INTO AN ARRAY OF pins */
209 /*this is ONLY TO BE USED if chipselect above is not used, it passes a pin directly for the chip select */
210 /* .controller_data =AT91_PIN_PA4 ,
211 .max_speed_hz = 25000 * 26,
212 .bus_num = 0,
213 .platform_data = &can_info,
214 .irq = AT91_PIN_PC0,
215 },
216 */
217 //max SPI chip needs to go here
218}; 144};
219 145
220static struct mtd_partition __initdata yl_9200_nand_partition[] = { 146/*
147 * NAND Flash
148 */
149static struct mtd_partition __initdata yl9200_nand_partition[] = {
221 { 150 {
222 .name = "AT91 NAND partition 1, boot", 151 .name = "AT91 NAND partition 1, boot",
223 .offset = 0, 152 .offset = 0,
@@ -242,442 +171,434 @@ static struct mtd_partition __initdata yl_9200_nand_partition[] = {
242 .name = "AT91 NAND partition 5, ext-fs", 171 .name = "AT91 NAND partition 5, ext-fs",
243 .offset = 32 * SZ_1M, 172 .offset = 32 * SZ_1M,
244 .size = 32 * SZ_1M 173 .size = 32 * SZ_1M
245 }, 174 }
246}; 175};
247 176
248static struct mtd_partition * __init nand_partitions(int size, int *num_partitions) 177static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
249{ 178{
250 *num_partitions = ARRAY_SIZE(yl_9200_nand_partition); 179 *num_partitions = ARRAY_SIZE(yl9200_nand_partition);
251 return yl_9200_nand_partition; 180 return yl9200_nand_partition;
252} 181}
253 182
254static struct at91_nand_data __initdata yl_9200_nand_data = { 183static struct at91_nand_data __initdata yl9200_nand_data = {
255 .ale= 6, 184 .ale = 6,
256 .cle= 7, 185 .cle = 7,
257 /*.det_pin = AT91_PIN_PCxx,*/ /*we don't have a det pin because NandFlash is fixed to board*/ 186 // .det_pin = ... not connected
258 .rdy_pin = AT91_PIN_PC14, /*R/!B Sheet10*/ 187 .rdy_pin = AT91_PIN_PC14, /* R/!B (Sheet10) */
259 .enable_pin = AT91_PIN_PC15, /*!CE Sheet10 */ 188 .enable_pin = AT91_PIN_PC15, /* !CE (Sheet10) */
260 .partition_info = nand_partitions, 189 .partition_info = nand_partitions,
261}; 190};
262 191
263
264
265/* 192/*
266TODO S.Birtles 193 * NOR Flash
267potentially a problem with the size above 194 */
268physmap platform flash device: 00800000 at 10000000 195#define YL9200_FLASH_BASE AT91_CHIPSELECT_0
269physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank 196#define YL9200_FLASH_SIZE 0x1000000
270NOR chip too large to fit in mapping. Attempting to cope...
271 Intel/Sharp Extended Query Table at 0x0031
272Using buffer write method
273cfi_cmdset_0001: Erase suspend on write enabled
274Reducing visibility of 16384KiB chip to 8192KiB
275*/
276 197
277static struct mtd_partition yl_9200_flash_partitions[] = { 198static struct mtd_partition yl9200_flash_partitions[] = {
199 {
200 .name = "Bootloader",
201 .size = 0x00040000,
202 .offset = 0,
203 .mask_flags = MTD_WRITEABLE, /* force read-only */
204 },
278 { 205 {
279 .name = "Bootloader", 206 .name = "Kernel",
280 .size = 0x00040000, 207 .size = 0x001C0000,
281 .offset = 0, 208 .offset = 0x00040000,
282 .mask_flags = MTD_WRITEABLE /* force read-only */ 209 },
283 },{ 210 {
284 .name = "Kernel", 211 .name = "Filesystem",
285 .size = 0x001C0000, 212 .size = MTDPART_SIZ_FULL,
286 .offset = 0x00040000, 213 .offset = 0x00200000
287 },{
288 .name = "Filesystem",
289 .size = MTDPART_SIZ_FULL,
290 .offset = 0x00200000
291 } 214 }
292
293}; 215};
294 216
295static struct physmap_flash_data yl_9200_flash_data = { 217static struct physmap_flash_data yl9200_flash_data = {
296 .width = 2, 218 .width = 2,
297 .parts = yl_9200_flash_partitions, 219 .parts = yl9200_flash_partitions,
298 .nr_parts = ARRAY_SIZE(yl_9200_flash_partitions), 220 .nr_parts = ARRAY_SIZE(yl9200_flash_partitions),
299}; 221};
300 222
301static struct resource yl_9200_flash_resources[] = { 223static struct resource yl9200_flash_resources[] = {
302{ 224 {
303 .start = YL_9200_FLASH_BASE, 225 .start = YL9200_FLASH_BASE,
304 .end = YL_9200_FLASH_BASE + YL_9200_FLASH_SIZE - 1, 226 .end = YL9200_FLASH_BASE + YL9200_FLASH_SIZE - 1,
305 .flags = IORESOURCE_MEM, 227 .flags = IORESOURCE_MEM,
306 } 228 }
307}; 229};
308 230
309static struct platform_device yl_9200_flash = { 231static struct platform_device yl9200_flash = {
310 .name = "physmap-flash", 232 .name = "physmap-flash",
311 .id = 0, 233 .id = 0,
312 .dev = { 234 .dev = {
313 .platform_data = &yl_9200_flash_data, 235 .platform_data = &yl9200_flash_data,
314 }, 236 },
315 .resource = yl_9200_flash_resources, 237 .resource = yl9200_flash_resources,
316 .num_resources = ARRAY_SIZE(yl_9200_flash_resources), 238 .num_resources = ARRAY_SIZE(yl9200_flash_resources),
317}; 239};
318 240
319 241/*
320static struct gpio_led yl_9200_leds[] = { 242 * I2C (TWI)
321/*D2 &D3 are passed directly in via at91_init_leds*/ 243 */
322 { 244static struct i2c_board_info __initdata yl9200_i2c_devices[] = {
323 .name = "led4", /*D4*/ 245 { /* EEPROM */
324 .gpio = AT91_PIN_PB15, 246 I2C_BOARD_INFO("24c128", 0x50),
325 .active_low = 1,
326 .default_trigger = "heartbeat",
327 /*.default_trigger = "timer",*/
328 },
329 {
330 .name = "led5", /*D5*/
331 .gpio = AT91_PIN_PB8,
332 .active_low = 1,
333 .default_trigger = "heartbeat",
334 }
335};
336
337//static struct gpio_sounder yl_9200_sounder[] = {*/
338/*This is a simple speaker attached to a gpo line*/
339
340// {
341// .name = "Speaker", /*LS1*/
342// .gpio = AT91_PIN_PA22,
343// .active_low = 0,
344// .default_trigger = "heartbeat",
345 /*.default_trigger = "timer",*/
346// },
347//};
348
349
350
351static struct i2c_board_info __initdata yl_9200_i2c_devices[] = {
352 {
353 /*TODO*/
354 I2C_BOARD_INFO("CS4334", 0x00),
355 } 247 }
356}; 248};
357 249
358 250/*
359 /*
360 * GPIO Buttons 251 * GPIO Buttons
361 */ 252*/
362#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 253#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
363static struct gpio_keys_button yl_9200_buttons[] = { 254static struct gpio_keys_button yl9200_buttons[] = {
364 { 255 {
365 .gpio = AT91_PIN_PA24, 256 .gpio = AT91_PIN_PA24,
366 .code = BTN_2, 257 .code = BTN_2,
367 .desc = "SW2", 258 .desc = "SW2",
368 .active_low = 1, 259 .active_low = 1,
369 .wakeup = 1, 260 .wakeup = 1,
370 }, 261 },
371 { 262 {
372 .gpio = AT91_PIN_PB1, 263 .gpio = AT91_PIN_PB1,
373 .code = BTN_3, 264 .code = BTN_3,
374 .desc = "SW3", 265 .desc = "SW3",
375 .active_low = 1, 266 .active_low = 1,
376 .wakeup = 1, 267 .wakeup = 1,
377 }, 268 },
378 { 269 {
379 .gpio = AT91_PIN_PB2, 270 .gpio = AT91_PIN_PB2,
380 .code = BTN_4, 271 .code = BTN_4,
381 .desc = "SW4", 272 .desc = "SW4",
382 .active_low = 1, 273 .active_low = 1,
383 .wakeup = 1, 274 .wakeup = 1,
384 }, 275 },
385 { 276 {
386 .gpio = AT91_PIN_PB6, 277 .gpio = AT91_PIN_PB6,
387 .code = BTN_5, 278 .code = BTN_5,
388 .desc = "SW5", 279 .desc = "SW5",
389 .active_low = 1, 280 .active_low = 1,
390 .wakeup = 1, 281 .wakeup = 1,
391 }, 282 }
392
393}; 283};
394 284
395static struct gpio_keys_platform_data yl_9200_button_data = { 285static struct gpio_keys_platform_data yl9200_button_data = {
396 .buttons = yl_9200_buttons, 286 .buttons = yl9200_buttons,
397 .nbuttons = ARRAY_SIZE(yl_9200_buttons), 287 .nbuttons = ARRAY_SIZE(yl9200_buttons),
398}; 288};
399 289
400static struct platform_device yl_9200_button_device = { 290static struct platform_device yl9200_button_device = {
401 .name = "gpio-keys", 291 .name = "gpio-keys",
402 .id = -1, 292 .id = -1,
403 .num_resources = 0, 293 .num_resources = 0,
404 .dev = { 294 .dev = {
405 .platform_data = &yl_9200_button_data, 295 .platform_data = &yl9200_button_data,
406 } 296 }
407}; 297};
408 298
409static void __init yl_9200_add_device_buttons(void) 299static void __init yl9200_add_device_buttons(void)
410{ 300{
411 //SW2 301 at91_set_gpio_input(AT91_PIN_PA24, 1); /* SW2 */
412 at91_set_gpio_input(AT91_PIN_PA24, 0);
413 at91_set_deglitch(AT91_PIN_PA24, 1); 302 at91_set_deglitch(AT91_PIN_PA24, 1);
414 303 at91_set_gpio_input(AT91_PIN_PB1, 1); /* SW3 */
415 //SW3
416 at91_set_gpio_input(AT91_PIN_PB1, 0);
417 at91_set_deglitch(AT91_PIN_PB1, 1); 304 at91_set_deglitch(AT91_PIN_PB1, 1);
418 //SW4 305 at91_set_gpio_input(AT91_PIN_PB2, 1); /* SW4 */
419 at91_set_gpio_input(AT91_PIN_PB2, 0);
420 at91_set_deglitch(AT91_PIN_PB2, 1); 306 at91_set_deglitch(AT91_PIN_PB2, 1);
421 307 at91_set_gpio_input(AT91_PIN_PB6, 1); /* SW5 */
422 //SW5
423 at91_set_gpio_input(AT91_PIN_PB6, 0);
424 at91_set_deglitch(AT91_PIN_PB6, 1); 308 at91_set_deglitch(AT91_PIN_PB6, 1);
425 309
310 /* Enable buttons (Sheet 5) */
311 at91_set_gpio_output(AT91_PIN_PB7, 1);
312
313 platform_device_register(&yl9200_button_device);
314}
315#else
316static void __init yl9200_add_device_buttons(void) {}
317#endif
318
319/*
320 * Touchscreen
321 */
322#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
323static int ads7843_pendown_state(void)
324{
325 return !at91_get_gpio_value(AT91_PIN_PB11); /* Touchscreen PENIRQ */
326}
327
328static struct ads7846_platform_data ads_info = {
329 .model = 7843,
330 .x_min = 150,
331 .x_max = 3830,
332 .y_min = 190,
333 .y_max = 3830,
334 .vref_delay_usecs = 100,
335
336 /* For a 8" touch-screen */
337 // .x_plate_ohms = 603,
338 // .y_plate_ohms = 332,
339
340 /* For a 10.4" touch-screen */
341 // .x_plate_ohms = 611,
342 // .y_plate_ohms = 325,
343
344 .x_plate_ohms = 576,
345 .y_plate_ohms = 366,
346
347 .pressure_max = 15000, /* generally nonsense on the 7843 */
348 .debounce_max = 1,
349 .debounce_rep = 0,
350 .debounce_tol = (~0),
351 .get_pendown_state = ads7843_pendown_state,
352};
426 353
427 at91_set_gpio_output(AT91_PIN_PB7, 1); /* #TURN BUTTONS ON, SHEET 5 of schematics */ 354static void __init yl9200_add_device_ts(void)
428 platform_device_register(&yl_9200_button_device); 355{
356 at91_set_gpio_input(AT91_PIN_PB11, 1); /* Touchscreen interrupt pin */
357 at91_set_gpio_input(AT91_PIN_PB10, 1); /* Touchscreen BUSY signal - not used! */
429} 358}
430#else 359#else
431static void __init yl_9200_add_device_buttons(void) {} 360static void __init yl9200_add_device_ts(void) {}
361#endif
362
363/*
364 * SPI devices
365 */
366static struct spi_board_info yl9200_spi_devices[] = {
367#if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
368 { /* Touchscreen */
369 .modalias = "ads7846",
370 .chip_select = 0,
371 .max_speed_hz = 5000 * 26,
372 .platform_data = &ads_info,
373 .irq = AT91_PIN_PB11,
374 },
432#endif 375#endif
376 { /* CAN */
377 .modalias = "mcp2510",
378 .chip_select = 1,
379 .max_speed_hz = 25000 * 26,
380 .irq = AT91_PIN_PC0,
381 }
382};
433 383
384/*
385 * LCD / VGA
386 *
387 * EPSON S1D13806 FB (discontinued chip)
388 * EPSON S1D13506 FB
389 */
434#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE) 390#if defined(CONFIG_FB_S1D135XX) || defined(CONFIG_FB_S1D13XXX_MODULE)
435#include <video/s1d13xxxfb.h> 391#include <video/s1d13xxxfb.h>
436 392
437/* EPSON S1D13806 FB (discontinued chip)*/
438/* EPSON S1D13506 FB */
439
440#define AT91_FB_REG_BASE 0x80000000L 393#define AT91_FB_REG_BASE 0x80000000L
441#define AT91_FB_REG_SIZE 0x200 394#define AT91_FB_REG_SIZE 0x200
442#define AT91_FB_VMEM_BASE 0x80200000L 395#define AT91_FB_VMEM_BASE 0x80200000L
443#define AT91_FB_VMEM_SIZE 0x200000L 396#define AT91_FB_VMEM_SIZE 0x200000L
444 397
445/*#define S1D_DISPLAY_WIDTH 640*/ 398static void __init yl9200_init_video(void)
446/*#define S1D_DISPLAY_HEIGHT 480*/
447
448
449static void __init yl_9200_init_video(void)
450{ 399{
451 at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6); 400 /* NWAIT Signal */
452 at91_sys_write(AT91_PIOC + PIO_BSR,0); 401 at91_set_A_periph(AT91_PIN_PC6, 0);
453 at91_sys_write(AT91_PIOC + PIO_ASR,AT91_PIN_PC6);
454
455 at91_sys_write( AT91_SMC_CSR(2),
456 AT91_SMC_NWS_(0x4) |
457 AT91_SMC_WSEN |
458 AT91_SMC_TDF_(0x100) |
459 AT91_SMC_DBW
460 );
461
462
463 402
403 /* Initialization of the Static Memory Controller for Chip Select 2 */
404 at91_sys_write(AT91_SMC_CSR(2), AT91_SMC_DBW_16 /* 16 bit */
405 | AT91_SMC_WSEN | AT91_SMC_NWS_(0x4) /* wait states */
406 | AT91_SMC_TDF_(0x100) /* float time */
407 );
464} 408}
465 409
466 410static struct s1d13xxxfb_regval yl9200_s1dfb_initregs[] =
467static struct s1d13xxxfb_regval yl_9200_s1dfb_initregs[] =
468{ 411{
469 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/ 412 {S1DREG_MISC, 0x00}, /* Miscellaneous Register*/
470 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ 413 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
471 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/ 414 {S1DREG_GPIO_CNF0, 0x00}, /* General IO Pins Configuration Register*/
472 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/ 415 {S1DREG_GPIO_CTL0, 0x00}, /* General IO Pins Control Register*/
473 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/ 416 {S1DREG_CLK_CNF, 0x11}, /* Memory Clock Configuration Register*/
474 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/ 417 {S1DREG_LCD_CLK_CNF, 0x10}, /* LCD Pixel Clock Configuration Register*/
475 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/ 418 {S1DREG_CRT_CLK_CNF, 0x12}, /* CRT/TV Pixel Clock Configuration Register*/
476 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/ 419 {S1DREG_MPLUG_CLK_CNF, 0x01}, /* MediaPlug Clock Configuration Register*/
477 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/ 420 {S1DREG_CPU2MEM_WST_SEL, 0x02}, /* CPU To Memory Wait State Select Register*/
478 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/ 421 {S1DREG_MEM_CNF, 0x00}, /* Memory Configuration Register*/
479 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/ 422 {S1DREG_SDRAM_REF_RATE, 0x04}, /* DRAM Refresh Rate Register, MCLK source*/
480 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/ 423 {S1DREG_SDRAM_TC0, 0x12}, /* DRAM Timings Control Register 0*/
481 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/ 424 {S1DREG_SDRAM_TC1, 0x02}, /* DRAM Timings Control Register 1*/
482 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/ 425 {S1DREG_PANEL_TYPE, 0x25}, /* Panel Type Register*/
483 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/ 426 {S1DREG_MOD_RATE, 0x00}, /* MOD Rate Register*/
484 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/ 427 {S1DREG_LCD_DISP_HWIDTH, 0x4F}, /* LCD Horizontal Display Width Register*/
485 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/ 428 {S1DREG_LCD_NDISP_HPER, 0x13}, /* LCD Horizontal Non-Display Period Register*/
486 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/ 429 {S1DREG_TFT_FPLINE_START, 0x01}, /* TFT FPLINE Start Position Register*/
487 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/ 430 {S1DREG_TFT_FPLINE_PWIDTH, 0x0c}, /* TFT FPLINE Pulse Width Register*/
488 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/ 431 {S1DREG_LCD_DISP_VHEIGHT0, 0xDF}, /* LCD Vertical Display Height Register 0*/
489 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/ 432 {S1DREG_LCD_DISP_VHEIGHT1, 0x01}, /* LCD Vertical Display Height Register 1*/
490 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/ 433 {S1DREG_LCD_NDISP_VPER, 0x2c}, /* LCD Vertical Non-Display Period Register*/
491 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/ 434 {S1DREG_TFT_FPFRAME_START, 0x0a}, /* TFT FPFRAME Start Position Register*/
492 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/ 435 {S1DREG_TFT_FPFRAME_PWIDTH, 0x02}, /* TFT FPFRAME Pulse Width Register*/
493 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/ 436 {S1DREG_LCD_DISP_MODE, 0x05}, /* LCD Display Mode Register*/
494 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/ 437 {S1DREG_LCD_MISC, 0x01}, /* LCD Miscellaneous Register*/
495 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/ 438 {S1DREG_LCD_DISP_START0, 0x00}, /* LCD Display Start Address Register 0*/
496 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/ 439 {S1DREG_LCD_DISP_START1, 0x00}, /* LCD Display Start Address Register 1*/
497 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/ 440 {S1DREG_LCD_DISP_START2, 0x00}, /* LCD Display Start Address Register 2*/
498 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/ 441 {S1DREG_LCD_MEM_OFF0, 0x80}, /* LCD Memory Address Offset Register 0*/
499 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/ 442 {S1DREG_LCD_MEM_OFF1, 0x02}, /* LCD Memory Address Offset Register 1*/
500 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/ 443 {S1DREG_LCD_PIX_PAN, 0x03}, /* LCD Pixel Panning Register*/
501 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/ 444 {S1DREG_LCD_DISP_FIFO_HTC, 0x00}, /* LCD Display FIFO High Threshold Control Register*/
502 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/ 445 {S1DREG_LCD_DISP_FIFO_LTC, 0x00}, /* LCD Display FIFO Low Threshold Control Register*/
503 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/ 446 {S1DREG_CRT_DISP_HWIDTH, 0x4F}, /* CRT/TV Horizontal Display Width Register*/
504 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/ 447 {S1DREG_CRT_NDISP_HPER, 0x13}, /* CRT/TV Horizontal Non-Display Period Register*/
505 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/ 448 {S1DREG_CRT_HRTC_START, 0x01}, /* CRT/TV HRTC Start Position Register*/
506 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/ 449 {S1DREG_CRT_HRTC_PWIDTH, 0x0B}, /* CRT/TV HRTC Pulse Width Register*/
507 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/ 450 {S1DREG_CRT_DISP_VHEIGHT0, 0xDF}, /* CRT/TV Vertical Display Height Register 0*/
508 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/ 451 {S1DREG_CRT_DISP_VHEIGHT1, 0x01}, /* CRT/TV Vertical Display Height Register 1*/
509 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/ 452 {S1DREG_CRT_NDISP_VPER, 0x2B}, /* CRT/TV Vertical Non-Display Period Register*/
510 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/ 453 {S1DREG_CRT_VRTC_START, 0x09}, /* CRT/TV VRTC Start Position Register*/
511 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/ 454 {S1DREG_CRT_VRTC_PWIDTH, 0x01}, /* CRT/TV VRTC Pulse Width Register*/
512 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */ 455 {S1DREG_TV_OUT_CTL, 0x18}, /* TV Output Control Register */
513 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/ 456 {S1DREG_CRT_DISP_MODE, 0x05}, /* CRT/TV Display Mode Register, 16BPP*/
514 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/ 457 {S1DREG_CRT_DISP_START0, 0x00}, /* CRT/TV Display Start Address Register 0*/
515 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/ 458 {S1DREG_CRT_DISP_START1, 0x00}, /* CRT/TV Display Start Address Register 1*/
516 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/ 459 {S1DREG_CRT_DISP_START2, 0x00}, /* CRT/TV Display Start Address Register 2*/
517 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/ 460 {S1DREG_CRT_MEM_OFF0, 0x80}, /* CRT/TV Memory Address Offset Register 0*/
518 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/ 461 {S1DREG_CRT_MEM_OFF1, 0x02}, /* CRT/TV Memory Address Offset Register 1*/
519 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/ 462 {S1DREG_CRT_PIX_PAN, 0x00}, /* CRT/TV Pixel Panning Register*/
520 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/ 463 {S1DREG_CRT_DISP_FIFO_HTC, 0x00}, /* CRT/TV Display FIFO High Threshold Control Register*/
521 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/ 464 {S1DREG_CRT_DISP_FIFO_LTC, 0x00}, /* CRT/TV Display FIFO Low Threshold Control Register*/
522 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/ 465 {S1DREG_LCD_CUR_CTL, 0x00}, /* LCD Ink/Cursor Control Register*/
523 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/ 466 {S1DREG_LCD_CUR_START, 0x01}, /* LCD Ink/Cursor Start Address Register*/
524 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/ 467 {S1DREG_LCD_CUR_XPOS0, 0x00}, /* LCD Cursor X Position Register 0*/
525 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/ 468 {S1DREG_LCD_CUR_XPOS1, 0x00}, /* LCD Cursor X Position Register 1*/
526 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/ 469 {S1DREG_LCD_CUR_YPOS0, 0x00}, /* LCD Cursor Y Position Register 0*/
527 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/ 470 {S1DREG_LCD_CUR_YPOS1, 0x00}, /* LCD Cursor Y Position Register 1*/
528 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/ 471 {S1DREG_LCD_CUR_BCTL0, 0x00}, /* LCD Ink/Cursor Blue Color 0 Register*/
529 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/ 472 {S1DREG_LCD_CUR_GCTL0, 0x00}, /* LCD Ink/Cursor Green Color 0 Register*/
530 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/ 473 {S1DREG_LCD_CUR_RCTL0, 0x00}, /* LCD Ink/Cursor Red Color 0 Register*/
531 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/ 474 {S1DREG_LCD_CUR_BCTL1, 0x1F}, /* LCD Ink/Cursor Blue Color 1 Register*/
532 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/ 475 {S1DREG_LCD_CUR_GCTL1, 0x3F}, /* LCD Ink/Cursor Green Color 1 Register*/
533 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/ 476 {S1DREG_LCD_CUR_RCTL1, 0x1F}, /* LCD Ink/Cursor Red Color 1 Register*/
534 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/ 477 {S1DREG_LCD_CUR_FIFO_HTC, 0x00}, /* LCD Ink/Cursor FIFO Threshold Register*/
535 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/ 478 {S1DREG_CRT_CUR_CTL, 0x00}, /* CRT/TV Ink/Cursor Control Register*/
536 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/ 479 {S1DREG_CRT_CUR_START, 0x01}, /* CRT/TV Ink/Cursor Start Address Register*/
537 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/ 480 {S1DREG_CRT_CUR_XPOS0, 0x00}, /* CRT/TV Cursor X Position Register 0*/
538 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/ 481 {S1DREG_CRT_CUR_XPOS1, 0x00}, /* CRT/TV Cursor X Position Register 1*/
539 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/ 482 {S1DREG_CRT_CUR_YPOS0, 0x00}, /* CRT/TV Cursor Y Position Register 0*/
540 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/ 483 {S1DREG_CRT_CUR_YPOS1, 0x00}, /* CRT/TV Cursor Y Position Register 1*/
541 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/ 484 {S1DREG_CRT_CUR_BCTL0, 0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register*/
542 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/ 485 {S1DREG_CRT_CUR_GCTL0, 0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register*/
543 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/ 486 {S1DREG_CRT_CUR_RCTL0, 0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register*/
544 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/ 487 {S1DREG_CRT_CUR_BCTL1, 0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register*/
545 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/ 488 {S1DREG_CRT_CUR_GCTL1, 0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register*/
546 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/ 489 {S1DREG_CRT_CUR_RCTL1, 0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register*/
547 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/ 490 {S1DREG_CRT_CUR_FIFO_HTC, 0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register*/
548 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/ 491 {S1DREG_BBLT_CTL0, 0x00}, /* BitBlt Control Register 0*/
549 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/ 492 {S1DREG_BBLT_CTL1, 0x01}, /* BitBlt Control Register 1*/
550 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/ 493 {S1DREG_BBLT_CC_EXP, 0x00}, /* BitBlt ROP Code/Color Expansion Register*/
551 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/ 494 {S1DREG_BBLT_OP, 0x00}, /* BitBlt Operation Register*/
552 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/ 495 {S1DREG_BBLT_SRC_START0, 0x00}, /* BitBlt Source Start Address Register 0*/
553 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/ 496 {S1DREG_BBLT_SRC_START1, 0x00}, /* BitBlt Source Start Address Register 1*/
554 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/ 497 {S1DREG_BBLT_SRC_START2, 0x00}, /* BitBlt Source Start Address Register 2*/
555 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/ 498 {S1DREG_BBLT_DST_START0, 0x00}, /* BitBlt Destination Start Address Register 0*/
556 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/ 499 {S1DREG_BBLT_DST_START1, 0x00}, /* BitBlt Destination Start Address Register 1*/
557 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/ 500 {S1DREG_BBLT_DST_START2, 0x00}, /* BitBlt Destination Start Address Register 2*/
558 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/ 501 {S1DREG_BBLT_MEM_OFF0, 0x00}, /* BitBlt Memory Address Offset Register 0*/
559 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/ 502 {S1DREG_BBLT_MEM_OFF1, 0x00}, /* BitBlt Memory Address Offset Register 1*/
560 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/ 503 {S1DREG_BBLT_WIDTH0, 0x00}, /* BitBlt Width Register 0*/
561 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/ 504 {S1DREG_BBLT_WIDTH1, 0x00}, /* BitBlt Width Register 1*/
562 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/ 505 {S1DREG_BBLT_HEIGHT0, 0x00}, /* BitBlt Height Register 0*/
563 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/ 506 {S1DREG_BBLT_HEIGHT1, 0x00}, /* BitBlt Height Register 1*/
564 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/ 507 {S1DREG_BBLT_BGC0, 0x00}, /* BitBlt Background Color Register 0*/
565 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/ 508 {S1DREG_BBLT_BGC1, 0x00}, /* BitBlt Background Color Register 1*/
566 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/ 509 {S1DREG_BBLT_FGC0, 0x00}, /* BitBlt Foreground Color Register 0*/
567 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/ 510 {S1DREG_BBLT_FGC1, 0x00}, /* BitBlt Foreground Color Register 1*/
568 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/ 511 {S1DREG_LKUP_MODE, 0x00}, /* Look-Up Table Mode Register*/
569 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/ 512 {S1DREG_LKUP_ADDR, 0x00}, /* Look-Up Table Address Register*/
570 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/ 513 {S1DREG_PS_CNF, 0x00}, /* Power Save Configuration Register*/
571 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/ 514 {S1DREG_PS_STATUS, 0x00}, /* Power Save Status Register*/
572 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/ 515 {S1DREG_CPU2MEM_WDOGT, 0x00}, /* CPU-to-Memory Access Watchdog Timer Register*/
573 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/ 516 {S1DREG_COM_DISP_MODE, 0x01}, /* Display Mode Register, LCD only*/
574}; 517};
575 518
576static u64 s1dfb_dmamask = 0xffffffffUL; 519static u64 s1dfb_dmamask = DMA_BIT_MASK(32);
577 520
578static struct s1d13xxxfb_pdata yl_9200_s1dfb_pdata = { 521static struct s1d13xxxfb_pdata yl9200_s1dfb_pdata = {
579 .initregs = yl_9200_s1dfb_initregs, 522 .initregs = yl9200_s1dfb_initregs,
580 .initregssize = ARRAY_SIZE(yl_9200_s1dfb_initregs), 523 .initregssize = ARRAY_SIZE(yl9200_s1dfb_initregs),
581 .platform_init_video = yl_9200_init_video, 524 .platform_init_video = yl9200_init_video,
582}; 525};
583 526
584static struct resource yl_9200_s1dfb_resource[] = { 527static struct resource yl9200_s1dfb_resource[] = {
585 [0] = { /* video mem */ 528 [0] = { /* video mem */
586 .name = "s1d13xxxfb memory", 529 .name = "s1d13xxxfb memory",
587 /* .name = "s1d13806 memory",*/ 530 .start = AT91_FB_VMEM_BASE,
588 .start = AT91_FB_VMEM_BASE, 531 .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1,
589 .end = AT91_FB_VMEM_BASE + AT91_FB_VMEM_SIZE -1, 532 .flags = IORESOURCE_MEM,
590 .flags = IORESOURCE_MEM,
591 }, 533 },
592 [1] = { /* video registers */ 534 [1] = { /* video registers */
593 .name = "s1d13xxxfb registers", 535 .name = "s1d13xxxfb registers",
594 /* .name = "s1d13806 registers",*/ 536 .start = AT91_FB_REG_BASE,
595 .start = AT91_FB_REG_BASE, 537 .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1,
596 .end = AT91_FB_REG_BASE + AT91_FB_REG_SIZE -1, 538 .flags = IORESOURCE_MEM,
597 .flags = IORESOURCE_MEM,
598 }, 539 },
599}; 540};
600 541
601static struct platform_device yl_9200_s1dfb_device = { 542static struct platform_device yl9200_s1dfb_device = {
602 /*TODO S.Birtles , really we need the chip revision in here as well*/ 543 .name = "s1d13806fb",
603 .name = "s1d13806fb", 544 .id = -1,
604 /* .name = "s1d13506fb",*/ 545 .dev = {
605 .id = -1,
606 .dev = {
607 /*TODO theres a waring here!!*/
608 /*WARNING: vmlinux.o(.data+0x2dbc): Section mismatch: reference to .init.text: (between 'yl_9200_s1dfb_pdata' and 's1dfb_dmamask')*/
609 .dma_mask = &s1dfb_dmamask, 546 .dma_mask = &s1dfb_dmamask,
610 .coherent_dma_mask = 0xffffffff, 547 .coherent_dma_mask = DMA_BIT_MASK(32),
611 .platform_data = &yl_9200_s1dfb_pdata, 548 .platform_data = &yl9200_s1dfb_pdata,
612 }, 549 },
613 .resource = yl_9200_s1dfb_resource, 550 .resource = yl9200_s1dfb_resource,
614 .num_resources = ARRAY_SIZE(yl_9200_s1dfb_resource), 551 .num_resources = ARRAY_SIZE(yl9200_s1dfb_resource),
615}; 552};
616 553
617void __init yl_9200_add_device_video(void) 554void __init yl9200_add_device_video(void)
618{ 555{
619 platform_device_register(&yl_9200_s1dfb_device); 556 platform_device_register(&yl9200_s1dfb_device);
620} 557}
621#else 558#else
622 void __init yl_9200_add_device_video(void) {} 559void __init yl9200_add_device_video(void) {}
623#endif 560#endif
624 561
625/*this is not called first , yl_9200_map_io is called first*/ 562
626static void __init yl_9200_board_init(void) 563static void __init yl9200_board_init(void)
627{ 564{
628 /* Serial */ 565 /* Serial */
629 at91_add_device_serial(); 566 at91_add_device_serial();
630 /* Ethernet */ 567 /* Ethernet */
631 at91_add_device_eth(&yl_9200_eth_data); 568 at91_add_device_eth(&yl9200_eth_data);
632 /* USB Host */ 569 /* USB Host */
633 at91_add_device_usbh(&yl_9200_usbh_data); 570 at91_add_device_usbh(&yl9200_usbh_data);
634 /* USB Device */ 571 /* USB Device */
635 at91_add_device_udc(&yl_9200_udc_data); 572 at91_add_device_udc(&yl9200_udc_data);
636 /* pullup_pin it is actually active low, but this is not needed, driver sets it up */
637 /*at91_set_multi_drive(yl_9200_udc_data.pullup_pin, 0);*/
638
639 /* Compact Flash */
640 /*at91_add_device_cf(&yl_9200_cf_data);*/
641
642 /* I2C */ 573 /* I2C */
643 at91_add_device_i2c(yl_9200_i2c_devices, ARRAY_SIZE(yl_9200_i2c_devices)); 574 at91_add_device_i2c(yl9200_i2c_devices, ARRAY_SIZE(yl9200_i2c_devices));
644 /* SPI */ 575 /* MMC */
645 /*TODO YL9200 we have 2 spi interfaces touch screen & CAN*/ 576 at91_add_device_mmc(0, &yl9200_mmc_data);
646 /* AT91_PIN_PA5, AT91_PIN_PA6 , are used on the max 485 NOT SPI*/
647
648 /*touch screen and CAN*/
649 at91_add_device_spi(yl_9200_spi_devices, ARRAY_SIZE(yl_9200_spi_devices));
650
651 /*Basically the TS uses PB11 & PB10 , PB11 is configured by the SPI system BP10 IS NOT USED!!*/
652 /* we need this incase the board is running without a touch screen*/
653 #if defined(CONFIG_TOUCHSCREEN_ADS7846) || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
654 at91_init_device_ts(); /*init the touch screen device*/
655 #endif
656 /* DataFlash card */
657 at91_add_device_mmc(0, &yl_9200_mmc_data);
658 /* NAND */ 577 /* NAND */
659 at91_add_device_nand(&yl_9200_nand_data); 578 at91_add_device_nand(&yl9200_nand_data);
660 /* NOR Flash */ 579 /* NOR Flash */
661 platform_device_register(&yl_9200_flash); 580 platform_device_register(&yl9200_flash);
662 /* LEDs. Note!! this does not include the led's we passed for the processor status */ 581#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
663 at91_gpio_leds(yl_9200_leds, ARRAY_SIZE(yl_9200_leds)); 582 /* SPI */
664 /* VGA */ 583 at91_add_device_spi(yl9200_spi_devices, ARRAY_SIZE(yl9200_spi_devices));
665 /*this is self registered by including the s1d13xxx chip in the kernel build*/ 584 /* Touchscreen */
666 yl_9200_add_device_video(); 585 yl9200_add_device_ts();
586#endif
587 /* LEDs. */
588 at91_gpio_leds(yl9200_leds, ARRAY_SIZE(yl9200_leds));
667 /* Push Buttons */ 589 /* Push Buttons */
668 yl_9200_add_device_buttons(); 590 yl9200_add_device_buttons();
669 /*TODO fixup the Sounder */ 591 /* VGA */
670// yl_9200_add_device_sounder(yl_9200_sounder,ARRAY_SIZE(yl_9200_sounder)); 592 yl9200_add_device_video();
671
672} 593}
673 594
674MACHINE_START(YL9200, "uCdragon YL-9200") 595MACHINE_START(YL9200, "uCdragon YL-9200")
675 /* Maintainer: S.Birtles*/ 596 /* Maintainer: S.Birtles */
676 .phys_io = AT91_BASE_SYS, 597 .phys_io = AT91_BASE_SYS,
677 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc, 598 .io_pg_offst = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
678 .boot_params = AT91_SDRAM_BASE + 0x100, 599 .boot_params = AT91_SDRAM_BASE + 0x100,
679 .timer = &at91rm9200_timer, 600 .timer = &at91rm9200_timer,
680 .map_io = yl_9200_map_io, 601 .map_io = yl9200_map_io,
681 .init_irq = yl_9200_init_irq, 602 .init_irq = yl9200_init_irq,
682 .init_machine = yl_9200_board_init, 603 .init_machine = yl9200_board_init,
683MACHINE_END 604MACHINE_END
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a33dfe450726..464bdbbf74df 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -112,12 +112,34 @@ static void pmc_sys_mode(struct clk *clk, int is_on)
112 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask); 112 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
113} 113}
114 114
115static void pmc_uckr_mode(struct clk *clk, int is_on)
116{
117 unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
118
119 if (is_on) {
120 is_on = AT91_PMC_LOCKU;
121 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
122 } else
123 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
124
125 do {
126 cpu_relax();
127 } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
128}
129
115/* USB function clocks (PLLB must be 48 MHz) */ 130/* USB function clocks (PLLB must be 48 MHz) */
116static struct clk udpck = { 131static struct clk udpck = {
117 .name = "udpck", 132 .name = "udpck",
118 .parent = &pllb, 133 .parent = &pllb,
119 .mode = pmc_sys_mode, 134 .mode = pmc_sys_mode,
120}; 135};
136static struct clk utmi_clk = {
137 .name = "utmi_clk",
138 .parent = &main_clk,
139 .pmc_mask = AT91_PMC_UPLLEN, /* in CKGR_UCKR */
140 .mode = pmc_uckr_mode,
141 .type = CLK_TYPE_PLL,
142};
121static struct clk uhpck = { 143static struct clk uhpck = {
122 .name = "uhpck", 144 .name = "uhpck",
123 .parent = &pllb, 145 .parent = &pllb,
@@ -361,7 +383,7 @@ static void __init init_programmable_clock(struct clk *clk)
361 383
362static int at91_clk_show(struct seq_file *s, void *unused) 384static int at91_clk_show(struct seq_file *s, void *unused)
363{ 385{
364 u32 scsr, pcsr, sr; 386 u32 scsr, pcsr, uckr = 0, sr;
365 struct clk *clk; 387 struct clk *clk;
366 388
367 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR)); 389 seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
@@ -369,7 +391,10 @@ static int at91_clk_show(struct seq_file *s, void *unused)
369 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR)); 391 seq_printf(s, "MOR = %8x\n", at91_sys_read(AT91_CKGR_MOR));
370 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR)); 392 seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
371 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR)); 393 seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
372 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR)); 394 if (!cpu_is_at91sam9rl())
395 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
396 if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
397 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
373 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR)); 398 seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
374 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR)); 399 seq_printf(s, "SR = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
375 400
@@ -382,6 +407,8 @@ static int at91_clk_show(struct seq_file *s, void *unused)
382 state = (scsr & clk->pmc_mask) ? "on" : "off"; 407 state = (scsr & clk->pmc_mask) ? "on" : "off";
383 else if (clk->mode == pmc_periph_mode) 408 else if (clk->mode == pmc_periph_mode)
384 state = (pcsr & clk->pmc_mask) ? "on" : "off"; 409 state = (pcsr & clk->pmc_mask) ? "on" : "off";
410 else if (clk->mode == pmc_uckr_mode)
411 state = (uckr & clk->pmc_mask) ? "on" : "off";
385 else if (clk->pmc_mask) 412 else if (clk->pmc_mask)
386 state = (sr & clk->pmc_mask) ? "on" : "off"; 413 state = (sr & clk->pmc_mask) ? "on" : "off";
387 else if (clk == &clk32k || clk == &main_clk) 414 else if (clk == &clk32k || clk == &main_clk)
@@ -488,14 +515,19 @@ static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
488 /* 515 /*
489 * PLL input between 1MHz and 32MHz per spec, but lower 516 * PLL input between 1MHz and 32MHz per spec, but lower
490 * frequences seem necessary in some cases so allow 100K. 517 * frequences seem necessary in some cases so allow 100K.
518 * Warning: some newer products need 2MHz min.
491 */ 519 */
492 input = main_freq / i; 520 input = main_freq / i;
521 if (cpu_is_at91sam9g20() && input < 2000000)
522 continue;
493 if (input < 100000) 523 if (input < 100000)
494 continue; 524 continue;
495 if (input > 32000000) 525 if (input > 32000000)
496 continue; 526 continue;
497 527
498 mul1 = out_freq / input; 528 mul1 = out_freq / input;
529 if (cpu_is_at91sam9g20() && mul > 63)
530 continue;
499 if (mul1 > 2048) 531 if (mul1 > 2048)
500 continue; 532 continue;
501 if (mul1 < 2) 533 if (mul1 < 2)
@@ -555,7 +587,8 @@ int __init at91_clock_init(unsigned long main_clock)
555 587
556 /* report if PLLA is more than mildly overclocked */ 588 /* report if PLLA is more than mildly overclocked */
557 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR)); 589 plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
558 if (plla.rate_hz > 209000000) 590 if ((!cpu_is_at91sam9g20() && plla.rate_hz > 209000000)
591 || (cpu_is_at91sam9g20() && plla.rate_hz > 800000000))
559 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000); 592 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
560 593
561 /* 594 /*
@@ -570,7 +603,7 @@ int __init at91_clock_init(unsigned long main_clock)
570 uhpck.pmc_mask = AT91RM9200_PMC_UHP; 603 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
571 udpck.pmc_mask = AT91RM9200_PMC_UDP; 604 udpck.pmc_mask = AT91RM9200_PMC_UDP;
572 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP); 605 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
573 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) { 606 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
574 uhpck.pmc_mask = AT91SAM926x_PMC_UHP; 607 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
575 udpck.pmc_mask = AT91SAM926x_PMC_UDP; 608 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
576 } else if (cpu_is_at91cap9()) { 609 } else if (cpu_is_at91cap9()) {
@@ -582,6 +615,17 @@ int __init at91_clock_init(unsigned long main_clock)
582 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init); 615 uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
583 616
584 /* 617 /*
618 * USB HS clock init
619 */
620 if (cpu_is_at91cap9() || cpu_is_at91sam9rl()) {
621 /*
622 * multiplier is hard-wired to 40
623 * (obtain the USB High Speed 480 MHz when input is 12 MHz)
624 */
625 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
626 }
627
628 /*
585 * MCK and CPU derive from one of those primary clocks. 629 * MCK and CPU derive from one of those primary clocks.
586 * For now, assume this parentage won't change. 630 * For now, assume this parentage won't change.
587 */ 631 */
@@ -591,13 +635,21 @@ int __init at91_clock_init(unsigned long main_clock)
591 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */ 635 freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2)); /* prescale */
592 if (cpu_is_at91rm9200()) 636 if (cpu_is_at91rm9200())
593 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 637 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
594 else 638 else if (cpu_is_at91sam9g20()) {
595 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */ 639 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
640 freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq; /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
641 if (mckr & AT91_PMC_PDIV)
642 freq /= 2; /* processor clock division */
643 } else
644 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
596 645
597 /* Register the PMC's standard clocks */ 646 /* Register the PMC's standard clocks */
598 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) 647 for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
599 list_add_tail(&standard_pmc_clocks[i]->node, &clocks); 648 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
600 649
650 if (cpu_is_at91cap9() || cpu_is_at91sam9rl())
651 list_add_tail(&utmi_clk.node, &clocks);
652
601 /* MCK and CPU clock are "always on" */ 653 /* MCK and CPU clock are "always on" */
602 clk_enable(&mck); 654 clk_enable(&mck);
603 655
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index aa863c157708..8ab4feb1ec5b 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -202,7 +202,7 @@ static int at91_pm_verify_clocks(void)
202 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); 202 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
203 return 0; 203 return 0;
204 } 204 }
205 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()) { 205 } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
206 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) { 206 if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
207 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n"); 207 pr_debug("AT91: PM - Suspend-to-RAM with USB still active\n");
208 return 0; 208 return 0;
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 9d7515c36bff..f62c35500bb7 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -74,6 +74,7 @@ struct clk *clk_get(struct device *dev, const char *id)
74 74
75 return ERR_PTR(-ENOENT); 75 return ERR_PTR(-ENOENT);
76} 76}
77EXPORT_SYMBOL(clk_get);
77 78
78int clk_enable(struct clk *clk) 79int clk_enable(struct clk *clk)
79{ 80{
@@ -86,6 +87,7 @@ int clk_enable(struct clk *clk)
86 87
87 return 0; 88 return 0;
88} 89}
90EXPORT_SYMBOL(clk_enable);
89 91
90void clk_disable(struct clk *clk) 92void clk_disable(struct clk *clk)
91{ 93{
@@ -96,15 +98,18 @@ void clk_disable(struct clk *clk)
96 __raw_writel(value & ~clk->enable_mask, clk->enable_reg); 98 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
97 } 99 }
98} 100}
101EXPORT_SYMBOL(clk_disable);
99 102
100unsigned long clk_get_rate(struct clk *clk) 103unsigned long clk_get_rate(struct clk *clk)
101{ 104{
102 return clk->rate; 105 return clk->rate;
103} 106}
107EXPORT_SYMBOL(clk_get_rate);
104 108
105void clk_put(struct clk *clk) 109void clk_put(struct clk *clk)
106{ 110{
107} 111}
112EXPORT_SYMBOL(clk_put);
108 113
109 114
110 115
diff --git a/arch/arm/mach-footbridge/Makefile b/arch/arm/mach-footbridge/Makefile
index 0694ad6b6476..32f8609e4f85 100644
--- a/arch/arm/mach-footbridge/Makefile
+++ b/arch/arm/mach-footbridge/Makefile
@@ -14,12 +14,10 @@ pci-$(CONFIG_ARCH_EBSA285_HOST) += ebsa285-pci.o
14pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o 14pci-$(CONFIG_ARCH_NETWINDER) += netwinder-pci.o
15pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o 15pci-$(CONFIG_ARCH_PERSONAL_SERVER) += personal-pci.o
16 16
17leds-$(CONFIG_ARCH_CO285) += ebsa285-leds.o
18leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o 17leds-$(CONFIG_ARCH_EBSA285) += ebsa285-leds.o
19leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o 18leds-$(CONFIG_ARCH_NETWINDER) += netwinder-leds.o
20 19
21obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o 20obj-$(CONFIG_ARCH_CATS) += cats-hw.o isa-timer.o
22obj-$(CONFIG_ARCH_CO285) += co285.o dc21285-timer.o
23obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o 21obj-$(CONFIG_ARCH_EBSA285) += ebsa285.o dc21285-timer.o
24obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o 22obj-$(CONFIG_ARCH_NETWINDER) += netwinder-hw.o isa-timer.o
25obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o 23obj-$(CONFIG_ARCH_PERSONAL_SERVER) += personal.o dc21285-timer.o
diff --git a/arch/arm/mach-footbridge/co285.c b/arch/arm/mach-footbridge/co285.c
deleted file mode 100644
index 4545576ad8d9..000000000000
--- a/arch/arm/mach-footbridge/co285.c
+++ /dev/null
@@ -1,39 +0,0 @@
1/*
2 * linux/arch/arm/mach-footbridge/co285.c
3 *
4 * CO285 machine fixup
5 */
6#include <linux/init.h>
7
8#include <asm/hardware/dec21285.h>
9#include <asm/mach-types.h>
10
11#include <asm/mach/arch.h>
12
13#include "common.h"
14
15static void __init
16fixup_coebsa285(struct machine_desc *desc, struct tag *tags,
17 char **cmdline, struct meminfo *mi)
18{
19 extern unsigned long boot_memory_end;
20 extern char boot_command_line[];
21
22 mi->nr_banks = 1;
23 mi->bank[0].start = PHYS_OFFSET;
24 mi->bank[0].size = boot_memory_end;
25 mi->bank[0].node = 0;
26
27 *cmdline = boot_command_line;
28}
29
30MACHINE_START(CO285, "co-EBSA285")
31 /* Maintainer: Mark van Doesburg */
32 .phys_io = DC21285_ARMCSR_BASE,
33 .io_pg_offst = ((0x7cf00000) >> 18) & 0xfffc,
34 .fixup = fixup_coebsa285,
35 .map_io = footbridge_map_io,
36 .init_irq = footbridge_init_irq,
37 .timer = &footbridge_timer,
38MACHINE_END
39
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index ef29fc34ce65..b08ab507c052 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -177,25 +177,6 @@ static struct map_desc ebsa285_host_io_desc[] __initdata = {
177#endif 177#endif
178}; 178};
179 179
180/*
181 * The CO-ebsa285 mapping.
182 */
183static struct map_desc co285_io_desc[] __initdata = {
184#ifdef CONFIG_ARCH_CO285
185 {
186 .virtual = PCIO_BASE,
187 .pfn = __phys_to_pfn(DC21285_PCI_IO),
188 .length = PCIO_SIZE,
189 .type = MT_DEVICE,
190 }, {
191 .virtual = PCIMEM_BASE,
192 .pfn = __phys_to_pfn(DC21285_PCI_MEM),
193 .length = PCIMEM_SIZE,
194 .type = MT_DEVICE,
195 },
196#endif
197};
198
199void __init footbridge_map_io(void) 180void __init footbridge_map_io(void)
200{ 181{
201 /* 182 /*
@@ -208,8 +189,6 @@ void __init footbridge_map_io(void)
208 * Now, work out what we've got to map in addition on this 189 * Now, work out what we've got to map in addition on this
209 * platform. 190 * platform.
210 */ 191 */
211 if (machine_is_co285())
212 iotable_init(co285_io_desc, ARRAY_SIZE(co285_io_desc));
213 if (footbridge_cfn_mode()) 192 if (footbridge_cfn_mode())
214 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc)); 193 iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
215} 194}
diff --git a/arch/arm/mach-footbridge/ebsa285-leds.c b/arch/arm/mach-footbridge/ebsa285-leds.c
index a64e22226515..09c1fbc51876 100644
--- a/arch/arm/mach-footbridge/ebsa285-leds.c
+++ b/arch/arm/mach-footbridge/ebsa285-leds.c
@@ -128,7 +128,7 @@ static void ebsa285_leds_event(led_event_t evt)
128 128
129static int __init leds_init(void) 129static int __init leds_init(void)
130{ 130{
131 if (machine_is_ebsa285() || machine_is_co285()) 131 if (machine_is_ebsa285())
132 leds_event = ebsa285_leds_event; 132 leds_event = ebsa285_leds_event;
133 133
134 leds_event(led_start); 134 leds_event(led_start);
diff --git a/arch/arm/mach-footbridge/time.c b/arch/arm/mach-footbridge/time.c
index 5d02e95dede3..d5cfcda385d6 100644
--- a/arch/arm/mach-footbridge/time.c
+++ b/arch/arm/mach-footbridge/time.c
@@ -115,8 +115,7 @@ static int set_isa_cmos_time(void)
115 115
116void __init isa_rtc_init(void) 116void __init isa_rtc_init(void)
117{ 117{
118 if (machine_is_co285() || 118 if (machine_is_personal_server())
119 machine_is_personal_server())
120 /* 119 /*
121 * Add-in 21285s shouldn't access the RTC 120 * Add-in 21285s shouldn't access the RTC
122 */ 121 */
diff --git a/arch/arm/mach-imx/dma.c b/arch/arm/mach-imx/dma.c
index a59ff2987cb7..ee1c6f06ff64 100644
--- a/arch/arm/mach-imx/dma.c
+++ b/arch/arm/mach-imx/dma.c
@@ -410,7 +410,6 @@ void imx_dma_free(imx_dmach_t dma_ch)
410 410
411/** 411/**
412 * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority 412 * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
413 * @dma_ch: i.MX DMA channel number
414 * @name: the driver/caller own non-%NULL identification 413 * @name: the driver/caller own non-%NULL identification
415 * @prio: one of the hardware distinguished priority level: 414 * @prio: one of the hardware distinguished priority level:
416 * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW 415 * %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
@@ -420,11 +419,9 @@ void imx_dma_free(imx_dmach_t dma_ch)
420 * in the higher and then even lower priority groups. 419 * in the higher and then even lower priority groups.
421 * 420 *
422 * Return value: If there is no free channel to allocate, -%ENODEV is returned. 421 * Return value: If there is no free channel to allocate, -%ENODEV is returned.
423 * Zero value indicates successful channel allocation. 422 * On successful allocation channel is returned.
424 */ 423 */
425int 424imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio)
426imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
427 imx_dma_prio prio)
428{ 425{
429 int i; 426 int i;
430 int best; 427 int best;
@@ -444,15 +441,13 @@ imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
444 441
445 for (i = best; i < IMX_DMA_CHANNELS; i++) { 442 for (i = best; i < IMX_DMA_CHANNELS; i++) {
446 if (!imx_dma_request(i, name)) { 443 if (!imx_dma_request(i, name)) {
447 *pdma_ch = i; 444 return i;
448 return 0;
449 } 445 }
450 } 446 }
451 447
452 for (i = best - 1; i >= 0; i--) { 448 for (i = best - 1; i >= 0; i--) {
453 if (!imx_dma_request(i, name)) { 449 if (!imx_dma_request(i, name)) {
454 *pdma_ch = i; 450 return i;
455 return 0;
456 } 451 }
457 } 452 }
458 453
diff --git a/arch/arm/mach-integrator/Makefile b/arch/arm/mach-integrator/Makefile
index 158daaf9e3b0..6a5ef8d30b10 100644
--- a/arch/arm/mach-integrator/Makefile
+++ b/arch/arm/mach-integrator/Makefile
@@ -4,7 +4,7 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := clock.o core.o lm.o time.o 7obj-y := clock.o core.o lm.o
8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o 8obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o 9obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
10 10
diff --git a/arch/arm/mach-integrator/time.c b/arch/arm/mach-integrator/time.c
deleted file mode 100644
index 8508a0db3eaf..000000000000
--- a/arch/arm/mach-integrator/time.c
+++ /dev/null
@@ -1,223 +0,0 @@
1/*
2 * linux/arch/arm/mach-integrator/time.c
3 *
4 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/time.h>
13#include <linux/mc146818rtc.h>
14#include <linux/interrupt.h>
15#include <linux/init.h>
16#include <linux/device.h>
17#include <linux/amba/bus.h>
18
19#include <asm/hardware.h>
20#include <asm/io.h>
21#include <asm/uaccess.h>
22#include <asm/rtc.h>
23
24#include <asm/mach/time.h>
25
26#define RTC_DR (0)
27#define RTC_MR (4)
28#define RTC_STAT (8)
29#define RTC_EOI (8)
30#define RTC_LR (12)
31#define RTC_CR (16)
32#define RTC_CR_MIE (1 << 0)
33
34extern int (*set_rtc)(void);
35static void __iomem *rtc_base;
36
37static int integrator_set_rtc(void)
38{
39 __raw_writel(xtime.tv_sec, rtc_base + RTC_LR);
40 return 1;
41}
42
43static int integrator_rtc_read_alarm(struct rtc_wkalrm *alrm)
44{
45 rtc_time_to_tm(readl(rtc_base + RTC_MR), &alrm->time);
46 return 0;
47}
48
49static inline int integrator_rtc_set_alarm(struct rtc_wkalrm *alrm)
50{
51 unsigned long time;
52 int ret;
53
54 /*
55 * At the moment, we can only deal with non-wildcarded alarm times.
56 */
57 ret = rtc_valid_tm(&alrm->time);
58 if (ret == 0)
59 ret = rtc_tm_to_time(&alrm->time, &time);
60 if (ret == 0)
61 writel(time, rtc_base + RTC_MR);
62 return ret;
63}
64
65static int integrator_rtc_read_time(struct rtc_time *tm)
66{
67 rtc_time_to_tm(readl(rtc_base + RTC_DR), tm);
68 return 0;
69}
70
71/*
72 * Set the RTC time. Unfortunately, we can't accurately set
73 * the point at which the counter updates.
74 *
75 * Also, since RTC_LR is transferred to RTC_CR on next rising
76 * edge of the 1Hz clock, we must write the time one second
77 * in advance.
78 */
79static inline int integrator_rtc_set_time(struct rtc_time *tm)
80{
81 unsigned long time;
82 int ret;
83
84 ret = rtc_tm_to_time(tm, &time);
85 if (ret == 0)
86 writel(time + 1, rtc_base + RTC_LR);
87
88 return ret;
89}
90
91static struct rtc_ops rtc_ops = {
92 .owner = THIS_MODULE,
93 .read_time = integrator_rtc_read_time,
94 .set_time = integrator_rtc_set_time,
95 .read_alarm = integrator_rtc_read_alarm,
96 .set_alarm = integrator_rtc_set_alarm,
97};
98
99static irqreturn_t arm_rtc_interrupt(int irq, void *dev_id)
100{
101 writel(0, rtc_base + RTC_EOI);
102 return IRQ_HANDLED;
103}
104
105static int rtc_probe(struct amba_device *dev, void *id)
106{
107 int ret;
108
109 if (rtc_base)
110 return -EBUSY;
111
112 ret = amba_request_regions(dev, NULL);
113 if (ret)
114 goto out;
115
116 rtc_base = ioremap(dev->res.start, SZ_4K);
117 if (!rtc_base) {
118 ret = -ENOMEM;
119 goto res_out;
120 }
121
122 __raw_writel(0, rtc_base + RTC_CR);
123 __raw_writel(0, rtc_base + RTC_EOI);
124
125 xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
126
127 /* note that 'dev' is merely used for irq disambiguation;
128 * it is not actually referenced in the irq handler
129 */
130 ret = request_irq(dev->irq[0], arm_rtc_interrupt, IRQF_DISABLED,
131 "rtc-pl030", dev);
132 if (ret)
133 goto map_out;
134
135 ret = register_rtc(&rtc_ops);
136 if (ret)
137 goto irq_out;
138
139 set_rtc = integrator_set_rtc;
140 return 0;
141
142 irq_out:
143 free_irq(dev->irq[0], dev);
144 map_out:
145 iounmap(rtc_base);
146 rtc_base = NULL;
147 res_out:
148 amba_release_regions(dev);
149 out:
150 return ret;
151}
152
153static int rtc_remove(struct amba_device *dev)
154{
155 set_rtc = NULL;
156
157 writel(0, rtc_base + RTC_CR);
158
159 free_irq(dev->irq[0], dev);
160 unregister_rtc(&rtc_ops);
161
162 iounmap(rtc_base);
163 rtc_base = NULL;
164 amba_release_regions(dev);
165
166 return 0;
167}
168
169static struct timespec rtc_delta;
170
171static int rtc_suspend(struct amba_device *dev, pm_message_t state)
172{
173 struct timespec rtc;
174
175 rtc.tv_sec = readl(rtc_base + RTC_DR);
176 rtc.tv_nsec = 0;
177 save_time_delta(&rtc_delta, &rtc);
178
179 return 0;
180}
181
182static int rtc_resume(struct amba_device *dev)
183{
184 struct timespec rtc;
185
186 rtc.tv_sec = readl(rtc_base + RTC_DR);
187 rtc.tv_nsec = 0;
188 restore_time_delta(&rtc_delta, &rtc);
189
190 return 0;
191}
192
193static struct amba_id rtc_ids[] = {
194 {
195 .id = 0x00041030,
196 .mask = 0x000fffff,
197 },
198 { 0, 0 },
199};
200
201static struct amba_driver rtc_driver = {
202 .drv = {
203 .name = "rtc-pl030",
204 },
205 .probe = rtc_probe,
206 .remove = rtc_remove,
207 .suspend = rtc_suspend,
208 .resume = rtc_resume,
209 .id_table = rtc_ids,
210};
211
212static int __init integrator_rtc_init(void)
213{
214 return amba_driver_register(&rtc_driver);
215}
216
217static void __exit integrator_rtc_exit(void)
218{
219 amba_driver_unregister(&rtc_driver);
220}
221
222module_init(integrator_rtc_init);
223module_exit(integrator_rtc_exit);
diff --git a/arch/arm/mach-ixp4xx/Kconfig b/arch/arm/mach-ixp4xx/Kconfig
index e774447c0592..db8b5fe06c0d 100644
--- a/arch/arm/mach-ixp4xx/Kconfig
+++ b/arch/arm/mach-ixp4xx/Kconfig
@@ -125,6 +125,15 @@ config ARCH_IXDP4XX
125 depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435 125 depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
126 default y 126 default y
127 127
128config MACH_FSG
129 bool
130 prompt "Freecom FSG-3"
131 select PCI
132 help
133 Say 'Y' here if you want your kernel to support Freecom's
134 FSG-3 device. For more information on this platform,
135 see http://www.nslu2-linux.org/wiki/FSG3/HomePage
136
128# 137#
129# Certain registers and IRQs are only enabled if supporting IXP465 CPUs 138# Certain registers and IRQs are only enabled if supporting IXP465 CPUs
130# 139#
diff --git a/arch/arm/mach-ixp4xx/Makefile b/arch/arm/mach-ixp4xx/Makefile
index c1956882c48b..2e6bbf927a74 100644
--- a/arch/arm/mach-ixp4xx/Makefile
+++ b/arch/arm/mach-ixp4xx/Makefile
@@ -15,6 +15,7 @@ obj-pci-$(CONFIG_MACH_NAS100D) += nas100d-pci.o
15obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o 15obj-pci-$(CONFIG_MACH_DSMG600) += dsmg600-pci.o
16obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o 16obj-pci-$(CONFIG_MACH_GATEWAY7001) += gateway7001-pci.o
17obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o 17obj-pci-$(CONFIG_MACH_WG302V2) += wg302v2-pci.o
18obj-pci-$(CONFIG_MACH_FSG) += fsg-pci.o
18 19
19obj-y += common.o 20obj-y += common.o
20 21
@@ -28,6 +29,7 @@ obj-$(CONFIG_MACH_NAS100D) += nas100d-setup.o
28obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o 29obj-$(CONFIG_MACH_DSMG600) += dsmg600-setup.o
29obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o 30obj-$(CONFIG_MACH_GATEWAY7001) += gateway7001-setup.o
30obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o 31obj-$(CONFIG_MACH_WG302V2) += wg302v2-setup.o
32obj-$(CONFIG_MACH_FSG) += fsg-setup.o
31 33
32obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o 34obj-$(CONFIG_PCI) += $(obj-pci-$(CONFIG_PCI)) common-pci.o
33obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o 35obj-$(CONFIG_IXP4XX_QMGR) += ixp4xx_qmgr.o
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
new file mode 100644
index 000000000000..f19f3f6feda1
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -0,0 +1,71 @@
1/*
2 * arch/arch/mach-ixp4xx/fsg-pci.c
3 *
4 * FSG board-level PCI initialization
5 *
6 * Author: Rod Whitby <rod@whitby.id.au>
7 * Maintainer: http://www.nslu2-linux.org/
8 *
9 * based on ixdp425-pci.c:
10 * Copyright (C) 2002 Intel Corporation.
11 * Copyright (C) 2003-2004 MontaVista Software, Inc.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 *
17 */
18
19#include <linux/pci.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22
23#include <asm/mach/pci.h>
24#include <asm/mach-types.h>
25
26void __init fsg_pci_preinit(void)
27{
28 set_irq_type(IRQ_FSG_PCI_INTA, IRQT_LOW);
29 set_irq_type(IRQ_FSG_PCI_INTB, IRQT_LOW);
30 set_irq_type(IRQ_FSG_PCI_INTC, IRQT_LOW);
31
32 ixp4xx_pci_preinit();
33}
34
35static int __init fsg_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
36{
37 static int pci_irq_table[FSG_PCI_IRQ_LINES] = {
38 IRQ_FSG_PCI_INTC,
39 IRQ_FSG_PCI_INTB,
40 IRQ_FSG_PCI_INTA,
41 };
42
43 int irq = -1;
44 slot = slot - 11;
45
46 if (slot >= 1 && slot <= FSG_PCI_MAX_DEV &&
47 pin >= 1 && pin <= FSG_PCI_IRQ_LINES)
48 irq = pci_irq_table[(slot - 1)];
49 printk(KERN_INFO "%s: Mapped slot %d pin %d to IRQ %d\n",
50 __func__, slot, pin, irq);
51
52 return irq;
53}
54
55struct hw_pci fsg_pci __initdata = {
56 .nr_controllers = 1,
57 .preinit = fsg_pci_preinit,
58 .swizzle = pci_std_swizzle,
59 .setup = ixp4xx_setup,
60 .scan = ixp4xx_scan_bus,
61 .map_irq = fsg_map_irq,
62};
63
64int __init fsg_pci_init(void)
65{
66 if (machine_is_fsg())
67 pci_common_init(&fsg_pci);
68 return 0;
69}
70
71subsys_initcall(fsg_pci_init);
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
new file mode 100644
index 000000000000..0db3a909ae61
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -0,0 +1,276 @@
1/*
2 * arch/arm/mach-ixp4xx/fsg-setup.c
3 *
4 * FSG board-setup
5 *
6 * Copyright (C) 2008 Rod Whitby <rod@whitby.id.au>
7 *
8 * based on ixdp425-setup.c:
9 * Copyright (C) 2003-2004 MontaVista Software, Inc.
10 * based on nslu2-power.c
11 * Copyright (C) 2005 Tower Technologies
12 *
13 * Author: Rod Whitby <rod@whitby.id.au>
14 * Maintainers: http://www.nslu2-linux.org/
15 *
16 */
17
18#include <linux/if_ether.h>
19#include <linux/irq.h>
20#include <linux/serial.h>
21#include <linux/serial_8250.h>
22#include <linux/leds.h>
23#include <linux/reboot.h>
24#include <linux/i2c.h>
25#include <linux/i2c-gpio.h>
26
27#include <asm/mach-types.h>
28#include <asm/mach/arch.h>
29#include <asm/mach/flash.h>
30#include <asm/io.h>
31#include <asm/gpio.h>
32
33static struct flash_platform_data fsg_flash_data = {
34 .map_name = "cfi_probe",
35 .width = 2,
36};
37
38static struct resource fsg_flash_resource = {
39 .flags = IORESOURCE_MEM,
40};
41
42static struct platform_device fsg_flash = {
43 .name = "IXP4XX-Flash",
44 .id = 0,
45 .dev = {
46 .platform_data = &fsg_flash_data,
47 },
48 .num_resources = 1,
49 .resource = &fsg_flash_resource,
50};
51
52static struct i2c_gpio_platform_data fsg_i2c_gpio_data = {
53 .sda_pin = FSG_SDA_PIN,
54 .scl_pin = FSG_SCL_PIN,
55};
56
57static struct platform_device fsg_i2c_gpio = {
58 .name = "i2c-gpio",
59 .id = 0,
60 .dev = {
61 .platform_data = &fsg_i2c_gpio_data,
62 },
63};
64
65static struct i2c_board_info __initdata fsg_i2c_board_info [] = {
66 {
67 I2C_BOARD_INFO("rtc-isl1208", 0x6f),
68 },
69};
70
71static struct resource fsg_uart_resources[] = {
72 {
73 .start = IXP4XX_UART1_BASE_PHYS,
74 .end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
75 .flags = IORESOURCE_MEM,
76 },
77 {
78 .start = IXP4XX_UART2_BASE_PHYS,
79 .end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
80 .flags = IORESOURCE_MEM,
81 }
82};
83
84static struct plat_serial8250_port fsg_uart_data[] = {
85 {
86 .mapbase = IXP4XX_UART1_BASE_PHYS,
87 .membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
88 .irq = IRQ_IXP4XX_UART1,
89 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
90 .iotype = UPIO_MEM,
91 .regshift = 2,
92 .uartclk = IXP4XX_UART_XTAL,
93 },
94 {
95 .mapbase = IXP4XX_UART2_BASE_PHYS,
96 .membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
97 .irq = IRQ_IXP4XX_UART2,
98 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
99 .iotype = UPIO_MEM,
100 .regshift = 2,
101 .uartclk = IXP4XX_UART_XTAL,
102 },
103 { }
104};
105
106static struct platform_device fsg_uart = {
107 .name = "serial8250",
108 .id = PLAT8250_DEV_PLATFORM,
109 .dev = {
110 .platform_data = fsg_uart_data,
111 },
112 .num_resources = ARRAY_SIZE(fsg_uart_resources),
113 .resource = fsg_uart_resources,
114};
115
116static struct platform_device fsg_leds = {
117 .name = "fsg-led",
118 .id = -1,
119};
120
121/* Built-in 10/100 Ethernet MAC interfaces */
122static struct eth_plat_info fsg_plat_eth[] = {
123 {
124 .phy = 5,
125 .rxq = 3,
126 .txreadyq = 20,
127 }, {
128 .phy = 4,
129 .rxq = 4,
130 .txreadyq = 21,
131 }
132};
133
134static struct platform_device fsg_eth[] = {
135 {
136 .name = "ixp4xx_eth",
137 .id = IXP4XX_ETH_NPEB,
138 .dev = {
139 .platform_data = fsg_plat_eth,
140 },
141 }, {
142 .name = "ixp4xx_eth",
143 .id = IXP4XX_ETH_NPEC,
144 .dev = {
145 .platform_data = fsg_plat_eth + 1,
146 },
147 }
148};
149
150static struct platform_device *fsg_devices[] __initdata = {
151 &fsg_i2c_gpio,
152 &fsg_flash,
153 &fsg_leds,
154 &fsg_eth[0],
155 &fsg_eth[1],
156};
157
158static irqreturn_t fsg_power_handler(int irq, void *dev_id)
159{
160 /* Signal init to do the ctrlaltdel action, this will bypass init if
161 * it hasn't started and do a kernel_restart.
162 */
163 ctrl_alt_del();
164
165 return IRQ_HANDLED;
166}
167
168static irqreturn_t fsg_reset_handler(int irq, void *dev_id)
169{
170 /* This is the paper-clip reset which does an emergency reboot. */
171 printk(KERN_INFO "Restarting system.\n");
172 machine_restart(NULL);
173
174 /* This should never be reached. */
175 return IRQ_HANDLED;
176}
177
178static void __init fsg_init(void)
179{
180 DECLARE_MAC_BUF(mac_buf);
181 uint8_t __iomem *f;
182 int i;
183
184 ixp4xx_sys_init();
185
186 fsg_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
187 fsg_flash_resource.end =
188 IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
189
190 *IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
191 *IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
192
193 /* Configure CS2 for operation, 8bit and writable */
194 *IXP4XX_EXP_CS2 = 0xbfff0002;
195
196 i2c_register_board_info(0, fsg_i2c_board_info,
197 ARRAY_SIZE(fsg_i2c_board_info));
198
199 /* This is only useful on a modified machine, but it is valuable
200 * to have it first in order to see debug messages, and so that
201 * it does *not* get removed if platform_add_devices fails!
202 */
203 (void)platform_device_register(&fsg_uart);
204
205 platform_add_devices(fsg_devices, ARRAY_SIZE(fsg_devices));
206
207 if (request_irq(gpio_to_irq(FSG_RB_GPIO), &fsg_reset_handler,
208 IRQF_DISABLED | IRQF_TRIGGER_LOW,
209 "FSG reset button", NULL) < 0) {
210
211 printk(KERN_DEBUG "Reset Button IRQ %d not available\n",
212 gpio_to_irq(FSG_RB_GPIO));
213 }
214
215 if (request_irq(gpio_to_irq(FSG_SB_GPIO), &fsg_power_handler,
216 IRQF_DISABLED | IRQF_TRIGGER_LOW,
217 "FSG power button", NULL) < 0) {
218
219 printk(KERN_DEBUG "Power Button IRQ %d not available\n",
220 gpio_to_irq(FSG_SB_GPIO));
221 }
222
223 /*
224 * Map in a portion of the flash and read the MAC addresses.
225 * Since it is stored in BE in the flash itself, we need to
226 * byteswap it if we're in LE mode.
227 */
228 f = ioremap(IXP4XX_EXP_BUS_BASE(0), 0x400000);
229 if (f) {
230#ifdef __ARMEB__
231 for (i = 0; i < 6; i++) {
232 fsg_plat_eth[0].hwaddr[i] = readb(f + 0x3C0422 + i);
233 fsg_plat_eth[1].hwaddr[i] = readb(f + 0x3C043B + i);
234 }
235#else
236
237 /*
238 Endian-swapped reads from unaligned addresses are
239 required to extract the two MACs from the big-endian
240 Redboot config area in flash.
241 */
242
243 fsg_plat_eth[0].hwaddr[0] = readb(f + 0x3C0421);
244 fsg_plat_eth[0].hwaddr[1] = readb(f + 0x3C0420);
245 fsg_plat_eth[0].hwaddr[2] = readb(f + 0x3C0427);
246 fsg_plat_eth[0].hwaddr[3] = readb(f + 0x3C0426);
247 fsg_plat_eth[0].hwaddr[4] = readb(f + 0x3C0425);
248 fsg_plat_eth[0].hwaddr[5] = readb(f + 0x3C0424);
249
250 fsg_plat_eth[1].hwaddr[0] = readb(f + 0x3C0439);
251 fsg_plat_eth[1].hwaddr[1] = readb(f + 0x3C043F);
252 fsg_plat_eth[1].hwaddr[2] = readb(f + 0x3C043E);
253 fsg_plat_eth[1].hwaddr[3] = readb(f + 0x3C043D);
254 fsg_plat_eth[1].hwaddr[4] = readb(f + 0x3C043C);
255 fsg_plat_eth[1].hwaddr[5] = readb(f + 0x3C0443);
256#endif
257 iounmap(f);
258 }
259 printk(KERN_INFO "FSG: Using MAC address %s for port 0\n",
260 print_mac(mac_buf, fsg_plat_eth[0].hwaddr));
261 printk(KERN_INFO "FSG: Using MAC address %s for port 1\n",
262 print_mac(mac_buf, fsg_plat_eth[1].hwaddr));
263
264}
265
266MACHINE_START(FSG, "Freecom FSG-3")
267 /* Maintainer: www.nslu2-linux.org */
268 .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
269 .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
270 .map_io = ixp4xx_map_io,
271 .init_irq = ixp4xx_init_irq,
272 .timer = &ixp4xx_timer,
273 .boot_params = 0x0100,
274 .init_machine = fsg_init,
275MACHINE_END
276
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
new file mode 100644
index 000000000000..3600cd9f0519
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -0,0 +1,25 @@
1if ARCH_KIRKWOOD
2
3menu "Marvell Kirkwood Implementations"
4
5config MACH_DB88F6281_BP
6 bool "Marvell DB-88F6281-BP Development Board"
7 help
8 Say 'Y' here if you want your kernel to support the
9 Marvell DB-88F6281-BP Development Board.
10
11config MACH_RD88F6192_NAS
12 bool "Marvell RD-88F6192-NAS Reference Board"
13 help
14 Say 'Y' here if you want your kernel to support the
15 Marvell RD-88F6192-NAS Reference Board.
16
17config MACH_RD88F6281
18 bool "Marvell RD-88F6281 Reference Board"
19 help
20 Say 'Y' here if you want your kernel to support the
21 Marvell RD-88F6281 Reference Board.
22
23endmenu
24
25endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
new file mode 100644
index 000000000000..e14bf40bfb07
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -0,0 +1,5 @@
1obj-y += common.o addr-map.o irq.o pcie.o
2
3obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o
4obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
5obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6281-setup.o
diff --git a/arch/arm/mach-kirkwood/Makefile.boot b/arch/arm/mach-kirkwood/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-kirkwood/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
new file mode 100644
index 000000000000..a39f0f3c4730
--- /dev/null
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -0,0 +1,139 @@
1/*
2 * arch/arm/mach-kirkwood/addr-map.c
3 *
4 * Address map functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <linux/io.h>
15#include <asm/hardware.h>
16#include "common.h"
17
18/*
19 * Generic Address Decode Windows bit settings
20 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1
23#define TARGET_PCIE 4
24#define ATTR_DEV_SPI_ROM 0x1e
25#define ATTR_DEV_BOOT 0x1d
26#define ATTR_DEV_NAND 0x2f
27#define ATTR_DEV_CS3 0x37
28#define ATTR_DEV_CS2 0x3b
29#define ATTR_DEV_CS1 0x3d
30#define ATTR_DEV_CS0 0x3e
31#define ATTR_PCIE_IO 0xe0
32#define ATTR_PCIE_MEM 0xe8
33
34/*
35 * Helpers to get DDR bank info
36 */
37#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
38#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
39
40/*
41 * CPU Address Decode Windows registers
42 */
43#define WIN_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
44#define WIN_CTRL_OFF 0x0000
45#define WIN_BASE_OFF 0x0004
46#define WIN_REMAP_LO_OFF 0x0008
47#define WIN_REMAP_HI_OFF 0x000c
48
49
50struct mbus_dram_target_info kirkwood_mbus_dram_info;
51
52static int __init cpu_win_can_remap(int win)
53{
54 if (win < 4)
55 return 1;
56
57 return 0;
58}
59
60static void __init setup_cpu_win(int win, u32 base, u32 size,
61 u8 target, u8 attr, int remap)
62{
63 void __iomem *addr = (void __iomem *)WIN_OFF(win);
64 u32 ctrl;
65
66 base &= 0xffff0000;
67 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
68
69 writel(base, addr + WIN_BASE_OFF);
70 writel(ctrl, addr + WIN_CTRL_OFF);
71 if (cpu_win_can_remap(win)) {
72 if (remap < 0)
73 remap = base;
74
75 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
76 writel(0, addr + WIN_REMAP_HI_OFF);
77 }
78}
79
80void __init kirkwood_setup_cpu_mbus(void)
81{
82 void __iomem *addr;
83 int i;
84 int cs;
85
86 /*
87 * First, disable and clear windows.
88 */
89 for (i = 0; i < 8; i++) {
90 addr = (void __iomem *)WIN_OFF(i);
91
92 writel(0, addr + WIN_BASE_OFF);
93 writel(0, addr + WIN_CTRL_OFF);
94 if (cpu_win_can_remap(i)) {
95 writel(0, addr + WIN_REMAP_LO_OFF);
96 writel(0, addr + WIN_REMAP_HI_OFF);
97 }
98 }
99
100 /*
101 * Setup windows for PCIe IO+MEM space.
102 */
103 setup_cpu_win(0, KIRKWOOD_PCIE_IO_PHYS_BASE, KIRKWOOD_PCIE_IO_SIZE,
104 TARGET_PCIE, ATTR_PCIE_IO, KIRKWOOD_PCIE_IO_BUS_BASE);
105 setup_cpu_win(1, KIRKWOOD_PCIE_MEM_PHYS_BASE, KIRKWOOD_PCIE_MEM_SIZE,
106 TARGET_PCIE, ATTR_PCIE_MEM, -1);
107
108 /*
109 * Setup window for NAND controller.
110 */
111 setup_cpu_win(2, KIRKWOOD_NAND_MEM_PHYS_BASE, KIRKWOOD_NAND_MEM_SIZE,
112 TARGET_DEV_BUS, ATTR_DEV_NAND, -1);
113
114 /*
115 * Setup MBUS dram target info.
116 */
117 kirkwood_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
118
119 addr = (void __iomem *)DDR_WINDOW_CPU_BASE;
120
121 for (i = 0, cs = 0; i < 4; i++) {
122 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
123 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
124
125 /*
126 * Chip select enabled?
127 */
128 if (size & 1) {
129 struct mbus_dram_window *w;
130
131 w = &kirkwood_mbus_dram_info.cs[cs++];
132 w->cs_index = i;
133 w->mbus_attr = 0xf & ~(1 << i);
134 w->base = base & 0xffff0000;
135 w->size = (size | 0x0000ffff) + 1;
136 }
137 }
138 kirkwood_mbus_dram_info.num_cs = cs;
139}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
new file mode 100644
index 000000000000..5938a3b33cdc
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.c
@@ -0,0 +1,331 @@
1/*
2 * arch/arm/mach-kirkwood/common.c
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/ata_platform.h>
18#include <asm/page.h>
19#include <asm/timex.h>
20#include <asm/mach/map.h>
21#include <asm/mach/time.h>
22#include <asm/arch/kirkwood.h>
23#include <asm/plat-orion/cache-feroceon-l2.h>
24#include <asm/plat-orion/ehci-orion.h>
25#include <asm/plat-orion/orion_nand.h>
26#include <asm/plat-orion/time.h>
27#include "common.h"
28
29/*****************************************************************************
30 * I/O Address Mapping
31 ****************************************************************************/
32static struct map_desc kirkwood_io_desc[] __initdata = {
33 {
34 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
35 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
36 .length = KIRKWOOD_PCIE_IO_SIZE,
37 .type = MT_DEVICE,
38 }, {
39 .virtual = KIRKWOOD_REGS_VIRT_BASE,
40 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
41 .length = KIRKWOOD_REGS_SIZE,
42 .type = MT_DEVICE,
43 },
44};
45
46void __init kirkwood_map_io(void)
47{
48 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
49}
50
51
52/*****************************************************************************
53 * EHCI
54 ****************************************************************************/
55static struct orion_ehci_data kirkwood_ehci_data = {
56 .dram = &kirkwood_mbus_dram_info,
57};
58
59static u64 ehci_dmamask = 0xffffffffUL;
60
61
62/*****************************************************************************
63 * EHCI0
64 ****************************************************************************/
65static struct resource kirkwood_ehci_resources[] = {
66 {
67 .start = USB_PHYS_BASE,
68 .end = USB_PHYS_BASE + 0x0fff,
69 .flags = IORESOURCE_MEM,
70 }, {
71 .start = IRQ_KIRKWOOD_USB,
72 .end = IRQ_KIRKWOOD_USB,
73 .flags = IORESOURCE_IRQ,
74 },
75};
76
77static struct platform_device kirkwood_ehci = {
78 .name = "orion-ehci",
79 .id = 0,
80 .dev = {
81 .dma_mask = &ehci_dmamask,
82 .coherent_dma_mask = 0xffffffff,
83 .platform_data = &kirkwood_ehci_data,
84 },
85 .resource = kirkwood_ehci_resources,
86 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
87};
88
89void __init kirkwood_ehci_init(void)
90{
91 platform_device_register(&kirkwood_ehci);
92}
93
94
95/*****************************************************************************
96 * GE00
97 ****************************************************************************/
98struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
99 .t_clk = KIRKWOOD_TCLK,
100 .dram = &kirkwood_mbus_dram_info,
101};
102
103static struct resource kirkwood_ge00_shared_resources[] = {
104 {
105 .name = "ge00 base",
106 .start = GE00_PHYS_BASE + 0x2000,
107 .end = GE00_PHYS_BASE + 0x3fff,
108 .flags = IORESOURCE_MEM,
109 },
110};
111
112static struct platform_device kirkwood_ge00_shared = {
113 .name = MV643XX_ETH_SHARED_NAME,
114 .id = 0,
115 .dev = {
116 .platform_data = &kirkwood_ge00_shared_data,
117 },
118 .num_resources = 1,
119 .resource = kirkwood_ge00_shared_resources,
120};
121
122static struct resource kirkwood_ge00_resources[] = {
123 {
124 .name = "ge00 irq",
125 .start = IRQ_KIRKWOOD_GE00_SUM,
126 .end = IRQ_KIRKWOOD_GE00_SUM,
127 .flags = IORESOURCE_IRQ,
128 },
129};
130
131static struct platform_device kirkwood_ge00 = {
132 .name = MV643XX_ETH_NAME,
133 .id = 0,
134 .num_resources = 1,
135 .resource = kirkwood_ge00_resources,
136};
137
138void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
139{
140 eth_data->shared = &kirkwood_ge00_shared;
141 kirkwood_ge00.dev.platform_data = eth_data;
142
143 platform_device_register(&kirkwood_ge00_shared);
144 platform_device_register(&kirkwood_ge00);
145}
146
147
148/*****************************************************************************
149 * SoC RTC
150 ****************************************************************************/
151static struct resource kirkwood_rtc_resource = {
152 .start = RTC_PHYS_BASE,
153 .end = RTC_PHYS_BASE + SZ_16 - 1,
154 .flags = IORESOURCE_MEM,
155};
156
157void __init kirkwood_rtc_init(void)
158{
159 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
160}
161
162
163/*****************************************************************************
164 * SATA
165 ****************************************************************************/
166static struct resource kirkwood_sata_resources[] = {
167 {
168 .name = "sata base",
169 .start = SATA_PHYS_BASE,
170 .end = SATA_PHYS_BASE + 0x5000 - 1,
171 .flags = IORESOURCE_MEM,
172 }, {
173 .name = "sata irq",
174 .start = IRQ_KIRKWOOD_SATA,
175 .end = IRQ_KIRKWOOD_SATA,
176 .flags = IORESOURCE_IRQ,
177 },
178};
179
180static struct platform_device kirkwood_sata = {
181 .name = "sata_mv",
182 .id = 0,
183 .dev = {
184 .coherent_dma_mask = 0xffffffff,
185 },
186 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
187 .resource = kirkwood_sata_resources,
188};
189
190void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
191{
192 sata_data->dram = &kirkwood_mbus_dram_info;
193 kirkwood_sata.dev.platform_data = sata_data;
194 platform_device_register(&kirkwood_sata);
195}
196
197
198/*****************************************************************************
199 * UART0
200 ****************************************************************************/
201static struct plat_serial8250_port kirkwood_uart0_data[] = {
202 {
203 .mapbase = UART0_PHYS_BASE,
204 .membase = (char *)UART0_VIRT_BASE,
205 .irq = IRQ_KIRKWOOD_UART_0,
206 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
207 .iotype = UPIO_MEM,
208 .regshift = 2,
209 .uartclk = KIRKWOOD_TCLK,
210 }, {
211 },
212};
213
214static struct resource kirkwood_uart0_resources[] = {
215 {
216 .start = UART0_PHYS_BASE,
217 .end = UART0_PHYS_BASE + 0xff,
218 .flags = IORESOURCE_MEM,
219 }, {
220 .start = IRQ_KIRKWOOD_UART_0,
221 .end = IRQ_KIRKWOOD_UART_0,
222 .flags = IORESOURCE_IRQ,
223 },
224};
225
226static struct platform_device kirkwood_uart0 = {
227 .name = "serial8250",
228 .id = 0,
229 .dev = {
230 .platform_data = kirkwood_uart0_data,
231 },
232 .resource = kirkwood_uart0_resources,
233 .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
234};
235
236void __init kirkwood_uart0_init(void)
237{
238 platform_device_register(&kirkwood_uart0);
239}
240
241
242/*****************************************************************************
243 * UART1
244 ****************************************************************************/
245static struct plat_serial8250_port kirkwood_uart1_data[] = {
246 {
247 .mapbase = UART1_PHYS_BASE,
248 .membase = (char *)UART1_VIRT_BASE,
249 .irq = IRQ_KIRKWOOD_UART_1,
250 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
251 .iotype = UPIO_MEM,
252 .regshift = 2,
253 .uartclk = KIRKWOOD_TCLK,
254 }, {
255 },
256};
257
258static struct resource kirkwood_uart1_resources[] = {
259 {
260 .start = UART1_PHYS_BASE,
261 .end = UART1_PHYS_BASE + 0xff,
262 .flags = IORESOURCE_MEM,
263 }, {
264 .start = IRQ_KIRKWOOD_UART_1,
265 .end = IRQ_KIRKWOOD_UART_1,
266 .flags = IORESOURCE_IRQ,
267 },
268};
269
270static struct platform_device kirkwood_uart1 = {
271 .name = "serial8250",
272 .id = 1,
273 .dev = {
274 .platform_data = kirkwood_uart1_data,
275 },
276 .resource = kirkwood_uart1_resources,
277 .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
278};
279
280void __init kirkwood_uart1_init(void)
281{
282 platform_device_register(&kirkwood_uart1);
283}
284
285
286/*****************************************************************************
287 * Time handling
288 ****************************************************************************/
289static void kirkwood_timer_init(void)
290{
291 orion_time_init(IRQ_KIRKWOOD_BRIDGE, KIRKWOOD_TCLK);
292}
293
294struct sys_timer kirkwood_timer = {
295 .init = kirkwood_timer_init,
296};
297
298
299/*****************************************************************************
300 * General
301 ****************************************************************************/
302static char * __init kirkwood_id(void)
303{
304 switch (readl(DEVICE_ID) & 0x3) {
305 case 0:
306 return "88F6180";
307 case 1:
308 return "88F6192";
309 case 2:
310 return "88F6281";
311 }
312
313 return "unknown 88F6000 variant";
314}
315
316static int __init is_l2_writethrough(void)
317{
318 return !!(readl(L2_CONFIG_REG) & L2_WRITETHROUGH);
319}
320
321void __init kirkwood_init(void)
322{
323 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
324 kirkwood_id(), KIRKWOOD_TCLK);
325
326 kirkwood_setup_cpu_mbus();
327
328#ifdef CONFIG_CACHE_FEROCEON_L2
329 feroceon_l2_init(is_l2_writethrough());
330#endif
331}
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
new file mode 100644
index 000000000000..5dee2f6b40a5
--- /dev/null
+++ b/arch/arm/mach-kirkwood/common.h
@@ -0,0 +1,42 @@
1/*
2 * arch/arm/mach-kirkwood/common.h
3 *
4 * Core functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_KIRKWOOD_COMMON_H
12#define __ARCH_KIRKWOOD_COMMON_H
13
14struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data;
16
17/*
18 * Basic Kirkwood init functions used early by machine-setup.
19 */
20void kirkwood_map_io(void);
21void kirkwood_init(void);
22void kirkwood_init_irq(void);
23
24extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
25void kirkwood_setup_cpu_mbus(void);
26void kirkwood_setup_pcie_io_win(int window, u32 base, u32 size,
27 int maj, int min);
28void kirkwood_setup_pcie_mem_win(int window, u32 base, u32 size,
29 int maj, int min);
30
31void kirkwood_ehci_init(void);
32void kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data);
33void kirkwood_pcie_init(void);
34void kirkwood_rtc_init(void);
35void kirkwood_sata_init(struct mv_sata_platform_data *sata_data);
36void kirkwood_uart0_init(void);
37void kirkwood_uart1_init(void);
38
39extern struct sys_timer kirkwood_timer;
40
41
42#endif
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
new file mode 100644
index 000000000000..d5c482c628e3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -0,0 +1,68 @@
1/*
2 * arch/arm/mach-kirkwood/db88f6281-bp-setup.c
3 *
4 * Marvell DB-88F6281-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h>
18#include <linux/timer.h>
19#include <linux/ata_platform.h>
20#include <linux/mv643xx_eth.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/kirkwood.h>
25#include "common.h"
26
27static struct mv643xx_eth_platform_data db88f6281_ge00_data = {
28 .phy_addr = 8,
29};
30
31static struct mv_sata_platform_data db88f6281_sata_data = {
32 .n_ports = 2,
33};
34
35static void __init db88f6281_init(void)
36{
37 /*
38 * Basic setup. Needs to be called early.
39 */
40 kirkwood_init();
41
42 kirkwood_ehci_init();
43 kirkwood_ge00_init(&db88f6281_ge00_data);
44 kirkwood_rtc_init();
45 kirkwood_sata_init(&db88f6281_sata_data);
46 kirkwood_uart0_init();
47 kirkwood_uart1_init();
48}
49
50static int __init db88f6281_pci_init(void)
51{
52 if (machine_is_db88f6281_bp())
53 kirkwood_pcie_init();
54
55 return 0;
56}
57subsys_initcall(db88f6281_pci_init);
58
59MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
60 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
61 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
62 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
63 .boot_params = 0x00000100,
64 .init_machine = db88f6281_init,
65 .map_io = kirkwood_map_io,
66 .init_irq = kirkwood_init_irq,
67 .timer = &kirkwood_timer,
68MACHINE_END
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
new file mode 100644
index 000000000000..302bb2cf6669
--- /dev/null
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-kirkwood/irq.c
3 *
4 * Kirkwood IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <linux/io.h>
15#include <asm/plat-orion/irq.h>
16#include "common.h"
17
18void __init kirkwood_init_irq(void)
19{
20 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
21 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
22}
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
new file mode 100644
index 000000000000..8282d0ff84bf
--- /dev/null
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -0,0 +1,180 @@
1/*
2 * arch/arm/mach-kirkwood/pcie.c
3 *
4 * PCIe functions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/plat-orion/pcie.h>
16#include "common.h"
17
18
19#define PCIE_BASE ((void __iomem *)PCIE_VIRT_BASE)
20
21static int pcie_valid_config(int bus, int dev)
22{
23 /*
24 * Don't go out when trying to access --
25 * 1. nonexisting device on local bus
26 * 2. where there's no device connected (no link)
27 */
28 if (bus == 0 && dev == 0)
29 return 1;
30
31 if (!orion_pcie_link_up(PCIE_BASE))
32 return 0;
33
34 if (bus == 0 && dev != 1)
35 return 0;
36
37 return 1;
38}
39
40
41/*
42 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
43 * and then reading the PCIE_CONF_DATA register. Need to make sure these
44 * transactions are atomic.
45 */
46static DEFINE_SPINLOCK(kirkwood_pcie_lock);
47
48static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
49 int size, u32 *val)
50{
51 unsigned long flags;
52 int ret;
53
54 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0) {
55 *val = 0xffffffff;
56 return PCIBIOS_DEVICE_NOT_FOUND;
57 }
58
59 spin_lock_irqsave(&kirkwood_pcie_lock, flags);
60 ret = orion_pcie_rd_conf(PCIE_BASE, bus, devfn, where, size, val);
61 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
62
63 return ret;
64}
65
66static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
67 int where, int size, u32 val)
68{
69 unsigned long flags;
70 int ret;
71
72 if (pcie_valid_config(bus->number, PCI_SLOT(devfn)) == 0)
73 return PCIBIOS_DEVICE_NOT_FOUND;
74
75 spin_lock_irqsave(&kirkwood_pcie_lock, flags);
76 ret = orion_pcie_wr_conf(PCIE_BASE, bus, devfn, where, size, val);
77 spin_unlock_irqrestore(&kirkwood_pcie_lock, flags);
78
79 return ret;
80}
81
82static struct pci_ops pcie_ops = {
83 .read = pcie_rd_conf,
84 .write = pcie_wr_conf,
85};
86
87
88static int kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
89{
90 struct resource *res;
91
92 /*
93 * Generic PCIe unit setup.
94 */
95 orion_pcie_setup(PCIE_BASE, &kirkwood_mbus_dram_info);
96
97 /*
98 * Request resources.
99 */
100 res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
101 if (!res)
102 panic("pcie_setup unable to alloc resources");
103
104 /*
105 * IORESOURCE_IO
106 */
107 res[0].name = "PCIe I/O Space";
108 res[0].flags = IORESOURCE_IO;
109 res[0].start = KIRKWOOD_PCIE_IO_PHYS_BASE;
110 res[0].end = res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
111 if (request_resource(&ioport_resource, &res[0]))
112 panic("Request PCIe IO resource failed\n");
113 sys->resource[0] = &res[0];
114
115 /*
116 * IORESOURCE_MEM
117 */
118 res[1].name = "PCIe Memory Space";
119 res[1].flags = IORESOURCE_MEM;
120 res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
121 res[1].end = res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
122 if (request_resource(&iomem_resource, &res[1]))
123 panic("Request PCIe Memory resource failed\n");
124 sys->resource[1] = &res[1];
125
126 sys->resource[2] = NULL;
127 sys->io_offset = 0;
128
129 return 1;
130}
131
132static void __devinit rc_pci_fixup(struct pci_dev *dev)
133{
134 /*
135 * Prevent enumeration of root complex.
136 */
137 if (dev->bus->parent == NULL && dev->devfn == 0) {
138 int i;
139
140 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
141 dev->resource[i].start = 0;
142 dev->resource[i].end = 0;
143 dev->resource[i].flags = 0;
144 }
145 }
146}
147DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
148
149static struct pci_bus __init *
150kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
151{
152 struct pci_bus *bus;
153
154 if (nr == 0) {
155 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
156 } else {
157 bus = NULL;
158 BUG();
159 }
160
161 return bus;
162}
163
164static int __init kirkwood_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
165{
166 return IRQ_KIRKWOOD_PCIE;
167}
168
169static struct hw_pci kirkwood_pci __initdata = {
170 .nr_controllers = 1,
171 .swizzle = pci_std_swizzle,
172 .setup = kirkwood_pcie_setup,
173 .scan = kirkwood_pcie_scan_bus,
174 .map_irq = kirkwood_pcie_map_irq,
175};
176
177void __init kirkwood_pcie_init(void)
178{
179 pci_common_init(&kirkwood_pci);
180}
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
new file mode 100644
index 000000000000..6cf642c504d3
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -0,0 +1,69 @@
1/*
2 * arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
3 *
4 * Marvell RD-88F6192-NAS Reference Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h>
18#include <linux/timer.h>
19#include <linux/ata_platform.h>
20#include <linux/mv643xx_eth.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/kirkwood.h>
25#include "common.h"
26
27#define RD88F6192_GPIO_USB_VBUS 10
28
29static struct mv643xx_eth_platform_data rd88f6192_ge00_data = {
30 .phy_addr = 8,
31};
32
33static struct mv_sata_platform_data rd88f6192_sata_data = {
34 .n_ports = 2,
35};
36
37static void __init rd88f6192_init(void)
38{
39 /*
40 * Basic setup. Needs to be called early.
41 */
42 kirkwood_init();
43
44 kirkwood_ehci_init();
45 kirkwood_ge00_init(&rd88f6192_ge00_data);
46 kirkwood_rtc_init();
47 kirkwood_sata_init(&rd88f6192_sata_data);
48 kirkwood_uart0_init();
49}
50
51static int __init rd88f6192_pci_init(void)
52{
53 if (machine_is_rd88f6192_nas())
54 kirkwood_pcie_init();
55
56 return 0;
57}
58subsys_initcall(rd88f6192_pci_init);
59
60MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
61 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
62 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
63 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
64 .boot_params = 0x00000100,
65 .init_machine = rd88f6192_init,
66 .map_io = kirkwood_map_io,
67 .init_irq = kirkwood_init_irq,
68 .timer = &kirkwood_timer,
69MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
new file mode 100644
index 000000000000..e1f8de2c74a2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -0,0 +1,113 @@
1/*
2 * arch/arm/mach-kirkwood/rd88f6281-setup.c
3 *
4 * Marvell RD-88F6281 Reference Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h>
18#include <linux/timer.h>
19#include <linux/ata_platform.h>
20#include <linux/mv643xx_eth.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/kirkwood.h>
25#include <asm/plat-orion/orion_nand.h>
26#include "common.h"
27
28static struct mtd_partition rd88f6281_nand_parts[] = {
29 {
30 .name = "u-boot",
31 .offset = 0,
32 .size = SZ_1M
33 }, {
34 .name = "uImage",
35 .offset = MTDPART_OFS_NXTBLK,
36 .size = SZ_2M
37 }, {
38 .name = "root",
39 .offset = MTDPART_OFS_NXTBLK,
40 .size = MTDPART_SIZ_FULL
41 },
42};
43
44static struct resource rd88f6281_nand_resource = {
45 .flags = IORESOURCE_MEM,
46 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
47 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
48 KIRKWOOD_NAND_MEM_SIZE - 1,
49};
50
51static struct orion_nand_data rd88f6281_nand_data = {
52 .parts = rd88f6281_nand_parts,
53 .nr_parts = ARRAY_SIZE(rd88f6281_nand_parts),
54 .cle = 0,
55 .ale = 1,
56 .width = 8,
57 .chip_delay = 25,
58};
59
60static struct platform_device rd88f6281_nand_flash = {
61 .name = "orion_nand",
62 .id = -1,
63 .dev = {
64 .platform_data = &rd88f6281_nand_data,
65 },
66 .resource = &rd88f6281_nand_resource,
67 .num_resources = 1,
68};
69
70static struct mv643xx_eth_platform_data rd88f6281_ge00_data = {
71 .phy_addr = -1,
72};
73
74static struct mv_sata_platform_data rd88f6281_sata_data = {
75 .n_ports = 2,
76};
77
78static void __init rd88f6281_init(void)
79{
80 /*
81 * Basic setup. Needs to be called early.
82 */
83 kirkwood_init();
84
85 kirkwood_ehci_init();
86 kirkwood_ge00_init(&rd88f6281_ge00_data);
87 kirkwood_rtc_init();
88 kirkwood_sata_init(&rd88f6281_sata_data);
89 kirkwood_uart0_init();
90 kirkwood_uart1_init();
91
92 platform_device_register(&rd88f6281_nand_flash);
93}
94
95static int __init rd88f6281_pci_init(void)
96{
97 if (machine_is_rd88f6281())
98 kirkwood_pcie_init();
99
100 return 0;
101}
102subsys_initcall(rd88f6281_pci_init);
103
104MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
105 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
106 .phys_io = KIRKWOOD_REGS_PHYS_BASE,
107 .io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
108 .boot_params = 0x00000100,
109 .init_machine = rd88f6281_init,
110 .map_io = kirkwood_map_io,
111 .init_irq = kirkwood_init_irq,
112 .timer = &kirkwood_timer,
113MACHINE_END
diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig
new file mode 100644
index 000000000000..0045bdd761ca
--- /dev/null
+++ b/arch/arm/mach-loki/Kconfig
@@ -0,0 +1,13 @@
1if ARCH_LOKI
2
3menu "Marvell Loki (88RC8480) Implementations"
4
5config MACH_LB88RC8480
6 bool "Marvell LB88RC8480 Development Board"
7 help
8 Say 'Y' here if you want your kernel to support the
9 Marvell LB88RC8480 Development Board.
10
11endmenu
12
13endif
diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile
new file mode 100644
index 000000000000..d43233ee590f
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile
@@ -0,0 +1,3 @@
1obj-y += common.o addr-map.o irq.o
2
3obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o
diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-loki/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-loki/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
new file mode 100644
index 000000000000..ba25e56ade58
--- /dev/null
+++ b/arch/arm/mach-loki/addr-map.c
@@ -0,0 +1,121 @@
1/*
2 * arch/arm/mach-loki/addr-map.c
3 *
4 * Address map functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <asm/hardware.h>
15#include <asm/io.h>
16#include "common.h"
17
18/*
19 * Generic Address Decode Windows bit settings
20 */
21#define TARGET_DDR 0
22#define TARGET_DEV_BUS 1
23#define TARGET_PCIE0 3
24#define TARGET_PCIE1 4
25#define ATTR_DEV_BOOT 0x0f
26#define ATTR_DEV_CS2 0x1b
27#define ATTR_DEV_CS1 0x1d
28#define ATTR_DEV_CS0 0x1e
29#define ATTR_PCIE_IO 0x51
30#define ATTR_PCIE_MEM 0x59
31
32/*
33 * Helpers to get DDR bank info
34 */
35#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
36#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
37
38/*
39 * CPU Address Decode Windows registers
40 */
41#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
42#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
43#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
44#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
45
46
47struct mbus_dram_target_info loki_mbus_dram_info;
48
49static void __init setup_cpu_win(int win, u32 base, u32 size,
50 u8 target, u8 attr, int remap)
51{
52 u32 ctrl;
53
54 base &= 0xffff0000;
55 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
56
57 writel(base, CPU_WIN_BASE(win));
58 writel(ctrl, CPU_WIN_CTRL(win));
59 if (win < 2) {
60 if (remap < 0)
61 remap = base;
62
63 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
64 writel(0, CPU_WIN_REMAP_HI(win));
65 }
66}
67
68void __init loki_setup_cpu_mbus(void)
69{
70 int i;
71 int cs;
72
73 /*
74 * First, disable and clear windows.
75 */
76 for (i = 0; i < 8; i++) {
77 writel(0, CPU_WIN_BASE(i));
78 writel(0, CPU_WIN_CTRL(i));
79 if (i < 2) {
80 writel(0, CPU_WIN_REMAP_LO(i));
81 writel(0, CPU_WIN_REMAP_HI(i));
82 }
83 }
84
85 /*
86 * Setup windows for PCIe IO+MEM space.
87 */
88 setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
89 TARGET_PCIE0, ATTR_PCIE_MEM, -1);
90 setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
91 TARGET_PCIE1, ATTR_PCIE_MEM, -1);
92
93 /*
94 * Setup MBUS dram target info.
95 */
96 loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
97
98 for (i = 0, cs = 0; i < 4; i++) {
99 u32 base = readl(DDR_BASE_CS(i));
100 u32 size = readl(DDR_SIZE_CS(i));
101
102 /*
103 * Chip select enabled?
104 */
105 if (size & 1) {
106 struct mbus_dram_window *w;
107
108 w = &loki_mbus_dram_info.cs[cs++];
109 w->cs_index = i;
110 w->mbus_attr = 0xf & ~(1 << i);
111 w->base = base & 0xffff0000;
112 w->size = (size | 0x0000ffff) + 1;
113 }
114 }
115 loki_mbus_dram_info.num_cs = cs;
116}
117
118void __init loki_setup_dev_boot_win(u32 base, u32 size)
119{
120 setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
121}
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
new file mode 100644
index 000000000000..410f50399dd3
--- /dev/null
+++ b/arch/arm/mach-loki/common.c
@@ -0,0 +1,305 @@
1/*
2 * arch/arm/mach-loki/common.c
3 *
4 * Core functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <asm/page.h>
18#include <asm/timex.h>
19#include <asm/mach/map.h>
20#include <asm/mach/time.h>
21#include <asm/arch/loki.h>
22#include <asm/plat-orion/orion_nand.h>
23#include <asm/plat-orion/time.h>
24#include "common.h"
25
26/*****************************************************************************
27 * I/O Address Mapping
28 ****************************************************************************/
29static struct map_desc loki_io_desc[] __initdata = {
30 {
31 .virtual = LOKI_REGS_VIRT_BASE,
32 .pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
33 .length = LOKI_REGS_SIZE,
34 .type = MT_DEVICE,
35 },
36};
37
38void __init loki_map_io(void)
39{
40 iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
41}
42
43
44/*****************************************************************************
45 * GE0
46 ****************************************************************************/
47struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
48 .t_clk = LOKI_TCLK,
49 .dram = &loki_mbus_dram_info,
50};
51
52static struct resource loki_ge0_shared_resources[] = {
53 {
54 .name = "ge0 base",
55 .start = GE0_PHYS_BASE + 0x2000,
56 .end = GE0_PHYS_BASE + 0x3fff,
57 .flags = IORESOURCE_MEM,
58 },
59};
60
61static struct platform_device loki_ge0_shared = {
62 .name = MV643XX_ETH_SHARED_NAME,
63 .id = 0,
64 .dev = {
65 .platform_data = &loki_ge0_shared_data,
66 },
67 .num_resources = 1,
68 .resource = loki_ge0_shared_resources,
69};
70
71static struct resource loki_ge0_resources[] = {
72 {
73 .name = "ge0 irq",
74 .start = IRQ_LOKI_GBE_A_INT,
75 .end = IRQ_LOKI_GBE_A_INT,
76 .flags = IORESOURCE_IRQ,
77 },
78};
79
80static struct platform_device loki_ge0 = {
81 .name = MV643XX_ETH_NAME,
82 .id = 0,
83 .num_resources = 1,
84 .resource = loki_ge0_resources,
85};
86
87void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
88{
89 eth_data->shared = &loki_ge0_shared;
90 loki_ge0.dev.platform_data = eth_data;
91
92 writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
93 platform_device_register(&loki_ge0_shared);
94 platform_device_register(&loki_ge0);
95}
96
97
98/*****************************************************************************
99 * GE1
100 ****************************************************************************/
101struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
102 .t_clk = LOKI_TCLK,
103 .dram = &loki_mbus_dram_info,
104};
105
106static struct resource loki_ge1_shared_resources[] = {
107 {
108 .name = "ge1 base",
109 .start = GE1_PHYS_BASE + 0x2000,
110 .end = GE1_PHYS_BASE + 0x3fff,
111 .flags = IORESOURCE_MEM,
112 },
113};
114
115static struct platform_device loki_ge1_shared = {
116 .name = MV643XX_ETH_SHARED_NAME,
117 .id = 1,
118 .dev = {
119 .platform_data = &loki_ge1_shared_data,
120 },
121 .num_resources = 1,
122 .resource = loki_ge1_shared_resources,
123};
124
125static struct resource loki_ge1_resources[] = {
126 {
127 .name = "ge1 irq",
128 .start = IRQ_LOKI_GBE_B_INT,
129 .end = IRQ_LOKI_GBE_B_INT,
130 .flags = IORESOURCE_IRQ,
131 },
132};
133
134static struct platform_device loki_ge1 = {
135 .name = MV643XX_ETH_NAME,
136 .id = 1,
137 .num_resources = 1,
138 .resource = loki_ge1_resources,
139};
140
141void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
142{
143 eth_data->shared = &loki_ge1_shared;
144 loki_ge1.dev.platform_data = eth_data;
145
146 writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
147 platform_device_register(&loki_ge1_shared);
148 platform_device_register(&loki_ge1);
149}
150
151
152/*****************************************************************************
153 * SAS/SATA
154 ****************************************************************************/
155static struct resource loki_sas_resources[] = {
156 {
157 .name = "mvsas0 mem",
158 .start = SAS0_PHYS_BASE,
159 .end = SAS0_PHYS_BASE + 0x01ff,
160 .flags = IORESOURCE_MEM,
161 }, {
162 .name = "mvsas0 irq",
163 .start = IRQ_LOKI_SAS_A,
164 .end = IRQ_LOKI_SAS_A,
165 .flags = IORESOURCE_IRQ,
166 }, {
167 .name = "mvsas1 mem",
168 .start = SAS1_PHYS_BASE,
169 .end = SAS1_PHYS_BASE + 0x01ff,
170 .flags = IORESOURCE_MEM,
171 }, {
172 .name = "mvsas1 irq",
173 .start = IRQ_LOKI_SAS_B,
174 .end = IRQ_LOKI_SAS_B,
175 .flags = IORESOURCE_IRQ,
176 },
177};
178
179static struct platform_device loki_sas = {
180 .name = "mvsas",
181 .id = 0,
182 .dev = {
183 .coherent_dma_mask = 0xffffffff,
184 },
185 .num_resources = ARRAY_SIZE(loki_sas_resources),
186 .resource = loki_sas_resources,
187};
188
189void __init loki_sas_init(void)
190{
191 writel(0x8300f707, DDR_REG(0x1424));
192 platform_device_register(&loki_sas);
193}
194
195
196/*****************************************************************************
197 * UART0
198 ****************************************************************************/
199static struct plat_serial8250_port loki_uart0_data[] = {
200 {
201 .mapbase = UART0_PHYS_BASE,
202 .membase = (char *)UART0_VIRT_BASE,
203 .irq = IRQ_LOKI_UART0,
204 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
205 .iotype = UPIO_MEM,
206 .regshift = 2,
207 .uartclk = LOKI_TCLK,
208 }, {
209 },
210};
211
212static struct resource loki_uart0_resources[] = {
213 {
214 .start = UART0_PHYS_BASE,
215 .end = UART0_PHYS_BASE + 0xff,
216 .flags = IORESOURCE_MEM,
217 }, {
218 .start = IRQ_LOKI_UART0,
219 .end = IRQ_LOKI_UART0,
220 .flags = IORESOURCE_IRQ,
221 },
222};
223
224static struct platform_device loki_uart0 = {
225 .name = "serial8250",
226 .id = 0,
227 .dev = {
228 .platform_data = loki_uart0_data,
229 },
230 .resource = loki_uart0_resources,
231 .num_resources = ARRAY_SIZE(loki_uart0_resources),
232};
233
234void __init loki_uart0_init(void)
235{
236 platform_device_register(&loki_uart0);
237}
238
239
240/*****************************************************************************
241 * UART1
242 ****************************************************************************/
243static struct plat_serial8250_port loki_uart1_data[] = {
244 {
245 .mapbase = UART1_PHYS_BASE,
246 .membase = (char *)UART1_VIRT_BASE,
247 .irq = IRQ_LOKI_UART1,
248 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
249 .iotype = UPIO_MEM,
250 .regshift = 2,
251 .uartclk = LOKI_TCLK,
252 }, {
253 },
254};
255
256static struct resource loki_uart1_resources[] = {
257 {
258 .start = UART1_PHYS_BASE,
259 .end = UART1_PHYS_BASE + 0xff,
260 .flags = IORESOURCE_MEM,
261 }, {
262 .start = IRQ_LOKI_UART1,
263 .end = IRQ_LOKI_UART1,
264 .flags = IORESOURCE_IRQ,
265 },
266};
267
268static struct platform_device loki_uart1 = {
269 .name = "serial8250",
270 .id = 1,
271 .dev = {
272 .platform_data = loki_uart1_data,
273 },
274 .resource = loki_uart1_resources,
275 .num_resources = ARRAY_SIZE(loki_uart1_resources),
276};
277
278void __init loki_uart1_init(void)
279{
280 platform_device_register(&loki_uart1);
281}
282
283
284/*****************************************************************************
285 * Time handling
286 ****************************************************************************/
287static void loki_timer_init(void)
288{
289 orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
290}
291
292struct sys_timer loki_timer = {
293 .init = loki_timer_init,
294};
295
296
297/*****************************************************************************
298 * General
299 ****************************************************************************/
300void __init loki_init(void)
301{
302 printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
303
304 loki_setup_cpu_mbus();
305}
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
new file mode 100644
index 000000000000..26054fd0f05e
--- /dev/null
+++ b/arch/arm/mach-loki/common.h
@@ -0,0 +1,36 @@
1/*
2 * arch/arm/mach-loki/common.h
3 *
4 * Core functions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_LOKI_COMMON_H
12#define __ARCH_LOKI_COMMON_H
13
14struct mv643xx_eth_platform_data;
15
16/*
17 * Basic Loki init functions used early by machine-setup.
18 */
19void loki_map_io(void);
20void loki_init(void);
21void loki_init_irq(void);
22
23extern struct mbus_dram_target_info loki_mbus_dram_info;
24void loki_setup_cpu_mbus(void);
25void loki_setup_dev_boot_win(u32 base, u32 size);
26
27void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
28void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
29void loki_sas_init(void);
30void loki_uart0_init(void);
31void loki_uart1_init(void);
32
33extern struct sys_timer loki_timer;
34
35
36#endif
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
new file mode 100644
index 000000000000..d839af91fe03
--- /dev/null
+++ b/arch/arm/mach-loki/irq.c
@@ -0,0 +1,21 @@
1/*
2 * arch/arm/mach-loki/irq.c
3 *
4 * Marvell Loki (88RC8480) IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/irq.h>
14#include <asm/io.h>
15#include <asm/plat-orion/irq.h>
16#include "common.h"
17
18void __init loki_init_irq(void)
19{
20 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
21}
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
new file mode 100644
index 000000000000..d1b9e6e6253a
--- /dev/null
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -0,0 +1,100 @@
1/*
2 * arch/arm/mach-loki/lb88rc8480-setup.c
3 *
4 * Marvell LB88RC8480 Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mtd/nand.h>
17#include <linux/timer.h>
18#include <linux/ata_platform.h>
19#include <linux/mv643xx_eth.h>
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/arch/loki.h>
23#include "common.h"
24
25#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
26#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
27
28#define LB88RC8480_NOR_BOOT_BASE 0xff000000
29#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
30
31static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
32 {
33 .name = "kernel",
34 .offset = 0,
35 .size = SZ_2M,
36 }, {
37 .name = "root-fs",
38 .offset = SZ_2M,
39 .size = (SZ_8M + SZ_4M + SZ_1M),
40 }, {
41 .name = "u-boot",
42 .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
43 .size = SZ_1M,
44 },
45};
46
47static struct physmap_flash_data lb88rc8480_boot_flash_data = {
48 .parts = lb88rc8480_boot_flash_parts,
49 .nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
50 .width = 1, /* 8 bit bus width */
51};
52
53static struct resource lb88rc8480_boot_flash_resource = {
54 .flags = IORESOURCE_MEM,
55 .start = LB88RC8480_NOR_BOOT_BASE,
56 .end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
57};
58
59static struct platform_device lb88rc8480_boot_flash = {
60 .name = "physmap-flash",
61 .id = 0,
62 .dev = {
63 .platform_data = &lb88rc8480_boot_flash_data,
64 },
65 .num_resources = 1,
66 .resource = &lb88rc8480_boot_flash_resource,
67};
68
69static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
70 .phy_addr = 1,
71 .mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
72};
73
74static void __init lb88rc8480_init(void)
75{
76 /*
77 * Basic setup. Needs to be called early.
78 */
79 loki_init();
80
81 loki_ge0_init(&lb88rc8480_ge0_data);
82 loki_sas_init();
83 loki_uart0_init();
84 loki_uart1_init();
85
86 loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
87 LB88RC8480_FLASH_BOOT_CS_SIZE);
88 platform_device_register(&lb88rc8480_boot_flash);
89}
90
91MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
92 /* Maintainer: Ke Wei <kewei@marvell.com> */
93 .phys_io = LOKI_REGS_PHYS_BASE,
94 .io_pg_offst = ((LOKI_REGS_VIRT_BASE) >> 18) & 0xfffc,
95 .boot_params = 0x00000100,
96 .init_machine = lb88rc8480_init,
97 .map_io = loki_map_io,
98 .init_irq = loki_init_irq,
99 .timer = &loki_timer,
100MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
new file mode 100644
index 000000000000..d83cb86837db
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Kconfig
@@ -0,0 +1,13 @@
1if ARCH_MV78XX0
2
3menu "Marvell MV78xx0 Implementations"
4
5config MACH_DB78X00_BP
6 bool "Marvell DB-78x00-BP Development Board"
7 help
8 Say 'Y' here if you want your kernel to support the
9 Marvell DB-78x00-BP Development Board.
10
11endmenu
12
13endif
diff --git a/arch/arm/mach-mv78xx0/Makefile b/arch/arm/mach-mv78xx0/Makefile
new file mode 100644
index 000000000000..ec16c05c3b1b
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile
@@ -0,0 +1,2 @@
1obj-y += common.o addr-map.o irq.o pcie.o
2obj-$(CONFIG_MACH_DB78X00_BP) += db78x00-bp-setup.o
diff --git a/arch/arm/mach-mv78xx0/Makefile.boot b/arch/arm/mach-mv78xx0/Makefile.boot
new file mode 100644
index 000000000000..67039c3e0c48
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/Makefile.boot
@@ -0,0 +1,3 @@
1 zreladdr-y := 0x00008000
2params_phys-y := 0x00000100
3initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
new file mode 100644
index 000000000000..4004b672a2eb
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -0,0 +1,156 @@
1/*
2 * arch/arm/mach-mv78xx0/addr-map.c
3 *
4 * Address map functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <asm/io.h>
15#include "common.h"
16
17/*
18 * Generic Address Decode Windows bit settings
19 */
20#define TARGET_DDR 0
21#define TARGET_DEV_BUS 1
22#define TARGET_PCIE0 4
23#define TARGET_PCIE1 8
24#define TARGET_PCIE(i) ((i) ? TARGET_PCIE1 : TARGET_PCIE0)
25#define ATTR_DEV_SPI_ROM 0x1f
26#define ATTR_DEV_BOOT 0x2f
27#define ATTR_DEV_CS3 0x37
28#define ATTR_DEV_CS2 0x3b
29#define ATTR_DEV_CS1 0x3d
30#define ATTR_DEV_CS0 0x3e
31#define ATTR_PCIE_IO(l) (0xf0 & ~(0x10 << (l)))
32#define ATTR_PCIE_MEM(l) (0xf8 & ~(0x10 << (l)))
33
34/*
35 * Helpers to get DDR bank info
36 */
37#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
38#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
39
40/*
41 * CPU Address Decode Windows registers
42 */
43#define WIN0_OFF(n) (BRIDGE_VIRT_BASE + 0x0000 + ((n) << 4))
44#define WIN8_OFF(n) (BRIDGE_VIRT_BASE + 0x0900 + (((n) - 8) << 4))
45#define WIN_CTRL_OFF 0x0000
46#define WIN_BASE_OFF 0x0004
47#define WIN_REMAP_LO_OFF 0x0008
48#define WIN_REMAP_HI_OFF 0x000c
49
50
51struct mbus_dram_target_info mv78xx0_mbus_dram_info;
52
53static void __init __iomem *win_cfg_base(int win)
54{
55 /*
56 * Find the control register base address for this window.
57 *
58 * BRIDGE_VIRT_BASE points to the right (CPU0's or CPU1's)
59 * MBUS bridge depending on which CPU core we're running on,
60 * so we don't need to take that into account here.
61 */
62
63 return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
64}
65
66static int __init cpu_win_can_remap(int win)
67{
68 if (win < 8)
69 return 1;
70
71 return 0;
72}
73
74static void __init setup_cpu_win(int win, u32 base, u32 size,
75 u8 target, u8 attr, int remap)
76{
77 void __iomem *addr = win_cfg_base(win);
78 u32 ctrl;
79
80 base &= 0xffff0000;
81 ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
82
83 writel(base, addr + WIN_BASE_OFF);
84 writel(ctrl, addr + WIN_CTRL_OFF);
85 if (cpu_win_can_remap(win)) {
86 if (remap < 0)
87 remap = base;
88
89 writel(remap & 0xffff0000, addr + WIN_REMAP_LO_OFF);
90 writel(0, addr + WIN_REMAP_HI_OFF);
91 }
92}
93
94void __init mv78xx0_setup_cpu_mbus(void)
95{
96 void __iomem *addr;
97 int i;
98 int cs;
99
100 /*
101 * First, disable and clear windows.
102 */
103 for (i = 0; i < 14; i++) {
104 addr = win_cfg_base(i);
105
106 writel(0, addr + WIN_BASE_OFF);
107 writel(0, addr + WIN_CTRL_OFF);
108 if (cpu_win_can_remap(i)) {
109 writel(0, addr + WIN_REMAP_LO_OFF);
110 writel(0, addr + WIN_REMAP_HI_OFF);
111 }
112 }
113
114 /*
115 * Setup MBUS dram target info.
116 */
117 mv78xx0_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
118
119 if (mv78xx0_core_index() == 0)
120 addr = (void __iomem *)DDR_WINDOW_CPU0_BASE;
121 else
122 addr = (void __iomem *)DDR_WINDOW_CPU1_BASE;
123
124 for (i = 0, cs = 0; i < 4; i++) {
125 u32 base = readl(addr + DDR_BASE_CS_OFF(i));
126 u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
127
128 /*
129 * Chip select enabled?
130 */
131 if (size & 1) {
132 struct mbus_dram_window *w;
133
134 w = &mv78xx0_mbus_dram_info.cs[cs++];
135 w->cs_index = i;
136 w->mbus_attr = 0xf & ~(1 << i);
137 w->base = base & 0xffff0000;
138 w->size = (size | 0x0000ffff) + 1;
139 }
140 }
141 mv78xx0_mbus_dram_info.num_cs = cs;
142}
143
144void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
145 int maj, int min)
146{
147 setup_cpu_win(window, base, size, TARGET_PCIE(maj),
148 ATTR_PCIE_IO(min), -1);
149}
150
151void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
152 int maj, int min)
153{
154 setup_cpu_win(window, base, size, TARGET_PCIE(maj),
155 ATTR_PCIE_MEM(min), -1);
156}
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
new file mode 100644
index 000000000000..d27b83b7bf62
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -0,0 +1,754 @@
1/*
2 * arch/arm/mach-mv78xx0/common.c
3 *
4 * Core functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/serial_8250.h>
15#include <linux/mbus.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/ata_platform.h>
18#include <asm/mach/map.h>
19#include <asm/mach/time.h>
20#include <asm/arch/mv78xx0.h>
21#include <asm/plat-orion/cache-feroceon-l2.h>
22#include <asm/plat-orion/ehci-orion.h>
23#include <asm/plat-orion/orion_nand.h>
24#include <asm/plat-orion/time.h>
25#include "common.h"
26
27
28/*****************************************************************************
29 * Common bits
30 ****************************************************************************/
31int mv78xx0_core_index(void)
32{
33 u32 extra;
34
35 /*
36 * Read Extra Features register.
37 */
38 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
39
40 return !!(extra & 0x00004000);
41}
42
43static int get_hclk(void)
44{
45 int hclk;
46
47 /*
48 * HCLK tick rate is configured by DEV_D[7:5] pins.
49 */
50 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
51 case 0:
52 hclk = 166666667;
53 break;
54 case 1:
55 hclk = 200000000;
56 break;
57 case 2:
58 hclk = 266666667;
59 break;
60 case 3:
61 hclk = 333333333;
62 break;
63 case 4:
64 hclk = 400000000;
65 break;
66 default:
67 panic("unknown HCLK PLL setting: %.8x\n",
68 readl(SAMPLE_AT_RESET_LOW));
69 }
70
71 return hclk;
72}
73
74static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
75{
76 u32 cfg;
77
78 /*
79 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
80 * PCLK/L2CLK by bits [19:14].
81 */
82 if (core_index == 0) {
83 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
84 } else {
85 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
86 }
87
88 /*
89 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
90 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
91 */
92 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
93
94 /*
95 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
96 * ratio (1, 2, 3).
97 */
98 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
99}
100
101static int get_tclk(void)
102{
103 int tclk;
104
105 /*
106 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
107 */
108 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
109 case 1:
110 tclk = 166666667;
111 break;
112 case 3:
113 tclk = 200000000;
114 break;
115 default:
116 panic("unknown TCLK PLL setting: %.8x\n",
117 readl(SAMPLE_AT_RESET_HIGH));
118 }
119
120 return tclk;
121}
122
123
124/*****************************************************************************
125 * I/O Address Mapping
126 ****************************************************************************/
127static struct map_desc mv78xx0_io_desc[] __initdata = {
128 {
129 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
130 .pfn = 0,
131 .length = MV78XX0_CORE_REGS_SIZE,
132 .type = MT_DEVICE,
133 }, {
134 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
135 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
136 .length = MV78XX0_PCIE_IO_SIZE * 8,
137 .type = MT_DEVICE,
138 }, {
139 .virtual = MV78XX0_REGS_VIRT_BASE,
140 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
141 .length = MV78XX0_REGS_SIZE,
142 .type = MT_DEVICE,
143 },
144};
145
146void __init mv78xx0_map_io(void)
147{
148 unsigned long phys;
149
150 /*
151 * Map the right set of per-core registers depending on
152 * which core we are running on.
153 */
154 if (mv78xx0_core_index() == 0) {
155 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
156 } else {
157 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
158 }
159 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
160
161 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
162}
163
164
165/*****************************************************************************
166 * EHCI
167 ****************************************************************************/
168static struct orion_ehci_data mv78xx0_ehci_data = {
169 .dram = &mv78xx0_mbus_dram_info,
170};
171
172static u64 ehci_dmamask = 0xffffffffUL;
173
174
175/*****************************************************************************
176 * EHCI0
177 ****************************************************************************/
178static struct resource mv78xx0_ehci0_resources[] = {
179 {
180 .start = USB0_PHYS_BASE,
181 .end = USB0_PHYS_BASE + 0x0fff,
182 .flags = IORESOURCE_MEM,
183 }, {
184 .start = IRQ_MV78XX0_USB_0,
185 .end = IRQ_MV78XX0_USB_0,
186 .flags = IORESOURCE_IRQ,
187 },
188};
189
190static struct platform_device mv78xx0_ehci0 = {
191 .name = "orion-ehci",
192 .id = 0,
193 .dev = {
194 .dma_mask = &ehci_dmamask,
195 .coherent_dma_mask = 0xffffffff,
196 .platform_data = &mv78xx0_ehci_data,
197 },
198 .resource = mv78xx0_ehci0_resources,
199 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
200};
201
202void __init mv78xx0_ehci0_init(void)
203{
204 platform_device_register(&mv78xx0_ehci0);
205}
206
207
208/*****************************************************************************
209 * EHCI1
210 ****************************************************************************/
211static struct resource mv78xx0_ehci1_resources[] = {
212 {
213 .start = USB1_PHYS_BASE,
214 .end = USB1_PHYS_BASE + 0x0fff,
215 .flags = IORESOURCE_MEM,
216 }, {
217 .start = IRQ_MV78XX0_USB_1,
218 .end = IRQ_MV78XX0_USB_1,
219 .flags = IORESOURCE_IRQ,
220 },
221};
222
223static struct platform_device mv78xx0_ehci1 = {
224 .name = "orion-ehci",
225 .id = 1,
226 .dev = {
227 .dma_mask = &ehci_dmamask,
228 .coherent_dma_mask = 0xffffffff,
229 .platform_data = &mv78xx0_ehci_data,
230 },
231 .resource = mv78xx0_ehci1_resources,
232 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
233};
234
235void __init mv78xx0_ehci1_init(void)
236{
237 platform_device_register(&mv78xx0_ehci1);
238}
239
240
241/*****************************************************************************
242 * EHCI2
243 ****************************************************************************/
244static struct resource mv78xx0_ehci2_resources[] = {
245 {
246 .start = USB2_PHYS_BASE,
247 .end = USB2_PHYS_BASE + 0x0fff,
248 .flags = IORESOURCE_MEM,
249 }, {
250 .start = IRQ_MV78XX0_USB_2,
251 .end = IRQ_MV78XX0_USB_2,
252 .flags = IORESOURCE_IRQ,
253 },
254};
255
256static struct platform_device mv78xx0_ehci2 = {
257 .name = "orion-ehci",
258 .id = 2,
259 .dev = {
260 .dma_mask = &ehci_dmamask,
261 .coherent_dma_mask = 0xffffffff,
262 .platform_data = &mv78xx0_ehci_data,
263 },
264 .resource = mv78xx0_ehci2_resources,
265 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
266};
267
268void __init mv78xx0_ehci2_init(void)
269{
270 platform_device_register(&mv78xx0_ehci2);
271}
272
273
274/*****************************************************************************
275 * GE00
276 ****************************************************************************/
277struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
278 .t_clk = 0,
279 .dram = &mv78xx0_mbus_dram_info,
280};
281
282static struct resource mv78xx0_ge00_shared_resources[] = {
283 {
284 .name = "ge00 base",
285 .start = GE00_PHYS_BASE + 0x2000,
286 .end = GE00_PHYS_BASE + 0x3fff,
287 .flags = IORESOURCE_MEM,
288 },
289};
290
291static struct platform_device mv78xx0_ge00_shared = {
292 .name = MV643XX_ETH_SHARED_NAME,
293 .id = 0,
294 .dev = {
295 .platform_data = &mv78xx0_ge00_shared_data,
296 },
297 .num_resources = 1,
298 .resource = mv78xx0_ge00_shared_resources,
299};
300
301static struct resource mv78xx0_ge00_resources[] = {
302 {
303 .name = "ge00 irq",
304 .start = IRQ_MV78XX0_GE00_SUM,
305 .end = IRQ_MV78XX0_GE00_SUM,
306 .flags = IORESOURCE_IRQ,
307 },
308};
309
310static struct platform_device mv78xx0_ge00 = {
311 .name = MV643XX_ETH_NAME,
312 .id = 0,
313 .num_resources = 1,
314 .resource = mv78xx0_ge00_resources,
315};
316
317void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
318{
319 eth_data->shared = &mv78xx0_ge00_shared;
320 mv78xx0_ge00.dev.platform_data = eth_data;
321
322 platform_device_register(&mv78xx0_ge00_shared);
323 platform_device_register(&mv78xx0_ge00);
324}
325
326
327/*****************************************************************************
328 * GE01
329 ****************************************************************************/
330struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
331 .t_clk = 0,
332 .dram = &mv78xx0_mbus_dram_info,
333};
334
335static struct resource mv78xx0_ge01_shared_resources[] = {
336 {
337 .name = "ge01 base",
338 .start = GE01_PHYS_BASE + 0x2000,
339 .end = GE01_PHYS_BASE + 0x3fff,
340 .flags = IORESOURCE_MEM,
341 },
342};
343
344static struct platform_device mv78xx0_ge01_shared = {
345 .name = MV643XX_ETH_SHARED_NAME,
346 .id = 1,
347 .dev = {
348 .platform_data = &mv78xx0_ge01_shared_data,
349 },
350 .num_resources = 1,
351 .resource = mv78xx0_ge01_shared_resources,
352};
353
354static struct resource mv78xx0_ge01_resources[] = {
355 {
356 .name = "ge01 irq",
357 .start = IRQ_MV78XX0_GE01_SUM,
358 .end = IRQ_MV78XX0_GE01_SUM,
359 .flags = IORESOURCE_IRQ,
360 },
361};
362
363static struct platform_device mv78xx0_ge01 = {
364 .name = MV643XX_ETH_NAME,
365 .id = 1,
366 .num_resources = 1,
367 .resource = mv78xx0_ge01_resources,
368};
369
370void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
371{
372 eth_data->shared = &mv78xx0_ge01_shared;
373 eth_data->shared_smi = &mv78xx0_ge00_shared;
374 mv78xx0_ge01.dev.platform_data = eth_data;
375
376 platform_device_register(&mv78xx0_ge01_shared);
377 platform_device_register(&mv78xx0_ge01);
378}
379
380
381/*****************************************************************************
382 * GE10
383 ****************************************************************************/
384struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
385 .t_clk = 0,
386 .dram = &mv78xx0_mbus_dram_info,
387};
388
389static struct resource mv78xx0_ge10_shared_resources[] = {
390 {
391 .name = "ge10 base",
392 .start = GE10_PHYS_BASE + 0x2000,
393 .end = GE10_PHYS_BASE + 0x3fff,
394 .flags = IORESOURCE_MEM,
395 },
396};
397
398static struct platform_device mv78xx0_ge10_shared = {
399 .name = MV643XX_ETH_SHARED_NAME,
400 .id = 2,
401 .dev = {
402 .platform_data = &mv78xx0_ge10_shared_data,
403 },
404 .num_resources = 1,
405 .resource = mv78xx0_ge10_shared_resources,
406};
407
408static struct resource mv78xx0_ge10_resources[] = {
409 {
410 .name = "ge10 irq",
411 .start = IRQ_MV78XX0_GE10_SUM,
412 .end = IRQ_MV78XX0_GE10_SUM,
413 .flags = IORESOURCE_IRQ,
414 },
415};
416
417static struct platform_device mv78xx0_ge10 = {
418 .name = MV643XX_ETH_NAME,
419 .id = 2,
420 .num_resources = 1,
421 .resource = mv78xx0_ge10_resources,
422};
423
424void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
425{
426 eth_data->shared = &mv78xx0_ge10_shared;
427 eth_data->shared_smi = &mv78xx0_ge00_shared;
428 mv78xx0_ge10.dev.platform_data = eth_data;
429
430 platform_device_register(&mv78xx0_ge10_shared);
431 platform_device_register(&mv78xx0_ge10);
432}
433
434
435/*****************************************************************************
436 * GE11
437 ****************************************************************************/
438struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
439 .t_clk = 0,
440 .dram = &mv78xx0_mbus_dram_info,
441};
442
443static struct resource mv78xx0_ge11_shared_resources[] = {
444 {
445 .name = "ge11 base",
446 .start = GE11_PHYS_BASE + 0x2000,
447 .end = GE11_PHYS_BASE + 0x3fff,
448 .flags = IORESOURCE_MEM,
449 },
450};
451
452static struct platform_device mv78xx0_ge11_shared = {
453 .name = MV643XX_ETH_SHARED_NAME,
454 .id = 3,
455 .dev = {
456 .platform_data = &mv78xx0_ge11_shared_data,
457 },
458 .num_resources = 1,
459 .resource = mv78xx0_ge11_shared_resources,
460};
461
462static struct resource mv78xx0_ge11_resources[] = {
463 {
464 .name = "ge11 irq",
465 .start = IRQ_MV78XX0_GE11_SUM,
466 .end = IRQ_MV78XX0_GE11_SUM,
467 .flags = IORESOURCE_IRQ,
468 },
469};
470
471static struct platform_device mv78xx0_ge11 = {
472 .name = MV643XX_ETH_NAME,
473 .id = 3,
474 .num_resources = 1,
475 .resource = mv78xx0_ge11_resources,
476};
477
478void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
479{
480 eth_data->shared = &mv78xx0_ge11_shared;
481 eth_data->shared_smi = &mv78xx0_ge00_shared;
482 mv78xx0_ge11.dev.platform_data = eth_data;
483
484 platform_device_register(&mv78xx0_ge11_shared);
485 platform_device_register(&mv78xx0_ge11);
486}
487
488
489/*****************************************************************************
490 * SATA
491 ****************************************************************************/
492static struct resource mv78xx0_sata_resources[] = {
493 {
494 .name = "sata base",
495 .start = SATA_PHYS_BASE,
496 .end = SATA_PHYS_BASE + 0x5000 - 1,
497 .flags = IORESOURCE_MEM,
498 }, {
499 .name = "sata irq",
500 .start = IRQ_MV78XX0_SATA,
501 .end = IRQ_MV78XX0_SATA,
502 .flags = IORESOURCE_IRQ,
503 },
504};
505
506static struct platform_device mv78xx0_sata = {
507 .name = "sata_mv",
508 .id = 0,
509 .dev = {
510 .coherent_dma_mask = 0xffffffff,
511 },
512 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
513 .resource = mv78xx0_sata_resources,
514};
515
516void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
517{
518 sata_data->dram = &mv78xx0_mbus_dram_info;
519 mv78xx0_sata.dev.platform_data = sata_data;
520 platform_device_register(&mv78xx0_sata);
521}
522
523
524/*****************************************************************************
525 * UART0
526 ****************************************************************************/
527static struct plat_serial8250_port mv78xx0_uart0_data[] = {
528 {
529 .mapbase = UART0_PHYS_BASE,
530 .membase = (char *)UART0_VIRT_BASE,
531 .irq = IRQ_MV78XX0_UART_0,
532 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
533 .iotype = UPIO_MEM,
534 .regshift = 2,
535 .uartclk = 0,
536 }, {
537 },
538};
539
540static struct resource mv78xx0_uart0_resources[] = {
541 {
542 .start = UART0_PHYS_BASE,
543 .end = UART0_PHYS_BASE + 0xff,
544 .flags = IORESOURCE_MEM,
545 }, {
546 .start = IRQ_MV78XX0_UART_0,
547 .end = IRQ_MV78XX0_UART_0,
548 .flags = IORESOURCE_IRQ,
549 },
550};
551
552static struct platform_device mv78xx0_uart0 = {
553 .name = "serial8250",
554 .id = 0,
555 .dev = {
556 .platform_data = mv78xx0_uart0_data,
557 },
558 .resource = mv78xx0_uart0_resources,
559 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
560};
561
562void __init mv78xx0_uart0_init(void)
563{
564 platform_device_register(&mv78xx0_uart0);
565}
566
567
568/*****************************************************************************
569 * UART1
570 ****************************************************************************/
571static struct plat_serial8250_port mv78xx0_uart1_data[] = {
572 {
573 .mapbase = UART1_PHYS_BASE,
574 .membase = (char *)UART1_VIRT_BASE,
575 .irq = IRQ_MV78XX0_UART_1,
576 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
577 .iotype = UPIO_MEM,
578 .regshift = 2,
579 .uartclk = 0,
580 }, {
581 },
582};
583
584static struct resource mv78xx0_uart1_resources[] = {
585 {
586 .start = UART1_PHYS_BASE,
587 .end = UART1_PHYS_BASE + 0xff,
588 .flags = IORESOURCE_MEM,
589 }, {
590 .start = IRQ_MV78XX0_UART_1,
591 .end = IRQ_MV78XX0_UART_1,
592 .flags = IORESOURCE_IRQ,
593 },
594};
595
596static struct platform_device mv78xx0_uart1 = {
597 .name = "serial8250",
598 .id = 1,
599 .dev = {
600 .platform_data = mv78xx0_uart1_data,
601 },
602 .resource = mv78xx0_uart1_resources,
603 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
604};
605
606void __init mv78xx0_uart1_init(void)
607{
608 platform_device_register(&mv78xx0_uart1);
609}
610
611
612/*****************************************************************************
613 * UART2
614 ****************************************************************************/
615static struct plat_serial8250_port mv78xx0_uart2_data[] = {
616 {
617 .mapbase = UART2_PHYS_BASE,
618 .membase = (char *)UART2_VIRT_BASE,
619 .irq = IRQ_MV78XX0_UART_2,
620 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
621 .iotype = UPIO_MEM,
622 .regshift = 2,
623 .uartclk = 0,
624 }, {
625 },
626};
627
628static struct resource mv78xx0_uart2_resources[] = {
629 {
630 .start = UART2_PHYS_BASE,
631 .end = UART2_PHYS_BASE + 0xff,
632 .flags = IORESOURCE_MEM,
633 }, {
634 .start = IRQ_MV78XX0_UART_2,
635 .end = IRQ_MV78XX0_UART_2,
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device mv78xx0_uart2 = {
641 .name = "serial8250",
642 .id = 2,
643 .dev = {
644 .platform_data = mv78xx0_uart2_data,
645 },
646 .resource = mv78xx0_uart2_resources,
647 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
648};
649
650void __init mv78xx0_uart2_init(void)
651{
652 platform_device_register(&mv78xx0_uart2);
653}
654
655
656/*****************************************************************************
657 * UART3
658 ****************************************************************************/
659static struct plat_serial8250_port mv78xx0_uart3_data[] = {
660 {
661 .mapbase = UART3_PHYS_BASE,
662 .membase = (char *)UART3_VIRT_BASE,
663 .irq = IRQ_MV78XX0_UART_3,
664 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
665 .iotype = UPIO_MEM,
666 .regshift = 2,
667 .uartclk = 0,
668 }, {
669 },
670};
671
672static struct resource mv78xx0_uart3_resources[] = {
673 {
674 .start = UART3_PHYS_BASE,
675 .end = UART3_PHYS_BASE + 0xff,
676 .flags = IORESOURCE_MEM,
677 }, {
678 .start = IRQ_MV78XX0_UART_3,
679 .end = IRQ_MV78XX0_UART_3,
680 .flags = IORESOURCE_IRQ,
681 },
682};
683
684static struct platform_device mv78xx0_uart3 = {
685 .name = "serial8250",
686 .id = 3,
687 .dev = {
688 .platform_data = mv78xx0_uart3_data,
689 },
690 .resource = mv78xx0_uart3_resources,
691 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
692};
693
694void __init mv78xx0_uart3_init(void)
695{
696 platform_device_register(&mv78xx0_uart3);
697}
698
699
700/*****************************************************************************
701 * Time handling
702 ****************************************************************************/
703static void mv78xx0_timer_init(void)
704{
705 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
706}
707
708struct sys_timer mv78xx0_timer = {
709 .init = mv78xx0_timer_init,
710};
711
712
713/*****************************************************************************
714 * General
715 ****************************************************************************/
716static int __init is_l2_writethrough(void)
717{
718 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
719}
720
721void __init mv78xx0_init(void)
722{
723 int core_index;
724 int hclk;
725 int pclk;
726 int l2clk;
727 int tclk;
728
729 core_index = mv78xx0_core_index();
730 hclk = get_hclk();
731 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
732 tclk = get_tclk();
733
734 printk(KERN_INFO "MV78xx0 core #%d, ", core_index);
735 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
736 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
737 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
738 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
739
740 mv78xx0_setup_cpu_mbus();
741
742#ifdef CONFIG_CACHE_FEROCEON_L2
743 feroceon_l2_init(is_l2_writethrough());
744#endif
745
746 mv78xx0_ge00_shared_data.t_clk = tclk;
747 mv78xx0_ge01_shared_data.t_clk = tclk;
748 mv78xx0_ge10_shared_data.t_clk = tclk;
749 mv78xx0_ge11_shared_data.t_clk = tclk;
750 mv78xx0_uart0_data[0].uartclk = tclk;
751 mv78xx0_uart1_data[0].uartclk = tclk;
752 mv78xx0_uart2_data[0].uartclk = tclk;
753 mv78xx0_uart3_data[0].uartclk = tclk;
754}
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
new file mode 100644
index 000000000000..78af5de319dd
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -0,0 +1,49 @@
1/*
2 * arch/arm/mach-mv78xx0/common.h
3 *
4 * Core functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ARCH_MV78XX0_COMMON_H
12#define __ARCH_MV78XX0_COMMON_H
13
14struct mv643xx_eth_platform_data;
15struct mv_sata_platform_data;
16
17/*
18 * Basic MV78xx0 init functions used early by machine-setup.
19 */
20int mv78xx0_core_index(void);
21void mv78xx0_map_io(void);
22void mv78xx0_init(void);
23void mv78xx0_init_irq(void);
24
25extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
26void mv78xx0_setup_cpu_mbus(void);
27void mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
28 int maj, int min);
29void mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
30 int maj, int min);
31
32void mv78xx0_ehci0_init(void);
33void mv78xx0_ehci1_init(void);
34void mv78xx0_ehci2_init(void);
35void mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data);
36void mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data);
37void mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data);
38void mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data);
39void mv78xx0_pcie_init(int init_port0, int init_port1);
40void mv78xx0_sata_init(struct mv_sata_platform_data *sata_data);
41void mv78xx0_uart0_init(void);
42void mv78xx0_uart1_init(void);
43void mv78xx0_uart2_init(void);
44void mv78xx0_uart3_init(void);
45
46extern struct sys_timer mv78xx0_timer;
47
48
49#endif
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
new file mode 100644
index 000000000000..0c93d19193df
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -0,0 +1,94 @@
1/*
2 * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
3 *
4 * Marvell DB-78x00-BP Development Board Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/ata_platform.h>
15#include <linux/mv643xx_eth.h>
16#include <asm/arch/mv78xx0.h>
17#include <asm/mach-types.h>
18#include <asm/mach/arch.h>
19#include "common.h"
20
21static struct mv643xx_eth_platform_data db78x00_ge00_data = {
22 .phy_addr = 8,
23};
24
25static struct mv643xx_eth_platform_data db78x00_ge01_data = {
26 .phy_addr = 9,
27};
28
29static struct mv643xx_eth_platform_data db78x00_ge10_data = {
30 .phy_addr = -1,
31};
32
33static struct mv643xx_eth_platform_data db78x00_ge11_data = {
34 .phy_addr = -1,
35};
36
37static struct mv_sata_platform_data db78x00_sata_data = {
38 .n_ports = 2,
39};
40
41static void __init db78x00_init(void)
42{
43 /*
44 * Basic MV78xx0 setup. Needs to be called early.
45 */
46 mv78xx0_init();
47
48 /*
49 * Partition on-chip peripherals between the two CPU cores.
50 */
51 if (mv78xx0_core_index() == 0) {
52 mv78xx0_ehci0_init();
53 mv78xx0_ehci1_init();
54 mv78xx0_ehci2_init();
55 mv78xx0_ge00_init(&db78x00_ge00_data);
56 mv78xx0_ge01_init(&db78x00_ge01_data);
57 mv78xx0_ge10_init(&db78x00_ge10_data);
58 mv78xx0_ge11_init(&db78x00_ge11_data);
59 mv78xx0_sata_init(&db78x00_sata_data);
60 mv78xx0_uart0_init();
61 mv78xx0_uart2_init();
62 } else {
63 mv78xx0_uart1_init();
64 mv78xx0_uart3_init();
65 }
66}
67
68static int __init db78x00_pci_init(void)
69{
70 if (machine_is_db78x00_bp()) {
71 /*
72 * Assign the x16 PCIe slot on the board to CPU core
73 * #0, and let CPU core #1 have the four x1 slots.
74 */
75 if (mv78xx0_core_index() == 0)
76 mv78xx0_pcie_init(0, 1);
77 else
78 mv78xx0_pcie_init(1, 0);
79 }
80
81 return 0;
82}
83subsys_initcall(db78x00_pci_init);
84
85MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
86 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
87 .phys_io = MV78XX0_REGS_PHYS_BASE,
88 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
89 .boot_params = 0x00000100,
90 .init_machine = db78x00_init,
91 .map_io = mv78xx0_map_io,
92 .init_irq = mv78xx0_init_irq,
93 .timer = &mv78xx0_timer,
94MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
new file mode 100644
index 000000000000..60f4ee4d4532
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -0,0 +1,22 @@
1/*
2 * arch/arm/mach-mv78xx0/irq.c
3 *
4 * MV78xx0 IRQ handling.
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/pci.h>
14#include <asm/arch/mv78xx0.h>
15#include <asm/plat-orion/irq.h>
16#include "common.h"
17
18void __init mv78xx0_init_irq(void)
19{
20 orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
21 orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
22}
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
new file mode 100644
index 000000000000..b78e1443159f
--- /dev/null
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -0,0 +1,312 @@
1/*
2 * arch/arm/mach-mv78xx0/pcie.c
3 *
4 * PCIe functions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/mbus.h>
14#include <asm/mach/pci.h>
15#include <asm/plat-orion/pcie.h>
16#include "common.h"
17
18struct pcie_port {
19 u8 maj;
20 u8 min;
21 u8 root_bus_nr;
22 void __iomem *base;
23 spinlock_t conf_lock;
24 char io_space_name[16];
25 char mem_space_name[16];
26 struct resource res[2];
27};
28
29static struct pcie_port pcie_port[8];
30static int num_pcie_ports;
31static struct resource pcie_io_space;
32static struct resource pcie_mem_space;
33
34
35static void __init mv78xx0_pcie_preinit(void)
36{
37 int i;
38 u32 size_each;
39 u32 start;
40 int win;
41
42 pcie_io_space.name = "PCIe I/O Space";
43 pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
44 pcie_io_space.end =
45 MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
46 pcie_io_space.flags = IORESOURCE_IO;
47 if (request_resource(&iomem_resource, &pcie_io_space))
48 panic("can't allocate PCIe I/O space");
49
50 pcie_mem_space.name = "PCIe MEM Space";
51 pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
52 pcie_mem_space.end =
53 MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
54 pcie_mem_space.flags = IORESOURCE_MEM;
55 if (request_resource(&iomem_resource, &pcie_mem_space))
56 panic("can't allocate PCIe MEM space");
57
58 for (i = 0; i < num_pcie_ports; i++) {
59 struct pcie_port *pp = pcie_port + i;
60
61 snprintf(pp->io_space_name, sizeof(pp->io_space_name),
62 "PCIe %d.%d I/O", pp->maj, pp->min);
63 pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
64 pp->res[0].name = pp->io_space_name;
65 pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
66 pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
67 pp->res[0].flags = IORESOURCE_IO;
68
69 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
70 "PCIe %d.%d MEM", pp->maj, pp->min);
71 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
72 pp->res[1].name = pp->mem_space_name;
73 pp->res[1].flags = IORESOURCE_MEM;
74 }
75
76 switch (num_pcie_ports) {
77 case 0:
78 size_each = 0;
79 break;
80
81 case 1:
82 size_each = 0x30000000;
83 break;
84
85 case 2 ... 3:
86 size_each = 0x10000000;
87 break;
88
89 case 4 ... 6:
90 size_each = 0x08000000;
91 break;
92
93 case 7:
94 size_each = 0x04000000;
95 break;
96
97 default:
98 panic("invalid number of PCIe ports");
99 }
100
101 start = MV78XX0_PCIE_MEM_PHYS_BASE;
102 for (i = 0; i < num_pcie_ports; i++) {
103 struct pcie_port *pp = pcie_port + i;
104
105 pp->res[1].start = start;
106 pp->res[1].end = start + size_each - 1;
107 start += size_each;
108 }
109
110 for (i = 0; i < num_pcie_ports; i++) {
111 struct pcie_port *pp = pcie_port + i;
112
113 if (request_resource(&pcie_io_space, &pp->res[0]))
114 panic("can't allocate PCIe I/O sub-space");
115
116 if (request_resource(&pcie_mem_space, &pp->res[1]))
117 panic("can't allocate PCIe MEM sub-space");
118 }
119
120 win = 0;
121 for (i = 0; i < num_pcie_ports; i++) {
122 struct pcie_port *pp = pcie_port + i;
123
124 mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
125 pp->res[0].end - pp->res[0].start + 1,
126 pp->maj, pp->min);
127
128 mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
129 pp->res[1].end - pp->res[1].start + 1,
130 pp->maj, pp->min);
131 }
132}
133
134static int __init mv78xx0_pcie_setup(int nr, struct pci_sys_data *sys)
135{
136 struct pcie_port *pp;
137
138 if (nr >= num_pcie_ports)
139 return 0;
140
141 pp = &pcie_port[nr];
142 pp->root_bus_nr = sys->busnr;
143
144 /*
145 * Generic PCIe unit setup.
146 */
147 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
148 orion_pcie_setup(pp->base, &mv78xx0_mbus_dram_info);
149
150 sys->resource[0] = &pp->res[0];
151 sys->resource[1] = &pp->res[1];
152 sys->resource[2] = NULL;
153
154 return 1;
155}
156
157static struct pcie_port *bus_to_port(int bus)
158{
159 int i;
160
161 for (i = num_pcie_ports - 1; i >= 0; i--) {
162 int rbus = pcie_port[i].root_bus_nr;
163 if (rbus != -1 && rbus <= bus)
164 break;
165 }
166
167 return i >= 0 ? pcie_port + i : NULL;
168}
169
170static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
171{
172 /*
173 * Don't go out when trying to access nonexisting devices
174 * on the local bus.
175 */
176 if (bus == pp->root_bus_nr && dev > 1)
177 return 0;
178
179 return 1;
180}
181
182static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
183 int size, u32 *val)
184{
185 struct pcie_port *pp = bus_to_port(bus->number);
186 unsigned long flags;
187 int ret;
188
189 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
190 *val = 0xffffffff;
191 return PCIBIOS_DEVICE_NOT_FOUND;
192 }
193
194 spin_lock_irqsave(&pp->conf_lock, flags);
195 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
196 spin_unlock_irqrestore(&pp->conf_lock, flags);
197
198 return ret;
199}
200
201static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
202 int where, int size, u32 val)
203{
204 struct pcie_port *pp = bus_to_port(bus->number);
205 unsigned long flags;
206 int ret;
207
208 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
209 return PCIBIOS_DEVICE_NOT_FOUND;
210
211 spin_lock_irqsave(&pp->conf_lock, flags);
212 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
213 spin_unlock_irqrestore(&pp->conf_lock, flags);
214
215 return ret;
216}
217
218static struct pci_ops pcie_ops = {
219 .read = pcie_rd_conf,
220 .write = pcie_wr_conf,
221};
222
223static void __devinit rc_pci_fixup(struct pci_dev *dev)
224{
225 /*
226 * Prevent enumeration of root complex.
227 */
228 if (dev->bus->parent == NULL && dev->devfn == 0) {
229 int i;
230
231 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
232 dev->resource[i].start = 0;
233 dev->resource[i].end = 0;
234 dev->resource[i].flags = 0;
235 }
236 }
237}
238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
239
240static struct pci_bus __init *
241mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys)
242{
243 struct pci_bus *bus;
244
245 if (nr < num_pcie_ports) {
246 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
247 } else {
248 bus = NULL;
249 BUG();
250 }
251
252 return bus;
253}
254
255static int __init mv78xx0_pcie_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
256{
257 struct pcie_port *pp = bus_to_port(dev->bus->number);
258
259 return IRQ_MV78XX0_PCIE_00 + (pp->maj << 2) + pp->min;
260}
261
262static struct hw_pci mv78xx0_pci __initdata = {
263 .nr_controllers = 8,
264 .preinit = mv78xx0_pcie_preinit,
265 .swizzle = pci_std_swizzle,
266 .setup = mv78xx0_pcie_setup,
267 .scan = mv78xx0_pcie_scan_bus,
268 .map_irq = mv78xx0_pcie_map_irq,
269};
270
271static void __init add_pcie_port(int maj, int min, unsigned long base)
272{
273 printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
274
275 if (orion_pcie_link_up((void __iomem *)base)) {
276 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
277
278 printk("link up\n");
279
280 pp->maj = maj;
281 pp->min = min;
282 pp->root_bus_nr = -1;
283 pp->base = (void __iomem *)base;
284 spin_lock_init(&pp->conf_lock);
285 memset(pp->res, 0, sizeof(pp->res));
286 } else {
287 printk("link down, ignoring\n");
288 }
289}
290
291void __init mv78xx0_pcie_init(int init_port0, int init_port1)
292{
293 if (init_port0) {
294 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
295 if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
296 add_pcie_port(0, 1, PCIE01_VIRT_BASE);
297 add_pcie_port(0, 2, PCIE02_VIRT_BASE);
298 add_pcie_port(0, 3, PCIE03_VIRT_BASE);
299 }
300 }
301
302 if (init_port1) {
303 add_pcie_port(1, 0, PCIE10_VIRT_BASE);
304 if (!orion_pcie_x4_mode((void __iomem *)PCIE10_VIRT_BASE)) {
305 add_pcie_port(1, 1, PCIE11_VIRT_BASE);
306 add_pcie_port(1, 2, PCIE12_VIRT_BASE);
307 add_pcie_port(1, 3, PCIE13_VIRT_BASE);
308 }
309 }
310
311 pci_common_init(&mv78xx0_pci);
312}
diff --git a/arch/arm/mach-omap1/Makefile b/arch/arm/mach-omap1/Makefile
index c06f5254c0f3..1bda8f5d7546 100644
--- a/arch/arm/mach-omap1/Makefile
+++ b/arch/arm/mach-omap1/Makefile
@@ -3,7 +3,9 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := io.o id.o clock.o irq.o mux.o serial.o devices.o 6obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o
7
8obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
7 9
8obj-$(CONFIG_OMAP_MPU_TIMER) += time.o 10obj-$(CONFIG_OMAP_MPU_TIMER) += time.o
9obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o 11obj-$(CONFIG_OMAP_32K_TIMER) += timer32k.o
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index bcb984f2300f..3f39e0e79c9f 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/mutex.h>
13#include <linux/platform_device.h> 14#include <linux/platform_device.h>
14#include <linux/input.h> 15#include <linux/input.h>
15#include <linux/clk.h> 16#include <linux/clk.h>
@@ -202,7 +203,7 @@ static struct omap_board_config_kernel nokia770_config[] __initdata = {
202#define AMPLIFIER_CTRL_GPIO 58 203#define AMPLIFIER_CTRL_GPIO 58
203 204
204static struct clk *dspxor_ck; 205static struct clk *dspxor_ck;
205static DECLARE_MUTEX(audio_pwr_sem); 206static DEFINE_MUTEX(audio_pwr_lock);
206/* 207/*
207 * audio_pwr_state 208 * audio_pwr_state
208 * +--+-------------------------+---------------------------------------+ 209 * +--+-------------------------+---------------------------------------+
@@ -218,7 +219,7 @@ static DECLARE_MUTEX(audio_pwr_sem);
218static int audio_pwr_state = -1; 219static int audio_pwr_state = -1;
219 220
220/* 221/*
221 * audio_pwr_up / down should be called under audio_pwr_sem 222 * audio_pwr_up / down should be called under audio_pwr_lock
222 */ 223 */
223static void nokia770_audio_pwr_up(void) 224static void nokia770_audio_pwr_up(void)
224{ 225{
@@ -237,11 +238,11 @@ static void nokia770_audio_pwr_up(void)
237 238
238static void codec_delayed_power_down(struct work_struct *work) 239static void codec_delayed_power_down(struct work_struct *work)
239{ 240{
240 down(&audio_pwr_sem); 241 mutex_lock(&audio_pwr_lock);
241 if (audio_pwr_state == -1) 242 if (audio_pwr_state == -1)
242 aic23_power_down(); 243 aic23_power_down();
243 clk_disable(dspxor_ck); 244 clk_disable(dspxor_ck);
244 up(&audio_pwr_sem); 245 mutex_unlock(&audio_pwr_lock);
245} 246}
246 247
247static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down); 248static DECLARE_DELAYED_WORK(codec_power_down_work, codec_delayed_power_down);
@@ -258,19 +259,19 @@ static void nokia770_audio_pwr_down(void)
258static int 259static int
259nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage) 260nokia770_audio_pwr_up_request(struct dsp_kfunc_device *kdev, int stage)
260{ 261{
261 down(&audio_pwr_sem); 262 mutex_lock(&audio_pwr_lock);
262 if (audio_pwr_state == -1) 263 if (audio_pwr_state == -1)
263 nokia770_audio_pwr_up(); 264 nokia770_audio_pwr_up();
264 /* force audio_pwr_state = 0, even if it was 1. */ 265 /* force audio_pwr_state = 0, even if it was 1. */
265 audio_pwr_state = 0; 266 audio_pwr_state = 0;
266 up(&audio_pwr_sem); 267 mutex_unlock(&audio_pwr_lock);
267 return 0; 268 return 0;
268} 269}
269 270
270static int 271static int
271nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage) 272nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
272{ 273{
273 down(&audio_pwr_sem); 274 mutex_lock(&audio_pwr_lock);
274 switch (stage) { 275 switch (stage) {
275 case 1: 276 case 1:
276 if (audio_pwr_state == 0) 277 if (audio_pwr_state == 0)
@@ -283,7 +284,7 @@ nokia770_audio_pwr_down_request(struct dsp_kfunc_device *kdev, int stage)
283 } 284 }
284 break; 285 break;
285 } 286 }
286 up(&audio_pwr_sem); 287 mutex_unlock(&audio_pwr_lock);
287 return 0; 288 return 0;
288} 289}
289 290
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index a66505f58b15..845c66371ca3 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -267,13 +267,17 @@ static struct i2c_board_info __initdata osk_i2c_board_info[] = {
267 267
268static void __init osk_init_smc91x(void) 268static void __init osk_init_smc91x(void)
269{ 269{
270 u32 l;
271
270 if ((gpio_request(0, "smc_irq")) < 0) { 272 if ((gpio_request(0, "smc_irq")) < 0) {
271 printk("Error requesting gpio 0 for smc91x irq\n"); 273 printk("Error requesting gpio 0 for smc91x irq\n");
272 return; 274 return;
273 } 275 }
274 276
275 /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */ 277 /* Check EMIFS wait states to fix errors with SMC_GET_PKT_HDR */
276 EMIFS_CCS(1) |= 0x3; 278 l = omap_readl(EMIFS_CCS(1));
279 l |= 0x3;
280 omap_writel(l, EMIFS_CCS(1));
277} 281}
278 282
279static void __init osk_init_cf(void) 283static void __init osk_init_cf(void)
@@ -526,20 +530,26 @@ static void __init osk_mistral_init(void) { }
526 530
527static void __init osk_init(void) 531static void __init osk_init(void)
528{ 532{
533 u32 l;
534
529 /* Workaround for wrong CS3 (NOR flash) timing 535 /* Workaround for wrong CS3 (NOR flash) timing
530 * There are some U-Boot versions out there which configure 536 * There are some U-Boot versions out there which configure
531 * wrong CS3 memory timings. This mainly leads to CRC 537 * wrong CS3 memory timings. This mainly leads to CRC
532 * or similar errors if you use NOR flash (e.g. with JFFS2) 538 * or similar errors if you use NOR flash (e.g. with JFFS2)
533 */ 539 */
534 if (EMIFS_CCS(3) != EMIFS_CS3_VAL) 540 l = omap_readl(EMIFS_CCS(3));
535 EMIFS_CCS(3) = EMIFS_CS3_VAL; 541 if (l != EMIFS_CS3_VAL)
542 omap_writel(EMIFS_CS3_VAL, EMIFS_CCS(3));
536 543
537 osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys(); 544 osk_flash_resource.end = osk_flash_resource.start = omap_cs3_phys();
538 osk_flash_resource.end += SZ_32M - 1; 545 osk_flash_resource.end += SZ_32M - 1;
539 platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices)); 546 platform_add_devices(osk5912_devices, ARRAY_SIZE(osk5912_devices));
540 omap_board_config = osk_config; 547 omap_board_config = osk_config;
541 omap_board_config_size = ARRAY_SIZE(osk_config); 548 omap_board_config_size = ARRAY_SIZE(osk_config);
542 USB_TRANSCEIVER_CTRL_REG |= (3 << 1); 549
550 l = omap_readl(USB_TRANSCEIVER_CTRL);
551 l |= (3 << 1);
552 omap_writel(l, USB_TRANSCEIVER_CTRL);
543 553
544 /* irq for tps65010 chip */ 554 /* irq for tps65010 chip */
545 /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */ 555 /* bootloader effectively does: omap_cfg_reg(U19_1610_MPUIO1); */
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 30e188109046..0cf62ef5ecb7 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -32,7 +32,7 @@
32 32
33static void fpga_mask_irq(unsigned int irq) 33static void fpga_mask_irq(unsigned int irq)
34{ 34{
35 irq -= OMAP1510_IH_FPGA_BASE; 35 irq -= OMAP_FPGA_IRQ_BASE;
36 36
37 if (irq < 8) 37 if (irq < 8)
38 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) 38 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO)
@@ -65,7 +65,7 @@ static void fpga_ack_irq(unsigned int irq)
65 65
66static void fpga_unmask_irq(unsigned int irq) 66static void fpga_unmask_irq(unsigned int irq)
67{ 67{
68 irq -= OMAP1510_IH_FPGA_BASE; 68 irq -= OMAP_FPGA_IRQ_BASE;
69 69
70 if (irq < 8) 70 if (irq < 8)
71 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)), 71 __raw_writeb((__raw_readb(OMAP1510_FPGA_IMR_LO) | (1 << irq)),
@@ -95,8 +95,8 @@ void innovator_fpga_IRQ_demux(unsigned int irq, struct irq_desc *desc)
95 if (!stat) 95 if (!stat)
96 return; 96 return;
97 97
98 for (fpga_irq = OMAP1510_IH_FPGA_BASE; 98 for (fpga_irq = OMAP_FPGA_IRQ_BASE;
99 (fpga_irq < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS)) && stat; 99 (fpga_irq < OMAP_FPGA_IRQ_END) && stat;
100 fpga_irq++, stat >>= 1) { 100 fpga_irq++, stat >>= 1) {
101 if (stat & 1) { 101 if (stat & 1) {
102 d = irq_desc + fpga_irq; 102 d = irq_desc + fpga_irq;
@@ -151,7 +151,7 @@ void omap1510_fpga_init_irq(void)
151 __raw_writeb(0, OMAP1510_FPGA_IMR_HI); 151 __raw_writeb(0, OMAP1510_FPGA_IMR_HI);
152 __raw_writeb(0, INNOVATOR_FPGA_IMR2); 152 __raw_writeb(0, INNOVATOR_FPGA_IMR2);
153 153
154 for (i = OMAP1510_IH_FPGA_BASE; i < (OMAP1510_IH_FPGA_BASE + NR_FPGA_IRQS); i++) { 154 for (i = OMAP_FPGA_IRQ_BASE; i < OMAP_FPGA_IRQ_END; i++) {
155 155
156 if (i == OMAP1510_INT_FPGA_TS) { 156 if (i == OMAP1510_INT_FPGA_TS) {
157 /* 157 /*
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
new file mode 100644
index 000000000000..2d2c2522b048
--- /dev/null
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -0,0 +1,280 @@
1/*
2 * linux/arch/arm/mach-omap1/mcbsp.c
3 *
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Multichannel mode not supported.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19
20#include <asm/arch/dma.h>
21#include <asm/arch/mux.h>
22#include <asm/arch/cpu.h>
23#include <asm/arch/mcbsp.h>
24#include <asm/arch/dsp_common.h>
25
26#define DPS_RSTCT2_PER_EN (1 << 0)
27#define DSP_RSTCT2_WD_PER_EN (1 << 1)
28
29struct mcbsp_internal_clk {
30 struct clk clk;
31 struct clk **childs;
32 int n_childs;
33};
34
35#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX)
36static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
37{
38 const char *clk_names[] = { "dsp_ck", "api_ck", "dspxor_ck" };
39 int i;
40
41 mclk->n_childs = ARRAY_SIZE(clk_names);
42 mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
43 GFP_KERNEL);
44
45 for (i = 0; i < mclk->n_childs; i++) {
46 /* We fake a platform device to get correct device id */
47 struct platform_device pdev;
48
49 pdev.dev.bus = &platform_bus_type;
50 pdev.id = mclk->clk.id;
51 mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
52 if (IS_ERR(mclk->childs[i]))
53 printk(KERN_ERR "Could not get clock %s (%d).\n",
54 clk_names[i], mclk->clk.id);
55 }
56}
57
58static int omap_mcbsp_clk_enable(struct clk *clk)
59{
60 struct mcbsp_internal_clk *mclk = container_of(clk,
61 struct mcbsp_internal_clk, clk);
62 int i;
63
64 for (i = 0; i < mclk->n_childs; i++)
65 clk_enable(mclk->childs[i]);
66 return 0;
67}
68
69static void omap_mcbsp_clk_disable(struct clk *clk)
70{
71 struct mcbsp_internal_clk *mclk = container_of(clk,
72 struct mcbsp_internal_clk, clk);
73 int i;
74
75 for (i = 0; i < mclk->n_childs; i++)
76 clk_disable(mclk->childs[i]);
77}
78
79static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
80 {
81 .clk = {
82 .name = "mcbsp_clk",
83 .id = 1,
84 .enable = omap_mcbsp_clk_enable,
85 .disable = omap_mcbsp_clk_disable,
86 },
87 },
88 {
89 .clk = {
90 .name = "mcbsp_clk",
91 .id = 3,
92 .enable = omap_mcbsp_clk_enable,
93 .disable = omap_mcbsp_clk_disable,
94 },
95 },
96};
97
98#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
99#else
100#define omap_mcbsp_clks_size 0
101static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
102static inline void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
103{ }
104#endif
105
106static int omap1_mcbsp_check(unsigned int id)
107{
108 /* REVISIT: Check correctly for number of registered McBSPs */
109 if (cpu_is_omap730()) {
110 if (id > OMAP_MAX_MCBSP_COUNT - 2) {
111 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
112 id + 1);
113 return -ENODEV;
114 }
115 return 0;
116 }
117
118 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
119 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
120 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n",
121 id + 1);
122 return -ENODEV;
123 }
124 return 0;
125 }
126
127 return -ENODEV;
128}
129
130static void omap1_mcbsp_request(unsigned int id)
131{
132 /*
133 * On 1510, 1610 and 1710, McBSP1 and McBSP3
134 * are DSP public peripherals.
135 */
136 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
137 omap_dsp_request_mem();
138 /*
139 * DSP external peripheral reset
140 * FIXME: This should be moved to dsp code
141 */
142 __raw_writew(__raw_readw(DSP_RSTCT2) | DPS_RSTCT2_PER_EN |
143 DSP_RSTCT2_WD_PER_EN, DSP_RSTCT2);
144 }
145}
146
147static void omap1_mcbsp_free(unsigned int id)
148{
149 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
150 omap_dsp_release_mem();
151}
152
153static struct omap_mcbsp_ops omap1_mcbsp_ops = {
154 .check = omap1_mcbsp_check,
155 .request = omap1_mcbsp_request,
156 .free = omap1_mcbsp_free,
157};
158
159#ifdef CONFIG_ARCH_OMAP730
160static struct omap_mcbsp_platform_data omap730_mcbsp_pdata[] = {
161 {
162 .virt_base = io_p2v(OMAP730_MCBSP1_BASE),
163 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
164 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
165 .rx_irq = INT_730_McBSP1RX,
166 .tx_irq = INT_730_McBSP1TX,
167 .ops = &omap1_mcbsp_ops,
168 },
169 {
170 .virt_base = io_p2v(OMAP730_MCBSP2_BASE),
171 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
172 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
173 .rx_irq = INT_730_McBSP2RX,
174 .tx_irq = INT_730_McBSP2TX,
175 .ops = &omap1_mcbsp_ops,
176 },
177};
178#define OMAP730_MCBSP_PDATA_SZ ARRAY_SIZE(omap730_mcbsp_pdata)
179#else
180#define omap730_mcbsp_pdata NULL
181#define OMAP730_MCBSP_PDATA_SZ 0
182#endif
183
184#ifdef CONFIG_ARCH_OMAP15XX
185static struct omap_mcbsp_platform_data omap15xx_mcbsp_pdata[] = {
186 {
187 .virt_base = OMAP1510_MCBSP1_BASE,
188 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
189 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
190 .rx_irq = INT_McBSP1RX,
191 .tx_irq = INT_McBSP1TX,
192 .ops = &omap1_mcbsp_ops,
193 .clk_name = "mcbsp_clk",
194 },
195 {
196 .virt_base = io_p2v(OMAP1510_MCBSP2_BASE),
197 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
198 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
199 .rx_irq = INT_1510_SPI_RX,
200 .tx_irq = INT_1510_SPI_TX,
201 .ops = &omap1_mcbsp_ops,
202 },
203 {
204 .virt_base = OMAP1510_MCBSP3_BASE,
205 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
206 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
207 .rx_irq = INT_McBSP3RX,
208 .tx_irq = INT_McBSP3TX,
209 .ops = &omap1_mcbsp_ops,
210 .clk_name = "mcbsp_clk",
211 },
212};
213#define OMAP15XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap15xx_mcbsp_pdata)
214#else
215#define omap15xx_mcbsp_pdata NULL
216#define OMAP15XX_MCBSP_PDATA_SZ 0
217#endif
218
219#ifdef CONFIG_ARCH_OMAP16XX
220static struct omap_mcbsp_platform_data omap16xx_mcbsp_pdata[] = {
221 {
222 .virt_base = OMAP1610_MCBSP1_BASE,
223 .dma_rx_sync = OMAP_DMA_MCBSP1_RX,
224 .dma_tx_sync = OMAP_DMA_MCBSP1_TX,
225 .rx_irq = INT_McBSP1RX,
226 .tx_irq = INT_McBSP1TX,
227 .ops = &omap1_mcbsp_ops,
228 .clk_name = "mcbsp_clk",
229 },
230 {
231 .virt_base = io_p2v(OMAP1610_MCBSP2_BASE),
232 .dma_rx_sync = OMAP_DMA_MCBSP2_RX,
233 .dma_tx_sync = OMAP_DMA_MCBSP2_TX,
234 .rx_irq = INT_1610_McBSP2_RX,
235 .tx_irq = INT_1610_McBSP2_TX,
236 .ops = &omap1_mcbsp_ops,
237 },
238 {
239 .virt_base = OMAP1610_MCBSP3_BASE,
240 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
241 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
242 .rx_irq = INT_McBSP3RX,
243 .tx_irq = INT_McBSP3TX,
244 .ops = &omap1_mcbsp_ops,
245 .clk_name = "mcbsp_clk",
246 },
247};
248#define OMAP16XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap16xx_mcbsp_pdata)
249#else
250#define omap16xx_mcbsp_pdata NULL
251#define OMAP16XX_MCBSP_PDATA_SZ 0
252#endif
253
254int __init omap1_mcbsp_init(void)
255{
256 int i;
257
258 for (i = 0; i < omap_mcbsp_clks_size; i++) {
259 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
260 omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
261 clk_register(&omap_mcbsp_clks[i].clk);
262 }
263 }
264
265 if (cpu_is_omap730())
266 omap_mcbsp_register_board_cfg(omap730_mcbsp_pdata,
267 OMAP730_MCBSP_PDATA_SZ);
268
269 if (cpu_is_omap15xx())
270 omap_mcbsp_register_board_cfg(omap15xx_mcbsp_pdata,
271 OMAP15XX_MCBSP_PDATA_SZ);
272
273 if (cpu_is_omap16xx())
274 omap_mcbsp_register_board_cfg(omap16xx_mcbsp_pdata,
275 OMAP16XX_MCBSP_PDATA_SZ);
276
277 return omap_mcbsp_init();
278}
279
280arch_initcall(omap1_mcbsp_init);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index e6c64e10b7ec..742f79e73bd7 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -116,13 +116,6 @@ void omap_pm_idle(void)
116 return; 116 return;
117 } 117 }
118 118
119 /*
120 * Since an interrupt may set up a timer, we don't want to
121 * reprogram the hardware timer with interrupts enabled.
122 * Re-enable interrupts only after returning from idle.
123 */
124 timer_dyn_reprogram();
125
126#ifdef CONFIG_OMAP_MPU_TIMER 119#ifdef CONFIG_OMAP_MPU_TIMER
127#warning Enable 32kHz OS timer in order to allow sleep states in idle 120#warning Enable 32kHz OS timer in order to allow sleep states in idle
128 use_idlect1 = use_idlect1 & ~(1 << 9); 121 use_idlect1 = use_idlect1 & ~(1 << 9);
diff --git a/arch/arm/plat-omap/sram-fn.S b/arch/arm/mach-omap1/sram.S
index 9e1813c77e05..126d252062d7 100644
--- a/arch/arm/plat-omap/sram-fn.S
+++ b/arch/arm/mach-omap1/sram.S
@@ -18,7 +18,7 @@
18/* 18/*
19 * Reprograms ULPD and CKCTL. 19 * Reprograms ULPD and CKCTL.
20 */ 20 */
21ENTRY(sram_reprogram_clock) 21ENTRY(omap1_sram_reprogram_clock)
22 stmfd sp!, {r0 - r12, lr} @ save registers on stack 22 stmfd sp!, {r0 - r12, lr} @ save registers on stack
23 23
24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000 24 mov r2, #IO_ADDRESS(DPLL_CTL) & 0xff000000
@@ -53,5 +53,5 @@ lock: ldrh r4, [r2], #0 @ read back dpll value
53 53
54out: 54out:
55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return 55 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
56ENTRY(sram_reprogram_clock_sz) 56ENTRY(omap1_sram_reprogram_clock_sz)
57 .word . - sram_reprogram_clock 57 .word . - omap1_sram_reprogram_clock
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 2feb6870b735..93ee990618ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,9 +3,15 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o id.o io.o sram-fn.o memory.o control.o prcm.o clock.o mux.o \ 6obj-y := irq.o id.o io.o memory.o control.o prcm.o clock.o mux.o \
7 devices.o serial.o gpmc.o timer-gp.o 7 devices.o serial.o gpmc.o timer-gp.o
8 8
9obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
10
11# Functions loaded to SRAM
12obj-$(CONFIG_ARCH_OMAP2420) += sram242x.o
13obj-$(CONFIG_ARCH_OMAP2430) += sram243x.o
14
9# Power Management 15# Power Management
10obj-$(CONFIG_PM) += pm.o sleep.o 16obj-$(CONFIG_PM) += pm.o sleep.o
11 17
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index ab9fc57d25f1..15675bce8012 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -41,6 +41,24 @@
41 41
42#define MAX_CLOCK_ENABLE_WAIT 100000 42#define MAX_CLOCK_ENABLE_WAIT 100000
43 43
44/* DPLL rate rounding: minimum DPLL multiplier, divider values */
45#define DPLL_MIN_MULTIPLIER 1
46#define DPLL_MIN_DIVIDER 1
47
48/* Possible error results from _dpll_test_mult */
49#define DPLL_MULT_UNDERFLOW (1 << 0)
50
51/*
52 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
53 * The higher the scale factor, the greater the risk of arithmetic overflow,
54 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
55 * must be a power of DPLL_SCALE_BASE.
56 */
57#define DPLL_SCALE_FACTOR 64
58#define DPLL_SCALE_BASE 2
59#define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
60 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
61
44u8 cpu_mask; 62u8 cpu_mask;
45 63
46/*------------------------------------------------------------------------- 64/*-------------------------------------------------------------------------
@@ -95,7 +113,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
95{ 113{
96 long long dpll_clk; 114 long long dpll_clk;
97 u32 dpll_mult, dpll_div, dpll; 115 u32 dpll_mult, dpll_div, dpll;
98 const struct dpll_data *dd; 116 struct dpll_data *dd;
99 117
100 dd = clk->dpll_data; 118 dd = clk->dpll_data;
101 /* REVISIT: What do we return on error? */ 119 /* REVISIT: What do we return on error? */
@@ -603,7 +621,8 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
603 clk->rate = clk->parent->rate / new_div; 621 clk->rate = clk->parent->rate / new_div;
604 622
605 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) { 623 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
606 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL); 624 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
625 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
607 wmb(); 626 wmb();
608 } 627 }
609 628
@@ -723,6 +742,184 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
723 return 0; 742 return 0;
724} 743}
725 744
745/* DPLL rate rounding code */
746
747/**
748 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
749 * @clk: struct clk * of the DPLL
750 * @tolerance: maximum rate error tolerance
751 *
752 * Set the maximum DPLL rate error tolerance for the rate rounding
753 * algorithm. The rate tolerance is an attempt to balance DPLL power
754 * saving (the least divider value "n") vs. rate fidelity (the least
755 * difference between the desired DPLL target rate and the rounded
756 * rate out of the algorithm). So, increasing the tolerance is likely
757 * to decrease DPLL power consumption and increase DPLL rate error.
758 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
759 * DPLL; or 0 upon success.
760 */
761int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
762{
763 if (!clk || !clk->dpll_data)
764 return -EINVAL;
765
766 clk->dpll_data->rate_tolerance = tolerance;
767
768 return 0;
769}
770
771static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
772{
773 unsigned long long num;
774
775 num = (unsigned long long)parent_rate * m;
776 do_div(num, n);
777 return num;
778}
779
780/*
781 * _dpll_test_mult - test a DPLL multiplier value
782 * @m: pointer to the DPLL m (multiplier) value under test
783 * @n: current DPLL n (divider) value under test
784 * @new_rate: pointer to storage for the resulting rounded rate
785 * @target_rate: the desired DPLL rate
786 * @parent_rate: the DPLL's parent clock rate
787 *
788 * This code tests a DPLL multiplier value, ensuring that the
789 * resulting rate will not be higher than the target_rate, and that
790 * the multiplier value itself is valid for the DPLL. Initially, the
791 * integer pointed to by the m argument should be prescaled by
792 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
793 * a non-scaled m upon return. This non-scaled m will result in a
794 * new_rate as close as possible to target_rate (but not greater than
795 * target_rate) given the current (parent_rate, n, prescaled m)
796 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
797 * non-scaled m attempted to underflow, which can allow the calling
798 * function to bail out early; or 0 upon success.
799 */
800static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
801 unsigned long target_rate,
802 unsigned long parent_rate)
803{
804 int flags = 0, carry = 0;
805
806 /* Unscale m and round if necessary */
807 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
808 carry = 1;
809 *m = (*m / DPLL_SCALE_FACTOR) + carry;
810
811 /*
812 * The new rate must be <= the target rate to avoid programming
813 * a rate that is impossible for the hardware to handle
814 */
815 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
816 if (*new_rate > target_rate) {
817 (*m)--;
818 *new_rate = 0;
819 }
820
821 /* Guard against m underflow */
822 if (*m < DPLL_MIN_MULTIPLIER) {
823 *m = DPLL_MIN_MULTIPLIER;
824 *new_rate = 0;
825 flags = DPLL_MULT_UNDERFLOW;
826 }
827
828 if (*new_rate == 0)
829 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
830
831 return flags;
832}
833
834/**
835 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
836 * @clk: struct clk * for a DPLL
837 * @target_rate: desired DPLL clock rate
838 *
839 * Given a DPLL, a desired target rate, and a rate tolerance, round
840 * the target rate to a possible, programmable rate for this DPLL.
841 * Rate tolerance is assumed to be set by the caller before this
842 * function is called. Attempts to select the minimum possible n
843 * within the tolerance to reduce power consumption. Stores the
844 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
845 * will not need to call this (expensive) function again. Returns ~0
846 * if the target rate cannot be rounded, either because the rate is
847 * too low or because the rate tolerance is set too tightly; or the
848 * rounded rate upon success.
849 */
850long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
851{
852 int m, n, r, e, scaled_max_m;
853 unsigned long scaled_rt_rp, new_rate;
854 int min_e = -1, min_e_m = -1, min_e_n = -1;
855
856 if (!clk || !clk->dpll_data)
857 return ~0;
858
859 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
860 "%ld\n", clk->name, target_rate);
861
862 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
863 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
864
865 clk->dpll_data->last_rounded_rate = 0;
866
867 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
868
869 /* Compute the scaled DPLL multiplier, based on the divider */
870 m = scaled_rt_rp * n;
871
872 /*
873 * Since we're counting n down, a m overflow means we can
874 * can immediately skip to the next n
875 */
876 if (m > scaled_max_m)
877 continue;
878
879 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
880 clk->parent->rate);
881
882 e = target_rate - new_rate;
883 pr_debug("clock: n = %d: m = %d: rate error is %d "
884 "(new_rate = %ld)\n", n, m, e, new_rate);
885
886 if (min_e == -1 ||
887 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
888 min_e = e;
889 min_e_m = m;
890 min_e_n = n;
891
892 pr_debug("clock: found new least error %d\n", min_e);
893 }
894
895 /*
896 * Since we're counting n down, a m underflow means we
897 * can bail out completely (since as n decreases in
898 * the next iteration, there's no way that m can
899 * increase beyond the current m)
900 */
901 if (r & DPLL_MULT_UNDERFLOW)
902 break;
903 }
904
905 if (min_e < 0) {
906 pr_debug("clock: error: target rate or tolerance too low\n");
907 return ~0;
908 }
909
910 clk->dpll_data->last_rounded_m = min_e_m;
911 clk->dpll_data->last_rounded_n = min_e_n;
912 clk->dpll_data->last_rounded_rate =
913 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
914
915 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
916 min_e, min_e_m, min_e_n);
917 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
918 clk->dpll_data->last_rounded_rate, target_rate);
919
920 return clk->dpll_data->last_rounded_rate;
921}
922
726/*------------------------------------------------------------------------- 923/*-------------------------------------------------------------------------
727 * Omap2 clock reset and init functions 924 * Omap2 clock reset and init functions
728 *-------------------------------------------------------------------------*/ 925 *-------------------------------------------------------------------------*/
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index d5980a9e09a4..3cd37cb57c5a 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -18,11 +18,16 @@
18 18
19#include <asm/arch/clock.h> 19#include <asm/arch/clock.h>
20 20
21/* The maximum error between a target DPLL rate and the rounded rate in Hz */
22#define DEFAULT_DPLL_RATE_TOLERANCE 50000
23
21int omap2_clk_enable(struct clk *clk); 24int omap2_clk_enable(struct clk *clk);
22void omap2_clk_disable(struct clk *clk); 25void omap2_clk_disable(struct clk *clk);
23long omap2_clk_round_rate(struct clk *clk, unsigned long rate); 26long omap2_clk_round_rate(struct clk *clk, unsigned long rate);
24int omap2_clk_set_rate(struct clk *clk, unsigned long rate); 27int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
25int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); 28int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
29int omap2_dpll_rate_tolerance_set(struct clk *clk, unsigned int tolerance);
30long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
26 31
27#ifdef CONFIG_OMAP_RESET_CLOCKS 32#ifdef CONFIG_OMAP_RESET_CLOCKS
28void omap2_clk_disable_unused(struct clk *clk); 33void omap2_clk_disable_unused(struct clk *clk);
@@ -42,6 +47,7 @@ long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
42int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); 47int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
43u32 omap2_get_dpll_rate(struct clk *clk); 48u32 omap2_get_dpll_rate(struct clk *clk);
44int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); 49int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
50void omap2_clk_prepare_for_reboot(void);
45 51
46extern u8 cpu_mask; 52extern u8 cpu_mask;
47 53
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index ece32d8acba4..aa567876651d 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -154,7 +154,7 @@ static void omap2_clk_fixed_disable(struct clk *clk)
154 * Uses the current prcm set to tell if a rate is valid. 154 * Uses the current prcm set to tell if a rate is valid.
155 * You can go slower, but not faster within a given rate set. 155 * You can go slower, but not faster within a given rate set.
156 */ 156 */
157static u32 omap2_dpll_round_rate(unsigned long target_rate) 157long omap2_dpllcore_round_rate(unsigned long target_rate)
158{ 158{
159 u32 high, low, core_clk_src; 159 u32 high, low, core_clk_src;
160 160
@@ -183,14 +183,14 @@ static u32 omap2_dpll_round_rate(unsigned long target_rate)
183 183
184} 184}
185 185
186static void omap2_dpll_recalc(struct clk *clk) 186static void omap2_dpllcore_recalc(struct clk *clk)
187{ 187{
188 clk->rate = omap2_get_dpll_rate_24xx(clk); 188 clk->rate = omap2_get_dpll_rate_24xx(clk);
189 189
190 propagate_rate(clk); 190 propagate_rate(clk);
191} 191}
192 192
193static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate) 193static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate)
194{ 194{
195 u32 cur_rate, low, mult, div, valid_rate, done_rate; 195 u32 cur_rate, low, mult, div, valid_rate, done_rate;
196 u32 bypass = 0; 196 u32 bypass = 0;
@@ -209,7 +209,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
209 } else if ((rate == (cur_rate * 2)) && (mult == 1)) { 209 } else if ((rate == (cur_rate * 2)) && (mult == 1)) {
210 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1); 210 omap2_reprogram_sdrc(CORE_CLK_SRC_DPLL_X2, 1);
211 } else if (rate != cur_rate) { 211 } else if (rate != cur_rate) {
212 valid_rate = omap2_dpll_round_rate(rate); 212 valid_rate = omap2_dpllcore_round_rate(rate);
213 if (valid_rate != rate) 213 if (valid_rate != rate)
214 goto dpll_exit; 214 goto dpll_exit;
215 215
@@ -256,7 +256,7 @@ static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate)
256 omap2_init_memory_params(omap2_dll_force_needed()); 256 omap2_init_memory_params(omap2_dll_force_needed());
257 omap2_reprogram_sdrc(done_rate, 0); 257 omap2_reprogram_sdrc(done_rate, 0);
258 } 258 }
259 omap2_dpll_recalc(&dpll_ck); 259 omap2_dpllcore_recalc(&dpll_ck);
260 ret = 0; 260 ret = 0;
261 261
262dpll_exit: 262dpll_exit:
@@ -383,7 +383,7 @@ static int omap2_select_table_rate(struct clk *clk, unsigned long rate)
383 383
384 local_irq_restore(flags); 384 local_irq_restore(flags);
385 } 385 }
386 omap2_dpll_recalc(&dpll_ck); 386 omap2_dpllcore_recalc(&dpll_ck);
387 387
388 return 0; 388 return 0;
389} 389}
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h
index 88081ed13f96..be4e25554e05 100644
--- a/arch/arm/mach-omap2/clock24xx.h
+++ b/arch/arm/mach-omap2/clock24xx.h
@@ -30,12 +30,12 @@ static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
30static void omap2_sys_clk_recalc(struct clk *clk); 30static void omap2_sys_clk_recalc(struct clk *clk);
31static void omap2_osc_clk_recalc(struct clk *clk); 31static void omap2_osc_clk_recalc(struct clk *clk);
32static void omap2_sys_clk_recalc(struct clk *clk); 32static void omap2_sys_clk_recalc(struct clk *clk);
33static void omap2_dpll_recalc(struct clk *clk); 33static void omap2_dpllcore_recalc(struct clk *clk);
34static int omap2_clk_fixed_enable(struct clk *clk); 34static int omap2_clk_fixed_enable(struct clk *clk);
35static void omap2_clk_fixed_disable(struct clk *clk); 35static void omap2_clk_fixed_disable(struct clk *clk);
36static int omap2_enable_osc_ck(struct clk *clk); 36static int omap2_enable_osc_ck(struct clk *clk);
37static void omap2_disable_osc_ck(struct clk *clk); 37static void omap2_disable_osc_ck(struct clk *clk);
38static int omap2_reprogram_dpll(struct clk *clk, unsigned long rate); 38static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
39 39
40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated. 40/* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP 41 * xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,CM_CLKSEL_DSP
@@ -665,20 +665,27 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */
665 * deal with this 665 * deal with this
666 */ 666 */
667 667
668static const struct dpll_data dpll_dd = { 668static struct dpll_data dpll_dd = {
669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 669 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
670 .mult_mask = OMAP24XX_DPLL_MULT_MASK, 670 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
671 .div1_mask = OMAP24XX_DPLL_DIV_MASK, 671 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
672 .max_multiplier = 1024,
673 .max_divider = 16,
674 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
672}; 675};
673 676
677/*
678 * XXX Cannot add round_rate here yet, as this is still a composite clock,
679 * not just a DPLL
680 */
674static struct clk dpll_ck = { 681static struct clk dpll_ck = {
675 .name = "dpll_ck", 682 .name = "dpll_ck",
676 .parent = &sys_ck, /* Can be func_32k also */ 683 .parent = &sys_ck, /* Can be func_32k also */
677 .dpll_data = &dpll_dd, 684 .dpll_data = &dpll_dd,
678 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | 685 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X |
679 RATE_PROPAGATES | ALWAYS_ENABLED, 686 RATE_PROPAGATES | ALWAYS_ENABLED,
680 .recalc = &omap2_dpll_recalc, 687 .recalc = &omap2_dpllcore_recalc,
681 .set_rate = &omap2_reprogram_dpll, 688 .set_rate = &omap2_reprogram_dpllcore,
682}; 689};
683 690
684static struct clk apll96_ck = { 691static struct clk apll96_ck = {
@@ -1747,7 +1754,8 @@ static struct clk gpt12_fck = {
1747}; 1754};
1748 1755
1749static struct clk mcbsp1_ick = { 1756static struct clk mcbsp1_ick = {
1750 .name = "mcbsp1_ick", 1757 .name = "mcbsp_ick",
1758 .id = 1,
1751 .parent = &l4_ck, 1759 .parent = &l4_ck,
1752 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1753 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1761 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1756,7 +1764,8 @@ static struct clk mcbsp1_ick = {
1756}; 1764};
1757 1765
1758static struct clk mcbsp1_fck = { 1766static struct clk mcbsp1_fck = {
1759 .name = "mcbsp1_fck", 1767 .name = "mcbsp_fck",
1768 .id = 1,
1760 .parent = &func_96m_ck, 1769 .parent = &func_96m_ck,
1761 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1765,7 +1774,8 @@ static struct clk mcbsp1_fck = {
1765}; 1774};
1766 1775
1767static struct clk mcbsp2_ick = { 1776static struct clk mcbsp2_ick = {
1768 .name = "mcbsp2_ick", 1777 .name = "mcbsp_ick",
1778 .id = 2,
1769 .parent = &l4_ck, 1779 .parent = &l4_ck,
1770 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1780 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1771 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1781 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
@@ -1774,7 +1784,8 @@ static struct clk mcbsp2_ick = {
1774}; 1784};
1775 1785
1776static struct clk mcbsp2_fck = { 1786static struct clk mcbsp2_fck = {
1777 .name = "mcbsp2_fck", 1787 .name = "mcbsp_fck",
1788 .id = 2,
1778 .parent = &func_96m_ck, 1789 .parent = &func_96m_ck,
1779 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, 1790 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
1780 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1791 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
@@ -1783,7 +1794,8 @@ static struct clk mcbsp2_fck = {
1783}; 1794};
1784 1795
1785static struct clk mcbsp3_ick = { 1796static struct clk mcbsp3_ick = {
1786 .name = "mcbsp3_ick", 1797 .name = "mcbsp_ick",
1798 .id = 3,
1787 .parent = &l4_ck, 1799 .parent = &l4_ck,
1788 .flags = CLOCK_IN_OMAP243X, 1800 .flags = CLOCK_IN_OMAP243X,
1789 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1801 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1792,7 +1804,8 @@ static struct clk mcbsp3_ick = {
1792}; 1804};
1793 1805
1794static struct clk mcbsp3_fck = { 1806static struct clk mcbsp3_fck = {
1795 .name = "mcbsp3_fck", 1807 .name = "mcbsp_fck",
1808 .id = 3,
1796 .parent = &func_96m_ck, 1809 .parent = &func_96m_ck,
1797 .flags = CLOCK_IN_OMAP243X, 1810 .flags = CLOCK_IN_OMAP243X,
1798 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1811 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1801,7 +1814,8 @@ static struct clk mcbsp3_fck = {
1801}; 1814};
1802 1815
1803static struct clk mcbsp4_ick = { 1816static struct clk mcbsp4_ick = {
1804 .name = "mcbsp4_ick", 1817 .name = "mcbsp_ick",
1818 .id = 4,
1805 .parent = &l4_ck, 1819 .parent = &l4_ck,
1806 .flags = CLOCK_IN_OMAP243X, 1820 .flags = CLOCK_IN_OMAP243X,
1807 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1821 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1810,7 +1824,8 @@ static struct clk mcbsp4_ick = {
1810}; 1824};
1811 1825
1812static struct clk mcbsp4_fck = { 1826static struct clk mcbsp4_fck = {
1813 .name = "mcbsp4_fck", 1827 .name = "mcbsp_fck",
1828 .id = 4,
1814 .parent = &func_96m_ck, 1829 .parent = &func_96m_ck,
1815 .flags = CLOCK_IN_OMAP243X, 1830 .flags = CLOCK_IN_OMAP243X,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1831 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
@@ -1819,7 +1834,8 @@ static struct clk mcbsp4_fck = {
1819}; 1834};
1820 1835
1821static struct clk mcbsp5_ick = { 1836static struct clk mcbsp5_ick = {
1822 .name = "mcbsp5_ick", 1837 .name = "mcbsp_ick",
1838 .id = 5,
1823 .parent = &l4_ck, 1839 .parent = &l4_ck,
1824 .flags = CLOCK_IN_OMAP243X, 1840 .flags = CLOCK_IN_OMAP243X,
1825 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), 1841 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
@@ -1828,7 +1844,8 @@ static struct clk mcbsp5_ick = {
1828}; 1844};
1829 1845
1830static struct clk mcbsp5_fck = { 1846static struct clk mcbsp5_fck = {
1831 .name = "mcbsp5_fck", 1847 .name = "mcbsp_fck",
1848 .id = 5,
1832 .parent = &func_96m_ck, 1849 .parent = &func_96m_ck,
1833 .flags = CLOCK_IN_OMAP243X, 1850 .flags = CLOCK_IN_OMAP243X,
1834 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), 1851 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index b42bdd6079a5..4263099b1ad3 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -1,10 +1,11 @@
1/* 1/*
2 * OMAP3-specific clock framework functions 2 * OMAP3-specific clock framework functions
3 * 3 *
4 * Copyright (C) 2007 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007 Nokia Corporation 5 * Copyright (C) 2007-2008 Nokia Corporation
6 * 6 *
7 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * Testing and integration fixes by Jouni Högander
8 * 9 *
9 * Parts of this code are based on code written by 10 * Parts of this code are based on code written by
10 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu 11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
@@ -23,6 +24,7 @@
23#include <linux/delay.h> 24#include <linux/delay.h>
24#include <linux/clk.h> 25#include <linux/clk.h>
25#include <linux/io.h> 26#include <linux/io.h>
27#include <linux/limits.h>
26 28
27#include <asm/arch/clock.h> 29#include <asm/arch/clock.h>
28#include <asm/arch/sram.h> 30#include <asm/arch/sram.h>
@@ -37,8 +39,11 @@
37#include "cm.h" 39#include "cm.h"
38#include "cm-regbits-34xx.h" 40#include "cm-regbits-34xx.h"
39 41
40/* CM_CLKEN_PLL*.EN* bit values */ 42/* CM_AUTOIDLE_PLL*.AUTO_* bit values */
41#define DPLL_LOCKED 0x7 43#define DPLL_AUTOIDLE_DISABLE 0x0
44#define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1
45
46#define MAX_DPLL_WAIT_TRIES 1000000
42 47
43/** 48/**
44 * omap3_dpll_recalc - recalculate DPLL rate 49 * omap3_dpll_recalc - recalculate DPLL rate
@@ -53,6 +58,290 @@ static void omap3_dpll_recalc(struct clk *clk)
53 propagate_rate(clk); 58 propagate_rate(clk);
54} 59}
55 60
61/* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */
62static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits)
63{
64 const struct dpll_data *dd;
65
66 dd = clk->dpll_data;
67
68 cm_rmw_reg_bits(dd->enable_mask, clken_bits << __ffs(dd->enable_mask),
69 dd->control_reg);
70}
71
72/* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */
73static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
74{
75 const struct dpll_data *dd;
76 int i = 0;
77 int ret = -EINVAL;
78 u32 idlest_mask;
79
80 dd = clk->dpll_data;
81
82 state <<= dd->idlest_bit;
83 idlest_mask = 1 << dd->idlest_bit;
84
85 while (((cm_read_reg(dd->idlest_reg) & idlest_mask) != state) &&
86 i < MAX_DPLL_WAIT_TRIES) {
87 i++;
88 udelay(1);
89 }
90
91 if (i == MAX_DPLL_WAIT_TRIES) {
92 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
93 clk->name, (state) ? "locked" : "bypassed");
94 } else {
95 pr_debug("clock: %s transition to '%s' in %d loops\n",
96 clk->name, (state) ? "locked" : "bypassed", i);
97
98 ret = 0;
99 }
100
101 return ret;
102}
103
104/* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */
105
106/*
107 * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness
108 * @clk: pointer to a DPLL struct clk
109 *
110 * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report
111 * readiness before returning. Will save and restore the DPLL's
112 * autoidle state across the enable, per the CDP code. If the DPLL
113 * locked successfully, return 0; if the DPLL did not lock in the time
114 * allotted, or DPLL3 was passed in, return -EINVAL.
115 */
116static int _omap3_noncore_dpll_lock(struct clk *clk)
117{
118 u8 ai;
119 int r;
120
121 if (clk == &dpll3_ck)
122 return -EINVAL;
123
124 pr_debug("clock: locking DPLL %s\n", clk->name);
125
126 ai = omap3_dpll_autoidle_read(clk);
127
128 _omap3_dpll_write_clken(clk, DPLL_LOCKED);
129
130 if (ai) {
131 /*
132 * If no downstream clocks are enabled, CM_IDLEST bit
133 * may never become active, so don't wait for DPLL to lock.
134 */
135 r = 0;
136 omap3_dpll_allow_idle(clk);
137 } else {
138 r = _omap3_wait_dpll_status(clk, 1);
139 omap3_dpll_deny_idle(clk);
140 };
141
142 return r;
143}
144
145/*
146 * omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness
147 * @clk: pointer to a DPLL struct clk
148 *
149 * Instructs a non-CORE DPLL to enter low-power bypass mode. In
150 * bypass mode, the DPLL's rate is set equal to its parent clock's
151 * rate. Waits for the DPLL to report readiness before returning.
152 * Will save and restore the DPLL's autoidle state across the enable,
153 * per the CDP code. If the DPLL entered bypass mode successfully,
154 * return 0; if the DPLL did not enter bypass in the time allotted, or
155 * DPLL3 was passed in, or the DPLL does not support low-power bypass,
156 * return -EINVAL.
157 */
158static int _omap3_noncore_dpll_bypass(struct clk *clk)
159{
160 int r;
161 u8 ai;
162
163 if (clk == &dpll3_ck)
164 return -EINVAL;
165
166 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS)))
167 return -EINVAL;
168
169 pr_debug("clock: configuring DPLL %s for low-power bypass\n",
170 clk->name);
171
172 ai = omap3_dpll_autoidle_read(clk);
173
174 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS);
175
176 r = _omap3_wait_dpll_status(clk, 0);
177
178 if (ai)
179 omap3_dpll_allow_idle(clk);
180 else
181 omap3_dpll_deny_idle(clk);
182
183 return r;
184}
185
186/*
187 * _omap3_noncore_dpll_stop - instruct a DPLL to stop
188 * @clk: pointer to a DPLL struct clk
189 *
190 * Instructs a non-CORE DPLL to enter low-power stop. Will save and
191 * restore the DPLL's autoidle state across the stop, per the CDP
192 * code. If DPLL3 was passed in, or the DPLL does not support
193 * low-power stop, return -EINVAL; otherwise, return 0.
194 */
195static int _omap3_noncore_dpll_stop(struct clk *clk)
196{
197 u8 ai;
198
199 if (clk == &dpll3_ck)
200 return -EINVAL;
201
202 if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
203 return -EINVAL;
204
205 pr_debug("clock: stopping DPLL %s\n", clk->name);
206
207 ai = omap3_dpll_autoidle_read(clk);
208
209 _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP);
210
211 if (ai)
212 omap3_dpll_allow_idle(clk);
213 else
214 omap3_dpll_deny_idle(clk);
215
216 return 0;
217}
218
219/**
220 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
221 * @clk: pointer to a DPLL struct clk
222 *
223 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
224 * The choice of modes depends on the DPLL's programmed rate: if it is
225 * the same as the DPLL's parent clock, it will enter bypass;
226 * otherwise, it will enter lock. This code will wait for the DPLL to
227 * indicate readiness before returning, unless the DPLL takes too long
228 * to enter the target state. Intended to be used as the struct clk's
229 * enable function. If DPLL3 was passed in, or the DPLL does not
230 * support low-power stop, or if the DPLL took too long to enter
231 * bypass or lock, return -EINVAL; otherwise, return 0.
232 */
233static int omap3_noncore_dpll_enable(struct clk *clk)
234{
235 int r;
236
237 if (clk == &dpll3_ck)
238 return -EINVAL;
239
240 if (clk->parent->rate == clk_get_rate(clk))
241 r = _omap3_noncore_dpll_bypass(clk);
242 else
243 r = _omap3_noncore_dpll_lock(clk);
244
245 return r;
246}
247
248/**
249 * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode
250 * @clk: pointer to a DPLL struct clk
251 *
252 * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock.
253 * The choice of modes depends on the DPLL's programmed rate: if it is
254 * the same as the DPLL's parent clock, it will enter bypass;
255 * otherwise, it will enter lock. This code will wait for the DPLL to
256 * indicate readiness before returning, unless the DPLL takes too long
257 * to enter the target state. Intended to be used as the struct clk's
258 * enable function. If DPLL3 was passed in, or the DPLL does not
259 * support low-power stop, or if the DPLL took too long to enter
260 * bypass or lock, return -EINVAL; otherwise, return 0.
261 */
262static void omap3_noncore_dpll_disable(struct clk *clk)
263{
264 if (clk == &dpll3_ck)
265 return;
266
267 _omap3_noncore_dpll_stop(clk);
268}
269
270/**
271 * omap3_dpll_autoidle_read - read a DPLL's autoidle bits
272 * @clk: struct clk * of the DPLL to read
273 *
274 * Return the DPLL's autoidle bits, shifted down to bit 0. Returns
275 * -EINVAL if passed a null pointer or if the struct clk does not
276 * appear to refer to a DPLL.
277 */
278static u32 omap3_dpll_autoidle_read(struct clk *clk)
279{
280 const struct dpll_data *dd;
281 u32 v;
282
283 if (!clk || !clk->dpll_data)
284 return -EINVAL;
285
286 dd = clk->dpll_data;
287
288 v = cm_read_reg(dd->autoidle_reg);
289 v &= dd->autoidle_mask;
290 v >>= __ffs(dd->autoidle_mask);
291
292 return v;
293}
294
295/**
296 * omap3_dpll_allow_idle - enable DPLL autoidle bits
297 * @clk: struct clk * of the DPLL to operate on
298 *
299 * Enable DPLL automatic idle control. This automatic idle mode
300 * switching takes effect only when the DPLL is locked, at least on
301 * OMAP3430. The DPLL will enter low-power stop when its downstream
302 * clocks are gated. No return value.
303 */
304static void omap3_dpll_allow_idle(struct clk *clk)
305{
306 const struct dpll_data *dd;
307
308 if (!clk || !clk->dpll_data)
309 return;
310
311 dd = clk->dpll_data;
312
313 /*
314 * REVISIT: CORE DPLL can optionally enter low-power bypass
315 * by writing 0x5 instead of 0x1. Add some mechanism to
316 * optionally enter this mode.
317 */
318 cm_rmw_reg_bits(dd->autoidle_mask,
319 DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask),
320 dd->autoidle_reg);
321}
322
323/**
324 * omap3_dpll_deny_idle - prevent DPLL from automatically idling
325 * @clk: struct clk * of the DPLL to operate on
326 *
327 * Disable DPLL automatic idle control. No return value.
328 */
329static void omap3_dpll_deny_idle(struct clk *clk)
330{
331 const struct dpll_data *dd;
332
333 if (!clk || !clk->dpll_data)
334 return;
335
336 dd = clk->dpll_data;
337
338 cm_rmw_reg_bits(dd->autoidle_mask,
339 DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask),
340 dd->autoidle_reg);
341}
342
343/* Clock control for DPLL outputs */
344
56/** 345/**
57 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate 346 * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate
58 * @clk: DPLL output struct clk 347 * @clk: DPLL output struct clk
@@ -89,6 +378,8 @@ static void omap3_clkoutx2_recalc(struct clk *clk)
89 propagate_rate(clk); 378 propagate_rate(clk);
90} 379}
91 380
381/* Common clock code */
382
92/* 383/*
93 * As it is structured now, this will prevent an OMAP2/3 multiboot 384 * As it is structured now, this will prevent an OMAP2/3 multiboot
94 * kernel from compiling. This will need further attention. 385 * kernel from compiling. This will need further attention.
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index c9c5972a2e25..05757eb032bc 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -1,14 +1,19 @@
1/* 1/*
2 * OMAP3 clock framework 2 * OMAP3 clock framework
3 * 3 *
4 * Virtual clocks are introduced as a convenient tools.
5 * They are sources for other clocks and not supposed
6 * to be requested from drivers directly.
7 *
8 * Copyright (C) 2007-2008 Texas Instruments, Inc. 4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
9 * Copyright (C) 2007-2008 Nokia Corporation 5 * Copyright (C) 2007-2008 Nokia Corporation
10 * 6 *
11 * Written by Paul Walmsley 7 * Written by Paul Walmsley
8 * With many device clock fixes by Kevin Hilman and Jouni Högander
9 * DPLL bypass clock support added by Roman Tereshonkov
10 *
11 */
12
13/*
14 * Virtual clocks are introduced as convenient tools.
15 * They are sources for other clocks and not supposed
16 * to be requested from drivers directly.
12 */ 17 */
13 18
14#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H 19#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H
@@ -24,6 +29,15 @@
24 29
25static void omap3_dpll_recalc(struct clk *clk); 30static void omap3_dpll_recalc(struct clk *clk);
26static void omap3_clkoutx2_recalc(struct clk *clk); 31static void omap3_clkoutx2_recalc(struct clk *clk);
32static void omap3_dpll_allow_idle(struct clk *clk);
33static void omap3_dpll_deny_idle(struct clk *clk);
34static u32 omap3_dpll_autoidle_read(struct clk *clk);
35static int omap3_noncore_dpll_enable(struct clk *clk);
36static void omap3_noncore_dpll_disable(struct clk *clk);
37
38/* Maximum DPLL multiplier, divider values for OMAP3 */
39#define OMAP3_MAX_DPLL_MULT 2048
40#define OMAP3_MAX_DPLL_DIV 128
27 41
28/* 42/*
29 * DPLL1 supplies clock to the MPU. 43 * DPLL1 supplies clock to the MPU.
@@ -33,6 +47,11 @@ static void omap3_clkoutx2_recalc(struct clk *clk);
33 * DPLL5 supplies other peripheral clocks (USBHOST, USIM). 47 * DPLL5 supplies other peripheral clocks (USBHOST, USIM).
34 */ 48 */
35 49
50/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
51#define DPLL_LOW_POWER_STOP 0x1
52#define DPLL_LOW_POWER_BYPASS 0x5
53#define DPLL_LOCKED 0x7
54
36/* PRM CLOCKS */ 55/* PRM CLOCKS */
37 56
38/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ 57/* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */
@@ -240,15 +259,23 @@ static const struct clksel_rate div16_dpll_rates[] = {
240/* DPLL1 */ 259/* DPLL1 */
241/* MPU clock source */ 260/* MPU clock source */
242/* Type: DPLL */ 261/* Type: DPLL */
243static const struct dpll_data dpll1_dd = { 262static struct dpll_data dpll1_dd = {
244 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), 263 .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL),
245 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, 264 .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK,
246 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, 265 .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK,
247 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), 266 .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL),
248 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, 267 .enable_mask = OMAP3430_EN_MPU_DPLL_MASK,
268 .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
249 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, 269 .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT,
250 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, 270 .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT,
251 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, 271 .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT,
272 .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL),
273 .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK,
274 .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL),
275 .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT,
276 .max_multiplier = OMAP3_MAX_DPLL_MULT,
277 .max_divider = OMAP3_MAX_DPLL_DIV,
278 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
252}; 279};
253 280
254static struct clk dpll1_ck = { 281static struct clk dpll1_ck = {
@@ -256,6 +283,7 @@ static struct clk dpll1_ck = {
256 .parent = &sys_ck, 283 .parent = &sys_ck,
257 .dpll_data = &dpll1_dd, 284 .dpll_data = &dpll1_dd,
258 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 285 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
286 .round_rate = &omap2_dpll_round_rate,
259 .recalc = &omap3_dpll_recalc, 287 .recalc = &omap3_dpll_recalc,
260}; 288};
261 289
@@ -297,22 +325,34 @@ static struct clk dpll1_x2m2_ck = {
297/* IVA2 clock source */ 325/* IVA2 clock source */
298/* Type: DPLL */ 326/* Type: DPLL */
299 327
300static const struct dpll_data dpll2_dd = { 328static struct dpll_data dpll2_dd = {
301 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), 329 .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL),
302 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, 330 .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK,
303 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, 331 .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK,
304 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), 332 .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL),
305 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, 333 .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK,
334 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) |
335 (1 << DPLL_LOW_POWER_BYPASS),
306 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, 336 .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT,
307 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, 337 .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT,
308 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, 338 .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT,
339 .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL),
340 .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK,
341 .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL),
342 .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT,
343 .max_multiplier = OMAP3_MAX_DPLL_MULT,
344 .max_divider = OMAP3_MAX_DPLL_DIV,
345 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
309}; 346};
310 347
311static struct clk dpll2_ck = { 348static struct clk dpll2_ck = {
312 .name = "dpll2_ck", 349 .name = "dpll2_ck",
313 .parent = &sys_ck, 350 .parent = &sys_ck,
314 .dpll_data = &dpll2_dd, 351 .dpll_data = &dpll2_dd,
315 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 352 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
353 .enable = &omap3_noncore_dpll_enable,
354 .disable = &omap3_noncore_dpll_disable,
355 .round_rate = &omap2_dpll_round_rate,
316 .recalc = &omap3_dpll_recalc, 356 .recalc = &omap3_dpll_recalc,
317}; 357};
318 358
@@ -338,10 +378,12 @@ static struct clk dpll2_m2_ck = {
338 .recalc = &omap2_clksel_recalc, 378 .recalc = &omap2_clksel_recalc,
339}; 379};
340 380
341/* DPLL3 */ 381/*
342/* Source clock for all interfaces and for some device fclks */ 382 * DPLL3
343/* Type: DPLL */ 383 * Source clock for all interfaces and for some device fclks
344static const struct dpll_data dpll3_dd = { 384 * REVISIT: Also supports fast relock bypass - not included below
385 */
386static struct dpll_data dpll3_dd = {
345 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), 387 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
346 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, 388 .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK,
347 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, 389 .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK,
@@ -350,6 +392,11 @@ static const struct dpll_data dpll3_dd = {
350 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, 392 .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT,
351 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, 393 .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT,
352 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, 394 .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT,
395 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
396 .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK,
397 .max_multiplier = OMAP3_MAX_DPLL_MULT,
398 .max_divider = OMAP3_MAX_DPLL_DIV,
399 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
353}; 400};
354 401
355static struct clk dpll3_ck = { 402static struct clk dpll3_ck = {
@@ -357,6 +404,7 @@ static struct clk dpll3_ck = {
357 .parent = &sys_ck, 404 .parent = &sys_ck,
358 .dpll_data = &dpll3_dd, 405 .dpll_data = &dpll3_dd,
359 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 406 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED,
407 .round_rate = &omap2_dpll_round_rate,
360 .recalc = &omap3_dpll_recalc, 408 .recalc = &omap3_dpll_recalc,
361}; 409};
362 410
@@ -439,7 +487,7 @@ static struct clk core_ck = {
439 .name = "core_ck", 487 .name = "core_ck",
440 .init = &omap2_init_clksel_parent, 488 .init = &omap2_init_clksel_parent,
441 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 489 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
442 .clksel_mask = OMAP3430_ST_CORE_CLK, 490 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
443 .clksel = core_ck_clksel, 491 .clksel = core_ck_clksel,
444 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 492 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
445 PARENT_CONTROLS_CLOCK, 493 PARENT_CONTROLS_CLOCK,
@@ -456,7 +504,7 @@ static struct clk dpll3_m2x2_ck = {
456 .name = "dpll3_m2x2_ck", 504 .name = "dpll3_m2x2_ck",
457 .init = &omap2_init_clksel_parent, 505 .init = &omap2_init_clksel_parent,
458 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 506 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
459 .clksel_mask = OMAP3430_ST_CORE_CLK, 507 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
460 .clksel = dpll3_m2x2_ck_clksel, 508 .clksel = dpll3_m2x2_ck_clksel,
461 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 509 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
462 PARENT_CONTROLS_CLOCK, 510 PARENT_CONTROLS_CLOCK,
@@ -503,7 +551,7 @@ static struct clk emu_core_alwon_ck = {
503 .parent = &dpll3_m3x2_ck, 551 .parent = &dpll3_m3x2_ck,
504 .init = &omap2_init_clksel_parent, 552 .init = &omap2_init_clksel_parent,
505 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 553 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
506 .clksel_mask = OMAP3430_ST_CORE_CLK, 554 .clksel_mask = OMAP3430_ST_CORE_CLK_MASK,
507 .clksel = emu_core_alwon_ck_clksel, 555 .clksel = emu_core_alwon_ck_clksel,
508 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 556 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
509 PARENT_CONTROLS_CLOCK, 557 PARENT_CONTROLS_CLOCK,
@@ -513,22 +561,33 @@ static struct clk emu_core_alwon_ck = {
513/* DPLL4 */ 561/* DPLL4 */
514/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ 562/* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */
515/* Type: DPLL */ 563/* Type: DPLL */
516static const struct dpll_data dpll4_dd = { 564static struct dpll_data dpll4_dd = {
517 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), 565 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2),
518 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, 566 .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK,
519 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, 567 .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK,
520 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), 568 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
521 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, 569 .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK,
570 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
522 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, 571 .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT,
523 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, 572 .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT,
524 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, 573 .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT,
574 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE),
575 .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK,
576 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
577 .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT,
578 .max_multiplier = OMAP3_MAX_DPLL_MULT,
579 .max_divider = OMAP3_MAX_DPLL_DIV,
580 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
525}; 581};
526 582
527static struct clk dpll4_ck = { 583static struct clk dpll4_ck = {
528 .name = "dpll4_ck", 584 .name = "dpll4_ck",
529 .parent = &sys_ck, 585 .parent = &sys_ck,
530 .dpll_data = &dpll4_dd, 586 .dpll_data = &dpll4_dd,
531 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, 587 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES,
588 .enable = &omap3_noncore_dpll_enable,
589 .disable = &omap3_noncore_dpll_disable,
590 .round_rate = &omap2_dpll_round_rate,
532 .recalc = &omap3_dpll_recalc, 591 .recalc = &omap3_dpll_recalc,
533}; 592};
534 593
@@ -584,7 +643,7 @@ static struct clk omap_96m_alwon_fck = {
584 .parent = &dpll4_m2x2_ck, 643 .parent = &dpll4_m2x2_ck,
585 .init = &omap2_init_clksel_parent, 644 .init = &omap2_init_clksel_parent,
586 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 645 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
587 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 646 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
588 .clksel = omap_96m_alwon_fck_clksel, 647 .clksel = omap_96m_alwon_fck_clksel,
589 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 648 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
590 PARENT_CONTROLS_CLOCK, 649 PARENT_CONTROLS_CLOCK,
@@ -610,7 +669,7 @@ static struct clk cm_96m_fck = {
610 .parent = &dpll4_m2x2_ck, 669 .parent = &dpll4_m2x2_ck,
611 .init = &omap2_init_clksel_parent, 670 .init = &omap2_init_clksel_parent,
612 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 671 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
613 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 672 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
614 .clksel = cm_96m_fck_clksel, 673 .clksel = cm_96m_fck_clksel,
615 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 674 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
616 PARENT_CONTROLS_CLOCK, 675 PARENT_CONTROLS_CLOCK,
@@ -652,7 +711,7 @@ static struct clk virt_omap_54m_fck = {
652 .parent = &dpll4_m3x2_ck, 711 .parent = &dpll4_m3x2_ck,
653 .init = &omap2_init_clksel_parent, 712 .init = &omap2_init_clksel_parent,
654 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 713 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
655 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 714 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
656 .clksel = virt_omap_54m_fck_clksel, 715 .clksel = virt_omap_54m_fck_clksel,
657 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | 716 .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES |
658 PARENT_CONTROLS_CLOCK, 717 PARENT_CONTROLS_CLOCK,
@@ -804,23 +863,33 @@ static struct clk emu_per_alwon_ck = {
804/* Supplies 120MHz clock, USIM source clock */ 863/* Supplies 120MHz clock, USIM source clock */
805/* Type: DPLL */ 864/* Type: DPLL */
806/* 3430ES2 only */ 865/* 3430ES2 only */
807static const struct dpll_data dpll5_dd = { 866static struct dpll_data dpll5_dd = {
808 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), 867 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4),
809 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, 868 .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK,
810 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, 869 .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK,
811 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), 870 .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2),
812 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, 871 .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK,
872 .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED),
813 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, 873 .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT,
814 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, 874 .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT,
815 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, 875 .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT,
876 .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL),
877 .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK,
878 .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2),
879 .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT,
880 .max_multiplier = OMAP3_MAX_DPLL_MULT,
881 .max_divider = OMAP3_MAX_DPLL_DIV,
882 .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE
816}; 883};
817 884
818static struct clk dpll5_ck = { 885static struct clk dpll5_ck = {
819 .name = "dpll5_ck", 886 .name = "dpll5_ck",
820 .parent = &sys_ck, 887 .parent = &sys_ck,
821 .dpll_data = &dpll5_dd, 888 .dpll_data = &dpll5_dd,
822 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | 889 .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES,
823 ALWAYS_ENABLED, 890 .enable = &omap3_noncore_dpll_enable,
891 .disable = &omap3_noncore_dpll_disable,
892 .round_rate = &omap2_dpll_round_rate,
824 .recalc = &omap3_dpll_recalc, 893 .recalc = &omap3_dpll_recalc,
825}; 894};
826 895
@@ -1365,7 +1434,8 @@ static const struct clksel mcbsp_15_clksel[] = {
1365}; 1434};
1366 1435
1367static struct clk mcbsp5_fck = { 1436static struct clk mcbsp5_fck = {
1368 .name = "mcbsp5_fck", 1437 .name = "mcbsp_fck",
1438 .id = 5,
1369 .init = &omap2_init_clksel_parent, 1439 .init = &omap2_init_clksel_parent,
1370 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1440 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1371 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1441 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1377,7 +1447,8 @@ static struct clk mcbsp5_fck = {
1377}; 1447};
1378 1448
1379static struct clk mcbsp1_fck = { 1449static struct clk mcbsp1_fck = {
1380 .name = "mcbsp1_fck", 1450 .name = "mcbsp_fck",
1451 .id = 1,
1381 .init = &omap2_init_clksel_parent, 1452 .init = &omap2_init_clksel_parent,
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), 1453 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1383 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1454 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1789,7 +1860,8 @@ static struct clk gpt10_ick = {
1789}; 1860};
1790 1861
1791static struct clk mcbsp5_ick = { 1862static struct clk mcbsp5_ick = {
1792 .name = "mcbsp5_ick", 1863 .name = "mcbsp_ick",
1864 .id = 5,
1793 .parent = &core_l4_ick, 1865 .parent = &core_l4_ick,
1794 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1866 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1795 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, 1867 .enable_bit = OMAP3430_EN_MCBSP5_SHIFT,
@@ -1798,7 +1870,8 @@ static struct clk mcbsp5_ick = {
1798}; 1870};
1799 1871
1800static struct clk mcbsp1_ick = { 1872static struct clk mcbsp1_ick = {
1801 .name = "mcbsp1_ick", 1873 .name = "mcbsp_ick",
1874 .id = 1,
1802 .parent = &core_l4_ick, 1875 .parent = &core_l4_ick,
1803 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), 1876 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1804 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, 1877 .enable_bit = OMAP3430_EN_MCBSP1_SHIFT,
@@ -1935,7 +2008,7 @@ static struct clk dss1_alwon_fck = {
1935 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), 2008 .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN),
1936 .enable_bit = OMAP3430_EN_DSS1_SHIFT, 2009 .enable_bit = OMAP3430_EN_DSS1_SHIFT,
1937 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2010 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1938 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 2011 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
1939 .clksel = dss1_alwon_fck_clksel, 2012 .clksel = dss1_alwon_fck_clksel,
1940 .flags = CLOCK_IN_OMAP343X, 2013 .flags = CLOCK_IN_OMAP343X,
1941 .recalc = &omap2_clksel_recalc, 2014 .recalc = &omap2_clksel_recalc,
@@ -1991,7 +2064,7 @@ static struct clk cam_mclk = {
1991 .parent = &dpll4_m5x2_ck, 2064 .parent = &dpll4_m5x2_ck,
1992 .init = &omap2_init_clksel_parent, 2065 .init = &omap2_init_clksel_parent,
1993 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), 2066 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST),
1994 .clksel_mask = OMAP3430_ST_PERIPH_CLK, 2067 .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK,
1995 .clksel = cam_mclk_clksel, 2068 .clksel = cam_mclk_clksel,
1996 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), 2069 .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN),
1997 .enable_bit = OMAP3430_EN_CAM_SHIFT, 2070 .enable_bit = OMAP3430_EN_CAM_SHIFT,
@@ -2541,7 +2614,8 @@ static struct clk gpt2_ick = {
2541}; 2614};
2542 2615
2543static struct clk mcbsp2_ick = { 2616static struct clk mcbsp2_ick = {
2544 .name = "mcbsp2_ick", 2617 .name = "mcbsp_ick",
2618 .id = 2,
2545 .parent = &per_l4_ick, 2619 .parent = &per_l4_ick,
2546 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2620 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2547 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2621 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2550,7 +2624,8 @@ static struct clk mcbsp2_ick = {
2550}; 2624};
2551 2625
2552static struct clk mcbsp3_ick = { 2626static struct clk mcbsp3_ick = {
2553 .name = "mcbsp3_ick", 2627 .name = "mcbsp_ick",
2628 .id = 3,
2554 .parent = &per_l4_ick, 2629 .parent = &per_l4_ick,
2555 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2630 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2556 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2631 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2559,7 +2634,8 @@ static struct clk mcbsp3_ick = {
2559}; 2634};
2560 2635
2561static struct clk mcbsp4_ick = { 2636static struct clk mcbsp4_ick = {
2562 .name = "mcbsp4_ick", 2637 .name = "mcbsp_ick",
2638 .id = 4,
2563 .parent = &per_l4_ick, 2639 .parent = &per_l4_ick,
2564 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), 2640 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN),
2565 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2641 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
@@ -2574,7 +2650,8 @@ static const struct clksel mcbsp_234_clksel[] = {
2574}; 2650};
2575 2651
2576static struct clk mcbsp2_fck = { 2652static struct clk mcbsp2_fck = {
2577 .name = "mcbsp2_fck", 2653 .name = "mcbsp_fck",
2654 .id = 2,
2578 .init = &omap2_init_clksel_parent, 2655 .init = &omap2_init_clksel_parent,
2579 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2656 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2580 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, 2657 .enable_bit = OMAP3430_EN_MCBSP2_SHIFT,
@@ -2586,7 +2663,8 @@ static struct clk mcbsp2_fck = {
2586}; 2663};
2587 2664
2588static struct clk mcbsp3_fck = { 2665static struct clk mcbsp3_fck = {
2589 .name = "mcbsp3_fck", 2666 .name = "mcbsp_fck",
2667 .id = 3,
2590 .init = &omap2_init_clksel_parent, 2668 .init = &omap2_init_clksel_parent,
2591 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2669 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2592 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, 2670 .enable_bit = OMAP3430_EN_MCBSP3_SHIFT,
@@ -2598,7 +2676,8 @@ static struct clk mcbsp3_fck = {
2598}; 2676};
2599 2677
2600static struct clk mcbsp4_fck = { 2678static struct clk mcbsp4_fck = {
2601 .name = "mcbsp4_fck", 2679 .name = "mcbsp_fck",
2680 .id = 4,
2602 .init = &omap2_init_clksel_parent, 2681 .init = &omap2_init_clksel_parent,
2603 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), 2682 .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
2604 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, 2683 .enable_bit = OMAP3430_EN_MCBSP4_SHIFT,
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 3c38395f6442..ee4c0ca1a708 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -72,7 +72,8 @@
72#define OMAP3430_ST_IVA2 (1 << 0) 72#define OMAP3430_ST_IVA2 (1 << 0)
73 73
74/* CM_IDLEST_PLL_IVA2 */ 74/* CM_IDLEST_PLL_IVA2 */
75#define OMAP3430_ST_IVA2_CLK (1 << 0) 75#define OMAP3430_ST_IVA2_CLK_SHIFT 0
76#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
76 77
77/* CM_AUTOIDLE_PLL_IVA2 */ 78/* CM_AUTOIDLE_PLL_IVA2 */
78#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0 79#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
@@ -115,10 +116,7 @@
115#define OMAP3430_ST_MPU (1 << 0) 116#define OMAP3430_ST_MPU (1 << 0)
116 117
117/* CM_IDLEST_PLL_MPU */ 118/* CM_IDLEST_PLL_MPU */
118#define OMAP3430_ST_MPU_CLK (1 << 0) 119#define OMAP3430_ST_MPU_CLK_SHIFT 0
119#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
120
121/* CM_IDLEST_PLL_MPU */
122#define OMAP3430_ST_MPU_CLK_MASK (1 << 0) 120#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
123 121
124/* CM_AUTOIDLE_PLL_MPU */ 122/* CM_AUTOIDLE_PLL_MPU */
@@ -408,8 +406,10 @@
408#define OMAP3430_ST_12M_CLK (1 << 4) 406#define OMAP3430_ST_12M_CLK (1 << 4)
409#define OMAP3430_ST_48M_CLK (1 << 3) 407#define OMAP3430_ST_48M_CLK (1 << 3)
410#define OMAP3430_ST_96M_CLK (1 << 2) 408#define OMAP3430_ST_96M_CLK (1 << 2)
411#define OMAP3430_ST_PERIPH_CLK (1 << 1) 409#define OMAP3430_ST_PERIPH_CLK_SHIFT 1
412#define OMAP3430_ST_CORE_CLK (1 << 0) 410#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
411#define OMAP3430_ST_CORE_CLK_SHIFT 0
412#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
413 413
414/* CM_IDLEST2_CKGEN */ 414/* CM_IDLEST2_CKGEN */
415#define OMAP3430ES2_ST_120M_CLK_SHIFT 1 415#define OMAP3430ES2_ST_120M_CLK_SHIFT 1
@@ -423,6 +423,10 @@
423#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0 423#define OMAP3430_AUTO_CORE_DPLL_SHIFT 0
424#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0) 424#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
425 425
426/* CM_AUTOIDLE2_PLL */
427#define OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT 0
428#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
429
426/* CM_CLKSEL1_PLL */ 430/* CM_CLKSEL1_PLL */
427/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */ 431/* Note that OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK was (0x3 << 27) on 3430ES1 */
428#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27 432#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h
index 8489f3029fed..87a44c715aa4 100644
--- a/arch/arm/mach-omap2/cm.h
+++ b/arch/arm/mach-omap2/cm.h
@@ -81,6 +81,7 @@
81#define OMAP3430ES2_CM_FCLKEN3 0x0008 81#define OMAP3430ES2_CM_FCLKEN3 0x0008
82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 82#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2
83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 83#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2
84#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2
84#define OMAP3430_CM_CLKSEL1 CM_CLKSEL 85#define OMAP3430_CM_CLKSEL1 CM_CLKSEL
85#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL 86#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL
86#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 87#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2
@@ -96,15 +97,21 @@
96/* Clock management domain register get/set */ 97/* Clock management domain register get/set */
97 98
98#ifndef __ASSEMBLER__ 99#ifndef __ASSEMBLER__
99static inline void cm_write_mod_reg(u32 val, s16 module, s16 idx) 100
101extern u32 cm_read_mod_reg(s16 module, u16 idx);
102extern void cm_write_mod_reg(u32 val, s16 module, u16 idx);
103extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
104
105static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
100{ 106{
101 __raw_writel(val, OMAP_CM_REGADDR(module, idx)); 107 return cm_rmw_mod_reg_bits(bits, bits, module, idx);
102} 108}
103 109
104static inline u32 cm_read_mod_reg(s16 module, s16 idx) 110static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
105{ 111{
106 return __raw_readl(OMAP_CM_REGADDR(module, idx)); 112 return cm_rmw_mod_reg_bits(bits, 0x0, module, idx);
107} 113}
114
108#endif 115#endif
109 116
110/* CM register bits shared between 24XX and 3430 */ 117/* CM register bits shared between 24XX and 3430 */
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c
index a5d86a49c213..51f70300996f 100644
--- a/arch/arm/mach-omap2/control.c
+++ b/arch/arm/mach-omap2/control.c
@@ -13,22 +13,21 @@
13#undef DEBUG 13#undef DEBUG
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/io.h>
16 17
17#include <asm/io.h> 18#include <asm/arch/common.h>
18
19#include <asm/arch/control.h> 19#include <asm/arch/control.h>
20 20
21static u32 omap2_ctrl_base; 21static void __iomem *omap2_ctrl_base;
22 22
23#define OMAP_CTRL_REGADDR(reg) (void __iomem *)IO_ADDRESS(omap2_ctrl_base \ 23#define OMAP_CTRL_REGADDR(reg) (omap2_ctrl_base + (reg))
24 + (reg))
25 24
26void omap_ctrl_base_set(u32 base) 25void __init omap2_set_globals_control(struct omap_globals *omap2_globals)
27{ 26{
28 omap2_ctrl_base = base; 27 omap2_ctrl_base = omap2_globals->ctrl;
29} 28}
30 29
31u32 omap_ctrl_base_get(void) 30void __iomem *omap_ctrl_base_get(void)
32{ 31{
33 return omap2_ctrl_base; 32 return omap2_ctrl_base;
34} 33}
@@ -50,25 +49,16 @@ u32 omap_ctrl_readl(u16 offset)
50 49
51void omap_ctrl_writeb(u8 val, u16 offset) 50void omap_ctrl_writeb(u8 val, u16 offset)
52{ 51{
53 pr_debug("omap_ctrl_writeb: writing 0x%0x to 0x%0x\n", val,
54 (u32)OMAP_CTRL_REGADDR(offset));
55
56 __raw_writeb(val, OMAP_CTRL_REGADDR(offset)); 52 __raw_writeb(val, OMAP_CTRL_REGADDR(offset));
57} 53}
58 54
59void omap_ctrl_writew(u16 val, u16 offset) 55void omap_ctrl_writew(u16 val, u16 offset)
60{ 56{
61 pr_debug("omap_ctrl_writew: writing 0x%0x to 0x%0x\n", val,
62 (u32)OMAP_CTRL_REGADDR(offset));
63
64 __raw_writew(val, OMAP_CTRL_REGADDR(offset)); 57 __raw_writew(val, OMAP_CTRL_REGADDR(offset));
65} 58}
66 59
67void omap_ctrl_writel(u32 val, u16 offset) 60void omap_ctrl_writel(u32 val, u16 offset)
68{ 61{
69 pr_debug("omap_ctrl_writel: writing 0x%0x to 0x%0x\n", val,
70 (u32)OMAP_CTRL_REGADDR(offset));
71
72 __raw_writel(val, OMAP_CTRL_REGADDR(offset)); 62 __raw_writel(val, OMAP_CTRL_REGADDR(offset));
73} 63}
74 64
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 02cede295e89..dbf68dc50ae2 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -42,7 +42,7 @@
42#define GPMC_STATUS 0x54 42#define GPMC_STATUS 0x54
43#define GPMC_PREFETCH_CONFIG1 0x1e0 43#define GPMC_PREFETCH_CONFIG1 0x1e0
44#define GPMC_PREFETCH_CONFIG2 0x1e4 44#define GPMC_PREFETCH_CONFIG2 0x1e4
45#define GPMC_PREFETCH_CONTROL 0x1e8 45#define GPMC_PREFETCH_CONTROL 0x1ec
46#define GPMC_PREFETCH_STATUS 0x1f0 46#define GPMC_PREFETCH_STATUS 0x1f0
47#define GPMC_ECC_CONFIG 0x1f4 47#define GPMC_ECC_CONFIG 0x1f4
48#define GPMC_ECC_CONTROL 0x1f8 48#define GPMC_ECC_CONTROL 0x1f8
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 4dfd878d7968..dff4b16cead6 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -17,16 +17,23 @@
17 17
18#include <asm/io.h> 18#include <asm/io.h>
19 19
20#if defined(CONFIG_ARCH_OMAP2420) 20#include <asm/arch/control.h>
21#define OMAP24XX_TAP_BASE io_p2v(0x48014000) 21#include <asm/arch/cpu.h>
22#endif
23 22
24#if defined(CONFIG_ARCH_OMAP2430) 23#if defined(CONFIG_ARCH_OMAP2420)
25#define OMAP24XX_TAP_BASE io_p2v(0x4900A000) 24#define TAP_BASE io_p2v(0x48014000)
25#elif defined(CONFIG_ARCH_OMAP2430)
26#define TAP_BASE io_p2v(0x4900A000)
27#elif defined(CONFIG_ARCH_OMAP34XX)
28#define TAP_BASE io_p2v(0x4830A000)
26#endif 29#endif
27 30
28#define OMAP_TAP_IDCODE 0x0204 31#define OMAP_TAP_IDCODE 0x0204
32#if defined(CONFIG_ARCH_OMAP34XX)
33#define OMAP_TAP_PROD_ID 0x0210
34#else
29#define OMAP_TAP_PROD_ID 0x0208 35#define OMAP_TAP_PROD_ID 0x0208
36#endif
30 37
31#define OMAP_TAP_DIE_ID_0 0x0218 38#define OMAP_TAP_DIE_ID_0 0x0218
32#define OMAP_TAP_DIE_ID_1 0x021C 39#define OMAP_TAP_DIE_ID_1 0x021C
@@ -56,9 +63,134 @@ static struct omap_id omap_ids[] __initdata = {
56 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 }, 63 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300000 },
57}; 64};
58 65
66static struct omap_chip_id omap_chip;
67
68/**
69 * omap_chip_is - test whether currently running OMAP matches a chip type
70 * @oc: omap_chip_t to test against
71 *
72 * Test whether the currently-running OMAP chip matches the supplied
73 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
74 */
75int omap_chip_is(struct omap_chip_id oci)
76{
77 return (oci.oc & omap_chip.oc) ? 1 : 0;
78}
79EXPORT_SYMBOL(omap_chip_is);
80
59static u32 __init read_tap_reg(int reg) 81static u32 __init read_tap_reg(int reg)
60{ 82{
61 return __raw_readl(OMAP24XX_TAP_BASE + reg); 83 unsigned int regval = 0;
84 u32 cpuid;
85
86 /* Reading the IDCODE register on 3430 ES1 results in a
87 * data abort as the register is not exposed on the OCP
88 * Hence reading the Cortex Rev
89 */
90 cpuid = read_cpuid(CPUID_ID);
91
92 /* If the processor type is Cortex-A8 and the revision is 0x0
93 * it means its Cortex r0p0 which is 3430 ES1
94 */
95 if ((((cpuid >> 4) & 0xFFF) == 0xC08) && ((cpuid & 0xF) == 0x0)) {
96 switch (reg) {
97 case OMAP_TAP_IDCODE : regval = 0x0B7AE02F; break;
98 /* Making DevType as 0xF in ES1 to differ from ES2 */
99 case OMAP_TAP_PROD_ID : regval = 0x000F00F0; break;
100 case OMAP_TAP_DIE_ID_0: regval = 0x01000000; break;
101 case OMAP_TAP_DIE_ID_1: regval = 0x1012d687; break;
102 case OMAP_TAP_DIE_ID_2: regval = 0x00000000; break;
103 case OMAP_TAP_DIE_ID_3: regval = 0x2d2c0000; break;
104 }
105 } else
106 regval = __raw_readl(TAP_BASE + reg);
107
108 return regval;
109
110}
111
112/*
113 * _set_system_rev - set the system_rev global based on current OMAP chip type
114 *
115 * Set the system_rev global. This is primarily used by the cpu_is_omapxxxx()
116 * macros.
117 */
118static void __init _set_system_rev(u32 type, u8 rev)
119{
120 u32 i, ctrl_status;
121
122 /*
123 * system_rev encoding is as follows
124 * system_rev & 0xff000000 -> Omap Class (24xx/34xx)
125 * system_rev & 0xfff00000 -> Omap Sub Class (242x/343x)
126 * system_rev & 0xffff0000 -> Omap type (2420/2422/2423/2430/3430)
127 * system_rev & 0x0000f000 -> Silicon revision (ES1, ES2 )
128 * system_rev & 0x00000700 -> Device Type ( EMU/HS/GP/BAD )
129 * system_rev & 0x000000c0 -> IDCODE revision[6:7]
130 * system_rev & 0x0000003f -> sys_boot[0:5]
131 */
132 /* Embedding the ES revision info in type field */
133 system_rev = type;
134 /* Also add IDCODE revision info only two lower bits */
135 system_rev |= ((rev & 0x3) << 6);
136
137 /* Add in the device type and sys_boot fields (see above) */
138 if (cpu_is_omap24xx()) {
139 i = OMAP24XX_CONTROL_STATUS;
140 } else if (cpu_is_omap343x()) {
141 i = OMAP343X_CONTROL_STATUS;
142 } else {
143 printk(KERN_ERR "id: unknown CPU type\n");
144 BUG();
145 }
146 ctrl_status = omap_ctrl_readl(i);
147 system_rev |= (ctrl_status & (OMAP2_SYSBOOT_5_MASK |
148 OMAP2_SYSBOOT_4_MASK |
149 OMAP2_SYSBOOT_3_MASK |
150 OMAP2_SYSBOOT_2_MASK |
151 OMAP2_SYSBOOT_1_MASK |
152 OMAP2_SYSBOOT_0_MASK));
153 system_rev |= (ctrl_status & OMAP2_DEVICETYPE_MASK);
154}
155
156
157/*
158 * _set_omap_chip - set the omap_chip global based on OMAP chip type
159 *
160 * Build the omap_chip bits. This variable is used by powerdomain and
161 * clockdomain code to indicate whether structures are applicable for
162 * the current OMAP chip type by ANDing it against a 'platform' bitfield
163 * in the structure.
164 */
165static void __init _set_omap_chip(void)
166{
167 if (cpu_is_omap343x()) {
168
169 omap_chip.oc = CHIP_IS_OMAP3430;
170 if (is_sil_rev_equal_to(OMAP3430_REV_ES1_0))
171 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
172 else if (is_sil_rev_greater_than(OMAP3430_REV_ES1_0))
173 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
174
175 } else if (cpu_is_omap243x()) {
176
177 /* Currently only supports 2430ES2.1 and 2430-all */
178 omap_chip.oc |= CHIP_IS_OMAP2430;
179
180 } else if (cpu_is_omap242x()) {
181
182 /* Currently only supports 2420ES2.1.1 and 2420-all */
183 omap_chip.oc |= CHIP_IS_OMAP2420;
184
185 } else {
186
187 /* Current CPU not supported by this code. */
188 printk(KERN_WARNING "OMAP chip type code does not yet support "
189 "this CPU type.\n");
190 WARN_ON(1);
191
192 }
193
62} 194}
63 195
64void __init omap2_check_revision(void) 196void __init omap2_check_revision(void)
@@ -76,21 +208,31 @@ void __init omap2_check_revision(void)
76 rev = (idcode >> 28) & 0x0f; 208 rev = (idcode >> 28) & 0x0f;
77 dev_type = (prod_id >> 16) & 0x0f; 209 dev_type = (prod_id >> 16) & 0x0f;
78 210
79#ifdef DEBUG 211 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
80 printk(KERN_DEBUG "OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n", 212 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
81 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff); 213 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
82 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_0: 0x%08x\n", 214 read_tap_reg(OMAP_TAP_DIE_ID_0));
83 read_tap_reg(OMAP_TAP_DIE_ID_0)); 215 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
84 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n", 216 read_tap_reg(OMAP_TAP_DIE_ID_1),
85 read_tap_reg(OMAP_TAP_DIE_ID_1), 217 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
86 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf); 218 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
87 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_2: 0x%08x\n", 219 read_tap_reg(OMAP_TAP_DIE_ID_2));
88 read_tap_reg(OMAP_TAP_DIE_ID_2)); 220 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
89 printk(KERN_DEBUG "OMAP_TAP_DIE_ID_3: 0x%08x\n", 221 read_tap_reg(OMAP_TAP_DIE_ID_3));
90 read_tap_reg(OMAP_TAP_DIE_ID_3)); 222 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
91 printk(KERN_DEBUG "OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n", 223 prod_id, dev_type);
92 prod_id, dev_type); 224
93#endif 225 /*
226 * Detection for 34xx ES2.0 and above can be done with just
227 * hawkeye and rev. See TRM 1.5.2 Device Identification.
228 * Note that rev cannot be used directly as ES1.0 uses value 0.
229 */
230 if (hawkeye == 0xb7ae) {
231 system_rev = 0x34300000 | ((1 + rev) << 12);
232 pr_info("OMAP%04x ES2.%i\n", system_rev >> 16, rev);
233 _set_omap_chip();
234 return;
235 }
94 236
95 /* Check hawkeye ids */ 237 /* Check hawkeye ids */
96 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) { 238 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
@@ -114,16 +256,15 @@ void __init omap2_check_revision(void)
114 omap_ids[i].type >> 16); 256 omap_ids[i].type >> 16);
115 j = i; 257 j = i;
116 } 258 }
117 system_rev = omap_ids[j].type;
118 259
119 system_rev |= rev << 8; 260 _set_system_rev(omap_ids[j].type, rev);
120 261
121 /* Add the cpu class info (24xx) */ 262 _set_omap_chip();
122 system_rev |= 0x24;
123 263
124 pr_info("OMAP%04x", system_rev >> 16); 264 pr_info("OMAP%04x", system_rev >> 16);
125 if ((system_rev >> 8) & 0x0f) 265 if ((system_rev >> 8) & 0x0f)
126 printk("%x", (system_rev >> 8) & 0x0f); 266 pr_info("ES%x", (system_rev >> 12) & 0xf);
127 printk("\n"); 267 pr_info("\n");
268
128} 269}
129 270
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
new file mode 100644
index 000000000000..17cf199d1130
--- /dev/null
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -0,0 +1,208 @@
1/*
2 * linux/arch/arm/mach-omap2/mcbsp.c
3 *
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * Multichannel mode not supported.
12 */
13#include <linux/module.h>
14#include <linux/init.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/platform_device.h>
19
20#include <asm/arch/dma.h>
21#include <asm/arch/mux.h>
22#include <asm/arch/cpu.h>
23#include <asm/arch/mcbsp.h>
24
25struct mcbsp_internal_clk {
26 struct clk clk;
27 struct clk **childs;
28 int n_childs;
29};
30
31#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
32static void omap_mcbsp_clk_init(struct mcbsp_internal_clk *mclk)
33{
34 const char *clk_names[] = { "mcbsp_ick", "mcbsp_fck" };
35 int i;
36
37 mclk->n_childs = ARRAY_SIZE(clk_names);
38 mclk->childs = kzalloc(mclk->n_childs * sizeof(struct clk *),
39 GFP_KERNEL);
40
41 for (i = 0; i < mclk->n_childs; i++) {
42 /* We fake a platform device to get correct device id */
43 struct platform_device pdev;
44
45 pdev.dev.bus = &platform_bus_type;
46 pdev.id = mclk->clk.id;
47 mclk->childs[i] = clk_get(&pdev.dev, clk_names[i]);
48 if (IS_ERR(mclk->childs[i]))
49 printk(KERN_ERR "Could not get clock %s (%d).\n",
50 clk_names[i], mclk->clk.id);
51 }
52}
53
54static int omap_mcbsp_clk_enable(struct clk *clk)
55{
56 struct mcbsp_internal_clk *mclk = container_of(clk,
57 struct mcbsp_internal_clk, clk);
58 int i;
59
60 for (i = 0; i < mclk->n_childs; i++)
61 clk_enable(mclk->childs[i]);
62 return 0;
63}
64
65static void omap_mcbsp_clk_disable(struct clk *clk)
66{
67 struct mcbsp_internal_clk *mclk = container_of(clk,
68 struct mcbsp_internal_clk, clk);
69 int i;
70
71 for (i = 0; i < mclk->n_childs; i++)
72 clk_disable(mclk->childs[i]);
73}
74
75static struct mcbsp_internal_clk omap_mcbsp_clks[] = {
76 {
77 .clk = {
78 .name = "mcbsp_clk",
79 .id = 1,
80 .enable = omap_mcbsp_clk_enable,
81 .disable = omap_mcbsp_clk_disable,
82 },
83 },
84 {
85 .clk = {
86 .name = "mcbsp_clk",
87 .id = 2,
88 .enable = omap_mcbsp_clk_enable,
89 .disable = omap_mcbsp_clk_disable,
90 },
91 },
92};
93
94#define omap_mcbsp_clks_size ARRAY_SIZE(omap_mcbsp_clks)
95#else
96#define omap_mcbsp_clks_size 0
97static struct mcbsp_internal_clk __initdata *omap_mcbsp_clks;
98static inline void omap_mcbsp_clk_init(struct clk *clk)
99{ }
100#endif
101
102static void omap2_mcbsp2_mux_setup(void)
103{
104 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
105 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
106 omap_cfg_reg(W15_24XX_MCBSP2_DR);
107 omap_cfg_reg(V15_24XX_MCBSP2_DX);
108 omap_cfg_reg(V14_24XX_GPIO117);
109 /*
110 * TODO: Need to add MUX settings for OMAP 2430 SDP
111 */
112}
113
114static void omap2_mcbsp_request(unsigned int id)
115{
116 if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
117 omap2_mcbsp2_mux_setup();
118}
119
120static int omap2_mcbsp_check(unsigned int id)
121{
122 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
123 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
124 return -ENODEV;
125 }
126 return 0;
127}
128
129static struct omap_mcbsp_ops omap2_mcbsp_ops = {
130 .request = omap2_mcbsp_request,
131 .check = omap2_mcbsp_check,
132};
133
134#ifdef CONFIG_ARCH_OMAP24XX
135static struct omap_mcbsp_platform_data omap24xx_mcbsp_pdata[] = {
136 {
137 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
138 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
139 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
140 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
141 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
142 .ops = &omap2_mcbsp_ops,
143 .clk_name = "mcbsp_clk",
144 },
145 {
146 .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
147 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
148 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
149 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
150 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
151 .ops = &omap2_mcbsp_ops,
152 .clk_name = "mcbsp_clk",
153 },
154};
155#define OMAP24XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap24xx_mcbsp_pdata)
156#else
157#define omap24xx_mcbsp_pdata NULL
158#define OMAP24XX_MCBSP_PDATA_SZ 0
159#endif
160
161#ifdef CONFIG_ARCH_OMAP34XX
162static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
163 {
164 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP1_BASE),
165 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
166 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
167 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
168 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
169 .ops = &omap2_mcbsp_ops,
170 .clk_name = "mcbsp_clk",
171 },
172 {
173 .virt_base = IO_ADDRESS(OMAP34XX_MCBSP2_BASE),
174 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
175 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
176 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
177 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
178 .ops = &omap2_mcbsp_ops,
179 .clk_name = "mcbsp_clk",
180 },
181};
182#define OMAP34XX_MCBSP_PDATA_SZ ARRAY_SIZE(omap34xx_mcbsp_pdata)
183#else
184#define omap34xx_mcbsp_pdata NULL
185#define OMAP34XX_MCBSP_PDATA_SZ 0
186#endif
187
188int __init omap2_mcbsp_init(void)
189{
190 int i;
191
192 for (i = 0; i < omap_mcbsp_clks_size; i++) {
193 /* Once we call clk_get inside init, we do not register it */
194 omap_mcbsp_clk_init(&omap_mcbsp_clks[i]);
195 clk_register(&omap_mcbsp_clks[i].clk);
196 }
197
198 if (cpu_is_omap24xx())
199 omap_mcbsp_register_board_cfg(omap24xx_mcbsp_pdata,
200 OMAP24XX_MCBSP_PDATA_SZ);
201
202 if (cpu_is_omap34xx())
203 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
204 OMAP34XX_MCBSP_PDATA_SZ);
205
206 return omap_mcbsp_init();
207}
208arch_initcall(omap2_mcbsp_init);
diff --git a/arch/arm/mach-omap2/memory.c b/arch/arm/mach-omap2/memory.c
index 12479081881a..73cadb2c75cf 100644
--- a/arch/arm/mach-omap2/memory.c
+++ b/arch/arm/mach-omap2/memory.c
@@ -24,6 +24,7 @@
24 24
25#include <asm/io.h> 25#include <asm/io.h>
26 26
27#include <asm/arch/common.h>
27#include <asm/arch/clock.h> 28#include <asm/arch/clock.h>
28#include <asm/arch/sram.h> 29#include <asm/arch/sram.h>
29 30
@@ -32,8 +33,8 @@
32#include "memory.h" 33#include "memory.h"
33#include "sdrc.h" 34#include "sdrc.h"
34 35
35unsigned long omap2_sdrc_base; 36void __iomem *omap2_sdrc_base;
36unsigned long omap2_sms_base; 37void __iomem *omap2_sms_base;
37 38
38static struct memory_timings mem_timings; 39static struct memory_timings mem_timings;
39static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2; 40static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
@@ -154,6 +155,12 @@ void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
154 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8)); 155 mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
155} 156}
156 157
158void __init omap2_set_globals_memory(struct omap_globals *omap2_globals)
159{
160 omap2_sdrc_base = omap2_globals->sdrc;
161 omap2_sms_base = omap2_globals->sms;
162}
163
157/* turn on smart idle modes for SDRAM scheduler and controller */ 164/* turn on smart idle modes for SDRAM scheduler and controller */
158void __init omap2_init_memory(void) 165void __init omap2_init_memory(void)
159{ 166{
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 930770012a75..8f98b20f30a1 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -236,7 +236,7 @@ void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
236 warn = (orig != reg); 236 warn = (orig != reg);
237 if (debug || warn) 237 if (debug || warn)
238 printk(KERN_WARNING 238 printk(KERN_WARNING
239 "MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n", 239 "MUX: setup %s (0x%p): 0x%04x -> 0x%04x\n",
240 cfg->name, omap_ctrl_base_get() + cfg->mux_reg, 240 cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
241 orig, reg); 241 orig, reg);
242} 242}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index aad781dcf1b1..d6c9de82ca0c 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -57,13 +57,6 @@ void omap2_pm_idle(void)
57 return; 57 return;
58 } 58 }
59 59
60 /*
61 * Since an interrupt may set up a timer, we don't want to
62 * reprogram the hardware timer with interrupts enabled.
63 * Re-enable interrupts only after returning from idle.
64 */
65 timer_dyn_reprogram();
66
67 omap2_sram_idle(); 60 omap2_sram_idle();
68 local_fiq_enable(); 61 local_fiq_enable();
69 local_irq_enable(); 62 local_irq_enable();
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index cacb34086e35..54c32f482131 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -32,6 +32,7 @@
32 32
33 33
34/* Chip-specific module offsets */ 34/* Chip-specific module offsets */
35#define OMAP24XX_GR_MOD OCP_MOD
35#define OMAP24XX_DSP_MOD 0x800 36#define OMAP24XX_DSP_MOD 0x800
36 37
37#define OMAP2430_MDM_MOD 0xc00 38#define OMAP2430_MDM_MOD 0xc00
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index b12f423b8595..fd92a80f38f2 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -16,16 +16,21 @@
16#include <linux/module.h> 16#include <linux/module.h>
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/clk.h> 18#include <linux/clk.h>
19#include <linux/io.h>
19 20
20#include <asm/io.h> 21#include <asm/arch/common.h>
22#include <asm/arch/prcm.h>
21 23
24#include "clock.h"
22#include "prm.h" 25#include "prm.h"
23#include "prm-regbits-24xx.h" 26#include "prm-regbits-24xx.h"
24 27
25extern void omap2_clk_prepare_for_reboot(void); 28static void __iomem *prm_base;
29static void __iomem *cm_base;
26 30
27u32 omap_prcm_get_reset_sources(void) 31u32 omap_prcm_get_reset_sources(void)
28{ 32{
33 /* XXX This presumably needs modification for 34XX */
29 return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f; 34 return prm_read_mod_reg(WKUP_MOD, RM_RSTST) & 0x7f;
30} 35}
31EXPORT_SYMBOL(omap_prcm_get_reset_sources); 36EXPORT_SYMBOL(omap_prcm_get_reset_sources);
@@ -33,11 +38,90 @@ EXPORT_SYMBOL(omap_prcm_get_reset_sources);
33/* Resets clock rates and reboots the system. Only called from system.h */ 38/* Resets clock rates and reboots the system. Only called from system.h */
34void omap_prcm_arch_reset(char mode) 39void omap_prcm_arch_reset(char mode)
35{ 40{
36 u32 wkup; 41 s16 prcm_offs;
37 omap2_clk_prepare_for_reboot(); 42 omap2_clk_prepare_for_reboot();
38 43
39 if (cpu_is_omap24xx()) { 44 if (cpu_is_omap24xx())
40 wkup = prm_read_mod_reg(WKUP_MOD, RM_RSTCTRL) | OMAP_RST_DPLL3; 45 prcm_offs = WKUP_MOD;
41 prm_write_mod_reg(wkup, WKUP_MOD, RM_RSTCTRL); 46 else if (cpu_is_omap34xx())
42 } 47 prcm_offs = OMAP3430_GR_MOD;
48 else
49 WARN_ON(1);
50
51 prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
52}
53
54static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
55{
56 BUG_ON(!base);
57 return __raw_readl(base + module + reg);
58}
59
60static inline void __omap_prcm_write(u32 value, void __iomem *base,
61 s16 module, u16 reg)
62{
63 BUG_ON(!base);
64 __raw_writel(value, base + module + reg);
65}
66
67/* Read a register in a PRM module */
68u32 prm_read_mod_reg(s16 module, u16 idx)
69{
70 return __omap_prcm_read(prm_base, module, idx);
71}
72EXPORT_SYMBOL(prm_read_mod_reg);
73
74/* Write into a register in a PRM module */
75void prm_write_mod_reg(u32 val, s16 module, u16 idx)
76{
77 __omap_prcm_write(val, prm_base, module, idx);
78}
79EXPORT_SYMBOL(prm_write_mod_reg);
80
81/* Read-modify-write a register in a PRM module. Caller must lock */
82u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
83{
84 u32 v;
85
86 v = prm_read_mod_reg(module, idx);
87 v &= ~mask;
88 v |= bits;
89 prm_write_mod_reg(v, module, idx);
90
91 return v;
92}
93EXPORT_SYMBOL(prm_rmw_mod_reg_bits);
94
95/* Read a register in a CM module */
96u32 cm_read_mod_reg(s16 module, u16 idx)
97{
98 return __omap_prcm_read(cm_base, module, idx);
99}
100EXPORT_SYMBOL(cm_read_mod_reg);
101
102/* Write into a register in a CM module */
103void cm_write_mod_reg(u32 val, s16 module, u16 idx)
104{
105 __omap_prcm_write(val, cm_base, module, idx);
106}
107EXPORT_SYMBOL(cm_write_mod_reg);
108
109/* Read-modify-write a register in a CM module. Caller must lock */
110u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
111{
112 u32 v;
113
114 v = cm_read_mod_reg(module, idx);
115 v &= ~mask;
116 v |= bits;
117 cm_write_mod_reg(v, module, idx);
118
119 return v;
120}
121EXPORT_SYMBOL(cm_rmw_mod_reg_bits);
122
123void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
124{
125 prm_base = omap2_globals->prm;
126 cm_base = omap2_globals->cm;
43} 127}
diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h
index 618f8111658a..bbf41fc8e9a9 100644
--- a/arch/arm/mach-omap2/prm.h
+++ b/arch/arm/mach-omap2/prm.h
@@ -38,13 +38,29 @@
38 * 38 *
39 */ 39 */
40 40
41/* Global 24xx registers in GR_MOD (Same as OCP_MOD for 24xx) */
42#define OMAP24XX_PRCM_VOLTCTRL_OFFSET 0x0050
43#define OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET 0x0080
44
45/* 242x GR_MOD registers, use these only for assembly code */
46#define OMAP242X_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
47 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
48#define OMAP242X_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OMAP24XX_GR_MOD, \
49 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
50
51/* 243x GR_MOD registers, use these only for assembly code */
52#define OMAP243X_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
53 OMAP24XX_PRCM_VOLTCTRL_OFFSET)
54#define OMAP243X_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OMAP24XX_GR_MOD, \
55 OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET)
56
57/* These will disappear */
41#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000) 58#define OMAP24XX_PRCM_REVISION OMAP_PRM_REGADDR(OCP_MOD, 0x0000)
42#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010) 59#define OMAP24XX_PRCM_SYSCONFIG OMAP_PRM_REGADDR(OCP_MOD, 0x0010)
43 60
44#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018) 61#define OMAP24XX_PRCM_IRQSTATUS_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x0018)
45#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c) 62#define OMAP24XX_PRCM_IRQENABLE_MPU OMAP_PRM_REGADDR(OCP_MOD, 0x001c)
46 63
47#define OMAP24XX_PRCM_VOLTCTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0050)
48#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054) 64#define OMAP24XX_PRCM_VOLTST OMAP_PRM_REGADDR(OCP_MOD, 0x0054)
49#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060) 65#define OMAP24XX_PRCM_CLKSRC_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0060)
50#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070) 66#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP_PRM_REGADDR(OCP_MOD, 0x0070)
@@ -150,15 +166,19 @@
150#ifndef __ASSEMBLER__ 166#ifndef __ASSEMBLER__
151 167
152/* Power/reset management domain register get/set */ 168/* Power/reset management domain register get/set */
169extern u32 prm_read_mod_reg(s16 module, u16 idx);
170extern void prm_write_mod_reg(u32 val, s16 module, u16 idx);
171extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx);
153 172
154static inline void prm_write_mod_reg(u32 val, s16 module, s16 idx) 173/* Read-modify-write bits in a PRM register (by domain) */
174static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx)
155{ 175{
156 __raw_writel(val, OMAP_PRM_REGADDR(module, idx)); 176 return prm_rmw_mod_reg_bits(bits, bits, module, idx);
157} 177}
158 178
159static inline u32 prm_read_mod_reg(s16 module, s16 idx) 179static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx)
160{ 180{
161 return __raw_readl(OMAP_PRM_REGADDR(module, idx)); 181 return prm_rmw_mod_reg_bits(bits, 0x0, module, idx);
162} 182}
163 183
164#endif 184#endif
diff --git a/arch/arm/mach-omap2/sdrc.h b/arch/arm/mach-omap2/sdrc.h
index d7f23bc9550a..1b1fe4f6e030 100644
--- a/arch/arm/mach-omap2/sdrc.h
+++ b/arch/arm/mach-omap2/sdrc.h
@@ -18,13 +18,11 @@
18#include <asm/arch/sdrc.h> 18#include <asm/arch/sdrc.h>
19 19
20#ifndef __ASSEMBLER__ 20#ifndef __ASSEMBLER__
21extern unsigned long omap2_sdrc_base; 21extern void __iomem *omap2_sdrc_base;
22extern unsigned long omap2_sms_base; 22extern void __iomem *omap2_sms_base;
23 23
24#define OMAP_SDRC_REGADDR(reg) \ 24#define OMAP_SDRC_REGADDR(reg) (omap2_sdrc_base + (reg))
25 (void __iomem *)IO_ADDRESS(omap2_sdrc_base + (reg)) 25#define OMAP_SMS_REGADDR(reg) (omap2_sms_base + (reg))
26#define OMAP_SMS_REGADDR(reg) \
27 (void __iomem *)IO_ADDRESS(omap2_sms_base + (reg))
28 26
29/* SDRC global register get/set */ 27/* SDRC global register get/set */
30 28
diff --git a/arch/arm/mach-omap2/sram-fn.S b/arch/arm/mach-omap2/sram242x.S
index 4a9e49140716..4c274510f3e9 100644
--- a/arch/arm/mach-omap2/sram-fn.S
+++ b/arch/arm/mach-omap2/sram242x.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-omap2/sram-fn.S 2 * linux/arch/arm/mach-omap2/sram242x.S
3 * 3 *
4 * Omap2 specific functions that need to be run in internal SRAM 4 * Omap2 specific functions that need to be run in internal SRAM
5 * 5 *
@@ -27,22 +27,20 @@
27#include <asm/arch/io.h> 27#include <asm/arch/io.h>
28#include <asm/hardware.h> 28#include <asm/hardware.h>
29 29
30#include "sdrc.h"
31#include "prm.h" 30#include "prm.h"
32#include "cm.h" 31#include "cm.h"
33 32#include "sdrc.h"
34#define TIMER_32KSYNCT_CR_V IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
35 33
36 .text 34 .text
37 35
38ENTRY(sram_ddr_init) 36ENTRY(omap242x_sram_ddr_init)
39 stmfd sp!, {r0 - r12, lr} @ save registers on stack 37 stmfd sp!, {r0 - r12, lr} @ save registers on stack
40 38
41 mov r12, r2 @ capture CS1 vs CS0 39 mov r12, r2 @ capture CS1 vs CS0
42 mov r8, r3 @ capture force parameter 40 mov r8, r3 @ capture force parameter
43 41
44 /* frequency shift down */ 42 /* frequency shift down */
45 ldr r2, cm_clksel2_pll @ get address of dpllout reg 43 ldr r2, omap242x_sdi_cm_clksel2_pll @ get address of dpllout reg
46 mov r3, #0x1 @ value for 1x operation 44 mov r3, #0x1 @ value for 1x operation
47 str r3, [r2] @ go to L1-freq operation 45 str r3, [r2] @ go to L1-freq operation
48 46
@@ -51,7 +49,7 @@ ENTRY(sram_ddr_init)
51 bl voltage_shift @ go drop voltage 49 bl voltage_shift @ go drop voltage
52 50
53 /* dll lock mode */ 51 /* dll lock mode */
54 ldr r11, sdrc_dlla_ctrl @ addr of dlla ctrl 52 ldr r11, omap242x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
55 ldr r10, [r11] @ get current val 53 ldr r10, [r11] @ get current val
56 cmp r12, #0x1 @ cs1 base (2422 es2.05/1) 54 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
57 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB 55 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
@@ -102,7 +100,7 @@ i_dll_delay:
102 * wait for it to finish, use 32k sync counter, 1tick=31uS. 100 * wait for it to finish, use 32k sync counter, 1tick=31uS.
103 */ 101 */
104voltage_shift: 102voltage_shift:
105 ldr r4, prcm_voltctrl @ get addr of volt ctrl. 103 ldr r4, omap242x_sdi_prcm_voltctrl @ get addr of volt ctrl.
106 ldr r5, [r4] @ get value. 104 ldr r5, [r4] @ get value.
107 ldr r6, prcm_mask_val @ get value of mask 105 ldr r6, prcm_mask_val @ get value of mask
108 and r5, r5, r6 @ apply mask to clear bits 106 and r5, r5, r6 @ apply mask to clear bits
@@ -112,7 +110,7 @@ voltage_shift:
112 orr r5, r5, r3 @ build value for force 110 orr r5, r5, r3 @ build value for force
113 str r5, [r4] @ Force transition to L1 111 str r5, [r4] @ Force transition to L1
114 112
115 ldr r3, timer_32ksynct_cr @ get addr of counter 113 ldr r3, omap242x_sdi_timer_32ksynct_cr @ get addr of counter
116 ldr r5, [r3] @ get value 114 ldr r5, [r3] @ get value
117 add r5, r5, #0x3 @ give it at most 93uS 115 add r5, r5, #0x3 @ give it at most 93uS
118volt_delay: 116volt_delay:
@@ -121,32 +119,31 @@ volt_delay:
121 bhi volt_delay @ not yet->branch 119 bhi volt_delay @ not yet->branch
122 mov pc, lr @ back to caller. 120 mov pc, lr @ back to caller.
123 121
124/* relative load constants */ 122omap242x_sdi_cm_clksel2_pll:
125cm_clksel2_pll:
126 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) 123 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
127sdrc_dlla_ctrl: 124omap242x_sdi_sdrc_dlla_ctrl:
128 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 125 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
129prcm_voltctrl: 126omap242x_sdi_prcm_voltctrl:
130 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) 127 .word OMAP242X_PRCM_VOLTCTRL
131prcm_mask_val: 128prcm_mask_val:
132 .word 0xFFFF3FFC 129 .word 0xFFFF3FFC
133timer_32ksynct_cr: 130omap242x_sdi_timer_32ksynct_cr:
134 .word TIMER_32KSYNCT_CR_V 131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
135ENTRY(sram_ddr_init_sz) 132ENTRY(omap242x_sram_ddr_init_sz)
136 .word . - sram_ddr_init 133 .word . - omap242x_sram_ddr_init
137 134
138/* 135/*
139 * Reprograms memory timings. 136 * Reprograms memory timings.
140 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR] 137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
141 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0 138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
142 */ 139 */
143ENTRY(sram_reprogram_sdrc) 140ENTRY(omap242x_sram_reprogram_sdrc)
144 stmfd sp!, {r0 - r10, lr} @ save registers on stack 141 stmfd sp!, {r0 - r10, lr} @ save registers on stack
145 mov r3, #0x0 @ clear for mrc call 142 mov r3, #0x0 @ clear for mrc call
146 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR 143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
147 nop 144 nop
148 nop 145 nop
149 ldr r6, ddr_sdrc_rfr_ctrl @ get addr of refresh reg 146 ldr r6, omap242x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
150 ldr r5, [r6] @ get value 147 ldr r5, [r6] @ get value
151 mov r5, r5, lsr #8 @ isolate rfr field and drop burst 148 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
152 149
@@ -160,7 +157,7 @@ ENTRY(sram_reprogram_sdrc)
160 movne r5, r5, lsl #1 @ mult by 2 if to full 157 movne r5, r5, lsl #1 @ mult by 2 if to full
161 mov r5, r5, lsl #8 @ put rfr field back into place 158 mov r5, r5, lsl #8 @ put rfr field back into place
162 add r5, r5, #0x1 @ turn on burst of 1 159 add r5, r5, #0x1 @ turn on burst of 1
163 ldr r4, ddr_cm_clksel2_pll @ get address of out reg 160 ldr r4, omap242x_srs_cm_clksel2_pll @ get address of out reg
164 ldr r3, [r4] @ get curr value 161 ldr r3, [r4] @ get curr value
165 orr r3, r3, #0x3 162 orr r3, r3, #0x3
166 bic r3, r3, #0x3 @ clear lower bits 163 bic r3, r3, #0x3 @ clear lower bits
@@ -181,7 +178,7 @@ ENTRY(sram_reprogram_sdrc)
181 bne freq_out @ leave if SDR, no DLL function 178 bne freq_out @ leave if SDR, no DLL function
182 179
183 /* With DDR, we need to take care of the DLL for the frequency change */ 180 /* With DDR, we need to take care of the DLL for the frequency change */
184 ldr r2, ddr_sdrc_dlla_ctrl @ addr of dlla ctrl 181 ldr r2, omap242x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
185 str r1, [r2] @ write out new SDRC_DLLA_CTRL 182 str r1, [r2] @ write out new SDRC_DLLA_CTRL
186 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL 183 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
187 str r1, [r2] @ commit to SDRC_DLLB_CTRL 184 str r1, [r2] @ commit to SDRC_DLLB_CTRL
@@ -197,7 +194,7 @@ freq_out:
197 * wait for it to finish, use 32k sync counter, 1tick=31uS. 194 * wait for it to finish, use 32k sync counter, 1tick=31uS.
198 */ 195 */
199voltage_shift_c: 196voltage_shift_c:
200 ldr r10, ddr_prcm_voltctrl @ get addr of volt ctrl 197 ldr r10, omap242x_srs_prcm_voltctrl @ get addr of volt ctrl
201 ldr r8, [r10] @ get value 198 ldr r8, [r10] @ get value
202 ldr r7, ddr_prcm_mask_val @ get value of mask 199 ldr r7, ddr_prcm_mask_val @ get value of mask
203 and r8, r8, r7 @ apply mask to clear bits 200 and r8, r8, r7 @ apply mask to clear bits
@@ -207,7 +204,7 @@ voltage_shift_c:
207 orr r8, r8, r7 @ build value for force 204 orr r8, r8, r7 @ build value for force
208 str r8, [r10] @ Force transition to L1 205 str r8, [r10] @ Force transition to L1
209 206
210 ldr r10, ddr_timer_32ksynct @ get addr of counter 207 ldr r10, omap242x_srs_timer_32ksynct @ get addr of counter
211 ldr r8, [r10] @ get value 208 ldr r8, [r10] @ get value
212 add r8, r8, #0x2 @ give it at most 62uS (min 31+) 209 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
213volt_delay_c: 210volt_delay_c:
@@ -216,39 +213,39 @@ volt_delay_c:
216 bhi volt_delay_c @ not yet->branch 213 bhi volt_delay_c @ not yet->branch
217 mov pc, lr @ back to caller 214 mov pc, lr @ back to caller
218 215
219ddr_cm_clksel2_pll: 216omap242x_srs_cm_clksel2_pll:
220 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2) 217 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
221ddr_sdrc_dlla_ctrl: 218omap242x_srs_sdrc_dlla_ctrl:
222 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 219 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
223ddr_sdrc_rfr_ctrl: 220omap242x_srs_sdrc_rfr_ctrl:
224 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 221 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
225ddr_prcm_voltctrl: 222omap242x_srs_prcm_voltctrl:
226 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x50) 223 .word OMAP242X_PRCM_VOLTCTRL
227ddr_prcm_mask_val: 224ddr_prcm_mask_val:
228 .word 0xFFFF3FFC 225 .word 0xFFFF3FFC
229ddr_timer_32ksynct: 226omap242x_srs_timer_32ksynct:
230 .word TIMER_32KSYNCT_CR_V 227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
231 228
232ENTRY(sram_reprogram_sdrc_sz) 229ENTRY(omap242x_sram_reprogram_sdrc_sz)
233 .word . - sram_reprogram_sdrc 230 .word . - omap242x_sram_reprogram_sdrc
234 231
235/* 232/*
236 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode. 233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
237 */ 234 */
238ENTRY(sram_set_prcm) 235ENTRY(omap242x_sram_set_prcm)
239 stmfd sp!, {r0-r12, lr} @ regs to stack 236 stmfd sp!, {r0-r12, lr} @ regs to stack
240 adr r4, pbegin @ addr of preload start 237 adr r4, pbegin @ addr of preload start
241 adr r8, pend @ addr of preload end 238 adr r8, pend @ addr of preload end
242 mcrr p15, 1, r8, r4, c12 @ preload into icache 239 mcrr p15, 1, r8, r4, c12 @ preload into icache
243pbegin: 240pbegin:
244 /* move into fast relock bypass */ 241 /* move into fast relock bypass */
245 ldr r8, pll_ctl @ get addr 242 ldr r8, omap242x_ssp_pll_ctl @ get addr
246 ldr r5, [r8] @ get val 243 ldr r5, [r8] @ get val
247 mvn r6, #0x3 @ clear mask 244 mvn r6, #0x3 @ clear mask
248 and r5, r5, r6 @ clear field 245 and r5, r5, r6 @ clear field
249 orr r7, r5, #0x2 @ fast relock val 246 orr r7, r5, #0x2 @ fast relock val
250 str r7, [r8] @ go to fast relock 247 str r7, [r8] @ go to fast relock
251 ldr r4, pll_stat @ addr of stat 248 ldr r4, omap242x_ssp_pll_stat @ addr of stat
252block: 249block:
253 /* wait for bypass */ 250 /* wait for bypass */
254 ldr r8, [r4] @ stat value 251 ldr r8, [r4] @ stat value
@@ -257,10 +254,10 @@ block:
257 bne block @ loop if not 254 bne block @ loop if not
258 255
259 /* set new dpll dividers _after_ in bypass */ 256 /* set new dpll dividers _after_ in bypass */
260 ldr r4, pll_div @ get addr 257 ldr r4, omap242x_ssp_pll_div @ get addr
261 str r0, [r4] @ set dpll ctrl val 258 str r0, [r4] @ set dpll ctrl val
262 259
263 ldr r4, set_config @ get addr 260 ldr r4, omap242x_ssp_set_config @ get addr
264 mov r8, #1 @ valid cfg msk 261 mov r8, #1 @ valid cfg msk
265 str r8, [r4] @ make dividers take 262 str r8, [r4] @ make dividers take
266 263
@@ -274,8 +271,8 @@ wait_a_bit:
274 beq pend @ jump over dpll relock 271 beq pend @ jump over dpll relock
275 272
276 /* relock DPLL with new vals */ 273 /* relock DPLL with new vals */
277 ldr r5, pll_stat @ get addr 274 ldr r5, omap242x_ssp_pll_stat @ get addr
278 ldr r4, pll_ctl @ get addr 275 ldr r4, omap242x_ssp_pll_ctl @ get addr
279 orr r8, r7, #0x3 @ val for lock dpll 276 orr r8, r7, #0x3 @ val for lock dpll
280 str r8, [r4] @ set val 277 str r8, [r4] @ set val
281 mov r0, #1000 @ dead spin a bit 278 mov r0, #1000 @ dead spin a bit
@@ -289,9 +286,9 @@ wait_lock:
289 bne wait_lock @ wait if not 286 bne wait_lock @ wait if not
290pend: 287pend:
291 /* update memory timings & briefly lock dll */ 288 /* update memory timings & briefly lock dll */
292 ldr r4, sdrc_rfr @ get addr 289 ldr r4, omap242x_ssp_sdrc_rfr @ get addr
293 str r1, [r4] @ update refresh timing 290 str r1, [r4] @ update refresh timing
294 ldr r11, dlla_ctrl @ get addr of DLLA ctrl 291 ldr r11, omap242x_ssp_dlla_ctrl @ get addr of DLLA ctrl
295 ldr r10, [r11] @ get current val 292 ldr r10, [r11] @ get current val
296 mvn r9, #0x4 @ mask to get clear bit2 293 mvn r9, #0x4 @ mask to get clear bit2
297 and r10, r10, r9 @ clear bit2 for lock mode 294 and r10, r10, r9 @ clear bit2 for lock mode
@@ -307,18 +304,18 @@ wait_dll_lock:
307 nop 304 nop
308 ldmfd sp!, {r0-r12, pc} @ restore regs and return 305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
309 306
310set_config: 307omap242x_ssp_set_config:
311 .word OMAP2420_PRM_REGADDR(OCP_MOD, 0x80) 308 .word OMAP242X_PRCM_CLKCFG_CTRL
312pll_ctl: 309omap242x_ssp_pll_ctl:
313 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_FCLKEN1) 310 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKEN)
314pll_stat: 311omap242x_ssp_pll_stat:
315 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST1) 312 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_IDLEST)
316pll_div: 313omap242x_ssp_pll_div:
317 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL) 314 .word OMAP2420_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
318sdrc_rfr: 315omap242x_ssp_sdrc_rfr:
319 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0) 316 .word OMAP242X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
320dlla_ctrl: 317omap242x_ssp_dlla_ctrl:
321 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL) 318 .word OMAP242X_SDRC_REGADDR(SDRC_DLLA_CTRL)
322 319
323ENTRY(sram_set_prcm_sz) 320ENTRY(omap242x_sram_set_prcm_sz)
324 .word . - sram_set_prcm 321 .word . - omap242x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S
new file mode 100644
index 000000000000..a3fa48dc08cd
--- /dev/null
+++ b/arch/arm/mach-omap2/sram243x.S
@@ -0,0 +1,321 @@
1/*
2 * linux/arch/arm/mach-omap2/sram243x.S
3 *
4 * Omap2 specific functions that need to be run in internal SRAM
5 *
6 * (C) Copyright 2004
7 * Texas Instruments, <www.ti.com>
8 * Richard Woodruff <r-woodruff2@ti.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#include <linux/linkage.h>
26#include <asm/assembler.h>
27#include <asm/arch/io.h>
28#include <asm/hardware.h>
29
30#include "prm.h"
31#include "cm.h"
32#include "sdrc.h"
33
34 .text
35
36ENTRY(omap243x_sram_ddr_init)
37 stmfd sp!, {r0 - r12, lr} @ save registers on stack
38
39 mov r12, r2 @ capture CS1 vs CS0
40 mov r8, r3 @ capture force parameter
41
42 /* frequency shift down */
43 ldr r2, omap243x_sdi_cm_clksel2_pll @ get address of dpllout reg
44 mov r3, #0x1 @ value for 1x operation
45 str r3, [r2] @ go to L1-freq operation
46
47 /* voltage shift down */
48 mov r9, #0x1 @ set up for L1 voltage call
49 bl voltage_shift @ go drop voltage
50
51 /* dll lock mode */
52 ldr r11, omap243x_sdi_sdrc_dlla_ctrl @ addr of dlla ctrl
53 ldr r10, [r11] @ get current val
54 cmp r12, #0x1 @ cs1 base (2422 es2.05/1)
55 addeq r11, r11, #0x8 @ if cs1 base, move to DLLB
56 mvn r9, #0x4 @ mask to get clear bit2
57 and r10, r10, r9 @ clear bit2 for lock mode.
58 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
59 orr r10, r10, #0x2 @ 90 degree phase for all below 133Mhz
60 str r10, [r11] @ commit to DLLA_CTRL
61 bl i_dll_wait @ wait for dll to lock
62
63 /* get dll value */
64 add r11, r11, #0x4 @ get addr of status reg
65 ldr r10, [r11] @ get locked value
66
67 /* voltage shift up */
68 mov r9, #0x0 @ shift back to L0-voltage
69 bl voltage_shift @ go raise voltage
70
71 /* frequency shift up */
72 mov r3, #0x2 @ value for 2x operation
73 str r3, [r2] @ go to L0-freq operation
74
75 /* reset entry mode for dllctrl */
76 sub r11, r11, #0x4 @ move from status to ctrl
77 cmp r12, #0x1 @ normalize if cs1 based
78 subeq r11, r11, #0x8 @ possibly back to DLLA
79 cmp r8, #0x1 @ if forced unlock exit
80 orreq r1, r1, #0x4 @ make sure exit with unlocked value
81 str r1, [r11] @ restore DLLA_CTRL high value
82 add r11, r11, #0x8 @ move to DLLB_CTRL addr
83 str r1, [r11] @ set value DLLB_CTRL
84 bl i_dll_wait @ wait for possible lock
85
86 /* set up for return, DDR should be good */
87 str r10, [r0] @ write dll_status and return counter
88 ldmfd sp!, {r0 - r12, pc} @ restore regs and return
89
90 /* ensure the DLL has relocked */
91i_dll_wait:
92 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
93i_dll_delay:
94 subs r4, r4, #0x1
95 bne i_dll_delay
96 mov pc, lr
97
98 /*
99 * shift up or down voltage, use R9 as input to tell level.
100 * wait for it to finish, use 32k sync counter, 1tick=31uS.
101 */
102voltage_shift:
103 ldr r4, omap243x_sdi_prcm_voltctrl @ get addr of volt ctrl.
104 ldr r5, [r4] @ get value.
105 ldr r6, prcm_mask_val @ get value of mask
106 and r5, r5, r6 @ apply mask to clear bits
107 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
108 str r5, [r4] @ set up for change.
109 mov r3, #0x4000 @ get val for force
110 orr r5, r5, r3 @ build value for force
111 str r5, [r4] @ Force transition to L1
112
113 ldr r3, omap243x_sdi_timer_32ksynct_cr @ get addr of counter
114 ldr r5, [r3] @ get value
115 add r5, r5, #0x3 @ give it at most 93uS
116volt_delay:
117 ldr r7, [r3] @ get timer value
118 cmp r5, r7 @ time up?
119 bhi volt_delay @ not yet->branch
120 mov pc, lr @ back to caller.
121
122omap243x_sdi_cm_clksel2_pll:
123 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
124omap243x_sdi_sdrc_dlla_ctrl:
125 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
126omap243x_sdi_prcm_voltctrl:
127 .word OMAP243X_PRCM_VOLTCTRL
128prcm_mask_val:
129 .word 0xFFFF3FFC
130omap243x_sdi_timer_32ksynct_cr:
131 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
132ENTRY(omap243x_sram_ddr_init_sz)
133 .word . - omap243x_sram_ddr_init
134
135/*
136 * Reprograms memory timings.
137 * r0 = [PRCM_FULL | PRCM_HALF] r1 = SDRC_DLLA_CTRL value r2 = [DDR | SDR]
138 * PRCM_FULL = 2, PRCM_HALF = 1, DDR = 1, SDR = 0
139 */
140ENTRY(omap243x_sram_reprogram_sdrc)
141 stmfd sp!, {r0 - r10, lr} @ save registers on stack
142 mov r3, #0x0 @ clear for mrc call
143 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
144 nop
145 nop
146 ldr r6, omap243x_srs_sdrc_rfr_ctrl @ get addr of refresh reg
147 ldr r5, [r6] @ get value
148 mov r5, r5, lsr #8 @ isolate rfr field and drop burst
149
150 cmp r0, #0x1 @ going to half speed?
151 movne r9, #0x0 @ if up set flag up for pre up, hi volt
152
153 blne voltage_shift_c @ adjust voltage
154
155 cmp r0, #0x1 @ going to half speed (post branch link)
156 moveq r5, r5, lsr #1 @ divide by 2 if to half
157 movne r5, r5, lsl #1 @ mult by 2 if to full
158 mov r5, r5, lsl #8 @ put rfr field back into place
159 add r5, r5, #0x1 @ turn on burst of 1
160 ldr r4, omap243x_srs_cm_clksel2_pll @ get address of out reg
161 ldr r3, [r4] @ get curr value
162 orr r3, r3, #0x3
163 bic r3, r3, #0x3 @ clear lower bits
164 orr r3, r3, r0 @ new state value
165 str r3, [r4] @ set new state (pll/x, x=1 or 2)
166 nop
167 nop
168
169 moveq r9, #0x1 @ if speed down, post down, drop volt
170 bleq voltage_shift_c
171
172 mcr p15, 0, r3, c7, c10, 4 @ memory barrier
173 str r5, [r6] @ set new RFR_1 value
174 add r6, r6, #0x30 @ get RFR_2 addr
175 str r5, [r6] @ set RFR_2
176 nop
177 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
178 bne freq_out @ leave if SDR, no DLL function
179
180 /* With DDR, we need to take care of the DLL for the frequency change */
181 ldr r2, omap243x_srs_sdrc_dlla_ctrl @ addr of dlla ctrl
182 str r1, [r2] @ write out new SDRC_DLLA_CTRL
183 add r2, r2, #0x8 @ addr to SDRC_DLLB_CTRL
184 str r1, [r2] @ commit to SDRC_DLLB_CTRL
185 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
186dll_wait:
187 subs r1, r1, #0x1
188 bne dll_wait
189freq_out:
190 ldmfd sp!, {r0 - r10, pc} @ restore regs and return
191
192 /*
193 * shift up or down voltage, use R9 as input to tell level.
194 * wait for it to finish, use 32k sync counter, 1tick=31uS.
195 */
196voltage_shift_c:
197 ldr r10, omap243x_srs_prcm_voltctrl @ get addr of volt ctrl
198 ldr r8, [r10] @ get value
199 ldr r7, ddr_prcm_mask_val @ get value of mask
200 and r8, r8, r7 @ apply mask to clear bits
201 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
202 str r8, [r10] @ set up for change.
203 mov r7, #0x4000 @ get val for force
204 orr r8, r8, r7 @ build value for force
205 str r8, [r10] @ Force transition to L1
206
207 ldr r10, omap243x_srs_timer_32ksynct @ get addr of counter
208 ldr r8, [r10] @ get value
209 add r8, r8, #0x2 @ give it at most 62uS (min 31+)
210volt_delay_c:
211 ldr r7, [r10] @ get timer value
212 cmp r8, r7 @ time up?
213 bhi volt_delay_c @ not yet->branch
214 mov pc, lr @ back to caller
215
216omap243x_srs_cm_clksel2_pll:
217 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL2)
218omap243x_srs_sdrc_dlla_ctrl:
219 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
220omap243x_srs_sdrc_rfr_ctrl:
221 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
222omap243x_srs_prcm_voltctrl:
223 .word OMAP243X_PRCM_VOLTCTRL
224ddr_prcm_mask_val:
225 .word 0xFFFF3FFC
226omap243x_srs_timer_32ksynct:
227 .word IO_ADDRESS(OMAP2_32KSYNCT_BASE + 0x010)
228
229ENTRY(omap243x_sram_reprogram_sdrc_sz)
230 .word . - omap243x_sram_reprogram_sdrc
231
232/*
233 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
234 */
235ENTRY(omap243x_sram_set_prcm)
236 stmfd sp!, {r0-r12, lr} @ regs to stack
237 adr r4, pbegin @ addr of preload start
238 adr r8, pend @ addr of preload end
239 mcrr p15, 1, r8, r4, c12 @ preload into icache
240pbegin:
241 /* move into fast relock bypass */
242 ldr r8, omap243x_ssp_pll_ctl @ get addr
243 ldr r5, [r8] @ get val
244 mvn r6, #0x3 @ clear mask
245 and r5, r5, r6 @ clear field
246 orr r7, r5, #0x2 @ fast relock val
247 str r7, [r8] @ go to fast relock
248 ldr r4, omap243x_ssp_pll_stat @ addr of stat
249block:
250 /* wait for bypass */
251 ldr r8, [r4] @ stat value
252 and r8, r8, #0x3 @ mask for stat
253 cmp r8, #0x1 @ there yet
254 bne block @ loop if not
255
256 /* set new dpll dividers _after_ in bypass */
257 ldr r4, omap243x_ssp_pll_div @ get addr
258 str r0, [r4] @ set dpll ctrl val
259
260 ldr r4, omap243x_ssp_set_config @ get addr
261 mov r8, #1 @ valid cfg msk
262 str r8, [r4] @ make dividers take
263
264 mov r4, #100 @ dead spin a bit
265wait_a_bit:
266 subs r4, r4, #1 @ dec loop
267 bne wait_a_bit @ delay done?
268
269 /* check if staying in bypass */
270 cmp r2, #0x1 @ stay in bypass?
271 beq pend @ jump over dpll relock
272
273 /* relock DPLL with new vals */
274 ldr r5, omap243x_ssp_pll_stat @ get addr
275 ldr r4, omap243x_ssp_pll_ctl @ get addr
276 orr r8, r7, #0x3 @ val for lock dpll
277 str r8, [r4] @ set val
278 mov r0, #1000 @ dead spin a bit
279wait_more:
280 subs r0, r0, #1 @ dec loop
281 bne wait_more @ delay done?
282wait_lock:
283 ldr r8, [r5] @ get lock val
284 and r8, r8, #3 @ isolate field
285 cmp r8, #2 @ locked?
286 bne wait_lock @ wait if not
287pend:
288 /* update memory timings & briefly lock dll */
289 ldr r4, omap243x_ssp_sdrc_rfr @ get addr
290 str r1, [r4] @ update refresh timing
291 ldr r11, omap243x_ssp_dlla_ctrl @ get addr of DLLA ctrl
292 ldr r10, [r11] @ get current val
293 mvn r9, #0x4 @ mask to get clear bit2
294 and r10, r10, r9 @ clear bit2 for lock mode
295 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
296 str r10, [r11] @ commit to DLLA_CTRL
297 add r11, r11, #0x8 @ move to dllb
298 str r10, [r11] @ hit DLLB also
299
300 mov r4, #0x800 @ relock time (min 0x400 L3 clocks)
301wait_dll_lock:
302 subs r4, r4, #0x1
303 bne wait_dll_lock
304 nop
305 ldmfd sp!, {r0-r12, pc} @ restore regs and return
306
307omap243x_ssp_set_config:
308 .word OMAP243X_PRCM_CLKCFG_CTRL
309omap243x_ssp_pll_ctl:
310 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKEN)
311omap243x_ssp_pll_stat:
312 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_IDLEST)
313omap243x_ssp_pll_div:
314 .word OMAP2430_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
315omap243x_ssp_sdrc_rfr:
316 .word OMAP243X_SDRC_REGADDR(SDRC_RFR_CTRL_0)
317omap243x_ssp_dlla_ctrl:
318 .word OMAP243X_SDRC_REGADDR(SDRC_DLLA_CTRL)
319
320ENTRY(omap243x_sram_set_prcm_sz)
321 .word . - omap243x_sram_set_prcm
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
index 78d05f203fff..557603f99313 100644
--- a/arch/arm/mach-omap2/timer-gp.c
+++ b/arch/arm/mach-omap2/timer-gp.c
@@ -59,8 +59,7 @@ static struct irqaction omap2_gp_timer_irq = {
59static int omap2_gp_timer_set_next_event(unsigned long cycles, 59static int omap2_gp_timer_set_next_event(unsigned long cycles,
60 struct clock_event_device *evt) 60 struct clock_event_device *evt)
61{ 61{
62 omap_dm_timer_set_load(gptimer, 0, 0xffffffff - cycles); 62 omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
63 omap_dm_timer_start(gptimer);
64 63
65 return 0; 64 return 0;
66} 65}
@@ -77,8 +76,7 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
77 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; 76 period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
78 period -= 1; 77 period -= 1;
79 78
80 omap_dm_timer_set_load(gptimer, 1, 0xffffffff - period); 79 omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
81 omap_dm_timer_start(gptimer);
82 break; 80 break;
83 case CLOCK_EVT_MODE_ONESHOT: 81 case CLOCK_EVT_MODE_ONESHOT:
84 break; 82 break;
@@ -172,8 +170,7 @@ static void __init omap2_gp_clocksource_init(void)
172 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); 170 tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
173 tick_period = (tick_rate / HZ) - 1; 171 tick_period = (tick_rate / HZ) - 1;
174 172
175 omap_dm_timer_set_load(gpt, 1, 0); 173 omap_dm_timer_set_load_start(gpt, 1, 0);
176 omap_dm_timer_start(gpt);
177 174
178 clocksource_gpt.mult = 175 clocksource_gpt.mult =
179 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); 176 clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift);
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 93debf336155..ddcd41b15d17 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -44,6 +44,54 @@ config MACH_LINKSTATION_PRO
44 Buffalo Linkstation Pro/Live platform. Both v1 and 44 Buffalo Linkstation Pro/Live platform. Both v1 and
45 v2 devices are supported. 45 v2 devices are supported.
46 46
47config MACH_TS409
48 bool "QNAP TS-409"
49 help
50 Say 'Y' here if you want your kernel to support the
51 QNAP TS-409 platform.
52
53config MACH_WRT350N_V2
54 bool "Linksys WRT350N v2"
55 help
56 Say 'Y' here if you want your kernel to support the
57 Linksys WRT350N v2 platform.
58
59config MACH_TS78XX
60 bool "Technologic Systems TS-78xx"
61 help
62 Say 'Y' here if you want your kernel to support the
63 Technologic Systems TS-78xx platform.
64
65config MACH_MV2120
66 bool "HP Media Vault mv2120"
67 help
68 Say 'Y' here if you want your kernel to support the
69 HP Media Vault mv2120 or mv5100.
70
71config MACH_MSS2
72 bool "Maxtor Shared Storage II"
73 help
74 Say 'Y' here if you want your kernel to support the
75 Maxtor Shared Storage II platform.
76
77config MACH_WNR854T
78 bool "Netgear WNR854T"
79 help
80 Say 'Y' here if you want your kernel to support the
81 Netgear WNR854T platform.
82
83config MACH_RD88F5181L_GE
84 bool "Marvell Orion-VoIP GE Reference Design"
85 help
86 Say 'Y' here if you want your kernel to support the
87 Marvell Orion-VoIP GE (88F5181L) RD.
88
89config MACH_RD88F5181L_FXO
90 bool "Marvell Orion-VoIP FXO Reference Design"
91 help
92 Say 'Y' here if you want your kernel to support the
93 Marvell Orion-VoIP FXO (88F5181L) RD.
94
47endmenu 95endmenu
48 96
49endif 97endif
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index 9301bf55910b..fcc48a8864f3 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -1,7 +1,15 @@
1obj-y += common.o addr-map.o pci.o gpio.o irq.o 1obj-y += common.o addr-map.o pci.o gpio.o irq.o mpp.o
2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o 2obj-$(CONFIG_MACH_DB88F5281) += db88f5281-setup.o
3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o 3obj-$(CONFIG_MACH_RD88F5182) += rd88f5182-setup.o
4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o 4obj-$(CONFIG_MACH_KUROBOX_PRO) += kurobox_pro-setup.o
5obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o 5obj-$(CONFIG_MACH_LINKSTATION_PRO) += kurobox_pro-setup.o
6obj-$(CONFIG_MACH_DNS323) += dns323-setup.o 6obj-$(CONFIG_MACH_DNS323) += dns323-setup.o
7obj-$(CONFIG_MACH_TS209) += ts209-setup.o 7obj-$(CONFIG_MACH_TS209) += ts209-setup.o tsx09-common.o
8obj-$(CONFIG_MACH_TS409) += ts409-setup.o tsx09-common.o
9obj-$(CONFIG_MACH_WRT350N_V2) += wrt350n-v2-setup.o
10obj-$(CONFIG_MACH_TS78XX) += ts78xx-setup.o
11obj-$(CONFIG_MACH_MV2120) += mv2120-setup.o
12obj-$(CONFIG_MACH_MSS2) += mss2-setup.o
13obj-$(CONFIG_MACH_WNR854T) += wnr854t-setup.o
14obj-$(CONFIG_MACH_RD88F5181L_GE) += rd88f5181l-ge-setup.o
15obj-$(CONFIG_MACH_RD88F5181L_FXO) += rd88f5181l-fxo-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index e63fb05dc893..6f0dbda6c44c 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -70,6 +70,7 @@
70 70
71 71
72struct mbus_dram_target_info orion5x_mbus_dram_info; 72struct mbus_dram_target_info orion5x_mbus_dram_info;
73static int __initdata win_alloc_count;
73 74
74static int __init orion5x_cpu_win_can_remap(int win) 75static int __init orion5x_cpu_win_can_remap(int win)
75{ 76{
@@ -87,16 +88,22 @@ static int __init orion5x_cpu_win_can_remap(int win)
87static void __init setup_cpu_win(int win, u32 base, u32 size, 88static void __init setup_cpu_win(int win, u32 base, u32 size,
88 u8 target, u8 attr, int remap) 89 u8 target, u8 attr, int remap)
89{ 90{
90 orion5x_write(CPU_WIN_BASE(win), base & 0xffff0000); 91 if (win >= 8) {
91 orion5x_write(CPU_WIN_CTRL(win), 92 printk(KERN_ERR "setup_cpu_win: trying to allocate "
92 ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1); 93 "window %d\n", win);
94 return;
95 }
96
97 writel(base & 0xffff0000, CPU_WIN_BASE(win));
98 writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
99 CPU_WIN_CTRL(win));
93 100
94 if (orion5x_cpu_win_can_remap(win)) { 101 if (orion5x_cpu_win_can_remap(win)) {
95 if (remap < 0) 102 if (remap < 0)
96 remap = base; 103 remap = base;
97 104
98 orion5x_write(CPU_WIN_REMAP_LO(win), remap & 0xffff0000); 105 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
99 orion5x_write(CPU_WIN_REMAP_HI(win), 0); 106 writel(0, CPU_WIN_REMAP_HI(win));
100 } 107 }
101} 108}
102 109
@@ -109,11 +116,11 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
109 * First, disable and clear windows. 116 * First, disable and clear windows.
110 */ 117 */
111 for (i = 0; i < 8; i++) { 118 for (i = 0; i < 8; i++) {
112 orion5x_write(CPU_WIN_BASE(i), 0); 119 writel(0, CPU_WIN_BASE(i));
113 orion5x_write(CPU_WIN_CTRL(i), 0); 120 writel(0, CPU_WIN_CTRL(i));
114 if (orion5x_cpu_win_can_remap(i)) { 121 if (orion5x_cpu_win_can_remap(i)) {
115 orion5x_write(CPU_WIN_REMAP_LO(i), 0); 122 writel(0, CPU_WIN_REMAP_LO(i));
116 orion5x_write(CPU_WIN_REMAP_HI(i), 0); 123 writel(0, CPU_WIN_REMAP_HI(i));
117 } 124 }
118 } 125 }
119 126
@@ -128,6 +135,7 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
128 TARGET_PCIE, ATTR_PCIE_MEM, -1); 135 TARGET_PCIE, ATTR_PCIE_MEM, -1);
129 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE, 136 setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
130 TARGET_PCI, ATTR_PCI_MEM, -1); 137 TARGET_PCI, ATTR_PCI_MEM, -1);
138 win_alloc_count = 4;
131 139
132 /* 140 /*
133 * Setup MBUS dram target info. 141 * Setup MBUS dram target info.
@@ -147,8 +155,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
147 w = &orion5x_mbus_dram_info.cs[cs++]; 155 w = &orion5x_mbus_dram_info.cs[cs++];
148 w->cs_index = i; 156 w->cs_index = i;
149 w->mbus_attr = 0xf & ~(1 << i); 157 w->mbus_attr = 0xf & ~(1 << i);
150 w->base = base & 0xff000000; 158 w->base = base & 0xffff0000;
151 w->size = (size | 0x00ffffff) + 1; 159 w->size = (size | 0x0000ffff) + 1;
152 } 160 }
153 } 161 }
154 orion5x_mbus_dram_info.num_cs = cs; 162 orion5x_mbus_dram_info.num_cs = cs;
@@ -156,25 +164,30 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
156 164
157void __init orion5x_setup_dev_boot_win(u32 base, u32 size) 165void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
158{ 166{
159 setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1); 167 setup_cpu_win(win_alloc_count++, base, size,
168 TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
160} 169}
161 170
162void __init orion5x_setup_dev0_win(u32 base, u32 size) 171void __init orion5x_setup_dev0_win(u32 base, u32 size)
163{ 172{
164 setup_cpu_win(5, base, size, TARGET_DEV_BUS, ATTR_DEV_CS0, -1); 173 setup_cpu_win(win_alloc_count++, base, size,
174 TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
165} 175}
166 176
167void __init orion5x_setup_dev1_win(u32 base, u32 size) 177void __init orion5x_setup_dev1_win(u32 base, u32 size)
168{ 178{
169 setup_cpu_win(6, base, size, TARGET_DEV_BUS, ATTR_DEV_CS1, -1); 179 setup_cpu_win(win_alloc_count++, base, size,
180 TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
170} 181}
171 182
172void __init orion5x_setup_dev2_win(u32 base, u32 size) 183void __init orion5x_setup_dev2_win(u32 base, u32 size)
173{ 184{
174 setup_cpu_win(7, base, size, TARGET_DEV_BUS, ATTR_DEV_CS2, -1); 185 setup_cpu_win(win_alloc_count++, base, size,
186 TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
175} 187}
176 188
177void __init orion5x_setup_pcie_wa_win(u32 base, u32 size) 189void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
178{ 190{
179 setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1); 191 setup_cpu_win(win_alloc_count++, base, size,
192 TARGET_PCIE, ATTR_PCIE_WA, -1);
180} 193}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 4f13fd037f04..faf4e3211918 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -39,25 +39,22 @@ static struct map_desc orion5x_io_desc[] __initdata = {
39 .virtual = ORION5X_REGS_VIRT_BASE, 39 .virtual = ORION5X_REGS_VIRT_BASE,
40 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE), 40 .pfn = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
41 .length = ORION5X_REGS_SIZE, 41 .length = ORION5X_REGS_SIZE,
42 .type = MT_DEVICE 42 .type = MT_DEVICE,
43 }, 43 }, {
44 {
45 .virtual = ORION5X_PCIE_IO_VIRT_BASE, 44 .virtual = ORION5X_PCIE_IO_VIRT_BASE,
46 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE), 45 .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
47 .length = ORION5X_PCIE_IO_SIZE, 46 .length = ORION5X_PCIE_IO_SIZE,
48 .type = MT_DEVICE 47 .type = MT_DEVICE,
49 }, 48 }, {
50 {
51 .virtual = ORION5X_PCI_IO_VIRT_BASE, 49 .virtual = ORION5X_PCI_IO_VIRT_BASE,
52 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE), 50 .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
53 .length = ORION5X_PCI_IO_SIZE, 51 .length = ORION5X_PCI_IO_SIZE,
54 .type = MT_DEVICE 52 .type = MT_DEVICE,
55 }, 53 }, {
56 {
57 .virtual = ORION5X_PCIE_WA_VIRT_BASE, 54 .virtual = ORION5X_PCIE_WA_VIRT_BASE,
58 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE), 55 .pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
59 .length = ORION5X_PCIE_WA_SIZE, 56 .length = ORION5X_PCIE_WA_SIZE,
60 .type = MT_DEVICE 57 .type = MT_DEVICE,
61 }, 58 },
62}; 59};
63 60
@@ -66,101 +63,32 @@ void __init orion5x_map_io(void)
66 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc)); 63 iotable_init(orion5x_io_desc, ARRAY_SIZE(orion5x_io_desc));
67} 64}
68 65
66
69/***************************************************************************** 67/*****************************************************************************
70 * UART 68 * EHCI
71 ****************************************************************************/ 69 ****************************************************************************/
72 70static struct orion_ehci_data orion5x_ehci_data = {
73static struct resource orion5x_uart_resources[] = { 71 .dram = &orion5x_mbus_dram_info,
74 {
75 .start = UART0_PHYS_BASE,
76 .end = UART0_PHYS_BASE + 0xff,
77 .flags = IORESOURCE_MEM,
78 },
79 {
80 .start = IRQ_ORION5X_UART0,
81 .end = IRQ_ORION5X_UART0,
82 .flags = IORESOURCE_IRQ,
83 },
84 {
85 .start = UART1_PHYS_BASE,
86 .end = UART1_PHYS_BASE + 0xff,
87 .flags = IORESOURCE_MEM,
88 },
89 {
90 .start = IRQ_ORION5X_UART1,
91 .end = IRQ_ORION5X_UART1,
92 .flags = IORESOURCE_IRQ,
93 },
94};
95
96static struct plat_serial8250_port orion5x_uart_data[] = {
97 {
98 .mapbase = UART0_PHYS_BASE,
99 .membase = (char *)UART0_VIRT_BASE,
100 .irq = IRQ_ORION5X_UART0,
101 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
102 .iotype = UPIO_MEM,
103 .regshift = 2,
104 .uartclk = ORION5X_TCLK,
105 },
106 {
107 .mapbase = UART1_PHYS_BASE,
108 .membase = (char *)UART1_VIRT_BASE,
109 .irq = IRQ_ORION5X_UART1,
110 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
111 .iotype = UPIO_MEM,
112 .regshift = 2,
113 .uartclk = ORION5X_TCLK,
114 },
115 { },
116}; 72};
117 73
118static struct platform_device orion5x_uart = { 74static u64 ehci_dmamask = 0xffffffffUL;
119 .name = "serial8250",
120 .id = PLAT8250_DEV_PLATFORM,
121 .dev = {
122 .platform_data = orion5x_uart_data,
123 },
124 .resource = orion5x_uart_resources,
125 .num_resources = ARRAY_SIZE(orion5x_uart_resources),
126};
127 75
128/*******************************************************************************
129 * USB Controller - 2 interfaces
130 ******************************************************************************/
131 76
77/*****************************************************************************
78 * EHCI0
79 ****************************************************************************/
132static struct resource orion5x_ehci0_resources[] = { 80static struct resource orion5x_ehci0_resources[] = {
133 { 81 {
134 .start = ORION5X_USB0_PHYS_BASE, 82 .start = ORION5X_USB0_PHYS_BASE,
135 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1, 83 .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
136 .flags = IORESOURCE_MEM, 84 .flags = IORESOURCE_MEM,
137 }, 85 }, {
138 {
139 .start = IRQ_ORION5X_USB0_CTRL, 86 .start = IRQ_ORION5X_USB0_CTRL,
140 .end = IRQ_ORION5X_USB0_CTRL, 87 .end = IRQ_ORION5X_USB0_CTRL,
141 .flags = IORESOURCE_IRQ, 88 .flags = IORESOURCE_IRQ,
142 }, 89 },
143}; 90};
144 91
145static struct resource orion5x_ehci1_resources[] = {
146 {
147 .start = ORION5X_USB1_PHYS_BASE,
148 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
149 .flags = IORESOURCE_MEM,
150 },
151 {
152 .start = IRQ_ORION5X_USB1_CTRL,
153 .end = IRQ_ORION5X_USB1_CTRL,
154 .flags = IORESOURCE_IRQ,
155 },
156};
157
158static struct orion_ehci_data orion5x_ehci_data = {
159 .dram = &orion5x_mbus_dram_info,
160};
161
162static u64 ehci_dmamask = 0xffffffffUL;
163
164static struct platform_device orion5x_ehci0 = { 92static struct platform_device orion5x_ehci0 = {
165 .name = "orion-ehci", 93 .name = "orion-ehci",
166 .id = 0, 94 .id = 0,
@@ -173,6 +101,27 @@ static struct platform_device orion5x_ehci0 = {
173 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources), 101 .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
174}; 102};
175 103
104void __init orion5x_ehci0_init(void)
105{
106 platform_device_register(&orion5x_ehci0);
107}
108
109
110/*****************************************************************************
111 * EHCI1
112 ****************************************************************************/
113static struct resource orion5x_ehci1_resources[] = {
114 {
115 .start = ORION5X_USB1_PHYS_BASE,
116 .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
117 .flags = IORESOURCE_MEM,
118 }, {
119 .start = IRQ_ORION5X_USB1_CTRL,
120 .end = IRQ_ORION5X_USB1_CTRL,
121 .flags = IORESOURCE_IRQ,
122 },
123};
124
176static struct platform_device orion5x_ehci1 = { 125static struct platform_device orion5x_ehci1 = {
177 .name = "orion-ehci", 126 .name = "orion-ehci",
178 .id = 1, 127 .id = 1,
@@ -185,11 +134,15 @@ static struct platform_device orion5x_ehci1 = {
185 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources), 134 .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
186}; 135};
187 136
137void __init orion5x_ehci1_init(void)
138{
139 platform_device_register(&orion5x_ehci1);
140}
141
142
188/***************************************************************************** 143/*****************************************************************************
189 * Gigabit Ethernet port 144 * GigE
190 * (The Orion and Discovery (MV643xx) families use the same Ethernet driver)
191 ****************************************************************************/ 145 ****************************************************************************/
192
193struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = { 146struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
194 .dram = &orion5x_mbus_dram_info, 147 .dram = &orion5x_mbus_dram_info,
195 .t_clk = ORION5X_TCLK, 148 .t_clk = ORION5X_TCLK,
@@ -219,7 +172,7 @@ static struct resource orion5x_eth_resources[] = {
219 .start = IRQ_ORION5X_ETH_SUM, 172 .start = IRQ_ORION5X_ETH_SUM,
220 .end = IRQ_ORION5X_ETH_SUM, 173 .end = IRQ_ORION5X_ETH_SUM,
221 .flags = IORESOURCE_IRQ, 174 .flags = IORESOURCE_IRQ,
222 } 175 },
223}; 176};
224 177
225static struct platform_device orion5x_eth = { 178static struct platform_device orion5x_eth = {
@@ -238,11 +191,10 @@ void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
238 platform_device_register(&orion5x_eth); 191 platform_device_register(&orion5x_eth);
239} 192}
240 193
194
241/***************************************************************************** 195/*****************************************************************************
242 * I2C controller 196 * I2C
243 * (The Orion and Discovery (MV643xx) families share the same I2C controller)
244 ****************************************************************************/ 197 ****************************************************************************/
245
246static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = { 198static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
247 .freq_m = 8, /* assumes 166 MHz TCLK */ 199 .freq_m = 8, /* assumes 166 MHz TCLK */
248 .freq_n = 3, 200 .freq_n = 3,
@@ -251,16 +203,15 @@ static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
251 203
252static struct resource orion5x_i2c_resources[] = { 204static struct resource orion5x_i2c_resources[] = {
253 { 205 {
254 .name = "i2c base", 206 .name = "i2c base",
255 .start = I2C_PHYS_BASE, 207 .start = I2C_PHYS_BASE,
256 .end = I2C_PHYS_BASE + 0x20 -1, 208 .end = I2C_PHYS_BASE + 0x1f,
257 .flags = IORESOURCE_MEM, 209 .flags = IORESOURCE_MEM,
258 }, 210 }, {
259 { 211 .name = "i2c irq",
260 .name = "i2c irq", 212 .start = IRQ_ORION5X_I2C,
261 .start = IRQ_ORION5X_I2C, 213 .end = IRQ_ORION5X_I2C,
262 .end = IRQ_ORION5X_I2C, 214 .flags = IORESOURCE_IRQ,
263 .flags = IORESOURCE_IRQ,
264 }, 215 },
265}; 216};
266 217
@@ -270,36 +221,41 @@ static struct platform_device orion5x_i2c = {
270 .num_resources = ARRAY_SIZE(orion5x_i2c_resources), 221 .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
271 .resource = orion5x_i2c_resources, 222 .resource = orion5x_i2c_resources,
272 .dev = { 223 .dev = {
273 .platform_data = &orion5x_i2c_pdata, 224 .platform_data = &orion5x_i2c_pdata,
274 }, 225 },
275}; 226};
276 227
228void __init orion5x_i2c_init(void)
229{
230 platform_device_register(&orion5x_i2c);
231}
232
233
277/***************************************************************************** 234/*****************************************************************************
278 * Sata port 235 * SATA
279 ****************************************************************************/ 236 ****************************************************************************/
280static struct resource orion5x_sata_resources[] = { 237static struct resource orion5x_sata_resources[] = {
281 {
282 .name = "sata base",
283 .start = ORION5X_SATA_PHYS_BASE,
284 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
285 .flags = IORESOURCE_MEM,
286 },
287 { 238 {
288 .name = "sata irq", 239 .name = "sata base",
289 .start = IRQ_ORION5X_SATA, 240 .start = ORION5X_SATA_PHYS_BASE,
290 .end = IRQ_ORION5X_SATA, 241 .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
291 .flags = IORESOURCE_IRQ, 242 .flags = IORESOURCE_MEM,
292 }, 243 }, {
244 .name = "sata irq",
245 .start = IRQ_ORION5X_SATA,
246 .end = IRQ_ORION5X_SATA,
247 .flags = IORESOURCE_IRQ,
248 },
293}; 249};
294 250
295static struct platform_device orion5x_sata = { 251static struct platform_device orion5x_sata = {
296 .name = "sata_mv", 252 .name = "sata_mv",
297 .id = 0, 253 .id = 0,
298 .dev = { 254 .dev = {
299 .coherent_dma_mask = 0xffffffff, 255 .coherent_dma_mask = 0xffffffff,
300 }, 256 },
301 .num_resources = ARRAY_SIZE(orion5x_sata_resources), 257 .num_resources = ARRAY_SIZE(orion5x_sata_resources),
302 .resource = orion5x_sata_resources, 258 .resource = orion5x_sata_resources,
303}; 259};
304 260
305void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data) 261void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
@@ -309,23 +265,111 @@ void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
309 platform_device_register(&orion5x_sata); 265 platform_device_register(&orion5x_sata);
310} 266}
311 267
268
312/***************************************************************************** 269/*****************************************************************************
313 * Time handling 270 * UART0
271 ****************************************************************************/
272static struct plat_serial8250_port orion5x_uart0_data[] = {
273 {
274 .mapbase = UART0_PHYS_BASE,
275 .membase = (char *)UART0_VIRT_BASE,
276 .irq = IRQ_ORION5X_UART0,
277 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
278 .iotype = UPIO_MEM,
279 .regshift = 2,
280 .uartclk = ORION5X_TCLK,
281 }, {
282 },
283};
284
285static struct resource orion5x_uart0_resources[] = {
286 {
287 .start = UART0_PHYS_BASE,
288 .end = UART0_PHYS_BASE + 0xff,
289 .flags = IORESOURCE_MEM,
290 }, {
291 .start = IRQ_ORION5X_UART0,
292 .end = IRQ_ORION5X_UART0,
293 .flags = IORESOURCE_IRQ,
294 },
295};
296
297static struct platform_device orion5x_uart0 = {
298 .name = "serial8250",
299 .id = PLAT8250_DEV_PLATFORM,
300 .dev = {
301 .platform_data = orion5x_uart0_data,
302 },
303 .resource = orion5x_uart0_resources,
304 .num_resources = ARRAY_SIZE(orion5x_uart0_resources),
305};
306
307void __init orion5x_uart0_init(void)
308{
309 platform_device_register(&orion5x_uart0);
310}
311
312
313/*****************************************************************************
314 * UART1
314 ****************************************************************************/ 315 ****************************************************************************/
316static struct plat_serial8250_port orion5x_uart1_data[] = {
317 {
318 .mapbase = UART1_PHYS_BASE,
319 .membase = (char *)UART1_VIRT_BASE,
320 .irq = IRQ_ORION5X_UART1,
321 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
322 .iotype = UPIO_MEM,
323 .regshift = 2,
324 .uartclk = ORION5X_TCLK,
325 }, {
326 },
327};
328
329static struct resource orion5x_uart1_resources[] = {
330 {
331 .start = UART1_PHYS_BASE,
332 .end = UART1_PHYS_BASE + 0xff,
333 .flags = IORESOURCE_MEM,
334 }, {
335 .start = IRQ_ORION5X_UART1,
336 .end = IRQ_ORION5X_UART1,
337 .flags = IORESOURCE_IRQ,
338 },
339};
340
341static struct platform_device orion5x_uart1 = {
342 .name = "serial8250",
343 .id = PLAT8250_DEV_PLATFORM1,
344 .dev = {
345 .platform_data = orion5x_uart1_data,
346 },
347 .resource = orion5x_uart1_resources,
348 .num_resources = ARRAY_SIZE(orion5x_uart1_resources),
349};
350
351void __init orion5x_uart1_init(void)
352{
353 platform_device_register(&orion5x_uart1);
354}
355
315 356
357/*****************************************************************************
358 * Time handling
359 ****************************************************************************/
316static void orion5x_timer_init(void) 360static void orion5x_timer_init(void)
317{ 361{
318 orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK); 362 orion_time_init(IRQ_ORION5X_BRIDGE, ORION5X_TCLK);
319} 363}
320 364
321struct sys_timer orion5x_timer = { 365struct sys_timer orion5x_timer = {
322 .init = orion5x_timer_init, 366 .init = orion5x_timer_init,
323}; 367};
324 368
369
325/***************************************************************************** 370/*****************************************************************************
326 * General 371 * General
327 ****************************************************************************/ 372 ****************************************************************************/
328
329/* 373/*
330 * Identify device ID and rev from PCIe configuration header space '0'. 374 * Identify device ID and rev from PCIe configuration header space '0'.
331 */ 375 */
@@ -350,8 +394,10 @@ static void __init orion5x_id(u32 *dev, u32 *rev, char **dev_name)
350 } else if (*dev == MV88F5181_DEV_ID) { 394 } else if (*dev == MV88F5181_DEV_ID) {
351 if (*rev == MV88F5181_REV_B1) { 395 if (*rev == MV88F5181_REV_B1) {
352 *dev_name = "MV88F5181-Rev-B1"; 396 *dev_name = "MV88F5181-Rev-B1";
397 } else if (*rev == MV88F5181L_REV_A1) {
398 *dev_name = "MV88F5181L-Rev-A1";
353 } else { 399 } else {
354 *dev_name = "MV88F5181-Rev-Unsupported"; 400 *dev_name = "MV88F5181(L)-Rev-Unsupported";
355 } 401 }
356 } else { 402 } else {
357 *dev_name = "Device-Unknown"; 403 *dev_name = "Device-Unknown";
@@ -370,15 +416,6 @@ void __init orion5x_init(void)
370 * Setup Orion address map 416 * Setup Orion address map
371 */ 417 */
372 orion5x_setup_cpu_mbus_bridge(); 418 orion5x_setup_cpu_mbus_bridge();
373
374 /*
375 * Register devices.
376 */
377 platform_device_register(&orion5x_uart);
378 platform_device_register(&orion5x_ehci0);
379 if (dev == MV88F5182_DEV_ID)
380 platform_device_register(&orion5x_ehci1);
381 platform_device_register(&orion5x_i2c);
382} 419}
383 420
384/* 421/*
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index bd0f05de6e18..f72cf0e77544 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -1,10 +1,12 @@
1#ifndef __ARCH_ORION5X_COMMON_H 1#ifndef __ARCH_ORION5X_COMMON_H
2#define __ARCH_ORION5X_COMMON_H 2#define __ARCH_ORION5X_COMMON_H
3 3
4struct mv643xx_eth_platform_data;
5struct mv_sata_platform_data;
6
4/* 7/*
5 * Basic Orion init functions used early by machine-setup. 8 * Basic Orion init functions used early by machine-setup.
6 */ 9 */
7
8void orion5x_map_io(void); 10void orion5x_map_io(void);
9void orion5x_init_irq(void); 11void orion5x_init_irq(void);
10void orion5x_init(void); 12void orion5x_init(void);
@@ -23,15 +25,22 @@ void orion5x_setup_dev1_win(u32 base, u32 size);
23void orion5x_setup_dev2_win(u32 base, u32 size); 25void orion5x_setup_dev2_win(u32 base, u32 size);
24void orion5x_setup_pcie_wa_win(u32 base, u32 size); 26void orion5x_setup_pcie_wa_win(u32 base, u32 size);
25 27
28void orion5x_ehci0_init(void);
29void orion5x_ehci1_init(void);
30void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
31void orion5x_i2c_init(void);
32void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
33void orion5x_uart0_init(void);
34void orion5x_uart1_init(void);
35
26/* 36/*
27 * Shared code used internally by other Orion core functions. 37 * PCIe/PCI functions.
28 * (/mach-orion/pci.c)
29 */ 38 */
30
31struct pci_sys_data;
32struct pci_bus; 39struct pci_bus;
40struct pci_sys_data;
33 41
34void orion5x_pcie_id(u32 *dev, u32 *rev); 42void orion5x_pcie_id(u32 *dev, u32 *rev);
43void orion5x_pci_set_cardbus_mode(void);
35int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys); 44int orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys);
36struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys); 45struct pci_bus *orion5x_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
37int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); 46int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
@@ -40,26 +49,9 @@ int orion5x_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
40 * Valid GPIO pins according to MPP setup, used by machine-setup. 49 * Valid GPIO pins according to MPP setup, used by machine-setup.
41 * (/mach-orion/gpio.c). 50 * (/mach-orion/gpio.c).
42 */ 51 */
43 52void orion5x_gpio_set_valid(unsigned pin, int valid);
44void orion5x_gpio_set_valid_pins(u32 pins);
45void gpio_display(void); /* debug */ 53void gpio_display(void); /* debug */
46 54
47/*
48 * Pull in Orion Ethernet platform_data, used by machine-setup
49 */
50
51struct mv643xx_eth_platform_data;
52
53void orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data);
54
55/*
56 * Orion Sata platform_data, used by machine-setup
57 */
58
59struct mv_sata_platform_data;
60
61void orion5x_sata_init(struct mv_sata_platform_data *sata_data);
62
63struct machine_desc; 55struct machine_desc;
64struct meminfo; 56struct meminfo;
65struct tag; 57struct tag;
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 44c64342dacb..88405e74e5e3 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -27,6 +27,7 @@
27#include <asm/arch/orion5x.h> 27#include <asm/arch/orion5x.h>
28#include <asm/plat-orion/orion_nand.h> 28#include <asm/plat-orion/orion_nand.h>
29#include "common.h" 29#include "common.h"
30#include "mpp.h"
30 31
31/***************************************************************************** 32/*****************************************************************************
32 * DB-88F5281 on board devices 33 * DB-88F5281 on board devices
@@ -86,7 +87,7 @@ static struct platform_device db88f5281_boot_flash = {
86 .name = "physmap-flash", 87 .name = "physmap-flash",
87 .id = 0, 88 .id = 0,
88 .dev = { 89 .dev = {
89 .platform_data = &db88f5281_boot_flash_data, 90 .platform_data = &db88f5281_boot_flash_data,
90 }, 91 },
91 .num_resources = 1, 92 .num_resources = 1,
92 .resource = &db88f5281_boot_flash_resource, 93 .resource = &db88f5281_boot_flash_resource,
@@ -110,7 +111,7 @@ static struct platform_device db88f5281_nor_flash = {
110 .name = "physmap-flash", 111 .name = "physmap-flash",
111 .id = 1, 112 .id = 1,
112 .dev = { 113 .dev = {
113 .platform_data = &db88f5281_nor_flash_data, 114 .platform_data = &db88f5281_nor_flash_data,
114 }, 115 },
115 .num_resources = 1, 116 .num_resources = 1,
116 .resource = &db88f5281_nor_flash_resource, 117 .resource = &db88f5281_nor_flash_resource,
@@ -125,18 +126,15 @@ static struct mtd_partition db88f5281_nand_parts[] = {
125 .name = "kernel", 126 .name = "kernel",
126 .offset = 0, 127 .offset = 0,
127 .size = SZ_2M, 128 .size = SZ_2M,
128 }, 129 }, {
129 {
130 .name = "root", 130 .name = "root",
131 .offset = SZ_2M, 131 .offset = SZ_2M,
132 .size = (SZ_16M - SZ_2M), 132 .size = (SZ_16M - SZ_2M),
133 }, 133 }, {
134 {
135 .name = "user", 134 .name = "user",
136 .offset = SZ_16M, 135 .offset = SZ_16M,
137 .size = SZ_8M, 136 .size = SZ_8M,
138 }, 137 }, {
139 {
140 .name = "recovery", 138 .name = "recovery",
141 .offset = (SZ_16M + SZ_8M), 139 .offset = (SZ_16M + SZ_8M),
142 .size = SZ_8M, 140 .size = SZ_8M,
@@ -288,7 +286,6 @@ subsys_initcall(db88f5281_pci_init);
288 ****************************************************************************/ 286 ****************************************************************************/
289static struct mv643xx_eth_platform_data db88f5281_eth_data = { 287static struct mv643xx_eth_platform_data db88f5281_eth_data = {
290 .phy_addr = 8, 288 .phy_addr = 8,
291 .force_phy_addr = 1,
292}; 289};
293 290
294/***************************************************************************** 291/*****************************************************************************
@@ -301,11 +298,28 @@ static struct i2c_board_info __initdata db88f5281_i2c_rtc = {
301/***************************************************************************** 298/*****************************************************************************
302 * General Setup 299 * General Setup
303 ****************************************************************************/ 300 ****************************************************************************/
304 301static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
305static struct platform_device *db88f5281_devs[] __initdata = { 302 { 0, MPP_GPIO }, /* USB Over Current */
306 &db88f5281_boot_flash, 303 { 1, MPP_GPIO }, /* USB Vbat input */
307 &db88f5281_nor_flash, 304 { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */
308 &db88f5281_nand_flash, 305 { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */
306 { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */
307 { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */
308 { 6, MPP_GPIO }, /* JP0, CON17.2 */
309 { 7, MPP_GPIO }, /* JP1, CON17.1 */
310 { 8, MPP_GPIO }, /* JP2, CON11.2 */
311 { 9, MPP_GPIO }, /* JP3, CON11.3 */
312 { 10, MPP_GPIO }, /* RTC int */
313 { 11, MPP_GPIO }, /* Baud Rate Generator */
314 { 12, MPP_GPIO }, /* PCI int 1 */
315 { 13, MPP_GPIO }, /* PCI int 2 */
316 { 14, MPP_NAND }, /* NAND_REn[2] */
317 { 15, MPP_NAND }, /* NAND_WEn[2] */
318 { 16, MPP_UART }, /* UART1_RX */
319 { 17, MPP_UART }, /* UART1_TX */
320 { 18, MPP_UART }, /* UART1_CTSn */
321 { 19, MPP_UART }, /* UART1_RTSn */
322 { -1 },
309}; 323};
310 324
311static void __init db88f5281_init(void) 325static void __init db88f5281_init(void)
@@ -315,39 +329,31 @@ static void __init db88f5281_init(void)
315 */ 329 */
316 orion5x_init(); 330 orion5x_init();
317 331
332 orion5x_mpp_conf(db88f5281_mpp_modes);
333 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
334
318 /* 335 /*
319 * Setup the CPU address decode windows for our on-board devices 336 * Configure peripherals.
320 */ 337 */
338 orion5x_ehci0_init();
339 orion5x_eth_init(&db88f5281_eth_data);
340 orion5x_i2c_init();
341 orion5x_uart0_init();
342 orion5x_uart1_init();
343
321 orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE, 344 orion5x_setup_dev_boot_win(DB88F5281_NOR_BOOT_BASE,
322 DB88F5281_NOR_BOOT_SIZE); 345 DB88F5281_NOR_BOOT_SIZE);
346 platform_device_register(&db88f5281_boot_flash);
347
323 orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE); 348 orion5x_setup_dev0_win(DB88F5281_7SEG_BASE, DB88F5281_7SEG_SIZE);
324 orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
325 orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
326 349
327 /* 350 orion5x_setup_dev1_win(DB88F5281_NOR_BASE, DB88F5281_NOR_SIZE);
328 * Setup Multiplexing Pins: 351 platform_device_register(&db88f5281_nor_flash);
329 * MPP0: GPIO (USB Over Current) MPP1: GPIO (USB Vbat input)
330 * MPP2: PCI_REQn[2] MPP3: PCI_GNTn[2]
331 * MPP4: PCI_REQn[3] MPP5: PCI_GNTn[3]
332 * MPP6: GPIO (JP0, CON17.2) MPP7: GPIO (JP1, CON17.1)
333 * MPP8: GPIO (JP2, CON11.2) MPP9: GPIO (JP3, CON11.3)
334 * MPP10: GPIO (RTC int) MPP11: GPIO (Baud Rate Generator)
335 * MPP12: GPIO (PCI int 1) MPP13: GPIO (PCI int 2)
336 * MPP14: NAND_REn[2] MPP15: NAND_WEn[2]
337 * MPP16: UART1_RX MPP17: UART1_TX
338 * MPP18: UART1_CTS MPP19: UART1_RTS
339 * MPP-DEV: DEV_D[16:31]
340 */
341 orion5x_write(MPP_0_7_CTRL, 0x00222203);
342 orion5x_write(MPP_8_15_CTRL, 0x44000000);
343 orion5x_write(MPP_16_19_CTRL, 0);
344 orion5x_write(MPP_DEV_CTRL, 0);
345 352
346 orion5x_gpio_set_valid_pins(0x00003fc3); 353 orion5x_setup_dev2_win(DB88F5281_NAND_BASE, DB88F5281_NAND_SIZE);
354 platform_device_register(&db88f5281_nand_flash);
347 355
348 platform_add_devices(db88f5281_devs, ARRAY_SIZE(db88f5281_devs));
349 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1); 356 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
350 orion5x_eth_init(&db88f5281_eth_data);
351} 357}
352 358
353MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 359MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 27ce967ab9e5..3791ca6f001a 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -27,6 +27,7 @@
27#include <asm/mach/pci.h> 27#include <asm/mach/pci.h>
28#include <asm/arch/orion5x.h> 28#include <asm/arch/orion5x.h>
29#include "common.h" 29#include "common.h"
30#include "mpp.h"
30 31
31#define DNS323_GPIO_LED_RIGHT_AMBER 1 32#define DNS323_GPIO_LED_RIGHT_AMBER 1
32#define DNS323_GPIO_LED_LEFT_AMBER 2 33#define DNS323_GPIO_LED_LEFT_AMBER 2
@@ -52,8 +53,6 @@ static int __init dns323_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
52 if (irq != -1) 53 if (irq != -1)
53 return irq; 54 return irq;
54 55
55 pr_err("%s: requested mapping for unknown device\n", __func__);
56
57 return -1; 56 return -1;
58} 57}
59 58
@@ -81,7 +80,6 @@ subsys_initcall(dns323_pci_init);
81 80
82static struct mv643xx_eth_platform_data dns323_eth_data = { 81static struct mv643xx_eth_platform_data dns323_eth_data = {
83 .phy_addr = 8, 82 .phy_addr = 8,
84 .force_phy_addr = 1,
85}; 83};
86 84
87/**************************************************************************** 85/****************************************************************************
@@ -119,7 +117,7 @@ static struct mtd_partition dns323_partitions[] = {
119 .name = "u-boot", 117 .name = "u-boot",
120 .size = 0x00030000, 118 .size = 0x00030000,
121 .offset = 0x007d0000, 119 .offset = 0x007d0000,
122 } 120 },
123}; 121};
124 122
125static struct physmap_flash_data dns323_nor_flash_data = { 123static struct physmap_flash_data dns323_nor_flash_data = {
@@ -137,7 +135,9 @@ static struct resource dns323_nor_flash_resource = {
137static struct platform_device dns323_nor_flash = { 135static struct platform_device dns323_nor_flash = {
138 .name = "physmap-flash", 136 .name = "physmap-flash",
139 .id = 0, 137 .id = 0,
140 .dev = { .platform_data = &dns323_nor_flash_data, }, 138 .dev = {
139 .platform_data = &dns323_nor_flash_data,
140 },
141 .resource = &dns323_nor_flash_resource, 141 .resource = &dns323_nor_flash_resource,
142 .num_resources = 1, 142 .num_resources = 1,
143}; 143};
@@ -170,7 +170,9 @@ static struct gpio_led_platform_data dns323_led_data = {
170static struct platform_device dns323_gpio_leds = { 170static struct platform_device dns323_gpio_leds = {
171 .name = "leds-gpio", 171 .name = "leds-gpio",
172 .id = -1, 172 .id = -1,
173 .dev = { .platform_data = &dns323_led_data, }, 173 .dev = {
174 .platform_data = &dns323_led_data,
175 },
174}; 176};
175 177
176/**************************************************************************** 178/****************************************************************************
@@ -183,35 +185,53 @@ static struct gpio_keys_button dns323_buttons[] = {
183 .gpio = DNS323_GPIO_KEY_RESET, 185 .gpio = DNS323_GPIO_KEY_RESET,
184 .desc = "Reset Button", 186 .desc = "Reset Button",
185 .active_low = 1, 187 .active_low = 1,
186 }, 188 }, {
187 {
188 .code = KEY_POWER, 189 .code = KEY_POWER,
189 .gpio = DNS323_GPIO_KEY_POWER, 190 .gpio = DNS323_GPIO_KEY_POWER,
190 .desc = "Power Button", 191 .desc = "Power Button",
191 .active_low = 1, 192 .active_low = 1,
192 } 193 },
193}; 194};
194 195
195static struct gpio_keys_platform_data dns323_button_data = { 196static struct gpio_keys_platform_data dns323_button_data = {
196 .buttons = dns323_buttons, 197 .buttons = dns323_buttons,
197 .nbuttons = ARRAY_SIZE(dns323_buttons), 198 .nbuttons = ARRAY_SIZE(dns323_buttons),
198}; 199};
199 200
200static struct platform_device dns323_button_device = { 201static struct platform_device dns323_button_device = {
201 .name = "gpio-keys", 202 .name = "gpio-keys",
202 .id = -1, 203 .id = -1,
203 .num_resources = 0, 204 .num_resources = 0,
204 .dev = { .platform_data = &dns323_button_data, }, 205 .dev = {
206 .platform_data = &dns323_button_data,
207 },
205}; 208};
206 209
207/**************************************************************************** 210/****************************************************************************
208 * General Setup 211 * General Setup
209 */ 212 */
210 213static struct orion5x_mpp_mode dns323_mpp_modes[] __initdata = {
211static struct platform_device *dns323_plat_devices[] __initdata = { 214 { 0, MPP_PCIE_RST_OUTn },
212 &dns323_nor_flash, 215 { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
213 &dns323_gpio_leds, 216 { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
214 &dns323_button_device, 217 { 3, MPP_UNUSED },
218 { 4, MPP_GPIO }, /* power button LED */
219 { 5, MPP_GPIO }, /* power button LED */
220 { 6, MPP_GPIO }, /* GMT G751-2f overtemp */
221 { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
222 { 8, MPP_GPIO }, /* triggers power off */
223 { 9, MPP_GPIO }, /* power button switch */
224 { 10, MPP_GPIO }, /* reset button switch */
225 { 11, MPP_UNUSED },
226 { 12, MPP_UNUSED },
227 { 13, MPP_UNUSED },
228 { 14, MPP_UNUSED },
229 { 15, MPP_UNUSED },
230 { 16, MPP_UNUSED },
231 { 17, MPP_UNUSED },
232 { 18, MPP_UNUSED },
233 { 19, MPP_UNUSED },
234 { -1 },
215}; 235};
216 236
217/* 237/*
@@ -225,17 +245,15 @@ static struct platform_device *dns323_plat_devices[] __initdata = {
225static struct i2c_board_info __initdata dns323_i2c_devices[] = { 245static struct i2c_board_info __initdata dns323_i2c_devices[] = {
226 { 246 {
227 I2C_BOARD_INFO("g760a", 0x3e), 247 I2C_BOARD_INFO("g760a", 0x3e),
228 },
229#if 0 248#if 0
230 /* this entry requires the new-style driver model lm75 driver, 249 /* this entry requires the new-style driver model lm75 driver,
231 * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */ 250 * for the meantime "insmod lm75.ko force_lm75=0,0x48" is needed */
232 { 251 }, {
233 I2C_BOARD_INFO("g751", 0x48), 252 I2C_BOARD_INFO("g751", 0x48),
234 },
235#endif 253#endif
236 { 254 }, {
237 I2C_BOARD_INFO("m41t80", 0x68), 255 I2C_BOARD_INFO("m41t80", 0x68),
238 } 256 },
239}; 257};
240 258
241/* DNS-323 specific power off method */ 259/* DNS-323 specific power off method */
@@ -250,62 +268,35 @@ static void __init dns323_init(void)
250 /* Setup basic Orion functions. Need to be called early. */ 268 /* Setup basic Orion functions. Need to be called early. */
251 orion5x_init(); 269 orion5x_init();
252 270
271 orion5x_mpp_conf(dns323_mpp_modes);
272 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
273
274 /*
275 * Configure peripherals.
276 */
277 orion5x_ehci0_init();
278 orion5x_eth_init(&dns323_eth_data);
279 orion5x_i2c_init();
280 orion5x_uart0_init();
281
253 /* setup flash mapping 282 /* setup flash mapping
254 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4 283 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
255 */ 284 */
256 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE); 285 orion5x_setup_dev_boot_win(DNS323_NOR_BOOT_BASE, DNS323_NOR_BOOT_SIZE);
286 platform_device_register(&dns323_nor_flash);
257 287
258 /* DNS-323 has a Marvell 88X7042 SATA controller attached via PCIe 288 platform_device_register(&dns323_gpio_leds);
259 *
260 * Open a special address decode windows for the PCIe WA.
261 */
262 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
263 ORION5X_PCIE_WA_SIZE);
264
265 /* set MPP to 0 as D-Link's 2.6.12.6 kernel did */
266 orion5x_write(MPP_0_7_CTRL, 0);
267 orion5x_write(MPP_8_15_CTRL, 0);
268 orion5x_write(MPP_16_19_CTRL, 0);
269 orion5x_write(MPP_DEV_CTRL, 0);
270
271 /* Define used GPIO pins
272
273 GPIO Map:
274
275 | 0 | | PEX_RST_OUT (not controlled by GPIO)
276 | 1 | Out | right amber LED (= sata ch0 LED) (low-active)
277 | 2 | Out | left amber LED (= sata ch1 LED) (low-active)
278 | 3 | Out | //unknown//
279 | 4 | Out | power button LED (low-active, together with pin #5)
280 | 5 | Out | power button LED (low-active, together with pin #4)
281 | 6 | In | GMT G751-2f overtemp. shutdown signal (low-active)
282 | 7 | In | M41T80 nIRQ/OUT/SQW signal
283 | 8 | Out | triggers power off (high-active)
284 | 9 | In | power button switch (low-active)
285 | 10 | In | reset button switch (low-active)
286 | 11 | Out | //unknown//
287 | 12 | Out | //unknown//
288 | 13 | Out | //unknown//
289 | 14 | Out | //unknown//
290 | 15 | Out | //unknown//
291 */
292 orion5x_gpio_set_valid_pins(0x07f6);
293
294 /* register dns323 specific power-off method */
295 if ((gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0)
296 || (gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0))
297 pr_err("DNS323: failed to setup power-off GPIO\n");
298
299 pm_power_off = dns323_power_off;
300 289
301 /* register flash and other platform devices */ 290 platform_device_register(&dns323_button_device);
302 platform_add_devices(dns323_plat_devices,
303 ARRAY_SIZE(dns323_plat_devices));
304 291
305 i2c_register_board_info(0, dns323_i2c_devices, 292 i2c_register_board_info(0, dns323_i2c_devices,
306 ARRAY_SIZE(dns323_i2c_devices)); 293 ARRAY_SIZE(dns323_i2c_devices));
307 294
308 orion5x_eth_init(&dns323_eth_data); 295 /* register dns323 specific power-off method */
296 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
297 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
298 pr_err("DNS323: failed to setup power-off GPIO\n");
299 pm_power_off = dns323_power_off;
309} 300}
310 301
311/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 302/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
diff --git a/arch/arm/mach-orion5x/gpio.c b/arch/arm/mach-orion5x/gpio.c
index 8108c316c426..d09797990f41 100644
--- a/arch/arm/mach-orion5x/gpio.c
+++ b/arch/arm/mach-orion5x/gpio.c
@@ -24,9 +24,12 @@ static DEFINE_SPINLOCK(gpio_lock);
24static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)]; 24static unsigned long gpio_valid[BITS_TO_LONGS(GPIO_MAX)];
25static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */ 25static const char *gpio_label[GPIO_MAX]; /* non null for allocated GPIOs */
26 26
27void __init orion5x_gpio_set_valid_pins(u32 pins) 27void __init orion5x_gpio_set_valid(unsigned pin, int valid)
28{ 28{
29 gpio_valid[0] = pins; 29 if (valid)
30 __set_bit(pin, gpio_valid);
31 else
32 __clear_bit(pin, gpio_valid);
30} 33}
31 34
32/* 35/*
@@ -93,10 +96,10 @@ int gpio_get_value(unsigned pin)
93{ 96{
94 int val, mask = 1 << pin; 97 int val, mask = 1 << pin;
95 98
96 if (orion5x_read(GPIO_IO_CONF) & mask) 99 if (readl(GPIO_IO_CONF) & mask)
97 val = orion5x_read(GPIO_DATA_IN) ^ orion5x_read(GPIO_IN_POL); 100 val = readl(GPIO_DATA_IN) ^ readl(GPIO_IN_POL);
98 else 101 else
99 val = orion5x_read(GPIO_OUT); 102 val = readl(GPIO_OUT);
100 103
101 return val & mask; 104 return val & mask;
102} 105}
@@ -188,39 +191,39 @@ void gpio_display(void)
188 printk("GPIO, free\n"); 191 printk("GPIO, free\n");
189 } else { 192 } else {
190 printk("GPIO, used by %s, ", gpio_label[i]); 193 printk("GPIO, used by %s, ", gpio_label[i]);
191 if (orion5x_read(GPIO_IO_CONF) & (1 << i)) { 194 if (readl(GPIO_IO_CONF) & (1 << i)) {
192 printk("input, active %s, level %s, edge %s\n", 195 printk("input, active %s, level %s, edge %s\n",
193 ((orion5x_read(GPIO_IN_POL) >> i) & 1) ? "low" : "high", 196 ((readl(GPIO_IN_POL) >> i) & 1) ? "low" : "high",
194 ((orion5x_read(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked", 197 ((readl(GPIO_LEVEL_MASK) >> i) & 1) ? "enabled" : "masked",
195 ((orion5x_read(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked"); 198 ((readl(GPIO_EDGE_MASK) >> i) & 1) ? "enabled" : "masked");
196 } else { 199 } else {
197 printk("output, val=%d\n", (orion5x_read(GPIO_OUT) >> i) & 1); 200 printk("output, val=%d\n", (readl(GPIO_OUT) >> i) & 1);
198 } 201 }
199 } 202 }
200 } 203 }
201 204
202 printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n", 205 printk(KERN_DEBUG "MPP_0_7_CTRL (0x%08x) = 0x%08x\n",
203 MPP_0_7_CTRL, orion5x_read(MPP_0_7_CTRL)); 206 MPP_0_7_CTRL, readl(MPP_0_7_CTRL));
204 printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n", 207 printk(KERN_DEBUG "MPP_8_15_CTRL (0x%08x) = 0x%08x\n",
205 MPP_8_15_CTRL, orion5x_read(MPP_8_15_CTRL)); 208 MPP_8_15_CTRL, readl(MPP_8_15_CTRL));
206 printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n", 209 printk(KERN_DEBUG "MPP_16_19_CTRL (0x%08x) = 0x%08x\n",
207 MPP_16_19_CTRL, orion5x_read(MPP_16_19_CTRL)); 210 MPP_16_19_CTRL, readl(MPP_16_19_CTRL));
208 printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n", 211 printk(KERN_DEBUG "MPP_DEV_CTRL (0x%08x) = 0x%08x\n",
209 MPP_DEV_CTRL, orion5x_read(MPP_DEV_CTRL)); 212 MPP_DEV_CTRL, readl(MPP_DEV_CTRL));
210 printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n", 213 printk(KERN_DEBUG "GPIO_OUT (0x%08x) = 0x%08x\n",
211 GPIO_OUT, orion5x_read(GPIO_OUT)); 214 GPIO_OUT, readl(GPIO_OUT));
212 printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n", 215 printk(KERN_DEBUG "GPIO_IO_CONF (0x%08x) = 0x%08x\n",
213 GPIO_IO_CONF, orion5x_read(GPIO_IO_CONF)); 216 GPIO_IO_CONF, readl(GPIO_IO_CONF));
214 printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n", 217 printk(KERN_DEBUG "GPIO_BLINK_EN (0x%08x) = 0x%08x\n",
215 GPIO_BLINK_EN, orion5x_read(GPIO_BLINK_EN)); 218 GPIO_BLINK_EN, readl(GPIO_BLINK_EN));
216 printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n", 219 printk(KERN_DEBUG "GPIO_IN_POL (0x%08x) = 0x%08x\n",
217 GPIO_IN_POL, orion5x_read(GPIO_IN_POL)); 220 GPIO_IN_POL, readl(GPIO_IN_POL));
218 printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n", 221 printk(KERN_DEBUG "GPIO_DATA_IN (0x%08x) = 0x%08x\n",
219 GPIO_DATA_IN, orion5x_read(GPIO_DATA_IN)); 222 GPIO_DATA_IN, readl(GPIO_DATA_IN));
220 printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n", 223 printk(KERN_DEBUG "GPIO_LEVEL_MASK (0x%08x) = 0x%08x\n",
221 GPIO_LEVEL_MASK, orion5x_read(GPIO_LEVEL_MASK)); 224 GPIO_LEVEL_MASK, readl(GPIO_LEVEL_MASK));
222 printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n", 225 printk(KERN_DEBUG "GPIO_EDGE_CAUSE (0x%08x) = 0x%08x\n",
223 GPIO_EDGE_CAUSE, orion5x_read(GPIO_EDGE_CAUSE)); 226 GPIO_EDGE_CAUSE, readl(GPIO_EDGE_CAUSE));
224 printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n", 227 printk(KERN_DEBUG "GPIO_EDGE_MASK (0x%08x) = 0x%08x\n",
225 GPIO_EDGE_MASK, orion5x_read(GPIO_EDGE_MASK)); 228 GPIO_EDGE_MASK, readl(GPIO_EDGE_MASK));
226} 229}
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index dd21f38c5d37..e2a0084ab4a3 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -82,7 +82,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
82 int pin = irq_to_gpio(irq); 82 int pin = irq_to_gpio(irq);
83 struct irq_desc *desc; 83 struct irq_desc *desc;
84 84
85 if ((orion5x_read(GPIO_IO_CONF) & (1 << pin)) == 0) { 85 if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
86 printk(KERN_ERR "orion5x_gpio_set_irq_type failed " 86 printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
87 "(irq %d, pin %d).\n", irq, pin); 87 "(irq %d, pin %d).\n", irq, pin);
88 return -EINVAL; 88 return -EINVAL;
@@ -117,7 +117,7 @@ static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
117 /* 117 /*
118 * set initial polarity based on current input level 118 * set initial polarity based on current input level
119 */ 119 */
120 if ((orion5x_read(GPIO_IN_POL) ^ orion5x_read(GPIO_DATA_IN)) 120 if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
121 & (1 << pin)) 121 & (1 << pin))
122 orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */ 122 orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
123 else 123 else
@@ -149,8 +149,8 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
149 149
150 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31); 150 BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
151 offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8; 151 offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
152 cause = (orion5x_read(GPIO_DATA_IN) & orion5x_read(GPIO_LEVEL_MASK)) | 152 cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
153 (orion5x_read(GPIO_EDGE_CAUSE) & orion5x_read(GPIO_EDGE_MASK)); 153 (readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
154 154
155 for (pin = offs; pin < offs + 8; pin++) { 155 for (pin = offs; pin < offs + 8; pin++) {
156 if (cause & (1 << pin)) { 156 if (cause & (1 << pin)) {
@@ -158,9 +158,9 @@ static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
158 desc = irq_desc + irq; 158 desc = irq_desc + irq;
159 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) { 159 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
160 /* Swap polarity (race with GPIO line) */ 160 /* Swap polarity (race with GPIO line) */
161 u32 polarity = orion5x_read(GPIO_IN_POL); 161 u32 polarity = readl(GPIO_IN_POL);
162 polarity ^= 1 << pin; 162 polarity ^= 1 << pin;
163 orion5x_write(GPIO_IN_POL, polarity); 163 writel(polarity, GPIO_IN_POL);
164 } 164 }
165 desc_handle_irq(irq, desc); 165 desc_handle_irq(irq, desc);
166 } 166 }
@@ -175,9 +175,9 @@ static void __init orion5x_init_gpio_irq(void)
175 /* 175 /*
176 * Mask and clear GPIO IRQ interrupts 176 * Mask and clear GPIO IRQ interrupts
177 */ 177 */
178 orion5x_write(GPIO_LEVEL_MASK, 0x0); 178 writel(0x0, GPIO_LEVEL_MASK);
179 orion5x_write(GPIO_EDGE_MASK, 0x0); 179 writel(0x0, GPIO_EDGE_MASK);
180 orion5x_write(GPIO_EDGE_CAUSE, 0x0); 180 writel(0x0, GPIO_EDGE_CAUSE);
181 181
182 /* 182 /*
183 * Register chained level handlers for GPIO IRQs by default. 183 * Register chained level handlers for GPIO IRQs by default.
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index f5074b877b7f..84feac4a1fe2 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -13,10 +13,12 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/pci.h> 14#include <linux/pci.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/delay.h>
16#include <linux/mtd/physmap.h> 17#include <linux/mtd/physmap.h>
17#include <linux/mtd/nand.h> 18#include <linux/mtd/nand.h>
18#include <linux/mv643xx_eth.h> 19#include <linux/mv643xx_eth.h>
19#include <linux/i2c.h> 20#include <linux/i2c.h>
21#include <linux/serial_reg.h>
20#include <linux/ata_platform.h> 22#include <linux/ata_platform.h>
21#include <asm/mach-types.h> 23#include <asm/mach-types.h>
22#include <asm/gpio.h> 24#include <asm/gpio.h>
@@ -25,6 +27,7 @@
25#include <asm/arch/orion5x.h> 27#include <asm/arch/orion5x.h>
26#include <asm/plat-orion/orion_nand.h> 28#include <asm/plat-orion/orion_nand.h>
27#include "common.h" 29#include "common.h"
30#include "mpp.h"
28 31
29/***************************************************************************** 32/*****************************************************************************
30 * KUROBOX-PRO Info 33 * KUROBOX-PRO Info
@@ -53,13 +56,11 @@ static struct mtd_partition kurobox_pro_nand_parts[] = {
53 .name = "uImage", 56 .name = "uImage",
54 .offset = 0, 57 .offset = 0,
55 .size = SZ_4M, 58 .size = SZ_4M,
56 }, 59 }, {
57 {
58 .name = "rootfs", 60 .name = "rootfs",
59 .offset = SZ_4M, 61 .offset = SZ_4M,
60 .size = SZ_64M, 62 .size = SZ_64M,
61 }, 63 }, {
62 {
63 .name = "extra", 64 .name = "extra",
64 .offset = SZ_4M + SZ_64M, 65 .offset = SZ_4M + SZ_64M,
65 .size = SZ_256M - (SZ_4M + SZ_64M), 66 .size = SZ_256M - (SZ_4M + SZ_64M),
@@ -132,8 +133,6 @@ static int __init kurobox_pro_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
132 /* 133 /*
133 * PCI isn't used on the Kuro 134 * PCI isn't used on the Kuro
134 */ 135 */
135 printk(KERN_ERR "kurobox_pro_pci_map_irq failed, unknown bus\n");
136
137 return -1; 136 return -1;
138} 137}
139 138
@@ -161,7 +160,6 @@ subsys_initcall(kurobox_pro_pci_init);
161 160
162static struct mv643xx_eth_platform_data kurobox_pro_eth_data = { 161static struct mv643xx_eth_platform_data kurobox_pro_eth_data = {
163 .phy_addr = 8, 162 .phy_addr = 8,
164 .force_phy_addr = 1,
165}; 163};
166 164
167/***************************************************************************** 165/*****************************************************************************
@@ -175,12 +173,169 @@ static struct i2c_board_info __initdata kurobox_pro_i2c_rtc = {
175 * SATA 173 * SATA
176 ****************************************************************************/ 174 ****************************************************************************/
177static struct mv_sata_platform_data kurobox_pro_sata_data = { 175static struct mv_sata_platform_data kurobox_pro_sata_data = {
178 .n_ports = 2, 176 .n_ports = 2,
179}; 177};
180 178
181/***************************************************************************** 179/*****************************************************************************
180 * Kurobox Pro specific power off method via UART1-attached microcontroller
181 ****************************************************************************/
182
183#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
184
185static int kurobox_pro_miconread(unsigned char *buf, int count)
186{
187 int i;
188 int timeout;
189
190 for (i = 0; i < count; i++) {
191 timeout = 10;
192
193 while (!(readl(UART1_REG(LSR)) & UART_LSR_DR)) {
194 if (--timeout == 0)
195 break;
196 udelay(1000);
197 }
198
199 if (timeout == 0)
200 break;
201 buf[i] = readl(UART1_REG(RX));
202 }
203
204 /* return read bytes */
205 return i;
206}
207
208static int kurobox_pro_miconwrite(const unsigned char *buf, int count)
209{
210 int i = 0;
211
212 while (count--) {
213 while (!(readl(UART1_REG(LSR)) & UART_LSR_THRE))
214 barrier();
215 writel(buf[i++], UART1_REG(TX));
216 }
217
218 return 0;
219}
220
221static int kurobox_pro_miconsend(const unsigned char *data, int count)
222{
223 int i;
224 unsigned char checksum = 0;
225 unsigned char recv_buf[40];
226 unsigned char send_buf[40];
227 unsigned char correct_ack[3];
228 int retry = 2;
229
230 /* Generate checksum */
231 for (i = 0; i < count; i++)
232 checksum -= data[i];
233
234 do {
235 /* Send data */
236 kurobox_pro_miconwrite(data, count);
237
238 /* send checksum */
239 kurobox_pro_miconwrite(&checksum, 1);
240
241 if (kurobox_pro_miconread(recv_buf, sizeof(recv_buf)) <= 3) {
242 printk(KERN_ERR ">%s: receive failed.\n", __func__);
243
244 /* send preamble to clear the receive buffer */
245 memset(&send_buf, 0xff, sizeof(send_buf));
246 kurobox_pro_miconwrite(send_buf, sizeof(send_buf));
247
248 /* make dummy reads */
249 mdelay(100);
250 kurobox_pro_miconread(recv_buf, sizeof(recv_buf));
251 } else {
252 /* Generate expected ack */
253 correct_ack[0] = 0x01;
254 correct_ack[1] = data[1];
255 correct_ack[2] = 0x00;
256
257 /* checksum Check */
258 if ((recv_buf[0] + recv_buf[1] + recv_buf[2] +
259 recv_buf[3]) & 0xFF) {
260 printk(KERN_ERR ">%s: Checksum Error : "
261 "Received data[%02x, %02x, %02x, %02x]"
262 "\n", __func__, recv_buf[0],
263 recv_buf[1], recv_buf[2], recv_buf[3]);
264 } else {
265 /* Check Received Data */
266 if (correct_ack[0] == recv_buf[0] &&
267 correct_ack[1] == recv_buf[1] &&
268 correct_ack[2] == recv_buf[2]) {
269 /* Interval for next command */
270 mdelay(10);
271
272 /* Receive ACK */
273 return 0;
274 }
275 }
276 /* Received NAK or illegal Data */
277 printk(KERN_ERR ">%s: Error : NAK or Illegal Data "
278 "Received\n", __func__);
279 }
280 } while (retry--);
281
282 /* Interval for next command */
283 mdelay(10);
284
285 return -1;
286}
287
288static void kurobox_pro_power_off(void)
289{
290 const unsigned char watchdogkill[] = {0x01, 0x35, 0x00};
291 const unsigned char shutdownwait[] = {0x00, 0x0c};
292 const unsigned char poweroff[] = {0x00, 0x06};
293 /* 38400 baud divisor */
294 const unsigned divisor = ((ORION5X_TCLK + (8 * 38400)) / (16 * 38400));
295
296 pr_info("%s: triggering power-off...\n", __func__);
297
298 /* hijack uart1 and reset into sane state (38400,8n1,even parity) */
299 writel(0x83, UART1_REG(LCR));
300 writel(divisor & 0xff, UART1_REG(DLL));
301 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
302 writel(0x1b, UART1_REG(LCR));
303 writel(0x00, UART1_REG(IER));
304 writel(0x07, UART1_REG(FCR));
305 writel(0x00, UART1_REG(MCR));
306
307 /* Send the commands to shutdown the Kurobox Pro */
308 kurobox_pro_miconsend(watchdogkill, sizeof(watchdogkill)) ;
309 kurobox_pro_miconsend(shutdownwait, sizeof(shutdownwait)) ;
310 kurobox_pro_miconsend(poweroff, sizeof(poweroff));
311}
312
313/*****************************************************************************
182 * General Setup 314 * General Setup
183 ****************************************************************************/ 315 ****************************************************************************/
316static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
317 { 0, MPP_UNUSED },
318 { 1, MPP_UNUSED },
319 { 2, MPP_GPIO }, /* GPIO Micon */
320 { 3, MPP_GPIO }, /* GPIO Rtc */
321 { 4, MPP_UNUSED },
322 { 5, MPP_UNUSED },
323 { 6, MPP_NAND }, /* NAND Flash REn */
324 { 7, MPP_NAND }, /* NAND Flash WEn */
325 { 8, MPP_UNUSED },
326 { 9, MPP_UNUSED },
327 { 10, MPP_UNUSED },
328 { 11, MPP_UNUSED },
329 { 12, MPP_SATA_LED }, /* SATA 0 presence */
330 { 13, MPP_SATA_LED }, /* SATA 1 presence */
331 { 14, MPP_SATA_LED }, /* SATA 0 active */
332 { 15, MPP_SATA_LED }, /* SATA 1 active */
333 { 16, MPP_UART }, /* UART1 RXD */
334 { 17, MPP_UART }, /* UART1 TXD */
335 { 18, MPP_UART }, /* UART1 CTSn */
336 { 19, MPP_UART }, /* UART1 RTSn */
337 { -1 },
338};
184 339
185static void __init kurobox_pro_init(void) 340static void __init kurobox_pro_init(void)
186{ 341{
@@ -189,46 +344,33 @@ static void __init kurobox_pro_init(void)
189 */ 344 */
190 orion5x_init(); 345 orion5x_init();
191 346
192 /* 347 orion5x_mpp_conf(kurobox_pro_mpp_modes);
193 * Setup the CPU address decode windows for our devices
194 */
195 orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
196 KUROBOX_PRO_NOR_BOOT_SIZE);
197 orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE, KUROBOX_PRO_NAND_SIZE);
198 348
199 /* 349 /*
200 * Open a special address decode windows for the PCIe WA. 350 * Configure peripherals.
201 */ 351 */
202 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE, 352 orion5x_ehci0_init();
203 ORION5X_PCIE_WA_SIZE); 353 orion5x_ehci1_init();
204 354 orion5x_eth_init(&kurobox_pro_eth_data);
205 /* 355 orion5x_i2c_init();
206 * Setup Multiplexing Pins -- 356 orion5x_sata_init(&kurobox_pro_sata_data);
207 * MPP[0-1] Not used 357 orion5x_uart0_init();
208 * MPP[2] GPIO Micon 358 orion5x_uart1_init();
209 * MPP[3] GPIO RTC
210 * MPP[4-5] Not used
211 * MPP[6] Nand Flash REn
212 * MPP[7] Nand Flash WEn
213 * MPP[8-11] Not used
214 * MPP[12] SATA 0 presence Indication
215 * MPP[13] SATA 1 presence Indication
216 * MPP[14] SATA 0 active Indication
217 * MPP[15] SATA 1 active indication
218 * MPP[16-19] Not used
219 */
220 orion5x_write(MPP_0_7_CTRL, 0x44220003);
221 orion5x_write(MPP_8_15_CTRL, 0x55550000);
222 orion5x_write(MPP_16_19_CTRL, 0x0);
223
224 orion5x_gpio_set_valid_pins(0x0000000c);
225 359
360 orion5x_setup_dev_boot_win(KUROBOX_PRO_NOR_BOOT_BASE,
361 KUROBOX_PRO_NOR_BOOT_SIZE);
226 platform_device_register(&kurobox_pro_nor_flash); 362 platform_device_register(&kurobox_pro_nor_flash);
227 if (machine_is_kurobox_pro()) 363
364 if (machine_is_kurobox_pro()) {
365 orion5x_setup_dev0_win(KUROBOX_PRO_NAND_BASE,
366 KUROBOX_PRO_NAND_SIZE);
228 platform_device_register(&kurobox_pro_nand_flash); 367 platform_device_register(&kurobox_pro_nand_flash);
368 }
369
229 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1); 370 i2c_register_board_info(0, &kurobox_pro_i2c_rtc, 1);
230 orion5x_eth_init(&kurobox_pro_eth_data); 371
231 orion5x_sata_init(&kurobox_pro_sata_data); 372 /* register Kurobox Pro specific power-off method */
373 pm_power_off = kurobox_pro_power_off;
232} 374}
233 375
234#ifdef CONFIG_MACH_KUROBOX_PRO 376#ifdef CONFIG_MACH_KUROBOX_PRO
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
new file mode 100644
index 000000000000..a48cadb01590
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -0,0 +1,163 @@
1/*
2 * arch/arm/mach-orion5x/mpp.c
3 *
4 * MPP functions for Marvell Orion 5x SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/mbus.h>
14#include <asm/hardware.h>
15#include <asm/io.h>
16#include "common.h"
17#include "mpp.h"
18
19static int is_5181l(void)
20{
21 u32 dev;
22 u32 rev;
23
24 orion5x_pcie_id(&dev, &rev);
25
26 return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
27}
28
29static int is_5182(void)
30{
31 u32 dev;
32 u32 rev;
33
34 orion5x_pcie_id(&dev, &rev);
35
36 return !!(dev == MV88F5182_DEV_ID);
37}
38
39static int is_5281(void)
40{
41 u32 dev;
42 u32 rev;
43
44 orion5x_pcie_id(&dev, &rev);
45
46 return !!(dev == MV88F5281_DEV_ID);
47}
48
49static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
50{
51 switch (type) {
52 case MPP_UNUSED:
53 case MPP_GPIO:
54 if (mpp == 0)
55 return 3;
56 if (mpp >= 1 && mpp <= 15)
57 return 0;
58 if (mpp >= 16 && mpp <= 19) {
59 if (is_5182())
60 return 5;
61 if (type == MPP_UNUSED)
62 return 0;
63 }
64 return -1;
65
66 case MPP_PCIE_RST_OUTn:
67 if (mpp == 0)
68 return 0;
69 return -1;
70
71 case MPP_PCI_ARB:
72 if (mpp >= 0 && mpp <= 7)
73 return 2;
74 return -1;
75
76 case MPP_PCI_PMEn:
77 if (mpp == 2)
78 return 3;
79 return -1;
80
81 case MPP_GIGE:
82 if (mpp >= 8 && mpp <= 19)
83 return 1;
84 return -1;
85
86 case MPP_NAND:
87 if (is_5182() || is_5281()) {
88 if (mpp >= 4 && mpp <= 7)
89 return 4;
90 if (mpp >= 12 && mpp <= 17)
91 return 4;
92 }
93 return -1;
94
95 case MPP_PCI_CLK:
96 if (is_5181l() && mpp >= 6 && mpp <= 7)
97 return 5;
98 return -1;
99
100 case MPP_SATA_LED:
101 if (is_5182()) {
102 if (mpp >= 4 && mpp <= 7)
103 return 5;
104 if (mpp >= 12 && mpp <= 15)
105 return 5;
106 }
107 return -1;
108
109 case MPP_UART:
110 if (mpp >= 16 && mpp <= 19)
111 return 0;
112 return -1;
113 }
114
115 printk(KERN_INFO "unknown MPP type %d\n", type);
116
117 return -1;
118}
119
120void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
121{
122 u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
123 u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
124 u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
125
126 while (mode->mpp >= 0) {
127 u32 *reg;
128 int num_type;
129 int shift;
130
131 if (mode->mpp >= 0 && mode->mpp <= 7)
132 reg = &mpp_0_7_ctrl;
133 else if (mode->mpp >= 8 && mode->mpp <= 15)
134 reg = &mpp_8_15_ctrl;
135 else if (mode->mpp >= 16 && mode->mpp <= 19)
136 reg = &mpp_16_19_ctrl;
137 else {
138 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
139 "(%d)\n", mode->mpp);
140 continue;
141 }
142
143 num_type = determine_type_encoding(mode->mpp, mode->type);
144 if (num_type < 0) {
145 printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
146 "combination (%d, %d)\n", mode->mpp,
147 mode->type);
148 continue;
149 }
150
151 shift = (mode->mpp & 7) << 2;
152 *reg &= ~(0xf << shift);
153 *reg |= (num_type & 0xf) << shift;
154
155 orion5x_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
156
157 mode++;
158 }
159
160 writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
161 writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
162 writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
163}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
new file mode 100644
index 000000000000..290e610dc012
--- /dev/null
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -0,0 +1,74 @@
1#ifndef __ARCH_ORION5X_MPP_H
2#define __ARCH_ORION5X_MPP_H
3
4enum orion5x_mpp_type {
5 /*
6 * This MPP is unused.
7 */
8 MPP_UNUSED,
9
10 /*
11 * This MPP pin is used as a generic GPIO pin. Valid for
12 * MPPs 0-15 and device bus data pins 16-31. On 5182, also
13 * valid for MPPs 16-19.
14 */
15 MPP_GPIO,
16
17 /*
18 * This MPP is used as PCIe_RST_OUTn pin. Valid for
19 * MPP 0 only.
20 */
21 MPP_PCIE_RST_OUTn,
22
23 /*
24 * This MPP is used as PCI arbiter pin (REQn/GNTn).
25 * Valid for MPPs 0-7 only.
26 */
27 MPP_PCI_ARB,
28
29 /*
30 * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
31 */
32 MPP_PCI_PMEn,
33
34 /*
35 * This MPP is used as GigE half-duplex (COL, CRS) or GMII
36 * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
37 * MPPs 8-19 only.
38 */
39 MPP_GIGE,
40
41 /*
42 * This MPP is used as NAND REn/WEn pin. Valid for MPPs
43 * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
44 */
45 MPP_NAND,
46
47 /*
48 * This MPP is used as a PCI clock output pin. Valid for
49 * MPPs 6-7 only, and only on the 5181l.
50 */
51 MPP_PCI_CLK,
52
53 /*
54 * This MPP is used as a SATA presence/activity LED.
55 * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
56 */
57 MPP_SATA_LED,
58
59 /*
60 * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
61 * Valid for MPPs 16-19 only.
62 */
63 MPP_UART,
64};
65
66struct orion5x_mpp_mode {
67 int mpp;
68 enum orion5x_mpp_type type;
69};
70
71void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
72
73
74#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
new file mode 100644
index 000000000000..7ce9e407d9d1
--- /dev/null
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -0,0 +1,270 @@
1/*
2 * Maxtor Shared Storage II Board Setup
3 *
4 * Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/irq.h>
17#include <linux/mtd/physmap.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/leds.h>
20#include <linux/gpio_keys.h>
21#include <linux/input.h>
22#include <linux/i2c.h>
23#include <linux/ata_platform.h>
24#include <linux/gpio.h>
25#include <asm/mach-types.h>
26#include <asm/mach/arch.h>
27#include <asm/mach/pci.h>
28#include <asm/arch/orion5x.h>
29#include "common.h"
30#include "mpp.h"
31
32#define MSS2_NOR_BOOT_BASE 0xff800000
33#define MSS2_NOR_BOOT_SIZE SZ_256K
34
35/*****************************************************************************
36 * Maxtor Shared Storage II Info
37 ****************************************************************************/
38
39/*
40 * Maxtor Shared Storage II hardware :
41 * - Marvell 88F5182-A2 C500
42 * - Marvell 88E1111 Gigabit Ethernet PHY
43 * - RTC M41T81 (@0x68) on I2C bus
44 * - 256KB NOR flash
45 * - 64MB of RAM
46 */
47
48/*****************************************************************************
49 * 256KB NOR Flash on BOOT Device
50 ****************************************************************************/
51
52static struct physmap_flash_data mss2_nor_flash_data = {
53 .width = 1,
54};
55
56static struct resource mss2_nor_flash_resource = {
57 .flags = IORESOURCE_MEM,
58 .start = MSS2_NOR_BOOT_BASE,
59 .end = MSS2_NOR_BOOT_BASE + MSS2_NOR_BOOT_SIZE - 1,
60};
61
62static struct platform_device mss2_nor_flash = {
63 .name = "physmap-flash",
64 .id = 0,
65 .dev = {
66 .platform_data = &mss2_nor_flash_data,
67 },
68 .resource = &mss2_nor_flash_resource,
69 .num_resources = 1,
70};
71
72/****************************************************************************
73 * PCI setup
74 ****************************************************************************/
75static int __init mss2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
76{
77 int irq;
78
79 /*
80 * Check for devices with hard-wired IRQs.
81 */
82 irq = orion5x_pci_map_irq(dev, slot, pin);
83 if (irq != -1)
84 return irq;
85
86 return -1;
87}
88
89static struct hw_pci mss2_pci __initdata = {
90 .nr_controllers = 2,
91 .swizzle = pci_std_swizzle,
92 .setup = orion5x_pci_sys_setup,
93 .scan = orion5x_pci_sys_scan_bus,
94 .map_irq = mss2_pci_map_irq,
95};
96
97static int __init mss2_pci_init(void)
98{
99 if (machine_is_mss2())
100 pci_common_init(&mss2_pci);
101
102 return 0;
103}
104subsys_initcall(mss2_pci_init);
105
106
107/*****************************************************************************
108 * Ethernet
109 ****************************************************************************/
110
111static struct mv643xx_eth_platform_data mss2_eth_data = {
112 .phy_addr = 8,
113};
114
115/*****************************************************************************
116 * SATA
117 ****************************************************************************/
118
119static struct mv_sata_platform_data mss2_sata_data = {
120 .n_ports = 2,
121};
122
123/*****************************************************************************
124 * GPIO buttons
125 ****************************************************************************/
126
127#define MSS2_GPIO_KEY_RESET 12
128#define MSS2_GPIO_KEY_POWER 11
129
130static struct gpio_keys_button mss2_buttons[] = {
131 {
132 .code = KEY_POWER,
133 .gpio = MSS2_GPIO_KEY_POWER,
134 .desc = "Power",
135 .active_low = 1,
136 }, {
137 .code = KEY_RESTART,
138 .gpio = MSS2_GPIO_KEY_RESET,
139 .desc = "Reset",
140 .active_low = 1,
141 },
142};
143
144static struct gpio_keys_platform_data mss2_button_data = {
145 .buttons = mss2_buttons,
146 .nbuttons = ARRAY_SIZE(mss2_buttons),
147};
148
149static struct platform_device mss2_button_device = {
150 .name = "gpio-keys",
151 .id = -1,
152 .dev = {
153 .platform_data = &mss2_button_data,
154 },
155};
156
157/*****************************************************************************
158 * RTC m41t81 on I2C bus
159 ****************************************************************************/
160
161#define MSS2_GPIO_RTC_IRQ 3
162
163static struct i2c_board_info __initdata mss2_i2c_rtc = {
164 I2C_BOARD_INFO("m41t81", 0x68),
165};
166
167/*****************************************************************************
168 * MSS2 power off method
169 ****************************************************************************/
170/*
171 * On the Maxtor Shared Storage II, the shutdown process is the following :
172 * - Userland modifies U-boot env to tell U-boot to go idle at next boot
173 * - The board reboots
174 * - U-boot starts and go into an idle mode until the user press "power"
175 */
176static void mss2_power_off(void)
177{
178 u32 reg;
179
180 /*
181 * Enable and issue soft reset
182 */
183 reg = readl(CPU_RESET_MASK);
184 reg |= 1 << 2;
185 writel(reg, CPU_RESET_MASK);
186
187 reg = readl(CPU_SOFT_RESET);
188 reg |= 1;
189 writel(reg, CPU_SOFT_RESET);
190}
191
192/****************************************************************************
193 * General Setup
194 ****************************************************************************/
195static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
196 { 0, MPP_GPIO }, /* Power LED */
197 { 1, MPP_GPIO }, /* Error LED */
198 { 2, MPP_UNUSED },
199 { 3, MPP_GPIO }, /* RTC interrupt */
200 { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/
201 { 5, MPP_GPIO }, /* HD0 5V control */
202 { 6, MPP_GPIO }, /* HD0 12V control */
203 { 7, MPP_GPIO }, /* HD1 5V control */
204 { 8, MPP_GPIO }, /* HD1 12V control */
205 { 9, MPP_UNUSED },
206 { 10, MPP_GPIO }, /* Fan control */
207 { 11, MPP_GPIO }, /* Power button */
208 { 12, MPP_GPIO }, /* Reset button */
209 { 13, MPP_UNUSED },
210 { 14, MPP_SATA_LED }, /* SATA 0 active */
211 { 15, MPP_SATA_LED }, /* SATA 1 active */
212 { 16, MPP_UNUSED },
213 { 17, MPP_UNUSED },
214 { 18, MPP_UNUSED },
215 { 19, MPP_UNUSED },
216 { -1 },
217};
218
219static void __init mss2_init(void)
220{
221 /* Setup basic Orion functions. Need to be called early. */
222 orion5x_init();
223
224 orion5x_mpp_conf(mss2_mpp_modes);
225
226 /*
227 * MPP[20] Unused
228 * MPP[21] PCI clock
229 * MPP[22] USB 0 over current
230 * MPP[23] USB 1 over current
231 */
232
233 /*
234 * Configure peripherals.
235 */
236 orion5x_ehci0_init();
237 orion5x_ehci1_init();
238 orion5x_eth_init(&mss2_eth_data);
239 orion5x_i2c_init();
240 orion5x_sata_init(&mss2_sata_data);
241 orion5x_uart0_init();
242
243 orion5x_setup_dev_boot_win(MSS2_NOR_BOOT_BASE, MSS2_NOR_BOOT_SIZE);
244 platform_device_register(&mss2_nor_flash);
245
246 platform_device_register(&mss2_button_device);
247
248 if (gpio_request(MSS2_GPIO_RTC_IRQ, "rtc") == 0) {
249 if (gpio_direction_input(MSS2_GPIO_RTC_IRQ) == 0)
250 mss2_i2c_rtc.irq = gpio_to_irq(MSS2_GPIO_RTC_IRQ);
251 else
252 gpio_free(MSS2_GPIO_RTC_IRQ);
253 }
254 i2c_register_board_info(0, &mss2_i2c_rtc, 1);
255
256 /* register mss2 specific power-off method */
257 pm_power_off = mss2_power_off;
258}
259
260MACHINE_START(MSS2, "Maxtor Shared Storage II")
261 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
262 .phys_io = ORION5X_REGS_PHYS_BASE,
263 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
264 .boot_params = 0x00000100,
265 .init_machine = mss2_init,
266 .map_io = orion5x_map_io,
267 .init_irq = orion5x_init_irq,
268 .timer = &orion5x_timer,
269 .fixup = tag_fixup_mem32
270MACHINE_END
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
new file mode 100644
index 000000000000..55f3b0fdef8b
--- /dev/null
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -0,0 +1,239 @@
1/*
2 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
3 * Copyright (C) 2008 Martin Michlmayr <tbm@cyrius.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU Lesser General Public License as
7 * published by the Free Software Foundation; either version 2 of the
8 * License, or (at your option) any later version.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/irq.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mv643xx_eth.h>
17#include <linux/leds.h>
18#include <linux/gpio_keys.h>
19#include <linux/input.h>
20#include <linux/i2c.h>
21#include <linux/ata_platform.h>
22#include <asm/mach-types.h>
23#include <asm/gpio.h>
24#include <asm/mach/arch.h>
25#include <asm/arch/orion5x.h>
26#include "common.h"
27#include "mpp.h"
28
29#define MV2120_NOR_BOOT_BASE 0xf4000000
30#define MV2120_NOR_BOOT_SIZE SZ_512K
31
32#define MV2120_GPIO_RTC_IRQ 3
33#define MV2120_GPIO_KEY_RESET 17
34#define MV2120_GPIO_KEY_POWER 18
35#define MV2120_GPIO_POWER_OFF 19
36
37
38/*****************************************************************************
39 * Ethernet
40 ****************************************************************************/
41static struct mv643xx_eth_platform_data mv2120_eth_data = {
42 .phy_addr = 8,
43};
44
45static struct mv_sata_platform_data mv2120_sata_data = {
46 .n_ports = 2,
47};
48
49static struct mtd_partition mv2120_partitions[] = {
50 {
51 .name = "firmware",
52 .size = 0x00080000,
53 .offset = 0,
54 },
55};
56
57static struct physmap_flash_data mv2120_nor_flash_data = {
58 .width = 1,
59 .parts = mv2120_partitions,
60 .nr_parts = ARRAY_SIZE(mv2120_partitions)
61};
62
63static struct resource mv2120_nor_flash_resource = {
64 .flags = IORESOURCE_MEM,
65 .start = MV2120_NOR_BOOT_BASE,
66 .end = MV2120_NOR_BOOT_BASE + MV2120_NOR_BOOT_SIZE - 1,
67};
68
69static struct platform_device mv2120_nor_flash = {
70 .name = "physmap-flash",
71 .id = 0,
72 .dev = {
73 .platform_data = &mv2120_nor_flash_data,
74 },
75 .resource = &mv2120_nor_flash_resource,
76 .num_resources = 1,
77};
78
79static struct gpio_keys_button mv2120_buttons[] = {
80 {
81 .code = KEY_RESTART,
82 .gpio = MV2120_GPIO_KEY_RESET,
83 .desc = "reset",
84 .active_low = 1,
85 }, {
86 .code = KEY_POWER,
87 .gpio = MV2120_GPIO_KEY_POWER,
88 .desc = "power",
89 .active_low = 1,
90 },
91};
92
93static struct gpio_keys_platform_data mv2120_button_data = {
94 .buttons = mv2120_buttons,
95 .nbuttons = ARRAY_SIZE(mv2120_buttons),
96};
97
98static struct platform_device mv2120_button_device = {
99 .name = "gpio-keys",
100 .id = -1,
101 .num_resources = 0,
102 .dev = {
103 .platform_data = &mv2120_button_data,
104 },
105};
106
107
108/****************************************************************************
109 * General Setup
110 ****************************************************************************/
111static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
112 { 0, MPP_GPIO }, /* Sys status LED */
113 { 1, MPP_GPIO }, /* Sys error LED */
114 { 2, MPP_GPIO }, /* OverTemp interrupt */
115 { 3, MPP_GPIO }, /* RTC interrupt */
116 { 4, MPP_GPIO }, /* V_LED 5V */
117 { 5, MPP_GPIO }, /* V_LED 3.3V */
118 { 6, MPP_UNUSED },
119 { 7, MPP_UNUSED },
120 { 8, MPP_GPIO }, /* SATA 0 fail LED */
121 { 9, MPP_GPIO }, /* SATA 1 fail LED */
122 { 10, MPP_UNUSED },
123 { 11, MPP_UNUSED },
124 { 12, MPP_SATA_LED }, /* SATA 0 presence */
125 { 13, MPP_SATA_LED }, /* SATA 1 presence */
126 { 14, MPP_SATA_LED }, /* SATA 0 active */
127 { 15, MPP_SATA_LED }, /* SATA 1 active */
128 { 16, MPP_UNUSED },
129 { 17, MPP_GPIO }, /* Reset button */
130 { 18, MPP_GPIO }, /* Power button */
131 { 19, MPP_GPIO }, /* Power off */
132 { -1 },
133};
134
135static struct i2c_board_info __initdata mv2120_i2c_rtc = {
136 I2C_BOARD_INFO("pcf8563", 0x51),
137 .irq = 0,
138};
139
140static struct gpio_led mv2120_led_pins[] = {
141 {
142 .name = "mv2120:blue:health",
143 .gpio = 0,
144 },
145 {
146 .name = "mv2120:red:health",
147 .gpio = 1,
148 },
149 {
150 .name = "mv2120:led:bright",
151 .gpio = 4,
152 .default_trigger = "default-on",
153 },
154 {
155 .name = "mv2120:led:dimmed",
156 .gpio = 5,
157 },
158 {
159 .name = "mv2120:red:sata0",
160 .gpio = 8,
161 .active_low = 1,
162 },
163 {
164 .name = "mv2120:red:sata1",
165 .gpio = 9,
166 .active_low = 1,
167 },
168
169};
170
171static struct gpio_led_platform_data mv2120_led_data = {
172 .leds = mv2120_led_pins,
173 .num_leds = ARRAY_SIZE(mv2120_led_pins),
174};
175
176static struct platform_device mv2120_leds = {
177 .name = "leds-gpio",
178 .id = -1,
179 .dev = {
180 .platform_data = &mv2120_led_data,
181 }
182};
183
184static void mv2120_power_off(void)
185{
186 pr_info("%s: triggering power-off...\n", __func__);
187 gpio_set_value(MV2120_GPIO_POWER_OFF, 0);
188}
189
190static void __init mv2120_init(void)
191{
192 /* Setup basic Orion functions. Need to be called early. */
193 orion5x_init();
194
195 orion5x_mpp_conf(mv2120_mpp_modes);
196
197 /*
198 * Configure peripherals.
199 */
200 orion5x_ehci0_init();
201 orion5x_ehci1_init();
202 orion5x_eth_init(&mv2120_eth_data);
203 orion5x_i2c_init();
204 orion5x_sata_init(&mv2120_sata_data);
205 orion5x_uart0_init();
206
207 orion5x_setup_dev_boot_win(MV2120_NOR_BOOT_BASE, MV2120_NOR_BOOT_SIZE);
208 platform_device_register(&mv2120_nor_flash);
209
210 platform_device_register(&mv2120_button_device);
211
212 if (gpio_request(MV2120_GPIO_RTC_IRQ, "rtc") == 0) {
213 if (gpio_direction_input(MV2120_GPIO_RTC_IRQ) == 0)
214 mv2120_i2c_rtc.irq = gpio_to_irq(MV2120_GPIO_RTC_IRQ);
215 else
216 gpio_free(MV2120_GPIO_RTC_IRQ);
217 }
218 i2c_register_board_info(0, &mv2120_i2c_rtc, 1);
219 platform_device_register(&mv2120_leds);
220
221 /* register mv2120 specific power-off method */
222 if (gpio_request(MV2120_GPIO_POWER_OFF, "POWEROFF") != 0 ||
223 gpio_direction_output(MV2120_GPIO_POWER_OFF, 1) != 0)
224 pr_err("mv2120: failed to setup power-off GPIO\n");
225 pm_power_off = mv2120_power_off;
226}
227
228/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
229MACHINE_START(MV2120, "HP Media Vault mv2120")
230 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
231 .phys_io = ORION5X_REGS_PHYS_BASE,
232 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
233 .boot_params = 0x00000100,
234 .init_machine = mv2120_init,
235 .map_io = orion5x_map_io,
236 .init_irq = orion5x_init_irq,
237 .timer = &orion5x_timer,
238 .fixup = tag_fixup_mem32
239MACHINE_END
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 9d5d39fa19c3..256a4f680935 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -152,6 +152,8 @@ static int __init pcie_setup(struct pci_sys_data *sys)
152 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) { 152 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
153 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config " 153 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
154 "read transaction workaround\n"); 154 "read transaction workaround\n");
155 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
156 ORION5X_PCIE_WA_SIZE);
155 pcie_ops.read = pcie_rd_conf_wa; 157 pcie_ops.read = pcie_rd_conf_wa;
156 } 158 }
157 159
@@ -240,13 +242,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
240 * PCI Address Decode Windows registers 242 * PCI Address Decode Windows registers
241 */ 243 */
242#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \ 244#define PCI_BAR_SIZE_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc08) : \
243 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \ 245 ((n) == 1) ? ORION5X_PCI_REG(0xd08) : \
244 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \ 246 ((n) == 2) ? ORION5X_PCI_REG(0xc0c) : \
245 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0) 247 ((n) == 3) ? ORION5X_PCI_REG(0xd0c) : 0)
246#define PCI_BAR_REMAP_DDR_CS(n) (((n) ==0) ? ORION5X_PCI_REG(0xc48) : \ 248#define PCI_BAR_REMAP_DDR_CS(n) (((n) == 0) ? ORION5X_PCI_REG(0xc48) : \
247 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \ 249 ((n) == 1) ? ORION5X_PCI_REG(0xd48) : \
248 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \ 250 ((n) == 2) ? ORION5X_PCI_REG(0xc4c) : \
249 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0) 251 ((n) == 3) ? ORION5X_PCI_REG(0xd4c) : 0)
250#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c) 252#define PCI_BAR_ENABLE ORION5X_PCI_REG(0xc3c)
251#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c) 253#define PCI_ADDR_DECODE_CTRL ORION5X_PCI_REG(0xd3c)
252 254
@@ -264,9 +266,11 @@ static int __init pcie_setup(struct pci_sys_data *sys)
264 */ 266 */
265static DEFINE_SPINLOCK(orion5x_pci_lock); 267static DEFINE_SPINLOCK(orion5x_pci_lock);
266 268
269static int orion5x_pci_cardbus_mode;
270
267static int orion5x_pci_local_bus_nr(void) 271static int orion5x_pci_local_bus_nr(void)
268{ 272{
269 u32 conf = orion5x_read(PCI_P2P_CONF); 273 u32 conf = readl(PCI_P2P_CONF);
270 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS); 274 return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
271} 275}
272 276
@@ -276,11 +280,11 @@ static int orion5x_pci_hw_rd_conf(int bus, int dev, u32 func,
276 unsigned long flags; 280 unsigned long flags;
277 spin_lock_irqsave(&orion5x_pci_lock, flags); 281 spin_lock_irqsave(&orion5x_pci_lock, flags);
278 282
279 orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | 283 writel(PCI_CONF_BUS(bus) |
280 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 284 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
281 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); 285 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
282 286
283 *val = orion5x_read(PCI_CONF_DATA); 287 *val = readl(PCI_CONF_DATA);
284 288
285 if (size == 1) 289 if (size == 1)
286 *val = (*val >> (8*(where & 0x3))) & 0xff; 290 *val = (*val >> (8*(where & 0x3))) & 0xff;
@@ -300,9 +304,9 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
300 304
301 spin_lock_irqsave(&orion5x_pci_lock, flags); 305 spin_lock_irqsave(&orion5x_pci_lock, flags);
302 306
303 orion5x_write(PCI_CONF_ADDR, PCI_CONF_BUS(bus) | 307 writel(PCI_CONF_BUS(bus) |
304 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) | 308 PCI_CONF_DEV(dev) | PCI_CONF_REG(where) |
305 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN); 309 PCI_CONF_FUNC(func) | PCI_CONF_ADDR_EN, PCI_CONF_ADDR);
306 310
307 if (size == 4) { 311 if (size == 4) {
308 __raw_writel(val, PCI_CONF_DATA); 312 __raw_writel(val, PCI_CONF_DATA);
@@ -319,14 +323,30 @@ static int orion5x_pci_hw_wr_conf(int bus, int dev, u32 func,
319 return ret; 323 return ret;
320} 324}
321 325
326static int orion5x_pci_valid_config(int bus, u32 devfn)
327{
328 if (bus == orion5x_pci_local_bus_nr()) {
329 /*
330 * Don't go out for local device
331 */
332 if (PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
333 return 0;
334
335 /*
336 * When the PCI signals are directly connected to a
337 * Cardbus slot, ignore all but device IDs 0 and 1.
338 */
339 if (orion5x_pci_cardbus_mode && PCI_SLOT(devfn) > 1)
340 return 0;
341 }
342
343 return 1;
344}
345
322static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn, 346static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
323 int where, int size, u32 *val) 347 int where, int size, u32 *val)
324{ 348{
325 /* 349 if (!orion5x_pci_valid_config(bus->number, devfn)) {
326 * Don't go out for local device
327 */
328 if (bus->number == orion5x_pci_local_bus_nr() &&
329 PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0) {
330 *val = 0xffffffff; 350 *val = 0xffffffff;
331 return PCIBIOS_DEVICE_NOT_FOUND; 351 return PCIBIOS_DEVICE_NOT_FOUND;
332 } 352 }
@@ -338,8 +358,7 @@ static int orion5x_pci_rd_conf(struct pci_bus *bus, u32 devfn,
338static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn, 358static int orion5x_pci_wr_conf(struct pci_bus *bus, u32 devfn,
339 int where, int size, u32 val) 359 int where, int size, u32 val)
340{ 360{
341 if (bus->number == orion5x_pci_local_bus_nr() && 361 if (!orion5x_pci_valid_config(bus->number, devfn))
342 PCI_SLOT(devfn) == 0 && PCI_FUNC(devfn) != 0)
343 return PCIBIOS_DEVICE_NOT_FOUND; 362 return PCIBIOS_DEVICE_NOT_FOUND;
344 363
345 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn), 364 return orion5x_pci_hw_wr_conf(bus->number, PCI_SLOT(devfn),
@@ -353,9 +372,9 @@ static struct pci_ops pci_ops = {
353 372
354static void __init orion5x_pci_set_bus_nr(int nr) 373static void __init orion5x_pci_set_bus_nr(int nr)
355{ 374{
356 u32 p2p = orion5x_read(PCI_P2P_CONF); 375 u32 p2p = readl(PCI_P2P_CONF);
357 376
358 if (orion5x_read(PCI_MODE) & PCI_MODE_PCIX) { 377 if (readl(PCI_MODE) & PCI_MODE_PCIX) {
359 /* 378 /*
360 * PCI-X mode 379 * PCI-X mode
361 */ 380 */
@@ -372,7 +391,7 @@ static void __init orion5x_pci_set_bus_nr(int nr)
372 */ 391 */
373 p2p &= ~PCI_P2P_BUS_MASK; 392 p2p &= ~PCI_P2P_BUS_MASK;
374 p2p |= (nr << PCI_P2P_BUS_OFFS); 393 p2p |= (nr << PCI_P2P_BUS_OFFS);
375 orion5x_write(PCI_P2P_CONF, p2p); 394 writel(p2p, PCI_P2P_CONF);
376 } 395 }
377} 396}
378 397
@@ -399,7 +418,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
399 * First, disable windows. 418 * First, disable windows.
400 */ 419 */
401 win_enable = 0xffffffff; 420 win_enable = 0xffffffff;
402 orion5x_write(PCI_BAR_ENABLE, win_enable); 421 writel(win_enable, PCI_BAR_ENABLE);
403 422
404 /* 423 /*
405 * Setup windows for DDR banks. 424 * Setup windows for DDR banks.
@@ -425,10 +444,10 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
425 */ 444 */
426 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index); 445 reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
427 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0); 446 orion5x_pci_hw_wr_conf(bus, 0, func, reg, 4, 0);
428 orion5x_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index), 447 writel((cs->size - 1) & 0xfffff000,
429 (cs->size - 1) & 0xfffff000); 448 PCI_BAR_SIZE_DDR_CS(cs->cs_index));
430 orion5x_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index), 449 writel(cs->base & 0xfffff000,
431 cs->base & 0xfffff000); 450 PCI_BAR_REMAP_DDR_CS(cs->cs_index));
432 451
433 /* 452 /*
434 * Enable decode window for this chip select. 453 * Enable decode window for this chip select.
@@ -439,7 +458,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
439 /* 458 /*
440 * Re-enable decode windows. 459 * Re-enable decode windows.
441 */ 460 */
442 orion5x_write(PCI_BAR_ENABLE, win_enable); 461 writel(win_enable, PCI_BAR_ENABLE);
443 462
444 /* 463 /*
445 * Disable automatic update of address remaping when writing to BARs. 464 * Disable automatic update of address remaping when writing to BARs.
@@ -522,6 +541,11 @@ static void __devinit rc_pci_fixup(struct pci_dev *dev)
522} 541}
523DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup); 542DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
524 543
544void __init orion5x_pci_set_cardbus_mode(void)
545{
546 orion5x_pci_cardbus_mode = 1;
547}
548
525int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys) 549int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
526{ 550{
527 int ret = 0; 551 int ret = 0;
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
new file mode 100644
index 000000000000..d50e3650a09e
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -0,0 +1,161 @@
1/*
2 * arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
3 *
4 * Marvell Orion-VoIP FXO Reference Design Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mv643xx_eth.h>
18#include <asm/mach-types.h>
19#include <asm/gpio.h>
20#include <asm/leds.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/pci.h>
23#include <asm/arch/orion5x.h>
24#include "common.h"
25#include "mpp.h"
26
27/*****************************************************************************
28 * RD-88F5181L FXO Info
29 ****************************************************************************/
30/*
31 * 8M NOR flash Device bus boot chip select
32 */
33#define RD88F5181L_FXO_NOR_BOOT_BASE 0xff800000
34#define RD88F5181L_FXO_NOR_BOOT_SIZE SZ_8M
35
36
37/*****************************************************************************
38 * 8M NOR Flash on Device bus Boot chip select
39 ****************************************************************************/
40static struct physmap_flash_data rd88f5181l_fxo_nor_boot_flash_data = {
41 .width = 1,
42};
43
44static struct resource rd88f5181l_fxo_nor_boot_flash_resource = {
45 .flags = IORESOURCE_MEM,
46 .start = RD88F5181L_FXO_NOR_BOOT_BASE,
47 .end = RD88F5181L_FXO_NOR_BOOT_BASE +
48 RD88F5181L_FXO_NOR_BOOT_SIZE - 1,
49};
50
51static struct platform_device rd88f5181l_fxo_nor_boot_flash = {
52 .name = "physmap-flash",
53 .id = 0,
54 .dev = {
55 .platform_data = &rd88f5181l_fxo_nor_boot_flash_data,
56 },
57 .num_resources = 1,
58 .resource = &rd88f5181l_fxo_nor_boot_flash_resource,
59};
60
61
62/*****************************************************************************
63 * General Setup
64 ****************************************************************************/
65static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
66 { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */
67 { 1, MPP_GPIO }, /* PCI_intA */
68 { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/
69 { 3, MPP_GPIO }, /* FXS or DAA select */
70 { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */
71 { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */
72 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
73 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
74 { 8, MPP_GPIO }, /* CardBus reset */
75 { 9, MPP_GPIO }, /* GE_RXERR */
76 { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */
77 { 11, MPP_GPIO }, /* Lifeline control */
78 { 12, MPP_GIGE }, /* GE_TXD[4] */
79 { 13, MPP_GIGE }, /* GE_TXD[5] */
80 { 14, MPP_GIGE }, /* GE_TXD[6] */
81 { 15, MPP_GIGE }, /* GE_TXD[7] */
82 { 16, MPP_GIGE }, /* GE_RXD[4] */
83 { 17, MPP_GIGE }, /* GE_RXD[5] */
84 { 18, MPP_GIGE }, /* GE_RXD[6] */
85 { 19, MPP_GIGE }, /* GE_RXD[7] */
86 { -1 },
87};
88
89static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
90 .phy_addr = -1,
91};
92
93static void __init rd88f5181l_fxo_init(void)
94{
95 /*
96 * Setup basic Orion functions. Need to be called early.
97 */
98 orion5x_init();
99
100 orion5x_mpp_conf(rd88f5181l_fxo_mpp_modes);
101
102 /*
103 * Configure peripherals.
104 */
105 orion5x_ehci0_init();
106 orion5x_eth_init(&rd88f5181l_fxo_eth_data);
107 orion5x_uart0_init();
108
109 orion5x_setup_dev_boot_win(RD88F5181L_FXO_NOR_BOOT_BASE,
110 RD88F5181L_FXO_NOR_BOOT_SIZE);
111 platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
112}
113
114static int __init
115rd88f5181l_fxo_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
116{
117 int irq;
118
119 /*
120 * Check for devices with hard-wired IRQs.
121 */
122 irq = orion5x_pci_map_irq(dev, slot, pin);
123 if (irq != -1)
124 return irq;
125
126 /*
127 * Mini-PCI / Cardbus slot.
128 */
129 return gpio_to_irq(1);
130}
131
132static struct hw_pci rd88f5181l_fxo_pci __initdata = {
133 .nr_controllers = 2,
134 .swizzle = pci_std_swizzle,
135 .setup = orion5x_pci_sys_setup,
136 .scan = orion5x_pci_sys_scan_bus,
137 .map_irq = rd88f5181l_fxo_pci_map_irq,
138};
139
140static int __init rd88f5181l_fxo_pci_init(void)
141{
142 if (machine_is_rd88f5181l_fxo()) {
143 orion5x_pci_set_cardbus_mode();
144 pci_common_init(&rd88f5181l_fxo_pci);
145 }
146
147 return 0;
148}
149subsys_initcall(rd88f5181l_fxo_pci_init);
150
151MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
152 /* Maintainer: Nicolas Pitre <nico@marvell.com> */
153 .phys_io = ORION5X_REGS_PHYS_BASE,
154 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
155 .boot_params = 0x00000100,
156 .init_machine = rd88f5181l_fxo_init,
157 .map_io = orion5x_map_io,
158 .init_irq = orion5x_init_irq,
159 .timer = &orion5x_timer,
160 .fixup = tag_fixup_mem32,
161MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
new file mode 100644
index 000000000000..b56447d32e17
--- /dev/null
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -0,0 +1,172 @@
1/*
2 * arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
3 *
4 * Marvell Orion-VoIP GE Reference Design Setup
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/pci.h>
15#include <linux/irq.h>
16#include <linux/mtd/physmap.h>
17#include <linux/mv643xx_eth.h>
18#include <linux/i2c.h>
19#include <asm/mach-types.h>
20#include <asm/gpio.h>
21#include <asm/leds.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/pci.h>
24#include <asm/arch/orion5x.h>
25#include "common.h"
26#include "mpp.h"
27
28/*****************************************************************************
29 * RD-88F5181L GE Info
30 ****************************************************************************/
31/*
32 * 16M NOR flash Device bus boot chip select
33 */
34#define RD88F5181L_GE_NOR_BOOT_BASE 0xff000000
35#define RD88F5181L_GE_NOR_BOOT_SIZE SZ_16M
36
37
38/*****************************************************************************
39 * 16M NOR Flash on Device bus Boot chip select
40 ****************************************************************************/
41static struct physmap_flash_data rd88f5181l_ge_nor_boot_flash_data = {
42 .width = 1,
43};
44
45static struct resource rd88f5181l_ge_nor_boot_flash_resource = {
46 .flags = IORESOURCE_MEM,
47 .start = RD88F5181L_GE_NOR_BOOT_BASE,
48 .end = RD88F5181L_GE_NOR_BOOT_BASE +
49 RD88F5181L_GE_NOR_BOOT_SIZE - 1,
50};
51
52static struct platform_device rd88f5181l_ge_nor_boot_flash = {
53 .name = "physmap-flash",
54 .id = 0,
55 .dev = {
56 .platform_data = &rd88f5181l_ge_nor_boot_flash_data,
57 },
58 .num_resources = 1,
59 .resource = &rd88f5181l_ge_nor_boot_flash_resource,
60};
61
62
63/*****************************************************************************
64 * General Setup
65 ****************************************************************************/
66static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
67 { 0, MPP_GPIO }, /* LED1 */
68 { 1, MPP_GPIO }, /* LED5 */
69 { 2, MPP_GPIO }, /* LED4 */
70 { 3, MPP_GPIO }, /* LED3 */
71 { 4, MPP_GPIO }, /* PCI_intA */
72 { 5, MPP_GPIO }, /* RTC interrupt */
73 { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
74 { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
75 { 8, MPP_GPIO }, /* 88e6131 interrupt */
76 { 9, MPP_GPIO }, /* GE_RXERR */
77 { 10, MPP_GPIO }, /* PCI_intB */
78 { 11, MPP_GPIO }, /* LED2 */
79 { 12, MPP_GIGE }, /* GE_TXD[4] */
80 { 13, MPP_GIGE }, /* GE_TXD[5] */
81 { 14, MPP_GIGE }, /* GE_TXD[6] */
82 { 15, MPP_GIGE }, /* GE_TXD[7] */
83 { 16, MPP_GIGE }, /* GE_RXD[4] */
84 { 17, MPP_GIGE }, /* GE_RXD[5] */
85 { 18, MPP_GIGE }, /* GE_RXD[6] */
86 { 19, MPP_GIGE }, /* GE_RXD[7] */
87 { -1 },
88};
89
90static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
91 .phy_addr = -1,
92};
93
94static struct i2c_board_info __initdata rd88f5181l_ge_i2c_rtc = {
95 I2C_BOARD_INFO("ds1338", 0x68),
96};
97
98static void __init rd88f5181l_ge_init(void)
99{
100 /*
101 * Setup basic Orion functions. Need to be called early.
102 */
103 orion5x_init();
104
105 orion5x_mpp_conf(rd88f5181l_ge_mpp_modes);
106
107 /*
108 * Configure peripherals.
109 */
110 orion5x_ehci0_init();
111 orion5x_eth_init(&rd88f5181l_ge_eth_data);
112 orion5x_i2c_init();
113 orion5x_uart0_init();
114
115 orion5x_setup_dev_boot_win(RD88F5181L_GE_NOR_BOOT_BASE,
116 RD88F5181L_GE_NOR_BOOT_SIZE);
117 platform_device_register(&rd88f5181l_ge_nor_boot_flash);
118
119 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
120}
121
122static int __init
123rd88f5181l_ge_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
124{
125 int irq;
126
127 /*
128 * Check for devices with hard-wired IRQs.
129 */
130 irq = orion5x_pci_map_irq(dev, slot, pin);
131 if (irq != -1)
132 return irq;
133
134 /*
135 * Cardbus slot.
136 */
137 if (pin == 1)
138 return gpio_to_irq(4);
139 else
140 return gpio_to_irq(10);
141}
142
143static struct hw_pci rd88f5181l_ge_pci __initdata = {
144 .nr_controllers = 2,
145 .swizzle = pci_std_swizzle,
146 .setup = orion5x_pci_sys_setup,
147 .scan = orion5x_pci_sys_scan_bus,
148 .map_irq = rd88f5181l_ge_pci_map_irq,
149};
150
151static int __init rd88f5181l_ge_pci_init(void)
152{
153 if (machine_is_rd88f5181l_ge()) {
154 orion5x_pci_set_cardbus_mode();
155 pci_common_init(&rd88f5181l_ge_pci);
156 }
157
158 return 0;
159}
160subsys_initcall(rd88f5181l_ge_pci_init);
161
162MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
163 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
164 .phys_io = ORION5X_REGS_PHYS_BASE,
165 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
166 .boot_params = 0x00000100,
167 .init_machine = rd88f5181l_ge_init,
168 .map_io = orion5x_map_io,
169 .init_irq = orion5x_init_irq,
170 .timer = &orion5x_timer,
171 .fixup = tag_fixup_mem32,
172MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 81abc1003aae..10ae62864269 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -26,6 +26,7 @@
26#include <asm/mach/pci.h> 26#include <asm/mach/pci.h>
27#include <asm/arch/orion5x.h> 27#include <asm/arch/orion5x.h>
28#include "common.h" 28#include "common.h"
29#include "mpp.h"
29 30
30/***************************************************************************** 31/*****************************************************************************
31 * RD-88F5182 Info 32 * RD-88F5182 Info
@@ -125,6 +126,7 @@ static int __init rd88f5182_dbgled_init(void)
125 126
126 leds_event = rd88f5182_dbgled_event; 127 leds_event = rd88f5182_dbgled_event;
127 } 128 }
129
128 return 0; 130 return 0;
129} 131}
130 132
@@ -220,7 +222,6 @@ subsys_initcall(rd88f5182_pci_init);
220 222
221static struct mv643xx_eth_platform_data rd88f5182_eth_data = { 223static struct mv643xx_eth_platform_data rd88f5182_eth_data = {
222 .phy_addr = 8, 224 .phy_addr = 8,
223 .force_phy_addr = 1,
224}; 225};
225 226
226/***************************************************************************** 227/*****************************************************************************
@@ -234,15 +235,34 @@ static struct i2c_board_info __initdata rd88f5182_i2c_rtc = {
234 * Sata 235 * Sata
235 ****************************************************************************/ 236 ****************************************************************************/
236static struct mv_sata_platform_data rd88f5182_sata_data = { 237static struct mv_sata_platform_data rd88f5182_sata_data = {
237 .n_ports = 2, 238 .n_ports = 2,
238}; 239};
239 240
240/***************************************************************************** 241/*****************************************************************************
241 * General Setup 242 * General Setup
242 ****************************************************************************/ 243 ****************************************************************************/
243 244static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
244static struct platform_device *rd88f5182_devices[] __initdata = { 245 { 0, MPP_GPIO }, /* Debug Led */
245 &rd88f5182_nor_flash, 246 { 1, MPP_GPIO }, /* Reset Switch */
247 { 2, MPP_UNUSED },
248 { 3, MPP_GPIO }, /* RTC Int */
249 { 4, MPP_GPIO },
250 { 5, MPP_GPIO },
251 { 6, MPP_GPIO }, /* PCI_intA */
252 { 7, MPP_GPIO }, /* PCI_intB */
253 { 8, MPP_UNUSED },
254 { 9, MPP_UNUSED },
255 { 10, MPP_UNUSED },
256 { 11, MPP_UNUSED },
257 { 12, MPP_SATA_LED }, /* SATA 0 presence */
258 { 13, MPP_SATA_LED }, /* SATA 1 presence */
259 { 14, MPP_SATA_LED }, /* SATA 0 active */
260 { 15, MPP_SATA_LED }, /* SATA 1 active */
261 { 16, MPP_UNUSED },
262 { 17, MPP_UNUSED },
263 { 18, MPP_UNUSED },
264 { 19, MPP_UNUSED },
265 { -1 },
246}; 266};
247 267
248static void __init rd88f5182_init(void) 268static void __init rd88f5182_init(void)
@@ -252,35 +272,9 @@ static void __init rd88f5182_init(void)
252 */ 272 */
253 orion5x_init(); 273 orion5x_init();
254 274
255 /* 275 orion5x_mpp_conf(rd88f5182_mpp_modes);
256 * Setup the CPU address decode windows for our devices
257 */
258 orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
259 RD88F5182_NOR_BOOT_SIZE);
260 orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
261
262 /*
263 * Open a special address decode windows for the PCIe WA.
264 */
265 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
266 ORION5X_PCIE_WA_SIZE);
267 276
268 /* 277 /*
269 * Setup Multiplexing Pins --
270 * MPP[0] Debug Led (GPIO - Out)
271 * MPP[1] Debug Led (GPIO - Out)
272 * MPP[2] N/A
273 * MPP[3] RTC_Int (GPIO - In)
274 * MPP[4] GPIO
275 * MPP[5] GPIO
276 * MPP[6] PCI_intA (GPIO - In)
277 * MPP[7] PCI_intB (GPIO - In)
278 * MPP[8-11] N/A
279 * MPP[12] SATA 0 presence Indication
280 * MPP[13] SATA 1 presence Indication
281 * MPP[14] SATA 0 active Indication
282 * MPP[15] SATA 1 active indication
283 * MPP[16-19] Not used
284 * MPP[20] PCI Clock to MV88F5182 278 * MPP[20] PCI Clock to MV88F5182
285 * MPP[21] PCI Clock to mini PCI CON11 279 * MPP[21] PCI Clock to mini PCI CON11
286 * MPP[22] USB 0 over current indication 280 * MPP[22] USB 0 over current indication
@@ -289,16 +283,23 @@ static void __init rd88f5182_init(void)
289 * MPP[25] USB 0 over current enable 283 * MPP[25] USB 0 over current enable
290 */ 284 */
291 285
292 orion5x_write(MPP_0_7_CTRL, 0x00000003); 286 /*
293 orion5x_write(MPP_8_15_CTRL, 0x55550000); 287 * Configure peripherals.
294 orion5x_write(MPP_16_19_CTRL, 0x5555); 288 */
289 orion5x_ehci0_init();
290 orion5x_ehci1_init();
291 orion5x_eth_init(&rd88f5182_eth_data);
292 orion5x_i2c_init();
293 orion5x_sata_init(&rd88f5182_sata_data);
294 orion5x_uart0_init();
295 295
296 orion5x_gpio_set_valid_pins(0x000000fb); 296 orion5x_setup_dev_boot_win(RD88F5182_NOR_BOOT_BASE,
297 RD88F5182_NOR_BOOT_SIZE);
298
299 orion5x_setup_dev1_win(RD88F5182_NOR_BASE, RD88F5182_NOR_SIZE);
300 platform_device_register(&rd88f5182_nor_flash);
297 301
298 platform_add_devices(rd88f5182_devices, ARRAY_SIZE(rd88f5182_devices));
299 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1); 302 i2c_register_board_info(0, &rd88f5182_i2c_rtc, 1);
300 orion5x_eth_init(&rd88f5182_eth_data);
301 orion5x_sata_init(&rd88f5182_sata_data);
302} 303}
303 304
304MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 305MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 9afb41ee6e07..a9cef9703d5b 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -28,6 +28,8 @@
28#include <asm/mach/pci.h> 28#include <asm/mach/pci.h>
29#include <asm/arch/orion5x.h> 29#include <asm/arch/orion5x.h>
30#include "common.h" 30#include "common.h"
31#include "mpp.h"
32#include "tsx09-common.h"
31 33
32#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000 34#define QNAP_TS209_NOR_BOOT_BASE 0xf4000000
33#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M 35#define QNAP_TS209_NOR_BOOT_SIZE SZ_8M
@@ -47,52 +49,54 @@
47 ***************************************************************************/ 49 ***************************************************************************/
48static struct mtd_partition qnap_ts209_partitions[] = { 50static struct mtd_partition qnap_ts209_partitions[] = {
49 { 51 {
50 .name = "U-Boot", 52 .name = "U-Boot",
51 .size = 0x00080000, 53 .size = 0x00080000,
52 .offset = 0x00780000, 54 .offset = 0x00780000,
53 .mask_flags = MTD_WRITEABLE, 55 .mask_flags = MTD_WRITEABLE,
54 }, { 56 }, {
55 .name = "Kernel", 57 .name = "Kernel",
56 .size = 0x00200000, 58 .size = 0x00200000,
57 .offset = 0, 59 .offset = 0,
58 }, { 60 }, {
59 .name = "RootFS1", 61 .name = "RootFS1",
60 .size = 0x00400000, 62 .size = 0x00400000,
61 .offset = 0x00200000, 63 .offset = 0x00200000,
62 }, { 64 }, {
63 .name = "RootFS2", 65 .name = "RootFS2",
64 .size = 0x00100000, 66 .size = 0x00100000,
65 .offset = 0x00600000, 67 .offset = 0x00600000,
66 }, { 68 }, {
67 .name = "U-Boot Config", 69 .name = "U-Boot Config",
68 .size = 0x00020000, 70 .size = 0x00020000,
69 .offset = 0x00760000, 71 .offset = 0x00760000,
70 }, { 72 }, {
71 .name = "NAS Config", 73 .name = "NAS Config",
72 .size = 0x00060000, 74 .size = 0x00060000,
73 .offset = 0x00700000, 75 .offset = 0x00700000,
74 .mask_flags = MTD_WRITEABLE, 76 .mask_flags = MTD_WRITEABLE,
75 } 77 },
76}; 78};
77 79
78static struct physmap_flash_data qnap_ts209_nor_flash_data = { 80static struct physmap_flash_data qnap_ts209_nor_flash_data = {
79 .width = 1, 81 .width = 1,
80 .parts = qnap_ts209_partitions, 82 .parts = qnap_ts209_partitions,
81 .nr_parts = ARRAY_SIZE(qnap_ts209_partitions) 83 .nr_parts = ARRAY_SIZE(qnap_ts209_partitions)
82}; 84};
83 85
84static struct resource qnap_ts209_nor_flash_resource = { 86static struct resource qnap_ts209_nor_flash_resource = {
85 .flags = IORESOURCE_MEM, 87 .flags = IORESOURCE_MEM,
86 .start = QNAP_TS209_NOR_BOOT_BASE, 88 .start = QNAP_TS209_NOR_BOOT_BASE,
87 .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1, 89 .end = QNAP_TS209_NOR_BOOT_BASE + QNAP_TS209_NOR_BOOT_SIZE - 1,
88}; 90};
89 91
90static struct platform_device qnap_ts209_nor_flash = { 92static struct platform_device qnap_ts209_nor_flash = {
91 .name = "physmap-flash", 93 .name = "physmap-flash",
92 .id = 0, 94 .id = 0,
93 .dev = { .platform_data = &qnap_ts209_nor_flash_data, }, 95 .dev = {
94 .resource = &qnap_ts209_nor_flash_resource, 96 .platform_data = &qnap_ts209_nor_flash_data,
95 .num_resources = 1, 97 },
98 .resource = &qnap_ts209_nor_flash_resource,
99 .num_resources = 1,
96}; 100};
97 101
98/***************************************************************************** 102/*****************************************************************************
@@ -164,12 +168,12 @@ static int __init qnap_ts209_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
164} 168}
165 169
166static struct hw_pci qnap_ts209_pci __initdata = { 170static struct hw_pci qnap_ts209_pci __initdata = {
167 .nr_controllers = 2, 171 .nr_controllers = 2,
168 .preinit = qnap_ts209_pci_preinit, 172 .preinit = qnap_ts209_pci_preinit,
169 .swizzle = pci_std_swizzle, 173 .swizzle = pci_std_swizzle,
170 .setup = orion5x_pci_sys_setup, 174 .setup = orion5x_pci_sys_setup,
171 .scan = orion5x_pci_sys_scan_bus, 175 .scan = orion5x_pci_sys_scan_bus,
172 .map_irq = qnap_ts209_pci_map_irq, 176 .map_irq = qnap_ts209_pci_map_irq,
173}; 177};
174 178
175static int __init qnap_ts209_pci_init(void) 179static int __init qnap_ts209_pci_init(void)
@@ -183,96 +187,6 @@ static int __init qnap_ts209_pci_init(void)
183subsys_initcall(qnap_ts209_pci_init); 187subsys_initcall(qnap_ts209_pci_init);
184 188
185/***************************************************************************** 189/*****************************************************************************
186 * Ethernet
187 ****************************************************************************/
188
189static struct mv643xx_eth_platform_data qnap_ts209_eth_data = {
190 .phy_addr = 8,
191 .force_phy_addr = 1,
192};
193
194static int __init parse_hex_nibble(char n)
195{
196 if (n >= '0' && n <= '9')
197 return n - '0';
198
199 if (n >= 'A' && n <= 'F')
200 return n - 'A' + 10;
201
202 if (n >= 'a' && n <= 'f')
203 return n - 'a' + 10;
204
205 return -1;
206}
207
208static int __init parse_hex_byte(const char *b)
209{
210 int hi;
211 int lo;
212
213 hi = parse_hex_nibble(b[0]);
214 lo = parse_hex_nibble(b[1]);
215
216 if (hi < 0 || lo < 0)
217 return -1;
218
219 return (hi << 4) | lo;
220}
221
222static int __init check_mac_addr(const char *addr_str)
223{
224 u_int8_t addr[6];
225 int i;
226
227 for (i = 0; i < 6; i++) {
228 int byte;
229
230 /*
231 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
232 */
233 if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
234 return -1;
235
236 byte = parse_hex_byte(addr_str + (i * 3));
237 if (byte < 0)
238 return -1;
239 addr[i] = byte;
240 }
241
242 printk(KERN_INFO "ts209: found ethernet mac address ");
243 for (i = 0; i < 6; i++)
244 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
245
246 memcpy(qnap_ts209_eth_data.mac_addr, addr, 6);
247
248 return 0;
249}
250
251/*
252 * The 'NAS Config' flash partition has an ext2 filesystem which
253 * contains a file that has the ethernet MAC address in plain text
254 * (format "xx:xx:xx:xx:xx:xx\n".)
255 */
256static void __init ts209_find_mac_addr(void)
257{
258 unsigned long addr;
259
260 for (addr = 0x00700000; addr < 0x00760000; addr += 1024) {
261 char *nor_page;
262 int ret = 0;
263
264 nor_page = ioremap(QNAP_TS209_NOR_BOOT_BASE + addr, 1024);
265 if (nor_page != NULL) {
266 ret = check_mac_addr(nor_page);
267 iounmap(nor_page);
268 }
269
270 if (ret == 0)
271 break;
272 }
273}
274
275/*****************************************************************************
276 * RTC S35390A on I2C bus 190 * RTC S35390A on I2C bus
277 ****************************************************************************/ 191 ****************************************************************************/
278 192
@@ -280,7 +194,7 @@ static void __init ts209_find_mac_addr(void)
280 194
281static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = { 195static struct i2c_board_info __initdata qnap_ts209_i2c_rtc = {
282 I2C_BOARD_INFO("s35390a", 0x30), 196 I2C_BOARD_INFO("s35390a", 0x30),
283 .irq = 0, 197 .irq = 0,
284}; 198};
285 199
286/**************************************************************************** 200/****************************************************************************
@@ -297,70 +211,63 @@ static struct gpio_keys_button qnap_ts209_buttons[] = {
297 .gpio = QNAP_TS209_GPIO_KEY_MEDIA, 211 .gpio = QNAP_TS209_GPIO_KEY_MEDIA,
298 .desc = "USB Copy Button", 212 .desc = "USB Copy Button",
299 .active_low = 1, 213 .active_low = 1,
300 }, 214 }, {
301 {
302 .code = KEY_POWER, 215 .code = KEY_POWER,
303 .gpio = QNAP_TS209_GPIO_KEY_RESET, 216 .gpio = QNAP_TS209_GPIO_KEY_RESET,
304 .desc = "Reset Button", 217 .desc = "Reset Button",
305 .active_low = 1, 218 .active_low = 1,
306 } 219 },
307}; 220};
308 221
309static struct gpio_keys_platform_data qnap_ts209_button_data = { 222static struct gpio_keys_platform_data qnap_ts209_button_data = {
310 .buttons = qnap_ts209_buttons, 223 .buttons = qnap_ts209_buttons,
311 .nbuttons = ARRAY_SIZE(qnap_ts209_buttons), 224 .nbuttons = ARRAY_SIZE(qnap_ts209_buttons),
312}; 225};
313 226
314static struct platform_device qnap_ts209_button_device = { 227static struct platform_device qnap_ts209_button_device = {
315 .name = "gpio-keys", 228 .name = "gpio-keys",
316 .id = -1, 229 .id = -1,
317 .num_resources = 0, 230 .num_resources = 0,
318 .dev = { .platform_data = &qnap_ts209_button_data, }, 231 .dev = {
232 .platform_data = &qnap_ts209_button_data,
233 },
319}; 234};
320 235
321/***************************************************************************** 236/*****************************************************************************
322 * SATA 237 * SATA
323 ****************************************************************************/ 238 ****************************************************************************/
324static struct mv_sata_platform_data qnap_ts209_sata_data = { 239static struct mv_sata_platform_data qnap_ts209_sata_data = {
325 .n_ports = 2, 240 .n_ports = 2,
326}; 241};
327 242
328/***************************************************************************** 243/*****************************************************************************
329 244
330 * General Setup 245 * General Setup
331 ****************************************************************************/ 246 ****************************************************************************/
332 247static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
333static struct platform_device *qnap_ts209_devices[] __initdata = { 248 { 0, MPP_UNUSED },
334 &qnap_ts209_nor_flash, 249 { 1, MPP_GPIO }, /* USB copy button */
335 &qnap_ts209_button_device, 250 { 2, MPP_GPIO }, /* Load defaults button */
251 { 3, MPP_GPIO }, /* GPIO RTC */
252 { 4, MPP_UNUSED },
253 { 5, MPP_UNUSED },
254 { 6, MPP_GPIO }, /* PCI Int A */
255 { 7, MPP_GPIO }, /* PCI Int B */
256 { 8, MPP_UNUSED },
257 { 9, MPP_UNUSED },
258 { 10, MPP_UNUSED },
259 { 11, MPP_UNUSED },
260 { 12, MPP_SATA_LED }, /* SATA 0 presence */
261 { 13, MPP_SATA_LED }, /* SATA 1 presence */
262 { 14, MPP_SATA_LED }, /* SATA 0 active */
263 { 15, MPP_SATA_LED }, /* SATA 1 active */
264 { 16, MPP_UART }, /* UART1 RXD */
265 { 17, MPP_UART }, /* UART1 TXD */
266 { 18, MPP_GPIO }, /* SW_RST */
267 { 19, MPP_UNUSED },
268 { -1 },
336}; 269};
337 270
338/*
339 * QNAP TS-[12]09 specific power off method via UART1-attached PIC
340 */
341
342#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
343
344static void qnap_ts209_power_off(void)
345{
346 /* 19200 baud divisor */
347 const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
348
349 pr_info("%s: triggering power-off...\n", __func__);
350
351 /* hijack uart1 and reset into sane state (19200,8n1) */
352 orion5x_write(UART1_REG(LCR), 0x83);
353 orion5x_write(UART1_REG(DLL), divisor & 0xff);
354 orion5x_write(UART1_REG(DLM), (divisor >> 8) & 0xff);
355 orion5x_write(UART1_REG(LCR), 0x03);
356 orion5x_write(UART1_REG(IER), 0x00);
357 orion5x_write(UART1_REG(FCR), 0x00);
358 orion5x_write(UART1_REG(MCR), 0x00);
359
360 /* send the power-off command 'A' to PIC */
361 orion5x_write(UART1_REG(TX), 'A');
362}
363
364static void __init qnap_ts209_init(void) 271static void __init qnap_ts209_init(void)
365{ 272{
366 /* 273 /*
@@ -368,51 +275,33 @@ static void __init qnap_ts209_init(void)
368 */ 275 */
369 orion5x_init(); 276 orion5x_init();
370 277
371 /* 278 orion5x_mpp_conf(ts209_mpp_modes);
372 * Setup flash mapping
373 */
374 orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
375 QNAP_TS209_NOR_BOOT_SIZE);
376
377 /*
378 * Open a special address decode windows for the PCIe WA.
379 */
380 orion5x_setup_pcie_wa_win(ORION5X_PCIE_WA_PHYS_BASE,
381 ORION5X_PCIE_WA_SIZE);
382 279
383 /* 280 /*
384 * Setup Multiplexing Pins --
385 * MPP[0] Reserved
386 * MPP[1] USB copy button (0 active)
387 * MPP[2] Load defaults button (0 active)
388 * MPP[3] GPIO RTC
389 * MPP[4-5] Reserved
390 * MPP[6] PCI Int A
391 * MPP[7] PCI Int B
392 * MPP[8-11] Reserved
393 * MPP[12] SATA 0 presence
394 * MPP[13] SATA 1 presence
395 * MPP[14] SATA 0 active
396 * MPP[15] SATA 1 active
397 * MPP[16] UART1 RXD
398 * MPP[17] UART1 TXD
399 * MPP[18] SW_RST (0 active)
400 * MPP[19] Reserved
401 * MPP[20] PCI clock 0 281 * MPP[20] PCI clock 0
402 * MPP[21] PCI clock 1 282 * MPP[21] PCI clock 1
403 * MPP[22] USB 0 over current 283 * MPP[22] USB 0 over current
404 * MPP[23-25] Reserved 284 * MPP[23-25] Reserved
405 */ 285 */
406 orion5x_write(MPP_0_7_CTRL, 0x3);
407 orion5x_write(MPP_8_15_CTRL, 0x55550000);
408 orion5x_write(MPP_16_19_CTRL, 0x5500);
409 orion5x_gpio_set_valid_pins(0x3cc0fff);
410 286
411 /* register ts209 specific power-off method */ 287 /*
412 pm_power_off = qnap_ts209_power_off; 288 * Configure peripherals.
289 */
290 orion5x_ehci0_init();
291 orion5x_ehci1_init();
292 qnap_tsx09_find_mac_addr(QNAP_TS209_NOR_BOOT_BASE +
293 qnap_ts209_partitions[5].offset,
294 qnap_ts209_partitions[5].size);
295 orion5x_eth_init(&qnap_tsx09_eth_data);
296 orion5x_i2c_init();
297 orion5x_sata_init(&qnap_ts209_sata_data);
298 orion5x_uart0_init();
299
300 orion5x_setup_dev_boot_win(QNAP_TS209_NOR_BOOT_BASE,
301 QNAP_TS209_NOR_BOOT_SIZE);
302 platform_device_register(&qnap_ts209_nor_flash);
413 303
414 platform_add_devices(qnap_ts209_devices, 304 platform_device_register(&qnap_ts209_button_device);
415 ARRAY_SIZE(qnap_ts209_devices));
416 305
417 /* Get RTC IRQ and register the chip */ 306 /* Get RTC IRQ and register the chip */
418 if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) { 307 if (gpio_request(TS209_RTC_GPIO, "rtc") == 0) {
@@ -425,14 +314,12 @@ static void __init qnap_ts209_init(void)
425 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n"); 314 pr_warning("qnap_ts209_init: failed to get RTC IRQ\n");
426 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1); 315 i2c_register_board_info(0, &qnap_ts209_i2c_rtc, 1);
427 316
428 ts209_find_mac_addr(); 317 /* register tsx09 specific power-off method */
429 orion5x_eth_init(&qnap_ts209_eth_data); 318 pm_power_off = qnap_tsx09_power_off;
430
431 orion5x_sata_init(&qnap_ts209_sata_data);
432} 319}
433 320
434MACHINE_START(TS209, "QNAP TS-109/TS-209") 321MACHINE_START(TS209, "QNAP TS-109/TS-209")
435 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 322 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
436 .phys_io = ORION5X_REGS_PHYS_BASE, 323 .phys_io = ORION5X_REGS_PHYS_BASE,
437 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC, 324 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
438 .boot_params = 0x00000100, 325 .boot_params = 0x00000100,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
new file mode 100644
index 000000000000..32f0ff073b7e
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -0,0 +1,273 @@
1/*
2 * QNAP TS-409 Board Setup
3 *
4 * Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/platform_device.h>
15#include <linux/pci.h>
16#include <linux/irq.h>
17#include <linux/mtd/physmap.h>
18#include <linux/mv643xx_eth.h>
19#include <linux/gpio_keys.h>
20#include <linux/input.h>
21#include <linux/i2c.h>
22#include <linux/serial_reg.h>
23#include <asm/mach-types.h>
24#include <asm/gpio.h>
25#include <asm/mach/arch.h>
26#include <asm/mach/pci.h>
27#include <asm/arch/orion5x.h>
28#include "common.h"
29#include "mpp.h"
30#include "tsx09-common.h"
31
32/*****************************************************************************
33 * QNAP TS-409 Info
34 ****************************************************************************/
35
36/*
37 * QNAP TS-409 hardware :
38 * - Marvell 88F5281-D0
39 * - Marvell 88SX7042 SATA controller (PCIe)
40 * - Marvell 88E1118 Gigabit Ethernet PHY
41 * - RTC S35390A (@0x30) on I2C bus
42 * - 8MB NOR flash
43 * - 256MB of DDR-2 RAM
44 */
45
46/*
47 * 8MB NOR flash Device bus boot chip select
48 */
49
50#define QNAP_TS409_NOR_BOOT_BASE 0xff800000
51#define QNAP_TS409_NOR_BOOT_SIZE SZ_8M
52
53/****************************************************************************
54 * 8MiB NOR flash. The struct mtd_partition is not in the same order as the
55 * partitions on the device because we want to keep compatability with
56 * existing QNAP firmware.
57 *
58 * Layout as used by QNAP:
59 * [2] 0x00000000-0x00200000 : "Kernel"
60 * [3] 0x00200000-0x00600000 : "RootFS1"
61 * [4] 0x00600000-0x00700000 : "RootFS2"
62 * [6] 0x00700000-0x00760000 : "NAS Config" (read-only)
63 * [5] 0x00760000-0x00780000 : "U-Boot Config"
64 * [1] 0x00780000-0x00800000 : "U-Boot" (read-only)
65 ***************************************************************************/
66static struct mtd_partition qnap_ts409_partitions[] = {
67 {
68 .name = "U-Boot",
69 .size = 0x00080000,
70 .offset = 0x00780000,
71 .mask_flags = MTD_WRITEABLE,
72 }, {
73 .name = "Kernel",
74 .size = 0x00200000,
75 .offset = 0,
76 }, {
77 .name = "RootFS1",
78 .size = 0x00400000,
79 .offset = 0x00200000,
80 }, {
81 .name = "RootFS2",
82 .size = 0x00100000,
83 .offset = 0x00600000,
84 }, {
85 .name = "U-Boot Config",
86 .size = 0x00020000,
87 .offset = 0x00760000,
88 }, {
89 .name = "NAS Config",
90 .size = 0x00060000,
91 .offset = 0x00700000,
92 .mask_flags = MTD_WRITEABLE,
93 },
94};
95
96static struct physmap_flash_data qnap_ts409_nor_flash_data = {
97 .width = 1,
98 .parts = qnap_ts409_partitions,
99 .nr_parts = ARRAY_SIZE(qnap_ts409_partitions)
100};
101
102static struct resource qnap_ts409_nor_flash_resource = {
103 .flags = IORESOURCE_MEM,
104 .start = QNAP_TS409_NOR_BOOT_BASE,
105 .end = QNAP_TS409_NOR_BOOT_BASE + QNAP_TS409_NOR_BOOT_SIZE - 1,
106};
107
108static struct platform_device qnap_ts409_nor_flash = {
109 .name = "physmap-flash",
110 .id = 0,
111 .dev = { .platform_data = &qnap_ts409_nor_flash_data, },
112 .num_resources = 1,
113 .resource = &qnap_ts409_nor_flash_resource,
114};
115
116/*****************************************************************************
117 * PCI
118 ****************************************************************************/
119
120static int __init qnap_ts409_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
121{
122 int irq;
123
124 /*
125 * Check for devices with hard-wired IRQs.
126 */
127 irq = orion5x_pci_map_irq(dev, slot, pin);
128 if (irq != -1)
129 return irq;
130
131 /*
132 * PCI isn't used on the TS-409
133 */
134 return -1;
135}
136
137static struct hw_pci qnap_ts409_pci __initdata = {
138 .nr_controllers = 2,
139 .swizzle = pci_std_swizzle,
140 .setup = orion5x_pci_sys_setup,
141 .scan = orion5x_pci_sys_scan_bus,
142 .map_irq = qnap_ts409_pci_map_irq,
143};
144
145static int __init qnap_ts409_pci_init(void)
146{
147 if (machine_is_ts409())
148 pci_common_init(&qnap_ts409_pci);
149
150 return 0;
151}
152
153subsys_initcall(qnap_ts409_pci_init);
154
155/*****************************************************************************
156 * RTC S35390A on I2C bus
157 ****************************************************************************/
158
159#define TS409_RTC_GPIO 10
160
161static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
162 I2C_BOARD_INFO("s35390a", 0x30),
163};
164
165/****************************************************************************
166 * GPIO Attached Keys
167 * Power button is attached to the PIC microcontroller
168 ****************************************************************************/
169
170#define QNAP_TS409_GPIO_KEY_MEDIA 15
171
172static struct gpio_keys_button qnap_ts409_buttons[] = {
173 {
174 .code = KEY_RESTART,
175 .gpio = QNAP_TS409_GPIO_KEY_MEDIA,
176 .desc = "USB Copy Button",
177 .active_low = 1,
178 },
179};
180
181static struct gpio_keys_platform_data qnap_ts409_button_data = {
182 .buttons = qnap_ts409_buttons,
183 .nbuttons = ARRAY_SIZE(qnap_ts409_buttons),
184};
185
186static struct platform_device qnap_ts409_button_device = {
187 .name = "gpio-keys",
188 .id = -1,
189 .num_resources = 0,
190 .dev = {
191 .platform_data = &qnap_ts409_button_data,
192 },
193};
194
195/*****************************************************************************
196 * General Setup
197 ****************************************************************************/
198static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
199 { 0, MPP_UNUSED },
200 { 1, MPP_UNUSED },
201 { 2, MPP_UNUSED },
202 { 3, MPP_UNUSED },
203 { 4, MPP_GPIO }, /* HDD 1 status */
204 { 5, MPP_GPIO }, /* HDD 2 status */
205 { 6, MPP_GPIO }, /* HDD 3 status */
206 { 7, MPP_GPIO }, /* HDD 4 status */
207 { 8, MPP_UNUSED },
208 { 9, MPP_UNUSED },
209 { 10, MPP_GPIO }, /* RTC int */
210 { 11, MPP_UNUSED },
211 { 12, MPP_UNUSED },
212 { 13, MPP_UNUSED },
213 { 14, MPP_GPIO }, /* SW_RST */
214 { 15, MPP_GPIO }, /* USB copy button */
215 { 16, MPP_UART }, /* UART1 RXD */
216 { 17, MPP_UART }, /* UART1 TXD */
217 { 18, MPP_UNUSED },
218 { 19, MPP_UNUSED },
219 { -1 },
220};
221
222static void __init qnap_ts409_init(void)
223{
224 /*
225 * Setup basic Orion functions. Need to be called early.
226 */
227 orion5x_init();
228
229 orion5x_mpp_conf(ts409_mpp_modes);
230
231 /*
232 * Configure peripherals.
233 */
234 orion5x_ehci0_init();
235 qnap_tsx09_find_mac_addr(QNAP_TS409_NOR_BOOT_BASE +
236 qnap_ts409_partitions[5].offset,
237 qnap_ts409_partitions[5].size);
238 orion5x_eth_init(&qnap_tsx09_eth_data);
239 orion5x_i2c_init();
240 orion5x_uart0_init();
241
242 orion5x_setup_dev_boot_win(QNAP_TS409_NOR_BOOT_BASE,
243 QNAP_TS409_NOR_BOOT_SIZE);
244 platform_device_register(&qnap_ts409_nor_flash);
245
246 platform_device_register(&qnap_ts409_button_device);
247
248 /* Get RTC IRQ and register the chip */
249 if (gpio_request(TS409_RTC_GPIO, "rtc") == 0) {
250 if (gpio_direction_input(TS409_RTC_GPIO) == 0)
251 qnap_ts409_i2c_rtc.irq = gpio_to_irq(TS409_RTC_GPIO);
252 else
253 gpio_free(TS409_RTC_GPIO);
254 }
255 if (qnap_ts409_i2c_rtc.irq == 0)
256 pr_warning("qnap_ts409_init: failed to get RTC IRQ\n");
257 i2c_register_board_info(0, &qnap_ts409_i2c_rtc, 1);
258
259 /* register tsx09 specific power-off method */
260 pm_power_off = qnap_tsx09_power_off;
261}
262
263MACHINE_START(TS409, "QNAP TS-409")
264 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
265 .phys_io = ORION5X_REGS_PHYS_BASE,
266 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
267 .boot_params = 0x00000100,
268 .init_machine = qnap_ts409_init,
269 .map_io = orion5x_map_io,
270 .init_irq = orion5x_init_irq,
271 .timer = &orion5x_timer,
272 .fixup = tag_fixup_mem32,
273MACHINE_END
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
new file mode 100644
index 000000000000..77e9f351f07a
--- /dev/null
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -0,0 +1,277 @@
1/*
2 * arch/arm/mach-orion5x/ts78xx-setup.c
3 *
4 * Maintainer: Alexander Clouter <alex@digriz.org.uk>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/mtd/physmap.h>
15#include <linux/mv643xx_eth.h>
16#include <linux/ata_platform.h>
17#include <linux/m48t86.h>
18#include <asm/mach-types.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/map.h>
21#include <asm/arch/orion5x.h>
22#include "common.h"
23#include "mpp.h"
24
25/*****************************************************************************
26 * TS-78xx Info
27 ****************************************************************************/
28
29/*
30 * FPGA - lives where the PCI bus would be at ORION5X_PCI_MEM_PHYS_BASE
31 */
32#define TS78XX_FPGA_REGS_PHYS_BASE 0xe8000000
33#define TS78XX_FPGA_REGS_VIRT_BASE 0xff900000
34#define TS78XX_FPGA_REGS_SIZE SZ_1M
35
36#define TS78XX_FPGA_REGS_SYSCON_ID (TS78XX_FPGA_REGS_VIRT_BASE | 0x000)
37#define TS78XX_FPGA_REGS_SYSCON_LCDI (TS78XX_FPGA_REGS_VIRT_BASE | 0x004)
38#define TS78XX_FPGA_REGS_SYSCON_LCDO (TS78XX_FPGA_REGS_VIRT_BASE | 0x008)
39
40#define TS78XX_FPGA_REGS_RTC_CTRL (TS78XX_FPGA_REGS_VIRT_BASE | 0x808)
41#define TS78XX_FPGA_REGS_RTC_DATA (TS78XX_FPGA_REGS_VIRT_BASE | 0x80c)
42
43/*
44 * 512kB NOR flash Device
45 */
46#define TS78XX_NOR_BOOT_BASE 0xff800000
47#define TS78XX_NOR_BOOT_SIZE SZ_512K
48
49/*****************************************************************************
50 * I/O Address Mapping
51 ****************************************************************************/
52static struct map_desc ts78xx_io_desc[] __initdata = {
53 {
54 .virtual = TS78XX_FPGA_REGS_VIRT_BASE,
55 .pfn = __phys_to_pfn(TS78XX_FPGA_REGS_PHYS_BASE),
56 .length = TS78XX_FPGA_REGS_SIZE,
57 .type = MT_DEVICE,
58 },
59};
60
61void __init ts78xx_map_io(void)
62{
63 orion5x_map_io();
64 iotable_init(ts78xx_io_desc, ARRAY_SIZE(ts78xx_io_desc));
65}
66
67/*****************************************************************************
68 * 512kB NOR Boot Flash - the chip is a M25P40
69 ****************************************************************************/
70static struct mtd_partition ts78xx_nor_boot_flash_resources[] = {
71 {
72 .name = "ts-bootrom",
73 .offset = 0,
74 /* only the first 256kB is used */
75 .size = SZ_256K,
76 .mask_flags = MTD_WRITEABLE,
77 },
78};
79
80static struct physmap_flash_data ts78xx_nor_boot_flash_data = {
81 .width = 1,
82 .parts = ts78xx_nor_boot_flash_resources,
83 .nr_parts = ARRAY_SIZE(ts78xx_nor_boot_flash_resources),
84};
85
86static struct resource ts78xx_nor_boot_flash_resource = {
87 .flags = IORESOURCE_MEM,
88 .start = TS78XX_NOR_BOOT_BASE,
89 .end = TS78XX_NOR_BOOT_BASE + TS78XX_NOR_BOOT_SIZE - 1,
90};
91
92static struct platform_device ts78xx_nor_boot_flash = {
93 .name = "physmap-flash",
94 .id = -1,
95 .dev = {
96 .platform_data = &ts78xx_nor_boot_flash_data,
97 },
98 .num_resources = 1,
99 .resource = &ts78xx_nor_boot_flash_resource,
100};
101
102/*****************************************************************************
103 * Ethernet
104 ****************************************************************************/
105static struct mv643xx_eth_platform_data ts78xx_eth_data = {
106 .phy_addr = 0,
107 .force_phy_addr = 1,
108};
109
110/*****************************************************************************
111 * RTC M48T86 - nicked^Wborrowed from arch/arm/mach-ep93xx/ts72xx.c
112 ****************************************************************************/
113#ifdef CONFIG_RTC_DRV_M48T86
114static unsigned char ts78xx_rtc_readbyte(unsigned long addr)
115{
116 writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
117 return readb(TS78XX_FPGA_REGS_RTC_DATA);
118}
119
120static void ts78xx_rtc_writebyte(unsigned char value, unsigned long addr)
121{
122 writeb(addr, TS78XX_FPGA_REGS_RTC_CTRL);
123 writeb(value, TS78XX_FPGA_REGS_RTC_DATA);
124}
125
126static struct m48t86_ops ts78xx_rtc_ops = {
127 .readbyte = ts78xx_rtc_readbyte,
128 .writebyte = ts78xx_rtc_writebyte,
129};
130
131static struct platform_device ts78xx_rtc_device = {
132 .name = "rtc-m48t86",
133 .id = -1,
134 .dev = {
135 .platform_data = &ts78xx_rtc_ops,
136 },
137 .num_resources = 0,
138};
139
140/*
141 * TS uses some of the user storage space on the RTC chip so see if it is
142 * present; as it's an optional feature at purchase time and not all boards
143 * will have it present
144 *
145 * I've used the method TS use in their rtc7800.c example for the detection
146 *
147 * TODO: track down a guinea pig without an RTC to see if we can work out a
148 * better RTC detection routine
149 */
150static int __init ts78xx_rtc_init(void)
151{
152 unsigned char tmp_rtc0, tmp_rtc1;
153
154 tmp_rtc0 = ts78xx_rtc_readbyte(126);
155 tmp_rtc1 = ts78xx_rtc_readbyte(127);
156
157 ts78xx_rtc_writebyte(0x00, 126);
158 ts78xx_rtc_writebyte(0x55, 127);
159 if (ts78xx_rtc_readbyte(127) == 0x55) {
160 ts78xx_rtc_writebyte(0xaa, 127);
161 if (ts78xx_rtc_readbyte(127) == 0xaa
162 && ts78xx_rtc_readbyte(126) == 0x00) {
163 ts78xx_rtc_writebyte(tmp_rtc0, 126);
164 ts78xx_rtc_writebyte(tmp_rtc1, 127);
165 platform_device_register(&ts78xx_rtc_device);
166 return 1;
167 }
168 }
169
170 return 0;
171};
172#else
173static int __init ts78xx_rtc_init(void)
174{
175 return 0;
176}
177#endif
178
179/*****************************************************************************
180 * SATA
181 ****************************************************************************/
182static struct mv_sata_platform_data ts78xx_sata_data = {
183 .n_ports = 2,
184};
185
186/*****************************************************************************
187 * print some information regarding the board
188 ****************************************************************************/
189static void __init ts78xx_print_board_id(void)
190{
191 unsigned int board_info;
192
193 board_info = readl(TS78XX_FPGA_REGS_SYSCON_ID);
194 printk(KERN_INFO "TS-78xx Info: FPGA rev=%.2x, Board Magic=%.6x, ",
195 board_info & 0xff,
196 (board_info >> 8) & 0xffffff);
197 board_info = readl(TS78XX_FPGA_REGS_SYSCON_LCDI);
198 printk("JP1=%d, JP2=%d\n",
199 (board_info >> 30) & 0x1,
200 (board_info >> 31) & 0x1);
201};
202
203/*****************************************************************************
204 * General Setup
205 ****************************************************************************/
206static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
207 { 0, MPP_UNUSED },
208 { 1, MPP_GPIO }, /* JTAG Clock */
209 { 2, MPP_GPIO }, /* JTAG Data In */
210 { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */
211 { 4, MPP_GPIO }, /* JTAG Data Out */
212 { 5, MPP_GPIO }, /* JTAG TMS */
213 { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
214 { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */
215 { 8, MPP_UNUSED },
216 { 9, MPP_UNUSED },
217 { 10, MPP_UNUSED },
218 { 11, MPP_UNUSED },
219 { 12, MPP_UNUSED },
220 { 13, MPP_UNUSED },
221 { 14, MPP_UNUSED },
222 { 15, MPP_UNUSED },
223 { 16, MPP_UART },
224 { 17, MPP_UART },
225 { 18, MPP_UART },
226 { 19, MPP_UART },
227 { -1 },
228};
229
230static void __init ts78xx_init(void)
231{
232 /*
233 * Setup basic Orion functions. Need to be called early.
234 */
235 orion5x_init();
236
237 ts78xx_print_board_id();
238
239 orion5x_mpp_conf(ts78xx_mpp_modes);
240
241 /*
242 * MPP[20] PCI Clock Out 1
243 * MPP[21] PCI Clock Out 0
244 * MPP[22] Unused
245 * MPP[23] Unused
246 * MPP[24] Unused
247 * MPP[25] Unused
248 */
249
250 /*
251 * Configure peripherals.
252 */
253 orion5x_ehci0_init();
254 orion5x_ehci1_init();
255 orion5x_eth_init(&ts78xx_eth_data);
256 orion5x_sata_init(&ts78xx_sata_data);
257 orion5x_uart0_init();
258 orion5x_uart1_init();
259
260 orion5x_setup_dev_boot_win(TS78XX_NOR_BOOT_BASE,
261 TS78XX_NOR_BOOT_SIZE);
262 platform_device_register(&ts78xx_nor_boot_flash);
263
264 if (!ts78xx_rtc_init())
265 printk(KERN_INFO "TS-78xx RTC not detected or enabled\n");
266}
267
268MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
269 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
270 .phys_io = ORION5X_REGS_PHYS_BASE,
271 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
272 .boot_params = 0x00000100,
273 .init_machine = ts78xx_init,
274 .map_io = ts78xx_map_io,
275 .init_irq = orion5x_init_irq,
276 .timer = &orion5x_timer,
277MACHINE_END
diff --git a/arch/arm/mach-orion5x/tsx09-common.c b/arch/arm/mach-orion5x/tsx09-common.c
new file mode 100644
index 000000000000..83feac3147a6
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.c
@@ -0,0 +1,133 @@
1/*
2 * QNAP TS-x09 Boards common functions
3 *
4 * Maintainers: Lennert Buytenhek <buytenh@marvell.com>
5 * Byron Bradley <byron.bbradley@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/kernel.h>
14#include <linux/pci.h>
15#include <linux/mv643xx_eth.h>
16#include <linux/timex.h>
17#include <linux/serial_reg.h>
18#include "tsx09-common.h"
19
20/*****************************************************************************
21 * QNAP TS-x09 specific power off method via UART1-attached PIC
22 ****************************************************************************/
23
24#define UART1_REG(x) (UART1_VIRT_BASE + ((UART_##x) << 2))
25
26void qnap_tsx09_power_off(void)
27{
28 /* 19200 baud divisor */
29 const unsigned divisor = ((ORION5X_TCLK + (8 * 19200)) / (16 * 19200));
30
31 pr_info("%s: triggering power-off...\n", __func__);
32
33 /* hijack uart1 and reset into sane state (19200,8n1) */
34 writel(0x83, UART1_REG(LCR));
35 writel(divisor & 0xff, UART1_REG(DLL));
36 writel((divisor >> 8) & 0xff, UART1_REG(DLM));
37 writel(0x03, UART1_REG(LCR));
38 writel(0x00, UART1_REG(IER));
39 writel(0x00, UART1_REG(FCR));
40 writel(0x00, UART1_REG(MCR));
41
42 /* send the power-off command 'A' to PIC */
43 writel('A', UART1_REG(TX));
44}
45
46/*****************************************************************************
47 * Ethernet
48 ****************************************************************************/
49
50struct mv643xx_eth_platform_data qnap_tsx09_eth_data = {
51 .phy_addr = 8,
52};
53
54static int __init qnap_tsx09_parse_hex_nibble(char n)
55{
56 if (n >= '0' && n <= '9')
57 return n - '0';
58
59 if (n >= 'A' && n <= 'F')
60 return n - 'A' + 10;
61
62 if (n >= 'a' && n <= 'f')
63 return n - 'a' + 10;
64
65 return -1;
66}
67
68static int __init qnap_tsx09_parse_hex_byte(const char *b)
69{
70 int hi;
71 int lo;
72
73 hi = qnap_tsx09_parse_hex_nibble(b[0]);
74 lo = qnap_tsx09_parse_hex_nibble(b[1]);
75
76 if (hi < 0 || lo < 0)
77 return -1;
78
79 return (hi << 4) | lo;
80}
81
82static int __init qnap_tsx09_check_mac_addr(const char *addr_str)
83{
84 u_int8_t addr[6];
85 int i;
86
87 for (i = 0; i < 6; i++) {
88 int byte;
89
90 /*
91 * Enforce "xx:xx:xx:xx:xx:xx\n" format.
92 */
93 if (addr_str[(i * 3) + 2] != ((i < 5) ? ':' : '\n'))
94 return -1;
95
96 byte = qnap_tsx09_parse_hex_byte(addr_str + (i * 3));
97 if (byte < 0)
98 return -1;
99 addr[i] = byte;
100 }
101
102 printk(KERN_INFO "tsx09: found ethernet mac address ");
103 for (i = 0; i < 6; i++)
104 printk("%.2x%s", addr[i], (i < 5) ? ":" : ".\n");
105
106 memcpy(qnap_tsx09_eth_data.mac_addr, addr, 6);
107
108 return 0;
109}
110
111/*
112 * The 'NAS Config' flash partition has an ext2 filesystem which
113 * contains a file that has the ethernet MAC address in plain text
114 * (format "xx:xx:xx:xx:xx:xx\n").
115 */
116void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size)
117{
118 unsigned long addr;
119
120 for (addr = mem_base; addr < (mem_base + size); addr += 1024) {
121 char *nor_page;
122 int ret = 0;
123
124 nor_page = ioremap(addr, 1024);
125 if (nor_page != NULL) {
126 ret = qnap_tsx09_check_mac_addr(nor_page);
127 iounmap(nor_page);
128 }
129
130 if (ret == 0)
131 break;
132 }
133}
diff --git a/arch/arm/mach-orion5x/tsx09-common.h b/arch/arm/mach-orion5x/tsx09-common.h
new file mode 100644
index 000000000000..0984264616f0
--- /dev/null
+++ b/arch/arm/mach-orion5x/tsx09-common.h
@@ -0,0 +1,20 @@
1#ifndef __ARCH_ORION5X_TSX09_COMMON_H
2#define __ARCH_ORION5X_TSX09_COMMON_H
3
4/*
5 * QNAP TS-x09 Boards power-off function
6 */
7extern void qnap_tsx09_power_off(void);
8
9/*
10 * QNAP TS-x09 Boards function to find Ethernet MAC address in flash memory
11 */
12extern void __init qnap_tsx09_find_mac_addr(u32 mem_base, u32 size);
13
14/*
15 * QNAP TS-x09 Boards ethernet declaration
16 */
17extern struct mv643xx_eth_platform_data qnap_tsx09_eth_data;
18
19
20#endif
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
new file mode 100644
index 000000000000..1af093ff8cf3
--- /dev/null
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -0,0 +1,164 @@
1/*
2 * arch/arm/mach-orion5x/wnr854t-setup.c
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/pci.h>
13#include <linux/irq.h>
14#include <linux/delay.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mv643xx_eth.h>
17#include <asm/mach-types.h>
18#include <asm/gpio.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/pci.h>
21#include <asm/arch/orion5x.h>
22#include "common.h"
23#include "mpp.h"
24
25static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
26 { 0, MPP_GPIO }, /* Power LED green (0=on) */
27 { 1, MPP_GPIO }, /* Reset Button (0=off) */
28 { 2, MPP_GPIO }, /* Power LED blink (0=off) */
29 { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */
30 { 4, MPP_GPIO }, /* PCI int */
31 { 5, MPP_GPIO }, /* ??? */
32 { 6, MPP_GPIO }, /* ??? */
33 { 7, MPP_GPIO }, /* ??? */
34 { 8, MPP_UNUSED }, /* ??? */
35 { 9, MPP_GIGE }, /* GE_RXERR */
36 { 10, MPP_UNUSED }, /* ??? */
37 { 11, MPP_UNUSED }, /* ??? */
38 { 12, MPP_GIGE }, /* GE_TXD[4] */
39 { 13, MPP_GIGE }, /* GE_TXD[5] */
40 { 14, MPP_GIGE }, /* GE_TXD[6] */
41 { 15, MPP_GIGE }, /* GE_TXD[7] */
42 { 16, MPP_GIGE }, /* GE_RXD[4] */
43 { 17, MPP_GIGE }, /* GE_RXD[5] */
44 { 18, MPP_GIGE }, /* GE_RXD[6] */
45 { 19, MPP_GIGE }, /* GE_RXD[7] */
46 { -1 },
47};
48
49/*
50 * 8M NOR flash Device bus boot chip select
51 */
52#define WNR854T_NOR_BOOT_BASE 0xf4000000
53#define WNR854T_NOR_BOOT_SIZE SZ_8M
54
55static struct mtd_partition wnr854t_nor_flash_partitions[] = {
56 {
57 .name = "kernel",
58 .offset = 0x00000000,
59 .size = 0x00100000,
60 }, {
61 .name = "rootfs",
62 .offset = 0x00100000,
63 .size = 0x00660000,
64 }, {
65 .name = "uboot",
66 .offset = 0x00760000,
67 .size = 0x00040000,
68 },
69};
70
71static struct physmap_flash_data wnr854t_nor_flash_data = {
72 .width = 2,
73 .parts = wnr854t_nor_flash_partitions,
74 .nr_parts = ARRAY_SIZE(wnr854t_nor_flash_partitions),
75};
76
77static struct resource wnr854t_nor_flash_resource = {
78 .flags = IORESOURCE_MEM,
79 .start = WNR854T_NOR_BOOT_BASE,
80 .end = WNR854T_NOR_BOOT_BASE + WNR854T_NOR_BOOT_SIZE - 1,
81};
82
83static struct platform_device wnr854t_nor_flash = {
84 .name = "physmap-flash",
85 .id = 0,
86 .dev = {
87 .platform_data = &wnr854t_nor_flash_data,
88 },
89 .num_resources = 1,
90 .resource = &wnr854t_nor_flash_resource,
91};
92
93static struct mv643xx_eth_platform_data wnr854t_eth_data = {
94 .phy_addr = -1,
95};
96
97static void __init wnr854t_init(void)
98{
99 /*
100 * Setup basic Orion functions. Need to be called early.
101 */
102 orion5x_init();
103
104 orion5x_mpp_conf(wnr854t_mpp_modes);
105
106 /*
107 * Configure peripherals.
108 */
109 orion5x_eth_init(&wnr854t_eth_data);
110 orion5x_uart0_init();
111
112 orion5x_setup_dev_boot_win(WNR854T_NOR_BOOT_BASE,
113 WNR854T_NOR_BOOT_SIZE);
114 platform_device_register(&wnr854t_nor_flash);
115}
116
117static int __init wnr854t_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
118{
119 int irq;
120
121 /*
122 * Check for devices with hard-wired IRQs.
123 */
124 irq = orion5x_pci_map_irq(dev, slot, pin);
125 if (irq != -1)
126 return irq;
127
128 /*
129 * Mini-PCI slot.
130 */
131 if (slot == 7)
132 return gpio_to_irq(4);
133
134 return -1;
135}
136
137static struct hw_pci wnr854t_pci __initdata = {
138 .nr_controllers = 2,
139 .swizzle = pci_std_swizzle,
140 .setup = orion5x_pci_sys_setup,
141 .scan = orion5x_pci_sys_scan_bus,
142 .map_irq = wnr854t_pci_map_irq,
143};
144
145static int __init wnr854t_pci_init(void)
146{
147 if (machine_is_wnr854t())
148 pci_common_init(&wnr854t_pci);
149
150 return 0;
151}
152subsys_initcall(wnr854t_pci_init);
153
154MACHINE_START(WNR854T, "Netgear WNR854T")
155 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
156 .phys_io = ORION5X_REGS_PHYS_BASE,
157 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
158 .boot_params = 0x00000100,
159 .init_machine = wnr854t_init,
160 .map_io = orion5x_map_io,
161 .init_irq = orion5x_init_irq,
162 .timer = &orion5x_timer,
163 .fixup = tag_fixup_mem32,
164MACHINE_END
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
new file mode 100644
index 000000000000..aeab55c6a82d
--- /dev/null
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -0,0 +1,173 @@
1/*
2 * arch/arm/mach-orion5x/wrt350n-v2-setup.c
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/kernel.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/pci.h>
13#include <linux/irq.h>
14#include <linux/delay.h>
15#include <linux/mtd/physmap.h>
16#include <linux/mv643xx_eth.h>
17#include <asm/mach-types.h>
18#include <asm/gpio.h>
19#include <asm/mach/arch.h>
20#include <asm/mach/pci.h>
21#include <asm/arch/orion5x.h>
22#include "common.h"
23#include "mpp.h"
24
25static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
26 { 0, MPP_GPIO }, /* Power LED green (0=on) */
27 { 1, MPP_GPIO }, /* Security LED (0=on) */
28 { 2, MPP_GPIO }, /* Internal Button (0=on) */
29 { 3, MPP_GPIO }, /* Reset Button (0=on) */
30 { 4, MPP_GPIO }, /* PCI int */
31 { 5, MPP_GPIO }, /* Power LED orange (0=on) */
32 { 6, MPP_GPIO }, /* USB LED (0=on) */
33 { 7, MPP_GPIO }, /* Wireless LED (0=on) */
34 { 8, MPP_UNUSED }, /* ??? */
35 { 9, MPP_GIGE }, /* GE_RXERR */
36 { 10, MPP_UNUSED }, /* ??? */
37 { 11, MPP_UNUSED }, /* ??? */
38 { 12, MPP_GIGE }, /* GE_TXD[4] */
39 { 13, MPP_GIGE }, /* GE_TXD[5] */
40 { 14, MPP_GIGE }, /* GE_TXD[6] */
41 { 15, MPP_GIGE }, /* GE_TXD[7] */
42 { 16, MPP_GIGE }, /* GE_RXD[4] */
43 { 17, MPP_GIGE }, /* GE_RXD[5] */
44 { 18, MPP_GIGE }, /* GE_RXD[6] */
45 { 19, MPP_GIGE }, /* GE_RXD[7] */
46 { -1 },
47};
48
49/*
50 * 8M NOR flash Device bus boot chip select
51 */
52#define WRT350N_V2_NOR_BOOT_BASE 0xf4000000
53#define WRT350N_V2_NOR_BOOT_SIZE SZ_8M
54
55static struct mtd_partition wrt350n_v2_nor_flash_partitions[] = {
56 {
57 .name = "kernel",
58 .offset = 0x00000000,
59 .size = 0x00760000,
60 }, {
61 .name = "rootfs",
62 .offset = 0x001a0000,
63 .size = 0x005c0000,
64 }, {
65 .name = "lang",
66 .offset = 0x00760000,
67 .size = 0x00040000,
68 }, {
69 .name = "nvram",
70 .offset = 0x007a0000,
71 .size = 0x00020000,
72 }, {
73 .name = "u-boot",
74 .offset = 0x007c0000,
75 .size = 0x00040000,
76 },
77};
78
79static struct physmap_flash_data wrt350n_v2_nor_flash_data = {
80 .width = 1,
81 .parts = wrt350n_v2_nor_flash_partitions,
82 .nr_parts = ARRAY_SIZE(wrt350n_v2_nor_flash_partitions),
83};
84
85static struct resource wrt350n_v2_nor_flash_resource = {
86 .flags = IORESOURCE_MEM,
87 .start = WRT350N_V2_NOR_BOOT_BASE,
88 .end = WRT350N_V2_NOR_BOOT_BASE + WRT350N_V2_NOR_BOOT_SIZE - 1,
89};
90
91static struct platform_device wrt350n_v2_nor_flash = {
92 .name = "physmap-flash",
93 .id = 0,
94 .dev = {
95 .platform_data = &wrt350n_v2_nor_flash_data,
96 },
97 .num_resources = 1,
98 .resource = &wrt350n_v2_nor_flash_resource,
99};
100
101static struct mv643xx_eth_platform_data wrt350n_v2_eth_data = {
102 .phy_addr = -1,
103};
104
105static void __init wrt350n_v2_init(void)
106{
107 /*
108 * Setup basic Orion functions. Need to be called early.
109 */
110 orion5x_init();
111
112 orion5x_mpp_conf(wrt350n_v2_mpp_modes);
113
114 /*
115 * Configure peripherals.
116 */
117 orion5x_ehci0_init();
118 orion5x_eth_init(&wrt350n_v2_eth_data);
119 orion5x_uart0_init();
120
121 orion5x_setup_dev_boot_win(WRT350N_V2_NOR_BOOT_BASE,
122 WRT350N_V2_NOR_BOOT_SIZE);
123 platform_device_register(&wrt350n_v2_nor_flash);
124}
125
126static int __init wrt350n_v2_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
127{
128 int irq;
129
130 /*
131 * Check for devices with hard-wired IRQs.
132 */
133 irq = orion5x_pci_map_irq(dev, slot, pin);
134 if (irq != -1)
135 return irq;
136
137 /*
138 * Mini-PCI slot.
139 */
140 if (slot == 7)
141 return gpio_to_irq(4);
142
143 return -1;
144}
145
146static struct hw_pci wrt350n_v2_pci __initdata = {
147 .nr_controllers = 2,
148 .swizzle = pci_std_swizzle,
149 .setup = orion5x_pci_sys_setup,
150 .scan = orion5x_pci_sys_scan_bus,
151 .map_irq = wrt350n_v2_pci_map_irq,
152};
153
154static int __init wrt350n_v2_pci_init(void)
155{
156 if (machine_is_wrt350n_v2())
157 pci_common_init(&wrt350n_v2_pci);
158
159 return 0;
160}
161subsys_initcall(wrt350n_v2_pci_init);
162
163MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
164 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
165 .phys_io = ORION5X_REGS_PHYS_BASE,
166 .io_pg_offst = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
167 .boot_params = 0x00000100,
168 .init_machine = wrt350n_v2_init,
169 .map_io = orion5x_map_io,
170 .init_irq = orion5x_init_irq,
171 .timer = &orion5x_timer,
172 .fixup = tag_fixup_mem32,
173MACHINE_END
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 3e57428affee..8e813ed57519 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -74,6 +74,8 @@ static DEFINE_SPINLOCK(boot_lock);
74 74
75void __cpuinit platform_secondary_init(unsigned int cpu) 75void __cpuinit platform_secondary_init(unsigned int cpu)
76{ 76{
77 trace_hardirqs_off();
78
77 /* 79 /*
78 * the primary core may have used a "cross call" soft interrupt 80 * the primary core may have used a "cross call" soft interrupt
79 * to get this processor out of WFI in the BootMonitor - make 81 * to get this processor out of WFI in the BootMonitor - make
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index cd3dc0834b3b..99fdc736698c 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -37,6 +37,17 @@ config S3C2410_CLOCK
37 help 37 help
38 Clock code for the S3C2410, and similar processors 38 Clock code for the S3C2410, and similar processors
39 39
40config SIMTEC_NOR
41 bool
42 help
43 Internal node to specify machine has simtec NOR mapping
44
45config MACH_BAST_IDE
46 bool
47 select HAVE_PATA_PLATFORM
48 help
49 Internal node for machines with an BAST style IDE
50 interface
40 51
41menu "S3C2410 Machines" 52menu "S3C2410 Machines"
42 53
@@ -61,15 +72,18 @@ config PM_H1940
61 Internal node for H1940 and related PM 72 Internal node for H1940 and related PM
62 73
63config MACH_N30 74config MACH_N30
64 bool "Acer N30" 75 bool "Acer N30 family"
65 select CPU_S3C2410 76 select CPU_S3C2410
66 help 77 help
67 Say Y here if you are using the Acer N30 78 Say Y here if you want suppt for the Acer N30, Acer N35,
79 Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
68 80
69config ARCH_BAST 81config ARCH_BAST
70 bool "Simtec Electronics BAST (EB2410ITX)" 82 bool "Simtec Electronics BAST (EB2410ITX)"
71 select CPU_S3C2410 83 select CPU_S3C2410
72 select PM_SIMTEC if PM 84 select PM_SIMTEC if PM
85 select SIMTEC_NOR
86 select MACH_BAST_IDE
73 select ISA 87 select ISA
74 help 88 help
75 Say Y here if you are using the Simtec Electronics EB2410ITX 89 Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -107,6 +121,8 @@ config MACH_TCT_HAMMER
107config MACH_VR1000 121config MACH_VR1000
108 bool "Thorcom VR1000" 122 bool "Thorcom VR1000"
109 select PM_SIMTEC if PM 123 select PM_SIMTEC if PM
124 select SIMTEC_NOR
125 select MACH_BAST_IDE
110 select CPU_S3C2410 126 select CPU_S3C2410
111 help 127 help
112 Say Y here if you are using the Thorcom VR1000 board. 128 Say Y here if you are using the Thorcom VR1000 board.
@@ -118,4 +134,3 @@ config MACH_QT2410
118 Say Y here if you are using the Armzone QT2410 134 Say Y here if you are using the Armzone QT2410
119 135
120endmenu 136endmenu
121
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index cabc13ce09e4..00f31f8c4e78 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -30,3 +30,11 @@ obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
30obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o 30obj-$(CONFIG_MACH_TCT_HAMMER) += mach-tct_hammer.o
31obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o 31obj-$(CONFIG_MACH_VR1000) += mach-vr1000.o usb-simtec.o
32obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o 32obj-$(CONFIG_MACH_QT2410) += mach-qt2410.o
33
34# Common bits of machine support
35
36obj-$(CONFIG_SIMTEC_NOR) += nor-simtec.o
37
38# machine additions
39
40obj-$(CONFIG_MACH_BAST_IDE) += bast-ide.o
diff --git a/arch/arm/mach-s3c2410/bast-ide.c b/arch/arm/mach-s3c2410/bast-ide.c
new file mode 100644
index 000000000000..df95fe37cdc8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/bast-ide.c
@@ -0,0 +1,112 @@
1/* linux/arch/arm/mach-s3c2410/bast-ide.c
2 *
3 * Copyright 2007 Simtec Electronics
4 * http://www.simtec.co.uk/products/EB2410ITX/
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/interrupt.h>
17
18#include <linux/platform_device.h>
19#include <linux/ata_platform.h>
20
21#include <asm/mach-types.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/arch/map.h>
28#include <asm/arch/bast-map.h>
29#include <asm/arch/bast-irq.h>
30
31/* IDE ports */
32
33static struct pata_platform_info bast_ide_platdata = {
34 .ioport_shift = 5,
35};
36
37#define IDE_CS S3C2410_CS5
38
39static struct resource bast_ide0_resource[] = {
40 [0] = {
41 .start = IDE_CS + BAST_PA_IDEPRI,
42 .end = IDE_CS + BAST_PA_IDEPRI + (8 * 0x20) - 1,
43 .flags = IORESOURCE_MEM,
44 },
45 [1] = {
46 .start = IDE_CS + BAST_PA_IDEPRIAUX + (6 * 0x20) ,
47 .end = IDE_CS + BAST_PA_IDEPRIAUX + (7 * 0x20) - 1,
48 .flags = IORESOURCE_MEM,
49 },
50 [2] = {
51 .start = IRQ_IDE0,
52 .end = IRQ_IDE0,
53 .flags = IORESOURCE_IRQ,
54 },
55};
56
57static struct platform_device bast_device_ide0 = {
58 .name = "pata_platform",
59 .id = 0,
60 .num_resources = ARRAY_SIZE(bast_ide0_resource),
61 .resource = bast_ide0_resource,
62 .dev = {
63 .platform_data = &bast_ide_platdata,
64 .coherent_dma_mask = ~0,
65 }
66
67};
68
69static struct resource bast_ide1_resource[] = {
70 [0] = {
71 .start = IDE_CS + BAST_PA_IDESEC,
72 .end = IDE_CS + BAST_PA_IDESEC + (8 * 0x20) - 1,
73 .flags = IORESOURCE_MEM,
74 },
75 [1] = {
76 .start = IDE_CS + BAST_PA_IDESECAUX + (6 * 0x20),
77 .end = IDE_CS + BAST_PA_IDESECAUX + (7 * 0x20) - 1,
78 .flags = IORESOURCE_MEM,
79 },
80 [2] = {
81 .start = IRQ_IDE1,
82 .end = IRQ_IDE1,
83 .flags = IORESOURCE_IRQ,
84 },
85};
86
87static struct platform_device bast_device_ide1 = {
88 .name = "pata_platform",
89 .id = 1,
90 .num_resources = ARRAY_SIZE(bast_ide1_resource),
91 .resource = bast_ide1_resource,
92 .dev = {
93 .platform_data = &bast_ide_platdata,
94 .coherent_dma_mask = ~0,
95 }
96};
97
98static struct platform_device *bast_ide_devices[] __initdata = {
99 &bast_device_ide0,
100 &bast_device_ide1,
101};
102
103static __init int bast_ide_init(void)
104{
105 if (machine_is_bast() || machine_is_vr1000())
106 return platform_add_devices(bast_ide_devices,
107 ARRAY_SIZE(bast_ide_devices));
108
109 return 0;
110}
111
112fs_initcall(bast_ide_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 27f63d5d3a7b..965f27129707 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2410/mach-bast.c 1/* linux/arch/arm/mach-s3c2410/mach-bast.c
2 * 2 *
3 * Copyright (c) 2003-2005 Simtec Electronics 3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * http://www.simtec.co.uk/products/EB2410ITX/ 6 * http://www.simtec.co.uk/products/EB2410ITX/
@@ -20,6 +20,8 @@
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/dm9000.h> 22#include <linux/dm9000.h>
23#include <linux/ata_platform.h>
24#include <linux/i2c.h>
23 25
24#include <net/ax88796.h> 26#include <net/ax88796.h>
25 27
@@ -56,7 +58,9 @@
56#include <asm/plat-s3c24xx/clock.h> 58#include <asm/plat-s3c24xx/clock.h>
57#include <asm/plat-s3c24xx/devs.h> 59#include <asm/plat-s3c24xx/devs.h>
58#include <asm/plat-s3c24xx/cpu.h> 60#include <asm/plat-s3c24xx/cpu.h>
61
59#include "usb-simtec.h" 62#include "usb-simtec.h"
63#include "nor-simtec.h"
60 64
61#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics" 65#define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
62 66
@@ -134,37 +138,21 @@ static struct map_desc bast_iodesc[] __initdata = {
134 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 138 { VA_C2(BAST_VA_ISAIO), PA_CS2(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
135 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 139 { VA_C2(BAST_VA_ISAMEM), PA_CS2(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
136 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 140 { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
137 { VA_C2(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
138 { VA_C2(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
139 { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
140 { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
141 141
142 /* slow, word */ 142 /* slow, word */
143 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 143 { VA_C3(BAST_VA_ISAIO), PA_CS3(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
144 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 144 { VA_C3(BAST_VA_ISAMEM), PA_CS3(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
145 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 145 { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
146 { VA_C3(BAST_VA_IDEPRI), PA_CS3(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
147 { VA_C3(BAST_VA_IDESEC), PA_CS3(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
148 { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
149 { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
150 146
151 /* fast, byte */ 147 /* fast, byte */
152 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 148 { VA_C4(BAST_VA_ISAIO), PA_CS4(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
153 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 149 { VA_C4(BAST_VA_ISAMEM), PA_CS4(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
154 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 150 { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
155 { VA_C4(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
156 { VA_C4(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
157 { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
158 { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
159 151
160 /* fast, word */ 152 /* fast, word */
161 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE }, 153 { VA_C5(BAST_VA_ISAIO), PA_CS5(BAST_PA_ISAIO), SZ_16M, MT_DEVICE },
162 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE }, 154 { VA_C5(BAST_VA_ISAMEM), PA_CS5(BAST_PA_ISAMEM), SZ_16M, MT_DEVICE },
163 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE }, 155 { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO), SZ_1M, MT_DEVICE },
164 { VA_C5(BAST_VA_IDEPRI), PA_CS5(BAST_PA_IDEPRI), SZ_1M, MT_DEVICE },
165 { VA_C5(BAST_VA_IDESEC), PA_CS5(BAST_PA_IDESEC), SZ_1M, MT_DEVICE },
166 { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
167 { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
168}; 156};
169 157
170#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 158#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -218,23 +206,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
218 } 206 }
219}; 207};
220 208
221/* NOR Flash on BAST board */
222
223static struct resource bast_nor_resource[] = {
224 [0] = {
225 .start = S3C2410_CS1 + 0x4000000,
226 .end = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
227 .flags = IORESOURCE_MEM,
228 }
229};
230
231static struct platform_device bast_device_nor = {
232 .name = "bast-nor",
233 .id = -1,
234 .num_resources = ARRAY_SIZE(bast_nor_resource),
235 .resource = bast_nor_resource,
236};
237
238/* NAND Flash on BAST board */ 209/* NAND Flash on BAST board */
239 210
240#ifdef CONFIG_PM 211#ifdef CONFIG_PM
@@ -374,7 +345,7 @@ static struct resource bast_dm9k_resource[] = {
374 [2] = { 345 [2] = {
375 .start = IRQ_DM9000, 346 .start = IRQ_DM9000,
376 .end = IRQ_DM9000, 347 .end = IRQ_DM9000,
377 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, 348 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
378 } 349 }
379 350
380}; 351};
@@ -564,6 +535,18 @@ static struct s3c2410fb_mach_info __initdata bast_fb_info = {
564 .default_display = 1, 535 .default_display = 1,
565}; 536};
566 537
538/* I2C devices fitted. */
539
540static struct i2c_board_info bast_i2c_devs[] __initdata = {
541 {
542 I2C_BOARD_INFO("tlv320aic23", 0x1a),
543 }, {
544 I2C_BOARD_INFO("simtec-pmu", 0x6b),
545 }, {
546 I2C_BOARD_INFO("ch7013", 0x75),
547 },
548};
549
567/* Standard BAST devices */ 550/* Standard BAST devices */
568 551
569static struct platform_device *bast_devices[] __initdata = { 552static struct platform_device *bast_devices[] __initdata = {
@@ -573,7 +556,6 @@ static struct platform_device *bast_devices[] __initdata = {
573 &s3c_device_i2c, 556 &s3c_device_i2c,
574 &s3c_device_rtc, 557 &s3c_device_rtc,
575 &s3c_device_nand, 558 &s3c_device_nand,
576 &bast_device_nor,
577 &bast_device_dm9k, 559 &bast_device_dm9k,
578 &bast_device_asix, 560 &bast_device_asix,
579 &bast_device_axpp, 561 &bast_device_axpp,
@@ -622,6 +604,11 @@ static void __init bast_init(void)
622 604
623 s3c24xx_fb_set_platdata(&bast_fb_info); 605 s3c24xx_fb_set_platdata(&bast_fb_info);
624 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices)); 606 platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
607
608 i2c_register_board_info(0, bast_i2c_devs,
609 ARRAY_SIZE(bast_i2c_devs));
610
611 nor_simtec_init();
625} 612}
626 613
627MACHINE_START(BAST, "Simtec-BAST") 614MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 621f548da610..43c2e915c5bf 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -1,9 +1,10 @@
1/* linux/arch/arm/mach-s3c2410/mach-n30.c 1/* Machine specific code for the Acer n30, Acer N35, Navman PiN 570,
2 * Yakumo AlphaX and Airis NC05 PDAs.
2 * 3 *
3 * Copyright (c) 2003-2005 Simtec Electronics 4 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * Copyright (c) 2005 Christer Weinigel <christer@weinigel.se> 7 * Copyright (c) 2005-2008 Christer Weinigel <christer@weinigel.se>
7 * 8 *
8 * There is a wiki with more information about the n30 port at 9 * There is a wiki with more information about the n30 port at
9 * http://handhelds.org/moin/moin.cgi/AcerN30Documentation . 10 * http://handhelds.org/moin/moin.cgi/AcerN30Documentation .
@@ -11,36 +12,42 @@
11 * This program is free software; you can redistribute it and/or modify 12 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
14*/ 15 */
15 16
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/types.h> 18#include <linux/types.h>
18#include <linux/interrupt.h> 19
19#include <linux/list.h>
20#include <linux/timer.h>
21#include <linux/init.h>
22#include <linux/delay.h> 20#include <linux/delay.h>
23#include <linux/serial_core.h> 21#include <linux/gpio_keys.h>
22#include <linux/init.h>
23#include <linux/input.h>
24#include <linux/interrupt.h>
24#include <linux/platform_device.h> 25#include <linux/platform_device.h>
25#include <linux/kthread.h> 26#include <linux/serial_core.h>
26 27#include <linux/timer.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/map.h>
29#include <asm/mach/irq.h>
30 28
31#include <asm/hardware.h> 29#include <asm/hardware.h>
32#include <asm/io.h> 30#include <asm/io.h>
33#include <asm/irq.h> 31#include <asm/irq.h>
34#include <asm/mach-types.h> 32#include <asm/mach-types.h>
35 33
36#include <asm/plat-s3c/regs-serial.h> 34#include <asm/arch/fb.h>
35#include <asm/arch/leds-gpio.h>
37#include <asm/arch/regs-gpio.h> 36#include <asm/arch/regs-gpio.h>
37#include <asm/arch/regs-lcd.h>
38
39#include <asm/mach/arch.h>
40#include <asm/mach/irq.h>
41#include <asm/mach/map.h>
42
38#include <asm/plat-s3c/iic.h> 43#include <asm/plat-s3c/iic.h>
44#include <asm/plat-s3c/regs-serial.h>
39 45
40#include <asm/plat-s3c24xx/s3c2410.h>
41#include <asm/plat-s3c24xx/clock.h> 46#include <asm/plat-s3c24xx/clock.h>
42#include <asm/plat-s3c24xx/devs.h>
43#include <asm/plat-s3c24xx/cpu.h> 47#include <asm/plat-s3c24xx/cpu.h>
48#include <asm/plat-s3c24xx/devs.h>
49#include <asm/plat-s3c24xx/s3c2410.h>
50#include <asm/plat-s3c24xx/udc.h>
44 51
45static struct map_desc n30_iodesc[] __initdata = { 52static struct map_desc n30_iodesc[] __initdata = {
46 /* nothing here yet */ 53 /* nothing here yet */
@@ -64,7 +71,8 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
64 .ulcon = 0x43, 71 .ulcon = 0x43,
65 .ufcon = 0x51, 72 .ufcon = 0x51,
66 }, 73 },
67 /* The BlueTooth controller is connected to port 2 */ 74 /* On the N30 the bluetooth controller is connected here.
75 * On the N35 and variants the GPS receiver is connected here. */
68 [2] = { 76 [2] = {
69 .hwport = 2, 77 .hwport = 2,
70 .flags = 0, 78 .flags = 0,
@@ -74,13 +82,260 @@ static struct s3c2410_uartcfg n30_uartcfgs[] = {
74 }, 82 },
75}; 83};
76 84
85static void n30_udc_pullup(enum s3c2410_udc_cmd_e cmd)
86{
87 switch (cmd) {
88 case S3C2410_UDC_P_ENABLE :
89 s3c2410_gpio_setpin(S3C2410_GPB3, 1);
90 break;
91 case S3C2410_UDC_P_DISABLE :
92 s3c2410_gpio_setpin(S3C2410_GPB3, 0);
93 break;
94 case S3C2410_UDC_P_RESET :
95 break;
96 default:
97 break;
98 }
99}
100
101static struct s3c2410_udc_mach_info n30_udc_cfg __initdata = {
102 .udc_command = n30_udc_pullup,
103 .vbus_pin = S3C2410_GPG1,
104 .vbus_pin_inverted = 0,
105};
106
107static struct gpio_keys_button n30_buttons[] = {
108 {
109 .gpio = S3C2410_GPF0,
110 .code = KEY_POWER,
111 .desc = "Power",
112 .active_low = 0,
113 },
114 {
115 .gpio = S3C2410_GPG9,
116 .code = KEY_UP,
117 .desc = "Thumbwheel Up",
118 .active_low = 0,
119 },
120 {
121 .gpio = S3C2410_GPG8,
122 .code = KEY_DOWN,
123 .desc = "Thumbwheel Down",
124 .active_low = 0,
125 },
126 {
127 .gpio = S3C2410_GPG7,
128 .code = KEY_ENTER,
129 .desc = "Thumbwheel Press",
130 .active_low = 0,
131 },
132 {
133 .gpio = S3C2410_GPF7,
134 .code = KEY_HOMEPAGE,
135 .desc = "Home",
136 .active_low = 0,
137 },
138 {
139 .gpio = S3C2410_GPF6,
140 .code = KEY_CALENDAR,
141 .desc = "Calendar",
142 .active_low = 0,
143 },
144 {
145 .gpio = S3C2410_GPF5,
146 .code = KEY_ADDRESSBOOK,
147 .desc = "Contacts",
148 .active_low = 0,
149 },
150 {
151 .gpio = S3C2410_GPF4,
152 .code = KEY_MAIL,
153 .desc = "Mail",
154 .active_low = 0,
155 },
156};
157
158static struct gpio_keys_platform_data n30_button_data = {
159 .buttons = n30_buttons,
160 .nbuttons = ARRAY_SIZE(n30_buttons),
161};
162
163static struct platform_device n30_button_device = {
164 .name = "gpio-keys",
165 .id = -1,
166 .dev = {
167 .platform_data = &n30_button_data,
168 }
169};
170
171static struct gpio_keys_button n35_buttons[] = {
172 {
173 .gpio = S3C2410_GPF0,
174 .code = KEY_POWER,
175 .desc = "Power",
176 .active_low = 0,
177 },
178 {
179 .gpio = S3C2410_GPG9,
180 .code = KEY_UP,
181 .desc = "Joystick Up",
182 .active_low = 0,
183 },
184 {
185 .gpio = S3C2410_GPG8,
186 .code = KEY_DOWN,
187 .desc = "Joystick Down",
188 .active_low = 0,
189 },
190 {
191 .gpio = S3C2410_GPG6,
192 .code = KEY_DOWN,
193 .desc = "Joystick Left",
194 .active_low = 0,
195 },
196 {
197 .gpio = S3C2410_GPG5,
198 .code = KEY_DOWN,
199 .desc = "Joystick Right",
200 .active_low = 0,
201 },
202 {
203 .gpio = S3C2410_GPG7,
204 .code = KEY_ENTER,
205 .desc = "Joystick Press",
206 .active_low = 0,
207 },
208 {
209 .gpio = S3C2410_GPF7,
210 .code = KEY_HOMEPAGE,
211 .desc = "Home",
212 .active_low = 0,
213 },
214 {
215 .gpio = S3C2410_GPF6,
216 .code = KEY_CALENDAR,
217 .desc = "Calendar",
218 .active_low = 0,
219 },
220 {
221 .gpio = S3C2410_GPF5,
222 .code = KEY_ADDRESSBOOK,
223 .desc = "Contacts",
224 .active_low = 0,
225 },
226 {
227 .gpio = S3C2410_GPF4,
228 .code = KEY_MAIL,
229 .desc = "Mail",
230 .active_low = 0,
231 },
232 {
233 .gpio = S3C2410_GPF3,
234 .code = SW_RADIO,
235 .desc = "GPS Antenna",
236 .active_low = 0,
237 },
238 {
239 .gpio = S3C2410_GPG2,
240 .code = SW_HEADPHONE_INSERT,
241 .desc = "Headphone",
242 .active_low = 0,
243 },
244};
245
246static struct gpio_keys_platform_data n35_button_data = {
247 .buttons = n35_buttons,
248 .nbuttons = ARRAY_SIZE(n35_buttons),
249};
250
251static struct platform_device n35_button_device = {
252 .name = "gpio-keys",
253 .id = -1,
254 .num_resources = 0,
255 .dev = {
256 .platform_data = &n35_button_data,
257 }
258};
259
260/* This is the bluetooth LED on the device. */
261static struct s3c24xx_led_platdata n30_blue_led_pdata = {
262 .name = "blue_led",
263 .gpio = S3C2410_GPG6,
264 .def_trigger = "",
265};
266
267/* This LED is driven by the battery microcontroller, and is blinking
268 * red, blinking green or solid green when the battery is low,
269 * charging or full respectively. By driving GPD9 low, it's possible
270 * to force the LED to blink red, so call that warning LED. */
271static struct s3c24xx_led_platdata n30_warning_led_pdata = {
272 .name = "warning_led",
273 .flags = S3C24XX_LEDF_ACTLOW,
274 .gpio = S3C2410_GPD9,
275 .def_trigger = "",
276};
277
278static struct platform_device n30_blue_led = {
279 .name = "s3c24xx_led",
280 .id = 1,
281 .dev = {
282 .platform_data = &n30_blue_led_pdata,
283 },
284};
285
286static struct platform_device n30_warning_led = {
287 .name = "s3c24xx_led",
288 .id = 2,
289 .dev = {
290 .platform_data = &n30_warning_led_pdata,
291 },
292};
293
294static struct s3c2410fb_display n30_display __initdata = {
295 .type = S3C2410_LCDCON1_TFT,
296 .width = 240,
297 .height = 320,
298 .pixclock = 170000,
299
300 .xres = 240,
301 .yres = 320,
302 .bpp = 16,
303 .left_margin = 3,
304 .right_margin = 40,
305 .hsync_len = 40,
306 .upper_margin = 2,
307 .lower_margin = 3,
308 .vsync_len = 2,
309
310 .lcdcon5 = S3C2410_LCDCON5_INVVLINE | S3C2410_LCDCON5_INVVFRAME,
311};
312
313static struct s3c2410fb_mach_info n30_fb_info __initdata = {
314 .displays = &n30_display,
315 .num_displays = 1,
316 .default_display = 0,
317 .lpcsel = 0x06,
318};
319
77static struct platform_device *n30_devices[] __initdata = { 320static struct platform_device *n30_devices[] __initdata = {
321 &s3c_device_lcd,
322 &s3c_device_wdt,
323 &s3c_device_i2c,
324 &s3c_device_iis,
78 &s3c_device_usb, 325 &s3c_device_usb,
326 &s3c_device_usbgadget,
327 &n30_button_device,
328 &n30_blue_led,
329 &n30_warning_led,
330};
331
332static struct platform_device *n35_devices[] __initdata = {
79 &s3c_device_lcd, 333 &s3c_device_lcd,
80 &s3c_device_wdt, 334 &s3c_device_wdt,
81 &s3c_device_i2c, 335 &s3c_device_i2c,
82 &s3c_device_iis, 336 &s3c_device_iis,
83 &s3c_device_usbgadget, 337 &s3c_device_usbgadget,
338 &n35_button_device,
84}; 339};
85 340
86static struct s3c2410_platform_i2c n30_i2ccfg = { 341static struct s3c2410_platform_i2c n30_i2ccfg = {
@@ -90,9 +345,148 @@ static struct s3c2410_platform_i2c n30_i2ccfg = {
90 .max_freq = 10*1000, 345 .max_freq = 10*1000,
91}; 346};
92 347
348/* Lots of hardcoded stuff, but it sets up the hardware in a useful
349 * state so that we can boot Linux directly from flash. */
350static void __init n30_hwinit(void)
351{
352 /* GPA0-11 special functions -- unknown what they do
353 * GPA12 N30 special function -- unknown what it does
354 * N35/PiN output -- unknown what it does
355 *
356 * A12 is nGCS1 on the N30 and an output on the N35/PiN. I
357 * don't think it does anything useful on the N30, so I ought
358 * to make it an output there too since it always driven to 0
359 * as far as I can tell. */
360 if (machine_is_n30())
361 __raw_writel(0x007fffff, S3C2410_GPACON);
362 if (machine_is_n35())
363 __raw_writel(0x007fefff, S3C2410_GPACON);
364 __raw_writel(0x00000000, S3C2410_GPADAT);
365
366 /* GPB0 TOUT0 backlight level
367 * GPB1 output 1=backlight on
368 * GPB2 output IrDA enable 0=transceiver enabled, 1=disabled
369 * GPB3 output USB D+ pull up 0=disabled, 1=enabled
370 * GPB4 N30 output -- unknown function
371 * N30/PiN GPS control 0=GPS enabled, 1=GPS disabled
372 * GPB5 output -- unknown function
373 * GPB6 input -- unknown function
374 * GPB7 output -- unknown function
375 * GPB8 output -- probably LCD driver enable
376 * GPB9 output -- probably LCD VSYNC driver enable
377 * GPB10 output -- probably LCD HSYNC driver enable
378 */
379 __raw_writel(0x00154556, S3C2410_GPBCON);
380 __raw_writel(0x00000750, S3C2410_GPBDAT);
381 __raw_writel(0x00000073, S3C2410_GPBUP);
382
383 /* GPC0 input RS232 DCD/DSR/RI
384 * GPC1 LCD
385 * GPC2 output RS232 DTR?
386 * GPC3 input RS232 DCD/DSR/RI
387 * GPC4 LCD
388 * GPC5 output 0=NAND write enabled, 1=NAND write protect
389 * GPC6 input -- unknown function
390 * GPC7 input charger status 0=charger connected
391 * this input can be triggered by power on the USB device
392 * port too, but will go back to disconnected soon after.
393 * GPC8 N30/N35 output -- unknown function, always driven to 1
394 * PiN input -- unknown function, always read as 1
395 * Make it an input with a pull up for all models.
396 * GPC9-15 LCD
397 */
398 __raw_writel(0xaaa80618, S3C2410_GPCCON);
399 __raw_writel(0x0000014c, S3C2410_GPCDAT);
400 __raw_writel(0x0000fef2, S3C2410_GPCUP);
401
402 /* GPD0 input -- unknown function
403 * GPD1-D7 LCD
404 * GPD8 N30 output -- unknown function
405 * N35/PiN output 1=GPS LED on
406 * GPD9 output 0=power led blinks red, 1=normal power led function
407 * GPD10 output -- unknown function
408 * GPD11-15 LCD drivers
409 */
410 __raw_writel(0xaa95aaa4, S3C2410_GPDCON);
411 __raw_writel(0x00000601, S3C2410_GPDDAT);
412 __raw_writel(0x0000fbfe, S3C2410_GPDUP);
413
414 /* GPE0-4 I2S audio bus
415 * GPE5-10 SD/MMC bus
416 * E11-13 outputs -- unknown function, probably power management
417 * E14-15 I2C bus connected to the battery controller
418 */
419 __raw_writel(0xa56aaaaa, S3C2410_GPECON);
420 __raw_writel(0x0000efc5, S3C2410_GPEDAT);
421 __raw_writel(0x0000f81f, S3C2410_GPEUP);
422
423 /* GPF0 input 0=power button pressed
424 * GPF1 input SD/MMC switch 0=card present
425 * GPF2 N30 1=reset button pressed (inverted compared to the rest)
426 * N35/PiN 0=reset button pressed
427 * GPF3 N30/PiN input -- unknown function
428 * N35 input GPS antenna position, 0=antenna closed, 1=open
429 * GPF4 input 0=button 4 pressed
430 * GPF5 input 0=button 3 pressed
431 * GPF6 input 0=button 2 pressed
432 * GPF7 input 0=button 1 pressed
433 */
434 __raw_writel(0x0000aaaa, S3C2410_GPFCON);
435 __raw_writel(0x00000000, S3C2410_GPFDAT);
436 __raw_writel(0x000000ff, S3C2410_GPFUP);
437
438 /* GPG0 input RS232 DCD/DSR/RI
439 * GPG1 input 1=USB gadget port has power from a host
440 * GPG2 N30 input -- unknown function
441 * N35/PiN input 0=headphones plugged in, 1=not plugged in
442 * GPG3 N30 output -- unknown function
443 * N35/PiN input with unknown function
444 * GPG4 N30 output 0=MMC enabled, 1=MMC disabled
445 * GPG5 N30 output 0=BlueTooth chip disabled, 1=enabled
446 * N35/PiN input joystick right
447 * GPG6 N30 output 0=blue led on, 1=off
448 * N35/PiN input joystick left
449 * GPG7 input 0=thumbwheel pressed
450 * GPG8 input 0=thumbwheel down
451 * GPG9 input 0=thumbwheel up
452 * GPG10 input SD/MMC write protect switch
453 * GPG11 N30 input -- unknown function
454 * N35 output 0=GPS antenna powered, 1=not powered
455 * PiN output -- unknown function
456 * GPG12-15 touch screen functions
457 *
458 * The pullups differ between the models, so enable all
459 * pullups that are enabled on any of the models.
460 */
461 if (machine_is_n30())
462 __raw_writel(0xff0a956a, S3C2410_GPGCON);
463 if (machine_is_n35())
464 __raw_writel(0xff4aa92a, S3C2410_GPGCON);
465 __raw_writel(0x0000e800, S3C2410_GPGDAT);
466 __raw_writel(0x0000f86f, S3C2410_GPGUP);
467
468 /* GPH0/1/2/3 RS232 serial port
469 * GPH4/5 IrDA serial port
470 * GPH6/7 N30 BlueTooth serial port
471 * N35/PiN GPS receiver
472 * GPH8 input -- unknown function
473 * GPH9 CLKOUT0 HCLK -- unknown use
474 * GPH10 CLKOUT1 FCLK -- unknown use
475 *
476 * The pull ups for H6/H7 are enabled on N30 but not on the
477 * N35/PiN. I suppose is useful for a budget model of the N30
478 * with no bluetooh. It doesn't hurt to have the pull ups
479 * enabled on the N35, so leave them enabled for all models.
480 */
481 __raw_writel(0x0028aaaa, S3C2410_GPHCON);
482 __raw_writel(0x000005ef, S3C2410_GPHDAT);
483 __raw_writel(0x0000063f, S3C2410_GPHUP);
484}
485
93static void __init n30_map_io(void) 486static void __init n30_map_io(void)
94{ 487{
95 s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc)); 488 s3c24xx_init_io(n30_iodesc, ARRAY_SIZE(n30_iodesc));
489 n30_hwinit();
96 s3c24xx_init_clocks(0); 490 s3c24xx_init_clocks(0);
97 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); 491 s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
98} 492}
@@ -106,7 +500,9 @@ static void __init n30_init_irq(void)
106 500
107static void __init n30_init(void) 501static void __init n30_init(void)
108{ 502{
503 s3c24xx_fb_set_platdata(&n30_fb_info);
109 s3c_device_i2c.dev.platform_data = &n30_i2ccfg; 504 s3c_device_i2c.dev.platform_data = &n30_i2ccfg;
505 s3c24xx_udc_set_platdata(&n30_udc_cfg);
110 506
111 /* Turn off suspend on both USB ports, and switch the 507 /* Turn off suspend on both USB ports, and switch the
112 * selectable USB port to USB device mode. */ 508 * selectable USB port to USB device mode. */
@@ -115,7 +511,32 @@ static void __init n30_init(void)
115 S3C2410_MISCCR_USBSUSPND0 | 511 S3C2410_MISCCR_USBSUSPND0 |
116 S3C2410_MISCCR_USBSUSPND1, 0x0); 512 S3C2410_MISCCR_USBSUSPND1, 0x0);
117 513
118 platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices)); 514 if (machine_is_n30()) {
515 /* Turn off suspend on both USB ports, and switch the
516 * selectable USB port to USB device mode. */
517 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
518 S3C2410_MISCCR_USBSUSPND0 |
519 S3C2410_MISCCR_USBSUSPND1, 0x0);
520
521 platform_add_devices(n30_devices, ARRAY_SIZE(n30_devices));
522 }
523
524 if (machine_is_n35()) {
525 /* Turn off suspend and switch the selectable USB port
526 * to USB device mode. Turn on suspend for the host
527 * port since it is not connected on the N35.
528 *
529 * Actually, the host port is available at some pads
530 * on the back of the device, so it would actually be
531 * possible to add a USB device inside the N35 if you
532 * are willing to do some hardware modifications. */
533 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
534 S3C2410_MISCCR_USBSUSPND0 |
535 S3C2410_MISCCR_USBSUSPND1,
536 S3C2410_MISCCR_USBSUSPND1);
537
538 platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
539 }
119} 540}
120 541
121MACHINE_START(N30, "Acer-N30") 542MACHINE_START(N30, "Acer-N30")
@@ -131,9 +552,14 @@ MACHINE_START(N30, "Acer-N30")
131 .map_io = n30_map_io, 552 .map_io = n30_map_io,
132MACHINE_END 553MACHINE_END
133 554
134/* 555MACHINE_START(N35, "Acer-N35")
135 Local variables: 556 /* Maintainer: Christer Weinigel <christer@weinigel.se>
136 compile-command: "make ARCH=arm CROSS_COMPILE=/usr/local/arm/3.3.2/bin/arm-linux- -k -C ../../.." 557 */
137 c-basic-offset: 8 558 .phys_io = S3C2410_PA_UART,
138 End: 559 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
139*/ 560 .boot_params = S3C2410_SDRAM_PA + 0x100,
561 .timer = &s3c24xx_timer,
562 .init_machine = n30_init,
563 .init_irq = n30_init_irq,
564 .map_io = n30_map_io,
565MACHINE_END
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 4c4b5c4207c4..9a0965ac5e11 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2410/mach-vr1000.c 1/* linux/arch/arm/mach-s3c2410/mach-vr1000.c
2 * 2 *
3 * Copyright (c) 2003-2005 Simtec Electronics 3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by 6 * Machine support for Thorcom VR1000 board. Designed for Thorcom by
@@ -19,6 +19,7 @@
19#include <linux/timer.h> 19#include <linux/timer.h>
20#include <linux/init.h> 20#include <linux/init.h>
21#include <linux/dm9000.h> 21#include <linux/dm9000.h>
22#include <linux/i2c.h>
22 23
23#include <linux/serial.h> 24#include <linux/serial.h>
24#include <linux/tty.h> 25#include <linux/tty.h>
@@ -46,7 +47,9 @@
46#include <asm/plat-s3c24xx/clock.h> 47#include <asm/plat-s3c24xx/clock.h>
47#include <asm/plat-s3c24xx/devs.h> 48#include <asm/plat-s3c24xx/devs.h>
48#include <asm/plat-s3c24xx/cpu.h> 49#include <asm/plat-s3c24xx/cpu.h>
50
49#include "usb-simtec.h" 51#include "usb-simtec.h"
52#include "nor-simtec.h"
50 53
51/* macros for virtual address mods for the io space entries */ 54/* macros for virtual address mods for the io space entries */
52#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) 55#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -97,34 +100,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {
97 .length = SZ_1M, 100 .length = SZ_1M,
98 .type = MT_DEVICE, 101 .type = MT_DEVICE,
99 }, 102 },
100
101 /* peripheral space... one for each of fast/slow/byte/16bit */
102 /* note, ide is only decoded in word space, even though some registers
103 * are only 8bit */
104
105 /* slow, byte */
106 { VA_C2(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
107 { VA_C2(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
108 { VA_C2(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
109 { VA_C2(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
110
111 /* slow, word */
112 { VA_C3(VR1000_VA_IDEPRI), PA_CS3(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
113 { VA_C3(VR1000_VA_IDESEC), PA_CS3(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
114 { VA_C3(VR1000_VA_IDEPRIAUX), PA_CS3(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
115 { VA_C3(VR1000_VA_IDESECAUX), PA_CS3(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
116
117 /* fast, byte */
118 { VA_C4(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
119 { VA_C4(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
120 { VA_C4(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
121 { VA_C4(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
122
123 /* fast, word */
124 { VA_C5(VR1000_VA_IDEPRI), PA_CS5(VR1000_PA_IDEPRI), SZ_1M, MT_DEVICE },
125 { VA_C5(VR1000_VA_IDESEC), PA_CS5(VR1000_PA_IDESEC), SZ_1M, MT_DEVICE },
126 { VA_C5(VR1000_VA_IDEPRIAUX), PA_CS5(VR1000_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
127 { VA_C5(VR1000_VA_IDESECAUX), PA_CS5(VR1000_PA_IDESECAUX), SZ_1M, MT_DEVICE },
128}; 103};
129 104
130#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK 105#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
@@ -230,23 +205,6 @@ static struct platform_device serial_device = {
230 }, 205 },
231}; 206};
232 207
233/* MTD NOR Flash */
234
235static struct resource vr1000_nor_resource[] = {
236 [0] = {
237 .start = S3C2410_CS1 + 0x4000000,
238 .end = S3C2410_CS1 + 0x4000000 + SZ_16M - 1,
239 .flags = IORESOURCE_MEM,
240 }
241};
242
243static struct platform_device vr1000_nor = {
244 .name = "bast-nor",
245 .id = -1,
246 .num_resources = ARRAY_SIZE(vr1000_nor_resource),
247 .resource = vr1000_nor_resource,
248};
249
250/* DM9000 ethernet devices */ 208/* DM9000 ethernet devices */
251 209
252static struct resource vr1000_dm9k0_resource[] = { 210static struct resource vr1000_dm9k0_resource[] = {
@@ -263,7 +221,7 @@ static struct resource vr1000_dm9k0_resource[] = {
263 [2] = { 221 [2] = {
264 .start = IRQ_VR1000_DM9000A, 222 .start = IRQ_VR1000_DM9000A,
265 .end = IRQ_VR1000_DM9000A, 223 .end = IRQ_VR1000_DM9000A,
266 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, 224 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
267 } 225 }
268 226
269}; 227};
@@ -282,7 +240,7 @@ static struct resource vr1000_dm9k1_resource[] = {
282 [2] = { 240 [2] = {
283 .start = IRQ_VR1000_DM9000N, 241 .start = IRQ_VR1000_DM9000N,
284 .end = IRQ_VR1000_DM9000N, 242 .end = IRQ_VR1000_DM9000N,
285 .flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH, 243 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
286 } 244 }
287}; 245};
288 246
@@ -358,6 +316,18 @@ static struct platform_device vr1000_led3 = {
358 }, 316 },
359}; 317};
360 318
319/* I2C devices. */
320
321static struct i2c_board_info vr1000_i2c_devs[] __initdata = {
322 {
323 I2C_BOARD_INFO("tlv320aic23", 0x1a),
324 }, {
325 I2C_BOARD_INFO("tmp101", 0x48),
326 }, {
327 I2C_BOARD_INFO("m41st87", 0x68),
328 },
329};
330
361/* devices for this board */ 331/* devices for this board */
362 332
363static struct platform_device *vr1000_devices[] __initdata = { 333static struct platform_device *vr1000_devices[] __initdata = {
@@ -367,7 +337,6 @@ static struct platform_device *vr1000_devices[] __initdata = {
367 &s3c_device_i2c, 337 &s3c_device_i2c,
368 &s3c_device_adc, 338 &s3c_device_adc,
369 &serial_device, 339 &serial_device,
370 &vr1000_nor,
371 &vr1000_dm9k0, 340 &vr1000_dm9k0,
372 &vr1000_dm9k1, 341 &vr1000_dm9k1,
373 &vr1000_led1, 342 &vr1000_led1,
@@ -416,6 +385,11 @@ static void __init vr1000_map_io(void)
416static void __init vr1000_init(void) 385static void __init vr1000_init(void)
417{ 386{
418 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices)); 387 platform_add_devices(vr1000_devices, ARRAY_SIZE(vr1000_devices));
388
389 i2c_register_board_info(0, vr1000_i2c_devs,
390 ARRAY_SIZE(vr1000_i2c_devs));
391
392 nor_simtec_init();
419} 393}
420 394
421MACHINE_START(VR1000, "Thorcom-VR1000") 395MACHINE_START(VR1000, "Thorcom-VR1000")
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
new file mode 100644
index 000000000000..f44e21b9c3ba
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -0,0 +1,86 @@
1/* linux/arch/arm/mach-s3c2410/nor-simtec.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Simtec NOR mapping
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include <linux/module.h>
15#include <linux/types.h>
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/platform_device.h>
19
20#include <linux/mtd/mtd.h>
21#include <linux/mtd/map.h>
22#include <linux/mtd/physmap.h>
23#include <linux/mtd/partitions.h>
24
25#include <asm/mach/arch.h>
26#include <asm/mach/map.h>
27#include <asm/mach/irq.h>
28
29#include <asm/arch/map.h>
30#include <asm/arch/bast-map.h>
31#include <asm/arch/bast-cpld.h>
32
33
34static void simtec_nor_vpp(struct map_info *map, int vpp)
35{
36 unsigned int val;
37 unsigned long flags;
38
39 local_irq_save(flags);
40 val = __raw_readb(BAST_VA_CTRL3);
41
42 printk(KERN_DEBUG "%s(%d)\n", __func__, vpp);
43
44 if (vpp)
45 val |= BAST_CPLD_CTRL3_ROMWEN;
46 else
47 val &= ~BAST_CPLD_CTRL3_ROMWEN;
48
49 __raw_writeb(val, BAST_VA_CTRL3);
50 local_irq_restore(flags);
51}
52
53struct physmap_flash_data simtec_nor_pdata = {
54 .width = 2,
55 .set_vpp = simtec_nor_vpp,
56 .nr_parts = 0,
57};
58
59static struct resource simtec_nor_resource[] = {
60 [0] = {
61 .start = S3C2410_CS1 + 0x4000000,
62 .end = S3C2410_CS1 + 0x4000000 + SZ_8M - 1,
63 .flags = IORESOURCE_MEM,
64 }
65};
66
67static struct platform_device simtec_device_nor = {
68 .name = "physmap-flash",
69 .id = -1,
70 .num_resources = ARRAY_SIZE(simtec_nor_resource),
71 .resource = simtec_nor_resource,
72 .dev = {
73 .platform_data = &simtec_nor_pdata,
74 },
75};
76
77void __init nor_simtec_init(void)
78{
79 int ret;
80
81 ret = platform_device_register(&simtec_device_nor);
82 if (ret < 0)
83 printk(KERN_ERR "failed to register physmap-flash device\n");
84 else
85 simtec_nor_vpp(NULL, 1);
86}
diff --git a/arch/arm/mach-s3c2410/nor-simtec.h b/arch/arm/mach-s3c2410/nor-simtec.h
new file mode 100644
index 000000000000..f619c1e0d0c8
--- /dev/null
+++ b/arch/arm/mach-s3c2410/nor-simtec.h
@@ -0,0 +1,14 @@
1/* linux/arch/arm/mach-s3c2410/nor-simtec.h
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * Simtec NOR mapping
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14extern void nor_simtec_init(void);
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 0b43431d4b75..c59a9d2ee9a6 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -34,6 +34,16 @@ config S3C2412_PM
34 34
35menu "S3C2412 Machines" 35menu "S3C2412 Machines"
36 36
37config MACH_JIVE
38 bool "Logitech Jive"
39 select CPU_S3C2412
40 help
41 Say Y here if you are using the Logitech Jive.
42
43config MACH_JIVE_SHOW_BOOTLOADER
44 bool "Allow access to bootloader partitions in MTD"
45 depends on MACH_JIVE && EXPERIMENTAL
46
37config MACH_SMDK2413 47config MACH_SMDK2413
38 bool "SMDK2413" 48 bool "SMDK2413"
39 select CPU_S3C2412 49 select CPU_S3C2412
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 267f3348301e..20918d5dc6a9 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -18,5 +18,6 @@ obj-$(CONFIG_S3C2412_PM) += pm.o sleep.o
18 18
19# Machine support 19# Machine support
20 20
21obj-$(CONFIG_MACH_JIVE) += mach-jive.o
21obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o 22obj-$(CONFIG_MACH_SMDK2413) += mach-smdk2413.o
22obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o 23obj-$(CONFIG_MACH_VSTMS) += mach-vstms.o
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 2697a65ba727..1157b5a16263 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -631,6 +631,17 @@ static struct clk_init clks_src[] __initdata = {
631 .bit = S3C2412_CLKSRC_USBCLK_HCLK, 631 .bit = S3C2412_CLKSRC_USBCLK_HCLK,
632 .src_0 = &clk_usysclk, 632 .src_0 = &clk_usysclk,
633 .src_1 = &clk_h, 633 .src_1 = &clk_h,
634 /* here we assume OM[4] select xtal */
635 }, {
636 .clk = &clk_erefclk,
637 .bit = S3C2412_CLKSRC_EREFCLK_EXTCLK,
638 .src_0 = &clk_xtal,
639 .src_1 = &clk_ext,
640 }, {
641 .clk = &clk_urefclk,
642 .bit = S3C2412_CLKSRC_UREFCLK_EXTCLK,
643 .src_0 = &clk_xtal,
644 .src_1 = &clk_ext,
634 }, 645 },
635}; 646};
636 647
@@ -666,8 +677,6 @@ static void __init s3c2412_clk_initparents(void)
666static struct clk *clks[] __initdata = { 677static struct clk *clks[] __initdata = {
667 &clk_ext, 678 &clk_ext,
668 &clk_usb_bus, 679 &clk_usb_bus,
669 &clk_erefclk,
670 &clk_urefclk,
671 &clk_mrefclk, 680 &clk_mrefclk,
672 &clk_armclk, 681 &clk_armclk,
673}; 682};
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
new file mode 100644
index 000000000000..7f5924713485
--- /dev/null
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -0,0 +1,687 @@
1/* linux/arch/arm/mach-s3c2410/mach-jive.c
2 *
3 * Copyright 2007 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/sysdev.h>
20#include <linux/delay.h>
21#include <linux/serial_core.h>
22#include <linux/platform_device.h>
23#include <linux/i2c.h>
24
25#include <video/ili9320.h>
26
27#include <linux/spi/spi.h>
28
29#include <linux/mtd/mtd.h>
30#include <linux/mtd/partitions.h>
31
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34#include <asm/mach/irq.h>
35
36#include <asm/plat-s3c/regs-serial.h>
37#include <asm/plat-s3c/nand.h>
38#include <asm/plat-s3c/iic.h>
39
40#include <asm/arch/regs-power.h>
41#include <asm/arch/regs-gpio.h>
42#include <asm/arch/regs-mem.h>
43#include <asm/arch/regs-lcd.h>
44#include <asm/arch/spi-gpio.h>
45#include <asm/arch/fb.h>
46
47#include <asm/mach-types.h>
48
49#include <linux/mtd/mtd.h>
50#include <linux/mtd/nand.h>
51#include <linux/mtd/nand_ecc.h>
52#include <linux/mtd/partitions.h>
53
54#include <asm/plat-s3c24xx/clock.h>
55#include <asm/plat-s3c24xx/devs.h>
56#include <asm/plat-s3c24xx/cpu.h>
57#include <asm/plat-s3c24xx/pm.h>
58#include <asm/plat-s3c24xx/udc.h>
59
60static struct map_desc jive_iodesc[] __initdata = {
61};
62
63#define UCON S3C2410_UCON_DEFAULT
64#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
65#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
66
67static struct s3c2410_uartcfg jive_uartcfgs[] = {
68 [0] = {
69 .hwport = 0,
70 .flags = 0,
71 .ucon = UCON,
72 .ulcon = ULCON,
73 .ufcon = UFCON,
74 },
75 [1] = {
76 .hwport = 1,
77 .flags = 0,
78 .ucon = UCON,
79 .ulcon = ULCON,
80 .ufcon = UFCON,
81 },
82 [2] = {
83 .hwport = 2,
84 .flags = 0,
85 .ucon = UCON,
86 .ulcon = ULCON,
87 .ufcon = UFCON,
88 }
89};
90
91/* Jive flash assignment
92 *
93 * 0x00000000-0x00028000 : uboot
94 * 0x00028000-0x0002c000 : uboot env
95 * 0x0002c000-0x00030000 : spare
96 * 0x00030000-0x00200000 : zimage A
97 * 0x00200000-0x01600000 : cramfs A
98 * 0x01600000-0x017d0000 : zimage B
99 * 0x017d0000-0x02bd0000 : cramfs B
100 * 0x02bd0000-0x03fd0000 : yaffs
101 */
102static struct mtd_partition jive_imageA_nand_part[] = {
103
104#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
105 /* Don't allow access to the bootloader from linux */
106 {
107 .name = "uboot",
108 .offset = 0,
109 .size = (160 * SZ_1K),
110 .mask_flags = MTD_WRITEABLE, /* force read-only */
111 },
112
113 /* spare */
114 {
115 .name = "spare",
116 .offset = (176 * SZ_1K),
117 .size = (16 * SZ_1K),
118 },
119#endif
120
121 /* booted images */
122 {
123 .name = "kernel (ro)",
124 .offset = (192 * SZ_1K),
125 .size = (SZ_2M) - (192 * SZ_1K),
126 .mask_flags = MTD_WRITEABLE, /* force read-only */
127 }, {
128 .name = "root (ro)",
129 .offset = (SZ_2M),
130 .size = (20 * SZ_1M),
131 .mask_flags = MTD_WRITEABLE, /* force read-only */
132 },
133
134 /* yaffs */
135 {
136 .name = "yaffs",
137 .offset = (44 * SZ_1M),
138 .size = (20 * SZ_1M),
139 },
140
141 /* bootloader environment */
142 {
143 .name = "env",
144 .offset = (160 * SZ_1K),
145 .size = (16 * SZ_1K),
146 },
147
148 /* upgrade images */
149 {
150 .name = "zimage",
151 .offset = (22 * SZ_1M),
152 .size = (2 * SZ_1M) - (192 * SZ_1K),
153 }, {
154 .name = "cramfs",
155 .offset = (24 * SZ_1M) - (192*SZ_1K),
156 .size = (20 * SZ_1M),
157 },
158};
159
160static struct mtd_partition jive_imageB_nand_part[] = {
161
162#ifdef CONFIG_MACH_JIVE_SHOW_BOOTLOADER
163 /* Don't allow access to the bootloader from linux */
164 {
165 .name = "uboot",
166 .offset = 0,
167 .size = (160 * SZ_1K),
168 .mask_flags = MTD_WRITEABLE, /* force read-only */
169 },
170
171 /* spare */
172 {
173 .name = "spare",
174 .offset = (176 * SZ_1K),
175 .size = (16 * SZ_1K),
176 },
177#endif
178
179 /* booted images */
180 {
181 .name = "kernel (ro)",
182 .offset = (22 * SZ_1M),
183 .size = (2 * SZ_1M) - (192 * SZ_1K),
184 .mask_flags = MTD_WRITEABLE, /* force read-only */
185 },
186 {
187 .name = "root (ro)",
188 .offset = (24 * SZ_1M) - (192 * SZ_1K),
189 .size = (20 * SZ_1M),
190 .mask_flags = MTD_WRITEABLE, /* force read-only */
191 },
192
193 /* yaffs */
194 {
195 .name = "yaffs",
196 .offset = (44 * SZ_1M),
197 .size = (20 * SZ_1M),
198 },
199
200 /* bootloader environment */
201 {
202 .name = "env",
203 .offset = (160 * SZ_1K),
204 .size = (16 * SZ_1K),
205 },
206
207 /* upgrade images */
208 {
209 .name = "zimage",
210 .offset = (192 * SZ_1K),
211 .size = (2 * SZ_1M) - (192 * SZ_1K),
212 }, {
213 .name = "cramfs",
214 .offset = (2 * SZ_1M),
215 .size = (20 * SZ_1M),
216 },
217};
218
219static struct s3c2410_nand_set jive_nand_sets[] = {
220 [0] = {
221 .name = "flash",
222 .nr_chips = 1,
223 .nr_partitions = ARRAY_SIZE(jive_imageA_nand_part),
224 .partitions = jive_imageA_nand_part,
225 },
226};
227
228static struct s3c2410_platform_nand jive_nand_info = {
229 /* set taken from osiris nand timings, possibly still conservative */
230 .tacls = 30,
231 .twrph0 = 55,
232 .twrph1 = 40,
233 .sets = jive_nand_sets,
234 .nr_sets = ARRAY_SIZE(jive_nand_sets),
235};
236
237static int __init jive_mtdset(char *options)
238{
239 struct s3c2410_nand_set *nand = &jive_nand_sets[0];
240 unsigned long set;
241
242 if (options == NULL || options[0] == '\0')
243 return 0;
244
245 if (strict_strtoul(options, 10, &set)) {
246 printk(KERN_ERR "failed to parse mtdset=%s\n", options);
247 return 0;
248 }
249
250 switch (set) {
251 case 1:
252 nand->nr_partitions = ARRAY_SIZE(jive_imageB_nand_part);
253 nand->partitions = jive_imageB_nand_part;
254 case 0:
255 /* this is already setup in the nand info */
256 break;
257 default:
258 printk(KERN_ERR "Unknown mtd set %ld specified,"
259 "using default.", set);
260 }
261
262 return 0;
263}
264
265/* parse the mtdset= option given to the kernel command line */
266__setup("mtdset=", jive_mtdset);
267
268/* LCD timing and setup */
269
270#define LCD_XRES (240)
271#define LCD_YRES (320)
272#define LCD_LEFT_MARGIN (12)
273#define LCD_RIGHT_MARGIN (12)
274#define LCD_LOWER_MARGIN (12)
275#define LCD_UPPER_MARGIN (12)
276#define LCD_VSYNC (2)
277#define LCD_HSYNC (2)
278
279#define LCD_REFRESH (60)
280
281#define LCD_HTOT (LCD_HSYNC + LCD_LEFT_MARGIN + LCD_XRES + LCD_RIGHT_MARGIN)
282#define LCD_VTOT (LCD_VSYNC + LCD_LOWER_MARGIN + LCD_YRES + LCD_UPPER_MARGIN)
283
284struct s3c2410fb_display jive_vgg2432a4_display[] = {
285 [0] = {
286 .width = LCD_XRES,
287 .height = LCD_YRES,
288 .xres = LCD_XRES,
289 .yres = LCD_YRES,
290 .left_margin = LCD_LEFT_MARGIN,
291 .right_margin = LCD_RIGHT_MARGIN,
292 .upper_margin = LCD_UPPER_MARGIN,
293 .lower_margin = LCD_LOWER_MARGIN,
294 .hsync_len = LCD_HSYNC,
295 .vsync_len = LCD_VSYNC,
296
297 .pixclock = (1000000000000LL /
298 (LCD_REFRESH * LCD_HTOT * LCD_VTOT)),
299
300 .bpp = 16,
301 .type = (S3C2410_LCDCON1_TFT16BPP |
302 S3C2410_LCDCON1_TFT),
303
304 .lcdcon5 = (S3C2410_LCDCON5_FRM565 |
305 S3C2410_LCDCON5_INVVLINE |
306 S3C2410_LCDCON5_INVVFRAME |
307 S3C2410_LCDCON5_INVVDEN |
308 S3C2410_LCDCON5_PWREN),
309 },
310};
311
312/* todo - put into gpio header */
313
314#define S3C2410_GPCCON_MASK(x) (3 << ((x) * 2))
315#define S3C2410_GPDCON_MASK(x) (3 << ((x) * 2))
316
317struct s3c2410fb_mach_info jive_lcd_config = {
318 .displays = jive_vgg2432a4_display,
319 .num_displays = ARRAY_SIZE(jive_vgg2432a4_display),
320 .default_display = 0,
321
322 /* Enable VD[2..7], VD[10..15], VD[18..23] and VCLK, syncs, VDEN
323 * and disable the pull down resistors on pins we are using for LCD
324 * data. */
325
326 .gpcup = (0xf << 1) | (0x3f << 10),
327
328 .gpccon = (S3C2410_GPC1_VCLK | S3C2410_GPC2_VLINE |
329 S3C2410_GPC3_VFRAME | S3C2410_GPC4_VM |
330 S3C2410_GPC10_VD2 | S3C2410_GPC11_VD3 |
331 S3C2410_GPC12_VD4 | S3C2410_GPC13_VD5 |
332 S3C2410_GPC14_VD6 | S3C2410_GPC15_VD7),
333
334 .gpccon_mask = (S3C2410_GPCCON_MASK(1) | S3C2410_GPCCON_MASK(2) |
335 S3C2410_GPCCON_MASK(3) | S3C2410_GPCCON_MASK(4) |
336 S3C2410_GPCCON_MASK(10) | S3C2410_GPCCON_MASK(11) |
337 S3C2410_GPCCON_MASK(12) | S3C2410_GPCCON_MASK(13) |
338 S3C2410_GPCCON_MASK(14) | S3C2410_GPCCON_MASK(15)),
339
340 .gpdup = (0x3f << 2) | (0x3f << 10),
341
342 .gpdcon = (S3C2410_GPD2_VD10 | S3C2410_GPD3_VD11 |
343 S3C2410_GPD4_VD12 | S3C2410_GPD5_VD13 |
344 S3C2410_GPD6_VD14 | S3C2410_GPD7_VD15 |
345 S3C2410_GPD10_VD18 | S3C2410_GPD11_VD19 |
346 S3C2410_GPD12_VD20 | S3C2410_GPD13_VD21 |
347 S3C2410_GPD14_VD22 | S3C2410_GPD15_VD23),
348
349 .gpdcon_mask = (S3C2410_GPDCON_MASK(2) | S3C2410_GPDCON_MASK(3) |
350 S3C2410_GPDCON_MASK(4) | S3C2410_GPDCON_MASK(5) |
351 S3C2410_GPDCON_MASK(6) | S3C2410_GPDCON_MASK(7) |
352 S3C2410_GPDCON_MASK(10) | S3C2410_GPDCON_MASK(11)|
353 S3C2410_GPDCON_MASK(12) | S3C2410_GPDCON_MASK(13)|
354 S3C2410_GPDCON_MASK(14) | S3C2410_GPDCON_MASK(15)),
355};
356
357/* ILI9320 support. */
358
359static void jive_lcm_reset(unsigned int set)
360{
361 printk(KERN_DEBUG "%s(%d)\n", __func__, set);
362
363 s3c2410_gpio_setpin(S3C2410_GPG13, set);
364 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
365}
366
367#undef LCD_UPPER_MARGIN
368#define LCD_UPPER_MARGIN 2
369
370static struct ili9320_platdata jive_lcm_config = {
371 .hsize = LCD_XRES,
372 .vsize = LCD_YRES,
373
374 .reset = jive_lcm_reset,
375 .suspend = ILI9320_SUSPEND_DEEP,
376
377 .entry_mode = ILI9320_ENTRYMODE_ID(3) | ILI9320_ENTRYMODE_BGR,
378 .display2 = (ILI9320_DISPLAY2_FP(LCD_UPPER_MARGIN) |
379 ILI9320_DISPLAY2_BP(LCD_LOWER_MARGIN)),
380 .display3 = 0x0,
381 .display4 = 0x0,
382 .rgb_if1 = (ILI9320_RGBIF1_RIM_RGB18 |
383 ILI9320_RGBIF1_RM | ILI9320_RGBIF1_CLK_RGBIF),
384 .rgb_if2 = ILI9320_RGBIF2_DPL,
385 .interface2 = 0x0,
386 .interface3 = 0x3,
387 .interface4 = (ILI9320_INTERFACE4_RTNE(16) |
388 ILI9320_INTERFACE4_DIVE(1)),
389 .interface5 = 0x0,
390 .interface6 = 0x0,
391};
392
393/* LCD SPI support */
394
395static void jive_lcd_spi_chipselect(struct s3c2410_spigpio_info *spi, int cs)
396{
397 s3c2410_gpio_setpin(S3C2410_GPB7, cs ? 0 : 1);
398}
399
400static struct s3c2410_spigpio_info jive_lcd_spi = {
401 .bus_num = 0,
402 .pin_clk = S3C2410_GPG8,
403 .pin_mosi = S3C2410_GPB8,
404 .chip_select = jive_lcd_spi_chipselect,
405};
406
407static struct platform_device jive_device_lcdspi = {
408 .name = "s3c24xx-spi-gpio",
409 .id = 1,
410 .num_resources = 0,
411 .dev.platform_data = &jive_lcd_spi,
412};
413
414/* WM8750 audio code SPI definition */
415
416static void jive_wm8750_chipselect(struct s3c2410_spigpio_info *spi, int cs)
417{
418 s3c2410_gpio_setpin(S3C2410_GPH10, cs ? 0 : 1);
419}
420
421static struct s3c2410_spigpio_info jive_wm8750_spi = {
422 .bus_num = 2,
423 .pin_clk = S3C2410_GPB4,
424 .pin_mosi = S3C2410_GPB9,
425 .chip_select = jive_wm8750_chipselect,
426};
427
428static struct platform_device jive_device_wm8750 = {
429 .name = "s3c24xx-spi-gpio",
430 .id = 2,
431 .num_resources = 0,
432 .dev.platform_data = &jive_wm8750_spi,
433};
434
435/* JIVE SPI devices. */
436
437static struct spi_board_info __initdata jive_spi_devs[] = {
438 [0] = {
439 .modalias = "VGG2432A4",
440 .bus_num = 1,
441 .chip_select = 0,
442 .mode = SPI_MODE_3, /* CPOL=1, CPHA=1 */
443 .max_speed_hz = 100000,
444 .platform_data = &jive_lcm_config,
445 }, {
446 .modalias = "WM8750",
447 .bus_num = 2,
448 .chip_select = 0,
449 .mode = SPI_MODE_0, /* CPOL=0, CPHA=0 */
450 .max_speed_hz = 100000,
451 },
452};
453
454/* I2C bus and device configuration. */
455
456static struct s3c2410_platform_i2c jive_i2c_cfg = {
457 .max_freq = 80 * 1000,
458 .bus_freq = 50 * 1000,
459 .flags = S3C_IICFLG_FILTER,
460 .sda_delay = 2,
461};
462
463static struct i2c_board_info jive_i2c_devs[] = {
464 [0] = {
465 I2C_BOARD_INFO("lis302dl", 0x1c),
466 .irq = IRQ_EINT14,
467 },
468};
469
470/* The platform devices being used. */
471
472static struct platform_device *jive_devices[] __initdata = {
473 &s3c_device_usb,
474 &s3c_device_rtc,
475 &s3c_device_wdt,
476 &s3c_device_i2c,
477 &s3c_device_lcd,
478 &jive_device_lcdspi,
479 &jive_device_wm8750,
480 &s3c_device_nand,
481 &s3c_device_usbgadget,
482};
483
484static struct s3c2410_udc_mach_info jive_udc_cfg __initdata = {
485 .vbus_pin = S3C2410_GPG1, /* detect is on GPG1 */
486};
487
488/* Jive power management device */
489
490#ifdef CONFIG_PM
491static int jive_pm_suspend(struct sys_device *sd, pm_message_t state)
492{
493 /* Write the magic value u-boot uses to check for resume into
494 * the INFORM0 register, and ensure INFORM1 is set to the
495 * correct address to resume from. */
496
497 __raw_writel(0x2BED, S3C2412_INFORM0);
498 __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1);
499
500 return 0;
501}
502
503static int jive_pm_resume(struct sys_device *sd)
504{
505 __raw_writel(0x0, S3C2412_INFORM0);
506 return 0;
507}
508
509#else
510#define jive_pm_suspend NULL
511#define jive_pm_resume NULL
512#endif
513
514static struct sysdev_class jive_pm_sysclass = {
515 .name = "jive-pm",
516 .suspend = jive_pm_suspend,
517 .resume = jive_pm_resume,
518};
519
520static struct sys_device jive_pm_sysdev = {
521 .cls = &jive_pm_sysclass,
522};
523
524static void __init jive_map_io(void)
525{
526 s3c24xx_init_io(jive_iodesc, ARRAY_SIZE(jive_iodesc));
527 s3c24xx_init_clocks(12000000);
528 s3c24xx_init_uarts(jive_uartcfgs, ARRAY_SIZE(jive_uartcfgs));
529}
530
531static void jive_power_off(void)
532{
533 printk(KERN_INFO "powering system down...\n");
534
535 s3c2410_gpio_setpin(S3C2410_GPC5, 1);
536 s3c2410_gpio_cfgpin(S3C2410_GPC5, S3C2410_GPIO_OUTPUT);
537}
538
539static void __init jive_machine_init(void)
540{
541 /* register system devices for managing low level suspend */
542
543 sysdev_class_register(&jive_pm_sysclass);
544 sysdev_register(&jive_pm_sysdev);
545
546 /* write our sleep configurations for the IO. Pull down all unused
547 * IO, ensure that we have turned off all peripherals we do not
548 * need, and configure the ones we do need. */
549
550 /* Port B sleep */
551
552 __raw_writel(S3C2412_SLPCON_IN(0) |
553 S3C2412_SLPCON_PULL(1) |
554 S3C2412_SLPCON_HIGH(2) |
555 S3C2412_SLPCON_PULL(3) |
556 S3C2412_SLPCON_PULL(4) |
557 S3C2412_SLPCON_PULL(5) |
558 S3C2412_SLPCON_PULL(6) |
559 S3C2412_SLPCON_HIGH(7) |
560 S3C2412_SLPCON_PULL(8) |
561 S3C2412_SLPCON_PULL(9) |
562 S3C2412_SLPCON_PULL(10), S3C2412_GPBSLPCON);
563
564 /* Port C sleep */
565
566 __raw_writel(S3C2412_SLPCON_PULL(0) |
567 S3C2412_SLPCON_PULL(1) |
568 S3C2412_SLPCON_PULL(2) |
569 S3C2412_SLPCON_PULL(3) |
570 S3C2412_SLPCON_PULL(4) |
571 S3C2412_SLPCON_PULL(5) |
572 S3C2412_SLPCON_LOW(6) |
573 S3C2412_SLPCON_PULL(6) |
574 S3C2412_SLPCON_PULL(7) |
575 S3C2412_SLPCON_PULL(8) |
576 S3C2412_SLPCON_PULL(9) |
577 S3C2412_SLPCON_PULL(10) |
578 S3C2412_SLPCON_PULL(11) |
579 S3C2412_SLPCON_PULL(12) |
580 S3C2412_SLPCON_PULL(13) |
581 S3C2412_SLPCON_PULL(14) |
582 S3C2412_SLPCON_PULL(15), S3C2412_GPCSLPCON);
583
584 /* Port D sleep */
585
586 __raw_writel(S3C2412_SLPCON_ALL_PULL, S3C2412_GPDSLPCON);
587
588 /* Port F sleep */
589
590 __raw_writel(S3C2412_SLPCON_LOW(0) |
591 S3C2412_SLPCON_LOW(1) |
592 S3C2412_SLPCON_LOW(2) |
593 S3C2412_SLPCON_EINT(3) |
594 S3C2412_SLPCON_EINT(4) |
595 S3C2412_SLPCON_EINT(5) |
596 S3C2412_SLPCON_EINT(6) |
597 S3C2412_SLPCON_EINT(7), S3C2412_GPFSLPCON);
598
599 /* Port G sleep */
600
601 __raw_writel(S3C2412_SLPCON_IN(0) |
602 S3C2412_SLPCON_IN(1) |
603 S3C2412_SLPCON_IN(2) |
604 S3C2412_SLPCON_IN(3) |
605 S3C2412_SLPCON_IN(4) |
606 S3C2412_SLPCON_IN(5) |
607 S3C2412_SLPCON_IN(6) |
608 S3C2412_SLPCON_IN(7) |
609 S3C2412_SLPCON_PULL(8) |
610 S3C2412_SLPCON_PULL(9) |
611 S3C2412_SLPCON_IN(10) |
612 S3C2412_SLPCON_PULL(11) |
613 S3C2412_SLPCON_PULL(12) |
614 S3C2412_SLPCON_PULL(13) |
615 S3C2412_SLPCON_IN(14) |
616 S3C2412_SLPCON_PULL(15), S3C2412_GPGSLPCON);
617
618 /* Port H sleep */
619
620 __raw_writel(S3C2412_SLPCON_PULL(0) |
621 S3C2412_SLPCON_PULL(1) |
622 S3C2412_SLPCON_PULL(2) |
623 S3C2412_SLPCON_PULL(3) |
624 S3C2412_SLPCON_PULL(4) |
625 S3C2412_SLPCON_PULL(5) |
626 S3C2412_SLPCON_PULL(6) |
627 S3C2412_SLPCON_IN(7) |
628 S3C2412_SLPCON_IN(8) |
629 S3C2412_SLPCON_PULL(9) |
630 S3C2412_SLPCON_IN(10), S3C2412_GPHSLPCON);
631
632 /* initialise the power management now we've setup everything. */
633
634 s3c2410_pm_init();
635
636 s3c_device_nand.dev.platform_data = &jive_nand_info;
637
638 /* initialise the spi */
639
640 s3c2410_gpio_setpin(S3C2410_GPG13, 0);
641 s3c2410_gpio_cfgpin(S3C2410_GPG13, S3C2410_GPIO_OUTPUT);
642
643 s3c2410_gpio_setpin(S3C2410_GPB7, 1);
644 s3c2410_gpio_cfgpin(S3C2410_GPB7, S3C2410_GPIO_OUTPUT);
645
646 s3c2410_gpio_setpin(S3C2410_GPB6, 0);
647 s3c2410_gpio_cfgpin(S3C2410_GPB6, S3C2410_GPIO_OUTPUT);
648
649 s3c2410_gpio_setpin(S3C2410_GPG8, 1);
650 s3c2410_gpio_cfgpin(S3C2410_GPG8, S3C2410_GPIO_OUTPUT);
651
652 /* initialise the WM8750 spi */
653
654 s3c2410_gpio_setpin(S3C2410_GPH10, 1);
655 s3c2410_gpio_cfgpin(S3C2410_GPH10, S3C2410_GPIO_OUTPUT);
656
657 /* Turn off suspend on both USB ports, and switch the
658 * selectable USB port to USB device mode. */
659
660 s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
661 S3C2410_MISCCR_USBSUSPND0 |
662 S3C2410_MISCCR_USBSUSPND1, 0x0);
663
664 s3c24xx_udc_set_platdata(&jive_udc_cfg);
665 s3c24xx_fb_set_platdata(&jive_lcd_config);
666
667 spi_register_board_info(jive_spi_devs, ARRAY_SIZE(jive_spi_devs));
668
669 s3c_device_i2c.dev.platform_data = &jive_i2c_cfg;
670 i2c_register_board_info(0, jive_i2c_devs, ARRAY_SIZE(jive_i2c_devs));
671
672 pm_power_off = jive_power_off;
673
674 platform_add_devices(jive_devices, ARRAY_SIZE(jive_devices));
675}
676
677MACHINE_START(JIVE, "JIVE")
678 /* Maintainer: Ben Dooks <ben@fluff.org> */
679 .phys_io = S3C2410_PA_UART,
680 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
681 .boot_params = S3C2410_SDRAM_PA + 0x100,
682
683 .init_irq = s3c24xx_init_irq,
684 .map_io = jive_map_io,
685 .init_machine = jive_machine_init,
686 .timer = &s3c24xx_timer,
687MACHINE_END
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index f1915bd61d15..25de042ab996 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -29,6 +29,7 @@ config MACH_ANUBIS
29 bool "Simtec Electronics ANUBIS" 29 bool "Simtec Electronics ANUBIS"
30 select CPU_S3C2440 30 select CPU_S3C2440
31 select PM_SIMTEC if PM 31 select PM_SIMTEC if PM
32 select HAVE_PATA_PLATFORM
32 help 33 help
33 Say Y here if you are using the Simtec Electronics ANUBIS 34 Say Y here if you are using the Simtec Electronics ANUBIS
34 development system 35 development system
@@ -67,6 +68,11 @@ config SMDK2440_CPU2440
67 default y if ARCH_S3C2440 68 default y if ARCH_S3C2440
68 select CPU_S3C2440 69 select CPU_S3C2440
69 70
71config MACH_AT2440EVB
72 bool "Avantech AT2440EVB development board"
73 select CPU_S3C2440
74 help
75 Say Y here if you are using the AT2440EVB development board
70 76
71endmenu 77endmenu
72 78
diff --git a/arch/arm/mach-s3c2440/Makefile b/arch/arm/mach-s3c2440/Makefile
index c81ed6248dcb..0b4440e79b90 100644
--- a/arch/arm/mach-s3c2440/Makefile
+++ b/arch/arm/mach-s3c2440/Makefile
@@ -21,3 +21,4 @@ obj-$(CONFIG_MACH_OSIRIS) += mach-osiris.o
21obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o 21obj-$(CONFIG_MACH_RX3715) += mach-rx3715.o
22obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o 22obj-$(CONFIG_ARCH_S3C2440) += mach-smdk2440.o
23obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o 23obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
24obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 47258915a2f9..09af8b23500b 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2440/mach-anubis.c 1/* linux/arch/arm/mach-s3c2440/mach-anubis.c
2 * 2 *
3 * Copyright (c) 2003-2005 Simtec Electronics 3 * Copyright (c) 2003-2005,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
@@ -17,6 +17,8 @@
17#include <linux/init.h> 17#include <linux/init.h>
18#include <linux/serial_core.h> 18#include <linux/serial_core.h>
19#include <linux/platform_device.h> 19#include <linux/platform_device.h>
20#include <linux/ata_platform.h>
21#include <linux/i2c.h>
20 22
21#include <linux/sm501.h> 23#include <linux/sm501.h>
22#include <linux/sm501-regs.h> 24#include <linux/sm501-regs.h>
@@ -241,14 +243,18 @@ static struct s3c2410_platform_nand anubis_nand_info = {
241 243
242/* IDE channels */ 244/* IDE channels */
243 245
246struct pata_platform_info anubis_ide_platdata = {
247 .ioport_shift = 5,
248};
249
244static struct resource anubis_ide0_resource[] = { 250static struct resource anubis_ide0_resource[] = {
245 { 251 {
246 .start = S3C2410_CS3, 252 .start = S3C2410_CS3,
247 .end = S3C2410_CS3 + (8*32) - 1, 253 .end = S3C2410_CS3 + (8*32) - 1,
248 .flags = IORESOURCE_MEM, 254 .flags = IORESOURCE_MEM,
249 }, { 255 }, {
250 .start = S3C2410_CS3 + (1<<26), 256 .start = S3C2410_CS3 + (1<<26) + (6*32),
251 .end = S3C2410_CS3 + (1<<26) + (8*32) - 1, 257 .end = S3C2410_CS3 + (1<<26) + (7*32) - 1,
252 .flags = IORESOURCE_MEM, 258 .flags = IORESOURCE_MEM,
253 }, { 259 }, {
254 .start = IRQ_IDE0, 260 .start = IRQ_IDE0,
@@ -258,10 +264,14 @@ static struct resource anubis_ide0_resource[] = {
258}; 264};
259 265
260static struct platform_device anubis_device_ide0 = { 266static struct platform_device anubis_device_ide0 = {
261 .name = "simtec-ide", 267 .name = "pata_platform",
262 .id = 0, 268 .id = 0,
263 .num_resources = ARRAY_SIZE(anubis_ide0_resource), 269 .num_resources = ARRAY_SIZE(anubis_ide0_resource),
264 .resource = anubis_ide0_resource, 270 .resource = anubis_ide0_resource,
271 .dev = {
272 .platform_data = &anubis_ide_platdata,
273 .coherent_dma_mask = ~0,
274 },
265}; 275};
266 276
267static struct resource anubis_ide1_resource[] = { 277static struct resource anubis_ide1_resource[] = {
@@ -270,8 +280,8 @@ static struct resource anubis_ide1_resource[] = {
270 .end = S3C2410_CS4 + (8*32) - 1, 280 .end = S3C2410_CS4 + (8*32) - 1,
271 .flags = IORESOURCE_MEM, 281 .flags = IORESOURCE_MEM,
272 }, { 282 }, {
273 .start = S3C2410_CS4 + (1<<26), 283 .start = S3C2410_CS4 + (1<<26) + (6*32),
274 .end = S3C2410_CS4 + (1<<26) + (8*32) - 1, 284 .end = S3C2410_CS4 + (1<<26) + (7*32) - 1,
275 .flags = IORESOURCE_MEM, 285 .flags = IORESOURCE_MEM,
276 }, { 286 }, {
277 .start = IRQ_IDE0, 287 .start = IRQ_IDE0,
@@ -280,12 +290,15 @@ static struct resource anubis_ide1_resource[] = {
280 }, 290 },
281}; 291};
282 292
283
284static struct platform_device anubis_device_ide1 = { 293static struct platform_device anubis_device_ide1 = {
285 .name = "simtec-ide", 294 .name = "pata_platform",
286 .id = 1, 295 .id = 1,
287 .num_resources = ARRAY_SIZE(anubis_ide1_resource), 296 .num_resources = ARRAY_SIZE(anubis_ide1_resource),
288 .resource = anubis_ide1_resource, 297 .resource = anubis_ide1_resource,
298 .dev = {
299 .platform_data = &anubis_ide_platdata,
300 .coherent_dma_mask = ~0,
301 },
289}; 302};
290 303
291/* Asix AX88796 10/100 ethernet controller */ 304/* Asix AX88796 10/100 ethernet controller */
@@ -409,6 +422,15 @@ static struct clk *anubis_clocks[] = {
409 &s3c24xx_uclk, 422 &s3c24xx_uclk,
410}; 423};
411 424
425/* I2C devices. */
426
427static struct i2c_board_info anubis_i2c_devs[] __initdata = {
428 {
429 I2C_BOARD_INFO("tps65011", 0x48),
430 .irq = IRQ_EINT20,
431 }
432};
433
412static void __init anubis_map_io(void) 434static void __init anubis_map_io(void)
413{ 435{
414 /* initialise the clocks */ 436 /* initialise the clocks */
@@ -448,6 +470,9 @@ static void __init anubis_map_io(void)
448static void __init anubis_init(void) 470static void __init anubis_init(void)
449{ 471{
450 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices)); 472 platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
473
474 i2c_register_board_info(0, anubis_i2c_devs,
475 ARRAY_SIZE(anubis_i2c_devs));
451} 476}
452 477
453 478
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
new file mode 100644
index 000000000000..f5e3c7f27639
--- /dev/null
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -0,0 +1,198 @@
1/* linux/arch/arm/mach-s3c2440/mach-at2440evb.c
2 *
3 * Copyright (c) 2008 Ramax Lo <ramaxlo@gmail.com>
4 * Based on mach-anubis.c by Ben Dooks <ben@simtec.co.uk>
5 * and modifications by SBZ <sbz@spgui.org> and
6 * Weibing <http://weibing.blogbus.com>
7 *
8 * For product information, visit http://www.arm9e.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/serial_core.h>
23#include <linux/dm9000.h>
24#include <linux/platform_device.h>
25
26#include <asm/mach/arch.h>
27#include <asm/mach/map.h>
28#include <asm/mach/irq.h>
29
30#include <asm/hardware.h>
31#include <asm/irq.h>
32#include <asm/mach-types.h>
33
34#include <asm/plat-s3c/regs-serial.h>
35#include <asm/arch/regs-gpio.h>
36#include <asm/arch/regs-mem.h>
37#include <asm/arch/regs-lcd.h>
38#include <asm/plat-s3c/nand.h>
39
40#include <linux/mtd/mtd.h>
41#include <linux/mtd/nand.h>
42#include <linux/mtd/nand_ecc.h>
43#include <linux/mtd/partitions.h>
44
45#include <asm/plat-s3c24xx/clock.h>
46#include <asm/plat-s3c24xx/devs.h>
47#include <asm/plat-s3c24xx/cpu.h>
48
49static struct map_desc at2440evb_iodesc[] __initdata = {
50 /* Nothing here */
51};
52
53#define UCON S3C2410_UCON_DEFAULT
54#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
55#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
56
57static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = {
58 [0] = {
59 .name = "uclk",
60 .divisor = 1,
61 .min_baud = 0,
62 .max_baud = 0,
63 },
64 [1] = {
65 .name = "pclk",
66 .divisor = 1,
67 .min_baud = 0,
68 .max_baud = 0,
69 }
70};
71
72
73static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = {
74 [0] = {
75 .hwport = 0,
76 .flags = 0,
77 .ucon = UCON,
78 .ulcon = ULCON,
79 .ufcon = UFCON,
80 .clocks = at2440evb_serial_clocks,
81 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
82 },
83 [1] = {
84 .hwport = 1,
85 .flags = 0,
86 .ucon = UCON,
87 .ulcon = ULCON,
88 .ufcon = UFCON,
89 .clocks = at2440evb_serial_clocks,
90 .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks),
91 },
92};
93
94/* NAND Flash on AT2440EVB board */
95
96static struct mtd_partition at2440evb_default_nand_part[] = {
97 [0] = {
98 .name = "Boot Agent",
99 .size = SZ_256K,
100 .offset = 0,
101 },
102 [1] = {
103 .name = "Kernel",
104 .size = SZ_2M,
105 .offset = SZ_256K,
106 },
107 [2] = {
108 .name = "Root",
109 .offset = SZ_256K + SZ_2M,
110 .size = MTDPART_SIZ_FULL,
111 },
112};
113
114static struct s3c2410_nand_set at2440evb_nand_sets[] = {
115 [0] = {
116 .name = "nand",
117 .nr_chips = 1,
118 .nr_partitions = ARRAY_SIZE(at2440evb_default_nand_part),
119 .partitions = at2440evb_default_nand_part,
120 },
121};
122
123static struct s3c2410_platform_nand at2440evb_nand_info = {
124 .tacls = 25,
125 .twrph0 = 55,
126 .twrph1 = 40,
127 .nr_sets = ARRAY_SIZE(at2440evb_nand_sets),
128 .sets = at2440evb_nand_sets,
129};
130
131/* DM9000AEP 10/100 ethernet controller */
132
133static struct resource at2440evb_dm9k_resource[] = {
134 [0] = {
135 .start = S3C2410_CS3,
136 .end = S3C2410_CS3 + 3,
137 .flags = IORESOURCE_MEM
138 },
139 [1] = {
140 .start = S3C2410_CS3 + 4,
141 .end = S3C2410_CS3 + 7,
142 .flags = IORESOURCE_MEM
143 },
144 [2] = {
145 .start = IRQ_EINT7,
146 .end = IRQ_EINT7,
147 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
148 }
149};
150
151static struct dm9000_plat_data at2440evb_dm9k_pdata = {
152 .flags = (DM9000_PLATF_16BITONLY | DM9000_PLATF_NO_EEPROM),
153};
154
155static struct platform_device at2440evb_device_eth = {
156 .name = "dm9000",
157 .id = -1,
158 .num_resources = ARRAY_SIZE(at2440evb_dm9k_resource),
159 .resource = at2440evb_dm9k_resource,
160 .dev = {
161 .platform_data = &at2440evb_dm9k_pdata,
162 },
163};
164
165static struct platform_device *at2440evb_devices[] __initdata = {
166 &s3c_device_usb,
167 &s3c_device_wdt,
168 &s3c_device_adc,
169 &s3c_device_i2c,
170 &s3c_device_rtc,
171 &s3c_device_nand,
172 &at2440evb_device_eth,
173};
174
175static void __init at2440evb_map_io(void)
176{
177 s3c_device_nand.dev.platform_data = &at2440evb_nand_info;
178
179 s3c24xx_init_io(at2440evb_iodesc, ARRAY_SIZE(at2440evb_iodesc));
180 s3c24xx_init_clocks(16934400);
181 s3c24xx_init_uarts(at2440evb_uartcfgs, ARRAY_SIZE(at2440evb_uartcfgs));
182}
183
184static void __init at2440evb_init(void)
185{
186 platform_add_devices(at2440evb_devices, ARRAY_SIZE(at2440evb_devices));
187}
188
189
190MACHINE_START(AT2440EVB, "AT2440EVB")
191 .phys_io = S3C2410_PA_UART,
192 .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
193 .boot_params = S3C2410_SDRAM_PA + 0x100,
194 .map_io = at2440evb_map_io,
195 .init_machine = at2440evb_init,
196 .init_irq = s3c24xx_init_irq,
197 .timer = &s3c24xx_timer,
198MACHINE_END
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 8a8acdbd072d..af996b0e91e8 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2440/mach-osiris.c 1/* linux/arch/arm/mach-s3c2440/mach-osiris.c
2 * 2 *
3 * Copyright (c) 2005 Simtec Electronics 3 * Copyright (c) 2005,2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/ 4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk> 5 * Ben Dooks <ben@simtec.co.uk>
6 * 6 *
@@ -19,6 +19,7 @@
19#include <linux/sysdev.h> 19#include <linux/sysdev.h>
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/clk.h> 21#include <linux/clk.h>
22#include <linux/i2c.h>
22 23
23#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
24#include <asm/mach/map.h> 25#include <asm/mach/map.h>
@@ -322,6 +323,15 @@ static struct sys_device osiris_pm_sysdev = {
322 .cls = &osiris_pm_sysclass, 323 .cls = &osiris_pm_sysclass,
323}; 324};
324 325
326/* I2C devices fitted. */
327
328static struct i2c_board_info osiris_i2c_devs[] __initdata = {
329 {
330 I2C_BOARD_INFO("tps65011", 0x48),
331 .irq = IRQ_EINT20,
332 },
333};
334
325/* Standard Osiris devices */ 335/* Standard Osiris devices */
326 336
327static struct platform_device *osiris_devices[] __initdata = { 337static struct platform_device *osiris_devices[] __initdata = {
@@ -388,6 +398,9 @@ static void __init osiris_init(void)
388 sysdev_class_register(&osiris_pm_sysclass); 398 sysdev_class_register(&osiris_pm_sysclass);
389 sysdev_register(&osiris_pm_sysdev); 399 sysdev_register(&osiris_pm_sysdev);
390 400
401 i2c_register_board_info(0, osiris_i2c_devs,
402 ARRAY_SIZE(osiris_i2c_devs));
403
391 platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices)); 404 platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
392}; 405};
393 406
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index b42f956738d0..17f064fabdaf 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -81,7 +81,7 @@ static int s3c2443_clkcon_enable_p(struct clk *clk, int enable)
81 else 81 else
82 clkcon &= ~clocks; 82 clkcon &= ~clocks;
83 83
84 __raw_writel(clkcon, S3C2443_HCLKCON); 84 __raw_writel(clkcon, S3C2443_PCLKCON);
85 85
86 return 0; 86 return 0;
87} 87}
@@ -221,7 +221,6 @@ static struct clk clk_mdivclk = {
221 .get_rate = s3c2443_getrate_mdivclk, 221 .get_rate = s3c2443_getrate_mdivclk,
222}; 222};
223 223
224
225static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent) 224static int s3c2443_setparent_msysclk(struct clk *clk, struct clk *parent)
226{ 225{
227 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC); 226 unsigned long clksrc = __raw_readl(S3C2443_CLKSRC);
@@ -249,6 +248,46 @@ static struct clk clk_msysclk = {
249 .set_parent = s3c2443_setparent_msysclk, 248 .set_parent = s3c2443_setparent_msysclk,
250}; 249};
251 250
251/* armdiv
252 *
253 * this clock is sourced from msysclk and can have a number of
254 * divider values applied to it to then be fed into armclk.
255*/
256
257static struct clk clk_armdiv = {
258 .name = "armdiv",
259 .id = -1,
260 .parent = &clk_msysclk,
261};
262
263/* armclk
264 *
265 * this is the clock fed into the ARM core itself, either from
266 * armdiv or from hclk.
267 */
268
269static int s3c2443_setparent_armclk(struct clk *clk, struct clk *parent)
270{
271 unsigned long clkdiv0;
272
273 clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
274
275 if (parent == &clk_armdiv)
276 clkdiv0 &= ~S3C2443_CLKDIV0_DVS;
277 else if (parent == &clk_h)
278 clkdiv0 |= S3C2443_CLKDIV0_DVS;
279 else
280 return -EINVAL;
281
282 __raw_writel(clkdiv0, S3C2443_CLKDIV0);
283 return 0;
284}
285
286static struct clk clk_arm = {
287 .name = "armclk",
288 .id = -1,
289 .set_parent = s3c2443_setparent_armclk,
290};
252 291
253/* esysclk 292/* esysclk
254 * 293 *
@@ -639,6 +678,29 @@ static struct clk clk_display = {
639 .round_rate = s3c2443_roundrate_clksrc256, 678 .round_rate = s3c2443_roundrate_clksrc256,
640}; 679};
641 680
681/* prediv
682 *
683 * this divides the msysclk down to pass to h/p/etc.
684 */
685
686static unsigned long s3c2443_prediv_getrate(struct clk *clk)
687{
688 unsigned long rate = clk_get_rate(clk->parent);
689 unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0);
690
691 clkdiv0 &= S3C2443_CLKDIV0_PREDIV_MASK;
692 clkdiv0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
693
694 return rate / (clkdiv0 + 1);
695}
696
697static struct clk clk_prediv = {
698 .name = "prediv",
699 .id = -1,
700 .parent = &clk_msysclk,
701 .get_rate = s3c2443_prediv_getrate,
702};
703
642/* standard clock definitions */ 704/* standard clock definitions */
643 705
644static struct clk init_clocks_disable[] = { 706static struct clk init_clocks_disable[] = {
@@ -887,6 +949,15 @@ static void __init s3c2443_clk_initparents(void)
887 } 949 }
888 950
889 clk_init_set_parent(&clk_msysclk, parent); 951 clk_init_set_parent(&clk_msysclk, parent);
952
953 /* arm */
954
955 if (__raw_readl(S3C2443_CLKDIV0) & S3C2443_CLKDIV0_DVS)
956 parent = &clk_h;
957 else
958 parent = &clk_armdiv;
959
960 clk_init_set_parent(&clk_arm, parent);
890} 961}
891 962
892/* armdiv divisor table */ 963/* armdiv divisor table */
@@ -909,10 +980,9 @@ static inline unsigned int s3c2443_fclk_div(unsigned long clkcon0)
909 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT]; 980 return armdiv[clkcon0 >> S3C2443_CLKDIV0_ARMDIV_SHIFT];
910} 981}
911 982
912static inline unsigned long s3c2443_get_prediv(unsigned long clkcon0) 983static inline unsigned long s3c2443_get_hdiv(unsigned long clkcon0)
913{ 984{
914 clkcon0 &= S3C2443_CLKDIV0_PREDIV_MASK; 985 clkcon0 &= S3C2443_CLKDIV0_HCLKDIV_MASK;
915 clkcon0 >>= S3C2443_CLKDIV0_PREDIV_SHIFT;
916 986
917 return clkcon0 + 1; 987 return clkcon0 + 1;
918} 988}
@@ -936,6 +1006,9 @@ static struct clk *clks[] __initdata = {
936 &clk_hsspi, 1006 &clk_hsspi,
937 &clk_hsmmc_div, 1007 &clk_hsmmc_div,
938 &clk_hsmmc, 1008 &clk_hsmmc,
1009 &clk_armdiv,
1010 &clk_arm,
1011 &clk_prediv,
939}; 1012};
940 1013
941void __init s3c2443_init_clocks(int xtal) 1014void __init s3c2443_init_clocks(int xtal)
@@ -951,10 +1024,16 @@ void __init s3c2443_init_clocks(int xtal)
951 int ret; 1024 int ret;
952 int ptr; 1025 int ptr;
953 1026
1027 /* s3c2443 parents h and p clocks from prediv */
1028 clk_h.parent = &clk_prediv;
1029 clk_p.parent = &clk_prediv;
1030
954 pll = s3c2443_get_mpll(mpllcon, xtal); 1031 pll = s3c2443_get_mpll(mpllcon, xtal);
1032 clk_msysclk.rate = pll;
955 1033
956 fclk = pll / s3c2443_fclk_div(clkdiv0); 1034 fclk = pll / s3c2443_fclk_div(clkdiv0);
957 hclk = fclk / s3c2443_get_prediv(clkdiv0); 1035 hclk = s3c2443_prediv_getrate(&clk_prediv);
1036 hclk = hclk / s3c2443_get_hdiv(clkdiv0);
958 hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1); 1037 hclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_HCLK) ? 2 : 1);
959 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); 1038 pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1);
960 1039
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 33ed048502a3..a2c8b006d710 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -180,8 +180,8 @@ config CPU_ARM925T
180# ARM926T 180# ARM926T
181config CPU_ARM926T 181config CPU_ARM926T
182 bool "Support ARM926T processor" 182 bool "Support ARM926T processor"
183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 183 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI 184 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008 || ARCH_NETX || CPU_S3C2412 || ARCH_AT91SAM9260 || ARCH_AT91SAM9261 || ARCH_AT91SAM9263 || ARCH_AT91SAM9RL || ARCH_AT91SAM9G20 || ARCH_AT91CAP9 || ARCH_NS9XXX || ARCH_DAVINCI
185 select CPU_32v5 185 select CPU_32v5
186 select CPU_ABRT_EV5TJ 186 select CPU_ABRT_EV5TJ
187 select CPU_PABRT_NOIFAR 187 select CPU_PABRT_NOIFAR
@@ -365,7 +365,7 @@ config CPU_XSC3
365# Feroceon 365# Feroceon
366config CPU_FEROCEON 366config CPU_FEROCEON
367 bool 367 bool
368 depends on ARCH_ORION5X 368 depends on ARCH_ORION5X || ARCH_LOKI || ARCH_KIRKWOOD || ARCH_MV78XX0
369 default y 369 default y
370 select CPU_32v5 370 select CPU_32v5
371 select CPU_ABRT_EV5T 371 select CPU_ABRT_EV5T
@@ -373,7 +373,7 @@ config CPU_FEROCEON
373 select CPU_CACHE_VIVT 373 select CPU_CACHE_VIVT
374 select CPU_CP15_MMU 374 select CPU_CP15_MMU
375 select CPU_COPY_FEROCEON if MMU 375 select CPU_COPY_FEROCEON if MMU
376 select CPU_TLB_V4WBI if MMU 376 select CPU_TLB_FEROCEON if MMU
377 377
378config CPU_FEROCEON_OLD_ID 378config CPU_FEROCEON_OLD_ID
379 bool "Accept early Feroceon cores with an ARM926 ID" 379 bool "Accept early Feroceon cores with an ARM926 ID"
@@ -551,6 +551,11 @@ config CPU_TLB_V4WBI
551 ARM Architecture Version 4 TLB with writeback cache and invalidate 551 ARM Architecture Version 4 TLB with writeback cache and invalidate
552 instruction cache entry. 552 instruction cache entry.
553 553
554config CPU_TLB_FEROCEON
555 bool
556 help
557 Feroceon TLB (v4wbi with non-outer-cachable page table walks).
558
554config CPU_TLB_V6 559config CPU_TLB_V6
555 bool 560 bool
556 561
@@ -709,6 +714,14 @@ config OUTER_CACHE
709 bool 714 bool
710 default n 715 default n
711 716
717config CACHE_FEROCEON_L2
718 bool "Enable the Feroceon L2 cache controller"
719 depends on ARCH_KIRKWOOD || ARCH_MV78XX0
720 default y
721 select OUTER_CACHE
722 help
723 This option enables the Feroceon L2 cache controller.
724
712config CACHE_L2X0 725config CACHE_L2X0
713 bool "Enable the L2x0 outer cache controller" 726 bool "Enable the L2x0 outer cache controller"
714 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 727 depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 32b2d2d213a6..f64b92557b11 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -46,6 +46,7 @@ obj-$(CONFIG_CPU_TLB_V3) += tlb-v3.o
46obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o 46obj-$(CONFIG_CPU_TLB_V4WT) += tlb-v4.o
47obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o 47obj-$(CONFIG_CPU_TLB_V4WB) += tlb-v4wb.o
48obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o 48obj-$(CONFIG_CPU_TLB_V4WBI) += tlb-v4wbi.o
49obj-$(CONFIG_CPU_TLB_FEROCEON) += tlb-v4wbi.o # reuse v4wbi TLB functions
49obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o 50obj-$(CONFIG_CPU_TLB_V6) += tlb-v6.o
50obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o 51obj-$(CONFIG_CPU_TLB_V7) += tlb-v7.o
51 52
@@ -73,4 +74,5 @@ obj-$(CONFIG_CPU_FEROCEON) += proc-feroceon.o
73obj-$(CONFIG_CPU_V6) += proc-v6.o 74obj-$(CONFIG_CPU_V6) += proc-v6.o
74obj-$(CONFIG_CPU_V7) += proc-v7.o 75obj-$(CONFIG_CPU_V7) += proc-v7.o
75 76
77obj-$(CONFIG_CACHE_FEROCEON_L2) += cache-feroceon-l2.o
76obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o 78obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
diff --git a/arch/arm/mm/cache-feroceon-l2.c b/arch/arm/mm/cache-feroceon-l2.c
new file mode 100644
index 000000000000..20eec4ba173f
--- /dev/null
+++ b/arch/arm/mm/cache-feroceon-l2.c
@@ -0,0 +1,318 @@
1/*
2 * arch/arm/mm/cache-feroceon-l2.c - Feroceon L2 cache controller support
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 *
10 * References:
11 * - Unified Layer 2 Cache for Feroceon CPU Cores,
12 * Document ID MV-S104858-00, Rev. A, October 23 2007.
13 */
14
15#include <linux/init.h>
16#include <asm/cacheflush.h>
17#include <asm/plat-orion/cache-feroceon-l2.h>
18
19
20/*
21 * Low-level cache maintenance operations.
22 *
23 * As well as the regular 'clean/invalidate/flush L2 cache line by
24 * MVA' instructions, the Feroceon L2 cache controller also features
25 * 'clean/invalidate L2 range by MVA' operations.
26 *
27 * Cache range operations are initiated by writing the start and
28 * end addresses to successive cp15 registers, and process every
29 * cache line whose first byte address lies in the inclusive range
30 * [start:end].
31 *
32 * The cache range operations stall the CPU pipeline until completion.
33 *
34 * The range operations require two successive cp15 writes, in
35 * between which we don't want to be preempted.
36 */
37static inline void l2_clean_pa(unsigned long addr)
38{
39 __asm__("mcr p15, 1, %0, c15, c9, 3" : : "r" (addr));
40}
41
42static inline void l2_clean_mva_range(unsigned long start, unsigned long end)
43{
44 unsigned long flags;
45
46 /*
47 * Make sure 'start' and 'end' reference the same page, as
48 * L2 is PIPT and range operations only do a TLB lookup on
49 * the start address.
50 */
51 BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
52
53 raw_local_irq_save(flags);
54 __asm__("mcr p15, 1, %0, c15, c9, 4" : : "r" (start));
55 __asm__("mcr p15, 1, %0, c15, c9, 5" : : "r" (end));
56 raw_local_irq_restore(flags);
57}
58
59static inline void l2_clean_pa_range(unsigned long start, unsigned long end)
60{
61 l2_clean_mva_range(__phys_to_virt(start), __phys_to_virt(end));
62}
63
64static inline void l2_clean_inv_pa(unsigned long addr)
65{
66 __asm__("mcr p15, 1, %0, c15, c10, 3" : : "r" (addr));
67}
68
69static inline void l2_inv_pa(unsigned long addr)
70{
71 __asm__("mcr p15, 1, %0, c15, c11, 3" : : "r" (addr));
72}
73
74static inline void l2_inv_mva_range(unsigned long start, unsigned long end)
75{
76 unsigned long flags;
77
78 /*
79 * Make sure 'start' and 'end' reference the same page, as
80 * L2 is PIPT and range operations only do a TLB lookup on
81 * the start address.
82 */
83 BUG_ON((start ^ end) & ~(PAGE_SIZE - 1));
84
85 raw_local_irq_save(flags);
86 __asm__("mcr p15, 1, %0, c15, c11, 4" : : "r" (start));
87 __asm__("mcr p15, 1, %0, c15, c11, 5" : : "r" (end));
88 raw_local_irq_restore(flags);
89}
90
91static inline void l2_inv_pa_range(unsigned long start, unsigned long end)
92{
93 l2_inv_mva_range(__phys_to_virt(start), __phys_to_virt(end));
94}
95
96
97/*
98 * Linux primitives.
99 *
100 * Note that the end addresses passed to Linux primitives are
101 * noninclusive, while the hardware cache range operations use
102 * inclusive start and end addresses.
103 */
104#define CACHE_LINE_SIZE 32
105#define MAX_RANGE_SIZE 1024
106
107static int l2_wt_override;
108
109static unsigned long calc_range_end(unsigned long start, unsigned long end)
110{
111 unsigned long range_end;
112
113 BUG_ON(start & (CACHE_LINE_SIZE - 1));
114 BUG_ON(end & (CACHE_LINE_SIZE - 1));
115
116 /*
117 * Try to process all cache lines between 'start' and 'end'.
118 */
119 range_end = end;
120
121 /*
122 * Limit the number of cache lines processed at once,
123 * since cache range operations stall the CPU pipeline
124 * until completion.
125 */
126 if (range_end > start + MAX_RANGE_SIZE)
127 range_end = start + MAX_RANGE_SIZE;
128
129 /*
130 * Cache range operations can't straddle a page boundary.
131 */
132 if (range_end > (start | (PAGE_SIZE - 1)) + 1)
133 range_end = (start | (PAGE_SIZE - 1)) + 1;
134
135 return range_end;
136}
137
138static void feroceon_l2_inv_range(unsigned long start, unsigned long end)
139{
140 /*
141 * Clean and invalidate partial first cache line.
142 */
143 if (start & (CACHE_LINE_SIZE - 1)) {
144 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1));
145 start = (start | (CACHE_LINE_SIZE - 1)) + 1;
146 }
147
148 /*
149 * Clean and invalidate partial last cache line.
150 */
151 if (end & (CACHE_LINE_SIZE - 1)) {
152 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1));
153 end &= ~(CACHE_LINE_SIZE - 1);
154 }
155
156 /*
157 * Invalidate all full cache lines between 'start' and 'end'.
158 */
159 while (start != end) {
160 unsigned long range_end = calc_range_end(start, end);
161 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
162 start = range_end;
163 }
164
165 dsb();
166}
167
168static void feroceon_l2_clean_range(unsigned long start, unsigned long end)
169{
170 /*
171 * If L2 is forced to WT, the L2 will always be clean and we
172 * don't need to do anything here.
173 */
174 if (!l2_wt_override) {
175 start &= ~(CACHE_LINE_SIZE - 1);
176 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
177 while (start != end) {
178 unsigned long range_end = calc_range_end(start, end);
179 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
180 start = range_end;
181 }
182 }
183
184 dsb();
185}
186
187static void feroceon_l2_flush_range(unsigned long start, unsigned long end)
188{
189 start &= ~(CACHE_LINE_SIZE - 1);
190 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1);
191 while (start != end) {
192 unsigned long range_end = calc_range_end(start, end);
193 if (!l2_wt_override)
194 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE);
195 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE);
196 start = range_end;
197 }
198
199 dsb();
200}
201
202
203/*
204 * Routines to disable and re-enable the D-cache and I-cache at run
205 * time. These are necessary because the L2 cache can only be enabled
206 * or disabled while the L1 Dcache and Icache are both disabled.
207 */
208static void __init invalidate_and_disable_dcache(void)
209{
210 u32 cr;
211
212 cr = get_cr();
213 if (cr & CR_C) {
214 unsigned long flags;
215
216 raw_local_irq_save(flags);
217 flush_cache_all();
218 set_cr(cr & ~CR_C);
219 raw_local_irq_restore(flags);
220 }
221}
222
223static void __init enable_dcache(void)
224{
225 u32 cr;
226
227 cr = get_cr();
228 if (!(cr & CR_C))
229 set_cr(cr | CR_C);
230}
231
232static void __init __invalidate_icache(void)
233{
234 int dummy;
235
236 __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 0\n" : "=r" (dummy));
237}
238
239static void __init invalidate_and_disable_icache(void)
240{
241 u32 cr;
242
243 cr = get_cr();
244 if (cr & CR_I) {
245 set_cr(cr & ~CR_I);
246 __invalidate_icache();
247 }
248}
249
250static void __init enable_icache(void)
251{
252 u32 cr;
253
254 cr = get_cr();
255 if (!(cr & CR_I))
256 set_cr(cr | CR_I);
257}
258
259static inline u32 read_extra_features(void)
260{
261 u32 u;
262
263 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (u));
264
265 return u;
266}
267
268static inline void write_extra_features(u32 u)
269{
270 __asm__("mcr p15, 1, %0, c15, c1, 0" : : "r" (u));
271}
272
273static void __init disable_l2_prefetch(void)
274{
275 u32 u;
276
277 /*
278 * Read the CPU Extra Features register and verify that the
279 * Disable L2 Prefetch bit is set.
280 */
281 u = read_extra_features();
282 if (!(u & 0x01000000)) {
283 printk(KERN_INFO "Feroceon L2: Disabling L2 prefetch.\n");
284 write_extra_features(u | 0x01000000);
285 }
286}
287
288static void __init enable_l2(void)
289{
290 u32 u;
291
292 u = read_extra_features();
293 if (!(u & 0x00400000)) {
294 printk(KERN_INFO "Feroceon L2: Enabling L2\n");
295
296 invalidate_and_disable_dcache();
297 invalidate_and_disable_icache();
298 write_extra_features(u | 0x00400000);
299 enable_icache();
300 enable_dcache();
301 }
302}
303
304void __init feroceon_l2_init(int __l2_wt_override)
305{
306 l2_wt_override = __l2_wt_override;
307
308 disable_l2_prefetch();
309
310 outer_cache.inv_range = feroceon_l2_inv_range;
311 outer_cache.clean_range = feroceon_l2_clean_range;
312 outer_cache.flush_range = feroceon_l2_flush_range;
313
314 enable_l2();
315
316 printk(KERN_INFO "Feroceon L2: Cache support initialised%s.\n",
317 l2_wt_override ? ", in WT override mode" : "");
318}
diff --git a/arch/arm/mm/fault-armv.c b/arch/arm/mm/fault-armv.c
index 44558d5f9313..fbfa26058442 100644
--- a/arch/arm/mm/fault-armv.c
+++ b/arch/arm/mm/fault-armv.c
@@ -144,13 +144,17 @@ void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte)
144 page = pfn_to_page(pfn); 144 page = pfn_to_page(pfn);
145 mapping = page_mapping(page); 145 mapping = page_mapping(page);
146 if (mapping) { 146 if (mapping) {
147#ifndef CONFIG_SMP
147 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags); 148 int dirty = test_and_clear_bit(PG_dcache_dirty, &page->flags);
148 149
149 if (dirty) 150 if (dirty)
150 __flush_dcache_page(mapping, page); 151 __flush_dcache_page(mapping, page);
152#endif
151 153
152 if (cache_is_vivt()) 154 if (cache_is_vivt())
153 make_coherent(mapping, vma, addr, pfn); 155 make_coherent(mapping, vma, addr, pfn);
156 else if (vma->vm_flags & VM_EXEC)
157 __flush_icache_all();
154 } 158 }
155} 159}
156 160
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 9df507d36e0b..029ee65fda2b 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -199,6 +199,8 @@ void flush_dcache_page(struct page *page)
199 __flush_dcache_page(mapping, page); 199 __flush_dcache_page(mapping, page);
200 if (mapping && cache_is_vivt()) 200 if (mapping && cache_is_vivt())
201 __flush_dcache_aliases(mapping, page); 201 __flush_dcache_aliases(mapping, page);
202 else if (mapping)
203 __flush_icache_all();
202 } 204 }
203} 205}
204EXPORT_SYMBOL(flush_dcache_page); 206EXPORT_SYMBOL(flush_dcache_page);
diff --git a/arch/arm/mm/proc-feroceon.S b/arch/arm/mm/proc-feroceon.S
index a02c1712b52d..f2e5884c513a 100644
--- a/arch/arm/mm/proc-feroceon.S
+++ b/arch/arm/mm/proc-feroceon.S
@@ -44,11 +44,31 @@
44 */ 44 */
45#define CACHE_DLINESIZE 32 45#define CACHE_DLINESIZE 32
46 46
47 .bss
48 .align 3
49__cache_params_loc:
50 .space 8
51
47 .text 52 .text
53__cache_params:
54 .word __cache_params_loc
55
48/* 56/*
49 * cpu_feroceon_proc_init() 57 * cpu_feroceon_proc_init()
50 */ 58 */
51ENTRY(cpu_feroceon_proc_init) 59ENTRY(cpu_feroceon_proc_init)
60 mrc p15, 0, r0, c0, c0, 1 @ read cache type register
61 ldr r1, __cache_params
62 mov r2, #(16 << 5)
63 tst r0, #(1 << 16) @ get way
64 mov r0, r0, lsr #18 @ get cache size order
65 movne r3, #((4 - 1) << 30) @ 4-way
66 and r0, r0, #0xf
67 moveq r3, #0 @ 1-way
68 mov r2, r2, lsl r0 @ actual cache size
69 movne r2, r2, lsr #2 @ turned into # of sets
70 sub r2, r2, #(1 << 5)
71 stmia r1, {r2, r3}
52 mov pc, lr 72 mov pc, lr
53 73
54/* 74/*
@@ -59,6 +79,13 @@ ENTRY(cpu_feroceon_proc_fin)
59 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE 79 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
60 msr cpsr_c, ip 80 msr cpsr_c, ip
61 bl feroceon_flush_kern_cache_all 81 bl feroceon_flush_kern_cache_all
82
83#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
84 mov r0, #0
85 mcr p15, 1, r0, c15, c9, 0 @ clean L2
86 mcr p15, 0, r0, c7, c10, 4 @ drain WB
87#endif
88
62 mrc p15, 0, r0, c1, c0, 0 @ ctrl register 89 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
63 bic r0, r0, #0x1000 @ ...i............ 90 bic r0, r0, #0x1000 @ ...i............
64 bic r0, r0, #0x000e @ ............wca. 91 bic r0, r0, #0x000e @ ............wca.
@@ -117,11 +144,19 @@ ENTRY(feroceon_flush_user_cache_all)
117 */ 144 */
118ENTRY(feroceon_flush_kern_cache_all) 145ENTRY(feroceon_flush_kern_cache_all)
119 mov r2, #VM_EXEC 146 mov r2, #VM_EXEC
120 mov ip, #0 147
121__flush_whole_cache: 148__flush_whole_cache:
1221: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 149 ldr r1, __cache_params
123 bne 1b 150 ldmia r1, {r1, r3}
1511: orr ip, r1, r3
1522: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
153 subs ip, ip, #(1 << 30) @ next way
154 bcs 2b
155 subs r1, r1, #(1 << 5) @ next set
156 bcs 1b
157
124 tst r2, #VM_EXEC 158 tst r2, #VM_EXEC
159 mov ip, #0
125 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache 160 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
126 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 161 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
127 mov pc, lr 162 mov pc, lr
@@ -138,7 +173,6 @@ __flush_whole_cache:
138 */ 173 */
139 .align 5 174 .align 5
140ENTRY(feroceon_flush_user_cache_range) 175ENTRY(feroceon_flush_user_cache_range)
141 mov ip, #0
142 sub r3, r1, r0 @ calculate total size 176 sub r3, r1, r0 @ calculate total size
143 cmp r3, #CACHE_DLIMIT 177 cmp r3, #CACHE_DLIMIT
144 bgt __flush_whole_cache 178 bgt __flush_whole_cache
@@ -152,6 +186,7 @@ ENTRY(feroceon_flush_user_cache_range)
152 cmp r0, r1 186 cmp r0, r1
153 blo 1b 187 blo 1b
154 tst r2, #VM_EXEC 188 tst r2, #VM_EXEC
189 mov ip, #0
155 mcrne p15, 0, ip, c7, c10, 4 @ drain WB 190 mcrne p15, 0, ip, c7, c10, 4 @ drain WB
156 mov pc, lr 191 mov pc, lr
157 192
@@ -209,6 +244,20 @@ ENTRY(feroceon_flush_kern_dcache_page)
209 mcr p15, 0, r0, c7, c10, 4 @ drain WB 244 mcr p15, 0, r0, c7, c10, 4 @ drain WB
210 mov pc, lr 245 mov pc, lr
211 246
247 .align 5
248ENTRY(feroceon_range_flush_kern_dcache_page)
249 mrs r2, cpsr
250 add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
251 orr r3, r2, #PSR_I_BIT
252 msr cpsr_c, r3 @ disable interrupts
253 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
254 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
255 msr cpsr_c, r2 @ restore interrupts
256 mov r0, #0
257 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
258 mcr p15, 0, r0, c7, c10, 4 @ drain WB
259 mov pc, lr
260
212/* 261/*
213 * dma_inv_range(start, end) 262 * dma_inv_range(start, end)
214 * 263 *
@@ -225,10 +274,10 @@ ENTRY(feroceon_flush_kern_dcache_page)
225 .align 5 274 .align 5
226ENTRY(feroceon_dma_inv_range) 275ENTRY(feroceon_dma_inv_range)
227 tst r0, #CACHE_DLINESIZE - 1 276 tst r0, #CACHE_DLINESIZE - 1
277 bic r0, r0, #CACHE_DLINESIZE - 1
228 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry 278 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
229 tst r1, #CACHE_DLINESIZE - 1 279 tst r1, #CACHE_DLINESIZE - 1
230 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry 280 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
231 bic r0, r0, #CACHE_DLINESIZE - 1
2321: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry 2811: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
233 add r0, r0, #CACHE_DLINESIZE 282 add r0, r0, #CACHE_DLINESIZE
234 cmp r0, r1 283 cmp r0, r1
@@ -236,6 +285,22 @@ ENTRY(feroceon_dma_inv_range)
236 mcr p15, 0, r0, c7, c10, 4 @ drain WB 285 mcr p15, 0, r0, c7, c10, 4 @ drain WB
237 mov pc, lr 286 mov pc, lr
238 287
288 .align 5
289ENTRY(feroceon_range_dma_inv_range)
290 mrs r2, cpsr
291 tst r0, #CACHE_DLINESIZE - 1
292 mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
293 tst r1, #CACHE_DLINESIZE - 1
294 mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
295 cmp r1, r0
296 subne r1, r1, #1 @ top address is inclusive
297 orr r3, r2, #PSR_I_BIT
298 msr cpsr_c, r3 @ disable interrupts
299 mcr p15, 5, r0, c15, c14, 0 @ D inv range start
300 mcr p15, 5, r1, c15, c14, 1 @ D inv range top
301 msr cpsr_c, r2 @ restore interrupts
302 mov pc, lr
303
239/* 304/*
240 * dma_clean_range(start, end) 305 * dma_clean_range(start, end)
241 * 306 *
@@ -256,6 +321,19 @@ ENTRY(feroceon_dma_clean_range)
256 mcr p15, 0, r0, c7, c10, 4 @ drain WB 321 mcr p15, 0, r0, c7, c10, 4 @ drain WB
257 mov pc, lr 322 mov pc, lr
258 323
324 .align 5
325ENTRY(feroceon_range_dma_clean_range)
326 mrs r2, cpsr
327 cmp r1, r0
328 subne r1, r1, #1 @ top address is inclusive
329 orr r3, r2, #PSR_I_BIT
330 msr cpsr_c, r3 @ disable interrupts
331 mcr p15, 5, r0, c15, c13, 0 @ D clean range start
332 mcr p15, 5, r1, c15, c13, 1 @ D clean range top
333 msr cpsr_c, r2 @ restore interrupts
334 mcr p15, 0, r0, c7, c10, 4 @ drain WB
335 mov pc, lr
336
259/* 337/*
260 * dma_flush_range(start, end) 338 * dma_flush_range(start, end)
261 * 339 *
@@ -274,6 +352,19 @@ ENTRY(feroceon_dma_flush_range)
274 mcr p15, 0, r0, c7, c10, 4 @ drain WB 352 mcr p15, 0, r0, c7, c10, 4 @ drain WB
275 mov pc, lr 353 mov pc, lr
276 354
355 .align 5
356ENTRY(feroceon_range_dma_flush_range)
357 mrs r2, cpsr
358 cmp r1, r0
359 subne r1, r1, #1 @ top address is inclusive
360 orr r3, r2, #PSR_I_BIT
361 msr cpsr_c, r3 @ disable interrupts
362 mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
363 mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
364 msr cpsr_c, r2 @ restore interrupts
365 mcr p15, 0, r0, c7, c10, 4 @ drain WB
366 mov pc, lr
367
277ENTRY(feroceon_cache_fns) 368ENTRY(feroceon_cache_fns)
278 .long feroceon_flush_kern_cache_all 369 .long feroceon_flush_kern_cache_all
279 .long feroceon_flush_user_cache_all 370 .long feroceon_flush_user_cache_all
@@ -285,12 +376,33 @@ ENTRY(feroceon_cache_fns)
285 .long feroceon_dma_clean_range 376 .long feroceon_dma_clean_range
286 .long feroceon_dma_flush_range 377 .long feroceon_dma_flush_range
287 378
379ENTRY(feroceon_range_cache_fns)
380 .long feroceon_flush_kern_cache_all
381 .long feroceon_flush_user_cache_all
382 .long feroceon_flush_user_cache_range
383 .long feroceon_coherent_kern_range
384 .long feroceon_coherent_user_range
385 .long feroceon_range_flush_kern_dcache_page
386 .long feroceon_range_dma_inv_range
387 .long feroceon_range_dma_clean_range
388 .long feroceon_range_dma_flush_range
389
288 .align 5 390 .align 5
289ENTRY(cpu_feroceon_dcache_clean_area) 391ENTRY(cpu_feroceon_dcache_clean_area)
392#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
393 mov r2, r0
394 mov r3, r1
395#endif
2901: mcr p15, 0, r0, c7, c10, 1 @ clean D entry 3961: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
291 add r0, r0, #CACHE_DLINESIZE 397 add r0, r0, #CACHE_DLINESIZE
292 subs r1, r1, #CACHE_DLINESIZE 398 subs r1, r1, #CACHE_DLINESIZE
293 bhi 1b 399 bhi 1b
400#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
4011: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
402 add r2, r2, #CACHE_DLINESIZE
403 subs r3, r3, #CACHE_DLINESIZE
404 bhi 1b
405#endif
294 mcr p15, 0, r0, c7, c10, 4 @ drain WB 406 mcr p15, 0, r0, c7, c10, 4 @ drain WB
295 mov pc, lr 407 mov pc, lr
296 408
@@ -306,16 +418,25 @@ ENTRY(cpu_feroceon_dcache_clean_area)
306 .align 5 418 .align 5
307ENTRY(cpu_feroceon_switch_mm) 419ENTRY(cpu_feroceon_switch_mm)
308#ifdef CONFIG_MMU 420#ifdef CONFIG_MMU
309 mov ip, #0 421 /*
310@ && 'Clean & Invalidate whole DCache' 422 * Note: we wish to call __flush_whole_cache but we need to preserve
3111: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate 423 * lr to do so. The only way without touching main memory is to
312 bne 1b 424 * use r2 which is normally used to test the VM_EXEC flag, and
313 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 425 * compensate locally for the skipped ops if it is not set.
314 mcr p15, 0, ip, c7, c10, 4 @ drain WB 426 */
427 mov r2, lr @ abuse r2 to preserve lr
428 bl __flush_whole_cache
429 @ if r2 contains the VM_EXEC bit then the next 2 ops are done already
430 tst r2, #VM_EXEC
431 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
432 mcreq p15, 0, ip, c7, c10, 4 @ drain WB
433
315 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer 434 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
316 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 435 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
317#endif 436 mov pc, r2
437#else
318 mov pc, lr 438 mov pc, lr
439#endif
319 440
320/* 441/*
321 * cpu_feroceon_set_pte_ext(ptep, pte, ext) 442 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
@@ -345,6 +466,9 @@ ENTRY(cpu_feroceon_set_pte_ext)
345 str r2, [r0] @ hardware version 466 str r2, [r0] @ hardware version
346 mov r0, r0 467 mov r0, r0
347 mcr p15, 0, r0, c7, c10, 1 @ clean D entry 468 mcr p15, 0, r0, c7, c10, 1 @ clean D entry
469#if defined(CONFIG_CACHE_FEROCEON_L2) && !defined(CONFIG_L2_CACHE_WRITETHROUGH)
470 mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
471#endif
348 mcr p15, 0, r0, c7, c10, 4 @ drain WB 472 mcr p15, 0, r0, c7, c10, 4 @ drain WB
349#endif 473#endif
350 mov pc, lr 474 mov pc, lr
@@ -369,14 +493,15 @@ __feroceon_setup:
369 .size __feroceon_setup, . - __feroceon_setup 493 .size __feroceon_setup, . - __feroceon_setup
370 494
371 /* 495 /*
372 * R 496 * B
373 * .RVI ZFRS BLDP WCAM 497 * R P
374 * .011 0001 ..11 0101 498 * .RVI UFRS BLDP WCAM
499 * .011 .001 ..11 0101
375 * 500 *
376 */ 501 */
377 .type feroceon_crval, #object 502 .type feroceon_crval, #object
378feroceon_crval: 503feroceon_crval:
379 crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134 504 crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
380 505
381 __INITDATA 506 __INITDATA
382 507
@@ -414,6 +539,21 @@ cpu_feroceon_name:
414 .asciz "Feroceon" 539 .asciz "Feroceon"
415 .size cpu_feroceon_name, . - cpu_feroceon_name 540 .size cpu_feroceon_name, . - cpu_feroceon_name
416 541
542 .type cpu_88fr531_name, #object
543cpu_88fr531_name:
544 .asciz "Feroceon 88FR531-vd"
545 .size cpu_88fr531_name, . - cpu_88fr531_name
546
547 .type cpu_88fr571_name, #object
548cpu_88fr571_name:
549 .asciz "Feroceon 88FR571-vd"
550 .size cpu_88fr571_name, . - cpu_88fr571_name
551
552 .type cpu_88fr131_name, #object
553cpu_88fr131_name:
554 .asciz "Feroceon 88FR131"
555 .size cpu_88fr131_name, . - cpu_88fr131_name
556
417 .align 557 .align
418 558
419 .section ".proc.info.init", #alloc, #execinstr 559 .section ".proc.info.init", #alloc, #execinstr
@@ -421,15 +561,15 @@ cpu_feroceon_name:
421#ifdef CONFIG_CPU_FEROCEON_OLD_ID 561#ifdef CONFIG_CPU_FEROCEON_OLD_ID
422 .type __feroceon_old_id_proc_info,#object 562 .type __feroceon_old_id_proc_info,#object
423__feroceon_old_id_proc_info: 563__feroceon_old_id_proc_info:
424 .long 0x41069260 564 .long 0x41009260
425 .long 0xfffffff0 565 .long 0xff00fff0
426 .long PMD_TYPE_SECT | \ 566 .long PMD_TYPE_SECT | \
427 PMD_SECT_BUFFERABLE | \ 567 PMD_SECT_BUFFERABLE | \
428 PMD_SECT_CACHEABLE | \ 568 PMD_SECT_CACHEABLE | \
429 PMD_BIT4 | \ 569 PMD_BIT4 | \
430 PMD_SECT_AP_WRITE | \ 570 PMD_SECT_AP_WRITE | \
431 PMD_SECT_AP_READ 571 PMD_SECT_AP_READ
432 .long PMD_TYPE_SECT | \ 572 .long PMD_TYPE_SECT | \
433 PMD_BIT4 | \ 573 PMD_BIT4 | \
434 PMD_SECT_AP_WRITE | \ 574 PMD_SECT_AP_WRITE | \
435 PMD_SECT_AP_READ 575 PMD_SECT_AP_READ
@@ -445,17 +585,17 @@ __feroceon_old_id_proc_info:
445 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info 585 .size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
446#endif 586#endif
447 587
448 .type __feroceon_proc_info,#object 588 .type __88fr531_proc_info,#object
449__feroceon_proc_info: 589__88fr531_proc_info:
450 .long 0x56055310 590 .long 0x56055310
451 .long 0xfffffff0 591 .long 0xfffffff0
452 .long PMD_TYPE_SECT | \ 592 .long PMD_TYPE_SECT | \
453 PMD_SECT_BUFFERABLE | \ 593 PMD_SECT_BUFFERABLE | \
454 PMD_SECT_CACHEABLE | \ 594 PMD_SECT_CACHEABLE | \
455 PMD_BIT4 | \ 595 PMD_BIT4 | \
456 PMD_SECT_AP_WRITE | \ 596 PMD_SECT_AP_WRITE | \
457 PMD_SECT_AP_READ 597 PMD_SECT_AP_READ
458 .long PMD_TYPE_SECT | \ 598 .long PMD_TYPE_SECT | \
459 PMD_BIT4 | \ 599 PMD_BIT4 | \
460 PMD_SECT_AP_WRITE | \ 600 PMD_SECT_AP_WRITE | \
461 PMD_SECT_AP_READ 601 PMD_SECT_AP_READ
@@ -463,9 +603,59 @@ __feroceon_proc_info:
463 .long cpu_arch_name 603 .long cpu_arch_name
464 .long cpu_elf_name 604 .long cpu_elf_name
465 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP 605 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
466 .long cpu_feroceon_name 606 .long cpu_88fr531_name
467 .long feroceon_processor_functions 607 .long feroceon_processor_functions
468 .long v4wbi_tlb_fns 608 .long v4wbi_tlb_fns
469 .long feroceon_user_fns 609 .long feroceon_user_fns
470 .long feroceon_cache_fns 610 .long feroceon_cache_fns
471 .size __feroceon_proc_info, . - __feroceon_proc_info 611 .size __88fr531_proc_info, . - __88fr531_proc_info
612
613 .type __88fr571_proc_info,#object
614__88fr571_proc_info:
615 .long 0x56155710
616 .long 0xfffffff0
617 .long PMD_TYPE_SECT | \
618 PMD_SECT_BUFFERABLE | \
619 PMD_SECT_CACHEABLE | \
620 PMD_BIT4 | \
621 PMD_SECT_AP_WRITE | \
622 PMD_SECT_AP_READ
623 .long PMD_TYPE_SECT | \
624 PMD_BIT4 | \
625 PMD_SECT_AP_WRITE | \
626 PMD_SECT_AP_READ
627 b __feroceon_setup
628 .long cpu_arch_name
629 .long cpu_elf_name
630 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
631 .long cpu_88fr571_name
632 .long feroceon_processor_functions
633 .long v4wbi_tlb_fns
634 .long feroceon_user_fns
635 .long feroceon_range_cache_fns
636 .size __88fr571_proc_info, . - __88fr571_proc_info
637
638 .type __88fr131_proc_info,#object
639__88fr131_proc_info:
640 .long 0x56251310
641 .long 0xfffffff0
642 .long PMD_TYPE_SECT | \
643 PMD_SECT_BUFFERABLE | \
644 PMD_SECT_CACHEABLE | \
645 PMD_BIT4 | \
646 PMD_SECT_AP_WRITE | \
647 PMD_SECT_AP_READ
648 .long PMD_TYPE_SECT | \
649 PMD_BIT4 | \
650 PMD_SECT_AP_WRITE | \
651 PMD_SECT_AP_READ
652 b __feroceon_setup
653 .long cpu_arch_name
654 .long cpu_elf_name
655 .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
656 .long cpu_88fr131_name
657 .long feroceon_processor_functions
658 .long v4wbi_tlb_fns
659 .long feroceon_user_fns
660 .long feroceon_range_cache_fns
661 .size __88fr131_proc_info, . - __88fr131_proc_info
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index bc639a30d6d1..2c4051cc79a1 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := common.o sram.o sram-fn.o clock.o devices.o dma.o mux.o gpio.o \ 6obj-y := common.o sram.o clock.o devices.o dma.o mux.o gpio.o \
7 usb.o fb.o 7 usb.o fb.o
8obj-m := 8obj-m :=
9obj-n := 9obj-n :=
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 2db5580048d8..c2e741de0203 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/clock.c 2 * linux/arch/arm/plat-omap/clock.c
3 * 3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation 4 * Copyright (C) 2004 - 2008 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> 5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * 6 *
7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> 7 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
@@ -22,6 +22,7 @@
22#include <linux/mutex.h> 22#include <linux/mutex.h>
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/cpufreq.h> 24#include <linux/cpufreq.h>
25#include <linux/debugfs.h>
25 26
26#include <asm/io.h> 27#include <asm/io.h>
27 28
@@ -33,41 +34,6 @@ static DEFINE_SPINLOCK(clockfw_lock);
33 34
34static struct clk_functions *arch_clock; 35static struct clk_functions *arch_clock;
35 36
36#ifdef CONFIG_PM_DEBUG
37
38static void print_parents(struct clk *clk)
39{
40 struct clk *p;
41 int printed = 0;
42
43 list_for_each_entry(p, &clocks, node) {
44 if (p->parent == clk && p->usecount) {
45 if (!clk->usecount && !printed) {
46 printk("MISMATCH: %s\n", clk->name);
47 printed = 1;
48 }
49 printk("\t%-15s\n", p->name);
50 }
51 }
52}
53
54void clk_print_usecounts(void)
55{
56 unsigned long flags;
57 struct clk *p;
58
59 spin_lock_irqsave(&clockfw_lock, flags);
60 list_for_each_entry(p, &clocks, node) {
61 if (p->usecount)
62 printk("%-15s: %d\n", p->name, p->usecount);
63 print_parents(p);
64
65 }
66 spin_unlock_irqrestore(&clockfw_lock, flags);
67}
68
69#endif
70
71/*------------------------------------------------------------------------- 37/*-------------------------------------------------------------------------
72 * Standard clock functions defined in include/linux/clk.h 38 * Standard clock functions defined in include/linux/clk.h
73 *-------------------------------------------------------------------------*/ 39 *-------------------------------------------------------------------------*/
@@ -446,3 +412,93 @@ int __init clk_init(struct clk_functions * custom_clocks)
446 return 0; 412 return 0;
447} 413}
448 414
415#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
416/*
417 * debugfs support to trace clock tree hierarchy and attributes
418 */
419static struct dentry *clk_debugfs_root;
420
421static int clk_debugfs_register_one(struct clk *c)
422{
423 int err;
424 struct dentry *d, *child;
425 struct clk *pa = c->parent;
426 char s[255];
427 char *p = s;
428
429 p += sprintf(p, "%s", c->name);
430 if (c->id != 0)
431 sprintf(p, ":%d", c->id);
432 d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
433 if (IS_ERR(d))
434 return PTR_ERR(d);
435 c->dent = d;
436
437 d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
438 if (IS_ERR(d)) {
439 err = PTR_ERR(d);
440 goto err_out;
441 }
442 d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
443 if (IS_ERR(d)) {
444 err = PTR_ERR(d);
445 goto err_out;
446 }
447 d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
448 if (IS_ERR(d)) {
449 err = PTR_ERR(d);
450 goto err_out;
451 }
452 return 0;
453
454err_out:
455 d = c->dent;
456 list_for_each_entry(child, &d->d_subdirs, d_u.d_child)
457 debugfs_remove(child);
458 debugfs_remove(c->dent);
459 return err;
460}
461
462static int clk_debugfs_register(struct clk *c)
463{
464 int err;
465 struct clk *pa = c->parent;
466
467 if (pa && !pa->dent) {
468 err = clk_debugfs_register(pa);
469 if (err)
470 return err;
471 }
472
473 if (!c->dent) {
474 err = clk_debugfs_register_one(c);
475 if (err)
476 return err;
477 }
478 return 0;
479}
480
481static int __init clk_debugfs_init(void)
482{
483 struct clk *c;
484 struct dentry *d;
485 int err;
486
487 d = debugfs_create_dir("clock", NULL);
488 if (IS_ERR(d))
489 return PTR_ERR(d);
490 clk_debugfs_root = d;
491
492 list_for_each_entry(c, &clocks, node) {
493 err = clk_debugfs_register(c);
494 if (err)
495 goto err_out;
496 }
497 return 0;
498err_out:
499 debugfs_remove(clk_debugfs_root); /* REVISIT: Cleanup correctly */
500 return err;
501}
502late_initcall(clk_debugfs_init);
503
504#endif /* defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS) */
diff --git a/arch/arm/plat-omap/common.c b/arch/arm/plat-omap/common.c
index bd1cef2c3c14..8d04929a3c75 100644
--- a/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@ -26,6 +26,7 @@
26#include <asm/io.h> 26#include <asm/io.h>
27#include <asm/setup.h> 27#include <asm/setup.h>
28 28
29#include <asm/arch/common.h>
29#include <asm/arch/board.h> 30#include <asm/arch/board.h>
30#include <asm/arch/control.h> 31#include <asm/arch/control.h>
31#include <asm/arch/mux.h> 32#include <asm/arch/mux.h>
@@ -241,30 +242,70 @@ arch_initcall(omap_init_clocksource_32k);
241 242
242/* Global address base setup code */ 243/* Global address base setup code */
243 244
245#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
246
247static struct omap_globals *omap2_globals;
248
249static void __init __omap2_set_globals(void)
250{
251 omap2_set_globals_memory(omap2_globals);
252 omap2_set_globals_control(omap2_globals);
253 omap2_set_globals_prcm(omap2_globals);
254}
255
256#endif
257
244#if defined(CONFIG_ARCH_OMAP2420) 258#if defined(CONFIG_ARCH_OMAP2420)
259
260static struct omap_globals omap242x_globals = {
261 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x48014000),
262 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SDRC_BASE),
263 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_SMS_BASE),
264 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CTRL_BASE),
265 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_PRM_BASE),
266 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2420_CM_BASE),
267};
268
245void __init omap2_set_globals_242x(void) 269void __init omap2_set_globals_242x(void)
246{ 270{
247 omap2_sdrc_base = OMAP2420_SDRC_BASE; 271 omap2_globals = &omap242x_globals;
248 omap2_sms_base = OMAP2420_SMS_BASE; 272 __omap2_set_globals();
249 omap_ctrl_base_set(OMAP2420_CTRL_BASE);
250} 273}
251#endif 274#endif
252 275
253#if defined(CONFIG_ARCH_OMAP2430) 276#if defined(CONFIG_ARCH_OMAP2430)
277
278static struct omap_globals omap243x_globals = {
279 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4900a000),
280 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SDRC_BASE),
281 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_SMS_BASE),
282 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP243X_CTRL_BASE),
283 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_PRM_BASE),
284 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP2430_CM_BASE),
285};
286
254void __init omap2_set_globals_243x(void) 287void __init omap2_set_globals_243x(void)
255{ 288{
256 omap2_sdrc_base = OMAP243X_SDRC_BASE; 289 omap2_globals = &omap243x_globals;
257 omap2_sms_base = OMAP243X_SMS_BASE; 290 __omap2_set_globals();
258 omap_ctrl_base_set(OMAP243X_CTRL_BASE);
259} 291}
260#endif 292#endif
261 293
262#if defined(CONFIG_ARCH_OMAP3430) 294#if defined(CONFIG_ARCH_OMAP3430)
295
296static struct omap_globals omap343x_globals = {
297 .tap = (__force void __iomem *)OMAP2_IO_ADDRESS(0x4830A000),
298 .sdrc = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SDRC_BASE),
299 .sms = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_SMS_BASE),
300 .ctrl = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP343X_CTRL_BASE),
301 .prm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_PRM_BASE),
302 .cm = (__force void __iomem *)OMAP2_IO_ADDRESS(OMAP3430_CM_BASE),
303};
304
263void __init omap2_set_globals_343x(void) 305void __init omap2_set_globals_343x(void)
264{ 306{
265 omap2_sdrc_base = OMAP343X_SDRC_BASE; 307 omap2_globals = &omap343x_globals;
266 omap2_sms_base = OMAP343X_SMS_BASE; 308 __omap2_set_globals();
267 omap_ctrl_base_set(OMAP343X_CTRL_BASE);
268} 309}
269#endif 310#endif
270 311
diff --git a/arch/arm/plat-omap/devices.c b/arch/arm/plat-omap/devices.c
index 4a53f9ba6c43..81002b722da1 100644
--- a/arch/arm/plat-omap/devices.c
+++ b/arch/arm/plat-omap/devices.c
@@ -24,6 +24,7 @@
24#include <asm/arch/mux.h> 24#include <asm/arch/mux.h>
25#include <asm/arch/gpio.h> 25#include <asm/arch/gpio.h>
26#include <asm/arch/menelaus.h> 26#include <asm/arch/menelaus.h>
27#include <asm/arch/mcbsp.h>
27 28
28#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE) 29#if defined(CONFIG_OMAP_DSP) || defined(CONFIG_OMAP_DSP_MODULE)
29 30
@@ -145,6 +146,53 @@ static inline void omap_init_kp(void) {}
145#endif 146#endif
146 147
147/*-------------------------------------------------------------------------*/ 148/*-------------------------------------------------------------------------*/
149#if defined(CONFIG_OMAP_MCBSP) || defined(CONFIG_OMAP_MCBSP_MODULE)
150
151static struct platform_device **omap_mcbsp_devices;
152
153void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
154 int size)
155{
156 int i;
157
158 if (size > OMAP_MAX_MCBSP_COUNT) {
159 printk(KERN_WARNING "Registered too many McBSPs platform_data."
160 " Using maximum (%d) available.\n",
161 OMAP_MAX_MCBSP_COUNT);
162 size = OMAP_MAX_MCBSP_COUNT;
163 }
164
165 omap_mcbsp_devices = kzalloc(size * sizeof(struct platform_device *),
166 GFP_KERNEL);
167 if (!omap_mcbsp_devices) {
168 printk(KERN_ERR "Could not register McBSP devices\n");
169 return;
170 }
171
172 for (i = 0; i < size; i++) {
173 struct platform_device *new_mcbsp;
174 int ret;
175
176 new_mcbsp = platform_device_alloc("omap-mcbsp", i + 1);
177 if (!new_mcbsp)
178 continue;
179 new_mcbsp->dev.platform_data = &config[i];
180 ret = platform_device_add(new_mcbsp);
181 if (ret) {
182 platform_device_put(new_mcbsp);
183 continue;
184 }
185 omap_mcbsp_devices[i] = new_mcbsp;
186 }
187}
188
189#else
190void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
191 int size)
192{ }
193#endif
194
195/*-------------------------------------------------------------------------*/
148 196
149#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) 197#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE)
150 198
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index c00eda588cd8..fac8e994f588 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * linux/arch/arm/plat-omap/dma.c 2 * linux/arch/arm/plat-omap/dma.c
3 * 3 *
4 * Copyright (C) 2003 Nokia Corporation 4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com> 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations 7 * Graphics DMA and LCD DMA graphics tranformations
@@ -25,11 +25,11 @@
25#include <linux/errno.h> 25#include <linux/errno.h>
26#include <linux/interrupt.h> 26#include <linux/interrupt.h>
27#include <linux/irq.h> 27#include <linux/irq.h>
28#include <linux/io.h>
28 29
29#include <asm/system.h> 30#include <asm/system.h>
30#include <asm/hardware.h> 31#include <asm/hardware.h>
31#include <asm/dma.h> 32#include <asm/dma.h>
32#include <asm/io.h>
33 33
34#include <asm/arch/tc.h> 34#include <asm/arch/tc.h>
35 35
@@ -43,13 +43,13 @@ enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED }; 43enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
44#endif 44#endif
45 45
46#define OMAP_DMA_ACTIVE 0x01 46#define OMAP_DMA_ACTIVE 0x01
47#define OMAP_DMA_CCR_EN (1 << 7) 47#define OMAP_DMA_CCR_EN (1 << 7)
48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe 48#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
49 49
50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec) 50#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
51 51
52static int enable_1510_mode = 0; 52static int enable_1510_mode;
53 53
54struct omap_dma_lch { 54struct omap_dma_lch {
55 int next_lch; 55 int next_lch;
@@ -57,7 +57,7 @@ struct omap_dma_lch {
57 u16 saved_csr; 57 u16 saved_csr;
58 u16 enabled_irqs; 58 u16 enabled_irqs;
59 const char *dev_name; 59 const char *dev_name;
60 void (* callback)(int lch, u16 ch_status, void *data); 60 void (*callback)(int lch, u16 ch_status, void *data);
61 void *data; 61 void *data;
62 62
63#ifndef CONFIG_ARCH_OMAP1 63#ifndef CONFIG_ARCH_OMAP1
@@ -72,7 +72,6 @@ struct omap_dma_lch {
72 long flags; 72 long flags;
73}; 73};
74 74
75#ifndef CONFIG_ARCH_OMAP1
76struct dma_link_info { 75struct dma_link_info {
77 int *linked_dmach_q; 76 int *linked_dmach_q;
78 int no_of_lchs_linked; 77 int no_of_lchs_linked;
@@ -86,7 +85,9 @@ struct dma_link_info {
86 85
87}; 86};
88 87
89static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT]; 88static struct dma_link_info *dma_linked_lch;
89
90#ifndef CONFIG_ARCH_OMAP1
90 91
91/* Chain handling macros */ 92/* Chain handling macros */
92#define OMAP_DMA_CHAIN_QINIT(chain_id) \ 93#define OMAP_DMA_CHAIN_QINIT(chain_id) \
@@ -119,12 +120,15 @@ static struct dma_link_info dma_linked_lch[OMAP_LOGICAL_DMA_CH_COUNT];
119 dma_linked_lch[chain_id].q_count++; \ 120 dma_linked_lch[chain_id].q_count++; \
120 } while (0) 121 } while (0)
121#endif 122#endif
123
124static int dma_lch_count;
122static int dma_chan_count; 125static int dma_chan_count;
123 126
124static spinlock_t dma_chan_lock; 127static spinlock_t dma_chan_lock;
125static struct omap_dma_lch dma_chan[OMAP_LOGICAL_DMA_CH_COUNT]; 128static struct omap_dma_lch *dma_chan;
129static void __iomem *omap_dma_base;
126 130
127static const u8 omap1_dma_irq[OMAP_LOGICAL_DMA_CH_COUNT] = { 131static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
128 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3, 132 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
129 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7, 133 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
130 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10, 134 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
@@ -139,6 +143,24 @@ static inline void omap_enable_channel_irq(int lch);
139#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \ 143#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
140 __func__); 144 __func__);
141 145
146#define dma_read(reg) \
147({ \
148 u32 __val; \
149 if (cpu_class_is_omap1()) \
150 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
151 else \
152 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
153 __val; \
154})
155
156#define dma_write(val, reg) \
157({ \
158 if (cpu_class_is_omap1()) \
159 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
160 else \
161 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
162})
163
142#ifdef CONFIG_ARCH_OMAP15XX 164#ifdef CONFIG_ARCH_OMAP15XX
143/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */ 165/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
144int omap_dma_in_1510_mode(void) 166int omap_dma_in_1510_mode(void)
@@ -173,13 +195,14 @@ static inline void set_gdma_dev(int req, int dev)
173#define set_gdma_dev(req, dev) do {} while (0) 195#define set_gdma_dev(req, dev) do {} while (0)
174#endif 196#endif
175 197
198/* Omap1 only */
176static void clear_lch_regs(int lch) 199static void clear_lch_regs(int lch)
177{ 200{
178 int i; 201 int i;
179 u32 lch_base = OMAP_DMA_BASE + lch * 0x40; 202 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
180 203
181 for (i = 0; i < 0x2c; i += 2) 204 for (i = 0; i < 0x2c; i += 2)
182 omap_writew(0, lch_base + i); 205 __raw_writew(0, lch_base + i);
183} 206}
184 207
185void omap_set_dma_priority(int lch, int dst_port, int priority) 208void omap_set_dma_priority(int lch, int dst_port, int priority)
@@ -212,33 +235,49 @@ void omap_set_dma_priority(int lch, int dst_port, int priority)
212 } 235 }
213 236
214 if (cpu_class_is_omap2()) { 237 if (cpu_class_is_omap2()) {
238 u32 ccr;
239
240 ccr = dma_read(CCR(lch));
215 if (priority) 241 if (priority)
216 OMAP_DMA_CCR_REG(lch) |= (1 << 6); 242 ccr |= (1 << 6);
217 else 243 else
218 OMAP_DMA_CCR_REG(lch) &= ~(1 << 6); 244 ccr &= ~(1 << 6);
245 dma_write(ccr, CCR(lch));
219 } 246 }
220} 247}
248EXPORT_SYMBOL(omap_set_dma_priority);
221 249
222void omap_set_dma_transfer_params(int lch, int data_type, int elem_count, 250void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
223 int frame_count, int sync_mode, 251 int frame_count, int sync_mode,
224 int dma_trigger, int src_or_dst_synch) 252 int dma_trigger, int src_or_dst_synch)
225{ 253{
226 OMAP_DMA_CSDP_REG(lch) &= ~0x03; 254 u32 l;
227 OMAP_DMA_CSDP_REG(lch) |= data_type; 255
256 l = dma_read(CSDP(lch));
257 l &= ~0x03;
258 l |= data_type;
259 dma_write(l, CSDP(lch));
228 260
229 if (cpu_class_is_omap1()) { 261 if (cpu_class_is_omap1()) {
230 OMAP_DMA_CCR_REG(lch) &= ~(1 << 5); 262 u16 ccr;
263
264 ccr = dma_read(CCR(lch));
265 ccr &= ~(1 << 5);
231 if (sync_mode == OMAP_DMA_SYNC_FRAME) 266 if (sync_mode == OMAP_DMA_SYNC_FRAME)
232 OMAP_DMA_CCR_REG(lch) |= 1 << 5; 267 ccr |= 1 << 5;
268 dma_write(ccr, CCR(lch));
233 269
234 OMAP1_DMA_CCR2_REG(lch) &= ~(1 << 2); 270 ccr = dma_read(CCR2(lch));
271 ccr &= ~(1 << 2);
235 if (sync_mode == OMAP_DMA_SYNC_BLOCK) 272 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
236 OMAP1_DMA_CCR2_REG(lch) |= 1 << 2; 273 ccr |= 1 << 2;
274 dma_write(ccr, CCR2(lch));
237 } 275 }
238 276
239 if (cpu_class_is_omap2() && dma_trigger) { 277 if (cpu_class_is_omap2() && dma_trigger) {
240 u32 val = OMAP_DMA_CCR_REG(lch); 278 u32 val;
241 279
280 val = dma_read(CCR(lch));
242 val &= ~(3 << 19); 281 val &= ~(3 << 19);
243 if (dma_trigger > 63) 282 if (dma_trigger > 63)
244 val |= 1 << 20; 283 val |= 1 << 20;
@@ -263,12 +302,13 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
263 else 302 else
264 val &= ~(1 << 24); /* dest synch */ 303 val &= ~(1 << 24); /* dest synch */
265 304
266 OMAP_DMA_CCR_REG(lch) = val; 305 dma_write(val, CCR(lch));
267 } 306 }
268 307
269 OMAP_DMA_CEN_REG(lch) = elem_count; 308 dma_write(elem_count, CEN(lch));
270 OMAP_DMA_CFN_REG(lch) = frame_count; 309 dma_write(frame_count, CFN(lch));
271} 310}
311EXPORT_SYMBOL(omap_set_dma_transfer_params);
272 312
273void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color) 313void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
274{ 314{
@@ -281,7 +321,9 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
281 return; 321 return;
282 } 322 }
283 323
284 w = OMAP1_DMA_CCR2_REG(lch) & ~0x03; 324 w = dma_read(CCR2(lch));
325 w &= ~0x03;
326
285 switch (mode) { 327 switch (mode) {
286 case OMAP_DMA_CONSTANT_FILL: 328 case OMAP_DMA_CONSTANT_FILL:
287 w |= 0x01; 329 w |= 0x01;
@@ -294,52 +336,81 @@ void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
294 default: 336 default:
295 BUG(); 337 BUG();
296 } 338 }
297 OMAP1_DMA_CCR2_REG(lch) = w; 339 dma_write(w, CCR2(lch));
298 340
299 w = OMAP1_DMA_LCH_CTRL_REG(lch) & ~0x0f; 341 w = dma_read(LCH_CTRL(lch));
342 w &= ~0x0f;
300 /* Default is channel type 2D */ 343 /* Default is channel type 2D */
301 if (mode) { 344 if (mode) {
302 OMAP1_DMA_COLOR_L_REG(lch) = (u16)color; 345 dma_write((u16)color, COLOR_L(lch));
303 OMAP1_DMA_COLOR_U_REG(lch) = (u16)(color >> 16); 346 dma_write((u16)(color >> 16), COLOR_U(lch));
304 w |= 1; /* Channel type G */ 347 w |= 1; /* Channel type G */
305 } 348 }
306 OMAP1_DMA_LCH_CTRL_REG(lch) = w; 349 dma_write(w, LCH_CTRL(lch));
307} 350}
351EXPORT_SYMBOL(omap_set_dma_color_mode);
308 352
309void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode) 353void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
310{ 354{
311 if (cpu_class_is_omap2()) { 355 if (cpu_class_is_omap2()) {
312 OMAP_DMA_CSDP_REG(lch) &= ~(0x3 << 16); 356 u32 csdp;
313 OMAP_DMA_CSDP_REG(lch) |= (mode << 16); 357
358 csdp = dma_read(CSDP(lch));
359 csdp &= ~(0x3 << 16);
360 csdp |= (mode << 16);
361 dma_write(csdp, CSDP(lch));
362 }
363}
364EXPORT_SYMBOL(omap_set_dma_write_mode);
365
366void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
367{
368 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
369 u32 l;
370
371 l = dma_read(LCH_CTRL(lch));
372 l &= ~0x7;
373 l |= mode;
374 dma_write(l, LCH_CTRL(lch));
314 } 375 }
315} 376}
377EXPORT_SYMBOL(omap_set_dma_channel_mode);
316 378
317/* Note that src_port is only for omap1 */ 379/* Note that src_port is only for omap1 */
318void omap_set_dma_src_params(int lch, int src_port, int src_amode, 380void omap_set_dma_src_params(int lch, int src_port, int src_amode,
319 unsigned long src_start, 381 unsigned long src_start,
320 int src_ei, int src_fi) 382 int src_ei, int src_fi)
321{ 383{
384 u32 l;
385
322 if (cpu_class_is_omap1()) { 386 if (cpu_class_is_omap1()) {
323 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 2); 387 u16 w;
324 OMAP_DMA_CSDP_REG(lch) |= src_port << 2; 388
389 w = dma_read(CSDP(lch));
390 w &= ~(0x1f << 2);
391 w |= src_port << 2;
392 dma_write(w, CSDP(lch));
325 } 393 }
326 394
327 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 12); 395 l = dma_read(CCR(lch));
328 OMAP_DMA_CCR_REG(lch) |= src_amode << 12; 396 l &= ~(0x03 << 12);
397 l |= src_amode << 12;
398 dma_write(l, CCR(lch));
329 399
330 if (cpu_class_is_omap1()) { 400 if (cpu_class_is_omap1()) {
331 OMAP1_DMA_CSSA_U_REG(lch) = src_start >> 16; 401 dma_write(src_start >> 16, CSSA_U(lch));
332 OMAP1_DMA_CSSA_L_REG(lch) = src_start; 402 dma_write((u16)src_start, CSSA_L(lch));
333 } 403 }
334 404
335 if (cpu_class_is_omap2()) 405 if (cpu_class_is_omap2())
336 OMAP2_DMA_CSSA_REG(lch) = src_start; 406 dma_write(src_start, CSSA(lch));
337 407
338 OMAP_DMA_CSEI_REG(lch) = src_ei; 408 dma_write(src_ei, CSEI(lch));
339 OMAP_DMA_CSFI_REG(lch) = src_fi; 409 dma_write(src_fi, CSFI(lch));
340} 410}
411EXPORT_SYMBOL(omap_set_dma_src_params);
341 412
342void omap_set_dma_params(int lch, struct omap_dma_channel_params * params) 413void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
343{ 414{
344 omap_set_dma_transfer_params(lch, params->data_type, 415 omap_set_dma_transfer_params(lch, params->data_type,
345 params->elem_count, params->frame_count, 416 params->elem_count, params->frame_count,
@@ -356,28 +427,37 @@ void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
356 omap_dma_set_prio_lch(lch, params->read_prio, 427 omap_dma_set_prio_lch(lch, params->read_prio,
357 params->write_prio); 428 params->write_prio);
358} 429}
430EXPORT_SYMBOL(omap_set_dma_params);
359 431
360void omap_set_dma_src_index(int lch, int eidx, int fidx) 432void omap_set_dma_src_index(int lch, int eidx, int fidx)
361{ 433{
362 if (cpu_class_is_omap2()) { 434 if (cpu_class_is_omap2())
363 REVISIT_24XX();
364 return; 435 return;
365 } 436
366 OMAP_DMA_CSEI_REG(lch) = eidx; 437 dma_write(eidx, CSEI(lch));
367 OMAP_DMA_CSFI_REG(lch) = fidx; 438 dma_write(fidx, CSFI(lch));
368} 439}
440EXPORT_SYMBOL(omap_set_dma_src_index);
369 441
370void omap_set_dma_src_data_pack(int lch, int enable) 442void omap_set_dma_src_data_pack(int lch, int enable)
371{ 443{
372 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 6); 444 u32 l;
445
446 l = dma_read(CSDP(lch));
447 l &= ~(1 << 6);
373 if (enable) 448 if (enable)
374 OMAP_DMA_CSDP_REG(lch) |= (1 << 6); 449 l |= (1 << 6);
450 dma_write(l, CSDP(lch));
375} 451}
452EXPORT_SYMBOL(omap_set_dma_src_data_pack);
376 453
377void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 454void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
378{ 455{
379 unsigned int burst = 0; 456 unsigned int burst = 0;
380 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 7); 457 u32 l;
458
459 l = dma_read(CSDP(lch));
460 l &= ~(0x03 << 7);
381 461
382 switch (burst_mode) { 462 switch (burst_mode) {
383 case OMAP_DMA_DATA_BURST_DIS: 463 case OMAP_DMA_DATA_BURST_DIS:
@@ -408,55 +488,73 @@ void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
408 default: 488 default:
409 BUG(); 489 BUG();
410 } 490 }
411 OMAP_DMA_CSDP_REG(lch) |= (burst << 7); 491
492 l |= (burst << 7);
493 dma_write(l, CSDP(lch));
412} 494}
495EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
413 496
414/* Note that dest_port is only for OMAP1 */ 497/* Note that dest_port is only for OMAP1 */
415void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode, 498void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
416 unsigned long dest_start, 499 unsigned long dest_start,
417 int dst_ei, int dst_fi) 500 int dst_ei, int dst_fi)
418{ 501{
502 u32 l;
503
419 if (cpu_class_is_omap1()) { 504 if (cpu_class_is_omap1()) {
420 OMAP_DMA_CSDP_REG(lch) &= ~(0x1f << 9); 505 l = dma_read(CSDP(lch));
421 OMAP_DMA_CSDP_REG(lch) |= dest_port << 9; 506 l &= ~(0x1f << 9);
507 l |= dest_port << 9;
508 dma_write(l, CSDP(lch));
422 } 509 }
423 510
424 OMAP_DMA_CCR_REG(lch) &= ~(0x03 << 14); 511 l = dma_read(CCR(lch));
425 OMAP_DMA_CCR_REG(lch) |= dest_amode << 14; 512 l &= ~(0x03 << 14);
513 l |= dest_amode << 14;
514 dma_write(l, CCR(lch));
426 515
427 if (cpu_class_is_omap1()) { 516 if (cpu_class_is_omap1()) {
428 OMAP1_DMA_CDSA_U_REG(lch) = dest_start >> 16; 517 dma_write(dest_start >> 16, CDSA_U(lch));
429 OMAP1_DMA_CDSA_L_REG(lch) = dest_start; 518 dma_write(dest_start, CDSA_L(lch));
430 } 519 }
431 520
432 if (cpu_class_is_omap2()) 521 if (cpu_class_is_omap2())
433 OMAP2_DMA_CDSA_REG(lch) = dest_start; 522 dma_write(dest_start, CDSA(lch));
434 523
435 OMAP_DMA_CDEI_REG(lch) = dst_ei; 524 dma_write(dst_ei, CDEI(lch));
436 OMAP_DMA_CDFI_REG(lch) = dst_fi; 525 dma_write(dst_fi, CDFI(lch));
437} 526}
527EXPORT_SYMBOL(omap_set_dma_dest_params);
438 528
439void omap_set_dma_dest_index(int lch, int eidx, int fidx) 529void omap_set_dma_dest_index(int lch, int eidx, int fidx)
440{ 530{
441 if (cpu_class_is_omap2()) { 531 if (cpu_class_is_omap2())
442 REVISIT_24XX();
443 return; 532 return;
444 } 533
445 OMAP_DMA_CDEI_REG(lch) = eidx; 534 dma_write(eidx, CDEI(lch));
446 OMAP_DMA_CDFI_REG(lch) = fidx; 535 dma_write(fidx, CDFI(lch));
447} 536}
537EXPORT_SYMBOL(omap_set_dma_dest_index);
448 538
449void omap_set_dma_dest_data_pack(int lch, int enable) 539void omap_set_dma_dest_data_pack(int lch, int enable)
450{ 540{
451 OMAP_DMA_CSDP_REG(lch) &= ~(1 << 13); 541 u32 l;
542
543 l = dma_read(CSDP(lch));
544 l &= ~(1 << 13);
452 if (enable) 545 if (enable)
453 OMAP_DMA_CSDP_REG(lch) |= 1 << 13; 546 l |= 1 << 13;
547 dma_write(l, CSDP(lch));
454} 548}
549EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
455 550
456void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode) 551void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
457{ 552{
458 unsigned int burst = 0; 553 unsigned int burst = 0;
459 OMAP_DMA_CSDP_REG(lch) &= ~(0x03 << 14); 554 u32 l;
555
556 l = dma_read(CSDP(lch));
557 l &= ~(0x03 << 14);
460 558
461 switch (burst_mode) { 559 switch (burst_mode) {
462 case OMAP_DMA_DATA_BURST_DIS: 560 case OMAP_DMA_DATA_BURST_DIS:
@@ -486,8 +584,10 @@ void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
486 BUG(); 584 BUG();
487 return; 585 return;
488 } 586 }
489 OMAP_DMA_CSDP_REG(lch) |= (burst << 14); 587 l |= (burst << 14);
588 dma_write(l, CSDP(lch));
490} 589}
590EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
491 591
492static inline void omap_enable_channel_irq(int lch) 592static inline void omap_enable_channel_irq(int lch)
493{ 593{
@@ -495,64 +595,74 @@ static inline void omap_enable_channel_irq(int lch)
495 595
496 /* Clear CSR */ 596 /* Clear CSR */
497 if (cpu_class_is_omap1()) 597 if (cpu_class_is_omap1())
498 status = OMAP_DMA_CSR_REG(lch); 598 status = dma_read(CSR(lch));
499 else if (cpu_class_is_omap2()) 599 else if (cpu_class_is_omap2())
500 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 600 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
501 601
502 /* Enable some nice interrupts. */ 602 /* Enable some nice interrupts. */
503 OMAP_DMA_CICR_REG(lch) = dma_chan[lch].enabled_irqs; 603 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
504
505 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
506} 604}
507 605
508static void omap_disable_channel_irq(int lch) 606static void omap_disable_channel_irq(int lch)
509{ 607{
510 if (cpu_class_is_omap2()) 608 if (cpu_class_is_omap2())
511 OMAP_DMA_CICR_REG(lch) = 0; 609 dma_write(0, CICR(lch));
512} 610}
513 611
514void omap_enable_dma_irq(int lch, u16 bits) 612void omap_enable_dma_irq(int lch, u16 bits)
515{ 613{
516 dma_chan[lch].enabled_irqs |= bits; 614 dma_chan[lch].enabled_irqs |= bits;
517} 615}
616EXPORT_SYMBOL(omap_enable_dma_irq);
518 617
519void omap_disable_dma_irq(int lch, u16 bits) 618void omap_disable_dma_irq(int lch, u16 bits)
520{ 619{
521 dma_chan[lch].enabled_irqs &= ~bits; 620 dma_chan[lch].enabled_irqs &= ~bits;
522} 621}
622EXPORT_SYMBOL(omap_disable_dma_irq);
523 623
524static inline void enable_lnk(int lch) 624static inline void enable_lnk(int lch)
525{ 625{
626 u32 l;
627
628 l = dma_read(CLNK_CTRL(lch));
629
526 if (cpu_class_is_omap1()) 630 if (cpu_class_is_omap1())
527 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 14); 631 l &= ~(1 << 14);
528 632
529 /* Set the ENABLE_LNK bits */ 633 /* Set the ENABLE_LNK bits */
530 if (dma_chan[lch].next_lch != -1) 634 if (dma_chan[lch].next_lch != -1)
531 OMAP_DMA_CLNK_CTRL_REG(lch) = 635 l = dma_chan[lch].next_lch | (1 << 15);
532 dma_chan[lch].next_lch | (1 << 15);
533 636
534#ifndef CONFIG_ARCH_OMAP1 637#ifndef CONFIG_ARCH_OMAP1
535 if (dma_chan[lch].next_linked_ch != -1) 638 if (cpu_class_is_omap2())
536 OMAP_DMA_CLNK_CTRL_REG(lch) = 639 if (dma_chan[lch].next_linked_ch != -1)
537 dma_chan[lch].next_linked_ch | (1 << 15); 640 l = dma_chan[lch].next_linked_ch | (1 << 15);
538#endif 641#endif
642
643 dma_write(l, CLNK_CTRL(lch));
539} 644}
540 645
541static inline void disable_lnk(int lch) 646static inline void disable_lnk(int lch)
542{ 647{
648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
543 /* Disable interrupts */ 652 /* Disable interrupts */
544 if (cpu_class_is_omap1()) { 653 if (cpu_class_is_omap1()) {
545 OMAP_DMA_CICR_REG(lch) = 0; 654 dma_write(0, CICR(lch));
546 /* Set the STOP_LNK bit */ 655 /* Set the STOP_LNK bit */
547 OMAP_DMA_CLNK_CTRL_REG(lch) |= 1 << 14; 656 l |= 1 << 14;
548 } 657 }
549 658
550 if (cpu_class_is_omap2()) { 659 if (cpu_class_is_omap2()) {
551 omap_disable_channel_irq(lch); 660 omap_disable_channel_irq(lch);
552 /* Clear the ENABLE_LNK bit */ 661 /* Clear the ENABLE_LNK bit */
553 OMAP_DMA_CLNK_CTRL_REG(lch) &= ~(1 << 15); 662 l &= ~(1 << 15);
554 } 663 }
555 664
665 dma_write(l, CLNK_CTRL(lch));
556 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 666 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
557} 667}
558 668
@@ -563,13 +673,13 @@ static inline void omap2_enable_irq_lch(int lch)
563 if (!cpu_class_is_omap2()) 673 if (!cpu_class_is_omap2())
564 return; 674 return;
565 675
566 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 676 val = dma_read(IRQENABLE_L0);
567 val |= 1 << lch; 677 val |= 1 << lch;
568 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 678 dma_write(val, IRQENABLE_L0);
569} 679}
570 680
571int omap_request_dma(int dev_id, const char *dev_name, 681int omap_request_dma(int dev_id, const char *dev_name,
572 void (* callback)(int lch, u16 ch_status, void *data), 682 void (*callback)(int lch, u16 ch_status, void *data),
573 void *data, int *dma_ch_out) 683 void *data, int *dma_ch_out)
574{ 684{
575 int ch, free_ch = -1; 685 int ch, free_ch = -1;
@@ -602,10 +712,14 @@ int omap_request_dma(int dev_id, const char *dev_name,
602 chan->dev_name = dev_name; 712 chan->dev_name = dev_name;
603 chan->callback = callback; 713 chan->callback = callback;
604 chan->data = data; 714 chan->data = data;
715
605#ifndef CONFIG_ARCH_OMAP1 716#ifndef CONFIG_ARCH_OMAP1
606 chan->chain_id = -1; 717 if (cpu_class_is_omap2()) {
607 chan->next_linked_ch = -1; 718 chan->chain_id = -1;
719 chan->next_linked_ch = -1;
720 }
608#endif 721#endif
722
609 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ; 723 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
610 724
611 if (cpu_class_is_omap1()) 725 if (cpu_class_is_omap1())
@@ -620,26 +734,28 @@ int omap_request_dma(int dev_id, const char *dev_name,
620 set_gdma_dev(free_ch + 1, dev_id); 734 set_gdma_dev(free_ch + 1, dev_id);
621 dev_id = free_ch + 1; 735 dev_id = free_ch + 1;
622 } 736 }
623 /* Disable the 1510 compatibility mode and set the sync device 737 /*
624 * id. */ 738 * Disable the 1510 compatibility mode and set the sync device
625 OMAP_DMA_CCR_REG(free_ch) = dev_id | (1 << 10); 739 * id.
740 */
741 dma_write(dev_id | (1 << 10), CCR(free_ch));
626 } else if (cpu_is_omap730() || cpu_is_omap15xx()) { 742 } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
627 OMAP_DMA_CCR_REG(free_ch) = dev_id; 743 dma_write(dev_id, CCR(free_ch));
628 } 744 }
629 745
630 if (cpu_class_is_omap2()) { 746 if (cpu_class_is_omap2()) {
631 omap2_enable_irq_lch(free_ch); 747 omap2_enable_irq_lch(free_ch);
632
633 omap_enable_channel_irq(free_ch); 748 omap_enable_channel_irq(free_ch);
634 /* Clear the CSR register and IRQ status register */ 749 /* Clear the CSR register and IRQ status register */
635 OMAP_DMA_CSR_REG(free_ch) = OMAP2_DMA_CSR_CLEAR_MASK; 750 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
636 omap_writel(1 << free_ch, OMAP_DMA4_IRQSTATUS_L0); 751 dma_write(1 << free_ch, IRQSTATUS_L0);
637 } 752 }
638 753
639 *dma_ch_out = free_ch; 754 *dma_ch_out = free_ch;
640 755
641 return 0; 756 return 0;
642} 757}
758EXPORT_SYMBOL(omap_request_dma);
643 759
644void omap_free_dma(int lch) 760void omap_free_dma(int lch)
645{ 761{
@@ -647,11 +763,12 @@ void omap_free_dma(int lch)
647 763
648 spin_lock_irqsave(&dma_chan_lock, flags); 764 spin_lock_irqsave(&dma_chan_lock, flags);
649 if (dma_chan[lch].dev_id == -1) { 765 if (dma_chan[lch].dev_id == -1) {
650 printk("omap_dma: trying to free nonallocated DMA channel %d\n", 766 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
651 lch); 767 lch);
652 spin_unlock_irqrestore(&dma_chan_lock, flags); 768 spin_unlock_irqrestore(&dma_chan_lock, flags);
653 return; 769 return;
654 } 770 }
771
655 dma_chan[lch].dev_id = -1; 772 dma_chan[lch].dev_id = -1;
656 dma_chan[lch].next_lch = -1; 773 dma_chan[lch].next_lch = -1;
657 dma_chan[lch].callback = NULL; 774 dma_chan[lch].callback = NULL;
@@ -659,30 +776,31 @@ void omap_free_dma(int lch)
659 776
660 if (cpu_class_is_omap1()) { 777 if (cpu_class_is_omap1()) {
661 /* Disable all DMA interrupts for the channel. */ 778 /* Disable all DMA interrupts for the channel. */
662 OMAP_DMA_CICR_REG(lch) = 0; 779 dma_write(0, CICR(lch));
663 /* Make sure the DMA transfer is stopped. */ 780 /* Make sure the DMA transfer is stopped. */
664 OMAP_DMA_CCR_REG(lch) = 0; 781 dma_write(0, CCR(lch));
665 } 782 }
666 783
667 if (cpu_class_is_omap2()) { 784 if (cpu_class_is_omap2()) {
668 u32 val; 785 u32 val;
669 /* Disable interrupts */ 786 /* Disable interrupts */
670 val = omap_readl(OMAP_DMA4_IRQENABLE_L0); 787 val = dma_read(IRQENABLE_L0);
671 val &= ~(1 << lch); 788 val &= ~(1 << lch);
672 omap_writel(val, OMAP_DMA4_IRQENABLE_L0); 789 dma_write(val, IRQENABLE_L0);
673 790
674 /* Clear the CSR register and IRQ status register */ 791 /* Clear the CSR register and IRQ status register */
675 OMAP_DMA_CSR_REG(lch) = OMAP2_DMA_CSR_CLEAR_MASK; 792 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
676 omap_writel(1 << lch, OMAP_DMA4_IRQSTATUS_L0); 793 dma_write(1 << lch, IRQSTATUS_L0);
677 794
678 /* Disable all DMA interrupts for the channel. */ 795 /* Disable all DMA interrupts for the channel. */
679 OMAP_DMA_CICR_REG(lch) = 0; 796 dma_write(0, CICR(lch));
680 797
681 /* Make sure the DMA transfer is stopped. */ 798 /* Make sure the DMA transfer is stopped. */
682 OMAP_DMA_CCR_REG(lch) = 0; 799 dma_write(0, CCR(lch));
683 omap_clear_dma(lch); 800 omap_clear_dma(lch);
684 } 801 }
685} 802}
803EXPORT_SYMBOL(omap_free_dma);
686 804
687/** 805/**
688 * @brief omap_dma_set_global_params : Set global priority settings for dma 806 * @brief omap_dma_set_global_params : Set global priority settings for dma
@@ -710,7 +828,7 @@ omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
710 reg = (arb_rate & 0xff) << 16; 828 reg = (arb_rate & 0xff) << 16;
711 reg |= (0xff & max_fifo_depth); 829 reg |= (0xff & max_fifo_depth);
712 830
713 omap_writel(reg, OMAP_DMA4_GCR_REG); 831 dma_write(reg, GCR);
714} 832}
715EXPORT_SYMBOL(omap_dma_set_global_params); 833EXPORT_SYMBOL(omap_dma_set_global_params);
716 834
@@ -727,20 +845,21 @@ int
727omap_dma_set_prio_lch(int lch, unsigned char read_prio, 845omap_dma_set_prio_lch(int lch, unsigned char read_prio,
728 unsigned char write_prio) 846 unsigned char write_prio)
729{ 847{
730 u32 w; 848 u32 l;
731 849
732 if (unlikely((lch < 0 || lch >= OMAP_LOGICAL_DMA_CH_COUNT))) { 850 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
733 printk(KERN_ERR "Invalid channel id\n"); 851 printk(KERN_ERR "Invalid channel id\n");
734 return -EINVAL; 852 return -EINVAL;
735 } 853 }
736 w = OMAP_DMA_CCR_REG(lch); 854 l = dma_read(CCR(lch));
737 w &= ~((1 << 6) | (1 << 26)); 855 l &= ~((1 << 6) | (1 << 26));
738 if (cpu_is_omap2430() || cpu_is_omap34xx()) 856 if (cpu_is_omap2430() || cpu_is_omap34xx())
739 w |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26); 857 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
740 else 858 else
741 w |= ((read_prio & 0x1) << 6); 859 l |= ((read_prio & 0x1) << 6);
860
861 dma_write(l, CCR(lch));
742 862
743 OMAP_DMA_CCR_REG(lch) = w;
744 return 0; 863 return 0;
745} 864}
746EXPORT_SYMBOL(omap_dma_set_prio_lch); 865EXPORT_SYMBOL(omap_dma_set_prio_lch);
@@ -756,28 +875,34 @@ void omap_clear_dma(int lch)
756 local_irq_save(flags); 875 local_irq_save(flags);
757 876
758 if (cpu_class_is_omap1()) { 877 if (cpu_class_is_omap1()) {
759 int status; 878 u32 l;
760 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN; 879
880 l = dma_read(CCR(lch));
881 l &= ~OMAP_DMA_CCR_EN;
882 dma_write(l, CCR(lch));
761 883
762 /* Clear pending interrupts */ 884 /* Clear pending interrupts */
763 status = OMAP_DMA_CSR_REG(lch); 885 l = dma_read(CSR(lch));
764 } 886 }
765 887
766 if (cpu_class_is_omap2()) { 888 if (cpu_class_is_omap2()) {
767 int i; 889 int i;
768 u32 lch_base = OMAP_DMA4_BASE + lch * 0x60 + 0x80; 890 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
769 for (i = 0; i < 0x44; i += 4) 891 for (i = 0; i < 0x44; i += 4)
770 omap_writel(0, lch_base + i); 892 __raw_writel(0, lch_base + i);
771 } 893 }
772 894
773 local_irq_restore(flags); 895 local_irq_restore(flags);
774} 896}
897EXPORT_SYMBOL(omap_clear_dma);
775 898
776void omap_start_dma(int lch) 899void omap_start_dma(int lch)
777{ 900{
901 u32 l;
902
778 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 903 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
779 int next_lch, cur_lch; 904 int next_lch, cur_lch;
780 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 905 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
781 906
782 dma_chan_link_map[lch] = 1; 907 dma_chan_link_map[lch] = 1;
783 /* Set the link register of the first channel */ 908 /* Set the link register of the first channel */
@@ -801,27 +926,34 @@ void omap_start_dma(int lch)
801 } while (next_lch != -1); 926 } while (next_lch != -1);
802 } else if (cpu_class_is_omap2()) { 927 } else if (cpu_class_is_omap2()) {
803 /* Errata: Need to write lch even if not using chaining */ 928 /* Errata: Need to write lch even if not using chaining */
804 OMAP_DMA_CLNK_CTRL_REG(lch) = lch; 929 dma_write(lch, CLNK_CTRL(lch));
805 } 930 }
806 931
807 omap_enable_channel_irq(lch); 932 omap_enable_channel_irq(lch);
808 933
809 /* Errata: On ES2.0 BUFFERING disable must be set. 934 l = dma_read(CCR(lch));
810 * This will always fail on ES1.0 */
811 if (cpu_is_omap24xx()) {
812 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN;
813 }
814 935
815 OMAP_DMA_CCR_REG(lch) |= OMAP_DMA_CCR_EN; 936 /*
937 * Errata: On ES2.0 BUFFERING disable must be set.
938 * This will always fail on ES1.0
939 */
940 if (cpu_is_omap24xx())
941 l |= OMAP_DMA_CCR_EN;
942
943 l |= OMAP_DMA_CCR_EN;
944 dma_write(l, CCR(lch));
816 945
817 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 946 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
818} 947}
948EXPORT_SYMBOL(omap_start_dma);
819 949
820void omap_stop_dma(int lch) 950void omap_stop_dma(int lch)
821{ 951{
952 u32 l;
953
822 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { 954 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
823 int next_lch, cur_lch = lch; 955 int next_lch, cur_lch = lch;
824 char dma_chan_link_map[OMAP_LOGICAL_DMA_CH_COUNT]; 956 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
825 957
826 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); 958 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
827 do { 959 do {
@@ -842,18 +974,22 @@ void omap_stop_dma(int lch)
842 974
843 /* Disable all interrupts on the channel */ 975 /* Disable all interrupts on the channel */
844 if (cpu_class_is_omap1()) 976 if (cpu_class_is_omap1())
845 OMAP_DMA_CICR_REG(lch) = 0; 977 dma_write(0, CICR(lch));
978
979 l = dma_read(CCR(lch));
980 l &= ~OMAP_DMA_CCR_EN;
981 dma_write(l, CCR(lch));
846 982
847 OMAP_DMA_CCR_REG(lch) &= ~OMAP_DMA_CCR_EN;
848 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE; 983 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
849} 984}
985EXPORT_SYMBOL(omap_stop_dma);
850 986
851/* 987/*
852 * Allows changing the DMA callback function or data. This may be needed if 988 * Allows changing the DMA callback function or data. This may be needed if
853 * the driver shares a single DMA channel for multiple dma triggers. 989 * the driver shares a single DMA channel for multiple dma triggers.
854 */ 990 */
855int omap_set_dma_callback(int lch, 991int omap_set_dma_callback(int lch,
856 void (* callback)(int lch, u16 ch_status, void *data), 992 void (*callback)(int lch, u16 ch_status, void *data),
857 void *data) 993 void *data)
858{ 994{
859 unsigned long flags; 995 unsigned long flags;
@@ -873,6 +1009,7 @@ int omap_set_dma_callback(int lch,
873 1009
874 return 0; 1010 return 0;
875} 1011}
1012EXPORT_SYMBOL(omap_set_dma_callback);
876 1013
877/* 1014/*
878 * Returns current physical source address for the given DMA channel. 1015 * Returns current physical source address for the given DMA channel.
@@ -886,15 +1023,24 @@ dma_addr_t omap_get_dma_src_pos(int lch)
886{ 1023{
887 dma_addr_t offset = 0; 1024 dma_addr_t offset = 0;
888 1025
889 if (cpu_class_is_omap1()) 1026 if (cpu_is_omap15xx())
890 offset = (dma_addr_t) (OMAP1_DMA_CSSA_L_REG(lch) | 1027 offset = dma_read(CPC(lch));
891 (OMAP1_DMA_CSSA_U_REG(lch) << 16)); 1028 else
1029 offset = dma_read(CSAC(lch));
892 1030
893 if (cpu_class_is_omap2()) 1031 /*
894 offset = OMAP_DMA_CSAC_REG(lch); 1032 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1033 * read before the DMA controller finished disabling the channel.
1034 */
1035 if (!cpu_is_omap15xx() && offset == 0)
1036 offset = dma_read(CSAC(lch));
1037
1038 if (cpu_class_is_omap1())
1039 offset |= (dma_read(CSSA_U(lch)) << 16);
895 1040
896 return offset; 1041 return offset;
897} 1042}
1043EXPORT_SYMBOL(omap_get_dma_src_pos);
898 1044
899/* 1045/*
900 * Returns current physical destination address for the given DMA channel. 1046 * Returns current physical destination address for the given DMA channel.
@@ -908,25 +1054,30 @@ dma_addr_t omap_get_dma_dst_pos(int lch)
908{ 1054{
909 dma_addr_t offset = 0; 1055 dma_addr_t offset = 0;
910 1056
911 if (cpu_class_is_omap1()) 1057 if (cpu_is_omap15xx())
912 offset = (dma_addr_t) (OMAP1_DMA_CDSA_L_REG(lch) | 1058 offset = dma_read(CPC(lch));
913 (OMAP1_DMA_CDSA_U_REG(lch) << 16)); 1059 else
1060 offset = dma_read(CDAC(lch));
914 1061
915 if (cpu_class_is_omap2()) 1062 /*
916 offset = OMAP_DMA_CDAC_REG(lch); 1063 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1064 * read before the DMA controller finished disabling the channel.
1065 */
1066 if (!cpu_is_omap15xx() && offset == 0)
1067 offset = dma_read(CDAC(lch));
1068
1069 if (cpu_class_is_omap1())
1070 offset |= (dma_read(CDSA_U(lch)) << 16);
917 1071
918 return offset; 1072 return offset;
919} 1073}
1074EXPORT_SYMBOL(omap_get_dma_dst_pos);
920 1075
921/* 1076int omap_get_dma_active_status(int lch)
922 * Returns current source transfer counting for the given DMA channel.
923 * Can be used to monitor the progress of a transfer inside a block.
924 * It must be called with disabled interrupts.
925 */
926int omap_get_dma_src_addr_counter(int lch)
927{ 1077{
928 return (dma_addr_t) OMAP_DMA_CSAC_REG(lch); 1078 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
929} 1079}
1080EXPORT_SYMBOL(omap_get_dma_active_status);
930 1081
931int omap_dma_running(void) 1082int omap_dma_running(void)
932{ 1083{
@@ -938,7 +1089,7 @@ int omap_dma_running(void)
938 return 1; 1089 return 1;
939 1090
940 for (lch = 0; lch < dma_chan_count; lch++) 1091 for (lch = 0; lch < dma_chan_count; lch++)
941 if (OMAP_DMA_CCR_REG(lch) & OMAP_DMA_CCR_EN) 1092 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
942 return 1; 1093 return 1;
943 1094
944 return 0; 1095 return 0;
@@ -949,7 +1100,7 @@ int omap_dma_running(void)
949 * For this DMA link to start, you still need to start (see omap_start_dma) 1100 * For this DMA link to start, you still need to start (see omap_start_dma)
950 * the first one. That will fire up the entire queue. 1101 * the first one. That will fire up the entire queue.
951 */ 1102 */
952void omap_dma_link_lch (int lch_head, int lch_queue) 1103void omap_dma_link_lch(int lch_head, int lch_queue)
953{ 1104{
954 if (omap_dma_in_1510_mode()) { 1105 if (omap_dma_in_1510_mode()) {
955 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1106 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -966,11 +1117,12 @@ void omap_dma_link_lch (int lch_head, int lch_queue)
966 1117
967 dma_chan[lch_head].next_lch = lch_queue; 1118 dma_chan[lch_head].next_lch = lch_queue;
968} 1119}
1120EXPORT_SYMBOL(omap_dma_link_lch);
969 1121
970/* 1122/*
971 * Once the DMA queue is stopped, we can destroy it. 1123 * Once the DMA queue is stopped, we can destroy it.
972 */ 1124 */
973void omap_dma_unlink_lch (int lch_head, int lch_queue) 1125void omap_dma_unlink_lch(int lch_head, int lch_queue)
974{ 1126{
975 if (omap_dma_in_1510_mode()) { 1127 if (omap_dma_in_1510_mode()) {
976 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n"); 1128 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
@@ -985,7 +1137,6 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
985 dump_stack(); 1137 dump_stack();
986 } 1138 }
987 1139
988
989 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) || 1140 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
990 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) { 1141 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
991 printk(KERN_ERR "omap_dma: You need to stop the DMA channels " 1142 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
@@ -995,12 +1146,15 @@ void omap_dma_unlink_lch (int lch_head, int lch_queue)
995 1146
996 dma_chan[lch_head].next_lch = -1; 1147 dma_chan[lch_head].next_lch = -1;
997} 1148}
1149EXPORT_SYMBOL(omap_dma_unlink_lch);
1150
1151/*----------------------------------------------------------------------------*/
998 1152
999#ifndef CONFIG_ARCH_OMAP1 1153#ifndef CONFIG_ARCH_OMAP1
1000/* Create chain of DMA channesls */ 1154/* Create chain of DMA channesls */
1001static void create_dma_lch_chain(int lch_head, int lch_queue) 1155static void create_dma_lch_chain(int lch_head, int lch_queue)
1002{ 1156{
1003 u32 w; 1157 u32 l;
1004 1158
1005 /* Check if this is the first link in chain */ 1159 /* Check if this is the first link in chain */
1006 if (dma_chan[lch_head].next_linked_ch == -1) { 1160 if (dma_chan[lch_head].next_linked_ch == -1) {
@@ -1020,15 +1174,15 @@ static void create_dma_lch_chain(int lch_head, int lch_queue)
1020 lch_queue; 1174 lch_queue;
1021 } 1175 }
1022 1176
1023 w = OMAP_DMA_CLNK_CTRL_REG(lch_head); 1177 l = dma_read(CLNK_CTRL(lch_head));
1024 w &= ~(0x1f); 1178 l &= ~(0x1f);
1025 w |= lch_queue; 1179 l |= lch_queue;
1026 OMAP_DMA_CLNK_CTRL_REG(lch_head) = w; 1180 dma_write(l, CLNK_CTRL(lch_head));
1027 1181
1028 w = OMAP_DMA_CLNK_CTRL_REG(lch_queue); 1182 l = dma_read(CLNK_CTRL(lch_queue));
1029 w &= ~(0x1f); 1183 l &= ~(0x1f);
1030 w |= (dma_chan[lch_queue].next_linked_ch); 1184 l |= (dma_chan[lch_queue].next_linked_ch);
1031 OMAP_DMA_CLNK_CTRL_REG(lch_queue) = w; 1185 dma_write(l, CLNK_CTRL(lch_queue));
1032} 1186}
1033 1187
1034/** 1188/**
@@ -1063,7 +1217,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1063 } 1217 }
1064 1218
1065 if (unlikely((no_of_chans < 1 1219 if (unlikely((no_of_chans < 1
1066 || no_of_chans > OMAP_LOGICAL_DMA_CH_COUNT))) { 1220 || no_of_chans > dma_lch_count))) {
1067 printk(KERN_ERR "Invalid Number of channels requested\n"); 1221 printk(KERN_ERR "Invalid Number of channels requested\n");
1068 return -EINVAL; 1222 return -EINVAL;
1069 } 1223 }
@@ -1118,6 +1272,7 @@ int omap_request_dma_chain(int dev_id, const char *dev_name,
1118 for (i = 0; i < (no_of_chans - 1); i++) 1272 for (i = 0; i < (no_of_chans - 1); i++)
1119 create_dma_lch_chain(channels[i], channels[i + 1]); 1273 create_dma_lch_chain(channels[i], channels[i + 1]);
1120 } 1274 }
1275
1121 return 0; 1276 return 0;
1122} 1277}
1123EXPORT_SYMBOL(omap_request_dma_chain); 1278EXPORT_SYMBOL(omap_request_dma_chain);
@@ -1140,7 +1295,7 @@ int omap_modify_dma_chain_params(int chain_id,
1140 1295
1141 /* Check for input params */ 1296 /* Check for input params */
1142 if (unlikely((chain_id < 0 1297 if (unlikely((chain_id < 0
1143 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1298 || chain_id >= dma_lch_count))) {
1144 printk(KERN_ERR "Invalid chain id\n"); 1299 printk(KERN_ERR "Invalid chain id\n");
1145 return -EINVAL; 1300 return -EINVAL;
1146 } 1301 }
@@ -1160,6 +1315,7 @@ int omap_modify_dma_chain_params(int chain_id,
1160 */ 1315 */
1161 omap_set_dma_params(channels[i], &params); 1316 omap_set_dma_params(channels[i], &params);
1162 } 1317 }
1318
1163 return 0; 1319 return 0;
1164} 1320}
1165EXPORT_SYMBOL(omap_modify_dma_chain_params); 1321EXPORT_SYMBOL(omap_modify_dma_chain_params);
@@ -1178,7 +1334,7 @@ int omap_free_dma_chain(int chain_id)
1178 u32 i; 1334 u32 i;
1179 1335
1180 /* Check for input params */ 1336 /* Check for input params */
1181 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1337 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1182 printk(KERN_ERR "Invalid chain id\n"); 1338 printk(KERN_ERR "Invalid chain id\n");
1183 return -EINVAL; 1339 return -EINVAL;
1184 } 1340 }
@@ -1203,6 +1359,7 @@ int omap_free_dma_chain(int chain_id)
1203 dma_linked_lch[chain_id].linked_dmach_q = NULL; 1359 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1204 dma_linked_lch[chain_id].chain_mode = -1; 1360 dma_linked_lch[chain_id].chain_mode = -1;
1205 dma_linked_lch[chain_id].chain_state = -1; 1361 dma_linked_lch[chain_id].chain_state = -1;
1362
1206 return (0); 1363 return (0);
1207} 1364}
1208EXPORT_SYMBOL(omap_free_dma_chain); 1365EXPORT_SYMBOL(omap_free_dma_chain);
@@ -1218,7 +1375,7 @@ EXPORT_SYMBOL(omap_free_dma_chain);
1218int omap_dma_chain_status(int chain_id) 1375int omap_dma_chain_status(int chain_id)
1219{ 1376{
1220 /* Check for input params */ 1377 /* Check for input params */
1221 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1378 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1222 printk(KERN_ERR "Invalid chain id\n"); 1379 printk(KERN_ERR "Invalid chain id\n");
1223 return -EINVAL; 1380 return -EINVAL;
1224 } 1381 }
@@ -1233,6 +1390,7 @@ int omap_dma_chain_status(int chain_id)
1233 1390
1234 if (OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1391 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1235 return OMAP_DMA_CHAIN_INACTIVE; 1392 return OMAP_DMA_CHAIN_INACTIVE;
1393
1236 return OMAP_DMA_CHAIN_ACTIVE; 1394 return OMAP_DMA_CHAIN_ACTIVE;
1237} 1395}
1238EXPORT_SYMBOL(omap_dma_chain_status); 1396EXPORT_SYMBOL(omap_dma_chain_status);
@@ -1255,11 +1413,13 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1255 int elem_count, int frame_count, void *callbk_data) 1413 int elem_count, int frame_count, void *callbk_data)
1256{ 1414{
1257 int *channels; 1415 int *channels;
1258 u32 w, lch; 1416 u32 l, lch;
1259 int start_dma = 0; 1417 int start_dma = 0;
1260 1418
1261 /* if buffer size is less than 1 then there is 1419 /*
1262 * no use of starting the chain */ 1420 * if buffer size is less than 1 then there is
1421 * no use of starting the chain
1422 */
1263 if (elem_count < 1) { 1423 if (elem_count < 1) {
1264 printk(KERN_ERR "Invalid buffer size\n"); 1424 printk(KERN_ERR "Invalid buffer size\n");
1265 return -EINVAL; 1425 return -EINVAL;
@@ -1267,7 +1427,7 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1267 1427
1268 /* Check for input params */ 1428 /* Check for input params */
1269 if (unlikely((chain_id < 0 1429 if (unlikely((chain_id < 0
1270 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1430 || chain_id >= dma_lch_count))) {
1271 printk(KERN_ERR "Invalid chain id\n"); 1431 printk(KERN_ERR "Invalid chain id\n");
1272 return -EINVAL; 1432 return -EINVAL;
1273 } 1433 }
@@ -1296,20 +1456,24 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1296 1456
1297 /* Set the params to the free channel */ 1457 /* Set the params to the free channel */
1298 if (src_start != 0) 1458 if (src_start != 0)
1299 OMAP2_DMA_CSSA_REG(lch) = src_start; 1459 dma_write(src_start, CSSA(lch));
1300 if (dest_start != 0) 1460 if (dest_start != 0)
1301 OMAP2_DMA_CDSA_REG(lch) = dest_start; 1461 dma_write(dest_start, CDSA(lch));
1302 1462
1303 /* Write the buffer size */ 1463 /* Write the buffer size */
1304 OMAP_DMA_CEN_REG(lch) = elem_count; 1464 dma_write(elem_count, CEN(lch));
1305 OMAP_DMA_CFN_REG(lch) = frame_count; 1465 dma_write(frame_count, CFN(lch));
1306 1466
1307 /* If the chain is dynamically linked, 1467 /*
1308 * then we may have to start the chain if its not active */ 1468 * If the chain is dynamically linked,
1469 * then we may have to start the chain if its not active
1470 */
1309 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) { 1471 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1310 1472
1311 /* In Dynamic chain, if the chain is not started, 1473 /*
1312 * queue the channel */ 1474 * In Dynamic chain, if the chain is not started,
1475 * queue the channel
1476 */
1313 if (dma_linked_lch[chain_id].chain_state == 1477 if (dma_linked_lch[chain_id].chain_state ==
1314 DMA_CHAIN_NOTSTARTED) { 1478 DMA_CHAIN_NOTSTARTED) {
1315 /* Enable the link in previous channel */ 1479 /* Enable the link in previous channel */
@@ -1319,8 +1483,10 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1319 dma_chan[lch].state = DMA_CH_QUEUED; 1483 dma_chan[lch].state = DMA_CH_QUEUED;
1320 } 1484 }
1321 1485
1322 /* Chain is already started, make sure its active, 1486 /*
1323 * if not then start the chain */ 1487 * Chain is already started, make sure its active,
1488 * if not then start the chain
1489 */
1324 else { 1490 else {
1325 start_dma = 1; 1491 start_dma = 1;
1326 1492
@@ -1329,8 +1495,8 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1329 enable_lnk(dma_chan[lch].prev_linked_ch); 1495 enable_lnk(dma_chan[lch].prev_linked_ch);
1330 dma_chan[lch].state = DMA_CH_QUEUED; 1496 dma_chan[lch].state = DMA_CH_QUEUED;
1331 start_dma = 0; 1497 start_dma = 0;
1332 if (0 == ((1 << 7) & (OMAP_DMA_CCR_REG 1498 if (0 == ((1 << 7) & dma_read(
1333 (dma_chan[lch].prev_linked_ch)))) { 1499 CCR(dma_chan[lch].prev_linked_ch)))) {
1334 disable_lnk(dma_chan[lch]. 1500 disable_lnk(dma_chan[lch].
1335 prev_linked_ch); 1501 prev_linked_ch);
1336 pr_debug("\n prev ch is stopped\n"); 1502 pr_debug("\n prev ch is stopped\n");
@@ -1346,27 +1512,28 @@ int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1346 } 1512 }
1347 omap_enable_channel_irq(lch); 1513 omap_enable_channel_irq(lch);
1348 1514
1349 w = OMAP_DMA_CCR_REG(lch); 1515 l = dma_read(CCR(lch));
1350 1516
1351 if ((0 == (w & (1 << 24)))) 1517 if ((0 == (l & (1 << 24))))
1352 w &= ~(1 << 25); 1518 l &= ~(1 << 25);
1353 else 1519 else
1354 w |= (1 << 25); 1520 l |= (1 << 25);
1355 if (start_dma == 1) { 1521 if (start_dma == 1) {
1356 if (0 == (w & (1 << 7))) { 1522 if (0 == (l & (1 << 7))) {
1357 w |= (1 << 7); 1523 l |= (1 << 7);
1358 dma_chan[lch].state = DMA_CH_STARTED; 1524 dma_chan[lch].state = DMA_CH_STARTED;
1359 pr_debug("starting %d\n", lch); 1525 pr_debug("starting %d\n", lch);
1360 OMAP_DMA_CCR_REG(lch) = w; 1526 dma_write(l, CCR(lch));
1361 } else 1527 } else
1362 start_dma = 0; 1528 start_dma = 0;
1363 } else { 1529 } else {
1364 if (0 == (w & (1 << 7))) 1530 if (0 == (l & (1 << 7)))
1365 OMAP_DMA_CCR_REG(lch) = w; 1531 dma_write(l, CCR(lch));
1366 } 1532 }
1367 dma_chan[lch].flags |= OMAP_DMA_ACTIVE; 1533 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1368 } 1534 }
1369 } 1535 }
1536
1370 return 0; 1537 return 0;
1371} 1538}
1372EXPORT_SYMBOL(omap_dma_chain_a_transfer); 1539EXPORT_SYMBOL(omap_dma_chain_a_transfer);
@@ -1382,9 +1549,9 @@ EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1382int omap_start_dma_chain_transfers(int chain_id) 1549int omap_start_dma_chain_transfers(int chain_id)
1383{ 1550{
1384 int *channels; 1551 int *channels;
1385 u32 w, i; 1552 u32 l, i;
1386 1553
1387 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1554 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1388 printk(KERN_ERR "Invalid chain id\n"); 1555 printk(KERN_ERR "Invalid chain id\n");
1389 return -EINVAL; 1556 return -EINVAL;
1390 } 1557 }
@@ -1406,18 +1573,19 @@ int omap_start_dma_chain_transfers(int chain_id)
1406 omap_enable_channel_irq(channels[0]); 1573 omap_enable_channel_irq(channels[0]);
1407 } 1574 }
1408 1575
1409 w = OMAP_DMA_CCR_REG(channels[0]); 1576 l = dma_read(CCR(channels[0]));
1410 w |= (1 << 7); 1577 l |= (1 << 7);
1411 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED; 1578 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1412 dma_chan[channels[0]].state = DMA_CH_STARTED; 1579 dma_chan[channels[0]].state = DMA_CH_STARTED;
1413 1580
1414 if ((0 == (w & (1 << 24)))) 1581 if ((0 == (l & (1 << 24))))
1415 w &= ~(1 << 25); 1582 l &= ~(1 << 25);
1416 else 1583 else
1417 w |= (1 << 25); 1584 l |= (1 << 25);
1418 OMAP_DMA_CCR_REG(channels[0]) = w; 1585 dma_write(l, CCR(channels[0]));
1419 1586
1420 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE; 1587 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
1588
1421 return 0; 1589 return 0;
1422} 1590}
1423EXPORT_SYMBOL(omap_start_dma_chain_transfers); 1591EXPORT_SYMBOL(omap_start_dma_chain_transfers);
@@ -1433,11 +1601,11 @@ EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1433int omap_stop_dma_chain_transfers(int chain_id) 1601int omap_stop_dma_chain_transfers(int chain_id)
1434{ 1602{
1435 int *channels; 1603 int *channels;
1436 u32 w, i; 1604 u32 l, i;
1437 u32 sys_cf; 1605 u32 sys_cf;
1438 1606
1439 /* Check for input params */ 1607 /* Check for input params */
1440 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1608 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1441 printk(KERN_ERR "Invalid chain id\n"); 1609 printk(KERN_ERR "Invalid chain id\n");
1442 return -EINVAL; 1610 return -EINVAL;
1443 } 1611 }
@@ -1449,21 +1617,22 @@ int omap_stop_dma_chain_transfers(int chain_id)
1449 } 1617 }
1450 channels = dma_linked_lch[chain_id].linked_dmach_q; 1618 channels = dma_linked_lch[chain_id].linked_dmach_q;
1451 1619
1452 /* DMA Errata: 1620 /*
1621 * DMA Errata:
1453 * Special programming model needed to disable DMA before end of block 1622 * Special programming model needed to disable DMA before end of block
1454 */ 1623 */
1455 sys_cf = omap_readl(OMAP_DMA4_OCP_SYSCONFIG); 1624 sys_cf = dma_read(OCP_SYSCONFIG);
1456 w = sys_cf; 1625 l = sys_cf;
1457 /* Middle mode reg set no Standby */ 1626 /* Middle mode reg set no Standby */
1458 w &= ~((1 << 12)|(1 << 13)); 1627 l &= ~((1 << 12)|(1 << 13));
1459 omap_writel(w, OMAP_DMA4_OCP_SYSCONFIG); 1628 dma_write(l, OCP_SYSCONFIG);
1460 1629
1461 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) { 1630 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1462 1631
1463 /* Stop the Channel transmission */ 1632 /* Stop the Channel transmission */
1464 w = OMAP_DMA_CCR_REG(channels[i]); 1633 l = dma_read(CCR(channels[i]));
1465 w &= ~(1 << 7); 1634 l &= ~(1 << 7);
1466 OMAP_DMA_CCR_REG(channels[i]) = w; 1635 dma_write(l, CCR(channels[i]));
1467 1636
1468 /* Disable the link in all the channels */ 1637 /* Disable the link in all the channels */
1469 disable_lnk(channels[i]); 1638 disable_lnk(channels[i]);
@@ -1476,7 +1645,8 @@ int omap_stop_dma_chain_transfers(int chain_id)
1476 OMAP_DMA_CHAIN_QINIT(chain_id); 1645 OMAP_DMA_CHAIN_QINIT(chain_id);
1477 1646
1478 /* Errata - put in the old value */ 1647 /* Errata - put in the old value */
1479 omap_writel(sys_cf, OMAP_DMA4_OCP_SYSCONFIG); 1648 dma_write(sys_cf, OCP_SYSCONFIG);
1649
1480 return 0; 1650 return 0;
1481} 1651}
1482EXPORT_SYMBOL(omap_stop_dma_chain_transfers); 1652EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
@@ -1499,7 +1669,7 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1499 int *channels; 1669 int *channels;
1500 1670
1501 /* Check for input params */ 1671 /* Check for input params */
1502 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1672 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1503 printk(KERN_ERR "Invalid chain id\n"); 1673 printk(KERN_ERR "Invalid chain id\n");
1504 return -EINVAL; 1674 return -EINVAL;
1505 } 1675 }
@@ -1517,8 +1687,8 @@ int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1517 /* Get the current channel */ 1687 /* Get the current channel */
1518 lch = channels[dma_linked_lch[chain_id].q_head]; 1688 lch = channels[dma_linked_lch[chain_id].q_head];
1519 1689
1520 *ei = OMAP2_DMA_CCEN_REG(lch); 1690 *ei = dma_read(CCEN(lch));
1521 *fi = OMAP2_DMA_CCFN_REG(lch); 1691 *fi = dma_read(CCFN(lch));
1522 1692
1523 return 0; 1693 return 0;
1524} 1694}
@@ -1539,7 +1709,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1539 int *channels; 1709 int *channels;
1540 1710
1541 /* Check for input params */ 1711 /* Check for input params */
1542 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1712 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1543 printk(KERN_ERR "Invalid chain id\n"); 1713 printk(KERN_ERR "Invalid chain id\n");
1544 return -EINVAL; 1714 return -EINVAL;
1545 } 1715 }
@@ -1555,7 +1725,7 @@ int omap_get_dma_chain_dst_pos(int chain_id)
1555 /* Get the current channel */ 1725 /* Get the current channel */
1556 lch = channels[dma_linked_lch[chain_id].q_head]; 1726 lch = channels[dma_linked_lch[chain_id].q_head];
1557 1727
1558 return (OMAP_DMA_CDAC_REG(lch)); 1728 return dma_read(CDAC(lch));
1559} 1729}
1560EXPORT_SYMBOL(omap_get_dma_chain_dst_pos); 1730EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1561 1731
@@ -1573,7 +1743,7 @@ int omap_get_dma_chain_src_pos(int chain_id)
1573 int *channels; 1743 int *channels;
1574 1744
1575 /* Check for input params */ 1745 /* Check for input params */
1576 if (unlikely((chain_id < 0 || chain_id >= OMAP_LOGICAL_DMA_CH_COUNT))) { 1746 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
1577 printk(KERN_ERR "Invalid chain id\n"); 1747 printk(KERN_ERR "Invalid chain id\n");
1578 return -EINVAL; 1748 return -EINVAL;
1579 } 1749 }
@@ -1589,10 +1759,10 @@ int omap_get_dma_chain_src_pos(int chain_id)
1589 /* Get the current channel */ 1759 /* Get the current channel */
1590 lch = channels[dma_linked_lch[chain_id].q_head]; 1760 lch = channels[dma_linked_lch[chain_id].q_head];
1591 1761
1592 return (OMAP_DMA_CSAC_REG(lch)); 1762 return dma_read(CSAC(lch));
1593} 1763}
1594EXPORT_SYMBOL(omap_get_dma_chain_src_pos); 1764EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1595#endif 1765#endif /* ifndef CONFIG_ARCH_OMAP1 */
1596 1766
1597/*----------------------------------------------------------------------------*/ 1767/*----------------------------------------------------------------------------*/
1598 1768
@@ -1600,13 +1770,13 @@ EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
1600 1770
1601static int omap1_dma_handle_ch(int ch) 1771static int omap1_dma_handle_ch(int ch)
1602{ 1772{
1603 u16 csr; 1773 u32 csr;
1604 1774
1605 if (enable_1510_mode && ch >= 6) { 1775 if (enable_1510_mode && ch >= 6) {
1606 csr = dma_chan[ch].saved_csr; 1776 csr = dma_chan[ch].saved_csr;
1607 dma_chan[ch].saved_csr = 0; 1777 dma_chan[ch].saved_csr = 0;
1608 } else 1778 } else
1609 csr = OMAP_DMA_CSR_REG(ch); 1779 csr = dma_read(CSR(ch));
1610 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) { 1780 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1611 dma_chan[ch + 6].saved_csr = csr >> 7; 1781 dma_chan[ch + 6].saved_csr = csr >> 7;
1612 csr &= 0x7f; 1782 csr &= 0x7f;
@@ -1628,6 +1798,7 @@ static int omap1_dma_handle_ch(int ch)
1628 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE; 1798 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1629 if (likely(dma_chan[ch].callback != NULL)) 1799 if (likely(dma_chan[ch].callback != NULL))
1630 dma_chan[ch].callback(ch, csr, dma_chan[ch].data); 1800 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
1801
1631 return 1; 1802 return 1;
1632} 1803}
1633 1804
@@ -1658,12 +1829,13 @@ static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1658 1829
1659static int omap2_dma_handle_ch(int ch) 1830static int omap2_dma_handle_ch(int ch)
1660{ 1831{
1661 u32 status = OMAP_DMA_CSR_REG(ch); 1832 u32 status = dma_read(CSR(ch));
1662 1833
1663 if (!status) { 1834 if (!status) {
1664 if (printk_ratelimit()) 1835 if (printk_ratelimit())
1665 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch); 1836 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1666 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1837 ch);
1838 dma_write(1 << ch, IRQSTATUS_L0);
1667 return 0; 1839 return 0;
1668 } 1840 }
1669 if (unlikely(dma_chan[ch].dev_id == -1)) { 1841 if (unlikely(dma_chan[ch].dev_id == -1)) {
@@ -1686,14 +1858,14 @@ static int omap2_dma_handle_ch(int ch)
1686 printk(KERN_INFO "DMA misaligned error with device %d\n", 1858 printk(KERN_INFO "DMA misaligned error with device %d\n",
1687 dma_chan[ch].dev_id); 1859 dma_chan[ch].dev_id);
1688 1860
1689 OMAP_DMA_CSR_REG(ch) = OMAP2_DMA_CSR_CLEAR_MASK; 1861 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1690 omap_writel(1 << ch, OMAP_DMA4_IRQSTATUS_L0); 1862 dma_write(1 << ch, IRQSTATUS_L0);
1691 1863
1692 /* If the ch is not chained then chain_id will be -1 */ 1864 /* If the ch is not chained then chain_id will be -1 */
1693 if (dma_chan[ch].chain_id != -1) { 1865 if (dma_chan[ch].chain_id != -1) {
1694 int chain_id = dma_chan[ch].chain_id; 1866 int chain_id = dma_chan[ch].chain_id;
1695 dma_chan[ch].state = DMA_CH_NOTSTARTED; 1867 dma_chan[ch].state = DMA_CH_NOTSTARTED;
1696 if (OMAP_DMA_CLNK_CTRL_REG(ch) & (1 << 15)) 1868 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
1697 dma_chan[dma_chan[ch].next_linked_ch].state = 1869 dma_chan[dma_chan[ch].next_linked_ch].state =
1698 DMA_CH_STARTED; 1870 DMA_CH_STARTED;
1699 if (dma_linked_lch[chain_id].chain_mode == 1871 if (dma_linked_lch[chain_id].chain_mode ==
@@ -1703,13 +1875,13 @@ static int omap2_dma_handle_ch(int ch)
1703 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id)) 1875 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1704 OMAP_DMA_CHAIN_INCQHEAD(chain_id); 1876 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1705 1877
1706 status = OMAP_DMA_CSR_REG(ch); 1878 status = dma_read(CSR(ch));
1707 } 1879 }
1708 1880
1709 if (likely(dma_chan[ch].callback != NULL)) 1881 if (likely(dma_chan[ch].callback != NULL))
1710 dma_chan[ch].callback(ch, status, dma_chan[ch].data); 1882 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
1711 1883
1712 OMAP_DMA_CSR_REG(ch) = status; 1884 dma_write(status, CSR(ch));
1713 1885
1714 return 0; 1886 return 0;
1715} 1887}
@@ -1720,13 +1892,13 @@ static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1720 u32 val; 1892 u32 val;
1721 int i; 1893 int i;
1722 1894
1723 val = omap_readl(OMAP_DMA4_IRQSTATUS_L0); 1895 val = dma_read(IRQSTATUS_L0);
1724 if (val == 0) { 1896 if (val == 0) {
1725 if (printk_ratelimit()) 1897 if (printk_ratelimit())
1726 printk(KERN_WARNING "Spurious DMA IRQ\n"); 1898 printk(KERN_WARNING "Spurious DMA IRQ\n");
1727 return IRQ_HANDLED; 1899 return IRQ_HANDLED;
1728 } 1900 }
1729 for (i = 0; i < OMAP_LOGICAL_DMA_CH_COUNT && val != 0; i++) { 1901 for (i = 0; i < dma_lch_count && val != 0; i++) {
1730 if (val & 1) 1902 if (val & 1)
1731 omap2_dma_handle_ch(i); 1903 omap2_dma_handle_ch(i);
1732 val >>= 1; 1904 val >>= 1;
@@ -1750,7 +1922,7 @@ static struct irqaction omap24xx_dma_irq;
1750static struct lcd_dma_info { 1922static struct lcd_dma_info {
1751 spinlock_t lock; 1923 spinlock_t lock;
1752 int reserved; 1924 int reserved;
1753 void (* callback)(u16 status, void *data); 1925 void (*callback)(u16 status, void *data);
1754 void *cb_data; 1926 void *cb_data;
1755 1927
1756 int active; 1928 int active;
@@ -1772,6 +1944,7 @@ void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1772 lcd_dma.xres = fb_xres; 1944 lcd_dma.xres = fb_xres;
1773 lcd_dma.yres = fb_yres; 1945 lcd_dma.yres = fb_yres;
1774} 1946}
1947EXPORT_SYMBOL(omap_set_lcd_dma_b1);
1775 1948
1776void omap_set_lcd_dma_src_port(int port) 1949void omap_set_lcd_dma_src_port(int port)
1777{ 1950{
@@ -1782,12 +1955,13 @@ void omap_set_lcd_dma_ext_controller(int external)
1782{ 1955{
1783 lcd_dma.ext_ctrl = external; 1956 lcd_dma.ext_ctrl = external;
1784} 1957}
1958EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
1785 1959
1786void omap_set_lcd_dma_single_transfer(int single) 1960void omap_set_lcd_dma_single_transfer(int single)
1787{ 1961{
1788 lcd_dma.single_transfer = single; 1962 lcd_dma.single_transfer = single;
1789} 1963}
1790 1964EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
1791 1965
1792void omap_set_lcd_dma_b1_rotation(int rotate) 1966void omap_set_lcd_dma_b1_rotation(int rotate)
1793{ 1967{
@@ -1798,6 +1972,7 @@ void omap_set_lcd_dma_b1_rotation(int rotate)
1798 } 1972 }
1799 lcd_dma.rotate = rotate; 1973 lcd_dma.rotate = rotate;
1800} 1974}
1975EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
1801 1976
1802void omap_set_lcd_dma_b1_mirror(int mirror) 1977void omap_set_lcd_dma_b1_mirror(int mirror)
1803{ 1978{
@@ -1807,6 +1982,7 @@ void omap_set_lcd_dma_b1_mirror(int mirror)
1807 } 1982 }
1808 lcd_dma.mirror = mirror; 1983 lcd_dma.mirror = mirror;
1809} 1984}
1985EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
1810 1986
1811void omap_set_lcd_dma_b1_vxres(unsigned long vxres) 1987void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1812{ 1988{
@@ -1817,6 +1993,7 @@ void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
1817 } 1993 }
1818 lcd_dma.vxres = vxres; 1994 lcd_dma.vxres = vxres;
1819} 1995}
1996EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
1820 1997
1821void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale) 1998void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1822{ 1999{
@@ -1827,6 +2004,7 @@ void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
1827 lcd_dma.xscale = xscale; 2004 lcd_dma.xscale = xscale;
1828 lcd_dma.yscale = yscale; 2005 lcd_dma.yscale = yscale;
1829} 2006}
2007EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
1830 2008
1831static void set_b1_regs(void) 2009static void set_b1_regs(void)
1832{ 2010{
@@ -1857,8 +2035,11 @@ static void set_b1_regs(void)
1857 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1; 2035 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
1858 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1; 2036 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
1859 BUG_ON(vxres < lcd_dma.xres); 2037 BUG_ON(vxres < lcd_dma.xres);
1860#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es) 2038
2039#define PIXADDR(x, y) (lcd_dma.addr + \
2040 ((y) * vxres * yscale + (x) * xscale) * es)
1861#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1) 2041#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
2042
1862 switch (lcd_dma.rotate) { 2043 switch (lcd_dma.rotate) {
1863 case 0: 2044 case 0:
1864 if (!lcd_dma.mirror) { 2045 if (!lcd_dma.mirror) {
@@ -1867,8 +2048,8 @@ static void set_b1_regs(void)
1867 /* 1510 DMA requires the bottom address to be 2 more 2048 /* 1510 DMA requires the bottom address to be 2 more
1868 * than the actual last memory access location. */ 2049 * than the actual last memory access location. */
1869 if (omap_dma_in_1510_mode() && 2050 if (omap_dma_in_1510_mode() &&
1870 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32) 2051 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
1871 bottom += 2; 2052 bottom += 2;
1872 ei = PIXSTEP(0, 0, 1, 0); 2053 ei = PIXSTEP(0, 0, 1, 0);
1873 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1); 2054 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
1874 } else { 2055 } else {
@@ -1995,7 +2176,7 @@ static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
1995 return IRQ_HANDLED; 2176 return IRQ_HANDLED;
1996} 2177}
1997 2178
1998int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 2179int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
1999 void *data) 2180 void *data)
2000{ 2181{
2001 spin_lock_irq(&lcd_dma.lock); 2182 spin_lock_irq(&lcd_dma.lock);
@@ -2021,6 +2202,7 @@ int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
2021 2202
2022 return 0; 2203 return 0;
2023} 2204}
2205EXPORT_SYMBOL(omap_request_lcd_dma);
2024 2206
2025void omap_free_lcd_dma(void) 2207void omap_free_lcd_dma(void)
2026{ 2208{
@@ -2037,12 +2219,14 @@ void omap_free_lcd_dma(void)
2037 lcd_dma.reserved = 0; 2219 lcd_dma.reserved = 0;
2038 spin_unlock(&lcd_dma.lock); 2220 spin_unlock(&lcd_dma.lock);
2039} 2221}
2222EXPORT_SYMBOL(omap_free_lcd_dma);
2040 2223
2041void omap_enable_lcd_dma(void) 2224void omap_enable_lcd_dma(void)
2042{ 2225{
2043 u16 w; 2226 u16 w;
2044 2227
2045 /* Set the Enable bit only if an external controller is 2228 /*
2229 * Set the Enable bit only if an external controller is
2046 * connected. Otherwise the OMAP internal controller will 2230 * connected. Otherwise the OMAP internal controller will
2047 * start the transfer when it gets enabled. 2231 * start the transfer when it gets enabled.
2048 */ 2232 */
@@ -2059,6 +2243,7 @@ void omap_enable_lcd_dma(void)
2059 w |= 1 << 7; 2243 w |= 1 << 7;
2060 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2244 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2061} 2245}
2246EXPORT_SYMBOL(omap_enable_lcd_dma);
2062 2247
2063void omap_setup_lcd_dma(void) 2248void omap_setup_lcd_dma(void)
2064{ 2249{
@@ -2074,16 +2259,18 @@ void omap_setup_lcd_dma(void)
2074 u16 w; 2259 u16 w;
2075 2260
2076 w = omap_readw(OMAP1610_DMA_LCD_CCR); 2261 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2077 /* If DMA was already active set the end_prog bit to have 2262 /*
2263 * If DMA was already active set the end_prog bit to have
2078 * the programmed register set loaded into the active 2264 * the programmed register set loaded into the active
2079 * register set. 2265 * register set.
2080 */ 2266 */
2081 w |= 1 << 11; /* End_prog */ 2267 w |= 1 << 11; /* End_prog */
2082 if (!lcd_dma.single_transfer) 2268 if (!lcd_dma.single_transfer)
2083 w |= (3 << 8); /* Auto_init, repeat */ 2269 w |= (3 << 8); /* Auto_init, repeat */
2084 omap_writew(w, OMAP1610_DMA_LCD_CCR); 2270 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2085 } 2271 }
2086} 2272}
2273EXPORT_SYMBOL(omap_setup_lcd_dma);
2087 2274
2088void omap_stop_lcd_dma(void) 2275void omap_stop_lcd_dma(void)
2089{ 2276{
@@ -2101,6 +2288,7 @@ void omap_stop_lcd_dma(void)
2101 w &= ~(1 << 8); 2288 w &= ~(1 << 8);
2102 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2289 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2103} 2290}
2291EXPORT_SYMBOL(omap_stop_lcd_dma);
2104 2292
2105/*----------------------------------------------------------------------------*/ 2293/*----------------------------------------------------------------------------*/
2106 2294
@@ -2108,27 +2296,55 @@ static int __init omap_init_dma(void)
2108{ 2296{
2109 int ch, r; 2297 int ch, r;
2110 2298
2299 if (cpu_class_is_omap1()) {
2300 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
2301 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
2302 } else if (cpu_is_omap24xx()) {
2303 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
2304 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2305 } else if (cpu_is_omap34xx()) {
2306 omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
2307 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2308 } else {
2309 pr_err("DMA init failed for unsupported omap\n");
2310 return -ENODEV;
2311 }
2312
2313 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2314 GFP_KERNEL);
2315 if (!dma_chan)
2316 return -ENOMEM;
2317
2318 if (cpu_class_is_omap2()) {
2319 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2320 dma_lch_count, GFP_KERNEL);
2321 if (!dma_linked_lch) {
2322 kfree(dma_chan);
2323 return -ENOMEM;
2324 }
2325 }
2326
2111 if (cpu_is_omap15xx()) { 2327 if (cpu_is_omap15xx()) {
2112 printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); 2328 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
2113 dma_chan_count = 9; 2329 dma_chan_count = 9;
2114 enable_1510_mode = 1; 2330 enable_1510_mode = 1;
2115 } else if (cpu_is_omap16xx() || cpu_is_omap730()) { 2331 } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
2116 printk(KERN_INFO "OMAP DMA hardware version %d\n", 2332 printk(KERN_INFO "OMAP DMA hardware version %d\n",
2117 omap_readw(OMAP_DMA_HW_ID)); 2333 dma_read(HW_ID));
2118 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", 2334 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
2119 (omap_readw(OMAP_DMA_CAPS_0_U) << 16) | 2335 (dma_read(CAPS_0_U) << 16) |
2120 omap_readw(OMAP_DMA_CAPS_0_L), 2336 dma_read(CAPS_0_L),
2121 (omap_readw(OMAP_DMA_CAPS_1_U) << 16) | 2337 (dma_read(CAPS_1_U) << 16) |
2122 omap_readw(OMAP_DMA_CAPS_1_L), 2338 dma_read(CAPS_1_L),
2123 omap_readw(OMAP_DMA_CAPS_2), omap_readw(OMAP_DMA_CAPS_3), 2339 dma_read(CAPS_2), dma_read(CAPS_3),
2124 omap_readw(OMAP_DMA_CAPS_4)); 2340 dma_read(CAPS_4));
2125 if (!enable_1510_mode) { 2341 if (!enable_1510_mode) {
2126 u16 w; 2342 u16 w;
2127 2343
2128 /* Disable OMAP 3.0/3.1 compatibility mode. */ 2344 /* Disable OMAP 3.0/3.1 compatibility mode. */
2129 w = omap_readw(OMAP_DMA_GSCR); 2345 w = dma_read(GSCR);
2130 w |= 1 << 3; 2346 w |= 1 << 3;
2131 omap_writew(w, OMAP_DMA_GSCR); 2347 dma_write(w, GSCR);
2132 dma_chan_count = 16; 2348 dma_chan_count = 16;
2133 } else 2349 } else
2134 dma_chan_count = 9; 2350 dma_chan_count = 9;
@@ -2141,19 +2357,17 @@ static int __init omap_init_dma(void)
2141 omap_writew(w, OMAP1610_DMA_LCD_CTRL); 2357 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2142 } 2358 }
2143 } else if (cpu_class_is_omap2()) { 2359 } else if (cpu_class_is_omap2()) {
2144 u8 revision = omap_readb(OMAP_DMA4_REVISION); 2360 u8 revision = dma_read(REVISION) & 0xff;
2145 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n", 2361 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2146 revision >> 4, revision & 0xf); 2362 revision >> 4, revision & 0xf);
2147 dma_chan_count = OMAP_LOGICAL_DMA_CH_COUNT; 2363 dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
2148 } else { 2364 } else {
2149 dma_chan_count = 0; 2365 dma_chan_count = 0;
2150 return 0; 2366 return 0;
2151 } 2367 }
2152 2368
2153 memset(&lcd_dma, 0, sizeof(lcd_dma));
2154 spin_lock_init(&lcd_dma.lock); 2369 spin_lock_init(&lcd_dma.lock);
2155 spin_lock_init(&dma_chan_lock); 2370 spin_lock_init(&dma_chan_lock);
2156 memset(&dma_chan, 0, sizeof(dma_chan));
2157 2371
2158 for (ch = 0; ch < dma_chan_count; ch++) { 2372 for (ch = 0; ch < dma_chan_count; ch++) {
2159 omap_clear_dma(ch); 2373 omap_clear_dma(ch);
@@ -2164,8 +2378,10 @@ static int __init omap_init_dma(void)
2164 continue; 2378 continue;
2165 2379
2166 if (cpu_class_is_omap1()) { 2380 if (cpu_class_is_omap1()) {
2167 /* request_irq() doesn't like dev_id (ie. ch) being 2381 /*
2168 * zero, so we have to kludge around this. */ 2382 * request_irq() doesn't like dev_id (ie. ch) being
2383 * zero, so we have to kludge around this.
2384 */
2169 r = request_irq(omap1_dma_irq[ch], 2385 r = request_irq(omap1_dma_irq[ch],
2170 omap1_dma_irq_handler, 0, "DMA", 2386 omap1_dma_irq_handler, 0, "DMA",
2171 (void *) (ch + 1)); 2387 (void *) (ch + 1));
@@ -2210,48 +2426,4 @@ static int __init omap_init_dma(void)
2210 2426
2211arch_initcall(omap_init_dma); 2427arch_initcall(omap_init_dma);
2212 2428
2213EXPORT_SYMBOL(omap_get_dma_src_pos);
2214EXPORT_SYMBOL(omap_get_dma_dst_pos);
2215EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
2216EXPORT_SYMBOL(omap_clear_dma);
2217EXPORT_SYMBOL(omap_set_dma_priority);
2218EXPORT_SYMBOL(omap_request_dma);
2219EXPORT_SYMBOL(omap_free_dma);
2220EXPORT_SYMBOL(omap_start_dma);
2221EXPORT_SYMBOL(omap_stop_dma);
2222EXPORT_SYMBOL(omap_set_dma_callback);
2223EXPORT_SYMBOL(omap_enable_dma_irq);
2224EXPORT_SYMBOL(omap_disable_dma_irq);
2225
2226EXPORT_SYMBOL(omap_set_dma_transfer_params);
2227EXPORT_SYMBOL(omap_set_dma_color_mode);
2228EXPORT_SYMBOL(omap_set_dma_write_mode);
2229
2230EXPORT_SYMBOL(omap_set_dma_src_params);
2231EXPORT_SYMBOL(omap_set_dma_src_index);
2232EXPORT_SYMBOL(omap_set_dma_src_data_pack);
2233EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
2234
2235EXPORT_SYMBOL(omap_set_dma_dest_params);
2236EXPORT_SYMBOL(omap_set_dma_dest_index);
2237EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
2238EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
2239
2240EXPORT_SYMBOL(omap_set_dma_params);
2241
2242EXPORT_SYMBOL(omap_dma_link_lch);
2243EXPORT_SYMBOL(omap_dma_unlink_lch);
2244
2245EXPORT_SYMBOL(omap_request_lcd_dma);
2246EXPORT_SYMBOL(omap_free_lcd_dma);
2247EXPORT_SYMBOL(omap_enable_lcd_dma);
2248EXPORT_SYMBOL(omap_setup_lcd_dma);
2249EXPORT_SYMBOL(omap_stop_lcd_dma);
2250EXPORT_SYMBOL(omap_set_lcd_dma_b1);
2251EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
2252EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
2253EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
2254EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
2255EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
2256EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
2257 2429
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 302ad8dff2cb..f22506af0e67 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -38,34 +38,113 @@
38#include <asm/arch/irqs.h> 38#include <asm/arch/irqs.h>
39 39
40/* register offsets */ 40/* register offsets */
41#define OMAP_TIMER_ID_REG 0x00 41#define _OMAP_TIMER_ID_OFFSET 0x00
42#define OMAP_TIMER_OCP_CFG_REG 0x10 42#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
43#define OMAP_TIMER_SYS_STAT_REG 0x14 43#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
44#define OMAP_TIMER_STAT_REG 0x18 44#define _OMAP_TIMER_STAT_OFFSET 0x18
45#define OMAP_TIMER_INT_EN_REG 0x1c 45#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
46#define OMAP_TIMER_WAKEUP_EN_REG 0x20 46#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
47#define OMAP_TIMER_CTRL_REG 0x24 47#define _OMAP_TIMER_CTRL_OFFSET 0x24
48#define OMAP_TIMER_COUNTER_REG 0x28 48#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
49#define OMAP_TIMER_LOAD_REG 0x2c 49#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
50#define OMAP_TIMER_TRIGGER_REG 0x30 50#define OMAP_TIMER_CTRL_PT (1 << 12)
51#define OMAP_TIMER_WRITE_PEND_REG 0x34 51#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
52#define OMAP_TIMER_MATCH_REG 0x38 52#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
53#define OMAP_TIMER_CAPTURE_REG 0x3c 53#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
54#define OMAP_TIMER_IF_CTRL_REG 0x40 54#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
55 55#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
56/* timer control reg bits */ 56#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
57#define OMAP_TIMER_CTRL_GPOCFG (1 << 14) 57#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
58#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13) 58#define OMAP_TIMER_CTRL_POSTED (1 << 2)
59#define OMAP_TIMER_CTRL_PT (1 << 12) 59#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
60#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8) 60#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
61#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8) 61#define _OMAP_TIMER_COUNTER_OFFSET 0x28
62#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8) 62#define _OMAP_TIMER_LOAD_OFFSET 0x2c
63#define OMAP_TIMER_CTRL_SCPWM (1 << 7) 63#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
64#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */ 64#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
65#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */ 65#define WP_NONE 0 /* no write pending bit */
66#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* how much to shift the prescaler value */ 66#define WP_TCLR (1 << 0)
67#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */ 67#define WP_TCRR (1 << 1)
68#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */ 68#define WP_TLDR (1 << 2)
69#define WP_TTGR (1 << 3)
70#define WP_TMAR (1 << 4)
71#define WP_TPIR (1 << 5)
72#define WP_TNIR (1 << 6)
73#define WP_TCVR (1 << 7)
74#define WP_TOCR (1 << 8)
75#define WP_TOWR (1 << 9)
76#define _OMAP_TIMER_MATCH_OFFSET 0x38
77#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
78#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
79#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
80#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
81#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
82#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
83#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
84#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
85
86/* register offsets with the write pending bit encoded */
87#define WPSHIFT 16
88
89#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
90 | (WP_NONE << WPSHIFT))
91
92#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
93 | (WP_NONE << WPSHIFT))
94
95#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
96 | (WP_NONE << WPSHIFT))
97
98#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
99 | (WP_NONE << WPSHIFT))
100
101#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
102 | (WP_NONE << WPSHIFT))
103
104#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
105 | (WP_NONE << WPSHIFT))
106
107#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
108 | (WP_TCLR << WPSHIFT))
109
110#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
111 | (WP_TCRR << WPSHIFT))
112
113#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
114 | (WP_TLDR << WPSHIFT))
115
116#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
117 | (WP_TTGR << WPSHIFT))
118
119#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
120 | (WP_NONE << WPSHIFT))
121
122#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
123 | (WP_TMAR << WPSHIFT))
124
125#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
126 | (WP_NONE << WPSHIFT))
127
128#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
129 | (WP_NONE << WPSHIFT))
130
131#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
132 | (WP_NONE << WPSHIFT))
133
134#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
135 | (WP_TPIR << WPSHIFT))
136
137#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
138 | (WP_TNIR << WPSHIFT))
139
140#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
141 | (WP_TCVR << WPSHIFT))
142
143#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
144 (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
145
146#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
147 (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
69 148
70struct omap_dm_timer { 149struct omap_dm_timer {
71 unsigned long phys_base; 150 unsigned long phys_base;
@@ -76,6 +155,7 @@ struct omap_dm_timer {
76 void __iomem *io_base; 155 void __iomem *io_base;
77 unsigned reserved:1; 156 unsigned reserved:1;
78 unsigned enabled:1; 157 unsigned enabled:1;
158 unsigned posted:1;
79}; 159};
80 160
81#ifdef CONFIG_ARCH_OMAP1 161#ifdef CONFIG_ARCH_OMAP1
@@ -181,16 +261,34 @@ static struct clk **dm_source_clocks;
181 261
182static spinlock_t dm_timer_lock; 262static spinlock_t dm_timer_lock;
183 263
184static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, int reg) 264/*
265 * Reads timer registers in posted and non-posted mode. The posted mode bit
266 * is encoded in reg. Note that in posted mode write pending bit must be
267 * checked. Otherwise a read of a non completed write will produce an error.
268 */
269static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
185{ 270{
186 return readl(timer->io_base + reg); 271 if (timer->posted)
272 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
273 & (reg >> WPSHIFT))
274 cpu_relax();
275 return readl(timer->io_base + (reg & 0xff));
187} 276}
188 277
189static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, int reg, u32 value) 278/*
279 * Writes timer registers in posted and non-posted mode. The posted mode bit
280 * is encoded in reg. Note that in posted mode the write pending bit must be
281 * checked. Otherwise a write on a register which has a pending write will be
282 * lost.
283 */
284static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
285 u32 value)
190{ 286{
191 writel(value, timer->io_base + reg); 287 if (timer->posted)
192 while (omap_dm_timer_read_reg(timer, OMAP_TIMER_WRITE_PEND_REG)) 288 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
193 ; 289 & (reg >> WPSHIFT))
290 cpu_relax();
291 writel(value, timer->io_base + (reg & 0xff));
194} 292}
195 293
196static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer) 294static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -217,17 +315,23 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
217 } 315 }
218 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ); 316 omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
219 317
220 /* Set to smart-idle mode */
221 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG); 318 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
222 l |= 0x02 << 3; 319 l |= 0x02 << 3; /* Set to smart-idle mode */
223 320 l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
224 if (cpu_class_is_omap2() && timer == &dm_timers[0]) { 321
225 /* Enable wake-up only for GPT1 on OMAP2 CPUs*/ 322 /*
323 * Enable wake-up only for GPT1 on OMAP2 CPUs.
324 * FIXME: All timers should have wake-up enabled and clear
325 * PRCM status.
326 */
327 if (cpu_class_is_omap2() && (timer == &dm_timers[0]))
226 l |= 1 << 2; 328 l |= 1 << 2;
227 /* Non-posted mode */
228 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0);
229 }
230 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l); 329 omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
330
331 /* Match hardware reset default of posted mode */
332 omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
333 OMAP_TIMER_CTRL_POSTED);
334 timer->posted = 1;
231} 335}
232 336
233static void omap_dm_timer_prepare(struct omap_dm_timer *timer) 337static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
@@ -434,9 +538,32 @@ void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
434 l &= ~OMAP_TIMER_CTRL_AR; 538 l &= ~OMAP_TIMER_CTRL_AR;
435 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l); 539 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
436 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load); 540 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
541
542 /* REVISIT: hw feature, ttgr overtaking tldr? */
543 while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff)))
544 cpu_relax();
545
437 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0); 546 omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
438} 547}
439 548
549/* Optimized set_load which removes costly spin wait in timer_start */
550void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
551 unsigned int load)
552{
553 u32 l;
554
555 l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
556 if (autoreload)
557 l |= OMAP_TIMER_CTRL_AR;
558 else
559 l &= ~OMAP_TIMER_CTRL_AR;
560 l |= OMAP_TIMER_CTRL_ST;
561
562 omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
563 omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
564 omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
565}
566
440void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, 567void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
441 unsigned int match) 568 unsigned int match)
442{ 569{
@@ -451,7 +578,6 @@ void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
451 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match); 578 omap_dm_timer_write_reg(timer, OMAP_TIMER_MATCH_REG, match);
452} 579}
453 580
454
455void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, 581void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
456 int toggle, int trigger) 582 int toggle, int trigger)
457{ 583{
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 9cf83c4da9fa..c7f74064696c 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -15,95 +15,66 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/init.h> 16#include <linux/init.h>
17#include <linux/device.h> 17#include <linux/device.h>
18#include <linux/platform_device.h>
18#include <linux/wait.h> 19#include <linux/wait.h>
19#include <linux/completion.h> 20#include <linux/completion.h>
20#include <linux/interrupt.h> 21#include <linux/interrupt.h>
21#include <linux/err.h> 22#include <linux/err.h>
22#include <linux/clk.h> 23#include <linux/clk.h>
23#include <linux/delay.h> 24#include <linux/delay.h>
24 25#include <linux/io.h>
25#include <asm/io.h>
26#include <asm/irq.h>
27 26
28#include <asm/arch/dma.h> 27#include <asm/arch/dma.h>
29#include <asm/arch/mux.h>
30#include <asm/arch/irqs.h>
31#include <asm/arch/dsp_common.h>
32#include <asm/arch/mcbsp.h> 28#include <asm/arch/mcbsp.h>
33 29
34#ifdef CONFIG_MCBSP_DEBUG
35#define DBG(x...) printk(x)
36#else
37#define DBG(x...) do { } while (0)
38#endif
39
40struct omap_mcbsp {
41 u32 io_base;
42 u8 id;
43 u8 free;
44 omap_mcbsp_word_length rx_word_length;
45 omap_mcbsp_word_length tx_word_length;
46
47 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
48 /* IRQ based TX/RX */
49 int rx_irq;
50 int tx_irq;
51
52 /* DMA stuff */
53 u8 dma_rx_sync;
54 short dma_rx_lch;
55 u8 dma_tx_sync;
56 short dma_tx_lch;
57
58 /* Completion queues */
59 struct completion tx_irq_completion;
60 struct completion rx_irq_completion;
61 struct completion tx_dma_completion;
62 struct completion rx_dma_completion;
63
64 spinlock_t lock;
65};
66
67static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT]; 30static struct omap_mcbsp mcbsp[OMAP_MAX_MCBSP_COUNT];
68#ifdef CONFIG_ARCH_OMAP1 31
69static struct clk *mcbsp_dsp_ck = 0; 32#define omap_mcbsp_check_valid_id(id) (mcbsp[id].pdata && \
70static struct clk *mcbsp_api_ck = 0; 33 mcbsp[id].pdata->ops && \
71static struct clk *mcbsp_dspxor_ck = 0; 34 mcbsp[id].pdata->ops->check && \
72#endif 35 (mcbsp[id].pdata->ops->check(id) == 0))
73#ifdef CONFIG_ARCH_OMAP2
74static struct clk *mcbsp1_ick = 0;
75static struct clk *mcbsp1_fck = 0;
76static struct clk *mcbsp2_ick = 0;
77static struct clk *mcbsp2_fck = 0;
78#endif
79 36
80static void omap_mcbsp_dump_reg(u8 id) 37static void omap_mcbsp_dump_reg(u8 id)
81{ 38{
82 DBG("**** MCBSP%d regs ****\n", mcbsp[id].id); 39 dev_dbg(mcbsp[id].dev, "**** McBSP%d regs ****\n", mcbsp[id].id);
83 DBG("DRR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2)); 40 dev_dbg(mcbsp[id].dev, "DRR2: 0x%04x\n",
84 DBG("DRR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1)); 41 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR2));
85 DBG("DXR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2)); 42 dev_dbg(mcbsp[id].dev, "DRR1: 0x%04x\n",
86 DBG("DXR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1)); 43 OMAP_MCBSP_READ(mcbsp[id].io_base, DRR1));
87 DBG("SPCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2)); 44 dev_dbg(mcbsp[id].dev, "DXR2: 0x%04x\n",
88 DBG("SPCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1)); 45 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR2));
89 DBG("RCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2)); 46 dev_dbg(mcbsp[id].dev, "DXR1: 0x%04x\n",
90 DBG("RCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1)); 47 OMAP_MCBSP_READ(mcbsp[id].io_base, DXR1));
91 DBG("XCR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2)); 48 dev_dbg(mcbsp[id].dev, "SPCR2: 0x%04x\n",
92 DBG("XCR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1)); 49 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR2));
93 DBG("SRGR2: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2)); 50 dev_dbg(mcbsp[id].dev, "SPCR1: 0x%04x\n",
94 DBG("SRGR1: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1)); 51 OMAP_MCBSP_READ(mcbsp[id].io_base, SPCR1));
95 DBG("PCR0: 0x%04x\n", OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0)); 52 dev_dbg(mcbsp[id].dev, "RCR2: 0x%04x\n",
96 DBG("***********************\n"); 53 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR2));
54 dev_dbg(mcbsp[id].dev, "RCR1: 0x%04x\n",
55 OMAP_MCBSP_READ(mcbsp[id].io_base, RCR1));
56 dev_dbg(mcbsp[id].dev, "XCR2: 0x%04x\n",
57 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR2));
58 dev_dbg(mcbsp[id].dev, "XCR1: 0x%04x\n",
59 OMAP_MCBSP_READ(mcbsp[id].io_base, XCR1));
60 dev_dbg(mcbsp[id].dev, "SRGR2: 0x%04x\n",
61 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR2));
62 dev_dbg(mcbsp[id].dev, "SRGR1: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp[id].io_base, SRGR1));
64 dev_dbg(mcbsp[id].dev, "PCR0: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp[id].io_base, PCR0));
66 dev_dbg(mcbsp[id].dev, "***********************\n");
97} 67}
98 68
99static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id) 69static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
100{ 70{
101 struct omap_mcbsp *mcbsp_tx = dev_id; 71 struct omap_mcbsp *mcbsp_tx = dev_id;
102 72
103 DBG("TX IRQ callback : 0x%x\n", 73 dev_dbg(mcbsp_tx->dev, "TX IRQ callback : 0x%x\n",
104 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2)); 74 OMAP_MCBSP_READ(mcbsp_tx->io_base, SPCR2));
105 75
106 complete(&mcbsp_tx->tx_irq_completion); 76 complete(&mcbsp_tx->tx_irq_completion);
77
107 return IRQ_HANDLED; 78 return IRQ_HANDLED;
108} 79}
109 80
@@ -111,10 +82,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
111{ 82{
112 struct omap_mcbsp *mcbsp_rx = dev_id; 83 struct omap_mcbsp *mcbsp_rx = dev_id;
113 84
114 DBG("RX IRQ callback : 0x%x\n", 85 dev_dbg(mcbsp_rx->dev, "RX IRQ callback : 0x%x\n",
115 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2)); 86 OMAP_MCBSP_READ(mcbsp_rx->io_base, SPCR2));
116 87
117 complete(&mcbsp_rx->rx_irq_completion); 88 complete(&mcbsp_rx->rx_irq_completion);
89
118 return IRQ_HANDLED; 90 return IRQ_HANDLED;
119} 91}
120 92
@@ -122,8 +94,8 @@ static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
122{ 94{
123 struct omap_mcbsp *mcbsp_dma_tx = data; 95 struct omap_mcbsp *mcbsp_dma_tx = data;
124 96
125 DBG("TX DMA callback : 0x%x\n", 97 dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
126 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2)); 98 OMAP_MCBSP_READ(mcbsp_dma_tx->io_base, SPCR2));
127 99
128 /* We can free the channels */ 100 /* We can free the channels */
129 omap_free_dma(mcbsp_dma_tx->dma_tx_lch); 101 omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
@@ -136,8 +108,8 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
136{ 108{
137 struct omap_mcbsp *mcbsp_dma_rx = data; 109 struct omap_mcbsp *mcbsp_dma_rx = data;
138 110
139 DBG("RX DMA callback : 0x%x\n", 111 dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
140 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2)); 112 OMAP_MCBSP_READ(mcbsp_dma_rx->io_base, SPCR2));
141 113
142 /* We can free the channels */ 114 /* We can free the channels */
143 omap_free_dma(mcbsp_dma_rx->dma_rx_lch); 115 omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
@@ -146,19 +118,24 @@ static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
146 complete(&mcbsp_dma_rx->rx_dma_completion); 118 complete(&mcbsp_dma_rx->rx_dma_completion);
147} 119}
148 120
149
150/* 121/*
151 * omap_mcbsp_config simply write a config to the 122 * omap_mcbsp_config simply write a config to the
152 * appropriate McBSP. 123 * appropriate McBSP.
153 * You either call this function or set the McBSP registers 124 * You either call this function or set the McBSP registers
154 * by yourself before calling omap_mcbsp_start(). 125 * by yourself before calling omap_mcbsp_start().
155 */ 126 */
156 127void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
157void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config)
158{ 128{
159 u32 io_base = mcbsp[id].io_base; 129 u32 io_base;
130
131 if (!omap_mcbsp_check_valid_id(id)) {
132 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
133 return;
134 }
160 135
161 DBG("OMAP-McBSP: McBSP%d io_base: 0x%8x\n", id+1, io_base); 136 io_base = mcbsp[id].io_base;
137 dev_dbg(mcbsp[id].dev, "Configuring McBSP%d io_base: 0x%8x\n",
138 mcbsp[id].id, io_base);
162 139
163 /* We write the given config */ 140 /* We write the given config */
164 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2); 141 OMAP_MCBSP_WRITE(io_base, SPCR2, config->spcr2);
@@ -173,83 +150,7 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config
173 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1); 150 OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
174 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0); 151 OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
175} 152}
176 153EXPORT_SYMBOL(omap_mcbsp_config);
177
178
179static int omap_mcbsp_check(unsigned int id)
180{
181 if (cpu_is_omap730()) {
182 if (id > OMAP_MAX_MCBSP_COUNT - 1) {
183 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
184 return -1;
185 }
186 return 0;
187 }
188
189 if (cpu_is_omap15xx() || cpu_is_omap16xx() || cpu_is_omap24xx()) {
190 if (id > OMAP_MAX_MCBSP_COUNT) {
191 printk(KERN_ERR "OMAP-McBSP: McBSP%d doesn't exist\n", id + 1);
192 return -1;
193 }
194 return 0;
195 }
196
197 return -1;
198}
199
200#ifdef CONFIG_ARCH_OMAP1
201static void omap_mcbsp_dsp_request(void)
202{
203 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
204 int ret;
205
206 ret = omap_dsp_request_mem();
207 if (ret < 0) {
208 printk(KERN_ERR "Could not get dsp memory: %i\n", ret);
209 return;
210 }
211
212 clk_enable(mcbsp_dsp_ck);
213 clk_enable(mcbsp_api_ck);
214
215 /* enable 12MHz clock to mcbsp 1 & 3 */
216 clk_enable(mcbsp_dspxor_ck);
217
218 /*
219 * DSP external peripheral reset
220 * FIXME: This should be moved to dsp code
221 */
222 __raw_writew(__raw_readw(DSP_RSTCT2) | 1 | 1 << 1,
223 DSP_RSTCT2);
224 }
225}
226
227static void omap_mcbsp_dsp_free(void)
228{
229 if (cpu_is_omap15xx() || cpu_is_omap16xx()) {
230 omap_dsp_release_mem();
231 clk_disable(mcbsp_dspxor_ck);
232 clk_disable(mcbsp_dsp_ck);
233 clk_disable(mcbsp_api_ck);
234 }
235}
236#endif
237
238#ifdef CONFIG_ARCH_OMAP2
239static void omap2_mcbsp2_mux_setup(void)
240{
241 if (cpu_is_omap2420()) {
242 omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
243 omap_cfg_reg(R14_24XX_MCBSP2_FSX);
244 omap_cfg_reg(W15_24XX_MCBSP2_DR);
245 omap_cfg_reg(V15_24XX_MCBSP2_DX);
246 omap_cfg_reg(V14_24XX_GPIO117);
247 }
248 /*
249 * Need to add MUX settings for OMAP 2430 SDP
250 */
251}
252#endif
253 154
254/* 155/*
255 * We can choose between IRQ based or polled IO. 156 * We can choose between IRQ based or polled IO.
@@ -257,13 +158,16 @@ static void omap2_mcbsp2_mux_setup(void)
257 */ 158 */
258int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type) 159int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
259{ 160{
260 if (omap_mcbsp_check(id) < 0) 161 if (!omap_mcbsp_check_valid_id(id)) {
261 return -EINVAL; 162 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
163 return -ENODEV;
164 }
262 165
263 spin_lock(&mcbsp[id].lock); 166 spin_lock(&mcbsp[id].lock);
264 167
265 if (!mcbsp[id].free) { 168 if (!mcbsp[id].free) {
266 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 169 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
170 mcbsp[id].id);
267 spin_unlock(&mcbsp[id].lock); 171 spin_unlock(&mcbsp[id].lock);
268 return -EINVAL; 172 return -EINVAL;
269 } 173 }
@@ -274,38 +178,26 @@ int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
274 178
275 return 0; 179 return 0;
276} 180}
181EXPORT_SYMBOL(omap_mcbsp_set_io_type);
277 182
278int omap_mcbsp_request(unsigned int id) 183int omap_mcbsp_request(unsigned int id)
279{ 184{
280 int err; 185 int err;
281 186
282 if (omap_mcbsp_check(id) < 0) 187 if (!omap_mcbsp_check_valid_id(id)) {
283 return -EINVAL; 188 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
284 189 return -ENODEV;
285#ifdef CONFIG_ARCH_OMAP1
286 /*
287 * On 1510, 1610 and 1710, McBSP1 and McBSP3
288 * are DSP public peripherals.
289 */
290 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
291 omap_mcbsp_dsp_request();
292#endif
293
294#ifdef CONFIG_ARCH_OMAP2
295 if (cpu_is_omap24xx()) {
296 if (id == OMAP_MCBSP1) {
297 clk_enable(mcbsp1_ick);
298 clk_enable(mcbsp1_fck);
299 } else {
300 clk_enable(mcbsp2_ick);
301 clk_enable(mcbsp2_fck);
302 }
303 } 190 }
304#endif 191
192 if (mcbsp[id].pdata->ops->request)
193 mcbsp[id].pdata->ops->request(id);
194
195 clk_enable(mcbsp[id].clk);
305 196
306 spin_lock(&mcbsp[id].lock); 197 spin_lock(&mcbsp[id].lock);
307 if (!mcbsp[id].free) { 198 if (!mcbsp[id].free) {
308 printk (KERN_ERR "OMAP-McBSP: McBSP%d is currently in use\n", id + 1); 199 dev_err(mcbsp[id].dev, "McBSP%d is currently in use\n",
200 mcbsp[id].id);
309 spin_unlock(&mcbsp[id].lock); 201 spin_unlock(&mcbsp[id].lock);
310 return -1; 202 return -1;
311 } 203 }
@@ -315,24 +207,23 @@ int omap_mcbsp_request(unsigned int id)
315 207
316 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) { 208 if (mcbsp[id].io_type == OMAP_MCBSP_IRQ_IO) {
317 /* We need to get IRQs here */ 209 /* We need to get IRQs here */
318 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler, 0, 210 err = request_irq(mcbsp[id].tx_irq, omap_mcbsp_tx_irq_handler,
319 "McBSP", 211 0, "McBSP", (void *) (&mcbsp[id]));
320 (void *) (&mcbsp[id]));
321 if (err != 0) { 212 if (err != 0) {
322 printk(KERN_ERR "OMAP-McBSP: Unable to request TX IRQ %d for McBSP%d\n", 213 dev_err(mcbsp[id].dev, "Unable to request TX IRQ %d "
323 mcbsp[id].tx_irq, mcbsp[id].id); 214 "for McBSP%d\n", mcbsp[id].tx_irq,
215 mcbsp[id].id);
324 return err; 216 return err;
325 } 217 }
326 218
327 init_completion(&(mcbsp[id].tx_irq_completion)); 219 init_completion(&(mcbsp[id].tx_irq_completion));
328 220
329 221 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler,
330 err = request_irq(mcbsp[id].rx_irq, omap_mcbsp_rx_irq_handler, 0, 222 0, "McBSP", (void *) (&mcbsp[id]));
331 "McBSP",
332 (void *) (&mcbsp[id]));
333 if (err != 0) { 223 if (err != 0) {
334 printk(KERN_ERR "OMAP-McBSP: Unable to request RX IRQ %d for McBSP%d\n", 224 dev_err(mcbsp[id].dev, "Unable to request RX IRQ %d "
335 mcbsp[id].rx_irq, mcbsp[id].id); 225 "for McBSP%d\n", mcbsp[id].rx_irq,
226 mcbsp[id].id);
336 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 227 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
337 return err; 228 return err;
338 } 229 }
@@ -341,36 +232,25 @@ int omap_mcbsp_request(unsigned int id)
341 } 232 }
342 233
343 return 0; 234 return 0;
344
345} 235}
236EXPORT_SYMBOL(omap_mcbsp_request);
346 237
347void omap_mcbsp_free(unsigned int id) 238void omap_mcbsp_free(unsigned int id)
348{ 239{
349 if (omap_mcbsp_check(id) < 0) 240 if (!omap_mcbsp_check_valid_id(id)) {
241 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
350 return; 242 return;
351
352#ifdef CONFIG_ARCH_OMAP1
353 if (cpu_class_is_omap1()) {
354 if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3)
355 omap_mcbsp_dsp_free();
356 } 243 }
357#endif 244
358 245 if (mcbsp[id].pdata->ops->free)
359#ifdef CONFIG_ARCH_OMAP2 246 mcbsp[id].pdata->ops->free(id);
360 if (cpu_is_omap24xx()) { 247
361 if (id == OMAP_MCBSP1) { 248 clk_disable(mcbsp[id].clk);
362 clk_disable(mcbsp1_ick);
363 clk_disable(mcbsp1_fck);
364 } else {
365 clk_disable(mcbsp2_ick);
366 clk_disable(mcbsp2_fck);
367 }
368 }
369#endif
370 249
371 spin_lock(&mcbsp[id].lock); 250 spin_lock(&mcbsp[id].lock);
372 if (mcbsp[id].free) { 251 if (mcbsp[id].free) {
373 printk (KERN_ERR "OMAP-McBSP: McBSP%d was not reserved\n", id + 1); 252 dev_err(mcbsp[id].dev, "McBSP%d was not reserved\n",
253 mcbsp[id].id);
374 spin_unlock(&mcbsp[id].lock); 254 spin_unlock(&mcbsp[id].lock);
375 return; 255 return;
376 } 256 }
@@ -384,6 +264,7 @@ void omap_mcbsp_free(unsigned int id)
384 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id])); 264 free_irq(mcbsp[id].tx_irq, (void *) (&mcbsp[id]));
385 } 265 }
386} 266}
267EXPORT_SYMBOL(omap_mcbsp_free);
387 268
388/* 269/*
389 * Here we start the McBSP, by enabling the sample 270 * Here we start the McBSP, by enabling the sample
@@ -395,13 +276,15 @@ void omap_mcbsp_start(unsigned int id)
395 u32 io_base; 276 u32 io_base;
396 u16 w; 277 u16 w;
397 278
398 if (omap_mcbsp_check(id) < 0) 279 if (!omap_mcbsp_check_valid_id(id)) {
280 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
399 return; 281 return;
282 }
400 283
401 io_base = mcbsp[id].io_base; 284 io_base = mcbsp[id].io_base;
402 285
403 mcbsp[id].rx_word_length = ((OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7); 286 mcbsp[id].rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
404 mcbsp[id].tx_word_length = ((OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7); 287 mcbsp[id].tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
405 288
406 /* Start the sample generator */ 289 /* Start the sample generator */
407 w = OMAP_MCBSP_READ(io_base, SPCR2); 290 w = OMAP_MCBSP_READ(io_base, SPCR2);
@@ -422,20 +305,22 @@ void omap_mcbsp_start(unsigned int id)
422 305
423 /* Dump McBSP Regs */ 306 /* Dump McBSP Regs */
424 omap_mcbsp_dump_reg(id); 307 omap_mcbsp_dump_reg(id);
425
426} 308}
309EXPORT_SYMBOL(omap_mcbsp_start);
427 310
428void omap_mcbsp_stop(unsigned int id) 311void omap_mcbsp_stop(unsigned int id)
429{ 312{
430 u32 io_base; 313 u32 io_base;
431 u16 w; 314 u16 w;
432 315
433 if (omap_mcbsp_check(id) < 0) 316 if (!omap_mcbsp_check_valid_id(id)) {
317 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
434 return; 318 return;
319 }
435 320
436 io_base = mcbsp[id].io_base; 321 io_base = mcbsp[id].io_base;
437 322
438 /* Reset transmitter */ 323 /* Reset transmitter */
439 w = OMAP_MCBSP_READ(io_base, SPCR2); 324 w = OMAP_MCBSP_READ(io_base, SPCR2);
440 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1)); 325 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
441 326
@@ -447,12 +332,19 @@ void omap_mcbsp_stop(unsigned int id)
447 w = OMAP_MCBSP_READ(io_base, SPCR2); 332 w = OMAP_MCBSP_READ(io_base, SPCR2);
448 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6)); 333 OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
449} 334}
450 335EXPORT_SYMBOL(omap_mcbsp_stop);
451 336
452/* polled mcbsp i/o operations */ 337/* polled mcbsp i/o operations */
453int omap_mcbsp_pollwrite(unsigned int id, u16 buf) 338int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
454{ 339{
455 u32 base = mcbsp[id].io_base; 340 u32 base;
341
342 if (!omap_mcbsp_check_valid_id(id)) {
343 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
344 return -ENODEV;
345 }
346
347 base = mcbsp[id].io_base;
456 writew(buf, base + OMAP_MCBSP_REG_DXR1); 348 writew(buf, base + OMAP_MCBSP_REG_DXR1);
457 /* if frame sync error - clear the error */ 349 /* if frame sync error - clear the error */
458 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) { 350 if (readw(base + OMAP_MCBSP_REG_SPCR2) & XSYNC_ERR) {
@@ -474,18 +366,27 @@ int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
474 (XRST), 366 (XRST),
475 base + OMAP_MCBSP_REG_SPCR2); 367 base + OMAP_MCBSP_REG_SPCR2);
476 udelay(10); 368 udelay(10);
477 printk(KERN_ERR 369 dev_err(mcbsp[id].dev, "Could not write to"
478 " Could not write to McBSP Register\n"); 370 " McBSP%d Register\n", mcbsp[id].id);
479 return -2; 371 return -2;
480 } 372 }
481 } 373 }
482 } 374 }
375
483 return 0; 376 return 0;
484} 377}
378EXPORT_SYMBOL(omap_mcbsp_pollwrite);
485 379
486int omap_mcbsp_pollread(unsigned int id, u16 * buf) 380int omap_mcbsp_pollread(unsigned int id, u16 *buf)
487{ 381{
488 u32 base = mcbsp[id].io_base; 382 u32 base;
383
384 if (!omap_mcbsp_check_valid_id(id)) {
385 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
386 return -ENODEV;
387 }
388
389 base = mcbsp[id].io_base;
489 /* if frame sync error - clear the error */ 390 /* if frame sync error - clear the error */
490 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) { 391 if (readw(base + OMAP_MCBSP_REG_SPCR1) & RSYNC_ERR) {
491 /* clear error */ 392 /* clear error */
@@ -506,15 +407,17 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
506 (RRST), 407 (RRST),
507 base + OMAP_MCBSP_REG_SPCR1); 408 base + OMAP_MCBSP_REG_SPCR1);
508 udelay(10); 409 udelay(10);
509 printk(KERN_ERR 410 dev_err(mcbsp[id].dev, "Could not read from"
510 " Could not read from McBSP Register\n"); 411 " McBSP%d Register\n", mcbsp[id].id);
511 return -2; 412 return -2;
512 } 413 }
513 } 414 }
514 } 415 }
515 *buf = readw(base + OMAP_MCBSP_REG_DRR1); 416 *buf = readw(base + OMAP_MCBSP_REG_DRR1);
417
516 return 0; 418 return 0;
517} 419}
420EXPORT_SYMBOL(omap_mcbsp_pollread);
518 421
519/* 422/*
520 * IRQ based word transmission. 423 * IRQ based word transmission.
@@ -522,12 +425,15 @@ int omap_mcbsp_pollread(unsigned int id, u16 * buf)
522void omap_mcbsp_xmit_word(unsigned int id, u32 word) 425void omap_mcbsp_xmit_word(unsigned int id, u32 word)
523{ 426{
524 u32 io_base; 427 u32 io_base;
525 omap_mcbsp_word_length word_length = mcbsp[id].tx_word_length; 428 omap_mcbsp_word_length word_length;
526 429
527 if (omap_mcbsp_check(id) < 0) 430 if (!omap_mcbsp_check_valid_id(id)) {
431 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
528 return; 432 return;
433 }
529 434
530 io_base = mcbsp[id].io_base; 435 io_base = mcbsp[id].io_base;
436 word_length = mcbsp[id].tx_word_length;
531 437
532 wait_for_completion(&(mcbsp[id].tx_irq_completion)); 438 wait_for_completion(&(mcbsp[id].tx_irq_completion));
533 439
@@ -535,16 +441,20 @@ void omap_mcbsp_xmit_word(unsigned int id, u32 word)
535 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16); 441 OMAP_MCBSP_WRITE(io_base, DXR2, word >> 16);
536 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff); 442 OMAP_MCBSP_WRITE(io_base, DXR1, word & 0xffff);
537} 443}
444EXPORT_SYMBOL(omap_mcbsp_xmit_word);
538 445
539u32 omap_mcbsp_recv_word(unsigned int id) 446u32 omap_mcbsp_recv_word(unsigned int id)
540{ 447{
541 u32 io_base; 448 u32 io_base;
542 u16 word_lsb, word_msb = 0; 449 u16 word_lsb, word_msb = 0;
543 omap_mcbsp_word_length word_length = mcbsp[id].rx_word_length; 450 omap_mcbsp_word_length word_length;
544 451
545 if (omap_mcbsp_check(id) < 0) 452 if (!omap_mcbsp_check_valid_id(id)) {
546 return -EINVAL; 453 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
454 return -ENODEV;
455 }
547 456
457 word_length = mcbsp[id].rx_word_length;
548 io_base = mcbsp[id].io_base; 458 io_base = mcbsp[id].io_base;
549 459
550 wait_for_completion(&(mcbsp[id].rx_irq_completion)); 460 wait_for_completion(&(mcbsp[id].rx_irq_completion));
@@ -555,15 +465,24 @@ u32 omap_mcbsp_recv_word(unsigned int id)
555 465
556 return (word_lsb | (word_msb << 16)); 466 return (word_lsb | (word_msb << 16));
557} 467}
558 468EXPORT_SYMBOL(omap_mcbsp_recv_word);
559 469
560int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word) 470int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
561{ 471{
562 u32 io_base = mcbsp[id].io_base; 472 u32 io_base;
563 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 473 omap_mcbsp_word_length tx_word_length;
564 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 474 omap_mcbsp_word_length rx_word_length;
565 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 475 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
566 476
477 if (!omap_mcbsp_check_valid_id(id)) {
478 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
479 return -ENODEV;
480 }
481
482 io_base = mcbsp[id].io_base;
483 tx_word_length = mcbsp[id].tx_word_length;
484 rx_word_length = mcbsp[id].rx_word_length;
485
567 if (tx_word_length != rx_word_length) 486 if (tx_word_length != rx_word_length)
568 return -EINVAL; 487 return -EINVAL;
569 488
@@ -577,7 +496,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
577 udelay(10); 496 udelay(10);
578 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 497 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
579 udelay(10); 498 udelay(10);
580 printk("McBSP transmitter not ready\n"); 499 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
500 "ready\n", mcbsp[id].id);
581 return -EAGAIN; 501 return -EAGAIN;
582 } 502 }
583 } 503 }
@@ -597,7 +517,8 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
597 udelay(10); 517 udelay(10);
598 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 518 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
599 udelay(10); 519 udelay(10);
600 printk("McBSP receiver not ready\n"); 520 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
521 "ready\n", mcbsp[id].id);
601 return -EAGAIN; 522 return -EAGAIN;
602 } 523 }
603 } 524 }
@@ -609,14 +530,24 @@ int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
609 530
610 return 0; 531 return 0;
611} 532}
533EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
612 534
613int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word) 535int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
614{ 536{
615 u32 io_base = mcbsp[id].io_base, clock_word = 0; 537 u32 io_base, clock_word = 0;
616 omap_mcbsp_word_length tx_word_length = mcbsp[id].tx_word_length; 538 omap_mcbsp_word_length tx_word_length;
617 omap_mcbsp_word_length rx_word_length = mcbsp[id].rx_word_length; 539 omap_mcbsp_word_length rx_word_length;
618 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0; 540 u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
619 541
542 if (!omap_mcbsp_check_valid_id(id)) {
543 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
544 return -ENODEV;
545 }
546
547 io_base = mcbsp[id].io_base;
548 tx_word_length = mcbsp[id].tx_word_length;
549 rx_word_length = mcbsp[id].rx_word_length;
550
620 if (tx_word_length != rx_word_length) 551 if (tx_word_length != rx_word_length)
621 return -EINVAL; 552 return -EINVAL;
622 553
@@ -630,7 +561,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
630 udelay(10); 561 udelay(10);
631 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST); 562 OMAP_MCBSP_WRITE(io_base, SPCR2, spcr2 | XRST);
632 udelay(10); 563 udelay(10);
633 printk("McBSP transmitter not ready\n"); 564 dev_err(mcbsp[id].dev, "McBSP%d transmitter not "
565 "ready\n", mcbsp[id].id);
634 return -EAGAIN; 566 return -EAGAIN;
635 } 567 }
636 } 568 }
@@ -650,7 +582,8 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
650 udelay(10); 582 udelay(10);
651 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST); 583 OMAP_MCBSP_WRITE(io_base, SPCR1, spcr1 | RRST);
652 udelay(10); 584 udelay(10);
653 printk("McBSP receiver not ready\n"); 585 dev_err(mcbsp[id].dev, "McBSP%d receiver not "
586 "ready\n", mcbsp[id].id);
654 return -EAGAIN; 587 return -EAGAIN;
655 } 588 }
656 } 589 }
@@ -664,7 +597,7 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
664 597
665 return 0; 598 return 0;
666} 599}
667 600EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
668 601
669/* 602/*
670 * Simple DMA based buffer rx/tx routines. 603 * Simple DMA based buffer rx/tx routines.
@@ -673,25 +606,32 @@ int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word)
673 * For anything fancier, you should use your own customized DMA 606 * For anything fancier, you should use your own customized DMA
674 * routines and callbacks. 607 * routines and callbacks.
675 */ 608 */
676int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 609int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
610 unsigned int length)
677{ 611{
678 int dma_tx_ch; 612 int dma_tx_ch;
679 int src_port = 0; 613 int src_port = 0;
680 int dest_port = 0; 614 int dest_port = 0;
681 int sync_dev = 0; 615 int sync_dev = 0;
682 616
683 if (omap_mcbsp_check(id) < 0) 617 if (!omap_mcbsp_check_valid_id(id)) {
684 return -EINVAL; 618 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
619 return -ENODEV;
620 }
685 621
686 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX", omap_mcbsp_tx_dma_callback, 622 if (omap_request_dma(mcbsp[id].dma_tx_sync, "McBSP TX",
687 &mcbsp[id], 623 omap_mcbsp_tx_dma_callback,
688 &dma_tx_ch)) { 624 &mcbsp[id],
689 printk("OMAP-McBSP: Unable to request DMA channel for McBSP%d TX. Trying IRQ based TX\n", id+1); 625 &dma_tx_ch)) {
626 dev_err(mcbsp[id].dev, " Unable to request DMA channel for "
627 "McBSP%d TX. Trying IRQ based TX\n",
628 mcbsp[id].id);
690 return -EAGAIN; 629 return -EAGAIN;
691 } 630 }
692 mcbsp[id].dma_tx_lch = dma_tx_ch; 631 mcbsp[id].dma_tx_lch = dma_tx_ch;
693 632
694 DBG("TX DMA on channel %d\n", dma_tx_ch); 633 dev_err(mcbsp[id].dev, "McBSP%d TX DMA on channel %d\n", mcbsp[id].id,
634 dma_tx_ch);
695 635
696 init_completion(&(mcbsp[id].tx_dma_completion)); 636 init_completion(&(mcbsp[id].tx_dma_completion));
697 637
@@ -699,7 +639,7 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
699 src_port = OMAP_DMA_PORT_TIPB; 639 src_port = OMAP_DMA_PORT_TIPB;
700 dest_port = OMAP_DMA_PORT_EMIFF; 640 dest_port = OMAP_DMA_PORT_EMIFF;
701 } 641 }
702 if (cpu_is_omap24xx()) 642 if (cpu_class_is_omap2())
703 sync_dev = mcbsp[id].dma_tx_sync; 643 sync_dev = mcbsp[id].dma_tx_sync;
704 644
705 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch, 645 omap_set_dma_transfer_params(mcbsp[id].dma_tx_lch,
@@ -722,29 +662,37 @@ int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
722 662
723 omap_start_dma(mcbsp[id].dma_tx_lch); 663 omap_start_dma(mcbsp[id].dma_tx_lch);
724 wait_for_completion(&(mcbsp[id].tx_dma_completion)); 664 wait_for_completion(&(mcbsp[id].tx_dma_completion));
665
725 return 0; 666 return 0;
726} 667}
668EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
727 669
728 670int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
729int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length) 671 unsigned int length)
730{ 672{
731 int dma_rx_ch; 673 int dma_rx_ch;
732 int src_port = 0; 674 int src_port = 0;
733 int dest_port = 0; 675 int dest_port = 0;
734 int sync_dev = 0; 676 int sync_dev = 0;
735 677
736 if (omap_mcbsp_check(id) < 0) 678 if (!omap_mcbsp_check_valid_id(id)) {
737 return -EINVAL; 679 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
680 return -ENODEV;
681 }
738 682
739 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX", omap_mcbsp_rx_dma_callback, 683 if (omap_request_dma(mcbsp[id].dma_rx_sync, "McBSP RX",
740 &mcbsp[id], 684 omap_mcbsp_rx_dma_callback,
741 &dma_rx_ch)) { 685 &mcbsp[id],
742 printk("Unable to request DMA channel for McBSP%d RX. Trying IRQ based RX\n", id+1); 686 &dma_rx_ch)) {
687 dev_err(mcbsp[id].dev, "Unable to request DMA channel for "
688 "McBSP%d RX. Trying IRQ based RX\n",
689 mcbsp[id].id);
743 return -EAGAIN; 690 return -EAGAIN;
744 } 691 }
745 mcbsp[id].dma_rx_lch = dma_rx_ch; 692 mcbsp[id].dma_rx_lch = dma_rx_ch;
746 693
747 DBG("RX DMA on channel %d\n", dma_rx_ch); 694 dev_err(mcbsp[id].dev, "McBSP%d RX DMA on channel %d\n", mcbsp[id].id,
695 dma_rx_ch);
748 696
749 init_completion(&(mcbsp[id].rx_dma_completion)); 697 init_completion(&(mcbsp[id].rx_dma_completion));
750 698
@@ -752,14 +700,14 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
752 src_port = OMAP_DMA_PORT_TIPB; 700 src_port = OMAP_DMA_PORT_TIPB;
753 dest_port = OMAP_DMA_PORT_EMIFF; 701 dest_port = OMAP_DMA_PORT_EMIFF;
754 } 702 }
755 if (cpu_is_omap24xx()) 703 if (cpu_class_is_omap2())
756 sync_dev = mcbsp[id].dma_rx_sync; 704 sync_dev = mcbsp[id].dma_rx_sync;
757 705
758 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch, 706 omap_set_dma_transfer_params(mcbsp[id].dma_rx_lch,
759 OMAP_DMA_DATA_TYPE_S16, 707 OMAP_DMA_DATA_TYPE_S16,
760 length >> 1, 1, 708 length >> 1, 1,
761 OMAP_DMA_SYNC_ELEMENT, 709 OMAP_DMA_SYNC_ELEMENT,
762 sync_dev, 0); 710 sync_dev, 0);
763 711
764 omap_set_dma_src_params(mcbsp[id].dma_rx_lch, 712 omap_set_dma_src_params(mcbsp[id].dma_rx_lch,
765 src_port, 713 src_port,
@@ -768,16 +716,17 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
768 0, 0); 716 0, 0);
769 717
770 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch, 718 omap_set_dma_dest_params(mcbsp[id].dma_rx_lch,
771 dest_port, 719 dest_port,
772 OMAP_DMA_AMODE_POST_INC, 720 OMAP_DMA_AMODE_POST_INC,
773 buffer, 721 buffer,
774 0, 0); 722 0, 0);
775 723
776 omap_start_dma(mcbsp[id].dma_rx_lch); 724 omap_start_dma(mcbsp[id].dma_rx_lch);
777 wait_for_completion(&(mcbsp[id].rx_dma_completion)); 725 wait_for_completion(&(mcbsp[id].rx_dma_completion));
726
778 return 0; 727 return 0;
779} 728}
780 729EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
781 730
782/* 731/*
783 * SPI wrapper. 732 * SPI wrapper.
@@ -785,12 +734,15 @@ int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int leng
785 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input. 734 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
786 * Once this is done, you can call omap_mcbsp_start(). 735 * Once this is done, you can call omap_mcbsp_start().
787 */ 736 */
788void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg) 737void omap_mcbsp_set_spi_mode(unsigned int id,
738 const struct omap_mcbsp_spi_cfg *spi_cfg)
789{ 739{
790 struct omap_mcbsp_reg_cfg mcbsp_cfg; 740 struct omap_mcbsp_reg_cfg mcbsp_cfg;
791 741
792 if (omap_mcbsp_check(id) < 0) 742 if (!omap_mcbsp_check_valid_id(id)) {
743 printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
793 return; 744 return;
745 }
794 746
795 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg)); 747 memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
796 748
@@ -798,7 +750,7 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
798 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0)); 750 mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
799 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0)); 751 mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
800 752
801 /* Clock stop mode */ 753 /* Clock stop mode */
802 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY) 754 if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
803 mcbsp_cfg.spcr1 |= (1 << 12); 755 mcbsp_cfg.spcr1 |= (1 << 12);
804 else 756 else
@@ -827,13 +779,12 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
827 779
828 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) { 780 if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
829 mcbsp_cfg.pcr0 |= CLKXM; 781 mcbsp_cfg.pcr0 |= CLKXM;
830 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div -1); 782 mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
831 mcbsp_cfg.pcr0 |= FSXM; 783 mcbsp_cfg.pcr0 |= FSXM;
832 mcbsp_cfg.srgr2 &= ~FSGM; 784 mcbsp_cfg.srgr2 &= ~FSGM;
833 mcbsp_cfg.xcr2 |= XDATDLY(1); 785 mcbsp_cfg.xcr2 |= XDATDLY(1);
834 mcbsp_cfg.rcr2 |= RDATDLY(1); 786 mcbsp_cfg.rcr2 |= RDATDLY(1);
835 } 787 } else {
836 else {
837 mcbsp_cfg.pcr0 &= ~CLKXM; 788 mcbsp_cfg.pcr0 &= ~CLKXM;
838 mcbsp_cfg.srgr1 |= CLKGDV(1); 789 mcbsp_cfg.srgr1 |= CLKGDV(1);
839 mcbsp_cfg.pcr0 &= ~FSXM; 790 mcbsp_cfg.pcr0 &= ~FSXM;
@@ -846,199 +797,99 @@ void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg *
846 797
847 omap_mcbsp_config(id, &mcbsp_cfg); 798 omap_mcbsp_config(id, &mcbsp_cfg);
848} 799}
849 800EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
850 801
851/* 802/*
852 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510. 803 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
853 * 730 has only 2 McBSP, and both of them are MPU peripherals. 804 * 730 has only 2 McBSP, and both of them are MPU peripherals.
854 */ 805 */
855struct omap_mcbsp_info { 806static int __init omap_mcbsp_probe(struct platform_device *pdev)
856 u32 virt_base; 807{
857 u8 dma_rx_sync, dma_tx_sync; 808 struct omap_mcbsp_platform_data *pdata = pdev->dev.platform_data;
858 u16 rx_irq, tx_irq; 809 int id = pdev->id - 1;
859}; 810 int ret = 0;
860 811
861#ifdef CONFIG_ARCH_OMAP730 812 if (!pdata) {
862static const struct omap_mcbsp_info mcbsp_730[] = { 813 dev_err(&pdev->dev, "McBSP device initialized without"
863 [0] = { .virt_base = io_p2v(OMAP730_MCBSP1_BASE), 814 "platform data\n");
864 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 815 ret = -EINVAL;
865 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 816 goto exit;
866 .rx_irq = INT_730_McBSP1RX, 817 }
867 .tx_irq = INT_730_McBSP1TX }, 818
868 [1] = { .virt_base = io_p2v(OMAP730_MCBSP2_BASE), 819 dev_dbg(&pdev->dev, "Initializing OMAP McBSP (%d).\n", pdev->id);
869 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 820
870 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 821 if (id >= OMAP_MAX_MCBSP_COUNT) {
871 .rx_irq = INT_730_McBSP2RX, 822 dev_err(&pdev->dev, "Invalid McBSP device id (%d)\n", id);
872 .tx_irq = INT_730_McBSP2TX }, 823 ret = -EINVAL;
873}; 824 goto exit;
874#endif 825 }
875 826
876#ifdef CONFIG_ARCH_OMAP15XX 827 spin_lock_init(&mcbsp[id].lock);
877static const struct omap_mcbsp_info mcbsp_1510[] = { 828 mcbsp[id].id = id + 1;
878 [0] = { .virt_base = OMAP1510_MCBSP1_BASE, 829 mcbsp[id].free = 1;
879 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 830 mcbsp[id].dma_tx_lch = -1;
880 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 831 mcbsp[id].dma_rx_lch = -1;
881 .rx_irq = INT_McBSP1RX, 832
882 .tx_irq = INT_McBSP1TX }, 833 mcbsp[id].io_base = pdata->virt_base;
883 [1] = { .virt_base = io_p2v(OMAP1510_MCBSP2_BASE), 834 /* Default I/O is IRQ based */
884 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 835 mcbsp[id].io_type = OMAP_MCBSP_IRQ_IO;
885 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 836 mcbsp[id].tx_irq = pdata->tx_irq;
886 .rx_irq = INT_1510_SPI_RX, 837 mcbsp[id].rx_irq = pdata->rx_irq;
887 .tx_irq = INT_1510_SPI_TX }, 838 mcbsp[id].dma_rx_sync = pdata->dma_rx_sync;
888 [2] = { .virt_base = OMAP1510_MCBSP3_BASE, 839 mcbsp[id].dma_tx_sync = pdata->dma_tx_sync;
889 .dma_rx_sync = OMAP_DMA_MCBSP3_RX, 840
890 .dma_tx_sync = OMAP_DMA_MCBSP3_TX, 841 if (pdata->clk_name)
891 .rx_irq = INT_McBSP3RX, 842 mcbsp[id].clk = clk_get(&pdev->dev, pdata->clk_name);
892 .tx_irq = INT_McBSP3TX }, 843 if (IS_ERR(mcbsp[id].clk)) {
893}; 844 mcbsp[id].free = 0;
894#endif 845 dev_err(&pdev->dev,
895 846 "Invalid clock configuration for McBSP%d.\n",
896#if defined(CONFIG_ARCH_OMAP16XX) 847 mcbsp[id].id);
897static const struct omap_mcbsp_info mcbsp_1610[] = { 848 ret = -EINVAL;
898 [0] = { .virt_base = OMAP1610_MCBSP1_BASE, 849 goto exit;
899 .dma_rx_sync = OMAP_DMA_MCBSP1_RX, 850 }
900 .dma_tx_sync = OMAP_DMA_MCBSP1_TX, 851
901 .rx_irq = INT_McBSP1RX, 852 mcbsp[id].pdata = pdata;
902 .tx_irq = INT_McBSP1TX }, 853 mcbsp[id].dev = &pdev->dev;
903 [1] = { .virt_base = io_p2v(OMAP1610_MCBSP2_BASE), 854 platform_set_drvdata(pdev, &mcbsp[id]);
904 .dma_rx_sync = OMAP_DMA_MCBSP2_RX, 855
905 .dma_tx_sync = OMAP_DMA_MCBSP2_TX, 856exit:
906 .rx_irq = INT_1610_McBSP2_RX, 857 return ret;
907 .tx_irq = INT_1610_McBSP2_TX }, 858}
908 [2] = { .virt_base = OMAP1610_MCBSP3_BASE,
909 .dma_rx_sync = OMAP_DMA_MCBSP3_RX,
910 .dma_tx_sync = OMAP_DMA_MCBSP3_TX,
911 .rx_irq = INT_McBSP3RX,
912 .tx_irq = INT_McBSP3TX },
913};
914#endif
915
916#if defined(CONFIG_ARCH_OMAP24XX)
917static const struct omap_mcbsp_info mcbsp_24xx[] = {
918 [0] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP1_BASE),
919 .dma_rx_sync = OMAP24XX_DMA_MCBSP1_RX,
920 .dma_tx_sync = OMAP24XX_DMA_MCBSP1_TX,
921 .rx_irq = INT_24XX_MCBSP1_IRQ_RX,
922 .tx_irq = INT_24XX_MCBSP1_IRQ_TX,
923 },
924 [1] = { .virt_base = IO_ADDRESS(OMAP24XX_MCBSP2_BASE),
925 .dma_rx_sync = OMAP24XX_DMA_MCBSP2_RX,
926 .dma_tx_sync = OMAP24XX_DMA_MCBSP2_TX,
927 .rx_irq = INT_24XX_MCBSP2_IRQ_RX,
928 .tx_irq = INT_24XX_MCBSP2_IRQ_TX,
929 },
930};
931#endif
932 859
933static int __init omap_mcbsp_init(void) 860static int omap_mcbsp_remove(struct platform_device *pdev)
934{ 861{
935 int mcbsp_count = 0, i; 862 struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
936 static const struct omap_mcbsp_info *mcbsp_info;
937 863
938 printk("Initializing OMAP McBSP system\n"); 864 platform_set_drvdata(pdev, NULL);
865 if (mcbsp) {
939 866
940#ifdef CONFIG_ARCH_OMAP1 867 if (mcbsp->pdata && mcbsp->pdata->ops &&
941 mcbsp_dsp_ck = clk_get(0, "dsp_ck"); 868 mcbsp->pdata->ops->free)
942 if (IS_ERR(mcbsp_dsp_ck)) { 869 mcbsp->pdata->ops->free(mcbsp->id);
943 printk(KERN_ERR "mcbsp: could not acquire dsp_ck handle.\n");
944 return PTR_ERR(mcbsp_dsp_ck);
945 }
946 mcbsp_api_ck = clk_get(0, "api_ck");
947 if (IS_ERR(mcbsp_api_ck)) {
948 printk(KERN_ERR "mcbsp: could not acquire api_ck handle.\n");
949 return PTR_ERR(mcbsp_api_ck);
950 }
951 mcbsp_dspxor_ck = clk_get(0, "dspxor_ck");
952 if (IS_ERR(mcbsp_dspxor_ck)) {
953 printk(KERN_ERR "mcbsp: could not acquire dspxor_ck handle.\n");
954 return PTR_ERR(mcbsp_dspxor_ck);
955 }
956#endif
957#ifdef CONFIG_ARCH_OMAP2
958 mcbsp1_ick = clk_get(0, "mcbsp1_ick");
959 if (IS_ERR(mcbsp1_ick)) {
960 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_ick handle.\n");
961 return PTR_ERR(mcbsp1_ick);
962 }
963 mcbsp1_fck = clk_get(0, "mcbsp1_fck");
964 if (IS_ERR(mcbsp1_fck)) {
965 printk(KERN_ERR "mcbsp: could not acquire mcbsp1_fck handle.\n");
966 return PTR_ERR(mcbsp1_fck);
967 }
968 mcbsp2_ick = clk_get(0, "mcbsp2_ick");
969 if (IS_ERR(mcbsp2_ick)) {
970 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_ick handle.\n");
971 return PTR_ERR(mcbsp2_ick);
972 }
973 mcbsp2_fck = clk_get(0, "mcbsp2_fck");
974 if (IS_ERR(mcbsp2_fck)) {
975 printk(KERN_ERR "mcbsp: could not acquire mcbsp2_fck handle.\n");
976 return PTR_ERR(mcbsp2_fck);
977 }
978#endif
979 870
980#ifdef CONFIG_ARCH_OMAP730 871 clk_disable(mcbsp->clk);
981 if (cpu_is_omap730()) { 872 clk_put(mcbsp->clk);
982 mcbsp_info = mcbsp_730; 873
983 mcbsp_count = ARRAY_SIZE(mcbsp_730); 874 mcbsp->clk = NULL;
984 } 875 mcbsp->free = 0;
985#endif 876 mcbsp->dev = NULL;
986#ifdef CONFIG_ARCH_OMAP15XX
987 if (cpu_is_omap15xx()) {
988 mcbsp_info = mcbsp_1510;
989 mcbsp_count = ARRAY_SIZE(mcbsp_1510);
990 }
991#endif
992#if defined(CONFIG_ARCH_OMAP16XX)
993 if (cpu_is_omap16xx()) {
994 mcbsp_info = mcbsp_1610;
995 mcbsp_count = ARRAY_SIZE(mcbsp_1610);
996 }
997#endif
998#if defined(CONFIG_ARCH_OMAP24XX)
999 if (cpu_is_omap24xx()) {
1000 mcbsp_info = mcbsp_24xx;
1001 mcbsp_count = ARRAY_SIZE(mcbsp_24xx);
1002 omap2_mcbsp2_mux_setup();
1003 }
1004#endif
1005 for (i = 0; i < OMAP_MAX_MCBSP_COUNT ; i++) {
1006 if (i >= mcbsp_count) {
1007 mcbsp[i].io_base = 0;
1008 mcbsp[i].free = 0;
1009 continue;
1010 }
1011 mcbsp[i].id = i + 1;
1012 mcbsp[i].free = 1;
1013 mcbsp[i].dma_tx_lch = -1;
1014 mcbsp[i].dma_rx_lch = -1;
1015
1016 mcbsp[i].io_base = mcbsp_info[i].virt_base;
1017 mcbsp[i].io_type = OMAP_MCBSP_IRQ_IO; /* Default I/O is IRQ based */
1018 mcbsp[i].tx_irq = mcbsp_info[i].tx_irq;
1019 mcbsp[i].rx_irq = mcbsp_info[i].rx_irq;
1020 mcbsp[i].dma_rx_sync = mcbsp_info[i].dma_rx_sync;
1021 mcbsp[i].dma_tx_sync = mcbsp_info[i].dma_tx_sync;
1022 spin_lock_init(&mcbsp[i].lock);
1023 } 877 }
1024 878
1025 return 0; 879 return 0;
1026} 880}
1027 881
1028arch_initcall(omap_mcbsp_init); 882static struct platform_driver omap_mcbsp_driver = {
883 .probe = omap_mcbsp_probe,
884 .remove = omap_mcbsp_remove,
885 .driver = {
886 .name = "omap-mcbsp",
887 },
888};
889
890int __init omap_mcbsp_init(void)
891{
892 /* Register the McBSP driver */
893 return platform_driver_register(&omap_mcbsp_driver);
894}
1029 895
1030EXPORT_SYMBOL(omap_mcbsp_config);
1031EXPORT_SYMBOL(omap_mcbsp_request);
1032EXPORT_SYMBOL(omap_mcbsp_set_io_type);
1033EXPORT_SYMBOL(omap_mcbsp_free);
1034EXPORT_SYMBOL(omap_mcbsp_start);
1035EXPORT_SYMBOL(omap_mcbsp_stop);
1036EXPORT_SYMBOL(omap_mcbsp_pollread);
1037EXPORT_SYMBOL(omap_mcbsp_pollwrite);
1038EXPORT_SYMBOL(omap_mcbsp_xmit_word);
1039EXPORT_SYMBOL(omap_mcbsp_recv_word);
1040EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
1041EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
1042EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
1043EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
1044EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index 1f23f0459e5f..554ee58e1294 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -10,6 +10,7 @@
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13#undef DEBUG
13 14
14#include <linux/module.h> 15#include <linux/module.h>
15#include <linux/kernel.h> 16#include <linux/kernel.h>
@@ -24,25 +25,43 @@
24#include <asm/arch/sram.h> 25#include <asm/arch/sram.h>
25#include <asm/arch/board.h> 26#include <asm/arch/board.h>
26 27
28#include <asm/arch/control.h>
29
30#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
31# include "../mach-omap2/prm.h"
32# include "../mach-omap2/cm.h"
33# include "../mach-omap2/sdrc.h"
34#endif
35
27#define OMAP1_SRAM_PA 0x20000000 36#define OMAP1_SRAM_PA 0x20000000
28#define OMAP1_SRAM_VA 0xd0000000 37#define OMAP1_SRAM_VA VMALLOC_END
29#define OMAP2_SRAM_PA 0x40200000 38#define OMAP2_SRAM_PA 0x40200000
30#define OMAP2_SRAM_PUB_PA 0x4020f800 39#define OMAP2_SRAM_PUB_PA 0x4020f800
31#define OMAP2_SRAM_VA 0xd0000000 40#define OMAP2_SRAM_VA VMALLOC_END
32#define OMAP2_SRAM_PUB_VA 0xd0000800 41#define OMAP2_SRAM_PUB_VA (VMALLOC_END + 0x800)
33 42#define OMAP3_SRAM_PA 0x40200000
34#if defined(CONFIG_ARCH_OMAP24XX) 43#define OMAP3_SRAM_VA 0xd7000000
44#define OMAP3_SRAM_PUB_PA 0x40208000
45#define OMAP3_SRAM_PUB_VA 0xd7008000
46
47#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
35#define SRAM_BOOTLOADER_SZ 0x00 48#define SRAM_BOOTLOADER_SZ 0x00
36#else 49#else
37#define SRAM_BOOTLOADER_SZ 0x80 50#define SRAM_BOOTLOADER_SZ 0x80
38#endif 51#endif
39 52
40#define VA_REQINFOPERM0 IO_ADDRESS(0x68005048) 53#define OMAP24XX_VA_REQINFOPERM0 IO_ADDRESS(0x68005048)
41#define VA_READPERM0 IO_ADDRESS(0x68005050) 54#define OMAP24XX_VA_READPERM0 IO_ADDRESS(0x68005050)
42#define VA_WRITEPERM0 IO_ADDRESS(0x68005058) 55#define OMAP24XX_VA_WRITEPERM0 IO_ADDRESS(0x68005058)
43#define VA_CONTROL_STAT IO_ADDRESS(0x480002F8) 56
57#define OMAP34XX_VA_REQINFOPERM0 IO_ADDRESS(0x68012848)
58#define OMAP34XX_VA_READPERM0 IO_ADDRESS(0x68012850)
59#define OMAP34XX_VA_WRITEPERM0 IO_ADDRESS(0x68012858)
60#define OMAP34XX_VA_ADDR_MATCH2 IO_ADDRESS(0x68012880)
61#define OMAP34XX_VA_SMS_RG_ATT0 IO_ADDRESS(0x6C000048)
62#define OMAP34XX_VA_CONTROL_STAT IO_ADDRESS(0x480022F0)
63
44#define GP_DEVICE 0x300 64#define GP_DEVICE 0x300
45#define TYPE_MASK 0x700
46 65
47#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1))) 66#define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
48 67
@@ -68,14 +87,21 @@ static int is_sram_locked(void)
68 int type = 0; 87 int type = 0;
69 88
70 if (cpu_is_omap242x()) 89 if (cpu_is_omap242x())
71 type = __raw_readl(VA_CONTROL_STAT) & TYPE_MASK; 90 type = system_rev & OMAP2_DEVICETYPE_MASK;
72 91
73 if (type == GP_DEVICE) { 92 if (type == GP_DEVICE) {
74 /* RAMFW: R/W access to all initiators for all qualifier sets */ 93 /* RAMFW: R/W access to all initiators for all qualifier sets */
75 if (cpu_is_omap242x()) { 94 if (cpu_is_omap242x()) {
76 __raw_writel(0xFF, VA_REQINFOPERM0); /* all q-vects */ 95 __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
77 __raw_writel(0xCFDE, VA_READPERM0); /* all i-read */ 96 __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0); /* all i-read */
78 __raw_writel(0xCFDE, VA_WRITEPERM0); /* all i-write */ 97 __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
98 }
99 if (cpu_is_omap34xx()) {
100 __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
101 __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0); /* all i-read */
102 __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
103 __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
104 __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
79 } 105 }
80 return 0; 106 return 0;
81 } else 107 } else
@@ -92,18 +118,30 @@ void __init omap_detect_sram(void)
92{ 118{
93 unsigned long reserved; 119 unsigned long reserved;
94 120
95 if (cpu_is_omap24xx()) { 121 if (cpu_class_is_omap2()) {
96 if (is_sram_locked()) { 122 if (is_sram_locked()) {
97 omap_sram_base = OMAP2_SRAM_PUB_VA; 123 if (cpu_is_omap34xx()) {
98 omap_sram_start = OMAP2_SRAM_PUB_PA; 124 omap_sram_base = OMAP3_SRAM_PUB_VA;
99 omap_sram_size = 0x800; /* 2K */ 125 omap_sram_start = OMAP3_SRAM_PUB_PA;
126 omap_sram_size = 0x8000; /* 32K */
127 } else {
128 omap_sram_base = OMAP2_SRAM_PUB_VA;
129 omap_sram_start = OMAP2_SRAM_PUB_PA;
130 omap_sram_size = 0x800; /* 2K */
131 }
100 } else { 132 } else {
101 omap_sram_base = OMAP2_SRAM_VA; 133 if (cpu_is_omap34xx()) {
102 omap_sram_start = OMAP2_SRAM_PA; 134 omap_sram_base = OMAP3_SRAM_VA;
103 if (cpu_is_omap242x()) 135 omap_sram_start = OMAP3_SRAM_PA;
104 omap_sram_size = 0xa0000; /* 640K */
105 else if (cpu_is_omap243x())
106 omap_sram_size = 0x10000; /* 64K */ 136 omap_sram_size = 0x10000; /* 64K */
137 } else {
138 omap_sram_base = OMAP2_SRAM_VA;
139 omap_sram_start = OMAP2_SRAM_PA;
140 if (cpu_is_omap242x())
141 omap_sram_size = 0xa0000; /* 640K */
142 else if (cpu_is_omap243x())
143 omap_sram_size = 0x10000; /* 64K */
144 }
107 } 145 }
108 } else { 146 } else {
109 omap_sram_base = OMAP1_SRAM_VA; 147 omap_sram_base = OMAP1_SRAM_VA;
@@ -157,6 +195,13 @@ void __init omap_map_sram(void)
157 omap_sram_io_desc[0].pfn = __phys_to_pfn(base); 195 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
158 } 196 }
159 197
198 if (cpu_is_omap34xx()) {
199 omap_sram_io_desc[0].virtual = OMAP3_SRAM_VA;
200 base = OMAP3_SRAM_PA;
201 base = ROUND_DOWN(base, PAGE_SIZE);
202 omap_sram_io_desc[0].pfn = __phys_to_pfn(base);
203 }
204
160 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */ 205 omap_sram_io_desc[0].length = 1024 * 1024; /* Use section desc */
161 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc)); 206 iotable_init(omap_sram_io_desc, ARRAY_SIZE(omap_sram_io_desc));
162 207
@@ -191,6 +236,7 @@ void * omap_sram_push(void * start, unsigned long size)
191 omap_sram_ceil -= size; 236 omap_sram_ceil -= size;
192 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *)); 237 omap_sram_ceil = ROUND_DOWN(omap_sram_ceil, sizeof(void *));
193 memcpy((void *)omap_sram_ceil, start, size); 238 memcpy((void *)omap_sram_ceil, start, size);
239 flush_icache_range((unsigned long)start, (unsigned long)(start + size));
194 240
195 return (void *)omap_sram_ceil; 241 return (void *)omap_sram_ceil;
196} 242}
@@ -214,8 +260,9 @@ void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
214 260
215int __init omap1_sram_init(void) 261int __init omap1_sram_init(void)
216{ 262{
217 _omap_sram_reprogram_clock = omap_sram_push(sram_reprogram_clock, 263 _omap_sram_reprogram_clock =
218 sram_reprogram_clock_sz); 264 omap_sram_push(omap1_sram_reprogram_clock,
265 omap1_sram_reprogram_clock_sz);
219 266
220 return 0; 267 return 0;
221} 268}
@@ -224,7 +271,7 @@ int __init omap1_sram_init(void)
224#define omap1_sram_init() do {} while (0) 271#define omap1_sram_init() do {} while (0)
225#endif 272#endif
226 273
227#ifdef CONFIG_ARCH_OMAP2 274#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
228 275
229static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 276static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
230 u32 base_cs, u32 force_unlock); 277 u32 base_cs, u32 force_unlock);
@@ -259,19 +306,109 @@ u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
259 306
260 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass); 307 return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
261} 308}
309#endif
310
311#ifdef CONFIG_ARCH_OMAP2420
312int __init omap242x_sram_init(void)
313{
314 _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
315 omap242x_sram_ddr_init_sz);
316
317 _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
318 omap242x_sram_reprogram_sdrc_sz);
319
320 _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
321 omap242x_sram_set_prcm_sz);
322
323 return 0;
324}
325#else
326static inline int omap242x_sram_init(void)
327{
328 return 0;
329}
330#endif
331
332#ifdef CONFIG_ARCH_OMAP2430
333int __init omap243x_sram_init(void)
334{
335 _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
336 omap243x_sram_ddr_init_sz);
337
338 _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
339 omap243x_sram_reprogram_sdrc_sz);
340
341 _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
342 omap243x_sram_set_prcm_sz);
343
344 return 0;
345}
346#else
347static inline int omap243x_sram_init(void)
348{
349 return 0;
350}
351#endif
352
353#ifdef CONFIG_ARCH_OMAP3
354
355static u32 (*_omap2_sram_reprogram_gpmc)(u32 perf_level);
356u32 omap2_sram_reprogram_gpmc(u32 perf_level)
357{
358 if (!_omap2_sram_reprogram_gpmc)
359 omap_sram_error();
360
361 return _omap2_sram_reprogram_gpmc(perf_level);
362}
363
364static u32 (*_omap2_sram_configure_core_dpll)(u32 m, u32 n,
365 u32 freqsel, u32 m2);
366u32 omap2_sram_configure_core_dpll(u32 m, u32 n, u32 freqsel, u32 m2)
367{
368 if (!_omap2_sram_configure_core_dpll)
369 omap_sram_error();
370
371 return _omap2_sram_configure_core_dpll(m, n, freqsel, m2);
372}
262 373
263int __init omap2_sram_init(void) 374/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
375void restore_sram_functions(void)
264{ 376{
265 _omap2_sram_ddr_init = omap_sram_push(sram_ddr_init, sram_ddr_init_sz); 377 omap_sram_ceil = omap_sram_base + omap_sram_size;
266 378
267 _omap2_sram_reprogram_sdrc = omap_sram_push(sram_reprogram_sdrc, 379 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
268 sram_reprogram_sdrc_sz); 380 omap34xx_sram_reprogram_gpmc_sz);
269 _omap2_set_prcm = omap_sram_push(sram_set_prcm, sram_set_prcm_sz); 381
382 _omap2_sram_configure_core_dpll =
383 omap_sram_push(omap34xx_sram_configure_core_dpll,
384 omap34xx_sram_configure_core_dpll_sz);
385}
386
387int __init omap34xx_sram_init(void)
388{
389 _omap2_sram_ddr_init = omap_sram_push(omap34xx_sram_ddr_init,
390 omap34xx_sram_ddr_init_sz);
391
392 _omap2_sram_reprogram_sdrc = omap_sram_push(omap34xx_sram_reprogram_sdrc,
393 omap34xx_sram_reprogram_sdrc_sz);
394
395 _omap2_set_prcm = omap_sram_push(omap34xx_sram_set_prcm,
396 omap34xx_sram_set_prcm_sz);
397
398 _omap2_sram_reprogram_gpmc = omap_sram_push(omap34xx_sram_reprogram_gpmc,
399 omap34xx_sram_reprogram_gpmc_sz);
400
401 _omap2_sram_configure_core_dpll =
402 omap_sram_push(omap34xx_sram_configure_core_dpll,
403 omap34xx_sram_configure_core_dpll_sz);
270 404
271 return 0; 405 return 0;
272} 406}
273#else 407#else
274#define omap2_sram_init() do {} while (0) 408static inline int omap34xx_sram_init(void)
409{
410 return 0;
411}
275#endif 412#endif
276 413
277int __init omap_sram_init(void) 414int __init omap_sram_init(void)
@@ -279,10 +416,14 @@ int __init omap_sram_init(void)
279 omap_detect_sram(); 416 omap_detect_sram();
280 omap_map_sram(); 417 omap_map_sram();
281 418
282 if (!cpu_is_omap24xx()) 419 if (!(cpu_class_is_omap2()))
283 omap1_sram_init(); 420 omap1_sram_init();
284 else 421 else if (cpu_is_omap242x())
285 omap2_sram_init(); 422 omap242x_sram_init();
423 else if (cpu_is_omap2430())
424 omap243x_sram_init();
425 else if (cpu_is_omap34xx())
426 omap34xx_sram_init();
286 427
287 return 0; 428 return 0;
288} 429}
diff --git a/arch/arm/plat-omap/usb.c b/arch/arm/plat-omap/usb.c
index a619475c4b76..2699c16d4da0 100644
--- a/arch/arm/plat-omap/usb.c
+++ b/arch/arm/plat-omap/usb.c
@@ -1,4 +1,4 @@
1/* 1 /*
2 * arch/arm/plat-omap/usb.c -- platform level USB initialization 2 * arch/arm/plat-omap/usb.c -- platform level USB initialization
3 * 3 *
4 * Copyright (C) 2004 Texas Instruments, Inc. 4 * Copyright (C) 2004 Texas Instruments, Inc.
@@ -156,8 +156,12 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
156 156
157 if (nwires == 0) { 157 if (nwires == 0) {
158 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { 158 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
159 u32 l;
160
159 /* pulldown D+/D- */ 161 /* pulldown D+/D- */
160 USB_TRANSCEIVER_CTRL_REG &= ~(3 << 1); 162 l = omap_readl(USB_TRANSCEIVER_CTRL);
163 l &= ~(3 << 1);
164 omap_writel(l, USB_TRANSCEIVER_CTRL);
161 } 165 }
162 return 0; 166 return 0;
163 } 167 }
@@ -171,6 +175,8 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
171 175
172 /* internal transceiver (unavailable on 17xx, 24xx) */ 176 /* internal transceiver (unavailable on 17xx, 24xx) */
173 if (!cpu_class_is_omap2() && nwires == 2) { 177 if (!cpu_class_is_omap2() && nwires == 2) {
178 u32 l;
179
174 // omap_cfg_reg(P9_USB_DP); 180 // omap_cfg_reg(P9_USB_DP);
175 // omap_cfg_reg(R8_USB_DM); 181 // omap_cfg_reg(R8_USB_DM);
176 182
@@ -185,9 +191,11 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
185 * - OTG support on this port not yet written 191 * - OTG support on this port not yet written
186 */ 192 */
187 193
188 USB_TRANSCEIVER_CTRL_REG &= ~(7 << 4); 194 l = omap_readl(USB_TRANSCEIVER_CTRL);
195 l &= ~(7 << 4);
189 if (!is_device) 196 if (!is_device)
190 USB_TRANSCEIVER_CTRL_REG |= (3 << 1); 197 l |= (3 << 1);
198 omap_writel(l, USB_TRANSCEIVER_CTRL);
191 199
192 return 3 << 16; 200 return 3 << 16;
193 } 201 }
@@ -217,8 +225,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
217 * with VBUS switching and overcurrent detection. 225 * with VBUS switching and overcurrent detection.
218 */ 226 */
219 227
220 if (cpu_class_is_omap1() && nwires != 6) 228 if (cpu_class_is_omap1() && nwires != 6) {
221 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; 229 u32 l;
230
231 l = omap_readl(USB_TRANSCEIVER_CTRL);
232 l &= ~CONF_USB2_UNI_R;
233 omap_writel(l, USB_TRANSCEIVER_CTRL);
234 }
222 235
223 switch (nwires) { 236 switch (nwires) {
224 case 3: 237 case 3:
@@ -238,9 +251,13 @@ static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device)
238 omap_cfg_reg(K20_24XX_USB0_VM); 251 omap_cfg_reg(K20_24XX_USB0_VM);
239 omap2_usb_devconf_set(0, USB_UNIDIR); 252 omap2_usb_devconf_set(0, USB_UNIDIR);
240 } else { 253 } else {
254 u32 l;
255
241 omap_cfg_reg(AA9_USB0_VP); 256 omap_cfg_reg(AA9_USB0_VP);
242 omap_cfg_reg(R9_USB0_VM); 257 omap_cfg_reg(R9_USB0_VM);
243 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; 258 l = omap_readl(USB_TRANSCEIVER_CTRL);
259 l |= CONF_USB2_UNI_R;
260 omap_writel(l, USB_TRANSCEIVER_CTRL);
244 } 261 }
245 break; 262 break;
246 default: 263 default:
@@ -254,8 +271,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
254{ 271{
255 u32 syscon1 = 0; 272 u32 syscon1 = 0;
256 273
257 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) 274 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
258 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB1_UNI_R; 275 u32 l;
276
277 l = omap_readl(USB_TRANSCEIVER_CTRL);
278 l &= ~CONF_USB1_UNI_R;
279 omap_writel(l, USB_TRANSCEIVER_CTRL);
280 }
259 if (cpu_is_omap24xx()) 281 if (cpu_is_omap24xx())
260 omap2_usb_devconf_clear(1, USB_BIDIR_TLL); 282 omap2_usb_devconf_clear(1, USB_BIDIR_TLL);
261 283
@@ -316,8 +338,13 @@ static u32 __init omap_usb1_init(unsigned nwires)
316 syscon1 = 3; 338 syscon1 = 3;
317 omap_cfg_reg(USB1_VP); 339 omap_cfg_reg(USB1_VP);
318 omap_cfg_reg(USB1_VM); 340 omap_cfg_reg(USB1_VM);
319 if (!cpu_is_omap15xx()) 341 if (!cpu_is_omap15xx()) {
320 USB_TRANSCEIVER_CTRL_REG |= CONF_USB1_UNI_R; 342 u32 l;
343
344 l = omap_readl(USB_TRANSCEIVER_CTRL);
345 l |= CONF_USB1_UNI_R;
346 omap_writel(l, USB_TRANSCEIVER_CTRL);
347 }
321 break; 348 break;
322 default: 349 default:
323bad: 350bad:
@@ -340,8 +367,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
340 if (alt_pingroup || nwires == 0) 367 if (alt_pingroup || nwires == 0)
341 return 0; 368 return 0;
342 369
343 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) 370 if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) {
344 USB_TRANSCEIVER_CTRL_REG &= ~CONF_USB2_UNI_R; 371 u32 l;
372
373 l = omap_readl(USB_TRANSCEIVER_CTRL);
374 l &= ~CONF_USB2_UNI_R;
375 omap_writel(l, USB_TRANSCEIVER_CTRL);
376 }
345 377
346 /* external transceiver */ 378 /* external transceiver */
347 if (cpu_is_omap15xx()) { 379 if (cpu_is_omap15xx()) {
@@ -410,9 +442,13 @@ static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup)
410 omap_cfg_reg(USB2_VP); 442 omap_cfg_reg(USB2_VP);
411 omap_cfg_reg(USB2_VM); 443 omap_cfg_reg(USB2_VM);
412 } else { 444 } else {
445 u32 l;
446
413 omap_cfg_reg(AA9_USB2_VP); 447 omap_cfg_reg(AA9_USB2_VP);
414 omap_cfg_reg(R9_USB2_VM); 448 omap_cfg_reg(R9_USB2_VM);
415 USB_TRANSCEIVER_CTRL_REG |= CONF_USB2_UNI_R; 449 l = omap_readl(USB_TRANSCEIVER_CTRL);
450 l |= CONF_USB2_UNI_R;
451 omap_writel(l, USB_TRANSCEIVER_CTRL);
416 } 452 }
417 break; 453 break;
418 default: 454 default:
@@ -531,10 +567,6 @@ static struct platform_device otg_device = {
531 567
532/*-------------------------------------------------------------------------*/ 568/*-------------------------------------------------------------------------*/
533 569
534#define ULPD_CLOCK_CTRL_REG __REG16(ULPD_CLOCK_CTRL)
535#define ULPD_SOFT_REQ_REG __REG16(ULPD_SOFT_REQ)
536
537
538// FIXME correct answer depends on hmc_mode, 570// FIXME correct answer depends on hmc_mode,
539// as does (on omap1) any nonzero value for config->otg port number 571// as does (on omap1) any nonzero value for config->otg port number
540#ifdef CONFIG_USB_GADGET_OMAP 572#ifdef CONFIG_USB_GADGET_OMAP
@@ -550,17 +582,17 @@ static struct platform_device otg_device = {
550void __init 582void __init
551omap_otg_init(struct omap_usb_config *config) 583omap_otg_init(struct omap_usb_config *config)
552{ 584{
553 u32 syscon = OTG_SYSCON_1_REG & 0xffff; 585 u32 syscon;
554 int status; 586 int status;
555 int alt_pingroup = 0; 587 int alt_pingroup = 0;
556 588
557 /* NOTE: no bus or clock setup (yet?) */ 589 /* NOTE: no bus or clock setup (yet?) */
558 590
559 syscon = OTG_SYSCON_1_REG & 0xffff; 591 syscon = omap_readl(OTG_SYSCON_1) & 0xffff;
560 if (!(syscon & OTG_RESET_DONE)) 592 if (!(syscon & OTG_RESET_DONE))
561 pr_debug("USB resets not complete?\n"); 593 pr_debug("USB resets not complete?\n");
562 594
563 // OTG_IRQ_EN_REG = 0; 595 //omap_writew(0, OTG_IRQ_EN);
564 596
565 /* pin muxing and transceiver pinouts */ 597 /* pin muxing and transceiver pinouts */
566 if (config->pins[0] > 2) /* alt pingroup 2 */ 598 if (config->pins[0] > 2) /* alt pingroup 2 */
@@ -568,8 +600,8 @@ omap_otg_init(struct omap_usb_config *config)
568 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); 600 syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config));
569 syscon |= omap_usb1_init(config->pins[1]); 601 syscon |= omap_usb1_init(config->pins[1]);
570 syscon |= omap_usb2_init(config->pins[2], alt_pingroup); 602 syscon |= omap_usb2_init(config->pins[2], alt_pingroup);
571 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); 603 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
572 OTG_SYSCON_1_REG = syscon; 604 omap_writel(syscon, OTG_SYSCON_1);
573 605
574 syscon = config->hmc_mode; 606 syscon = config->hmc_mode;
575 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; 607 syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */;
@@ -578,9 +610,10 @@ omap_otg_init(struct omap_usb_config *config)
578 syscon |= OTG_EN; 610 syscon |= OTG_EN;
579#endif 611#endif
580 if (cpu_class_is_omap1()) 612 if (cpu_class_is_omap1())
581 pr_debug("USB_TRANSCEIVER_CTRL_REG = %03x\n", USB_TRANSCEIVER_CTRL_REG); 613 pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
582 pr_debug("OTG_SYSCON_2_REG = %08x\n", syscon); 614 omap_readl(USB_TRANSCEIVER_CTRL));
583 OTG_SYSCON_2_REG = syscon; 615 pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
616 omap_writel(syscon, OTG_SYSCON_2);
584 617
585 printk("USB: hmc %d", config->hmc_mode); 618 printk("USB: hmc %d", config->hmc_mode);
586 if (!alt_pingroup) 619 if (!alt_pingroup)
@@ -597,12 +630,19 @@ omap_otg_init(struct omap_usb_config *config)
597 printk("\n"); 630 printk("\n");
598 631
599 if (cpu_class_is_omap1()) { 632 if (cpu_class_is_omap1()) {
633 u16 w;
634
600 /* leave USB clocks/controllers off until needed */ 635 /* leave USB clocks/controllers off until needed */
601 ULPD_SOFT_REQ_REG &= ~SOFT_USB_CLK_REQ; 636 w = omap_readw(ULPD_SOFT_REQ);
602 ULPD_CLOCK_CTRL_REG &= ~USB_MCLK_EN; 637 w &= ~SOFT_USB_CLK_REQ;
603 ULPD_CLOCK_CTRL_REG |= DIS_USB_PVCI_CLK; 638 omap_writew(w, ULPD_SOFT_REQ);
639
640 w = omap_readw(ULPD_CLOCK_CTRL);
641 w &= ~USB_MCLK_EN;
642 w |= DIS_USB_PVCI_CLK;
643 omap_writew(w, ULPD_CLOCK_CTRL);
604 } 644 }
605 syscon = OTG_SYSCON_1_REG; 645 syscon = omap_readl(OTG_SYSCON_1);
606 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; 646 syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
607 647
608#ifdef CONFIG_USB_GADGET_OMAP 648#ifdef CONFIG_USB_GADGET_OMAP
@@ -639,8 +679,8 @@ omap_otg_init(struct omap_usb_config *config)
639 pr_debug("can't register OTG device, %d\n", status); 679 pr_debug("can't register OTG device, %d\n", status);
640 } 680 }
641#endif 681#endif
642 pr_debug("OTG_SYSCON_1_REG = %08x\n", syscon); 682 pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1));
643 OTG_SYSCON_1_REG = syscon; 683 omap_writel(syscon, OTG_SYSCON_1);
644 684
645 status = 0; 685 status = 0;
646} 686}
@@ -653,18 +693,19 @@ static inline void omap_otg_init(struct omap_usb_config *config) {}
653 693
654#ifdef CONFIG_ARCH_OMAP15XX 694#ifdef CONFIG_ARCH_OMAP15XX
655 695
656#define ULPD_DPLL_CTRL_REG __REG16(ULPD_DPLL_CTRL) 696/* ULPD_DPLL_CTRL */
657#define DPLL_IOB (1 << 13) 697#define DPLL_IOB (1 << 13)
658#define DPLL_PLL_ENABLE (1 << 4) 698#define DPLL_PLL_ENABLE (1 << 4)
659#define DPLL_LOCK (1 << 0) 699#define DPLL_LOCK (1 << 0)
660 700
661#define ULPD_APLL_CTRL_REG __REG16(ULPD_APLL_CTRL) 701/* ULPD_APLL_CTRL */
662#define APLL_NDPLL_SWITCH (1 << 0) 702#define APLL_NDPLL_SWITCH (1 << 0)
663 703
664 704
665static void __init omap_1510_usb_init(struct omap_usb_config *config) 705static void __init omap_1510_usb_init(struct omap_usb_config *config)
666{ 706{
667 unsigned int val; 707 unsigned int val;
708 u16 w;
668 709
669 omap_usb0_init(config->pins[0], is_usb0_device(config)); 710 omap_usb0_init(config->pins[0], is_usb0_device(config));
670 omap_usb1_init(config->pins[1]); 711 omap_usb1_init(config->pins[1]);
@@ -685,12 +726,22 @@ static void __init omap_1510_usb_init(struct omap_usb_config *config)
685 printk("\n"); 726 printk("\n");
686 727
687 /* use DPLL for 48 MHz function clock */ 728 /* use DPLL for 48 MHz function clock */
688 pr_debug("APLL %04x DPLL %04x REQ %04x\n", ULPD_APLL_CTRL_REG, 729 pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
689 ULPD_DPLL_CTRL_REG, ULPD_SOFT_REQ_REG); 730 omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ));
690 ULPD_APLL_CTRL_REG &= ~APLL_NDPLL_SWITCH; 731
691 ULPD_DPLL_CTRL_REG |= DPLL_IOB | DPLL_PLL_ENABLE; 732 w = omap_readw(ULPD_APLL_CTRL);
692 ULPD_SOFT_REQ_REG |= SOFT_UDC_REQ | SOFT_DPLL_REQ; 733 w &= ~APLL_NDPLL_SWITCH;
693 while (!(ULPD_DPLL_CTRL_REG & DPLL_LOCK)) 734 omap_writew(w, ULPD_APLL_CTRL);
735
736 w = omap_readw(ULPD_DPLL_CTRL);
737 w |= DPLL_IOB | DPLL_PLL_ENABLE;
738 omap_writew(w, ULPD_DPLL_CTRL);
739
740 w = omap_readw(ULPD_SOFT_REQ);
741 w |= SOFT_UDC_REQ | SOFT_DPLL_REQ;
742 omap_writew(w, ULPD_SOFT_REQ);
743
744 while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK))
694 cpu_relax(); 745 cpu_relax();
695 746
696#ifdef CONFIG_USB_GADGET_OMAP 747#ifdef CONFIG_USB_GADGET_OMAP
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index c5b669d234bc..fe66a1835169 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -36,8 +36,8 @@ static void orion_irq_unmask(u32 irq)
36 36
37static struct irq_chip orion_irq_chip = { 37static struct irq_chip orion_irq_chip = {
38 .name = "orion_irq", 38 .name = "orion_irq",
39 .ack = orion_irq_mask,
40 .mask = orion_irq_mask, 39 .mask = orion_irq_mask,
40 .mask_ack = orion_irq_mask,
41 .unmask = orion_irq_unmask, 41 .unmask = orion_irq_unmask,
42}; 42};
43 43
@@ -59,6 +59,7 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
59 set_irq_chip(irq, &orion_irq_chip); 59 set_irq_chip(irq, &orion_irq_chip);
60 set_irq_chip_data(irq, maskaddr); 60 set_irq_chip_data(irq, maskaddr);
61 set_irq_handler(irq, handle_level_irq); 61 set_irq_handler(irq, handle_level_irq);
62 irq_desc[irq].status |= IRQ_LEVEL;
62 set_irq_flags(irq, IRQF_VALID); 63 set_irq_flags(irq, IRQF_VALID);
63 } 64 }
64} 65}
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index abfda53f1800..ca32c60e14d7 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -39,6 +39,7 @@
39#define PCIE_CONF_DATA_OFF 0x18fc 39#define PCIE_CONF_DATA_OFF 0x18fc
40#define PCIE_MASK_OFF 0x1910 40#define PCIE_MASK_OFF 0x1910
41#define PCIE_CTRL_OFF 0x1a00 41#define PCIE_CTRL_OFF 0x1a00
42#define PCIE_CTRL_X1_MODE 0x0001
42#define PCIE_STAT_OFF 0x1a04 43#define PCIE_STAT_OFF 0x1a04
43#define PCIE_STAT_DEV_OFFS 20 44#define PCIE_STAT_DEV_OFFS 20
44#define PCIE_STAT_DEV_MASK 0x1f 45#define PCIE_STAT_DEV_MASK 0x1f
@@ -62,6 +63,11 @@ int orion_pcie_link_up(void __iomem *base)
62 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN); 63 return !(readl(base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
63} 64}
64 65
66int __init orion_pcie_x4_mode(void __iomem *base)
67{
68 return !(readl(base + PCIE_CTRL_OFF) & PCIE_CTRL_X1_MODE);
69}
70
65int orion_pcie_get_local_bus_nr(void __iomem *base) 71int orion_pcie_get_local_bus_nr(void __iomem *base)
66{ 72{
67 u32 stat = readl(base + PCIE_STAT_OFF); 73 u32 stat = readl(base + PCIE_STAT_OFF);
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 28b5285446e8..93c4ef9f0067 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -74,7 +74,7 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
74 /* 74 /*
75 * Clear and enable clockevent timer interrupt. 75 * Clear and enable clockevent timer interrupt.
76 */ 76 */
77 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); 77 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
78 78
79 u = readl(BRIDGE_MASK); 79 u = readl(BRIDGE_MASK);
80 u |= BRIDGE_INT_TIMER1; 80 u |= BRIDGE_INT_TIMER1;
@@ -138,7 +138,7 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
138 /* 138 /*
139 * ACK pending timer interrupt. 139 * ACK pending timer interrupt.
140 */ 140 */
141 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); 141 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
142 142
143 } 143 }
144 local_irq_restore(flags); 144 local_irq_restore(flags);
@@ -159,7 +159,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
159 /* 159 /*
160 * ACK timer interrupt and call event handler. 160 * ACK timer interrupt and call event handler.
161 */ 161 */
162 writel(~BRIDGE_INT_TIMER1, BRIDGE_CAUSE); 162 writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
163 orion_clkevt.event_handler(&orion_clkevt); 163 orion_clkevt.event_handler(&orion_clkevt);
164 164
165 return IRQ_HANDLED; 165 return IRQ_HANDLED;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index b66fb3c4e228..5e28c217b8c2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -9,6 +9,7 @@ config PLAT_S3C24XX
9 depends on ARCH_S3C2410 9 depends on ARCH_S3C2410
10 default y if ARCH_S3C2410 10 default y if ARCH_S3C2410
11 select NO_IOPORT 11 select NO_IOPORT
12 select HAVE_GPIO_LIB
12 help 13 help
13 Base platform code for any Samsung S3C24XX device 14 Base platform code for any Samsung S3C24XX device
14 15
@@ -20,6 +21,13 @@ config CPU_S3C244X
20 help 21 help
21 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems. 22 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
22 23
24config S3C24XX_PWM
25 bool "PWM device support"
26 select HAVE_PWM
27 help
28 Support for exporting the PWM timer blocks via the pwm device
29 system.
30
23config PM_SIMTEC 31config PM_SIMTEC
24 bool 32 bool
25 help 33 help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 131d20237dd7..d82767b2b833 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -16,8 +16,10 @@ obj-y += cpu.o
16obj-y += irq.o 16obj-y += irq.o
17obj-y += devs.o 17obj-y += devs.o
18obj-y += gpio.o 18obj-y += gpio.o
19obj-y += gpiolib.o
19obj-y += time.o 20obj-y += time.o
20obj-y += clock.o 21obj-y += clock.o
22obj-y += pwm-clock.o
21 23
22# Architecture dependant builds 24# Architecture dependant builds
23 25
@@ -27,5 +29,6 @@ obj-$(CONFIG_CPU_S3C244X) += s3c244x-clock.o
27obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 29obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
28obj-$(CONFIG_PM) += pm.o 30obj-$(CONFIG_PM) += pm.o
29obj-$(CONFIG_PM) += sleep.o 31obj-$(CONFIG_PM) += sleep.o
32obj-$(CONFIG_HAVE_PWM) += pwm.o
30obj-$(CONFIG_S3C2410_DMA) += dma.o 33obj-$(CONFIG_S3C2410_DMA) += dma.o
31obj-$(CONFIG_MACH_SMDK) += common-smdk.o 34obj-$(CONFIG_MACH_SMDK) += common-smdk.o
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index e546e933b3f7..eea3b32ff798 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -495,106 +495,6 @@ struct platform_device s3c_device_spi1 = {
495 495
496EXPORT_SYMBOL(s3c_device_spi1); 496EXPORT_SYMBOL(s3c_device_spi1);
497 497
498/* pwm timer blocks */
499
500static struct resource s3c_timer0_resource[] = {
501 [0] = {
502 .start = S3C24XX_PA_TIMER + 0x0C,
503 .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
504 .flags = IORESOURCE_MEM,
505 },
506 [1] = {
507 .start = IRQ_TIMER0,
508 .end = IRQ_TIMER0,
509 .flags = IORESOURCE_IRQ,
510 }
511
512};
513
514struct platform_device s3c_device_timer0 = {
515 .name = "s3c2410-timer",
516 .id = 0,
517 .num_resources = ARRAY_SIZE(s3c_timer0_resource),
518 .resource = s3c_timer0_resource,
519};
520
521EXPORT_SYMBOL(s3c_device_timer0);
522
523/* timer 1 */
524
525static struct resource s3c_timer1_resource[] = {
526 [0] = {
527 .start = S3C24XX_PA_TIMER + 0x18,
528 .end = S3C24XX_PA_TIMER + 0x23,
529 .flags = IORESOURCE_MEM,
530 },
531 [1] = {
532 .start = IRQ_TIMER1,
533 .end = IRQ_TIMER1,
534 .flags = IORESOURCE_IRQ,
535 }
536
537};
538
539struct platform_device s3c_device_timer1 = {
540 .name = "s3c2410-timer",
541 .id = 1,
542 .num_resources = ARRAY_SIZE(s3c_timer1_resource),
543 .resource = s3c_timer1_resource,
544};
545
546EXPORT_SYMBOL(s3c_device_timer1);
547
548/* timer 2 */
549
550static struct resource s3c_timer2_resource[] = {
551 [0] = {
552 .start = S3C24XX_PA_TIMER + 0x24,
553 .end = S3C24XX_PA_TIMER + 0x2F,
554 .flags = IORESOURCE_MEM,
555 },
556 [1] = {
557 .start = IRQ_TIMER2,
558 .end = IRQ_TIMER2,
559 .flags = IORESOURCE_IRQ,
560 }
561
562};
563
564struct platform_device s3c_device_timer2 = {
565 .name = "s3c2410-timer",
566 .id = 2,
567 .num_resources = ARRAY_SIZE(s3c_timer2_resource),
568 .resource = s3c_timer2_resource,
569};
570
571EXPORT_SYMBOL(s3c_device_timer2);
572
573/* timer 3 */
574
575static struct resource s3c_timer3_resource[] = {
576 [0] = {
577 .start = S3C24XX_PA_TIMER + 0x30,
578 .end = S3C24XX_PA_TIMER + 0x3B,
579 .flags = IORESOURCE_MEM,
580 },
581 [1] = {
582 .start = IRQ_TIMER3,
583 .end = IRQ_TIMER3,
584 .flags = IORESOURCE_IRQ,
585 }
586
587};
588
589struct platform_device s3c_device_timer3 = {
590 .name = "s3c2410-timer",
591 .id = 3,
592 .num_resources = ARRAY_SIZE(s3c_timer3_resource),
593 .resource = s3c_timer3_resource,
594};
595
596EXPORT_SYMBOL(s3c_device_timer3);
597
598#ifdef CONFIG_CPU_S3C2440 498#ifdef CONFIG_CPU_S3C2440
599 499
600/* Camif Controller */ 500/* Camif Controller */
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c
new file mode 100644
index 000000000000..825d8d0c5ca2
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/gpiolib.c
@@ -0,0 +1,259 @@
1/* linux/arch/arm/plat-s3c24xx/gpiolib.c
2 *
3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C24XX GPIOlib support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/interrupt.h>
18#include <linux/ioport.h>
19#include <linux/io.h>
20#include <linux/gpio.h>
21
22#include <asm/hardware.h>
23#include <asm/irq.h>
24
25#include <asm/arch/regs-gpio.h>
26
27struct s3c24xx_gpio_chip {
28 struct gpio_chip chip;
29 void __iomem *base;
30};
31
32static inline struct s3c24xx_gpio_chip *to_s3c_chip(struct gpio_chip *gpc)
33{
34 return container_of(gpc, struct s3c24xx_gpio_chip, chip);
35}
36
37/* these routines are exported for use by other parts of the platform
38 * and system support, but are not intended to be used directly by the
39 * drivers themsevles.
40 */
41
42int s3c24xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
43{
44 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
45 void __iomem *base = ourchip->base;
46 unsigned long flags;
47 unsigned long con;
48
49 local_irq_save(flags);
50
51 con = __raw_readl(base + 0x00);
52 con &= ~(3 << (offset * 2));
53 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
54
55 __raw_writel(con, base + 0x00);
56
57 local_irq_restore(flags);
58 return 0;
59}
60
61int s3c24xx_gpiolib_output(struct gpio_chip *chip,
62 unsigned offset, int value)
63{
64 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
65 void __iomem *base = ourchip->base;
66 unsigned long flags;
67 unsigned long dat;
68 unsigned long con;
69
70 local_irq_save(flags);
71
72 dat = __raw_readl(base + 0x04);
73 dat &= ~(1 << offset);
74 if (value)
75 dat |= 1 << offset;
76 __raw_writel(dat, base + 0x04);
77
78 con = __raw_readl(base + 0x00);
79 con &= ~(3 << (offset * 2));
80 con |= (S3C2410_GPIO_OUTPUT & 0xf) << (offset * 2);
81
82 __raw_writel(con, base + 0x00);
83 __raw_writel(dat, base + 0x04);
84
85 local_irq_restore(flags);
86 return 0;
87}
88
89void s3c24xx_gpiolib_set(struct gpio_chip *chip, unsigned offset, int value)
90{
91 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
92 void __iomem *base = ourchip->base;
93 unsigned long flags;
94 unsigned long dat;
95
96 local_irq_save(flags);
97
98 dat = __raw_readl(base + 0x04);
99 dat &= ~(1 << offset);
100 if (value)
101 dat |= 1 << offset;
102 __raw_writel(dat, base + 0x04);
103
104 local_irq_restore(flags);
105}
106
107int s3c24xx_gpiolib_get(struct gpio_chip *chip, unsigned offset)
108{
109 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
110 unsigned long val;
111
112 val = __raw_readl(ourchip->base + 0x04);
113 val >>= offset;
114 val &= 1;
115
116 return val;
117}
118
119static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset)
120{
121 return -EINVAL;
122}
123
124static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
125 unsigned offset, int value)
126{
127 struct s3c24xx_gpio_chip *ourchip = to_s3c_chip(chip);
128 void __iomem *base = ourchip->base;
129 unsigned long flags;
130 unsigned long dat;
131 unsigned long con;
132
133 local_irq_save(flags);
134
135 con = __raw_readl(base + 0x00);
136 dat = __raw_readl(base + 0x04);
137
138 dat &= ~(1 << offset);
139 if (value)
140 dat |= 1 << offset;
141
142 __raw_writel(dat, base + 0x04);
143
144 con &= ~(1 << offset);
145
146 __raw_writel(con, base + 0x00);
147 __raw_writel(dat, base + 0x04);
148
149 local_irq_restore(flags);
150 return 0;
151}
152
153
154struct s3c24xx_gpio_chip gpios[] = {
155 [0] = {
156 .base = S3C24XX_GPIO_BASE(S3C2410_GPA0),
157 .chip = {
158 .base = S3C2410_GPA0,
159 .owner = THIS_MODULE,
160 .label = "GPIOA",
161 .ngpio = 24,
162 .direction_input = s3c24xx_gpiolib_banka_input,
163 .direction_output = s3c24xx_gpiolib_banka_output,
164 .set = s3c24xx_gpiolib_set,
165 .get = s3c24xx_gpiolib_get,
166 },
167 },
168 [1] = {
169 .base = S3C24XX_GPIO_BASE(S3C2410_GPB0),
170 .chip = {
171 .base = S3C2410_GPB0,
172 .owner = THIS_MODULE,
173 .label = "GPIOB",
174 .ngpio = 16,
175 .direction_input = s3c24xx_gpiolib_input,
176 .direction_output = s3c24xx_gpiolib_output,
177 .set = s3c24xx_gpiolib_set,
178 .get = s3c24xx_gpiolib_get,
179 },
180 },
181 [2] = {
182 .base = S3C24XX_GPIO_BASE(S3C2410_GPC0),
183 .chip = {
184 .base = S3C2410_GPC0,
185 .owner = THIS_MODULE,
186 .label = "GPIOC",
187 .ngpio = 16,
188 .direction_input = s3c24xx_gpiolib_input,
189 .direction_output = s3c24xx_gpiolib_output,
190 .set = s3c24xx_gpiolib_set,
191 .get = s3c24xx_gpiolib_get,
192 },
193 },
194 [3] = {
195 .base = S3C24XX_GPIO_BASE(S3C2410_GPD0),
196 .chip = {
197 .base = S3C2410_GPD0,
198 .owner = THIS_MODULE,
199 .label = "GPIOD",
200 .ngpio = 16,
201 .direction_input = s3c24xx_gpiolib_input,
202 .direction_output = s3c24xx_gpiolib_output,
203 .set = s3c24xx_gpiolib_set,
204 .get = s3c24xx_gpiolib_get,
205 },
206 },
207 [4] = {
208 .base = S3C24XX_GPIO_BASE(S3C2410_GPE0),
209 .chip = {
210 .base = S3C2410_GPE0,
211 .label = "GPIOE",
212 .owner = THIS_MODULE,
213 .ngpio = 16,
214 .direction_input = s3c24xx_gpiolib_input,
215 .direction_output = s3c24xx_gpiolib_output,
216 .set = s3c24xx_gpiolib_set,
217 .get = s3c24xx_gpiolib_get,
218 },
219 },
220 [5] = {
221 .base = S3C24XX_GPIO_BASE(S3C2410_GPF0),
222 .chip = {
223 .base = S3C2410_GPF0,
224 .owner = THIS_MODULE,
225 .label = "GPIOF",
226 .ngpio = 8,
227 .direction_input = s3c24xx_gpiolib_input,
228 .direction_output = s3c24xx_gpiolib_output,
229 .set = s3c24xx_gpiolib_set,
230 .get = s3c24xx_gpiolib_get,
231 },
232 },
233 [6] = {
234 .base = S3C24XX_GPIO_BASE(S3C2410_GPG0),
235 .chip = {
236 .base = S3C2410_GPG0,
237 .owner = THIS_MODULE,
238 .label = "GPIOG",
239 .ngpio = 10,
240 .direction_input = s3c24xx_gpiolib_input,
241 .direction_output = s3c24xx_gpiolib_output,
242 .set = s3c24xx_gpiolib_set,
243 .get = s3c24xx_gpiolib_get,
244 },
245 },
246};
247
248static __init int s3c24xx_gpiolib_init(void)
249{
250 struct s3c24xx_gpio_chip *chip = gpios;
251 int gpn;
252
253 for (gpn = 0; gpn < ARRAY_SIZE(gpios); gpn++, chip++)
254 gpiochip_add(&chip->chip);
255
256 return 0;
257}
258
259arch_initcall(s3c24xx_gpiolib_init);
diff --git a/arch/arm/plat-s3c24xx/pwm-clock.c b/arch/arm/plat-s3c24xx/pwm-clock.c
new file mode 100644
index 000000000000..2cda3e3c6786
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm-clock.c
@@ -0,0 +1,437 @@
1/* linux/arch/arm/plat-s3c24xx/pwm-clock.c
2 *
3 * Copyright (c) 2007 Simtec Electronics
4 * Copyright (c) 2007, 2008 Ben Dooks
5 * Ben Dooks <ben-linux@fluff.org>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10*/
11
12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/io.h>
20
21#include <asm/hardware.h>
22#include <asm/irq.h>
23
24#include <asm/arch/regs-clock.h>
25#include <asm/arch/regs-gpio.h>
26
27#include <asm/plat-s3c24xx/clock.h>
28#include <asm/plat-s3c24xx/cpu.h>
29
30#include <asm/plat-s3c/regs-timer.h>
31
32/* Each of the timers 0 through 5 go through the following
33 * clock tree, with the inputs depending on the timers.
34 *
35 * pclk ---- [ prescaler 0 ] -+---> timer 0
36 * +---> timer 1
37 *
38 * pclk ---- [ prescaler 1 ] -+---> timer 2
39 * +---> timer 3
40 * \---> timer 4
41 *
42 * Which are fed into the timers as so:
43 *
44 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
45 * [mux] -> timer 0
46 * tclk 0 ------------------------------/
47 *
48 * prescaled 0 ---- [ div 2,4,8,16 ] ---\
49 * [mux] -> timer 1
50 * tclk 0 ------------------------------/
51 *
52 *
53 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
54 * [mux] -> timer 2
55 * tclk 1 ------------------------------/
56 *
57 * prescaled 1 ---- [ div 2,4,8,16 ] ---\
58 * [mux] -> timer 3
59 * tclk 1 ------------------------------/
60 *
61 * prescaled 1 ---- [ div 2,4,8, 16 ] --\
62 * [mux] -> timer 4
63 * tclk 1 ------------------------------/
64 *
65 * Since the mux and the divider are tied together in the
66 * same register space, it is impossible to set the parent
67 * and the rate at the same time. To avoid this, we add an
68 * intermediate 'prescaled-and-divided' clock to select
69 * as the parent for the timer input clock called tdiv.
70 *
71 * prescaled clk --> pwm-tdiv ---\
72 * [ mux ] --> timer X
73 * tclk -------------------------/
74*/
75
76static unsigned long clk_pwm_scaler_getrate(struct clk *clk)
77{
78 unsigned long tcfg0 = __raw_readl(S3C2410_TCFG0);
79
80 if (clk->id == 1) {
81 tcfg0 &= S3C2410_TCFG_PRESCALER1_MASK;
82 tcfg0 >>= S3C2410_TCFG_PRESCALER1_SHIFT;
83 } else {
84 tcfg0 &= S3C2410_TCFG_PRESCALER0_MASK;
85 }
86
87 return clk_get_rate(clk->parent) / (tcfg0 + 1);
88}
89
90/* TODO - add set rate calls. */
91
92struct clk clk_timer_scaler[] = {
93 [0] = {
94 .name = "pwm-scaler0",
95 .id = -1,
96 .get_rate = clk_pwm_scaler_getrate,
97 },
98 [1] = {
99 .name = "pwm-scaler1",
100 .id = -1,
101 .get_rate = clk_pwm_scaler_getrate,
102 },
103};
104
105struct clk clk_timer_tclk[] = {
106 [0] = {
107 .name = "pwm-tclk0",
108 .id = -1,
109 },
110 [1] = {
111 .name = "pwm-tclk1",
112 .id = -1,
113 },
114};
115
116struct pwm_tdiv_clk {
117 struct clk clk;
118 unsigned int divisor;
119};
120
121static inline struct pwm_tdiv_clk *to_tdiv(struct clk *clk)
122{
123 return container_of(clk, struct pwm_tdiv_clk, clk);
124}
125
126static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
127{
128 return 1 << (1 + tcfg1);
129}
130
131static unsigned long clk_pwm_tdiv_get_rate(struct clk *clk)
132{
133 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
134 unsigned int divisor;
135
136 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
137 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
138
139 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
140 divisor = to_tdiv(clk)->divisor;
141 else
142 divisor = tcfg_to_divisor(tcfg1);
143
144 return clk_get_rate(clk->parent) / divisor;
145}
146
147static unsigned long clk_pwm_tdiv_round_rate(struct clk *clk,
148 unsigned long rate)
149{
150 unsigned long parent_rate;
151 unsigned long divisor;
152
153 parent_rate = clk_get_rate(clk->parent);
154 divisor = parent_rate / rate;
155
156 if (divisor <= 2)
157 divisor = 2;
158 else if (divisor <= 4)
159 divisor = 4;
160 else if (divisor <= 8)
161 divisor = 8;
162 else
163 divisor = 16;
164
165 return parent_rate / divisor;
166}
167
168static unsigned long clk_pwm_tdiv_bits(struct pwm_tdiv_clk *divclk)
169{
170 unsigned long bits;
171
172 switch (divclk->divisor) {
173 case 2:
174 bits = S3C2410_TCFG1_MUX_DIV2;
175 break;
176 case 4:
177 bits = S3C2410_TCFG1_MUX_DIV4;
178 break;
179 case 8:
180 bits = S3C2410_TCFG1_MUX_DIV8;
181 break;
182 case 16:
183 default:
184 bits = S3C2410_TCFG1_MUX_DIV16;
185 break;
186 }
187
188 return bits;
189}
190
191static void clk_pwm_tdiv_update(struct pwm_tdiv_clk *divclk)
192{
193 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
194 unsigned long bits = clk_pwm_tdiv_bits(divclk);
195 unsigned long flags;
196 unsigned long shift = S3C2410_TCFG1_SHIFT(divclk->clk.id);
197
198 local_irq_save(flags);
199
200 tcfg1 = __raw_readl(S3C2410_TCFG1);
201 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
202 tcfg1 |= bits << shift;
203 __raw_writel(tcfg1, S3C2410_TCFG1);
204
205 local_irq_restore(flags);
206}
207
208static int clk_pwm_tdiv_set_rate(struct clk *clk, unsigned long rate)
209{
210 struct pwm_tdiv_clk *divclk = to_tdiv(clk);
211 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
212 unsigned long parent_rate = clk_get_rate(clk->parent);
213 unsigned long divisor;
214
215 tcfg1 >>= S3C2410_TCFG1_SHIFT(clk->id);
216 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
217
218 rate = clk_round_rate(clk, rate);
219 divisor = parent_rate / rate;
220
221 if (divisor > 16)
222 return -EINVAL;
223
224 divclk->divisor = divisor;
225
226 /* Update the current MUX settings if we are currently
227 * selected as the clock source for this clock. */
228
229 if (tcfg1 != S3C2410_TCFG1_MUX_TCLK)
230 clk_pwm_tdiv_update(divclk);
231
232 return 0;
233}
234
235struct pwm_tdiv_clk clk_timer_tdiv[] = {
236 [0] = {
237 .clk = {
238 .name = "pwm-tdiv",
239 .parent = &clk_timer_scaler[0],
240 .get_rate = clk_pwm_tdiv_get_rate,
241 .set_rate = clk_pwm_tdiv_set_rate,
242 .round_rate = clk_pwm_tdiv_round_rate,
243 },
244 },
245 [1] = {
246 .clk = {
247 .name = "pwm-tdiv",
248 .parent = &clk_timer_scaler[0],
249 .get_rate = clk_pwm_tdiv_get_rate,
250 .set_rate = clk_pwm_tdiv_set_rate,
251 .round_rate = clk_pwm_tdiv_round_rate,
252 }
253 },
254 [2] = {
255 .clk = {
256 .name = "pwm-tdiv",
257 .parent = &clk_timer_scaler[1],
258 .get_rate = clk_pwm_tdiv_get_rate,
259 .set_rate = clk_pwm_tdiv_set_rate,
260 .round_rate = clk_pwm_tdiv_round_rate,
261 },
262 },
263 [3] = {
264 .clk = {
265 .name = "pwm-tdiv",
266 .parent = &clk_timer_scaler[1],
267 .get_rate = clk_pwm_tdiv_get_rate,
268 .set_rate = clk_pwm_tdiv_set_rate,
269 .round_rate = clk_pwm_tdiv_round_rate,
270 },
271 },
272 [4] = {
273 .clk = {
274 .name = "pwm-tdiv",
275 .parent = &clk_timer_scaler[1],
276 .get_rate = clk_pwm_tdiv_get_rate,
277 .set_rate = clk_pwm_tdiv_set_rate,
278 .round_rate = clk_pwm_tdiv_round_rate,
279 },
280 },
281};
282
283static int __init clk_pwm_tdiv_register(unsigned int id)
284{
285 struct pwm_tdiv_clk *divclk = &clk_timer_tdiv[id];
286 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
287
288 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
289 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
290
291 divclk->clk.id = id;
292 divclk->divisor = tcfg_to_divisor(tcfg1);
293
294 return s3c24xx_register_clock(&divclk->clk);
295}
296
297static inline struct clk *s3c24xx_pwmclk_tclk(unsigned int id)
298{
299 return (id >= 2) ? &clk_timer_tclk[1] : &clk_timer_tclk[0];
300}
301
302static inline struct clk *s3c24xx_pwmclk_tdiv(unsigned int id)
303{
304 return &clk_timer_tdiv[id].clk;
305}
306
307static int clk_pwm_tin_set_parent(struct clk *clk, struct clk *parent)
308{
309 unsigned int id = clk->id;
310 unsigned long tcfg1;
311 unsigned long flags;
312 unsigned long bits;
313 unsigned long shift = S3C2410_TCFG1_SHIFT(id);
314
315 if (parent == s3c24xx_pwmclk_tclk(id))
316 bits = S3C2410_TCFG1_MUX_TCLK << shift;
317 else if (parent == s3c24xx_pwmclk_tdiv(id))
318 bits = clk_pwm_tdiv_bits(to_tdiv(clk)) << shift;
319 else
320 return -EINVAL;
321
322 clk->parent = parent;
323
324 local_irq_save(flags);
325
326 tcfg1 = __raw_readl(S3C2410_TCFG1);
327 tcfg1 &= ~(S3C2410_TCFG1_MUX_MASK << shift);
328 __raw_writel(tcfg1 | bits, S3C2410_TCFG1);
329
330 local_irq_restore(flags);
331
332 return 0;
333}
334
335static struct clk clk_tin[] = {
336 [0] = {
337 .name = "pwm-tin",
338 .id = 0,
339 .set_parent = clk_pwm_tin_set_parent,
340 },
341 [1] = {
342 .name = "pwm-tin",
343 .id = 1,
344 .set_parent = clk_pwm_tin_set_parent,
345 },
346 [2] = {
347 .name = "pwm-tin",
348 .id = 2,
349 .set_parent = clk_pwm_tin_set_parent,
350 },
351 [3] = {
352 .name = "pwm-tin",
353 .id = 3,
354 .set_parent = clk_pwm_tin_set_parent,
355 },
356 [4] = {
357 .name = "pwm-tin",
358 .id = 4,
359 .set_parent = clk_pwm_tin_set_parent,
360 },
361};
362
363static __init int clk_pwm_tin_register(struct clk *pwm)
364{
365 unsigned long tcfg1 = __raw_readl(S3C2410_TCFG1);
366 unsigned int id = pwm->id;
367
368 struct clk *parent;
369 int ret;
370
371 ret = s3c24xx_register_clock(pwm);
372 if (ret < 0)
373 return ret;
374
375 tcfg1 >>= S3C2410_TCFG1_SHIFT(id);
376 tcfg1 &= S3C2410_TCFG1_MUX_MASK;
377
378 if (tcfg1 == S3C2410_TCFG1_MUX_TCLK)
379 parent = s3c24xx_pwmclk_tclk(id);
380 else
381 parent = s3c24xx_pwmclk_tdiv(id);
382
383 return clk_set_parent(pwm, parent);
384}
385
386static __init int s3c24xx_pwmclk_init(void)
387{
388 struct clk *clk_timers;
389 unsigned int clk;
390 int ret;
391
392 clk_timers = clk_get(NULL, "timers");
393 if (IS_ERR(clk_timers)) {
394 printk(KERN_ERR "%s: no parent clock\n", __func__);
395 return -EINVAL;
396 }
397
398 for (clk = 0; clk < ARRAY_SIZE(clk_timer_scaler); clk++) {
399 clk_timer_scaler[clk].parent = clk_timers;
400 ret = s3c24xx_register_clock(&clk_timer_scaler[clk]);
401 if (ret < 0) {
402 printk(KERN_ERR "error adding pwm scaler%d clock\n", clk);
403 goto err;
404 }
405 }
406
407 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tclk); clk++) {
408 ret = s3c24xx_register_clock(&clk_timer_tclk[clk]);
409 if (ret < 0) {
410 printk(KERN_ERR "error adding pww tclk%d\n", clk);
411 goto err;
412 }
413 }
414
415 for (clk = 0; clk < ARRAY_SIZE(clk_timer_tdiv); clk++) {
416 ret = clk_pwm_tdiv_register(clk);
417 if (ret < 0) {
418 printk(KERN_ERR "error adding pwm%d tdiv clock\n", clk);
419 goto err;
420 }
421 }
422
423 for (clk = 0; clk < ARRAY_SIZE(clk_tin); clk++) {
424 ret = clk_pwm_tin_register(&clk_tin[clk]);
425 if (ret < 0) {
426 printk(KERN_ERR "error adding pwm%d tin clock\n", clk);
427 goto err;
428 }
429 }
430
431 return 0;
432
433 err:
434 return ret;
435}
436
437arch_initcall(s3c24xx_pwmclk_init);
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c24xx/pwm.c
new file mode 100644
index 000000000000..18c4bdc49a05
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/pwm.c
@@ -0,0 +1,402 @@
1/* arch/arm/plat-s3c24xx/pwm.c
2 *
3 * Copyright (c) 2007 Ben Dooks
4 * Copyright (c) 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
6 *
7 * S3C24XX PWM device core
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License.
12*/
13
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/platform_device.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/pwm.h>
21
22#include <asm/plat-s3c/regs-timer.h>
23
24struct pwm_device {
25 struct list_head list;
26 struct platform_device *pdev;
27
28 struct clk *clk_div;
29 struct clk *clk;
30 const char *label;
31
32 unsigned int period_ns;
33 unsigned int duty_ns;
34
35 unsigned char tcon_base;
36 unsigned char running;
37 unsigned char use_count;
38 unsigned char pwm_id;
39};
40
41#define pwm_dbg(_pwm, msg...) dev_info(&(_pwm)->pdev->dev, msg)
42
43static struct clk *clk_scaler[2];
44
45/* Standard setup for a timer block. */
46
47#define TIMER_RESOURCE_SIZE (1)
48
49#define TIMER_RESOURCE(_tmr, _irq) \
50 (struct resource [TIMER_RESOURCE_SIZE]) { \
51 [0] = { \
52 .start = _irq, \
53 .end = _irq, \
54 .flags = IORESOURCE_IRQ \
55 } \
56 }
57
58#define DEFINE_TIMER(_tmr_no, _irq) \
59 .name = "s3c24xx-pwm", \
60 .id = _tmr_no, \
61 .num_resources = TIMER_RESOURCE_SIZE, \
62 .resource = TIMER_RESOURCE(_tmr_no, _irq), \
63
64/* since we already have an static mapping for the timer, we do not
65 * bother setting any IO resource for the base.
66 */
67
68struct platform_device s3c_device_timer[] = {
69 [0] = { DEFINE_TIMER(0, IRQ_TIMER0) },
70 [1] = { DEFINE_TIMER(1, IRQ_TIMER1) },
71 [2] = { DEFINE_TIMER(2, IRQ_TIMER2) },
72 [3] = { DEFINE_TIMER(3, IRQ_TIMER3) },
73 [4] = { DEFINE_TIMER(4, IRQ_TIMER4) },
74};
75
76static inline int pwm_is_tdiv(struct pwm_device *pwm)
77{
78 return clk_get_parent(pwm->clk) == pwm->clk_div;
79}
80
81static DEFINE_MUTEX(pwm_lock);
82static LIST_HEAD(pwm_list);
83
84struct pwm_device *pwm_request(int pwm_id, const char *label)
85{
86 struct pwm_device *pwm;
87 int found = 0;
88
89 mutex_lock(&pwm_lock);
90
91 list_for_each_entry(pwm, &pwm_list, list) {
92 if (pwm->pwm_id == pwm_id) {
93 found = 1;
94 break;
95 }
96 }
97
98 if (found) {
99 if (pwm->use_count == 0) {
100 pwm->use_count = 1;
101 pwm->label = label;
102 } else
103 pwm = ERR_PTR(-EBUSY);
104 } else
105 pwm = ERR_PTR(-ENOENT);
106
107 mutex_unlock(&pwm_lock);
108 return pwm;
109}
110
111EXPORT_SYMBOL(pwm_request);
112
113
114void pwm_free(struct pwm_device *pwm)
115{
116 mutex_lock(&pwm_lock);
117
118 if (pwm->use_count) {
119 pwm->use_count--;
120 pwm->label = NULL;
121 } else
122 printk(KERN_ERR "PWM%d device already freed\n", pwm->pwm_id);
123
124 mutex_unlock(&pwm_lock);
125}
126
127EXPORT_SYMBOL(pwm_free);
128
129#define pwm_tcon_start(pwm) (1 << (pwm->tcon_base + 0))
130#define pwm_tcon_invert(pwm) (1 << (pwm->tcon_base + 2))
131#define pwm_tcon_autoreload(pwm) (1 << (pwm->tcon_base + 3))
132#define pwm_tcon_manulupdate(pwm) (1 << (pwm->tcon_base + 1))
133
134int pwm_enable(struct pwm_device *pwm)
135{
136 unsigned long flags;
137 unsigned long tcon;
138
139 local_irq_save(flags);
140
141 tcon = __raw_readl(S3C2410_TCON);
142 tcon |= pwm_tcon_start(pwm);
143 __raw_writel(tcon, S3C2410_TCON);
144
145 local_irq_restore(flags);
146
147 pwm->running = 1;
148 return 0;
149}
150
151EXPORT_SYMBOL(pwm_enable);
152
153void pwm_disable(struct pwm_device *pwm)
154{
155 unsigned long flags;
156 unsigned long tcon;
157
158 local_irq_save(flags);
159
160 tcon = __raw_readl(S3C2410_TCON);
161 tcon &= ~pwm_tcon_start(pwm);
162 __raw_writel(tcon, S3C2410_TCON);
163
164 local_irq_restore(flags);
165
166 pwm->running = 0;
167}
168
169EXPORT_SYMBOL(pwm_disable);
170
171unsigned long pwm_calc_tin(struct pwm_device *pwm, unsigned long freq)
172{
173 unsigned long tin_parent_rate;
174 unsigned int div;
175
176 tin_parent_rate = clk_get_rate(clk_get_parent(pwm->clk_div));
177 pwm_dbg(pwm, "tin parent at %lu\n", tin_parent_rate);
178
179 for (div = 2; div <= 16; div *= 2) {
180 if ((tin_parent_rate / (div << 16)) < freq)
181 return tin_parent_rate / div;
182 }
183
184 return tin_parent_rate / 16;
185}
186
187#define NS_IN_HZ (1000000000UL)
188
189int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
190{
191 unsigned long tin_rate;
192 unsigned long tin_ns;
193 unsigned long period;
194 unsigned long flags;
195 unsigned long tcon;
196 unsigned long tcnt;
197 long tcmp;
198
199 /* We currently avoid using 64bit arithmetic by using the
200 * fact that anything faster than 1Hz is easily representable
201 * by 32bits. */
202
203 if (period_ns > NS_IN_HZ || duty_ns > NS_IN_HZ)
204 return -ERANGE;
205
206 if (duty_ns > period_ns)
207 return -EINVAL;
208
209 if (period_ns == pwm->period_ns &&
210 duty_ns == pwm->duty_ns)
211 return 0;
212
213 /* The TCMP and TCNT can be read without a lock, they're not
214 * shared between the timers. */
215
216 tcmp = __raw_readl(S3C2410_TCMPB(pwm->pwm_id));
217 tcnt = __raw_readl(S3C2410_TCNTB(pwm->pwm_id));
218
219 period = NS_IN_HZ / period_ns;
220
221 pwm_dbg(pwm, "duty_ns=%d, period_ns=%d (%lu)\n",
222 duty_ns, period_ns, period);
223
224 /* Check to see if we are changing the clock rate of the PWM */
225
226 if (pwm->period_ns != period_ns) {
227 if (pwm_is_tdiv(pwm)) {
228 tin_rate = pwm_calc_tin(pwm, period);
229 clk_set_rate(pwm->clk_div, tin_rate);
230 } else
231 tin_rate = clk_get_rate(pwm->clk);
232
233 pwm->period_ns = period_ns;
234
235 pwm_dbg(pwm, "tin_rate=%lu\n", tin_rate);
236
237 tin_ns = NS_IN_HZ / tin_rate;
238 tcnt = period_ns / tin_ns;
239 } else
240 tin_ns = NS_IN_HZ / clk_get_rate(pwm->clk);
241
242 /* Note, counters count down */
243
244 tcmp = duty_ns / tin_ns;
245 tcmp = tcnt - tcmp;
246
247 pwm_dbg(pwm, "tin_ns=%lu, tcmp=%ld/%lu\n", tin_ns, tcmp, tcnt);
248
249 if (tcmp < 0)
250 tcmp = 0;
251
252 /* Update the PWM register block. */
253
254 local_irq_save(flags);
255
256 __raw_writel(tcmp, S3C2410_TCMPB(pwm->pwm_id));
257 __raw_writel(tcnt, S3C2410_TCNTB(pwm->pwm_id));
258
259 tcon = __raw_readl(S3C2410_TCON);
260 tcon |= pwm_tcon_manulupdate(pwm);
261 tcon |= pwm_tcon_autoreload(pwm);
262 __raw_writel(tcon, S3C2410_TCON);
263
264 tcon &= ~pwm_tcon_manulupdate(pwm);
265 __raw_writel(tcon, S3C2410_TCON);
266
267 local_irq_restore(flags);
268
269 return 0;
270}
271
272EXPORT_SYMBOL(pwm_config);
273
274static int pwm_register(struct pwm_device *pwm)
275{
276 pwm->duty_ns = -1;
277 pwm->period_ns = -1;
278
279 mutex_lock(&pwm_lock);
280 list_add_tail(&pwm->list, &pwm_list);
281 mutex_unlock(&pwm_lock);
282
283 return 0;
284}
285
286static int s3c_pwm_probe(struct platform_device *pdev)
287{
288 struct device *dev = &pdev->dev;
289 struct pwm_device *pwm;
290 unsigned long flags;
291 unsigned long tcon;
292 unsigned int id = pdev->id;
293 int ret;
294
295 if (id == 4) {
296 dev_err(dev, "TIMER4 is currently not supported\n");
297 return -ENXIO;
298 }
299
300 pwm = kzalloc(sizeof(struct pwm_device), GFP_KERNEL);
301 if (pwm == NULL) {
302 dev_err(dev, "failed to allocate pwm_device\n");
303 return -ENOMEM;
304 }
305
306 pwm->pdev = pdev;
307 pwm->pwm_id = id;
308
309 /* calculate base of control bits in TCON */
310 pwm->tcon_base = id == 0 ? 0 : (id * 4) + 4;
311
312 pwm->clk = clk_get(dev, "pwm-tin");
313 if (IS_ERR(pwm->clk)) {
314 dev_err(dev, "failed to get pwm tin clk\n");
315 ret = PTR_ERR(pwm->clk);
316 goto err_alloc;
317 }
318
319 pwm->clk_div = clk_get(dev, "pwm-tdiv");
320 if (IS_ERR(pwm->clk_div)) {
321 dev_err(dev, "failed to get pwm tdiv clk\n");
322 ret = PTR_ERR(pwm->clk_div);
323 goto err_clk_tin;
324 }
325
326 local_irq_save(flags);
327
328 tcon = __raw_readl(S3C2410_TCON);
329 tcon |= pwm_tcon_invert(pwm);
330 __raw_writel(tcon, S3C2410_TCON);
331
332 local_irq_restore(flags);
333
334
335 ret = pwm_register(pwm);
336 if (ret) {
337 dev_err(dev, "failed to register pwm\n");
338 goto err_clk_tdiv;
339 }
340
341 pwm_dbg(pwm, "config bits %02x\n",
342 (__raw_readl(S3C2410_TCON) >> pwm->tcon_base) & 0x0f);
343
344 dev_info(dev, "tin at %lu, tdiv at %lu, tin=%sclk, base %d\n",
345 clk_get_rate(pwm->clk),
346 clk_get_rate(pwm->clk_div),
347 pwm_is_tdiv(pwm) ? "div" : "ext", pwm->tcon_base);
348
349 platform_set_drvdata(pdev, pwm);
350 return 0;
351
352 err_clk_tdiv:
353 clk_put(pwm->clk_div);
354
355 err_clk_tin:
356 clk_put(pwm->clk);
357
358 err_alloc:
359 kfree(pwm);
360 return ret;
361}
362
363static int s3c_pwm_remove(struct platform_device *pdev)
364{
365 struct pwm_device *pwm = platform_get_drvdata(pdev);
366
367 clk_put(pwm->clk_div);
368 clk_put(pwm->clk);
369 kfree(pwm);
370
371 return 0;
372}
373
374static struct platform_driver s3c_pwm_driver = {
375 .driver = {
376 .name = "s3c24xx-pwm",
377 .owner = THIS_MODULE,
378 },
379 .probe = s3c_pwm_probe,
380 .remove = __devexit_p(s3c_pwm_remove),
381};
382
383static int __init pwm_init(void)
384{
385 int ret;
386
387 clk_scaler[0] = clk_get(NULL, "pwm-scaler0");
388 clk_scaler[1] = clk_get(NULL, "pwm-scaler1");
389
390 if (IS_ERR(clk_scaler[0]) || IS_ERR(clk_scaler[1])) {
391 printk(KERN_ERR "%s: failed to get scaler clocks\n", __func__);
392 return -EINVAL;
393 }
394
395 ret = platform_driver_register(&s3c_pwm_driver);
396 if (ret)
397 printk(KERN_ERR "%s: failed to add pwm driver\n", __func__);
398
399 return ret;
400}
401
402arch_initcall(pwm_init);
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 207a8b5a0c4a..0be5630ff568 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
12# 12#
13# http://www.arm.linux.org.uk/developer/machines/?action=new 13# http://www.arm.linux.org.uk/developer/machines/?action=new
14# 14#
15# Last update: Sat Apr 19 11:23:38 2008 15# Last update: Mon Jul 7 16:25:39 2008
16# 16#
17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number 17# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
18# 18#
@@ -560,7 +560,6 @@ husky MACH_HUSKY HUSKY 543
560boxer MACH_BOXER BOXER 544 560boxer MACH_BOXER BOXER 544
561shepherd MACH_SHEPHERD SHEPHERD 545 561shepherd MACH_SHEPHERD SHEPHERD 545
562aml42800aa MACH_AML42800AA AML42800AA 546 562aml42800aa MACH_AML42800AA AML42800AA 546
563ml674001 MACH_MACH_TYPE_ML674001 MACH_TYPE_ML674001 547
564lpc2294 MACH_LPC2294 LPC2294 548 563lpc2294 MACH_LPC2294 LPC2294 548
565switchgrass MACH_SWITCHGRASS SWITCHGRASS 549 564switchgrass MACH_SWITCHGRASS SWITCHGRASS 549
566ens_cmu MACH_ENS_CMU ENS_CMU 550 565ens_cmu MACH_ENS_CMU ENS_CMU 550
@@ -748,7 +747,6 @@ anubis MACH_ANUBIS ANUBIS 734
748ite8152 MACH_ITE8152 ITE8152 735 747ite8152 MACH_ITE8152 ITE8152 735
749lpc3xxx MACH_LPC3XXX LPC3XXX 736 748lpc3xxx MACH_LPC3XXX LPC3XXX 736
750puppeteer MACH_PUPPETEER PUPPETEER 737 749puppeteer MACH_PUPPETEER PUPPETEER 737
751vt001 MACH_MACH_VADATECH MACH_VADATECH 738
752e570 MACH_E570 E570 739 750e570 MACH_E570 E570 739
753x50 MACH_X50 X50 740 751x50 MACH_X50 X50 740
754recon MACH_RECON RECON 741 752recon MACH_RECON RECON 741
@@ -839,7 +837,7 @@ ccxp270 MACH_CCXP CCXP 825
839omap_gsample MACH_OMAP_GSAMPLE OMAP_GSAMPLE 826 837omap_gsample MACH_OMAP_GSAMPLE OMAP_GSAMPLE 826
840realview_eb MACH_REALVIEW_EB REALVIEW_EB 827 838realview_eb MACH_REALVIEW_EB REALVIEW_EB 827
841samoa MACH_SAMOA SAMOA 828 839samoa MACH_SAMOA SAMOA 828
842t3xscale MACH_T3XSCALE T3XSCALE 829 840palmt3 MACH_PALMT3 PALMT3 829
843i878 MACH_I878 I878 830 841i878 MACH_I878 I878 830
844borzoi MACH_BORZOI BORZOI 831 842borzoi MACH_BORZOI BORZOI 831
845gecko MACH_GECKO GECKO 832 843gecko MACH_GECKO GECKO 832
@@ -895,7 +893,7 @@ mio8390 MACH_MIO8390 MIO8390 881
895omi_board MACH_OMI_BOARD OMI_BOARD 882 893omi_board MACH_OMI_BOARD OMI_BOARD 882
896mx21civ MACH_MX21CIV MX21CIV 883 894mx21civ MACH_MX21CIV MX21CIV 883
897mahi_cdac MACH_MAHI_CDAC MAHI_CDAC 884 895mahi_cdac MACH_MAHI_CDAC MAHI_CDAC 884
898xscale_palmtx MACH_XSCALE_PALMTX XSCALE_PALMTX 885 896palmtx MACH_PALMTX PALMTX 885
899s3c2413 MACH_S3C2413 S3C2413 887 897s3c2413 MACH_S3C2413 S3C2413 887
900samsys_ep0 MACH_SAMSYS_EP0 SAMSYS_EP0 888 898samsys_ep0 MACH_SAMSYS_EP0 SAMSYS_EP0 888
901wg302v1 MACH_WG302V1 WG302V1 889 899wg302v1 MACH_WG302V1 WG302V1 889
@@ -918,7 +916,7 @@ nxdb500 MACH_NXDB500 NXDB500 905
918apf9328 MACH_APF9328 APF9328 906 916apf9328 MACH_APF9328 APF9328 906
919omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907 917omap_wipoq MACH_OMAP_WIPOQ OMAP_WIPOQ 907
920omap_twip MACH_OMAP_TWIP OMAP_TWIP 908 918omap_twip MACH_OMAP_TWIP OMAP_TWIP 908
921xscale_treo650 MACH_XSCALE_PALMTREO650 XSCALE_PALMTREO650 909 919palmtreo650 MACH_PALMTREO650 PALMTREO650 909
922acumen MACH_ACUMEN ACUMEN 910 920acumen MACH_ACUMEN ACUMEN 910
923xp100 MACH_XP100 XP100 911 921xp100 MACH_XP100 XP100 911
924fs2410 MACH_FS2410 FS2410 912 922fs2410 MACH_FS2410 FS2410 912
@@ -926,8 +924,8 @@ pxa270_cerf MACH_PXA270_CERF PXA270_CERF 913
926sq2ftlpalm MACH_SQ2FTLPALM SQ2FTLPALM 914 924sq2ftlpalm MACH_SQ2FTLPALM SQ2FTLPALM 914
927bsemserver MACH_BSEMSERVER BSEMSERVER 915 925bsemserver MACH_BSEMSERVER BSEMSERVER 915
928netclient MACH_NETCLIENT NETCLIENT 916 926netclient MACH_NETCLIENT NETCLIENT 916
929xscale_palmtt5 MACH_XSCALE_PALMTT5 XSCALE_PALMTT5 917 927palmt5 MACH_PALMT5 PALMT5 917
930xscale_palmtc MACH_OMAP_PALMTC OMAP_PALMTC 918 928palmtc MACH_PALMTC PALMTC 918
931omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919 929omap_apollon MACH_OMAP_APOLLON OMAP_APOLLON 919
932mxc30030evb MACH_MXC30030EVB MXC30030EVB 920 930mxc30030evb MACH_MXC30030EVB MXC30030EVB 920
933rea_2d MACH_REA_2D REA_2D 921 931rea_2d MACH_REA_2D REA_2D 921
@@ -1220,7 +1218,6 @@ empca400 MACH_EMPCA400 EMPCA400 1211
1220em7210 MACH_EM7210 EM7210 1212 1218em7210 MACH_EM7210 EM7210 1212
1221htchermes MACH_HTCHERMES HTCHERMES 1213 1219htchermes MACH_HTCHERMES HTCHERMES 1213
1222eti_c1 MACH_ETI_C1 ETI_C1 1214 1220eti_c1 MACH_ETI_C1 ETI_C1 1214
1223mach_dep2410 MACH_MACH_DEP2410 MACH_DEP2410 1215
1224ac100 MACH_AC100 AC100 1216 1221ac100 MACH_AC100 AC100 1216
1225sneetch MACH_SNEETCH SNEETCH 1217 1222sneetch MACH_SNEETCH SNEETCH 1217
1226studentmate MACH_STUDENTMATE STUDENTMATE 1218 1223studentmate MACH_STUDENTMATE STUDENTMATE 1218
@@ -1421,10 +1418,10 @@ looxc550 MACH_LOOXC550 LOOXC550 1417
1421cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418 1418cnty_titan MACH_CNTY_TITAN CNTY_TITAN 1418
1422app3xx MACH_APP3XX APP3XX 1419 1419app3xx MACH_APP3XX APP3XX 1419
1423sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420 1420sideoatsgrama MACH_SIDEOATSGRAMA SIDEOATSGRAMA 1420
1424xscale_palmt700p MACH_XSCALE_PALMT700P XSCALE_PALMT700P 1421 1421palmtreo700p MACH_PALMTREO700P PALMTREO700P 1421
1425xscale_palmt700w MACH_XSCALE_PALMT700W XSCALE_PALMT700W 1422 1422palmtreo700w MACH_PALMTREO700W PALMTREO700W 1422
1426xscale_palmt750 MACH_XSCALE_PALMT750 XSCALE_PALMT750 1423 1423palmtreo750 MACH_PALMTREO750 PALMTREO750 1423
1427xscale_palmt755p MACH_XSCALE_PALMT755P XSCALE_PALMT755P 1424 1424palmtreo755p MACH_PALMTREO755P PALMTREO755P 1424
1428ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425 1425ezreganut9200 MACH_EZREGANUT9200 EZREGANUT9200 1425
1429sarge MACH_SARGE SARGE 1426 1426sarge MACH_SARGE SARGE 1426
1430a696 MACH_A696 A696 1427 1427a696 MACH_A696 A696 1427
@@ -1463,7 +1460,7 @@ artemis MACH_ARTEMIS ARTEMIS 1462
1463htctitan MACH_HTCTITAN HTCTITAN 1463 1460htctitan MACH_HTCTITAN HTCTITAN 1463
1464qranium MACH_QRANIUM QRANIUM 1464 1461qranium MACH_QRANIUM QRANIUM 1464
1465adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465 1462adx_wsc2 MACH_ADX_WSC2 ADX_WSC2 1465
1466adx_medcom MACH_ADX_MEDINET ADX_MEDINET 1466 1463adx_medcom MACH_ADX_MEDCOM ADX_MEDCOM 1466
1467bboard MACH_BBOARD BBOARD 1467 1464bboard MACH_BBOARD BBOARD 1467
1468cambria MACH_CAMBRIA CAMBRIA 1468 1465cambria MACH_CAMBRIA CAMBRIA 1468
1469mt7xxx MACH_MT7XXX MT7XXX 1469 1466mt7xxx MACH_MT7XXX MT7XXX 1469
@@ -1519,7 +1516,7 @@ wp188 MACH_WP188 WP188 1518
1519corsica MACH_CORSICA CORSICA 1519 1516corsica MACH_CORSICA CORSICA 1519
1520bigeye MACH_BIGEYE BIGEYE 1520 1517bigeye MACH_BIGEYE BIGEYE 1520
1521tll5000 MACH_TLL5000 TLL5000 1522 1518tll5000 MACH_TLL5000 TLL5000 1522
1522hni270 MACH_HNI_X270 HNI_X270 1523 1519bebot MACH_BEBOT BEBOT 1523
1523qong MACH_QONG QONG 1524 1520qong MACH_QONG QONG 1524
1524tcompact MACH_TCOMPACT TCOMPACT 1525 1521tcompact MACH_TCOMPACT TCOMPACT 1525
1525puma5 MACH_PUMA5 PUMA5 1526 1522puma5 MACH_PUMA5 PUMA5 1526
@@ -1636,7 +1633,6 @@ awlug4lcu MACH_AWLUG4LCU AWLUG4LCU 1637
1636palermoc MACH_PALERMOC PALERMOC 1638 1633palermoc MACH_PALERMOC PALERMOC 1638
1637omap_ldp MACH_OMAP_LDP OMAP_LDP 1639 1634omap_ldp MACH_OMAP_LDP OMAP_LDP 1639
1638ip500 MACH_IP500 IP500 1640 1635ip500 MACH_IP500 IP500 1640
1639mx35ads MACH_MACH_MX35ADS MACH_MX35ADS 1641
1640ase2 MACH_ASE2 ASE2 1642 1636ase2 MACH_ASE2 ASE2 1642
1641mx35evb MACH_MX35EVB MX35EVB 1643 1637mx35evb MACH_MX35EVB MX35EVB 1643
1642aml_m8050 MACH_AML_M8050 AML_M8050 1644 1638aml_m8050 MACH_AML_M8050 AML_M8050 1644
@@ -1647,7 +1643,7 @@ badger MACH_BADGER BADGER 1648
1647trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649 1643trizeps4wl MACH_TRIZEPS4WL TRIZEPS4WL 1649
1648trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650 1644trizeps5 MACH_TRIZEPS5 TRIZEPS5 1650
1649marlin MACH_MARLIN MARLIN 1651 1645marlin MACH_MARLIN MARLIN 1651
1650ts7800 MACH_TS7800 TS7800 1652 1646ts78xx MACH_TS78XX TS78XX 1652
1651hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653 1647hpipaq214 MACH_HPIPAQ214 HPIPAQ214 1653
1652at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654 1648at572d940dcm MACH_AT572D940DCM AT572D940DCM 1654
1653ne1board MACH_NE1BOARD NE1BOARD 1655 1649ne1board MACH_NE1BOARD NE1BOARD 1655
@@ -1720,3 +1716,99 @@ htc_kaiser MACH_HTC_KAISER HTC_KAISER 1724
1720lg_ks20 MACH_LG_KS20 LG_KS20 1725 1716lg_ks20 MACH_LG_KS20 LG_KS20 1725
1721hhgps MACH_HHGPS HHGPS 1726 1717hhgps MACH_HHGPS HHGPS 1726
1722nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727 1718nokia_n810_wimax MACH_NOKIA_N810_WIMAX NOKIA_N810_WIMAX 1727
1719insight MACH_INSIGHT INSIGHT 1728
1720sapphire MACH_SAPPHIRE SAPPHIRE 1729
1721csb637xo MACH_CSB637XO CSB637XO 1730
1722evisiong MACH_EVISIONG EVISIONG 1731
1723stmp37xx MACH_STMP37XX STMP37XX 1732
1724stmp378x MACH_STMP38XX STMP38XX 1733
1725tnt MACH_TNT TNT 1734
1726tbxt MACH_TBXT TBXT 1735
1727playmate MACH_PLAYMATE PLAYMATE 1736
1728pns10 MACH_PNS10 PNS10 1737
1729eznavi MACH_EZNAVI EZNAVI 1738
1730ps4000 MACH_PS4000 PS4000 1739
1731ezx_a780 MACH_EZX_A780 EZX_A780 1740
1732ezx_e680 MACH_EZX_E680 EZX_E680 1741
1733ezx_a1200 MACH_EZX_A1200 EZX_A1200 1742
1734ezx_e6 MACH_EZX_E6 EZX_E6 1743
1735ezx_e2 MACH_EZX_E2 EZX_E2 1744
1736ezx_a910 MACH_EZX_A910 EZX_A910 1745
1737cwmx31 MACH_CWMX31 CWMX31 1746
1738sl2312 MACH_SL2312 SL2312 1747
1739blenny MACH_BLENNY BLENNY 1748
1740ds107 MACH_DS107 DS107 1749
1741dsx07 MACH_DSX07 DSX07 1750
1742picocom1 MACH_PICOCOM1 PICOCOM1 1751
1743lynx_wolverine MACH_LYNX_WOLVERINE LYNX_WOLVERINE 1752
1744ubisys_p9_sc19 MACH_UBISYS_P9_SC19 UBISYS_P9_SC19 1753
1745kratos_low MACH_KRATOS_LOW KRATOS_LOW 1754
1746m700 MACH_M700 M700 1755
1747edmini_v2 MACH_EDMINI_V2 EDMINI_V2 1756
1748zipit2 MACH_ZIPIT2 ZIPIT2 1757
1749hslfemtocell MACH_HSLFEMTOCELL HSLFEMTOCELL 1758
1750daintree_at91 MACH_DAINTREE_AT91 DAINTREE_AT91 1759
1751sg560usb MACH_SG560USB SG560USB 1760
1752omap3_pandora MACH_OMAP3_PANDORA OMAP3_PANDORA 1761
1753usr8200 MACH_USR8200 USR8200 1762
1754s1s65k MACH_S1S65K S1S65K 1763
1755s2s65a MACH_S2S65A S2S65A 1764
1756icore MACH_ICORE ICORE 1765
1757mss2 MACH_MSS2 MSS2 1766
1758belmont MACH_BELMONT BELMONT 1767
1759asusp525 MACH_ASUSP525 ASUSP525 1768
1760lb88rc8480 MACH_LB88RC8480 LB88RC8480 1769
1761hipxa MACH_HIPXA HIPXA 1770
1762mx25_3ds MACH_MX25_3DS MX25_3DS 1771
1763m800 MACH_M800 M800 1772
1764omap3530_lv_som MACH_OMAP3530_LV_SOM OMAP3530_LV_SOM 1773
1765prima_evb MACH_PRIMA_EVB PRIMA_EVB 1774
1766mx31bt1 MACH_MX31BT1 MX31BT1 1775
1767atlas4_evb MACH_ATLAS4_EVB ATLAS4_EVB 1776
1768mx31cicada MACH_MX31CICADA MX31CICADA 1777
1769mi424wr MACH_MI424WR MI424WR 1778
1770axs_ultrax MACH_AXS_ULTRAX AXS_ULTRAX 1779
1771at572d940deb MACH_AT572D940DEB AT572D940DEB 1780
1772davinci_da8xx_evm MACH_DAVINCI_DA8XX_EVM DAVINCI_DA8XX_EVM 1781
1773ep9302 MACH_EP9302 EP9302 1782
1774at572d940hfeb MACH_AT572D940HFEB AT572D940HFEB 1783
1775cybook3 MACH_CYBOOK3 CYBOOK3 1784
1776wdg002 MACH_WDG002 WDG002 1785
1777sg560adsl MACH_SG560ADSL SG560ADSL 1786
1778nextio_n2800_ica MACH_NEXTIO_N2800_ICA NEXTIO_N2800_ICA 1787
1779marvell_newdb MACH_MARVELL_NEWDB MARVELL_NEWDB 1789
1780vandihud MACH_VANDIHUD VANDIHUD 1790
1781magx_e8 MACH_MAGX_E8 MAGX_E8 1791
1782magx_z6 MACH_MAGX_Z6 MAGX_Z6 1792
1783magx_v8 MACH_MAGX_V8 MAGX_V8 1793
1784magx_u9 MACH_MAGX_U9 MAGX_U9 1794
1785toughcf08 MACH_TOUGHCF08 TOUGHCF08 1795
1786zw4400 MACH_ZW4400 ZW4400 1796
1787marat91 MACH_MARAT91 MARAT91 1797
1788overo MACH_OVERO OVERO 1798
1789at2440evb MACH_AT2440EVB AT2440EVB 1799
1790neocore926 MACH_NEOCORE926 NEOCORE926 1800
1791wnr854t MACH_WNR854T WNR854T 1801
1792imx27 MACH_IMX27 IMX27 1802
1793moose_db MACH_MOOSE_DB MOOSE_DB 1803
1794fab4 MACH_FAB4 FAB4 1804
1795htcdiamond MACH_HTCDIAMOND HTCDIAMOND 1805
1796fiona MACH_FIONA FIONA 1806
1797mxc30030_x MACH_MXC30030_X MXC30030_X 1807
1798bmp1000 MACH_BMP1000 BMP1000 1808
1799logi9200 MACH_LOGI9200 LOGI9200 1809
1800tqma31 MACH_TQMA31 TQMA31 1810
1801ccw9p9215js MACH_CCW9P9215JS CCW9P9215JS 1811
1802rd88f5181l_ge MACH_RD88F5181L_GE RD88F5181L_GE 1812
1803sifmain MACH_SIFMAIN SIFMAIN 1813
1804sam9_l9261 MACH_SAM9_L9261 SAM9_L9261 1814
1805cc9m2443js MACH_CC9M2443JS CC9M2443JS 1815
1806xaria300 MACH_XARIA300 XARIA300 1816
1807it9200 MACH_IT9200 IT9200 1817
1808rd88f5181l_fxo MACH_RD88F5181L_FXO RD88F5181L_FXO 1818
1809kriss_sensor MACH_KRISS_SENSOR KRISS_SENSOR 1819
1810pilz_pmi5 MACH_PILZ_PMI5 PILZ_PMI5 1820
1811jade MACH_JADE JADE 1821
1812ks8695_softplc MACH_KS8695_SOFTPLC KS8695_SOFTPLC 1822
1813gprisc4 MACH_GPRISC4 GPRISC4 1823
1814stamp9260 MACH_STAMP9260 STAMP9260 1824