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-rw-r--r--arch/arm/Kconfig8
-rw-r--r--arch/arm/boot/dts/highbank.dts91
-rw-r--r--arch/arm/kernel/bios32.c4
-rw-r--r--arch/arm/mach-davinci/Kconfig6
-rw-r--r--arch/arm/mach-highbank/Makefile2
-rw-r--r--arch/arm/mach-highbank/clock.c62
-rw-r--r--arch/arm/mach-highbank/highbank.c7
-rw-r--r--arch/arm/mach-integrator/core.c55
-rw-r--r--arch/arm/mach-integrator/include/mach/clkdev.h26
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c8
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c69
-rw-r--r--arch/arm/mach-omap2/board-apollon.c2
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c2
-rw-r--r--arch/arm/mach-omap2/omap-mpuss-lowpower.c2
-rw-r--r--arch/arm/mach-omap2/sr_device.c2
-rw-r--r--arch/arm/mach-omap2/twl-common.c2
-rw-r--r--arch/arm/mach-u300/Makefile2
-rw-r--r--arch/arm/mach-u300/clock.c1504
-rw-r--r--arch/arm/mach-u300/clock.h50
-rw-r--r--arch/arm/mach-u300/core.c21
-rw-r--r--arch/arm/mach-u300/timer.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500.c14
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg.h2
23 files changed, 155 insertions, 1788 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c7e6d208fa8d..b25c9d3c379a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -273,8 +273,8 @@ config ARCH_INTEGRATOR
273 bool "ARM Ltd. Integrator family" 273 bool "ARM Ltd. Integrator family"
274 select ARM_AMBA 274 select ARM_AMBA
275 select ARCH_HAS_CPUFREQ 275 select ARCH_HAS_CPUFREQ
276 select CLKDEV_LOOKUP 276 select COMMON_CLK
277 select HAVE_MACH_CLKDEV 277 select CLK_VERSATILE
278 select HAVE_TCM 278 select HAVE_TCM
279 select ICST 279 select ICST
280 select GENERIC_CLOCKEVENTS 280 select GENERIC_CLOCKEVENTS
@@ -336,6 +336,7 @@ config ARCH_VEXPRESS
336 select ICST 336 select ICST
337 select NO_IOPORT 337 select NO_IOPORT
338 select PLAT_VERSATILE 338 select PLAT_VERSATILE
339 select PLAT_VERSATILE_CLOCK
339 select PLAT_VERSATILE_CLCD 340 select PLAT_VERSATILE_CLCD
340 select REGULATOR_FIXED_VOLTAGE if REGULATOR 341 select REGULATOR_FIXED_VOLTAGE if REGULATOR
341 help 342 help
@@ -372,6 +373,7 @@ config ARCH_HIGHBANK
372 select ARM_TIMER_SP804 373 select ARM_TIMER_SP804
373 select CACHE_L2X0 374 select CACHE_L2X0
374 select CLKDEV_LOOKUP 375 select CLKDEV_LOOKUP
376 select COMMON_CLK
375 select CPU_V7 377 select CPU_V7
376 select GENERIC_CLOCKEVENTS 378 select GENERIC_CLOCKEVENTS
377 select HAVE_ARM_SCU 379 select HAVE_ARM_SCU
@@ -929,7 +931,7 @@ config ARCH_U300
929 select ARM_VIC 931 select ARM_VIC
930 select GENERIC_CLOCKEVENTS 932 select GENERIC_CLOCKEVENTS
931 select CLKDEV_LOOKUP 933 select CLKDEV_LOOKUP
932 select HAVE_MACH_CLKDEV 934 select COMMON_CLK
933 select GENERIC_GPIO 935 select GENERIC_GPIO
934 select ARCH_REQUIRE_GPIOLIB 936 select ARCH_REQUIRE_GPIOLIB
935 help 937 help
diff --git a/arch/arm/boot/dts/highbank.dts b/arch/arm/boot/dts/highbank.dts
index 83e72294aefb..2e1cfa00c25b 100644
--- a/arch/arm/boot/dts/highbank.dts
+++ b/arch/arm/boot/dts/highbank.dts
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2011 Calxeda, Inc. 2 * Copyright 2011-2012 Calxeda, Inc.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -24,6 +24,7 @@
24 compatible = "calxeda,highbank"; 24 compatible = "calxeda,highbank";
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <1>; 26 #size-cells = <1>;
27 clock-ranges;
27 28
28 cpus { 29 cpus {
29 #address-cells = <1>; 30 #address-cells = <1>;
@@ -33,24 +34,32 @@
33 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
34 reg = <0>; 35 reg = <0>;
35 next-level-cache = <&L2>; 36 next-level-cache = <&L2>;
37 clocks = <&a9pll>;
38 clock-names = "cpu";
36 }; 39 };
37 40
38 cpu@1 { 41 cpu@1 {
39 compatible = "arm,cortex-a9"; 42 compatible = "arm,cortex-a9";
40 reg = <1>; 43 reg = <1>;
41 next-level-cache = <&L2>; 44 next-level-cache = <&L2>;
45 clocks = <&a9pll>;
46 clock-names = "cpu";
42 }; 47 };
43 48
44 cpu@2 { 49 cpu@2 {
45 compatible = "arm,cortex-a9"; 50 compatible = "arm,cortex-a9";
46 reg = <2>; 51 reg = <2>;
47 next-level-cache = <&L2>; 52 next-level-cache = <&L2>;
53 clocks = <&a9pll>;
54 clock-names = "cpu";
48 }; 55 };
49 56
50 cpu@3 { 57 cpu@3 {
51 compatible = "arm,cortex-a9"; 58 compatible = "arm,cortex-a9";
52 reg = <3>; 59 reg = <3>;
53 next-level-cache = <&L2>; 60 next-level-cache = <&L2>;
61 clocks = <&a9pll>;
62 clock-names = "cpu";
54 }; 63 };
55 }; 64 };
56 65
@@ -75,12 +84,14 @@
75 compatible = "arm,cortex-a9-twd-timer"; 84 compatible = "arm,cortex-a9-twd-timer";
76 reg = <0xfff10600 0x20>; 85 reg = <0xfff10600 0x20>;
77 interrupts = <1 13 0xf01>; 86 interrupts = <1 13 0xf01>;
87 clocks = <&a9periphclk>;
78 }; 88 };
79 89
80 watchdog@fff10620 { 90 watchdog@fff10620 {
81 compatible = "arm,cortex-a9-twd-wdt"; 91 compatible = "arm,cortex-a9-twd-wdt";
82 reg = <0xfff10620 0x20>; 92 reg = <0xfff10620 0x20>;
83 interrupts = <1 14 0xf01>; 93 interrupts = <1 14 0xf01>;
94 clocks = <&a9periphclk>;
84 }; 95 };
85 96
86 intc: interrupt-controller@fff11000 { 97 intc: interrupt-controller@fff11000 {
@@ -116,12 +127,15 @@
116 compatible = "calxeda,hb-sdhci"; 127 compatible = "calxeda,hb-sdhci";
117 reg = <0xffe0e000 0x1000>; 128 reg = <0xffe0e000 0x1000>;
118 interrupts = <0 90 4>; 129 interrupts = <0 90 4>;
130 clocks = <&eclk>;
119 }; 131 };
120 132
121 ipc@fff20000 { 133 ipc@fff20000 {
122 compatible = "arm,pl320", "arm,primecell"; 134 compatible = "arm,pl320", "arm,primecell";
123 reg = <0xfff20000 0x1000>; 135 reg = <0xfff20000 0x1000>;
124 interrupts = <0 7 4>; 136 interrupts = <0 7 4>;
137 clocks = <&pclk>;
138 clock-names = "apb_pclk";
125 }; 139 };
126 140
127 gpioe: gpio@fff30000 { 141 gpioe: gpio@fff30000 {
@@ -130,6 +144,8 @@
130 gpio-controller; 144 gpio-controller;
131 reg = <0xfff30000 0x1000>; 145 reg = <0xfff30000 0x1000>;
132 interrupts = <0 14 4>; 146 interrupts = <0 14 4>;
147 clocks = <&pclk>;
148 clock-names = "apb_pclk";
133 }; 149 };
134 150
135 gpiof: gpio@fff31000 { 151 gpiof: gpio@fff31000 {
@@ -138,6 +154,8 @@
138 gpio-controller; 154 gpio-controller;
139 reg = <0xfff31000 0x1000>; 155 reg = <0xfff31000 0x1000>;
140 interrupts = <0 15 4>; 156 interrupts = <0 15 4>;
157 clocks = <&pclk>;
158 clock-names = "apb_pclk";
141 }; 159 };
142 160
143 gpiog: gpio@fff32000 { 161 gpiog: gpio@fff32000 {
@@ -146,6 +164,8 @@
146 gpio-controller; 164 gpio-controller;
147 reg = <0xfff32000 0x1000>; 165 reg = <0xfff32000 0x1000>;
148 interrupts = <0 16 4>; 166 interrupts = <0 16 4>;
167 clocks = <&pclk>;
168 clock-names = "apb_pclk";
149 }; 169 };
150 170
151 gpioh: gpio@fff33000 { 171 gpioh: gpio@fff33000 {
@@ -154,24 +174,32 @@
154 gpio-controller; 174 gpio-controller;
155 reg = <0xfff33000 0x1000>; 175 reg = <0xfff33000 0x1000>;
156 interrupts = <0 17 4>; 176 interrupts = <0 17 4>;
177 clocks = <&pclk>;
178 clock-names = "apb_pclk";
157 }; 179 };
158 180
159 timer { 181 timer {
160 compatible = "arm,sp804", "arm,primecell"; 182 compatible = "arm,sp804", "arm,primecell";
161 reg = <0xfff34000 0x1000>; 183 reg = <0xfff34000 0x1000>;
162 interrupts = <0 18 4>; 184 interrupts = <0 18 4>;
185 clocks = <&pclk>;
186 clock-names = "apb_pclk";
163 }; 187 };
164 188
165 rtc@fff35000 { 189 rtc@fff35000 {
166 compatible = "arm,pl031", "arm,primecell"; 190 compatible = "arm,pl031", "arm,primecell";
167 reg = <0xfff35000 0x1000>; 191 reg = <0xfff35000 0x1000>;
168 interrupts = <0 19 4>; 192 interrupts = <0 19 4>;
193 clocks = <&pclk>;
194 clock-names = "apb_pclk";
169 }; 195 };
170 196
171 serial@fff36000 { 197 serial@fff36000 {
172 compatible = "arm,pl011", "arm,primecell"; 198 compatible = "arm,pl011", "arm,primecell";
173 reg = <0xfff36000 0x1000>; 199 reg = <0xfff36000 0x1000>;
174 interrupts = <0 20 4>; 200 interrupts = <0 20 4>;
201 clocks = <&pclk>;
202 clock-names = "apb_pclk";
175 }; 203 };
176 204
177 smic@fff3a000 { 205 smic@fff3a000 {
@@ -186,12 +214,73 @@
186 sregs@fff3c000 { 214 sregs@fff3c000 {
187 compatible = "calxeda,hb-sregs"; 215 compatible = "calxeda,hb-sregs";
188 reg = <0xfff3c000 0x1000>; 216 reg = <0xfff3c000 0x1000>;
217
218 clocks {
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 osc: oscillator {
223 #clock-cells = <0>;
224 compatible = "fixed-clock";
225 clock-frequency = <33333000>;
226 };
227
228 ddrpll: ddrpll {
229 #clock-cells = <0>;
230 compatible = "calxeda,hb-pll-clock";
231 clocks = <&osc>;
232 reg = <0x108>;
233 };
234
235 a9pll: a9pll {
236 #clock-cells = <0>;
237 compatible = "calxeda,hb-pll-clock";
238 clocks = <&osc>;
239 reg = <0x100>;
240 };
241
242 a9periphclk: a9periphclk {
243 #clock-cells = <0>;
244 compatible = "calxeda,hb-a9periph-clock";
245 clocks = <&a9pll>;
246 reg = <0x104>;
247 };
248
249 a9bclk: a9bclk {
250 #clock-cells = <0>;
251 compatible = "calxeda,hb-a9bus-clock";
252 clocks = <&a9pll>;
253 reg = <0x104>;
254 };
255
256 emmcpll: emmcpll {
257 #clock-cells = <0>;
258 compatible = "calxeda,hb-pll-clock";
259 clocks = <&osc>;
260 reg = <0x10C>;
261 };
262
263 eclk: eclk {
264 #clock-cells = <0>;
265 compatible = "calxeda,hb-emmc-clock";
266 clocks = <&emmcpll>;
267 reg = <0x114>;
268 };
269
270 pclk: pclk {
271 #clock-cells = <0>;
272 compatible = "fixed-clock";
273 clock-frequency = <150000000>;
274 };
275 };
189 }; 276 };
190 277
191 dma@fff3d000 { 278 dma@fff3d000 {
192 compatible = "arm,pl330", "arm,primecell"; 279 compatible = "arm,pl330", "arm,primecell";
193 reg = <0xfff3d000 0x1000>; 280 reg = <0xfff3d000 0x1000>;
194 interrupts = <0 92 4>; 281 interrupts = <0 92 4>;
282 clocks = <&pclk>;
283 clock-names = "apb_pclk";
195 }; 284 };
196 285
197 ethernet@fff50000 { 286 ethernet@fff50000 {
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 25552508c3fd..2b2f25e7fef5 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -253,7 +253,7 @@ static void __devinit pci_fixup_cy82c693(struct pci_dev *dev)
253} 253}
254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693); 254DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
255 255
256static void __init pci_fixup_it8152(struct pci_dev *dev) 256static void __devinit pci_fixup_it8152(struct pci_dev *dev)
257{ 257{
258 int i; 258 int i;
259 /* fixup for ITE 8152 devices */ 259 /* fixup for ITE 8152 devices */
@@ -461,7 +461,7 @@ static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
461 if (!sys->bus) 461 if (!sys->bus)
462 panic("PCI: unable to scan bus!"); 462 panic("PCI: unable to scan bus!");
463 463
464 busnr = sys->bus->subordinate + 1; 464 busnr = sys->bus->busn_res.end + 1;
465 465
466 list_add(&sys->node, head); 466 list_add(&sys->node, head);
467 } else { 467 } else {
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index 2ce1ef07c13d..ab99c3c3b752 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -62,7 +62,6 @@ config MACH_DAVINCI_EVM
62 bool "TI DM644x EVM" 62 bool "TI DM644x EVM"
63 default ARCH_DAVINCI_DM644x 63 default ARCH_DAVINCI_DM644x
64 depends on ARCH_DAVINCI_DM644x 64 depends on ARCH_DAVINCI_DM644x
65 select MISC_DEVICES
66 select EEPROM_AT24 65 select EEPROM_AT24
67 select I2C 66 select I2C
68 help 67 help
@@ -72,7 +71,6 @@ config MACH_DAVINCI_EVM
72config MACH_SFFSDR 71config MACH_SFFSDR
73 bool "Lyrtech SFFSDR" 72 bool "Lyrtech SFFSDR"
74 depends on ARCH_DAVINCI_DM644x 73 depends on ARCH_DAVINCI_DM644x
75 select MISC_DEVICES
76 select EEPROM_AT24 74 select EEPROM_AT24
77 select I2C 75 select I2C
78 help 76 help
@@ -106,7 +104,6 @@ config MACH_DAVINCI_DM6467_EVM
106 default ARCH_DAVINCI_DM646x 104 default ARCH_DAVINCI_DM646x
107 depends on ARCH_DAVINCI_DM646x 105 depends on ARCH_DAVINCI_DM646x
108 select MACH_DAVINCI_DM6467TEVM 106 select MACH_DAVINCI_DM6467TEVM
109 select MISC_DEVICES
110 select EEPROM_AT24 107 select EEPROM_AT24
111 select I2C 108 select I2C
112 help 109 help
@@ -120,7 +117,6 @@ config MACH_DAVINCI_DM365_EVM
120 bool "TI DM365 EVM" 117 bool "TI DM365 EVM"
121 default ARCH_DAVINCI_DM365 118 default ARCH_DAVINCI_DM365
122 depends on ARCH_DAVINCI_DM365 119 depends on ARCH_DAVINCI_DM365
123 select MISC_DEVICES
124 select EEPROM_AT24 120 select EEPROM_AT24
125 select I2C 121 select I2C
126 help 122 help
@@ -132,7 +128,6 @@ config MACH_DAVINCI_DA830_EVM
132 default ARCH_DAVINCI_DA830 128 default ARCH_DAVINCI_DA830
133 depends on ARCH_DAVINCI_DA830 129 depends on ARCH_DAVINCI_DA830
134 select GPIO_PCF857X 130 select GPIO_PCF857X
135 select MISC_DEVICES
136 select EEPROM_AT24 131 select EEPROM_AT24
137 select I2C 132 select I2C
138 help 133 help
@@ -219,7 +214,6 @@ config MACH_TNETV107X
219config MACH_MITYOMAPL138 214config MACH_MITYOMAPL138
220 bool "Critical Link MityDSP-L138/MityARM-1808 SoM" 215 bool "Critical Link MityDSP-L138/MityARM-1808 SoM"
221 depends on ARCH_DAVINCI_DA850 216 depends on ARCH_DAVINCI_DA850
222 select MISC_DEVICES
223 select EEPROM_AT24 217 select EEPROM_AT24
224 select I2C 218 select I2C
225 help 219 help
diff --git a/arch/arm/mach-highbank/Makefile b/arch/arm/mach-highbank/Makefile
index ded4652ada80..3ec8bdd25d09 100644
--- a/arch/arm/mach-highbank/Makefile
+++ b/arch/arm/mach-highbank/Makefile
@@ -1,4 +1,4 @@
1obj-y := clock.o highbank.o system.o smc.o 1obj-y := highbank.o system.o smc.o
2 2
3plus_sec := $(call as-instr,.arch_extension sec,+sec) 3plus_sec := $(call as-instr,.arch_extension sec,+sec)
4AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec) 4AFLAGS_smc.o :=-Wa,-march=armv7-a$(plus_sec)
diff --git a/arch/arm/mach-highbank/clock.c b/arch/arm/mach-highbank/clock.c
deleted file mode 100644
index c25a2ae4fde1..000000000000
--- a/arch/arm/mach-highbank/clock.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Copyright 2011 Calxeda, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/errno.h>
19#include <linux/clk.h>
20#include <linux/clkdev.h>
21
22struct clk {
23 unsigned long rate;
24};
25
26int clk_enable(struct clk *clk)
27{
28 return 0;
29}
30
31void clk_disable(struct clk *clk)
32{}
33
34unsigned long clk_get_rate(struct clk *clk)
35{
36 return clk->rate;
37}
38
39long clk_round_rate(struct clk *clk, unsigned long rate)
40{
41 return clk->rate;
42}
43
44int clk_set_rate(struct clk *clk, unsigned long rate)
45{
46 return 0;
47}
48
49static struct clk eclk = { .rate = 200000000 };
50static struct clk pclk = { .rate = 150000000 };
51
52static struct clk_lookup lookups[] = {
53 { .clk = &pclk, .con_id = "apb_pclk", },
54 { .clk = &pclk, .dev_id = "sp804", },
55 { .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
56 { .clk = &pclk, .dev_id = "fff36000.serial", },
57};
58
59void __init highbank_clocks_init(void)
60{
61 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
62}
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 8777612b1a42..d75b0a78d88a 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -105,6 +105,11 @@ static void __init highbank_init_irq(void)
105#endif 105#endif
106} 106}
107 107
108static struct clk_lookup lookup = {
109 .dev_id = "sp804",
110 .con_id = NULL,
111};
112
108static void __init highbank_timer_init(void) 113static void __init highbank_timer_init(void)
109{ 114{
110 int irq; 115 int irq;
@@ -122,6 +127,8 @@ static void __init highbank_timer_init(void)
122 irq = irq_of_parse_and_map(np, 0); 127 irq = irq_of_parse_and_map(np, 0);
123 128
124 highbank_clocks_init(); 129 highbank_clocks_init();
130 lookup.clk = of_clk_get(np, 0);
131 clkdev_add(&lookup);
125 132
126 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1"); 133 sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
127 sp804_clockevents_init(timer_base, irq, "timer0"); 134 sp804_clockevents_init(timer_base, irq, "timer0");
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index eaf6c6366ffa..ebf680bebdf2 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -21,7 +21,6 @@
21#include <linux/amba/bus.h> 21#include <linux/amba/bus.h>
22#include <linux/amba/serial.h> 22#include <linux/amba/serial.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/clkdev.h>
25 24
26#include <mach/hardware.h> 25#include <mach/hardware.h>
27#include <mach/platform.h> 26#include <mach/platform.h>
@@ -41,17 +40,17 @@ static struct amba_pl010_data integrator_uart_data;
41#define KMI0_IRQ { IRQ_KMIINT0 } 40#define KMI0_IRQ { IRQ_KMIINT0 }
42#define KMI1_IRQ { IRQ_KMIINT1 } 41#define KMI1_IRQ { IRQ_KMIINT1 }
43 42
44static AMBA_APB_DEVICE(rtc, "mb:15", 0, 43static AMBA_APB_DEVICE(rtc, "rtc", 0,
45 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); 44 INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL);
46 45
47static AMBA_APB_DEVICE(uart0, "mb:16", 0, 46static AMBA_APB_DEVICE(uart0, "uart0", 0,
48 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data); 47 INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, &integrator_uart_data);
49 48
50static AMBA_APB_DEVICE(uart1, "mb:17", 0, 49static AMBA_APB_DEVICE(uart1, "uart1", 0,
51 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data); 50 INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, &integrator_uart_data);
52 51
53static AMBA_APB_DEVICE(kmi0, "mb:18", 0, KMI0_BASE, KMI0_IRQ, NULL); 52static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL);
54static AMBA_APB_DEVICE(kmi1, "mb:19", 0, KMI1_BASE, KMI1_IRQ, NULL); 53static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL);
55 54
56static struct amba_device *amba_devs[] __initdata = { 55static struct amba_device *amba_devs[] __initdata = {
57 &rtc_device, 56 &rtc_device,
@@ -61,50 +60,6 @@ static struct amba_device *amba_devs[] __initdata = {
61 &kmi1_device, 60 &kmi1_device,
62}; 61};
63 62
64/*
65 * These are fixed clocks.
66 */
67static struct clk clk24mhz = {
68 .rate = 24000000,
69};
70
71static struct clk uartclk = {
72 .rate = 14745600,
73};
74
75static struct clk dummy_apb_pclk;
76
77static struct clk_lookup lookups[] = {
78 { /* Bus clock */
79 .con_id = "apb_pclk",
80 .clk = &dummy_apb_pclk,
81 }, {
82 /* Integrator/AP timer frequency */
83 .dev_id = "ap_timer",
84 .clk = &clk24mhz,
85 }, { /* UART0 */
86 .dev_id = "mb:16",
87 .clk = &uartclk,
88 }, { /* UART1 */
89 .dev_id = "mb:17",
90 .clk = &uartclk,
91 }, { /* KMI0 */
92 .dev_id = "mb:18",
93 .clk = &clk24mhz,
94 }, { /* KMI1 */
95 .dev_id = "mb:19",
96 .clk = &clk24mhz,
97 }, { /* MMCI - IntegratorCP */
98 .dev_id = "mb:1c",
99 .clk = &uartclk,
100 }
101};
102
103void __init integrator_init_early(void)
104{
105 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
106}
107
108static int __init integrator_init(void) 63static int __init integrator_init(void)
109{ 64{
110 int i; 65 int i;
diff --git a/arch/arm/mach-integrator/include/mach/clkdev.h b/arch/arm/mach-integrator/include/mach/clkdev.h
deleted file mode 100644
index bfe07679faec..000000000000
--- a/arch/arm/mach-integrator/include/mach/clkdev.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4#include <linux/module.h>
5#include <plat/clock.h>
6
7struct clk {
8 unsigned long rate;
9 const struct clk_ops *ops;
10 struct module *owner;
11 const struct icst_params *params;
12 void __iomem *vcoreg;
13 void *data;
14};
15
16static inline int __clk_get(struct clk *clk)
17{
18 return try_module_get(clk->owner);
19}
20
21static inline void __clk_put(struct clk *clk)
22{
23 module_put(clk->owner);
24}
25
26#endif
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index c857501c5783..7b1055c8e0b9 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -33,6 +33,7 @@
33#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/mtd/physmap.h> 34#include <linux/mtd/physmap.h>
35#include <linux/clk.h> 35#include <linux/clk.h>
36#include <linux/platform_data/clk-integrator.h>
36#include <video/vga.h> 37#include <video/vga.h>
37 38
38#include <mach/hardware.h> 39#include <mach/hardware.h>
@@ -174,6 +175,7 @@ static void __init ap_init_irq(void)
174 175
175 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, 176 fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START,
176 -1, INTEGRATOR_SC_VALID_INT, NULL); 177 -1, INTEGRATOR_SC_VALID_INT, NULL);
178 integrator_clk_init(false);
177} 179}
178 180
179#ifdef CONFIG_PM 181#ifdef CONFIG_PM
@@ -440,6 +442,10 @@ static void integrator_clockevent_init(unsigned long inrate)
440 0xffffU); 442 0xffffU);
441} 443}
442 444
445void __init ap_init_early(void)
446{
447}
448
443/* 449/*
444 * Set up timer(s). 450 * Set up timer(s).
445 */ 451 */
@@ -471,7 +477,7 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
471 .reserve = integrator_reserve, 477 .reserve = integrator_reserve,
472 .map_io = ap_map_io, 478 .map_io = ap_map_io,
473 .nr_irqs = NR_IRQS_INTEGRATOR_AP, 479 .nr_irqs = NR_IRQS_INTEGRATOR_AP,
474 .init_early = integrator_init_early, 480 .init_early = ap_init_early,
475 .init_irq = ap_init_irq, 481 .init_irq = ap_init_irq,
476 .handle_irq = fpga_handle_irq, 482 .handle_irq = fpga_handle_irq,
477 .timer = &ap_timer, 483 .timer = &ap_timer,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index a56c53608939..82d5c837cc74 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -21,8 +21,8 @@
21#include <linux/amba/mmci.h> 21#include <linux/amba/mmci.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/gfp.h> 23#include <linux/gfp.h>
24#include <linux/clkdev.h>
25#include <linux/mtd/physmap.h> 24#include <linux/mtd/physmap.h>
25#include <linux/platform_data/clk-integrator.h>
26 26
27#include <mach/hardware.h> 27#include <mach/hardware.h>
28#include <mach/platform.h> 28#include <mach/platform.h>
@@ -171,65 +171,10 @@ static void __init intcp_init_irq(void)
171 171
172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, 172 fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START,
173 IRQ_CP_CPPLDINT, sic_mask, NULL); 173 IRQ_CP_CPPLDINT, sic_mask, NULL);
174 integrator_clk_init(true);
174} 175}
175 176
176/* 177/*
177 * Clock handling
178 */
179#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
180#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
181
182static const struct icst_params cp_auxvco_params = {
183 .ref = 24000000,
184 .vco_max = ICST525_VCO_MAX_5V,
185 .vco_min = ICST525_VCO_MIN,
186 .vd_min = 8,
187 .vd_max = 263,
188 .rd_min = 3,
189 .rd_max = 65,
190 .s2div = icst525_s2div,
191 .idx2s = icst525_idx2s,
192};
193
194static void cp_auxvco_set(struct clk *clk, struct icst_vco vco)
195{
196 u32 val;
197
198 val = readl(clk->vcoreg) & ~0x7ffff;
199 val |= vco.v | (vco.r << 9) | (vco.s << 16);
200
201 writel(0xa05f, CM_LOCK);
202 writel(val, clk->vcoreg);
203 writel(0, CM_LOCK);
204}
205
206static const struct clk_ops cp_auxclk_ops = {
207 .round = icst_clk_round,
208 .set = icst_clk_set,
209 .setvco = cp_auxvco_set,
210};
211
212static struct clk cp_auxclk = {
213 .ops = &cp_auxclk_ops,
214 .params = &cp_auxvco_params,
215 .vcoreg = CM_AUXOSC,
216};
217
218static struct clk sp804_clk = {
219 .rate = 1000000,
220};
221
222static struct clk_lookup cp_lookups[] = {
223 { /* CLCD */
224 .dev_id = "mb:c0",
225 .clk = &cp_auxclk,
226 }, { /* SP804 timers */
227 .dev_id = "sp804",
228 .clk = &sp804_clk,
229 },
230};
231
232/*
233 * Flash handling. 178 * Flash handling.
234 */ 179 */
235static int intcp_flash_init(struct platform_device *dev) 180static int intcp_flash_init(struct platform_device *dev)
@@ -336,10 +281,10 @@ static struct mmci_platform_data mmc_data = {
336#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } 281#define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 }
337#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } 282#define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT }
338 283
339static AMBA_APB_DEVICE(mmc, "mb:1c", 0, INTEGRATOR_CP_MMC_BASE, 284static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE,
340 INTEGRATOR_CP_MMC_IRQS, &mmc_data); 285 INTEGRATOR_CP_MMC_IRQS, &mmc_data);
341 286
342static AMBA_APB_DEVICE(aaci, "mb:1d", 0, INTEGRATOR_CP_AACI_BASE, 287static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE,
343 INTEGRATOR_CP_AACI_IRQS, NULL); 288 INTEGRATOR_CP_AACI_IRQS, NULL);
344 289
345 290
@@ -393,7 +338,7 @@ static struct clcd_board clcd_data = {
393 .remove = versatile_clcd_remove_dma, 338 .remove = versatile_clcd_remove_dma,
394}; 339};
395 340
396static AMBA_AHB_DEVICE(clcd, "mb:c0", 0, INTCP_PA_CLCD_BASE, 341static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE,
397 { IRQ_CP_CLCDCINT }, &clcd_data); 342 { IRQ_CP_CLCDCINT }, &clcd_data);
398 343
399static struct amba_device *amba_devs[] __initdata = { 344static struct amba_device *amba_devs[] __initdata = {
@@ -406,10 +351,6 @@ static struct amba_device *amba_devs[] __initdata = {
406 351
407static void __init intcp_init_early(void) 352static void __init intcp_init_early(void)
408{ 353{
409 clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
410
411 integrator_init_early();
412
413#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK 354#ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
414 versatile_sched_clock_init(REFCOUNTER, 24000000); 355 versatile_sched_clock_init(REFCOUNTER, 24000000);
415#endif 356#endif
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 519bcd3079e8..e5fa46bfde2f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -311,7 +311,7 @@ static void __init omap_apollon_init(void)
311 /* LCD PWR_EN */ 311 /* LCD PWR_EN */
312 omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP); 312 omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
313 313
314 /* Use Interal loop-back in MMC/SDIO Module Input Clock selection */ 314 /* Use Internal loop-back in MMC/SDIO Module Input Clock selection */
315 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 315 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
316 v |= (1 << 24); 316 v |= (1 << 24);
317 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); 317 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index b627cdc12b84..70f6d1d25463 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -106,7 +106,7 @@ static struct platform_device leds_gpio = {
106static struct omap_abe_twl6040_data panda_abe_audio_data = { 106static struct omap_abe_twl6040_data panda_abe_audio_data = {
107 /* Audio out */ 107 /* Audio out */
108 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, 108 .has_hs = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
109 /* HandsFree through expasion connector */ 109 /* HandsFree through expansion connector */
110 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, 110 .has_hf = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
111 /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */ 111 /* PandaBoard: FM TX, PandaBoardES: can be connected to audio out */
112 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT, 112 .has_aux = ABE_TWL6040_LEFT | ABE_TWL6040_RIGHT,
diff --git a/arch/arm/mach-omap2/omap-mpuss-lowpower.c b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
index e35a86bf4e1d..637a1bdf2ac4 100644
--- a/arch/arm/mach-omap2/omap-mpuss-lowpower.c
+++ b/arch/arm/mach-omap2/omap-mpuss-lowpower.c
@@ -313,7 +313,7 @@ int __cpuinit omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
313 scu_pwrst_prepare(cpu, power_state); 313 scu_pwrst_prepare(cpu, power_state);
314 314
315 /* 315 /*
316 * CPU never retuns back if targetted power state is OFF mode. 316 * CPU never retuns back if targeted power state is OFF mode.
317 * CPU ONLINE follows normal CPU ONLINE ptah via 317 * CPU ONLINE follows normal CPU ONLINE ptah via
318 * omap_secondary_startup(). 318 * omap_secondary_startup().
319 */ 319 */
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index e107e3915a8a..d033a65f4e4e 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -131,7 +131,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
131 131
132 omap_voltage_get_volttable(sr_data->voltdm, &volt_data); 132 omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
133 if (!volt_data) { 133 if (!volt_data) {
134 pr_warning("%s: No Voltage table registerd fo VDD%d." 134 pr_warning("%s: No Voltage table registered fo VDD%d."
135 "Something really wrong\n\n", __func__, i + 1); 135 "Something really wrong\n\n", __func__, i + 1);
136 goto exit; 136 goto exit;
137 } 137 }
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 3882f3c7608c..de47f170ba50 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -96,7 +96,7 @@ void __init omap4_pmic_init(const char *pmic_type,
96 96
97void __init omap_pmic_late_init(void) 97void __init omap_pmic_late_init(void)
98{ 98{
99 /* Init the OMAP TWL parameters (if PMIC has been registerd) */ 99 /* Init the OMAP TWL parameters (if PMIC has been registered) */
100 if (pmic_i2c_board_info.irq) 100 if (pmic_i2c_board_info.irq)
101 omap3_twl_init(); 101 omap3_twl_init();
102 if (omap4_i2c1_board_info[0].irq) 102 if (omap4_i2c1_board_info[0].irq)
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index fd3a5c382f47..7e47d37aeb0e 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -2,7 +2,7 @@
2# Makefile for the linux kernel, U300 machine. 2# Makefile for the linux kernel, U300 machine.
3# 3#
4 4
5obj-y := core.o clock.o timer.o 5obj-y := core.o timer.o
6obj-m := 6obj-m :=
7obj-n := 7obj-n :=
8obj- := 8obj- :=
diff --git a/arch/arm/mach-u300/clock.c b/arch/arm/mach-u300/clock.c
deleted file mode 100644
index 5535dd0a78c9..000000000000
--- a/arch/arm/mach-u300/clock.c
+++ /dev/null
@@ -1,1504 +0,0 @@
1/*
2 *
3 * arch/arm/mach-u300/clock.c
4 *
5 *
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
11 *
12 */
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/list.h>
16#include <linux/errno.h>
17#include <linux/err.h>
18#include <linux/string.h>
19#include <linux/clk.h>
20#include <linux/mutex.h>
21#include <linux/spinlock.h>
22#include <linux/debugfs.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/timer.h>
26#include <linux/io.h>
27#include <linux/seq_file.h>
28#include <linux/clkdev.h>
29
30#include <mach/hardware.h>
31#include <mach/syscon.h>
32
33#include "clock.h"
34
35/*
36 * TODO:
37 * - move all handling of the CCR register into this file and create
38 * a spinlock for the CCR register
39 * - switch to the clkdevice lookup mechanism that maps clocks to
40 * device ID:s instead when it becomes available in kernel 2.6.29.
41 * - implement rate get/set for all clocks that need it.
42 */
43
44/*
45 * Syscon clock I/O registers lock so clock requests don't collide
46 * NOTE: this is a local lock only used to lock access to clock and
47 * reset registers in syscon.
48 */
49static DEFINE_SPINLOCK(syscon_clkreg_lock);
50static DEFINE_SPINLOCK(syscon_resetreg_lock);
51
52/*
53 * The clocking hierarchy currently looks like this.
54 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
55 * The ideas is to show dependencies, so a clock higher up in the
56 * hierarchy has to be on in order for another clock to be on. Now,
57 * both CPU and DMA can actually be on top of the hierarchy, and that
58 * is not modeled currently. Instead we have the backbone AMBA bus on
59 * top. This bus cannot be programmed in any way but conceptually it
60 * needs to be active for the bridges and devices to transport data.
61 *
62 * Please be aware that a few clocks are hw controlled, which mean that
63 * the hw itself can turn on/off or change the rate of the clock when
64 * needed!
65 *
66 * AMBA bus
67 * |
68 * +- CPU
69 * +- FSMC NANDIF NAND Flash interface
70 * +- SEMI Shared Memory interface
71 * +- ISP Image Signal Processor (U335 only)
72 * +- CDS (U335 only)
73 * +- DMA Direct Memory Access Controller
74 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
75 * +- APEX
76 * +- VIDEO_ENC AVE2/3 Video Encoder
77 * +- XGAM Graphics Accelerator Controller
78 * +- AHB
79 * |
80 * +- ahb:0 AHB Bridge
81 * | |
82 * | +- ahb:1 INTCON Interrupt controller
83 * | +- ahb:3 MSPRO Memory Stick Pro controller
84 * | +- ahb:4 EMIF External Memory interface
85 * |
86 * +- fast:0 FAST bridge
87 * | |
88 * | +- fast:1 MMCSD MMC/SD card reader controller
89 * | +- fast:2 I2S0 PCM I2S channel 0 controller
90 * | +- fast:3 I2S1 PCM I2S channel 1 controller
91 * | +- fast:4 I2C0 I2C channel 0 controller
92 * | +- fast:5 I2C1 I2C channel 1 controller
93 * | +- fast:6 SPI SPI controller
94 * | +- fast:7 UART1 Secondary UART (U335 only)
95 * |
96 * +- slow:0 SLOW bridge
97 * |
98 * +- slow:1 SYSCON (not possible to control)
99 * +- slow:2 WDOG Watchdog
100 * +- slow:3 UART0 primary UART
101 * +- slow:4 TIMER_APP Application timer - used in Linux
102 * +- slow:5 KEYPAD controller
103 * +- slow:6 GPIO controller
104 * +- slow:7 RTC controller
105 * +- slow:8 BT Bus Tracer (not used currently)
106 * +- slow:9 EH Event Handler (not used currently)
107 * +- slow:a TIMER_ACC Access style timer (not used currently)
108 * +- slow:b PPM (U335 only, what is that?)
109 */
110
111/*
112 * Reset control functions. We remember if a block has been
113 * taken out of reset and don't remove the reset assertion again
114 * and vice versa. Currently we only remove resets so the
115 * enablement function is defined out.
116 */
117static void syscon_block_reset_enable(struct clk *clk)
118{
119 u16 val;
120 unsigned long iflags;
121
122 /* Not all blocks support resetting */
123 if (!clk->res_reg || !clk->res_mask)
124 return;
125 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
126 val = readw(clk->res_reg);
127 val |= clk->res_mask;
128 writew(val, clk->res_reg);
129 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
130 clk->reset = true;
131}
132
133static void syscon_block_reset_disable(struct clk *clk)
134{
135 u16 val;
136 unsigned long iflags;
137
138 /* Not all blocks support resetting */
139 if (!clk->res_reg || !clk->res_mask)
140 return;
141 spin_lock_irqsave(&syscon_resetreg_lock, iflags);
142 val = readw(clk->res_reg);
143 val &= ~clk->res_mask;
144 writew(val, clk->res_reg);
145 spin_unlock_irqrestore(&syscon_resetreg_lock, iflags);
146 clk->reset = false;
147}
148
149int __clk_get(struct clk *clk)
150{
151 u16 val;
152
153 /* The MMC and MSPRO clocks need some special set-up */
154 if (!strcmp(clk->name, "MCLK")) {
155 /* Set default MMC clock divisor to 18.9 MHz */
156 writew(0x0054U, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
157 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
158 /* Disable the MMC feedback clock */
159 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
160 /* Disable MSPRO frequency */
161 val &= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
162 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
163 }
164 if (!strcmp(clk->name, "MSPRO")) {
165 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMCR);
166 /* Disable the MMC feedback clock */
167 val &= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE;
168 /* Enable MSPRO frequency */
169 val |= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE;
170 writew(val, U300_SYSCON_VBASE + U300_SYSCON_MMCR);
171 }
172 return 1;
173}
174EXPORT_SYMBOL(__clk_get);
175
176void __clk_put(struct clk *clk)
177{
178}
179EXPORT_SYMBOL(__clk_put);
180
181static void syscon_clk_disable(struct clk *clk)
182{
183 unsigned long iflags;
184
185 /* Don't touch the hardware controlled clocks */
186 if (clk->hw_ctrld)
187 return;
188
189 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
190 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCDR);
191 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
192}
193
194static void syscon_clk_enable(struct clk *clk)
195{
196 unsigned long iflags;
197
198 /* Don't touch the hardware controlled clocks */
199 if (clk->hw_ctrld)
200 return;
201
202 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
203 writew(clk->clk_val, U300_SYSCON_VBASE + U300_SYSCON_SBCER);
204 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
205}
206
207static u16 syscon_clk_get_rate(void)
208{
209 u16 val;
210 unsigned long iflags;
211
212 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
213 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
214 val &= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
215 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
216 return val;
217}
218
219#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220static void enable_i2s0_vcxo(void)
221{
222 u16 val;
223 unsigned long iflags;
224
225 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
226 /* Set I2S0 to use the VCXO 26 MHz clock */
227 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
228 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
229 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
230 val |= U300_SYSCON_CCR_I2S0_USE_VCXO;
231 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
232 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
233 val |= U300_SYSCON_CEFR_I2S0_CLK_EN;
234 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
235 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
236}
237
238static void enable_i2s1_vcxo(void)
239{
240 u16 val;
241 unsigned long iflags;
242
243 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
244 /* Set I2S1 to use the VCXO 26 MHz clock */
245 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
246 val |= U300_SYSCON_CCR_TURN_VCXO_ON;
247 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
248 val |= U300_SYSCON_CCR_I2S1_USE_VCXO;
249 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
250 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
251 val |= U300_SYSCON_CEFR_I2S1_CLK_EN;
252 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
253 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
254}
255
256static void disable_i2s0_vcxo(void)
257{
258 u16 val;
259 unsigned long iflags;
260
261 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
262 /* Disable I2S0 use of the VCXO 26 MHz clock */
263 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
264 val &= ~U300_SYSCON_CCR_I2S0_USE_VCXO;
265 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
266 /* Deactivate VCXO if no one else is using VCXO */
267 if (!(val & U300_SYSCON_CCR_I2S1_USE_VCXO))
268 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
269 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
270 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
271 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
272 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
273 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
274}
275
276static void disable_i2s1_vcxo(void)
277{
278 u16 val;
279 unsigned long iflags;
280
281 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
282 /* Disable I2S1 use of the VCXO 26 MHz clock */
283 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
284 val &= ~U300_SYSCON_CCR_I2S1_USE_VCXO;
285 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
286 /* Deactivate VCXO if no one else is using VCXO */
287 if (!(val & U300_SYSCON_CCR_I2S0_USE_VCXO))
288 val &= ~U300_SYSCON_CCR_TURN_VCXO_ON;
289 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
290 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CEFR);
291 val &= ~U300_SYSCON_CEFR_I2S0_CLK_EN;
292 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CEFR);
293 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
294}
295#endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
296
297
298static void syscon_clk_rate_set_mclk(unsigned long rate)
299{
300 u16 val;
301 u32 reg;
302 unsigned long iflags;
303
304 switch (rate) {
305 case 18900000:
306 val = 0x0054;
307 break;
308 case 20800000:
309 val = 0x0044;
310 break;
311 case 23100000:
312 val = 0x0043;
313 break;
314 case 26000000:
315 val = 0x0033;
316 break;
317 case 29700000:
318 val = 0x0032;
319 break;
320 case 34700000:
321 val = 0x0022;
322 break;
323 case 41600000:
324 val = 0x0021;
325 break;
326 case 52000000:
327 val = 0x0011;
328 break;
329 case 104000000:
330 val = 0x0000;
331 break;
332 default:
333 printk(KERN_ERR "Trying to set MCLK to unknown speed! %ld\n",
334 rate);
335 return;
336 }
337
338 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
339 reg = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
340 ~U300_SYSCON_MMF0R_MASK;
341 writew(reg | val, U300_SYSCON_VBASE + U300_SYSCON_MMF0R);
342 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
343}
344
345void syscon_clk_rate_set_cpuclk(unsigned long rate)
346{
347 u16 val;
348 unsigned long iflags;
349
350 switch (rate) {
351 case 13000000:
352 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER;
353 break;
354 case 52000000:
355 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE;
356 break;
357 case 104000000:
358 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH;
359 break;
360 case 208000000:
361 val = U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST;
362 break;
363 default:
364 return;
365 }
366 spin_lock_irqsave(&syscon_clkreg_lock, iflags);
367 val |= readw(U300_SYSCON_VBASE + U300_SYSCON_CCR) &
368 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK ;
369 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
370 spin_unlock_irqrestore(&syscon_clkreg_lock, iflags);
371}
372EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk);
373
374void clk_disable(struct clk *clk)
375{
376 unsigned long iflags;
377
378 spin_lock_irqsave(&clk->lock, iflags);
379 if (clk->usecount > 0 && !(--clk->usecount)) {
380 /* some blocks lack clocking registers and cannot be disabled */
381 if (clk->disable)
382 clk->disable(clk);
383 if (likely((u32)clk->parent))
384 clk_disable(clk->parent);
385 }
386#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387 if (unlikely(!strcmp(clk->name, "I2S0")))
388 disable_i2s0_vcxo();
389 if (unlikely(!strcmp(clk->name, "I2S1")))
390 disable_i2s1_vcxo();
391#endif
392 spin_unlock_irqrestore(&clk->lock, iflags);
393}
394EXPORT_SYMBOL(clk_disable);
395
396int clk_enable(struct clk *clk)
397{
398 int ret = 0;
399 unsigned long iflags;
400
401 spin_lock_irqsave(&clk->lock, iflags);
402 if (clk->usecount++ == 0) {
403 if (likely((u32)clk->parent))
404 ret = clk_enable(clk->parent);
405
406 if (unlikely(ret != 0))
407 clk->usecount--;
408 else {
409 /* remove reset line (we never enable reset again) */
410 syscon_block_reset_disable(clk);
411 /* clocks without enable function are always on */
412 if (clk->enable)
413 clk->enable(clk);
414#ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415 if (unlikely(!strcmp(clk->name, "I2S0")))
416 enable_i2s0_vcxo();
417 if (unlikely(!strcmp(clk->name, "I2S1")))
418 enable_i2s1_vcxo();
419#endif
420 }
421 }
422 spin_unlock_irqrestore(&clk->lock, iflags);
423 return ret;
424
425}
426EXPORT_SYMBOL(clk_enable);
427
428/* Returns the clock rate in Hz */
429static unsigned long clk_get_rate_cpuclk(struct clk *clk)
430{
431 u16 val;
432
433 val = syscon_clk_get_rate();
434
435 switch (val) {
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
437 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
438 return 13000000;
439 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
440 return 52000000;
441 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
442 return 104000000;
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
444 return 208000000;
445 default:
446 break;
447 }
448 return clk->rate;
449}
450
451static unsigned long clk_get_rate_ahb_clk(struct clk *clk)
452{
453 u16 val;
454
455 val = syscon_clk_get_rate();
456
457 switch (val) {
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
459 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
460 return 6500000;
461 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
462 return 26000000;
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
464 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
465 return 52000000;
466 default:
467 break;
468 }
469 return clk->rate;
470
471}
472
473static unsigned long clk_get_rate_emif_clk(struct clk *clk)
474{
475 u16 val;
476
477 val = syscon_clk_get_rate();
478
479 switch (val) {
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
481 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
482 return 13000000;
483 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
484 return 52000000;
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
486 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
487 return 104000000;
488 default:
489 break;
490 }
491 return clk->rate;
492
493}
494
495static unsigned long clk_get_rate_xgamclk(struct clk *clk)
496{
497 u16 val;
498
499 val = syscon_clk_get_rate();
500
501 switch (val) {
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
503 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
504 return 6500000;
505 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
506 return 26000000;
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
508 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
509 return 52000000;
510 default:
511 break;
512 }
513
514 return clk->rate;
515}
516
517static unsigned long clk_get_rate_mclk(struct clk *clk)
518{
519 u16 val;
520
521 val = syscon_clk_get_rate();
522
523 switch (val) {
524 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
525 /*
526 * Here, the 208 MHz PLL gets shut down and the always
527 * on 13 MHz PLL used for RTC etc kicks into use
528 * instead.
529 */
530 return 13000000;
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
534 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
535 {
536 /*
537 * This clock is under program control. The register is
538 * divided in two nybbles, bit 7-4 gives cycles-1 to count
539 * high, bit 3-0 gives cycles-1 to count low. Distribute
540 * these with no more than 1 cycle difference between
541 * low and high and add low and high to get the actual
542 * divisor. The base PLL is 208 MHz. Writing 0x00 will
543 * divide by 1 and 1 so the highest frequency possible
544 * is 104 MHz.
545 *
546 * e.g. 0x54 =>
547 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
548 */
549 u16 val = readw(U300_SYSCON_VBASE + U300_SYSCON_MMF0R) &
550 U300_SYSCON_MMF0R_MASK;
551 switch (val) {
552 case 0x0054:
553 return 18900000;
554 case 0x0044:
555 return 20800000;
556 case 0x0043:
557 return 23100000;
558 case 0x0033:
559 return 26000000;
560 case 0x0032:
561 return 29700000;
562 case 0x0022:
563 return 34700000;
564 case 0x0021:
565 return 41600000;
566 case 0x0011:
567 return 52000000;
568 case 0x0000:
569 return 104000000;
570 default:
571 break;
572 }
573 }
574 default:
575 break;
576 }
577
578 return clk->rate;
579}
580
581static unsigned long clk_get_rate_i2s_i2c_spi(struct clk *clk)
582{
583 u16 val;
584
585 val = syscon_clk_get_rate();
586
587 switch (val) {
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER:
589 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW:
590 return 13000000;
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH:
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST:
594 return 26000000;
595 default:
596 break;
597 }
598
599 return clk->rate;
600}
601
602unsigned long clk_get_rate(struct clk *clk)
603{
604 if (clk->get_rate)
605 return clk->get_rate(clk);
606 else
607 return clk->rate;
608}
609EXPORT_SYMBOL(clk_get_rate);
610
611static unsigned long clk_round_rate_mclk(struct clk *clk, unsigned long rate)
612{
613 if (rate <= 18900000)
614 return 18900000;
615 if (rate <= 20800000)
616 return 20800000;
617 if (rate <= 23100000)
618 return 23100000;
619 if (rate <= 26000000)
620 return 26000000;
621 if (rate <= 29700000)
622 return 29700000;
623 if (rate <= 34700000)
624 return 34700000;
625 if (rate <= 41600000)
626 return 41600000;
627 if (rate <= 52000000)
628 return 52000000;
629 return -EINVAL;
630}
631
632static unsigned long clk_round_rate_cpuclk(struct clk *clk, unsigned long rate)
633{
634 if (rate <= 13000000)
635 return 13000000;
636 if (rate <= 52000000)
637 return 52000000;
638 if (rate <= 104000000)
639 return 104000000;
640 if (rate <= 208000000)
641 return 208000000;
642 return -EINVAL;
643}
644
645/*
646 * This adjusts a requested rate to the closest exact rate
647 * a certain clock can provide. For a fixed clock it's
648 * mostly clk->rate.
649 */
650long clk_round_rate(struct clk *clk, unsigned long rate)
651{
652 /* TODO: get appropriate switches for EMIFCLK, AHBCLK and MCLK */
653 /* Else default to fixed value */
654
655 if (clk->round_rate) {
656 return (long) clk->round_rate(clk, rate);
657 } else {
658 printk(KERN_ERR "clock: Failed to round rate of %s\n",
659 clk->name);
660 }
661 return (long) clk->rate;
662}
663EXPORT_SYMBOL(clk_round_rate);
664
665static int clk_set_rate_mclk(struct clk *clk, unsigned long rate)
666{
667 syscon_clk_rate_set_mclk(clk_round_rate(clk, rate));
668 return 0;
669}
670
671static int clk_set_rate_cpuclk(struct clk *clk, unsigned long rate)
672{
673 syscon_clk_rate_set_cpuclk(clk_round_rate(clk, rate));
674 return 0;
675}
676
677int clk_set_rate(struct clk *clk, unsigned long rate)
678{
679 /* TODO: set for EMIFCLK and AHBCLK */
680 /* Else assume the clock is fixed and fail */
681 if (clk->set_rate) {
682 return clk->set_rate(clk, rate);
683 } else {
684 printk(KERN_ERR "clock: Failed to set %s to %ld hz\n",
685 clk->name, rate);
686 return -EINVAL;
687 }
688}
689EXPORT_SYMBOL(clk_set_rate);
690
691/*
692 * Clock definitions. The clock parents are set to respective
693 * bridge and the clock framework makes sure that the clocks have
694 * parents activated and are brought out of reset when in use.
695 *
696 * Clocks that have hw_ctrld = true are hw controlled, and the hw
697 * can by itself turn these clocks on and off.
698 * So in other words, we don't really have to care about them.
699 */
700
701static struct clk amba_clk = {
702 .name = "AMBA",
703 .rate = 52000000, /* this varies! */
704 .hw_ctrld = true,
705 .reset = false,
706 .lock = __SPIN_LOCK_UNLOCKED(amba_clk.lock),
707};
708
709/*
710 * These blocks are connected directly to the AMBA bus
711 * with no bridge.
712 */
713
714static struct clk cpu_clk = {
715 .name = "CPU",
716 .parent = &amba_clk,
717 .rate = 208000000, /* this varies! */
718 .hw_ctrld = true,
719 .reset = true,
720 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
721 .res_mask = U300_SYSCON_RRR_CPU_RESET_EN,
722 .set_rate = clk_set_rate_cpuclk,
723 .get_rate = clk_get_rate_cpuclk,
724 .round_rate = clk_round_rate_cpuclk,
725 .lock = __SPIN_LOCK_UNLOCKED(cpu_clk.lock),
726};
727
728static struct clk nandif_clk = {
729 .name = "FSMC",
730 .parent = &amba_clk,
731 .hw_ctrld = false,
732 .reset = true,
733 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
734 .res_mask = U300_SYSCON_RRR_NANDIF_RESET_EN,
735 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
736 .enable = syscon_clk_enable,
737 .disable = syscon_clk_disable,
738 .lock = __SPIN_LOCK_UNLOCKED(nandif_clk.lock),
739};
740
741static struct clk semi_clk = {
742 .name = "SEMI",
743 .parent = &amba_clk,
744 .rate = 0, /* FIXME */
745 /* It is not possible to reset SEMI */
746 .hw_ctrld = false,
747 .reset = false,
748 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
749 .enable = syscon_clk_enable,
750 .disable = syscon_clk_disable,
751 .lock = __SPIN_LOCK_UNLOCKED(semi_clk.lock),
752};
753
754#ifdef CONFIG_MACH_U300_BS335
755static struct clk isp_clk = {
756 .name = "ISP",
757 .parent = &amba_clk,
758 .rate = 0, /* FIXME */
759 .hw_ctrld = false,
760 .reset = true,
761 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
762 .res_mask = U300_SYSCON_RRR_ISP_RESET_EN,
763 .clk_val = U300_SYSCON_SBCER_ISP_CLK_EN,
764 .enable = syscon_clk_enable,
765 .disable = syscon_clk_disable,
766 .lock = __SPIN_LOCK_UNLOCKED(isp_clk.lock),
767};
768
769static struct clk cds_clk = {
770 .name = "CDS",
771 .parent = &amba_clk,
772 .rate = 0, /* FIXME */
773 .hw_ctrld = false,
774 .reset = true,
775 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
776 .res_mask = U300_SYSCON_RRR_CDS_RESET_EN,
777 .clk_val = U300_SYSCON_SBCER_CDS_CLK_EN,
778 .enable = syscon_clk_enable,
779 .disable = syscon_clk_disable,
780 .lock = __SPIN_LOCK_UNLOCKED(cds_clk.lock),
781};
782#endif
783
784static struct clk dma_clk = {
785 .name = "DMA",
786 .parent = &amba_clk,
787 .rate = 52000000, /* this varies! */
788 .hw_ctrld = true,
789 .reset = true,
790 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
791 .res_mask = U300_SYSCON_RRR_DMAC_RESET_EN,
792 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
793 .enable = syscon_clk_enable,
794 .disable = syscon_clk_disable,
795 .lock = __SPIN_LOCK_UNLOCKED(dma_clk.lock),
796};
797
798static struct clk aaif_clk = {
799 .name = "AAIF",
800 .parent = &amba_clk,
801 .rate = 52000000, /* this varies! */
802 .hw_ctrld = true,
803 .reset = true,
804 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
805 .res_mask = U300_SYSCON_RRR_AAIF_RESET_EN,
806 .clk_val = U300_SYSCON_SBCER_AAIF_CLK_EN,
807 .enable = syscon_clk_enable,
808 .disable = syscon_clk_disable,
809 .lock = __SPIN_LOCK_UNLOCKED(aaif_clk.lock),
810};
811
812static struct clk apex_clk = {
813 .name = "APEX",
814 .parent = &amba_clk,
815 .rate = 0, /* FIXME */
816 .hw_ctrld = true,
817 .reset = true,
818 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
819 .res_mask = U300_SYSCON_RRR_APEX_RESET_EN,
820 .clk_val = U300_SYSCON_SBCER_APEX_CLK_EN,
821 .enable = syscon_clk_enable,
822 .disable = syscon_clk_disable,
823 .lock = __SPIN_LOCK_UNLOCKED(apex_clk.lock),
824};
825
826static struct clk video_enc_clk = {
827 .name = "VIDEO_ENC",
828 .parent = &amba_clk,
829 .rate = 208000000, /* this varies! */
830 .hw_ctrld = false,
831 .reset = false,
832 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
833 /* This has XGAM in the name but refers to the video encoder */
834 .res_mask = U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN,
835 .clk_val = U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN,
836 .enable = syscon_clk_enable,
837 .disable = syscon_clk_disable,
838 .lock = __SPIN_LOCK_UNLOCKED(video_enc_clk.lock),
839};
840
841static struct clk xgam_clk = {
842 .name = "XGAMCLK",
843 .parent = &amba_clk,
844 .rate = 52000000, /* this varies! */
845 .hw_ctrld = false,
846 .reset = true,
847 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
848 .res_mask = U300_SYSCON_RRR_XGAM_RESET_EN,
849 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
850 .get_rate = clk_get_rate_xgamclk,
851 .enable = syscon_clk_enable,
852 .disable = syscon_clk_disable,
853 .lock = __SPIN_LOCK_UNLOCKED(xgam_clk.lock),
854};
855
856/* This clock is used to activate the video encoder */
857static struct clk ahb_clk = {
858 .name = "AHB",
859 .parent = &amba_clk,
860 .rate = 52000000, /* this varies! */
861 .hw_ctrld = false, /* This one is set to false due to HW bug */
862 .reset = true,
863 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
864 .res_mask = U300_SYSCON_RRR_AHB_RESET_EN,
865 .clk_val = U300_SYSCON_SBCER_AHB_CLK_EN,
866 .enable = syscon_clk_enable,
867 .disable = syscon_clk_disable,
868 .get_rate = clk_get_rate_ahb_clk,
869 .lock = __SPIN_LOCK_UNLOCKED(ahb_clk.lock),
870};
871
872
873/*
874 * Clocks on the AHB bridge
875 */
876
877static struct clk ahb_subsys_clk = {
878 .name = "AHB_SUBSYS",
879 .parent = &amba_clk,
880 .rate = 52000000, /* this varies! */
881 .hw_ctrld = true,
882 .reset = false,
883 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
884 .enable = syscon_clk_enable,
885 .disable = syscon_clk_disable,
886 .get_rate = clk_get_rate_ahb_clk,
887 .lock = __SPIN_LOCK_UNLOCKED(ahb_subsys_clk.lock),
888};
889
890static struct clk intcon_clk = {
891 .name = "INTCON",
892 .parent = &ahb_subsys_clk,
893 .rate = 52000000, /* this varies! */
894 .hw_ctrld = false,
895 .reset = true,
896 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
897 .res_mask = U300_SYSCON_RRR_INTCON_RESET_EN,
898 /* INTCON can be reset but not clock-gated */
899 .lock = __SPIN_LOCK_UNLOCKED(intcon_clk.lock),
900
901};
902
903static struct clk mspro_clk = {
904 .name = "MSPRO",
905 .parent = &ahb_subsys_clk,
906 .rate = 0, /* FIXME */
907 .hw_ctrld = false,
908 .reset = true,
909 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
910 .res_mask = U300_SYSCON_RRR_MSPRO_RESET_EN,
911 .clk_val = U300_SYSCON_SBCER_MSPRO_CLK_EN,
912 .enable = syscon_clk_enable,
913 .disable = syscon_clk_disable,
914 .lock = __SPIN_LOCK_UNLOCKED(mspro_clk.lock),
915};
916
917static struct clk emif_clk = {
918 .name = "EMIF",
919 .parent = &ahb_subsys_clk,
920 .rate = 104000000, /* this varies! */
921 .hw_ctrld = false,
922 .reset = true,
923 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RRR,
924 .res_mask = U300_SYSCON_RRR_EMIF_RESET_EN,
925 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
926 .enable = syscon_clk_enable,
927 .disable = syscon_clk_disable,
928 .get_rate = clk_get_rate_emif_clk,
929 .lock = __SPIN_LOCK_UNLOCKED(emif_clk.lock),
930};
931
932
933/*
934 * Clocks on the FAST bridge
935 */
936static struct clk fast_clk = {
937 .name = "FAST_BRIDGE",
938 .parent = &amba_clk,
939 .rate = 13000000, /* this varies! */
940 .hw_ctrld = true,
941 .reset = true,
942 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
943 .res_mask = U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE,
944 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
945 .enable = syscon_clk_enable,
946 .disable = syscon_clk_disable,
947 .lock = __SPIN_LOCK_UNLOCKED(fast_clk.lock),
948};
949
950/*
951 * The MMCI apb_pclk is hardwired to the same terminal as the
952 * external MCI clock. Thus this will be referenced twice.
953 */
954static struct clk mmcsd_clk = {
955 .name = "MCLK",
956 .parent = &fast_clk,
957 .rate = 18900000, /* this varies! */
958 .hw_ctrld = false,
959 .reset = true,
960 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
961 .res_mask = U300_SYSCON_RFR_MMC_RESET_ENABLE,
962 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
963 .get_rate = clk_get_rate_mclk,
964 .set_rate = clk_set_rate_mclk,
965 .round_rate = clk_round_rate_mclk,
966 .disable = syscon_clk_disable,
967 .enable = syscon_clk_enable,
968 .lock = __SPIN_LOCK_UNLOCKED(mmcsd_clk.lock),
969};
970
971static struct clk i2s0_clk = {
972 .name = "i2s0",
973 .parent = &fast_clk,
974 .rate = 26000000, /* this varies! */
975 .hw_ctrld = true,
976 .reset = true,
977 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
978 .res_mask = U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE,
979 .clk_val = U300_SYSCON_SBCER_I2S0_CORE_CLK_EN,
980 .enable = syscon_clk_enable,
981 .disable = syscon_clk_disable,
982 .get_rate = clk_get_rate_i2s_i2c_spi,
983 .lock = __SPIN_LOCK_UNLOCKED(i2s0_clk.lock),
984};
985
986static struct clk i2s1_clk = {
987 .name = "i2s1",
988 .parent = &fast_clk,
989 .rate = 26000000, /* this varies! */
990 .hw_ctrld = true,
991 .reset = true,
992 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
993 .res_mask = U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE,
994 .clk_val = U300_SYSCON_SBCER_I2S1_CORE_CLK_EN,
995 .enable = syscon_clk_enable,
996 .disable = syscon_clk_disable,
997 .get_rate = clk_get_rate_i2s_i2c_spi,
998 .lock = __SPIN_LOCK_UNLOCKED(i2s1_clk.lock),
999};
1000
1001static struct clk i2c0_clk = {
1002 .name = "I2C0",
1003 .parent = &fast_clk,
1004 .rate = 26000000, /* this varies! */
1005 .hw_ctrld = false,
1006 .reset = true,
1007 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1008 .res_mask = U300_SYSCON_RFR_I2C0_RESET_ENABLE,
1009 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
1010 .enable = syscon_clk_enable,
1011 .disable = syscon_clk_disable,
1012 .get_rate = clk_get_rate_i2s_i2c_spi,
1013 .lock = __SPIN_LOCK_UNLOCKED(i2c0_clk.lock),
1014};
1015
1016static struct clk i2c1_clk = {
1017 .name = "I2C1",
1018 .parent = &fast_clk,
1019 .rate = 26000000, /* this varies! */
1020 .hw_ctrld = false,
1021 .reset = true,
1022 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1023 .res_mask = U300_SYSCON_RFR_I2C1_RESET_ENABLE,
1024 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
1025 .enable = syscon_clk_enable,
1026 .disable = syscon_clk_disable,
1027 .get_rate = clk_get_rate_i2s_i2c_spi,
1028 .lock = __SPIN_LOCK_UNLOCKED(i2c1_clk.lock),
1029};
1030
1031/*
1032 * The SPI apb_pclk is hardwired to the same terminal as the
1033 * external SPI clock. Thus this will be referenced twice.
1034 */
1035static struct clk spi_clk = {
1036 .name = "SPI",
1037 .parent = &fast_clk,
1038 .rate = 26000000, /* this varies! */
1039 .hw_ctrld = false,
1040 .reset = true,
1041 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1042 .res_mask = U300_SYSCON_RFR_SPI_RESET_ENABLE,
1043 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
1044 .enable = syscon_clk_enable,
1045 .disable = syscon_clk_disable,
1046 .get_rate = clk_get_rate_i2s_i2c_spi,
1047 .lock = __SPIN_LOCK_UNLOCKED(spi_clk.lock),
1048};
1049
1050#ifdef CONFIG_MACH_U300_BS335
1051static struct clk uart1_pclk = {
1052 .name = "UART1_PCLK",
1053 .parent = &fast_clk,
1054 .hw_ctrld = false,
1055 .reset = true,
1056 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RFR,
1057 .res_mask = U300_SYSCON_RFR_UART1_RESET_ENABLE,
1058 .clk_val = U300_SYSCON_SBCER_UART1_CLK_EN,
1059 .enable = syscon_clk_enable,
1060 .disable = syscon_clk_disable,
1061 .lock = __SPIN_LOCK_UNLOCKED(uart1_pclk.lock),
1062};
1063
1064/* This one is hardwired to PLL13 */
1065static struct clk uart1_clk = {
1066 .name = "UART1_CLK",
1067 .rate = 13000000,
1068 .hw_ctrld = true,
1069 .lock = __SPIN_LOCK_UNLOCKED(uart1_clk.lock),
1070};
1071#endif
1072
1073
1074/*
1075 * Clocks on the SLOW bridge
1076 */
1077static struct clk slow_clk = {
1078 .name = "SLOW_BRIDGE",
1079 .parent = &amba_clk,
1080 .rate = 13000000,
1081 .hw_ctrld = true,
1082 .reset = true,
1083 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1084 .res_mask = U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN,
1085 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
1086 .enable = syscon_clk_enable,
1087 .disable = syscon_clk_disable,
1088 .lock = __SPIN_LOCK_UNLOCKED(slow_clk.lock),
1089};
1090
1091/* TODO: implement SYSCON clock? */
1092
1093static struct clk wdog_clk = {
1094 .name = "WDOG",
1095 .parent = &slow_clk,
1096 .hw_ctrld = false,
1097 .rate = 32768,
1098 .reset = false,
1099 /* This is always on, cannot be enabled/disabled or reset */
1100 .lock = __SPIN_LOCK_UNLOCKED(wdog_clk.lock),
1101};
1102
1103static struct clk uart0_pclk = {
1104 .name = "UART0_PCLK",
1105 .parent = &slow_clk,
1106 .hw_ctrld = false,
1107 .reset = true,
1108 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1109 .res_mask = U300_SYSCON_RSR_UART_RESET_EN,
1110 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
1111 .enable = syscon_clk_enable,
1112 .disable = syscon_clk_disable,
1113 .lock = __SPIN_LOCK_UNLOCKED(uart0_pclk.lock),
1114};
1115
1116/* This one is hardwired to PLL13 */
1117static struct clk uart0_clk = {
1118 .name = "UART0_CLK",
1119 .parent = &slow_clk,
1120 .rate = 13000000,
1121 .hw_ctrld = true,
1122 .lock = __SPIN_LOCK_UNLOCKED(uart0_clk.lock),
1123};
1124
1125static struct clk keypad_clk = {
1126 .name = "KEYPAD",
1127 .parent = &slow_clk,
1128 .rate = 32768,
1129 .hw_ctrld = false,
1130 .reset = true,
1131 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1132 .res_mask = U300_SYSCON_RSR_KEYPAD_RESET_EN,
1133 .clk_val = U300_SYSCON_SBCER_KEYPAD_CLK_EN,
1134 .enable = syscon_clk_enable,
1135 .disable = syscon_clk_disable,
1136 .lock = __SPIN_LOCK_UNLOCKED(keypad_clk.lock),
1137};
1138
1139static struct clk gpio_clk = {
1140 .name = "GPIO",
1141 .parent = &slow_clk,
1142 .rate = 13000000,
1143 .hw_ctrld = true,
1144 .reset = true,
1145 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1146 .res_mask = U300_SYSCON_RSR_GPIO_RESET_EN,
1147 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
1148 .enable = syscon_clk_enable,
1149 .disable = syscon_clk_disable,
1150 .lock = __SPIN_LOCK_UNLOCKED(gpio_clk.lock),
1151};
1152
1153static struct clk rtc_clk = {
1154 .name = "RTC",
1155 .parent = &slow_clk,
1156 .rate = 32768,
1157 .hw_ctrld = true,
1158 .reset = true,
1159 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1160 .res_mask = U300_SYSCON_RSR_RTC_RESET_EN,
1161 /* This clock is always on, cannot be enabled/disabled */
1162 .lock = __SPIN_LOCK_UNLOCKED(rtc_clk.lock),
1163};
1164
1165static struct clk bustr_clk = {
1166 .name = "BUSTR",
1167 .parent = &slow_clk,
1168 .rate = 13000000,
1169 .hw_ctrld = true,
1170 .reset = true,
1171 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1172 .res_mask = U300_SYSCON_RSR_BTR_RESET_EN,
1173 .clk_val = U300_SYSCON_SBCER_BTR_CLK_EN,
1174 .enable = syscon_clk_enable,
1175 .disable = syscon_clk_disable,
1176 .lock = __SPIN_LOCK_UNLOCKED(bustr_clk.lock),
1177};
1178
1179static struct clk evhist_clk = {
1180 .name = "EVHIST",
1181 .parent = &slow_clk,
1182 .rate = 13000000,
1183 .hw_ctrld = true,
1184 .reset = true,
1185 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1186 .res_mask = U300_SYSCON_RSR_EH_RESET_EN,
1187 .clk_val = U300_SYSCON_SBCER_EH_CLK_EN,
1188 .enable = syscon_clk_enable,
1189 .disable = syscon_clk_disable,
1190 .lock = __SPIN_LOCK_UNLOCKED(evhist_clk.lock),
1191};
1192
1193static struct clk timer_clk = {
1194 .name = "TIMER",
1195 .parent = &slow_clk,
1196 .rate = 13000000,
1197 .hw_ctrld = true,
1198 .reset = true,
1199 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1200 .res_mask = U300_SYSCON_RSR_ACC_TMR_RESET_EN,
1201 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
1202 .enable = syscon_clk_enable,
1203 .disable = syscon_clk_disable,
1204 .lock = __SPIN_LOCK_UNLOCKED(timer_clk.lock),
1205};
1206
1207/*
1208 * There is a binary divider in the hardware that divides
1209 * the 13MHz PLL by 13 down to 1 MHz.
1210 */
1211static struct clk app_timer_clk = {
1212 .name = "TIMER_APP",
1213 .parent = &slow_clk,
1214 .rate = 1000000,
1215 .hw_ctrld = true,
1216 .reset = true,
1217 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1218 .res_mask = U300_SYSCON_RSR_APP_TMR_RESET_EN,
1219 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
1220 .enable = syscon_clk_enable,
1221 .disable = syscon_clk_disable,
1222 .lock = __SPIN_LOCK_UNLOCKED(app_timer_clk.lock),
1223};
1224
1225#ifdef CONFIG_MACH_U300_BS335
1226static struct clk ppm_clk = {
1227 .name = "PPM",
1228 .parent = &slow_clk,
1229 .rate = 0, /* FIXME */
1230 .hw_ctrld = true, /* TODO: Look up if it is hw ctrld or not */
1231 .reset = true,
1232 .res_reg = U300_SYSCON_VBASE + U300_SYSCON_RSR,
1233 .res_mask = U300_SYSCON_RSR_PPM_RESET_EN,
1234 .clk_val = U300_SYSCON_SBCER_PPM_CLK_EN,
1235 .enable = syscon_clk_enable,
1236 .disable = syscon_clk_disable,
1237 .lock = __SPIN_LOCK_UNLOCKED(ppm_clk.lock),
1238};
1239#endif
1240
1241#define DEF_LOOKUP(devid, clkref) \
1242 { \
1243 .dev_id = devid, \
1244 .clk = clkref, \
1245 }
1246
1247#define DEF_LOOKUP_CON(devid, conid, clkref) \
1248 { \
1249 .dev_id = devid, \
1250 .con_id = conid, \
1251 .clk = clkref, \
1252 }
1253
1254/*
1255 * Here we only define clocks that are meaningful to
1256 * look up through clockdevice.
1257 */
1258static struct clk_lookup lookups[] = {
1259 /* Connected directly to the AMBA bus */
1260 DEF_LOOKUP("amba", &amba_clk),
1261 DEF_LOOKUP("cpu", &cpu_clk),
1262 DEF_LOOKUP("fsmc-nand", &nandif_clk),
1263 DEF_LOOKUP("semi", &semi_clk),
1264#ifdef CONFIG_MACH_U300_BS335
1265 DEF_LOOKUP("isp", &isp_clk),
1266 DEF_LOOKUP("cds", &cds_clk),
1267#endif
1268 DEF_LOOKUP("dma", &dma_clk),
1269 DEF_LOOKUP("msl", &aaif_clk),
1270 DEF_LOOKUP("apex", &apex_clk),
1271 DEF_LOOKUP("video_enc", &video_enc_clk),
1272 DEF_LOOKUP("xgam", &xgam_clk),
1273 DEF_LOOKUP("ahb", &ahb_clk),
1274 /* AHB bridge clocks */
1275 DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk),
1276 DEF_LOOKUP("intcon", &intcon_clk),
1277 DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk),
1278 DEF_LOOKUP("mspro", &mspro_clk),
1279 DEF_LOOKUP("pl172", &emif_clk),
1280 DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk),
1281 /* FAST bridge clocks */
1282 DEF_LOOKUP("fast", &fast_clk),
1283 DEF_LOOKUP("mmci", &mmcsd_clk),
1284 DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk),
1285 /*
1286 * The .0 and .1 identifiers on these comes from the platform device
1287 * .id field and are assigned when the platform devices are registered.
1288 */
1289 DEF_LOOKUP("i2s.0", &i2s0_clk),
1290 DEF_LOOKUP("i2s.1", &i2s1_clk),
1291 DEF_LOOKUP("stu300.0", &i2c0_clk),
1292 DEF_LOOKUP("stu300.1", &i2c1_clk),
1293 DEF_LOOKUP("pl022", &spi_clk),
1294 DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk),
1295#ifdef CONFIG_MACH_U300_BS335
1296 DEF_LOOKUP("uart1", &uart1_clk),
1297 DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk),
1298#endif
1299 /* SLOW bridge clocks */
1300 DEF_LOOKUP("slow", &slow_clk),
1301 DEF_LOOKUP("coh901327_wdog", &wdog_clk),
1302 DEF_LOOKUP("uart0", &uart0_clk),
1303 DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk),
1304 DEF_LOOKUP("apptimer", &app_timer_clk),
1305 DEF_LOOKUP("coh901461-keypad", &keypad_clk),
1306 DEF_LOOKUP("u300-gpio", &gpio_clk),
1307 DEF_LOOKUP("rtc-coh901331", &rtc_clk),
1308 DEF_LOOKUP("bustr", &bustr_clk),
1309 DEF_LOOKUP("evhist", &evhist_clk),
1310 DEF_LOOKUP("timer", &timer_clk),
1311#ifdef CONFIG_MACH_U300_BS335
1312 DEF_LOOKUP("ppm", &ppm_clk),
1313#endif
1314};
1315
1316static void __init clk_register(void)
1317{
1318 /* Register the lookups */
1319 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
1320}
1321
1322#if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1323/*
1324 * The following makes it possible to view the status (especially
1325 * reference count and reset status) for the clocks in the platform
1326 * by looking into the special file <debugfs>/u300_clocks
1327 */
1328
1329/* A list of all clocks in the platform */
1330static struct clk *clks[] = {
1331 /* Top node clock for the AMBA bus */
1332 &amba_clk,
1333 /* Connected directly to the AMBA bus */
1334 &cpu_clk,
1335 &nandif_clk,
1336 &semi_clk,
1337#ifdef CONFIG_MACH_U300_BS335
1338 &isp_clk,
1339 &cds_clk,
1340#endif
1341 &dma_clk,
1342 &aaif_clk,
1343 &apex_clk,
1344 &video_enc_clk,
1345 &xgam_clk,
1346 &ahb_clk,
1347
1348 /* AHB bridge clocks */
1349 &ahb_subsys_clk,
1350 &intcon_clk,
1351 &mspro_clk,
1352 &emif_clk,
1353 /* FAST bridge clocks */
1354 &fast_clk,
1355 &mmcsd_clk,
1356 &i2s0_clk,
1357 &i2s1_clk,
1358 &i2c0_clk,
1359 &i2c1_clk,
1360 &spi_clk,
1361#ifdef CONFIG_MACH_U300_BS335
1362 &uart1_clk,
1363 &uart1_pclk,
1364#endif
1365 /* SLOW bridge clocks */
1366 &slow_clk,
1367 &wdog_clk,
1368 &uart0_clk,
1369 &uart0_pclk,
1370 &app_timer_clk,
1371 &keypad_clk,
1372 &gpio_clk,
1373 &rtc_clk,
1374 &bustr_clk,
1375 &evhist_clk,
1376 &timer_clk,
1377#ifdef CONFIG_MACH_U300_BS335
1378 &ppm_clk,
1379#endif
1380};
1381
1382static int u300_clocks_show(struct seq_file *s, void *data)
1383{
1384 struct clk *clk;
1385 int i;
1386
1387 seq_printf(s, "CLOCK DEVICE RESET STATE\t" \
1388 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1389 seq_printf(s, "---------------------------------------------" \
1390 "-----------------------------------------\n");
1391 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1392 clk = clks[i];
1393 if (clk != ERR_PTR(-ENOENT)) {
1394 /* Format clock and device name nicely */
1395 char cdp[33];
1396 int chars;
1397
1398 chars = snprintf(&cdp[0], 17, "%s", clk->name);
1399 while (chars < 16) {
1400 cdp[chars] = ' ';
1401 chars++;
1402 }
1403 chars = snprintf(&cdp[16], 17, "%s", clk->dev ?
1404 dev_name(clk->dev) : "N/A");
1405 while (chars < 16) {
1406 cdp[chars+16] = ' ';
1407 chars++;
1408 }
1409 cdp[32] = '\0';
1410 if (clk->get_rate || clk->rate != 0)
1411 seq_printf(s,
1412 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1413 &cdp[0],
1414 clk->reset ?
1415 "ASSERTED" : "RELEASED",
1416 clk->usecount ? "ON" : "OFF",
1417 clk->usecount,
1418 clk->hw_ctrld ? "YES" : "NO ",
1419 clk_get_rate(clk));
1420 else
1421 seq_printf(s,
1422 "%s%s\t%s\t%d\t%s\t" \
1423 "(unknown rate)\n",
1424 &cdp[0],
1425 clk->reset ?
1426 "ASSERTED" : "RELEASED",
1427 clk->usecount ? "ON" : "OFF",
1428 clk->usecount,
1429 clk->hw_ctrld ? "YES" : "NO ");
1430 }
1431 }
1432 return 0;
1433}
1434
1435static int u300_clocks_open(struct inode *inode, struct file *file)
1436{
1437 return single_open(file, u300_clocks_show, NULL);
1438}
1439
1440static const struct file_operations u300_clocks_operations = {
1441 .open = u300_clocks_open,
1442 .read = seq_read,
1443 .llseek = seq_lseek,
1444 .release = single_release,
1445};
1446
1447static int __init init_clk_read_debugfs(void)
1448{
1449 /* Expose a simple debugfs interface to view all clocks */
1450 (void) debugfs_create_file("u300_clocks", S_IFREG | S_IRUGO,
1451 NULL, NULL,
1452 &u300_clocks_operations);
1453 return 0;
1454}
1455/*
1456 * This needs to come in after the core_initcall() for the
1457 * overall clocks, because debugfs is not available until
1458 * the subsystems come up.
1459 */
1460module_init(init_clk_read_debugfs);
1461#endif
1462
1463int __init u300_clock_init(void)
1464{
1465 u16 val;
1466
1467 /*
1468 * FIXME: shall all this powermanagement stuff really live here???
1469 */
1470
1471 /* Set system to run at PLL208, max performance, a known state. */
1472 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1473 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1474 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1475 /* Wait for the PLL208 to lock if not locked in yet */
1476 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1477 U300_SYSCON_CSR_PLL208_LOCK_IND));
1478
1479 /* Power management enable */
1480 val = readw(U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1481 val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
1482 writew(val, U300_SYSCON_VBASE + U300_SYSCON_PMCR);
1483
1484 clk_register();
1485
1486 /*
1487 * Some of these may be on when we boot the system so make sure they
1488 * are turned OFF.
1489 */
1490 syscon_block_reset_enable(&timer_clk);
1491 timer_clk.disable(&timer_clk);
1492
1493 /*
1494 * These shall be turned on by default when we boot the system
1495 * so make sure they are ON. (Adding CPU here is a bit too much.)
1496 * These clocks will be claimed by drivers later.
1497 */
1498 syscon_block_reset_disable(&semi_clk);
1499 syscon_block_reset_disable(&emif_clk);
1500 clk_enable(&semi_clk);
1501 clk_enable(&emif_clk);
1502
1503 return 0;
1504}
diff --git a/arch/arm/mach-u300/clock.h b/arch/arm/mach-u300/clock.h
deleted file mode 100644
index 4f50ca8f901e..000000000000
--- a/arch/arm/mach-u300/clock.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * arch/arm/mach-u300/include/mach/clock.h
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
7 * Copyright (C) 2007-2009 ST-Ericsson AB
8 * Adopted to ST-Ericsson U300 platforms by
9 * Jonas Aaberg <jonas.aberg@stericsson.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 */
16
17#ifndef __MACH_CLOCK_H
18#define __MACH_CLOCK_H
19
20#include <linux/clk.h>
21
22struct clk {
23 struct list_head node;
24 struct module *owner;
25 struct device *dev;
26 const char *name;
27 struct clk *parent;
28
29 spinlock_t lock;
30 unsigned long rate;
31 bool reset;
32 __u16 clk_val;
33 __s8 usecount;
34 void __iomem * res_reg;
35 __u16 res_mask;
36
37 bool hw_ctrld;
38
39 void (*recalc) (struct clk *);
40 int (*set_rate) (struct clk *, unsigned long);
41 unsigned long (*get_rate) (struct clk *);
42 unsigned long (*round_rate) (struct clk *, unsigned long);
43 void (*init) (struct clk *);
44 void (*enable) (struct clk *);
45 void (*disable) (struct clk *);
46};
47
48int u300_clock_init(void);
49
50#endif
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 33339745d432..03acf1883ec7 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -30,6 +30,7 @@
30#include <linux/pinctrl/consumer.h> 30#include <linux/pinctrl/consumer.h>
31#include <linux/pinctrl/pinconf-generic.h> 31#include <linux/pinctrl/pinconf-generic.h>
32#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
33#include <linux/platform_data/clk-u300.h>
33 34
34#include <asm/types.h> 35#include <asm/types.h>
35#include <asm/setup.h> 36#include <asm/setup.h>
@@ -44,7 +45,6 @@
44#include <mach/dma_channels.h> 45#include <mach/dma_channels.h>
45#include <mach/gpio-u300.h> 46#include <mach/gpio-u300.h>
46 47
47#include "clock.h"
48#include "spi.h" 48#include "spi.h"
49#include "i2c.h" 49#include "i2c.h"
50#include "u300-gpio.h" 50#include "u300-gpio.h"
@@ -1658,12 +1658,20 @@ void __init u300_init_irq(void)
1658 int i; 1658 int i;
1659 1659
1660 /* initialize clocking early, we want to clock the INTCON */ 1660 /* initialize clocking early, we want to clock the INTCON */
1661 u300_clock_init(); 1661 u300_clk_init(U300_SYSCON_VBASE);
1662
1663 /* Bootstrap EMIF and SEMI clocks */
1664 clk = clk_get_sys("pl172", NULL);
1665 BUG_ON(IS_ERR(clk));
1666 clk_prepare_enable(clk);
1667 clk = clk_get_sys("semi", NULL);
1668 BUG_ON(IS_ERR(clk));
1669 clk_prepare_enable(clk);
1662 1670
1663 /* Clock the interrupt controller */ 1671 /* Clock the interrupt controller */
1664 clk = clk_get_sys("intcon", NULL); 1672 clk = clk_get_sys("intcon", NULL);
1665 BUG_ON(IS_ERR(clk)); 1673 BUG_ON(IS_ERR(clk));
1666 clk_enable(clk); 1674 clk_prepare_enable(clk);
1667 1675
1668 for (i = 0; i < U300_VIC_IRQS_END; i++) 1676 for (i = 0; i < U300_VIC_IRQS_END; i++)
1669 set_bit(i, (unsigned long *) &mask[0]); 1677 set_bit(i, (unsigned long *) &mask[0]);
@@ -1811,13 +1819,6 @@ void __init u300_init_devices(void)
1811 /* Check what platform we run and print some status information */ 1819 /* Check what platform we run and print some status information */
1812 u300_init_check_chip(); 1820 u300_init_check_chip();
1813 1821
1814 /* Set system to run at PLL208, max performance, a known state. */
1815 val = readw(U300_SYSCON_VBASE + U300_SYSCON_CCR);
1816 val &= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK;
1817 writew(val, U300_SYSCON_VBASE + U300_SYSCON_CCR);
1818 /* Wait for the PLL208 to lock if not locked in yet */
1819 while (!(readw(U300_SYSCON_VBASE + U300_SYSCON_CSR) &
1820 U300_SYSCON_CSR_PLL208_LOCK_IND));
1821 /* Initialize SPI device with some board specifics */ 1822 /* Initialize SPI device with some board specifics */
1822 u300_spi_init(&pl022_device); 1823 u300_spi_init(&pl022_device);
1823 1824
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index bc1c7897e82d..56ac06d38ec1 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -354,7 +354,7 @@ static void __init u300_timer_init(void)
354 /* Clock the interrupt controller */ 354 /* Clock the interrupt controller */
355 clk = clk_get_sys("apptimer", NULL); 355 clk = clk_get_sys("apptimer", NULL);
356 BUG_ON(IS_ERR(clk)); 356 BUG_ON(IS_ERR(clk));
357 clk_enable(clk); 357 clk_prepare_enable(clk);
358 rate = clk_get_rate(clk); 358 rate = clk_get_rate(clk);
359 359
360 setup_sched_clock(u300_read_sched_clock, 32, rate); 360 setup_sched_clock(u300_read_sched_clock, 32, rate);
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 84461fa2a3ba..a310222951da 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -25,6 +25,7 @@
25#include <linux/mfd/tc3589x.h> 25#include <linux/mfd/tc3589x.h>
26#include <linux/mfd/tps6105x.h> 26#include <linux/mfd/tps6105x.h>
27#include <linux/mfd/abx500/ab8500-gpio.h> 27#include <linux/mfd/abx500/ab8500-gpio.h>
28#include <linux/mfd/abx500/ab8500-codec.h>
28#include <linux/leds-lp5521.h> 29#include <linux/leds-lp5521.h>
29#include <linux/input.h> 30#include <linux/input.h>
30#include <linux/smsc911x.h> 31#include <linux/smsc911x.h>
@@ -97,6 +98,18 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
97 0x7A, 0x00, 0x00}, 98 0x7A, 0x00, 0x00},
98}; 99};
99 100
101/* ab8500-codec */
102static struct ab8500_codec_platform_data ab8500_codec_pdata = {
103 .amics = {
104 .mic1_type = AMIC_TYPE_DIFFERENTIAL,
105 .mic2_type = AMIC_TYPE_DIFFERENTIAL,
106 .mic1a_micbias = AMIC_MICBIAS_VAMIC1,
107 .mic1b_micbias = AMIC_MICBIAS_VAMIC1,
108 .mic2_micbias = AMIC_MICBIAS_VAMIC2
109 },
110 .ear_cmv = EAR_CMV_0_95V
111};
112
100static struct gpio_keys_button snowball_key_array[] = { 113static struct gpio_keys_button snowball_key_array[] = {
101 { 114 {
102 .gpio = 32, 115 .gpio = 32,
@@ -195,6 +208,7 @@ static struct ab8500_platform_data ab8500_platdata = {
195 .regulator = ab8500_regulators, 208 .regulator = ab8500_regulators,
196 .num_regulator = ARRAY_SIZE(ab8500_regulators), 209 .num_regulator = ARRAY_SIZE(ab8500_regulators),
197 .gpio = &ab8500_gpio_pdata, 210 .gpio = &ab8500_gpio_pdata,
211 .codec = &ab8500_codec_pdata,
198}; 212};
199 213
200static struct resource ab8500_resources[] = { 214static struct resource ab8500_resources[] = {
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
index df8155b9d4d1..08740eed050c 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h
@@ -24,7 +24,7 @@
24#ifndef __PLAT_GPIO_CFG_H 24#ifndef __PLAT_GPIO_CFG_H
25#define __PLAT_GPIO_CFG_H __FILE__ 25#define __PLAT_GPIO_CFG_H __FILE__
26 26
27#include<linux/types.h> 27#include <linux/types.h>
28 28
29typedef unsigned int __bitwise__ samsung_gpio_pull_t; 29typedef unsigned int __bitwise__ samsung_gpio_pull_t;
30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; 30typedef unsigned int __bitwise__ s5p_gpio_drvstr_t;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 07:54:46 -0500