15 files changed, 242 insertions, 59 deletions

diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a2200c77bf70..4b89fae14a5a 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -279,6 +279,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
         clk_register_clkdev(clk[dummy], NULL, "imx-keypad");
         clk_register_clkdev(clk[tve_gate], NULL, "imx-tve.0");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx-tve.0");
+        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
 
         /* Set SDHC parents to be PLL2 */
         clk_set_parent(clk[esdhc_a_sel], clk[pll2_sw]);
@@ -336,7 +337,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
         clk_register_clkdev(clk[mx51_mipi], "mipi_hsp", NULL);
         clk_register_clkdev(clk[vpu_gate], NULL, "imx51-vpu.0");
         clk_register_clkdev(clk[fec_gate], NULL, "imx27-fec.0");
-        clk_register_clkdev(clk[gpc_dvfs], "gpc_dvfs", NULL);
         clk_register_clkdev(clk[ipu_gate], "bus", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di0_gate], "di0", "imx51-ipu");
         clk_register_clkdev(clk[ipu_di1_gate], "di1", "imx51-ipu");
diff --git a/arch/arm/mach-imx/imx53-dt.c b/arch/arm/mach-imx/imx53-dt.c
index eb04b6248e48..481c3e96ad7f 100644
--- a/arch/arm/mach-imx/imx53-dt.c
+++ b/arch/arm/mach-imx/imx53-dt.c
@@ -147,6 +147,7 @@ DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
         .handle_irq     = imx53_handle_irq,
         .timer          = &imx53_timer,
         .init_machine   = imx53_dt_init,
+        .init_late      = imx53_init_late,
         .dt_compat      = imx53_dt_board_compat,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index b47e98b7d539..d4ca2c470142 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,7 +12,9 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/cpuidle.h>
 #include <linux/delay.h>
+#include <linux/export.h>
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irq.h>
@@ -24,6 +26,7 @@
 #include <linux/pinctrl/machine.h>
 #include <linux/phy.h>
 #include <linux/micrel_phy.h>
+#include <asm/cpuidle.h>
 #include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
@@ -31,8 +34,10 @@
 #include <asm/mach/time.h>
 #include <asm/system_misc.h>
 #include <mach/common.h>
+#include <mach/cpuidle.h>
 #include <mach/hardware.h>
 
+
 void imx6q_restart(char mode, const char *cmd)
 {
         struct device_node *np;
@@ -129,6 +134,19 @@ static void __init imx6q_init_machine(void)
         imx6q_pm_init();
 }
 
+static struct cpuidle_driver imx6q_cpuidle_driver = {
+        .name                   = "imx6q_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .states[0]              = ARM_CPUIDLE_WFI_STATE,
+        .state_count            = 1,
+};
+
+static void __init imx6q_init_late(void)
+{
+        imx_cpuidle_init(&imx6q_cpuidle_driver);
+}
+
 static void __init imx6q_map_io(void)
 {
         imx_lluart_map_io();
@@ -186,6 +204,7 @@ DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad (Device Tree)")
         .handle_irq     = imx6q_handle_irq,
         .timer          = &imx6q_timer,
         .init_machine   = imx6q_init_machine,
+        .init_late      = imx6q_init_late,
         .dt_compat      = imx6q_dt_compat,
         .restart        = imx6q_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_ard.c b/arch/arm/mach-imx/mach-mx53_ard.c
index 05641980dc5e..f1e83d6d2dfc 100644
--- a/arch/arm/mach-imx/mach-mx53_ard.c
+++ b/arch/arm/mach-imx/mach-mx53_ard.c
@@ -266,5 +266,6 @@ MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_ard_timer,
         .init_machine = mx53_ard_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_evk.c b/arch/arm/mach-imx/mach-mx53_evk.c
index 5a72188b9cdb..8387496ef5ec 100644
--- a/arch/arm/mach-imx/mach-mx53_evk.c
+++ b/arch/arm/mach-imx/mach-mx53_evk.c
@@ -174,5 +174,6 @@ MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_evk_timer,
         .init_machine = mx53_evk_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_loco.c b/arch/arm/mach-imx/mach-mx53_loco.c
index 37f67cac15a4..e266f3f0f080 100644
--- a/arch/arm/mach-imx/mach-mx53_loco.c
+++ b/arch/arm/mach-imx/mach-mx53_loco.c
@@ -316,5 +316,6 @@ MACHINE_START(MX53_LOCO, "Freescale MX53 LOCO Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_loco_timer,
         .init_machine = mx53_loco_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx53_smd.c b/arch/arm/mach-imx/mach-mx53_smd.c
index 8e972c5c3e13..4f4c1b93ea66 100644
--- a/arch/arm/mach-imx/mach-mx53_smd.c
+++ b/arch/arm/mach-imx/mach-mx53_smd.c
@@ -163,5 +163,6 @@ MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board")
         .handle_irq = imx53_handle_irq,
         .timer = &mx53_smd_timer,
         .init_machine = mx53_smd_board_init,
+        .init_late      = imx53_init_late,
         .restart        = mxc_restart,
 MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 1d003053d562..f19d604e1b2a 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -16,7 +16,6 @@
 #include <linux/clk.h>
 #include <linux/pinctrl/machine.h>
 
-#include <asm/system_misc.h>
 #include <asm/mach/map.h>
 
 #include <mach/hardware.h>
@@ -24,24 +23,6 @@
 #include <mach/devices-common.h>
 #include <mach/iomux-v3.h>
 
-static struct clk *gpc_dvfs_clk;
-
-static void imx5_idle(void)
-{
-        /* gpc clock is needed for SRPG */
-        if (gpc_dvfs_clk == NULL) {
-                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
-                if (IS_ERR(gpc_dvfs_clk))
-                        return;
-                clk_prepare(gpc_dvfs_clk);
-        }
-        clk_enable(gpc_dvfs_clk);
-        mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-        if (!tzic_enable_wake())
-                cpu_do_idle();
-        clk_disable(gpc_dvfs_clk);
-}
-
 /*
  * Define the MX50 memory map.
  */
@@ -105,7 +86,6 @@ void __init imx51_init_early(void)
         mxc_set_cpu_type(MXC_CPU_MX51);
         mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
         mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
-        arm_pm_idle = imx5_idle;
 }
 
 void __init imx53_init_early(void)
@@ -243,4 +223,10 @@ void __init imx53_soc_init(void)
 void __init imx51_init_late(void)
 {
         mx51_neon_fixup();
+        imx51_pm_init();
+}
+
+void __init imx53_init_late(void)
+{
+        imx53_pm_init();
 }
diff --git a/arch/arm/mach-imx/pm-imx5.c b/arch/arm/mach-imx/pm-imx5.c
index e26a9cb05ed8..19621ed1ffa5 100644
--- a/arch/arm/mach-imx/pm-imx5.c
+++ b/arch/arm/mach-imx/pm-imx5.c
@@ -12,19 +12,30 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/err.h>
+#include <linux/export.h>
 #include <asm/cacheflush.h>
+#include <asm/system_misc.h>
 #include <asm/tlbflush.h>
 #include <mach/common.h>
+#include <mach/cpuidle.h>
 #include <mach/hardware.h>
 #include "crm-regs-imx5.h"
 
-static struct clk *gpc_dvfs_clk;
+/*
+ * The WAIT_UNCLOCKED_POWER_OFF state only requires <= 500ns to exit.
+ * This is also the lowest power state possible without affecting
+ * non-cpu parts of the system.  For these reasons, imx5 should default
+ * to always using this state for cpu idling.  The PM_SUSPEND_STANDBY also
+ * uses this state and needs to take no action when registers remain confgiured
+ * for this state.
+ */
+#define IMX5_DEFAULT_CPU_IDLE_STATE WAIT_UNCLOCKED_POWER_OFF
 
 /*
  * set cpu low power mode before WFI instruction. This function is called
  * mx5 because it can be used for mx50, mx51, and mx53.
  */
-void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
+static void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
 {
         u32 plat_lpc, arm_srpgcr, ccm_clpcr;
         u32 empgc0, empgc1;
@@ -87,11 +98,6 @@ void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode)
         }
 }
 
-static int mx5_suspend_prepare(void)
-{
-        return clk_prepare_enable(gpc_dvfs_clk);
-}
-
 static int mx5_suspend_enter(suspend_state_t state)
 {
         switch (state) {
@@ -99,7 +105,7 @@ static int mx5_suspend_enter(suspend_state_t state)
                 mx5_cpu_lp_set(STOP_POWER_OFF);
                 break;
         case PM_SUSPEND_STANDBY:
-                mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+                /* DEFAULT_IDLE_STATE already configured */
                 break;
         default:
                 return -EINVAL;
@@ -114,12 +120,10 @@ static int mx5_suspend_enter(suspend_state_t state)
                 __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
         }
         cpu_do_idle();
-        return 0;
-}
 
-static void mx5_suspend_finish(void)
-{
-        clk_disable_unprepare(gpc_dvfs_clk);
+        /* return registers to default idle state */
+        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
+        return 0;
 }
 
 static int mx5_pm_valid(suspend_state_t state)
@@ -129,25 +133,80 @@ static int mx5_pm_valid(suspend_state_t state)
 
 static const struct platform_suspend_ops mx5_suspend_ops = {
         .valid = mx5_pm_valid,
-        .prepare = mx5_suspend_prepare,
         .enter = mx5_suspend_enter,
-        .finish = mx5_suspend_finish,
 };
 
-static int __init mx5_pm_init(void)
+static inline int imx5_cpu_do_idle(void)
+{
+        int ret = tzic_enable_wake();
+
+        if (likely(!ret))
+                cpu_do_idle();
+
+        return ret;
+}
+
+static void imx5_pm_idle(void)
+{
+        imx5_cpu_do_idle();
+}
+
+static int imx5_cpuidle_enter(struct cpuidle_device *dev,
+                                struct cpuidle_driver *drv, int idx)
+{
+        int ret;
+
+        ret = imx5_cpu_do_idle();
+        if (ret < 0)
+                return ret;
+
+        return idx;
+}
+
+static struct cpuidle_driver imx5_cpuidle_driver = {
+        .name                   = "imx5_cpuidle",
+        .owner                  = THIS_MODULE,
+        .en_core_tk_irqen       = 1,
+        .states[0]      = {
+                .enter                  = imx5_cpuidle_enter,
+                .exit_latency           = 2,
+                .target_residency       = 1,
+                .flags                  = CPUIDLE_FLAG_TIME_VALID,
+                .name                   = "IMX5 SRPG",
+                .desc                   = "CPU state retained,powered off",
+        },
+        .state_count            = 1,
+};
+
+static int __init imx5_pm_common_init(void)
 {
-        if (!cpu_is_mx51() && !cpu_is_mx53())
-                return 0;
+        int ret;
+        struct clk *gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
 
-        if (gpc_dvfs_clk == NULL)
-                gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+        if (IS_ERR(gpc_dvfs_clk))
+                return PTR_ERR(gpc_dvfs_clk);
 
-        if (!IS_ERR(gpc_dvfs_clk)) {
-                if (cpu_is_mx51())
-                        suspend_set_ops(&mx5_suspend_ops);
-        } else
-                return -EPERM;
+        ret = clk_prepare_enable(gpc_dvfs_clk);
+        if (ret)
+                return ret;
 
+        arm_pm_idle = imx5_pm_idle;
+
+        /* Set the registers to the default cpu idle state. */
+        mx5_cpu_lp_set(IMX5_DEFAULT_CPU_IDLE_STATE);
+
+        imx_cpuidle_init(&imx5_cpuidle_driver);
         return 0;
 }
-device_initcall(mx5_pm_init);
+
+void __init imx51_pm_init(void)
+{
+        int ret = imx5_pm_common_init();
+        if (!ret)
+                suspend_set_ops(&mx5_suspend_ops);
+}
+
+void __init imx53_pm_init(void)
+{
+        imx5_pm_common_init();
+}
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index e81290c27c65..63b064b5c1d5 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
 obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
 ifdef CONFIG_SND_IMX_SOC
 obj-y += ssi-fiq.o
 obj-y += ssi-fiq-ksym.o
diff --git a/arch/arm/plat-mxc/cpuidle.c b/arch/arm/plat-mxc/cpuidle.c
new file mode 100644
index 000000000000..d4cb511a44a8
--- /dev/null
+++ b/arch/arm/plat-mxc/cpuidle.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+#include <linux/err.h>
+#include <linux/hrtimer.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+
+static struct cpuidle_device __percpu * imx_cpuidle_devices;
+
+static void __init imx_cpuidle_devices_uninit(void)
+{
+        int cpu_id;
+        struct cpuidle_device *dev;
+
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                cpuidle_unregister_device(dev);
+        }
+
+        free_percpu(imx_cpuidle_devices);
+}
+
+int __init imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        struct cpuidle_device *dev;
+        int cpu_id, ret;
+
+        if (drv->state_count > CPUIDLE_STATE_MAX) {
+                pr_err("%s: state_count exceeds maximum\n", __func__);
+                return -EINVAL;
+        }
+
+        ret = cpuidle_register_driver(drv);
+        if (ret) {
+                pr_err("%s: Failed to register cpuidle driver with error: %d\n",
+                         __func__, ret);
+                return ret;
+        }
+
+        imx_cpuidle_devices = alloc_percpu(struct cpuidle_device);
+        if (imx_cpuidle_devices == NULL) {
+                ret = -ENOMEM;
+                goto unregister_drv;
+        }
+
+        /* initialize state data for each cpuidle_device */
+        for_each_possible_cpu(cpu_id) {
+                dev = per_cpu_ptr(imx_cpuidle_devices, cpu_id);
+                dev->cpu = cpu_id;
+                dev->state_count = drv->state_count;
+
+                ret = cpuidle_register_device(dev);
+                if (ret) {
+                        pr_err("%s: Failed to register cpu %u, error: %d\n",
+                                __func__, cpu_id, ret);
+                        goto uninit;
+                }
+        }
+
+        return 0;
+
+uninit:
+        imx_cpuidle_devices_uninit();
+
+unregister_drv:
+        cpuidle_unregister_driver(drv);
+        return ret;
+}
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index e429ca1b814a..7ca15044154f 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -54,6 +54,7 @@ extern void imx50_soc_init(void);
 extern void imx51_soc_init(void);
 extern void imx53_soc_init(void);
 extern void imx51_init_late(void);
+extern void imx53_init_late(void);
 extern void epit_timer_init(void __iomem *base, int irq);
 extern void mxc_timer_init(void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
@@ -95,7 +96,6 @@ enum mx3_cpu_pwr_mode {
 };
 
 extern void mx3_cpu_lp_set(enum mx3_cpu_pwr_mode mode);
-extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
 extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
@@ -146,8 +146,12 @@ extern void imx6q_clock_map_io(void);
 
 #ifdef CONFIG_PM
 extern void imx6q_pm_init(void);
+extern void imx51_pm_init(void);
+extern void imx53_pm_init(void);
 #else
 static inline void imx6q_pm_init(void) {}
+static inline void imx51_pm_init(void) {}
+static inline void imx53_pm_init(void) {}
 #endif
 
 #ifdef CONFIG_NEON
diff --git a/arch/arm/plat-mxc/include/mach/cpuidle.h b/arch/arm/plat-mxc/include/mach/cpuidle.h
new file mode 100644
index 000000000000..bc932d1af372
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/cpuidle.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/cpuidle.h>
+
+#ifdef CONFIG_CPU_IDLE
+extern int imx_cpuidle_init(struct cpuidle_driver *drv);
+#else
+static inline int imx_cpuidle_init(struct cpuidle_driver *drv)
+{
+        return -ENODEV;
+}
+#endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 0630513554de..071afd0b9283 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -50,7 +50,7 @@
  *      IO      0x00200000+0x100000     ->      0xf4000000+0x100000
  * mx21:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xdf000000+0x004000     ->      0xf5f00000+0x004000
  * mx25:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
@@ -58,47 +58,50 @@
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
  * mx27:
  *      AIPI    0x10000000+0x100000     ->      0xf4400000+0x100000
- *      SAHB1   0x80000000+0x100000     ->      0xf4000000+0x100000
+ *      SAHB1   0x80000000+0x100000     ->      0xf5000000+0x100000
  *      X_MEMC  0xd8000000+0x100000     ->      0xf5c00000+0x100000
  * mx31:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx35:
  *      AIPS1   0x43f00000+0x100000     ->      0xf5300000+0x100000
  *      AIPS2   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AVIC    0x68000000+0x100000     ->      0xf5800000+0x100000
- *      X_MEMC  0xb8000000+0x010000     ->      0xf4c00000+0x010000
+ *      X_MEMC  0xb8000000+0x010000     ->      0xf5c00000+0x010000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  * mx50:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
- *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
+ *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx51:
- *      TZIC    0xe0000000+0x004000     ->      0xf5000000+0x004000
+ *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
  *      IRAM    0x1ffe0000+0x020000     ->      0xf4fe0000+0x020000
+ *      DEBUG   0x60000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x70000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x73f00000+0x100000     ->      0xf5700000+0x100000
- *      AIPS2   0x83f00000+0x100000     ->      0xf4300000+0x100000
+ *      AIPS2   0x83f00000+0x100000     ->      0xf5300000+0x100000
  * mx53:
  *      TZIC    0x0fffc000+0x004000     ->      0xf4bfc000+0x004000
+ *      DEBUG   0x40000000+0x100000     ->      0xf5000000+0x100000
  *      SPBA0   0x50000000+0x100000     ->      0xf5400000+0x100000
  *      AIPS1   0x53f00000+0x100000     ->      0xf5700000+0x100000
  *      AIPS2   0x63f00000+0x100000     ->      0xf5300000+0x100000
  * mx6q:
- *      SCU     0x00a00000+0x001000     ->      0xf4000000+0x001000
+ *      SCU     0x00a00000+0x004000     ->      0xf4000000+0x004000
  *      CCM     0x020c4000+0x004000     ->      0xf42c4000+0x004000
- *      ANATOP  0x020c8000+0x001000     ->      0xf42c8000+0x001000
+ *      ANATOP  0x020c8000+0x004000     ->      0xf42c8000+0x004000
  *      UART4   0x021f0000+0x004000     ->      0xf42f0000+0x004000
  */
 #define IMX_IO_P2V(x)   (                                               \
-                        0xf4000000 +                                    \
+                        (((x) & 0x80000000) >> 7) |                     \
+                        (0xf4000000 +                                   \
                         (((x) & 0x50000000) >> 6) +                     \
                         (((x) & 0x0b000000) >> 4) +                     \
-                        (((x) & 0x000fffff)))
+                        (((x) & 0x000fffff))))
 
 #define IMX_IO_ADDRESS(x)       IOMEM(IMX_IO_P2V(x))
 
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 98308ec1f321..a45dbea5e176 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -190,6 +190,10 @@ void __init tzic_init_irq(void __iomem *irqbase)
  * tzic_enable_wake() - enable wakeup interrupt
  *
  * @return                      0 if successful; non-zero otherwise
+ *
+ * This function provides an interrupt synchronization point that is required
+ * by tzic enabled platforms before entering imx specific low power modes (ie,
+ * those low power modes beyond the WAIT_CLOCKED basic ARM WFI only mode).
  */
 int tzic_enable_wake(void)
 {