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-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi119
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi106
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts35
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts135
-rw-r--r--arch/arm/boot/dts/imx51.dtsi246
-rw-r--r--arch/arm/boot/dts/imx53-ard.dts113
-rw-r--r--arch/arm/boot/dts/imx53-evk.dts120
-rw-r--r--arch/arm/boot/dts/imx53-qsb.dts125
-rw-r--r--arch/arm/boot/dts/imx53-smd.dts169
-rw-r--r--arch/arm/boot/dts/imx53.dtsi301
-rw-r--r--arch/arm/boot/dts/msm8660-surf.dts24
-rw-r--r--arch/arm/boot/dts/usb_a9g20.dts30
-rw-r--r--arch/arm/common/Kconfig1
-rw-r--r--arch/arm/common/gic.c188
-rw-r--r--arch/arm/include/asm/hardware/gic.h10
-rw-r--r--arch/arm/mach-at91/Kconfig11
-rw-r--r--arch/arm/mach-at91/Makefile3
-rw-r--r--arch/arm/mach-at91/Makefile.boot2
-rw-r--r--arch/arm/mach-at91/at91sam9260.c8
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c6
-rw-r--r--arch/arm/mach-at91/board-dt.c123
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c58
-rw-r--r--arch/arm/mach-mx5/Kconfig21
-rw-r--r--arch/arm/mach-mx5/Makefile3
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c12
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c9
-rw-r--r--arch/arm/mach-mx5/board-mx53_smd.c9
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c39
-rw-r--r--arch/arm/mach-mx5/imx51-dt.c116
-rw-r--r--arch/arm/mach-mx5/imx53-dt.c126
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h7
33 files changed, 2209 insertions, 84 deletions
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
new file mode 100644
index 000000000000..aeef04269cf8
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -0,0 +1,119 @@
1/*
2 * at91sam9g20.dtsi - Device Tree Include file for AT91SAM9G20 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9G20 family SoC";
15 compatible = "atmel,at91sam9g20";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
24 serial5 = &usart4;
25 serial6 = &usart5;
26 };
27 cpus {
28 cpu@0 {
29 compatible = "arm,arm926ejs";
30 };
31 };
32
33 memory@20000000 {
34 reg = <0x20000000 0x08000000>;
35 };
36
37 ahb {
38 compatible = "simple-bus";
39 #address-cells = <1>;
40 #size-cells = <1>;
41 ranges;
42
43 apb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 aic: interrupt-controller@fffff000 {
50 #interrupt-cells = <1>;
51 compatible = "atmel,at91rm9200-aic";
52 interrupt-controller;
53 interrupt-parent;
54 reg = <0xfffff000 0x200>;
55 };
56
57 dbgu: serial@fffff200 {
58 compatible = "atmel,at91sam9260-usart";
59 reg = <0xfffff200 0x200>;
60 interrupts = <1>;
61 status = "disabled";
62 };
63
64 usart0: serial@fffb0000 {
65 compatible = "atmel,at91sam9260-usart";
66 reg = <0xfffb0000 0x200>;
67 interrupts = <6>;
68 atmel,use-dma-rx;
69 atmel,use-dma-tx;
70 status = "disabled";
71 };
72
73 usart1: serial@fffb4000 {
74 compatible = "atmel,at91sam9260-usart";
75 reg = <0xfffb4000 0x200>;
76 interrupts = <7>;
77 atmel,use-dma-rx;
78 atmel,use-dma-tx;
79 status = "disabled";
80 };
81
82 usart2: serial@fffb8000 {
83 compatible = "atmel,at91sam9260-usart";
84 reg = <0xfffb8000 0x200>;
85 interrupts = <8>;
86 atmel,use-dma-rx;
87 atmel,use-dma-tx;
88 status = "disabled";
89 };
90
91 usart3: serial@fffd0000 {
92 compatible = "atmel,at91sam9260-usart";
93 reg = <0xfffd0000 0x200>;
94 interrupts = <23>;
95 atmel,use-dma-rx;
96 atmel,use-dma-tx;
97 status = "disabled";
98 };
99
100 usart4: serial@fffd4000 {
101 compatible = "atmel,at91sam9260-usart";
102 reg = <0xfffd4000 0x200>;
103 interrupts = <24>;
104 atmel,use-dma-rx;
105 atmel,use-dma-tx;
106 status = "disabled";
107 };
108
109 usart5: serial@fffd8000 {
110 compatible = "atmel,at91sam9260-usart";
111 reg = <0xfffd8000 0x200>;
112 interrupts = <25>;
113 atmel,use-dma-rx;
114 atmel,use-dma-tx;
115 status = "disabled";
116 };
117 };
118 };
119};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
new file mode 100644
index 000000000000..db6a45202f26
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -0,0 +1,106 @@
1/*
2 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
3 * applies to AT91SAM9G45, AT91SAM9M10,
4 * AT91SAM9G46, AT91SAM9M11 SoC
5 *
6 * Copyright (C) 2011 Atmel,
7 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
8 *
9 * Licensed under GPLv2 or later.
10 */
11
12/include/ "skeleton.dtsi"
13
14/ {
15 model = "Atmel AT91SAM9G45 family SoC";
16 compatible = "atmel,at91sam9g45";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 serial4 = &usart3;
25 };
26 cpus {
27 cpu@0 {
28 compatible = "arm,arm926ejs";
29 };
30 };
31
32 memory@70000000 {
33 reg = <0x70000000 0x10000000>;
34 };
35
36 ahb {
37 compatible = "simple-bus";
38 #address-cells = <1>;
39 #size-cells = <1>;
40 ranges;
41
42 apb {
43 compatible = "simple-bus";
44 #address-cells = <1>;
45 #size-cells = <1>;
46 ranges;
47
48 aic: interrupt-controller@fffff000 {
49 #interrupt-cells = <1>;
50 compatible = "atmel,at91rm9200-aic";
51 interrupt-controller;
52 interrupt-parent;
53 reg = <0xfffff000 0x200>;
54 };
55
56 dma: dma-controller@ffffec00 {
57 compatible = "atmel,at91sam9g45-dma";
58 reg = <0xffffec00 0x200>;
59 interrupts = <21>;
60 };
61
62 dbgu: serial@ffffee00 {
63 compatible = "atmel,at91sam9260-usart";
64 reg = <0xffffee00 0x200>;
65 interrupts = <1>;
66 status = "disabled";
67 };
68
69 usart0: serial@fff8c000 {
70 compatible = "atmel,at91sam9260-usart";
71 reg = <0xfff8c000 0x200>;
72 interrupts = <7>;
73 atmel,use-dma-rx;
74 atmel,use-dma-tx;
75 status = "disabled";
76 };
77
78 usart1: serial@fff90000 {
79 compatible = "atmel,at91sam9260-usart";
80 reg = <0xfff90000 0x200>;
81 interrupts = <8>;
82 atmel,use-dma-rx;
83 atmel,use-dma-tx;
84 status = "disabled";
85 };
86
87 usart2: serial@fff94000 {
88 compatible = "atmel,at91sam9260-usart";
89 reg = <0xfff94000 0x200>;
90 interrupts = <9>;
91 atmel,use-dma-rx;
92 atmel,use-dma-tx;
93 status = "disabled";
94 };
95
96 usart3: serial@fff98000 {
97 compatible = "atmel,at91sam9260-usart";
98 reg = <0xfff98000 0x200>;
99 interrupts = <10>;
100 atmel,use-dma-rx;
101 atmel,use-dma-tx;
102 status = "disabled";
103 };
104 };
105 };
106};
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
new file mode 100644
index 000000000000..85b34f59cd82
--- /dev/null
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -0,0 +1,35 @@
1/*
2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * Licensed under GPLv2 or later.
8 */
9/dts-v1/;
10/include/ "at91sam9g45.dtsi"
11
12/ {
13 model = "Atmel AT91SAM9M10G45-EK";
14 compatible = "atmel,at91sam9m10g45ek", "atmel,at91sam9g45", "atmel,at91sam9";
15
16 chosen {
17 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:4M(bootstrap/uboot/kernel)ro,60M(rootfs),-(data) root=/dev/mtdblock1 rw rootfstype=jffs2";
18 };
19
20 memory@70000000 {
21 reg = <0x70000000 0x4000000>;
22 };
23
24 ahb {
25 apb {
26 dbgu: serial@ffffee00 {
27 status = "okay";
28 };
29
30 usart1: serial@fff90000 {
31 status = "okay";
32 };
33 };
34 };
35};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
new file mode 100644
index 000000000000..f8766af11215
--- /dev/null
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -0,0 +1,135 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx51.dtsi"
15
16/ {
17 model = "Freescale i.MX51 Babbage Board";
18 compatible = "fsl,imx51-babbage", "fsl,imx51";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x90000000 0x20000000>;
26 };
27
28 soc {
29 aips@70000000 { /* aips-1 */
30 spba@70000000 {
31 esdhc@70004000 { /* ESDHC1 */
32 fsl,cd-internal;
33 fsl,wp-internal;
34 status = "okay";
35 };
36
37 esdhc@70008000 { /* ESDHC2 */
38 cd-gpios = <&gpio0 6 0>; /* GPIO1_6 */
39 wp-gpios = <&gpio0 5 0>; /* GPIO1_5 */
40 status = "okay";
41 };
42
43 uart2: uart@7000c000 { /* UART3 */
44 fsl,uart-has-rtscts;
45 status = "okay";
46 };
47
48 ecspi@70010000 { /* ECSPI1 */
49 fsl,spi-num-chipselects = <2>;
50 cs-gpios = <&gpio3 24 0>, /* GPIO4_24 */
51 <&gpio3 25 0>; /* GPIO4_25 */
52 status = "okay";
53
54 pmic: mc13892@0 {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 compatible = "fsl,mc13892";
58 spi-max-frequency = <6000000>;
59 reg = <0>;
60 mc13xxx-irq-gpios = <&gpio0 8 0>; /* GPIO1_8 */
61 fsl,mc13xxx-uses-regulator;
62 };
63
64 flash: at45db321d@1 {
65 #address-cells = <1>;
66 #size-cells = <1>;
67 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
68 spi-max-frequency = <25000000>;
69 reg = <1>;
70
71 partition@0 {
72 label = "U-Boot";
73 reg = <0x0 0x40000>;
74 read-only;
75 };
76
77 partition@40000 {
78 label = "Kernel";
79 reg = <0x40000 0x3c0000>;
80 };
81 };
82 };
83 };
84
85 wdog@73f98000 { /* WDOG1 */
86 status = "okay";
87 };
88
89 iomuxc@73fa8000 {
90 compatible = "fsl,imx51-iomuxc-babbage";
91 reg = <0x73fa8000 0x4000>;
92 };
93
94 uart0: uart@73fbc000 {
95 fsl,uart-has-rtscts;
96 status = "okay";
97 };
98
99 uart1: uart@73fc0000 {
100 status = "okay";
101 };
102 };
103
104 aips@80000000 { /* aips-2 */
105 sdma@83fb0000 {
106 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
107 };
108
109 i2c@83fc4000 { /* I2C2 */
110 status = "okay";
111
112 codec: sgtl5000@0a {
113 compatible = "fsl,sgtl5000";
114 reg = <0x0a>;
115 };
116 };
117
118 fec@83fec000 {
119 phy-mode = "mii";
120 status = "okay";
121 };
122 };
123 };
124
125 gpio-keys {
126 compatible = "gpio-keys";
127
128 power {
129 label = "Power Button";
130 gpios = <&gpio1 21 0>;
131 linux,code = <116>; /* KEY_POWER */
132 gpio-key,wakeup;
133 };
134 };
135};
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
new file mode 100644
index 000000000000..327ab8e3a4c8
--- /dev/null
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -0,0 +1,246 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 };
21
22 tzic: tz-interrupt-controller@e0000000 {
23 compatible = "fsl,imx51-tzic", "fsl,tzic";
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 reg = <0xe0000000 0x4000>;
27 };
28
29 clocks {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 ckil {
34 compatible = "fsl,imx-ckil", "fixed-clock";
35 clock-frequency = <32768>;
36 };
37
38 ckih1 {
39 compatible = "fsl,imx-ckih1", "fixed-clock";
40 clock-frequency = <22579200>;
41 };
42
43 ckih2 {
44 compatible = "fsl,imx-ckih2", "fixed-clock";
45 clock-frequency = <0>;
46 };
47
48 osc {
49 compatible = "fsl,imx-osc", "fixed-clock";
50 clock-frequency = <24000000>;
51 };
52 };
53
54 soc {
55 #address-cells = <1>;
56 #size-cells = <1>;
57 compatible = "simple-bus";
58 interrupt-parent = <&tzic>;
59 ranges;
60
61 aips@70000000 { /* AIPS1 */
62 compatible = "fsl,aips-bus", "simple-bus";
63 #address-cells = <1>;
64 #size-cells = <1>;
65 reg = <0x70000000 0x10000000>;
66 ranges;
67
68 spba@70000000 {
69 compatible = "fsl,spba-bus", "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 reg = <0x70000000 0x40000>;
73 ranges;
74
75 esdhc@70004000 { /* ESDHC1 */
76 compatible = "fsl,imx51-esdhc";
77 reg = <0x70004000 0x4000>;
78 interrupts = <1>;
79 status = "disabled";
80 };
81
82 esdhc@70008000 { /* ESDHC2 */
83 compatible = "fsl,imx51-esdhc";
84 reg = <0x70008000 0x4000>;
85 interrupts = <2>;
86 status = "disabled";
87 };
88
89 uart2: uart@7000c000 { /* UART3 */
90 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
91 reg = <0x7000c000 0x4000>;
92 interrupts = <33>;
93 status = "disabled";
94 };
95
96 ecspi@70010000 { /* ECSPI1 */
97 #address-cells = <1>;
98 #size-cells = <0>;
99 compatible = "fsl,imx51-ecspi";
100 reg = <0x70010000 0x4000>;
101 interrupts = <36>;
102 status = "disabled";
103 };
104
105 esdhc@70020000 { /* ESDHC3 */
106 compatible = "fsl,imx51-esdhc";
107 reg = <0x70020000 0x4000>;
108 interrupts = <3>;
109 status = "disabled";
110 };
111
112 esdhc@70024000 { /* ESDHC4 */
113 compatible = "fsl,imx51-esdhc";
114 reg = <0x70024000 0x4000>;
115 interrupts = <4>;
116 status = "disabled";
117 };
118 };
119
120 gpio0: gpio@73f84000 { /* GPIO1 */
121 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
122 reg = <0x73f84000 0x4000>;
123 interrupts = <50 51>;
124 gpio-controller;
125 #gpio-cells = <2>;
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
129
130 gpio1: gpio@73f88000 { /* GPIO2 */
131 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
132 reg = <0x73f88000 0x4000>;
133 interrupts = <52 53>;
134 gpio-controller;
135 #gpio-cells = <2>;
136 interrupt-controller;
137 #interrupt-cells = <1>;
138 };
139
140 gpio2: gpio@73f8c000 { /* GPIO3 */
141 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
142 reg = <0x73f8c000 0x4000>;
143 interrupts = <54 55>;
144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <1>;
148 };
149
150 gpio3: gpio@73f90000 { /* GPIO4 */
151 compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
152 reg = <0x73f90000 0x4000>;
153 interrupts = <56 57>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <1>;
158 };
159
160 wdog@73f98000 { /* WDOG1 */
161 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
162 reg = <0x73f98000 0x4000>;
163 interrupts = <58>;
164 status = "disabled";
165 };
166
167 wdog@73f9c000 { /* WDOG2 */
168 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
169 reg = <0x73f9c000 0x4000>;
170 interrupts = <59>;
171 status = "disabled";
172 };
173
174 uart0: uart@73fbc000 {
175 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
176 reg = <0x73fbc000 0x4000>;
177 interrupts = <31>;
178 status = "disabled";
179 };
180
181 uart1: uart@73fc0000 {
182 compatible = "fsl,imx51-uart", "fsl,imx21-uart";
183 reg = <0x73fc0000 0x4000>;
184 interrupts = <32>;
185 status = "disabled";
186 };
187 };
188
189 aips@80000000 { /* AIPS2 */
190 compatible = "fsl,aips-bus", "simple-bus";
191 #address-cells = <1>;
192 #size-cells = <1>;
193 reg = <0x80000000 0x10000000>;
194 ranges;
195
196 ecspi@83fac000 { /* ECSPI2 */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 compatible = "fsl,imx51-ecspi";
200 reg = <0x83fac000 0x4000>;
201 interrupts = <37>;
202 status = "disabled";
203 };
204
205 sdma@83fb0000 {
206 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
207 reg = <0x83fb0000 0x4000>;
208 interrupts = <6>;
209 };
210
211 cspi@83fc0000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
215 reg = <0x83fc0000 0x4000>;
216 interrupts = <38>;
217 status = "disabled";
218 };
219
220 i2c@83fc4000 { /* I2C2 */
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
224 reg = <0x83fc4000 0x4000>;
225 interrupts = <63>;
226 status = "disabled";
227 };
228
229 i2c@83fc8000 { /* I2C1 */
230 #address-cells = <1>;
231 #size-cells = <0>;
232 compatible = "fsl,imx51-i2c", "fsl,imx1-i2c";
233 reg = <0x83fc8000 0x4000>;
234 interrupts = <62>;
235 status = "disabled";
236 };
237
238 fec@83fec000 {
239 compatible = "fsl,imx51-fec", "fsl,imx27-fec";
240 reg = <0x83fec000 0x4000>;
241 interrupts = <87>;
242 status = "disabled";
243 };
244 };
245 };
246};
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
new file mode 100644
index 000000000000..2ab7f80a0a35
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -0,0 +1,113 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Automotive Reference Design Board";
18 compatible = "fsl,imx53-ard", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio0 1 0>; /* GPIO1_1 */
33 wp-gpios = <&gpio0 9 0>; /* GPIO1_9 */
34 status = "okay";
35 };
36 };
37
38 wdog@53f98000 { /* WDOG1 */
39 status = "okay";
40 };
41
42 iomuxc@53fa8000 {
43 compatible = "fsl,imx53-iomuxc-ard";
44 reg = <0x53fa8000 0x4000>;
45 };
46
47 uart0: uart@53fbc000 { /* UART1 */
48 status = "okay";
49 };
50 };
51
52 aips@60000000 { /* AIPS2 */
53 sdma@63fb0000 {
54 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
55 };
56 };
57 };
58
59 eim-cs1@f4000000 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "fsl,eim-bus", "simple-bus";
63 reg = <0xf4000000 0x3ff0000>;
64 ranges;
65
66 lan9220@f4000000 {
67 compatible = "smsc,lan9220", "smsc,lan9115";
68 reg = <0xf4000000 0x2000000>;
69 phy-mode = "mii";
70 interrupt-parent = <&gpio1>;
71 interrupts = <31>;
72 reg-io-width = <4>;
73 smsc,irq-push-pull;
74 };
75 };
76
77 gpio-keys {
78 compatible = "gpio-keys";
79
80 home {
81 label = "Home";
82 gpios = <&gpio4 10 0>; /* GPIO5_10 */
83 linux,code = <102>; /* KEY_HOME */
84 gpio-key,wakeup;
85 };
86
87 back {
88 label = "Back";
89 gpios = <&gpio4 11 0>; /* GPIO5_11 */
90 linux,code = <158>; /* KEY_BACK */
91 gpio-key,wakeup;
92 };
93
94 program {
95 label = "Program";
96 gpios = <&gpio4 12 0>; /* GPIO5_12 */
97 linux,code = <362>; /* KEY_PROGRAM */
98 gpio-key,wakeup;
99 };
100
101 volume-up {
102 label = "Volume Up";
103 gpios = <&gpio4 13 0>; /* GPIO5_13 */
104 linux,code = <115>; /* KEY_VOLUMEUP */
105 };
106
107 volume-down {
108 label = "Volume Down";
109 gpios = <&gpio3 0 0>; /* GPIO4_0 */
110 linux,code = <114>; /* KEY_VOLUMEDOWN */
111 };
112 };
113};
diff --git a/arch/arm/boot/dts/imx53-evk.dts b/arch/arm/boot/dts/imx53-evk.dts
new file mode 100644
index 000000000000..3f3a88185ff8
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-evk.dts
@@ -0,0 +1,120 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Evaluation Kit";
18 compatible = "fsl,imx53-evk", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x80000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 wp-gpios = <&gpio2 14 0>; /* GPIO3_14 */
34 status = "okay";
35 };
36
37 ecspi@50010000 { /* ECSPI1 */
38 fsl,spi-num-chipselects = <2>;
39 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
40 <&gpio2 19 0>; /* GPIO3_19 */
41 status = "okay";
42
43 flash: at45db321d@1 {
44 #address-cells = <1>;
45 #size-cells = <1>;
46 compatible = "atmel,at45db321d", "atmel,at45", "atmel,dataflash";
47 spi-max-frequency = <25000000>;
48 reg = <1>;
49
50 partition@0 {
51 label = "U-Boot";
52 reg = <0x0 0x40000>;
53 read-only;
54 };
55
56 partition@40000 {
57 label = "Kernel";
58 reg = <0x40000 0x3c0000>;
59 };
60 };
61 };
62
63 esdhc@50020000 { /* ESDHC3 */
64 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
65 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
66 status = "okay";
67 };
68 };
69
70 wdog@53f98000 { /* WDOG1 */
71 status = "okay";
72 };
73
74 iomuxc@53fa8000 {
75 compatible = "fsl,imx53-iomuxc-evk";
76 reg = <0x53fa8000 0x4000>;
77 };
78
79 uart0: uart@53fbc000 { /* UART1 */
80 status = "okay";
81 };
82 };
83
84 aips@60000000 { /* AIPS2 */
85 sdma@63fb0000 {
86 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
87 };
88
89 i2c@63fc4000 { /* I2C2 */
90 status = "okay";
91
92 pmic: mc13892@08 {
93 compatible = "fsl,mc13892", "fsl,mc13xxx";
94 reg = <0x08>;
95 };
96
97 codec: sgtl5000@0a {
98 compatible = "fsl,sgtl5000";
99 reg = <0x0a>;
100 };
101 };
102
103 fec@63fec000 {
104 phy-mode = "rmii";
105 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
106 status = "okay";
107 };
108 };
109 };
110
111 leds {
112 compatible = "gpio-leds";
113
114 green {
115 label = "Heartbeat";
116 gpios = <&gpio6 7 0>; /* GPIO7_7 */
117 linux,default-trigger = "heartbeat";
118 };
119 };
120};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
new file mode 100644
index 000000000000..ae6de6d0c3f1
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -0,0 +1,125 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Quick Start Board";
18 compatible = "fsl,imx53-qsb", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 status = "okay";
34 };
35
36 esdhc@50020000 { /* ESDHC3 */
37 cd-gpios = <&gpio2 11 0>; /* GPIO3_11 */
38 wp-gpios = <&gpio2 12 0>; /* GPIO3_12 */
39 status = "okay";
40 };
41 };
42
43 wdog@53f98000 { /* WDOG1 */
44 status = "okay";
45 };
46
47 iomuxc@53fa8000 {
48 compatible = "fsl,imx53-iomuxc-qsb";
49 reg = <0x53fa8000 0x4000>;
50 };
51
52 uart0: uart@53fbc000 { /* UART1 */
53 status = "okay";
54 };
55 };
56
57 aips@60000000 { /* AIPS2 */
58 sdma@63fb0000 {
59 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
60 };
61
62 i2c@63fc4000 { /* I2C2 */
63 status = "okay";
64
65 codec: sgtl5000@0a {
66 compatible = "fsl,sgtl5000";
67 reg = <0x0a>;
68 };
69 };
70
71 i2c@63fc8000 { /* I2C1 */
72 status = "okay";
73
74 accelerometer: mma8450@1c {
75 compatible = "fsl,mma8450";
76 reg = <0x1c>;
77 };
78
79 pmic: dialog@48 {
80 compatible = "dialog,da9053", "dialog,da9052";
81 reg = <0x48>;
82 };
83 };
84
85 fec@63fec000 {
86 phy-mode = "rmii";
87 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
88 status = "okay";
89 };
90 };
91 };
92
93 gpio-keys {
94 compatible = "gpio-keys";
95
96 power {
97 label = "Power Button";
98 gpios = <&gpio0 8 0>; /* GPIO1_8 */
99 linux,code = <116>; /* KEY_POWER */
100 gpio-key,wakeup;
101 };
102
103 volume-up {
104 label = "Volume Up";
105 gpios = <&gpio1 14 0>; /* GPIO2_14 */
106 linux,code = <115>; /* KEY_VOLUMEUP */
107 };
108
109 volume-down {
110 label = "Volume Down";
111 gpios = <&gpio1 15 0>; /* GPIO2_15 */
112 linux,code = <114>; /* KEY_VOLUMEDOWN */
113 };
114 };
115
116 leds {
117 compatible = "gpio-leds";
118
119 user {
120 label = "Heartbeat";
121 gpios = <&gpio6 7 0>; /* GPIO7_7 */
122 linux,default-trigger = "heartbeat";
123 };
124 };
125};
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
new file mode 100644
index 000000000000..b1c062eea715
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -0,0 +1,169 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "imx53.dtsi"
15
16/ {
17 model = "Freescale i.MX53 Smart Mobile Reference Design Board";
18 compatible = "fsl,imx53-smd", "fsl,imx53";
19
20 chosen {
21 bootargs = "console=ttymxc0,115200 root=/dev/mmcblk0p3 rootwait";
22 };
23
24 memory {
25 reg = <0x70000000 0x40000000>;
26 };
27
28 soc {
29 aips@50000000 { /* AIPS1 */
30 spba@50000000 {
31 esdhc@50004000 { /* ESDHC1 */
32 cd-gpios = <&gpio2 13 0>; /* GPIO3_13 */
33 wp-gpios = <&gpio3 11 0>; /* GPIO4_11 */
34 status = "okay";
35 };
36
37 esdhc@50008000 { /* ESDHC2 */
38 fsl,card-wired;
39 status = "okay";
40 };
41
42 uart2: uart@5000c000 { /* UART3 */
43 fsl,uart-has-rtscts;
44 status = "okay";
45 };
46
47 ecspi@50010000 { /* ECSPI1 */
48 fsl,spi-num-chipselects = <2>;
49 cs-gpios = <&gpio1 30 0>, /* GPIO2_30 */
50 <&gpio2 19 0>; /* GPIO3_19 */
51 status = "okay";
52
53 zigbee: mc1323@0 {
54 compatible = "fsl,mc1323";
55 spi-max-frequency = <8000000>;
56 reg = <0>;
57 };
58
59 flash: m25p32@1 {
60 #address-cells = <1>;
61 #size-cells = <1>;
62 compatible = "st,m25p32", "st,m25p";
63 spi-max-frequency = <20000000>;
64 reg = <1>;
65
66 partition@0 {
67 label = "U-Boot";
68 reg = <0x0 0x40000>;
69 read-only;
70 };
71
72 partition@40000 {
73 label = "Kernel";
74 reg = <0x40000 0x3c0000>;
75 };
76 };
77 };
78
79 esdhc@50020000 { /* ESDHC3 */
80 fsl,card-wired;
81 status = "okay";
82 };
83 };
84
85 wdog@53f98000 { /* WDOG1 */
86 status = "okay";
87 };
88
89 iomuxc@53fa8000 {
90 compatible = "fsl,imx53-iomuxc-smd";
91 reg = <0x53fa8000 0x4000>;
92 };
93
94 uart0: uart@53fbc000 { /* UART1 */
95 status = "okay";
96 };
97
98 uart1: uart@53fc0000 { /* UART2 */
99 status = "okay";
100 };
101 };
102
103 aips@60000000 { /* AIPS2 */
104 sdma@63fb0000 {
105 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
106 };
107
108 i2c@63fc4000 { /* I2C2 */
109 status = "okay";
110
111 codec: sgtl5000@0a {
112 compatible = "fsl,sgtl5000";
113 reg = <0x0a>;
114 };
115
116 magnetometer: mag3110@0e {
117 compatible = "fsl,mag3110";
118 reg = <0x0e>;
119 };
120
121 touchkey: mpr121@5a {
122 compatible = "fsl,mpr121";
123 reg = <0x5a>;
124 };
125 };
126
127 i2c@63fc8000 { /* I2C1 */
128 status = "okay";
129
130 accelerometer: mma8450@1c {
131 compatible = "fsl,mma8450";
132 reg = <0x1c>;
133 };
134
135 camera: ov5642@3c {
136 compatible = "ovti,ov5642";
137 reg = <0x3c>;
138 };
139
140 pmic: dialog@48 {
141 compatible = "dialog,da9053", "dialog,da9052";
142 reg = <0x48>;
143 };
144 };
145
146 fec@63fec000 {
147 phy-mode = "rmii";
148 phy-reset-gpios = <&gpio6 6 0>; /* GPIO7_6 */
149 status = "okay";
150 };
151 };
152 };
153
154 gpio-keys {
155 compatible = "gpio-keys";
156
157 volume-up {
158 label = "Volume Up";
159 gpios = <&gpio1 14 0>; /* GPIO2_14 */
160 linux,code = <115>; /* KEY_VOLUMEUP */
161 };
162
163 volume-down {
164 label = "Volume Down";
165 gpios = <&gpio1 15 0>; /* GPIO2_15 */
166 linux,code = <114>; /* KEY_VOLUMEDOWN */
167 };
168 };
169};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
new file mode 100644
index 000000000000..099cd84ee372
--- /dev/null
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -0,0 +1,301 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
17 serial0 = &uart0;
18 serial1 = &uart1;
19 serial2 = &uart2;
20 serial3 = &uart3;
21 serial4 = &uart4;
22 };
23
24 tzic: tz-interrupt-controller@0fffc000 {
25 compatible = "fsl,imx53-tzic", "fsl,tzic";
26 interrupt-controller;
27 #interrupt-cells = <1>;
28 reg = <0x0fffc000 0x4000>;
29 };
30
31 clocks {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 ckil {
36 compatible = "fsl,imx-ckil", "fixed-clock";
37 clock-frequency = <32768>;
38 };
39
40 ckih1 {
41 compatible = "fsl,imx-ckih1", "fixed-clock";
42 clock-frequency = <22579200>;
43 };
44
45 ckih2 {
46 compatible = "fsl,imx-ckih2", "fixed-clock";
47 clock-frequency = <0>;
48 };
49
50 osc {
51 compatible = "fsl,imx-osc", "fixed-clock";
52 clock-frequency = <24000000>;
53 };
54 };
55
56 soc {
57 #address-cells = <1>;
58 #size-cells = <1>;
59 compatible = "simple-bus";
60 interrupt-parent = <&tzic>;
61 ranges;
62
63 aips@50000000 { /* AIPS1 */
64 compatible = "fsl,aips-bus", "simple-bus";
65 #address-cells = <1>;
66 #size-cells = <1>;
67 reg = <0x50000000 0x10000000>;
68 ranges;
69
70 spba@50000000 {
71 compatible = "fsl,spba-bus", "simple-bus";
72 #address-cells = <1>;
73 #size-cells = <1>;
74 reg = <0x50000000 0x40000>;
75 ranges;
76
77 esdhc@50004000 { /* ESDHC1 */
78 compatible = "fsl,imx53-esdhc";
79 reg = <0x50004000 0x4000>;
80 interrupts = <1>;
81 status = "disabled";
82 };
83
84 esdhc@50008000 { /* ESDHC2 */
85 compatible = "fsl,imx53-esdhc";
86 reg = <0x50008000 0x4000>;
87 interrupts = <2>;
88 status = "disabled";
89 };
90
91 uart2: uart@5000c000 { /* UART3 */
92 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
93 reg = <0x5000c000 0x4000>;
94 interrupts = <33>;
95 status = "disabled";
96 };
97
98 ecspi@50010000 { /* ECSPI1 */
99 #address-cells = <1>;
100 #size-cells = <0>;
101 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
102 reg = <0x50010000 0x4000>;
103 interrupts = <36>;
104 status = "disabled";
105 };
106
107 esdhc@50020000 { /* ESDHC3 */
108 compatible = "fsl,imx53-esdhc";
109 reg = <0x50020000 0x4000>;
110 interrupts = <3>;
111 status = "disabled";
112 };
113
114 esdhc@50024000 { /* ESDHC4 */
115 compatible = "fsl,imx53-esdhc";
116 reg = <0x50024000 0x4000>;
117 interrupts = <4>;
118 status = "disabled";
119 };
120 };
121
122 gpio0: gpio@53f84000 { /* GPIO1 */
123 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
124 reg = <0x53f84000 0x4000>;
125 interrupts = <50 51>;
126 gpio-controller;
127 #gpio-cells = <2>;
128 interrupt-controller;
129 #interrupt-cells = <1>;
130 };
131
132 gpio1: gpio@53f88000 { /* GPIO2 */
133 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
134 reg = <0x53f88000 0x4000>;
135 interrupts = <52 53>;
136 gpio-controller;
137 #gpio-cells = <2>;
138 interrupt-controller;
139 #interrupt-cells = <1>;
140 };
141
142 gpio2: gpio@53f8c000 { /* GPIO3 */
143 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
144 reg = <0x53f8c000 0x4000>;
145 interrupts = <54 55>;
146 gpio-controller;
147 #gpio-cells = <2>;
148 interrupt-controller;
149 #interrupt-cells = <1>;
150 };
151
152 gpio3: gpio@53f90000 { /* GPIO4 */
153 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
154 reg = <0x53f90000 0x4000>;
155 interrupts = <56 57>;
156 gpio-controller;
157 #gpio-cells = <2>;
158 interrupt-controller;
159 #interrupt-cells = <1>;
160 };
161
162 wdog@53f98000 { /* WDOG1 */
163 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
164 reg = <0x53f98000 0x4000>;
165 interrupts = <58>;
166 status = "disabled";
167 };
168
169 wdog@53f9c000 { /* WDOG2 */
170 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
171 reg = <0x53f9c000 0x4000>;
172 interrupts = <59>;
173 status = "disabled";
174 };
175
176 uart0: uart@53fbc000 { /* UART1 */
177 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
178 reg = <0x53fbc000 0x4000>;
179 interrupts = <31>;
180 status = "disabled";
181 };
182
183 uart1: uart@53fc0000 { /* UART2 */
184 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
185 reg = <0x53fc0000 0x4000>;
186 interrupts = <32>;
187 status = "disabled";
188 };
189
190 gpio4: gpio@53fdc000 { /* GPIO5 */
191 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
192 reg = <0x53fdc000 0x4000>;
193 interrupts = <103 104>;
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
198 };
199
200 gpio5: gpio@53fe0000 { /* GPIO6 */
201 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
202 reg = <0x53fe0000 0x4000>;
203 interrupts = <105 106>;
204 gpio-controller;
205 #gpio-cells = <2>;
206 interrupt-controller;
207 #interrupt-cells = <1>;
208 };
209
210 gpio6: gpio@53fe4000 { /* GPIO7 */
211 compatible = "fsl,imx53-gpio", "fsl,imx31-gpio";
212 reg = <0x53fe4000 0x4000>;
213 interrupts = <107 108>;
214 gpio-controller;
215 #gpio-cells = <2>;
216 interrupt-controller;
217 #interrupt-cells = <1>;
218 };
219
220 i2c@53fec000 { /* I2C3 */
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
224 reg = <0x53fec000 0x4000>;
225 interrupts = <64>;
226 status = "disabled";
227 };
228
229 uart3: uart@53ff0000 { /* UART4 */
230 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
231 reg = <0x53ff0000 0x4000>;
232 interrupts = <13>;
233 status = "disabled";
234 };
235 };
236
237 aips@60000000 { /* AIPS2 */
238 compatible = "fsl,aips-bus", "simple-bus";
239 #address-cells = <1>;
240 #size-cells = <1>;
241 reg = <0x60000000 0x10000000>;
242 ranges;
243
244 uart4: uart@63f90000 { /* UART5 */
245 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
246 reg = <0x63f90000 0x4000>;
247 interrupts = <86>;
248 status = "disabled";
249 };
250
251 ecspi@63fac000 { /* ECSPI2 */
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
255 reg = <0x63fac000 0x4000>;
256 interrupts = <37>;
257 status = "disabled";
258 };
259
260 sdma@63fb0000 {
261 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
262 reg = <0x63fb0000 0x4000>;
263 interrupts = <6>;
264 };
265
266 cspi@63fc0000 {
267 #address-cells = <1>;
268 #size-cells = <0>;
269 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
270 reg = <0x63fc0000 0x4000>;
271 interrupts = <38>;
272 status = "disabled";
273 };
274
275 i2c@63fc4000 { /* I2C2 */
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
279 reg = <0x63fc4000 0x4000>;
280 interrupts = <63>;
281 status = "disabled";
282 };
283
284 i2c@63fc8000 { /* I2C1 */
285 #address-cells = <1>;
286 #size-cells = <0>;
287 compatible = "fsl,imx53-i2c", "fsl,imx1-i2c";
288 reg = <0x63fc8000 0x4000>;
289 interrupts = <62>;
290 status = "disabled";
291 };
292
293 fec@63fec000 {
294 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
295 reg = <0x63fec000 0x4000>;
296 interrupts = <87>;
297 status = "disabled";
298 };
299 };
300 };
301};
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
new file mode 100644
index 000000000000..15ded0deaa79
--- /dev/null
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -0,0 +1,24 @@
1/dts-v1/;
2
3/include/ "skeleton.dtsi"
4
5/ {
6 model = "Qualcomm MSM8660 SURF";
7 compatible = "qcom,msm8660-surf", "qcom,msm8660";
8 interrupt-parent = <&intc>;
9
10 intc: interrupt-controller@02080000 {
11 compatible = "qcom,msm-8660-qgic";
12 interrupt-controller;
13 #interrupt-cells = <1>;
14 reg = < 0x02080000 0x1000 >,
15 < 0x02081000 0x1000 >;
16 };
17
18 serial@19c400000 {
19 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
20 reg = <0x19c40000 0x1000>,
21 <0x19c00000 0x1000>;
22 interrupts = <195>;
23 };
24};
diff --git a/arch/arm/boot/dts/usb_a9g20.dts b/arch/arm/boot/dts/usb_a9g20.dts
new file mode 100644
index 000000000000..d66e2c00ac35
--- /dev/null
+++ b/arch/arm/boot/dts/usb_a9g20.dts
@@ -0,0 +1,30 @@
1/*
2 * usb_a9g20.dts - Device Tree file for Caloa USB A9G20 board
3 *
4 * Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 or later.
7 */
8/dts-v1/;
9/include/ "at91sam9g20.dtsi"
10
11/ {
12 model = "Calao USB A9G20";
13 compatible = "calao,usb-a9g20", "atmel,at91sam9g20", "atmel,at91sam9";
14
15 chosen {
16 bootargs = "mem=64M console=ttyS0,115200 mtdparts=atmel_nand:128k(at91bootstrap),256k(barebox)ro,128k(bareboxenv),128k(bareboxenv2),4M(kernel),120M(rootfs),-(data) root=/dev/mtdblock5 rw rootfstype=ubifs";
17 };
18
19 memory@20000000 {
20 reg = <0x20000000 0x4000000>;
21 };
22
23 ahb {
24 apb {
25 dbgu: serial@fffff200 {
26 status = "okay";
27 };
28 };
29 };
30};
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 4b71766fb21d..74df9ca2be31 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,4 +1,5 @@
1config ARM_GIC 1config ARM_GIC
2 select IRQ_DOMAIN
2 bool 3 bool
3 4
4config ARM_VIC 5config ARM_VIC
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index a8fc6b237592..0e6ae470c94f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -24,11 +24,17 @@
24 */ 24 */
25#include <linux/init.h> 25#include <linux/init.h>
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/err.h>
28#include <linux/module.h>
27#include <linux/list.h> 29#include <linux/list.h>
28#include <linux/smp.h> 30#include <linux/smp.h>
29#include <linux/cpu_pm.h> 31#include <linux/cpu_pm.h>
30#include <linux/cpumask.h> 32#include <linux/cpumask.h>
31#include <linux/io.h> 33#include <linux/io.h>
34#include <linux/of.h>
35#include <linux/of_address.h>
36#include <linux/of_irq.h>
37#include <linux/irqdomain.h>
32#include <linux/interrupt.h> 38#include <linux/interrupt.h>
33#include <linux/percpu.h> 39#include <linux/percpu.h>
34#include <linux/slab.h> 40#include <linux/slab.h>
@@ -75,8 +81,7 @@ static inline void __iomem *gic_cpu_base(struct irq_data *d)
75 81
76static inline unsigned int gic_irq(struct irq_data *d) 82static inline unsigned int gic_irq(struct irq_data *d)
77{ 83{
78 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 84 return d->hwirq;
79 return d->irq - gic_data->irq_offset;
80} 85}
81 86
82/* 87/*
@@ -84,7 +89,7 @@ static inline unsigned int gic_irq(struct irq_data *d)
84 */ 89 */
85static void gic_mask_irq(struct irq_data *d) 90static void gic_mask_irq(struct irq_data *d)
86{ 91{
87 u32 mask = 1 << (d->irq % 32); 92 u32 mask = 1 << (gic_irq(d) % 32);
88 93
89 raw_spin_lock(&irq_controller_lock); 94 raw_spin_lock(&irq_controller_lock);
90 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); 95 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
@@ -95,7 +100,7 @@ static void gic_mask_irq(struct irq_data *d)
95 100
96static void gic_unmask_irq(struct irq_data *d) 101static void gic_unmask_irq(struct irq_data *d)
97{ 102{
98 u32 mask = 1 << (d->irq % 32); 103 u32 mask = 1 << (gic_irq(d) % 32);
99 104
100 raw_spin_lock(&irq_controller_lock); 105 raw_spin_lock(&irq_controller_lock);
101 if (gic_arch_extn.irq_unmask) 106 if (gic_arch_extn.irq_unmask)
@@ -176,7 +181,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
176 bool force) 181 bool force)
177{ 182{
178 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 183 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
179 unsigned int shift = (d->irq % 4) * 8; 184 unsigned int shift = (gic_irq(d) % 4) * 8;
180 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 185 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask);
181 u32 val, mask, bit; 186 u32 val, mask, bit;
182 187
@@ -227,7 +232,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
227 if (gic_irq == 1023) 232 if (gic_irq == 1023)
228 goto out; 233 goto out;
229 234
230 cascade_irq = gic_irq + chip_data->irq_offset; 235 cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq);
231 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) 236 if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
232 do_bad_IRQ(cascade_irq, desc); 237 do_bad_IRQ(cascade_irq, desc);
233 else 238 else
@@ -259,14 +264,14 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
259 irq_set_chained_handler(irq, gic_handle_cascade_irq); 264 irq_set_chained_handler(irq, gic_handle_cascade_irq);
260} 265}
261 266
262static void __init gic_dist_init(struct gic_chip_data *gic, 267static void __init gic_dist_init(struct gic_chip_data *gic)
263 unsigned int irq_start)
264{ 268{
265 unsigned int gic_irqs, irq_limit, i; 269 unsigned int i, irq;
266 u32 cpumask; 270 u32 cpumask;
271 unsigned int gic_irqs = gic->gic_irqs;
272 struct irq_domain *domain = &gic->domain;
267 void __iomem *base = gic->dist_base; 273 void __iomem *base = gic->dist_base;
268 u32 cpu = 0; 274 u32 cpu = 0;
269 u32 nrppis = 0, ppi_base = 0;
270 275
271#ifdef CONFIG_SMP 276#ifdef CONFIG_SMP
272 cpu = cpu_logical_map(smp_processor_id()); 277 cpu = cpu_logical_map(smp_processor_id());
@@ -279,34 +284,6 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
279 writel_relaxed(0, base + GIC_DIST_CTRL); 284 writel_relaxed(0, base + GIC_DIST_CTRL);
280 285
281 /* 286 /*
282 * Find out how many interrupts are supported.
283 * The GIC only supports up to 1020 interrupt sources.
284 */
285 gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
286 gic_irqs = (gic_irqs + 1) * 32;
287 if (gic_irqs > 1020)
288 gic_irqs = 1020;
289
290 gic->gic_irqs = gic_irqs;
291
292 /*
293 * Nobody would be insane enough to use PPIs on a secondary
294 * GIC, right?
295 */
296 if (gic == &gic_data[0]) {
297 nrppis = (32 - irq_start) & 31;
298
299 /* The GIC only supports up to 16 PPIs. */
300 if (nrppis > 16)
301 BUG();
302
303 ppi_base = gic->irq_offset + 32 - nrppis;
304 }
305
306 pr_info("Configuring GIC with %d sources (%d PPIs)\n",
307 gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
308
309 /*
310 * Set all global interrupts to be level triggered, active low. 287 * Set all global interrupts to be level triggered, active low.
311 */ 288 */
312 for (i = 32; i < gic_irqs; i += 16) 289 for (i = 32; i < gic_irqs; i += 16)
@@ -332,29 +309,20 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
332 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); 309 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
333 310
334 /* 311 /*
335 * Limit number of interrupts registered to the platform maximum
336 */
337 irq_limit = gic->irq_offset + gic_irqs;
338 if (WARN_ON(irq_limit > NR_IRQS))
339 irq_limit = NR_IRQS;
340
341 /*
342 * Setup the Linux IRQ subsystem. 312 * Setup the Linux IRQ subsystem.
343 */ 313 */
344 for (i = 0; i < nrppis; i++) { 314 irq_domain_for_each_irq(domain, i, irq) {
345 int ppi = i + ppi_base; 315 if (i < 32) {
346 316 irq_set_percpu_devid(irq);
347 irq_set_percpu_devid(ppi); 317 irq_set_chip_and_handler(irq, &gic_chip,
348 irq_set_chip_and_handler(ppi, &gic_chip, 318 handle_percpu_devid_irq);
349 handle_percpu_devid_irq); 319 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
350 irq_set_chip_data(ppi, gic); 320 } else {
351 set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN); 321 irq_set_chip_and_handler(irq, &gic_chip,
352 } 322 handle_fasteoi_irq);
353 323 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
354 for (i = irq_start + nrppis; i < irq_limit; i++) { 324 }
355 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); 325 irq_set_chip_data(irq, gic);
356 irq_set_chip_data(i, gic);
357 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
358 } 326 }
359 327
360 writel_relaxed(1, base + GIC_DIST_CTRL); 328 writel_relaxed(1, base + GIC_DIST_CTRL);
@@ -566,23 +534,85 @@ static void __init gic_pm_init(struct gic_chip_data *gic)
566} 534}
567#endif 535#endif
568 536
569void __init gic_init(unsigned int gic_nr, unsigned int irq_start, 537#ifdef CONFIG_OF
538static int gic_irq_domain_dt_translate(struct irq_domain *d,
539 struct device_node *controller,
540 const u32 *intspec, unsigned int intsize,
541 unsigned long *out_hwirq, unsigned int *out_type)
542{
543 if (d->of_node != controller)
544 return -EINVAL;
545 if (intsize < 3)
546 return -EINVAL;
547
548 /* Get the interrupt number and add 16 to skip over SGIs */
549 *out_hwirq = intspec[1] + 16;
550
551 /* For SPIs, we need to add 16 more to get the GIC irq ID number */
552 if (!intspec[0])
553 *out_hwirq += 16;
554
555 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
556 return 0;
557}
558#endif
559
560const struct irq_domain_ops gic_irq_domain_ops = {
561#ifdef CONFIG_OF
562 .dt_translate = gic_irq_domain_dt_translate,
563#endif
564};
565
566void __init gic_init(unsigned int gic_nr, int irq_start,
570 void __iomem *dist_base, void __iomem *cpu_base) 567 void __iomem *dist_base, void __iomem *cpu_base)
571{ 568{
572 struct gic_chip_data *gic; 569 struct gic_chip_data *gic;
570 struct irq_domain *domain;
571 int gic_irqs;
573 572
574 BUG_ON(gic_nr >= MAX_GIC_NR); 573 BUG_ON(gic_nr >= MAX_GIC_NR);
575 574
576 gic = &gic_data[gic_nr]; 575 gic = &gic_data[gic_nr];
576 domain = &gic->domain;
577 gic->dist_base = dist_base; 577 gic->dist_base = dist_base;
578 gic->cpu_base = cpu_base; 578 gic->cpu_base = cpu_base;
579 gic->irq_offset = (irq_start - 1) & ~31;
580 579
581 if (gic_nr == 0) 580 /*
581 * For primary GICs, skip over SGIs.
582 * For secondary GICs, skip over PPIs, too.
583 */
584 if (gic_nr == 0) {
582 gic_cpu_base_addr = cpu_base; 585 gic_cpu_base_addr = cpu_base;
586 domain->hwirq_base = 16;
587 if (irq_start > 0)
588 irq_start = (irq_start & ~31) + 16;
589 } else
590 domain->hwirq_base = 32;
591
592 /*
593 * Find out how many interrupts are supported.
594 * The GIC only supports up to 1020 interrupt sources.
595 */
596 gic_irqs = readl_relaxed(dist_base + GIC_DIST_CTR) & 0x1f;
597 gic_irqs = (gic_irqs + 1) * 32;
598 if (gic_irqs > 1020)
599 gic_irqs = 1020;
600 gic->gic_irqs = gic_irqs;
601
602 domain->nr_irq = gic_irqs - domain->hwirq_base;
603 domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq,
604 numa_node_id());
605 if (IS_ERR_VALUE(domain->irq_base)) {
606 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
607 irq_start);
608 domain->irq_base = irq_start;
609 }
610 domain->priv = gic;
611 domain->ops = &gic_irq_domain_ops;
612 irq_domain_add(domain);
583 613
584 gic_chip.flags |= gic_arch_extn.flags; 614 gic_chip.flags |= gic_arch_extn.flags;
585 gic_dist_init(gic, irq_start); 615 gic_dist_init(gic);
586 gic_cpu_init(gic); 616 gic_cpu_init(gic);
587 gic_pm_init(gic); 617 gic_pm_init(gic);
588} 618}
@@ -614,3 +644,35 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
614 writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT); 644 writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
615} 645}
616#endif 646#endif
647
648#ifdef CONFIG_OF
649static int gic_cnt __initdata = 0;
650
651int __init gic_of_init(struct device_node *node, struct device_node *parent)
652{
653 void __iomem *cpu_base;
654 void __iomem *dist_base;
655 int irq;
656 struct irq_domain *domain = &gic_data[gic_cnt].domain;
657
658 if (WARN_ON(!node))
659 return -ENODEV;
660
661 dist_base = of_iomap(node, 0);
662 WARN(!dist_base, "unable to map gic dist registers\n");
663
664 cpu_base = of_iomap(node, 1);
665 WARN(!cpu_base, "unable to map gic cpu registers\n");
666
667 domain->of_node = of_node_get(node);
668
669 gic_init(gic_cnt, -1, dist_base, cpu_base);
670
671 if (parent) {
672 irq = irq_of_parse_and_map(node, 0);
673 gic_cascade_irq(gic_cnt, irq);
674 }
675 gic_cnt++;
676 return 0;
677}
678#endif
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 14867e12f205..3e91f22046f5 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,16 +33,19 @@
33#define GIC_DIST_SOFTINT 0xf00 33#define GIC_DIST_SOFTINT 0xf00
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36#include <linux/irqdomain.h>
37struct device_node;
38
36extern void __iomem *gic_cpu_base_addr; 39extern void __iomem *gic_cpu_base_addr;
37extern struct irq_chip gic_arch_extn; 40extern struct irq_chip gic_arch_extn;
38 41
39void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); 42void gic_init(unsigned int, int, void __iomem *, void __iomem *);
43int gic_of_init(struct device_node *node, struct device_node *parent);
40void gic_secondary_init(unsigned int); 44void gic_secondary_init(unsigned int);
41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 45void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 46void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
43 47
44struct gic_chip_data { 48struct gic_chip_data {
45 unsigned int irq_offset;
46 void __iomem *dist_base; 49 void __iomem *dist_base;
47 void __iomem *cpu_base; 50 void __iomem *cpu_base;
48#ifdef CONFIG_CPU_PM 51#ifdef CONFIG_CPU_PM
@@ -52,6 +55,9 @@ struct gic_chip_data {
52 u32 __percpu *saved_ppi_enable; 55 u32 __percpu *saved_ppi_enable;
53 u32 __percpu *saved_ppi_conf; 56 u32 __percpu *saved_ppi_conf;
54#endif 57#endif
58#ifdef CONFIG_IRQ_DOMAIN
59 struct irq_domain domain;
60#endif
55 unsigned int gic_irqs; 61 unsigned int gic_irqs;
56}; 62};
57#endif 63#endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 04a85c546abc..a6b7991d7fe8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -455,6 +455,17 @@ endif
455 455
456# ---------------------------------------------------------- 456# ----------------------------------------------------------
457 457
458comment "Generic Board Type"
459
460config MACH_AT91SAM_DT
461 bool "Atmel AT91SAM Evaluation Kits with device-tree support"
462 select USE_OF
463 help
464 Select this if you want to experiment device-tree with
465 an Atmel Evaluation Kit.
466
467# ----------------------------------------------------------
468
458comment "AT91 Board Options" 469comment "AT91 Board Options"
459 470
460config MTD_AT91_DATAFLASH_CARD 471config MTD_AT91_DATAFLASH_CARD
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d992dd5d9321..242174f9f355 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -76,6 +76,9 @@ obj-$(CONFIG_MACH_SNAPPER_9260) += board-snapper9260.o
76# AT91SAM9G45 board-specific support 76# AT91SAM9G45 board-specific support
77obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o 77obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
78 78
79# AT91SAM board with device-tree
80obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
81
79# AT91CAP9 board-specific support 82# AT91CAP9 board-specific support
80obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o 83obj-$(CONFIG_MACH_AT91CAP9ADK) += board-cap9adk.o
81 84
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 9ab5a3e5f4f1..8ddafadfdc7d 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -16,3 +16,5 @@ else
16params_phys-y := 0x20000100 16params_phys-y := 0x20000100
17initrd_phys-y := 0x20410000 17initrd_phys-y := 0x20410000
18endif 18endif
19
20dtb-$(CONFIG_MACH_AT91SAM_DT) += at91sam9m10g45ek.dtb usb_a9g20.dtb
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index a9be75825e34..b84a9f642f59 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -199,6 +199,14 @@ static struct clk_lookup periph_clocks_lookups[] = {
199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk), 199 CLKDEV_CON_DEV_ID("t4_clk", "atmel_tcb.1", &tc4_clk),
200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk), 200 CLKDEV_CON_DEV_ID("t5_clk", "atmel_tcb.1", &tc5_clk),
201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), 201 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk),
202 /* more usart lookup table for DT entries */
203 CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck),
204 CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk),
205 CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
206 CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk),
207 CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk),
208 CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
209 CLKDEV_CON_DEV_ID("usart", "fffd8000.serial", &usart5_clk),
202 /* fake hclk clock */ 210 /* fake hclk clock */
203 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), 211 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
204}; 212};
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 29def9095ab1..318b0407ea04 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -223,6 +223,12 @@ static struct clk_lookup periph_clocks_lookups[] = {
223 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), 223 CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk),
224 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), 224 CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk),
225 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), 225 CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk),
226 /* more usart lookup table for DT entries */
227 CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
228 CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk),
229 CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
230 CLKDEV_CON_DEV_ID("usart", "fff94000.serial", &usart2_clk),
231 CLKDEV_CON_DEV_ID("usart", "fff98000.serial", &usart3_clk),
226 /* fake hclk clock */ 232 /* fake hclk clock */
227 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk), 233 CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
228}; 234};
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt.c
new file mode 100644
index 000000000000..0b7d32778210
--- /dev/null
+++ b/arch/arm/mach-at91/board-dt.c
@@ -0,0 +1,123 @@
1/*
2 * Setup code for AT91SAM Evaluation Kits with Device Tree support
3 *
4 * Covers: * AT91SAM9G45-EKES board
5 * * AT91SAM9M10-EKES board
6 * * AT91SAM9M10G45-EK board
7 *
8 * Copyright (C) 2011 Atmel,
9 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>
10 *
11 * Licensed under GPLv2 or later.
12 */
13
14#include <linux/types.h>
15#include <linux/init.h>
16#include <linux/module.h>
17#include <linux/gpio.h>
18#include <linux/irqdomain.h>
19#include <linux/of_irq.h>
20#include <linux/of_platform.h>
21
22#include <mach/hardware.h>
23#include <mach/board.h>
24#include <mach/system_rev.h>
25#include <mach/at91sam9_smc.h>
26
27#include <asm/setup.h>
28#include <asm/irq.h>
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31#include <asm/mach/irq.h>
32
33#include "sam9_smc.h"
34#include "generic.h"
35
36
37static void __init ek_init_early(void)
38{
39 /* Initialize processor: 12.000 MHz crystal */
40 at91_initialize(12000000);
41
42 /* DGBU on ttyS0. (Rx & Tx only) */
43 at91_register_uart(0, 0, 0);
44
45 /* set serial console to ttyS0 (ie, DBGU) */
46 at91_set_serial_console(0);
47}
48
49/* det_pin is not connected */
50static struct atmel_nand_data __initdata ek_nand_data = {
51 .ale = 21,
52 .cle = 22,
53 .rdy_pin = AT91_PIN_PC8,
54 .enable_pin = AT91_PIN_PC14,
55};
56
57static struct sam9_smc_config __initdata ek_nand_smc_config = {
58 .ncs_read_setup = 0,
59 .nrd_setup = 2,
60 .ncs_write_setup = 0,
61 .nwe_setup = 2,
62
63 .ncs_read_pulse = 4,
64 .nrd_pulse = 4,
65 .ncs_write_pulse = 4,
66 .nwe_pulse = 4,
67
68 .read_cycle = 7,
69 .write_cycle = 7,
70
71 .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
72 .tdf_cycles = 3,
73};
74
75static void __init ek_add_device_nand(void)
76{
77 ek_nand_data.bus_width_16 = board_have_nand_16bit();
78 /* setup bus-width (8 or 16) */
79 if (ek_nand_data.bus_width_16)
80 ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
81 else
82 ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
83
84 /* configure chip-select 3 (NAND) */
85 sam9_smc_configure(3, &ek_nand_smc_config);
86
87 at91_add_device_nand(&ek_nand_data);
88}
89
90static const struct of_device_id aic_of_match[] __initconst = {
91 { .compatible = "atmel,at91rm9200-aic", },
92 {},
93};
94
95static void __init at91_dt_init_irq(void)
96{
97 irq_domain_generate_simple(aic_of_match, 0xfffff000, 0);
98 at91_init_irq_default();
99}
100
101static void __init at91_dt_device_init(void)
102{
103 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
104
105 /* NAND */
106 ek_add_device_nand();
107}
108
109static const char *at91_dt_board_compat[] __initdata = {
110 "atmel,at91sam9m10g45ek",
111 "calao,usb-a9g20",
112 NULL
113};
114
115DT_MACHINE_START(at91sam_dt, "Atmel AT91SAM (Device Tree)")
116 /* Maintainer: Atmel */
117 .timer = &at91sam926x_timer,
118 .map_io = at91_map_io,
119 .init_early = ek_init_early,
120 .init_irq = at91_dt_init_irq,
121 .init_machine = at91_dt_device_init,
122 .dt_compat = at91_dt_board_compat,
123MACHINE_END
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 106170fb1844..cf38e2284fa9 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -1,4 +1,4 @@
1/* Copyright (c) 2010, Code Aurora Forum. All rights reserved. 1/* Copyright (c) 2010, 2011, Code Aurora Forum. All rights reserved.
2 * 2 *
3 * This program is free software; you can redistribute it and/or modify 3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and 4 * it under the terms of the GNU General Public License version 2 and
@@ -8,18 +8,16 @@
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details. 10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
15 * 02110-1301, USA.
16 *
17 */ 11 */
18 12
19#include <linux/kernel.h> 13#include <linux/kernel.h>
20#include <linux/platform_device.h> 14#include <linux/platform_device.h>
21#include <linux/io.h> 15#include <linux/io.h>
22#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/irqdomain.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_platform.h>
23#include <linux/memblock.h> 21#include <linux/memblock.h>
24 22
25#include <asm/mach-types.h> 23#include <asm/mach-types.h>
@@ -70,6 +68,41 @@ static void __init msm8x60_init(void)
70{ 68{
71} 69}
72 70
71#ifdef CONFIG_OF
72static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
73 {}
74};
75
76static struct of_device_id msm_dt_gic_match[] __initdata = {
77 { .compatible = "qcom,msm-8660-qgic", },
78 {}
79};
80
81static void __init msm8x60_dt_init(void)
82{
83 struct device_node *node;
84
85 node = of_find_matching_node_by_address(NULL, msm_dt_gic_match,
86 MSM8X60_QGIC_DIST_PHYS);
87 if (node)
88 irq_domain_add_simple(node, GIC_SPI_START);
89
90 if (of_machine_is_compatible("qcom,msm8660-surf")) {
91 printk(KERN_INFO "Init surf UART registers\n");
92 msm8x60_init_uart12dm();
93 }
94
95 of_platform_populate(NULL, of_default_bus_match_table,
96 msm_auxdata_lookup, NULL);
97}
98
99static const char *msm8x60_fluid_match[] __initdata = {
100 "qcom,msm8660-fluid",
101 "qcom,msm8660-surf",
102 NULL
103};
104#endif /* CONFIG_OF */
105
73MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") 106MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
74 .fixup = msm8x60_fixup, 107 .fixup = msm8x60_fixup,
75 .reserve = msm8x60_reserve, 108 .reserve = msm8x60_reserve,
@@ -105,3 +138,14 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
105 .init_machine = msm8x60_init, 138 .init_machine = msm8x60_init,
106 .timer = &msm_timer, 139 .timer = &msm_timer,
107MACHINE_END 140MACHINE_END
141
142#ifdef CONFIG_OF
143/* TODO: General device tree support for all MSM. */
144DT_MACHINE_START(MSM_DT, "Qualcomm MSM (Flattened Device Tree)")
145 .map_io = msm8x60_map_io,
146 .init_irq = msm8x60_init_irq,
147 .init_machine = msm8x60_dt_init,
148 .timer = &msm_timer,
149 .dt_compat = msm8x60_fluid_match,
150MACHINE_END
151#endif /* CONFIG_OF */
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 3d4c31306ca7..af0c212e3c7b 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -56,6 +56,15 @@ config MACH_MX50_RDP
56 56
57comment "i.MX51 machines:" 57comment "i.MX51 machines:"
58 58
59config MACH_IMX51_DT
60 bool "Support i.MX51 platforms from device tree"
61 select SOC_IMX51
62 select USE_OF
63 select MACH_MX51_BABBAGE
64 help
65 Include support for Freescale i.MX51 based platforms
66 using the device tree for discovery
67
59config MACH_MX51_BABBAGE 68config MACH_MX51_BABBAGE
60 bool "Support MX51 BABBAGE platforms" 69 bool "Support MX51 BABBAGE platforms"
61 select SOC_IMX51 70 select SOC_IMX51
@@ -171,6 +180,18 @@ config MACH_MX51_EFIKASB
171 180
172comment "i.MX53 machines:" 181comment "i.MX53 machines:"
173 182
183config MACH_IMX53_DT
184 bool "Support i.MX53 platforms from device tree"
185 select SOC_IMX53
186 select USE_OF
187 select MACH_MX53_ARD
188 select MACH_MX53_EVK
189 select MACH_MX53_LOCO
190 select MACH_MX53_SMD
191 help
192 Include support for Freescale i.MX53 based platforms
193 using the device tree for discovery
194
174config MACH_MX53_EVK 195config MACH_MX53_EVK
175 bool "Support MX53 EVK platforms" 196 bool "Support MX53 EVK platforms"
176 select SOC_IMX53 197 select SOC_IMX53
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 9565304b7282..0fc60807fa2b 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -21,3 +21,6 @@ obj-$(CONFIG_MX51_EFIKA_COMMON) += mx51_efika.o
21obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 21obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
22obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o 22obj-$(CONFIG_MACH_MX51_EFIKASB) += board-mx51_efikasb.o
23obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o 23obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
24
25obj-$(CONFIG_MACH_IMX51_DT) += imx51-dt.o
26obj-$(CONFIG_MACH_IMX53_DT) += imx53-dt.o
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 5993208a8f00..5c837603ff0f 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -349,6 +349,12 @@ static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
349 .wp_type = ESDHC_WP_GPIO, 349 .wp_type = ESDHC_WP_GPIO,
350}; 350};
351 351
352void __init imx51_babbage_common_init(void)
353{
354 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads,
355 ARRAY_SIZE(mx51babbage_pads));
356}
357
352/* 358/*
353 * Board specific initialization. 359 * Board specific initialization.
354 */ 360 */
@@ -363,8 +369,7 @@ static void __init mx51_babbage_init(void)
363#if defined(CONFIG_CPU_FREQ_IMX) 369#if defined(CONFIG_CPU_FREQ_IMX)
364 get_cpu_op = mx51_get_cpu_op; 370 get_cpu_op = mx51_get_cpu_op;
365#endif 371#endif
366 mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, 372 imx51_babbage_common_init();
367 ARRAY_SIZE(mx51babbage_pads));
368 373
369 imx51_add_imx_uart(0, &uart_pdata); 374 imx51_add_imx_uart(0, &uart_pdata);
370 imx51_add_imx_uart(1, NULL); 375 imx51_add_imx_uart(1, NULL);
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
index 614edcb0aa7e..0d7f0fffb23a 100644
--- a/arch/arm/mach-mx5/board-mx53_ard.c
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -171,9 +171,6 @@ static struct imxi2c_platform_data mx53_ard_i2c3_data = {
171 171
172static void __init mx53_ard_io_init(void) 172static void __init mx53_ard_io_init(void)
173{ 173{
174 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
175 ARRAY_SIZE(mx53_ard_pads));
176
177 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b"); 174 gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
178 gpio_direction_input(ARD_ETHERNET_INT_B); 175 gpio_direction_input(ARD_ETHERNET_INT_B);
179 176
@@ -216,6 +213,13 @@ static int weim_cs_config(void)
216 return 0; 213 return 0;
217} 214}
218 215
216void __init imx53_ard_common_init(void)
217{
218 mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
219 ARRAY_SIZE(mx53_ard_pads));
220 weim_cs_config();
221}
222
219static struct platform_device *devices[] __initdata = { 223static struct platform_device *devices[] __initdata = {
220 &ard_smsc_lan9220_device, 224 &ard_smsc_lan9220_device,
221}; 225};
@@ -225,8 +229,8 @@ static void __init mx53_ard_board_init(void)
225 imx53_soc_init(); 229 imx53_soc_init();
226 imx53_add_imx_uart(0, NULL); 230 imx53_add_imx_uart(0, NULL);
227 231
232 imx53_ard_common_init();
228 mx53_ard_io_init(); 233 mx53_ard_io_init();
229 weim_cs_config();
230 platform_add_devices(devices, ARRAY_SIZE(devices)); 234 platform_add_devices(devices, ARRAY_SIZE(devices));
231 235
232 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data); 236 imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 6a3e6168e322..6bea31ab8f85 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -131,12 +131,17 @@ static const struct spi_imx_master mx53_evk_spi_data __initconst = {
131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs), 131 .num_chipselect = ARRAY_SIZE(mx53_evk_spi_cs),
132}; 132};
133 133
134void __init imx53_evk_common_init(void)
135{
136 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
137 ARRAY_SIZE(mx53_evk_pads));
138}
139
134static void __init mx53_evk_board_init(void) 140static void __init mx53_evk_board_init(void)
135{ 141{
136 imx53_soc_init(); 142 imx53_soc_init();
143 imx53_evk_common_init();
137 144
138 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
139 ARRAY_SIZE(mx53_evk_pads));
140 mx53_evk_init_uart(); 145 mx53_evk_init_uart();
141 mx53_evk_fec_reset(); 146 mx53_evk_fec_reset();
142 imx53_add_fec(&mx53_evk_fec_pdata); 147 imx53_add_fec(&mx53_evk_fec_pdata);
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 0af2766f8610..7678f7734db6 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -263,6 +263,12 @@ static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
263 .num_leds = ARRAY_SIZE(mx53loco_leds), 263 .num_leds = ARRAY_SIZE(mx53loco_leds),
264}; 264};
265 265
266void __init imx53_qsb_common_init(void)
267{
268 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
269 ARRAY_SIZE(mx53_loco_pads));
270}
271
266static struct i2c_board_info mx53loco_i2c_devices[] = { 272static struct i2c_board_info mx53loco_i2c_devices[] = {
267 { 273 {
268 I2C_BOARD_INFO("mma8450", 0x1C), 274 I2C_BOARD_INFO("mma8450", 0x1C),
@@ -273,9 +279,8 @@ static void __init mx53_loco_board_init(void)
273{ 279{
274 int ret; 280 int ret;
275 imx53_soc_init(); 281 imx53_soc_init();
282 imx53_qsb_common_init();
276 283
277 mxc_iomux_v3_setup_multiple_pads(mx53_loco_pads,
278 ARRAY_SIZE(mx53_loco_pads));
279 imx53_add_imx_uart(0, NULL); 284 imx53_add_imx_uart(0, NULL);
280 mx53_loco_fec_reset(); 285 mx53_loco_fec_reset();
281 imx53_add_fec(&mx53_loco_fec_data); 286 imx53_add_fec(&mx53_loco_fec_data);
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index d12fd3043ba6..59c0845eb4a6 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -125,12 +125,17 @@ static inline void mx53_smd_ahci_pwr_on(void)
125 } 125 }
126} 126}
127 127
128void __init imx53_smd_common_init(void)
129{
130 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
131 ARRAY_SIZE(mx53_smd_pads));
132}
133
128static void __init mx53_smd_board_init(void) 134static void __init mx53_smd_board_init(void)
129{ 135{
130 imx53_soc_init(); 136 imx53_soc_init();
137 imx53_smd_common_init();
131 138
132 mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads,
133 ARRAY_SIZE(mx53_smd_pads));
134 mx53_smd_init_uart(); 139 mx53_smd_init_uart();
135 mx53_smd_fec_reset(); 140 mx53_smd_fec_reset();
136 imx53_add_fec(&mx53_smd_fec_data); 141 imx53_add_fec(&mx53_smd_fec_data);
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index b94879e8679f..2aacf41c48e7 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -15,6 +15,7 @@
15#include <linux/clk.h> 15#include <linux/clk.h>
16#include <linux/io.h> 16#include <linux/io.h>
17#include <linux/clkdev.h> 17#include <linux/clkdev.h>
18#include <linux/of.h>
18 19
19#include <asm/div64.h> 20#include <asm/div64.h>
20 21
@@ -1632,3 +1633,41 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1632 MX53_INT_GPT); 1633 MX53_INT_GPT);
1633 return 0; 1634 return 0;
1634} 1635}
1636
1637static void __init clk_get_freq_dt(unsigned long *ckil, unsigned long *osc,
1638 unsigned long *ckih1, unsigned long *ckih2)
1639{
1640 struct device_node *np;
1641
1642 /* retrieve the freqency of fixed clocks from device tree */
1643 for_each_compatible_node(np, NULL, "fixed-clock") {
1644 u32 rate;
1645 if (of_property_read_u32(np, "clock-frequency", &rate))
1646 continue;
1647
1648 if (of_device_is_compatible(np, "fsl,imx-ckil"))
1649 *ckil = rate;
1650 else if (of_device_is_compatible(np, "fsl,imx-osc"))
1651 *osc = rate;
1652 else if (of_device_is_compatible(np, "fsl,imx-ckih1"))
1653 *ckih1 = rate;
1654 else if (of_device_is_compatible(np, "fsl,imx-ckih2"))
1655 *ckih2 = rate;
1656 }
1657}
1658
1659int __init mx51_clocks_init_dt(void)
1660{
1661 unsigned long ckil, osc, ckih1, ckih2;
1662
1663 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1664 return mx51_clocks_init(ckil, osc, ckih1, ckih2);
1665}
1666
1667int __init mx53_clocks_init_dt(void)
1668{
1669 unsigned long ckil, osc, ckih1, ckih2;
1670
1671 clk_get_freq_dt(&ckil, &osc, &ckih1, &ckih2);
1672 return mx53_clocks_init(ckil, osc, ckih1, ckih2);
1673}
diff --git a/arch/arm/mach-mx5/imx51-dt.c b/arch/arm/mach-mx5/imx51-dt.c
new file mode 100644
index 000000000000..ccc61585659b
--- /dev/null
+++ b/arch/arm/mach-mx5/imx51-dt.c
@@ -0,0 +1,116 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h>
17#include <asm/mach/arch.h>
18#include <asm/mach/time.h>
19#include <mach/common.h>
20#include <mach/mx51.h>
21
22/*
23 * Lookup table for attaching a specific name and platform_data pointer to
24 * devices as they get created by of_platform_populate(). Ideally this table
25 * would not exist, but the current clock implementation depends on some devices
26 * having a specific name.
27 */
28static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
29 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
30 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
31 OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
32 OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
33 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
34 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
35 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
36 OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
37 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
38 OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
39 OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
40 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
43 OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
44 { /* sentinel */ }
45};
46
47static void __init imx51_tzic_add_irq_domain(struct device_node *np,
48 struct device_node *interrupt_parent)
49{
50 irq_domain_add_simple(np, 0);
51}
52
53static void __init imx51_gpio_add_irq_domain(struct device_node *np,
54 struct device_node *interrupt_parent)
55{
56 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
57 32 * 4; /* imx51 gets 4 gpio ports */
58
59 irq_domain_add_simple(np, gpio_irq_base);
60 gpio_irq_base += 32;
61}
62
63static const struct of_device_id imx51_irq_match[] __initconst = {
64 { .compatible = "fsl,imx51-tzic", .data = imx51_tzic_add_irq_domain, },
65 { .compatible = "fsl,imx51-gpio", .data = imx51_gpio_add_irq_domain, },
66 { /* sentinel */ }
67};
68
69static const struct of_device_id imx51_iomuxc_of_match[] __initconst = {
70 { .compatible = "fsl,imx51-iomuxc-babbage", .data = imx51_babbage_common_init, },
71 { /* sentinel */ }
72};
73
74static void __init imx51_dt_init(void)
75{
76 struct device_node *node;
77 const struct of_device_id *of_id;
78 void (*func)(void);
79
80 of_irq_init(imx51_irq_match);
81
82 node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
83 if (node) {
84 of_id = of_match_node(imx51_iomuxc_of_match, node);
85 func = of_id->data;
86 func();
87 of_node_put(node);
88 }
89
90 of_platform_populate(NULL, of_default_bus_match_table,
91 imx51_auxdata_lookup, NULL);
92}
93
94static void __init imx51_timer_init(void)
95{
96 mx51_clocks_init_dt();
97}
98
99static struct sys_timer imx51_timer = {
100 .init = imx51_timer_init,
101};
102
103static const char *imx51_dt_board_compat[] __initdata = {
104 "fsl,imx51-babbage",
105 NULL
106};
107
108DT_MACHINE_START(IMX51_DT, "Freescale i.MX51 (Device Tree Support)")
109 .map_io = mx51_map_io,
110 .init_early = imx51_init_early,
111 .init_irq = mx51_init_irq,
112 .handle_irq = imx51_handle_irq,
113 .timer = &imx51_timer,
114 .init_machine = imx51_dt_init,
115 .dt_compat = imx51_dt_board_compat,
116MACHINE_END
diff --git a/arch/arm/mach-mx5/imx53-dt.c b/arch/arm/mach-mx5/imx53-dt.c
new file mode 100644
index 000000000000..ccaa0b81b768
--- /dev/null
+++ b/arch/arm/mach-mx5/imx53-dt.c
@@ -0,0 +1,126 @@
1/*
2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/irqdomain.h>
16#include <linux/of_irq.h>
17#include <linux/of_platform.h>
18#include <asm/mach/arch.h>
19#include <asm/mach/time.h>
20#include <mach/common.h>
21#include <mach/mx53.h>
22
23/*
24 * Lookup table for attaching a specific name and platform_data pointer to
25 * devices as they get created by of_platform_populate(). Ideally this table
26 * would not exist, but the current clock implementation depends on some devices
27 * having a specific name.
28 */
29static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
30 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
31 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
32 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
33 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
34 OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
35 OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
36 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
37 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
38 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
39 OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
40 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
41 OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
42 OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
43 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx-i2c.0", NULL),
44 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx-i2c.1", NULL),
45 OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx-i2c.2", NULL),
46 OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
47 OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
48 { /* sentinel */ }
49};
50
51static void __init imx53_tzic_add_irq_domain(struct device_node *np,
52 struct device_node *interrupt_parent)
53{
54 irq_domain_add_simple(np, 0);
55}
56
57static void __init imx53_gpio_add_irq_domain(struct device_node *np,
58 struct device_node *interrupt_parent)
59{
60 static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS -
61 32 * 7; /* imx53 gets 7 gpio ports */
62
63 irq_domain_add_simple(np, gpio_irq_base);
64 gpio_irq_base += 32;
65}
66
67static const struct of_device_id imx53_irq_match[] __initconst = {
68 { .compatible = "fsl,imx53-tzic", .data = imx53_tzic_add_irq_domain, },
69 { .compatible = "fsl,imx53-gpio", .data = imx53_gpio_add_irq_domain, },
70 { /* sentinel */ }
71};
72
73static const struct of_device_id imx53_iomuxc_of_match[] __initconst = {
74 { .compatible = "fsl,imx53-iomuxc-ard", .data = imx53_ard_common_init, },
75 { .compatible = "fsl,imx53-iomuxc-evk", .data = imx53_evk_common_init, },
76 { .compatible = "fsl,imx53-iomuxc-qsb", .data = imx53_qsb_common_init, },
77 { .compatible = "fsl,imx53-iomuxc-smd", .data = imx53_smd_common_init, },
78 { /* sentinel */ }
79};
80
81static void __init imx53_dt_init(void)
82{
83 struct device_node *node;
84 const struct of_device_id *of_id;
85 void (*func)(void);
86
87 of_irq_init(imx53_irq_match);
88
89 node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
90 if (node) {
91 of_id = of_match_node(imx53_iomuxc_of_match, node);
92 func = of_id->data;
93 func();
94 of_node_put(node);
95 }
96
97 of_platform_populate(NULL, of_default_bus_match_table,
98 imx53_auxdata_lookup, NULL);
99}
100
101static void __init imx53_timer_init(void)
102{
103 mx53_clocks_init_dt();
104}
105
106static struct sys_timer imx53_timer = {
107 .init = imx53_timer_init,
108};
109
110static const char *imx53_dt_board_compat[] __initdata = {
111 "fsl,imx53-ard",
112 "fsl,imx53-evk",
113 "fsl,imx53-qsb",
114 "fsl,imx53-smd",
115 NULL
116};
117
118DT_MACHINE_START(IMX53_DT, "Freescale i.MX53 (Device Tree Support)")
119 .map_io = mx53_map_io,
120 .init_early = imx53_init_early,
121 .init_irq = mx53_init_irq,
122 .handle_irq = imx53_handle_irq,
123 .timer = &imx53_timer,
124 .init_machine = imx53_dt_init,
125 .dt_compat = imx53_dt_board_compat,
126MACHINE_END
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index ace4bb550edc..c850af3650ea 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -64,6 +64,8 @@ extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
64 unsigned long ckih1, unsigned long ckih2); 64 unsigned long ckih1, unsigned long ckih2);
65extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, 65extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
66 unsigned long ckih1, unsigned long ckih2); 66 unsigned long ckih1, unsigned long ckih2);
67extern int mx51_clocks_init_dt(void);
68extern int mx53_clocks_init_dt(void);
67extern struct platform_device *mxc_register_gpio(char *name, int id, 69extern struct platform_device *mxc_register_gpio(char *name, int id,
68 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high); 70 resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
69extern void mxc_set_cpu_type(unsigned int type); 71extern void mxc_set_cpu_type(unsigned int type);
@@ -97,4 +99,9 @@ void tzic_handle_irq(struct pt_regs *);
97#define imx51_handle_irq tzic_handle_irq 99#define imx51_handle_irq tzic_handle_irq
98#define imx53_handle_irq tzic_handle_irq 100#define imx53_handle_irq tzic_handle_irq
99 101
102extern void imx51_babbage_common_init(void);
103extern void imx53_ard_common_init(void);
104extern void imx53_evk_common_init(void);
105extern void imx53_qsb_common_init(void);
106extern void imx53_smd_common_init(void);
100#endif 107#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 23:36:38 -0500