diff options
Diffstat (limited to 'arch/arm')
74 files changed, 1236 insertions, 719 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3146ed3f6eca..380e4f016654 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -3,7 +3,7 @@ config ARM | |||
3 | default y | 3 | default y |
4 | select HAVE_AOUT | 4 | select HAVE_AOUT |
5 | select HAVE_DMA_API_DEBUG | 5 | select HAVE_DMA_API_DEBUG |
6 | select HAVE_IDE | 6 | select HAVE_IDE if PCI || ISA || PCMCIA |
7 | select HAVE_MEMBLOCK | 7 | select HAVE_MEMBLOCK |
8 | select RTC_LIB | 8 | select RTC_LIB |
9 | select SYS_SUPPORTS_APM_EMULATION | 9 | select SYS_SUPPORTS_APM_EMULATION |
@@ -195,7 +195,8 @@ config VECTORS_BASE | |||
195 | The base address of exception vectors. | 195 | The base address of exception vectors. |
196 | 196 | ||
197 | config ARM_PATCH_PHYS_VIRT | 197 | config ARM_PATCH_PHYS_VIRT |
198 | bool "Patch physical to virtual translations at runtime" | 198 | bool "Patch physical to virtual translations at runtime" if EMBEDDED |
199 | default y | ||
199 | depends on !XIP_KERNEL && MMU | 200 | depends on !XIP_KERNEL && MMU |
200 | depends on !ARCH_REALVIEW || !SPARSEMEM | 201 | depends on !ARCH_REALVIEW || !SPARSEMEM |
201 | help | 202 | help |
@@ -204,16 +205,12 @@ config ARM_PATCH_PHYS_VIRT | |||
204 | kernel in system memory. | 205 | kernel in system memory. |
205 | 206 | ||
206 | This can only be used with non-XIP MMU kernels where the base | 207 | This can only be used with non-XIP MMU kernels where the base |
207 | of physical memory is at a 16MB boundary, or theoretically 64K | 208 | of physical memory is at a 16MB boundary. |
208 | for the MSM machine class. | 209 | |
210 | Only disable this option if you know that you do not require | ||
211 | this feature (eg, building a kernel for a single machine) and | ||
212 | you need to shrink the kernel to the minimal size. | ||
209 | 213 | ||
210 | config ARM_PATCH_PHYS_VIRT_16BIT | ||
211 | def_bool y | ||
212 | depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM | ||
213 | help | ||
214 | This option extends the physical to virtual translation patching | ||
215 | to allow physical memory down to a theoretical minimum of 64K | ||
216 | boundaries. | ||
217 | 214 | ||
218 | source "init/Kconfig" | 215 | source "init/Kconfig" |
219 | 216 | ||
@@ -301,7 +298,6 @@ config ARCH_AT91 | |||
301 | select ARCH_REQUIRE_GPIOLIB | 298 | select ARCH_REQUIRE_GPIOLIB |
302 | select HAVE_CLK | 299 | select HAVE_CLK |
303 | select CLKDEV_LOOKUP | 300 | select CLKDEV_LOOKUP |
304 | select ARM_PATCH_PHYS_VIRT if MMU | ||
305 | help | 301 | help |
306 | This enables support for systems based on the Atmel AT91RM9200, | 302 | This enables support for systems based on the Atmel AT91RM9200, |
307 | AT91SAM9 and AT91CAP9 processors. | 303 | AT91SAM9 and AT91CAP9 processors. |
@@ -385,6 +381,7 @@ config ARCH_FOOTBRIDGE | |||
385 | select CPU_SA110 | 381 | select CPU_SA110 |
386 | select FOOTBRIDGE | 382 | select FOOTBRIDGE |
387 | select GENERIC_CLOCKEVENTS | 383 | select GENERIC_CLOCKEVENTS |
384 | select HAVE_IDE | ||
388 | help | 385 | help |
389 | Support for systems based on the DC21285 companion chip | 386 | Support for systems based on the DC21285 companion chip |
390 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. | 387 | ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. |
@@ -631,6 +628,8 @@ config ARCH_PXA | |||
631 | select SPARSE_IRQ | 628 | select SPARSE_IRQ |
632 | select AUTO_ZRELADDR | 629 | select AUTO_ZRELADDR |
633 | select MULTI_IRQ_HANDLER | 630 | select MULTI_IRQ_HANDLER |
631 | select ARM_CPU_SUSPEND if PM | ||
632 | select HAVE_IDE | ||
634 | help | 633 | help |
635 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. | 634 | Support for Intel/Marvell's PXA2xx/PXA3xx processor line. |
636 | 635 | ||
@@ -671,6 +670,7 @@ config ARCH_RPC | |||
671 | select NO_IOPORT | 670 | select NO_IOPORT |
672 | select ARCH_SPARSEMEM_ENABLE | 671 | select ARCH_SPARSEMEM_ENABLE |
673 | select ARCH_USES_GETTIMEOFFSET | 672 | select ARCH_USES_GETTIMEOFFSET |
673 | select HAVE_IDE | ||
674 | help | 674 | help |
675 | On the Acorn Risc-PC, Linux can support the internal IDE disk and | 675 | On the Acorn Risc-PC, Linux can support the internal IDE disk and |
676 | CD-ROM interface, serial and parallel port, and the floppy drive. | 676 | CD-ROM interface, serial and parallel port, and the floppy drive. |
@@ -689,6 +689,7 @@ config ARCH_SA1100 | |||
689 | select HAVE_SCHED_CLOCK | 689 | select HAVE_SCHED_CLOCK |
690 | select TICK_ONESHOT | 690 | select TICK_ONESHOT |
691 | select ARCH_REQUIRE_GPIOLIB | 691 | select ARCH_REQUIRE_GPIOLIB |
692 | select HAVE_IDE | ||
692 | help | 693 | help |
693 | Support for StrongARM 11x0 based boards. | 694 | Support for StrongARM 11x0 based boards. |
694 | 695 | ||
@@ -1375,6 +1376,7 @@ config SMP | |||
1375 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ | 1376 | MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \ |
1376 | ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ | 1377 | ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ |
1377 | ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE | 1378 | ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE |
1379 | depends on MMU | ||
1378 | select USE_GENERIC_SMP_HELPERS | 1380 | select USE_GENERIC_SMP_HELPERS |
1379 | select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP | 1381 | select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP |
1380 | help | 1382 | help |
@@ -1407,6 +1409,31 @@ config SMP_ON_UP | |||
1407 | 1409 | ||
1408 | If you don't know what to do here, say Y. | 1410 | If you don't know what to do here, say Y. |
1409 | 1411 | ||
1412 | config ARM_CPU_TOPOLOGY | ||
1413 | bool "Support cpu topology definition" | ||
1414 | depends on SMP && CPU_V7 | ||
1415 | default y | ||
1416 | help | ||
1417 | Support ARM cpu topology definition. The MPIDR register defines | ||
1418 | affinity between processors which is then used to describe the cpu | ||
1419 | topology of an ARM System. | ||
1420 | |||
1421 | config SCHED_MC | ||
1422 | bool "Multi-core scheduler support" | ||
1423 | depends on ARM_CPU_TOPOLOGY | ||
1424 | help | ||
1425 | Multi-core scheduler support improves the CPU scheduler's decision | ||
1426 | making when dealing with multi-core CPU chips at a cost of slightly | ||
1427 | increased overhead in some places. If unsure say N here. | ||
1428 | |||
1429 | config SCHED_SMT | ||
1430 | bool "SMT scheduler support" | ||
1431 | depends on ARM_CPU_TOPOLOGY | ||
1432 | help | ||
1433 | Improves the CPU scheduler's decision making when dealing with | ||
1434 | MultiThreading at a cost of slightly increased overhead in some | ||
1435 | places. If unsure say N here. | ||
1436 | |||
1410 | config HAVE_ARM_SCU | 1437 | config HAVE_ARM_SCU |
1411 | bool | 1438 | bool |
1412 | help | 1439 | help |
@@ -1482,6 +1509,7 @@ config THUMB2_KERNEL | |||
1482 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL | 1509 | depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL |
1483 | select AEABI | 1510 | select AEABI |
1484 | select ARM_ASM_UNIFIED | 1511 | select ARM_ASM_UNIFIED |
1512 | select ARM_UNWIND | ||
1485 | help | 1513 | help |
1486 | By enabling this option, the kernel will be compiled in | 1514 | By enabling this option, the kernel will be compiled in |
1487 | Thumb-2 mode. A compiler/assembler that understand the unified | 1515 | Thumb-2 mode. A compiler/assembler that understand the unified |
@@ -2101,6 +2129,9 @@ config ARCH_SUSPEND_POSSIBLE | |||
2101 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE | 2129 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE |
2102 | def_bool y | 2130 | def_bool y |
2103 | 2131 | ||
2132 | config ARM_CPU_SUSPEND | ||
2133 | def_bool PM_SLEEP | ||
2134 | |||
2104 | endmenu | 2135 | endmenu |
2105 | 2136 | ||
2106 | source "net/Kconfig" | 2137 | source "net/Kconfig" |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 81cbe40c159c..df3eb3ccd769 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -65,13 +65,71 @@ config DEBUG_USER | |||
65 | 65 | ||
66 | # These options are only for real kernel hackers who want to get their hands dirty. | 66 | # These options are only for real kernel hackers who want to get their hands dirty. |
67 | config DEBUG_LL | 67 | config DEBUG_LL |
68 | bool "Kernel low-level debugging functions" | 68 | bool "Kernel low-level debugging functions (read help!)" |
69 | depends on DEBUG_KERNEL | 69 | depends on DEBUG_KERNEL |
70 | help | 70 | help |
71 | Say Y here to include definitions of printascii, printch, printhex | 71 | Say Y here to include definitions of printascii, printch, printhex |
72 | in the kernel. This is helpful if you are debugging code that | 72 | in the kernel. This is helpful if you are debugging code that |
73 | executes before the console is initialized. | 73 | executes before the console is initialized. |
74 | 74 | ||
75 | Note that selecting this option will limit the kernel to a single | ||
76 | UART definition, as specified below. Attempting to boot the kernel | ||
77 | image on a different platform *will not work*, so this option should | ||
78 | not be enabled for kernels that are intended to be portable. | ||
79 | |||
80 | choice | ||
81 | prompt "Kernel low-level debugging port" | ||
82 | depends on DEBUG_LL | ||
83 | |||
84 | config DEBUG_LL_UART_NONE | ||
85 | bool "No low-level debugging UART" | ||
86 | help | ||
87 | Say Y here if your platform doesn't provide a UART option | ||
88 | below. This relies on your platform choosing the right UART | ||
89 | definition internally in order for low-level debugging to | ||
90 | work. | ||
91 | |||
92 | config DEBUG_ICEDCC | ||
93 | bool "Kernel low-level debugging via EmbeddedICE DCC channel" | ||
94 | help | ||
95 | Say Y here if you want the debug print routines to direct | ||
96 | their output to the EmbeddedICE macrocell's DCC channel using | ||
97 | co-processor 14. This is known to work on the ARM9 style ICE | ||
98 | channel and on the XScale with the PEEDI. | ||
99 | |||
100 | Note that the system will appear to hang during boot if there | ||
101 | is nothing connected to read from the DCC. | ||
102 | |||
103 | config DEBUG_FOOTBRIDGE_COM1 | ||
104 | bool "Kernel low-level debugging messages via footbridge 8250 at PCI COM1" | ||
105 | depends on FOOTBRIDGE | ||
106 | help | ||
107 | Say Y here if you want the debug print routines to direct | ||
108 | their output to the 8250 at PCI COM1. | ||
109 | |||
110 | config DEBUG_DC21285_PORT | ||
111 | bool "Kernel low-level debugging messages via footbridge serial port" | ||
112 | depends on FOOTBRIDGE | ||
113 | help | ||
114 | Say Y here if you want the debug print routines to direct | ||
115 | their output to the serial port in the DC21285 (Footbridge). | ||
116 | |||
117 | config DEBUG_CLPS711X_UART1 | ||
118 | bool "Kernel low-level debugging messages via UART1" | ||
119 | depends on ARCH_CLPS711X | ||
120 | help | ||
121 | Say Y here if you want the debug print routines to direct | ||
122 | their output to the first serial port on these devices. | ||
123 | |||
124 | config DEBUG_CLPS711X_UART2 | ||
125 | bool "Kernel low-level debugging messages via UART2" | ||
126 | depends on ARCH_CLPS711X | ||
127 | help | ||
128 | Say Y here if you want the debug print routines to direct | ||
129 | their output to the second serial port on these devices. | ||
130 | |||
131 | endchoice | ||
132 | |||
75 | config EARLY_PRINTK | 133 | config EARLY_PRINTK |
76 | bool "Early printk" | 134 | bool "Early printk" |
77 | depends on DEBUG_LL | 135 | depends on DEBUG_LL |
@@ -80,43 +138,14 @@ config EARLY_PRINTK | |||
80 | kernel low-level debugging functions. Add earlyprintk to your | 138 | kernel low-level debugging functions. Add earlyprintk to your |
81 | kernel parameters to enable this console. | 139 | kernel parameters to enable this console. |
82 | 140 | ||
83 | config DEBUG_ICEDCC | ||
84 | bool "Kernel low-level debugging via EmbeddedICE DCC channel" | ||
85 | depends on DEBUG_LL | ||
86 | help | ||
87 | Say Y here if you want the debug print routines to direct their | ||
88 | output to the EmbeddedICE macrocell's DCC channel using | ||
89 | co-processor 14. This is known to work on the ARM9 style ICE | ||
90 | channel and on the XScale with the PEEDI. | ||
91 | |||
92 | It does include a timeout to ensure that the system does not | ||
93 | totally freeze when there is nothing connected to read. | ||
94 | |||
95 | config OC_ETM | 141 | config OC_ETM |
96 | bool "On-chip ETM and ETB" | 142 | bool "On-chip ETM and ETB" |
97 | select ARM_AMBA | 143 | depends on ARM_AMBA |
98 | help | 144 | help |
99 | Enables the on-chip embedded trace macrocell and embedded trace | 145 | Enables the on-chip embedded trace macrocell and embedded trace |
100 | buffer driver that will allow you to collect traces of the | 146 | buffer driver that will allow you to collect traces of the |
101 | kernel code. | 147 | kernel code. |
102 | 148 | ||
103 | config DEBUG_DC21285_PORT | ||
104 | bool "Kernel low-level debugging messages via footbridge serial port" | ||
105 | depends on DEBUG_LL && FOOTBRIDGE | ||
106 | help | ||
107 | Say Y here if you want the debug print routines to direct their | ||
108 | output to the serial port in the DC21285 (Footbridge). Saying N | ||
109 | will cause the debug messages to appear on the first 16550 | ||
110 | serial port. | ||
111 | |||
112 | config DEBUG_CLPS711X_UART2 | ||
113 | bool "Kernel low-level debugging messages via UART2" | ||
114 | depends on DEBUG_LL && ARCH_CLPS711X | ||
115 | help | ||
116 | Say Y here if you want the debug print routines to direct their | ||
117 | output to the second serial port on these devices. Saying N will | ||
118 | cause the debug messages to appear on the first serial port. | ||
119 | |||
120 | config DEBUG_S3C_UART | 149 | config DEBUG_S3C_UART |
121 | depends on PLAT_SAMSUNG | 150 | depends on PLAT_SAMSUNG |
122 | int "S3C UART to use for low-level debug" | 151 | int "S3C UART to use for low-level debug" |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 70c424eaf7b0..5665c2a3b652 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -128,6 +128,9 @@ textofs-$(CONFIG_PM_H1940) := 0x00108000 | |||
128 | ifeq ($(CONFIG_ARCH_SA1100),y) | 128 | ifeq ($(CONFIG_ARCH_SA1100),y) |
129 | textofs-$(CONFIG_SA1111) := 0x00208000 | 129 | textofs-$(CONFIG_SA1111) := 0x00208000 |
130 | endif | 130 | endif |
131 | textofs-$(CONFIG_ARCH_MSM7X30) := 0x00208000 | ||
132 | textofs-$(CONFIG_ARCH_MSM8X60) := 0x00208000 | ||
133 | textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000 | ||
131 | 134 | ||
132 | # Machine directory name. This list is sorted alphanumerically | 135 | # Machine directory name. This list is sorted alphanumerically |
133 | # by CONFIG_* macro name. | 136 | # by CONFIG_* macro name. |
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c index 3227ca952a12..666b278e56d7 100644 --- a/arch/arm/common/gic.c +++ b/arch/arm/common/gic.c | |||
@@ -180,7 +180,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, | |||
180 | return -EINVAL; | 180 | return -EINVAL; |
181 | 181 | ||
182 | mask = 0xff << shift; | 182 | mask = 0xff << shift; |
183 | bit = 1 << (cpu + shift); | 183 | bit = 1 << (cpu_logical_map(cpu) + shift); |
184 | 184 | ||
185 | spin_lock(&irq_controller_lock); | 185 | spin_lock(&irq_controller_lock); |
186 | val = readl_relaxed(reg) & ~mask; | 186 | val = readl_relaxed(reg) & ~mask; |
@@ -259,9 +259,15 @@ static void __init gic_dist_init(struct gic_chip_data *gic, | |||
259 | unsigned int irq_start) | 259 | unsigned int irq_start) |
260 | { | 260 | { |
261 | unsigned int gic_irqs, irq_limit, i; | 261 | unsigned int gic_irqs, irq_limit, i; |
262 | u32 cpumask; | ||
262 | void __iomem *base = gic->dist_base; | 263 | void __iomem *base = gic->dist_base; |
263 | u32 cpumask = 1 << smp_processor_id(); | 264 | u32 cpu = 0; |
264 | 265 | ||
266 | #ifdef CONFIG_SMP | ||
267 | cpu = cpu_logical_map(smp_processor_id()); | ||
268 | #endif | ||
269 | |||
270 | cpumask = 1 << cpu; | ||
265 | cpumask |= cpumask << 8; | 271 | cpumask |= cpumask << 8; |
266 | cpumask |= cpumask << 16; | 272 | cpumask |= cpumask << 16; |
267 | 273 | ||
@@ -382,7 +388,12 @@ void __cpuinit gic_enable_ppi(unsigned int irq) | |||
382 | #ifdef CONFIG_SMP | 388 | #ifdef CONFIG_SMP |
383 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) | 389 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
384 | { | 390 | { |
385 | unsigned long map = *cpus_addr(*mask); | 391 | int cpu; |
392 | unsigned long map = 0; | ||
393 | |||
394 | /* Convert our logical CPU mask into a physical one. */ | ||
395 | for_each_cpu(cpu, mask) | ||
396 | map |= 1 << cpu_logical_map(cpu); | ||
386 | 397 | ||
387 | /* | 398 | /* |
388 | * Ensure that stores to Normal memory are visible to the | 399 | * Ensure that stores to Normal memory are visible to the |
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c index 197f81c77351..01f18a421b17 100644 --- a/arch/arm/common/vic.c +++ b/arch/arm/common/vic.c | |||
@@ -346,7 +346,8 @@ void __init vic_init(void __iomem *base, unsigned int irq_start, | |||
346 | 346 | ||
347 | /* Identify which VIC cell this one is, by reading the ID */ | 347 | /* Identify which VIC cell this one is, by reading the ID */ |
348 | for (i = 0; i < 4; i++) { | 348 | for (i = 0; i < 4; i++) { |
349 | u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | 349 | void __iomem *addr; |
350 | addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4); | ||
350 | cellid |= (readl(addr) & 0xff) << (8 * i); | 351 | cellid |= (readl(addr) & 0xff) << (8 * i); |
351 | } | 352 | } |
352 | vendor = (cellid >> 12) & 0xff; | 353 | vendor = (cellid >> 12) & 0xff; |
diff --git a/arch/arm/include/asm/cputype.h b/arch/arm/include/asm/cputype.h index cd4458f64171..cb47d28cbe1f 100644 --- a/arch/arm/include/asm/cputype.h +++ b/arch/arm/include/asm/cputype.h | |||
@@ -8,6 +8,7 @@ | |||
8 | #define CPUID_CACHETYPE 1 | 8 | #define CPUID_CACHETYPE 1 |
9 | #define CPUID_TCM 2 | 9 | #define CPUID_TCM 2 |
10 | #define CPUID_TLBTYPE 3 | 10 | #define CPUID_TLBTYPE 3 |
11 | #define CPUID_MPIDR 5 | ||
11 | 12 | ||
12 | #define CPUID_EXT_PFR0 "c1, 0" | 13 | #define CPUID_EXT_PFR0 "c1, 0" |
13 | #define CPUID_EXT_PFR1 "c1, 1" | 14 | #define CPUID_EXT_PFR1 "c1, 1" |
@@ -70,6 +71,11 @@ static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) | |||
70 | return read_cpuid(CPUID_TCM); | 71 | return read_cpuid(CPUID_TCM); |
71 | } | 72 | } |
72 | 73 | ||
74 | static inline unsigned int __attribute_const__ read_cpuid_mpidr(void) | ||
75 | { | ||
76 | return read_cpuid(CPUID_MPIDR); | ||
77 | } | ||
78 | |||
73 | /* | 79 | /* |
74 | * Intel's XScale3 core supports some v6 features (supersections, L2) | 80 | * Intel's XScale3 core supports some v6 features (supersections, L2) |
75 | * but advertises itself as v5 as it does not support the v6 ISA. For | 81 | * but advertises itself as v5 as it does not support the v6 ISA. For |
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h index 7a21d0bf7134..28b7ee8d7398 100644 --- a/arch/arm/include/asm/dma-mapping.h +++ b/arch/arm/include/asm/dma-mapping.h | |||
@@ -32,7 +32,7 @@ static inline unsigned long dma_to_pfn(struct device *dev, dma_addr_t addr) | |||
32 | 32 | ||
33 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) | 33 | static inline void *dma_to_virt(struct device *dev, dma_addr_t addr) |
34 | { | 34 | { |
35 | return (void *)__bus_to_virt(addr); | 35 | return (void *)__bus_to_virt((unsigned long)addr); |
36 | } | 36 | } |
37 | 37 | ||
38 | static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) | 38 | static inline dma_addr_t virt_to_dma(struct device *dev, void *addr) |
diff --git a/arch/arm/include/asm/ecard.h b/arch/arm/include/asm/ecard.h index 29f2610efc70..eaea14676d57 100644 --- a/arch/arm/include/asm/ecard.h +++ b/arch/arm/include/asm/ecard.h | |||
@@ -161,7 +161,6 @@ struct expansion_card { | |||
161 | 161 | ||
162 | /* Private internal data */ | 162 | /* Private internal data */ |
163 | const char *card_desc; /* Card description */ | 163 | const char *card_desc; /* Card description */ |
164 | CONST unsigned int podaddr; /* Base Linux address for card */ | ||
165 | CONST loader_t loader; /* loader program */ | 164 | CONST loader_t loader; /* loader program */ |
166 | u64 dma_mask; | 165 | u64 dma_mask; |
167 | }; | 166 | }; |
diff --git a/arch/arm/include/asm/exception.h b/arch/arm/include/asm/exception.h new file mode 100644 index 000000000000..5abaf5bbd985 --- /dev/null +++ b/arch/arm/include/asm/exception.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * Annotations for marking C functions as exception handlers. | ||
3 | * | ||
4 | * These should only be used for C functions that are called from the low | ||
5 | * level exception entry code and not any intervening C code. | ||
6 | */ | ||
7 | #ifndef __ASM_ARM_EXCEPTION_H | ||
8 | #define __ASM_ARM_EXCEPTION_H | ||
9 | |||
10 | #include <linux/ftrace.h> | ||
11 | |||
12 | #define __exception __attribute__((section(".exception.text"))) | ||
13 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
14 | #define __exception_irq_entry __irq_entry | ||
15 | #else | ||
16 | #define __exception_irq_entry __exception | ||
17 | #endif | ||
18 | |||
19 | #endif /* __ASM_ARM_EXCEPTION_H */ | ||
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 99a6ed7e1bfd..434edccdf7f3 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h | |||
@@ -52,6 +52,8 @@ | |||
52 | #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 | 52 | #define L2X0_LOCKDOWN_WAY_D_BASE 0x900 |
53 | #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 | 53 | #define L2X0_LOCKDOWN_WAY_I_BASE 0x904 |
54 | #define L2X0_LOCKDOWN_STRIDE 0x08 | 54 | #define L2X0_LOCKDOWN_STRIDE 0x08 |
55 | #define L2X0_ADDR_FILTER_START 0xC00 | ||
56 | #define L2X0_ADDR_FILTER_END 0xC04 | ||
55 | #define L2X0_TEST_OPERATION 0xF00 | 57 | #define L2X0_TEST_OPERATION 0xF00 |
56 | #define L2X0_LINE_DATA 0xF10 | 58 | #define L2X0_LINE_DATA 0xF10 |
57 | #define L2X0_LINE_TAG 0xF30 | 59 | #define L2X0_LINE_TAG 0xF30 |
@@ -65,8 +67,23 @@ | |||
65 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) | 67 | #define L2X0_CACHE_ID_PART_MASK (0xf << 6) |
66 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) | 68 | #define L2X0_CACHE_ID_PART_L210 (1 << 6) |
67 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) | 69 | #define L2X0_CACHE_ID_PART_L310 (3 << 6) |
70 | #define L2X0_CACHE_ID_RTL_MASK 0x3f | ||
71 | #define L2X0_CACHE_ID_RTL_R0P0 0x0 | ||
72 | #define L2X0_CACHE_ID_RTL_R1P0 0x2 | ||
73 | #define L2X0_CACHE_ID_RTL_R2P0 0x4 | ||
74 | #define L2X0_CACHE_ID_RTL_R3P0 0x5 | ||
75 | #define L2X0_CACHE_ID_RTL_R3P1 0x6 | ||
76 | #define L2X0_CACHE_ID_RTL_R3P2 0x8 | ||
68 | 77 | ||
69 | #define L2X0_AUX_CTRL_MASK 0xc0000fff | 78 | #define L2X0_AUX_CTRL_MASK 0xc0000fff |
79 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT 0 | ||
80 | #define L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK 0x7 | ||
81 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT 3 | ||
82 | #define L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK (0x7 << 3) | ||
83 | #define L2X0_AUX_CTRL_TAG_LATENCY_SHIFT 6 | ||
84 | #define L2X0_AUX_CTRL_TAG_LATENCY_MASK (0x7 << 6) | ||
85 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT 9 | ||
86 | #define L2X0_AUX_CTRL_DIRTY_LATENCY_MASK (0x7 << 9) | ||
70 | #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 | 87 | #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 |
71 | #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 | 88 | #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 |
72 | #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) | 89 | #define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) |
@@ -77,8 +94,33 @@ | |||
77 | #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 | 94 | #define L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT 29 |
78 | #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 | 95 | #define L2X0_AUX_CTRL_EARLY_BRESP_SHIFT 30 |
79 | 96 | ||
97 | #define L2X0_LATENCY_CTRL_SETUP_SHIFT 0 | ||
98 | #define L2X0_LATENCY_CTRL_RD_SHIFT 4 | ||
99 | #define L2X0_LATENCY_CTRL_WR_SHIFT 8 | ||
100 | |||
101 | #define L2X0_ADDR_FILTER_EN 1 | ||
102 | |||
80 | #ifndef __ASSEMBLY__ | 103 | #ifndef __ASSEMBLY__ |
81 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); | 104 | extern void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask); |
105 | extern int l2x0_of_init(__u32 aux_val, __u32 aux_mask); | ||
106 | |||
107 | struct l2x0_regs { | ||
108 | unsigned long phy_base; | ||
109 | unsigned long aux_ctrl; | ||
110 | /* | ||
111 | * Whether the following registers need to be saved/restored | ||
112 | * depends on platform | ||
113 | */ | ||
114 | unsigned long tag_latency; | ||
115 | unsigned long data_latency; | ||
116 | unsigned long filter_start; | ||
117 | unsigned long filter_end; | ||
118 | unsigned long prefetch_ctrl; | ||
119 | unsigned long pwr_ctrl; | ||
120 | }; | ||
121 | |||
122 | extern struct l2x0_regs l2x0_saved_regs; | ||
123 | |||
82 | #endif | 124 | #endif |
83 | 125 | ||
84 | #endif | 126 | #endif |
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index d66605dea55a..dc2d5102e680 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h | |||
@@ -110,6 +110,27 @@ static inline void __iomem *__typesafe_io(unsigned long addr) | |||
110 | #include <mach/io.h> | 110 | #include <mach/io.h> |
111 | 111 | ||
112 | /* | 112 | /* |
113 | * This is the limit of PC card/PCI/ISA IO space, which is by default | ||
114 | * 64K if we have PC card, PCI or ISA support. Otherwise, default to | ||
115 | * zero to prevent ISA/PCI drivers claiming IO space (and potentially | ||
116 | * oopsing.) | ||
117 | * | ||
118 | * Only set this larger if you really need inb() et.al. to operate over | ||
119 | * a larger address space. Note that SOC_COMMON ioremaps each sockets | ||
120 | * IO space area, and so inb() et.al. must be defined to operate as per | ||
121 | * readb() et.al. on such platforms. | ||
122 | */ | ||
123 | #ifndef IO_SPACE_LIMIT | ||
124 | #if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE) | ||
125 | #define IO_SPACE_LIMIT ((resource_size_t)0xffffffff) | ||
126 | #elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD) | ||
127 | #define IO_SPACE_LIMIT ((resource_size_t)0xffff) | ||
128 | #else | ||
129 | #define IO_SPACE_LIMIT ((resource_size_t)0) | ||
130 | #endif | ||
131 | #endif | ||
132 | |||
133 | /* | ||
113 | * IO port access primitives | 134 | * IO port access primitives |
114 | * ------------------------- | 135 | * ------------------------- |
115 | * | 136 | * |
@@ -260,10 +281,16 @@ extern void _memset_io(volatile void __iomem *, int, size_t); | |||
260 | #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) | 281 | #define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; }) |
261 | #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) | 282 | #define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; }) |
262 | 283 | ||
284 | #define ioread16be(p) ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; }) | ||
285 | #define ioread32be(p) ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; }) | ||
286 | |||
263 | #define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); }) | 287 | #define iowrite8(v,p) ({ __iowmb(); (void)__raw_writeb(v, p); }) |
264 | #define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); }) | 288 | #define iowrite16(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_le16(v), p); }) |
265 | #define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); }) | 289 | #define iowrite32(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_le32(v), p); }) |
266 | 290 | ||
291 | #define iowrite16be(v,p) ({ __iowmb(); (void)__raw_writew((__force __u16)cpu_to_be16(v), p); }) | ||
292 | #define iowrite32be(v,p) ({ __iowmb(); (void)__raw_writel((__force __u32)cpu_to_be32(v), p); }) | ||
293 | |||
267 | #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) | 294 | #define ioread8_rep(p,d,c) __raw_readsb(p,d,c) |
268 | #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) | 295 | #define ioread16_rep(p,d,c) __raw_readsw(p,d,c) |
269 | #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) | 296 | #define ioread32_rep(p,d,c) __raw_readsl(p,d,c) |
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h index ff66638ff54d..6fd955d34c65 100644 --- a/arch/arm/include/asm/localtimer.h +++ b/arch/arm/include/asm/localtimer.h | |||
@@ -24,6 +24,10 @@ void percpu_timer_setup(void); | |||
24 | */ | 24 | */ |
25 | asmlinkage void do_local_timer(struct pt_regs *); | 25 | asmlinkage void do_local_timer(struct pt_regs *); |
26 | 26 | ||
27 | /* | ||
28 | * Called from C code | ||
29 | */ | ||
30 | void handle_local_timer(struct pt_regs *); | ||
27 | 31 | ||
28 | #ifdef CONFIG_LOCAL_TIMERS | 32 | #ifdef CONFIG_LOCAL_TIMERS |
29 | 33 | ||
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h index b8de516e600e..441fc4fe8263 100644 --- a/arch/arm/include/asm/memory.h +++ b/arch/arm/include/asm/memory.h | |||
@@ -160,7 +160,6 @@ | |||
160 | * so that all we need to do is modify the 8-bit constant field. | 160 | * so that all we need to do is modify the 8-bit constant field. |
161 | */ | 161 | */ |
162 | #define __PV_BITS_31_24 0x81000000 | 162 | #define __PV_BITS_31_24 0x81000000 |
163 | #define __PV_BITS_23_16 0x00810000 | ||
164 | 163 | ||
165 | extern unsigned long __pv_phys_offset; | 164 | extern unsigned long __pv_phys_offset; |
166 | #define PHYS_OFFSET __pv_phys_offset | 165 | #define PHYS_OFFSET __pv_phys_offset |
@@ -178,9 +177,6 @@ static inline unsigned long __virt_to_phys(unsigned long x) | |||
178 | { | 177 | { |
179 | unsigned long t; | 178 | unsigned long t; |
180 | __pv_stub(x, t, "add", __PV_BITS_31_24); | 179 | __pv_stub(x, t, "add", __PV_BITS_31_24); |
181 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
182 | __pv_stub(t, t, "add", __PV_BITS_23_16); | ||
183 | #endif | ||
184 | return t; | 180 | return t; |
185 | } | 181 | } |
186 | 182 | ||
@@ -188,9 +184,6 @@ static inline unsigned long __phys_to_virt(unsigned long x) | |||
188 | { | 184 | { |
189 | unsigned long t; | 185 | unsigned long t; |
190 | __pv_stub(x, t, "sub", __PV_BITS_31_24); | 186 | __pv_stub(x, t, "sub", __PV_BITS_31_24); |
191 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
192 | __pv_stub(t, t, "sub", __PV_BITS_23_16); | ||
193 | #endif | ||
194 | return t; | 187 | return t; |
195 | } | 188 | } |
196 | #else | 189 | #else |
diff --git a/arch/arm/include/asm/module.h b/arch/arm/include/asm/module.h index 543b44916d2c..6c6809f982f1 100644 --- a/arch/arm/include/asm/module.h +++ b/arch/arm/include/asm/module.h | |||
@@ -31,11 +31,7 @@ struct mod_arch_specific { | |||
31 | 31 | ||
32 | /* Add __virt_to_phys patching state as well */ | 32 | /* Add __virt_to_phys patching state as well */ |
33 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT | 33 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT |
34 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
35 | #define MODULE_ARCH_VERMAGIC_P2V "p2v16 " | ||
36 | #else | ||
37 | #define MODULE_ARCH_VERMAGIC_P2V "p2v8 " | 34 | #define MODULE_ARCH_VERMAGIC_P2V "p2v8 " |
38 | #endif | ||
39 | #else | 35 | #else |
40 | #define MODULE_ARCH_VERMAGIC_P2V "" | 36 | #define MODULE_ARCH_VERMAGIC_P2V "" |
41 | #endif | 37 | #endif |
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h index d8387437ec5a..53426c66352a 100644 --- a/arch/arm/include/asm/outercache.h +++ b/arch/arm/include/asm/outercache.h | |||
@@ -34,6 +34,7 @@ struct outer_cache_fns { | |||
34 | void (*sync)(void); | 34 | void (*sync)(void); |
35 | #endif | 35 | #endif |
36 | void (*set_debug)(unsigned long); | 36 | void (*set_debug)(unsigned long); |
37 | void (*resume)(void); | ||
37 | }; | 38 | }; |
38 | 39 | ||
39 | #ifdef CONFIG_OUTER_CACHE | 40 | #ifdef CONFIG_OUTER_CACHE |
@@ -74,6 +75,12 @@ static inline void outer_disable(void) | |||
74 | outer_cache.disable(); | 75 | outer_cache.disable(); |
75 | } | 76 | } |
76 | 77 | ||
78 | static inline void outer_resume(void) | ||
79 | { | ||
80 | if (outer_cache.resume) | ||
81 | outer_cache.resume(); | ||
82 | } | ||
83 | |||
77 | #else | 84 | #else |
78 | 85 | ||
79 | static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) | 86 | static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) |
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h index ac75d0848889..ca94653f1ecb 100644 --- a/arch/arm/include/asm/page.h +++ b/arch/arm/include/asm/page.h | |||
@@ -151,47 +151,7 @@ extern void __cpu_copy_user_highpage(struct page *to, struct page *from, | |||
151 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) | 151 | #define clear_page(page) memset((void *)(page), 0, PAGE_SIZE) |
152 | extern void copy_page(void *to, const void *from); | 152 | extern void copy_page(void *to, const void *from); |
153 | 153 | ||
154 | typedef unsigned long pteval_t; | 154 | #include <asm/pgtable-2level-types.h> |
155 | |||
156 | #undef STRICT_MM_TYPECHECKS | ||
157 | |||
158 | #ifdef STRICT_MM_TYPECHECKS | ||
159 | /* | ||
160 | * These are used to make use of C type-checking.. | ||
161 | */ | ||
162 | typedef struct { pteval_t pte; } pte_t; | ||
163 | typedef struct { unsigned long pmd; } pmd_t; | ||
164 | typedef struct { unsigned long pgd[2]; } pgd_t; | ||
165 | typedef struct { unsigned long pgprot; } pgprot_t; | ||
166 | |||
167 | #define pte_val(x) ((x).pte) | ||
168 | #define pmd_val(x) ((x).pmd) | ||
169 | #define pgd_val(x) ((x).pgd[0]) | ||
170 | #define pgprot_val(x) ((x).pgprot) | ||
171 | |||
172 | #define __pte(x) ((pte_t) { (x) } ) | ||
173 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
174 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
175 | |||
176 | #else | ||
177 | /* | ||
178 | * .. while these make it easier on the compiler | ||
179 | */ | ||
180 | typedef pteval_t pte_t; | ||
181 | typedef unsigned long pmd_t; | ||
182 | typedef unsigned long pgd_t[2]; | ||
183 | typedef unsigned long pgprot_t; | ||
184 | |||
185 | #define pte_val(x) (x) | ||
186 | #define pmd_val(x) (x) | ||
187 | #define pgd_val(x) ((x)[0]) | ||
188 | #define pgprot_val(x) (x) | ||
189 | |||
190 | #define __pte(x) (x) | ||
191 | #define __pmd(x) (x) | ||
192 | #define __pgprot(x) (x) | ||
193 | |||
194 | #endif /* STRICT_MM_TYPECHECKS */ | ||
195 | 155 | ||
196 | #endif /* CONFIG_MMU */ | 156 | #endif /* CONFIG_MMU */ |
197 | 157 | ||
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h index 22de005f159c..3e08fd3fbb6b 100644 --- a/arch/arm/include/asm/pgalloc.h +++ b/arch/arm/include/asm/pgalloc.h | |||
@@ -105,9 +105,9 @@ static inline void pte_free(struct mm_struct *mm, pgtable_t pte) | |||
105 | } | 105 | } |
106 | 106 | ||
107 | static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, | 107 | static inline void __pmd_populate(pmd_t *pmdp, phys_addr_t pte, |
108 | unsigned long prot) | 108 | pmdval_t prot) |
109 | { | 109 | { |
110 | unsigned long pmdval = (pte + PTE_HWTABLE_OFF) | prot; | 110 | pmdval_t pmdval = (pte + PTE_HWTABLE_OFF) | prot; |
111 | pmdp[0] = __pmd(pmdval); | 111 | pmdp[0] = __pmd(pmdval); |
112 | pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); | 112 | pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t)); |
113 | flush_pmd_entry(pmdp); | 113 | flush_pmd_entry(pmdp); |
diff --git a/arch/arm/include/asm/pgtable-2level-hwdef.h b/arch/arm/include/asm/pgtable-2level-hwdef.h new file mode 100644 index 000000000000..5cfba15cb401 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-hwdef.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable-2level-hwdef.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASM_PGTABLE_2LEVEL_HWDEF_H | ||
11 | #define _ASM_PGTABLE_2LEVEL_HWDEF_H | ||
12 | |||
13 | /* | ||
14 | * Hardware page table definitions. | ||
15 | * | ||
16 | * + Level 1 descriptor (PMD) | ||
17 | * - common | ||
18 | */ | ||
19 | #define PMD_TYPE_MASK (_AT(pmdval_t, 3) << 0) | ||
20 | #define PMD_TYPE_FAULT (_AT(pmdval_t, 0) << 0) | ||
21 | #define PMD_TYPE_TABLE (_AT(pmdval_t, 1) << 0) | ||
22 | #define PMD_TYPE_SECT (_AT(pmdval_t, 2) << 0) | ||
23 | #define PMD_BIT4 (_AT(pmdval_t, 1) << 4) | ||
24 | #define PMD_DOMAIN(x) (_AT(pmdval_t, (x)) << 5) | ||
25 | #define PMD_PROTECTION (_AT(pmdval_t, 1) << 9) /* v5 */ | ||
26 | /* | ||
27 | * - section | ||
28 | */ | ||
29 | #define PMD_SECT_BUFFERABLE (_AT(pmdval_t, 1) << 2) | ||
30 | #define PMD_SECT_CACHEABLE (_AT(pmdval_t, 1) << 3) | ||
31 | #define PMD_SECT_XN (_AT(pmdval_t, 1) << 4) /* v6 */ | ||
32 | #define PMD_SECT_AP_WRITE (_AT(pmdval_t, 1) << 10) | ||
33 | #define PMD_SECT_AP_READ (_AT(pmdval_t, 1) << 11) | ||
34 | #define PMD_SECT_TEX(x) (_AT(pmdval_t, (x)) << 12) /* v5 */ | ||
35 | #define PMD_SECT_APX (_AT(pmdval_t, 1) << 15) /* v6 */ | ||
36 | #define PMD_SECT_S (_AT(pmdval_t, 1) << 16) /* v6 */ | ||
37 | #define PMD_SECT_nG (_AT(pmdval_t, 1) << 17) /* v6 */ | ||
38 | #define PMD_SECT_SUPER (_AT(pmdval_t, 1) << 18) /* v6 */ | ||
39 | #define PMD_SECT_AF (_AT(pmdval_t, 0)) | ||
40 | |||
41 | #define PMD_SECT_UNCACHED (_AT(pmdval_t, 0)) | ||
42 | #define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) | ||
43 | #define PMD_SECT_WT (PMD_SECT_CACHEABLE) | ||
44 | #define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
45 | #define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) | ||
46 | #define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
47 | #define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) | ||
48 | |||
49 | /* | ||
50 | * - coarse table (not used) | ||
51 | */ | ||
52 | |||
53 | /* | ||
54 | * + Level 2 descriptor (PTE) | ||
55 | * - common | ||
56 | */ | ||
57 | #define PTE_TYPE_MASK (_AT(pteval_t, 3) << 0) | ||
58 | #define PTE_TYPE_FAULT (_AT(pteval_t, 0) << 0) | ||
59 | #define PTE_TYPE_LARGE (_AT(pteval_t, 1) << 0) | ||
60 | #define PTE_TYPE_SMALL (_AT(pteval_t, 2) << 0) | ||
61 | #define PTE_TYPE_EXT (_AT(pteval_t, 3) << 0) /* v5 */ | ||
62 | #define PTE_BUFFERABLE (_AT(pteval_t, 1) << 2) | ||
63 | #define PTE_CACHEABLE (_AT(pteval_t, 1) << 3) | ||
64 | |||
65 | /* | ||
66 | * - extended small page/tiny page | ||
67 | */ | ||
68 | #define PTE_EXT_XN (_AT(pteval_t, 1) << 0) /* v6 */ | ||
69 | #define PTE_EXT_AP_MASK (_AT(pteval_t, 3) << 4) | ||
70 | #define PTE_EXT_AP0 (_AT(pteval_t, 1) << 4) | ||
71 | #define PTE_EXT_AP1 (_AT(pteval_t, 2) << 4) | ||
72 | #define PTE_EXT_AP_UNO_SRO (_AT(pteval_t, 0) << 4) | ||
73 | #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) | ||
74 | #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) | ||
75 | #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) | ||
76 | #define PTE_EXT_TEX(x) (_AT(pteval_t, (x)) << 6) /* v5 */ | ||
77 | #define PTE_EXT_APX (_AT(pteval_t, 1) << 9) /* v6 */ | ||
78 | #define PTE_EXT_COHERENT (_AT(pteval_t, 1) << 9) /* XScale3 */ | ||
79 | #define PTE_EXT_SHARED (_AT(pteval_t, 1) << 10) /* v6 */ | ||
80 | #define PTE_EXT_NG (_AT(pteval_t, 1) << 11) /* v6 */ | ||
81 | |||
82 | /* | ||
83 | * - small page | ||
84 | */ | ||
85 | #define PTE_SMALL_AP_MASK (_AT(pteval_t, 0xff) << 4) | ||
86 | #define PTE_SMALL_AP_UNO_SRO (_AT(pteval_t, 0x00) << 4) | ||
87 | #define PTE_SMALL_AP_UNO_SRW (_AT(pteval_t, 0x55) << 4) | ||
88 | #define PTE_SMALL_AP_URO_SRW (_AT(pteval_t, 0xaa) << 4) | ||
89 | #define PTE_SMALL_AP_URW_SRW (_AT(pteval_t, 0xff) << 4) | ||
90 | |||
91 | #define PHYS_MASK (~0UL) | ||
92 | |||
93 | #endif | ||
diff --git a/arch/arm/include/asm/pgtable-2level-types.h b/arch/arm/include/asm/pgtable-2level-types.h new file mode 100644 index 000000000000..66cb5b0e89c5 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level-types.h | |||
@@ -0,0 +1,67 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable-2level-types.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2003 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
18 | */ | ||
19 | #ifndef _ASM_PGTABLE_2LEVEL_TYPES_H | ||
20 | #define _ASM_PGTABLE_2LEVEL_TYPES_H | ||
21 | |||
22 | #include <asm/types.h> | ||
23 | |||
24 | typedef u32 pteval_t; | ||
25 | typedef u32 pmdval_t; | ||
26 | |||
27 | #undef STRICT_MM_TYPECHECKS | ||
28 | |||
29 | #ifdef STRICT_MM_TYPECHECKS | ||
30 | /* | ||
31 | * These are used to make use of C type-checking.. | ||
32 | */ | ||
33 | typedef struct { pteval_t pte; } pte_t; | ||
34 | typedef struct { pmdval_t pmd; } pmd_t; | ||
35 | typedef struct { pmdval_t pgd[2]; } pgd_t; | ||
36 | typedef struct { pteval_t pgprot; } pgprot_t; | ||
37 | |||
38 | #define pte_val(x) ((x).pte) | ||
39 | #define pmd_val(x) ((x).pmd) | ||
40 | #define pgd_val(x) ((x).pgd[0]) | ||
41 | #define pgprot_val(x) ((x).pgprot) | ||
42 | |||
43 | #define __pte(x) ((pte_t) { (x) } ) | ||
44 | #define __pmd(x) ((pmd_t) { (x) } ) | ||
45 | #define __pgprot(x) ((pgprot_t) { (x) } ) | ||
46 | |||
47 | #else | ||
48 | /* | ||
49 | * .. while these make it easier on the compiler | ||
50 | */ | ||
51 | typedef pteval_t pte_t; | ||
52 | typedef pmdval_t pmd_t; | ||
53 | typedef pmdval_t pgd_t[2]; | ||
54 | typedef pteval_t pgprot_t; | ||
55 | |||
56 | #define pte_val(x) (x) | ||
57 | #define pmd_val(x) (x) | ||
58 | #define pgd_val(x) ((x)[0]) | ||
59 | #define pgprot_val(x) (x) | ||
60 | |||
61 | #define __pte(x) (x) | ||
62 | #define __pmd(x) (x) | ||
63 | #define __pgprot(x) (x) | ||
64 | |||
65 | #endif /* STRICT_MM_TYPECHECKS */ | ||
66 | |||
67 | #endif /* _ASM_PGTABLE_2LEVEL_TYPES_H */ | ||
diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h new file mode 100644 index 000000000000..470457e1cfc5 --- /dev/null +++ b/arch/arm/include/asm/pgtable-2level.h | |||
@@ -0,0 +1,143 @@ | |||
1 | /* | ||
2 | * arch/arm/include/asm/pgtable-2level.h | ||
3 | * | ||
4 | * Copyright (C) 1995-2002 Russell King | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | #ifndef _ASM_PGTABLE_2LEVEL_H | ||
11 | #define _ASM_PGTABLE_2LEVEL_H | ||
12 | |||
13 | /* | ||
14 | * Hardware-wise, we have a two level page table structure, where the first | ||
15 | * level has 4096 entries, and the second level has 256 entries. Each entry | ||
16 | * is one 32-bit word. Most of the bits in the second level entry are used | ||
17 | * by hardware, and there aren't any "accessed" and "dirty" bits. | ||
18 | * | ||
19 | * Linux on the other hand has a three level page table structure, which can | ||
20 | * be wrapped to fit a two level page table structure easily - using the PGD | ||
21 | * and PTE only. However, Linux also expects one "PTE" table per page, and | ||
22 | * at least a "dirty" bit. | ||
23 | * | ||
24 | * Therefore, we tweak the implementation slightly - we tell Linux that we | ||
25 | * have 2048 entries in the first level, each of which is 8 bytes (iow, two | ||
26 | * hardware pointers to the second level.) The second level contains two | ||
27 | * hardware PTE tables arranged contiguously, preceded by Linux versions | ||
28 | * which contain the state information Linux needs. We, therefore, end up | ||
29 | * with 512 entries in the "PTE" level. | ||
30 | * | ||
31 | * This leads to the page tables having the following layout: | ||
32 | * | ||
33 | * pgd pte | ||
34 | * | | | ||
35 | * +--------+ | ||
36 | * | | +------------+ +0 | ||
37 | * +- - - - + | Linux pt 0 | | ||
38 | * | | +------------+ +1024 | ||
39 | * +--------+ +0 | Linux pt 1 | | ||
40 | * | |-----> +------------+ +2048 | ||
41 | * +- - - - + +4 | h/w pt 0 | | ||
42 | * | |-----> +------------+ +3072 | ||
43 | * +--------+ +8 | h/w pt 1 | | ||
44 | * | | +------------+ +4096 | ||
45 | * | ||
46 | * See L_PTE_xxx below for definitions of bits in the "Linux pt", and | ||
47 | * PTE_xxx for definitions of bits appearing in the "h/w pt". | ||
48 | * | ||
49 | * PMD_xxx definitions refer to bits in the first level page table. | ||
50 | * | ||
51 | * The "dirty" bit is emulated by only granting hardware write permission | ||
52 | * iff the page is marked "writable" and "dirty" in the Linux PTE. This | ||
53 | * means that a write to a clean page will cause a permission fault, and | ||
54 | * the Linux MM layer will mark the page dirty via handle_pte_fault(). | ||
55 | * For the hardware to notice the permission change, the TLB entry must | ||
56 | * be flushed, and ptep_set_access_flags() does that for us. | ||
57 | * | ||
58 | * The "accessed" or "young" bit is emulated by a similar method; we only | ||
59 | * allow accesses to the page if the "young" bit is set. Accesses to the | ||
60 | * page will cause a fault, and handle_pte_fault() will set the young bit | ||
61 | * for us as long as the page is marked present in the corresponding Linux | ||
62 | * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is | ||
63 | * up to date. | ||
64 | * | ||
65 | * However, when the "young" bit is cleared, we deny access to the page | ||
66 | * by clearing the hardware PTE. Currently Linux does not flush the TLB | ||
67 | * for us in this case, which means the TLB will retain the transation | ||
68 | * until either the TLB entry is evicted under pressure, or a context | ||
69 | * switch which changes the user space mapping occurs. | ||
70 | */ | ||
71 | #define PTRS_PER_PTE 512 | ||
72 | #define PTRS_PER_PMD 1 | ||
73 | #define PTRS_PER_PGD 2048 | ||
74 | |||
75 | #define PTE_HWTABLE_PTRS (PTRS_PER_PTE) | ||
76 | #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) | ||
77 | #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) | ||
78 | |||
79 | /* | ||
80 | * PMD_SHIFT determines the size of the area a second-level page table can map | ||
81 | * PGDIR_SHIFT determines what a third-level page table entry can map | ||
82 | */ | ||
83 | #define PMD_SHIFT 21 | ||
84 | #define PGDIR_SHIFT 21 | ||
85 | |||
86 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
87 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
88 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
89 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
90 | |||
91 | /* | ||
92 | * section address mask and size definitions. | ||
93 | */ | ||
94 | #define SECTION_SHIFT 20 | ||
95 | #define SECTION_SIZE (1UL << SECTION_SHIFT) | ||
96 | #define SECTION_MASK (~(SECTION_SIZE-1)) | ||
97 | |||
98 | /* | ||
99 | * ARMv6 supersection address mask and size definitions. | ||
100 | */ | ||
101 | #define SUPERSECTION_SHIFT 24 | ||
102 | #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) | ||
103 | #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) | ||
104 | |||
105 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) | ||
106 | |||
107 | /* | ||
108 | * "Linux" PTE definitions. | ||
109 | * | ||
110 | * We keep two sets of PTEs - the hardware and the linux version. | ||
111 | * This allows greater flexibility in the way we map the Linux bits | ||
112 | * onto the hardware tables, and allows us to have YOUNG and DIRTY | ||
113 | * bits. | ||
114 | * | ||
115 | * The PTE table pointer refers to the hardware entries; the "Linux" | ||
116 | * entries are stored 1024 bytes below. | ||
117 | */ | ||
118 | #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) | ||
119 | #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) | ||
120 | #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ | ||
121 | #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) | ||
122 | #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) | ||
123 | #define L_PTE_USER (_AT(pteval_t, 1) << 8) | ||
124 | #define L_PTE_XN (_AT(pteval_t, 1) << 9) | ||
125 | #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ | ||
126 | |||
127 | /* | ||
128 | * These are the memory types, defined to be compatible with | ||
129 | * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB | ||
130 | */ | ||
131 | #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ | ||
132 | #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ | ||
133 | #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ | ||
134 | #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ | ||
135 | #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ | ||
136 | #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ | ||
137 | #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ | ||
138 | #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ | ||
139 | #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ | ||
140 | #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ | ||
141 | #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) | ||
142 | |||
143 | #endif /* _ASM_PGTABLE_2LEVEL_H */ | ||
diff --git a/arch/arm/include/asm/pgtable-hwdef.h b/arch/arm/include/asm/pgtable-hwdef.h index fd1521d5cb9d..183111164ce9 100644 --- a/arch/arm/include/asm/pgtable-hwdef.h +++ b/arch/arm/include/asm/pgtable-hwdef.h | |||
@@ -10,81 +10,6 @@ | |||
10 | #ifndef _ASMARM_PGTABLE_HWDEF_H | 10 | #ifndef _ASMARM_PGTABLE_HWDEF_H |
11 | #define _ASMARM_PGTABLE_HWDEF_H | 11 | #define _ASMARM_PGTABLE_HWDEF_H |
12 | 12 | ||
13 | /* | 13 | #include <asm/pgtable-2level-hwdef.h> |
14 | * Hardware page table definitions. | ||
15 | * | ||
16 | * + Level 1 descriptor (PMD) | ||
17 | * - common | ||
18 | */ | ||
19 | #define PMD_TYPE_MASK (3 << 0) | ||
20 | #define PMD_TYPE_FAULT (0 << 0) | ||
21 | #define PMD_TYPE_TABLE (1 << 0) | ||
22 | #define PMD_TYPE_SECT (2 << 0) | ||
23 | #define PMD_BIT4 (1 << 4) | ||
24 | #define PMD_DOMAIN(x) ((x) << 5) | ||
25 | #define PMD_PROTECTION (1 << 9) /* v5 */ | ||
26 | /* | ||
27 | * - section | ||
28 | */ | ||
29 | #define PMD_SECT_BUFFERABLE (1 << 2) | ||
30 | #define PMD_SECT_CACHEABLE (1 << 3) | ||
31 | #define PMD_SECT_XN (1 << 4) /* v6 */ | ||
32 | #define PMD_SECT_AP_WRITE (1 << 10) | ||
33 | #define PMD_SECT_AP_READ (1 << 11) | ||
34 | #define PMD_SECT_TEX(x) ((x) << 12) /* v5 */ | ||
35 | #define PMD_SECT_APX (1 << 15) /* v6 */ | ||
36 | #define PMD_SECT_S (1 << 16) /* v6 */ | ||
37 | #define PMD_SECT_nG (1 << 17) /* v6 */ | ||
38 | #define PMD_SECT_SUPER (1 << 18) /* v6 */ | ||
39 | |||
40 | #define PMD_SECT_UNCACHED (0) | ||
41 | #define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE) | ||
42 | #define PMD_SECT_WT (PMD_SECT_CACHEABLE) | ||
43 | #define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
44 | #define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE) | ||
45 | #define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE) | ||
46 | #define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2)) | ||
47 | |||
48 | /* | ||
49 | * - coarse table (not used) | ||
50 | */ | ||
51 | |||
52 | /* | ||
53 | * + Level 2 descriptor (PTE) | ||
54 | * - common | ||
55 | */ | ||
56 | #define PTE_TYPE_MASK (3 << 0) | ||
57 | #define PTE_TYPE_FAULT (0 << 0) | ||
58 | #define PTE_TYPE_LARGE (1 << 0) | ||
59 | #define PTE_TYPE_SMALL (2 << 0) | ||
60 | #define PTE_TYPE_EXT (3 << 0) /* v5 */ | ||
61 | #define PTE_BUFFERABLE (1 << 2) | ||
62 | #define PTE_CACHEABLE (1 << 3) | ||
63 | |||
64 | /* | ||
65 | * - extended small page/tiny page | ||
66 | */ | ||
67 | #define PTE_EXT_XN (1 << 0) /* v6 */ | ||
68 | #define PTE_EXT_AP_MASK (3 << 4) | ||
69 | #define PTE_EXT_AP0 (1 << 4) | ||
70 | #define PTE_EXT_AP1 (2 << 4) | ||
71 | #define PTE_EXT_AP_UNO_SRO (0 << 4) | ||
72 | #define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0) | ||
73 | #define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1) | ||
74 | #define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0) | ||
75 | #define PTE_EXT_TEX(x) ((x) << 6) /* v5 */ | ||
76 | #define PTE_EXT_APX (1 << 9) /* v6 */ | ||
77 | #define PTE_EXT_COHERENT (1 << 9) /* XScale3 */ | ||
78 | #define PTE_EXT_SHARED (1 << 10) /* v6 */ | ||
79 | #define PTE_EXT_NG (1 << 11) /* v6 */ | ||
80 | |||
81 | /* | ||
82 | * - small page | ||
83 | */ | ||
84 | #define PTE_SMALL_AP_MASK (0xff << 4) | ||
85 | #define PTE_SMALL_AP_UNO_SRO (0x00 << 4) | ||
86 | #define PTE_SMALL_AP_UNO_SRW (0x55 << 4) | ||
87 | #define PTE_SMALL_AP_URO_SRW (0xaa << 4) | ||
88 | #define PTE_SMALL_AP_URW_SRW (0xff << 4) | ||
89 | 14 | ||
90 | #endif | 15 | #endif |
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h index 5750704e0271..8ade1840c6f2 100644 --- a/arch/arm/include/asm/pgtable.h +++ b/arch/arm/include/asm/pgtable.h | |||
@@ -24,6 +24,8 @@ | |||
24 | #include <mach/vmalloc.h> | 24 | #include <mach/vmalloc.h> |
25 | #include <asm/pgtable-hwdef.h> | 25 | #include <asm/pgtable-hwdef.h> |
26 | 26 | ||
27 | #include <asm/pgtable-2level.h> | ||
28 | |||
27 | /* | 29 | /* |
28 | * Just any arbitrary offset to the start of the vmalloc VM area: the | 30 | * Just any arbitrary offset to the start of the vmalloc VM area: the |
29 | * current 8MB value just means that there will be a 8MB "hole" after the | 31 | * current 8MB value just means that there will be a 8MB "hole" after the |
@@ -41,79 +43,6 @@ | |||
41 | #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) | 43 | #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) |
42 | #endif | 44 | #endif |
43 | 45 | ||
44 | /* | ||
45 | * Hardware-wise, we have a two level page table structure, where the first | ||
46 | * level has 4096 entries, and the second level has 256 entries. Each entry | ||
47 | * is one 32-bit word. Most of the bits in the second level entry are used | ||
48 | * by hardware, and there aren't any "accessed" and "dirty" bits. | ||
49 | * | ||
50 | * Linux on the other hand has a three level page table structure, which can | ||
51 | * be wrapped to fit a two level page table structure easily - using the PGD | ||
52 | * and PTE only. However, Linux also expects one "PTE" table per page, and | ||
53 | * at least a "dirty" bit. | ||
54 | * | ||
55 | * Therefore, we tweak the implementation slightly - we tell Linux that we | ||
56 | * have 2048 entries in the first level, each of which is 8 bytes (iow, two | ||
57 | * hardware pointers to the second level.) The second level contains two | ||
58 | * hardware PTE tables arranged contiguously, preceded by Linux versions | ||
59 | * which contain the state information Linux needs. We, therefore, end up | ||
60 | * with 512 entries in the "PTE" level. | ||
61 | * | ||
62 | * This leads to the page tables having the following layout: | ||
63 | * | ||
64 | * pgd pte | ||
65 | * | | | ||
66 | * +--------+ | ||
67 | * | | +------------+ +0 | ||
68 | * +- - - - + | Linux pt 0 | | ||
69 | * | | +------------+ +1024 | ||
70 | * +--------+ +0 | Linux pt 1 | | ||
71 | * | |-----> +------------+ +2048 | ||
72 | * +- - - - + +4 | h/w pt 0 | | ||
73 | * | |-----> +------------+ +3072 | ||
74 | * +--------+ +8 | h/w pt 1 | | ||
75 | * | | +------------+ +4096 | ||
76 | * | ||
77 | * See L_PTE_xxx below for definitions of bits in the "Linux pt", and | ||
78 | * PTE_xxx for definitions of bits appearing in the "h/w pt". | ||
79 | * | ||
80 | * PMD_xxx definitions refer to bits in the first level page table. | ||
81 | * | ||
82 | * The "dirty" bit is emulated by only granting hardware write permission | ||
83 | * iff the page is marked "writable" and "dirty" in the Linux PTE. This | ||
84 | * means that a write to a clean page will cause a permission fault, and | ||
85 | * the Linux MM layer will mark the page dirty via handle_pte_fault(). | ||
86 | * For the hardware to notice the permission change, the TLB entry must | ||
87 | * be flushed, and ptep_set_access_flags() does that for us. | ||
88 | * | ||
89 | * The "accessed" or "young" bit is emulated by a similar method; we only | ||
90 | * allow accesses to the page if the "young" bit is set. Accesses to the | ||
91 | * page will cause a fault, and handle_pte_fault() will set the young bit | ||
92 | * for us as long as the page is marked present in the corresponding Linux | ||
93 | * PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is | ||
94 | * up to date. | ||
95 | * | ||
96 | * However, when the "young" bit is cleared, we deny access to the page | ||
97 | * by clearing the hardware PTE. Currently Linux does not flush the TLB | ||
98 | * for us in this case, which means the TLB will retain the transation | ||
99 | * until either the TLB entry is evicted under pressure, or a context | ||
100 | * switch which changes the user space mapping occurs. | ||
101 | */ | ||
102 | #define PTRS_PER_PTE 512 | ||
103 | #define PTRS_PER_PMD 1 | ||
104 | #define PTRS_PER_PGD 2048 | ||
105 | |||
106 | #define PTE_HWTABLE_PTRS (PTRS_PER_PTE) | ||
107 | #define PTE_HWTABLE_OFF (PTE_HWTABLE_PTRS * sizeof(pte_t)) | ||
108 | #define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u32)) | ||
109 | |||
110 | /* | ||
111 | * PMD_SHIFT determines the size of the area a second-level page table can map | ||
112 | * PGDIR_SHIFT determines what a third-level page table entry can map | ||
113 | */ | ||
114 | #define PMD_SHIFT 21 | ||
115 | #define PGDIR_SHIFT 21 | ||
116 | |||
117 | #define LIBRARY_TEXT_START 0x0c000000 | 46 | #define LIBRARY_TEXT_START 0x0c000000 |
118 | 47 | ||
119 | #ifndef __ASSEMBLY__ | 48 | #ifndef __ASSEMBLY__ |
@@ -124,12 +53,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); | |||
124 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) | 53 | #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte) |
125 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) | 54 | #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd) |
126 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) | 55 | #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd) |
127 | #endif /* !__ASSEMBLY__ */ | ||
128 | |||
129 | #define PMD_SIZE (1UL << PMD_SHIFT) | ||
130 | #define PMD_MASK (~(PMD_SIZE-1)) | ||
131 | #define PGDIR_SIZE (1UL << PGDIR_SHIFT) | ||
132 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | ||
133 | 56 | ||
134 | /* | 57 | /* |
135 | * This is the lowest virtual address we can permit any user space | 58 | * This is the lowest virtual address we can permit any user space |
@@ -138,60 +61,6 @@ extern void __pgd_error(const char *file, int line, pgd_t); | |||
138 | */ | 61 | */ |
139 | #define FIRST_USER_ADDRESS PAGE_SIZE | 62 | #define FIRST_USER_ADDRESS PAGE_SIZE |
140 | 63 | ||
141 | #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) | ||
142 | |||
143 | /* | ||
144 | * section address mask and size definitions. | ||
145 | */ | ||
146 | #define SECTION_SHIFT 20 | ||
147 | #define SECTION_SIZE (1UL << SECTION_SHIFT) | ||
148 | #define SECTION_MASK (~(SECTION_SIZE-1)) | ||
149 | |||
150 | /* | ||
151 | * ARMv6 supersection address mask and size definitions. | ||
152 | */ | ||
153 | #define SUPERSECTION_SHIFT 24 | ||
154 | #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT) | ||
155 | #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) | ||
156 | |||
157 | /* | ||
158 | * "Linux" PTE definitions. | ||
159 | * | ||
160 | * We keep two sets of PTEs - the hardware and the linux version. | ||
161 | * This allows greater flexibility in the way we map the Linux bits | ||
162 | * onto the hardware tables, and allows us to have YOUNG and DIRTY | ||
163 | * bits. | ||
164 | * | ||
165 | * The PTE table pointer refers to the hardware entries; the "Linux" | ||
166 | * entries are stored 1024 bytes below. | ||
167 | */ | ||
168 | #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) | ||
169 | #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) | ||
170 | #define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */ | ||
171 | #define L_PTE_DIRTY (_AT(pteval_t, 1) << 6) | ||
172 | #define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) | ||
173 | #define L_PTE_USER (_AT(pteval_t, 1) << 8) | ||
174 | #define L_PTE_XN (_AT(pteval_t, 1) << 9) | ||
175 | #define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */ | ||
176 | |||
177 | /* | ||
178 | * These are the memory types, defined to be compatible with | ||
179 | * pre-ARMv6 CPUs cacheable and bufferable bits: XXCB | ||
180 | */ | ||
181 | #define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */ | ||
182 | #define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */ | ||
183 | #define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */ | ||
184 | #define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */ | ||
185 | #define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */ | ||
186 | #define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */ | ||
187 | #define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */ | ||
188 | #define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */ | ||
189 | #define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */ | ||
190 | #define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */ | ||
191 | #define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2) | ||
192 | |||
193 | #ifndef __ASSEMBLY__ | ||
194 | |||
195 | /* | 64 | /* |
196 | * The pgprot_* and protection_map entries will be fixed up in runtime | 65 | * The pgprot_* and protection_map entries will be fixed up in runtime |
197 | * to include the cachable and bufferable bits based on memory policy, | 66 | * to include the cachable and bufferable bits based on memory policy, |
@@ -327,10 +196,10 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; | |||
327 | 196 | ||
328 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) | 197 | static inline pte_t *pmd_page_vaddr(pmd_t pmd) |
329 | { | 198 | { |
330 | return __va(pmd_val(pmd) & PAGE_MASK); | 199 | return __va(pmd_val(pmd) & PHYS_MASK & (s32)PAGE_MASK); |
331 | } | 200 | } |
332 | 201 | ||
333 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd))) | 202 | #define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd) & PHYS_MASK)) |
334 | 203 | ||
335 | /* we don't need complex calculations here as the pmd is folded into the pgd */ | 204 | /* we don't need complex calculations here as the pmd is folded into the pgd */ |
336 | #define pmd_addr_end(addr,end) (end) | 205 | #define pmd_addr_end(addr,end) (end) |
@@ -351,7 +220,7 @@ static inline pte_t *pmd_page_vaddr(pmd_t pmd) | |||
351 | #define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) | 220 | #define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr)) |
352 | #define pte_unmap(pte) __pte_unmap(pte) | 221 | #define pte_unmap(pte) __pte_unmap(pte) |
353 | 222 | ||
354 | #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) | 223 | #define pte_pfn(pte) ((pte_val(pte) & PHYS_MASK) >> PAGE_SHIFT) |
355 | #define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) | 224 | #define pfn_pte(pfn,prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot)) |
356 | 225 | ||
357 | #define pte_page(pte) pfn_to_page(pte_pfn(pte)) | 226 | #define pte_page(pte) pfn_to_page(pte_pfn(pte)) |
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h index e42d96a45d3e..0a17b62538c2 100644 --- a/arch/arm/include/asm/smp.h +++ b/arch/arm/include/asm/smp.h | |||
@@ -33,6 +33,11 @@ extern void show_ipi_list(struct seq_file *, int); | |||
33 | asmlinkage void do_IPI(int ipinr, struct pt_regs *regs); | 33 | asmlinkage void do_IPI(int ipinr, struct pt_regs *regs); |
34 | 34 | ||
35 | /* | 35 | /* |
36 | * Called from C code, this handles an IPI. | ||
37 | */ | ||
38 | void handle_IPI(int ipinr, struct pt_regs *regs); | ||
39 | |||
40 | /* | ||
36 | * Setup the set of possible CPUs (via set_cpu_possible) | 41 | * Setup the set of possible CPUs (via set_cpu_possible) |
37 | */ | 42 | */ |
38 | extern void smp_init_cpus(void); | 43 | extern void smp_init_cpus(void); |
@@ -66,6 +71,12 @@ extern void platform_secondary_init(unsigned int cpu); | |||
66 | extern void platform_smp_prepare_cpus(unsigned int); | 71 | extern void platform_smp_prepare_cpus(unsigned int); |
67 | 72 | ||
68 | /* | 73 | /* |
74 | * Logical CPU mapping. | ||
75 | */ | ||
76 | extern int __cpu_logical_map[NR_CPUS]; | ||
77 | #define cpu_logical_map(cpu) __cpu_logical_map[cpu] | ||
78 | |||
79 | /* | ||
69 | * Initial data for bringing up a secondary CPU. | 80 | * Initial data for bringing up a secondary CPU. |
70 | */ | 81 | */ |
71 | struct secondary_data { | 82 | struct secondary_data { |
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 832888d0c20c..ed6b0499a106 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h | |||
@@ -62,13 +62,6 @@ | |||
62 | 62 | ||
63 | #include <asm/outercache.h> | 63 | #include <asm/outercache.h> |
64 | 64 | ||
65 | #define __exception __attribute__((section(".exception.text"))) | ||
66 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER | ||
67 | #define __exception_irq_entry __irq_entry | ||
68 | #else | ||
69 | #define __exception_irq_entry __exception | ||
70 | #endif | ||
71 | |||
72 | struct thread_info; | 65 | struct thread_info; |
73 | struct task_struct; | 66 | struct task_struct; |
74 | 67 | ||
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h index 8077145698ff..02b2f8203982 100644 --- a/arch/arm/include/asm/tlbflush.h +++ b/arch/arm/include/asm/tlbflush.h | |||
@@ -471,7 +471,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
471 | * these operations. This is typically used when we are removing | 471 | * these operations. This is typically used when we are removing |
472 | * PMD entries. | 472 | * PMD entries. |
473 | */ | 473 | */ |
474 | static inline void flush_pmd_entry(pmd_t *pmd) | 474 | static inline void flush_pmd_entry(void *pmd) |
475 | { | 475 | { |
476 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 476 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
477 | 477 | ||
@@ -487,7 +487,7 @@ static inline void flush_pmd_entry(pmd_t *pmd) | |||
487 | dsb(); | 487 | dsb(); |
488 | } | 488 | } |
489 | 489 | ||
490 | static inline void clean_pmd_entry(pmd_t *pmd) | 490 | static inline void clean_pmd_entry(void *pmd) |
491 | { | 491 | { |
492 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 492 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
493 | 493 | ||
diff --git a/arch/arm/include/asm/topology.h b/arch/arm/include/asm/topology.h index accbd7cad9b5..a7e457ed27c3 100644 --- a/arch/arm/include/asm/topology.h +++ b/arch/arm/include/asm/topology.h | |||
@@ -1,6 +1,39 @@ | |||
1 | #ifndef _ASM_ARM_TOPOLOGY_H | 1 | #ifndef _ASM_ARM_TOPOLOGY_H |
2 | #define _ASM_ARM_TOPOLOGY_H | 2 | #define _ASM_ARM_TOPOLOGY_H |
3 | 3 | ||
4 | #ifdef CONFIG_ARM_CPU_TOPOLOGY | ||
5 | |||
6 | #include <linux/cpumask.h> | ||
7 | |||
8 | struct cputopo_arm { | ||
9 | int thread_id; | ||
10 | int core_id; | ||
11 | int socket_id; | ||
12 | cpumask_t thread_sibling; | ||
13 | cpumask_t core_sibling; | ||
14 | }; | ||
15 | |||
16 | extern struct cputopo_arm cpu_topology[NR_CPUS]; | ||
17 | |||
18 | #define topology_physical_package_id(cpu) (cpu_topology[cpu].socket_id) | ||
19 | #define topology_core_id(cpu) (cpu_topology[cpu].core_id) | ||
20 | #define topology_core_cpumask(cpu) (&cpu_topology[cpu].core_sibling) | ||
21 | #define topology_thread_cpumask(cpu) (&cpu_topology[cpu].thread_sibling) | ||
22 | |||
23 | #define mc_capable() (cpu_topology[0].socket_id != -1) | ||
24 | #define smt_capable() (cpu_topology[0].thread_id != -1) | ||
25 | |||
26 | void init_cpu_topology(void); | ||
27 | void store_cpu_topology(unsigned int cpuid); | ||
28 | const struct cpumask *cpu_coregroup_mask(unsigned int cpu); | ||
29 | |||
30 | #else | ||
31 | |||
32 | static inline void init_cpu_topology(void) { } | ||
33 | static inline void store_cpu_topology(unsigned int cpuid) { } | ||
34 | |||
35 | #endif | ||
36 | |||
4 | #include <asm-generic/topology.h> | 37 | #include <asm-generic/topology.h> |
5 | 38 | ||
6 | #endif /* _ASM_ARM_TOPOLOGY_H */ | 39 | #endif /* _ASM_ARM_TOPOLOGY_H */ |
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index f7887dc53c1f..68036eece340 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile | |||
@@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o | |||
29 | obj-$(CONFIG_ARTHUR) += arthur.o | 29 | obj-$(CONFIG_ARTHUR) += arthur.o |
30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o | 30 | obj-$(CONFIG_ISA_DMA) += dma-isa.o |
31 | obj-$(CONFIG_PCI) += bios32.o isa.o | 31 | obj-$(CONFIG_PCI) += bios32.o isa.o |
32 | obj-$(CONFIG_PM_SLEEP) += sleep.o | 32 | obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o |
33 | obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o | 33 | obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o |
34 | obj-$(CONFIG_SMP) += smp.o smp_tlb.o | 34 | obj-$(CONFIG_SMP) += smp.o smp_tlb.o |
35 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o | 35 | obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o |
@@ -66,6 +66,7 @@ obj-$(CONFIG_IWMMXT) += iwmmxt.o | |||
66 | obj-$(CONFIG_CPU_HAS_PMU) += pmu.o | 66 | obj-$(CONFIG_CPU_HAS_PMU) += pmu.o |
67 | obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o | 67 | obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o |
68 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt | 68 | AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt |
69 | obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o | ||
69 | 70 | ||
70 | ifneq ($(CONFIG_ARCH_EBSA110),y) | 71 | ifneq ($(CONFIG_ARCH_EBSA110),y) |
71 | obj-y += io.o | 72 | obj-y += io.o |
diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 16baba2e4369..1429d8989fb9 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/thread_info.h> | 20 | #include <asm/thread_info.h> |
21 | #include <asm/memory.h> | 21 | #include <asm/memory.h> |
22 | #include <asm/procinfo.h> | 22 | #include <asm/procinfo.h> |
23 | #include <asm/hardware/cache-l2x0.h> | ||
23 | #include <linux/kbuild.h> | 24 | #include <linux/kbuild.h> |
24 | 25 | ||
25 | /* | 26 | /* |
@@ -92,6 +93,17 @@ int main(void) | |||
92 | DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); | 93 | DEFINE(S_OLD_R0, offsetof(struct pt_regs, ARM_ORIG_r0)); |
93 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); | 94 | DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs)); |
94 | BLANK(); | 95 | BLANK(); |
96 | #ifdef CONFIG_CACHE_L2X0 | ||
97 | DEFINE(L2X0_R_PHY_BASE, offsetof(struct l2x0_regs, phy_base)); | ||
98 | DEFINE(L2X0_R_AUX_CTRL, offsetof(struct l2x0_regs, aux_ctrl)); | ||
99 | DEFINE(L2X0_R_TAG_LATENCY, offsetof(struct l2x0_regs, tag_latency)); | ||
100 | DEFINE(L2X0_R_DATA_LATENCY, offsetof(struct l2x0_regs, data_latency)); | ||
101 | DEFINE(L2X0_R_FILTER_START, offsetof(struct l2x0_regs, filter_start)); | ||
102 | DEFINE(L2X0_R_FILTER_END, offsetof(struct l2x0_regs, filter_end)); | ||
103 | DEFINE(L2X0_R_PREFETCH_CTRL, offsetof(struct l2x0_regs, prefetch_ctrl)); | ||
104 | DEFINE(L2X0_R_PWR_CTRL, offsetof(struct l2x0_regs, pwr_ctrl)); | ||
105 | BLANK(); | ||
106 | #endif | ||
95 | #ifdef CONFIG_CPU_HAS_ASID | 107 | #ifdef CONFIG_CPU_HAS_ASID |
96 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); | 108 | DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id)); |
97 | BLANK(); | 109 | BLANK(); |
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c index d6df359408f0..c0d9203fc75e 100644 --- a/arch/arm/kernel/bios32.c +++ b/arch/arm/kernel/bios32.c | |||
@@ -412,6 +412,9 @@ void pcibios_fixup_bus(struct pci_bus *bus) | |||
412 | printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", | 412 | printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n", |
413 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); | 413 | bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis"); |
414 | } | 414 | } |
415 | #ifdef CONFIG_HOTPLUG | ||
416 | EXPORT_SYMBOL(pcibios_fixup_bus); | ||
417 | #endif | ||
415 | 418 | ||
416 | /* | 419 | /* |
417 | * Convert from Linux-centric to bus-centric addresses for bridge devices. | 420 | * Convert from Linux-centric to bus-centric addresses for bridge devices. |
@@ -431,6 +434,7 @@ pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, | |||
431 | region->start = res->start - offset; | 434 | region->start = res->start - offset; |
432 | region->end = res->end - offset; | 435 | region->end = res->end - offset; |
433 | } | 436 | } |
437 | EXPORT_SYMBOL(pcibios_resource_to_bus); | ||
434 | 438 | ||
435 | void __devinit | 439 | void __devinit |
436 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | 440 | pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, |
@@ -447,12 +451,7 @@ pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, | |||
447 | res->start = region->start + offset; | 451 | res->start = region->start + offset; |
448 | res->end = region->end + offset; | 452 | res->end = region->end + offset; |
449 | } | 453 | } |
450 | |||
451 | #ifdef CONFIG_HOTPLUG | ||
452 | EXPORT_SYMBOL(pcibios_fixup_bus); | ||
453 | EXPORT_SYMBOL(pcibios_resource_to_bus); | ||
454 | EXPORT_SYMBOL(pcibios_bus_to_resource); | 454 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
455 | #endif | ||
456 | 455 | ||
457 | /* | 456 | /* |
458 | * Swizzle the device pin each time we cross a bridge. | 457 | * Swizzle the device pin each time we cross a bridge. |
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c index d16500110ee9..4dd0edab6a65 100644 --- a/arch/arm/kernel/ecard.c +++ b/arch/arm/kernel/ecard.c | |||
@@ -237,7 +237,7 @@ static void ecard_init_pgtables(struct mm_struct *mm) | |||
237 | 237 | ||
238 | memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (IO_SIZE / PGDIR_SIZE)); | 238 | memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (IO_SIZE / PGDIR_SIZE)); |
239 | 239 | ||
240 | src_pgd = pgd_offset(mm, EASI_BASE); | 240 | src_pgd = pgd_offset(mm, (unsigned long)EASI_BASE); |
241 | dst_pgd = pgd_offset(mm, EASI_START); | 241 | dst_pgd = pgd_offset(mm, EASI_START); |
242 | 242 | ||
243 | memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE)); | 243 | memcpy(dst_pgd, src_pgd, sizeof(pgd_t) * (EASI_SIZE / PGDIR_SIZE)); |
@@ -674,44 +674,37 @@ static int __init ecard_probeirqhw(void) | |||
674 | #define ecard_probeirqhw() (0) | 674 | #define ecard_probeirqhw() (0) |
675 | #endif | 675 | #endif |
676 | 676 | ||
677 | #ifndef IO_EC_MEMC8_BASE | 677 | static void __iomem *__ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed) |
678 | #define IO_EC_MEMC8_BASE 0 | ||
679 | #endif | ||
680 | |||
681 | static unsigned int __ecard_address(ecard_t *ec, card_type_t type, card_speed_t speed) | ||
682 | { | 678 | { |
683 | unsigned long address = 0; | 679 | void __iomem *address = NULL; |
684 | int slot = ec->slot_no; | 680 | int slot = ec->slot_no; |
685 | 681 | ||
686 | if (ec->slot_no == 8) | 682 | if (ec->slot_no == 8) |
687 | return IO_EC_MEMC8_BASE; | 683 | return ECARD_MEMC8_BASE; |
688 | 684 | ||
689 | ectcr &= ~(1 << slot); | 685 | ectcr &= ~(1 << slot); |
690 | 686 | ||
691 | switch (type) { | 687 | switch (type) { |
692 | case ECARD_MEMC: | 688 | case ECARD_MEMC: |
693 | if (slot < 4) | 689 | if (slot < 4) |
694 | address = IO_EC_MEMC_BASE + (slot << 12); | 690 | address = ECARD_MEMC_BASE + (slot << 14); |
695 | break; | 691 | break; |
696 | 692 | ||
697 | case ECARD_IOC: | 693 | case ECARD_IOC: |
698 | if (slot < 4) | 694 | if (slot < 4) |
699 | address = IO_EC_IOC_BASE + (slot << 12); | 695 | address = ECARD_IOC_BASE + (slot << 14); |
700 | #ifdef IO_EC_IOC4_BASE | ||
701 | else | 696 | else |
702 | address = IO_EC_IOC4_BASE + ((slot - 4) << 12); | 697 | address = ECARD_IOC4_BASE + ((slot - 4) << 14); |
703 | #endif | ||
704 | if (address) | 698 | if (address) |
705 | address += speed << 17; | 699 | address += speed << 19; |
706 | break; | 700 | break; |
707 | 701 | ||
708 | #ifdef IO_EC_EASI_BASE | ||
709 | case ECARD_EASI: | 702 | case ECARD_EASI: |
710 | address = IO_EC_EASI_BASE + (slot << 22); | 703 | address = ECARD_EASI_BASE + (slot << 24); |
711 | if (speed == ECARD_FAST) | 704 | if (speed == ECARD_FAST) |
712 | ectcr |= 1 << slot; | 705 | ectcr |= 1 << slot; |
713 | break; | 706 | break; |
714 | #endif | 707 | |
715 | default: | 708 | default: |
716 | break; | 709 | break; |
717 | } | 710 | } |
@@ -990,6 +983,7 @@ ecard_probe(int slot, card_type_t type) | |||
990 | ecard_t **ecp; | 983 | ecard_t **ecp; |
991 | ecard_t *ec; | 984 | ecard_t *ec; |
992 | struct ex_ecid cid; | 985 | struct ex_ecid cid; |
986 | void __iomem *addr; | ||
993 | int i, rc; | 987 | int i, rc; |
994 | 988 | ||
995 | ec = ecard_alloc_card(type, slot); | 989 | ec = ecard_alloc_card(type, slot); |
@@ -999,7 +993,7 @@ ecard_probe(int slot, card_type_t type) | |||
999 | } | 993 | } |
1000 | 994 | ||
1001 | rc = -ENODEV; | 995 | rc = -ENODEV; |
1002 | if ((ec->podaddr = __ecard_address(ec, type, ECARD_SYNC)) == 0) | 996 | if ((addr = __ecard_address(ec, type, ECARD_SYNC)) == NULL) |
1003 | goto nodev; | 997 | goto nodev; |
1004 | 998 | ||
1005 | cid.r_zero = 1; | 999 | cid.r_zero = 1; |
@@ -1019,7 +1013,7 @@ ecard_probe(int slot, card_type_t type) | |||
1019 | ec->cid.fiqmask = cid.r_fiqmask; | 1013 | ec->cid.fiqmask = cid.r_fiqmask; |
1020 | ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff); | 1014 | ec->cid.fiqoff = ecard_gets24(cid.r_fiqoff); |
1021 | ec->fiqaddr = | 1015 | ec->fiqaddr = |
1022 | ec->irqaddr = (void __iomem *)ioaddr(ec->podaddr); | 1016 | ec->irqaddr = addr; |
1023 | 1017 | ||
1024 | if (ec->cid.is) { | 1018 | if (ec->cid.is) { |
1025 | ec->irqmask = ec->cid.irqmask; | 1019 | ec->irqmask = ec->cid.irqmask; |
@@ -1048,10 +1042,8 @@ ecard_probe(int slot, card_type_t type) | |||
1048 | set_irq_flags(ec->irq, IRQF_VALID); | 1042 | set_irq_flags(ec->irq, IRQF_VALID); |
1049 | } | 1043 | } |
1050 | 1044 | ||
1051 | #ifdef IO_EC_MEMC8_BASE | ||
1052 | if (slot == 8) | 1045 | if (slot == 8) |
1053 | ec->irq = 11; | 1046 | ec->irq = 11; |
1054 | #endif | ||
1055 | #ifdef CONFIG_ARCH_RPC | 1047 | #ifdef CONFIG_ARCH_RPC |
1056 | /* On RiscPC, only first two slots have DMA capability */ | 1048 | /* On RiscPC, only first two slots have DMA capability */ |
1057 | if (slot < 2) | 1049 | if (slot < 2) |
@@ -1097,9 +1089,7 @@ static int __init ecard_init(void) | |||
1097 | ecard_probe(slot, ECARD_IOC); | 1089 | ecard_probe(slot, ECARD_IOC); |
1098 | } | 1090 | } |
1099 | 1091 | ||
1100 | #ifdef IO_EC_MEMC8_BASE | ||
1101 | ecard_probe(8, ECARD_IOC); | 1092 | ecard_probe(8, ECARD_IOC); |
1102 | #endif | ||
1103 | 1093 | ||
1104 | irqhw = ecard_probeirqhw(); | 1094 | irqhw = ecard_probeirqhw(); |
1105 | 1095 | ||
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 742b6108a001..239703dbdf4f 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <asm/memory.h> | 21 | #include <asm/memory.h> |
22 | #include <asm/thread_info.h> | 22 | #include <asm/thread_info.h> |
23 | #include <asm/system.h> | 23 | #include <asm/system.h> |
24 | #include <asm/pgtable.h> | ||
24 | 25 | ||
25 | #ifdef CONFIG_DEBUG_LL | 26 | #ifdef CONFIG_DEBUG_LL |
26 | #include <mach/debug-macro.S> | 27 | #include <mach/debug-macro.S> |
@@ -38,11 +39,14 @@ | |||
38 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 | 39 | #error KERNEL_RAM_VADDR must start at 0xXXXX8000 |
39 | #endif | 40 | #endif |
40 | 41 | ||
42 | #define PG_DIR_SIZE 0x4000 | ||
43 | #define PMD_ORDER 2 | ||
44 | |||
41 | .globl swapper_pg_dir | 45 | .globl swapper_pg_dir |
42 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000 | 46 | .equ swapper_pg_dir, KERNEL_RAM_VADDR - PG_DIR_SIZE |
43 | 47 | ||
44 | .macro pgtbl, rd, phys | 48 | .macro pgtbl, rd, phys |
45 | add \rd, \phys, #TEXT_OFFSET - 0x4000 | 49 | add \rd, \phys, #TEXT_OFFSET - PG_DIR_SIZE |
46 | .endm | 50 | .endm |
47 | 51 | ||
48 | #ifdef CONFIG_XIP_KERNEL | 52 | #ifdef CONFIG_XIP_KERNEL |
@@ -148,11 +152,11 @@ __create_page_tables: | |||
148 | pgtbl r4, r8 @ page table address | 152 | pgtbl r4, r8 @ page table address |
149 | 153 | ||
150 | /* | 154 | /* |
151 | * Clear the 16K level 1 swapper page table | 155 | * Clear the swapper page table |
152 | */ | 156 | */ |
153 | mov r0, r4 | 157 | mov r0, r4 |
154 | mov r3, #0 | 158 | mov r3, #0 |
155 | add r6, r0, #0x4000 | 159 | add r6, r0, #PG_DIR_SIZE |
156 | 1: str r3, [r0], #4 | 160 | 1: str r3, [r0], #4 |
157 | str r3, [r0], #4 | 161 | str r3, [r0], #4 |
158 | str r3, [r0], #4 | 162 | str r3, [r0], #4 |
@@ -171,30 +175,30 @@ __create_page_tables: | |||
171 | sub r0, r0, r3 @ virt->phys offset | 175 | sub r0, r0, r3 @ virt->phys offset |
172 | add r5, r5, r0 @ phys __enable_mmu | 176 | add r5, r5, r0 @ phys __enable_mmu |
173 | add r6, r6, r0 @ phys __enable_mmu_end | 177 | add r6, r6, r0 @ phys __enable_mmu_end |
174 | mov r5, r5, lsr #20 | 178 | mov r5, r5, lsr #SECTION_SHIFT |
175 | mov r6, r6, lsr #20 | 179 | mov r6, r6, lsr #SECTION_SHIFT |
176 | 180 | ||
177 | 1: orr r3, r7, r5, lsl #20 @ flags + kernel base | 181 | 1: orr r3, r7, r5, lsl #SECTION_SHIFT @ flags + kernel base |
178 | str r3, [r4, r5, lsl #2] @ identity mapping | 182 | str r3, [r4, r5, lsl #PMD_ORDER] @ identity mapping |
179 | teq r5, r6 | 183 | cmp r5, r6 |
180 | addne r5, r5, #1 @ next section | 184 | addlo r5, r5, #1 @ next section |
181 | bne 1b | 185 | blo 1b |
182 | 186 | ||
183 | /* | 187 | /* |
184 | * Now setup the pagetables for our kernel direct | 188 | * Now setup the pagetables for our kernel direct |
185 | * mapped region. | 189 | * mapped region. |
186 | */ | 190 | */ |
187 | mov r3, pc | 191 | mov r3, pc |
188 | mov r3, r3, lsr #20 | 192 | mov r3, r3, lsr #SECTION_SHIFT |
189 | orr r3, r7, r3, lsl #20 | 193 | orr r3, r7, r3, lsl #SECTION_SHIFT |
190 | add r0, r4, #(KERNEL_START & 0xff000000) >> 18 | 194 | add r0, r4, #(KERNEL_START & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) |
191 | str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]! | 195 | str r3, [r0, #((KERNEL_START & 0x00f00000) >> SECTION_SHIFT) << PMD_ORDER]! |
192 | ldr r6, =(KERNEL_END - 1) | 196 | ldr r6, =(KERNEL_END - 1) |
193 | add r0, r0, #4 | 197 | add r0, r0, #1 << PMD_ORDER |
194 | add r6, r4, r6, lsr #18 | 198 | add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) |
195 | 1: cmp r0, r6 | 199 | 1: cmp r0, r6 |
196 | add r3, r3, #1 << 20 | 200 | add r3, r3, #1 << SECTION_SHIFT |
197 | strls r3, [r0], #4 | 201 | strls r3, [r0], #1 << PMD_ORDER |
198 | bls 1b | 202 | bls 1b |
199 | 203 | ||
200 | #ifdef CONFIG_XIP_KERNEL | 204 | #ifdef CONFIG_XIP_KERNEL |
@@ -203,11 +207,11 @@ __create_page_tables: | |||
203 | */ | 207 | */ |
204 | add r3, r8, #TEXT_OFFSET | 208 | add r3, r8, #TEXT_OFFSET |
205 | orr r3, r3, r7 | 209 | orr r3, r3, r7 |
206 | add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18 | 210 | add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> (SECTION_SHIFT - PMD_ORDER) |
207 | str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]! | 211 | str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> (SECTION_SHIFT - PMD_ORDER)]! |
208 | ldr r6, =(_end - 1) | 212 | ldr r6, =(_end - 1) |
209 | add r0, r0, #4 | 213 | add r0, r0, #4 |
210 | add r6, r4, r6, lsr #18 | 214 | add r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER) |
211 | 1: cmp r0, r6 | 215 | 1: cmp r0, r6 |
212 | add r3, r3, #1 << 20 | 216 | add r3, r3, #1 << 20 |
213 | strls r3, [r0], #4 | 217 | strls r3, [r0], #4 |
@@ -218,12 +222,12 @@ __create_page_tables: | |||
218 | * Then map boot params address in r2 or | 222 | * Then map boot params address in r2 or |
219 | * the first 1MB of ram if boot params address is not specified. | 223 | * the first 1MB of ram if boot params address is not specified. |
220 | */ | 224 | */ |
221 | mov r0, r2, lsr #20 | 225 | mov r0, r2, lsr #SECTION_SHIFT |
222 | movs r0, r0, lsl #20 | 226 | movs r0, r0, lsl #SECTION_SHIFT |
223 | moveq r0, r8 | 227 | moveq r0, r8 |
224 | sub r3, r0, r8 | 228 | sub r3, r0, r8 |
225 | add r3, r3, #PAGE_OFFSET | 229 | add r3, r3, #PAGE_OFFSET |
226 | add r3, r4, r3, lsr #18 | 230 | add r3, r4, r3, lsr #(SECTION_SHIFT - PMD_ORDER) |
227 | orr r6, r7, r0 | 231 | orr r6, r7, r0 |
228 | str r6, [r3] | 232 | str r6, [r3] |
229 | 233 | ||
@@ -236,21 +240,21 @@ __create_page_tables: | |||
236 | */ | 240 | */ |
237 | addruart r7, r3 | 241 | addruart r7, r3 |
238 | 242 | ||
239 | mov r3, r3, lsr #20 | 243 | mov r3, r3, lsr #SECTION_SHIFT |
240 | mov r3, r3, lsl #2 | 244 | mov r3, r3, lsl #PMD_ORDER |
241 | 245 | ||
242 | add r0, r4, r3 | 246 | add r0, r4, r3 |
243 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) | 247 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) |
244 | cmp r3, #0x0800 @ limit to 512MB | 248 | cmp r3, #0x0800 @ limit to 512MB |
245 | movhi r3, #0x0800 | 249 | movhi r3, #0x0800 |
246 | add r6, r0, r3 | 250 | add r6, r0, r3 |
247 | mov r3, r7, lsr #20 | 251 | mov r3, r7, lsr #SECTION_SHIFT |
248 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags | 252 | ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags |
249 | orr r3, r7, r3, lsl #20 | 253 | orr r3, r7, r3, lsl #SECTION_SHIFT |
250 | 1: str r3, [r0], #4 | 254 | 1: str r3, [r0], #4 |
251 | add r3, r3, #1 << 20 | 255 | add r3, r3, #1 << SECTION_SHIFT |
252 | teq r0, r6 | 256 | cmp r0, r6 |
253 | bne 1b | 257 | blo 1b |
254 | 258 | ||
255 | #else /* CONFIG_DEBUG_ICEDCC */ | 259 | #else /* CONFIG_DEBUG_ICEDCC */ |
256 | /* we don't need any serial debugging mappings for ICEDCC */ | 260 | /* we don't need any serial debugging mappings for ICEDCC */ |
@@ -262,7 +266,7 @@ __create_page_tables: | |||
262 | * If we're using the NetWinder or CATS, we also need to map | 266 | * If we're using the NetWinder or CATS, we also need to map |
263 | * in the 16550-type serial port for the debug messages | 267 | * in the 16550-type serial port for the debug messages |
264 | */ | 268 | */ |
265 | add r0, r4, #0xff000000 >> 18 | 269 | add r0, r4, #0xff000000 >> (SECTION_SHIFT - PMD_ORDER) |
266 | orr r3, r7, #0x7c000000 | 270 | orr r3, r7, #0x7c000000 |
267 | str r3, [r0] | 271 | str r3, [r0] |
268 | #endif | 272 | #endif |
@@ -272,10 +276,10 @@ __create_page_tables: | |||
272 | * Similar reasons here - for debug. This is | 276 | * Similar reasons here - for debug. This is |
273 | * only for Acorn RiscPC architectures. | 277 | * only for Acorn RiscPC architectures. |
274 | */ | 278 | */ |
275 | add r0, r4, #0x02000000 >> 18 | 279 | add r0, r4, #0x02000000 >> (SECTION_SHIFT - PMD_ORDER) |
276 | orr r3, r7, #0x02000000 | 280 | orr r3, r7, #0x02000000 |
277 | str r3, [r0] | 281 | str r3, [r0] |
278 | add r0, r4, #0xd8000000 >> 18 | 282 | add r0, r4, #0xd8000000 >> (SECTION_SHIFT - PMD_ORDER) |
279 | str r3, [r0] | 283 | str r3, [r0] |
280 | #endif | 284 | #endif |
281 | #endif | 285 | #endif |
@@ -488,13 +492,8 @@ __fixup_pv_table: | |||
488 | add r5, r5, r3 @ adjust table end address | 492 | add r5, r5, r3 @ adjust table end address |
489 | add r7, r7, r3 @ adjust __pv_phys_offset address | 493 | add r7, r7, r3 @ adjust __pv_phys_offset address |
490 | str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset | 494 | str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset |
491 | #ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
492 | mov r6, r3, lsr #24 @ constant for add/sub instructions | 495 | mov r6, r3, lsr #24 @ constant for add/sub instructions |
493 | teq r3, r6, lsl #24 @ must be 16MiB aligned | 496 | teq r3, r6, lsl #24 @ must be 16MiB aligned |
494 | #else | ||
495 | mov r6, r3, lsr #16 @ constant for add/sub instructions | ||
496 | teq r3, r6, lsl #16 @ must be 64kiB aligned | ||
497 | #endif | ||
498 | THUMB( it ne @ cross section branch ) | 497 | THUMB( it ne @ cross section branch ) |
499 | bne __error | 498 | bne __error |
500 | str r6, [r7, #4] @ save to __pv_offset | 499 | str r6, [r7, #4] @ save to __pv_offset |
@@ -510,20 +509,8 @@ ENDPROC(__fixup_pv_table) | |||
510 | .text | 509 | .text |
511 | __fixup_a_pv_table: | 510 | __fixup_a_pv_table: |
512 | #ifdef CONFIG_THUMB2_KERNEL | 511 | #ifdef CONFIG_THUMB2_KERNEL |
513 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | 512 | lsls r6, #24 |
514 | lsls r0, r6, #24 | 513 | beq 2f |
515 | lsr r6, #8 | ||
516 | beq 1f | ||
517 | clz r7, r0 | ||
518 | lsr r0, #24 | ||
519 | lsl r0, r7 | ||
520 | bic r0, 0x0080 | ||
521 | lsrs r7, #1 | ||
522 | orrcs r0, #0x0080 | ||
523 | orr r0, r0, r7, lsl #12 | ||
524 | #endif | ||
525 | 1: lsls r6, #24 | ||
526 | beq 4f | ||
527 | clz r7, r6 | 514 | clz r7, r6 |
528 | lsr r6, #24 | 515 | lsr r6, #24 |
529 | lsl r6, r7 | 516 | lsl r6, r7 |
@@ -532,43 +519,25 @@ __fixup_a_pv_table: | |||
532 | orrcs r6, #0x0080 | 519 | orrcs r6, #0x0080 |
533 | orr r6, r6, r7, lsl #12 | 520 | orr r6, r6, r7, lsl #12 |
534 | orr r6, #0x4000 | 521 | orr r6, #0x4000 |
535 | b 4f | 522 | b 2f |
536 | 2: @ at this point the C flag is always clear | 523 | 1: add r7, r3 |
537 | add r7, r3 | 524 | ldrh ip, [r7, #2] |
538 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | ||
539 | ldrh ip, [r7] | ||
540 | tst ip, 0x0400 @ the i bit tells us LS or MS byte | ||
541 | beq 3f | ||
542 | cmp r0, #0 @ set C flag, and ... | ||
543 | biceq ip, 0x0400 @ immediate zero value has a special encoding | ||
544 | streqh ip, [r7] @ that requires the i bit cleared | ||
545 | #endif | ||
546 | 3: ldrh ip, [r7, #2] | ||
547 | and ip, 0x8f00 | 525 | and ip, 0x8f00 |
548 | orrcc ip, r6 @ mask in offset bits 31-24 | 526 | orr ip, r6 @ mask in offset bits 31-24 |
549 | orrcs ip, r0 @ mask in offset bits 23-16 | ||
550 | strh ip, [r7, #2] | 527 | strh ip, [r7, #2] |
551 | 4: cmp r4, r5 | 528 | 2: cmp r4, r5 |
552 | ldrcc r7, [r4], #4 @ use branch for delay slot | 529 | ldrcc r7, [r4], #4 @ use branch for delay slot |
553 | bcc 2b | 530 | bcc 1b |
554 | bx lr | 531 | bx lr |
555 | #else | 532 | #else |
556 | #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT | 533 | b 2f |
557 | and r0, r6, #255 @ offset bits 23-16 | 534 | 1: ldr ip, [r7, r3] |
558 | mov r6, r6, lsr #8 @ offset bits 31-24 | ||
559 | #else | ||
560 | mov r0, #0 @ just in case... | ||
561 | #endif | ||
562 | b 3f | ||
563 | 2: ldr ip, [r7, r3] | ||
564 | bic ip, ip, #0x000000ff | 535 | bic ip, ip, #0x000000ff |
565 | tst ip, #0x400 @ rotate shift tells us LS or MS byte | 536 | orr ip, ip, r6 @ mask in offset bits 31-24 |
566 | orrne ip, ip, r6 @ mask in offset bits 31-24 | ||
567 | orreq ip, ip, r0 @ mask in offset bits 23-16 | ||
568 | str ip, [r7, r3] | 537 | str ip, [r7, r3] |
569 | 3: cmp r4, r5 | 538 | 2: cmp r4, r5 |
570 | ldrcc r7, [r4], #4 @ use branch for delay slot | 539 | ldrcc r7, [r4], #4 @ use branch for delay slot |
571 | bcc 2b | 540 | bcc 1b |
572 | mov pc, lr | 541 | mov pc, lr |
573 | #endif | 542 | #endif |
574 | ENDPROC(__fixup_a_pv_table) | 543 | ENDPROC(__fixup_a_pv_table) |
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c index de3dcab8610b..53919b230e8b 100644 --- a/arch/arm/kernel/irq.c +++ b/arch/arm/kernel/irq.c | |||
@@ -35,8 +35,8 @@ | |||
35 | #include <linux/list.h> | 35 | #include <linux/list.h> |
36 | #include <linux/kallsyms.h> | 36 | #include <linux/kallsyms.h> |
37 | #include <linux/proc_fs.h> | 37 | #include <linux/proc_fs.h> |
38 | #include <linux/ftrace.h> | ||
39 | 38 | ||
39 | #include <asm/exception.h> | ||
40 | #include <asm/system.h> | 40 | #include <asm/system.h> |
41 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
42 | #include <asm/mach/irq.h> | 42 | #include <asm/mach/irq.h> |
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index cc2020c2c709..1e9be5d25e56 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c | |||
@@ -33,7 +33,7 @@ | |||
33 | * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. | 33 | * recompiling the whole kernel when CONFIG_XIP_KERNEL is turned on/off. |
34 | */ | 34 | */ |
35 | #undef MODULES_VADDR | 35 | #undef MODULES_VADDR |
36 | #define MODULES_VADDR (((unsigned long)_etext + ~PGDIR_MASK) & PGDIR_MASK) | 36 | #define MODULES_VADDR (((unsigned long)_etext + ~PMD_MASK) & PMD_MASK) |
37 | #endif | 37 | #endif |
38 | 38 | ||
39 | #ifdef CONFIG_MMU | 39 | #ifdef CONFIG_MMU |
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index d88ff0230e82..35417d0fb8ab 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c | |||
@@ -16,7 +16,6 @@ | |||
16 | #include <linux/cache.h> | 16 | #include <linux/cache.h> |
17 | #include <linux/profile.h> | 17 | #include <linux/profile.h> |
18 | #include <linux/errno.h> | 18 | #include <linux/errno.h> |
19 | #include <linux/ftrace.h> | ||
20 | #include <linux/mm.h> | 19 | #include <linux/mm.h> |
21 | #include <linux/err.h> | 20 | #include <linux/err.h> |
22 | #include <linux/cpu.h> | 21 | #include <linux/cpu.h> |
@@ -31,6 +30,8 @@ | |||
31 | #include <asm/cacheflush.h> | 30 | #include <asm/cacheflush.h> |
32 | #include <asm/cpu.h> | 31 | #include <asm/cpu.h> |
33 | #include <asm/cputype.h> | 32 | #include <asm/cputype.h> |
33 | #include <asm/exception.h> | ||
34 | #include <asm/topology.h> | ||
34 | #include <asm/mmu_context.h> | 35 | #include <asm/mmu_context.h> |
35 | #include <asm/pgtable.h> | 36 | #include <asm/pgtable.h> |
36 | #include <asm/pgalloc.h> | 37 | #include <asm/pgalloc.h> |
@@ -39,6 +40,7 @@ | |||
39 | #include <asm/tlbflush.h> | 40 | #include <asm/tlbflush.h> |
40 | #include <asm/ptrace.h> | 41 | #include <asm/ptrace.h> |
41 | #include <asm/localtimer.h> | 42 | #include <asm/localtimer.h> |
43 | #include <asm/smp_plat.h> | ||
42 | 44 | ||
43 | /* | 45 | /* |
44 | * as from 2.5, kernels no longer have an init_tasks structure | 46 | * as from 2.5, kernels no longer have an init_tasks structure |
@@ -259,6 +261,20 @@ void __ref cpu_die(void) | |||
259 | } | 261 | } |
260 | #endif /* CONFIG_HOTPLUG_CPU */ | 262 | #endif /* CONFIG_HOTPLUG_CPU */ |
261 | 263 | ||
264 | int __cpu_logical_map[NR_CPUS]; | ||
265 | |||
266 | void __init smp_setup_processor_id(void) | ||
267 | { | ||
268 | int i; | ||
269 | u32 cpu = is_smp() ? read_cpuid_mpidr() & 0xff : 0; | ||
270 | |||
271 | cpu_logical_map(0) = cpu; | ||
272 | for (i = 1; i < NR_CPUS; ++i) | ||
273 | cpu_logical_map(i) = i == cpu ? 0 : i; | ||
274 | |||
275 | printk(KERN_INFO "Booting Linux on physical CPU %d\n", cpu); | ||
276 | } | ||
277 | |||
262 | /* | 278 | /* |
263 | * Called by both boot and secondaries to move global data into | 279 | * Called by both boot and secondaries to move global data into |
264 | * per-processor storage. | 280 | * per-processor storage. |
@@ -268,6 +284,8 @@ static void __cpuinit smp_store_cpu_info(unsigned int cpuid) | |||
268 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); | 284 | struct cpuinfo_arm *cpu_info = &per_cpu(cpu_data, cpuid); |
269 | 285 | ||
270 | cpu_info->loops_per_jiffy = loops_per_jiffy; | 286 | cpu_info->loops_per_jiffy = loops_per_jiffy; |
287 | |||
288 | store_cpu_topology(cpuid); | ||
271 | } | 289 | } |
272 | 290 | ||
273 | /* | 291 | /* |
@@ -358,6 +376,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus) | |||
358 | { | 376 | { |
359 | unsigned int ncores = num_possible_cpus(); | 377 | unsigned int ncores = num_possible_cpus(); |
360 | 378 | ||
379 | init_cpu_topology(); | ||
380 | |||
361 | smp_store_cpu_info(smp_processor_id()); | 381 | smp_store_cpu_info(smp_processor_id()); |
362 | 382 | ||
363 | /* | 383 | /* |
@@ -460,6 +480,11 @@ static void ipi_timer(void) | |||
460 | #ifdef CONFIG_LOCAL_TIMERS | 480 | #ifdef CONFIG_LOCAL_TIMERS |
461 | asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs) | 481 | asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs) |
462 | { | 482 | { |
483 | handle_local_timer(regs); | ||
484 | } | ||
485 | |||
486 | void handle_local_timer(struct pt_regs *regs) | ||
487 | { | ||
463 | struct pt_regs *old_regs = set_irq_regs(regs); | 488 | struct pt_regs *old_regs = set_irq_regs(regs); |
464 | int cpu = smp_processor_id(); | 489 | int cpu = smp_processor_id(); |
465 | 490 | ||
@@ -567,6 +592,11 @@ static void ipi_cpu_stop(unsigned int cpu) | |||
567 | */ | 592 | */ |
568 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) | 593 | asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs) |
569 | { | 594 | { |
595 | handle_IPI(ipinr, regs); | ||
596 | } | ||
597 | |||
598 | void handle_IPI(int ipinr, struct pt_regs *regs) | ||
599 | { | ||
570 | unsigned int cpu = smp_processor_id(); | 600 | unsigned int cpu = smp_processor_id(); |
571 | struct pt_regs *old_regs = set_irq_regs(regs); | 601 | struct pt_regs *old_regs = set_irq_regs(regs); |
572 | 602 | ||
diff --git a/arch/arm/kernel/smp_scu.c b/arch/arm/kernel/smp_scu.c index 7fcddb75c877..8f5dd7963356 100644 --- a/arch/arm/kernel/smp_scu.c +++ b/arch/arm/kernel/smp_scu.c | |||
@@ -34,7 +34,7 @@ unsigned int __init scu_get_core_count(void __iomem *scu_base) | |||
34 | /* | 34 | /* |
35 | * Enable the SCU | 35 | * Enable the SCU |
36 | */ | 36 | */ |
37 | void __init scu_enable(void __iomem *scu_base) | 37 | void scu_enable(void __iomem *scu_base) |
38 | { | 38 | { |
39 | u32 scu_ctrl; | 39 | u32 scu_ctrl; |
40 | 40 | ||
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c index cb634c3e28e9..5a54b95d6bd2 100644 --- a/arch/arm/kernel/time.c +++ b/arch/arm/kernel/time.c | |||
@@ -39,13 +39,11 @@ | |||
39 | */ | 39 | */ |
40 | static struct sys_timer *system_timer; | 40 | static struct sys_timer *system_timer; |
41 | 41 | ||
42 | #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) | 42 | #if defined(CONFIG_RTC_DRV_CMOS) || defined(CONFIG_RTC_DRV_CMOS_MODULE) || \ |
43 | defined(CONFIG_NVRAM) || defined(CONFIG_NVRAM_MODULE) | ||
43 | /* this needs a better home */ | 44 | /* this needs a better home */ |
44 | DEFINE_SPINLOCK(rtc_lock); | 45 | DEFINE_SPINLOCK(rtc_lock); |
45 | |||
46 | #ifdef CONFIG_RTC_DRV_CMOS_MODULE | ||
47 | EXPORT_SYMBOL(rtc_lock); | 46 | EXPORT_SYMBOL(rtc_lock); |
48 | #endif | ||
49 | #endif /* pc-style 'CMOS' RTC support */ | 47 | #endif /* pc-style 'CMOS' RTC support */ |
50 | 48 | ||
51 | /* change this if you have some constant time drift */ | 49 | /* change this if you have some constant time drift */ |
diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c new file mode 100644 index 000000000000..1040c00405d0 --- /dev/null +++ b/arch/arm/kernel/topology.c | |||
@@ -0,0 +1,148 @@ | |||
1 | /* | ||
2 | * arch/arm/kernel/topology.c | ||
3 | * | ||
4 | * Copyright (C) 2011 Linaro Limited. | ||
5 | * Written by: Vincent Guittot | ||
6 | * | ||
7 | * based on arch/sh/kernel/topology.c | ||
8 | * | ||
9 | * This file is subject to the terms and conditions of the GNU General Public | ||
10 | * License. See the file "COPYING" in the main directory of this archive | ||
11 | * for more details. | ||
12 | */ | ||
13 | |||
14 | #include <linux/cpu.h> | ||
15 | #include <linux/cpumask.h> | ||
16 | #include <linux/init.h> | ||
17 | #include <linux/percpu.h> | ||
18 | #include <linux/node.h> | ||
19 | #include <linux/nodemask.h> | ||
20 | #include <linux/sched.h> | ||
21 | |||
22 | #include <asm/cputype.h> | ||
23 | #include <asm/topology.h> | ||
24 | |||
25 | #define MPIDR_SMP_BITMASK (0x3 << 30) | ||
26 | #define MPIDR_SMP_VALUE (0x2 << 30) | ||
27 | |||
28 | #define MPIDR_MT_BITMASK (0x1 << 24) | ||
29 | |||
30 | /* | ||
31 | * These masks reflect the current use of the affinity levels. | ||
32 | * The affinity level can be up to 16 bits according to ARM ARM | ||
33 | */ | ||
34 | |||
35 | #define MPIDR_LEVEL0_MASK 0x3 | ||
36 | #define MPIDR_LEVEL0_SHIFT 0 | ||
37 | |||
38 | #define MPIDR_LEVEL1_MASK 0xF | ||
39 | #define MPIDR_LEVEL1_SHIFT 8 | ||
40 | |||
41 | #define MPIDR_LEVEL2_MASK 0xFF | ||
42 | #define MPIDR_LEVEL2_SHIFT 16 | ||
43 | |||
44 | struct cputopo_arm cpu_topology[NR_CPUS]; | ||
45 | |||
46 | const struct cpumask *cpu_coregroup_mask(unsigned int cpu) | ||
47 | { | ||
48 | return &cpu_topology[cpu].core_sibling; | ||
49 | } | ||
50 | |||
51 | /* | ||
52 | * store_cpu_topology is called at boot when only one cpu is running | ||
53 | * and with the mutex cpu_hotplug.lock locked, when several cpus have booted, | ||
54 | * which prevents simultaneous write access to cpu_topology array | ||
55 | */ | ||
56 | void store_cpu_topology(unsigned int cpuid) | ||
57 | { | ||
58 | struct cputopo_arm *cpuid_topo = &cpu_topology[cpuid]; | ||
59 | unsigned int mpidr; | ||
60 | unsigned int cpu; | ||
61 | |||
62 | /* If the cpu topology has been already set, just return */ | ||
63 | if (cpuid_topo->core_id != -1) | ||
64 | return; | ||
65 | |||
66 | mpidr = read_cpuid_mpidr(); | ||
67 | |||
68 | /* create cpu topology mapping */ | ||
69 | if ((mpidr & MPIDR_SMP_BITMASK) == MPIDR_SMP_VALUE) { | ||
70 | /* | ||
71 | * This is a multiprocessor system | ||
72 | * multiprocessor format & multiprocessor mode field are set | ||
73 | */ | ||
74 | |||
75 | if (mpidr & MPIDR_MT_BITMASK) { | ||
76 | /* core performance interdependency */ | ||
77 | cpuid_topo->thread_id = (mpidr >> MPIDR_LEVEL0_SHIFT) | ||
78 | & MPIDR_LEVEL0_MASK; | ||
79 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL1_SHIFT) | ||
80 | & MPIDR_LEVEL1_MASK; | ||
81 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL2_SHIFT) | ||
82 | & MPIDR_LEVEL2_MASK; | ||
83 | } else { | ||
84 | /* largely independent cores */ | ||
85 | cpuid_topo->thread_id = -1; | ||
86 | cpuid_topo->core_id = (mpidr >> MPIDR_LEVEL0_SHIFT) | ||
87 | & MPIDR_LEVEL0_MASK; | ||
88 | cpuid_topo->socket_id = (mpidr >> MPIDR_LEVEL1_SHIFT) | ||
89 | & MPIDR_LEVEL1_MASK; | ||
90 | } | ||
91 | } else { | ||
92 | /* | ||
93 | * This is an uniprocessor system | ||
94 | * we are in multiprocessor format but uniprocessor system | ||
95 | * or in the old uniprocessor format | ||
96 | */ | ||
97 | cpuid_topo->thread_id = -1; | ||
98 | cpuid_topo->core_id = 0; | ||
99 | cpuid_topo->socket_id = -1; | ||
100 | } | ||
101 | |||
102 | /* update core and thread sibling masks */ | ||
103 | for_each_possible_cpu(cpu) { | ||
104 | struct cputopo_arm *cpu_topo = &cpu_topology[cpu]; | ||
105 | |||
106 | if (cpuid_topo->socket_id == cpu_topo->socket_id) { | ||
107 | cpumask_set_cpu(cpuid, &cpu_topo->core_sibling); | ||
108 | if (cpu != cpuid) | ||
109 | cpumask_set_cpu(cpu, | ||
110 | &cpuid_topo->core_sibling); | ||
111 | |||
112 | if (cpuid_topo->core_id == cpu_topo->core_id) { | ||
113 | cpumask_set_cpu(cpuid, | ||
114 | &cpu_topo->thread_sibling); | ||
115 | if (cpu != cpuid) | ||
116 | cpumask_set_cpu(cpu, | ||
117 | &cpuid_topo->thread_sibling); | ||
118 | } | ||
119 | } | ||
120 | } | ||
121 | smp_wmb(); | ||
122 | |||
123 | printk(KERN_INFO "CPU%u: thread %d, cpu %d, socket %d, mpidr %x\n", | ||
124 | cpuid, cpu_topology[cpuid].thread_id, | ||
125 | cpu_topology[cpuid].core_id, | ||
126 | cpu_topology[cpuid].socket_id, mpidr); | ||
127 | } | ||
128 | |||
129 | /* | ||
130 | * init_cpu_topology is called at boot when only one cpu is running | ||
131 | * which prevent simultaneous write access to cpu_topology array | ||
132 | */ | ||
133 | void init_cpu_topology(void) | ||
134 | { | ||
135 | unsigned int cpu; | ||
136 | |||
137 | /* init core mask */ | ||
138 | for_each_possible_cpu(cpu) { | ||
139 | struct cputopo_arm *cpu_topo = &(cpu_topology[cpu]); | ||
140 | |||
141 | cpu_topo->thread_id = -1; | ||
142 | cpu_topo->core_id = -1; | ||
143 | cpu_topo->socket_id = -1; | ||
144 | cpumask_clear(&cpu_topo->core_sibling); | ||
145 | cpumask_clear(&cpu_topo->thread_sibling); | ||
146 | } | ||
147 | smp_wmb(); | ||
148 | } | ||
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c index bc9f9da782cb..210382555af1 100644 --- a/arch/arm/kernel/traps.c +++ b/arch/arm/kernel/traps.c | |||
@@ -27,6 +27,7 @@ | |||
27 | 27 | ||
28 | #include <linux/atomic.h> | 28 | #include <linux/atomic.h> |
29 | #include <asm/cacheflush.h> | 29 | #include <asm/cacheflush.h> |
30 | #include <asm/exception.h> | ||
30 | #include <asm/system.h> | 31 | #include <asm/system.h> |
31 | #include <asm/unistd.h> | 32 | #include <asm/unistd.h> |
32 | #include <asm/traps.h> | 33 | #include <asm/traps.h> |
diff --git a/arch/arm/lib/uaccess_with_memcpy.c b/arch/arm/lib/uaccess_with_memcpy.c index 8b9b13649f81..025f742dd4df 100644 --- a/arch/arm/lib/uaccess_with_memcpy.c +++ b/arch/arm/lib/uaccess_with_memcpy.c | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <linux/sched.h> | 17 | #include <linux/sched.h> |
18 | #include <linux/hardirq.h> /* for in_atomic() */ | 18 | #include <linux/hardirq.h> /* for in_atomic() */ |
19 | #include <linux/gfp.h> | 19 | #include <linux/gfp.h> |
20 | #include <linux/highmem.h> | ||
20 | #include <asm/current.h> | 21 | #include <asm/current.h> |
21 | #include <asm/page.h> | 22 | #include <asm/page.h> |
22 | 23 | ||
diff --git a/arch/arm/mach-ebsa110/include/mach/io.h b/arch/arm/mach-ebsa110/include/mach/io.h index f68daa632af0..44679db672fb 100644 --- a/arch/arm/mach-ebsa110/include/mach/io.h +++ b/arch/arm/mach-ebsa110/include/mach/io.h | |||
@@ -13,8 +13,6 @@ | |||
13 | #ifndef __ASM_ARM_ARCH_IO_H | 13 | #ifndef __ASM_ARM_ARCH_IO_H |
14 | #define __ASM_ARM_ARCH_IO_H | 14 | #define __ASM_ARM_ARCH_IO_H |
15 | 15 | ||
16 | #define IO_SPACE_LIMIT 0xffff | ||
17 | |||
18 | u8 __inb8(unsigned int port); | 16 | u8 __inb8(unsigned int port); |
19 | void __outb8(u8 val, unsigned int port); | 17 | void __outb8(u8 val, unsigned int port); |
20 | 18 | ||
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig index 0c77ab99fa16..fc1f92dfbea8 100644 --- a/arch/arm/mach-exynos4/Kconfig +++ b/arch/arm/mach-exynos4/Kconfig | |||
@@ -12,6 +12,7 @@ if ARCH_EXYNOS4 | |||
12 | config CPU_EXYNOS4210 | 12 | config CPU_EXYNOS4210 |
13 | bool | 13 | bool |
14 | select S3C_PL330_DMA | 14 | select S3C_PL330_DMA |
15 | select ARM_CPU_SUSPEND if PM | ||
15 | help | 16 | help |
16 | Enable EXYNOS4210 CPU support | 17 | Enable EXYNOS4210 CPU support |
17 | 18 | ||
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c index df6ef1b2f98b..0c90896ad9a0 100644 --- a/arch/arm/mach-exynos4/platsmp.c +++ b/arch/arm/mach-exynos4/platsmp.c | |||
@@ -193,12 +193,10 @@ void __init smp_init_cpus(void) | |||
193 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | 193 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
194 | 194 | ||
195 | /* sanity check */ | 195 | /* sanity check */ |
196 | if (ncores > NR_CPUS) { | 196 | if (ncores > nr_cpu_ids) { |
197 | printk(KERN_WARNING | 197 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
198 | "EXYNOS4: no. of cores (%d) greater than configured " | 198 | ncores, nr_cpu_ids); |
199 | "maximum of %d - clipping\n", | 199 | ncores = nr_cpu_ids; |
200 | ncores, NR_CPUS); | ||
201 | ncores = NR_CPUS; | ||
202 | } | 200 | } |
203 | 201 | ||
204 | for (i = 0; i < ncores; i++) | 202 | for (i = 0; i < ncores; i++) |
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h index 32e4cc397c28..15a70396c27d 100644 --- a/arch/arm/mach-footbridge/include/mach/io.h +++ b/arch/arm/mach-footbridge/include/mach/io.h | |||
@@ -23,8 +23,6 @@ | |||
23 | #define PCIO_SIZE 0x00100000 | 23 | #define PCIO_SIZE 0x00100000 |
24 | #define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) | 24 | #define PCIO_BASE MMU_IO(0xff000000, 0x7c000000) |
25 | 25 | ||
26 | #define IO_SPACE_LIMIT 0xffff | ||
27 | |||
28 | /* | 26 | /* |
29 | * Translation of various region addresses to virtual addresses | 27 | * Translation of various region addresses to virtual addresses |
30 | */ | 28 | */ |
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h index f21bb5493dd9..37beed3fa3ed 100644 --- a/arch/arm/mach-integrator/include/mach/io.h +++ b/arch/arm/mach-integrator/include/mach/io.h | |||
@@ -20,8 +20,6 @@ | |||
20 | #ifndef __ASM_ARM_ARCH_IO_H | 20 | #ifndef __ASM_ARM_ARCH_IO_H |
21 | #define __ASM_ARM_ARCH_IO_H | 21 | #define __ASM_ARM_ARCH_IO_H |
22 | 22 | ||
23 | #define IO_SPACE_LIMIT 0xffff | ||
24 | |||
25 | /* | 23 | /* |
26 | * WARNING: this has to mirror definitions in platform.h | 24 | * WARNING: this has to mirror definitions in platform.h |
27 | */ | 25 | */ |
diff --git a/arch/arm/mach-ixp4xx/include/mach/io.h b/arch/arm/mach-ixp4xx/include/mach/io.h index 57b5410c31f4..ffb9d6afb89f 100644 --- a/arch/arm/mach-ixp4xx/include/mach/io.h +++ b/arch/arm/mach-ixp4xx/include/mach/io.h | |||
@@ -17,8 +17,6 @@ | |||
17 | 17 | ||
18 | #include <mach/hardware.h> | 18 | #include <mach/hardware.h> |
19 | 19 | ||
20 | #define IO_SPACE_LIMIT 0x0000ffff | ||
21 | |||
22 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); | 20 | extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data); |
23 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); | 21 | extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data); |
24 | 22 | ||
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c index b7a84966b711..d1e4cc83b1e6 100644 --- a/arch/arm/mach-msm/board-msm7x30.c +++ b/arch/arm/mach-msm/board-msm7x30.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/smsc911x.h> | 24 | #include <linux/smsc911x.h> |
25 | #include <linux/usb/msm_hsusb.h> | 25 | #include <linux/usb/msm_hsusb.h> |
26 | #include <linux/clkdev.h> | 26 | #include <linux/clkdev.h> |
27 | #include <linux/memblock.h> | ||
27 | 28 | ||
28 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
@@ -42,6 +43,21 @@ | |||
42 | 43 | ||
43 | extern struct sys_timer msm_timer; | 44 | extern struct sys_timer msm_timer; |
44 | 45 | ||
46 | static void __init msm7x30_fixup(struct machine_desc *desc, struct tag *tag, | ||
47 | char **cmdline, struct meminfo *mi) | ||
48 | { | ||
49 | for (; tag->hdr.size; tag = tag_next(tag)) | ||
50 | if (tag->hdr.tag == ATAG_MEM && tag->u.mem.start == 0x200000) { | ||
51 | tag->u.mem.start = 0; | ||
52 | tag->u.mem.size += SZ_2M; | ||
53 | } | ||
54 | } | ||
55 | |||
56 | static void __init msm7x30_reserve(void) | ||
57 | { | ||
58 | memblock_remove(0x0, SZ_2M); | ||
59 | } | ||
60 | |||
45 | static int hsusb_phy_init_seq[] = { | 61 | static int hsusb_phy_init_seq[] = { |
46 | 0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */ | 62 | 0x30, 0x32, /* Enable and set Pre-Emphasis Depth to 20% */ |
47 | 0x02, 0x36, /* Disable CDR Auto Reset feature */ | 63 | 0x02, 0x36, /* Disable CDR Auto Reset feature */ |
@@ -107,6 +123,8 @@ static void __init msm7x30_map_io(void) | |||
107 | 123 | ||
108 | MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") | 124 | MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") |
109 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 125 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
126 | .fixup = msm7x30_fixup, | ||
127 | .reserve = msm7x30_reserve, | ||
110 | .map_io = msm7x30_map_io, | 128 | .map_io = msm7x30_map_io, |
111 | .init_irq = msm7x30_init_irq, | 129 | .init_irq = msm7x30_init_irq, |
112 | .init_machine = msm7x30_init, | 130 | .init_machine = msm7x30_init, |
@@ -115,6 +133,8 @@ MACHINE_END | |||
115 | 133 | ||
116 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") | 134 | MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") |
117 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 135 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
136 | .fixup = msm7x30_fixup, | ||
137 | .reserve = msm7x30_reserve, | ||
118 | .map_io = msm7x30_map_io, | 138 | .map_io = msm7x30_map_io, |
119 | .init_irq = msm7x30_init_irq, | 139 | .init_irq = msm7x30_init_irq, |
120 | .init_machine = msm7x30_init, | 140 | .init_machine = msm7x30_init, |
@@ -123,6 +143,8 @@ MACHINE_END | |||
123 | 143 | ||
124 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") | 144 | MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") |
125 | .boot_params = PLAT_PHYS_OFFSET + 0x100, | 145 | .boot_params = PLAT_PHYS_OFFSET + 0x100, |
146 | .fixup = msm7x30_fixup, | ||
147 | .reserve = msm7x30_reserve, | ||
126 | .map_io = msm7x30_map_io, | 148 | .map_io = msm7x30_map_io, |
127 | .init_irq = msm7x30_init_irq, | 149 | .init_irq = msm7x30_init_irq, |
128 | .init_machine = msm7x30_init, | 150 | .init_machine = msm7x30_init, |
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c index 35c7ceeb3f29..b04468e7d00e 100644 --- a/arch/arm/mach-msm/board-msm8960.c +++ b/arch/arm/mach-msm/board-msm8960.c | |||
@@ -20,16 +20,34 @@ | |||
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | #include <linux/clkdev.h> | 22 | #include <linux/clkdev.h> |
23 | #include <linux/memblock.h> | ||
23 | 24 | ||
24 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
26 | #include <asm/hardware/gic.h> | 27 | #include <asm/hardware/gic.h> |
28 | #include <asm/setup.h> | ||
27 | 29 | ||
28 | #include <mach/board.h> | 30 | #include <mach/board.h> |
29 | #include <mach/msm_iomap.h> | 31 | #include <mach/msm_iomap.h> |
30 | 32 | ||
31 | #include "devices.h" | 33 | #include "devices.h" |
32 | 34 | ||
35 | static void __init msm8960_fixup(struct machine_desc *desc, struct tag *tag, | ||
36 | char **cmdline, struct meminfo *mi) | ||
37 | { | ||
38 | for (; tag->hdr.size; tag = tag_next(tag)) | ||
39 | if (tag->hdr.tag == ATAG_MEM && | ||
40 | tag->u.mem.start == 0x40200000) { | ||
41 | tag->u.mem.start = 0x40000000; | ||
42 | tag->u.mem.size += SZ_2M; | ||
43 | } | ||
44 | } | ||
45 | |||
46 | static void __init msm8960_reserve(void) | ||
47 | { | ||
48 | memblock_remove(0x40000000, SZ_2M); | ||
49 | } | ||
50 | |||
33 | static void __init msm8960_map_io(void) | 51 | static void __init msm8960_map_io(void) |
34 | { | 52 | { |
35 | msm_map_msm8960_io(); | 53 | msm_map_msm8960_io(); |
@@ -76,6 +94,8 @@ static void __init msm8960_rumi3_init(void) | |||
76 | } | 94 | } |
77 | 95 | ||
78 | MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") | 96 | MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") |
97 | .fixup = msm8960_fixup, | ||
98 | .reserve = msm8960_reserve, | ||
79 | .map_io = msm8960_map_io, | 99 | .map_io = msm8960_map_io, |
80 | .init_irq = msm8960_init_irq, | 100 | .init_irq = msm8960_init_irq, |
81 | .timer = &msm_timer, | 101 | .timer = &msm_timer, |
@@ -83,6 +103,8 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR") | |||
83 | MACHINE_END | 103 | MACHINE_END |
84 | 104 | ||
85 | MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") | 105 | MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3") |
106 | .fixup = msm8960_fixup, | ||
107 | .reserve = msm8960_reserve, | ||
86 | .map_io = msm8960_map_io, | 108 | .map_io = msm8960_map_io, |
87 | .init_irq = msm8960_init_irq, | 109 | .init_irq = msm8960_init_irq, |
88 | .timer = &msm_timer, | 110 | .timer = &msm_timer, |
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c index 1163b6fd05d2..9221f54778be 100644 --- a/arch/arm/mach-msm/board-msm8x60.c +++ b/arch/arm/mach-msm/board-msm8x60.c | |||
@@ -20,14 +20,31 @@ | |||
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/irq.h> | 22 | #include <linux/irq.h> |
23 | #include <linux/memblock.h> | ||
23 | 24 | ||
24 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
26 | #include <asm/hardware/gic.h> | 27 | #include <asm/hardware/gic.h> |
28 | #include <asm/setup.h> | ||
27 | 29 | ||
28 | #include <mach/board.h> | 30 | #include <mach/board.h> |
29 | #include <mach/msm_iomap.h> | 31 | #include <mach/msm_iomap.h> |
30 | 32 | ||
33 | static void __init msm8x60_fixup(struct machine_desc *desc, struct tag *tag, | ||
34 | char **cmdline, struct meminfo *mi) | ||
35 | { | ||
36 | for (; tag->hdr.size; tag = tag_next(tag)) | ||
37 | if (tag->hdr.tag == ATAG_MEM && | ||
38 | tag->u.mem.start == 0x40200000) { | ||
39 | tag->u.mem.start = 0x40000000; | ||
40 | tag->u.mem.size += SZ_2M; | ||
41 | } | ||
42 | } | ||
43 | |||
44 | static void __init msm8x60_reserve(void) | ||
45 | { | ||
46 | memblock_remove(0x40000000, SZ_2M); | ||
47 | } | ||
31 | 48 | ||
32 | static void __init msm8x60_map_io(void) | 49 | static void __init msm8x60_map_io(void) |
33 | { | 50 | { |
@@ -65,6 +82,8 @@ static void __init msm8x60_init(void) | |||
65 | } | 82 | } |
66 | 83 | ||
67 | MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") | 84 | MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") |
85 | .fixup = msm8x60_fixup, | ||
86 | .reserve = msm8x60_reserve, | ||
68 | .map_io = msm8x60_map_io, | 87 | .map_io = msm8x60_map_io, |
69 | .init_irq = msm8x60_init_irq, | 88 | .init_irq = msm8x60_init_irq, |
70 | .init_machine = msm8x60_init, | 89 | .init_machine = msm8x60_init, |
@@ -72,6 +91,8 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3") | |||
72 | MACHINE_END | 91 | MACHINE_END |
73 | 92 | ||
74 | MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") | 93 | MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") |
94 | .fixup = msm8x60_fixup, | ||
95 | .reserve = msm8x60_reserve, | ||
75 | .map_io = msm8x60_map_io, | 96 | .map_io = msm8x60_map_io, |
76 | .init_irq = msm8x60_init_irq, | 97 | .init_irq = msm8x60_init_irq, |
77 | .init_machine = msm8x60_init, | 98 | .init_machine = msm8x60_init, |
@@ -79,6 +100,8 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF") | |||
79 | MACHINE_END | 100 | MACHINE_END |
80 | 101 | ||
81 | MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") | 102 | MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") |
103 | .fixup = msm8x60_fixup, | ||
104 | .reserve = msm8x60_reserve, | ||
82 | .map_io = msm8x60_map_io, | 105 | .map_io = msm8x60_map_io, |
83 | .init_irq = msm8x60_init_irq, | 106 | .init_irq = msm8x60_init_irq, |
84 | .init_machine = msm8x60_init, | 107 | .init_machine = msm8x60_init, |
@@ -86,6 +109,8 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR") | |||
86 | MACHINE_END | 109 | MACHINE_END |
87 | 110 | ||
88 | MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") | 111 | MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA") |
112 | .fixup = msm8x60_fixup, | ||
113 | .reserve = msm8x60_reserve, | ||
89 | .map_io = msm8x60_map_io, | 114 | .map_io = msm8x60_map_io, |
90 | .init_irq = msm8x60_init_irq, | 115 | .init_irq = msm8x60_init_irq, |
91 | .init_machine = msm8x60_init, | 116 | .init_machine = msm8x60_init, |
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h index f2f8d299ba95..58d5e7eec431 100644 --- a/arch/arm/mach-msm/include/mach/memory.h +++ b/arch/arm/mach-msm/include/mach/memory.h | |||
@@ -22,11 +22,11 @@ | |||
22 | #elif defined(CONFIG_ARCH_QSD8X50) | 22 | #elif defined(CONFIG_ARCH_QSD8X50) |
23 | #define PLAT_PHYS_OFFSET UL(0x20000000) | 23 | #define PLAT_PHYS_OFFSET UL(0x20000000) |
24 | #elif defined(CONFIG_ARCH_MSM7X30) | 24 | #elif defined(CONFIG_ARCH_MSM7X30) |
25 | #define PLAT_PHYS_OFFSET UL(0x00200000) | 25 | #define PLAT_PHYS_OFFSET UL(0x00000000) |
26 | #elif defined(CONFIG_ARCH_MSM8X60) | 26 | #elif defined(CONFIG_ARCH_MSM8X60) |
27 | #define PLAT_PHYS_OFFSET UL(0x40200000) | 27 | #define PLAT_PHYS_OFFSET UL(0x40000000) |
28 | #elif defined(CONFIG_ARCH_MSM8960) | 28 | #elif defined(CONFIG_ARCH_MSM8960) |
29 | #define PLAT_PHYS_OFFSET UL(0x40200000) | 29 | #define PLAT_PHYS_OFFSET UL(0x40000000) |
30 | #else | 30 | #else |
31 | #define PLAT_PHYS_OFFSET UL(0x10000000) | 31 | #define PLAT_PHYS_OFFSET UL(0x10000000) |
32 | #endif | 32 | #endif |
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c index 1a1af9e56250..727659520912 100644 --- a/arch/arm/mach-msm/platsmp.c +++ b/arch/arm/mach-msm/platsmp.c | |||
@@ -156,6 +156,12 @@ void __init smp_init_cpus(void) | |||
156 | { | 156 | { |
157 | unsigned int i, ncores = get_core_count(); | 157 | unsigned int i, ncores = get_core_count(); |
158 | 158 | ||
159 | if (ncores > nr_cpu_ids) { | ||
160 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
161 | ncores, nr_cpu_ids); | ||
162 | ncores = nr_cpu_ids; | ||
163 | } | ||
164 | |||
159 | for (i = 0; i < ncores; i++) | 165 | for (i = 0; i < ncores; i++) |
160 | set_cpu_possible(i, true); | 166 | set_cpu_possible(i, true); |
161 | 167 | ||
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 57b66d590c52..89bfb49389f2 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig | |||
@@ -36,6 +36,7 @@ config ARCH_OMAP3 | |||
36 | select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 | 36 | select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4 |
37 | select ARCH_HAS_OPP | 37 | select ARCH_HAS_OPP |
38 | select PM_OPP if PM | 38 | select PM_OPP if PM |
39 | select ARM_CPU_SUSPEND if PM | ||
39 | 40 | ||
40 | config ARCH_OMAP4 | 41 | config ARCH_OMAP4 |
41 | bool "TI OMAP4" | 42 | bool "TI OMAP4" |
@@ -50,6 +51,7 @@ config ARCH_OMAP4 | |||
50 | select ARCH_HAS_OPP | 51 | select ARCH_HAS_OPP |
51 | select PM_OPP if PM | 52 | select PM_OPP if PM |
52 | select USB_ARCH_HAS_EHCI | 53 | select USB_ARCH_HAS_EHCI |
54 | select ARM_CPU_SUSPEND if PM | ||
53 | 55 | ||
54 | comment "OMAP Core Type" | 56 | comment "OMAP Core Type" |
55 | depends on ARCH_OMAP2 | 57 | depends on ARCH_OMAP2 |
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c index ce65e9329c7b..889464dc7b2d 100644 --- a/arch/arm/mach-omap2/omap-smp.c +++ b/arch/arm/mach-omap2/omap-smp.c | |||
@@ -109,12 +109,10 @@ void __init smp_init_cpus(void) | |||
109 | ncores = scu_get_core_count(scu_base); | 109 | ncores = scu_get_core_count(scu_base); |
110 | 110 | ||
111 | /* sanity check */ | 111 | /* sanity check */ |
112 | if (ncores > NR_CPUS) { | 112 | if (ncores > nr_cpu_ids) { |
113 | printk(KERN_WARNING | 113 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
114 | "OMAP4: no. of cores (%d) greater than configured " | 114 | ncores, nr_cpu_ids); |
115 | "maximum of %d - clipping\n", | 115 | ncores = nr_cpu_ids; |
116 | ncores, NR_CPUS); | ||
117 | ncores = NR_CPUS; | ||
118 | } | 116 | } |
119 | 117 | ||
120 | for (i = 0; i < ncores; i++) | 118 | for (i = 0; i < ncores; i++) |
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c index b09e848eb6c6..ca6075717824 100644 --- a/arch/arm/mach-pxa/irq.c +++ b/arch/arm/mach-pxa/irq.c | |||
@@ -19,6 +19,8 @@ | |||
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/irq.h> | 20 | #include <linux/irq.h> |
21 | 21 | ||
22 | #include <asm/exception.h> | ||
23 | |||
22 | #include <mach/hardware.h> | 24 | #include <mach/hardware.h> |
23 | #include <mach/irqs.h> | 25 | #include <mach/irqs.h> |
24 | #include <mach/gpio.h> | 26 | #include <mach/gpio.h> |
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c index 4ae943bafa92..e83c654a58d0 100644 --- a/arch/arm/mach-realview/platsmp.c +++ b/arch/arm/mach-realview/platsmp.c | |||
@@ -52,12 +52,10 @@ void __init smp_init_cpus(void) | |||
52 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | 52 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
53 | 53 | ||
54 | /* sanity check */ | 54 | /* sanity check */ |
55 | if (ncores > NR_CPUS) { | 55 | if (ncores > nr_cpu_ids) { |
56 | printk(KERN_WARNING | 56 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
57 | "Realview: no. of cores (%d) greater than configured " | 57 | ncores, nr_cpu_ids); |
58 | "maximum of %d - clipping\n", | 58 | ncores = nr_cpu_ids; |
59 | ncores, NR_CPUS); | ||
60 | ncores = NR_CPUS; | ||
61 | } | 59 | } |
62 | 60 | ||
63 | for (i = 0; i < ncores; i++) | 61 | for (i = 0; i < ncores; i++) |
diff --git a/arch/arm/mach-rpc/include/mach/hardware.h b/arch/arm/mach-rpc/include/mach/hardware.h index dde6b3c0e299..050d63c74cc1 100644 --- a/arch/arm/mach-rpc/include/mach/hardware.h +++ b/arch/arm/mach-rpc/include/mach/hardware.h | |||
@@ -36,7 +36,7 @@ | |||
36 | 36 | ||
37 | #define EASI_SIZE 0x08000000 /* EASI I/O */ | 37 | #define EASI_SIZE 0x08000000 /* EASI I/O */ |
38 | #define EASI_START 0x08000000 | 38 | #define EASI_START 0x08000000 |
39 | #define EASI_BASE 0xe5000000 | 39 | #define EASI_BASE IOMEM(0xe5000000) |
40 | 40 | ||
41 | #define IO_START 0x03000000 /* I/O */ | 41 | #define IO_START 0x03000000 /* I/O */ |
42 | #define IO_SIZE 0x01000000 | 42 | #define IO_SIZE 0x01000000 |
@@ -51,21 +51,20 @@ | |||
51 | /* | 51 | /* |
52 | * IO Addresses | 52 | * IO Addresses |
53 | */ | 53 | */ |
54 | #define VIDC_BASE IOMEM(0xe0400000) | 54 | #define ECARD_EASI_BASE (EASI_BASE) |
55 | #define EXPMASK_BASE 0xe0360000 | 55 | #define VIDC_BASE (IO_BASE + 0x00400000) |
56 | #define IOMD_BASE IOMEM(0xe0200000) | 56 | #define EXPMASK_BASE (IO_BASE + 0x00360000) |
57 | #define IOC_BASE IOMEM(0xe0200000) | 57 | #define ECARD_IOC4_BASE (IO_BASE + 0x00270000) |
58 | #define PCIO_BASE IOMEM(0xe0010000) | 58 | #define ECARD_IOC_BASE (IO_BASE + 0x00240000) |
59 | #define FLOPPYDMA_BASE IOMEM(0xe002a000) | 59 | #define IOMD_BASE (IO_BASE + 0x00200000) |
60 | #define IOC_BASE (IO_BASE + 0x00200000) | ||
61 | #define ECARD_MEMC8_BASE (IO_BASE + 0x0002b000) | ||
62 | #define FLOPPYDMA_BASE (IO_BASE + 0x0002a000) | ||
63 | #define PCIO_BASE (IO_BASE + 0x00010000) | ||
64 | #define ECARD_MEMC_BASE (IO_BASE + 0x00000000) | ||
60 | 65 | ||
61 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) | 66 | #define vidc_writel(val) __raw_writel(val, VIDC_BASE) |
62 | 67 | ||
63 | #define IO_EC_EASI_BASE 0x81400000 | ||
64 | #define IO_EC_IOC4_BASE 0x8009c000 | ||
65 | #define IO_EC_IOC_BASE 0x80090000 | ||
66 | #define IO_EC_MEMC8_BASE 0x8000ac00 | ||
67 | #define IO_EC_MEMC_BASE 0x80000000 | ||
68 | |||
69 | #define NETSLOT_BASE 0x0302b000 | 68 | #define NETSLOT_BASE 0x0302b000 |
70 | #define NETSLOT_SIZE 0x00001000 | 69 | #define NETSLOT_SIZE 0x00001000 |
71 | 70 | ||
diff --git a/arch/arm/mach-rpc/include/mach/io.h b/arch/arm/mach-rpc/include/mach/io.h index 20da7f486e51..695f4ed2e11b 100644 --- a/arch/arm/mach-rpc/include/mach/io.h +++ b/arch/arm/mach-rpc/include/mach/io.h | |||
@@ -15,195 +15,18 @@ | |||
15 | 15 | ||
16 | #include <mach/hardware.h> | 16 | #include <mach/hardware.h> |
17 | 17 | ||
18 | #define IO_SPACE_LIMIT 0xffffffff | 18 | #define IO_SPACE_LIMIT 0xffff |
19 | 19 | ||
20 | /* | 20 | /* |
21 | * We use two different types of addressing - PC style addresses, and ARM | 21 | * We need PC style IO addressing for: |
22 | * addresses. PC style accesses the PC hardware with the normal PC IO | 22 | * - floppy (at 0x3f2,0x3f4,0x3f5,0x3f7) |
23 | * addresses, eg 0x3f8 for serial#1. ARM addresses are 0x80000000+ | 23 | * - parport (at 0x278-0x27a, 0x27b-0x27f, 0x778-0x77a) |
24 | * and are translated to the start of IO. Note that all addresses are | 24 | * - 8250 serial (only for compile) |
25 | * shifted left! | ||
26 | */ | ||
27 | #define __PORT_PCIO(x) (!((x) & 0x80000000)) | ||
28 | |||
29 | /* | ||
30 | * Dynamic IO functions. | ||
31 | */ | ||
32 | static inline void __outb (unsigned int value, unsigned int port) | ||
33 | { | ||
34 | unsigned long temp; | ||
35 | __asm__ __volatile__( | ||
36 | "tst %2, #0x80000000\n\t" | ||
37 | "mov %0, %4\n\t" | ||
38 | "addeq %0, %0, %3\n\t" | ||
39 | "strb %1, [%0, %2, lsl #2] @ outb" | ||
40 | : "=&r" (temp) | ||
41 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
42 | : "cc"); | ||
43 | } | ||
44 | |||
45 | static inline void __outw (unsigned int value, unsigned int port) | ||
46 | { | ||
47 | unsigned long temp; | ||
48 | __asm__ __volatile__( | ||
49 | "tst %2, #0x80000000\n\t" | ||
50 | "mov %0, %4\n\t" | ||
51 | "addeq %0, %0, %3\n\t" | ||
52 | "str %1, [%0, %2, lsl #2] @ outw" | ||
53 | : "=&r" (temp) | ||
54 | : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
55 | : "cc"); | ||
56 | } | ||
57 | |||
58 | static inline void __outl (unsigned int value, unsigned int port) | ||
59 | { | ||
60 | unsigned long temp; | ||
61 | __asm__ __volatile__( | ||
62 | "tst %2, #0x80000000\n\t" | ||
63 | "mov %0, %4\n\t" | ||
64 | "addeq %0, %0, %3\n\t" | ||
65 | "str %1, [%0, %2, lsl #2] @ outl" | ||
66 | : "=&r" (temp) | ||
67 | : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) | ||
68 | : "cc"); | ||
69 | } | ||
70 | |||
71 | #define DECLARE_DYN_IN(sz,fnsuffix,instr) \ | ||
72 | static inline unsigned sz __in##fnsuffix (unsigned int port) \ | ||
73 | { \ | ||
74 | unsigned long temp, value; \ | ||
75 | __asm__ __volatile__( \ | ||
76 | "tst %2, #0x80000000\n\t" \ | ||
77 | "mov %0, %4\n\t" \ | ||
78 | "addeq %0, %0, %3\n\t" \ | ||
79 | "ldr" instr " %1, [%0, %2, lsl #2] @ in" #fnsuffix \ | ||
80 | : "=&r" (temp), "=r" (value) \ | ||
81 | : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE) \ | ||
82 | : "cc"); \ | ||
83 | return (unsigned sz)value; \ | ||
84 | } | ||
85 | |||
86 | static inline void __iomem *__deprecated __ioaddr(unsigned int port) | ||
87 | { | ||
88 | void __iomem *ret; | ||
89 | if (__PORT_PCIO(port)) | ||
90 | ret = PCIO_BASE; | ||
91 | else | ||
92 | ret = IO_BASE; | ||
93 | return ret + (port << 2); | ||
94 | } | ||
95 | |||
96 | #define DECLARE_IO(sz,fnsuffix,instr) \ | ||
97 | DECLARE_DYN_IN(sz,fnsuffix,instr) | ||
98 | |||
99 | DECLARE_IO(char,b,"b") | ||
100 | DECLARE_IO(short,w,"") | ||
101 | DECLARE_IO(int,l,"") | ||
102 | |||
103 | #undef DECLARE_IO | ||
104 | #undef DECLARE_DYN_IN | ||
105 | |||
106 | /* | ||
107 | * Constant address IO functions | ||
108 | * | 25 | * |
109 | * These have to be macros for the 'J' constraint to work - | 26 | * These peripherals are found in an area of MMIO which looks very much |
110 | * +/-4096 immediate operand. | 27 | * like an ISA bus, but with registers at the low byte of each word. |
111 | */ | 28 | */ |
112 | #define __outbc(value,port) \ | 29 | #define __io(a) (PCIO_BASE + ((a) << 2)) |
113 | ({ \ | ||
114 | if (__PORT_PCIO((port))) \ | ||
115 | __asm__ __volatile__( \ | ||
116 | "strb %0, [%1, %2] @ outbc" \ | ||
117 | : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
118 | else \ | ||
119 | __asm__ __volatile__( \ | ||
120 | "strb %0, [%1, %2] @ outbc" \ | ||
121 | : : "r" (value), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
122 | }) | ||
123 | |||
124 | #define __inbc(port) \ | ||
125 | ({ \ | ||
126 | unsigned char result; \ | ||
127 | if (__PORT_PCIO((port))) \ | ||
128 | __asm__ __volatile__( \ | ||
129 | "ldrb %0, [%1, %2] @ inbc" \ | ||
130 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
131 | else \ | ||
132 | __asm__ __volatile__( \ | ||
133 | "ldrb %0, [%1, %2] @ inbc" \ | ||
134 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
135 | result; \ | ||
136 | }) | ||
137 | |||
138 | #define __outwc(value,port) \ | ||
139 | ({ \ | ||
140 | unsigned long __v = value; \ | ||
141 | if (__PORT_PCIO((port))) \ | ||
142 | __asm__ __volatile__( \ | ||
143 | "str %0, [%1, %2] @ outwc" \ | ||
144 | : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
145 | else \ | ||
146 | __asm__ __volatile__( \ | ||
147 | "str %0, [%1, %2] @ outwc" \ | ||
148 | : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
149 | }) | ||
150 | |||
151 | #define __inwc(port) \ | ||
152 | ({ \ | ||
153 | unsigned short result; \ | ||
154 | if (__PORT_PCIO((port))) \ | ||
155 | __asm__ __volatile__( \ | ||
156 | "ldr %0, [%1, %2] @ inwc" \ | ||
157 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
158 | else \ | ||
159 | __asm__ __volatile__( \ | ||
160 | "ldr %0, [%1, %2] @ inwc" \ | ||
161 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
162 | result & 0xffff; \ | ||
163 | }) | ||
164 | |||
165 | #define __outlc(value,port) \ | ||
166 | ({ \ | ||
167 | unsigned long __v = value; \ | ||
168 | if (__PORT_PCIO((port))) \ | ||
169 | __asm__ __volatile__( \ | ||
170 | "str %0, [%1, %2] @ outlc" \ | ||
171 | : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
172 | else \ | ||
173 | __asm__ __volatile__( \ | ||
174 | "str %0, [%1, %2] @ outlc" \ | ||
175 | : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2)); \ | ||
176 | }) | ||
177 | |||
178 | #define __inlc(port) \ | ||
179 | ({ \ | ||
180 | unsigned long result; \ | ||
181 | if (__PORT_PCIO((port))) \ | ||
182 | __asm__ __volatile__( \ | ||
183 | "ldr %0, [%1, %2] @ inlc" \ | ||
184 | : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2)); \ | ||
185 | else \ | ||
186 | __asm__ __volatile__( \ | ||
187 | "ldr %0, [%1, %2] @ inlc" \ | ||
188 | : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2)); \ | ||
189 | result; \ | ||
190 | }) | ||
191 | |||
192 | #define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) | ||
193 | #define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) | ||
194 | #define inl(p) (__builtin_constant_p((p)) ? __inlc(p) : __inl(p)) | ||
195 | #define outb(v,p) (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p)) | ||
196 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | ||
197 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | ||
198 | |||
199 | /* the following macro is deprecated */ | ||
200 | #define ioaddr(port) ((unsigned long)__ioaddr((port))) | ||
201 | |||
202 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | ||
203 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | ||
204 | |||
205 | #define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l) | ||
206 | #define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l) | ||
207 | 30 | ||
208 | /* | 31 | /* |
209 | * 1:1 mapping for ioremapped regions. | 32 | * 1:1 mapping for ioremapped regions. |
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c index 580b3c73d2c7..1e0e60d04622 100644 --- a/arch/arm/mach-rpc/riscpc.c +++ b/arch/arm/mach-rpc/riscpc.c | |||
@@ -74,7 +74,7 @@ static struct map_desc rpc_io_desc[] __initdata = { | |||
74 | .length = IO_SIZE , | 74 | .length = IO_SIZE , |
75 | .type = MT_DEVICE | 75 | .type = MT_DEVICE |
76 | }, { /* EASI space */ | 76 | }, { /* EASI space */ |
77 | .virtual = EASI_BASE, | 77 | .virtual = (unsigned long)EASI_BASE, |
78 | .pfn = __phys_to_pfn(EASI_START), | 78 | .pfn = __phys_to_pfn(EASI_START), |
79 | .length = EASI_SIZE, | 79 | .length = EASI_SIZE, |
80 | .type = MT_DEVICE | 80 | .type = MT_DEVICE |
diff --git a/arch/arm/mach-s3c2410/include/mach/io.h b/arch/arm/mach-s3c2410/include/mach/io.h index 9813dbf2ae4f..118749f37c4c 100644 --- a/arch/arm/mach-s3c2410/include/mach/io.h +++ b/arch/arm/mach-s3c2410/include/mach/io.h | |||
@@ -199,8 +199,6 @@ DECLARE_IO(int,l,"") | |||
199 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) | 199 | #define outw(v,p) (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p)) |
200 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) | 200 | #define outl(v,p) (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p)) |
201 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) | 201 | #define __ioaddr(p) (__builtin_constant_p((p)) ? __ioaddr(p) : __ioaddrc(p)) |
202 | /* the following macro is deprecated */ | ||
203 | #define ioaddr(port) __ioaddr((port)) | ||
204 | 202 | ||
205 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) | 203 | #define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l) |
206 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) | 204 | #define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l) |
diff --git a/arch/arm/mach-sa1100/include/mach/io.h b/arch/arm/mach-sa1100/include/mach/io.h index d8b43f3dcd2d..dfc27ff08344 100644 --- a/arch/arm/mach-sa1100/include/mach/io.h +++ b/arch/arm/mach-sa1100/include/mach/io.h | |||
@@ -10,11 +10,9 @@ | |||
10 | #ifndef __ASM_ARM_ARCH_IO_H | 10 | #ifndef __ASM_ARM_ARCH_IO_H |
11 | #define __ASM_ARM_ARCH_IO_H | 11 | #define __ASM_ARM_ARCH_IO_H |
12 | 12 | ||
13 | #define IO_SPACE_LIMIT 0xffffffff | ||
14 | |||
15 | /* | 13 | /* |
16 | * We don't actually have real ISA nor PCI buses, but there is so many | 14 | * __io() is required to be an equivalent mapping to __mem_pci() for |
17 | * drivers out there that might just work if we fake them... | 15 | * SOC_COMMON to work. |
18 | */ | 16 | */ |
19 | #define __io(a) __typesafe_io(a) | 17 | #define __io(a) __typesafe_io(a) |
20 | #define __mem_pci(a) (a) | 18 | #define __mem_pci(a) (a) |
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 66f980625a33..e4e485fa2532 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c | |||
@@ -56,6 +56,12 @@ void __init smp_init_cpus(void) | |||
56 | unsigned int ncores = shmobile_smp_get_core_count(); | 56 | unsigned int ncores = shmobile_smp_get_core_count(); |
57 | unsigned int i; | 57 | unsigned int i; |
58 | 58 | ||
59 | if (ncores > nr_cpu_ids) { | ||
60 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
61 | ncores, nr_cpu_ids); | ||
62 | ncores = nr_cpu_ids; | ||
63 | } | ||
64 | |||
59 | for (i = 0; i < ncores; i++) | 65 | for (i = 0; i < ncores; i++) |
60 | set_cpu_possible(i, true); | 66 | set_cpu_possible(i, true); |
61 | 67 | ||
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 0886cbccddee..7d2b5d03c1df 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -114,10 +114,10 @@ void __init smp_init_cpus(void) | |||
114 | { | 114 | { |
115 | unsigned int i, ncores = scu_get_core_count(scu_base); | 115 | unsigned int i, ncores = scu_get_core_count(scu_base); |
116 | 116 | ||
117 | if (ncores > NR_CPUS) { | 117 | if (ncores > nr_cpu_ids) { |
118 | printk(KERN_ERR "Tegra: no. of cores (%u) greater than configured (%u), clipping\n", | 118 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
119 | ncores, NR_CPUS); | 119 | ncores, nr_cpu_ids); |
120 | ncores = NR_CPUS; | 120 | ncores = nr_cpu_ids; |
121 | } | 121 | } |
122 | 122 | ||
123 | for (i = 0; i < ncores; i++) | 123 | for (i = 0; i < ncores; i++) |
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c index a33df5f4c27a..eb5199102cfa 100644 --- a/arch/arm/mach-ux500/platsmp.c +++ b/arch/arm/mach-ux500/platsmp.c | |||
@@ -156,12 +156,10 @@ void __init smp_init_cpus(void) | |||
156 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; | 156 | ncores = scu_base ? scu_get_core_count(scu_base) : 1; |
157 | 157 | ||
158 | /* sanity check */ | 158 | /* sanity check */ |
159 | if (ncores > NR_CPUS) { | 159 | if (ncores > nr_cpu_ids) { |
160 | printk(KERN_WARNING | 160 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", |
161 | "U8500: no. of cores (%d) greater than configured " | 161 | ncores, nr_cpu_ids); |
162 | "maximum of %d - clipping\n", | 162 | ncores = nr_cpu_ids; |
163 | ncores, NR_CPUS); | ||
164 | ncores = NR_CPUS; | ||
165 | } | 163 | } |
166 | 164 | ||
167 | for (i = 0; i < ncores; i++) | 165 | for (i = 0; i < ncores; i++) |
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index bfd32f52c2db..2b1e836a76ed 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
@@ -221,6 +221,12 @@ static void ct_ca9x4_init_cpu_map(void) | |||
221 | { | 221 | { |
222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); | 222 | int i, ncores = scu_get_core_count(MMIO_P2V(A9_MPCORE_SCU)); |
223 | 223 | ||
224 | if (ncores > nr_cpu_ids) { | ||
225 | pr_warn("SMP: %u cores greater than maximum (%u), clipping\n", | ||
226 | ncores, nr_cpu_ids); | ||
227 | ncores = nr_cpu_ids; | ||
228 | } | ||
229 | |||
224 | for (i = 0; i < ncores; ++i) | 230 | for (i = 0; i < ncores; ++i) |
225 | set_cpu_possible(i, true); | 231 | set_cpu_possible(i, true); |
226 | 232 | ||
diff --git a/arch/arm/mach-vexpress/include/mach/io.h b/arch/arm/mach-vexpress/include/mach/io.h index 748bb524ee71..13522d86685e 100644 --- a/arch/arm/mach-vexpress/include/mach/io.h +++ b/arch/arm/mach-vexpress/include/mach/io.h | |||
@@ -20,8 +20,6 @@ | |||
20 | #ifndef __ASM_ARM_ARCH_IO_H | 20 | #ifndef __ASM_ARM_ARCH_IO_H |
21 | #define __ASM_ARM_ARCH_IO_H | 21 | #define __ASM_ARM_ARCH_IO_H |
22 | 22 | ||
23 | #define IO_SPACE_LIMIT 0xffffffff | ||
24 | |||
25 | #define __io(a) __typesafe_io(a) | 23 | #define __io(a) __typesafe_io(a) |
26 | #define __mem_pci(a) (a) | 24 | #define __mem_pci(a) (a) |
27 | 25 | ||
diff --git a/arch/arm/mach-vt8500/include/mach/io.h b/arch/arm/mach-vt8500/include/mach/io.h index 9077239f78c9..46181eecf273 100644 --- a/arch/arm/mach-vt8500/include/mach/io.h +++ b/arch/arm/mach-vt8500/include/mach/io.h | |||
@@ -20,8 +20,6 @@ | |||
20 | #ifndef __ASM_ARM_ARCH_IO_H | 20 | #ifndef __ASM_ARM_ARCH_IO_H |
21 | #define __ASM_ARM_ARCH_IO_H | 21 | #define __ASM_ARM_ARCH_IO_H |
22 | 22 | ||
23 | #define IO_SPACE_LIMIT 0xffff | ||
24 | |||
25 | #define __io(a) __typesafe_io((a) + 0xf0000000) | 23 | #define __io(a) __typesafe_io((a) + 0xf0000000) |
26 | #define __mem_pci(a) (a) | 24 | #define __mem_pci(a) (a) |
27 | 25 | ||
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c index cfbcf8b95599..c335c76e0d88 100644 --- a/arch/arm/mm/alignment.c +++ b/arch/arm/mm/alignment.c | |||
@@ -86,16 +86,6 @@ core_param(alignment, ai_usermode, int, 0600); | |||
86 | #define UM_FIXUP (1 << 1) | 86 | #define UM_FIXUP (1 << 1) |
87 | #define UM_SIGNAL (1 << 2) | 87 | #define UM_SIGNAL (1 << 2) |
88 | 88 | ||
89 | #ifdef CONFIG_PROC_FS | ||
90 | static const char *usermode_action[] = { | ||
91 | "ignored", | ||
92 | "warn", | ||
93 | "fixup", | ||
94 | "fixup+warn", | ||
95 | "signal", | ||
96 | "signal+warn" | ||
97 | }; | ||
98 | |||
99 | /* Return true if and only if the ARMv6 unaligned access model is in use. */ | 89 | /* Return true if and only if the ARMv6 unaligned access model is in use. */ |
100 | static bool cpu_is_v6_unaligned(void) | 90 | static bool cpu_is_v6_unaligned(void) |
101 | { | 91 | { |
@@ -123,6 +113,16 @@ static int safe_usermode(int new_usermode, bool warn) | |||
123 | return new_usermode; | 113 | return new_usermode; |
124 | } | 114 | } |
125 | 115 | ||
116 | #ifdef CONFIG_PROC_FS | ||
117 | static const char *usermode_action[] = { | ||
118 | "ignored", | ||
119 | "warn", | ||
120 | "fixup", | ||
121 | "fixup+warn", | ||
122 | "signal", | ||
123 | "signal+warn" | ||
124 | }; | ||
125 | |||
126 | static int alignment_proc_show(struct seq_file *m, void *v) | 126 | static int alignment_proc_show(struct seq_file *m, void *v) |
127 | { | 127 | { |
128 | seq_printf(m, "User:\t\t%lu\n", ai_user); | 128 | seq_printf(m, "User:\t\t%lu\n", ai_user); |
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 9ecfdb511951..3f9b9980478e 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c | |||
@@ -16,9 +16,12 @@ | |||
16 | * along with this program; if not, write to the Free Software | 16 | * along with this program; if not, write to the Free Software |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
18 | */ | 18 | */ |
19 | #include <linux/err.h> | ||
19 | #include <linux/init.h> | 20 | #include <linux/init.h> |
20 | #include <linux/spinlock.h> | 21 | #include <linux/spinlock.h> |
21 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/of.h> | ||
24 | #include <linux/of_address.h> | ||
22 | 25 | ||
23 | #include <asm/cacheflush.h> | 26 | #include <asm/cacheflush.h> |
24 | #include <asm/hardware/cache-l2x0.h> | 27 | #include <asm/hardware/cache-l2x0.h> |
@@ -30,11 +33,19 @@ static DEFINE_SPINLOCK(l2x0_lock); | |||
30 | static uint32_t l2x0_way_mask; /* Bitmask of active ways */ | 33 | static uint32_t l2x0_way_mask; /* Bitmask of active ways */ |
31 | static uint32_t l2x0_size; | 34 | static uint32_t l2x0_size; |
32 | 35 | ||
36 | struct l2x0_regs l2x0_saved_regs; | ||
37 | |||
38 | struct l2x0_of_data { | ||
39 | void (*setup)(const struct device_node *, __u32 *, __u32 *); | ||
40 | void (*save)(void); | ||
41 | void (*resume)(void); | ||
42 | }; | ||
43 | |||
33 | static inline void cache_wait_way(void __iomem *reg, unsigned long mask) | 44 | static inline void cache_wait_way(void __iomem *reg, unsigned long mask) |
34 | { | 45 | { |
35 | /* wait for cache operation by line or way to complete */ | 46 | /* wait for cache operation by line or way to complete */ |
36 | while (readl_relaxed(reg) & mask) | 47 | while (readl_relaxed(reg) & mask) |
37 | ; | 48 | cpu_relax(); |
38 | } | 49 | } |
39 | 50 | ||
40 | #ifdef CONFIG_CACHE_PL310 | 51 | #ifdef CONFIG_CACHE_PL310 |
@@ -277,7 +288,7 @@ static void l2x0_disable(void) | |||
277 | spin_unlock_irqrestore(&l2x0_lock, flags); | 288 | spin_unlock_irqrestore(&l2x0_lock, flags); |
278 | } | 289 | } |
279 | 290 | ||
280 | static void __init l2x0_unlock(__u32 cache_id) | 291 | static void l2x0_unlock(__u32 cache_id) |
281 | { | 292 | { |
282 | int lockregs; | 293 | int lockregs; |
283 | int i; | 294 | int i; |
@@ -353,6 +364,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) | |||
353 | /* l2x0 controller is disabled */ | 364 | /* l2x0 controller is disabled */ |
354 | writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); | 365 | writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL); |
355 | 366 | ||
367 | l2x0_saved_regs.aux_ctrl = aux; | ||
368 | |||
356 | l2x0_inv_all(); | 369 | l2x0_inv_all(); |
357 | 370 | ||
358 | /* enable L2X0 */ | 371 | /* enable L2X0 */ |
@@ -372,3 +385,202 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) | |||
372 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", | 385 | printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n", |
373 | ways, cache_id, aux, l2x0_size); | 386 | ways, cache_id, aux, l2x0_size); |
374 | } | 387 | } |
388 | |||
389 | #ifdef CONFIG_OF | ||
390 | static void __init l2x0_of_setup(const struct device_node *np, | ||
391 | __u32 *aux_val, __u32 *aux_mask) | ||
392 | { | ||
393 | u32 data[2] = { 0, 0 }; | ||
394 | u32 tag = 0; | ||
395 | u32 dirty = 0; | ||
396 | u32 val = 0, mask = 0; | ||
397 | |||
398 | of_property_read_u32(np, "arm,tag-latency", &tag); | ||
399 | if (tag) { | ||
400 | mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK; | ||
401 | val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT; | ||
402 | } | ||
403 | |||
404 | of_property_read_u32_array(np, "arm,data-latency", | ||
405 | data, ARRAY_SIZE(data)); | ||
406 | if (data[0] && data[1]) { | ||
407 | mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK | | ||
408 | L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK; | ||
409 | val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) | | ||
410 | ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT); | ||
411 | } | ||
412 | |||
413 | of_property_read_u32(np, "arm,dirty-latency", &dirty); | ||
414 | if (dirty) { | ||
415 | mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK; | ||
416 | val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT; | ||
417 | } | ||
418 | |||
419 | *aux_val &= ~mask; | ||
420 | *aux_val |= val; | ||
421 | *aux_mask &= ~mask; | ||
422 | } | ||
423 | |||
424 | static void __init pl310_of_setup(const struct device_node *np, | ||
425 | __u32 *aux_val, __u32 *aux_mask) | ||
426 | { | ||
427 | u32 data[3] = { 0, 0, 0 }; | ||
428 | u32 tag[3] = { 0, 0, 0 }; | ||
429 | u32 filter[2] = { 0, 0 }; | ||
430 | |||
431 | of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag)); | ||
432 | if (tag[0] && tag[1] && tag[2]) | ||
433 | writel_relaxed( | ||
434 | ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | | ||
435 | ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | | ||
436 | ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), | ||
437 | l2x0_base + L2X0_TAG_LATENCY_CTRL); | ||
438 | |||
439 | of_property_read_u32_array(np, "arm,data-latency", | ||
440 | data, ARRAY_SIZE(data)); | ||
441 | if (data[0] && data[1] && data[2]) | ||
442 | writel_relaxed( | ||
443 | ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) | | ||
444 | ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) | | ||
445 | ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT), | ||
446 | l2x0_base + L2X0_DATA_LATENCY_CTRL); | ||
447 | |||
448 | of_property_read_u32_array(np, "arm,filter-ranges", | ||
449 | filter, ARRAY_SIZE(filter)); | ||
450 | if (filter[1]) { | ||
451 | writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M), | ||
452 | l2x0_base + L2X0_ADDR_FILTER_END); | ||
453 | writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN, | ||
454 | l2x0_base + L2X0_ADDR_FILTER_START); | ||
455 | } | ||
456 | } | ||
457 | |||
458 | static void __init pl310_save(void) | ||
459 | { | ||
460 | u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & | ||
461 | L2X0_CACHE_ID_RTL_MASK; | ||
462 | |||
463 | l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base + | ||
464 | L2X0_TAG_LATENCY_CTRL); | ||
465 | l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base + | ||
466 | L2X0_DATA_LATENCY_CTRL); | ||
467 | l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base + | ||
468 | L2X0_ADDR_FILTER_END); | ||
469 | l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base + | ||
470 | L2X0_ADDR_FILTER_START); | ||
471 | |||
472 | if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { | ||
473 | /* | ||
474 | * From r2p0, there is Prefetch offset/control register | ||
475 | */ | ||
476 | l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base + | ||
477 | L2X0_PREFETCH_CTRL); | ||
478 | /* | ||
479 | * From r3p0, there is Power control register | ||
480 | */ | ||
481 | if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) | ||
482 | l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base + | ||
483 | L2X0_POWER_CTRL); | ||
484 | } | ||
485 | } | ||
486 | |||
487 | static void l2x0_resume(void) | ||
488 | { | ||
489 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { | ||
490 | /* restore aux ctrl and enable l2 */ | ||
491 | l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID)); | ||
492 | |||
493 | writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base + | ||
494 | L2X0_AUX_CTRL); | ||
495 | |||
496 | l2x0_inv_all(); | ||
497 | |||
498 | writel_relaxed(1, l2x0_base + L2X0_CTRL); | ||
499 | } | ||
500 | } | ||
501 | |||
502 | static void pl310_resume(void) | ||
503 | { | ||
504 | u32 l2x0_revision; | ||
505 | |||
506 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { | ||
507 | /* restore pl310 setup */ | ||
508 | writel_relaxed(l2x0_saved_regs.tag_latency, | ||
509 | l2x0_base + L2X0_TAG_LATENCY_CTRL); | ||
510 | writel_relaxed(l2x0_saved_regs.data_latency, | ||
511 | l2x0_base + L2X0_DATA_LATENCY_CTRL); | ||
512 | writel_relaxed(l2x0_saved_regs.filter_end, | ||
513 | l2x0_base + L2X0_ADDR_FILTER_END); | ||
514 | writel_relaxed(l2x0_saved_regs.filter_start, | ||
515 | l2x0_base + L2X0_ADDR_FILTER_START); | ||
516 | |||
517 | l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) & | ||
518 | L2X0_CACHE_ID_RTL_MASK; | ||
519 | |||
520 | if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) { | ||
521 | writel_relaxed(l2x0_saved_regs.prefetch_ctrl, | ||
522 | l2x0_base + L2X0_PREFETCH_CTRL); | ||
523 | if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0) | ||
524 | writel_relaxed(l2x0_saved_regs.pwr_ctrl, | ||
525 | l2x0_base + L2X0_POWER_CTRL); | ||
526 | } | ||
527 | } | ||
528 | |||
529 | l2x0_resume(); | ||
530 | } | ||
531 | |||
532 | static const struct l2x0_of_data pl310_data = { | ||
533 | pl310_of_setup, | ||
534 | pl310_save, | ||
535 | pl310_resume, | ||
536 | }; | ||
537 | |||
538 | static const struct l2x0_of_data l2x0_data = { | ||
539 | l2x0_of_setup, | ||
540 | NULL, | ||
541 | l2x0_resume, | ||
542 | }; | ||
543 | |||
544 | static const struct of_device_id l2x0_ids[] __initconst = { | ||
545 | { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data }, | ||
546 | { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data }, | ||
547 | { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data }, | ||
548 | {} | ||
549 | }; | ||
550 | |||
551 | int __init l2x0_of_init(__u32 aux_val, __u32 aux_mask) | ||
552 | { | ||
553 | struct device_node *np; | ||
554 | struct l2x0_of_data *data; | ||
555 | struct resource res; | ||
556 | |||
557 | np = of_find_matching_node(NULL, l2x0_ids); | ||
558 | if (!np) | ||
559 | return -ENODEV; | ||
560 | |||
561 | if (of_address_to_resource(np, 0, &res)) | ||
562 | return -ENODEV; | ||
563 | |||
564 | l2x0_base = ioremap(res.start, resource_size(&res)); | ||
565 | if (!l2x0_base) | ||
566 | return -ENOMEM; | ||
567 | |||
568 | l2x0_saved_regs.phy_base = res.start; | ||
569 | |||
570 | data = of_match_node(l2x0_ids, np)->data; | ||
571 | |||
572 | /* L2 configuration can only be changed if the cache is disabled */ | ||
573 | if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & 1)) { | ||
574 | if (data->setup) | ||
575 | data->setup(np, &aux_val, &aux_mask); | ||
576 | } | ||
577 | |||
578 | if (data->save) | ||
579 | data->save(); | ||
580 | |||
581 | l2x0_init(l2x0_base, aux_val, aux_mask); | ||
582 | |||
583 | outer_cache.resume = data->resume; | ||
584 | return 0; | ||
585 | } | ||
586 | #endif | ||
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index c3ff82f92d9c..235eb775fc78 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c | |||
@@ -123,8 +123,8 @@ static void __dma_free_buffer(struct page *page, size_t size) | |||
123 | #endif | 123 | #endif |
124 | 124 | ||
125 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) | 125 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
126 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) | 126 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PMD_SHIFT) |
127 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | 127 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PMD_SHIFT) |
128 | 128 | ||
129 | /* | 129 | /* |
130 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations | 130 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
@@ -183,7 +183,7 @@ static int __init consistent_init(void) | |||
183 | } | 183 | } |
184 | 184 | ||
185 | consistent_pte[i++] = pte; | 185 | consistent_pte[i++] = pte; |
186 | base += (1 << PGDIR_SHIFT); | 186 | base += PMD_SIZE; |
187 | } while (base < CONSISTENT_END); | 187 | } while (base < CONSISTENT_END); |
188 | 188 | ||
189 | return ret; | 189 | return ret; |
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c index 3b5ea68acbb8..aa33949fef60 100644 --- a/arch/arm/mm/fault.c +++ b/arch/arm/mm/fault.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/highmem.h> | 20 | #include <linux/highmem.h> |
21 | #include <linux/perf_event.h> | 21 | #include <linux/perf_event.h> |
22 | 22 | ||
23 | #include <asm/exception.h> | ||
23 | #include <asm/system.h> | 24 | #include <asm/system.h> |
24 | #include <asm/pgtable.h> | 25 | #include <asm/pgtable.h> |
25 | #include <asm/tlbflush.h> | 26 | #include <asm/tlbflush.h> |
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h index 010566799c80..ad7cce3bc431 100644 --- a/arch/arm/mm/mm.h +++ b/arch/arm/mm/mm.h | |||
@@ -12,8 +12,8 @@ static inline pmd_t *pmd_off_k(unsigned long virt) | |||
12 | 12 | ||
13 | struct mem_type { | 13 | struct mem_type { |
14 | pteval_t prot_pte; | 14 | pteval_t prot_pte; |
15 | unsigned int prot_l1; | 15 | pmdval_t prot_l1; |
16 | unsigned int prot_sect; | 16 | pmdval_t prot_sect; |
17 | unsigned int domain; | 17 | unsigned int domain; |
18 | }; | 18 | }; |
19 | 19 | ||
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c index 594d677b92c8..226f1804be12 100644 --- a/arch/arm/mm/mmu.c +++ b/arch/arm/mm/mmu.c | |||
@@ -60,7 +60,7 @@ EXPORT_SYMBOL(pgprot_kernel); | |||
60 | struct cachepolicy { | 60 | struct cachepolicy { |
61 | const char policy[16]; | 61 | const char policy[16]; |
62 | unsigned int cr_mask; | 62 | unsigned int cr_mask; |
63 | unsigned int pmd; | 63 | pmdval_t pmd; |
64 | pteval_t pte; | 64 | pteval_t pte; |
65 | }; | 65 | }; |
66 | 66 | ||
@@ -288,7 +288,7 @@ static void __init build_mem_type_table(void) | |||
288 | { | 288 | { |
289 | struct cachepolicy *cp; | 289 | struct cachepolicy *cp; |
290 | unsigned int cr = get_cr(); | 290 | unsigned int cr = get_cr(); |
291 | unsigned int user_pgprot, kern_pgprot, vecs_pgprot; | 291 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
292 | int cpu_arch = cpu_architecture(); | 292 | int cpu_arch = cpu_architecture(); |
293 | int i; | 293 | int i; |
294 | 294 | ||
@@ -863,14 +863,14 @@ static inline void prepare_page_table(void) | |||
863 | /* | 863 | /* |
864 | * Clear out all the mappings below the kernel image. | 864 | * Clear out all the mappings below the kernel image. |
865 | */ | 865 | */ |
866 | for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) | 866 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
867 | pmd_clear(pmd_off_k(addr)); | 867 | pmd_clear(pmd_off_k(addr)); |
868 | 868 | ||
869 | #ifdef CONFIG_XIP_KERNEL | 869 | #ifdef CONFIG_XIP_KERNEL |
870 | /* The XIP kernel is mapped in the module area -- skip over it */ | 870 | /* The XIP kernel is mapped in the module area -- skip over it */ |
871 | addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; | 871 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
872 | #endif | 872 | #endif |
873 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) | 873 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
874 | pmd_clear(pmd_off_k(addr)); | 874 | pmd_clear(pmd_off_k(addr)); |
875 | 875 | ||
876 | /* | 876 | /* |
@@ -885,10 +885,12 @@ static inline void prepare_page_table(void) | |||
885 | * memory bank, up to the end of the vmalloc region. | 885 | * memory bank, up to the end of the vmalloc region. |
886 | */ | 886 | */ |
887 | for (addr = __phys_to_virt(end); | 887 | for (addr = __phys_to_virt(end); |
888 | addr < VMALLOC_END; addr += PGDIR_SIZE) | 888 | addr < VMALLOC_END; addr += PMD_SIZE) |
889 | pmd_clear(pmd_off_k(addr)); | 889 | pmd_clear(pmd_off_k(addr)); |
890 | } | 890 | } |
891 | 891 | ||
892 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) | ||
893 | |||
892 | /* | 894 | /* |
893 | * Reserve the special regions of memory | 895 | * Reserve the special regions of memory |
894 | */ | 896 | */ |
@@ -898,7 +900,7 @@ void __init arm_mm_memblock_reserve(void) | |||
898 | * Reserve the page tables. These are already in use, | 900 | * Reserve the page tables. These are already in use, |
899 | * and can only be in node 0. | 901 | * and can only be in node 0. |
900 | */ | 902 | */ |
901 | memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); | 903 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
902 | 904 | ||
903 | #ifdef CONFIG_SA1111 | 905 | #ifdef CONFIG_SA1111 |
904 | /* | 906 | /* |
@@ -926,7 +928,7 @@ static void __init devicemaps_init(struct machine_desc *mdesc) | |||
926 | */ | 928 | */ |
927 | vectors_page = early_alloc(PAGE_SIZE); | 929 | vectors_page = early_alloc(PAGE_SIZE); |
928 | 930 | ||
929 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) | 931 | for (addr = VMALLOC_END; addr; addr += PMD_SIZE) |
930 | pmd_clear(pmd_off_k(addr)); | 932 | pmd_clear(pmd_off_k(addr)); |
931 | 933 | ||
932 | /* | 934 | /* |
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 9049c0764db2..9591c8e9fb8c 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S | |||
@@ -218,7 +218,7 @@ ENDPROC(cpu_v7_set_pte_ext) | |||
218 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ | 218 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ |
219 | .globl cpu_v7_suspend_size | 219 | .globl cpu_v7_suspend_size |
220 | .equ cpu_v7_suspend_size, 4 * 9 | 220 | .equ cpu_v7_suspend_size, 4 * 9 |
221 | #ifdef CONFIG_PM_SLEEP | 221 | #ifdef CONFIG_ARM_CPU_SUSPEND |
222 | ENTRY(cpu_v7_do_suspend) | 222 | ENTRY(cpu_v7_do_suspend) |
223 | stmfd sp!, {r4 - r11, lr} | 223 | stmfd sp!, {r4 - r11, lr} |
224 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID | 224 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig index bb8f4a6b3e37..5b605a9eb091 100644 --- a/arch/arm/plat-omap/Kconfig +++ b/arch/arm/plat-omap/Kconfig | |||
@@ -14,6 +14,7 @@ config ARCH_OMAP1 | |||
14 | select CLKDEV_LOOKUP | 14 | select CLKDEV_LOOKUP |
15 | select CLKSRC_MMIO | 15 | select CLKSRC_MMIO |
16 | select GENERIC_IRQ_CHIP | 16 | select GENERIC_IRQ_CHIP |
17 | select HAVE_IDE | ||
17 | help | 18 | help |
18 | "Systems based on omap7xx, omap15xx or omap16xx" | 19 | "Systems based on omap7xx, omap15xx or omap16xx" |
19 | 20 | ||
diff --git a/arch/arm/vfp/Makefile b/arch/arm/vfp/Makefile index 6de73aab0195..a81404c09d5d 100644 --- a/arch/arm/vfp/Makefile +++ b/arch/arm/vfp/Makefile | |||
@@ -7,7 +7,7 @@ | |||
7 | # ccflags-y := -DDEBUG | 7 | # ccflags-y := -DDEBUG |
8 | # asflags-y := -DDEBUG | 8 | # asflags-y := -DDEBUG |
9 | 9 | ||
10 | KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp) | 10 | KBUILD_AFLAGS :=$(KBUILD_AFLAGS:-msoft-float=-Wa,-mfpu=softvfp+vfp -mfloat-abi=soft) |
11 | LDFLAGS +=--no-warn-mismatch | 11 | LDFLAGS +=--no-warn-mismatch |
12 | 12 | ||
13 | obj-y += vfp.o | 13 | obj-y += vfp.o |