diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-s3c2410/s3c2410.c | 19 | ||||
-rw-r--r-- | arch/arm/mach-s3c2412/s3c2412.c | 21 | ||||
-rw-r--r-- | arch/arm/mach-s3c2443/clock.c | 35 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/clock.c | 25 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/include/plat/clock.h | 15 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/pm.c | 4 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/s3c244x.c | 21 |
7 files changed, 104 insertions, 36 deletions
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index 4e23bc05f4b5..feb141b1f915 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/clk.h> | ||
19 | #include <linux/sysdev.h> | 20 | #include <linux/sysdev.h> |
20 | #include <linux/serial_core.h> | 21 | #include <linux/serial_core.h> |
21 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
@@ -28,6 +29,8 @@ | |||
28 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
29 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
30 | 31 | ||
32 | #include <plat/cpu-freq.h> | ||
33 | |||
31 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
32 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
33 | 36 | ||
@@ -65,13 +68,19 @@ void __init s3c2410_map_io(void) | |||
65 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); | 68 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
66 | } | 69 | } |
67 | 70 | ||
68 | void __init s3c2410_init_clocks(int xtal) | 71 | void __init_or_cpufreq s3c2410_setup_clocks(void) |
69 | { | 72 | { |
73 | struct clk *xtal_clk; | ||
70 | unsigned long tmp; | 74 | unsigned long tmp; |
75 | unsigned long xtal; | ||
71 | unsigned long fclk; | 76 | unsigned long fclk; |
72 | unsigned long hclk; | 77 | unsigned long hclk; |
73 | unsigned long pclk; | 78 | unsigned long pclk; |
74 | 79 | ||
80 | xtal_clk = clk_get(NULL, "xtal"); | ||
81 | xtal = clk_get_rate(xtal_clk); | ||
82 | clk_put(xtal_clk); | ||
83 | |||
75 | /* now we've got our machine bits initialised, work out what | 84 | /* now we've got our machine bits initialised, work out what |
76 | * clocks we've got */ | 85 | * clocks we've got */ |
77 | 86 | ||
@@ -93,7 +102,13 @@ void __init s3c2410_init_clocks(int xtal) | |||
93 | * console to use them | 102 | * console to use them |
94 | */ | 103 | */ |
95 | 104 | ||
96 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 105 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
106 | } | ||
107 | |||
108 | void __init s3c2410_init_clocks(int xtal) | ||
109 | { | ||
110 | s3c24xx_register_baseclocks(xtal); | ||
111 | s3c2410_setup_clocks(); | ||
97 | s3c2410_baseclk_add(); | 112 | s3c2410_baseclk_add(); |
98 | } | 113 | } |
99 | 114 | ||
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c index 4bd2b5fb8669..5b5aba69ec3f 100644 --- a/arch/arm/mach-s3c2412/s3c2412.c +++ b/arch/arm/mach-s3c2412/s3c2412.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include <linux/list.h> | 16 | #include <linux/list.h> |
17 | #include <linux/timer.h> | 17 | #include <linux/timer.h> |
18 | #include <linux/init.h> | 18 | #include <linux/init.h> |
19 | #include <linux/clk.h> | ||
19 | #include <linux/delay.h> | 20 | #include <linux/delay.h> |
20 | #include <linux/sysdev.h> | 21 | #include <linux/sysdev.h> |
21 | #include <linux/serial_core.h> | 22 | #include <linux/serial_core.h> |
@@ -33,6 +34,8 @@ | |||
33 | #include <mach/reset.h> | 34 | #include <mach/reset.h> |
34 | #include <mach/idle.h> | 35 | #include <mach/idle.h> |
35 | 36 | ||
37 | #include <plat/cpu-freq.h> | ||
38 | |||
36 | #include <mach/regs-clock.h> | 39 | #include <mach/regs-clock.h> |
37 | #include <plat/regs-serial.h> | 40 | #include <plat/regs-serial.h> |
38 | #include <mach/regs-power.h> | 41 | #include <mach/regs-power.h> |
@@ -156,17 +159,23 @@ void __init s3c2412_map_io(void) | |||
156 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); | 159 | iotable_init(s3c2412_iodesc, ARRAY_SIZE(s3c2412_iodesc)); |
157 | } | 160 | } |
158 | 161 | ||
159 | void __init s3c2412_init_clocks(int xtal) | 162 | void __init_or_cpufreq s3c2412_setup_clocks(void) |
160 | { | 163 | { |
164 | struct clk *xtal_clk; | ||
161 | unsigned long tmp; | 165 | unsigned long tmp; |
166 | unsigned long xtal; | ||
162 | unsigned long fclk; | 167 | unsigned long fclk; |
163 | unsigned long hclk; | 168 | unsigned long hclk; |
164 | unsigned long pclk; | 169 | unsigned long pclk; |
165 | 170 | ||
171 | xtal_clk = clk_get(NULL, "xtal"); | ||
172 | xtal = clk_get_rate(xtal_clk); | ||
173 | clk_put(xtal_clk); | ||
174 | |||
166 | /* now we've got our machine bits initialised, work out what | 175 | /* now we've got our machine bits initialised, work out what |
167 | * clocks we've got */ | 176 | * clocks we've got */ |
168 | 177 | ||
169 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal*2); | 178 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal * 2); |
170 | 179 | ||
171 | clk_mpll.rate = fclk; | 180 | clk_mpll.rate = fclk; |
172 | 181 | ||
@@ -183,11 +192,17 @@ void __init s3c2412_init_clocks(int xtal) | |||
183 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | 192 | printk("S3C2412: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
184 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | 193 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
185 | 194 | ||
195 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
196 | } | ||
197 | |||
198 | void __init s3c2412_init_clocks(int xtal) | ||
199 | { | ||
186 | /* initialise the clocks here, to allow other things like the | 200 | /* initialise the clocks here, to allow other things like the |
187 | * console to use them | 201 | * console to use them |
188 | */ | 202 | */ |
189 | 203 | ||
190 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 204 | s3c24xx_register_baseclocks(xtal); |
205 | s3c2412_setup_clocks(); | ||
191 | s3c2412_baseclk_add(); | 206 | s3c2412_baseclk_add(); |
192 | } | 207 | } |
193 | 208 | ||
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c index f854e7385e3c..1df8429242b8 100644 --- a/arch/arm/mach-s3c2443/clock.c +++ b/arch/arm/mach-s3c2443/clock.c | |||
@@ -39,6 +39,8 @@ | |||
39 | 39 | ||
40 | #include <mach/regs-s3c2443-clock.h> | 40 | #include <mach/regs-s3c2443-clock.h> |
41 | 41 | ||
42 | #include <plat/cpu-freq.h> | ||
43 | |||
42 | #include <plat/s3c2443.h> | 44 | #include <plat/s3c2443.h> |
43 | #include <plat/clock.h> | 45 | #include <plat/clock.h> |
44 | #include <plat/cpu.h> | 46 | #include <plat/cpu.h> |
@@ -1011,22 +1013,20 @@ static struct clk *clks[] __initdata = { | |||
1011 | &clk_prediv, | 1013 | &clk_prediv, |
1012 | }; | 1014 | }; |
1013 | 1015 | ||
1014 | void __init s3c2443_init_clocks(int xtal) | 1016 | void __init_or_cpufreq s3c2443_setup_clocks(void) |
1015 | { | 1017 | { |
1016 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | ||
1017 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); | 1018 | unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); |
1018 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); | 1019 | unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); |
1020 | struct clk *xtal_clk; | ||
1021 | unsigned long xtal; | ||
1019 | unsigned long pll; | 1022 | unsigned long pll; |
1020 | unsigned long fclk; | 1023 | unsigned long fclk; |
1021 | unsigned long hclk; | 1024 | unsigned long hclk; |
1022 | unsigned long pclk; | 1025 | unsigned long pclk; |
1023 | struct clk *clkp; | ||
1024 | int ret; | ||
1025 | int ptr; | ||
1026 | 1026 | ||
1027 | /* s3c2443 parents h and p clocks from prediv */ | 1027 | xtal_clk = clk_get(NULL, "xtal"); |
1028 | clk_h.parent = &clk_prediv; | 1028 | xtal = clk_get_rate(xtal_clk); |
1029 | clk_p.parent = &clk_prediv; | 1029 | clk_put(xtal_clk); |
1030 | 1030 | ||
1031 | pll = s3c2443_get_mpll(mpllcon, xtal); | 1031 | pll = s3c2443_get_mpll(mpllcon, xtal); |
1032 | clk_msysclk.rate = pll; | 1032 | clk_msysclk.rate = pll; |
@@ -1036,13 +1036,29 @@ void __init s3c2443_init_clocks(int xtal) | |||
1036 | hclk /= s3c2443_get_hdiv(clkdiv0); | 1036 | hclk /= s3c2443_get_hdiv(clkdiv0); |
1037 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); | 1037 | pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); |
1038 | 1038 | ||
1039 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 1039 | s3c24xx_setup_clocks(fclk, hclk, pclk); |
1040 | 1040 | ||
1041 | printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", | 1041 | printk("S3C2443: mpll %s %ld.%03ld MHz, cpu %ld.%03ld MHz, mem %ld.%03ld MHz, pclk %ld.%03ld MHz\n", |
1042 | (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", | 1042 | (mpllcon & S3C2443_PLLCON_OFF) ? "off":"on", |
1043 | print_mhz(pll), print_mhz(fclk), | 1043 | print_mhz(pll), print_mhz(fclk), |
1044 | print_mhz(hclk), print_mhz(pclk)); | 1044 | print_mhz(hclk), print_mhz(pclk)); |
1045 | 1045 | ||
1046 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
1047 | } | ||
1048 | |||
1049 | void __init s3c2443_init_clocks(int xtal) | ||
1050 | { | ||
1051 | struct clk *clkp; | ||
1052 | unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); | ||
1053 | int ret; | ||
1054 | int ptr; | ||
1055 | |||
1056 | /* s3c2443 parents h and p clocks from prediv */ | ||
1057 | clk_h.parent = &clk_prediv; | ||
1058 | clk_p.parent = &clk_prediv; | ||
1059 | |||
1060 | s3c24xx_register_baseclocks(xtal); | ||
1061 | s3c2443_setup_clocks(); | ||
1046 | s3c2443_clk_initparents(); | 1062 | s3c2443_clk_initparents(); |
1047 | 1063 | ||
1048 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { | 1064 | for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) { |
@@ -1056,7 +1072,6 @@ void __init s3c2443_init_clocks(int xtal) | |||
1056 | } | 1072 | } |
1057 | 1073 | ||
1058 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); | 1074 | clk_epll.rate = s3c2443_get_epll(epllcon, xtal); |
1059 | |||
1060 | clk_usb_bus.parent = &clk_usb_bus_host; | 1075 | clk_usb_bus.parent = &clk_usb_bus_host; |
1061 | 1076 | ||
1062 | /* ensure usb bus clock is within correct rate of 48MHz */ | 1077 | /* ensure usb bus clock is within correct rate of 48MHz */ |
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c index 334e696200be..a4a0a67a3074 100644 --- a/arch/arm/plat-s3c24xx/clock.c +++ b/arch/arm/plat-s3c24xx/clock.c | |||
@@ -47,6 +47,8 @@ | |||
47 | #include <mach/regs-clock.h> | 47 | #include <mach/regs-clock.h> |
48 | #include <mach/regs-gpio.h> | 48 | #include <mach/regs-gpio.h> |
49 | 49 | ||
50 | #include <plat/cpu-freq.h> | ||
51 | |||
50 | #include <plat/clock.h> | 52 | #include <plat/clock.h> |
51 | #include <plat/cpu.h> | 53 | #include <plat/cpu.h> |
52 | #include <plat/pll.h> | 54 | #include <plat/pll.h> |
@@ -327,24 +329,24 @@ int s3c24xx_register_clocks(struct clk **clks, int nr_clks) | |||
327 | 329 | ||
328 | /* initalise all the clocks */ | 330 | /* initalise all the clocks */ |
329 | 331 | ||
330 | int __init s3c24xx_setup_clocks(unsigned long xtal, | 332 | void __init_or_cpufreq s3c24xx_setup_clocks(unsigned long fclk, |
331 | unsigned long fclk, | 333 | unsigned long hclk, |
332 | unsigned long hclk, | 334 | unsigned long pclk) |
333 | unsigned long pclk) | ||
334 | { | 335 | { |
335 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | 336 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), |
336 | 337 | clk_xtal.rate); | |
337 | /* initialise the main system clocks */ | ||
338 | |||
339 | clk_xtal.rate = xtal; | ||
340 | clk_upll.rate = s3c24xx_get_pll(__raw_readl(S3C2410_UPLLCON), xtal); | ||
341 | 338 | ||
342 | clk_mpll.rate = fclk; | 339 | clk_mpll.rate = fclk; |
343 | clk_h.rate = hclk; | 340 | clk_h.rate = hclk; |
344 | clk_p.rate = pclk; | 341 | clk_p.rate = pclk; |
345 | clk_f.rate = fclk; | 342 | clk_f.rate = fclk; |
343 | } | ||
346 | 344 | ||
347 | /* assume uart clocks are correctly setup */ | 345 | int __init s3c24xx_register_baseclocks(unsigned long xtal) |
346 | { | ||
347 | printk(KERN_INFO "S3C24XX Clocks, (c) 2004 Simtec Electronics\n"); | ||
348 | |||
349 | clk_xtal.rate = xtal; | ||
348 | 350 | ||
349 | /* register our clocks */ | 351 | /* register our clocks */ |
350 | 352 | ||
@@ -368,3 +370,4 @@ int __init s3c24xx_setup_clocks(unsigned long xtal, | |||
368 | 370 | ||
369 | return 0; | 371 | return 0; |
370 | } | 372 | } |
373 | |||
diff --git a/arch/arm/plat-s3c24xx/include/plat/clock.h b/arch/arm/plat-s3c24xx/include/plat/clock.h index 88a00c35b685..ba174aab76f2 100644 --- a/arch/arm/plat-s3c24xx/include/plat/clock.h +++ b/arch/arm/plat-s3c24xx/include/plat/clock.h | |||
@@ -60,7 +60,14 @@ extern int s3c2410_clkcon_enable(struct clk *clk, int enable); | |||
60 | extern int s3c24xx_register_clock(struct clk *clk); | 60 | extern int s3c24xx_register_clock(struct clk *clk); |
61 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); | 61 | extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks); |
62 | 62 | ||
63 | extern int s3c24xx_setup_clocks(unsigned long xtal, | 63 | extern int s3c24xx_register_baseclocks(unsigned long xtal); |
64 | unsigned long fclk, | 64 | |
65 | unsigned long hclk, | 65 | extern void s3c24xx_setup_clocks(unsigned long fclk, |
66 | unsigned long pclk); | 66 | unsigned long hclk, |
67 | unsigned long pclk); | ||
68 | |||
69 | extern void s3c2410_setup_clocks(void); | ||
70 | extern void s3c2412_setup_clocks(void); | ||
71 | extern void s3c244x_setup_clocks(void); | ||
72 | extern void s3c2443_setup_clocks(void); | ||
73 | |||
diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c index 8efb57ad5019..bc37cf49f973 100644 --- a/arch/arm/plat-s3c24xx/pm.c +++ b/arch/arm/plat-s3c24xx/pm.c | |||
@@ -76,11 +76,13 @@ static struct sleep_save core_save[] = { | |||
76 | SAVE_ITEM(S3C2410_BANKCON4), | 76 | SAVE_ITEM(S3C2410_BANKCON4), |
77 | SAVE_ITEM(S3C2410_BANKCON5), | 77 | SAVE_ITEM(S3C2410_BANKCON5), |
78 | 78 | ||
79 | #ifndef CONFIG_CPU_FREQ | ||
79 | SAVE_ITEM(S3C2410_CLKDIVN), | 80 | SAVE_ITEM(S3C2410_CLKDIVN), |
80 | SAVE_ITEM(S3C2410_MPLLCON), | 81 | SAVE_ITEM(S3C2410_MPLLCON), |
82 | SAVE_ITEM(S3C2410_REFRESH), | ||
83 | #endif | ||
81 | SAVE_ITEM(S3C2410_UPLLCON), | 84 | SAVE_ITEM(S3C2410_UPLLCON), |
82 | SAVE_ITEM(S3C2410_CLKSLOW), | 85 | SAVE_ITEM(S3C2410_CLKSLOW), |
83 | SAVE_ITEM(S3C2410_REFRESH), | ||
84 | }; | 86 | }; |
85 | 87 | ||
86 | static struct gpio_sleep { | 88 | static struct gpio_sleep { |
diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c index 7f33cef20bac..494368403055 100644 --- a/arch/arm/plat-s3c24xx/s3c244x.c +++ b/arch/arm/plat-s3c24xx/s3c244x.c | |||
@@ -29,6 +29,8 @@ | |||
29 | #include <mach/hardware.h> | 29 | #include <mach/hardware.h> |
30 | #include <asm/irq.h> | 30 | #include <asm/irq.h> |
31 | 31 | ||
32 | #include <plat/cpu-freq.h> | ||
33 | |||
32 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
33 | #include <plat/regs-serial.h> | 35 | #include <plat/regs-serial.h> |
34 | #include <mach/regs-gpio.h> | 36 | #include <mach/regs-gpio.h> |
@@ -71,15 +73,18 @@ void __init s3c244x_map_io(void) | |||
71 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; | 73 | s3c_device_usbgadget.name = "s3c2440-usbgadget"; |
72 | } | 74 | } |
73 | 75 | ||
74 | void __init s3c244x_init_clocks(int xtal) | 76 | void __init_or_cpufreq s3c244x_setup_clocks(void) |
75 | { | 77 | { |
78 | struct clk *xtal_clk; | ||
76 | unsigned long clkdiv; | 79 | unsigned long clkdiv; |
77 | unsigned long camdiv; | 80 | unsigned long camdiv; |
81 | unsigned long xtal; | ||
78 | unsigned long hclk, fclk, pclk; | 82 | unsigned long hclk, fclk, pclk; |
79 | int hdiv = 1; | 83 | int hdiv = 1; |
80 | 84 | ||
81 | /* now we've got our machine bits initialised, work out what | 85 | xtal_clk = clk_get(NULL, "xtal"); |
82 | * clocks we've got */ | 86 | xtal = clk_get_rate(xtal_clk); |
87 | clk_put(xtal_clk); | ||
83 | 88 | ||
84 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; | 89 | fclk = s3c24xx_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2; |
85 | 90 | ||
@@ -107,18 +112,24 @@ void __init s3c244x_init_clocks(int xtal) | |||
107 | } | 112 | } |
108 | 113 | ||
109 | hclk = fclk / hdiv; | 114 | hclk = fclk / hdiv; |
110 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1); | 115 | pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN) ? 2 : 1); |
111 | 116 | ||
112 | /* print brief summary of clocks, etc */ | 117 | /* print brief summary of clocks, etc */ |
113 | 118 | ||
114 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", | 119 | printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n", |
115 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); | 120 | print_mhz(fclk), print_mhz(hclk), print_mhz(pclk)); |
116 | 121 | ||
122 | s3c24xx_setup_clocks(fclk, hclk, pclk); | ||
123 | } | ||
124 | |||
125 | void __init s3c244x_init_clocks(int xtal) | ||
126 | { | ||
117 | /* initialise the clocks here, to allow other things like the | 127 | /* initialise the clocks here, to allow other things like the |
118 | * console to use them, and to add new ones after the initialisation | 128 | * console to use them, and to add new ones after the initialisation |
119 | */ | 129 | */ |
120 | 130 | ||
121 | s3c24xx_setup_clocks(xtal, fclk, hclk, pclk); | 131 | s3c24xx_register_baseclocks(xtal); |
132 | s3c244x_setup_clocks(); | ||
122 | s3c2410_baseclk_add(); | 133 | s3c2410_baseclk_add(); |
123 | } | 134 | } |
124 | 135 | ||