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-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/Kconfig.debug20
-rw-r--r--arch/arm/boot/dts/Makefile51
-rw-r--r--arch/arm/boot/dts/aks-cdu.dts6
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts105
-rw-r--r--arch/arm/boot/dts/am335x-pepper.dts653
-rw-r--r--arch/arm/boot/dts/am4372.dtsi8
-rw-r--r--arch/arm/boot/dts/am437x-gp-evm.dts71
-rw-r--r--arch/arm/boot/dts/am437x-sk-evm.dts613
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts59
-rw-r--r--arch/arm/boot/dts/animeo_ip.dts8
-rw-r--r--arch/arm/boot/dts/armada-375-db.dts26
-rw-r--r--arch/arm/boot/dts/armada-375.dtsi34
-rw-r--r--arch/arm/boot/dts/armada-38x.dtsi5
-rw-r--r--arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts284
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78230.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78260.dtsi2
-rw-r--r--arch/arm/boot/dts/armada-xp-mv78460.dtsi4
-rw-r--r--arch/arm/boot/dts/armada-xp.dtsi2
-rw-r--r--arch/arm/boot/dts/at91-ariag25.dts8
-rw-r--r--arch/arm/boot/dts/at91-cosino.dtsi8
-rw-r--r--arch/arm/boot/dts/at91-foxg20.dts8
-rw-r--r--arch/arm/boot/dts/at91-qil_a9260.dts8
-rw-r--r--arch/arm/boot/dts/at91-sama5d3_xplained.dts12
-rw-r--r--arch/arm/boot/dts/at91rm9200.dtsi304
-rw-r--r--arch/arm/boot/dts/at91rm9200ek.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9260.dtsi314
-rw-r--r--arch/arm/boot/dts/at91sam9261.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9261ek.dts16
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi311
-rw-r--r--arch/arm/boot/dts/at91sam9263ek.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9g20.dtsi24
-rw-r--r--arch/arm/boot/dts/at91sam9g20ek_common.dtsi8
-rw-r--r--arch/arm/boot/dts/at91sam9g45.dtsi342
-rw-r--r--arch/arm/boot/dts/at91sam9m10g45ek.dts8
-rw-r--r--arch/arm/boot/dts/at91sam9n12.dtsi20
-rw-r--r--arch/arm/boot/dts/at91sam9n12ek.dts18
-rw-r--r--arch/arm/boot/dts/at91sam9rl.dtsi32
-rw-r--r--arch/arm/boot/dts/at91sam9rlek.dts17
-rw-r--r--arch/arm/boot/dts/at91sam9x5.dtsi30
-rw-r--r--arch/arm/boot/dts/at91sam9x5cm.dtsi12
-rw-r--r--arch/arm/boot/dts/bcm11351.dtsi19
-rw-r--r--arch/arm/boot/dts/bcm21664.dtsi19
-rw-r--r--arch/arm/boot/dts/bcm7445-bcm97445svmb.dts14
-rw-r--r--arch/arm/boot/dts/bcm7445.dtsi111
-rw-r--r--arch/arm/boot/dts/berlin2.dtsi6
-rw-r--r--arch/arm/boot/dts/berlin2q-marvell-dmp.dts8
-rw-r--r--arch/arm/boot/dts/berlin2q.dtsi80
-rw-r--r--arch/arm/boot/dts/cros-ec-keyboard.dtsi105
-rw-r--r--arch/arm/boot/dts/dove-cubox-es.dts12
-rw-r--r--arch/arm/boot/dts/dove-cubox.dts3
-rw-r--r--arch/arm/boot/dts/dove.dtsi14
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts8
-rw-r--r--arch/arm/boot/dts/dra7.dtsi265
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi39
-rw-r--r--arch/arm/boot/dts/ethernut5.dts10
-rw-r--r--arch/arm/boot/dts/evk-pro3.dts6
-rw-r--r--arch/arm/boot/dts/exynos3250.dtsi28
-rw-r--r--arch/arm/boot/dts/exynos4.dtsi30
-rw-r--r--arch/arm/boot/dts/exynos4210.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos4412-odroid-common.dtsi371
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidu3.dts61
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx.dts279
-rw-r--r--arch/arm/boot/dts/exynos4412-odroidx2.dts32
-rw-r--r--arch/arm/boot/dts/exynos4412.dtsi4
-rw-r--r--arch/arm/boot/dts/exynos4x12.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5250-cros-common.dtsi159
-rw-r--r--arch/arm/boot/dts/exynos5250-smdk5250.dts2
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts259
-rw-r--r--arch/arm/boot/dts/exynos5260.dtsi5
-rw-r--r--arch/arm/boot/dts/exynos5410.dtsi9
-rw-r--r--arch/arm/boot/dts/exynos5420-peach-pit.dts392
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi6
-rw-r--r--arch/arm/boot/dts/exynos5800-peach-pi.dts374
-rw-r--r--arch/arm/boot/dts/ge863-pro3.dtsi4
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts73
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts45
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts45
-rw-r--r--arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts1
-rw-r--r--arch/arm/boot/dts/imx25-pdk.dts8
-rw-r--r--arch/arm/boot/dts/imx25.dtsi8
-rw-r--r--arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi296
-rw-r--r--arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts273
-rw-r--r--arch/arm/boot/dts/imx27-pdk.dts2
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts2
-rw-r--r--arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi3
-rw-r--r--arch/arm/boot/dts/imx27.dtsi115
-rw-r--r--arch/arm/boot/dts/imx28-cfa10036.dts22
-rw-r--r--arch/arm/boot/dts/imx28-m28.dtsi87
-rw-r--r--arch/arm/boot/dts/imx28-m28evk.dts62
-rw-r--r--arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts1
-rw-r--r--arch/arm/boot/dts/imx35.dtsi8
-rw-r--r--arch/arm/boot/dts/imx50.dtsi8
-rw-r--r--arch/arm/boot/dts/imx51-babbage.dts2
-rw-r--r--arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts1
-rw-r--r--arch/arm/boot/dts/imx51.dtsi3
-rw-r--r--arch/arm/boot/dts/imx53-m53.dtsi140
-rw-r--r--arch/arm/boot/dts/imx53-m53evk.dts113
-rw-r--r--arch/arm/boot/dts/imx53-mba53.dts1
-rw-r--r--arch/arm/boot/dts/imx53-qsb-common.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-tx53.dtsi1
-rw-r--r--arch/arm/boot/dts/imx53-voipac-bsb.dts1
-rw-r--r--arch/arm/boot/dts/imx53.dtsi15
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_4.dts85
-rw-r--r--arch/arm/boot/dts/imx6dl-aristainetos_7.dts74
-rw-r--r--arch/arm/boot/dts/imx6dl-gw51xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-gw52xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-gw53xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-gw54xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl-rex-basic.dts30
-rw-r--r--arch/arm/boot/dts/imx6dl-riotboard.dts33
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts103
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-801x.dts177
-rw-r--r--arch/arm/boot/dts/imx6dl-tx6u-811x.dts150
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard-revb1.dts22
-rw-r--r--arch/arm/boot/dts/imx6dl-wandboard.dts2
-rw-r--r--arch/arm/boot/dts/imx6dl.dtsi17
-rw-r--r--arch/arm/boot/dts/imx6q-cubox-i.dts4
-rw-r--r--arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts54
-rw-r--r--arch/arm/boot/dts/imx6q-gw51xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-gw52xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-gw53xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-gw5400-a.dts5
-rw-r--r--arch/arm/boot/dts/imx6q-gw54xx.dts2
-rw-r--r--arch/arm/boot/dts/imx6q-rex-pro.dts34
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts103
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1010.dts177
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts136
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1020.dts210
-rw-r--r--arch/arm/boot/dts/imx6q-tx6q-1110.dts154
-rw-r--r--arch/arm/boot/dts/imx6q-udoo.dts32
-rw-r--r--arch/arm/boot/dts/imx6q-wandboard-revb1.dts26
-rw-r--r--arch/arm/boot/dts/imx6q-wandboard.dts2
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi35
-rw-r--r--arch/arm/boot/dts/imx6qdl-aristainetos.dtsi418
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw52xx.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw53xx.dtsi5
-rw-r--r--arch/arm/boot/dts/imx6qdl-gw54xx.dtsi6
-rw-r--r--arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-rex.dtsi357
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabrelite.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6qdl-sabresd.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-tx6.dtsi696
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi42
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi41
-rw-r--r--arch/arm/boot/dts/imx6qdl-wandboard.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi161
-rw-r--r--arch/arm/boot/dts/imx6sl-evk.dts17
-rw-r--r--arch/arm/boot/dts/imx6sl.dtsi12
-rw-r--r--arch/arm/boot/dts/imx6sx-pinfunc.h1544
-rw-r--r--arch/arm/boot/dts/imx6sx-sdb.dts479
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi1208
-rw-r--r--arch/arm/boot/dts/k2e-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/k2hk-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/k2hk-evm.dts12
-rw-r--r--arch/arm/boot/dts/k2l-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/keystone-clocks.dtsi2
-rw-r--r--arch/arm/boot/dts/keystone.dtsi11
-rw-r--r--arch/arm/boot/dts/kirkwood-d2net.dts42
-rw-r--r--arch/arm/boot/dts/kirkwood-net2big.dts60
-rw-r--r--arch/arm/boot/dts/kirkwood-net5big.dts111
-rw-r--r--arch/arm/boot/dts/kirkwood-netxbig.dtsi154
-rw-r--r--arch/arm/boot/dts/kizbox.dts4
-rw-r--r--arch/arm/boot/dts/mpa1600.dts8
-rw-r--r--arch/arm/boot/dts/omap2420.dtsi3
-rw-r--r--arch/arm/boot/dts/omap2430.dtsi3
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts68
-rw-r--r--arch/arm/boot/dts/pm9g45.dts8
-rw-r--r--arch/arm/boot/dts/r7s72100-genmai.dts10
-rw-r--r--arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts14
-rw-r--r--arch/arm/boot/dts/r8a73a4.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts28
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi63
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw-reference.dts14
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi42
-rw-r--r--arch/arm/boot/dts/r8a7779.dtsi14
-rw-r--r--arch/arm/boot/dts/r8a7790-lager.dts88
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi207
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts45
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts89
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi218
-rw-r--r--arch/arm/boot/dts/rk3066a-bqcurie2.dts214
-rw-r--r--arch/arm/boot/dts/rk3066a-clocks.dtsi299
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi519
-rw-r--r--arch/arm/boot/dts/rk3188-clocks.dtsi289
-rw-r--r--arch/arm/boot/dts/rk3188-radxarock.dts218
-rw-r--r--arch/arm/boot/dts/rk3188.dtsi446
-rw-r--r--arch/arm/boot/dts/rk3288-evb-act8846.dts134
-rw-r--r--arch/arm/boot/dts/rk3288-evb-rk808.dts18
-rw-r--r--arch/arm/boot/dts/rk3288-evb.dtsi96
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi595
-rw-r--r--arch/arm/boot/dts/rk3xxx.dtsi356
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi22
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi12
-rw-r--r--arch/arm/boot/dts/sama5d3xmb.dtsi2
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts16
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi72
-rw-r--r--arch/arm/boot/dts/socfpga.dtsi1
-rw-r--r--arch/arm/boot/dts/ste-dbx5x0.dtsi10
-rw-r--r--arch/arm/boot/dts/ste-href-stuib.dtsi2
-rw-r--r--arch/arm/boot/dts/ste-href-tvk1281618.dtsi59
-rw-r--r--arch/arm/boot/dts/ste-hrefv60plus.dtsi24
-rw-r--r--arch/arm/boot/dts/ste-snowball.dts38
-rw-r--r--arch/arm/boot/dts/sun4i-a10-a1000.dts15
-rw-r--r--arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts110
-rw-r--r--arch/arm/boot/dts/sun4i-a10-cubieboard.dts15
-rw-r--r--arch/arm/boot/dts/sun4i-a10-hackberry.dts21
-rw-r--r--arch/arm/boot/dts/sun4i-a10-inet97fv2.dts21
-rw-r--r--arch/arm/boot/dts/sun4i-a10-mini-xplus.dts28
-rw-r--r--arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts15
-rw-r--r--arch/arm/boot/dts/sun4i-a10-pcduino.dts9
-rw-r--r--arch/arm/boot/dts/sun4i-a10.dtsi34
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a13.dtsi2
-rw-r--r--arch/arm/boot/dts/sun6i-a31-hummingbird.dts119
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi92
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts16
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubietruck.dts16
-rw-r--r--arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts22
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts10
-rw-r--r--arch/arm/boot/dts/sun7i-a20-pcduino3.dts173
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi34
-rw-r--r--arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts30
-rw-r--r--arch/arm/boot/dts/sun8i-a23.dtsi343
-rw-r--r--arch/arm/boot/dts/tegra114-roth.dts32
-rw-r--r--arch/arm/boot/dts/tegra124-jetson-tk1.dts33
-rw-r--r--arch/arm/boot/dts/tegra124-venice2.dts128
-rw-r--r--arch/arm/boot/dts/tegra124.dtsi40
-rw-r--r--arch/arm/boot/dts/tegra20-medcom-wide.dts61
-rw-r--r--arch/arm/boot/dts/tegra20-paz00.dts6
-rw-r--r--arch/arm/boot/dts/tegra20-plutux.dts41
-rw-r--r--arch/arm/boot/dts/tegra20-tamonten.dtsi10
-rw-r--r--arch/arm/boot/dts/tegra20-tec.dts41
-rw-r--r--arch/arm/boot/dts/tegra30-apalis-eval.dts260
-rw-r--r--arch/arm/boot/dts/tegra30-apalis.dtsi678
-rw-r--r--arch/arm/boot/dts/tny_a9260_common.dtsi8
-rw-r--r--arch/arm/boot/dts/tny_a9263.dts8
-rw-r--r--arch/arm/boot/dts/usb_a9260_common.dtsi8
-rw-r--r--arch/arm/boot/dts/usb_a9263.dts8
-rw-r--r--arch/arm/boot/dts/vf610.dtsi25
-rw-r--r--arch/arm/boot/dts/zynq-7000.dtsi90
-rw-r--r--arch/arm/boot/dts/zynq-parallella.dts64
-rw-r--r--arch/arm/boot/dts/zynq-zc702.dts4
-rw-r--r--arch/arm/configs/omap2plus_defconfig2
-rw-r--r--arch/arm/mach-at91/Kconfig4
-rw-r--r--arch/arm/mach-at91/at91rm9200.c6
-rw-r--r--arch/arm/mach-at91/at91sam9260.c6
-rw-r--r--arch/arm/mach-at91/at91sam9263.c6
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c6
-rw-r--r--arch/arm/mach-exynos/exynos.c2
-rw-r--r--arch/arm/mach-omap2/Makefile6
-rw-r--r--arch/arm/mach-omap2/cclock2420_data.c1931
-rw-r--r--arch/arm/mach-omap2/cclock2430_data.c2048
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_osc.c69
-rw-r--r--arch/arm/mach-omap2/clkt2xxx_sys.c47
-rw-r--r--arch/arm/mach-omap2/clock.c21
-rw-r--r--arch/arm/mach-omap2/clock.h3
-rw-r--r--arch/arm/mach-omap2/clock2xxx.h2
-rw-r--r--arch/arm/mach-omap2/cm-regbits-24xx.h1
-rw-r--r--arch/arm/mach-omap2/io.c7
-rw-r--r--arch/arm/mach-omap2/pm24xx.c4
-rw-r--r--arch/arm/mach-omap2/prm_common.c2
-rw-r--r--arch/arm/mach-rockchip/Kconfig1
-rw-r--r--arch/arm/mach-rockchip/rockchip.c1
-rw-r--r--arch/arm/mach-shmobile/clock-r8a73a4.c1
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7740.c3
-rw-r--r--arch/arm/mach-shmobile/clock-r8a7778.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh73a0.c1
-rw-r--r--arch/arm/mach-shmobile/setup-r8a73a4.c12
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7740.c8
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c12
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c8
273 files changed, 19154 insertions, 6820 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e60718b4b96d..916cedbd7a67 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1489,6 +1489,7 @@ config ARCH_NR_GPIO
1489 default 416 if ARCH_SUNXI 1489 default 416 if ARCH_SUNXI
1490 default 392 if ARCH_U8500 1490 default 392 if ARCH_U8500
1491 default 352 if ARCH_VT8500 1491 default 352 if ARCH_VT8500
1492 default 288 if ARCH_ROCKCHIP
1492 default 264 if MACH_H4700 1493 default 264 if MACH_H4700
1493 default 0 1494 default 0
1494 help 1495 help
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index edaf62737bc2..b11ad54f8d17 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -590,7 +590,7 @@ choice
590 on Rockchip based platforms. 590 on Rockchip based platforms.
591 591
592 config DEBUG_RK3X_UART0 592 config DEBUG_RK3X_UART0
593 bool "Kernel low-level debugging messages via Rockchip RK3X UART0" 593 bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART0"
594 depends on ARCH_ROCKCHIP 594 depends on ARCH_ROCKCHIP
595 select DEBUG_UART_8250 595 select DEBUG_UART_8250
596 help 596 help
@@ -598,7 +598,7 @@ choice
598 on Rockchip based platforms. 598 on Rockchip based platforms.
599 599
600 config DEBUG_RK3X_UART1 600 config DEBUG_RK3X_UART1
601 bool "Kernel low-level debugging messages via Rockchip RK3X UART1" 601 bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART1"
602 depends on ARCH_ROCKCHIP 602 depends on ARCH_ROCKCHIP
603 select DEBUG_UART_8250 603 select DEBUG_UART_8250
604 help 604 help
@@ -606,7 +606,7 @@ choice
606 on Rockchip based platforms. 606 on Rockchip based platforms.
607 607
608 config DEBUG_RK3X_UART2 608 config DEBUG_RK3X_UART2
609 bool "Kernel low-level debugging messages via Rockchip RK3X UART2" 609 bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART2"
610 depends on ARCH_ROCKCHIP 610 depends on ARCH_ROCKCHIP
611 select DEBUG_UART_8250 611 select DEBUG_UART_8250
612 help 612 help
@@ -614,13 +614,21 @@ choice
614 on Rockchip based platforms. 614 on Rockchip based platforms.
615 615
616 config DEBUG_RK3X_UART3 616 config DEBUG_RK3X_UART3
617 bool "Kernel low-level debugging messages via Rockchip RK3X UART3" 617 bool "Kernel low-level debugging messages via Rockchip RK30/RK31 UART3"
618 depends on ARCH_ROCKCHIP 618 depends on ARCH_ROCKCHIP
619 select DEBUG_UART_8250 619 select DEBUG_UART_8250
620 help 620 help
621 Say Y here if you want kernel low-level debugging support 621 Say Y here if you want kernel low-level debugging support
622 on Rockchip based platforms. 622 on Rockchip based platforms.
623 623
624 config DEBUG_RK32_UART2
625 bool "Kernel low-level debugging messages via Rockchip RK32 UART2"
626 depends on ARCH_ROCKCHIP
627 select DEBUG_UART_8250
628 help
629 Say Y here if you want kernel low-level debugging support
630 on Rockchip RK32xx based platforms.
631
624 config DEBUG_S3C_UART0 632 config DEBUG_S3C_UART0
625 depends on PLAT_SAMSUNG 633 depends on PLAT_SAMSUNG
626 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 634 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -1110,6 +1118,7 @@ config DEBUG_UART_PHYS
1110 default 0xf991e000 if DEBUG_QCOM_UARTDM 1118 default 0xf991e000 if DEBUG_QCOM_UARTDM
1111 default 0xfcb00000 if DEBUG_HI3620_UART 1119 default 0xfcb00000 if DEBUG_HI3620_UART
1112 default 0xfe800000 if ARCH_IOP32X 1120 default 0xfe800000 if ARCH_IOP32X
1121 default 0xff690000 if DEBUG_RK32_UART2
1113 default 0xffc02000 if DEBUG_SOCFPGA_UART 1122 default 0xffc02000 if DEBUG_SOCFPGA_UART
1114 default 0xffd82340 if ARCH_IOP13XX 1123 default 0xffd82340 if ARCH_IOP13XX
1115 default 0xfff36000 if DEBUG_HIGHBANK_UART 1124 default 0xfff36000 if DEBUG_HIGHBANK_UART
@@ -1167,6 +1176,7 @@ config DEBUG_UART_VIRT
1167 default 0xfec02000 if DEBUG_SOCFPGA_UART 1176 default 0xfec02000 if DEBUG_SOCFPGA_UART
1168 default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE 1177 default 0xfec12000 if DEBUG_MVEBU_UART || DEBUG_MVEBU_UART_ALTERNATE
1169 default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 1178 default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0
1179 default 0xfec90000 if DEBUG_RK32_UART2
1170 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 1180 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1
1171 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 1181 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2
1172 default 0xfed60000 if DEBUG_RK29_UART0 1182 default 0xfed60000 if DEBUG_RK29_UART0
@@ -1200,7 +1210,7 @@ config DEBUG_UART_8250_WORD
1200 ARCH_KEYSTONE || \ 1210 ARCH_KEYSTONE || \
1201 DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ 1211 DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \
1202 DEBUG_DAVINCI_DA8XX_UART2 || \ 1212 DEBUG_DAVINCI_DA8XX_UART2 || \
1203 DEBUG_BCM_KONA_UART 1213 DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2
1204 1214
1205config DEBUG_UART_8250_FLOW_CONTROL 1215config DEBUG_UART_8250_FLOW_CONTROL
1206 bool "Enable flow control for 8250 UART" 1216 bool "Enable flow control for 8250 UART"
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 74f2906211a9..b8c5cd3ddeb9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -59,6 +59,8 @@ dtb-$(CONFIG_ARCH_BERLIN) += \
59 berlin2-sony-nsz-gs7.dtb \ 59 berlin2-sony-nsz-gs7.dtb \
60 berlin2cd-google-chromecast.dtb \ 60 berlin2cd-google-chromecast.dtb \
61 berlin2q-marvell-dmp.dtb 61 berlin2q-marvell-dmp.dtb
62dtb-$(CONFIG_ARCH_BRCMSTB) += \
63 bcm7445-bcm97445svmb.dtb
62dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \ 64dtb-$(CONFIG_ARCH_DAVINCI) += da850-enbw-cmc.dtb \
63 da850-evm.dtb 65 da850-evm.dtb
64dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb 66dtb-$(CONFIG_ARCH_EFM32) += efm32gg-dk3750.dtb
@@ -66,7 +68,9 @@ dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
66 exynos4210-smdkv310.dtb \ 68 exynos4210-smdkv310.dtb \
67 exynos4210-trats.dtb \ 69 exynos4210-trats.dtb \
68 exynos4210-universal_c210.dtb \ 70 exynos4210-universal_c210.dtb \
71 exynos4412-odroidu3.dtb \
69 exynos4412-odroidx.dtb \ 72 exynos4412-odroidx.dtb \
73 exynos4412-odroidx2.dtb \
70 exynos4412-origen.dtb \ 74 exynos4412-origen.dtb \
71 exynos4412-smdk4412.dtb \ 75 exynos4412-smdk4412.dtb \
72 exynos4412-tiny4412.dtb \ 76 exynos4412-tiny4412.dtb \
@@ -93,6 +97,7 @@ dtb-$(CONFIG_ARCH_KEYSTONE) += k2hk-evm.dtb \
93 k2e-evm.dtb 97 k2e-evm.dtb
94dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \ 98dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
95 kirkwood-cloudbox.dtb \ 99 kirkwood-cloudbox.dtb \
100 kirkwood-d2net.dtb \
96 kirkwood-db-88f6281.dtb \ 101 kirkwood-db-88f6281.dtb \
97 kirkwood-db-88f6282.dtb \ 102 kirkwood-db-88f6282.dtb \
98 kirkwood-dns320.dtb \ 103 kirkwood-dns320.dtb \
@@ -123,6 +128,8 @@ dtb-$(CONFIG_MACH_KIRKWOOD) += kirkwood-b3.dtb \
123 kirkwood-lsxhl.dtb \ 128 kirkwood-lsxhl.dtb \
124 kirkwood-mplcec4.dtb \ 129 kirkwood-mplcec4.dtb \
125 kirkwood-mv88f6281gtw-ge.dtb \ 130 kirkwood-mv88f6281gtw-ge.dtb \
131 kirkwood-net2big.dtb \
132 kirkwood-net5big.dtb \
126 kirkwood-netgear_readynas_duo_v2.dtb \ 133 kirkwood-netgear_readynas_duo_v2.dtb \
127 kirkwood-netgear_readynas_nv+_v2.dtb \ 134 kirkwood-netgear_readynas_nv+_v2.dtb \
128 kirkwood-ns2.dtb \ 135 kirkwood-ns2.dtb \
@@ -155,10 +162,14 @@ dtb-$(CONFIG_ARCH_MARCO) += marco-evb.dtb
155dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb 162dtb-$(CONFIG_ARCH_MOXART) += moxart-uc7112lx.dtb
156dtb-$(CONFIG_ARCH_MXC) += \ 163dtb-$(CONFIG_ARCH_MXC) += \
157 imx25-eukrea-mbimxsd25-baseboard.dtb \ 164 imx25-eukrea-mbimxsd25-baseboard.dtb \
165 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dtb \
166 imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dtb \
167 imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dtb \
158 imx25-karo-tx25.dtb \ 168 imx25-karo-tx25.dtb \
159 imx25-pdk.dtb \ 169 imx25-pdk.dtb \
160 imx27-apf27.dtb \ 170 imx27-apf27.dtb \
161 imx27-apf27dev.dtb \ 171 imx27-apf27dev.dtb \
172 imx27-eukrea-mbimxsd27-baseboard.dtb \
162 imx27-pdk.dtb \ 173 imx27-pdk.dtb \
163 imx27-phytec-phycore-rdk.dtb \ 174 imx27-phytec-phycore-rdk.dtb \
164 imx27-phytec-phycard-s-rdk.dtb \ 175 imx27-phytec-phycard-s-rdk.dtb \
@@ -180,6 +191,8 @@ dtb-$(CONFIG_ARCH_MXC) += \
180 imx53-tx53-x03x.dtb \ 191 imx53-tx53-x03x.dtb \
181 imx53-tx53-x13x.dtb \ 192 imx53-tx53-x13x.dtb \
182 imx53-voipac-bsb.dtb \ 193 imx53-voipac-bsb.dtb \
194 imx6dl-aristainetos_4.dtb \
195 imx6dl-aristainetos_7.dtb \
183 imx6dl-cubox-i.dtb \ 196 imx6dl-cubox-i.dtb \
184 imx6dl-dfi-fs700-m60.dtb \ 197 imx6dl-dfi-fs700-m60.dtb \
185 imx6dl-gw51xx.dtb \ 198 imx6dl-gw51xx.dtb \
@@ -189,11 +202,16 @@ dtb-$(CONFIG_ARCH_MXC) += \
189 imx6dl-hummingboard.dtb \ 202 imx6dl-hummingboard.dtb \
190 imx6dl-nitrogen6x.dtb \ 203 imx6dl-nitrogen6x.dtb \
191 imx6dl-phytec-pbab01.dtb \ 204 imx6dl-phytec-pbab01.dtb \
205 imx6dl-rex-basic.dtb \
192 imx6dl-riotboard.dtb \ 206 imx6dl-riotboard.dtb \
193 imx6dl-sabreauto.dtb \ 207 imx6dl-sabreauto.dtb \
194 imx6dl-sabrelite.dtb \ 208 imx6dl-sabrelite.dtb \
195 imx6dl-sabresd.dtb \ 209 imx6dl-sabresd.dtb \
210 imx6dl-tx6dl-comtft.dtb \
211 imx6dl-tx6u-801x.dtb \
212 imx6dl-tx6u-811x.dtb \
196 imx6dl-wandboard.dtb \ 213 imx6dl-wandboard.dtb \
214 imx6dl-wandboard-revb1.dtb \
197 imx6q-arm2.dtb \ 215 imx6q-arm2.dtb \
198 imx6q-cm-fx6.dtb \ 216 imx6q-cm-fx6.dtb \
199 imx6q-cubox-i.dtb \ 217 imx6q-cubox-i.dtb \
@@ -207,13 +225,21 @@ dtb-$(CONFIG_ARCH_MXC) += \
207 imx6q-gw54xx.dtb \ 225 imx6q-gw54xx.dtb \
208 imx6q-nitrogen6x.dtb \ 226 imx6q-nitrogen6x.dtb \
209 imx6q-phytec-pbab01.dtb \ 227 imx6q-phytec-pbab01.dtb \
228 imx6q-rex-pro.dtb \
210 imx6q-sabreauto.dtb \ 229 imx6q-sabreauto.dtb \
211 imx6q-sabrelite.dtb \ 230 imx6q-sabrelite.dtb \
212 imx6q-sabresd.dtb \ 231 imx6q-sabresd.dtb \
213 imx6q-sbc6x.dtb \ 232 imx6q-sbc6x.dtb \
214 imx6q-udoo.dtb \ 233 imx6q-udoo.dtb \
215 imx6q-wandboard.dtb \ 234 imx6q-wandboard.dtb \
235 imx6q-wandboard-revb1.dtb \
236 imx6q-tx6q-1010.dtb \
237 imx6q-tx6q-1010-comtft.dtb \
238 imx6q-tx6q-1020.dtb \
239 imx6q-tx6q-1020-comtft.dtb \
240 imx6q-tx6q-1110.dtb \
216 imx6sl-evk.dtb \ 241 imx6sl-evk.dtb \
242 imx6sx-sdb.dtb \
217 vf610-colibri.dtb \ 243 vf610-colibri.dtb \
218 vf610-cosmic.dtb \ 244 vf610-cosmic.dtb \
219 vf610-twr.dtb 245 vf610-twr.dtb
@@ -289,7 +315,8 @@ dtb-$(CONFIG_SOC_AM33XX) += am335x-base0033.dtb \
289 am335x-boneblack.dtb \ 315 am335x-boneblack.dtb \
290 am335x-evm.dtb \ 316 am335x-evm.dtb \
291 am335x-evmsk.dtb \ 317 am335x-evmsk.dtb \
292 am335x-nano.dtb 318 am335x-nano.dtb \
319 am335x-pepper.dtb
293dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \ 320dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
294 omap4-panda.dtb \ 321 omap4-panda.dtb \
295 omap4-panda-a4.dtb \ 322 omap4-panda-a4.dtb \
@@ -299,6 +326,7 @@ dtb-$(CONFIG_ARCH_OMAP4) += omap4-duovero-parlor.dtb \
299 omap4-var-dvk-om44.dtb \ 326 omap4-var-dvk-om44.dtb \
300 omap4-var-stk-om44.dtb 327 omap4-var-stk-om44.dtb
301dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \ 328dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
329 am437x-sk-evm.dtb \
302 am437x-gp-evm.dtb 330 am437x-gp-evm.dtb
303dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \ 331dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
304 omap5-sbc-t54.dtb \ 332 omap5-sbc-t54.dtb \
@@ -316,6 +344,11 @@ dtb-$(CONFIG_ARCH_QCOM) += \
316 qcom-apq8084-mtp.dtb \ 344 qcom-apq8084-mtp.dtb \
317 qcom-msm8660-surf.dtb \ 345 qcom-msm8660-surf.dtb \
318 qcom-msm8960-cdp.dtb 346 qcom-msm8960-cdp.dtb
347dtb-$(CONFIG_ARCH_ROCKCHIP) += \
348 rk3066a-bqcurie2.dtb \
349 rk3188-radxarock.dtb \
350 rk3288-evb-act8846.dtb \
351 rk3288-evb-rk808.dtb
319dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb 352dtb-$(CONFIG_ARCH_S3C24XX) += s3c2416-smdk2416.dtb
320dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \ 353dtb-$(CONFIG_ARCH_S3C64XX) += s3c6410-mini6410.dtb \
321 s3c6410-smdk6410.dtb 354 s3c6410-smdk6410.dtb
@@ -363,6 +396,7 @@ dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
363 stih416-b2020e.dtb 396 stih416-b2020e.dtb
364dtb-$(CONFIG_MACH_SUN4I) += \ 397dtb-$(CONFIG_MACH_SUN4I) += \
365 sun4i-a10-a1000.dtb \ 398 sun4i-a10-a1000.dtb \
399 sun4i-a10-ba10-tvbox.dtb \
366 sun4i-a10-cubieboard.dtb \ 400 sun4i-a10-cubieboard.dtb \
367 sun4i-a10-mini-xplus.dtb \ 401 sun4i-a10-mini-xplus.dtb \
368 sun4i-a10-hackberry.dtb \ 402 sun4i-a10-hackberry.dtb \
@@ -377,12 +411,16 @@ dtb-$(CONFIG_MACH_SUN5I) += \
377dtb-$(CONFIG_MACH_SUN6I) += \ 411dtb-$(CONFIG_MACH_SUN6I) += \
378 sun6i-a31-app4-evb1.dtb \ 412 sun6i-a31-app4-evb1.dtb \
379 sun6i-a31-colombus.dtb \ 413 sun6i-a31-colombus.dtb \
414 sun6i-a31-hummingbird.dtb \
380 sun6i-a31-m9.dtb 415 sun6i-a31-m9.dtb
381dtb-$(CONFIG_MACH_SUN7I) += \ 416dtb-$(CONFIG_MACH_SUN7I) += \
382 sun7i-a20-cubieboard2.dtb \ 417 sun7i-a20-cubieboard2.dtb \
383 sun7i-a20-cubietruck.dtb \ 418 sun7i-a20-cubietruck.dtb \
384 sun7i-a20-i12-tvbox.dtb \ 419 sun7i-a20-i12-tvbox.dtb \
385 sun7i-a20-olinuxino-micro.dtb 420 sun7i-a20-olinuxino-micro.dtb \
421 sun7i-a20-pcduino3.dtb
422dtb-$(CONFIG_MACH_SUN8I) += \
423 sun8i-a23-ippo-q8h-v5.dtb
386dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 424dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
387 tegra20-iris-512.dtb \ 425 tegra20-iris-512.dtb \
388 tegra20-medcom-wide.dtb \ 426 tegra20-medcom-wide.dtb \
@@ -393,6 +431,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
393 tegra20-trimslice.dtb \ 431 tegra20-trimslice.dtb \
394 tegra20-ventana.dtb \ 432 tegra20-ventana.dtb \
395 tegra20-whistler.dtb \ 433 tegra20-whistler.dtb \
434 tegra30-apalis-eval.dtb \
396 tegra30-beaver.dtb \ 435 tegra30-beaver.dtb \
397 tegra30-cardhu-a02.dtb \ 436 tegra30-cardhu-a02.dtb \
398 tegra30-cardhu-a04.dtb \ 437 tegra30-cardhu-a04.dtb \
@@ -422,7 +461,9 @@ dtb-$(CONFIG_ARCH_VT8500) += vt8500-bv07.dtb \
422 wm8650-mid.dtb \ 461 wm8650-mid.dtb \
423 wm8750-apc8750.dtb \ 462 wm8750-apc8750.dtb \
424 wm8850-w70v2.dtb 463 wm8850-w70v2.dtb
425dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ 464dtb-$(CONFIG_ARCH_ZYNQ) += \
465 zynq-parallella.dtb \
466 zynq-zc702.dtb \
426 zynq-zc706.dtb \ 467 zynq-zc706.dtb \
427 zynq-zed.dtb 468 zynq-zed.dtb
428dtb-$(CONFIG_MACH_ARMADA_370) += \ 469dtb-$(CONFIG_MACH_ARMADA_370) += \
@@ -440,11 +481,13 @@ dtb-$(CONFIG_MACH_ARMADA_XP) += \
440 armada-xp-axpwifiap.dtb \ 481 armada-xp-axpwifiap.dtb \
441 armada-xp-db.dtb \ 482 armada-xp-db.dtb \
442 armada-xp-gp.dtb \ 483 armada-xp-gp.dtb \
443 armada-xp-netgear-rn2120.dtb \ 484 armada-xp-lenovo-ix4-300d.dtb \
444 armada-xp-matrix.dtb \ 485 armada-xp-matrix.dtb \
486 armada-xp-netgear-rn2120.dtb \
445 armada-xp-openblocks-ax3-4.dtb 487 armada-xp-openblocks-ax3-4.dtb
446dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \ 488dtb-$(CONFIG_MACH_DOVE) += dove-cm-a510.dtb \
447 dove-cubox.dtb \ 489 dove-cubox.dtb \
490 dove-cubox-es.dtb \
448 dove-d2plug.dtb \ 491 dove-d2plug.dtb \
449 dove-d3plug.dtb \ 492 dove-d3plug.dtb \
450 dove-dove-db.dtb 493 dove-dove-db.dtb
diff --git a/arch/arm/boot/dts/aks-cdu.dts b/arch/arm/boot/dts/aks-cdu.dts
index 54cb5cf8604a..d9c50fbb49d2 100644
--- a/arch/arm/boot/dts/aks-cdu.dts
+++ b/arch/arm/boot/dts/aks-cdu.dts
@@ -16,6 +16,12 @@
16 bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs"; 16 bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
17 }; 17 };
18 18
19 clocks {
20 slow_xtal {
21 clock-frequency = <32768>;
22 };
23 };
24
19 ahb { 25 ahb {
20 apb { 26 apb {
21 usart0: serial@fffb0000 { 27 usart0: serial@fffb0000 {
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 80a3b215e7d6..df5fee6b6b4b 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -149,12 +149,113 @@
149 "Headphone Jack", "HPLOUT", 149 "Headphone Jack", "HPLOUT",
150 "Headphone Jack", "HPROUT"; 150 "Headphone Jack", "HPROUT";
151 }; 151 };
152
153 panel {
154 compatible = "ti,tilcdc,panel";
155 pinctrl-names = "default", "sleep";
156 pinctrl-0 = <&lcd_pins_default>;
157 pinctrl-1 = <&lcd_pins_sleep>;
158 status = "okay";
159 panel-info {
160 ac-bias = <255>;
161 ac-bias-intrpt = <0>;
162 dma-burst-sz = <16>;
163 bpp = <32>;
164 fdd = <0x80>;
165 sync-edge = <0>;
166 sync-ctrl = <1>;
167 raster-order = <0>;
168 fifo-th = <0>;
169 };
170 display-timings {
171 480x272 {
172 hactive = <480>;
173 vactive = <272>;
174 hback-porch = <43>;
175 hfront-porch = <8>;
176 hsync-len = <4>;
177 vback-porch = <12>;
178 vfront-porch = <4>;
179 vsync-len = <10>;
180 clock-frequency = <9000000>;
181 hsync-active = <0>;
182 vsync-active = <0>;
183 };
184 };
185 };
152}; 186};
153 187
154&am33xx_pinmux { 188&am33xx_pinmux {
155 pinctrl-names = "default"; 189 pinctrl-names = "default";
156 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>; 190 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
157 191
192 lcd_pins_default: lcd_pins_default {
193 pinctrl-single,pins = <
194 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
195 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
196 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
197 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
198 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
199 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
200 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
201 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
202 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
203 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
204 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
205 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
206 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
207 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
208 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
209 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
210 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
211 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
212 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
213 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
214 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
215 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
216 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
217 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
218 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
219 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
220 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
221 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
222 >;
223 };
224
225 lcd_pins_sleep: lcd_pins_sleep {
226 pinctrl-single,pins = <
227 0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
228 0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
229 0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
230 0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
231 0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
232 0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
233 0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
234 0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
235 0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
236 0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
237 0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
238 0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
239 0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
240 0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
241 0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
242 0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
243 0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
244 0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
245 0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
246 0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
247 0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
248 0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
249 0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
250 0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
251 0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
252 0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
253 0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
254 0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
255 >;
256 };
257
258
158 user_leds_s0: user_leds_s0 { 259 user_leds_s0: user_leds_s0 {
159 pinctrl-single,pins = < 260 pinctrl-single,pins = <
160 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */ 261 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
@@ -573,3 +674,7 @@
573 ti,wire-config = <0x00 0x11 0x22 0x33>; 674 ti,wire-config = <0x00 0x11 0x22 0x33>;
574 }; 675 };
575}; 676};
677
678&lcdc {
679 status = "okay";
680};
diff --git a/arch/arm/boot/dts/am335x-pepper.dts b/arch/arm/boot/dts/am335x-pepper.dts
new file mode 100644
index 000000000000..0d35ab64641c
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-pepper.dts
@@ -0,0 +1,653 @@
1/*
2 * Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include <dt-bindings/input/input.h>
11#include "am33xx.dtsi"
12
13/ {
14 model = "Gumstix Pepper";
15 compatible = "gumstix,am335x-pepper", "ti,am33xx";
16
17 cpus {
18 cpu@0 {
19 cpu0-supply = <&dcdc3_reg>;
20 };
21 };
22
23 memory {
24 device_type = "memory";
25 reg = <0x80000000 0x20000000>; /* 512 MB */
26 };
27
28 buttons: user_buttons {
29 compatible = "gpio-keys";
30 };
31
32 leds: user_leds {
33 compatible = "gpio-leds";
34 };
35
36 panel: lcd_panel {
37 compatible = "ti,tilcdc,panel";
38 };
39
40 sound: sound_iface {
41 compatible = "ti,da830-evm-audio";
42 };
43
44 vbat: fixedregulator@0 {
45 compatible = "regulator-fixed";
46 };
47
48 v3v3c_reg: fixedregulator@1 {
49 compatible = "regulator-fixed";
50 };
51
52 vdd5_reg: fixedregulator@2 {
53 compatible = "regulator-fixed";
54 };
55};
56
57/* I2C Busses */
58&i2c0 {
59 status = "okay";
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins>;
62
63 clock-frequency = <400000>;
64
65 tps: tps@24 {
66 reg = <0x24>;
67 };
68
69 eeprom: eeprom@50 {
70 compatible = "at,24c256";
71 reg = <0x50>;
72 };
73
74 audio_codec: tlv320aic3106@1b {
75 compatible = "ti,tlv320aic3106";
76 reg = <0x1b>;
77 };
78
79 accel: lis331dlh@1d {
80 compatible = "st,lis3lv02d";
81 reg = <0x1d>;
82 };
83};
84
85&i2c1 {
86 status = "okay";
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c1_pins>;
89 clock-frequency = <400000>;
90};
91
92&am33xx_pinmux {
93 i2c0_pins: pinmux_i2c0 {
94 pinctrl-single,pins = <
95 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
96 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
97 >;
98 };
99 i2c1_pins: pinmux_i2c1 {
100 pinctrl-single,pins = <
101 0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
102 0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
103 >;
104 };
105};
106
107/* Accelerometer */
108&accel {
109 pinctrl-names = "default";
110 pinctrl-0 = <&accel_pins>;
111
112 Vdd-supply = <&ldo3_reg>;
113 Vdd_IO-supply = <&ldo3_reg>;
114 st,irq1-click;
115 st,wakeup-x-lo;
116 st,wakeup-x-hi;
117 st,wakeup-y-lo;
118 st,wakeup-y-hi;
119 st,wakeup-z-lo;
120 st,wakeup-z-hi;
121 st,min-limit-x = <92>;
122 st,max-limit-x = <14>;
123 st,min-limit-y = <14>;
124 st,max-limit-y = <92>;
125 st,min-limit-z = <92>;
126 st,max-limit-z = <14>;
127};
128
129&am33xx_pinmux {
130 accel_pins: pinmux_accel {
131 pinctrl-single,pins = <
132 0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
133 >;
134 };
135};
136
137/* Audio */
138&audio_codec {
139 status = "okay";
140
141 gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
142 AVDD-supply = <&ldo3_reg>;
143 IOVDD-supply = <&ldo3_reg>;
144 DRVDD-supply = <&ldo3_reg>;
145 DVDD-supply = <&dcdc1_reg>;
146};
147
148&sound {
149 ti,model = "AM335x-EVM";
150 ti,audio-codec = <&audio_codec>;
151 ti,mcasp-controller = <&mcasp0>;
152 ti,codec-clock-rate = <12000000>;
153 ti,audio-routing =
154 "Headphone Jack", "HPLOUT",
155 "Headphone Jack", "HPROUT",
156 "LINE1L", "Line In";
157};
158
159&mcasp0 {
160 status = "okay";
161 pinctrl-names = "default";
162 pinctrl-0 = <&audio_pins>;
163
164 op-mode = <0>; /* MCASP_ISS_MODE */
165 tdm-slots = <2>;
166 serial-dir = <
167 1 2 0 0
168 0 0 0 0
169 0 0 0 0
170 0 0 0 0
171 >;
172 tx-num-evt = <1>;
173 rx-num-evt = <1>;
174};
175
176&am33xx_pinmux {
177 audio_pins: pinmux_audio {
178 pinctrl-single,pins = <
179 0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
180 0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
181 0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
182 0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
183 0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
184 0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
185 >;
186 };
187};
188
189/* Display: 24-bit LCD Screen */
190&panel {
191 status = "okay";
192 pinctrl-names = "default";
193 pinctrl-0 = <&lcd_pins>;
194 panel-info {
195 ac-bias = <255>;
196 ac-bias-intrpt = <0>;
197 dma-burst-sz = <16>;
198 bpp = <32>;
199 fdd = <0x80>;
200 sync-edge = <0>;
201 sync-ctrl = <1>;
202 raster-order = <0>;
203 fifo-th = <0>;
204 };
205 display-timings {
206 native-mode = <&timing0>;
207 timing0: 480x272 {
208 clock-frequency = <18400000>;
209 hactive = <480>;
210 vactive = <272>;
211 hfront-porch = <8>;
212 hback-porch = <4>;
213 hsync-len = <41>;
214 vfront-porch = <4>;
215 vback-porch = <2>;
216 vsync-len = <10>;
217 hsync-active = <1>;
218 vsync-active = <1>;
219 };
220 };
221};
222
223&lcdc {
224 status = "okay";
225};
226
227&am33xx_pinmux {
228 lcd_pins: pinmux_lcd {
229 pinctrl-single,pins = <
230 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
231 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
232 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
233 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
234 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
235 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
236 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
237 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
238 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
239 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
240 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
241 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
242 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
243 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
244 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
245 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
246 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
247 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
248 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
249 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
250 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
251 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
252 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
253 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
254 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
255 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
256 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
257 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
258 /* Display Enable */
259 0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
260 >;
261 };
262};
263
264/* Ethernet */
265&cpsw_emac0 {
266 status = "okay";
267 phy_id = <&davinci_mdio>, <0>;
268 phy-mode = "rgmii";
269};
270
271&cpsw_emac1 {
272 status = "okay";
273 phy_id = <&davinci_mdio>, <1>;
274 phy-mode = "rgmii";
275};
276
277&davinci_mdio {
278 status = "okay";
279 pinctrl-names = "default";
280 pinctrl-0 = <&mdio_pins>;
281};
282
283&mac {
284 status = "okay";
285 pinctrl-names = "default";
286 pinctrl-0 = <&ethernet_pins>;
287};
288
289
290&am33xx_pinmux {
291 ethernet_pins: pinmux_ethernet {
292 pinctrl-single,pins = <
293 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
294 0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
295 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
296 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
297 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
298 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
299 0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
300 0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
301 0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
302 0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
303 0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
304 0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
305 /* ethernet interrupt */
306 0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
307 /* ethernet PHY nReset */
308 0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
309 >;
310 };
311
312 mdio_pins: pinmux_mdio {
313 pinctrl-single,pins = <
314 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
315 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
316 >;
317 };
318};
319
320/* MMC */
321&mmc1 {
322 /* Bootable SD card slot */
323 status = "okay";
324 vmmc-supply = <&ldo3_reg>;
325 bus-width = <4>;
326 pinctrl-names = "default";
327 pinctrl-0 = <&sd_pins>;
328 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
329};
330
331&mmc2 {
332 /* eMMC (not populated) on MMC #2 */
333 status = "disabled";
334 pinctrl-names = "default";
335 pinctrl-0 = <&emmc_pins>;
336 vmmc-supply = <&ldo3_reg>;
337 bus-width = <8>;
338 ti,non-removable;
339};
340
341&edma {
342 /* Map eDMA MMC2 Events from Crossbar */
343 ti,edma-xbar-event-map = /bits/ 16 <1 12
344 2 13>;
345};
346
347
348&mmc3 {
349 /* Wifi & Bluetooth on MMC #3 */
350 status = "okay";
351 pinctrl-names = "default";
352 pinctrl-0 = <&wireless_pins>;
353 vmmmc-supply = <&v3v3c_reg>;
354 bus-width = <4>;
355 ti,non-removable;
356 dmas = <&edma 12
357 &edma 13>;
358 dma-names = "tx", "rx";
359};
360
361
362&am33xx_pinmux {
363 sd_pins: pinmux_sd_card {
364 pinctrl-single,pins = <
365 0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
366 0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
367 0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
368 0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
369 0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
370 0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
371 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
372 >;
373 };
374 emmc_pins: pinmux_emmc {
375 pinctrl-single,pins = <
376 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
377 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
378 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
379 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
380 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
381 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
382 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
383 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
384 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
385 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
386 /* EMMC nReset */
387 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
388 >;
389 };
390 wireless_pins: pinmux_wireless {
391 pinctrl-single,pins = <
392 0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
393 0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
394 0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
395 0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
396 0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
397 0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
398 /* WLAN nReset */
399 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
400 /* WLAN nPower down */
401 0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
402 /* 32kHz Clock */
403 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
404 >;
405 };
406};
407
408/* Power */
409&vbat {
410 regulator-name = "vbat";
411 regulator-min-microvolt = <5000000>;
412 regulator-max-microvolt = <5000000>;
413};
414
415&v3v3c_reg {
416 regulator-name = "v3v3c_reg";
417 regulator-min-microvolt = <3300000>;
418 regulator-max-microvolt = <3300000>;
419 vin-supply = <&vbat>;
420};
421
422&vdd5_reg {
423 regulator-name = "vdd5_reg";
424 regulator-min-microvolt = <5000000>;
425 regulator-max-microvolt = <5000000>;
426 vin-supply = <&vbat>;
427};
428
429/include/ "tps65217.dtsi"
430
431&tps {
432 backlight {
433 isel = <1>; /* ISET1 */
434 fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
435 default-brightness = <80>;
436 };
437
438 regulators {
439 dcdc1_reg: regulator@0 {
440 /* VDD_1V8 system supply */
441 };
442
443 dcdc2_reg: regulator@1 {
444 /* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
445 regulator-name = "vdd_core";
446 regulator-min-microvolt = <925000>;
447 regulator-max-microvolt = <1325000>;
448 regulator-boot-on;
449 };
450
451 dcdc3_reg: regulator@2 {
452 /* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
453 regulator-name = "vdd_mpu";
454 regulator-min-microvolt = <925000>;
455 regulator-max-microvolt = <1150000>;
456 regulator-boot-on;
457 };
458
459 ldo1_reg: regulator@3 {
460 /* VRTC 1.8V always-on supply */
461 regulator-always-on;
462 };
463
464 ldo2_reg: regulator@4 {
465 /* 3.3V rail */
466 };
467
468 ldo3_reg: regulator@5 {
469 /* VDD_3V3A 3.3V rail */
470 regulator-min-microvolt = <3300000>;
471 regulator-max-microvolt = <3300000>;
472 };
473
474 ldo4_reg: regulator@6 {
475 /* VDD_3V3B 3.3V rail */
476 };
477 };
478};
479
480/* SPI Busses */
481&spi0 {
482 status = "okay";
483 pinctrl-names = "default";
484 pinctrl-0 = <&spi0_pins>;
485};
486
487&am33xx_pinmux {
488 spi0_pins: pinmux_spi0 {
489 pinctrl-single,pins = <
490 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
491 0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
492 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
493 0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
494 >;
495 };
496};
497
498/* Touch Screen */
499&tscadc {
500 status = "okay";
501 tsc {
502 ti,wires = <4>;
503 ti,x-plate-resistance = <200>;
504 ti,coordinate-readouts = <5>;
505 ti,wire-config = <0x00 0x11 0x22 0x33>;
506 };
507
508 adc {
509 ti,adc-channels = <4 5 6 7>;
510 };
511};
512
513/* UARTs */
514&uart0 {
515 /* Serial Console */
516 status = "okay";
517 pinctrl-names = "default";
518 pinctrl-0 = <&uart0_pins>;
519};
520
521&uart1 {
522 /* Broken out to J6 header */
523 status = "okay";
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart1_pins>;
526};
527
528&am33xx_pinmux {
529 uart0_pins: pinmux_uart0 {
530 pinctrl-single,pins = <
531 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
532 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
533 >;
534 };
535 uart1_pins: pinmux_uart1 {
536 pinctrl-single,pins = <
537 0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
538 0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
539 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
540 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
541 >;
542 };
543};
544
545/* USB */
546&usb {
547 status = "okay";
548
549 pinctrl-names = "default";
550 pinctrl-0 = <&usb_pins>;
551};
552
553&usb_ctrl_mod {
554 status = "okay";
555};
556
557&usb0_phy {
558 status = "okay";
559};
560
561&usb1_phy {
562 status = "okay";
563};
564
565&usb0 {
566 status = "okay";
567 dr_mode = "host";
568};
569
570&usb1 {
571 status = "okay";
572 dr_mode = "host";
573};
574
575&cppi41dma {
576 status = "okay";
577};
578
579&am33xx_pinmux {
580 usb_pins: pinmux_usb {
581 pinctrl-single,pins = <
582 /* USB0 Over-Current (active low) */
583 0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
584 /* USB1 Over-Current (active low) */
585 0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
586 >;
587 };
588};
589
590/* User IO */
591&leds {
592 pinctrl-names = "default";
593 pinctrl-0 = <&user_leds_pins>;
594
595 led@0 {
596 label = "pepper:user0:blue";
597 gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
598 linux,default-trigger = "none";
599 default-state = "off";
600 };
601
602 led@1 {
603 label = "pepper:user1:red";
604 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
605 linux,default-trigger = "none";
606 default-state = "off";
607 };
608};
609
610&buttons {
611 pinctrl-names = "default";
612 pinctrl-0 = <&user_buttons_pins>;
613 #address-cells = <1>;
614 #size-cells = <0>;
615
616 button@0 {
617 label = "home";
618 linux,code = <KEY_HOME>;
619 gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
620 gpio-key,wakeup;
621 };
622
623 button@1 {
624 label = "menu";
625 linux,code = <KEY_MENU>;
626 gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
627 gpio-key,wakeup;
628 };
629
630 buttons@2 {
631 label = "power";
632 linux,code = <KEY_POWER>;
633 gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
634 gpio-key,wakeup;
635 };
636};
637
638&am33xx_pinmux {
639 user_leds_pins: pinmux_user_leds {
640 pinctrl-single,pins = <
641 0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
642 0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
643 >;
644 };
645
646 user_buttons_pins: pinmux_user_buttons {
647 pinctrl-single,pins = <
648 0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
649 0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
650 0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
651 >;
652 };
653};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index c9aee0e799bb..9b3d2ba82f13 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -30,7 +30,7 @@
30 cpus { 30 cpus {
31 #address-cells = <1>; 31 #address-cells = <1>;
32 #size-cells = <0>; 32 #size-cells = <0>;
33 cpu@0 { 33 cpu: cpu@0 {
34 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
35 device_type = "cpu"; 35 device_type = "cpu";
36 reg = <0>; 36 reg = <0>;
@@ -267,7 +267,7 @@
267 ti,hwmods = "counter_32k"; 267 ti,hwmods = "counter_32k";
268 }; 268 };
269 269
270 rtc@44e3e000 { 270 rtc: rtc@44e3e000 {
271 compatible = "ti,am4372-rtc","ti,da830-rtc"; 271 compatible = "ti,am4372-rtc","ti,da830-rtc";
272 reg = <0x44e3e000 0x1000>; 272 reg = <0x44e3e000 0x1000>;
273 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH 273 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
@@ -276,7 +276,7 @@
276 status = "disabled"; 276 status = "disabled";
277 }; 277 };
278 278
279 wdt@44e35000 { 279 wdt: wdt@44e35000 {
280 compatible = "ti,am4372-wdt","ti,omap3-wdt"; 280 compatible = "ti,am4372-wdt","ti,omap3-wdt";
281 reg = <0x44e35000 0x1000>; 281 reg = <0x44e35000 0x1000>;
282 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 282 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -868,7 +868,7 @@
868 #size-cells = <1>; 868 #size-cells = <1>;
869 ranges; 869 ranges;
870 870
871 dispc@4832a400 { 871 dispc: dispc@4832a400 {
872 compatible = "ti,omap3-dispc"; 872 compatible = "ti,omap3-dispc";
873 reg = <0x4832a400 0x400>; 873 reg = <0x4832a400 0x400>;
874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 874 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/am437x-gp-evm.dts b/arch/arm/boot/dts/am437x-gp-evm.dts
index 003766c47bbf..f0422c2a7468 100644
--- a/arch/arm/boot/dts/am437x-gp-evm.dts
+++ b/arch/arm/boot/dts/am437x-gp-evm.dts
@@ -257,16 +257,73 @@
257}; 257};
258 258
259&i2c0 { 259&i2c0 {
260 status = "okay"; 260 status = "okay";
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&i2c0_pins>; 262 pinctrl-0 = <&i2c0_pins>;
263 clock-frequency = <400000>;
264
265 tps65218: tps65218@24 {
266 reg = <0x24>;
267 compatible = "ti,tps65218";
268 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
269 interrupt-parent = <&gic>;
270 interrupt-controller;
271 #interrupt-cells = <2>;
272
273 dcdc1: regulator-dcdc1 {
274 compatible = "ti,tps65218-dcdc1";
275 regulator-name = "vdd_core";
276 regulator-min-microvolt = <912000>;
277 regulator-max-microvolt = <1144000>;
278 regulator-boot-on;
279 regulator-always-on;
280 };
281
282 dcdc2: regulator-dcdc2 {
283 compatible = "ti,tps65218-dcdc2";
284 regulator-name = "vdd_mpu";
285 regulator-min-microvolt = <912000>;
286 regulator-max-microvolt = <1378000>;
287 regulator-boot-on;
288 regulator-always-on;
289 };
290
291 dcdc3: regulator-dcdc3 {
292 compatible = "ti,tps65218-dcdc3";
293 regulator-name = "vdcdc3";
294 regulator-min-microvolt = <1350000>;
295 regulator-max-microvolt = <1350000>;
296 regulator-boot-on;
297 regulator-always-on;
298 };
299 dcdc5: regulator-dcdc5 {
300 compatible = "ti,tps65218-dcdc5";
301 regulator-name = "v1_0bat";
302 regulator-min-microvolt = <1000000>;
303 regulator-max-microvolt = <1000000>;
304 };
305
306 dcdc6: regulator-dcdc6 {
307 compatible = "ti,tps65218-dcdc6";
308 regulator-name = "v1_8bat";
309 regulator-min-microvolt = <1800000>;
310 regulator-max-microvolt = <1800000>;
311 };
312
313 ldo1: regulator-ldo1 {
314 compatible = "ti,tps65218-ldo1";
315 regulator-min-microvolt = <1800000>;
316 regulator-max-microvolt = <1800000>;
317 regulator-boot-on;
318 regulator-always-on;
319 };
320 };
263}; 321};
264 322
265&i2c1 { 323&i2c1 {
266 status = "okay"; 324 status = "okay";
267 pinctrl-names = "default"; 325 pinctrl-names = "default";
268 pinctrl-0 = <&i2c1_pins>; 326 pinctrl-0 = <&i2c1_pins>;
269
270 pixcir_ts@5c { 327 pixcir_ts@5c {
271 compatible = "pixcir,pixcir_tangoc"; 328 compatible = "pixcir,pixcir_tangoc";
272 pinctrl-names = "default"; 329 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/am437x-sk-evm.dts b/arch/arm/boot/dts/am437x-sk-evm.dts
new file mode 100644
index 000000000000..859ff3d620ee
--- /dev/null
+++ b/arch/arm/boot/dts/am437x-sk-evm.dts
@@ -0,0 +1,613 @@
1/*
2 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/* AM437x SK EVM */
10
11/dts-v1/;
12
13#include "am4372.dtsi"
14#include <dt-bindings/pinctrl/am43xx.h>
15#include <dt-bindings/pwm/pwm.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "TI AM437x SK EVM";
21 compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
22
23 aliases {
24 display0 = &lcd0;
25 };
26
27 backlight {
28 compatible = "pwm-backlight";
29 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
30 brightness-levels = <0 51 53 56 62 75 101 152 255>;
31 default-brightness-level = <8>;
32 };
33
34 sound {
35 compatible = "ti,da830-evm-audio";
36 ti,model = "AM437x-SK-EVM";
37 ti,audio-codec = <&tlv320aic3106>;
38 ti,mcasp-controller = <&mcasp1>;
39 ti,codec-clock-rate = <24000000>;
40 ti,audio-routing =
41 "Headphone Jack", "HPLOUT",
42 "Headphone Jack", "HPROUT";
43 };
44
45 matrix_keypad: matrix_keypad@0 {
46 compatible = "gpio-matrix-keypad";
47
48 pinctrl-names = "default";
49 pinctrl-0 = <&matrix_keypad_pins>;
50
51 debounce-delay-ms = <5>;
52 col-scan-delay-us = <1500>;
53
54 row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
55 &gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
56
57 col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
58 &gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
59
60 linux,keymap = <
61 MATRIX_KEY(0, 0, KEY_DOWN)
62 MATRIX_KEY(0, 1, KEY_RIGHT)
63 MATRIX_KEY(1, 0, KEY_LEFT)
64 MATRIX_KEY(1, 1, KEY_UP)
65 >;
66 };
67
68 leds {
69 compatible = "gpio-leds";
70
71 pinctrl-names = "default";
72 pinctrl-0 = <&leds_pins>;
73
74 led@0 {
75 label = "am437x-sk:red:heartbeat";
76 gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
77 linux,default-trigger = "heartbeat";
78 default-state = "off";
79 };
80
81 led@1 {
82 label = "am437x-sk:green:mmc1";
83 gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
84 linux,default-trigger = "mmc0";
85 default-state = "off";
86 };
87
88 led@2 {
89 label = "am437x-sk:blue:cpu0";
90 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
91 linux,default-trigger = "cpu0";
92 default-state = "off";
93 };
94
95 led@3 {
96 label = "am437x-sk:blue:usr3";
97 gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
98 default-state = "off";
99 };
100 };
101
102 lcd0: display {
103 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
104 label = "lcd";
105
106 pinctrl-names = "default";
107 pinctrl-0 = <&lcd_pins>;
108
109 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
110
111 panel-timing {
112 clock-frequency = <9000000>;
113 hactive = <480>;
114 vactive = <272>;
115 hfront-porch = <8>;
116 hback-porch = <43>;
117 hsync-len = <4>;
118 vback-porch = <12>;
119 vfront-porch = <4>;
120 vsync-len = <10>;
121 hsync-active = <0>;
122 vsync-active = <0>;
123 de-active = <1>;
124 pixelclk-active = <1>;
125 };
126
127 port {
128 lcd_in: endpoint {
129 remote-endpoint = <&dpi_out>;
130 };
131 };
132 };
133};
134
135&am43xx_pinmux {
136 matrix_keypad_pins: matrix_keypad_pins {
137 pinctrl-single,pins = <
138 0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
139 0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
140 0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
141 0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
142 >;
143 };
144
145 leds_pins: leds_pins {
146 pinctrl-single,pins = <
147 0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
148 0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
149 0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
150 0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
151 >;
152 };
153
154 i2c0_pins: i2c0_pins {
155 pinctrl-single,pins = <
156 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
157 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
158 >;
159 };
160
161 i2c1_pins: i2c1_pins {
162 pinctrl-single,pins = <
163 0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
164 0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
165 >;
166 };
167
168 mmc1_pins: pinmux_mmc1_pins {
169 pinctrl-single,pins = <
170 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
171 >;
172 };
173
174 ecap0_pins: backlight_pins {
175 pinctrl-single,pins = <
176 0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
177 >;
178 };
179
180 edt_ft5306_ts_pins: edt_ft5306_ts_pins {
181 pinctrl-single,pins = <
182 0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
183 0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
184 >;
185 };
186
187 cpsw_default: cpsw_default {
188 pinctrl-single,pins = <
189 /* Slave 1 */
190 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
191 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
192 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
193 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
194 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
195 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
196 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
197 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
198 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
199 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
200 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
201 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
202
203 /* Slave 2 */
204 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
205 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
206 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
207 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
208 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
209 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
210 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
211 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
212 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
213 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
214 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
215 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
216 >;
217 };
218
219 cpsw_sleep: cpsw_sleep {
220 pinctrl-single,pins = <
221 /* Slave 1 reset value */
222 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
223 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
224 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
232 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
233 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
234
235 /* Slave 2 reset value */
236 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
237 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
238 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
239 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
240 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
241 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
242 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
243 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
248 >;
249 };
250
251 davinci_mdio_default: davinci_mdio_default {
252 pinctrl-single,pins = <
253 /* MDIO */
254 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
255 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
256 >;
257 };
258
259 davinci_mdio_sleep: davinci_mdio_sleep {
260 pinctrl-single,pins = <
261 /* MDIO reset value */
262 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
263 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
264 >;
265 };
266
267 dss_pins: dss_pins {
268 pinctrl-single,pins = <
269 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
270 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
271 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
272 0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
273 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
274 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
275 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
276 0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
277 0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
278 0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
279 0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
280 0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
281 0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
282 0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
283 0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
284 0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
285 0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
286 0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
287 0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
288 0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
289 0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
290 0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
291 0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
292 0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
293 0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
294 0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
295 0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
296 0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
297
298 >;
299 };
300
301 qspi_pins: qspi_pins {
302 pinctrl-single,pins = <
303 0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
304 0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
305 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
306 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
307 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
308 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
309 >;
310 };
311
312 mcasp1_pins: mcasp1_pins {
313 pinctrl-single,pins = <
314 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
315 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
316 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
317 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
318 >;
319 };
320
321 lcd_pins: lcd_pins {
322 pinctrl-single,pins = <
323 /* GPIO 5_8 to select LCD / HDMI */
324 0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
325 >;
326 };
327};
328
329&i2c0 {
330 status = "okay";
331 pinctrl-names = "default";
332 pinctrl-0 = <&i2c0_pins>;
333 clock-frequency = <400000>;
334
335 tps@24 {
336 compatible = "ti,tps65218";
337 reg = <0x24>;
338 interrupt-parent = <&gic>;
339 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
340 interrupt-controller;
341 #interrupt-cells = <2>;
342
343 dcdc1: regulator-dcdc1 {
344 compatible = "ti,tps65218-dcdc1";
345 /* VDD_CORE limits min of OPP50 and max of OPP100 */
346 regulator-name = "vdd_core";
347 regulator-min-microvolt = <912000>;
348 regulator-max-microvolt = <1144000>;
349 regulator-boot-on;
350 regulator-always-on;
351 };
352
353 dcdc2: regulator-dcdc2 {
354 compatible = "ti,tps65218-dcdc2";
355 /* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
356 regulator-name = "vdd_mpu";
357 regulator-min-microvolt = <912000>;
358 regulator-max-microvolt = <1378000>;
359 regulator-boot-on;
360 regulator-always-on;
361 };
362
363 dcdc3: regulator-dcdc3 {
364 compatible = "ti,tps65218-dcdc3";
365 regulator-name = "vdds_ddr";
366 regulator-min-microvolt = <1350000>;
367 regulator-max-microvolt = <1350000>;
368 regulator-boot-on;
369 regulator-always-on;
370 };
371
372 dcdc4: regulator-dcdc4 {
373 compatible = "ti,tps65218-dcdc4";
374 regulator-name = "v3_3d";
375 regulator-min-microvolt = <3300000>;
376 regulator-max-microvolt = <3300000>;
377 regulator-boot-on;
378 regulator-always-on;
379 };
380
381 ldo1: regulator-ldo1 {
382 compatible = "ti,tps65218-ldo1";
383 regulator-name = "v1_8d";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 regulator-boot-on;
387 regulator-always-on;
388 };
389
390 };
391
392 at24@50 {
393 compatible = "at24,24c256";
394 pagesize = <64>;
395 reg = <0x50>;
396 };
397};
398
399&i2c1 {
400 status = "okay";
401 pinctrl-names = "default";
402 pinctrl-0 = <&i2c1_pins>;
403 clock-frequency = <400000>;
404
405 edt-ft5306@38 {
406 status = "okay";
407 compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
408 pinctrl-names = "default";
409 pinctrl-0 = <&edt_ft5306_ts_pins>;
410
411 reg = <0x38>;
412 interrupt-parent = <&gpio0>;
413 interrupts = <31 0>;
414
415 wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
416
417 touchscreen-size-x = <480>;
418 touchscreen-size-y = <272>;
419 };
420
421 tlv320aic3106: tlv320aic3106@1b {
422 compatible = "ti,tlv320aic3106";
423 reg = <0x1b>;
424 status = "okay";
425
426 /* Regulators */
427 AVDD-supply = <&dcdc4>;
428 IOVDD-supply = <&dcdc4>;
429 DRVDD-supply = <&dcdc4>;
430 DVDD-supply = <&ldo1>;
431 };
432
433 lis331dlh@18 {
434 compatible = "st,lis331dlh";
435 reg = <0x18>;
436 status = "okay";
437
438 Vdd-supply = <&dcdc4>;
439 Vdd_IO-supply = <&dcdc4>;
440 interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
441 };
442};
443
444&epwmss0 {
445 status = "okay";
446};
447
448&ecap0 {
449 status = "okay";
450 pinctrl-names = "default";
451 pinctrl-0 = <&ecap0_pins>;
452};
453
454&gpio0 {
455 status = "okay";
456};
457
458&gpio1 {
459 status = "okay";
460};
461
462&gpio5 {
463 status = "okay";
464};
465
466&mmc1 {
467 status = "okay";
468 pinctrl-names = "default";
469 pinctrl-0 = <&mmc1_pins>;
470
471 vmmc-supply = <&dcdc4>;
472 bus-width = <4>;
473 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
474};
475
476&usb2_phy1 {
477 status = "okay";
478};
479
480&usb1 {
481 dr_mode = "peripheral";
482 status = "okay";
483};
484
485&usb2_phy2 {
486 status = "okay";
487};
488
489&usb2 {
490 dr_mode = "host";
491 status = "okay";
492};
493
494&qspi {
495 status = "okay";
496 pinctrl-names = "default";
497 pinctrl-0 = <&qspi_pins>;
498
499 spi-max-frequency = <48000000>;
500 m25p80@0 {
501 compatible = "mx66l51235l";
502 spi-max-frequency = <48000000>;
503 reg = <0>;
504 spi-cpol;
505 spi-cpha;
506 spi-tx-bus-width = <1>;
507 spi-rx-bus-width = <4>;
508 #address-cells = <1>;
509 #size-cells = <1>;
510
511 /* MTD partition table.
512 * The ROM checks the first 512KiB
513 * for a valid file to boot(XIP).
514 */
515 partition@0 {
516 label = "QSPI.U_BOOT";
517 reg = <0x00000000 0x000080000>;
518 };
519 partition@1 {
520 label = "QSPI.U_BOOT.backup";
521 reg = <0x00080000 0x00080000>;
522 };
523 partition@2 {
524 label = "QSPI.U-BOOT-SPL_OS";
525 reg = <0x00100000 0x00010000>;
526 };
527 partition@3 {
528 label = "QSPI.U_BOOT_ENV";
529 reg = <0x00110000 0x00010000>;
530 };
531 partition@4 {
532 label = "QSPI.U-BOOT-ENV.backup";
533 reg = <0x00120000 0x00010000>;
534 };
535 partition@5 {
536 label = "QSPI.KERNEL";
537 reg = <0x00130000 0x0800000>;
538 };
539 partition@6 {
540 label = "QSPI.FILESYSTEM";
541 reg = <0x00930000 0x36D0000>;
542 };
543 };
544};
545
546&mac {
547 pinctrl-names = "default", "sleep";
548 pinctrl-0 = <&cpsw_default>;
549 pinctrl-1 = <&cpsw_sleep>;
550 dual_emac = <1>;
551 status = "okay";
552};
553
554&davinci_mdio {
555 pinctrl-names = "default", "sleep";
556 pinctrl-0 = <&davinci_mdio_default>;
557 pinctrl-1 = <&davinci_mdio_sleep>;
558 status = "okay";
559};
560
561&cpsw_emac0 {
562 phy_id = <&davinci_mdio>, <4>;
563 phy-mode = "rgmii";
564 dual_emac_res_vlan = <1>;
565};
566
567&cpsw_emac1 {
568 phy_id = <&davinci_mdio>, <5>;
569 phy-mode = "rgmii";
570 dual_emac_res_vlan = <2>;
571};
572
573&elm {
574 status = "okay";
575};
576
577&mcasp1 {
578 pinctrl-names = "default";
579 pinctrl-0 = <&mcasp1_pins>;
580
581 status = "okay";
582
583 op-mode = <0>;
584 tdm-slots = <2>;
585 serial-dir = <
586 0 0 1 2
587 >;
588
589 tx-num-evt = <1>;
590 rx-num-evt = <1>;
591};
592
593&dss {
594 status = "okay";
595
596 pinctrl-names = "default";
597 pinctrl-0 = <&dss_pins>;
598
599 port {
600 dpi_out: endpoint@0 {
601 remote-endpoint = <&lcd_in>;
602 data-lines = <24>;
603 };
604 };
605};
606
607&rtc {
608 status = "okay";
609};
610
611&wdt {
612 status = "okay";
613};
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index 90098f98a5c8..f1ee74957512 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -327,6 +327,65 @@
327 status = "okay"; 327 status = "okay";
328 pinctrl-names = "default"; 328 pinctrl-names = "default";
329 pinctrl-0 = <&i2c0_pins>; 329 pinctrl-0 = <&i2c0_pins>;
330 clock-frequency = <400000>;
331
332 tps65218: tps65218@24 {
333 reg = <0x24>;
334 compatible = "ti,tps65218";
335 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
336 interrupt-parent = <&gic>;
337 interrupt-controller;
338 #interrupt-cells = <2>;
339
340 dcdc1: regulator-dcdc1 {
341 compatible = "ti,tps65218-dcdc1";
342 regulator-name = "vdd_core";
343 regulator-min-microvolt = <912000>;
344 regulator-max-microvolt = <1144000>;
345 regulator-boot-on;
346 regulator-always-on;
347 };
348
349 dcdc2: regulator-dcdc2 {
350 compatible = "ti,tps65218-dcdc2";
351 regulator-name = "vdd_mpu";
352 regulator-min-microvolt = <912000>;
353 regulator-max-microvolt = <1378000>;
354 regulator-boot-on;
355 regulator-always-on;
356 };
357
358 dcdc3: regulator-dcdc3 {
359 compatible = "ti,tps65218-dcdc3";
360 regulator-name = "vdcdc3";
361 regulator-min-microvolt = <1350000>;
362 regulator-max-microvolt = <1350000>;
363 regulator-boot-on;
364 regulator-always-on;
365 };
366
367 dcdc5: regulator-dcdc5 {
368 compatible = "ti,tps65218-dcdc5";
369 regulator-name = "v1_0bat";
370 regulator-min-microvolt = <1000000>;
371 regulator-max-microvolt = <1000000>;
372 };
373
374 dcdc6: regulator-dcdc6 {
375 compatible = "ti,tps65218-dcdc6";
376 regulator-name = "v1_8bat";
377 regulator-min-microvolt = <1800000>;
378 regulator-max-microvolt = <1800000>;
379 };
380
381 ldo1: regulator-ldo1 {
382 compatible = "ti,tps65218-ldo1";
383 regulator-min-microvolt = <1800000>;
384 regulator-max-microvolt = <1800000>;
385 regulator-boot-on;
386 regulator-always-on;
387 };
388 };
330 389
331 at24@50 { 390 at24@50 {
332 compatible = "at24,24c256"; 391 compatible = "at24,24c256";
diff --git a/arch/arm/boot/dts/animeo_ip.dts b/arch/arm/boot/dts/animeo_ip.dts
index 3c4f6d983cbd..4e0ad3b82796 100644
--- a/arch/arm/boot/dts/animeo_ip.dts
+++ b/arch/arm/boot/dts/animeo_ip.dts
@@ -40,6 +40,14 @@
40 compatible = "atmel,osc", "fixed-clock"; 40 compatible = "atmel,osc", "fixed-clock";
41 clock-frequency = <18432000>; 41 clock-frequency = <18432000>;
42 }; 42 };
43
44 slow_xtal {
45 clock-frequency = <32768>;
46 };
47
48 main_xtal {
49 clock-frequency = <18432000>;
50 };
43 }; 51 };
44 52
45 ahb { 53 ahb {
diff --git a/arch/arm/boot/dts/armada-375-db.dts b/arch/arm/boot/dts/armada-375-db.dts
index 1e2919d43d78..929ae00b4063 100644
--- a/arch/arm/boot/dts/armada-375-db.dts
+++ b/arch/arm/boot/dts/armada-375-db.dts
@@ -123,6 +123,32 @@
123 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 123 cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
124 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 124 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
125 }; 125 };
126
127 mdio {
128 phy0: ethernet-phy@0 {
129 reg = <0>;
130 };
131
132 phy3: ethernet-phy@3 {
133 reg = <3>;
134 };
135 };
136
137 ethernet@f0000 {
138 status = "okay";
139
140 eth0@c4000 {
141 status = "okay";
142 phy = <&phy0>;
143 phy-mode = "rgmii-id";
144 };
145
146 eth1@c5000 {
147 status = "okay";
148 phy = <&phy3>;
149 phy-mode = "gmii";
150 };
151 };
126 }; 152 };
127 153
128 pcie-controller { 154 pcie-controller {
diff --git a/arch/arm/boot/dts/armada-375.dtsi b/arch/arm/boot/dts/armada-375.dtsi
index fb92551a1e71..c1e49e7bf0fa 100644
--- a/arch/arm/boot/dts/armada-375.dtsi
+++ b/arch/arm/boot/dts/armada-375.dtsi
@@ -25,6 +25,8 @@
25 gpio0 = &gpio0; 25 gpio0 = &gpio0;
26 gpio1 = &gpio1; 26 gpio1 = &gpio1;
27 gpio2 = &gpio2; 27 gpio2 = &gpio2;
28 ethernet0 = &eth0;
29 ethernet1 = &eth1;
28 }; 30 };
29 31
30 clocks { 32 clocks {
@@ -151,6 +153,38 @@
151 <0xc100 0x100>; 153 <0xc100 0x100>;
152 }; 154 };
153 155
156 mdio {
157 #address-cells = <1>;
158 #size-cells = <0>;
159 compatible = "marvell,orion-mdio";
160 reg = <0xc0054 0x4>;
161 clocks = <&gateclk 19>;
162 };
163
164 /* Network controller */
165 ethernet@f0000 {
166 compatible = "marvell,armada-375-pp2";
167 reg = <0xf0000 0xa000>, /* Packet Processor regs */
168 <0xc0000 0x3060>, /* LMS regs */
169 <0xc4000 0x100>, /* eth0 regs */
170 <0xc5000 0x100>; /* eth1 regs */
171 clocks = <&gateclk 3>, <&gateclk 19>;
172 clock-names = "pp_clk", "gop_clk";
173 status = "disabled";
174
175 eth0: eth0@c4000 {
176 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
177 port-id = <0>;
178 status = "disabled";
179 };
180
181 eth1: eth1@c5000 {
182 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
183 port-id = <1>;
184 status = "disabled";
185 };
186 };
187
154 spi0: spi@10600 { 188 spi0: spi@10600 {
155 compatible = "marvell,orion-spi"; 189 compatible = "marvell,orion-spi";
156 reg = <0x10600 0x50>; 190 reg = <0x10600 0x50>;
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 689fa1a46728..242d0ecc99f3 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -286,6 +286,11 @@
286 reg = <0x20800 0x10>; 286 reg = <0x20800 0x10>;
287 }; 287 };
288 288
289 mpcore-soc-ctrl@20d20 {
290 compatible = "marvell,armada-380-mpcore-soc-ctrl";
291 reg = <0x20d20 0x6c>;
292 };
293
289 coherency-fabric@21010 { 294 coherency-fabric@21010 {
290 compatible = "marvell,armada-380-coherency-fabric"; 295 compatible = "marvell,armada-380-coherency-fabric";
291 reg = <0x21010 0x1c>; 296 reg = <0x21010 0x1c>;
diff --git a/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
new file mode 100644
index 000000000000..469cf7137595
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
@@ -0,0 +1,284 @@
1/*
2 * Device Tree file for Lenovo Iomega ix4-300d
3 *
4 * Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12/dts-v1/;
13
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include "armada-xp-mv78230.dtsi"
17
18/ {
19 model = "Lenovo Iomega ix4-300d";
20 compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
21 "marvell,armadaxp", "marvell,armada-370-xp";
22
23 chosen {
24 bootargs = "console=ttyS0,115200 earlyprintk";
25 stdout-path = "/soc/internal-regs/serial@12000";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0 0x00000000 0 0x20000000>; /* 512MB */
31 };
32
33 soc {
34 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
35 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
36
37 pcie-controller {
38 status = "okay";
39
40 /* Quad port sata: Marvell 88SX7042 */
41 pcie@1,0 {
42 /* Port 0, Lane 0 */
43 status = "okay";
44 };
45
46 /* USB 3.0 xHCI controller: NEC D720200F1 */
47 pcie@5,0 {
48 /* Port 1, Lane 0 */
49 status = "okay";
50 };
51 };
52
53 internal-regs {
54 pinctrl {
55 poweroff_pin: poweroff-pin {
56 marvell,pins = "mpp24";
57 marvell,function = "gpio";
58 };
59
60 power_button_pin: power-button-pin {
61 marvell,pins = "mpp44";
62 marvell,function = "gpio";
63 };
64
65 reset_button_pin: reset-button-pin {
66 marvell,pins = "mpp45";
67 marvell,function = "gpio";
68 };
69 select_button_pin: select-button-pin {
70 marvell,pins = "mpp41";
71 marvell,function = "gpio";
72 };
73
74 scroll_button_pin: scroll-button-pin {
75 marvell,pins = "mpp42";
76 marvell,function = "gpio";
77 };
78
79 hdd_led_pin: hdd-led-pin {
80 marvell,pins = "mpp26";
81 marvell,function = "gpio";
82 };
83 };
84
85 serial@12000 {
86 status = "okay";
87 };
88
89 mdio {
90 phy0: ethernet-phy@0 { /* Marvell 88E1318 */
91 reg = <0>;
92 };
93
94 phy1: ethernet-phy@1 { /* Marvell 88E1318 */
95 reg = <1>;
96 };
97 };
98
99 ethernet@70000 {
100 status = "okay";
101 phy = <&phy0>;
102 phy-mode = "rgmii-id";
103 };
104
105 ethernet@74000 {
106 status = "okay";
107 phy = <&phy1>;
108 phy-mode = "rgmii-id";
109 };
110
111 usb@50000 {
112 status = "okay";
113 };
114
115 usb@51000 {
116 status = "okay";
117 };
118
119 i2c@11000 {
120 clock-frequency = <400000>;
121 status = "okay";
122
123 adt7473@2e {
124 compatible = "adi,adt7473";
125 reg = <0x2e>;
126 };
127
128 pcf8563@51 {
129 compatible = "nxp,pcf8563";
130 reg = <0x51>;
131 };
132
133 };
134
135 nand@d0000 {
136 status = "okay";
137 num-cs = <1>;
138 marvell,nand-keep-config;
139 marvell,nand-enable-arbiter;
140 nand-on-flash-bbt;
141
142 partition@0 {
143 label = "u-boot";
144 reg = <0x0000000 0xe0000>;
145 read-only;
146 };
147
148 partition@e0000 {
149 label = "u-boot-env";
150 reg = <0xe0000 0x20000>;
151 read-only;
152 };
153
154 partition@100000 {
155 label = "u-boot-env2";
156 reg = <0x100000 0x20000>;
157 read-only;
158 };
159
160 partition@120000 {
161 label = "zImage";
162 reg = <0x120000 0x400000>;
163 };
164
165 partition@520000 {
166 label = "initrd";
167 reg = <0x520000 0x400000>;
168 };
169
170 partition@xE00000 {
171 label = "boot";
172 reg = <0xE00000 0x3F200000>;
173 };
174
175 partition@flash {
176 label = "flash";
177 reg = <0x0 0x40000000>;
178 };
179 };
180 };
181 };
182
183 gpio-keys {
184 compatible = "gpio-keys";
185 pinctrl-0 = <&power_button_pin &reset_button_pin
186 &select_button_pin &scroll_button_pin>;
187 pinctrl-names = "default";
188
189 power-button {
190 label = "Power Button";
191 linux,code = <KEY_POWER>;
192 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
193 };
194
195 reset-button {
196 label = "Reset Button";
197 linux,code = <KEY_RESTART>;
198 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
199 };
200
201 select-button {
202 label = "Select Button";
203 linux,code = <BTN_SELECT>;
204 gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
205 };
206
207 scroll-button {
208 label = "Scroll Button";
209 linux,code = <KEY_SCROLLDOWN>;
210 gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
211 };
212 };
213
214 spi3 {
215 compatible = "spi-gpio";
216 status = "okay";
217 gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>;
218 gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/
219 cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
220 num-chipselects = <1>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223
224 gpio_spi: gpio_spi@0 {
225 compatible = "fairchild,74hc595";
226 gpio-controller;
227 #gpio-cells = <2>;
228 reg = <0>;
229 registers-number = <2>;
230 spi-max-frequency = <100000>;
231 };
232 };
233
234 gpio-leds {
235 compatible = "gpio-leds";
236 pinctrl-0 = <&hdd_led_pin>;
237 pinctrl-names = "default";
238
239 hdd-led {
240 label = "ix4-300d:hdd:blue";
241 gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
242 default-state = "off";
243 };
244
245 power-led {
246 label = "ix4-300d:power:white";
247 gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
248 /* init blinking while booting */
249 linux,default-trigger = "timer";
250 default-state = "on";
251 };
252
253 sysfail-led {
254 label = "ix4-300d:sysfail:red";
255 gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>;
256 default-state = "off";
257 };
258
259 sys-led {
260 label = "ix4-300d:sys:blue";
261 gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>;
262 default-state = "off";
263 };
264
265 hddfail-led {
266 label = "ix4-300d:hddfail:red";
267 gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>;
268 default-state = "off";
269 };
270
271 };
272
273 /*
274 * Warning: you need both eth1 & 0 PHY initialized (i.e having
275 * them up does the tweak) for poweroff to shutdown otherwise it
276 * reboots
277 */
278 gpio-poweroff {
279 compatible = "gpio-poweroff";
280 pinctrl-0 = <&poweroff_pin>;
281 pinctrl-names = "default";
282 gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
283 };
284};
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
index 1257ff1ed278..2592e1c13560 100644
--- a/arch/arm/boot/dts/armada-xp-mv78230.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -34,6 +34,7 @@
34 compatible = "marvell,sheeva-v7"; 34 compatible = "marvell,sheeva-v7";
35 reg = <0>; 35 reg = <0>;
36 clocks = <&cpuclk 0>; 36 clocks = <&cpuclk 0>;
37 clock-latency = <1000000>;
37 }; 38 };
38 39
39 cpu@1 { 40 cpu@1 {
@@ -41,6 +42,7 @@
41 compatible = "marvell,sheeva-v7"; 42 compatible = "marvell,sheeva-v7";
42 reg = <1>; 43 reg = <1>;
43 clocks = <&cpuclk 1>; 44 clocks = <&cpuclk 1>;
45 clock-latency = <1000000>;
44 }; 46 };
45 }; 47 };
46 48
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index 3396b25b39e1..480e237a870f 100644
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -36,6 +36,7 @@
36 compatible = "marvell,sheeva-v7"; 36 compatible = "marvell,sheeva-v7";
37 reg = <0>; 37 reg = <0>;
38 clocks = <&cpuclk 0>; 38 clocks = <&cpuclk 0>;
39 clock-latency = <1000000>;
39 }; 40 };
40 41
41 cpu@1 { 42 cpu@1 {
@@ -43,6 +44,7 @@
43 compatible = "marvell,sheeva-v7"; 44 compatible = "marvell,sheeva-v7";
44 reg = <1>; 45 reg = <1>;
45 clocks = <&cpuclk 1>; 46 clocks = <&cpuclk 1>;
47 clock-latency = <1000000>;
46 }; 48 };
47 }; 49 };
48 50
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
index 6da84bf40aaf..2c7b1fef4703 100644
--- a/arch/arm/boot/dts/armada-xp-mv78460.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -37,6 +37,7 @@
37 compatible = "marvell,sheeva-v7"; 37 compatible = "marvell,sheeva-v7";
38 reg = <0>; 38 reg = <0>;
39 clocks = <&cpuclk 0>; 39 clocks = <&cpuclk 0>;
40 clock-latency = <1000000>;
40 }; 41 };
41 42
42 cpu@1 { 43 cpu@1 {
@@ -44,6 +45,7 @@
44 compatible = "marvell,sheeva-v7"; 45 compatible = "marvell,sheeva-v7";
45 reg = <1>; 46 reg = <1>;
46 clocks = <&cpuclk 1>; 47 clocks = <&cpuclk 1>;
48 clock-latency = <1000000>;
47 }; 49 };
48 50
49 cpu@2 { 51 cpu@2 {
@@ -51,6 +53,7 @@
51 compatible = "marvell,sheeva-v7"; 53 compatible = "marvell,sheeva-v7";
52 reg = <2>; 54 reg = <2>;
53 clocks = <&cpuclk 2>; 55 clocks = <&cpuclk 2>;
56 clock-latency = <1000000>;
54 }; 57 };
55 58
56 cpu@3 { 59 cpu@3 {
@@ -58,6 +61,7 @@
58 compatible = "marvell,sheeva-v7"; 61 compatible = "marvell,sheeva-v7";
59 reg = <3>; 62 reg = <3>;
60 clocks = <&cpuclk 3>; 63 clocks = <&cpuclk 3>;
64 clock-latency = <1000000>;
61 }; 65 };
62 }; 66 };
63 67
diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index 5902e8359c91..bff9f6c18db1 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -99,7 +99,7 @@
99 cpuclk: clock-complex@18700 { 99 cpuclk: clock-complex@18700 {
100 #clock-cells = <1>; 100 #clock-cells = <1>;
101 compatible = "marvell,armada-xp-cpu-clock"; 101 compatible = "marvell,armada-xp-cpu-clock";
102 reg = <0x18700 0xA0>; 102 reg = <0x18700 0xA0>, <0x1c054 0x10>;
103 clocks = <&coreclk 1>; 103 clocks = <&coreclk 1>;
104 }; 104 };
105 105
diff --git a/arch/arm/boot/dts/at91-ariag25.dts b/arch/arm/boot/dts/at91-ariag25.dts
index 55ab6180e350..e9ced30159a7 100644
--- a/arch/arm/boot/dts/at91-ariag25.dts
+++ b/arch/arm/boot/dts/at91-ariag25.dts
@@ -42,6 +42,14 @@
42 compatible = "atmel,osc", "fixed-clock"; 42 compatible = "atmel,osc", "fixed-clock";
43 clock-frequency = <12000000>; 43 clock-frequency = <12000000>;
44 }; 44 };
45
46 slow_xtal {
47 clock-frequency = <32768>;
48 };
49
50 main_xtal {
51 clock-frequency = <12000000>;
52 };
45 }; 53 };
46 54
47 ahb { 55 ahb {
diff --git a/arch/arm/boot/dts/at91-cosino.dtsi b/arch/arm/boot/dts/at91-cosino.dtsi
index df4b78695695..b6ea3f4a7206 100644
--- a/arch/arm/boot/dts/at91-cosino.dtsi
+++ b/arch/arm/boot/dts/at91-cosino.dtsi
@@ -34,6 +34,14 @@
34 compatible = "atmel,osc", "fixed-clock"; 34 compatible = "atmel,osc", "fixed-clock";
35 clock-frequency = <12000000>; 35 clock-frequency = <12000000>;
36 }; 36 };
37
38 slow_xtal {
39 clock-frequency = <32768>;
40 };
41
42 main_xtal {
43 clock-frequency = <12000000>;
44 };
37 }; 45 };
38 46
39 ahb { 47 ahb {
diff --git a/arch/arm/boot/dts/at91-foxg20.dts b/arch/arm/boot/dts/at91-foxg20.dts
index cbe967343997..f89598af4c2b 100644
--- a/arch/arm/boot/dts/at91-foxg20.dts
+++ b/arch/arm/boot/dts/at91-foxg20.dts
@@ -31,6 +31,14 @@
31 compatible = "atmel,osc", "fixed-clock"; 31 compatible = "atmel,osc", "fixed-clock";
32 clock-frequency = <18432000>; 32 clock-frequency = <18432000>;
33 }; 33 };
34
35 slow_xtal {
36 clock-frequency = <32768>;
37 };
38
39 main_xtal {
40 clock-frequency = <18432000>;
41 };
34 }; 42 };
35 43
36 ahb { 44 ahb {
diff --git a/arch/arm/boot/dts/at91-qil_a9260.dts b/arch/arm/boot/dts/at91-qil_a9260.dts
index 5576ae8786c0..a9aef53ab764 100644
--- a/arch/arm/boot/dts/at91-qil_a9260.dts
+++ b/arch/arm/boot/dts/at91-qil_a9260.dts
@@ -28,6 +28,14 @@
28 compatible = "atmel,osc", "fixed-clock"; 28 compatible = "atmel,osc", "fixed-clock";
29 clock-frequency = <12000000>; 29 clock-frequency = <12000000>;
30 }; 30 };
31
32 slow_xtal {
33 clock-frequency = <32768>;
34 };
35
36 main_xtal {
37 clock-frequency = <12000000>;
38 };
31 }; 39 };
32 40
33 ahb { 41 ahb {
diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
index 5b8e40400bec..fec1fca2ad66 100644
--- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts
@@ -21,12 +21,14 @@
21 reg = <0x20000000 0x10000000>; 21 reg = <0x20000000 0x10000000>;
22 }; 22 };
23 23
24 slow_xtal { 24 clocks {
25 clock-frequency = <32768>; 25 slow_xtal {
26 }; 26 clock-frequency = <32768>;
27 };
27 28
28 main_xtal { 29 main_xtal {
29 clock-frequency = <12000000>; 30 clock-frequency = <12000000>;
31 };
30 }; 32 };
31 33
32 ahb { 34 ahb {
diff --git a/arch/arm/boot/dts/at91rm9200.dtsi b/arch/arm/boot/dts/at91rm9200.dtsi
index c61b16fba79b..65ccf564b9a5 100644
--- a/arch/arm/boot/dts/at91rm9200.dtsi
+++ b/arch/arm/boot/dts/at91rm9200.dtsi
@@ -14,6 +14,7 @@
14#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
17 18
18/ { 19/ {
19 model = "Atmel AT91RM9200 family SoC"; 20 model = "Atmel AT91RM9200 family SoC";
@@ -51,6 +52,20 @@
51 reg = <0x20000000 0x04000000>; 52 reg = <0x20000000 0x04000000>;
52 }; 53 };
53 54
55 clocks {
56 slow_xtal: slow_xtal {
57 compatible = "fixed-clock";
58 #clock-cells = <0>;
59 clock-frequency = <0>;
60 };
61
62 main_xtal: main_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
67 };
68
54 ahb { 69 ahb {
55 compatible = "simple-bus"; 70 compatible = "simple-bus";
56 #address-cells = <1>; 71 #address-cells = <1>;
@@ -79,6 +94,260 @@
79 pmc: pmc@fffffc00 { 94 pmc: pmc@fffffc00 {
80 compatible = "atmel,at91rm9200-pmc"; 95 compatible = "atmel,at91rm9200-pmc";
81 reg = <0xfffffc00 0x100>; 96 reg = <0xfffffc00 0x100>;
97 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
98 interrupt-controller;
99 #address-cells = <1>;
100 #size-cells = <0>;
101 #interrupt-cells = <1>;
102
103 main_osc: main_osc {
104 compatible = "atmel,at91rm9200-clk-main-osc";
105 #clock-cells = <0>;
106 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
107 clocks = <&main_xtal>;
108 };
109
110 main: mainck {
111 compatible = "atmel,at91rm9200-clk-main";
112 #clock-cells = <0>;
113 clocks = <&main_osc>;
114 };
115
116 plla: pllack {
117 compatible = "atmel,at91rm9200-clk-pll";
118 #clock-cells = <0>;
119 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
120 clocks = <&main>;
121 reg = <0>;
122 atmel,clk-input-range = <1000000 32000000>;
123 #atmel,pll-clk-output-range-cells = <3>;
124 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
125 <150000000 180000000 2>;
126 };
127
128 pllb: pllbck {
129 compatible = "atmel,at91rm9200-clk-pll";
130 #clock-cells = <0>;
131 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
132 clocks = <&main>;
133 reg = <1>;
134 atmel,clk-input-range = <1000000 32000000>;
135 #atmel,pll-clk-output-range-cells = <3>;
136 atmel,pll-clk-output-ranges = <80000000 160000000 0>,
137 <150000000 180000000 2>;
138 };
139
140 mck: masterck {
141 compatible = "atmel,at91rm9200-clk-master";
142 #clock-cells = <0>;
143 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
144 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
145 atmel,clk-output-range = <0 80000000>;
146 atmel,clk-divisors = <1 2 3 4>;
147 };
148
149 usb: usbck {
150 compatible = "atmel,at91rm9200-clk-usb";
151 #clock-cells = <0>;
152 atmel,clk-divisors = <1 2>;
153 clocks = <&pllb>;
154 };
155
156 prog: progck {
157 compatible = "atmel,at91rm9200-clk-programmable";
158 #address-cells = <1>;
159 #size-cells = <0>;
160 interrupt-parent = <&pmc>;
161 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
162
163 prog0: prog0 {
164 #clock-cells = <0>;
165 reg = <0>;
166 interrupts = <AT91_PMC_PCKRDY(0)>;
167 };
168
169 prog1: prog1 {
170 #clock-cells = <0>;
171 reg = <1>;
172 interrupts = <AT91_PMC_PCKRDY(1)>;
173 };
174
175 prog2: prog2 {
176 #clock-cells = <0>;
177 reg = <2>;
178 interrupts = <AT91_PMC_PCKRDY(2)>;
179 };
180
181 prog3: prog3 {
182 #clock-cells = <0>;
183 reg = <3>;
184 interrupts = <AT91_PMC_PCKRDY(3)>;
185 };
186 };
187
188 systemck {
189 compatible = "atmel,at91rm9200-clk-system";
190 #address-cells = <1>;
191 #size-cells = <0>;
192
193 udpck: udpck {
194 #clock-cells = <0>;
195 reg = <2>;
196 clocks = <&usb>;
197 };
198
199 uhpck: uhpck {
200 #clock-cells = <0>;
201 reg = <4>;
202 clocks = <&usb>;
203 };
204
205 pck0: pck0 {
206 #clock-cells = <0>;
207 reg = <8>;
208 clocks = <&prog0>;
209 };
210
211 pck1: pck1 {
212 #clock-cells = <0>;
213 reg = <9>;
214 clocks = <&prog1>;
215 };
216
217 pck2: pck2 {
218 #clock-cells = <0>;
219 reg = <10>;
220 clocks = <&prog2>;
221 };
222
223 pck3: pck3 {
224 #clock-cells = <0>;
225 reg = <11>;
226 clocks = <&prog3>;
227 };
228 };
229
230 periphck {
231 compatible = "atmel,at91rm9200-clk-peripheral";
232 #address-cells = <1>;
233 #size-cells = <0>;
234 clocks = <&mck>;
235
236 pioA_clk: pioA_clk {
237 #clock-cells = <0>;
238 reg = <2>;
239 };
240
241 pioB_clk: pioB_clk {
242 #clock-cells = <0>;
243 reg = <3>;
244 };
245
246 pioC_clk: pioC_clk {
247 #clock-cells = <0>;
248 reg = <4>;
249 };
250
251 pioD_clk: pioD_clk {
252 #clock-cells = <0>;
253 reg = <5>;
254 };
255
256 usart0_clk: usart0_clk {
257 #clock-cells = <0>;
258 reg = <6>;
259 };
260
261 usart1_clk: usart1_clk {
262 #clock-cells = <0>;
263 reg = <7>;
264 };
265
266 usart2_clk: usart2_clk {
267 #clock-cells = <0>;
268 reg = <8>;
269 };
270
271 usart3_clk: usart3_clk {
272 #clock-cells = <0>;
273 reg = <9>;
274 };
275
276 mci0_clk: mci0_clk {
277 #clock-cells = <0>;
278 reg = <10>;
279 };
280
281 udc_clk: udc_clk {
282 #clock-cells = <0>;
283 reg = <11>;
284 };
285
286 twi0_clk: twi0_clk {
287 reg = <12>;
288 #clock-cells = <0>;
289 };
290
291 spi0_clk: spi0_clk {
292 #clock-cells = <0>;
293 reg = <13>;
294 };
295
296 ssc0_clk: ssc0_clk {
297 #clock-cells = <0>;
298 reg = <14>;
299 };
300
301 ssc1_clk: ssc1_clk {
302 #clock-cells = <0>;
303 reg = <15>;
304 };
305
306 ssc2_clk: ssc2_clk {
307 #clock-cells = <0>;
308 reg = <16>;
309 };
310
311 tc0_clk: tc0_clk {
312 #clock-cells = <0>;
313 reg = <17>;
314 };
315
316 tc1_clk: tc1_clk {
317 #clock-cells = <0>;
318 reg = <18>;
319 };
320
321 tc2_clk: tc2_clk {
322 #clock-cells = <0>;
323 reg = <19>;
324 };
325
326 tc3_clk: tc3_clk {
327 #clock-cells = <0>;
328 reg = <20>;
329 };
330
331 tc4_clk: tc4_clk {
332 #clock-cells = <0>;
333 reg = <21>;
334 };
335
336 tc5_clk: tc5_clk {
337 #clock-cells = <0>;
338 reg = <22>;
339 };
340
341 ohci_clk: ohci_clk {
342 #clock-cells = <0>;
343 reg = <23>;
344 };
345
346 macb0_clk: macb0_clk {
347 #clock-cells = <0>;
348 reg = <24>;
349 };
350 };
82 }; 351 };
83 352
84 st: timer@fffffd00 { 353 st: timer@fffffd00 {
@@ -93,6 +362,8 @@
93 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 362 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
94 18 IRQ_TYPE_LEVEL_HIGH 0 363 18 IRQ_TYPE_LEVEL_HIGH 0
95 19 IRQ_TYPE_LEVEL_HIGH 0>; 364 19 IRQ_TYPE_LEVEL_HIGH 0>;
365 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
366 clock-names = "t0_clk", "t1_clk", "t2_clk";
96 }; 367 };
97 368
98 tcb1: timer@fffa4000 { 369 tcb1: timer@fffa4000 {
@@ -101,6 +372,8 @@
101 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 372 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0
102 21 IRQ_TYPE_LEVEL_HIGH 0 373 21 IRQ_TYPE_LEVEL_HIGH 0
103 22 IRQ_TYPE_LEVEL_HIGH 0>; 374 22 IRQ_TYPE_LEVEL_HIGH 0>;
375 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
376 clock-names = "t0_clk", "t1_clk", "t2_clk";
104 }; 377 };
105 378
106 i2c0: i2c@fffb8000 { 379 i2c0: i2c@fffb8000 {
@@ -109,6 +382,7 @@
109 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 382 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
110 pinctrl-names = "default"; 383 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_twi>; 384 pinctrl-0 = <&pinctrl_twi>;
385 clocks = <&twi0_clk>;
112 #address-cells = <1>; 386 #address-cells = <1>;
113 #size-cells = <0>; 387 #size-cells = <0>;
114 status = "disabled"; 388 status = "disabled";
@@ -118,6 +392,8 @@
118 compatible = "atmel,hsmci"; 392 compatible = "atmel,hsmci";
119 reg = <0xfffb4000 0x4000>; 393 reg = <0xfffb4000 0x4000>;
120 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 394 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
395 clocks = <&mci0_clk>;
396 clock-names = "mci_clk";
121 #address-cells = <1>; 397 #address-cells = <1>;
122 #size-cells = <0>; 398 #size-cells = <0>;
123 pinctrl-names = "default"; 399 pinctrl-names = "default";
@@ -130,6 +406,8 @@
130 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 406 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
131 pinctrl-names = "default"; 407 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 408 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
409 clocks = <&ssc0_clk>;
410 clock-names = "pclk";
133 status = "disable"; 411 status = "disable";
134 }; 412 };
135 413
@@ -139,6 +417,8 @@
139 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 417 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
140 pinctrl-names = "default"; 418 pinctrl-names = "default";
141 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 419 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
420 clocks = <&ssc1_clk>;
421 clock-names = "pclk";
142 status = "disable"; 422 status = "disable";
143 }; 423 };
144 424
@@ -148,6 +428,8 @@
148 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 428 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
149 pinctrl-names = "default"; 429 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; 430 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>;
431 clocks = <&ssc2_clk>;
432 clock-names = "pclk";
151 status = "disable"; 433 status = "disable";
152 }; 434 };
153 435
@@ -158,6 +440,8 @@
158 phy-mode = "rmii"; 440 phy-mode = "rmii";
159 pinctrl-names = "default"; 441 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_macb_rmii>; 442 pinctrl-0 = <&pinctrl_macb_rmii>;
443 clocks = <&macb0_clk>;
444 clock-names = "ether_clk";
161 status = "disabled"; 445 status = "disabled";
162 }; 446 };
163 447
@@ -496,6 +780,7 @@
496 gpio-controller; 780 gpio-controller;
497 interrupt-controller; 781 interrupt-controller;
498 #interrupt-cells = <2>; 782 #interrupt-cells = <2>;
783 clocks = <&pioA_clk>;
499 }; 784 };
500 785
501 pioB: gpio@fffff600 { 786 pioB: gpio@fffff600 {
@@ -506,6 +791,7 @@
506 gpio-controller; 791 gpio-controller;
507 interrupt-controller; 792 interrupt-controller;
508 #interrupt-cells = <2>; 793 #interrupt-cells = <2>;
794 clocks = <&pioB_clk>;
509 }; 795 };
510 796
511 pioC: gpio@fffff800 { 797 pioC: gpio@fffff800 {
@@ -516,6 +802,7 @@
516 gpio-controller; 802 gpio-controller;
517 interrupt-controller; 803 interrupt-controller;
518 #interrupt-cells = <2>; 804 #interrupt-cells = <2>;
805 clocks = <&pioC_clk>;
519 }; 806 };
520 807
521 pioD: gpio@fffffa00 { 808 pioD: gpio@fffffa00 {
@@ -526,6 +813,7 @@
526 gpio-controller; 813 gpio-controller;
527 interrupt-controller; 814 interrupt-controller;
528 #interrupt-cells = <2>; 815 #interrupt-cells = <2>;
816 clocks = <&pioD_clk>;
529 }; 817 };
530 }; 818 };
531 819
@@ -535,6 +823,8 @@
535 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 823 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
536 pinctrl-names = "default"; 824 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_dbgu>; 825 pinctrl-0 = <&pinctrl_dbgu>;
826 clocks = <&mck>;
827 clock-names = "usart";
538 status = "disabled"; 828 status = "disabled";
539 }; 829 };
540 830
@@ -546,6 +836,8 @@
546 atmel,use-dma-tx; 836 atmel,use-dma-tx;
547 pinctrl-names = "default"; 837 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_uart0>; 838 pinctrl-0 = <&pinctrl_uart0>;
839 clocks = <&usart0_clk>;
840 clock-names = "usart";
549 status = "disabled"; 841 status = "disabled";
550 }; 842 };
551 843
@@ -557,6 +849,8 @@
557 atmel,use-dma-tx; 849 atmel,use-dma-tx;
558 pinctrl-names = "default"; 850 pinctrl-names = "default";
559 pinctrl-0 = <&pinctrl_uart1>; 851 pinctrl-0 = <&pinctrl_uart1>;
852 clocks = <&usart1_clk>;
853 clock-names = "usart";
560 status = "disabled"; 854 status = "disabled";
561 }; 855 };
562 856
@@ -568,6 +862,8 @@
568 atmel,use-dma-tx; 862 atmel,use-dma-tx;
569 pinctrl-names = "default"; 863 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_uart2>; 864 pinctrl-0 = <&pinctrl_uart2>;
865 clocks = <&usart2_clk>;
866 clock-names = "usart";
571 status = "disabled"; 867 status = "disabled";
572 }; 868 };
573 869
@@ -579,6 +875,8 @@
579 atmel,use-dma-tx; 875 atmel,use-dma-tx;
580 pinctrl-names = "default"; 876 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_uart3>; 877 pinctrl-0 = <&pinctrl_uart3>;
878 clocks = <&usart3_clk>;
879 clock-names = "usart";
582 status = "disabled"; 880 status = "disabled";
583 }; 881 };
584 882
@@ -586,6 +884,8 @@
586 compatible = "atmel,at91rm9200-udc"; 884 compatible = "atmel,at91rm9200-udc";
587 reg = <0xfffb0000 0x4000>; 885 reg = <0xfffb0000 0x4000>;
588 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; 886 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
887 clocks = <&udc_clk>, <&udpck>;
888 clock-names = "pclk", "hclk";
589 status = "disabled"; 889 status = "disabled";
590 }; 890 };
591 891
@@ -597,6 +897,8 @@
597 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 897 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
598 pinctrl-names = "default"; 898 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_spi0>; 899 pinctrl-0 = <&pinctrl_spi0>;
900 clocks = <&spi0_clk>;
901 clock-names = "spi_clk";
600 status = "disabled"; 902 status = "disabled";
601 }; 903 };
602 }; 904 };
@@ -622,6 +924,8 @@
622 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 924 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
623 reg = <0x00300000 0x100000>; 925 reg = <0x00300000 0x100000>;
624 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 926 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>;
927 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
928 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
625 status = "disabled"; 929 status = "disabled";
626 }; 930 };
627 }; 931 };
diff --git a/arch/arm/boot/dts/at91rm9200ek.dts b/arch/arm/boot/dts/at91rm9200ek.dts
index df6b0aa0e4dd..43eb779dd6f6 100644
--- a/arch/arm/boot/dts/at91rm9200ek.dts
+++ b/arch/arm/boot/dts/at91rm9200ek.dts
@@ -25,6 +25,14 @@
25 compatible = "atmel,osc", "fixed-clock"; 25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>; 26 clock-frequency = <18432000>;
27 }; 27 };
28
29 slow_xtal {
30 clock-frequency = <32768>;
31 };
32
33 main_xtal {
34 clock-frequency = <18432000>;
35 };
28 }; 36 };
29 37
30 ahb { 38 ahb {
diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index c0e0eae16a27..cb100b03a362 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -12,6 +12,7 @@
12#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/pinctrl/at91.h>
13#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/gpio/gpio.h> 14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/clock/at91.h>
15 16
16/ { 17/ {
17 model = "Atmel AT91SAM9260 family SoC"; 18 model = "Atmel AT91SAM9260 family SoC";
@@ -48,6 +49,26 @@
48 reg = <0x20000000 0x04000000>; 49 reg = <0x20000000 0x04000000>;
49 }; 50 };
50 51
52 clocks {
53 slow_xtal: slow_xtal {
54 compatible = "fixed-clock";
55 #clock-cells = <0>;
56 clock-frequency = <0>;
57 };
58
59 main_xtal: main_xtal {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <0>;
63 };
64
65 adc_op_clk: adc_op_clk{
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <5000000>;
69 };
70 };
71
51 ahb { 72 ahb {
52 compatible = "simple-bus"; 73 compatible = "simple-bus";
53 #address-cells = <1>; 74 #address-cells = <1>;
@@ -74,8 +95,260 @@
74 }; 95 };
75 96
76 pmc: pmc@fffffc00 { 97 pmc: pmc@fffffc00 {
77 compatible = "atmel,at91rm9200-pmc"; 98 compatible = "atmel,at91sam9260-pmc";
78 reg = <0xfffffc00 0x100>; 99 reg = <0xfffffc00 0x100>;
100 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
101 interrupt-controller;
102 #address-cells = <1>;
103 #size-cells = <0>;
104 #interrupt-cells = <1>;
105
106 main_osc: main_osc {
107 compatible = "atmel,at91rm9200-clk-main-osc";
108 #clock-cells = <0>;
109 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
110 clocks = <&main_xtal>;
111 };
112
113 main: mainck {
114 compatible = "atmel,at91rm9200-clk-main";
115 #clock-cells = <0>;
116 clocks = <&main_osc>;
117 };
118
119 slow_rc_osc: slow_rc_osc {
120 compatible = "fixed-clock";
121 #clock-cells = <0>;
122 clock-frequency = <32768>;
123 clock-accuracy = <50000000>;
124 };
125
126 clk32k: slck {
127 compatible = "atmel,at91sam9260-clk-slow";
128 #clock-cells = <0>;
129 clocks = <&slow_rc_osc>, <&slow_xtal>;
130 };
131
132 plla: pllack {
133 compatible = "atmel,at91rm9200-clk-pll";
134 #clock-cells = <0>;
135 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
136 clocks = <&main>;
137 reg = <0>;
138 atmel,clk-input-range = <1000000 32000000>;
139 #atmel,pll-clk-output-range-cells = <4>;
140 atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
141 <150000000 240000000 2 1>;
142 };
143
144 pllb: pllbck {
145 compatible = "atmel,at91rm9200-clk-pll";
146 #clock-cells = <0>;
147 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
148 clocks = <&main>;
149 reg = <1>;
150 atmel,clk-input-range = <1000000 5000000>;
151 #atmel,pll-clk-output-range-cells = <4>;
152 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
153 };
154
155 mck: masterck {
156 compatible = "atmel,at91rm9200-clk-master";
157 #clock-cells = <0>;
158 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
159 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
160 atmel,clk-output-range = <0 105000000>;
161 atmel,clk-divisors = <1 2 4 0>;
162 };
163
164 usb: usbck {
165 compatible = "atmel,at91rm9200-clk-usb";
166 #clock-cells = <0>;
167 atmel,clk-divisors = <1 2 4 0>;
168 clocks = <&pllb>;
169 };
170
171 prog: progck {
172 compatible = "atmel,at91rm9200-clk-programmable";
173 #address-cells = <1>;
174 #size-cells = <0>;
175 interrupt-parent = <&pmc>;
176 clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
177
178 prog0: prog0 {
179 #clock-cells = <0>;
180 reg = <0>;
181 interrupts = <AT91_PMC_PCKRDY(0)>;
182 };
183
184 prog1: prog1 {
185 #clock-cells = <0>;
186 reg = <1>;
187 interrupts = <AT91_PMC_PCKRDY(1)>;
188 };
189 };
190
191 systemck {
192 compatible = "atmel,at91rm9200-clk-system";
193 #address-cells = <1>;
194 #size-cells = <0>;
195
196 uhpck: uhpck {
197 #clock-cells = <0>;
198 reg = <6>;
199 clocks = <&usb>;
200 };
201
202 udpck: udpck {
203 #clock-cells = <0>;
204 reg = <7>;
205 clocks = <&usb>;
206 };
207
208 pck0: pck0 {
209 #clock-cells = <0>;
210 reg = <8>;
211 clocks = <&prog0>;
212 };
213
214 pck1: pck1 {
215 #clock-cells = <0>;
216 reg = <9>;
217 clocks = <&prog1>;
218 };
219 };
220
221 periphck {
222 compatible = "atmel,at91rm9200-clk-peripheral";
223 #address-cells = <1>;
224 #size-cells = <0>;
225 clocks = <&mck>;
226
227 pioA_clk: pioA_clk {
228 #clock-cells = <0>;
229 reg = <2>;
230 };
231
232 pioB_clk: pioB_clk {
233 #clock-cells = <0>;
234 reg = <3>;
235 };
236
237 pioC_clk: pioC_clk {
238 #clock-cells = <0>;
239 reg = <4>;
240 };
241
242 adc_clk: adc_clk {
243 #clock-cells = <0>;
244 reg = <5>;
245 };
246
247 usart0_clk: usart0_clk {
248 #clock-cells = <0>;
249 reg = <6>;
250 };
251
252 usart1_clk: usart1_clk {
253 #clock-cells = <0>;
254 reg = <7>;
255 };
256
257 usart2_clk: usart2_clk {
258 #clock-cells = <0>;
259 reg = <8>;
260 };
261
262 mci0_clk: mci0_clk {
263 #clock-cells = <0>;
264 reg = <9>;
265 };
266
267 udc_clk: udc_clk {
268 #clock-cells = <0>;
269 reg = <10>;
270 };
271
272 twi0_clk: twi0_clk {
273 reg = <11>;
274 #clock-cells = <0>;
275 };
276
277 spi0_clk: spi0_clk {
278 #clock-cells = <0>;
279 reg = <12>;
280 };
281
282 spi1_clk: spi1_clk {
283 #clock-cells = <0>;
284 reg = <13>;
285 };
286
287 ssc0_clk: ssc0_clk {
288 #clock-cells = <0>;
289 reg = <14>;
290 };
291
292 tc0_clk: tc0_clk {
293 #clock-cells = <0>;
294 reg = <17>;
295 };
296
297 tc1_clk: tc1_clk {
298 #clock-cells = <0>;
299 reg = <18>;
300 };
301
302 tc2_clk: tc2_clk {
303 #clock-cells = <0>;
304 reg = <19>;
305 };
306
307 ohci_clk: ohci_clk {
308 #clock-cells = <0>;
309 reg = <20>;
310 };
311
312 macb0_clk: macb0_clk {
313 #clock-cells = <0>;
314 reg = <21>;
315 };
316
317 isi_clk: isi_clk {
318 #clock-cells = <0>;
319 reg = <22>;
320 };
321
322 usart3_clk: usart3_clk {
323 #clock-cells = <0>;
324 reg = <23>;
325 };
326
327 uart0_clk: uart0_clk {
328 #clock-cells = <0>;
329 reg = <24>;
330 };
331
332 uart1_clk: uart1_clk {
333 #clock-cells = <0>;
334 reg = <25>;
335 };
336
337 tc3_clk: tc3_clk {
338 #clock-cells = <0>;
339 reg = <26>;
340 };
341
342 tc4_clk: tc4_clk {
343 #clock-cells = <0>;
344 reg = <27>;
345 };
346
347 tc5_clk: tc5_clk {
348 #clock-cells = <0>;
349 reg = <28>;
350 };
351 };
79 }; 352 };
80 353
81 rstc@fffffd00 { 354 rstc@fffffd00 {
@@ -92,6 +365,7 @@
92 compatible = "atmel,at91sam9260-pit"; 365 compatible = "atmel,at91sam9260-pit";
93 reg = <0xfffffd30 0xf>; 366 reg = <0xfffffd30 0xf>;
94 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 367 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
368 clocks = <&mck>;
95 }; 369 };
96 370
97 tcb0: timer@fffa0000 { 371 tcb0: timer@fffa0000 {
@@ -100,6 +374,8 @@
100 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 374 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
101 18 IRQ_TYPE_LEVEL_HIGH 0 375 18 IRQ_TYPE_LEVEL_HIGH 0
102 19 IRQ_TYPE_LEVEL_HIGH 0>; 376 19 IRQ_TYPE_LEVEL_HIGH 0>;
377 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>;
378 clock-names = "t0_clk", "t1_clk", "t2_clk";
103 }; 379 };
104 380
105 tcb1: timer@fffdc000 { 381 tcb1: timer@fffdc000 {
@@ -108,6 +384,8 @@
108 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0 384 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
109 27 IRQ_TYPE_LEVEL_HIGH 0 385 27 IRQ_TYPE_LEVEL_HIGH 0
110 28 IRQ_TYPE_LEVEL_HIGH 0>; 386 28 IRQ_TYPE_LEVEL_HIGH 0>;
387 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>;
388 clock-names = "t0_clk", "t1_clk", "t2_clk";
111 }; 389 };
112 390
113 pinctrl@fffff400 { 391 pinctrl@fffff400 {
@@ -443,6 +721,7 @@
443 gpio-controller; 721 gpio-controller;
444 interrupt-controller; 722 interrupt-controller;
445 #interrupt-cells = <2>; 723 #interrupt-cells = <2>;
724 clocks = <&pioA_clk>;
446 }; 725 };
447 726
448 pioB: gpio@fffff600 { 727 pioB: gpio@fffff600 {
@@ -453,6 +732,7 @@
453 gpio-controller; 732 gpio-controller;
454 interrupt-controller; 733 interrupt-controller;
455 #interrupt-cells = <2>; 734 #interrupt-cells = <2>;
735 clocks = <&pioB_clk>;
456 }; 736 };
457 737
458 pioC: gpio@fffff800 { 738 pioC: gpio@fffff800 {
@@ -463,6 +743,7 @@
463 gpio-controller; 743 gpio-controller;
464 interrupt-controller; 744 interrupt-controller;
465 #interrupt-cells = <2>; 745 #interrupt-cells = <2>;
746 clocks = <&pioC_clk>;
466 }; 747 };
467 }; 748 };
468 749
@@ -472,6 +753,8 @@
472 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 753 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
473 pinctrl-names = "default"; 754 pinctrl-names = "default";
474 pinctrl-0 = <&pinctrl_dbgu>; 755 pinctrl-0 = <&pinctrl_dbgu>;
756 clocks = <&mck>;
757 clock-names = "usart";
475 status = "disabled"; 758 status = "disabled";
476 }; 759 };
477 760
@@ -483,6 +766,8 @@
483 atmel,use-dma-tx; 766 atmel,use-dma-tx;
484 pinctrl-names = "default"; 767 pinctrl-names = "default";
485 pinctrl-0 = <&pinctrl_usart0>; 768 pinctrl-0 = <&pinctrl_usart0>;
769 clocks = <&usart0_clk>;
770 clock-names = "usart";
486 status = "disabled"; 771 status = "disabled";
487 }; 772 };
488 773
@@ -494,6 +779,8 @@
494 atmel,use-dma-tx; 779 atmel,use-dma-tx;
495 pinctrl-names = "default"; 780 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_usart1>; 781 pinctrl-0 = <&pinctrl_usart1>;
782 clocks = <&usart1_clk>;
783 clock-names = "usart";
497 status = "disabled"; 784 status = "disabled";
498 }; 785 };
499 786
@@ -505,6 +792,8 @@
505 atmel,use-dma-tx; 792 atmel,use-dma-tx;
506 pinctrl-names = "default"; 793 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_usart2>; 794 pinctrl-0 = <&pinctrl_usart2>;
795 clocks = <&usart2_clk>;
796 clock-names = "usart";
508 status = "disabled"; 797 status = "disabled";
509 }; 798 };
510 799
@@ -516,6 +805,8 @@
516 atmel,use-dma-tx; 805 atmel,use-dma-tx;
517 pinctrl-names = "default"; 806 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_usart3>; 807 pinctrl-0 = <&pinctrl_usart3>;
808 clocks = <&usart3_clk>;
809 clock-names = "usart";
519 status = "disabled"; 810 status = "disabled";
520 }; 811 };
521 812
@@ -527,6 +818,8 @@
527 atmel,use-dma-tx; 818 atmel,use-dma-tx;
528 pinctrl-names = "default"; 819 pinctrl-names = "default";
529 pinctrl-0 = <&pinctrl_uart0>; 820 pinctrl-0 = <&pinctrl_uart0>;
821 clocks = <&uart0_clk>;
822 clock-names = "usart";
530 status = "disabled"; 823 status = "disabled";
531 }; 824 };
532 825
@@ -538,6 +831,8 @@
538 atmel,use-dma-tx; 831 atmel,use-dma-tx;
539 pinctrl-names = "default"; 832 pinctrl-names = "default";
540 pinctrl-0 = <&pinctrl_uart1>; 833 pinctrl-0 = <&pinctrl_uart1>;
834 clocks = <&uart1_clk>;
835 clock-names = "usart";
541 status = "disabled"; 836 status = "disabled";
542 }; 837 };
543 838
@@ -547,6 +842,8 @@
547 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 842 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
548 pinctrl-names = "default"; 843 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_macb_rmii>; 844 pinctrl-0 = <&pinctrl_macb_rmii>;
845 clocks = <&macb0_clk>, <&macb0_clk>;
846 clock-names = "hclk", "pclk";
550 status = "disabled"; 847 status = "disabled";
551 }; 848 };
552 849
@@ -554,6 +851,8 @@
554 compatible = "atmel,at91rm9200-udc"; 851 compatible = "atmel,at91rm9200-udc";
555 reg = <0xfffa4000 0x4000>; 852 reg = <0xfffa4000 0x4000>;
556 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>; 853 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
854 clocks = <&udc_clk>, <&udpck>;
855 clock-names = "pclk", "hclk";
557 status = "disabled"; 856 status = "disabled";
558 }; 857 };
559 858
@@ -563,6 +862,7 @@
563 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>; 862 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
564 #address-cells = <1>; 863 #address-cells = <1>;
565 #size-cells = <0>; 864 #size-cells = <0>;
865 clocks = <&twi0_clk>;
566 status = "disabled"; 866 status = "disabled";
567 }; 867 };
568 868
@@ -573,6 +873,8 @@
573 #address-cells = <1>; 873 #address-cells = <1>;
574 #size-cells = <0>; 874 #size-cells = <0>;
575 pinctrl-names = "default"; 875 pinctrl-names = "default";
876 clocks = <&mci0_clk>;
877 clock-names = "mci_clk";
576 status = "disabled"; 878 status = "disabled";
577 }; 879 };
578 880
@@ -582,6 +884,8 @@
582 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 884 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
583 pinctrl-names = "default"; 885 pinctrl-names = "default";
584 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 886 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
887 clocks = <&ssc0_clk>;
888 clock-names = "pclk";
585 status = "disabled"; 889 status = "disabled";
586 }; 890 };
587 891
@@ -593,6 +897,8 @@
593 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>; 897 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
594 pinctrl-names = "default"; 898 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_spi0>; 899 pinctrl-0 = <&pinctrl_spi0>;
900 clocks = <&spi0_clk>;
901 clock-names = "spi_clk";
596 status = "disabled"; 902 status = "disabled";
597 }; 903 };
598 904
@@ -604,6 +910,8 @@
604 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 910 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
605 pinctrl-names = "default"; 911 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_spi1>; 912 pinctrl-0 = <&pinctrl_spi1>;
913 clocks = <&spi1_clk>;
914 clock-names = "spi_clk";
607 status = "disabled"; 915 status = "disabled";
608 }; 916 };
609 917
@@ -613,6 +921,8 @@
613 compatible = "atmel,at91sam9260-adc"; 921 compatible = "atmel,at91sam9260-adc";
614 reg = <0xfffe0000 0x100>; 922 reg = <0xfffe0000 0x100>;
615 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>; 923 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
924 clocks = <&adc_clk>, <&adc_op_clk>;
925 clock-names = "adc_clk", "adc_op_clk";
616 atmel,adc-use-external-triggers; 926 atmel,adc-use-external-triggers;
617 atmel,adc-channels-used = <0xf>; 927 atmel,adc-channels-used = <0xf>;
618 atmel,adc-vref = <3300>; 928 atmel,adc-vref = <3300>;
@@ -680,6 +990,8 @@
680 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 990 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
681 reg = <0x00500000 0x100000>; 991 reg = <0x00500000 0x100000>;
682 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>; 992 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
993 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
994 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
683 status = "disabled"; 995 status = "disabled";
684 }; 996 };
685 }; 997 };
diff --git a/arch/arm/boot/dts/at91sam9261.dtsi b/arch/arm/boot/dts/at91sam9261.dtsi
index 04927db1d6bf..a81aab4281a7 100644
--- a/arch/arm/boot/dts/at91sam9261.dtsi
+++ b/arch/arm/boot/dts/at91sam9261.dtsi
@@ -46,16 +46,18 @@
46 reg = <0x20000000 0x08000000>; 46 reg = <0x20000000 0x08000000>;
47 }; 47 };
48 48
49 main_xtal: main_xtal { 49 clocks {
50 compatible = "fixed-clock"; 50 main_xtal: main_xtal {
51 #clock-cells = <0>; 51 compatible = "fixed-clock";
52 clock-frequency = <0>; 52 #clock-cells = <0>;
53 }; 53 clock-frequency = <0>;
54 };
54 55
55 slow_xtal: slow_xtal { 56 slow_xtal: slow_xtal {
56 compatible = "fixed-clock"; 57 compatible = "fixed-clock";
57 #clock-cells = <0>; 58 #clock-cells = <0>;
58 clock-frequency = <0>; 59 clock-frequency = <0>;
60 };
59 }; 61 };
60 62
61 ahb { 63 ahb {
diff --git a/arch/arm/boot/dts/at91sam9261ek.dts b/arch/arm/boot/dts/at91sam9261ek.dts
index aa35a7aec9a8..f4a765729c7a 100644
--- a/arch/arm/boot/dts/at91sam9261ek.dts
+++ b/arch/arm/boot/dts/at91sam9261ek.dts
@@ -20,14 +20,6 @@
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23 slow_xtal {
24 clock-frequency = <32768>;
25 };
26
27 main_xtal {
28 clock-frequency = <18432000>;
29 };
30
31 clocks { 23 clocks {
32 #address-cells = <1>; 24 #address-cells = <1>;
33 #size-cells = <1>; 25 #size-cells = <1>;
@@ -37,6 +29,14 @@
37 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
38 clock-frequency = <18432000>; 30 clock-frequency = <18432000>;
39 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <18432000>;
39 };
40 }; 40 };
41 41
42 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index fece8665fb63..bb23c2d33cf8 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -10,6 +10,7 @@
10#include <dt-bindings/pinctrl/at91.h> 10#include <dt-bindings/pinctrl/at91.h>
11#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/clock/at91.h>
13 14
14/ { 15/ {
15 model = "Atmel AT91SAM9263 family SoC"; 16 model = "Atmel AT91SAM9263 family SoC";
@@ -32,6 +33,7 @@
32 ssc1 = &ssc1; 33 ssc1 = &ssc1;
33 pwm0 = &pwm0; 34 pwm0 = &pwm0;
34 }; 35 };
36
35 cpus { 37 cpus {
36 #address-cells = <0>; 38 #address-cells = <0>;
37 #size-cells = <0>; 39 #size-cells = <0>;
@@ -46,6 +48,20 @@
46 reg = <0x20000000 0x08000000>; 48 reg = <0x20000000 0x08000000>;
47 }; 49 };
48 50
51 clocks {
52 main_xtal: main_xtal {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <0>;
56 };
57
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63 };
64
49 ahb { 65 ahb {
50 compatible = "simple-bus"; 66 compatible = "simple-bus";
51 #address-cells = <1>; 67 #address-cells = <1>;
@@ -69,6 +85,264 @@
69 pmc: pmc@fffffc00 { 85 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc"; 86 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>; 87 reg = <0xfffffc00 0x100>;
88 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
89 interrupt-controller;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 #interrupt-cells = <1>;
93
94 main_osc: main_osc {
95 compatible = "atmel,at91rm9200-clk-main-osc";
96 #clock-cells = <0>;
97 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
98 clocks = <&main_xtal>;
99 };
100
101 main: mainck {
102 compatible = "atmel,at91rm9200-clk-main";
103 #clock-cells = <0>;
104 clocks = <&main_osc>;
105 };
106
107 plla: pllack {
108 compatible = "atmel,at91rm9200-clk-pll";
109 #clock-cells = <0>;
110 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
111 clocks = <&main>;
112 reg = <0>;
113 atmel,clk-input-range = <1000000 32000000>;
114 #atmel,pll-clk-output-range-cells = <4>;
115 atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
116 <190000000 240000000 2 1>;
117 };
118
119 pllb: pllbck {
120 compatible = "atmel,at91rm9200-clk-pll";
121 #clock-cells = <0>;
122 interrupts-extended = <&pmc AT91_PMC_LOCKB>;
123 clocks = <&main>;
124 reg = <1>;
125 atmel,clk-input-range = <1000000 5000000>;
126 #atmel,pll-clk-output-range-cells = <4>;
127 atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
128 };
129
130 mck: masterck {
131 compatible = "atmel,at91rm9200-clk-master";
132 #clock-cells = <0>;
133 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
134 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
135 atmel,clk-output-range = <0 120000000>;
136 atmel,clk-divisors = <1 2 4 0>;
137 };
138
139 usb: usbck {
140 compatible = "atmel,at91rm9200-clk-usb";
141 #clock-cells = <0>;
142 atmel,clk-divisors = <1 2 4 0>;
143 clocks = <&pllb>;
144 };
145
146 prog: progck {
147 compatible = "atmel,at91rm9200-clk-programmable";
148 #address-cells = <1>;
149 #size-cells = <0>;
150 interrupt-parent = <&pmc>;
151 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>;
152
153 prog0: prog0 {
154 #clock-cells = <0>;
155 reg = <0>;
156 interrupts = <AT91_PMC_PCKRDY(0)>;
157 };
158
159 prog1: prog1 {
160 #clock-cells = <0>;
161 reg = <1>;
162 interrupts = <AT91_PMC_PCKRDY(1)>;
163 };
164
165 prog2: prog2 {
166 #clock-cells = <0>;
167 reg = <2>;
168 interrupts = <AT91_PMC_PCKRDY(2)>;
169 };
170
171 prog3: prog3 {
172 #clock-cells = <0>;
173 reg = <3>;
174 interrupts = <AT91_PMC_PCKRDY(3)>;
175 };
176 };
177
178 systemck {
179 compatible = "atmel,at91rm9200-clk-system";
180 #address-cells = <1>;
181 #size-cells = <0>;
182
183 uhpck: uhpck {
184 #clock-cells = <0>;
185 reg = <6>;
186 clocks = <&usb>;
187 };
188
189 udpck: udpck {
190 #clock-cells = <0>;
191 reg = <7>;
192 clocks = <&usb>;
193 };
194
195 pck0: pck0 {
196 #clock-cells = <0>;
197 reg = <8>;
198 clocks = <&prog0>;
199 };
200
201 pck1: pck1 {
202 #clock-cells = <0>;
203 reg = <9>;
204 clocks = <&prog1>;
205 };
206
207 pck2: pck2 {
208 #clock-cells = <0>;
209 reg = <10>;
210 clocks = <&prog2>;
211 };
212
213 pck3: pck3 {
214 #clock-cells = <0>;
215 reg = <11>;
216 clocks = <&prog3>;
217 };
218 };
219
220 periphck {
221 compatible = "atmel,at91rm9200-clk-peripheral";
222 #address-cells = <1>;
223 #size-cells = <0>;
224 clocks = <&mck>;
225
226 pioA_clk: pioA_clk {
227 #clock-cells = <0>;
228 reg = <2>;
229 };
230
231 pioB_clk: pioB_clk {
232 #clock-cells = <0>;
233 reg = <3>;
234 };
235
236 pioCDE_clk: pioCDE_clk {
237 #clock-cells = <0>;
238 reg = <4>;
239 };
240
241 usart0_clk: usart0_clk {
242 #clock-cells = <0>;
243 reg = <7>;
244 };
245
246 usart1_clk: usart1_clk {
247 #clock-cells = <0>;
248 reg = <8>;
249 };
250
251 usart2_clk: usart2_clk {
252 #clock-cells = <0>;
253 reg = <9>;
254 };
255
256 mci0_clk: mci0_clk {
257 #clock-cells = <0>;
258 reg = <10>;
259 };
260
261 mci1_clk: mci1_clk {
262 #clock-cells = <0>;
263 reg = <11>;
264 };
265
266 can_clk: can_clk {
267 #clock-cells = <0>;
268 reg = <12>;
269 };
270
271 twi0_clk: twi0_clk {
272 #clock-cells = <0>;
273 reg = <13>;
274 };
275
276 spi0_clk: spi0_clk {
277 #clock-cells = <0>;
278 reg = <14>;
279 };
280
281 spi1_clk: spi1_clk {
282 #clock-cells = <0>;
283 reg = <15>;
284 };
285
286 ssc0_clk: ssc0_clk {
287 #clock-cells = <0>;
288 reg = <16>;
289 };
290
291 ssc1_clk: ssc1_clk {
292 #clock-cells = <0>;
293 reg = <17>;
294 };
295
296 ac91_clk: ac97_clk {
297 #clock-cells = <0>;
298 reg = <18>;
299 };
300
301 tcb_clk: tcb_clk {
302 #clock-cells = <0>;
303 reg = <19>;
304 };
305
306 pwm_clk: pwm_clk {
307 #clock-cells = <0>;
308 reg = <20>;
309 };
310
311 macb0_clk: macb0_clk {
312 #clock-cells = <0>;
313 reg = <21>;
314 };
315
316 g2de_clk: g2de_clk {
317 #clock-cells = <0>;
318 reg = <23>;
319 };
320
321 udc_clk: udc_clk {
322 #clock-cells = <0>;
323 reg = <24>;
324 };
325
326 isi_clk: isi_clk {
327 #clock-cells = <0>;
328 reg = <25>;
329 };
330
331 lcd_clk: lcd_clk {
332 #clock-cells = <0>;
333 reg = <26>;
334 };
335
336 dma_clk: dma_clk {
337 #clock-cells = <0>;
338 reg = <27>;
339 };
340
341 ohci_clk: ohci_clk {
342 #clock-cells = <0>;
343 reg = <29>;
344 };
345 };
72 }; 346 };
73 347
74 ramc: ramc@ffffe200 { 348 ramc: ramc@ffffe200 {
@@ -81,12 +355,15 @@
81 compatible = "atmel,at91sam9260-pit"; 355 compatible = "atmel,at91sam9260-pit";
82 reg = <0xfffffd30 0xf>; 356 reg = <0xfffffd30 0xf>;
83 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 357 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
358 clocks = <&mck>;
84 }; 359 };
85 360
86 tcb0: timer@fff7c000 { 361 tcb0: timer@fff7c000 {
87 compatible = "atmel,at91rm9200-tcb"; 362 compatible = "atmel,at91rm9200-tcb";
88 reg = <0xfff7c000 0x100>; 363 reg = <0xfff7c000 0x100>;
89 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>; 364 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
365 clocks = <&tcb_clk>;
366 clock-names = "t0_clk";
90 }; 367 };
91 368
92 rstc@fffffd00 { 369 rstc@fffffd00 {
@@ -403,6 +680,7 @@
403 gpio-controller; 680 gpio-controller;
404 interrupt-controller; 681 interrupt-controller;
405 #interrupt-cells = <2>; 682 #interrupt-cells = <2>;
683 clocks = <&pioA_clk>;
406 }; 684 };
407 685
408 pioB: gpio@fffff400 { 686 pioB: gpio@fffff400 {
@@ -413,6 +691,7 @@
413 gpio-controller; 691 gpio-controller;
414 interrupt-controller; 692 interrupt-controller;
415 #interrupt-cells = <2>; 693 #interrupt-cells = <2>;
694 clocks = <&pioB_clk>;
416 }; 695 };
417 696
418 pioC: gpio@fffff600 { 697 pioC: gpio@fffff600 {
@@ -423,6 +702,7 @@
423 gpio-controller; 702 gpio-controller;
424 interrupt-controller; 703 interrupt-controller;
425 #interrupt-cells = <2>; 704 #interrupt-cells = <2>;
705 clocks = <&pioCDE_clk>;
426 }; 706 };
427 707
428 pioD: gpio@fffff800 { 708 pioD: gpio@fffff800 {
@@ -433,6 +713,7 @@
433 gpio-controller; 713 gpio-controller;
434 interrupt-controller; 714 interrupt-controller;
435 #interrupt-cells = <2>; 715 #interrupt-cells = <2>;
716 clocks = <&pioCDE_clk>;
436 }; 717 };
437 718
438 pioE: gpio@fffffa00 { 719 pioE: gpio@fffffa00 {
@@ -443,6 +724,7 @@
443 gpio-controller; 724 gpio-controller;
444 interrupt-controller; 725 interrupt-controller;
445 #interrupt-cells = <2>; 726 #interrupt-cells = <2>;
727 clocks = <&pioCDE_clk>;
446 }; 728 };
447 }; 729 };
448 730
@@ -452,6 +734,8 @@
452 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 734 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
453 pinctrl-names = "default"; 735 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_dbgu>; 736 pinctrl-0 = <&pinctrl_dbgu>;
737 clocks = <&mck>;
738 clock-names = "usart";
455 status = "disabled"; 739 status = "disabled";
456 }; 740 };
457 741
@@ -463,6 +747,8 @@
463 atmel,use-dma-tx; 747 atmel,use-dma-tx;
464 pinctrl-names = "default"; 748 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_usart0>; 749 pinctrl-0 = <&pinctrl_usart0>;
750 clocks = <&usart0_clk>;
751 clock-names = "usart";
466 status = "disabled"; 752 status = "disabled";
467 }; 753 };
468 754
@@ -474,6 +760,8 @@
474 atmel,use-dma-tx; 760 atmel,use-dma-tx;
475 pinctrl-names = "default"; 761 pinctrl-names = "default";
476 pinctrl-0 = <&pinctrl_usart1>; 762 pinctrl-0 = <&pinctrl_usart1>;
763 clocks = <&usart1_clk>;
764 clock-names = "usart";
477 status = "disabled"; 765 status = "disabled";
478 }; 766 };
479 767
@@ -485,6 +773,8 @@
485 atmel,use-dma-tx; 773 atmel,use-dma-tx;
486 pinctrl-names = "default"; 774 pinctrl-names = "default";
487 pinctrl-0 = <&pinctrl_usart2>; 775 pinctrl-0 = <&pinctrl_usart2>;
776 clocks = <&usart2_clk>;
777 clock-names = "usart";
488 status = "disabled"; 778 status = "disabled";
489 }; 779 };
490 780
@@ -494,6 +784,8 @@
494 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 784 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
495 pinctrl-names = "default"; 785 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 786 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
787 clocks = <&ssc0_clk>;
788 clock-names = "pclk";
497 status = "disabled"; 789 status = "disabled";
498 }; 790 };
499 791
@@ -503,6 +795,8 @@
503 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 795 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
504 pinctrl-names = "default"; 796 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 797 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
798 clocks = <&ssc1_clk>;
799 clock-names = "pclk";
506 status = "disabled"; 800 status = "disabled";
507 }; 801 };
508 802
@@ -512,6 +806,8 @@
512 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>; 806 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
513 pinctrl-names = "default"; 807 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_macb_rmii>; 808 pinctrl-0 = <&pinctrl_macb_rmii>;
809 clocks = <&macb0_clk>, <&macb0_clk>;
810 clock-names = "hclk", "pclk";
515 status = "disabled"; 811 status = "disabled";
516 }; 812 };
517 813
@@ -519,6 +815,8 @@
519 compatible = "atmel,at91rm9200-udc"; 815 compatible = "atmel,at91rm9200-udc";
520 reg = <0xfff78000 0x4000>; 816 reg = <0xfff78000 0x4000>;
521 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>; 817 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
818 clocks = <&udc_clk>, <&udpck>;
819 clock-names = "pclk", "hclk";
522 status = "disabled"; 820 status = "disabled";
523 }; 821 };
524 822
@@ -528,6 +826,7 @@
528 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>; 826 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
529 #address-cells = <1>; 827 #address-cells = <1>;
530 #size-cells = <0>; 828 #size-cells = <0>;
829 clocks = <&twi0_clk>;
531 status = "disabled"; 830 status = "disabled";
532 }; 831 };
533 832
@@ -537,6 +836,8 @@
537 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 836 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
538 #address-cells = <1>; 837 #address-cells = <1>;
539 #size-cells = <0>; 838 #size-cells = <0>;
839 clocks = <&mci0_clk>;
840 clock-names = "mci_clk";
540 status = "disabled"; 841 status = "disabled";
541 }; 842 };
542 843
@@ -546,6 +847,8 @@
546 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>; 847 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
547 #address-cells = <1>; 848 #address-cells = <1>;
548 #size-cells = <0>; 849 #size-cells = <0>;
850 clocks = <&mci1_clk>;
851 clock-names = "mci_clk";
549 status = "disabled"; 852 status = "disabled";
550 }; 853 };
551 854
@@ -568,6 +871,8 @@
568 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>; 871 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
569 pinctrl-names = "default"; 872 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_spi0>; 873 pinctrl-0 = <&pinctrl_spi0>;
874 clocks = <&spi0_clk>;
875 clock-names = "spi_clk";
571 status = "disabled"; 876 status = "disabled";
572 }; 877 };
573 878
@@ -579,6 +884,8 @@
579 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>; 884 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
580 pinctrl-names = "default"; 885 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_spi1>; 886 pinctrl-0 = <&pinctrl_spi1>;
887 clocks = <&spi1_clk>;
888 clock-names = "spi_clk";
582 status = "disabled"; 889 status = "disabled";
583 }; 890 };
584 891
@@ -587,6 +894,8 @@
587 reg = <0xfffb8000 0x300>; 894 reg = <0xfffb8000 0x300>;
588 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>; 895 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
589 #pwm-cells = <3>; 896 #pwm-cells = <3>;
897 clocks = <&pwm_clk>;
898 clock-names = "pwm_clk";
590 status = "disabled"; 899 status = "disabled";
591 }; 900 };
592 }; 901 };
@@ -622,6 +931,8 @@
622 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 931 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
623 reg = <0x00a00000 0x100000>; 932 reg = <0x00a00000 0x100000>;
624 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>; 933 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
934 clocks = <&usb>, <&ohci_clk>, <&ohci_clk>, <&uhpck>;
935 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
625 status = "disabled"; 936 status = "disabled";
626 }; 937 };
627 }; 938 };
diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 15009c9f2293..5cf93eecd8f1 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -29,6 +29,14 @@
29 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <16367660>; 30 clock-frequency = <16367660>;
31 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <16367660>;
39 };
32 }; 40 };
33 41
34 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/at91sam9g20.dtsi b/arch/arm/boot/dts/at91sam9g20.dtsi
index b8e79466014f..31f7652612fc 100644
--- a/arch/arm/boot/dts/at91sam9g20.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20.dtsi
@@ -25,6 +25,30 @@
25 adc0: adc@fffe0000 { 25 adc0: adc@fffe0000 {
26 atmel,adc-startup-time = <40>; 26 atmel,adc-startup-time = <40>;
27 }; 27 };
28
29 pmc: pmc@fffffc00 {
30 plla: pllack {
31 atmel,clk-input-range = <2000000 32000000>;
32 atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
33 <695000000 750000000 1 0>,
34 <645000000 700000000 2 0>,
35 <595000000 650000000 3 0>,
36 <545000000 600000000 0 1>,
37 <495000000 550000000 1 1>,
38 <445000000 500000000 2 1>,
39 <400000000 450000000 3 1>;
40 };
41
42 pllb: pllbck {
43 atmel,clk-input-range = <2000000 32000000>;
44 atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
45 };
46
47 mck: masterck {
48 atmel,clk-output-range = <0 133000000>;
49 atmel,clk-divisors = <1 2 4 6>;
50 };
51 };
28 }; 52 };
29 }; 53 };
30}; 54};
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index cb2c010e08e2..d2919108e92d 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -26,6 +26,14 @@
26 compatible = "atmel,osc", "fixed-clock"; 26 compatible = "atmel,osc", "fixed-clock";
27 clock-frequency = <18432000>; 27 clock-frequency = <18432000>;
28 }; 28 };
29
30 slow_xtal {
31 clock-frequency = <32768>;
32 };
33
34 main_xtal {
35 clock-frequency = <18432000>;
36 };
29 }; 37 };
30 38
31 ahb { 39 ahb {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index ace6bf197b70..932a669156af 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -14,6 +14,7 @@
14#include <dt-bindings/pinctrl/at91.h> 14#include <dt-bindings/pinctrl/at91.h>
15#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/clock/at91.h>
17 18
18/ { 19/ {
19 model = "Atmel AT91SAM9G45 family SoC"; 20 model = "Atmel AT91SAM9G45 family SoC";
@@ -53,6 +54,26 @@
53 reg = <0x70000000 0x10000000>; 54 reg = <0x70000000 0x10000000>;
54 }; 55 };
55 56
57 clocks {
58 slow_xtal: slow_xtal {
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <0>;
62 };
63
64 main_xtal: main_xtal {
65 compatible = "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <0>;
68 };
69
70 adc_op_clk: adc_op_clk{
71 compatible = "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <300000>;
74 };
75 };
76
56 ahb { 77 ahb {
57 compatible = "simple-bus"; 78 compatible = "simple-bus";
58 #address-cells = <1>; 79 #address-cells = <1>;
@@ -77,11 +98,279 @@
77 compatible = "atmel,at91sam9g45-ddramc"; 98 compatible = "atmel,at91sam9g45-ddramc";
78 reg = <0xffffe400 0x200 99 reg = <0xffffe400 0x200
79 0xffffe600 0x200>; 100 0xffffe600 0x200>;
101 clocks = <&ddrck>;
102 clock-names = "ddrck";
80 }; 103 };
81 104
82 pmc: pmc@fffffc00 { 105 pmc: pmc@fffffc00 {
83 compatible = "atmel,at91rm9200-pmc"; 106 compatible = "atmel,at91sam9g45-pmc";
84 reg = <0xfffffc00 0x100>; 107 reg = <0xfffffc00 0x100>;
108 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
109 interrupt-controller;
110 #address-cells = <1>;
111 #size-cells = <0>;
112 #interrupt-cells = <1>;
113
114 main_osc: main_osc {
115 compatible = "atmel,at91rm9200-clk-main-osc";
116 #clock-cells = <0>;
117 interrupts-extended = <&pmc AT91_PMC_MOSCS>;
118 clocks = <&main_xtal>;
119 };
120
121 main: mainck {
122 compatible = "atmel,at91rm9200-clk-main";
123 #clock-cells = <0>;
124 clocks = <&main_osc>;
125 };
126
127 plla: pllack {
128 compatible = "atmel,at91rm9200-clk-pll";
129 #clock-cells = <0>;
130 interrupts-extended = <&pmc AT91_PMC_LOCKA>;
131 clocks = <&main>;
132 reg = <0>;
133 atmel,clk-input-range = <2000000 32000000>;
134 #atmel,pll-clk-output-range-cells = <4>;
135 atmel,pll-clk-output-ranges = <745000000 800000000 0 0
136 695000000 750000000 1 0
137 645000000 700000000 2 0
138 595000000 650000000 3 0
139 545000000 600000000 0 1
140 495000000 555000000 1 1
141 445000000 500000000 2 1
142 400000000 450000000 3 1>;
143 };
144
145 plladiv: plladivck {
146 compatible = "atmel,at91sam9x5-clk-plldiv";
147 #clock-cells = <0>;
148 clocks = <&plla>;
149 };
150
151 utmi: utmick {
152 compatible = "atmel,at91sam9x5-clk-utmi";
153 #clock-cells = <0>;
154 interrupts-extended = <&pmc AT91_PMC_LOCKU>;
155 clocks = <&main>;
156 };
157
158 mck: masterck {
159 compatible = "atmel,at91rm9200-clk-master";
160 #clock-cells = <0>;
161 interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
162 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
163 atmel,clk-output-range = <0 133333333>;
164 atmel,clk-divisors = <1 2 4 3>;
165 };
166
167 usb: usbck {
168 compatible = "atmel,at91sam9x5-clk-usb";
169 #clock-cells = <0>;
170 clocks = <&plladiv>, <&utmi>;
171 };
172
173 prog: progck {
174 compatible = "atmel,at91sam9g45-clk-programmable";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 interrupt-parent = <&pmc>;
178 clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
179
180 prog0: prog0 {
181 #clock-cells = <0>;
182 reg = <0>;
183 interrupts = <AT91_PMC_PCKRDY(0)>;
184 };
185
186 prog1: prog1 {
187 #clock-cells = <0>;
188 reg = <1>;
189 interrupts = <AT91_PMC_PCKRDY(1)>;
190 };
191 };
192
193 systemck {
194 compatible = "atmel,at91rm9200-clk-system";
195 #address-cells = <1>;
196 #size-cells = <0>;
197
198 ddrck: ddrck {
199 #clock-cells = <0>;
200 reg = <2>;
201 clocks = <&mck>;
202 };
203
204 uhpck: uhpck {
205 #clock-cells = <0>;
206 reg = <6>;
207 clocks = <&usb>;
208 };
209
210 pck0: pck0 {
211 #clock-cells = <0>;
212 reg = <8>;
213 clocks = <&prog0>;
214 };
215
216 pck1: pck1 {
217 #clock-cells = <0>;
218 reg = <9>;
219 clocks = <&prog1>;
220 };
221 };
222
223 periphck {
224 compatible = "atmel,at91rm9200-clk-peripheral";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 clocks = <&mck>;
228
229 pioA_clk: pioA_clk {
230 #clock-cells = <0>;
231 reg = <2>;
232 };
233
234 pioB_clk: pioB_clk {
235 #clock-cells = <0>;
236 reg = <3>;
237 };
238
239 pioC_clk: pioC_clk {
240 #clock-cells = <0>;
241 reg = <4>;
242 };
243
244 pioDE_clk: pioDE_clk {
245 #clock-cells = <0>;
246 reg = <5>;
247 };
248
249 trng_clk: trng_clk {
250 #clock-cells = <0>;
251 reg = <6>;
252 };
253
254 usart0_clk: usart0_clk {
255 #clock-cells = <0>;
256 reg = <7>;
257 };
258
259 usart1_clk: usart1_clk {
260 #clock-cells = <0>;
261 reg = <8>;
262 };
263
264 usart2_clk: usart2_clk {
265 #clock-cells = <0>;
266 reg = <9>;
267 };
268
269 usart3_clk: usart3_clk {
270 #clock-cells = <0>;
271 reg = <10>;
272 };
273
274 mci0_clk: mci0_clk {
275 #clock-cells = <0>;
276 reg = <11>;
277 };
278
279 twi0_clk: twi0_clk {
280 #clock-cells = <0>;
281 reg = <12>;
282 };
283
284 twi1_clk: twi1_clk {
285 #clock-cells = <0>;
286 reg = <13>;
287 };
288
289 spi0_clk: spi0_clk {
290 #clock-cells = <0>;
291 reg = <14>;
292 };
293
294 spi1_clk: spi1_clk {
295 #clock-cells = <0>;
296 reg = <15>;
297 };
298
299 ssc0_clk: ssc0_clk {
300 #clock-cells = <0>;
301 reg = <16>;
302 };
303
304 ssc1_clk: ssc1_clk {
305 #clock-cells = <0>;
306 reg = <17>;
307 };
308
309 tcb0_clk: tcb0_clk {
310 #clock-cells = <0>;
311 reg = <18>;
312 };
313
314 pwm_clk: pwm_clk {
315 #clock-cells = <0>;
316 reg = <19>;
317 };
318
319 adc_clk: adc_clk {
320 #clock-cells = <0>;
321 reg = <20>;
322 };
323
324 dma0_clk: dma0_clk {
325 #clock-cells = <0>;
326 reg = <21>;
327 };
328
329 uhphs_clk: uhphs_clk {
330 #clock-cells = <0>;
331 reg = <22>;
332 };
333
334 lcd_clk: lcd_clk {
335 #clock-cells = <0>;
336 reg = <23>;
337 };
338
339 ac97_clk: ac97_clk {
340 #clock-cells = <0>;
341 reg = <24>;
342 };
343
344 macb0_clk: macb0_clk {
345 #clock-cells = <0>;
346 reg = <25>;
347 };
348
349 isi_clk: isi_clk {
350 #clock-cells = <0>;
351 reg = <26>;
352 };
353
354 udphs_clk: udphs_clk {
355 #clock-cells = <0>;
356 reg = <27>;
357 };
358
359 aestdessha_clk: aestdessha_clk {
360 #clock-cells = <0>;
361 reg = <28>;
362 };
363
364 mci1_clk: mci1_clk {
365 #clock-cells = <0>;
366 reg = <29>;
367 };
368
369 vdec_clk: vdec_clk {
370 #clock-cells = <0>;
371 reg = <30>;
372 };
373 };
85 }; 374 };
86 375
87 rstc@fffffd00 { 376 rstc@fffffd00 {
@@ -93,6 +382,7 @@
93 compatible = "atmel,at91sam9260-pit"; 382 compatible = "atmel,at91sam9260-pit";
94 reg = <0xfffffd30 0xf>; 383 reg = <0xfffffd30 0xf>;
95 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 384 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
385 clocks = <&mck>;
96 }; 386 };
97 387
98 388
@@ -105,12 +395,16 @@
105 compatible = "atmel,at91rm9200-tcb"; 395 compatible = "atmel,at91rm9200-tcb";
106 reg = <0xfff7c000 0x100>; 396 reg = <0xfff7c000 0x100>;
107 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 397 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
398 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
399 clock-names = "t0_clk", "t1_clk", "t2_clk";
108 }; 400 };
109 401
110 tcb1: timer@fffd4000 { 402 tcb1: timer@fffd4000 {
111 compatible = "atmel,at91rm9200-tcb"; 403 compatible = "atmel,at91rm9200-tcb";
112 reg = <0xfffd4000 0x100>; 404 reg = <0xfffd4000 0x100>;
113 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>; 405 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
406 clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
407 clock-names = "t0_clk", "t1_clk", "t2_clk";
114 }; 408 };
115 409
116 dma: dma-controller@ffffec00 { 410 dma: dma-controller@ffffec00 {
@@ -118,6 +412,8 @@
118 reg = <0xffffec00 0x200>; 412 reg = <0xffffec00 0x200>;
119 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; 413 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
120 #dma-cells = <2>; 414 #dma-cells = <2>;
415 clocks = <&dma0_clk>;
416 clock-names = "dma_clk";
121 }; 417 };
122 418
123 pinctrl@fffff200 { 419 pinctrl@fffff200 {
@@ -516,6 +812,7 @@
516 gpio-controller; 812 gpio-controller;
517 interrupt-controller; 813 interrupt-controller;
518 #interrupt-cells = <2>; 814 #interrupt-cells = <2>;
815 clocks = <&pioA_clk>;
519 }; 816 };
520 817
521 pioB: gpio@fffff400 { 818 pioB: gpio@fffff400 {
@@ -526,6 +823,7 @@
526 gpio-controller; 823 gpio-controller;
527 interrupt-controller; 824 interrupt-controller;
528 #interrupt-cells = <2>; 825 #interrupt-cells = <2>;
826 clocks = <&pioB_clk>;
529 }; 827 };
530 828
531 pioC: gpio@fffff600 { 829 pioC: gpio@fffff600 {
@@ -536,6 +834,7 @@
536 gpio-controller; 834 gpio-controller;
537 interrupt-controller; 835 interrupt-controller;
538 #interrupt-cells = <2>; 836 #interrupt-cells = <2>;
837 clocks = <&pioC_clk>;
539 }; 838 };
540 839
541 pioD: gpio@fffff800 { 840 pioD: gpio@fffff800 {
@@ -546,6 +845,7 @@
546 gpio-controller; 845 gpio-controller;
547 interrupt-controller; 846 interrupt-controller;
548 #interrupt-cells = <2>; 847 #interrupt-cells = <2>;
848 clocks = <&pioDE_clk>;
549 }; 849 };
550 850
551 pioE: gpio@fffffa00 { 851 pioE: gpio@fffffa00 {
@@ -556,6 +856,7 @@
556 gpio-controller; 856 gpio-controller;
557 interrupt-controller; 857 interrupt-controller;
558 #interrupt-cells = <2>; 858 #interrupt-cells = <2>;
859 clocks = <&pioDE_clk>;
559 }; 860 };
560 }; 861 };
561 862
@@ -565,6 +866,8 @@
565 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 866 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
566 pinctrl-names = "default"; 867 pinctrl-names = "default";
567 pinctrl-0 = <&pinctrl_dbgu>; 868 pinctrl-0 = <&pinctrl_dbgu>;
869 clocks = <&mck>;
870 clock-names = "usart";
568 status = "disabled"; 871 status = "disabled";
569 }; 872 };
570 873
@@ -576,6 +879,8 @@
576 atmel,use-dma-tx; 879 atmel,use-dma-tx;
577 pinctrl-names = "default"; 880 pinctrl-names = "default";
578 pinctrl-0 = <&pinctrl_usart0>; 881 pinctrl-0 = <&pinctrl_usart0>;
882 clocks = <&usart0_clk>;
883 clock-names = "usart";
579 status = "disabled"; 884 status = "disabled";
580 }; 885 };
581 886
@@ -587,6 +892,8 @@
587 atmel,use-dma-tx; 892 atmel,use-dma-tx;
588 pinctrl-names = "default"; 893 pinctrl-names = "default";
589 pinctrl-0 = <&pinctrl_usart1>; 894 pinctrl-0 = <&pinctrl_usart1>;
895 clocks = <&usart1_clk>;
896 clock-names = "usart";
590 status = "disabled"; 897 status = "disabled";
591 }; 898 };
592 899
@@ -598,6 +905,8 @@
598 atmel,use-dma-tx; 905 atmel,use-dma-tx;
599 pinctrl-names = "default"; 906 pinctrl-names = "default";
600 pinctrl-0 = <&pinctrl_usart2>; 907 pinctrl-0 = <&pinctrl_usart2>;
908 clocks = <&usart2_clk>;
909 clock-names = "usart";
601 status = "disabled"; 910 status = "disabled";
602 }; 911 };
603 912
@@ -609,6 +918,8 @@
609 atmel,use-dma-tx; 918 atmel,use-dma-tx;
610 pinctrl-names = "default"; 919 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_usart3>; 920 pinctrl-0 = <&pinctrl_usart3>;
921 clocks = <&usart3_clk>;
922 clock-names = "usart";
612 status = "disabled"; 923 status = "disabled";
613 }; 924 };
614 925
@@ -618,6 +929,8 @@
618 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; 929 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
619 pinctrl-names = "default"; 930 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_macb_rmii>; 931 pinctrl-0 = <&pinctrl_macb_rmii>;
932 clocks = <&macb0_clk>, <&macb0_clk>;
933 clock-names = "hclk", "pclk";
621 status = "disabled"; 934 status = "disabled";
622 }; 935 };
623 936
@@ -629,6 +942,7 @@
629 pinctrl-0 = <&pinctrl_i2c0>; 942 pinctrl-0 = <&pinctrl_i2c0>;
630 #address-cells = <1>; 943 #address-cells = <1>;
631 #size-cells = <0>; 944 #size-cells = <0>;
945 clocks = <&twi0_clk>;
632 status = "disabled"; 946 status = "disabled";
633 }; 947 };
634 948
@@ -640,6 +954,7 @@
640 pinctrl-0 = <&pinctrl_i2c1>; 954 pinctrl-0 = <&pinctrl_i2c1>;
641 #address-cells = <1>; 955 #address-cells = <1>;
642 #size-cells = <0>; 956 #size-cells = <0>;
957 clocks = <&twi1_clk>;
643 status = "disabled"; 958 status = "disabled";
644 }; 959 };
645 960
@@ -649,6 +964,8 @@
649 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 964 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
650 pinctrl-names = "default"; 965 pinctrl-names = "default";
651 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 966 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
967 clocks = <&ssc0_clk>;
968 clock-names = "pclk";
652 status = "disabled"; 969 status = "disabled";
653 }; 970 };
654 971
@@ -658,6 +975,8 @@
658 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>; 975 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
659 pinctrl-names = "default"; 976 pinctrl-names = "default";
660 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 977 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
978 clocks = <&ssc1_clk>;
979 clock-names = "pclk";
661 status = "disabled"; 980 status = "disabled";
662 }; 981 };
663 982
@@ -667,6 +986,8 @@
667 compatible = "atmel,at91sam9g45-adc"; 986 compatible = "atmel,at91sam9g45-adc";
668 reg = <0xfffb0000 0x100>; 987 reg = <0xfffb0000 0x100>;
669 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 988 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
989 clocks = <&adc_clk>, <&adc_op_clk>;
990 clock-names = "adc_clk", "adc_op_clk";
670 atmel,adc-channels-used = <0xff>; 991 atmel,adc-channels-used = <0xff>;
671 atmel,adc-vref = <3300>; 992 atmel,adc-vref = <3300>;
672 atmel,adc-startup-time = <40>; 993 atmel,adc-startup-time = <40>;
@@ -706,6 +1027,7 @@
706 reg = <0xfffb8000 0x300>; 1027 reg = <0xfffb8000 0x300>;
707 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>; 1028 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
708 #pwm-cells = <3>; 1029 #pwm-cells = <3>;
1030 clocks = <&pwm_clk>;
709 status = "disabled"; 1031 status = "disabled";
710 }; 1032 };
711 1033
@@ -718,6 +1040,8 @@
718 dma-names = "rxtx"; 1040 dma-names = "rxtx";
719 #address-cells = <1>; 1041 #address-cells = <1>;
720 #size-cells = <0>; 1042 #size-cells = <0>;
1043 clocks = <&mci0_clk>;
1044 clock-names = "mci_clk";
721 status = "disabled"; 1045 status = "disabled";
722 }; 1046 };
723 1047
@@ -730,6 +1054,8 @@
730 dma-names = "rxtx"; 1054 dma-names = "rxtx";
731 #address-cells = <1>; 1055 #address-cells = <1>;
732 #size-cells = <0>; 1056 #size-cells = <0>;
1057 clocks = <&mci1_clk>;
1058 clock-names = "mci_clk";
733 status = "disabled"; 1059 status = "disabled";
734 }; 1060 };
735 1061
@@ -752,6 +1078,8 @@
752 interrupts = <14 4 3>; 1078 interrupts = <14 4 3>;
753 pinctrl-names = "default"; 1079 pinctrl-names = "default";
754 pinctrl-0 = <&pinctrl_spi0>; 1080 pinctrl-0 = <&pinctrl_spi0>;
1081 clocks = <&spi0_clk>;
1082 clock-names = "spi_clk";
755 status = "disabled"; 1083 status = "disabled";
756 }; 1084 };
757 1085
@@ -763,6 +1091,8 @@
763 interrupts = <15 4 3>; 1091 interrupts = <15 4 3>;
764 pinctrl-names = "default"; 1092 pinctrl-names = "default";
765 pinctrl-0 = <&pinctrl_spi1>; 1093 pinctrl-0 = <&pinctrl_spi1>;
1094 clocks = <&spi1_clk>;
1095 clock-names = "spi_clk";
766 status = "disabled"; 1096 status = "disabled";
767 }; 1097 };
768 1098
@@ -773,6 +1103,8 @@
773 reg = <0x00600000 0x80000 1103 reg = <0x00600000 0x80000
774 0xfff78000 0x400>; 1104 0xfff78000 0x400>;
775 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>; 1105 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1106 clocks = <&udphs_clk>, <&utmi>;
1107 clock-names = "pclk", "hclk";
776 status = "disabled"; 1108 status = "disabled";
777 1109
778 ep0 { 1110 ep0 {
@@ -835,6 +1167,8 @@
835 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>; 1167 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
836 pinctrl-names = "default"; 1168 pinctrl-names = "default";
837 pinctrl-0 = <&pinctrl_fb>; 1169 pinctrl-0 = <&pinctrl_fb>;
1170 clocks = <&lcd_clk>, <&lcd_clk>;
1171 clock-names = "hclk", "lcdc_clk";
838 status = "disabled"; 1172 status = "disabled";
839 }; 1173 };
840 1174
@@ -861,6 +1195,9 @@
861 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 1195 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
862 reg = <0x00700000 0x100000>; 1196 reg = <0x00700000 0x100000>;
863 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1197 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1198 //TODO
1199 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1200 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
864 status = "disabled"; 1201 status = "disabled";
865 }; 1202 };
866 1203
@@ -868,6 +1205,9 @@
868 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 1205 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
869 reg = <0x00800000 0x100000>; 1206 reg = <0x00800000 0x100000>;
870 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>; 1207 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1208 //TODO
1209 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
1210 clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
871 status = "disabled"; 1211 status = "disabled";
872 }; 1212 };
873 }; 1213 };
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 9f5b0a674995..96ccc7de4f0a 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -31,6 +31,14 @@
31 compatible = "atmel,osc", "fixed-clock"; 31 compatible = "atmel,osc", "fixed-clock";
32 clock-frequency = <12000000>; 32 clock-frequency = <12000000>;
33 }; 33 };
34
35 slow_xtal {
36 clock-frequency = <32768>;
37 };
38
39 main_xtal {
40 clock-frequency = <12000000>;
41 };
34 }; 42 };
35 43
36 ahb { 44 ahb {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index b84bac5bada4..2bfac310dbec 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -50,16 +50,18 @@
50 reg = <0x20000000 0x10000000>; 50 reg = <0x20000000 0x10000000>;
51 }; 51 };
52 52
53 slow_xtal: slow_xtal { 53 clocks {
54 compatible = "fixed-clock"; 54 slow_xtal: slow_xtal {
55 #clock-cells = <0>; 55 compatible = "fixed-clock";
56 clock-frequency = <0>; 56 #clock-cells = <0>;
57 }; 57 clock-frequency = <0>;
58 };
58 59
59 main_xtal: main_xtal { 60 main_xtal: main_xtal {
60 compatible = "fixed-clock"; 61 compatible = "fixed-clock";
61 #clock-cells = <0>; 62 #clock-cells = <0>;
62 clock-frequency = <0>; 63 clock-frequency = <0>;
64 };
63 }; 65 };
64 66
65 ahb { 67 ahb {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index 64bbe46e4f90..83d723711ae1 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -21,14 +21,6 @@
21 reg = <0x20000000 0x8000000>; 21 reg = <0x20000000 0x8000000>;
22 }; 22 };
23 23
24 slow_xtal {
25 clock-frequency = <32768>;
26 };
27
28 main_xtal {
29 clock-frequency = <16000000>;
30 };
31
32 clocks { 24 clocks {
33 #address-cells = <1>; 25 #address-cells = <1>;
34 #size-cells = <1>; 26 #size-cells = <1>;
@@ -38,6 +30,14 @@
38 compatible = "atmel,osc", "fixed-clock"; 30 compatible = "atmel,osc", "fixed-clock";
39 clock-frequency = <16000000>; 31 clock-frequency = <16000000>;
40 }; 32 };
33
34 slow_xtal {
35 clock-frequency = <32768>;
36 };
37
38 main_xtal {
39 clock-frequency = <16000000>;
40 };
41 }; 41 };
42 42
43 ahb { 43 ahb {
@@ -56,6 +56,8 @@
56 wm8904: codec@1a { 56 wm8904: codec@1a {
57 compatible = "wm8904"; 57 compatible = "wm8904";
58 reg = <0x1a>; 58 reg = <0x1a>;
59 clocks = <&pck0>;
60 clock-names = "mclk";
59 }; 61 };
60 62
61 qt1070: keyboard@1b { 63 qt1070: keyboard@1b {
diff --git a/arch/arm/boot/dts/at91sam9rl.dtsi b/arch/arm/boot/dts/at91sam9rl.dtsi
index 1da183155eee..ab56c8b81dfa 100644
--- a/arch/arm/boot/dts/at91sam9rl.dtsi
+++ b/arch/arm/boot/dts/at91sam9rl.dtsi
@@ -50,19 +50,19 @@
50 reg = <0x20000000 0x04000000>; 50 reg = <0x20000000 0x04000000>;
51 }; 51 };
52 52
53 slow_xtal: slow_xtal { 53 clocks {
54 compatible = "fixed-clock"; 54 slow_xtal: slow_xtal {
55 #clock-cells = <0>; 55 compatible = "fixed-clock";
56 clock-frequency = <0>; 56 #clock-cells = <0>;
57 }; 57 clock-frequency = <0>;
58 };
58 59
59 main_xtal: main_xtal { 60 main_xtal: main_xtal {
60 compatible = "fixed-clock"; 61 compatible = "fixed-clock";
61 #clock-cells = <0>; 62 #clock-cells = <0>;
62 clock-frequency = <0>; 63 clock-frequency = <0>;
63 }; 64 };
64 65
65 clocks {
66 adc_op_clk: adc_op_clk{ 66 adc_op_clk: adc_op_clk{
67 compatible = "fixed-clock"; 67 compatible = "fixed-clock";
68 #clock-cells = <0>; 68 #clock-cells = <0>;
@@ -95,6 +95,7 @@
95 <0xffffe800 0x200>; 95 <0xffffe800 0x200>;
96 atmel,nand-addr-offset = <21>; 96 atmel,nand-addr-offset = <21>;
97 atmel,nand-cmd-offset = <22>; 97 atmel,nand-cmd-offset = <22>;
98 atmel,nand-has-dma;
98 pinctrl-names = "default"; 99 pinctrl-names = "default";
99 pinctrl-0 = <&pinctrl_nand>; 100 pinctrl-0 = <&pinctrl_nand>;
100 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>, 101 gpios = <&pioD 17 GPIO_ACTIVE_HIGH>,
@@ -348,6 +349,15 @@
348 }; 349 };
349 }; 350 };
350 351
352 dma0: dma-controller@ffffe600 {
353 compatible = "atmel,at91sam9rl-dma";
354 reg = <0xffffe600 0x200>;
355 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
356 #dma-cells = <2>;
357 clocks = <&dma0_clk>;
358 clock-names = "dma_clk";
359 };
360
351 ramc0: ramc@ffffea00 { 361 ramc0: ramc@ffffea00 {
352 compatible = "atmel,at91sam9260-sdramc"; 362 compatible = "atmel,at91sam9260-sdramc";
353 reg = <0xffffea00 0x200>; 363 reg = <0xffffea00 0x200>;
diff --git a/arch/arm/boot/dts/at91sam9rlek.dts b/arch/arm/boot/dts/at91sam9rlek.dts
index d4a010e40fe3..9be5b540eebf 100644
--- a/arch/arm/boot/dts/at91sam9rlek.dts
+++ b/arch/arm/boot/dts/at91sam9rlek.dts
@@ -20,15 +20,6 @@
20 reg = <0x20000000 0x4000000>; 20 reg = <0x20000000 0x4000000>;
21 }; 21 };
22 22
23
24 slow_xtal {
25 clock-frequency = <32768>;
26 };
27
28 main_xtal {
29 clock-frequency = <12000000>;
30 };
31
32 clocks { 23 clocks {
33 #address-cells = <1>; 24 #address-cells = <1>;
34 #size-cells = <1>; 25 #size-cells = <1>;
@@ -38,6 +29,14 @@
38 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
39 clock-frequency = <12000000>; 30 clock-frequency = <12000000>;
40 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <12000000>;
39 };
41 }; 40 };
42 41
43 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 2c0d6ea3ab41..e1a5c70b885c 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -52,22 +52,24 @@
52 reg = <0x20000000 0x10000000>; 52 reg = <0x20000000 0x10000000>;
53 }; 53 };
54 54
55 slow_xtal: slow_xtal { 55 clocks {
56 compatible = "fixed-clock"; 56 slow_xtal: slow_xtal {
57 #clock-cells = <0>; 57 compatible = "fixed-clock";
58 clock-frequency = <0>; 58 #clock-cells = <0>;
59 }; 59 clock-frequency = <0>;
60 };
60 61
61 main_xtal: main_xtal { 62 main_xtal: main_xtal {
62 compatible = "fixed-clock"; 63 compatible = "fixed-clock";
63 #clock-cells = <0>; 64 #clock-cells = <0>;
64 clock-frequency = <0>; 65 clock-frequency = <0>;
65 }; 66 };
66 67
67 adc_op_clk: adc_op_clk{ 68 adc_op_clk: adc_op_clk{
68 compatible = "fixed-clock"; 69 compatible = "fixed-clock";
69 #clock-cells = <0>; 70 #clock-cells = <0>;
70 clock-frequency = <5000000>; 71 clock-frequency = <5000000>;
72 };
71 }; 73 };
72 74
73 ahb { 75 ahb {
diff --git a/arch/arm/boot/dts/at91sam9x5cm.dtsi b/arch/arm/boot/dts/at91sam9x5cm.dtsi
index 8413e21192eb..229d6c24a9c4 100644
--- a/arch/arm/boot/dts/at91sam9x5cm.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5cm.dtsi
@@ -23,12 +23,14 @@
23 }; 23 };
24 }; 24 };
25 25
26 slow_xtal { 26 clocks {
27 clock-frequency = <32768>; 27 slow_xtal {
28 }; 28 clock-frequency = <32768>;
29 };
29 30
30 main_xtal { 31 main_xtal {
31 clock-frequency = <12000000>; 32 clock-frequency = <12000000>;
33 };
32 }; 34 };
33 35
34 ahb { 36 ahb {
diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi
index 6b05ae6d476f..2ddaa5136611 100644
--- a/arch/arm/boot/dts/bcm11351.dtsi
+++ b/arch/arm/boot/dts/bcm11351.dtsi
@@ -27,6 +27,25 @@
27 bootargs = "console=ttyS0,115200n8"; 27 bootargs = "console=ttyS0,115200n8";
28 }; 28 };
29 29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x3500417c>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 };
47 };
48
30 gic: interrupt-controller@3ff00100 { 49 gic: interrupt-controller@3ff00100 {
31 compatible = "arm,cortex-a9-gic"; 50 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>; 51 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi
index 8b366822bb43..2016b72a8fb7 100644
--- a/arch/arm/boot/dts/bcm21664.dtsi
+++ b/arch/arm/boot/dts/bcm21664.dtsi
@@ -27,6 +27,25 @@
27 bootargs = "console=ttyS0,115200n8"; 27 bootargs = "console=ttyS0,115200n8";
28 }; 28 };
29 29
30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
33 enable-method = "brcm,bcm11351-cpu-method";
34 secondary-boot-reg = <0x35004178>;
35
36 cpu0: cpu@0 {
37 device_type = "cpu";
38 compatible = "arm,cortex-a9";
39 reg = <0>;
40 };
41
42 cpu1: cpu@1 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a9";
45 reg = <1>;
46 };
47 };
48
30 gic: interrupt-controller@3ff00100 { 49 gic: interrupt-controller@3ff00100 {
31 compatible = "arm,cortex-a9-gic"; 50 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>; 51 #interrupt-cells = <3>;
diff --git a/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
new file mode 100644
index 000000000000..9eec2ac1112f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445-bcm97445svmb.dts
@@ -0,0 +1,14 @@
1/dts-v1/;
2#include "bcm7445.dtsi"
3
4/ {
5 model = "Broadcom STB (bcm7445), SVMB reference board";
6 compatible = "brcm,bcm7445", "brcm,brcmstb";
7
8 memory {
9 device_type = "memory";
10 reg = <0x00 0x00000000 0x00 0x40000000>,
11 <0x00 0x40000000 0x00 0x40000000>,
12 <0x00 0x80000000 0x00 0x40000000>;
13 };
14};
diff --git a/arch/arm/boot/dts/bcm7445.dtsi b/arch/arm/boot/dts/bcm7445.dtsi
new file mode 100644
index 000000000000..0ca0f4e523d0
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445.dtsi
@@ -0,0 +1,111 @@
1#include <dt-bindings/interrupt-controller/arm-gic.h>
2
3#include "skeleton.dtsi"
4
5/ {
6 #address-cells = <2>;
7 #size-cells = <2>;
8 model = "Broadcom STB (bcm7445)";
9 compatible = "brcm,bcm7445", "brcm,brcmstb";
10 interrupt-parent = <&gic>;
11
12 chosen {
13 bootargs = "console=ttyS0,115200 earlyprintk";
14 };
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "brcm,brahma-b15";
22 device_type = "cpu";
23 enable-method = "brcm,brahma-b15";
24 reg = <0>;
25 };
26
27 cpu@1 {
28 compatible = "brcm,brahma-b15";
29 device_type = "cpu";
30 enable-method = "brcm,brahma-b15";
31 reg = <1>;
32 };
33
34 cpu@2 {
35 compatible = "brcm,brahma-b15";
36 device_type = "cpu";
37 enable-method = "brcm,brahma-b15";
38 reg = <2>;
39 };
40
41 cpu@3 {
42 compatible = "brcm,brahma-b15";
43 device_type = "cpu";
44 enable-method = "brcm,brahma-b15";
45 reg = <3>;
46 };
47 };
48
49 gic: interrupt-controller@ffd00000 {
50 compatible = "brcm,brahma-b15-gic", "arm,cortex-a15-gic";
51 reg = <0x00 0xffd01000 0x00 0x1000>,
52 <0x00 0xffd02000 0x00 0x2000>,
53 <0x00 0xffd04000 0x00 0x2000>,
54 <0x00 0xffd06000 0x00 0x2000>;
55 interrupt-controller;
56 #interrupt-cells = <3>;
57 };
58
59 timer {
60 compatible = "arm,armv7-timer";
61 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
62 <GIC_PPI 14 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
63 <GIC_PPI 11 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 10 (GIC_CPU_MASK_RAW(15) | IRQ_TYPE_LEVEL_LOW)>;
65 };
66
67 rdb {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 ranges = <0 0x00 0xf0000000 0x1000000>;
72
73 serial@40ab00 {
74 compatible = "ns16550a";
75 reg = <0x40ab00 0x20>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
79 clock-frequency = <0x4d3f640>;
80 };
81
82 sun_top_ctrl: syscon@404000 {
83 compatible = "brcm,bcm7445-sun-top-ctrl",
84 "syscon";
85 reg = <0x404000 0x51c>;
86 };
87
88 hif_cpubiuctrl: syscon@3e2400 {
89 compatible = "brcm,bcm7445-hif-cpubiuctrl",
90 "syscon";
91 reg = <0x3e2400 0x5b4>;
92 };
93
94 hif_continuation: syscon@452000 {
95 compatible = "brcm,bcm7445-hif-continuation",
96 "syscon";
97 reg = <0x452000 0x100>;
98 };
99 };
100
101 smpboot {
102 compatible = "brcm,brcmstb-smpboot";
103 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
104 syscon-cont = <&hif_continuation>;
105 };
106
107 reboot {
108 compatible = "brcm,brcmstb-reboot";
109 syscon = <&sun_top_ctrl 0x304 0x308>;
110 };
111};
diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi
index 2477dac4d643..9d7c810ebd0b 100644
--- a/arch/arm/boot/dts/berlin2.dtsi
+++ b/arch/arm/boot/dts/berlin2.dtsi
@@ -22,6 +22,7 @@
22 cpus { 22 cpus {
23 #address-cells = <1>; 23 #address-cells = <1>;
24 #size-cells = <0>; 24 #size-cells = <0>;
25 enable-method = "marvell,berlin-smp";
25 26
26 cpu@0 { 27 cpu@0 {
27 compatible = "marvell,pj4b"; 28 compatible = "marvell,pj4b";
@@ -78,6 +79,11 @@
78 clocks = <&chip CLKID_TWD>; 79 clocks = <&chip CLKID_TWD>;
79 }; 80 };
80 81
82 cpu-ctrl@dd0000 {
83 compatible = "marvell,berlin-cpu-ctrl";
84 reg = <0xdd0000 0x10000>;
85 };
86
81 apb@e80000 { 87 apb@e80000 {
82 compatible = "simple-bus"; 88 compatible = "simple-bus";
83 #address-cells = <1>; 89 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
index 995150f93795..a357ce02a64e 100644
--- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
+++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts
@@ -34,6 +34,14 @@
34 status = "okay"; 34 status = "okay";
35}; 35};
36 36
37&i2c0 {
38 status = "okay";
39};
40
41&i2c2 {
42 status = "okay";
43};
44
37&uart0 { 45&uart0 {
38 status = "okay"; 46 status = "okay";
39}; 47};
diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi
index 635a16a64cb4..400c40fceccc 100644
--- a/arch/arm/boot/dts/berlin2q.dtsi
+++ b/arch/arm/boot/dts/berlin2q.dtsi
@@ -18,6 +18,7 @@
18 cpus { 18 cpus {
19 #address-cells = <1>; 19 #address-cells = <1>;
20 #size-cells = <0>; 20 #size-cells = <0>;
21 enable-method = "marvell,berlin-smp";
21 22
22 cpu@0 { 23 cpu@0 {
23 compatible = "arm,cortex-a9"; 24 compatible = "arm,cortex-a9";
@@ -90,6 +91,8 @@
90 compatible = "arm,pl310-cache"; 91 compatible = "arm,pl310-cache";
91 reg = <0xac0000 0x1000>; 92 reg = <0xac0000 0x1000>;
92 cache-level = <2>; 93 cache-level = <2>;
94 arm,data-latency = <2 2 2>;
95 arm,tag-latency = <2 2 2>;
93 }; 96 };
94 97
95 scu: snoop-control-unit@ad0000 { 98 scu: snoop-control-unit@ad0000 {
@@ -111,6 +114,11 @@
111 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
112 }; 115 };
113 116
117 cpu-ctrl@dd0000 {
118 compatible = "marvell,berlin-cpu-ctrl";
119 reg = <0xdd0000 0x10000>;
120 };
121
114 apb@e80000 { 122 apb@e80000 {
115 compatible = "simple-bus"; 123 compatible = "simple-bus";
116 #address-cells = <1>; 124 #address-cells = <1>;
@@ -191,6 +199,32 @@
191 }; 199 };
192 }; 200 };
193 201
202 i2c0: i2c@1400 {
203 compatible = "snps,designware-i2c";
204 #address-cells = <1>;
205 #size-cells = <0>;
206 reg = <0x1400 0x100>;
207 interrupt-parent = <&aic>;
208 interrupts = <4>;
209 clocks = <&chip CLKID_CFG>;
210 pinctrl-0 = <&twsi0_pmux>;
211 pinctrl-names = "default";
212 status = "disabled";
213 };
214
215 i2c1: i2c@1800 {
216 compatible = "snps,designware-i2c";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 reg = <0x1800 0x100>;
220 interrupt-parent = <&aic>;
221 interrupts = <5>;
222 clocks = <&chip CLKID_CFG>;
223 pinctrl-0 = <&twsi1_pmux>;
224 pinctrl-names = "default";
225 status = "disabled";
226 };
227
194 timer0: timer@2c00 { 228 timer0: timer@2c00 {
195 compatible = "snps,dw-apb-timer"; 229 compatible = "snps,dw-apb-timer";
196 reg = <0x2c00 0x14>; 230 reg = <0x2c00 0x14>;
@@ -301,6 +335,16 @@
301 reg = <0xea0000 0x400>, <0xdd0170 0x10>; 335 reg = <0xea0000 0x400>, <0xdd0170 0x10>;
302 clocks = <&refclk>; 336 clocks = <&refclk>;
303 clock-names = "refclk"; 337 clock-names = "refclk";
338
339 twsi0_pmux: twsi0-pmux {
340 groups = "G6";
341 function = "twsi0";
342 };
343
344 twsi1_pmux: twsi1-pmux {
345 groups = "G7";
346 function = "twsi1";
347 };
304 }; 348 };
305 349
306 apb@fc0000 { 350 apb@fc0000 {
@@ -311,6 +355,32 @@
311 ranges = <0 0xfc0000 0x10000>; 355 ranges = <0 0xfc0000 0x10000>;
312 interrupt-parent = <&sic>; 356 interrupt-parent = <&sic>;
313 357
358 i2c2: i2c@7000 {
359 compatible = "snps,designware-i2c";
360 #address-cells = <1>;
361 #size-cells = <0>;
362 reg = <0x7000 0x100>;
363 interrupt-parent = <&sic>;
364 interrupts = <6>;
365 clocks = <&refclk>;
366 pinctrl-0 = <&twsi2_pmux>;
367 pinctrl-names = "default";
368 status = "disabled";
369 };
370
371 i2c3: i2c@8000 {
372 compatible = "snps,designware-i2c";
373 #address-cells = <1>;
374 #size-cells = <0>;
375 reg = <0x8000 0x100>;
376 interrupt-parent = <&sic>;
377 interrupts = <7>;
378 clocks = <&refclk>;
379 pinctrl-0 = <&twsi3_pmux>;
380 pinctrl-names = "default";
381 status = "disabled";
382 };
383
314 uart0: uart@9000 { 384 uart0: uart@9000 {
315 compatible = "snps,dw-apb-uart"; 385 compatible = "snps,dw-apb-uart";
316 reg = <0x9000 0x100>; 386 reg = <0x9000 0x100>;
@@ -348,6 +418,16 @@
348 groups = "GSM14"; 418 groups = "GSM14";
349 function = "uart1"; 419 function = "uart1";
350 }; 420 };
421
422 twsi2_pmux: twsi2-pmux {
423 groups = "GSM13";
424 function = "twsi2";
425 };
426
427 twsi3_pmux: twsi3-pmux {
428 groups = "GSM14";
429 function = "twsi3";
430 };
351 }; 431 };
352 432
353 sic: interrupt-controller@e000 { 433 sic: interrupt-controller@e000 {
diff --git a/arch/arm/boot/dts/cros-ec-keyboard.dtsi b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
new file mode 100644
index 000000000000..9c7fb0acae79
--- /dev/null
+++ b/arch/arm/boot/dts/cros-ec-keyboard.dtsi
@@ -0,0 +1,105 @@
1/*
2 * Keyboard dts fragment for devices that use cros-ec-keyboard
3 *
4 * Copyright (c) 2014 Google, Inc
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <dt-bindings/input/input.h>
12
13&cros_ec {
14 keyboard-controller {
15 compatible = "google,cros-ec-keyb";
16 keypad,num-rows = <8>;
17 keypad,num-columns = <13>;
18 google,needs-ghost-filter;
19
20 linux,keymap = <
21 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA)
22 MATRIX_KEY(0x00, 0x02, KEY_F1)
23 MATRIX_KEY(0x00, 0x03, KEY_B)
24 MATRIX_KEY(0x00, 0x04, KEY_F10)
25 MATRIX_KEY(0x00, 0x06, KEY_N)
26 MATRIX_KEY(0x00, 0x08, KEY_EQUAL)
27 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT)
28
29 MATRIX_KEY(0x01, 0x01, KEY_ESC)
30 MATRIX_KEY(0x01, 0x02, KEY_F4)
31 MATRIX_KEY(0x01, 0x03, KEY_G)
32 MATRIX_KEY(0x01, 0x04, KEY_F7)
33 MATRIX_KEY(0x01, 0x06, KEY_H)
34 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE)
35 MATRIX_KEY(0x01, 0x09, KEY_F9)
36 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE)
37
38 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
39 MATRIX_KEY(0x02, 0x01, KEY_TAB)
40 MATRIX_KEY(0x02, 0x02, KEY_F3)
41 MATRIX_KEY(0x02, 0x03, KEY_T)
42 MATRIX_KEY(0x02, 0x04, KEY_F6)
43 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
44 MATRIX_KEY(0x02, 0x06, KEY_Y)
45 MATRIX_KEY(0x02, 0x07, KEY_102ND)
46 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
47 MATRIX_KEY(0x02, 0x09, KEY_F8)
48
49 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
50 MATRIX_KEY(0x03, 0x02, KEY_F2)
51 MATRIX_KEY(0x03, 0x03, KEY_5)
52 MATRIX_KEY(0x03, 0x04, KEY_F5)
53 MATRIX_KEY(0x03, 0x06, KEY_6)
54 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
55 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
56
57 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
58 MATRIX_KEY(0x04, 0x01, KEY_A)
59 MATRIX_KEY(0x04, 0x02, KEY_D)
60 MATRIX_KEY(0x04, 0x03, KEY_F)
61 MATRIX_KEY(0x04, 0x04, KEY_S)
62 MATRIX_KEY(0x04, 0x05, KEY_K)
63 MATRIX_KEY(0x04, 0x06, KEY_J)
64 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
65 MATRIX_KEY(0x04, 0x09, KEY_L)
66 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
67 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
68
69 MATRIX_KEY(0x05, 0x01, KEY_Z)
70 MATRIX_KEY(0x05, 0x02, KEY_C)
71 MATRIX_KEY(0x05, 0x03, KEY_V)
72 MATRIX_KEY(0x05, 0x04, KEY_X)
73 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
74 MATRIX_KEY(0x05, 0x06, KEY_M)
75 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
76 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
77 MATRIX_KEY(0x05, 0x09, KEY_DOT)
78 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
79
80 MATRIX_KEY(0x06, 0x01, KEY_1)
81 MATRIX_KEY(0x06, 0x02, KEY_3)
82 MATRIX_KEY(0x06, 0x03, KEY_4)
83 MATRIX_KEY(0x06, 0x04, KEY_2)
84 MATRIX_KEY(0x06, 0x05, KEY_8)
85 MATRIX_KEY(0x06, 0x06, KEY_7)
86 MATRIX_KEY(0x06, 0x08, KEY_0)
87 MATRIX_KEY(0x06, 0x09, KEY_9)
88 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
89 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
90 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
91
92 MATRIX_KEY(0x07, 0x01, KEY_Q)
93 MATRIX_KEY(0x07, 0x02, KEY_E)
94 MATRIX_KEY(0x07, 0x03, KEY_R)
95 MATRIX_KEY(0x07, 0x04, KEY_W)
96 MATRIX_KEY(0x07, 0x05, KEY_I)
97 MATRIX_KEY(0x07, 0x06, KEY_U)
98 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
99 MATRIX_KEY(0x07, 0x08, KEY_P)
100 MATRIX_KEY(0x07, 0x09, KEY_O)
101 MATRIX_KEY(0x07, 0x0b, KEY_UP)
102 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
103 >;
104 };
105};
diff --git a/arch/arm/boot/dts/dove-cubox-es.dts b/arch/arm/boot/dts/dove-cubox-es.dts
new file mode 100644
index 000000000000..e28ef056dd17
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox-es.dts
@@ -0,0 +1,12 @@
1#include "dove-cubox.dts"
2
3/ {
4 model = "SolidRun CuBox (Engineering Sample)";
5 compatible = "solidrun,cubox-es", "solidrun,cubox", "marvell,dove";
6};
7
8&sdio0 {
9 /* sdio0 card detect is connected to wrong pin on CuBox ES */
10 cd-gpios = <&gpio0 12 1>;
11 pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>;
12};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
index 7a70f4ca502a..aae7efc09b0b 100644
--- a/arch/arm/boot/dts/dove-cubox.dts
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -111,9 +111,6 @@
111 111
112&sdio0 { 112&sdio0 {
113 status = "okay"; 113 status = "okay";
114 /* sdio0 card detect is connected to wrong pin on CuBox */
115 cd-gpios = <&gpio0 12 1>;
116 pinctrl-0 = <&pmx_sdio0 &pmx_gpio_12>;
117}; 114};
118 115
119&spi0 { 116&spi0 {
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 3b891dd20993..a5441d5482a6 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -630,6 +630,20 @@
630 reg = <0xe8400 0x0c>; 630 reg = <0xe8400 0x0c>;
631 ngpios = <8>; 631 ngpios = <8>;
632 }; 632 };
633
634 lcd1: lcd-controller@810000 {
635 compatible = "marvell,dove-lcd";
636 reg = <0x810000 0x1000>;
637 interrupts = <46>;
638 status = "disabled";
639 };
640
641 lcd0: lcd-controller@820000 {
642 compatible = "marvell,dove-lcd";
643 reg = <0x820000 0x1000>;
644 interrupts = <47>;
645 status = "disabled";
646 };
633 }; 647 };
634 }; 648 };
635}; 649};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 83089540e324..50f8022905a1 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -496,3 +496,11 @@
496 }; 496 };
497 }; 497 };
498}; 498};
499
500&usb2_phy1 {
501 phy-supply = <&ldousb_reg>;
502};
503
504&usb2_phy2 {
505 phy-supply = <&ldousb_reg>;
506};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 0686b1e9e7f9..97f603c4483d 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -12,6 +12,9 @@
12 12
13#include "skeleton.dtsi" 13#include "skeleton.dtsi"
14 14
15#define MAX_SOURCES 400
16#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
17
15/ { 18/ {
16 #address-cells = <1>; 19 #address-cells = <1>;
17 #size-cells = <1>; 20 #size-cells = <1>;
@@ -45,6 +48,7 @@
45 compatible = "arm,cortex-a15-gic"; 48 compatible = "arm,cortex-a15-gic";
46 interrupt-controller; 49 interrupt-controller;
47 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
51 arm,routable-irqs = <192>;
48 reg = <0x48211000 0x1000>, 52 reg = <0x48211000 0x1000>,
49 <0x48212000 0x1000>, 53 <0x48212000 0x1000>,
50 <0x48214000 0x2000>, 54 <0x48214000 0x2000>,
@@ -79,8 +83,8 @@
79 ti,hwmods = "l3_main_1", "l3_main_2"; 83 ti,hwmods = "l3_main_1", "l3_main_2";
80 reg = <0x44000000 0x1000000>, 84 reg = <0x44000000 0x1000000>,
81 <0x45000000 0x1000>; 85 <0x45000000 0x1000>;
82 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
84 88
85 prm: prm@4ae06000 { 89 prm: prm@4ae06000 {
86 compatible = "ti,dra7-prm"; 90 compatible = "ti,dra7-prm";
@@ -95,6 +99,75 @@
95 }; 99 };
96 }; 100 };
97 101
102 axi@0 {
103 compatible = "simple-bus";
104 #size-cells = <1>;
105 #address-cells = <1>;
106 ranges = <0x51000000 0x51000000 0x3000
107 0x0 0x20000000 0x10000000>;
108 pcie@51000000 {
109 compatible = "ti,dra7-pcie";
110 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
111 reg-names = "rc_dbics", "ti_conf", "config";
112 interrupts = <0 232 0x4>, <0 233 0x4>;
113 #address-cells = <3>;
114 #size-cells = <2>;
115 device_type = "pci";
116 ranges = <0x81000000 0 0 0x03000 0 0x00010000
117 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
118 #interrupt-cells = <1>;
119 num-lanes = <1>;
120 ti,hwmods = "pcie1";
121 phys = <&pcie1_phy>;
122 phy-names = "pcie-phy0";
123 interrupt-map-mask = <0 0 0 7>;
124 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
125 <0 0 0 2 &pcie1_intc 2>,
126 <0 0 0 3 &pcie1_intc 3>,
127 <0 0 0 4 &pcie1_intc 4>;
128 pcie1_intc: interrupt-controller {
129 interrupt-controller;
130 #address-cells = <0>;
131 #interrupt-cells = <1>;
132 };
133 };
134 };
135
136 axi@1 {
137 compatible = "simple-bus";
138 #size-cells = <1>;
139 #address-cells = <1>;
140 ranges = <0x51800000 0x51800000 0x3000
141 0x0 0x30000000 0x10000000>;
142 status = "disabled";
143 pcie@51000000 {
144 compatible = "ti,dra7-pcie";
145 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
146 reg-names = "rc_dbics", "ti_conf", "config";
147 interrupts = <0 355 0x4>, <0 356 0x4>;
148 #address-cells = <3>;
149 #size-cells = <2>;
150 device_type = "pci";
151 ranges = <0x81000000 0 0 0x03000 0 0x00010000
152 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
153 #interrupt-cells = <1>;
154 num-lanes = <1>;
155 ti,hwmods = "pcie2";
156 phys = <&pcie2_phy>;
157 phy-names = "pcie-phy0";
158 interrupt-map-mask = <0 0 0 7>;
159 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
160 <0 0 0 2 &pcie2_intc 2>,
161 <0 0 0 3 &pcie2_intc 3>,
162 <0 0 0 4 &pcie2_intc 4>;
163 pcie2_intc: interrupt-controller {
164 interrupt-controller;
165 #address-cells = <0>;
166 #interrupt-cells = <1>;
167 };
168 };
169 };
170
98 cm_core_aon: cm_core_aon@4a005000 { 171 cm_core_aon: cm_core_aon@4a005000 {
99 compatible = "ti,dra7-cm-core-aon"; 172 compatible = "ti,dra7-cm-core-aon";
100 reg = <0x4a005000 0x2000>; 173 reg = <0x4a005000 0x2000>;
@@ -155,10 +228,10 @@
155 sdma: dma-controller@4a056000 { 228 sdma: dma-controller@4a056000 {
156 compatible = "ti,omap4430-sdma"; 229 compatible = "ti,omap4430-sdma";
157 reg = <0x4a056000 0x1000>; 230 reg = <0x4a056000 0x1000>;
158 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 231 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 234 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
162 #dma-cells = <1>; 235 #dma-cells = <1>;
163 #dma-channels = <32>; 236 #dma-channels = <32>;
164 #dma-requests = <127>; 237 #dma-requests = <127>;
@@ -167,7 +240,7 @@
167 gpio1: gpio@4ae10000 { 240 gpio1: gpio@4ae10000 {
168 compatible = "ti,omap4-gpio"; 241 compatible = "ti,omap4-gpio";
169 reg = <0x4ae10000 0x200>; 242 reg = <0x4ae10000 0x200>;
170 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 243 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
171 ti,hwmods = "gpio1"; 244 ti,hwmods = "gpio1";
172 gpio-controller; 245 gpio-controller;
173 #gpio-cells = <2>; 246 #gpio-cells = <2>;
@@ -178,7 +251,7 @@
178 gpio2: gpio@48055000 { 251 gpio2: gpio@48055000 {
179 compatible = "ti,omap4-gpio"; 252 compatible = "ti,omap4-gpio";
180 reg = <0x48055000 0x200>; 253 reg = <0x48055000 0x200>;
181 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 254 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "gpio2"; 255 ti,hwmods = "gpio2";
183 gpio-controller; 256 gpio-controller;
184 #gpio-cells = <2>; 257 #gpio-cells = <2>;
@@ -189,7 +262,7 @@
189 gpio3: gpio@48057000 { 262 gpio3: gpio@48057000 {
190 compatible = "ti,omap4-gpio"; 263 compatible = "ti,omap4-gpio";
191 reg = <0x48057000 0x200>; 264 reg = <0x48057000 0x200>;
192 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 265 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "gpio3"; 266 ti,hwmods = "gpio3";
194 gpio-controller; 267 gpio-controller;
195 #gpio-cells = <2>; 268 #gpio-cells = <2>;
@@ -200,7 +273,7 @@
200 gpio4: gpio@48059000 { 273 gpio4: gpio@48059000 {
201 compatible = "ti,omap4-gpio"; 274 compatible = "ti,omap4-gpio";
202 reg = <0x48059000 0x200>; 275 reg = <0x48059000 0x200>;
203 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 276 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "gpio4"; 277 ti,hwmods = "gpio4";
205 gpio-controller; 278 gpio-controller;
206 #gpio-cells = <2>; 279 #gpio-cells = <2>;
@@ -211,7 +284,7 @@
211 gpio5: gpio@4805b000 { 284 gpio5: gpio@4805b000 {
212 compatible = "ti,omap4-gpio"; 285 compatible = "ti,omap4-gpio";
213 reg = <0x4805b000 0x200>; 286 reg = <0x4805b000 0x200>;
214 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 287 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "gpio5"; 288 ti,hwmods = "gpio5";
216 gpio-controller; 289 gpio-controller;
217 #gpio-cells = <2>; 290 #gpio-cells = <2>;
@@ -222,7 +295,7 @@
222 gpio6: gpio@4805d000 { 295 gpio6: gpio@4805d000 {
223 compatible = "ti,omap4-gpio"; 296 compatible = "ti,omap4-gpio";
224 reg = <0x4805d000 0x200>; 297 reg = <0x4805d000 0x200>;
225 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 298 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
226 ti,hwmods = "gpio6"; 299 ti,hwmods = "gpio6";
227 gpio-controller; 300 gpio-controller;
228 #gpio-cells = <2>; 301 #gpio-cells = <2>;
@@ -233,7 +306,7 @@
233 gpio7: gpio@48051000 { 306 gpio7: gpio@48051000 {
234 compatible = "ti,omap4-gpio"; 307 compatible = "ti,omap4-gpio";
235 reg = <0x48051000 0x200>; 308 reg = <0x48051000 0x200>;
236 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 309 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
237 ti,hwmods = "gpio7"; 310 ti,hwmods = "gpio7";
238 gpio-controller; 311 gpio-controller;
239 #gpio-cells = <2>; 312 #gpio-cells = <2>;
@@ -244,7 +317,7 @@
244 gpio8: gpio@48053000 { 317 gpio8: gpio@48053000 {
245 compatible = "ti,omap4-gpio"; 318 compatible = "ti,omap4-gpio";
246 reg = <0x48053000 0x200>; 319 reg = <0x48053000 0x200>;
247 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 320 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
248 ti,hwmods = "gpio8"; 321 ti,hwmods = "gpio8";
249 gpio-controller; 322 gpio-controller;
250 #gpio-cells = <2>; 323 #gpio-cells = <2>;
@@ -255,7 +328,7 @@
255 uart1: serial@4806a000 { 328 uart1: serial@4806a000 {
256 compatible = "ti,omap4-uart"; 329 compatible = "ti,omap4-uart";
257 reg = <0x4806a000 0x100>; 330 reg = <0x4806a000 0x100>;
258 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 331 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
259 ti,hwmods = "uart1"; 332 ti,hwmods = "uart1";
260 clock-frequency = <48000000>; 333 clock-frequency = <48000000>;
261 status = "disabled"; 334 status = "disabled";
@@ -264,7 +337,7 @@
264 uart2: serial@4806c000 { 337 uart2: serial@4806c000 {
265 compatible = "ti,omap4-uart"; 338 compatible = "ti,omap4-uart";
266 reg = <0x4806c000 0x100>; 339 reg = <0x4806c000 0x100>;
267 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
268 ti,hwmods = "uart2"; 341 ti,hwmods = "uart2";
269 clock-frequency = <48000000>; 342 clock-frequency = <48000000>;
270 status = "disabled"; 343 status = "disabled";
@@ -273,7 +346,7 @@
273 uart3: serial@48020000 { 346 uart3: serial@48020000 {
274 compatible = "ti,omap4-uart"; 347 compatible = "ti,omap4-uart";
275 reg = <0x48020000 0x100>; 348 reg = <0x48020000 0x100>;
276 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 349 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
277 ti,hwmods = "uart3"; 350 ti,hwmods = "uart3";
278 clock-frequency = <48000000>; 351 clock-frequency = <48000000>;
279 status = "disabled"; 352 status = "disabled";
@@ -282,7 +355,7 @@
282 uart4: serial@4806e000 { 355 uart4: serial@4806e000 {
283 compatible = "ti,omap4-uart"; 356 compatible = "ti,omap4-uart";
284 reg = <0x4806e000 0x100>; 357 reg = <0x4806e000 0x100>;
285 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
286 ti,hwmods = "uart4"; 359 ti,hwmods = "uart4";
287 clock-frequency = <48000000>; 360 clock-frequency = <48000000>;
288 status = "disabled"; 361 status = "disabled";
@@ -291,7 +364,7 @@
291 uart5: serial@48066000 { 364 uart5: serial@48066000 {
292 compatible = "ti,omap4-uart"; 365 compatible = "ti,omap4-uart";
293 reg = <0x48066000 0x100>; 366 reg = <0x48066000 0x100>;
294 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 367 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "uart5"; 368 ti,hwmods = "uart5";
296 clock-frequency = <48000000>; 369 clock-frequency = <48000000>;
297 status = "disabled"; 370 status = "disabled";
@@ -300,7 +373,7 @@
300 uart6: serial@48068000 { 373 uart6: serial@48068000 {
301 compatible = "ti,omap4-uart"; 374 compatible = "ti,omap4-uart";
302 reg = <0x48068000 0x100>; 375 reg = <0x48068000 0x100>;
303 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 376 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
304 ti,hwmods = "uart6"; 377 ti,hwmods = "uart6";
305 clock-frequency = <48000000>; 378 clock-frequency = <48000000>;
306 status = "disabled"; 379 status = "disabled";
@@ -309,6 +382,7 @@
309 uart7: serial@48420000 { 382 uart7: serial@48420000 {
310 compatible = "ti,omap4-uart"; 383 compatible = "ti,omap4-uart";
311 reg = <0x48420000 0x100>; 384 reg = <0x48420000 0x100>;
385 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
312 ti,hwmods = "uart7"; 386 ti,hwmods = "uart7";
313 clock-frequency = <48000000>; 387 clock-frequency = <48000000>;
314 status = "disabled"; 388 status = "disabled";
@@ -317,6 +391,7 @@
317 uart8: serial@48422000 { 391 uart8: serial@48422000 {
318 compatible = "ti,omap4-uart"; 392 compatible = "ti,omap4-uart";
319 reg = <0x48422000 0x100>; 393 reg = <0x48422000 0x100>;
394 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
320 ti,hwmods = "uart8"; 395 ti,hwmods = "uart8";
321 clock-frequency = <48000000>; 396 clock-frequency = <48000000>;
322 status = "disabled"; 397 status = "disabled";
@@ -325,6 +400,7 @@
325 uart9: serial@48424000 { 400 uart9: serial@48424000 {
326 compatible = "ti,omap4-uart"; 401 compatible = "ti,omap4-uart";
327 reg = <0x48424000 0x100>; 402 reg = <0x48424000 0x100>;
403 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
328 ti,hwmods = "uart9"; 404 ti,hwmods = "uart9";
329 clock-frequency = <48000000>; 405 clock-frequency = <48000000>;
330 status = "disabled"; 406 status = "disabled";
@@ -333,6 +409,7 @@
333 uart10: serial@4ae2b000 { 409 uart10: serial@4ae2b000 {
334 compatible = "ti,omap4-uart"; 410 compatible = "ti,omap4-uart";
335 reg = <0x4ae2b000 0x100>; 411 reg = <0x4ae2b000 0x100>;
412 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
336 ti,hwmods = "uart10"; 413 ti,hwmods = "uart10";
337 clock-frequency = <48000000>; 414 clock-frequency = <48000000>;
338 status = "disabled"; 415 status = "disabled";
@@ -458,7 +535,7 @@
458 timer1: timer@4ae18000 { 535 timer1: timer@4ae18000 {
459 compatible = "ti,omap5430-timer"; 536 compatible = "ti,omap5430-timer";
460 reg = <0x4ae18000 0x80>; 537 reg = <0x4ae18000 0x80>;
461 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 538 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
462 ti,hwmods = "timer1"; 539 ti,hwmods = "timer1";
463 ti,timer-alwon; 540 ti,timer-alwon;
464 }; 541 };
@@ -466,28 +543,28 @@
466 timer2: timer@48032000 { 543 timer2: timer@48032000 {
467 compatible = "ti,omap5430-timer"; 544 compatible = "ti,omap5430-timer";
468 reg = <0x48032000 0x80>; 545 reg = <0x48032000 0x80>;
469 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 546 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
470 ti,hwmods = "timer2"; 547 ti,hwmods = "timer2";
471 }; 548 };
472 549
473 timer3: timer@48034000 { 550 timer3: timer@48034000 {
474 compatible = "ti,omap5430-timer"; 551 compatible = "ti,omap5430-timer";
475 reg = <0x48034000 0x80>; 552 reg = <0x48034000 0x80>;
476 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 553 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
477 ti,hwmods = "timer3"; 554 ti,hwmods = "timer3";
478 }; 555 };
479 556
480 timer4: timer@48036000 { 557 timer4: timer@48036000 {
481 compatible = "ti,omap5430-timer"; 558 compatible = "ti,omap5430-timer";
482 reg = <0x48036000 0x80>; 559 reg = <0x48036000 0x80>;
483 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 560 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
484 ti,hwmods = "timer4"; 561 ti,hwmods = "timer4";
485 }; 562 };
486 563
487 timer5: timer@48820000 { 564 timer5: timer@48820000 {
488 compatible = "ti,omap5430-timer"; 565 compatible = "ti,omap5430-timer";
489 reg = <0x48820000 0x80>; 566 reg = <0x48820000 0x80>;
490 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 567 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
491 ti,hwmods = "timer5"; 568 ti,hwmods = "timer5";
492 ti,timer-dsp; 569 ti,timer-dsp;
493 }; 570 };
@@ -495,7 +572,7 @@
495 timer6: timer@48822000 { 572 timer6: timer@48822000 {
496 compatible = "ti,omap5430-timer"; 573 compatible = "ti,omap5430-timer";
497 reg = <0x48822000 0x80>; 574 reg = <0x48822000 0x80>;
498 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 575 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
499 ti,hwmods = "timer6"; 576 ti,hwmods = "timer6";
500 ti,timer-dsp; 577 ti,timer-dsp;
501 ti,timer-pwm; 578 ti,timer-pwm;
@@ -504,7 +581,7 @@
504 timer7: timer@48824000 { 581 timer7: timer@48824000 {
505 compatible = "ti,omap5430-timer"; 582 compatible = "ti,omap5430-timer";
506 reg = <0x48824000 0x80>; 583 reg = <0x48824000 0x80>;
507 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 584 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
508 ti,hwmods = "timer7"; 585 ti,hwmods = "timer7";
509 ti,timer-dsp; 586 ti,timer-dsp;
510 }; 587 };
@@ -512,7 +589,7 @@
512 timer8: timer@48826000 { 589 timer8: timer@48826000 {
513 compatible = "ti,omap5430-timer"; 590 compatible = "ti,omap5430-timer";
514 reg = <0x48826000 0x80>; 591 reg = <0x48826000 0x80>;
515 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 592 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
516 ti,hwmods = "timer8"; 593 ti,hwmods = "timer8";
517 ti,timer-dsp; 594 ti,timer-dsp;
518 ti,timer-pwm; 595 ti,timer-pwm;
@@ -521,21 +598,21 @@
521 timer9: timer@4803e000 { 598 timer9: timer@4803e000 {
522 compatible = "ti,omap5430-timer"; 599 compatible = "ti,omap5430-timer";
523 reg = <0x4803e000 0x80>; 600 reg = <0x4803e000 0x80>;
524 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 601 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
525 ti,hwmods = "timer9"; 602 ti,hwmods = "timer9";
526 }; 603 };
527 604
528 timer10: timer@48086000 { 605 timer10: timer@48086000 {
529 compatible = "ti,omap5430-timer"; 606 compatible = "ti,omap5430-timer";
530 reg = <0x48086000 0x80>; 607 reg = <0x48086000 0x80>;
531 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 608 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
532 ti,hwmods = "timer10"; 609 ti,hwmods = "timer10";
533 }; 610 };
534 611
535 timer11: timer@48088000 { 612 timer11: timer@48088000 {
536 compatible = "ti,omap5430-timer"; 613 compatible = "ti,omap5430-timer";
537 reg = <0x48088000 0x80>; 614 reg = <0x48088000 0x80>;
538 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 615 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
539 ti,hwmods = "timer11"; 616 ti,hwmods = "timer11";
540 ti,timer-pwm; 617 ti,timer-pwm;
541 }; 618 };
@@ -543,6 +620,7 @@
543 timer13: timer@48828000 { 620 timer13: timer@48828000 {
544 compatible = "ti,omap5430-timer"; 621 compatible = "ti,omap5430-timer";
545 reg = <0x48828000 0x80>; 622 reg = <0x48828000 0x80>;
623 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
546 ti,hwmods = "timer13"; 624 ti,hwmods = "timer13";
547 status = "disabled"; 625 status = "disabled";
548 }; 626 };
@@ -550,6 +628,7 @@
550 timer14: timer@4882a000 { 628 timer14: timer@4882a000 {
551 compatible = "ti,omap5430-timer"; 629 compatible = "ti,omap5430-timer";
552 reg = <0x4882a000 0x80>; 630 reg = <0x4882a000 0x80>;
631 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
553 ti,hwmods = "timer14"; 632 ti,hwmods = "timer14";
554 status = "disabled"; 633 status = "disabled";
555 }; 634 };
@@ -557,6 +636,7 @@
557 timer15: timer@4882c000 { 636 timer15: timer@4882c000 {
558 compatible = "ti,omap5430-timer"; 637 compatible = "ti,omap5430-timer";
559 reg = <0x4882c000 0x80>; 638 reg = <0x4882c000 0x80>;
639 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
560 ti,hwmods = "timer15"; 640 ti,hwmods = "timer15";
561 status = "disabled"; 641 status = "disabled";
562 }; 642 };
@@ -564,6 +644,7 @@
564 timer16: timer@4882e000 { 644 timer16: timer@4882e000 {
565 compatible = "ti,omap5430-timer"; 645 compatible = "ti,omap5430-timer";
566 reg = <0x4882e000 0x80>; 646 reg = <0x4882e000 0x80>;
647 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
567 ti,hwmods = "timer16"; 648 ti,hwmods = "timer16";
568 status = "disabled"; 649 status = "disabled";
569 }; 650 };
@@ -571,7 +652,7 @@
571 wdt2: wdt@4ae14000 { 652 wdt2: wdt@4ae14000 {
572 compatible = "ti,omap4-wdt"; 653 compatible = "ti,omap4-wdt";
573 reg = <0x4ae14000 0x80>; 654 reg = <0x4ae14000 0x80>;
574 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 655 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
575 ti,hwmods = "wd_timer2"; 656 ti,hwmods = "wd_timer2";
576 }; 657 };
577 658
@@ -585,14 +666,14 @@
585 dmm@4e000000 { 666 dmm@4e000000 {
586 compatible = "ti,omap5-dmm"; 667 compatible = "ti,omap5-dmm";
587 reg = <0x4e000000 0x800>; 668 reg = <0x4e000000 0x800>;
588 interrupts = <0 113 0x4>; 669 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
589 ti,hwmods = "dmm"; 670 ti,hwmods = "dmm";
590 }; 671 };
591 672
592 i2c1: i2c@48070000 { 673 i2c1: i2c@48070000 {
593 compatible = "ti,omap4-i2c"; 674 compatible = "ti,omap4-i2c";
594 reg = <0x48070000 0x100>; 675 reg = <0x48070000 0x100>;
595 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 676 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
596 #address-cells = <1>; 677 #address-cells = <1>;
597 #size-cells = <0>; 678 #size-cells = <0>;
598 ti,hwmods = "i2c1"; 679 ti,hwmods = "i2c1";
@@ -602,7 +683,7 @@
602 i2c2: i2c@48072000 { 683 i2c2: i2c@48072000 {
603 compatible = "ti,omap4-i2c"; 684 compatible = "ti,omap4-i2c";
604 reg = <0x48072000 0x100>; 685 reg = <0x48072000 0x100>;
605 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 686 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
606 #address-cells = <1>; 687 #address-cells = <1>;
607 #size-cells = <0>; 688 #size-cells = <0>;
608 ti,hwmods = "i2c2"; 689 ti,hwmods = "i2c2";
@@ -612,7 +693,7 @@
612 i2c3: i2c@48060000 { 693 i2c3: i2c@48060000 {
613 compatible = "ti,omap4-i2c"; 694 compatible = "ti,omap4-i2c";
614 reg = <0x48060000 0x100>; 695 reg = <0x48060000 0x100>;
615 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 696 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
616 #address-cells = <1>; 697 #address-cells = <1>;
617 #size-cells = <0>; 698 #size-cells = <0>;
618 ti,hwmods = "i2c3"; 699 ti,hwmods = "i2c3";
@@ -622,7 +703,7 @@
622 i2c4: i2c@4807a000 { 703 i2c4: i2c@4807a000 {
623 compatible = "ti,omap4-i2c"; 704 compatible = "ti,omap4-i2c";
624 reg = <0x4807a000 0x100>; 705 reg = <0x4807a000 0x100>;
625 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 706 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
626 #address-cells = <1>; 707 #address-cells = <1>;
627 #size-cells = <0>; 708 #size-cells = <0>;
628 ti,hwmods = "i2c4"; 709 ti,hwmods = "i2c4";
@@ -632,7 +713,7 @@
632 i2c5: i2c@4807c000 { 713 i2c5: i2c@4807c000 {
633 compatible = "ti,omap4-i2c"; 714 compatible = "ti,omap4-i2c";
634 reg = <0x4807c000 0x100>; 715 reg = <0x4807c000 0x100>;
635 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 716 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
636 #address-cells = <1>; 717 #address-cells = <1>;
637 #size-cells = <0>; 718 #size-cells = <0>;
638 ti,hwmods = "i2c5"; 719 ti,hwmods = "i2c5";
@@ -642,7 +723,7 @@
642 mmc1: mmc@4809c000 { 723 mmc1: mmc@4809c000 {
643 compatible = "ti,omap4-hsmmc"; 724 compatible = "ti,omap4-hsmmc";
644 reg = <0x4809c000 0x400>; 725 reg = <0x4809c000 0x400>;
645 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 726 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
646 ti,hwmods = "mmc1"; 727 ti,hwmods = "mmc1";
647 ti,dual-volt; 728 ti,dual-volt;
648 ti,needs-special-reset; 729 ti,needs-special-reset;
@@ -655,7 +736,7 @@
655 mmc2: mmc@480b4000 { 736 mmc2: mmc@480b4000 {
656 compatible = "ti,omap4-hsmmc"; 737 compatible = "ti,omap4-hsmmc";
657 reg = <0x480b4000 0x400>; 738 reg = <0x480b4000 0x400>;
658 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 739 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
659 ti,hwmods = "mmc2"; 740 ti,hwmods = "mmc2";
660 ti,needs-special-reset; 741 ti,needs-special-reset;
661 dmas = <&sdma 47>, <&sdma 48>; 742 dmas = <&sdma 47>, <&sdma 48>;
@@ -666,7 +747,7 @@
666 mmc3: mmc@480ad000 { 747 mmc3: mmc@480ad000 {
667 compatible = "ti,omap4-hsmmc"; 748 compatible = "ti,omap4-hsmmc";
668 reg = <0x480ad000 0x400>; 749 reg = <0x480ad000 0x400>;
669 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 750 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
670 ti,hwmods = "mmc3"; 751 ti,hwmods = "mmc3";
671 ti,needs-special-reset; 752 ti,needs-special-reset;
672 dmas = <&sdma 77>, <&sdma 78>; 753 dmas = <&sdma 77>, <&sdma 78>;
@@ -677,7 +758,7 @@
677 mmc4: mmc@480d1000 { 758 mmc4: mmc@480d1000 {
678 compatible = "ti,omap4-hsmmc"; 759 compatible = "ti,omap4-hsmmc";
679 reg = <0x480d1000 0x400>; 760 reg = <0x480d1000 0x400>;
680 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 761 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
681 ti,hwmods = "mmc4"; 762 ti,hwmods = "mmc4";
682 ti,needs-special-reset; 763 ti,needs-special-reset;
683 dmas = <&sdma 57>, <&sdma 58>; 764 dmas = <&sdma 57>, <&sdma 58>;
@@ -820,7 +901,7 @@
820 mcspi1: spi@48098000 { 901 mcspi1: spi@48098000 {
821 compatible = "ti,omap4-mcspi"; 902 compatible = "ti,omap4-mcspi";
822 reg = <0x48098000 0x200>; 903 reg = <0x48098000 0x200>;
823 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 904 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
824 #address-cells = <1>; 905 #address-cells = <1>;
825 #size-cells = <0>; 906 #size-cells = <0>;
826 ti,hwmods = "mcspi1"; 907 ti,hwmods = "mcspi1";
@@ -841,7 +922,7 @@
841 mcspi2: spi@4809a000 { 922 mcspi2: spi@4809a000 {
842 compatible = "ti,omap4-mcspi"; 923 compatible = "ti,omap4-mcspi";
843 reg = <0x4809a000 0x200>; 924 reg = <0x4809a000 0x200>;
844 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 925 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
845 #address-cells = <1>; 926 #address-cells = <1>;
846 #size-cells = <0>; 927 #size-cells = <0>;
847 ti,hwmods = "mcspi2"; 928 ti,hwmods = "mcspi2";
@@ -857,7 +938,7 @@
857 mcspi3: spi@480b8000 { 938 mcspi3: spi@480b8000 {
858 compatible = "ti,omap4-mcspi"; 939 compatible = "ti,omap4-mcspi";
859 reg = <0x480b8000 0x200>; 940 reg = <0x480b8000 0x200>;
860 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 941 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
861 #address-cells = <1>; 942 #address-cells = <1>;
862 #size-cells = <0>; 943 #size-cells = <0>;
863 ti,hwmods = "mcspi3"; 944 ti,hwmods = "mcspi3";
@@ -870,7 +951,7 @@
870 mcspi4: spi@480ba000 { 951 mcspi4: spi@480ba000 {
871 compatible = "ti,omap4-mcspi"; 952 compatible = "ti,omap4-mcspi";
872 reg = <0x480ba000 0x200>; 953 reg = <0x480ba000 0x200>;
873 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 954 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
874 #address-cells = <1>; 955 #address-cells = <1>;
875 #size-cells = <0>; 956 #size-cells = <0>;
876 ti,hwmods = "mcspi4"; 957 ti,hwmods = "mcspi4";
@@ -890,6 +971,7 @@
890 clocks = <&qspi_gfclk_div>; 971 clocks = <&qspi_gfclk_div>;
891 clock-names = "fck"; 972 clock-names = "fck";
892 num-cs = <4>; 973 num-cs = <4>;
974 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
893 status = "disabled"; 975 status = "disabled";
894 }; 976 };
895 977
@@ -920,18 +1002,76 @@
920 clock-names = "sysclk"; 1002 clock-names = "sysclk";
921 #phy-cells = <0>; 1003 #phy-cells = <0>;
922 }; 1004 };
1005
1006 pcie1_phy: pciephy@4a094000 {
1007 compatible = "ti,phy-pipe3-pcie";
1008 reg = <0x4a094000 0x80>, /* phy_rx */
1009 <0x4a094400 0x64>; /* phy_tx */
1010 reg-names = "phy_rx", "phy_tx";
1011 ctrl-module = <&omap_control_pcie1phy>;
1012 clocks = <&dpll_pcie_ref_ck>,
1013 <&dpll_pcie_ref_m2ldo_ck>,
1014 <&optfclk_pciephy1_32khz>,
1015 <&optfclk_pciephy1_clk>,
1016 <&optfclk_pciephy1_div_clk>,
1017 <&optfclk_pciephy_div>;
1018 clock-names = "dpll_ref", "dpll_ref_m2",
1019 "wkupclk", "refclk",
1020 "div-clk", "phy-div";
1021 #phy-cells = <0>;
1022 id = <1>;
1023 ti,hwmods = "pcie1-phy";
1024 };
1025
1026 pcie2_phy: pciephy@4a095000 {
1027 compatible = "ti,phy-pipe3-pcie";
1028 reg = <0x4a095000 0x80>, /* phy_rx */
1029 <0x4a095400 0x64>; /* phy_tx */
1030 reg-names = "phy_rx", "phy_tx";
1031 ctrl-module = <&omap_control_pcie2phy>;
1032 clocks = <&dpll_pcie_ref_ck>,
1033 <&dpll_pcie_ref_m2ldo_ck>,
1034 <&optfclk_pciephy2_32khz>,
1035 <&optfclk_pciephy2_clk>,
1036 <&optfclk_pciephy2_div_clk>,
1037 <&optfclk_pciephy_div>;
1038 clock-names = "dpll_ref", "dpll_ref_m2",
1039 "wkupclk", "refclk",
1040 "div-clk", "phy-div";
1041 #phy-cells = <0>;
1042 ti,hwmods = "pcie2-phy";
1043 id = <2>;
1044 status = "disabled";
1045 };
923 }; 1046 };
924 1047
925 sata: sata@4a141100 { 1048 sata: sata@4a141100 {
926 compatible = "snps,dwc-ahci"; 1049 compatible = "snps,dwc-ahci";
927 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1050 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
928 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1051 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
929 phys = <&sata_phy>; 1052 phys = <&sata_phy>;
930 phy-names = "sata-phy"; 1053 phy-names = "sata-phy";
931 clocks = <&sata_ref_clk>; 1054 clocks = <&sata_ref_clk>;
932 ti,hwmods = "sata"; 1055 ti,hwmods = "sata";
933 }; 1056 };
934 1057
1058 omap_control_pcie1phy: control-phy@0x4a003c40 {
1059 compatible = "ti,control-phy-pcie";
1060 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1061 reg-names = "power", "control_sma", "pcie_pcs";
1062 clocks = <&sys_clkin1>;
1063 clock-names = "sysclk";
1064 };
1065
1066 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1067 compatible = "ti,control-phy-pcie";
1068 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1069 reg-names = "power", "control_sma", "pcie_pcs";
1070 clocks = <&sys_clkin1>;
1071 clock-names = "sysclk";
1072 status = "disabled";
1073 };
1074
935 omap_control_usb2phy1: control-phy@4a002300 { 1075 omap_control_usb2phy1: control-phy@4a002300 {
936 compatible = "ti,control-phy-usb2"; 1076 compatible = "ti,control-phy-usb2";
937 reg = <0x4a002300 0x4>; 1077 reg = <0x4a002300 0x4>;
@@ -1002,7 +1142,7 @@
1002 compatible = "ti,dwc3"; 1142 compatible = "ti,dwc3";
1003 ti,hwmods = "usb_otg_ss1"; 1143 ti,hwmods = "usb_otg_ss1";
1004 reg = <0x48880000 0x10000>; 1144 reg = <0x48880000 0x10000>;
1005 interrupts = <0 77 4>; 1145 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1006 #address-cells = <1>; 1146 #address-cells = <1>;
1007 #size-cells = <1>; 1147 #size-cells = <1>;
1008 utmi-mode = <2>; 1148 utmi-mode = <2>;
@@ -1010,7 +1150,7 @@
1010 usb1: usb@48890000 { 1150 usb1: usb@48890000 {
1011 compatible = "snps,dwc3"; 1151 compatible = "snps,dwc3";
1012 reg = <0x48890000 0x17000>; 1152 reg = <0x48890000 0x17000>;
1013 interrupts = <0 76 4>; 1153 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1014 phys = <&usb2_phy1>, <&usb3_phy1>; 1154 phys = <&usb2_phy1>, <&usb3_phy1>;
1015 phy-names = "usb2-phy", "usb3-phy"; 1155 phy-names = "usb2-phy", "usb3-phy";
1016 tx-fifo-resize; 1156 tx-fifo-resize;
@@ -1023,7 +1163,7 @@
1023 compatible = "ti,dwc3"; 1163 compatible = "ti,dwc3";
1024 ti,hwmods = "usb_otg_ss2"; 1164 ti,hwmods = "usb_otg_ss2";
1025 reg = <0x488c0000 0x10000>; 1165 reg = <0x488c0000 0x10000>;
1026 interrupts = <0 92 4>; 1166 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1027 #address-cells = <1>; 1167 #address-cells = <1>;
1028 #size-cells = <1>; 1168 #size-cells = <1>;
1029 utmi-mode = <2>; 1169 utmi-mode = <2>;
@@ -1031,7 +1171,7 @@
1031 usb2: usb@488d0000 { 1171 usb2: usb@488d0000 {
1032 compatible = "snps,dwc3"; 1172 compatible = "snps,dwc3";
1033 reg = <0x488d0000 0x17000>; 1173 reg = <0x488d0000 0x17000>;
1034 interrupts = <0 78 4>; 1174 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1035 phys = <&usb2_phy2>; 1175 phys = <&usb2_phy2>;
1036 phy-names = "usb2-phy"; 1176 phy-names = "usb2-phy";
1037 tx-fifo-resize; 1177 tx-fifo-resize;
@@ -1045,7 +1185,7 @@
1045 compatible = "ti,dwc3"; 1185 compatible = "ti,dwc3";
1046 ti,hwmods = "usb_otg_ss3"; 1186 ti,hwmods = "usb_otg_ss3";
1047 reg = <0x48900000 0x10000>; 1187 reg = <0x48900000 0x10000>;
1048 /* interrupts = <0 TBD 4>; */ 1188 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1049 #address-cells = <1>; 1189 #address-cells = <1>;
1050 #size-cells = <1>; 1190 #size-cells = <1>;
1051 utmi-mode = <2>; 1191 utmi-mode = <2>;
@@ -1054,7 +1194,7 @@
1054 usb3: usb@48910000 { 1194 usb3: usb@48910000 {
1055 compatible = "snps,dwc3"; 1195 compatible = "snps,dwc3";
1056 reg = <0x48910000 0x17000>; 1196 reg = <0x48910000 0x17000>;
1057 /* interrupts = <0 93 4>; */ 1197 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1058 tx-fifo-resize; 1198 tx-fifo-resize;
1059 maximum-speed = "high-speed"; 1199 maximum-speed = "high-speed";
1060 dr_mode = "otg"; 1200 dr_mode = "otg";
@@ -1065,7 +1205,7 @@
1065 compatible = "ti,dwc3"; 1205 compatible = "ti,dwc3";
1066 ti,hwmods = "usb_otg_ss4"; 1206 ti,hwmods = "usb_otg_ss4";
1067 reg = <0x48940000 0x10000>; 1207 reg = <0x48940000 0x10000>;
1068 /* interrupts = <0 TBD 4>; */ 1208 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
1069 #address-cells = <1>; 1209 #address-cells = <1>;
1070 #size-cells = <1>; 1210 #size-cells = <1>;
1071 utmi-mode = <2>; 1211 utmi-mode = <2>;
@@ -1074,7 +1214,7 @@
1074 usb4: usb@48950000 { 1214 usb4: usb@48950000 {
1075 compatible = "snps,dwc3"; 1215 compatible = "snps,dwc3";
1076 reg = <0x48950000 0x17000>; 1216 reg = <0x48950000 0x17000>;
1077 /* interrupts = <0 TBD 4>; */ 1217 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
1078 tx-fifo-resize; 1218 tx-fifo-resize;
1079 maximum-speed = "high-speed"; 1219 maximum-speed = "high-speed";
1080 dr_mode = "otg"; 1220 dr_mode = "otg";
@@ -1084,7 +1224,7 @@
1084 elm: elm@48078000 { 1224 elm: elm@48078000 {
1085 compatible = "ti,am3352-elm"; 1225 compatible = "ti,am3352-elm";
1086 reg = <0x48078000 0xfc0>; /* device IO registers */ 1226 reg = <0x48078000 0xfc0>; /* device IO registers */
1087 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1227 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1088 ti,hwmods = "elm"; 1228 ti,hwmods = "elm";
1089 status = "disabled"; 1229 status = "disabled";
1090 }; 1230 };
@@ -1093,7 +1233,7 @@
1093 compatible = "ti,am3352-gpmc"; 1233 compatible = "ti,am3352-gpmc";
1094 ti,hwmods = "gpmc"; 1234 ti,hwmods = "gpmc";
1095 reg = <0x50000000 0x37c>; /* device IO registers */ 1235 reg = <0x50000000 0x37c>; /* device IO registers */
1096 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1236 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1097 gpmc,num-cs = <8>; 1237 gpmc,num-cs = <8>;
1098 gpmc,num-waitpins = <2>; 1238 gpmc,num-waitpins = <2>;
1099 #address-cells = <2>; 1239 #address-cells = <2>;
@@ -1111,6 +1251,17 @@
1111 clock-names = "fck"; 1251 clock-names = "fck";
1112 status = "disabled"; 1252 status = "disabled";
1113 }; 1253 };
1254
1255 crossbar_mpu: crossbar@4a020000 {
1256 compatible = "ti,irq-crossbar";
1257 reg = <0x4a002a48 0x130>;
1258 ti,max-irqs = <160>;
1259 ti,max-crossbar-sources = <MAX_SOURCES>;
1260 ti,reg-size = <2>;
1261 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1262 ti,irqs-skip = <10 133 139 140>;
1263 ti,irqs-safe-map = <0>;
1264 };
1114 }; 1265 };
1115}; 1266};
1116 1267
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index dc7a292fe939..2c05b3f017fa 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1154,7 +1154,7 @@
1154 1154
1155 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 { 1155 apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1156 compatible = "ti,mux-clock"; 1156 compatible = "ti,mux-clock";
1157 clocks = <&dpll_pcie_ref_ck>, <&pciesref_acs_clk_ck>; 1157 clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1158 #clock-cells = <0>; 1158 #clock-cells = <0>;
1159 reg = <0x021c 0x4>; 1159 reg = <0x021c 0x4>;
1160 ti,bit-shift = <7>; 1160 ti,bit-shift = <7>;
@@ -1167,16 +1167,33 @@
1167 reg = <0x021c>, <0x0220>; 1167 reg = <0x021c>, <0x0220>;
1168 }; 1168 };
1169 1169
1170 optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
1171 compatible = "ti,gate-clock";
1172 clocks = <&sys_32k_ck>;
1173 #clock-cells = <0>;
1174 reg = <0x13b0>;
1175 ti,bit-shift = <8>;
1176 };
1177
1178 optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
1179 compatible = "ti,gate-clock";
1180 clocks = <&sys_32k_ck>;
1181 #clock-cells = <0>;
1182 reg = <0x13b8>;
1183 ti,bit-shift = <8>;
1184 };
1185
1170 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c { 1186 optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1171 compatible = "ti,divider-clock"; 1187 compatible = "ti,divider-clock";
1172 clocks = <&apll_pcie_ck>; 1188 clocks = <&apll_pcie_ck>;
1173 #clock-cells = <0>; 1189 #clock-cells = <0>;
1174 reg = <0x021c>; 1190 reg = <0x021c>;
1191 ti,dividers = <2>, <1>;
1175 ti,bit-shift = <8>; 1192 ti,bit-shift = <8>;
1176 ti,max-div = <2>; 1193 ti,max-div = <2>;
1177 }; 1194 };
1178 1195
1179 optfclk_pciephy_clk: optfclk_pciephy_clk@4a0093b0 { 1196 optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
1180 compatible = "ti,gate-clock"; 1197 compatible = "ti,gate-clock";
1181 clocks = <&apll_pcie_ck>; 1198 clocks = <&apll_pcie_ck>;
1182 #clock-cells = <0>; 1199 #clock-cells = <0>;
@@ -1184,7 +1201,15 @@
1184 ti,bit-shift = <9>; 1201 ti,bit-shift = <9>;
1185 }; 1202 };
1186 1203
1187 optfclk_pciephy_div_clk: optfclk_pciephy_div_clk@4a0093b0 { 1204 optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
1205 compatible = "ti,gate-clock";
1206 clocks = <&apll_pcie_ck>;
1207 #clock-cells = <0>;
1208 reg = <0x13b8>;
1209 ti,bit-shift = <9>;
1210 };
1211
1212 optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
1188 compatible = "ti,gate-clock"; 1213 compatible = "ti,gate-clock";
1189 clocks = <&optfclk_pciephy_div>; 1214 clocks = <&optfclk_pciephy_div>;
1190 #clock-cells = <0>; 1215 #clock-cells = <0>;
@@ -1192,6 +1217,14 @@
1192 ti,bit-shift = <10>; 1217 ti,bit-shift = <10>;
1193 }; 1218 };
1194 1219
1220 optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
1221 compatible = "ti,gate-clock";
1222 clocks = <&optfclk_pciephy_div>;
1223 #clock-cells = <0>;
1224 reg = <0x13b8>;
1225 ti,bit-shift = <10>;
1226 };
1227
1195 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo { 1228 apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1196 #clock-cells = <0>; 1229 #clock-cells = <0>;
1197 compatible = "fixed-factor-clock"; 1230 compatible = "fixed-factor-clock";
diff --git a/arch/arm/boot/dts/ethernut5.dts b/arch/arm/boot/dts/ethernut5.dts
index 143b6d25bc80..8f941c2db7c6 100644
--- a/arch/arm/boot/dts/ethernut5.dts
+++ b/arch/arm/boot/dts/ethernut5.dts
@@ -20,6 +20,16 @@
20 reg = <0x20000000 0x08000000>; 20 reg = <0x20000000 0x08000000>;
21 }; 21 };
22 22
23 clocks {
24 slow_xtal {
25 clock-frequency = <32768>;
26 };
27
28 main_xtal {
29 clock-frequency = <18432000>;
30 };
31 };
32
23 ahb { 33 ahb {
24 apb { 34 apb {
25 dbgu: serial@fffff200 { 35 dbgu: serial@fffff200 {
diff --git a/arch/arm/boot/dts/evk-pro3.dts b/arch/arm/boot/dts/evk-pro3.dts
index 4d829685fdfb..f72969efe6d7 100644
--- a/arch/arm/boot/dts/evk-pro3.dts
+++ b/arch/arm/boot/dts/evk-pro3.dts
@@ -15,6 +15,12 @@
15 model = "Telit EVK-PRO3 for Telit GE863-PRO3"; 15 model = "Telit EVK-PRO3 for Telit GE863-PRO3";
16 compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9"; 16 compatible = "telit,evk-pro3", "atmel,at91sam9260", "atmel,at91sam9";
17 17
18 clocks {
19 slow_xtal {
20 clock-frequency = <32768>;
21 };
22 };
23
18 ahb { 24 ahb {
19 apb { 25 apb {
20 macb0: ethernet@fffc4000 { 26 macb0: ethernet@fffc4000 {
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index 94d59983fc2d..1d52de6370d5 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -170,6 +170,15 @@
170 status = "disabled"; 170 status = "disabled";
171 }; 171 };
172 172
173 tmu: tmu@100C0000 {
174 compatible = "samsung,exynos3250-tmu";
175 reg = <0x100C0000 0x100>;
176 interrupts = <0 216 0>;
177 clocks = <&cmu CLK_TMU_APBIF>;
178 clock-names = "tmu_apbif";
179 status = "disabled";
180 };
181
173 gic: interrupt-controller@10481000 { 182 gic: interrupt-controller@10481000 {
174 compatible = "arm,cortex-a15-gic"; 183 compatible = "arm,cortex-a15-gic";
175 #interrupt-cells = <3>; 184 #interrupt-cells = <3>;
@@ -197,7 +206,6 @@
197 206
198 wakeup-interrupt-controller { 207 wakeup-interrupt-controller {
199 compatible = "samsung,exynos4210-wakeup-eint"; 208 compatible = "samsung,exynos4210-wakeup-eint";
200 interrupt-parent = <&gic>;
201 interrupts = <0 48 0>; 209 interrupts = <0 48 0>;
202 }; 210 };
203 }; 211 };
@@ -236,7 +244,6 @@
236 compatible = "arm,amba-bus"; 244 compatible = "arm,amba-bus";
237 #address-cells = <1>; 245 #address-cells = <1>;
238 #size-cells = <1>; 246 #size-cells = <1>;
239 interrupt-parent = <&gic>;
240 ranges; 247 ranges;
241 248
242 pdma0: pdma@12680000 { 249 pdma0: pdma@12680000 {
@@ -280,6 +287,8 @@
280 interrupts = <0 109 0>; 287 interrupts = <0 109 0>;
281 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>; 288 clocks = <&cmu CLK_UART0>, <&cmu CLK_SCLK_UART0>;
282 clock-names = "uart", "clk_uart_baud0"; 289 clock-names = "uart", "clk_uart_baud0";
290 pinctrl-names = "default";
291 pinctrl-0 = <&uart0_data &uart0_fctl>;
283 status = "disabled"; 292 status = "disabled";
284 }; 293 };
285 294
@@ -289,6 +298,8 @@
289 interrupts = <0 110 0>; 298 interrupts = <0 110 0>;
290 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>; 299 clocks = <&cmu CLK_UART1>, <&cmu CLK_SCLK_UART1>;
291 clock-names = "uart", "clk_uart_baud0"; 300 clock-names = "uart", "clk_uart_baud0";
301 pinctrl-names = "default";
302 pinctrl-0 = <&uart1_data>;
292 status = "disabled"; 303 status = "disabled";
293 }; 304 };
294 305
@@ -428,6 +439,19 @@
428 status = "disabled"; 439 status = "disabled";
429 }; 440 };
430 441
442 i2s2: i2s@13970000 {
443 compatible = "samsung,s3c6410-i2s";
444 reg = <0x13970000 0x100>;
445 interrupts = <0 126 0>;
446 clocks = <&cmu CLK_I2S>, <&cmu CLK_SCLK_I2S>;
447 clock-names = "iis", "i2s_opclk0";
448 dmas = <&pdma0 14>, <&pdma0 13>;
449 dma-names = "tx", "rx";
450 pinctrl-0 = <&i2s2_bus>;
451 pinctrl-names = "default";
452 status = "disabled";
453 };
454
431 pwm: pwm@139D0000 { 455 pwm: pwm@139D0000 {
432 compatible = "samsung,exynos4210-pwm"; 456 compatible = "samsung,exynos4210-pwm";
433 reg = <0x139D0000 0x1000>; 457 reg = <0x139D0000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi
index bd3b9b537976..e0278ecbc816 100644
--- a/arch/arm/boot/dts/exynos4.dtsi
+++ b/arch/arm/boot/dts/exynos4.dtsi
@@ -127,6 +127,12 @@
127 reg = <0x10440000 0x1000>; 127 reg = <0x10440000 0x1000>;
128 }; 128 };
129 129
130 pmu {
131 compatible = "arm,cortex-a9-pmu";
132 interrupt-parent = <&combiner>;
133 interrupts = <2 2>, <3 2>;
134 };
135
130 sys_reg: syscon@10010000 { 136 sys_reg: syscon@10010000 {
131 compatible = "samsung,exynos4-sysreg", "syscon"; 137 compatible = "samsung,exynos4-sysreg", "syscon";
132 reg = <0x10010000 0x400>; 138 reg = <0x10010000 0x400>;
@@ -326,6 +332,23 @@
326 clocks = <&clock CLK_USB_HOST>; 332 clocks = <&clock CLK_USB_HOST>;
327 clock-names = "usbhost"; 333 clock-names = "usbhost";
328 status = "disabled"; 334 status = "disabled";
335 #address-cells = <1>;
336 #size-cells = <0>;
337 port@0 {
338 reg = <0>;
339 phys = <&exynos_usbphy 1>;
340 status = "disabled";
341 };
342 port@1 {
343 reg = <1>;
344 phys = <&exynos_usbphy 2>;
345 status = "disabled";
346 };
347 port@2 {
348 reg = <2>;
349 phys = <&exynos_usbphy 3>;
350 status = "disabled";
351 };
329 }; 352 };
330 353
331 ohci@12590000 { 354 ohci@12590000 {
@@ -335,6 +358,13 @@
335 clocks = <&clock CLK_USB_HOST>; 358 clocks = <&clock CLK_USB_HOST>;
336 clock-names = "usbhost"; 359 clock-names = "usbhost";
337 status = "disabled"; 360 status = "disabled";
361 #address-cells = <1>;
362 #size-cells = <0>;
363 port@0 {
364 reg = <0>;
365 phys = <&exynos_usbphy 1>;
366 status = "disabled";
367 };
338 }; 368 };
339 369
340 i2s1: i2s@13960000 { 370 i2s1: i2s@13960000 {
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 97ea7a9b1f62..807bb5bf91fc 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -103,12 +103,6 @@
103 #clock-cells = <1>; 103 #clock-cells = <1>;
104 }; 104 };
105 105
106 pmu {
107 compatible = "arm,cortex-a9-pmu";
108 interrupt-parent = <&combiner>;
109 interrupts = <2 2>, <3 2>;
110 };
111
112 pinctrl_0: pinctrl@11400000 { 106 pinctrl_0: pinctrl@11400000 {
113 compatible = "samsung,exynos4210-pinctrl"; 107 compatible = "samsung,exynos4210-pinctrl";
114 reg = <0x11400000 0x1000>; 108 reg = <0x11400000 0x1000>;
diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
new file mode 100644
index 000000000000..6d6d23c83d30
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi
@@ -0,0 +1,371 @@
1/*
2 * Common definition for Hardkernel's Exynos4412 based ODROID-X/X2/U2/U3 boards
3 * device tree source
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8*/
9
10#include <dt-bindings/input/input.h>
11#include "exynos4412.dtsi"
12
13/ {
14 firmware@0204F000 {
15 compatible = "samsung,secure-firmware";
16 reg = <0x0204F000 0x1000>;
17 };
18
19 gpio_keys {
20 compatible = "gpio-keys";
21 pinctrl-names = "default";
22 pinctrl-0 = <&gpio_power_key>;
23
24 power_key {
25 interrupt-parent = <&gpx1>;
26 interrupts = <3 0>;
27 gpios = <&gpx1 3 1>;
28 linux,code = <KEY_POWER>;
29 label = "power key";
30 debounce-interval = <10>;
31 gpio-key,wakeup;
32 };
33 };
34
35 i2s0: i2s@03830000 {
36 pinctrl-0 = <&i2s0_bus>;
37 pinctrl-names = "default";
38 status = "okay";
39 clocks = <&clock_audss EXYNOS_I2S_BUS>,
40 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
41 clock-names = "iis", "i2s_opclk0";
42 };
43
44 sound: sound {
45 compatible = "samsung,odroidx2-audio";
46 samsung,i2s-controller = <&i2s0>;
47 samsung,audio-codec = <&max98090>;
48 };
49
50 mmc@12550000 {
51 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
52 pinctrl-names = "default";
53 vmmc-supply = <&ldo20_reg &buck8_reg>;
54 status = "okay";
55
56 num-slots = <1>;
57 supports-highspeed;
58 broken-cd;
59 card-detect-delay = <200>;
60 samsung,dw-mshc-ciu-div = <3>;
61 samsung,dw-mshc-sdr-timing = <2 3>;
62 samsung,dw-mshc-ddr-timing = <1 2>;
63
64 slot@0 {
65 reg = <0>;
66 bus-width = <8>;
67 };
68 };
69
70 watchdog@10060000 {
71 status = "okay";
72 };
73
74 rtc@10070000 {
75 status = "okay";
76 };
77
78 g2d@10800000 {
79 status = "okay";
80 };
81
82 camera {
83 status = "okay";
84 pinctrl-names = "default";
85 pinctrl-0 = <>;
86
87 fimc_0: fimc@11800000 {
88 status = "okay";
89 };
90
91 fimc_1: fimc@11810000 {
92 status = "okay";
93 };
94
95 fimc_2: fimc@11820000 {
96 status = "okay";
97 };
98
99 fimc_3: fimc@11830000 {
100 status = "okay";
101 };
102 };
103
104 sdhci@12530000 {
105 bus-width = <4>;
106 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
107 pinctrl-names = "default";
108 vmmc-supply = <&ldo4_reg &ldo21_reg>;
109 cd-gpios = <&gpk2 2 0>;
110 cd-inverted;
111 status = "okay";
112 };
113
114 serial@13800000 {
115 status = "okay";
116 };
117
118 serial@13810000 {
119 status = "okay";
120 };
121
122 fixed-rate-clocks {
123 xxti {
124 compatible = "samsung,clock-xxti";
125 clock-frequency = <0>;
126 };
127
128 xusbxti {
129 compatible = "samsung,clock-xusbxti";
130 clock-frequency = <24000000>;
131 };
132 };
133
134 i2c@13860000 {
135 pinctrl-0 = <&i2c0_bus>;
136 pinctrl-names = "default";
137 status = "okay";
138
139 usb3503: usb3503@08 {
140 compatible = "smsc,usb3503";
141 reg = <0x08>;
142
143 intn-gpios = <&gpx3 0 0>;
144 connect-gpios = <&gpx3 4 0>;
145 reset-gpios = <&gpx3 5 0>;
146 initial-mode = <1>;
147 };
148
149 max77686: pmic@09 {
150 compatible = "maxim,max77686";
151 reg = <0x09>;
152 #clock-cells = <1>;
153
154 voltage-regulators {
155 ldo1_reg: LDO1 {
156 regulator-name = "VDD_ALIVE_1.0V";
157 regulator-min-microvolt = <1000000>;
158 regulator-max-microvolt = <1000000>;
159 regulator-always-on;
160 };
161
162 ldo2_reg: LDO2 {
163 regulator-name = "VDDQ_M1_2_1.8V";
164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-always-on;
167 };
168
169 ldo3_reg: LDO3 {
170 regulator-name = "VDDQ_EXT_1.8V";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-always-on;
174 };
175
176 ldo4_reg: LDO4 {
177 regulator-name = "VDDQ_MMC2_2.8V";
178 regulator-min-microvolt = <2800000>;
179 regulator-max-microvolt = <2800000>;
180 regulator-always-on;
181 regulator-boot-on;
182 };
183
184 ldo5_reg: LDO5 {
185 regulator-name = "VDDQ_MMC1_3_1.8V";
186 regulator-min-microvolt = <1800000>;
187 regulator-max-microvolt = <1800000>;
188 regulator-always-on;
189 regulator-boot-on;
190 };
191
192 ldo6_reg: LDO6 {
193 regulator-name = "VDD10_MPLL_1.0V";
194 regulator-min-microvolt = <1000000>;
195 regulator-max-microvolt = <1000000>;
196 regulator-always-on;
197 };
198
199 ldo7_reg: LDO7 {
200 regulator-name = "VDD10_XPLL_1.0V";
201 regulator-min-microvolt = <1000000>;
202 regulator-max-microvolt = <1000000>;
203 regulator-always-on;
204 };
205
206 ldo11_reg: LDO11 {
207 regulator-name = "VDD18_ABB1_1.8V";
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <1800000>;
210 regulator-always-on;
211 };
212
213 ldo12_reg: LDO12 {
214 regulator-name = "VDD33_USB_3.3V";
215 regulator-min-microvolt = <3300000>;
216 regulator-max-microvolt = <3300000>;
217 regulator-always-on;
218 regulator-boot-on;
219 };
220
221 ldo13_reg: LDO13 {
222 regulator-name = "VDDQ_C2C_W_1.8V";
223 regulator-min-microvolt = <1800000>;
224 regulator-max-microvolt = <1800000>;
225 regulator-always-on;
226 regulator-boot-on;
227 };
228
229 ldo14_reg: LDO14 {
230 regulator-name = "VDD18_ABB0_2_1.8V";
231 regulator-min-microvolt = <1800000>;
232 regulator-max-microvolt = <1800000>;
233 regulator-always-on;
234 regulator-boot-on;
235 };
236
237 ldo15_reg: LDO15 {
238 regulator-name = "VDD10_HSIC_1.0V";
239 regulator-min-microvolt = <1000000>;
240 regulator-max-microvolt = <1000000>;
241 regulator-always-on;
242 regulator-boot-on;
243 };
244
245 ldo16_reg: LDO16 {
246 regulator-name = "VDD18_HSIC_1.8V";
247 regulator-min-microvolt = <1800000>;
248 regulator-max-microvolt = <1800000>;
249 regulator-always-on;
250 regulator-boot-on;
251 };
252
253 ldo20_reg: LDO20 {
254 regulator-name = "LDO20_1.8V";
255 regulator-min-microvolt = <1800000>;
256 regulator-max-microvolt = <1800000>;
257 regulator-boot-on;
258 };
259
260 ldo21_reg: LDO21 {
261 regulator-name = "LDO21_3.3V";
262 regulator-min-microvolt = <3300000>;
263 regulator-max-microvolt = <3300000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267
268 ldo25_reg: LDO25 {
269 regulator-name = "VDDQ_LCD_1.8V";
270 regulator-min-microvolt = <1800000>;
271 regulator-max-microvolt = <1800000>;
272 regulator-always-on;
273 regulator-boot-on;
274 };
275
276 buck1_reg: BUCK1 {
277 regulator-name = "vdd_mif";
278 regulator-min-microvolt = <1000000>;
279 regulator-max-microvolt = <1000000>;
280 regulator-always-on;
281 regulator-boot-on;
282 };
283
284 buck2_reg: BUCK2 {
285 regulator-name = "vdd_arm";
286 regulator-min-microvolt = <900000>;
287 regulator-max-microvolt = <1350000>;
288 regulator-always-on;
289 regulator-boot-on;
290 };
291
292 buck3_reg: BUCK3 {
293 regulator-name = "vdd_int";
294 regulator-min-microvolt = <1000000>;
295 regulator-max-microvolt = <1000000>;
296 regulator-always-on;
297 regulator-boot-on;
298 };
299
300 buck4_reg: BUCK4 {
301 regulator-name = "vdd_g3d";
302 regulator-min-microvolt = <900000>;
303 regulator-max-microvolt = <1100000>;
304 regulator-microvolt-offset = <50000>;
305 };
306
307 buck5_reg: BUCK5 {
308 regulator-name = "VDDQ_CKEM1_2_1.2V";
309 regulator-min-microvolt = <1200000>;
310 regulator-max-microvolt = <1200000>;
311 regulator-always-on;
312 regulator-boot-on;
313 };
314
315 buck6_reg: BUCK6 {
316 regulator-name = "BUCK6_1.35V";
317 regulator-min-microvolt = <1350000>;
318 regulator-max-microvolt = <1350000>;
319 regulator-always-on;
320 regulator-boot-on;
321 };
322
323 buck7_reg: BUCK7 {
324 regulator-name = "BUCK7_2.0V";
325 regulator-min-microvolt = <2000000>;
326 regulator-max-microvolt = <2000000>;
327 regulator-always-on;
328 };
329
330 buck8_reg: BUCK8 {
331 regulator-name = "BUCK8_2.8V";
332 regulator-min-microvolt = <2800000>;
333 regulator-max-microvolt = <2800000>;
334 };
335 };
336 };
337 };
338
339 i2c@13870000 {
340 pinctrl-names = "default";
341 pinctrl-0 = <&i2c1_bus>;
342 status = "okay";
343 max98090: max98090@10 {
344 compatible = "maxim,max98090";
345 reg = <0x10>;
346 interrupt-parent = <&gpx0>;
347 interrupts = <0 0>;
348 };
349 };
350
351 exynos-usbphy@125B0000 {
352 status = "okay";
353 };
354
355 hsotg@12480000 {
356 status = "okay";
357 vusb_d-supply = <&ldo15_reg>;
358 vusb_a-supply = <&ldo12_reg>;
359 };
360
361 ehci: ehci@12580000 {
362 status = "okay";
363 };
364};
365
366&pinctrl_1 {
367 gpio_power_key: power_key {
368 samsung,pins = "gpx1-3";
369 samsung,pin-pud = <0>;
370 };
371};
diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts
new file mode 100644
index 000000000000..c8a64be55d07
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts
@@ -0,0 +1,61 @@
1/*
2 * Hardkernel's Exynos4412 based ODROID-U3 board device tree source
3 *
4 * Copyright (c) 2014 Marek Szyprowski <m.szyprowski@samsung.com>
5 *
6 * Device tree source file for Hardkernel's ODROID-U3 board which is based
7 * on Samsung's Exynos4412 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/dts-v1/;
15#include "exynos4412-odroid-common.dtsi"
16
17/ {
18 model = "Hardkernel ODROID-U3 board based on Exynos4412";
19 compatible = "hardkernel,odroid-u3", "samsung,exynos4412", "samsung,exynos4";
20
21 memory {
22 reg = <0x40000000 0x7FF00000>;
23 };
24
25 leds {
26 compatible = "gpio-leds";
27 led1 {
28 label = "led1:heart";
29 gpios = <&gpc1 0 1>;
30 default-state = "on";
31 linux,default-trigger = "heartbeat";
32 };
33 };
34};
35
36&usb3503 {
37 clock-names = "refclk";
38 clocks = <&pmu_system_controller 0>;
39 refclk-frequency = <24000000>;
40};
41
42&ehci {
43 port@1 {
44 status = "okay";
45 };
46 port@2 {
47 status = "okay";
48 };
49};
50
51&sound {
52 compatible = "samsung,odroidu3-audio";
53 samsung,model = "Odroid-U3";
54 samsung,audio-routing =
55 "Headphone Jack", "HPL",
56 "Headphone Jack", "HPR",
57 "Headphone Jack", "MICBIAS",
58 "IN1", "Headphone Jack",
59 "Speakers", "SPKL",
60 "Speakers", "SPKR";
61};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts
index 31db28a4bb33..cb1cfe7239c4 100644
--- a/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ b/arch/arm/boot/dts/exynos4412-odroidx.dts
@@ -3,8 +3,8 @@
3 * 3 *
4 * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com> 4 * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
5 * 5 *
6 * Device tree source file for Hardkernel's ODROID-X board which is based on 6 * Device tree source file for Hardkernel's ODROID-X board which is based
7 * Samsung's Exynos4412 SoC. 7 * on Samsung's Exynos4412 SoC.
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -12,14 +12,14 @@
12*/ 12*/
13 13
14/dts-v1/; 14/dts-v1/;
15#include "exynos4412.dtsi" 15#include "exynos4412-odroid-common.dtsi"
16 16
17/ { 17/ {
18 model = "Hardkernel ODROID-X board based on Exynos4412"; 18 model = "Hardkernel ODROID-X board based on Exynos4412";
19 compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4"; 19 compatible = "hardkernel,odroid-x", "samsung,exynos4412", "samsung,exynos4";
20 20
21 memory { 21 memory {
22 reg = <0x40000000 0x40000000>; 22 reg = <0x40000000 0x3FF00000>;
23 }; 23 };
24 24
25 leds { 25 leds {
@@ -38,23 +38,25 @@
38 }; 38 };
39 }; 39 };
40 40
41 mmc@12550000 { 41 serial@13820000 {
42 pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
43 pinctrl-names = "default";
44 vmmc-supply = <&ldo20_reg &buck8_reg>;
45 status = "okay"; 42 status = "okay";
43 };
46 44
47 num-slots = <1>; 45 serial@13830000 {
48 supports-highspeed; 46 status = "okay";
49 broken-cd; 47 };
50 card-detect-delay = <200>;
51 samsung,dw-mshc-ciu-div = <3>;
52 samsung,dw-mshc-sdr-timing = <2 3>;
53 samsung,dw-mshc-ddr-timing = <1 2>;
54 48
55 slot@0 { 49 gpio_keys {
56 reg = <0>; 50 pinctrl-0 = <&gpio_power_key &gpio_home_key>;
57 bus-width = <8>; 51
52 home_key {
53 interrupt-parent = <&gpx2>;
54 interrupts = <2 0>;
55 gpios = <&gpx2 2 0>;
56 linux,code = <KEY_HOME>;
57 label = "home key";
58 debounce-interval = <10>;
59 gpio-key,wakeup;
58 }; 60 };
59 }; 61 };
60 62
@@ -65,242 +67,19 @@
65 regulator-max-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>;
66 gpio = <&gpa1 1 1>; 68 gpio = <&gpa1 1 1>;
67 enable-active-high; 69 enable-active-high;
68 regulator-boot-on; 70 regulator-always-on;
69 };
70
71 rtc@10070000 {
72 status = "okay";
73 };
74
75 sdhci@12530000 {
76 bus-width = <4>;
77 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
78 pinctrl-names = "default";
79 vmmc-supply = <&ldo4_reg &ldo21_reg>;
80 status = "okay";
81 };
82
83 serial@13800000 {
84 status = "okay";
85 };
86
87 serial@13810000 {
88 status = "okay";
89 };
90
91 serial@13820000 {
92 status = "okay";
93 }; 71 };
72};
94 73
95 serial@13830000 { 74&ehci {
75 port@1 {
96 status = "okay"; 76 status = "okay";
97 }; 77 };
78};
98 79
99 fixed-rate-clocks { 80&pinctrl_1 {
100 xxti { 81 gpio_home_key: home_key {
101 compatible = "samsung,clock-xxti"; 82 samsung,pins = "gpx2-2";
102 clock-frequency = <0>; 83 samsung,pin-pud = <0>;
103 };
104
105 xusbxti {
106 compatible = "samsung,clock-xusbxti";
107 clock-frequency = <24000000>;
108 };
109 };
110
111 i2c@13860000 {
112 pinctrl-0 = <&i2c0_bus>;
113 pinctrl-names = "default";
114 status = "okay";
115
116 max77686: pmic@09 {
117 compatible = "maxim,max77686";
118 reg = <0x09>;
119 #clock-cells = <1>;
120
121 voltage-regulators {
122 ldo1_reg: LDO1 {
123 regulator-name = "VDD_ALIVE_1.0V";
124 regulator-min-microvolt = <1000000>;
125 regulator-max-microvolt = <1000000>;
126 regulator-always-on;
127 };
128
129 ldo2_reg: LDO2 {
130 regulator-name = "VDDQ_M1_2_1.8V";
131 regulator-min-microvolt = <1800000>;
132 regulator-max-microvolt = <1800000>;
133 regulator-always-on;
134 };
135
136 ldo3_reg: LDO3 {
137 regulator-name = "VDDQ_EXT_1.8V";
138 regulator-min-microvolt = <1800000>;
139 regulator-max-microvolt = <1800000>;
140 regulator-always-on;
141 };
142
143 ldo4_reg: LDO4 {
144 regulator-name = "VDDQ_MMC2_2.8V";
145 regulator-min-microvolt = <2800000>;
146 regulator-max-microvolt = <2800000>;
147 regulator-always-on;
148 regulator-boot-on;
149 };
150
151 ldo5_reg: LDO5 {
152 regulator-name = "VDDQ_MMC1_3_1.8V";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 regulator-always-on;
156 regulator-boot-on;
157 };
158
159 ldo6_reg: LDO6 {
160 regulator-name = "VDD10_MPLL_1.0V";
161 regulator-min-microvolt = <1000000>;
162 regulator-max-microvolt = <1000000>;
163 regulator-always-on;
164 };
165
166 ldo7_reg: LDO7 {
167 regulator-name = "VDD10_XPLL_1.0V";
168 regulator-min-microvolt = <1000000>;
169 regulator-max-microvolt = <1000000>;
170 regulator-always-on;
171 };
172
173 ldo11_reg: LDO11 {
174 regulator-name = "VDD18_ABB1_1.8V";
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>;
177 regulator-always-on;
178 };
179
180 ldo12_reg: LDO12 {
181 regulator-name = "VDD33_USB_3.3V";
182 regulator-min-microvolt = <3300000>;
183 regulator-max-microvolt = <3300000>;
184 regulator-always-on;
185 regulator-boot-on;
186 };
187
188 ldo13_reg: LDO13 {
189 regulator-name = "VDDQ_C2C_W_1.8V";
190 regulator-min-microvolt = <1800000>;
191 regulator-max-microvolt = <1800000>;
192 regulator-always-on;
193 regulator-boot-on;
194 };
195
196 ldo14_reg: LDO14 {
197 regulator-name = "VDD18_ABB0_2_1.8V";
198 regulator-min-microvolt = <1800000>;
199 regulator-max-microvolt = <1800000>;
200 regulator-always-on;
201 regulator-boot-on;
202 };
203
204 ldo15_reg: LDO15 {
205 regulator-name = "VDD10_HSIC_1.0V";
206 regulator-min-microvolt = <1000000>;
207 regulator-max-microvolt = <1000000>;
208 regulator-always-on;
209 regulator-boot-on;
210 };
211
212 ldo16_reg: LDO16 {
213 regulator-name = "VDD18_HSIC_1.8V";
214 regulator-min-microvolt = <1800000>;
215 regulator-max-microvolt = <1800000>;
216 regulator-always-on;
217 regulator-boot-on;
218 };
219
220 ldo20_reg: LDO20 {
221 regulator-name = "LDO20_1.8V";
222 regulator-min-microvolt = <1800000>;
223 regulator-max-microvolt = <1800000>;
224 regulator-boot-on;
225 };
226
227 ldo21_reg: LDO21 {
228 regulator-name = "LDO21_3.3V";
229 regulator-min-microvolt = <3300000>;
230 regulator-max-microvolt = <3300000>;
231 regulator-always-on;
232 regulator-boot-on;
233 };
234
235 ldo25_reg: LDO25 {
236 regulator-name = "VDDQ_LCD_1.8V";
237 regulator-min-microvolt = <1800000>;
238 regulator-max-microvolt = <1800000>;
239 regulator-always-on;
240 regulator-boot-on;
241 };
242
243 buck1_reg: BUCK1 {
244 regulator-name = "vdd_mif";
245 regulator-min-microvolt = <1000000>;
246 regulator-max-microvolt = <1000000>;
247 regulator-always-on;
248 regulator-boot-on;
249 };
250
251 buck2_reg: BUCK2 {
252 regulator-name = "vdd_arm";
253 regulator-min-microvolt = <900000>;
254 regulator-max-microvolt = <1350000>;
255 regulator-always-on;
256 regulator-boot-on;
257 };
258
259 buck3_reg: BUCK3 {
260 regulator-name = "vdd_int";
261 regulator-min-microvolt = <1000000>;
262 regulator-max-microvolt = <1000000>;
263 regulator-always-on;
264 regulator-boot-on;
265 };
266
267 buck4_reg: BUCK4 {
268 regulator-name = "vdd_g3d";
269 regulator-min-microvolt = <900000>;
270 regulator-max-microvolt = <1100000>;
271 regulator-microvolt-offset = <50000>;
272 };
273
274 buck5_reg: BUCK5 {
275 regulator-name = "VDDQ_CKEM1_2_1.2V";
276 regulator-min-microvolt = <1200000>;
277 regulator-max-microvolt = <1200000>;
278 regulator-always-on;
279 regulator-boot-on;
280 };
281
282 buck6_reg: BUCK6 {
283 regulator-name = "BUCK6_1.35V";
284 regulator-min-microvolt = <1350000>;
285 regulator-max-microvolt = <1350000>;
286 regulator-always-on;
287 regulator-boot-on;
288 };
289
290 buck7_reg: BUCK7 {
291 regulator-name = "BUCK7_2.0V";
292 regulator-min-microvolt = <2000000>;
293 regulator-max-microvolt = <2000000>;
294 regulator-always-on;
295 };
296
297 buck8_reg: BUCK8 {
298 regulator-name = "BUCK8_2.8V";
299 regulator-min-microvolt = <2800000>;
300 regulator-max-microvolt = <2800000>;
301 regulator-always-on;
302 };
303 };
304 };
305 }; 84 };
306}; 85};
diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts
new file mode 100644
index 000000000000..96b43f4497cc
--- /dev/null
+++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts
@@ -0,0 +1,32 @@
1/*
2 * Hardkernel's Exynos4412 based ODROID-X2 board device tree source
3 *
4 * Copyright (c) 2012 Dongjin Kim <tobetter@gmail.com>
5 *
6 * Device tree source file for Hardkernel's ODROID-X2 board which is based
7 * on Samsung's Exynos4412 SoC.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14#include "exynos4412-odroidx.dts"
15
16/ {
17 model = "Hardkernel ODROID-X2 board based on Exynos4412";
18 compatible = "hardkernel,odroid-x2", "samsung,exynos4412", "samsung,exynos4";
19
20 memory {
21 reg = <0x40000000 0x7FF00000>;
22 };
23};
24
25&sound {
26 samsung,model = "Odroid-X2";
27 samsung,audio-routing =
28 "Headphone Jack", "HPL",
29 "Headphone Jack", "HPR",
30 "IN1", "Mic Jack",
31 "Mic Jack", "MICBIAS";
32};
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index c42a3e196cd5..d8bc059e172f 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -26,6 +26,10 @@
26 samsung,combiner-nr = <20>; 26 samsung,combiner-nr = <20>;
27 }; 27 };
28 28
29 pmu {
30 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
31 };
32
29 gic: interrupt-controller@10490000 { 33 gic: interrupt-controller@10490000 {
30 cpu-offset = <0x4000>; 34 cpu-offset = <0x4000>;
31 }; 35 };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index de1f9c77b589..861bb919f6d3 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi
@@ -31,12 +31,6 @@
31 mshc0 = &mshc_0; 31 mshc0 = &mshc_0;
32 }; 32 };
33 33
34 pmu {
35 compatible = "arm,cortex-a9-pmu";
36 interrupt-parent = <&combiner>;
37 interrupts = <2 2>, <3 2>, <18 2>, <19 2>;
38 };
39
40 sysram@02020000 { 34 sysram@02020000 {
41 compatible = "mmio-sram"; 35 compatible = "mmio-sram";
42 reg = <0x02020000 0x40000>; 36 reg = <0x02020000 0x40000>;
diff --git a/arch/arm/boot/dts/exynos5250-cros-common.dtsi b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
index 89ac90f59e2e..e603e9c70142 100644
--- a/arch/arm/boot/dts/exynos5250-cros-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-cros-common.dtsi
@@ -27,177 +27,18 @@
27 i2c2_bus: i2c2-bus { 27 i2c2_bus: i2c2-bus {
28 samsung,pin-pud = <0>; 28 samsung,pin-pud = <0>;
29 }; 29 };
30
31 max77686_irq: max77686-irq {
32 samsung,pins = "gpx3-2";
33 samsung,pin-function = <0>;
34 samsung,pin-pud = <0>;
35 samsung,pin-drv = <0>;
36 };
37 }; 30 };
38 31
39 i2c@12C60000 { 32 i2c@12C60000 {
40 status = "okay"; 33 status = "okay";
41 samsung,i2c-sda-delay = <100>; 34 samsung,i2c-sda-delay = <100>;
42 samsung,i2c-max-bus-freq = <378000>; 35 samsung,i2c-max-bus-freq = <378000>;
43
44 max77686@09 {
45 compatible = "maxim,max77686";
46 interrupt-parent = <&gpx3>;
47 interrupts = <2 0>;
48 pinctrl-names = "default";
49 pinctrl-0 = <&max77686_irq>;
50 wakeup-source;
51 reg = <0x09>;
52 #clock-cells = <1>;
53
54 voltage-regulators {
55 ldo1_reg: LDO1 {
56 regulator-name = "P1.0V_LDO_OUT1";
57 regulator-min-microvolt = <1000000>;
58 regulator-max-microvolt = <1000000>;
59 regulator-always-on;
60 };
61
62 ldo2_reg: LDO2 {
63 regulator-name = "P1.8V_LDO_OUT2";
64 regulator-min-microvolt = <1800000>;
65 regulator-max-microvolt = <1800000>;
66 regulator-always-on;
67 };
68
69 ldo3_reg: LDO3 {
70 regulator-name = "P1.8V_LDO_OUT3";
71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <1800000>;
73 regulator-always-on;
74 };
75
76 ldo7_reg: LDO7 {
77 regulator-name = "P1.1V_LDO_OUT7";
78 regulator-min-microvolt = <1100000>;
79 regulator-max-microvolt = <1100000>;
80 regulator-always-on;
81 };
82
83 ldo8_reg: LDO8 {
84 regulator-name = "P1.0V_LDO_OUT8";
85 regulator-min-microvolt = <1000000>;
86 regulator-max-microvolt = <1000000>;
87 regulator-always-on;
88 };
89
90 ldo10_reg: LDO10 {
91 regulator-name = "P1.8V_LDO_OUT10";
92 regulator-min-microvolt = <1800000>;
93 regulator-max-microvolt = <1800000>;
94 regulator-always-on;
95 };
96
97 ldo12_reg: LDO12 {
98 regulator-name = "P3.0V_LDO_OUT12";
99 regulator-min-microvolt = <3000000>;
100 regulator-max-microvolt = <3000000>;
101 regulator-always-on;
102 };
103
104 ldo14_reg: LDO14 {
105 regulator-name = "P1.8V_LDO_OUT14";
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 regulator-always-on;
109 };
110
111 ldo15_reg: LDO15 {
112 regulator-name = "P1.0V_LDO_OUT15";
113 regulator-min-microvolt = <1000000>;
114 regulator-max-microvolt = <1000000>;
115 regulator-always-on;
116 };
117
118 ldo16_reg: LDO16 {
119 regulator-name = "P1.8V_LDO_OUT16";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-always-on;
123 };
124
125 buck1_reg: BUCK1 {
126 regulator-name = "vdd_mif";
127 regulator-min-microvolt = <950000>;
128 regulator-max-microvolt = <1300000>;
129 regulator-always-on;
130 regulator-boot-on;
131 };
132
133 buck2_reg: BUCK2 {
134 regulator-name = "vdd_arm";
135 regulator-min-microvolt = <850000>;
136 regulator-max-microvolt = <1350000>;
137 regulator-always-on;
138 regulator-boot-on;
139 };
140
141 buck3_reg: BUCK3 {
142 regulator-name = "vdd_int";
143 regulator-min-microvolt = <900000>;
144 regulator-max-microvolt = <1200000>;
145 regulator-always-on;
146 regulator-boot-on;
147 };
148
149 buck4_reg: BUCK4 {
150 regulator-name = "vdd_g3d";
151 regulator-min-microvolt = <850000>;
152 regulator-max-microvolt = <1300000>;
153 regulator-always-on;
154 regulator-boot-on;
155 };
156
157 buck5_reg: BUCK5 {
158 regulator-name = "P1.8V_BUCK_OUT5";
159 regulator-min-microvolt = <1800000>;
160 regulator-max-microvolt = <1800000>;
161 regulator-always-on;
162 regulator-boot-on;
163 };
164
165 buck6_reg: BUCK6 {
166 regulator-name = "P1.35V_BUCK_OUT6";
167 regulator-min-microvolt = <1350000>;
168 regulator-max-microvolt = <1350000>;
169 regulator-always-on;
170 };
171
172 buck7_reg: BUCK7 {
173 regulator-name = "P2.0V_BUCK_OUT7";
174 regulator-min-microvolt = <2000000>;
175 regulator-max-microvolt = <2000000>;
176 regulator-always-on;
177 };
178
179 buck8_reg: BUCK8 {
180 regulator-name = "P2.85V_BUCK_OUT8";
181 regulator-min-microvolt = <2850000>;
182 regulator-max-microvolt = <2850000>;
183 regulator-always-on;
184 };
185 };
186 };
187 }; 36 };
188 37
189 i2c@12C70000 { 38 i2c@12C70000 {
190 status = "okay"; 39 status = "okay";
191 samsung,i2c-sda-delay = <100>; 40 samsung,i2c-sda-delay = <100>;
192 samsung,i2c-max-bus-freq = <378000>; 41 samsung,i2c-max-bus-freq = <378000>;
193
194 trackpad {
195 reg = <0x67>;
196 compatible = "cypress,cyapa";
197 interrupts = <2 0>;
198 interrupt-parent = <&gpx1>;
199 wakeup-source;
200 };
201 }; 42 };
202 43
203 i2c@12C80000 { 44 i2c@12C80000 {
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0c6433ae63ac..b4b35adae565 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -44,6 +44,8 @@
44 max77686@09 { 44 max77686@09 {
45 compatible = "maxim,max77686"; 45 compatible = "maxim,max77686";
46 reg = <0x09>; 46 reg = <0x09>;
47 interrupt-parent = <&gpx3>;
48 interrupts = <2 0>;
47 49
48 voltage-regulators { 50 voltage-regulators {
49 ldo1_reg: LDO1 { 51 ldo1_reg: LDO1 {
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index 079fdf9e3f18..f2b8c4116541 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -137,7 +137,7 @@
137 sbs,poll-retry-count = <1>; 137 sbs,poll-retry-count = <1>;
138 }; 138 };
139 139
140 ec: embedded-controller { 140 cros_ec: embedded-controller {
141 compatible = "google,cros-ec-i2c"; 141 compatible = "google,cros-ec-i2c";
142 reg = <0x1e>; 142 reg = <0x1e>;
143 interrupts = <6 0>; 143 interrupts = <6 0>;
@@ -145,95 +145,6 @@
145 pinctrl-names = "default"; 145 pinctrl-names = "default";
146 pinctrl-0 = <&ec_irq>; 146 pinctrl-0 = <&ec_irq>;
147 wakeup-source; 147 wakeup-source;
148
149 keyboard-controller {
150 compatible = "google,cros-ec-keyb";
151 keypad,num-rows = <8>;
152 keypad,num-columns = <13>;
153 google,needs-ghost-filter;
154 linux,keymap = <0x0001007d /* L_META */
155 0x0002003b /* F1 */
156 0x00030030 /* B */
157 0x00040044 /* F10 */
158 0x00060031 /* N */
159 0x0008000d /* = */
160 0x000a0064 /* R_ALT */
161
162 0x01010001 /* ESC */
163 0x0102003e /* F4 */
164 0x01030022 /* G */
165 0x01040041 /* F7 */
166 0x01060023 /* H */
167 0x01080028 /* ' */
168 0x01090043 /* F9 */
169 0x010b000e /* BKSPACE */
170
171 0x0200001d /* L_CTRL */
172 0x0201000f /* TAB */
173 0x0202003d /* F3 */
174 0x02030014 /* T */
175 0x02040040 /* F6 */
176 0x0205001b /* ] */
177 0x02060015 /* Y */
178 0x02070056 /* 102ND */
179 0x0208001a /* [ */
180 0x02090042 /* F8 */
181
182 0x03010029 /* GRAVE */
183 0x0302003c /* F2 */
184 0x03030006 /* 5 */
185 0x0304003f /* F5 */
186 0x03060007 /* 6 */
187 0x0308000c /* - */
188 0x030b002b /* \ */
189
190 0x04000061 /* R_CTRL */
191 0x0401001e /* A */
192 0x04020020 /* D */
193 0x04030021 /* F */
194 0x0404001f /* S */
195 0x04050025 /* K */
196 0x04060024 /* J */
197 0x04080027 /* ; */
198 0x04090026 /* L */
199 0x040a002b /* \ */
200 0x040b001c /* ENTER */
201
202 0x0501002c /* Z */
203 0x0502002e /* C */
204 0x0503002f /* V */
205 0x0504002d /* X */
206 0x05050033 /* , */
207 0x05060032 /* M */
208 0x0507002a /* L_SHIFT */
209 0x05080035 /* / */
210 0x05090034 /* . */
211 0x050B0039 /* SPACE */
212
213 0x06010002 /* 1 */
214 0x06020004 /* 3 */
215 0x06030005 /* 4 */
216 0x06040003 /* 2 */
217 0x06050009 /* 8 */
218 0x06060008 /* 7 */
219 0x0608000b /* 0 */
220 0x0609000a /* 9 */
221 0x060a0038 /* L_ALT */
222 0x060b006c /* DOWN */
223 0x060c006a /* RIGHT */
224
225 0x07010010 /* Q */
226 0x07020012 /* E */
227 0x07030013 /* R */
228 0x07040011 /* W */
229 0x07050017 /* I */
230 0x07060016 /* U */
231 0x07070036 /* R_SHIFT */
232 0x07080019 /* P */
233 0x07090018 /* O */
234 0x070b0067 /* UP */
235 0x070c0069>; /* LEFT */
236 };
237 }; 148 };
238 149
239 power-regulator { 150 power-regulator {
@@ -351,6 +262,7 @@
351 sound { 262 sound {
352 compatible = "google,snow-audio-max98095"; 263 compatible = "google,snow-audio-max98095";
353 264
265 samsung,model = "Snow-I2S-MAX98095";
354 samsung,i2s-controller = <&i2s0>; 266 samsung,i2s-controller = <&i2s0>;
355 samsung,audio-codec = <&max98095>; 267 samsung,audio-codec = <&max98095>;
356 }; 268 };
@@ -431,3 +343,170 @@
431 }; 343 };
432 }; 344 };
433}; 345};
346
347&i2c_0 {
348 max77686@09 {
349 compatible = "maxim,max77686";
350 interrupt-parent = <&gpx3>;
351 interrupts = <2 0>;
352 pinctrl-names = "default";
353 pinctrl-0 = <&max77686_irq>;
354 wakeup-source;
355 reg = <0x09>;
356 #clock-cells = <1>;
357
358 voltage-regulators {
359 ldo1_reg: LDO1 {
360 regulator-name = "P1.0V_LDO_OUT1";
361 regulator-min-microvolt = <1000000>;
362 regulator-max-microvolt = <1000000>;
363 regulator-always-on;
364 };
365
366 ldo2_reg: LDO2 {
367 regulator-name = "P1.8V_LDO_OUT2";
368 regulator-min-microvolt = <1800000>;
369 regulator-max-microvolt = <1800000>;
370 regulator-always-on;
371 };
372
373 ldo3_reg: LDO3 {
374 regulator-name = "P1.8V_LDO_OUT3";
375 regulator-min-microvolt = <1800000>;
376 regulator-max-microvolt = <1800000>;
377 regulator-always-on;
378 };
379
380 ldo7_reg: LDO7 {
381 regulator-name = "P1.1V_LDO_OUT7";
382 regulator-min-microvolt = <1100000>;
383 regulator-max-microvolt = <1100000>;
384 regulator-always-on;
385 };
386
387 ldo8_reg: LDO8 {
388 regulator-name = "P1.0V_LDO_OUT8";
389 regulator-min-microvolt = <1000000>;
390 regulator-max-microvolt = <1000000>;
391 regulator-always-on;
392 };
393
394 ldo10_reg: LDO10 {
395 regulator-name = "P1.8V_LDO_OUT10";
396 regulator-min-microvolt = <1800000>;
397 regulator-max-microvolt = <1800000>;
398 regulator-always-on;
399 };
400
401 ldo12_reg: LDO12 {
402 regulator-name = "P3.0V_LDO_OUT12";
403 regulator-min-microvolt = <3000000>;
404 regulator-max-microvolt = <3000000>;
405 regulator-always-on;
406 };
407
408 ldo14_reg: LDO14 {
409 regulator-name = "P1.8V_LDO_OUT14";
410 regulator-min-microvolt = <1800000>;
411 regulator-max-microvolt = <1800000>;
412 regulator-always-on;
413 };
414
415 ldo15_reg: LDO15 {
416 regulator-name = "P1.0V_LDO_OUT15";
417 regulator-min-microvolt = <1000000>;
418 regulator-max-microvolt = <1000000>;
419 regulator-always-on;
420 };
421
422 ldo16_reg: LDO16 {
423 regulator-name = "P1.8V_LDO_OUT16";
424 regulator-min-microvolt = <1800000>;
425 regulator-max-microvolt = <1800000>;
426 regulator-always-on;
427 };
428
429 buck1_reg: BUCK1 {
430 regulator-name = "vdd_mif";
431 regulator-min-microvolt = <950000>;
432 regulator-max-microvolt = <1300000>;
433 regulator-always-on;
434 regulator-boot-on;
435 };
436
437 buck2_reg: BUCK2 {
438 regulator-name = "vdd_arm";
439 regulator-min-microvolt = <850000>;
440 regulator-max-microvolt = <1350000>;
441 regulator-always-on;
442 regulator-boot-on;
443 };
444
445 buck3_reg: BUCK3 {
446 regulator-name = "vdd_int";
447 regulator-min-microvolt = <900000>;
448 regulator-max-microvolt = <1200000>;
449 regulator-always-on;
450 regulator-boot-on;
451 };
452
453 buck4_reg: BUCK4 {
454 regulator-name = "vdd_g3d";
455 regulator-min-microvolt = <850000>;
456 regulator-max-microvolt = <1300000>;
457 regulator-always-on;
458 regulator-boot-on;
459 };
460
461 buck5_reg: BUCK5 {
462 regulator-name = "P1.8V_BUCK_OUT5";
463 regulator-min-microvolt = <1800000>;
464 regulator-max-microvolt = <1800000>;
465 regulator-always-on;
466 regulator-boot-on;
467 };
468
469 buck6_reg: BUCK6 {
470 regulator-name = "P1.35V_BUCK_OUT6";
471 regulator-min-microvolt = <1350000>;
472 regulator-max-microvolt = <1350000>;
473 regulator-always-on;
474 };
475
476 buck7_reg: BUCK7 {
477 regulator-name = "P2.0V_BUCK_OUT7";
478 regulator-min-microvolt = <2000000>;
479 regulator-max-microvolt = <2000000>;
480 regulator-always-on;
481 };
482
483 buck8_reg: BUCK8 {
484 regulator-name = "P2.85V_BUCK_OUT8";
485 regulator-min-microvolt = <2850000>;
486 regulator-max-microvolt = <2850000>;
487 regulator-always-on;
488 };
489 };
490 };
491};
492
493&i2c_1 {
494 trackpad {
495 reg = <0x67>;
496 compatible = "cypress,cyapa";
497 interrupts = <2 0>;
498 interrupt-parent = <&gpx1>;
499 wakeup-source;
500 };
501};
502
503&pinctrl_0 {
504 max77686_irq: max77686-irq {
505 samsung,pins = "gpx3-2";
506 samsung,pin-function = <0>;
507 samsung,pin-pud = <0>;
508 samsung,pin-drv = <0>;
509 };
510};
511
512#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 4539a0ae714d..36da38e29000 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -231,6 +231,11 @@
231 interrupts = <0 243 0>; 231 interrupts = <0 243 0>;
232 }; 232 };
233 233
234 pmu_system_controller: system-controller@10D50000 {
235 compatible = "samsung,exynos5260-pmu", "syscon";
236 reg = <0x10D50000 0x10000>;
237 };
238
234 uart0: serial@12C00000 { 239 uart0: serial@12C00000 {
235 compatible = "samsung,exynos4210-uart"; 240 compatible = "samsung,exynos4210-uart";
236 reg = <0x12C00000 0x100>; 241 reg = <0x12C00000 0x100>;
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 52070e54589a..731eefd23fa9 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -34,24 +34,28 @@
34 device_type = "cpu"; 34 device_type = "cpu";
35 compatible = "arm,cortex-a15"; 35 compatible = "arm,cortex-a15";
36 reg = <0x0>; 36 reg = <0x0>;
37 clock-frequency = <1600000000>;
37 }; 38 };
38 39
39 CPU1: cpu@1 { 40 CPU1: cpu@1 {
40 device_type = "cpu"; 41 device_type = "cpu";
41 compatible = "arm,cortex-a15"; 42 compatible = "arm,cortex-a15";
42 reg = <0x1>; 43 reg = <0x1>;
44 clock-frequency = <1600000000>;
43 }; 45 };
44 46
45 CPU2: cpu@2 { 47 CPU2: cpu@2 {
46 device_type = "cpu"; 48 device_type = "cpu";
47 compatible = "arm,cortex-a15"; 49 compatible = "arm,cortex-a15";
48 reg = <0x2>; 50 reg = <0x2>;
51 clock-frequency = <1600000000>;
49 }; 52 };
50 53
51 CPU3: cpu@3 { 54 CPU3: cpu@3 {
52 device_type = "cpu"; 55 device_type = "cpu";
53 compatible = "arm,cortex-a15"; 56 compatible = "arm,cortex-a15";
54 reg = <0x3>; 57 reg = <0x3>;
58 clock-frequency = <1600000000>;
55 }; 59 };
56 }; 60 };
57 61
@@ -93,6 +97,11 @@
93 reg = <0x10000000 0x100>; 97 reg = <0x10000000 0x100>;
94 }; 98 };
95 99
100 pmu_system_controller: system-controller@10040000 {
101 compatible = "samsung,exynos5410-pmu", "syscon";
102 reg = <0x10040000 0x5000>;
103 };
104
96 mct: mct@101C0000 { 105 mct: mct@101C0000 {
97 compatible = "samsung,exynos4210-mct"; 106 compatible = "samsung,exynos4210-mct";
98 reg = <0x101C0000 0xB00>; 107 reg = <0x101C0000 0xB00>;
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 1c5b8f9f4a36..228a6b1e0aa1 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -25,8 +25,18 @@
25 "google,pit", "google,peach","samsung,exynos5420", 25 "google,pit", "google,peach","samsung,exynos5420",
26 "samsung,exynos5"; 26 "samsung,exynos5";
27 27
28 memory { 28 aliases {
29 reg = <0x20000000 0x80000000>; 29 /* Assign 20 so we don't get confused w/ builtin ones */
30 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
31 };
32
33 backlight {
34 compatible = "pwm-backlight";
35 pwms = <&pwm 0 1000000 0>;
36 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
37 default-brightness-level = <7>;
38 pinctrl-0 = <&pwm0_out>;
39 pinctrl-names = "default";
30 }; 40 };
31 41
32 fixed-rate-clocks { 42 fixed-rate-clocks {
@@ -50,18 +60,14 @@
50 }; 60 };
51 }; 61 };
52 62
53 backlight { 63 memory {
54 compatible = "pwm-backlight"; 64 reg = <0x20000000 0x80000000>;
55 pwms = <&pwm 0 1000000 0>;
56 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
57 default-brightness-level = <7>;
58 pinctrl-0 = <&pwm0_out>;
59 pinctrl-names = "default";
60 }; 65 };
61 66
62 sound { 67 sound {
63 compatible = "google,snow-audio-max98090"; 68 compatible = "google,snow-audio-max98090";
64 69
70 samsung,model = "Peach-Pit-I2S-MAX98090";
65 samsung,i2s-controller = <&i2s0>; 71 samsung,i2s-controller = <&i2s0>;
66 samsung,audio-codec = <&max98090>; 72 samsung,audio-codec = <&max98090>;
67 }; 73 };
@@ -87,66 +93,92 @@
87 pinctrl-0 = <&usb301_vbus_en>; 93 pinctrl-0 = <&usb301_vbus_en>;
88 enable-active-high; 94 enable-active-high;
89 }; 95 };
90};
91 96
92&pinctrl_0 { 97 vbat: fixed-regulator {
93 max98090_irq: max98090-irq { 98 compatible = "regulator-fixed";
94 samsung,pins = "gpx0-2"; 99 regulator-name = "vbat-supply";
95 samsung,pin-function = <0>; 100 regulator-boot-on;
96 samsung,pin-pud = <0>; 101 regulator-always-on;
97 samsung,pin-drv = <0>;
98 }; 102 };
103};
99 104
100 tpm_irq: tpm-irq { 105&dp {
101 samsung,pins = "gpx1-0"; 106 status = "okay";
102 samsung,pin-function = <0>; 107 pinctrl-names = "default";
103 samsung,pin-pud = <0>; 108 pinctrl-0 = <&dp_hpd_gpio>;
104 samsung,pin-drv = <0>; 109 samsung,color-space = <0>;
105 }; 110 samsung,dynamic-range = <0>;
111 samsung,ycbcr-coeff = <0>;
112 samsung,color-depth = <1>;
113 samsung,link-rate = <0x06>;
114 samsung,lane-count = <2>;
115 samsung,hpd-gpio = <&gpx2 6 0>;
106 116
107 power_key_irq: power-key-irq { 117 display-timings {
108 samsung,pins = "gpx1-2"; 118 native-mode = <&timing1>;
109 samsung,pin-function = <0>;
110 samsung,pin-pud = <0>;
111 samsung,pin-drv = <0>;
112 };
113 119
114 hdmi_hpd_irq: hdmi-hpd-irq { 120 timing1: timing@1 {
115 samsung,pins = "gpx3-7"; 121 clock-frequency = <70589280>;
116 samsung,pin-function = <0>; 122 hactive = <1366>;
117 samsung,pin-pud = <1>; 123 vactive = <768>;
118 samsung,pin-drv = <0>; 124 hfront-porch = <40>;
125 hback-porch = <40>;
126 hsync-len = <32>;
127 vback-porch = <10>;
128 vfront-porch = <12>;
129 vsync-len = <6>;
130 };
119 }; 131 };
132};
120 133
121 dp_hpd_gpio: dp_hpd_gpio { 134&fimd {
122 samsung,pins = "gpx2-6"; 135 status = "okay";
123 samsung,pin-function = <0>; 136 samsung,invert-vclk;
124 samsung,pin-pud = <3>;
125 samsung,pin-drv = <0>;
126 };
127}; 137};
128 138
129&pinctrl_3 { 139&hdmi {
130 usb300_vbus_en: usb300-vbus-en { 140 status = "okay";
131 samsung,pins = "gph0-0"; 141 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
132 samsung,pin-function = <1>; 142 pinctrl-names = "default";
133 samsung,pin-pud = <0>; 143 pinctrl-0 = <&hdmi_hpd_irq>;
134 samsung,pin-drv = <0>; 144 ddc = <&i2c_2>;
145};
146
147&hsi2c_7 {
148 status = "okay";
149
150 max98090: codec@10 {
151 compatible = "maxim,max98090";
152 reg = <0x10>;
153 interrupts = <2 0>;
154 interrupt-parent = <&gpx0>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&max98090_irq>;
135 }; 157 };
158};
136 159
137 usb301_vbus_en: usb301-vbus-en { 160&hsi2c_9 {
138 samsung,pins = "gph0-1"; 161 status = "okay";
139 samsung,pin-function = <1>; 162 clock-frequency = <400000>;
140 samsung,pin-pud = <0>; 163
141 samsung,pin-drv = <0>; 164 tpm@20 {
165 compatible = "infineon,slb9645tt";
166 reg = <0x20>;
167
168 /* Unused irq; but still need to configure the pins */
169 pinctrl-names = "default";
170 pinctrl-0 = <&tpm_irq>;
142 }; 171 };
143}; 172};
144 173
145&rtc { 174&i2c_2 {
146 status = "okay"; 175 status = "okay";
176 samsung,i2c-sda-delay = <100>;
177 samsung,i2c-max-bus-freq = <66000>;
178 samsung,i2c-slave-addr = <0x50>;
147}; 179};
148 180
149&uart_3 { 181&i2s0 {
150 status = "okay"; 182 status = "okay";
151}; 183};
152 184
@@ -189,46 +221,210 @@
189 }; 221 };
190}; 222};
191 223
192&hsi2c_7 {
193 status = "okay";
194 224
195 max98090: codec@10 { 225&pinctrl_0 {
196 compatible = "maxim,max98090"; 226 pinctrl-names = "default";
197 reg = <0x10>; 227 pinctrl-0 = <&mask_tpm_reset>;
198 interrupts = <2 0>; 228
199 interrupt-parent = <&gpx0>; 229 max98090_irq: max98090-irq {
200 pinctrl-names = "default"; 230 samsung,pins = "gpx0-2";
201 pinctrl-0 = <&max98090_irq>; 231 samsung,pin-function = <0>;
232 samsung,pin-pud = <0>;
233 samsung,pin-drv = <0>;
234 };
235
236 /* We need GPX0_6 to be low at sleep time; just keep it low always */
237 mask_tpm_reset: mask-tpm-reset {
238 samsung,pins = "gpx0-6";
239 samsung,pin-function = <1>;
240 samsung,pin-pud = <0>;
241 samsung,pin-drv = <0>;
242 samsung,pin-val = <0>;
243 };
244
245 tpm_irq: tpm-irq {
246 samsung,pins = "gpx1-0";
247 samsung,pin-function = <0>;
248 samsung,pin-pud = <0>;
249 samsung,pin-drv = <0>;
250 };
251
252 power_key_irq: power-key-irq {
253 samsung,pins = "gpx1-2";
254 samsung,pin-function = <0>;
255 samsung,pin-pud = <0>;
256 samsung,pin-drv = <0>;
257 };
258
259 ec_irq: ec-irq {
260 samsung,pins = "gpx1-5";
261 samsung,pin-function = <0>;
262 samsung,pin-pud = <0>;
263 samsung,pin-drv = <0>;
264 };
265
266 tps65090_irq: tps65090-irq {
267 samsung,pins = "gpx2-5";
268 samsung,pin-function = <0>;
269 samsung,pin-pud = <0>;
270 samsung,pin-drv = <0>;
271 };
272
273 dp_hpd_gpio: dp_hpd_gpio {
274 samsung,pins = "gpx2-6";
275 samsung,pin-function = <0>;
276 samsung,pin-pud = <3>;
277 samsung,pin-drv = <0>;
278 };
279
280 hdmi_hpd_irq: hdmi-hpd-irq {
281 samsung,pins = "gpx3-7";
282 samsung,pin-function = <0>;
283 samsung,pin-pud = <1>;
284 samsung,pin-drv = <0>;
202 }; 285 };
203}; 286};
204 287
205&hsi2c_9 { 288&pinctrl_3 {
206 status = "okay"; 289 /* Drive SPI lines at x2 for better integrity */
207 clock-frequency = <400000>; 290 spi2-bus {
291 samsung,pin-drv = <2>;
292 };
208 293
209 tpm@20 { 294 /* Drive SPI chip select at x2 for better integrity */
210 compatible = "infineon,slb9645tt"; 295 ec_spi_cs: ec-spi-cs {
211 reg = <0x20>; 296 samsung,pins = "gpb1-2";
297 samsung,pin-function = <1>;
298 samsung,pin-pud = <0>;
299 samsung,pin-drv = <2>;
300 };
212 301
213 /* Unused irq; but still need to configure the pins */ 302 usb300_vbus_en: usb300-vbus-en {
214 pinctrl-names = "default"; 303 samsung,pins = "gph0-0";
215 pinctrl-0 = <&tpm_irq>; 304 samsung,pin-function = <1>;
305 samsung,pin-pud = <0>;
306 samsung,pin-drv = <0>;
307 };
308
309 usb301_vbus_en: usb301-vbus-en {
310 samsung,pins = "gph0-1";
311 samsung,pin-function = <1>;
312 samsung,pin-pud = <0>;
313 samsung,pin-drv = <0>;
216 }; 314 };
217}; 315};
218 316
219&i2c_2 { 317&rtc {
220 status = "okay"; 318 status = "okay";
221 samsung,i2c-sda-delay = <100>;
222 samsung,i2c-max-bus-freq = <66000>;
223 samsung,i2c-slave-addr = <0x50>;
224}; 319};
225 320
226&hdmi { 321&spi_2 {
322 status = "okay";
323 num-cs = <1>;
324 samsung,spi-src-clk = <0>;
325 cs-gpios = <&gpb1 2 0>;
326
327 cros_ec: cros-ec@0 {
328 compatible = "google,cros-ec-spi";
329 interrupt-parent = <&gpx1>;
330 interrupts = <5 0>;
331 pinctrl-names = "default";
332 pinctrl-0 = <&ec_spi_cs &ec_irq>;
333 reg = <0>;
334 spi-max-frequency = <3125000>;
335
336 controller-data {
337 samsung,spi-feedback-delay = <1>;
338 };
339
340 i2c-tunnel {
341 compatible = "google,cros-ec-i2c-tunnel";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 google,remote-bus = <0>;
345
346 battery: sbs-battery@b {
347 compatible = "sbs,sbs-battery";
348 reg = <0xb>;
349 sbs,poll-retry-count = <1>;
350 sbs,i2c-retry-count = <2>;
351 };
352
353 power-regulator@48 {
354 compatible = "ti,tps65090";
355 reg = <0x48>;
356
357 /*
358 * Config irq to disable internal pulls
359 * even though we run in polling mode.
360 */
361 pinctrl-names = "default";
362 pinctrl-0 = <&tps65090_irq>;
363
364 vsys1-supply = <&vbat>;
365 vsys2-supply = <&vbat>;
366 vsys3-supply = <&vbat>;
367 infet1-supply = <&vbat>;
368 infet2-supply = <&vbat>;
369 infet3-supply = <&vbat>;
370 infet4-supply = <&vbat>;
371 infet5-supply = <&vbat>;
372 infet6-supply = <&vbat>;
373 infet7-supply = <&vbat>;
374 vsys-l1-supply = <&vbat>;
375 vsys-l2-supply = <&vbat>;
376
377 regulators {
378 tps65090_dcdc1: dcdc1 {
379 ti,enable-ext-control;
380 };
381 tps65090_dcdc2: dcdc2 {
382 ti,enable-ext-control;
383 };
384 tps65090_dcdc3: dcdc3 {
385 ti,enable-ext-control;
386 };
387 tps65090_fet1: fet1 {
388 regulator-name = "vcd_led";
389 };
390 tps65090_fet2: fet2 {
391 regulator-name = "video_mid";
392 regulator-always-on;
393 };
394 tps65090_fet3: fet3 {
395 regulator-name = "wwan_r";
396 regulator-always-on;
397 };
398 tps65090_fet4: fet4 {
399 regulator-name = "sdcard";
400 regulator-always-on;
401 };
402 tps65090_fet5: fet5 {
403 regulator-name = "camout";
404 };
405 tps65090_fet6: fet6 {
406 regulator-name = "lcd_vdd";
407 };
408 tps65090_fet7: fet7 {
409 regulator-name = "video_mid_1a";
410 regulator-always-on;
411 };
412 tps65090_ldo1: ldo1 {
413 };
414 tps65090_ldo2: ldo2 {
415 };
416 };
417
418 charger {
419 compatible = "ti,tps65090-charger";
420 };
421 };
422 };
423 };
424};
425
426&uart_3 {
227 status = "okay"; 427 status = "okay";
228 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&hdmi_hpd_irq>;
231 ddc = <&i2c_2>;
232}; 428};
233 429
234&usbdrd_phy0 { 430&usbdrd_phy0 {
@@ -248,40 +444,4 @@
248 timeout-sec = <32>; 444 timeout-sec = <32>;
249}; 445};
250 446
251&i2s0 { 447#include "cros-ec-keyboard.dtsi"
252 status = "okay";
253};
254
255&fimd {
256 status = "okay";
257 samsung,invert-vclk;
258};
259
260&dp {
261 status = "okay";
262 pinctrl-names = "default";
263 pinctrl-0 = <&dp_hpd_gpio>;
264 samsung,color-space = <0>;
265 samsung,dynamic-range = <0>;
266 samsung,ycbcr-coeff = <0>;
267 samsung,color-depth = <1>;
268 samsung,link-rate = <0x06>;
269 samsung,lane-count = <2>;
270 samsung,hpd-gpio = <&gpx2 6 0>;
271
272 display-timings {
273 native-mode = <&timing1>;
274
275 timing1: timing@1 {
276 clock-frequency = <70589280>;
277 hactive = <1366>;
278 vactive = <768>;
279 hfront-porch = <40>;
280 hback-porch = <40>;
281 hsync-len = <32>;
282 vback-porch = <10>;
283 vfront-porch = <12>;
284 vsync-len = <6>;
285 };
286 };
287};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 08dd681c0019..95ec37dff3e8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -265,11 +265,6 @@
265 clock-names = "oscclk", "pclk0", "clk0"; 265 clock-names = "oscclk", "pclk0", "clk0";
266 }; 266 };
267 267
268 disp_pd: power-domain@100440C0 {
269 compatible = "samsung,exynos4210-pd";
270 reg = <0x100440C0 0x20>;
271 };
272
273 msc_pd: power-domain@10044120 { 268 msc_pd: power-domain@10044120 {
274 compatible = "samsung,exynos4210-pd"; 269 compatible = "samsung,exynos4210-pd";
275 reg = <0x10044120 0x20>; 270 reg = <0x10044120 0x20>;
@@ -541,7 +536,6 @@
541 }; 536 };
542 537
543 fimd: fimd@14400000 { 538 fimd: fimd@14400000 {
544 samsung,power-domain = <&disp_pd>;
545 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>; 539 clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
546 clock-names = "sclk_fimd", "fimd"; 540 clock-names = "sclk_fimd", "fimd";
547 }; 541 };
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index f3af2079a063..f3ee48bbe05f 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -23,8 +23,18 @@
23 "google,pi", "google,peach", "samsung,exynos5800", 23 "google,pi", "google,peach", "samsung,exynos5800",
24 "samsung,exynos5"; 24 "samsung,exynos5";
25 25
26 memory { 26 aliases {
27 reg = <0x20000000 0x80000000>; 27 /* Assign 20 so we don't get confused w/ builtin ones */
28 i2c20 = "/spi@12d40000/cros-ec@0/i2c-tunnel";
29 };
30
31 backlight {
32 compatible = "pwm-backlight";
33 pwms = <&pwm 0 1000000 0>;
34 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
35 default-brightness-level = <7>;
36 pinctrl-0 = <&pwm0_out>;
37 pinctrl-names = "default";
28 }; 38 };
29 39
30 fixed-rate-clocks { 40 fixed-rate-clocks {
@@ -48,13 +58,16 @@
48 }; 58 };
49 }; 59 };
50 60
51 backlight { 61 memory {
52 compatible = "pwm-backlight"; 62 reg = <0x20000000 0x80000000>;
53 pwms = <&pwm 0 1000000 0>; 63 };
54 brightness-levels = <0 100 500 1000 1500 2000 2500 2800>; 64
55 default-brightness-level = <7>; 65 sound {
56 pinctrl-0 = <&pwm0_out>; 66 compatible = "google,snow-audio-max98091";
57 pinctrl-names = "default"; 67
68 samsung,model = "Peach-Pi-I2S-MAX98091";
69 samsung,i2s-controller = <&i2s0>;
70 samsung,audio-codec = <&max98091>;
58 }; 71 };
59 72
60 usb300_vbus_reg: regulator-usb300 { 73 usb300_vbus_reg: regulator-usb300 {
@@ -78,59 +91,92 @@
78 pinctrl-0 = <&usb301_vbus_en>; 91 pinctrl-0 = <&usb301_vbus_en>;
79 enable-active-high; 92 enable-active-high;
80 }; 93 };
81};
82 94
83&pinctrl_0 { 95 vbat: fixed-regulator {
84 tpm_irq: tpm-irq { 96 compatible = "regulator-fixed";
85 samsung,pins = "gpx1-0"; 97 regulator-name = "vbat-supply";
86 samsung,pin-function = <0>; 98 regulator-boot-on;
87 samsung,pin-pud = <0>; 99 regulator-always-on;
88 samsung,pin-drv = <0>;
89 }; 100 };
101};
90 102
91 power_key_irq: power-key-irq { 103&dp {
92 samsung,pins = "gpx1-2"; 104 status = "okay";
93 samsung,pin-function = <0>; 105 pinctrl-names = "default";
94 samsung,pin-pud = <0>; 106 pinctrl-0 = <&dp_hpd_gpio>;
95 samsung,pin-drv = <0>; 107 samsung,color-space = <0>;
96 }; 108 samsung,dynamic-range = <0>;
109 samsung,ycbcr-coeff = <0>;
110 samsung,color-depth = <1>;
111 samsung,link-rate = <0x0a>;
112 samsung,lane-count = <2>;
113 samsung,hpd-gpio = <&gpx2 6 0>;
97 114
98 dp_hpd_gpio: dp_hpd_gpio { 115 display-timings {
99 samsung,pins = "gpx2-6"; 116 native-mode = <&timing1>;
100 samsung,pin-function = <0>;
101 samsung,pin-pud = <3>;
102 samsung,pin-drv = <0>;
103 };
104 117
105 hdmi_hpd_irq: hdmi-hpd-irq { 118 timing1: timing@1 {
106 samsung,pins = "gpx3-7"; 119 clock-frequency = <150660000>;
107 samsung,pin-function = <0>; 120 hactive = <1920>;
108 samsung,pin-pud = <1>; 121 vactive = <1080>;
109 samsung,pin-drv = <0>; 122 hfront-porch = <60>;
123 hback-porch = <172>;
124 hsync-len = <80>;
125 vback-porch = <25>;
126 vfront-porch = <10>;
127 vsync-len = <10>;
128 };
110 }; 129 };
111}; 130};
112 131
113&pinctrl_3 { 132&fimd {
114 usb300_vbus_en: usb300-vbus-en { 133 status = "okay";
115 samsung,pins = "gph0-0"; 134 samsung,invert-vclk;
116 samsung,pin-function = <1>; 135};
117 samsung,pin-pud = <0>; 136
118 samsung,pin-drv = <0>; 137&hdmi {
138 status = "okay";
139 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&hdmi_hpd_irq>;
142 ddc = <&i2c_2>;
143};
144
145&hsi2c_7 {
146 status = "okay";
147
148 max98091: codec@10 {
149 compatible = "maxim,max98091";
150 reg = <0x10>;
151 interrupts = <2 0>;
152 interrupt-parent = <&gpx0>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&max98091_irq>;
119 }; 155 };
156};
120 157
121 usb301_vbus_en: usb301-vbus-en { 158&hsi2c_9 {
122 samsung,pins = "gph0-1"; 159 status = "okay";
123 samsung,pin-function = <1>; 160 clock-frequency = <400000>;
124 samsung,pin-pud = <0>; 161
125 samsung,pin-drv = <0>; 162 tpm@20 {
163 compatible = "infineon,slb9645tt";
164 reg = <0x20>;
165
166 /* Unused irq; but still need to configure the pins */
167 pinctrl-names = "default";
168 pinctrl-0 = <&tpm_irq>;
126 }; 169 };
127}; 170};
128 171
129&rtc { 172&i2c_2 {
130 status = "okay"; 173 status = "okay";
174 samsung,i2c-sda-delay = <100>;
175 samsung,i2c-max-bus-freq = <66000>;
176 samsung,i2c-slave-addr = <0x50>;
131}; 177};
132 178
133&uart_3 { 179&i2s0 {
134 status = "okay"; 180 status = "okay";
135}; 181};
136 182
@@ -173,66 +219,210 @@
173 }; 219 };
174}; 220};
175 221
176&dp { 222
177 status = "okay"; 223&pinctrl_0 {
178 pinctrl-names = "default"; 224 pinctrl-names = "default";
179 pinctrl-0 = <&dp_hpd_gpio>; 225 pinctrl-0 = <&mask_tpm_reset>;
180 samsung,color-space = <0>;
181 samsung,dynamic-range = <0>;
182 samsung,ycbcr-coeff = <0>;
183 samsung,color-depth = <1>;
184 samsung,link-rate = <0x0a>;
185 samsung,lane-count = <2>;
186 samsung,hpd-gpio = <&gpx2 6 0>;
187 226
188 display-timings { 227 max98091_irq: max98091-irq {
189 native-mode = <&timing1>; 228 samsung,pins = "gpx0-2";
229 samsung,pin-function = <0>;
230 samsung,pin-pud = <0>;
231 samsung,pin-drv = <0>;
232 };
190 233
191 timing1: timing@1 { 234 /* We need GPX0_6 to be low at sleep time; just keep it low always */
192 clock-frequency = <150660000>; 235 mask_tpm_reset: mask-tpm-reset {
193 hactive = <1920>; 236 samsung,pins = "gpx0-6";
194 vactive = <1080>; 237 samsung,pin-function = <1>;
195 hfront-porch = <60>; 238 samsung,pin-pud = <0>;
196 hback-porch = <172>; 239 samsung,pin-drv = <0>;
197 hsync-len = <80>; 240 samsung,pin-val = <0>;
198 vback-porch = <25>;
199 vfront-porch = <10>;
200 vsync-len = <10>;
201 };
202 }; 241 };
203};
204 242
205&fimd { 243 tpm_irq: tpm-irq {
206 status = "okay"; 244 samsung,pins = "gpx1-0";
207 samsung,invert-vclk; 245 samsung,pin-function = <0>;
246 samsung,pin-pud = <0>;
247 samsung,pin-drv = <0>;
248 };
249
250 power_key_irq: power-key-irq {
251 samsung,pins = "gpx1-2";
252 samsung,pin-function = <0>;
253 samsung,pin-pud = <0>;
254 samsung,pin-drv = <0>;
255 };
256
257 ec_irq: ec-irq {
258 samsung,pins = "gpx1-5";
259 samsung,pin-function = <0>;
260 samsung,pin-pud = <0>;
261 samsung,pin-drv = <0>;
262 };
263
264 tps65090_irq: tps65090-irq {
265 samsung,pins = "gpx2-5";
266 samsung,pin-function = <0>;
267 samsung,pin-pud = <0>;
268 samsung,pin-drv = <0>;
269 };
270
271 dp_hpd_gpio: dp_hpd_gpio {
272 samsung,pins = "gpx2-6";
273 samsung,pin-function = <0>;
274 samsung,pin-pud = <3>;
275 samsung,pin-drv = <0>;
276 };
277
278 hdmi_hpd_irq: hdmi-hpd-irq {
279 samsung,pins = "gpx3-7";
280 samsung,pin-function = <0>;
281 samsung,pin-pud = <1>;
282 samsung,pin-drv = <0>;
283 };
208}; 284};
209 285
210&hsi2c_9 { 286&pinctrl_3 {
211 status = "okay"; 287 /* Drive SPI lines at x2 for better integrity */
212 clock-frequency = <400000>; 288 spi2-bus {
289 samsung,pin-drv = <2>;
290 };
213 291
214 tpm@20 { 292 /* Drive SPI chip select at x2 for better integrity */
215 compatible = "infineon,slb9645tt"; 293 ec_spi_cs: ec-spi-cs {
216 reg = <0x20>; 294 samsung,pins = "gpb1-2";
217 /* Unused irq; but still need to configure the pins */ 295 samsung,pin-function = <1>;
218 pinctrl-names = "default"; 296 samsung,pin-pud = <0>;
219 pinctrl-0 = <&tpm_irq>; 297 samsung,pin-drv = <2>;
298 };
299
300 usb300_vbus_en: usb300-vbus-en {
301 samsung,pins = "gph0-0";
302 samsung,pin-function = <1>;
303 samsung,pin-pud = <0>;
304 samsung,pin-drv = <0>;
305 };
306
307 usb301_vbus_en: usb301-vbus-en {
308 samsung,pins = "gph0-1";
309 samsung,pin-function = <1>;
310 samsung,pin-pud = <0>;
311 samsung,pin-drv = <0>;
220 }; 312 };
221}; 313};
222 314
223&i2c_2 { 315&rtc {
224 status = "okay"; 316 status = "okay";
225 samsung,i2c-sda-delay = <100>;
226 samsung,i2c-max-bus-freq = <66000>;
227 samsung,i2c-slave-addr = <0x50>;
228}; 317};
229 318
230&hdmi { 319&spi_2 {
320 status = "okay";
321 num-cs = <1>;
322 samsung,spi-src-clk = <0>;
323 cs-gpios = <&gpb1 2 0>;
324
325 cros_ec: cros-ec@0 {
326 compatible = "google,cros-ec-spi";
327 interrupt-parent = <&gpx1>;
328 interrupts = <5 0>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&ec_spi_cs &ec_irq>;
331 reg = <0>;
332 spi-max-frequency = <3125000>;
333
334 controller-data {
335 samsung,spi-feedback-delay = <1>;
336 };
337
338 i2c-tunnel {
339 compatible = "google,cros-ec-i2c-tunnel";
340 #address-cells = <1>;
341 #size-cells = <0>;
342 google,remote-bus = <0>;
343
344 battery: sbs-battery@b {
345 compatible = "sbs,sbs-battery";
346 reg = <0xb>;
347 sbs,poll-retry-count = <1>;
348 sbs,i2c-retry-count = <2>;
349 };
350
351 power-regulator@48 {
352 compatible = "ti,tps65090";
353 reg = <0x48>;
354
355 /*
356 * Config irq to disable internal pulls
357 * even though we run in polling mode.
358 */
359 pinctrl-names = "default";
360 pinctrl-0 = <&tps65090_irq>;
361
362 vsys1-supply = <&vbat>;
363 vsys2-supply = <&vbat>;
364 vsys3-supply = <&vbat>;
365 infet1-supply = <&vbat>;
366 infet2-supply = <&vbat>;
367 infet3-supply = <&vbat>;
368 infet4-supply = <&vbat>;
369 infet5-supply = <&vbat>;
370 infet6-supply = <&vbat>;
371 infet7-supply = <&vbat>;
372 vsys-l1-supply = <&vbat>;
373 vsys-l2-supply = <&vbat>;
374
375 regulators {
376 tps65090_dcdc1: dcdc1 {
377 ti,enable-ext-control;
378 };
379 tps65090_dcdc2: dcdc2 {
380 ti,enable-ext-control;
381 };
382 tps65090_dcdc3: dcdc3 {
383 ti,enable-ext-control;
384 };
385 tps65090_fet1: fet1 {
386 regulator-name = "vcd_led";
387 };
388 tps65090_fet2: fet2 {
389 regulator-name = "video_mid";
390 regulator-always-on;
391 };
392 tps65090_fet3: fet3 {
393 regulator-name = "wwan_r";
394 regulator-always-on;
395 };
396 tps65090_fet4: fet4 {
397 regulator-name = "sdcard";
398 regulator-always-on;
399 };
400 tps65090_fet5: fet5 {
401 regulator-name = "camout";
402 };
403 tps65090_fet6: fet6 {
404 regulator-name = "lcd_vdd";
405 };
406 tps65090_fet7: fet7 {
407 regulator-name = "video_mid_1a";
408 regulator-always-on;
409 };
410 tps65090_ldo1: ldo1 {
411 };
412 tps65090_ldo2: ldo2 {
413 };
414 };
415
416 charger {
417 compatible = "ti,tps65090-charger";
418 };
419 };
420 };
421 };
422};
423
424&uart_3 {
231 status = "okay"; 425 status = "okay";
232 hpd-gpio = <&gpx3 7 GPIO_ACTIVE_HIGH>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&hdmi_hpd_irq>;
235 ddc = <&i2c_2>;
236}; 426};
237 427
238&usbdrd_phy0 { 428&usbdrd_phy0 {
@@ -251,3 +441,5 @@
251&watchdog { 441&watchdog {
252 timeout-sec = <32>; 442 timeout-sec = <32>;
253}; 443};
444
445#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/ge863-pro3.dtsi b/arch/arm/boot/dts/ge863-pro3.dtsi
index 230099bb31c8..0d0e62489d93 100644
--- a/arch/arm/boot/dts/ge863-pro3.dtsi
+++ b/arch/arm/boot/dts/ge863-pro3.dtsi
@@ -19,6 +19,10 @@
19 compatible = "atmel,osc", "fixed-clock"; 19 compatible = "atmel,osc", "fixed-clock";
20 clock-frequency = <6000000>; 20 clock-frequency = <6000000>;
21 }; 21 };
22
23 main_xtal {
24 clock-frequency = <6000000>;
25 };
22 }; 26 };
23 27
24 ahb { 28 ahb {
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
new file mode 100644
index 000000000000..68d0834a2d1e
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -0,0 +1,73 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "imx25-eukrea-mbimxsd25-baseboard.dts"
15
16/ {
17 model = "Eukrea MBIMXSD25 with the CMO-QVGA Display";
18 compatible = "eukrea,mbimxsd25-baseboard-cmo-qvga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
19
20 cmo_qvga: display {
21 model = "CMO-QVGA";
22 bits-per-pixel = <16>;
23 fsl,pcr = <0xcad08b80>;
24 bus-width = <18>;
25 native-mode = <&qvga_timings>;
26 display-timings {
27 qvga_timings: 320x240 {
28 clock-frequency = <6500000>;
29 hactive = <320>;
30 vactive = <240>;
31 hback-porch = <30>;
32 hfront-porch = <38>;
33 vback-porch = <20>;
34 vfront-porch = <3>;
35 hsync-len = <15>;
36 vsync-len = <4>;
37 };
38 };
39 };
40
41 regulators {
42 compatible = "simple-bus";
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 reg_lcd_3v3: regulator@0 {
47 compatible = "regulator-fixed";
48 reg = <0>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_reg_lcd_3v3>;
51 regulator-name = "lcd-3v3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57 };
58};
59
60&iomuxc {
61 imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
62 pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
63 fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
64 };
65 };
66};
67
68&lcdc {
69 display = <&cmo_qvga>;
70 fsl,lpccr = <0x00a903ff>;
71 lcd-supply = <&reg_lcd_3v3>;
72 status = "okay";
73};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
new file mode 100644
index 000000000000..8eee2f65fe00
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-svga.dts
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "imx25-eukrea-mbimxsd25-baseboard.dts"
15
16/ {
17 model = "Eukrea MBIMXSD25 with the DVI-SVGA Display";
18 compatible = "eukrea,mbimxsd25-baseboard-dvi-svga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
19
20 dvi_svga: display {
21 model = "DVI-SVGA";
22 bits-per-pixel = <16>;
23 fsl,pcr = <0xfa208b80>;
24 bus-width = <18>;
25 native-mode = <&dvi_svga_timings>;
26 display-timings {
27 dvi_svga_timings: 800x600 {
28 clock-frequency = <40000000>;
29 hactive = <800>;
30 vactive = <600>;
31 hback-porch = <75>;
32 hfront-porch = <75>;
33 vback-porch = <7>;
34 vfront-porch = <75>;
35 hsync-len = <7>;
36 vsync-len = <7>;
37 };
38 };
39 };
40};
41
42&lcdc {
43 display = <&dvi_svga>;
44 status = "okay";
45};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
new file mode 100644
index 000000000000..447da6263169
--- /dev/null
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-dvi-vga.dts
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include "imx25-eukrea-mbimxsd25-baseboard.dts"
15
16/ {
17 model = "Eukrea MBIMXSD25 with the DVI-VGA Display";
18 compatible = "eukrea,mbimxsd25-baseboard-dvi-vga", "eukrea,mbimxsd25-baseboard", "eukrea,cpuimx25", "fsl,imx25";
19
20 dvi_vga: display {
21 model = "DVI-VGA";
22 bits-per-pixel = <16>;
23 fsl,pcr = <0xfa208b80>;
24 bus-width = <18>;
25 native-mode = <&dvi_vga_timings>;
26 display-timings {
27 dvi_vga_timings: 640x480 {
28 clock-frequency = <31250000>;
29 hactive = <640>;
30 vactive = <480>;
31 hback-porch = <100>;
32 hfront-porch = <100>;
33 vback-porch = <7>;
34 vfront-porch = <100>;
35 hsync-len = <7>;
36 vsync-len = <7>;
37 };
38 };
39 };
40};
41
42&lcdc {
43 display = <&dvi_vga>;
44 status = "okay";
45};
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index ad12da38fc92..ed1d0b4578ef 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -155,7 +155,6 @@
155 155
156&ssi1 { 156&ssi1 {
157 codec-handle = <&tlv320aic23>; 157 codec-handle = <&tlv320aic23>;
158 fsl,mode = "i2s-slave";
159 status = "okay"; 158 status = "okay";
160}; 159};
161 160
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index c608942b8a3b..9c21b1583762 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -233,7 +233,6 @@
233 233
234&ssi1 { 234&ssi1 {
235 codec-handle = <&codec>; 235 codec-handle = <&codec>;
236 fsl,mode = "i2s-slave";
237 status = "okay"; 236 status = "okay";
238}; 237};
239 238
@@ -249,3 +248,10 @@
249 dr_mode = "host"; 248 dr_mode = "host";
250 status = "okay"; 249 status = "okay";
251}; 250};
251
252&usbotg {
253 phy_type = "utmi";
254 dr_mode = "otg";
255 external-vbus-divider;
256 status = "okay";
257};
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index bb74d9582b7e..c1740396b2c9 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -312,7 +312,7 @@
312 gpt4: timer@53f84000 { 312 gpt4: timer@53f84000 {
313 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; 313 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
314 reg = <0x53f84000 0x4000>; 314 reg = <0x53f84000 0x4000>;
315 clocks = <&clks 9>, <&clks 45>; 315 clocks = <&clks 95>, <&clks 47>;
316 clock-names = "ipg", "per"; 316 clock-names = "ipg", "per";
317 interrupts = <1>; 317 interrupts = <1>;
318 }; 318 };
@@ -320,7 +320,7 @@
320 gpt3: timer@53f88000 { 320 gpt3: timer@53f88000 {
321 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; 321 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
322 reg = <0x53f88000 0x4000>; 322 reg = <0x53f88000 0x4000>;
323 clocks = <&clks 9>, <&clks 47>; 323 clocks = <&clks 94>, <&clks 47>;
324 clock-names = "ipg", "per"; 324 clock-names = "ipg", "per";
325 interrupts = <29>; 325 interrupts = <29>;
326 }; 326 };
@@ -328,7 +328,7 @@
328 gpt2: timer@53f8c000 { 328 gpt2: timer@53f8c000 {
329 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; 329 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
330 reg = <0x53f8c000 0x4000>; 330 reg = <0x53f8c000 0x4000>;
331 clocks = <&clks 9>, <&clks 47>; 331 clocks = <&clks 93>, <&clks 47>;
332 clock-names = "ipg", "per"; 332 clock-names = "ipg", "per";
333 interrupts = <53>; 333 interrupts = <53>;
334 }; 334 };
@@ -336,7 +336,7 @@
336 gpt1: timer@53f90000 { 336 gpt1: timer@53f90000 {
337 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt"; 337 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
338 reg = <0x53f90000 0x4000>; 338 reg = <0x53f90000 0x4000>;
339 clocks = <&clks 9>, <&clks 47>; 339 clocks = <&clks 92>, <&clks 47>;
340 clock-names = "ipg", "per"; 340 clock-names = "ipg", "per";
341 interrupts = <54>; 341 interrupts = <54>;
342 }; 342 };
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
new file mode 100644
index 000000000000..e2242638ea0b
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -0,0 +1,296 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx27.dtsi"
14
15/ {
16 model = "Eukrea CPUIMX27";
17 compatible = "eukrea,cpuimx27", "fsl,imx27";
18
19 memory {
20 reg = <0xa0000000 0x04000000>;
21 };
22
23 clocks {
24 #address-cells = <1>;
25 #size-cells = <0>;
26 compatible = "simple-bus";
27
28 clk14745600: clock@0 {
29 #clock-cells = <0>;
30 compatible = "fixed-clock";
31 clock-frequency = <14745600>;
32 reg = <0>;
33 };
34 };
35};
36
37&fec {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_fec>;
40 status = "okay";
41};
42
43&i2c1 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_i2c1>;
46 status = "okay";
47
48 pcf8563@51 {
49 compatible = "nxp,pcf8563";
50 reg = <0x51>;
51 };
52};
53
54&nfc {
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_nfc>;
57 nand-bus-width = <8>;
58 nand-ecc-mode = "hw";
59 nand-on-flash-bbt;
60 status = "okay";
61};
62
63&owire {
64 pinctrl-names = "default";
65 pinctrl-0 = <&pinctrl_owire>;
66 status = "okay";
67};
68
69&sdhci2 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_sdhc2>;
72 bus-width = <4>;
73 non-removable;
74 status = "okay";
75};
76
77&uart4 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_uart4>;
80 fsl,uart-has-rtscts;
81 status = "okay";
82};
83
84&usbh2 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&pinctrl_usbh2>;
87 dr_mode = "host";
88 phy_type = "ulpi";
89 disable-over-current;
90 status = "okay";
91};
92
93&usbotg {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_usbotg>;
96 dr_mode = "otg";
97 phy_type = "ulpi";
98 disable-over-current;
99 status = "okay";
100};
101
102&weim {
103 status = "okay";
104
105 nor: nor@0,0 {
106 #address-cells = <1>;
107 #size-cells = <1>;
108 compatible = "cfi-flash";
109 reg = <0 0x00000000 0x04000000>;
110 bank-width = <2>;
111 linux,mtd-name = "physmap-flash.0";
112 fsl,weim-cs-timing = <0x00008f03 0xa0330d01 0x002208c0>;
113 };
114
115 uart8250@3,200000 {
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_uart8250_1>;
118 compatible = "ns8250";
119 clocks = <&clk14745600>;
120 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
121 interrupts = <&gpio2 23 IRQ_TYPE_LEVEL_LOW>;
122 reg = <3 0x200000 0x1000>;
123 reg-shift = <1>;
124 reg-io-width = <1>;
125 no-loopback-test;
126 };
127
128 uart8250@3,400000 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_uart8250_2>;
131 compatible = "ns8250";
132 clocks = <&clk14745600>;
133 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
134 interrupts = <&gpio2 22 IRQ_TYPE_LEVEL_LOW>;
135 reg = <3 0x400000 0x1000>;
136 reg-shift = <1>;
137 reg-io-width = <1>;
138 no-loopback-test;
139 };
140
141 uart8250@3,800000 {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_uart8250_3>;
144 compatible = "ns8250";
145 clocks = <&clk14745600>;
146 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
147 interrupts = <&gpio2 27 IRQ_TYPE_LEVEL_LOW>;
148 reg = <3 0x800000 0x1000>;
149 reg-shift = <1>;
150 reg-io-width = <1>;
151 no-loopback-test;
152 };
153
154 uart8250@3,1000000 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_uart8250_4>;
157 compatible = "ns8250";
158 clocks = <&clk14745600>;
159 fsl,weim-cs-timing = <0x0000d603 0x0d1d0d01 0x00d20000>;
160 interrupts = <&gpio2 30 IRQ_TYPE_LEVEL_LOW>;
161 reg = <3 0x1000000 0x1000>;
162 reg-shift = <1>;
163 reg-io-width = <1>;
164 no-loopback-test;
165 };
166};
167
168&iomuxc {
169 imx27-eukrea-cpuimx27 {
170 pinctrl_fec: fecgrp {
171 fsl,pins = <
172 MX27_PAD_SD3_CMD__FEC_TXD0 0x0
173 MX27_PAD_SD3_CLK__FEC_TXD1 0x0
174 MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
175 MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
176 MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
177 MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
178 MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
179 MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
180 MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
181 MX27_PAD_ATA_DATA7__FEC_MDC 0x0
182 MX27_PAD_ATA_DATA8__FEC_CRS 0x0
183 MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
184 MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
185 MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
186 MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
187 MX27_PAD_ATA_DATA13__FEC_COL 0x0
188 MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
189 MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
190 >;
191 };
192
193 pinctrl_i2c1: i2c1grp {
194 fsl,pins = <
195 MX27_PAD_I2C_DATA__I2C_DATA 0x0
196 MX27_PAD_I2C_CLK__I2C_CLK 0x0
197 >;
198 };
199
200 pinctrl_nfc: nfcgrp {
201 fsl,pins = <
202 MX27_PAD_NFRB__NFRB 0x0
203 MX27_PAD_NFCLE__NFCLE 0x0
204 MX27_PAD_NFWP_B__NFWP_B 0x0
205 MX27_PAD_NFCE_B__NFCE_B 0x0
206 MX27_PAD_NFALE__NFALE 0x0
207 MX27_PAD_NFRE_B__NFRE_B 0x0
208 MX27_PAD_NFWE_B__NFWE_B 0x0
209 >;
210 };
211
212 pinctrl_owire: owiregrp {
213 fsl,pins = <
214 MX27_PAD_RTCK__OWIRE 0x0
215 >;
216 };
217
218 pinctrl_sdhc2: sdhc2grp {
219 fsl,pins = <
220 MX27_PAD_SD2_CLK__SD2_CLK 0x0
221 MX27_PAD_SD2_CMD__SD2_CMD 0x0
222 MX27_PAD_SD2_D0__SD2_D0 0x0
223 MX27_PAD_SD2_D1__SD2_D1 0x0
224 MX27_PAD_SD2_D2__SD2_D2 0x0
225 MX27_PAD_SD2_D3__SD2_D3 0x0
226 >;
227 };
228
229 pinctrl_uart4: uart4grp {
230 fsl,pins = <
231 MX27_PAD_USBH1_TXDM__UART4_TXD 0x0
232 MX27_PAD_USBH1_RXDP__UART4_RXD 0x0
233 MX27_PAD_USBH1_TXDP__UART4_CTS 0x0
234 MX27_PAD_USBH1_FS__UART4_RTS 0x0
235 >;
236 };
237
238 pinctrl_uart8250_1: uart82501grp {
239 fsl,pins = <
240 MX27_PAD_USB_PWR__GPIO2_23 0x0
241 >;
242 };
243
244 pinctrl_uart8250_2: uart82502grp {
245 fsl,pins = <
246 MX27_PAD_USBH1_SUSP__GPIO2_22 0x0
247 >;
248 };
249
250 pinctrl_uart8250_3: uart82503grp {
251 fsl,pins = <
252 MX27_PAD_USBH1_OE_B__GPIO2_27 0x0
253 >;
254 };
255
256 pinctrl_uart8250_4: uart82504grp {
257 fsl,pins = <
258 MX27_PAD_USBH1_RXDM__GPIO2_30 0x0
259 >;
260 };
261
262 pinctrl_usbh2: usbh2grp {
263 fsl,pins = <
264 MX27_PAD_USBH2_CLK__USBH2_CLK 0x0
265 MX27_PAD_USBH2_DIR__USBH2_DIR 0x0
266 MX27_PAD_USBH2_NXT__USBH2_NXT 0x0
267 MX27_PAD_USBH2_STP__USBH2_STP 0x0
268 MX27_PAD_CSPI2_SCLK__USBH2_DATA0 0x0
269 MX27_PAD_CSPI2_MOSI__USBH2_DATA1 0x0
270 MX27_PAD_CSPI2_MISO__USBH2_DATA2 0x0
271 MX27_PAD_CSPI2_SS1__USBH2_DATA3 0x0
272 MX27_PAD_CSPI2_SS2__USBH2_DATA4 0x0
273 MX27_PAD_CSPI1_SS2__USBH2_DATA5 0x0
274 MX27_PAD_CSPI2_SS0__USBH2_DATA6 0x0
275 MX27_PAD_USBH2_DATA7__USBH2_DATA7 0x0
276 >;
277 };
278
279 pinctrl_usbotg: usbotggrp {
280 fsl,pins = <
281 MX27_PAD_USBOTG_CLK__USBOTG_CLK 0x0
282 MX27_PAD_USBOTG_DIR__USBOTG_DIR 0x0
283 MX27_PAD_USBOTG_NXT__USBOTG_NXT 0x0
284 MX27_PAD_USBOTG_STP__USBOTG_STP 0x0
285 MX27_PAD_USBOTG_DATA0__USBOTG_DATA0 0x0
286 MX27_PAD_USBOTG_DATA1__USBOTG_DATA1 0x0
287 MX27_PAD_USBOTG_DATA2__USBOTG_DATA2 0x0
288 MX27_PAD_USBOTG_DATA3__USBOTG_DATA3 0x0
289 MX27_PAD_USBOTG_DATA4__USBOTG_DATA4 0x0
290 MX27_PAD_USBOTG_DATA5__USBOTG_DATA5 0x0
291 MX27_PAD_USBOTG_DATA6__USBOTG_DATA6 0x0
292 MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
293 >;
294 };
295 };
296};
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
new file mode 100644
index 000000000000..2ab65fc4c1e1
--- /dev/null
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -0,0 +1,273 @@
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx27-eukrea-cpuimx27.dtsi"
13
14/ {
15 model = "Eukrea MBIMXSD27";
16 compatible = "eukrea,mbimxsd27-baseboard", "eukrea,cpuimx27", "fsl,imx27";
17
18 display0: CMO-QVGA {
19 model = "CMO-QVGA";
20 native-mode = <&timing0>;
21 bits-per-pixel = <16>;
22 fsl,pcr = <0xfad08b80>;
23
24 display-timings {
25 timing0: 320x240 {
26 clock-frequency = <6500000>;
27 hactive = <320>;
28 vactive = <240>;
29 hback-porch = <20>;
30 hsync-len = <30>;
31 hfront-porch = <38>;
32 vback-porch = <4>;
33 vsync-len = <3>;
34 vfront-porch = <15>;
35 };
36 };
37 };
38
39 backlight {
40 compatible = "gpio-backlight";
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_backlight>;
43 gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
44 };
45
46 leds {
47 compatible = "gpio-leds";
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_gpioleds>;
50
51 led1 {
52 label = "system::live";
53 gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
54 linux,default-trigger = "heartbeat";
55 };
56
57 led2 {
58 label = "system::user";
59 gpios = <&gpio6 19 GPIO_ACTIVE_LOW>;
60 };
61 };
62
63 regulators {
64 #address-cells = <1>;
65 #size-cells = <0>;
66 compatible = "simple-bus";
67
68 reg_lcd: regulator@0 {
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_lcdreg>;
71 compatible = "regulator-fixed";
72 reg = <0>;
73 regulator-name = "LCD";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
77 enable-active-high;
78 };
79 };
80};
81
82&cspi1 {
83 pinctrl-0 = <&pinctrl_cspi1>;
84 fsl,spi-num-chipselects = <1>;
85 cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
86 status = "okay";
87
88 ads7846 {
89 compatible = "ti,ads7846";
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_touch>;
92 reg = <0>;
93 interrupts = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>;
94 spi-cpol;
95 spi-max-frequency = <1500000>;
96 ti,keep-vref-on;
97 };
98};
99
100&fb {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_imxfb>;
103 display = <&display0>;
104 lcd-supply = <&reg_lcd>;
105 fsl,dmacr = <0x00040060>;
106 fsl,lscr1 = <0x00120300>;
107 fsl,lpccr = <0x00a903ff>;
108 status = "okay";
109};
110
111&i2c1 {
112 codec: codec@1a {
113 compatible = "ti,tlv320aic23";
114 reg = <0x1a>;
115 };
116};
117
118&kpp {
119 linux,keymap = <
120 MATRIX_KEY(0, 0, KEY_UP)
121 MATRIX_KEY(0, 1, KEY_DOWN)
122 MATRIX_KEY(1, 0, KEY_RIGHT)
123 MATRIX_KEY(1, 1, KEY_LEFT)
124 >;
125 status = "okay";
126};
127
128&sdhci1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_sdhc1>;
131 bus-width = <4>;
132 status = "okay";
133};
134
135&ssi1 {
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ssi1>;
138 codec-handle = <&codec>;
139 status = "okay";
140};
141
142&uart1 {
143 fsl,uart-has-rtscts;
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_uart1>;
146 status = "okay";
147};
148
149&uart2 {
150 fsl,uart-has-rtscts;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart2>;
153 status = "okay";
154};
155
156&uart3 {
157 fsl,uart-has-rtscts;
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_uart3>;
160 status = "okay";
161};
162
163&iomuxc {
164 imx27-eukrea-cpuimx27-baseboard {
165 pinctrl_cspi1: cspi1grp {
166 fsl,pins = <
167 MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
168 MX27_PAD_CSPI1_MOSI__CSPI1_MOSI 0x0
169 MX27_PAD_CSPI1_SCLK__CSPI1_SCLK 0x0
170 MX27_PAD_CSPI1_SS0__GPIO4_28 0x0 /* CS0 */
171 >;
172 };
173
174 pinctrl_backlight: backlightgrp {
175 fsl,pins = <
176 MX27_PAD_PWMO__GPIO5_5 0x0
177 >;
178 };
179
180 pinctrl_gpioleds: gpioledsgrp {
181 fsl,pins = <
182 MX27_PAD_PC_PWRON__GPIO6_16 0x0
183 MX27_PAD_PC_CD2_B__GPIO6_19 0x0
184 >;
185 };
186
187 pinctrl_imxfb: imxfbgrp {
188 fsl,pins = <
189 MX27_PAD_LD0__LD0 0x0
190 MX27_PAD_LD1__LD1 0x0
191 MX27_PAD_LD2__LD2 0x0
192 MX27_PAD_LD3__LD3 0x0
193 MX27_PAD_LD4__LD4 0x0
194 MX27_PAD_LD5__LD5 0x0
195 MX27_PAD_LD6__LD6 0x0
196 MX27_PAD_LD7__LD7 0x0
197 MX27_PAD_LD8__LD8 0x0
198 MX27_PAD_LD9__LD9 0x0
199 MX27_PAD_LD10__LD10 0x0
200 MX27_PAD_LD11__LD11 0x0
201 MX27_PAD_LD12__LD12 0x0
202 MX27_PAD_LD13__LD13 0x0
203 MX27_PAD_LD14__LD14 0x0
204 MX27_PAD_LD15__LD15 0x0
205 MX27_PAD_LD16__LD16 0x0
206 MX27_PAD_LD17__LD17 0x0
207 MX27_PAD_CONTRAST__CONTRAST 0x0
208 MX27_PAD_OE_ACD__OE_ACD 0x0
209 MX27_PAD_HSYNC__HSYNC 0x0
210 MX27_PAD_VSYNC__VSYNC 0x0
211 >;
212 };
213
214 pinctrl_lcdreg: lcdreggrp {
215 fsl,pins = <
216 MX27_PAD_CLS__GPIO1_25 0x0
217 >;
218 };
219
220 pinctrl_sdhc1: sdhc1grp {
221 fsl,pins = <
222 MX27_PAD_SD1_CLK__SD1_CLK 0x0
223 MX27_PAD_SD1_CMD__SD1_CMD 0x0
224 MX27_PAD_SD1_D0__SD1_D0 0x0
225 MX27_PAD_SD1_D1__SD1_D1 0x0
226 MX27_PAD_SD1_D2__SD1_D2 0x0
227 MX27_PAD_SD1_D3__SD1_D3 0x0
228 >;
229 };
230
231 pinctrl_ssi1: ssi1grp {
232 fsl,pins = <
233 MX27_PAD_SSI4_CLK__SSI4_CLK 0x0
234 MX27_PAD_SSI4_FS__SSI4_FS 0x0
235 MX27_PAD_SSI4_RXDAT__SSI4_RXDAT 0x1
236 MX27_PAD_SSI4_TXDAT__SSI4_TXDAT 0x1
237 >;
238 };
239
240 pinctrl_touch: touchgrp {
241 fsl,pins = <
242 MX27_PAD_CSPI1_RDY__GPIO4_25 0x0 /* IRQ */
243 >;
244 };
245
246 pinctrl_uart1: uart1grp {
247 fsl,pins = <
248 MX27_PAD_UART1_TXD__UART1_TXD 0x0
249 MX27_PAD_UART1_RXD__UART1_RXD 0x0
250 MX27_PAD_UART1_CTS__UART1_CTS 0x0
251 MX27_PAD_UART1_RTS__UART1_RTS 0x0
252 >;
253 };
254
255 pinctrl_uart2: uart2grp {
256 fsl,pins = <
257 MX27_PAD_UART2_TXD__UART2_TXD 0x0
258 MX27_PAD_UART2_RXD__UART2_RXD 0x0
259 MX27_PAD_UART2_CTS__UART2_CTS 0x0
260 MX27_PAD_UART2_RTS__UART2_RTS 0x0
261 >;
262 };
263
264 pinctrl_uart3: uart3grp {
265 fsl,pins = <
266 MX27_PAD_UART3_TXD__UART3_TXD 0x0
267 MX27_PAD_UART3_RXD__UART3_RXD 0x0
268 MX27_PAD_UART3_CTS__UART3_CTS 0x0
269 MX27_PAD_UART3_RTS__UART3_RTS 0x0
270 >;
271 };
272 };
273};
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 4c317716b510..49450dbbcab8 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -28,7 +28,7 @@
28 usbphy0: usbphy@0 { 28 usbphy0: usbphy@0 {
29 compatible = "usb-nop-xceiv"; 29 compatible = "usb-nop-xceiv";
30 reg = <0>; 30 reg = <0>;
31 clocks = <&clks 0>; 31 clocks = <&clks IMX27_CLK_DUMMY>;
32 clock-names = "main_clk"; 32 clock-names = "main_clk";
33 }; 33 };
34 }; 34 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index fe02bc7a24fd..538568b0de26 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -61,7 +61,7 @@
61 compatible = "usb-nop-xceiv"; 61 compatible = "usb-nop-xceiv";
62 reg = <2>; 62 reg = <2>;
63 vcc-supply = <&reg_5v0>; 63 vcc-supply = <&reg_5v0>;
64 clocks = <&clks 0>; 64 clocks = <&clks IMX27_CLK_DUMMY>;
65 clock-names = "main_clk"; 65 clock-names = "main_clk";
66 }; 66 };
67 }; 67 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index 31e9f7049f73..b4e955e3be8d 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -51,7 +51,7 @@
51 compatible = "usb-nop-xceiv"; 51 compatible = "usb-nop-xceiv";
52 reg = <0>; 52 reg = <0>;
53 vcc-supply = <&sw3_reg>; 53 vcc-supply = <&sw3_reg>;
54 clocks = <&clks 0>; 54 clocks = <&clks IMX27_CLK_DUMMY>;
55 clock-names = "main_clk"; 55 clock-names = "main_clk";
56 }; 56 };
57 }; 57 };
@@ -310,7 +310,6 @@
310&ssi1 { 310&ssi1 {
311 pinctrl-names = "default"; 311 pinctrl-names = "default";
312 pinctrl-0 = <&pinctrl_ssi1>; 312 pinctrl-0 = <&pinctrl_ssi1>;
313 fsl,mode = "i2s-slave";
314 status = "okay"; 313 status = "okay";
315}; 314};
316 315
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index a75555c39533..107d713e1cbe 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -11,9 +11,11 @@
11 11
12#include "skeleton.dtsi" 12#include "skeleton.dtsi"
13#include "imx27-pinfunc.h" 13#include "imx27-pinfunc.h"
14
15#include <dt-bindings/clock/imx27-clock.h>
16#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/input/input.h> 17#include <dt-bindings/input/input.h>
15#include <dt-bindings/interrupt-controller/irq.h> 18#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/gpio/gpio.h>
17 19
18/ { 20/ {
19 aliases { 21 aliases {
@@ -68,7 +70,7 @@
68 399000 1450000 70 399000 1450000
69 >; 71 >;
70 clock-latency = <62500>; 72 clock-latency = <62500>;
71 clocks = <&clks 18>; 73 clocks = <&clks IMX27_CLK_CPU_DIV>;
72 voltage-tolerance = <5>; 74 voltage-tolerance = <5>;
73 }; 75 };
74 }; 76 };
@@ -91,7 +93,8 @@
91 compatible = "fsl,imx27-dma"; 93 compatible = "fsl,imx27-dma";
92 reg = <0x10001000 0x1000>; 94 reg = <0x10001000 0x1000>;
93 interrupts = <32>; 95 interrupts = <32>;
94 clocks = <&clks 50>, <&clks 70>; 96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
95 clock-names = "ipg", "ahb"; 98 clock-names = "ipg", "ahb";
96 #dma-cells = <1>; 99 #dma-cells = <1>;
97 #dma-channels = <16>; 100 #dma-channels = <16>;
@@ -101,14 +104,15 @@
101 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt"; 104 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
102 reg = <0x10002000 0x1000>; 105 reg = <0x10002000 0x1000>;
103 interrupts = <27>; 106 interrupts = <27>;
104 clocks = <&clks 74>; 107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
105 }; 108 };
106 109
107 gpt1: timer@10003000 { 110 gpt1: timer@10003000 {
108 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 111 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
109 reg = <0x10003000 0x1000>; 112 reg = <0x10003000 0x1000>;
110 interrupts = <26>; 113 interrupts = <26>;
111 clocks = <&clks 46>, <&clks 61>; 114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
112 clock-names = "ipg", "per"; 116 clock-names = "ipg", "per";
113 }; 117 };
114 118
@@ -116,7 +120,8 @@
116 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 120 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
117 reg = <0x10004000 0x1000>; 121 reg = <0x10004000 0x1000>;
118 interrupts = <25>; 122 interrupts = <25>;
119 clocks = <&clks 45>, <&clks 61>; 123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
120 clock-names = "ipg", "per"; 125 clock-names = "ipg", "per";
121 }; 126 };
122 127
@@ -124,7 +129,8 @@
124 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 129 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
125 reg = <0x10005000 0x1000>; 130 reg = <0x10005000 0x1000>;
126 interrupts = <24>; 131 interrupts = <24>;
127 clocks = <&clks 44>, <&clks 61>; 132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
128 clock-names = "ipg", "per"; 134 clock-names = "ipg", "per";
129 }; 135 };
130 136
@@ -133,7 +139,8 @@
133 compatible = "fsl,imx27-pwm"; 139 compatible = "fsl,imx27-pwm";
134 reg = <0x10006000 0x1000>; 140 reg = <0x10006000 0x1000>;
135 interrupts = <23>; 141 interrupts = <23>;
136 clocks = <&clks 34>, <&clks 61>; 142 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
143 <&clks IMX27_CLK_PER1_GATE>;
137 clock-names = "ipg", "per"; 144 clock-names = "ipg", "per";
138 }; 145 };
139 146
@@ -141,14 +148,14 @@
141 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp"; 148 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
142 reg = <0x10008000 0x1000>; 149 reg = <0x10008000 0x1000>;
143 interrupts = <21>; 150 interrupts = <21>;
144 clocks = <&clks 37>; 151 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
145 status = "disabled"; 152 status = "disabled";
146 }; 153 };
147 154
148 owire: owire@10009000 { 155 owire: owire@10009000 {
149 compatible = "fsl,imx27-owire", "fsl,imx21-owire"; 156 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
150 reg = <0x10009000 0x1000>; 157 reg = <0x10009000 0x1000>;
151 clocks = <&clks 35>; 158 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
152 status = "disabled"; 159 status = "disabled";
153 }; 160 };
154 161
@@ -156,7 +163,8 @@
156 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 163 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
157 reg = <0x1000a000 0x1000>; 164 reg = <0x1000a000 0x1000>;
158 interrupts = <20>; 165 interrupts = <20>;
159 clocks = <&clks 81>, <&clks 61>; 166 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
167 <&clks IMX27_CLK_PER1_GATE>;
160 clock-names = "ipg", "per"; 168 clock-names = "ipg", "per";
161 status = "disabled"; 169 status = "disabled";
162 }; 170 };
@@ -165,7 +173,8 @@
165 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 173 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
166 reg = <0x1000b000 0x1000>; 174 reg = <0x1000b000 0x1000>;
167 interrupts = <19>; 175 interrupts = <19>;
168 clocks = <&clks 80>, <&clks 61>; 176 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
177 <&clks IMX27_CLK_PER1_GATE>;
169 clock-names = "ipg", "per"; 178 clock-names = "ipg", "per";
170 status = "disabled"; 179 status = "disabled";
171 }; 180 };
@@ -174,7 +183,8 @@
174 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 183 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
175 reg = <0x1000c000 0x1000>; 184 reg = <0x1000c000 0x1000>;
176 interrupts = <18>; 185 interrupts = <18>;
177 clocks = <&clks 79>, <&clks 61>; 186 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
187 <&clks IMX27_CLK_PER1_GATE>;
178 clock-names = "ipg", "per"; 188 clock-names = "ipg", "per";
179 status = "disabled"; 189 status = "disabled";
180 }; 190 };
@@ -183,7 +193,8 @@
183 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 193 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
184 reg = <0x1000d000 0x1000>; 194 reg = <0x1000d000 0x1000>;
185 interrupts = <17>; 195 interrupts = <17>;
186 clocks = <&clks 78>, <&clks 61>; 196 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
197 <&clks IMX27_CLK_PER1_GATE>;
187 clock-names = "ipg", "per"; 198 clock-names = "ipg", "per";
188 status = "disabled"; 199 status = "disabled";
189 }; 200 };
@@ -194,7 +205,8 @@
194 compatible = "fsl,imx27-cspi"; 205 compatible = "fsl,imx27-cspi";
195 reg = <0x1000e000 0x1000>; 206 reg = <0x1000e000 0x1000>;
196 interrupts = <16>; 207 interrupts = <16>;
197 clocks = <&clks 53>, <&clks 60>; 208 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
209 <&clks IMX27_CLK_PER2_GATE>;
198 clock-names = "ipg", "per"; 210 clock-names = "ipg", "per";
199 status = "disabled"; 211 status = "disabled";
200 }; 212 };
@@ -205,7 +217,8 @@
205 compatible = "fsl,imx27-cspi"; 217 compatible = "fsl,imx27-cspi";
206 reg = <0x1000f000 0x1000>; 218 reg = <0x1000f000 0x1000>;
207 interrupts = <15>; 219 interrupts = <15>;
208 clocks = <&clks 52>, <&clks 60>; 220 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
221 <&clks IMX27_CLK_PER2_GATE>;
209 clock-names = "ipg", "per"; 222 clock-names = "ipg", "per";
210 status = "disabled"; 223 status = "disabled";
211 }; 224 };
@@ -215,7 +228,7 @@
215 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; 228 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
216 reg = <0x10010000 0x1000>; 229 reg = <0x10010000 0x1000>;
217 interrupts = <14>; 230 interrupts = <14>;
218 clocks = <&clks 26>; 231 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
219 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>; 232 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
220 dma-names = "rx0", "tx0", "rx1", "tx1"; 233 dma-names = "rx0", "tx0", "rx1", "tx1";
221 fsl,fifo-depth = <8>; 234 fsl,fifo-depth = <8>;
@@ -227,7 +240,7 @@
227 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi"; 240 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
228 reg = <0x10011000 0x1000>; 241 reg = <0x10011000 0x1000>;
229 interrupts = <13>; 242 interrupts = <13>;
230 clocks = <&clks 25>; 243 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
231 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>; 244 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
232 dma-names = "rx0", "tx0", "rx1", "tx1"; 245 dma-names = "rx0", "tx0", "rx1", "tx1";
233 fsl,fifo-depth = <8>; 246 fsl,fifo-depth = <8>;
@@ -240,7 +253,7 @@
240 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 253 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
241 reg = <0x10012000 0x1000>; 254 reg = <0x10012000 0x1000>;
242 interrupts = <12>; 255 interrupts = <12>;
243 clocks = <&clks 40>; 256 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
244 status = "disabled"; 257 status = "disabled";
245 }; 258 };
246 259
@@ -248,7 +261,8 @@
248 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 261 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
249 reg = <0x10013000 0x1000>; 262 reg = <0x10013000 0x1000>;
250 interrupts = <11>; 263 interrupts = <11>;
251 clocks = <&clks 30>, <&clks 60>; 264 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
265 <&clks IMX27_CLK_PER2_GATE>;
252 clock-names = "ipg", "per"; 266 clock-names = "ipg", "per";
253 dmas = <&dma 7>; 267 dmas = <&dma 7>;
254 dma-names = "rx-tx"; 268 dma-names = "rx-tx";
@@ -259,7 +273,8 @@
259 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 273 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
260 reg = <0x10014000 0x1000>; 274 reg = <0x10014000 0x1000>;
261 interrupts = <10>; 275 interrupts = <10>;
262 clocks = <&clks 29>, <&clks 60>; 276 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
277 <&clks IMX27_CLK_PER2_GATE>;
263 clock-names = "ipg", "per"; 278 clock-names = "ipg", "per";
264 dmas = <&dma 6>; 279 dmas = <&dma 6>;
265 dma-names = "rx-tx"; 280 dma-names = "rx-tx";
@@ -276,6 +291,7 @@
276 gpio1: gpio@10015000 { 291 gpio1: gpio@10015000 {
277 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 292 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
278 reg = <0x10015000 0x100>; 293 reg = <0x10015000 0x100>;
294 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
279 interrupts = <8>; 295 interrupts = <8>;
280 gpio-controller; 296 gpio-controller;
281 #gpio-cells = <2>; 297 #gpio-cells = <2>;
@@ -286,6 +302,7 @@
286 gpio2: gpio@10015100 { 302 gpio2: gpio@10015100 {
287 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 303 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
288 reg = <0x10015100 0x100>; 304 reg = <0x10015100 0x100>;
305 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
289 interrupts = <8>; 306 interrupts = <8>;
290 gpio-controller; 307 gpio-controller;
291 #gpio-cells = <2>; 308 #gpio-cells = <2>;
@@ -296,6 +313,7 @@
296 gpio3: gpio@10015200 { 313 gpio3: gpio@10015200 {
297 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 314 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
298 reg = <0x10015200 0x100>; 315 reg = <0x10015200 0x100>;
316 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
299 interrupts = <8>; 317 interrupts = <8>;
300 gpio-controller; 318 gpio-controller;
301 #gpio-cells = <2>; 319 #gpio-cells = <2>;
@@ -306,6 +324,7 @@
306 gpio4: gpio@10015300 { 324 gpio4: gpio@10015300 {
307 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 325 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
308 reg = <0x10015300 0x100>; 326 reg = <0x10015300 0x100>;
327 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
309 interrupts = <8>; 328 interrupts = <8>;
310 gpio-controller; 329 gpio-controller;
311 #gpio-cells = <2>; 330 #gpio-cells = <2>;
@@ -316,6 +335,7 @@
316 gpio5: gpio@10015400 { 335 gpio5: gpio@10015400 {
317 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 336 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
318 reg = <0x10015400 0x100>; 337 reg = <0x10015400 0x100>;
338 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
319 interrupts = <8>; 339 interrupts = <8>;
320 gpio-controller; 340 gpio-controller;
321 #gpio-cells = <2>; 341 #gpio-cells = <2>;
@@ -326,6 +346,7 @@
326 gpio6: gpio@10015500 { 346 gpio6: gpio@10015500 {
327 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio"; 347 compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
328 reg = <0x10015500 0x100>; 348 reg = <0x10015500 0x100>;
349 clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
329 interrupts = <8>; 350 interrupts = <8>;
330 gpio-controller; 351 gpio-controller;
331 #gpio-cells = <2>; 352 #gpio-cells = <2>;
@@ -337,7 +358,7 @@
337 audmux: audmux@10016000 { 358 audmux: audmux@10016000 {
338 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux"; 359 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
339 reg = <0x10016000 0x1000>; 360 reg = <0x10016000 0x1000>;
340 clocks = <&clks 0>; 361 clocks = <&clks IMX27_CLK_DUMMY>;
341 clock-names = "audmux"; 362 clock-names = "audmux";
342 status = "disabled"; 363 status = "disabled";
343 }; 364 };
@@ -348,7 +369,8 @@
348 compatible = "fsl,imx27-cspi"; 369 compatible = "fsl,imx27-cspi";
349 reg = <0x10017000 0x1000>; 370 reg = <0x10017000 0x1000>;
350 interrupts = <6>; 371 interrupts = <6>;
351 clocks = <&clks 51>, <&clks 60>; 372 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
373 <&clks IMX27_CLK_PER2_GATE>;
352 clock-names = "ipg", "per"; 374 clock-names = "ipg", "per";
353 status = "disabled"; 375 status = "disabled";
354 }; 376 };
@@ -357,7 +379,8 @@
357 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 379 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
358 reg = <0x10019000 0x1000>; 380 reg = <0x10019000 0x1000>;
359 interrupts = <4>; 381 interrupts = <4>;
360 clocks = <&clks 43>, <&clks 61>; 382 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
383 <&clks IMX27_CLK_PER1_GATE>;
361 clock-names = "ipg", "per"; 384 clock-names = "ipg", "per";
362 }; 385 };
363 386
@@ -365,7 +388,8 @@
365 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 388 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
366 reg = <0x1001a000 0x1000>; 389 reg = <0x1001a000 0x1000>;
367 interrupts = <3>; 390 interrupts = <3>;
368 clocks = <&clks 42>, <&clks 61>; 391 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
392 <&clks IMX27_CLK_PER1_GATE>;
369 clock-names = "ipg", "per"; 393 clock-names = "ipg", "per";
370 }; 394 };
371 395
@@ -373,7 +397,8 @@
373 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 397 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
374 reg = <0x1001b000 0x1000>; 398 reg = <0x1001b000 0x1000>;
375 interrupts = <49>; 399 interrupts = <49>;
376 clocks = <&clks 77>, <&clks 61>; 400 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
401 <&clks IMX27_CLK_PER1_GATE>;
377 clock-names = "ipg", "per"; 402 clock-names = "ipg", "per";
378 status = "disabled"; 403 status = "disabled";
379 }; 404 };
@@ -382,7 +407,8 @@
382 compatible = "fsl,imx27-uart", "fsl,imx21-uart"; 407 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
383 reg = <0x1001c000 0x1000>; 408 reg = <0x1001c000 0x1000>;
384 interrupts = <48>; 409 interrupts = <48>;
385 clocks = <&clks 78>, <&clks 61>; 410 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
411 <&clks IMX27_CLK_PER1_GATE>;
386 clock-names = "ipg", "per"; 412 clock-names = "ipg", "per";
387 status = "disabled"; 413 status = "disabled";
388 }; 414 };
@@ -393,7 +419,7 @@
393 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c"; 419 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
394 reg = <0x1001d000 0x1000>; 420 reg = <0x1001d000 0x1000>;
395 interrupts = <1>; 421 interrupts = <1>;
396 clocks = <&clks 39>; 422 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
397 status = "disabled"; 423 status = "disabled";
398 }; 424 };
399 425
@@ -401,7 +427,8 @@
401 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc"; 427 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
402 reg = <0x1001e000 0x1000>; 428 reg = <0x1001e000 0x1000>;
403 interrupts = <9>; 429 interrupts = <9>;
404 clocks = <&clks 28>, <&clks 60>; 430 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
431 <&clks IMX27_CLK_PER2_GATE>;
405 clock-names = "ipg", "per"; 432 clock-names = "ipg", "per";
406 dmas = <&dma 36>; 433 dmas = <&dma 36>;
407 dma-names = "rx-tx"; 434 dma-names = "rx-tx";
@@ -412,7 +439,8 @@
412 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; 439 compatible = "fsl,imx27-gpt", "fsl,imx1-gpt";
413 reg = <0x1001f000 0x1000>; 440 reg = <0x1001f000 0x1000>;
414 interrupts = <2>; 441 interrupts = <2>;
415 clocks = <&clks 41>, <&clks 61>; 442 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
443 <&clks IMX27_CLK_PER1_GATE>;
416 clock-names = "ipg", "per"; 444 clock-names = "ipg", "per";
417 }; 445 };
418 }; 446 };
@@ -428,7 +456,9 @@
428 compatible = "fsl,imx27-fb", "fsl,imx21-fb"; 456 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
429 interrupts = <61>; 457 interrupts = <61>;
430 reg = <0x10021000 0x1000>; 458 reg = <0x10021000 0x1000>;
431 clocks = <&clks 36>, <&clks 65>, <&clks 59>; 459 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
460 <&clks IMX27_CLK_LCDC_AHB_GATE>,
461 <&clks IMX27_CLK_PER3_GATE>;
432 clock-names = "ipg", "ahb", "per"; 462 clock-names = "ipg", "ahb", "per";
433 status = "disabled"; 463 status = "disabled";
434 }; 464 };
@@ -437,7 +467,8 @@
437 compatible = "fsl,imx27-vpu"; 467 compatible = "fsl,imx27-vpu";
438 reg = <0x10023000 0x0200>; 468 reg = <0x10023000 0x0200>;
439 interrupts = <53>; 469 interrupts = <53>;
440 clocks = <&clks 57>, <&clks 66>; 470 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
471 <&clks IMX27_CLK_VPU_AHB_GATE>;
441 clock-names = "per", "ahb"; 472 clock-names = "per", "ahb";
442 iram = <&iram>; 473 iram = <&iram>;
443 }; 474 };
@@ -446,7 +477,7 @@
446 compatible = "fsl,imx27-usb"; 477 compatible = "fsl,imx27-usb";
447 reg = <0x10024000 0x200>; 478 reg = <0x10024000 0x200>;
448 interrupts = <56>; 479 interrupts = <56>;
449 clocks = <&clks 75>; 480 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
450 fsl,usbmisc = <&usbmisc 0>; 481 fsl,usbmisc = <&usbmisc 0>;
451 status = "disabled"; 482 status = "disabled";
452 }; 483 };
@@ -455,7 +486,7 @@
455 compatible = "fsl,imx27-usb"; 486 compatible = "fsl,imx27-usb";
456 reg = <0x10024200 0x200>; 487 reg = <0x10024200 0x200>;
457 interrupts = <54>; 488 interrupts = <54>;
458 clocks = <&clks 75>; 489 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
459 fsl,usbmisc = <&usbmisc 1>; 490 fsl,usbmisc = <&usbmisc 1>;
460 status = "disabled"; 491 status = "disabled";
461 }; 492 };
@@ -464,7 +495,7 @@
464 compatible = "fsl,imx27-usb"; 495 compatible = "fsl,imx27-usb";
465 reg = <0x10024400 0x200>; 496 reg = <0x10024400 0x200>;
466 interrupts = <55>; 497 interrupts = <55>;
467 clocks = <&clks 75>; 498 clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
468 fsl,usbmisc = <&usbmisc 2>; 499 fsl,usbmisc = <&usbmisc 2>;
469 status = "disabled"; 500 status = "disabled";
470 }; 501 };
@@ -473,14 +504,15 @@
473 #index-cells = <1>; 504 #index-cells = <1>;
474 compatible = "fsl,imx27-usbmisc"; 505 compatible = "fsl,imx27-usbmisc";
475 reg = <0x10024600 0x200>; 506 reg = <0x10024600 0x200>;
476 clocks = <&clks 62>; 507 clocks = <&clks IMX27_CLK_USB_AHB_GATE>;
477 }; 508 };
478 509
479 sahara2: sahara@10025000 { 510 sahara2: sahara@10025000 {
480 compatible = "fsl,imx27-sahara"; 511 compatible = "fsl,imx27-sahara";
481 reg = <0x10025000 0x1000>; 512 reg = <0x10025000 0x1000>;
482 interrupts = <59>; 513 interrupts = <59>;
483 clocks = <&clks 32>, <&clks 64>; 514 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
515 <&clks IMX27_CLK_SAHARA_AHB_GATE>;
484 clock-names = "ipg", "ahb"; 516 clock-names = "ipg", "ahb";
485 }; 517 };
486 518
@@ -494,14 +526,15 @@
494 compatible = "fsl,imx27-iim"; 526 compatible = "fsl,imx27-iim";
495 reg = <0x10028000 0x1000>; 527 reg = <0x10028000 0x1000>;
496 interrupts = <62>; 528 interrupts = <62>;
497 clocks = <&clks 38>; 529 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
498 }; 530 };
499 531
500 fec: ethernet@1002b000 { 532 fec: ethernet@1002b000 {
501 compatible = "fsl,imx27-fec"; 533 compatible = "fsl,imx27-fec";
502 reg = <0x1002b000 0x4000>; 534 reg = <0x1002b000 0x4000>;
503 interrupts = <50>; 535 interrupts = <50>;
504 clocks = <&clks 48>, <&clks 67>; 536 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
537 <&clks IMX27_CLK_FEC_AHB_GATE>;
505 clock-names = "ipg", "ahb"; 538 clock-names = "ipg", "ahb";
506 status = "disabled"; 539 status = "disabled";
507 }; 540 };
@@ -513,7 +546,7 @@
513 compatible = "fsl,imx27-nand"; 546 compatible = "fsl,imx27-nand";
514 reg = <0xd8000000 0x1000>; 547 reg = <0xd8000000 0x1000>;
515 interrupts = <29>; 548 interrupts = <29>;
516 clocks = <&clks 54>; 549 clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
517 status = "disabled"; 550 status = "disabled";
518 }; 551 };
519 552
@@ -522,7 +555,7 @@
522 #size-cells = <1>; 555 #size-cells = <1>;
523 compatible = "fsl,imx27-weim"; 556 compatible = "fsl,imx27-weim";
524 reg = <0xd8002000 0x1000>; 557 reg = <0xd8002000 0x1000>;
525 clocks = <&clks 0>; 558 clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
526 ranges = < 559 ranges = <
527 0 0 0xc0000000 0x08000000 560 0 0 0xc0000000 0x08000000
528 1 0 0xc8000000 0x08000000 561 1 0 0xc8000000 0x08000000
diff --git a/arch/arm/boot/dts/imx28-cfa10036.dts b/arch/arm/boot/dts/imx28-cfa10036.dts
index ae7c3390e65a..b04b6b8850a7 100644
--- a/arch/arm/boot/dts/imx28-cfa10036.dts
+++ b/arch/arm/boot/dts/imx28-cfa10036.dts
@@ -53,6 +53,17 @@
53 fsl,pull-up = <MXS_PULL_DISABLE>; 53 fsl,pull-up = <MXS_PULL_DISABLE>;
54 }; 54 };
55 55
56 mmc_pwr_cfa10036: mmc_pwr_cfa10036@0 {
57 reg = <0>;
58 fsl,pinmux-ids = <
59 0x31c3 /*
60 MX28_PAD_PWM3__GPIO_3_28 */
61 >;
62 fsl,drive-strength = <0>;
63 fsl,voltage = <1>;
64 fsl,pull-up = <0>;
65 };
66
56 }; 67 };
57 68
58 ssp0: ssp@80010000 { 69 ssp0: ssp@80010000 {
@@ -60,6 +71,7 @@
60 pinctrl-names = "default"; 71 pinctrl-names = "default";
61 pinctrl-0 = <&mmc0_4bit_pins_a 72 pinctrl-0 = <&mmc0_4bit_pins_a
62 &mmc0_cd_cfg &mmc0_sck_cfg>; 73 &mmc0_cd_cfg &mmc0_sck_cfg>;
74 vmmc-supply = <&reg_vddio_sd0>;
63 bus-width = <4>; 75 bus-width = <4>;
64 status = "okay"; 76 status = "okay";
65 }; 77 };
@@ -116,4 +128,14 @@
116 default-state = "on"; 128 default-state = "on";
117 }; 129 };
118 }; 130 };
131
132 reg_vddio_sd0: vddio-sd0 {
133 compatible = "regulator-fixed";
134 pinctrl-names = "default";
135 pinctrl-0 = <&mmc_pwr_cfa10036>;
136 regulator-name = "vddio-sd0";
137 regulator-min-microvolt = <3300000>;
138 regulator-max-microvolt = <3300000>;
139 gpio = <&gpio3 28 0>;
140 };
119}; 141};
diff --git a/arch/arm/boot/dts/imx28-m28.dtsi b/arch/arm/boot/dts/imx28-m28.dtsi
new file mode 100644
index 000000000000..759cc56253dd
--- /dev/null
+++ b/arch/arm/boot/dts/imx28-m28.dtsi
@@ -0,0 +1,87 @@
1/*
2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx28.dtsi"
13
14/ {
15 model = "DENX M28";
16 compatible = "denx,m28", "fsl,imx28";
17
18 memory {
19 reg = <0x40000000 0x08000000>;
20 };
21
22 apb@80000000 {
23 apbh@80000000 {
24 gpmi-nand@8000c000 {
25 #address-cells = <1>;
26 #size-cells = <1>;
27 pinctrl-names = "default";
28 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
29 status = "okay";
30
31 partition@0 {
32 label = "bootloader";
33 reg = <0x00000000 0x00300000>;
34 read-only;
35 };
36
37 partition@1 {
38 label = "environment";
39 reg = <0x00300000 0x00080000>;
40 };
41
42 partition@2 {
43 label = "redundant-environment";
44 reg = <0x00380000 0x00080000>;
45 };
46
47 partition@3 {
48 label = "kernel";
49 reg = <0x00400000 0x00400000>;
50 };
51
52 partition@4 {
53 label = "filesystem";
54 reg = <0x00800000 0x0f800000>;
55 };
56 };
57 };
58
59 apbx@80040000 {
60 i2c0: i2c@80058000 {
61 pinctrl-names = "default";
62 pinctrl-0 = <&i2c0_pins_a>;
63 status = "okay";
64
65 rtc: rtc@68 {
66 compatible = "stm,m41t62";
67 reg = <0x68>;
68 };
69 };
70 };
71 };
72
73 regulators {
74 compatible = "simple-bus";
75 #address-cells = <1>;
76 #size-cells = <0>;
77
78 reg_3p3v: regulator@0 {
79 compatible = "regulator-fixed";
80 reg = <0>;
81 regulator-name = "3P3V";
82 regulator-min-microvolt = <3300000>;
83 regulator-max-microvolt = <3300000>;
84 regulator-always-on;
85 };
86 };
87};
diff --git a/arch/arm/boot/dts/imx28-m28evk.dts b/arch/arm/boot/dts/imx28-m28evk.dts
index f0ad7b9b9d9a..b3c09ae3b928 100644
--- a/arch/arm/boot/dts/imx28-m28evk.dts
+++ b/arch/arm/boot/dts/imx28-m28evk.dts
@@ -10,52 +10,14 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "imx28.dtsi" 13#include "imx28-m28.dtsi"
14 14
15/ { 15/ {
16 model = "DENX M28EVK"; 16 model = "DENX M28EVK";
17 compatible = "denx,m28evk", "fsl,imx28"; 17 compatible = "denx,m28evk", "fsl,imx28";
18 18
19 memory {
20 reg = <0x40000000 0x08000000>;
21 };
22
23 apb@80000000 { 19 apb@80000000 {
24 apbh@80000000 { 20 apbh@80000000 {
25 gpmi-nand@8000c000 {
26 #address-cells = <1>;
27 #size-cells = <1>;
28 pinctrl-names = "default";
29 pinctrl-0 = <&gpmi_pins_a &gpmi_status_cfg>;
30 status = "okay";
31
32 partition@0 {
33 label = "bootloader";
34 reg = <0x00000000 0x00300000>;
35 read-only;
36 };
37
38 partition@1 {
39 label = "environment";
40 reg = <0x00300000 0x00080000>;
41 };
42
43 partition@2 {
44 label = "redundant-environment";
45 reg = <0x00380000 0x00080000>;
46 };
47
48 partition@3 {
49 label = "kernel";
50 reg = <0x00400000 0x00400000>;
51 };
52
53 partition@4 {
54 label = "filesystem";
55 reg = <0x00800000 0x0f800000>;
56 };
57 };
58
59 ssp0: ssp@80010000 { 21 ssp0: ssp@80010000 {
60 compatible = "fsl,imx28-mmc"; 22 compatible = "fsl,imx28-mmc";
61 pinctrl-names = "default"; 23 pinctrl-names = "default";
@@ -175,10 +137,6 @@
175 }; 137 };
176 138
177 i2c0: i2c@80058000 { 139 i2c0: i2c@80058000 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&i2c0_pins_a>;
180 status = "okay";
181
182 sgtl5000: codec@0a { 140 sgtl5000: codec@0a {
183 compatible = "fsl,sgtl5000"; 141 compatible = "fsl,sgtl5000";
184 reg = <0x0a>; 142 reg = <0x0a>;
@@ -192,11 +150,6 @@
192 reg = <0x51>; 150 reg = <0x51>;
193 pagesize = <32>; 151 pagesize = <32>;
194 }; 152 };
195
196 rtc: rtc@68 {
197 compatible = "stm,m41t62";
198 reg = <0x68>;
199 };
200 }; 153 };
201 154
202 lradc@80050000 { 155 lradc@80050000 {
@@ -284,19 +237,6 @@
284 }; 237 };
285 238
286 regulators { 239 regulators {
287 compatible = "simple-bus";
288 #address-cells = <1>;
289 #size-cells = <0>;
290
291 reg_3p3v: regulator@0 {
292 compatible = "regulator-fixed";
293 reg = <0>;
294 regulator-name = "3P3V";
295 regulator-min-microvolt = <3300000>;
296 regulator-max-microvolt = <3300000>;
297 regulator-always-on;
298 };
299
300 reg_vddio_sd0: regulator@1 { 240 reg_vddio_sd0: regulator@1 {
301 compatible = "regulator-fixed"; 241 compatible = "regulator-fixed";
302 reg = <1>; 242 reg = <1>;
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index f04ae91eea89..75b036700d31 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -133,7 +133,6 @@
133 133
134&ssi1 { 134&ssi1 {
135 codec-handle = <&tlv320aic23>; 135 codec-handle = <&tlv320aic23>;
136 fsl,mode = "i2s-slave";
137 status = "okay"; 136 status = "okay";
138}; 137};
139 138
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index 4759abb49436..442e216ca9d9 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -193,6 +193,14 @@
193 #clock-cells = <1>; 193 #clock-cells = <1>;
194 }; 194 };
195 195
196 gpt: timer@53f90000 {
197 compatible = "fsl,imx35-gpt", "fsl,imx31-gpt";
198 reg = <0x53f90000 0x4000>;
199 interrupts = <29>;
200 clocks = <&clks 9>, <&clks 50>;
201 clock-names = "ipg", "per";
202 };
203
196 gpio3: gpio@53fa4000 { 204 gpio3: gpio@53fa4000 {
197 compatible = "fsl,imx35-gpio", "fsl,imx31-gpio"; 205 compatible = "fsl,imx35-gpio", "fsl,imx31-gpio";
198 reg = <0x53fa4000 0x4000>; 206 reg = <0x53fa4000 0x4000>;
diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi
index 6a201cf54366..c0e0f60ab6b2 100644
--- a/arch/arm/boot/dts/imx50.dtsi
+++ b/arch/arm/boot/dts/imx50.dtsi
@@ -151,8 +151,10 @@
151 reg = <0x50014000 0x4000>; 151 reg = <0x50014000 0x4000>;
152 interrupts = <30>; 152 interrupts = <30>;
153 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>; 153 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>;
154 dmas = <&sdma 24 1 0>,
155 <&sdma 25 1 0>;
156 dma-names = "rx", "tx";
154 fsl,fifo-depth = <15>; 157 fsl,fifo-depth = <15>;
155 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
156 status = "disabled"; 158 status = "disabled";
157 }; 159 };
158 160
@@ -457,8 +459,10 @@
457 reg = <0x63fcc000 0x4000>; 459 reg = <0x63fcc000 0x4000>;
458 interrupts = <29>; 460 interrupts = <29>;
459 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>; 461 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>;
462 dmas = <&sdma 28 0 0>,
463 <&sdma 29 0 0>;
464 dma-names = "rx", "tx";
460 fsl,fifo-depth = <15>; 465 fsl,fifo-depth = <15>;
461 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
462 status = "disabled"; 466 status = "disabled";
463 }; 467 };
464 468
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 181d77fa2fa6..56569cecaa78 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -203,6 +203,7 @@
203 reg = <0>; 203 reg = <0>;
204 interrupt-parent = <&gpio1>; 204 interrupt-parent = <&gpio1>;
205 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; 205 interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
206 fsl,mc13xxx-uses-rtc;
206 207
207 regulators { 208 regulators {
208 sw1_reg: sw1 { 209 sw1_reg: sw1 {
@@ -392,7 +393,6 @@
392}; 393};
393 394
394&ssi2 { 395&ssi2 {
395 fsl,mode = "i2s-slave";
396 status = "okay"; 396 status = "okay";
397}; 397};
398 398
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 31cfb7f2b02e..34599c547459 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -255,7 +255,6 @@
255 255
256&ssi2 { 256&ssi2 {
257 codec-handle = <&tlv320aic23>; 257 codec-handle = <&tlv320aic23>;
258 fsl,mode = "i2s-slave";
259 status = "okay"; 258 status = "okay";
260}; 259};
261 260
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index bebbf3ba0d5e..17c05a6fa776 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -218,7 +218,6 @@
218 <&sdma 25 1 0>; 218 <&sdma 25 1 0>;
219 dma-names = "rx", "tx"; 219 dma-names = "rx", "tx";
220 fsl,fifo-depth = <15>; 220 fsl,fifo-depth = <15>;
221 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
222 status = "disabled"; 221 status = "disabled";
223 }; 222 };
224 223
@@ -508,7 +507,6 @@
508 <&sdma 29 0 0>; 507 <&sdma 29 0 0>;
509 dma-names = "rx", "tx"; 508 dma-names = "rx", "tx";
510 fsl,fifo-depth = <15>; 509 fsl,fifo-depth = <15>;
511 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
512 status = "disabled"; 510 status = "disabled";
513 }; 511 };
514 512
@@ -564,7 +562,6 @@
564 <&sdma 47 0 0>; 562 <&sdma 47 0 0>;
565 dma-names = "rx", "tx"; 563 dma-names = "rx", "tx";
566 fsl,fifo-depth = <15>; 564 fsl,fifo-depth = <15>;
567 fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
568 status = "disabled"; 565 status = "disabled";
569 }; 566 };
570 567
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
new file mode 100644
index 000000000000..87a7fc709c2d
--- /dev/null
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -0,0 +1,140 @@
1/*
2 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "imx53.dtsi"
13
14/ {
15 model = "DENX M53";
16 compatible = "denx,imx53-m53", "fsl,imx53";
17
18 memory {
19 reg = <0x70000000 0x20000000>,
20 <0xb0000000 0x20000000>;
21 };
22
23 regulators {
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 reg_3p2v: regulator@0 {
29 compatible = "regulator-fixed";
30 reg = <0>;
31 regulator-name = "3P2V";
32 regulator-min-microvolt = <3200000>;
33 regulator-max-microvolt = <3200000>;
34 regulator-always-on;
35 };
36
37 reg_backlight: regulator@1 {
38 compatible = "regulator-fixed";
39 reg = <1>;
40 regulator-name = "lcd-supply";
41 regulator-min-microvolt = <3200000>;
42 regulator-max-microvolt = <3200000>;
43 regulator-always-on;
44 };
45 };
46};
47
48&i2c2 {
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_i2c2>;
51 clock-frequency = <400000>;
52 status = "okay";
53
54 stmpe610@41 {
55 compatible = "st,stmpe610";
56 #address-cells = <1>;
57 #size-cells = <0>;
58 reg = <0x41>;
59 id = <0>;
60 blocks = <0x5>;
61 interrupts = <6 0x0>;
62 interrupt-parent = <&gpio7>;
63 irq-trigger = <0x1>;
64
65 stmpe_touchscreen {
66 compatible = "st,stmpe-ts";
67 reg = <0>;
68 st,sample-time = <4>;
69 st,mod-12b = <1>;
70 st,ref-sel = <0>;
71 st,adc-freq = <1>;
72 st,ave-ctrl = <3>;
73 st,touch-det-delay = <3>;
74 st,settling = <4>;
75 st,fraction-z = <7>;
76 st,i-drive = <1>;
77 };
78 };
79
80 eeprom: eeprom@50 {
81 compatible = "atmel,24c128";
82 reg = <0x50>;
83 pagesize = <32>;
84 };
85
86 rtc: rtc@68 {
87 compatible = "stm,m41t62";
88 reg = <0x68>;
89 };
90};
91
92&iomuxc {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_hog>;
95
96 imx53-m53evk {
97 pinctrl_hog: hoggrp {
98 fsl,pins = <
99 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
100 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
101 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
102 >;
103 };
104
105 pinctrl_i2c2: i2c2grp {
106 fsl,pins = <
107 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
108 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
109 >;
110 };
111
112 pinctrl_nand: nandgrp {
113 fsl,pins = <
114 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
115 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
116 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
117 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
118 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
119 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
120 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
121 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
122 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
123 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
124 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
125 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
126 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
127 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
128 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
129 >;
130 };
131 };
132};
133
134&nfc {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_nand>;
137 nand-bus-width = <8>;
138 nand-ecc-mode = "hw";
139 status = "okay";
140};
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index c4956b0ffb35..d0e0f57eb432 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -10,17 +10,12 @@
10 */ 10 */
11 11
12/dts-v1/; 12/dts-v1/;
13#include "imx53.dtsi" 13#include "imx53-m53.dtsi"
14 14
15/ { 15/ {
16 model = "DENX M53EVK"; 16 model = "DENX M53EVK";
17 compatible = "denx,imx53-m53evk", "fsl,imx53"; 17 compatible = "denx,imx53-m53evk", "fsl,imx53";
18 18
19 memory {
20 reg = <0x70000000 0x20000000>,
21 <0xb0000000 0x20000000>;
22 };
23
24 display1: display@di1 { 19 display1: display@di1 {
25 compatible = "fsl,imx-parallel-display"; 20 compatible = "fsl,imx-parallel-display";
26 interface-pix-fmt = "bgr666"; 21 interface-pix-fmt = "bgr666";
@@ -81,25 +76,6 @@
81 #address-cells = <1>; 76 #address-cells = <1>;
82 #size-cells = <0>; 77 #size-cells = <0>;
83 78
84 reg_3p2v: regulator@0 {
85 compatible = "regulator-fixed";
86 reg = <0>;
87 regulator-name = "3P2V";
88 regulator-min-microvolt = <3200000>;
89 regulator-max-microvolt = <3200000>;
90 regulator-always-on;
91 };
92
93
94 reg_backlight: regulator@1 {
95 compatible = "regulator-fixed";
96 reg = <1>;
97 regulator-name = "lcd-supply";
98 regulator-min-microvolt = <3200000>;
99 regulator-max-microvolt = <3200000>;
100 regulator-always-on;
101 };
102
103 reg_usbh1_vbus: regulator@3 { 79 reg_usbh1_vbus: regulator@3 {
104 compatible = "regulator-fixed"; 80 compatible = "regulator-fixed";
105 reg = <3>; 81 reg = <3>;
@@ -174,50 +150,6 @@
174 }; 150 };
175}; 151};
176 152
177&i2c2 {
178 pinctrl-names = "default";
179 pinctrl-0 = <&pinctrl_i2c2>;
180 clock-frequency = <400000>;
181 status = "okay";
182
183 stmpe610@41 {
184 compatible = "st,stmpe610";
185 #address-cells = <1>;
186 #size-cells = <0>;
187 reg = <0x41>;
188 id = <0>;
189 blocks = <0x5>;
190 interrupts = <6 0x0>;
191 interrupt-parent = <&gpio7>;
192 irq-trigger = <0x1>;
193
194 stmpe_touchscreen {
195 compatible = "st,stmpe-ts";
196 reg = <0>;
197 st,sample-time = <4>;
198 st,mod-12b = <1>;
199 st,ref-sel = <0>;
200 st,adc-freq = <1>;
201 st,ave-ctrl = <3>;
202 st,touch-det-delay = <3>;
203 st,settling = <4>;
204 st,fraction-z = <7>;
205 st,i-drive = <1>;
206 };
207 };
208
209 eeprom: eeprom@50 {
210 compatible = "atmel,24c128";
211 reg = <0x50>;
212 pagesize = <32>;
213 };
214
215 rtc: rtc@68 {
216 compatible = "stm,m41t62";
217 reg = <0x68>;
218 };
219};
220
221&i2c3 { 153&i2c3 {
222 pinctrl-names = "default"; 154 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c3>; 155 pinctrl-0 = <&pinctrl_i2c3>;
@@ -229,11 +161,8 @@
229 pinctrl-0 = <&pinctrl_hog>; 161 pinctrl-0 = <&pinctrl_hog>;
230 162
231 imx53-m53evk { 163 imx53-m53evk {
232 pinctrl_hog: hoggrp { 164 pinctrl_usb: usbgrp {
233 fsl,pins = < 165 fsl,pins = <
234 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
235 MX53_PAD_EIM_EB3__GPIO2_31 0x80000000
236 MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
237 MX53_PAD_GPIO_2__GPIO1_2 0x80000000 166 MX53_PAD_GPIO_2__GPIO1_2 0x80000000
238 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000 167 MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x80000000
239 >; 168 >;
@@ -302,13 +231,6 @@
302 >; 231 >;
303 }; 232 };
304 233
305 pinctrl_i2c2: i2c2grp {
306 fsl,pins = <
307 MX53_PAD_EIM_D16__I2C2_SDA 0xc0000000
308 MX53_PAD_EIM_EB2__I2C2_SCL 0xc0000000
309 >;
310 };
311
312 pinctrl_i2c3: i2c3grp { 234 pinctrl_i2c3: i2c3grp {
313 fsl,pins = < 235 fsl,pins = <
314 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000 236 MX53_PAD_GPIO_6__I2C3_SDA 0xc0000000
@@ -353,26 +275,6 @@
353 >; 275 >;
354 }; 276 };
355 277
356 pinctrl_nand: nandgrp {
357 fsl,pins = <
358 MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4
359 MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4
360 MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4
361 MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4
362 MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0
363 MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0
364 MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4
365 MX53_PAD_PATA_DATA0__EMI_NANDF_D_0 0xa4
366 MX53_PAD_PATA_DATA1__EMI_NANDF_D_1 0xa4
367 MX53_PAD_PATA_DATA2__EMI_NANDF_D_2 0xa4
368 MX53_PAD_PATA_DATA3__EMI_NANDF_D_3 0xa4
369 MX53_PAD_PATA_DATA4__EMI_NANDF_D_4 0xa4
370 MX53_PAD_PATA_DATA5__EMI_NANDF_D_5 0xa4
371 MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 0xa4
372 MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 0xa4
373 >;
374 };
375
376 pinctrl_pwm1: pwm1grp { 278 pinctrl_pwm1: pwm1grp {
377 fsl,pins = < 279 fsl,pins = <
378 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5 280 MX53_PAD_DISP0_DAT8__PWM1_PWMO 0x5
@@ -408,14 +310,6 @@
408 remote-endpoint = <&display1_in>; 310 remote-endpoint = <&display1_in>;
409}; 311};
410 312
411&nfc {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_nand>;
414 nand-bus-width = <8>;
415 nand-ecc-mode = "hw";
416 status = "okay";
417};
418
419&pwm1 { 313&pwm1 {
420 pinctrl-names = "default"; 314 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_pwm1>; 315 pinctrl-0 = <&pinctrl_pwm1>;
@@ -427,7 +321,6 @@
427}; 321};
428 322
429&ssi2 { 323&ssi2 {
430 fsl,mode = "i2s-slave";
431 status = "okay"; 324 status = "okay";
432}; 325};
433 326
@@ -450,6 +343,8 @@
450}; 343};
451 344
452&usbh1 { 345&usbh1 {
346 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_usb>;
453 vbus-supply = <&reg_usbh1_vbus>; 348 vbus-supply = <&reg_usbh1_vbus>;
454 phy_type = "utmi"; 349 phy_type = "utmi";
455 status = "okay"; 350 status = "okay";
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 3e3f17aa93a1..2e44d2aba14e 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -225,7 +225,6 @@
225}; 225};
226 226
227&ssi2 { 227&ssi2 {
228 fsl,mode = "i2s-slave";
229 status = "okay"; 228 status = "okay";
230}; 229};
231 230
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index fd8c60dde7de..181ae5ebf23f 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -141,7 +141,6 @@
141}; 141};
142 142
143&ssi2 { 143&ssi2 {
144 fsl,mode = "i2s-slave";
145 status = "okay"; 144 status = "okay";
146}; 145};
147 146
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index e348796ba689..704bd72cbfec 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -502,7 +502,6 @@
502}; 502};
503 503
504&ssi1 { 504&ssi1 {
505 fsl,mode = "i2s-slave";
506 codec-handle = <&sgtl5000>; 505 codec-handle = <&sgtl5000>;
507 status = "okay"; 506 status = "okay";
508}; 507};
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index 7f6711a48615..c17d3ad6dba5 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -154,6 +154,5 @@
154}; 154};
155 155
156&ssi2 { 156&ssi2 {
157 fsl,mode = "i2s-slave";
158 status = "okay"; 157 status = "okay";
159}; 158};
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 6456a0084388..64fa27b36be0 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -108,7 +108,7 @@
108 clocks = <&clks IMX5_CLK_SATA_GATE>, 108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>, 109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>; 110 <&clks IMX5_CLK_AHB>;
111 clock-names = "sata_gate", "sata_ref", "ahb"; 111 clock-names = "sata", "sata_ref", "ahb";
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 114
@@ -231,7 +231,6 @@
231 <&sdma 25 1 0>; 231 <&sdma 25 1 0>;
232 dma-names = "rx", "tx"; 232 dma-names = "rx", "tx";
233 fsl,fifo-depth = <15>; 233 fsl,fifo-depth = <15>;
234 fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
235 status = "disabled"; 234 status = "disabled";
236 }; 235 };
237 236
@@ -260,6 +259,11 @@
260 }; 259 };
261 }; 260 };
262 261
262 aipstz1: bridge@53f00000 {
263 compatible = "fsl,imx53-aipstz";
264 reg = <0x53f00000 0x60>;
265 };
266
263 usbphy0: usbphy@0 { 267 usbphy0: usbphy@0 {
264 compatible = "usb-nop-xceiv"; 268 compatible = "usb-nop-xceiv";
265 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 269 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
@@ -572,6 +576,11 @@
572 reg = <0x60000000 0x10000000>; 576 reg = <0x60000000 0x10000000>;
573 ranges; 577 ranges;
574 578
579 aipstz2: bridge@63f00000 {
580 compatible = "fsl,imx53-aipstz";
581 reg = <0x63f00000 0x60>;
582 };
583
575 iim: iim@63f98000 { 584 iim: iim@63f98000 {
576 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 585 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
577 reg = <0x63f98000 0x4000>; 586 reg = <0x63f98000 0x4000>;
@@ -661,7 +670,6 @@
661 <&sdma 29 0 0>; 670 <&sdma 29 0 0>;
662 dma-names = "rx", "tx"; 671 dma-names = "rx", "tx";
663 fsl,fifo-depth = <15>; 672 fsl,fifo-depth = <15>;
664 fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
665 status = "disabled"; 673 status = "disabled";
666 }; 674 };
667 675
@@ -689,7 +697,6 @@
689 <&sdma 47 0 0>; 697 <&sdma 47 0 0>;
690 dma-names = "rx", "tx"; 698 dma-names = "rx", "tx";
691 fsl,fifo-depth = <15>; 699 fsl,fifo-depth = <15>;
692 fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
693 status = "disabled"; 700 status = "disabled";
694 }; 701 };
695 702
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
new file mode 100644
index 000000000000..9cd06e5e59f0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -0,0 +1,85 @@
1/*
2 * support fot the imx6 based aristainetos board
3 *
4 * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-aristainetos.dtsi"
14
15/ {
16 model = "aristainetos i.MX6 Dual Lite Board 4";
17 compatible = "fsl,imx6dl";
18
19 backlight {
20 compatible = "pwm-backlight";
21 pwms = <&pwm1 0 5000000>;
22 brightness-levels = <0 4 8 16 32 64 128 255>;
23 default-brightness-level = <7>;
24 enable-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_backlight>;
27 status = "okay";
28 };
29
30 memory {
31 reg = <0x10000000 0x40000000>;
32 };
33
34 soc {
35 display0: display@di0 {
36 compatible = "fsl,imx-parallel-display";
37 interface-pix-fmt = "rgb24";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_ipu_disp>;
40 status = "okay";
41
42 display-timings {
43 480x800p60 {
44 native-mode;
45 clock-frequency = <30000000>;
46 hactive = <480>;
47 vactive = <800>;
48 hfront-porch = <59>;
49 hback-porch = <10>;
50 hsync-len = <10>;
51 vback-porch = <15>;
52 vfront-porch = <15>;
53 vsync-len = <15>;
54 hsync-active = <1>;
55 vsync-active = <1>;
56 };
57 };
58
59 port {
60 display0_in: endpoint {
61 remote-endpoint = <&ipu1_di0_disp0>;
62 };
63 };
64 };
65 };
66};
67
68&ecspi2 {
69 fsl,spi-num-chipselects = <1>;
70 cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_ecspi2>;
73 status = "okay";
74};
75
76&i2c2 {
77 clock-frequency = <100000>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_i2c2>;
80 status = "okay";
81};
82
83&ipu1_di0_disp0 {
84 remote-endpoint = <&display0_in>;
85};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
new file mode 100644
index 000000000000..b413e24288dc
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_7.dts
@@ -0,0 +1,74 @@
1/*
2 * support fot the imx6 based aristainetos board
3 *
4 * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-aristainetos.dtsi"
14
15/ {
16 model = "aristainetos i.MX6 Dual Lite Board 7";
17 compatible = "fsl,imx6dl";
18
19 memory {
20 reg = <0x10000000 0x40000000>;
21 };
22
23 soc {
24 display0: display@di0 {
25 compatible = "fsl,imx-parallel-display";
26 interface-pix-fmt = "rgb24";
27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_ipu_disp>;
29 status = "okay";
30
31 display-timings {
32 800x480p60 {
33 native-mode;
34 clock-frequency = <33246000>;
35 hactive = <800>;
36 vactive = <480>;
37 hfront-porch = <88>;
38 hback-porch = <88>;
39 hsync-len = <80>;
40 vback-porch = <10>;
41 vfront-porch = <10>;
42 vsync-len = <25>;
43 vsync-active = <1>;
44 };
45 };
46
47 port {
48 display0_in: endpoint {
49 remote-endpoint = <&ipu1_di0_disp0>;
50 };
51 };
52 };
53 };
54
55 backlight {
56 compatible = "pwm-backlight";
57 pwms = <&pwm3 0 3000>;
58 brightness-levels = <0 4 8 16 32 64 128 255>;
59 default-brightness-level = <6>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_backlight>;
62 };
63};
64
65&i2c2 {
66 clock-frequency = <100000>;
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_i2c2>;
69 status = "okay";
70};
71
72&ipu1_di0_disp0 {
73 remote-endpoint = <&display0_in>;
74};
diff --git a/arch/arm/boot/dts/imx6dl-gw51xx.dts b/arch/arm/boot/dts/imx6dl-gw51xx.dts
index 4bd055f4c930..b2bd022fc6be 100644
--- a/arch/arm/boot/dts/imx6dl-gw51xx.dts
+++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts
@@ -14,6 +14,6 @@
14#include "imx6qdl-gw51xx.dtsi" 14#include "imx6qdl-gw51xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW51XX"; 17 model = "Gateworks Ventana i.MX6 DualLite/Solo GW51XX";
18 compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; 18 compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl";
19}; 19};
diff --git a/arch/arm/boot/dts/imx6dl-gw52xx.dts b/arch/arm/boot/dts/imx6dl-gw52xx.dts
index c9136058f15e..a2e0b73fdd4a 100644
--- a/arch/arm/boot/dts/imx6dl-gw52xx.dts
+++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts
@@ -14,6 +14,6 @@
14#include "imx6qdl-gw52xx.dtsi" 14#include "imx6qdl-gw52xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW52XX"; 17 model = "Gateworks Ventana i.MX6 DualLite/Solo GW52XX";
18 compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; 18 compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl";
19}; 19};
diff --git a/arch/arm/boot/dts/imx6dl-gw53xx.dts b/arch/arm/boot/dts/imx6dl-gw53xx.dts
index 61818a14fde6..6844b708d2f8 100644
--- a/arch/arm/boot/dts/imx6dl-gw53xx.dts
+++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts
@@ -14,6 +14,6 @@
14#include "imx6qdl-gw53xx.dtsi" 14#include "imx6qdl-gw53xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW53XX"; 17 model = "Gateworks Ventana i.MX6 DualLite/Solo GW53XX";
18 compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; 18 compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl";
19}; 19};
diff --git a/arch/arm/boot/dts/imx6dl-gw54xx.dts b/arch/arm/boot/dts/imx6dl-gw54xx.dts
index ab38b6770a06..be915412f852 100644
--- a/arch/arm/boot/dts/imx6dl-gw54xx.dts
+++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts
@@ -14,6 +14,6 @@
14#include "imx6qdl-gw54xx.dtsi" 14#include "imx6qdl-gw54xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 DualLite GW54XX"; 17 model = "Gateworks Ventana i.MX6 DualLite/Solo GW54XX";
18 compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; 18 compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl";
19}; 19};
diff --git a/arch/arm/boot/dts/imx6dl-rex-basic.dts b/arch/arm/boot/dts/imx6dl-rex-basic.dts
new file mode 100644
index 000000000000..b13845c2823b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-rex-basic.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2014 FEDEVEL, Inc.
3 *
4 * Author: Robert Nelson <robertcnelson@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-rex.dtsi"
14
15/ {
16 model = "Rex Basic i.MX6 Dual Lite Board";
17 compatible = "rex,imx6dl-rex-basic", "fsl,imx6dl";
18
19 memory {
20 reg = <0x10000000 0x20000000>;
21 };
22};
23
24&ecspi3 {
25 flash: m25p80@0 {
26 compatible = "sst,sst25vf016b";
27 spi-max-frequency = <20000000>;
28 reg = <0>;
29 };
30};
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 909fafc0b650..43cb3fd76be7 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -254,7 +254,6 @@
254}; 254};
255 255
256&ssi1 { 256&ssi1 {
257 fsl,mode = "i2s-slave";
258 status = "okay"; 257 status = "okay";
259}; 258};
260 259
@@ -335,10 +334,10 @@
335 imx6-riotboard { 334 imx6-riotboard {
336 pinctrl_audmux: audmuxgrp { 335 pinctrl_audmux: audmuxgrp {
337 fsl,pins = < 336 fsl,pins = <
338 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x8000000 337 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
339 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x8000000 338 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
340 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x8000000 339 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
341 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x8000000 340 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
342 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */ 341 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* CAM_MCLK */
343 >; 342 >;
344 }; 343 };
@@ -376,7 +375,7 @@
376 fsl,pins = < 375 fsl,pins = <
377 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 376 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
378 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 377 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
379 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x80000000 378 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
380 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 379 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
381 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 380 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
382 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 381 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
@@ -389,9 +388,9 @@
389 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */ 388 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 /* AR8035 pin strapping: MODE#1: pull up */
390 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */ 389 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 /* AR8035 pin strapping: MODE#3: pull up */
391 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */ 390 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x130b0 /* AR8035 pin strapping: MODE#0: pull down */
392 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0xc0000000 /* GPIO16 -> AR8035 25MHz */ 391 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 /* GPIO16 -> AR8035 25MHz */
393 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */ 392 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0 /* RGMII_nRST */
394 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* AR8035 interrupt */ 393 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x180b0 /* AR8035 interrupt */
395 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 394 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
396 >; 395 >;
397 }; 396 };
@@ -426,8 +425,8 @@
426 425
427 pinctrl_led: ledgrp { 426 pinctrl_led: ledgrp {
428 fsl,pins = < 427 fsl,pins = <
429 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* user led0 */ 428 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* user led0 */
430 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x80000000 /* user led1 */ 429 MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x1b0b1 /* user led1 */
431 >; 430 >;
432 }; 431 };
433 432
@@ -493,8 +492,8 @@
493 pinctrl_usbotg: usbotggrp { 492 pinctrl_usbotg: usbotggrp {
494 fsl,pins = < 493 fsl,pins = <
495 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 494 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
496 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */ 495 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 /* MX6QDL_PAD_EIM_D22__USB_OTG_PWR */
497 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x80000000 496 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
498 >; 497 >;
499 }; 498 };
500 499
@@ -506,8 +505,8 @@
506 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 505 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
507 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 506 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
508 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 507 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
509 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x80000000 /* SD2 CD */ 508 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0 /* SD2 CD */
510 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* SD2 WP */ 509 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1f0b0 /* SD2 WP */
511 >; 510 >;
512 }; 511 };
513 512
@@ -519,8 +518,8 @@
519 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 518 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
520 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 519 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
521 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 520 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
522 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3 CD */ 521 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* SD3 CD */
523 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x80000000 /* SD3 WP */ 522 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* SD3 WP */
524 >; 523 >;
525 }; 524 };
526 525
@@ -532,7 +531,7 @@
532 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 531 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
533 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 532 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
534 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 533 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
535 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x80000000 /* SD4 RST (eMMC) */ 534 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x17059 /* SD4 RST (eMMC) */
536 >; 535 >;
537 }; 536 };
538 }; 537 };
diff --git a/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
new file mode 100644
index 000000000000..913bb9a0466a
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6dl-comtft.dts
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6DL Module on CoMpact TFT";
18 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 0>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 native-mode = <&ET070001DM6>;
61
62 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
63 clock-frequency = <33264000>;
64 hactive = <800>;
65 vactive = <480>;
66 hback-porch = <88>;
67 hsync-len = <128>;
68 hfront-porch = <40>;
69 vback-porch = <33>;
70 vsync-len = <2>;
71 vfront-porch = <10>;
72 hsync-active = <0>;
73 vsync-active = <0>;
74 de-active = <1>;
75 pixelclk-active = <1>;
76 };
77 };
78 };
79};
80
81&can1 {
82 status = "disabled";
83};
84
85&can2 {
86 xceiver-supply = <&reg_3v3>;
87};
88
89&ipu1_di0_disp0 {
90 remote-endpoint = <&display0_in>;
91};
92
93&kpp {
94 status = "disabled";
95};
96
97&reg_can_xcvr {
98 status = "disabled";
99};
100
101&touchscreen {
102 status = "disabled";
103};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-801x.dts b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
new file mode 100644
index 000000000000..5fe465c2814e
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6u-801x.dts
@@ -0,0 +1,177 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6U-801x Module";
18 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 VGA {
61 clock-frequency = <25200000>;
62 hactive = <640>;
63 vactive = <480>;
64 hback-porch = <48>;
65 hsync-len = <96>;
66 hfront-porch = <16>;
67 vback-porch = <31>;
68 vsync-len = <2>;
69 vfront-porch = <12>;
70 hsync-active = <0>;
71 vsync-active = <0>;
72 de-active = <1>;
73 pixelclk-active = <0>;
74 };
75
76 ETV570 {
77 clock-frequency = <25200000>;
78 hactive = <640>;
79 vactive = <480>;
80 hback-porch = <114>;
81 hsync-len = <30>;
82 hfront-porch = <16>;
83 vback-porch = <32>;
84 vsync-len = <3>;
85 vfront-porch = <10>;
86 hsync-active = <0>;
87 vsync-active = <0>;
88 de-active = <1>;
89 pixelclk-active = <0>;
90 };
91
92 ET0350 {
93 clock-frequency = <6413760>;
94 hactive = <320>;
95 vactive = <240>;
96 hback-porch = <34>;
97 hsync-len = <34>;
98 hfront-porch = <20>;
99 vback-porch = <15>;
100 vsync-len = <3>;
101 vfront-porch = <4>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <0>;
106 };
107
108 ET0430 {
109 clock-frequency = <9009000>;
110 hactive = <480>;
111 vactive = <272>;
112 hback-porch = <2>;
113 hsync-len = <41>;
114 hfront-porch = <2>;
115 vback-porch = <2>;
116 vsync-len = <10>;
117 vfront-porch = <2>;
118 hsync-active = <0>;
119 vsync-active = <0>;
120 de-active = <1>;
121 pixelclk-active = <1>;
122 };
123
124 ET0500 {
125 clock-frequency = <33264000>;
126 hactive = <800>;
127 vactive = <480>;
128 hback-porch = <88>;
129 hsync-len = <128>;
130 hfront-porch = <40>;
131 vback-porch = <33>;
132 vsync-len = <2>;
133 vfront-porch = <10>;
134 hsync-active = <0>;
135 vsync-active = <0>;
136 de-active = <1>;
137 pixelclk-active = <0>;
138 };
139
140 ET0700 { /* same as ET0500 */
141 clock-frequency = <33264000>;
142 hactive = <800>;
143 vactive = <480>;
144 hback-porch = <88>;
145 hsync-len = <128>;
146 hfront-porch = <40>;
147 vback-porch = <33>;
148 vsync-len = <2>;
149 vfront-porch = <10>;
150 hsync-active = <0>;
151 vsync-active = <0>;
152 de-active = <1>;
153 pixelclk-active = <0>;
154 };
155
156 ETQ570 {
157 clock-frequency = <6596040>;
158 hactive = <320>;
159 vactive = <240>;
160 hback-porch = <38>;
161 hsync-len = <30>;
162 hfront-porch = <30>;
163 vback-porch = <16>;
164 vsync-len = <3>;
165 vfront-porch = <4>;
166 hsync-active = <0>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <0>;
170 };
171 };
172 };
173};
174
175&ipu1_di0_disp0 {
176 remote-endpoint = <&display0_in>;
177};
diff --git a/arch/arm/boot/dts/imx6dl-tx6u-811x.dts b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts
new file mode 100644
index 000000000000..c275eecc9472
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-tx6u-811x.dts
@@ -0,0 +1,150 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6dl.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6U-811x Module";
18 compatible = "karo,imx6dl-tx6dl", "fsl,imx6dl";
19
20 aliases {
21 display = &lvds0;
22 lvds0 = &lvds0;
23 lvds1 = &lvds1;
24 };
25
26 backlight0: backlight0 {
27 compatible = "pwm-backlight";
28 pwms = <&pwm2 0 500000 0>;
29 power-supply = <&reg_lcd0_pwr>;
30 /*
31 * a poor man's way to create a 1:1 relationship between
32 * the PWM value and the actual duty cycle
33 */
34 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
35 10 11 12 13 14 15 16 17 18 19
36 20 21 22 23 24 25 26 27 28 29
37 30 31 32 33 34 35 36 37 38 39
38 40 41 42 43 44 45 46 47 48 49
39 50 51 52 53 54 55 56 57 58 59
40 60 61 62 63 64 65 66 67 68 69
41 70 71 72 73 74 75 76 77 78 79
42 80 81 82 83 84 85 86 87 88 89
43 90 91 92 93 94 95 96 97 98 99
44 100>;
45 default-brightness-level = <50>;
46 };
47
48 backlight1: backlight1 {
49 compatible = "pwm-backlight";
50 pwms = <&pwm1 0 500000 0>;
51 power-supply = <&reg_lcd1_pwr>;
52 /*
53 * a poor man's way to create a 1:1 relationship between
54 * the PWM value and the actual duty cycle
55 */
56 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
57 10 11 12 13 14 15 16 17 18 19
58 20 21 22 23 24 25 26 27 28 29
59 30 31 32 33 34 35 36 37 38 39
60 40 41 42 43 44 45 46 47 48 49
61 50 51 52 53 54 55 56 57 58 59
62 60 61 62 63 64 65 66 67 68 69
63 70 71 72 73 74 75 76 77 78 79
64 80 81 82 83 84 85 86 87 88 89
65 90 91 92 93 94 95 96 97 98 99
66 100>;
67 default-brightness-level = <50>;
68 };
69};
70
71&i2c3 {
72 polytouch2: eeti@04 {
73 compatible = "eeti,egalax_ts";
74 reg = <0x04>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_eeti>;
77 interrupt-parent = <&gpio3>;
78 interrupts = <22 0>;
79 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
80 linux,wakeup;
81 };
82};
83
84&iomuxc {
85 imx6dl-tx6u-811x {
86 pinctrl_eeti: eetigrp {
87 fsl,pins = <
88 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
89 >;
90 };
91 };
92};
93
94&kpp {
95 status = "disabled"; /* pad conflict with backlight1 PWM */
96};
97
98&ldb {
99 status = "okay";
100
101 lvds0: lvds-channel@0 {
102 fsl,data-mapping = "spwg";
103 fsl,data-width = <18>;
104 status = "okay";
105
106 display-timings {
107 native-mode = <&lvds_timing0>;
108 lvds_timing0: hsd100pxn1 {
109 clock-frequency = <65000000>;
110 hactive = <1024>;
111 vactive = <768>;
112 hback-porch = <220>;
113 hfront-porch = <40>;
114 vback-porch = <21>;
115 vfront-porch = <7>;
116 hsync-len = <60>;
117 vsync-len = <10>;
118 de-active = <1>;
119 pixelclk-active = <1>;
120 };
121 };
122 };
123
124 lvds1: lvds-channel@1 {
125 fsl,data-mapping = "spwg";
126 fsl,data-width = <18>;
127 status = "disabled";
128
129 display-timings {
130 native-mode = <&lvds_timing1>;
131 lvds_timing1: hsd100pxn1 {
132 clock-frequency = <65000000>;
133 hactive = <1024>;
134 vactive = <768>;
135 hback-porch = <220>;
136 hfront-porch = <40>;
137 vback-porch = <21>;
138 vfront-porch = <7>;
139 hsync-len = <60>;
140 vsync-len = <10>;
141 de-active = <1>;
142 pixelclk-active = <1>;
143 };
144 };
145 };
146};
147
148&pwm1 {
149 status = "okay";
150};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
new file mode 100644
index 000000000000..f607d4f1d244
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-wandboard-revb1.dts
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6dl.dtsi"
13#include "imx6qdl-wandboard-revb1.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Dual Lite Board";
17 compatible = "wand,imx6dl-wandboard", "fsl,imx6dl";
18
19 memory {
20 reg = <0x10000000 0x40000000>;
21 };
22};
diff --git a/arch/arm/boot/dts/imx6dl-wandboard.dts b/arch/arm/boot/dts/imx6dl-wandboard.dts
index e672891c1626..bbb616723097 100644
--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11/dts-v1/; 11/dts-v1/;
12#include "imx6dl.dtsi" 12#include "imx6dl.dtsi"
13#include "imx6qdl-wandboard.dtsi" 13#include "imx6qdl-wandboard-revc1.dtsi"
14 14
15/ { 15/ {
16 model = "Wandboard i.MX6 Dual Lite Board"; 16 model = "Wandboard i.MX6 Dual Lite Board";
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 0a9c49d69d41..b453e0e28aee 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -35,8 +35,11 @@
35 396000 1175000 35 396000 1175000
36 >; 36 >;
37 clock-latency = <61036>; /* two CLK32 periods */ 37 clock-latency = <61036>; /* two CLK32 periods */
38 clocks = <&clks 104>, <&clks 6>, <&clks 16>, 38 clocks = <&clks IMX6QDL_CLK_ARM>,
39 <&clks 17>, <&clks 170>; 39 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
40 <&clks IMX6QDL_CLK_STEP>,
41 <&clks IMX6QDL_CLK_PLL1_SW>,
42 <&clks IMX6QDL_CLK_PLL1_SYS>;
40 clock-names = "arm", "pll2_pfd2_396m", "step", 43 clock-names = "arm", "pll2_pfd2_396m", "step",
41 "pll1_sw", "pll1_sys"; 44 "pll1_sw", "pll1_sys";
42 arm-supply = <&reg_arm>; 45 arm-supply = <&reg_arm>;
@@ -56,7 +59,7 @@
56 ocram: sram@00900000 { 59 ocram: sram@00900000 {
57 compatible = "mmio-sram"; 60 compatible = "mmio-sram";
58 reg = <0x00900000 0x20000>; 61 reg = <0x00900000 0x20000>;
59 clocks = <&clks 142>; 62 clocks = <&clks IMX6QDL_CLK_OCRAM>;
60 }; 63 };
61 64
62 aips1: aips-bus@02000000 { 65 aips1: aips-bus@02000000 {
@@ -87,7 +90,7 @@
87 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 90 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
88 reg = <0x021f8000 0x4000>; 91 reg = <0x021f8000 0x4000>;
89 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 92 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clks 116>; 93 clocks = <&clks IMX6DL_CLK_I2C4>;
91 status = "disabled"; 94 status = "disabled";
92 }; 95 };
93 }; 96 };
@@ -104,9 +107,9 @@
104}; 107};
105 108
106&ldb { 109&ldb {
107 clocks = <&clks 33>, <&clks 34>, 110 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
108 <&clks 39>, <&clks 40>, 111 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
109 <&clks 135>, <&clks 136>; 112 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
110 clock-names = "di0_pll", "di1_pll", 113 clock-names = "di0_pll", "di1_pll",
111 "di0_sel", "di1_sel", 114 "di0_sel", "di1_sel",
112 "di0", "di1"; 115 "di0", "di1";
diff --git a/arch/arm/boot/dts/imx6q-cubox-i.dts b/arch/arm/boot/dts/imx6q-cubox-i.dts
index bc5f31e3e892..9efd8b0c8011 100644
--- a/arch/arm/boot/dts/imx6q-cubox-i.dts
+++ b/arch/arm/boot/dts/imx6q-cubox-i.dts
@@ -13,4 +13,8 @@
13 13
14&sata { 14&sata {
15 status = "okay"; 15 status = "okay";
16 fsl,transmit-level-mV = <1104>;
17 fsl,transmit-boost-mdB = <0>;
18 fsl,transmit-atten-16ths = <9>;
19 fsl,no-spread-spectrum;
16}; 20};
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index e0302636aff5..8c1cb53464a0 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -95,6 +95,12 @@
95 }; 95 };
96}; 96};
97 97
98&can1 {
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_can1>;
101 status = "okay";
102};
103
98&ecspi5 { 104&ecspi5 {
99 pinctrl-names = "default"; 105 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_ecspi5>; 106 pinctrl-0 = <&pinctrl_ecspi5>;
@@ -118,6 +124,13 @@
118 status = "okay"; 124 status = "okay";
119}; 125};
120 126
127&i2c1 {
128 clock-frequency = <100000>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_i2c1>;
131 status = "okay";
132};
133
121&i2c2 { 134&i2c2 {
122 clock-frequency = <100000>; 135 clock-frequency = <100000>;
123 pinctrl-names = "default"; 136 pinctrl-names = "default";
@@ -274,6 +287,13 @@
274 }; 287 };
275}; 288};
276 289
290&i2c3 {
291 clock-frequency = <100000>;
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_i2c3>;
294 status = "okay";
295};
296
277&iomuxc { 297&iomuxc {
278 pinctrl-names = "default"; 298 pinctrl-names = "default";
279 pinctrl-0 = <&pinctrl_hog>; 299 pinctrl-0 = <&pinctrl_hog>;
@@ -286,6 +306,13 @@
286 >; 306 >;
287 }; 307 };
288 308
309 pinctrl_can1: can1grp {
310 fsl,pins = <
311 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
312 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
313 >;
314 };
315
289 pinctrl_ecspi5: ecspi5rp-1 { 316 pinctrl_ecspi5: ecspi5rp-1 {
290 fsl,pins = < 317 fsl,pins = <
291 MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000 318 MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO 0x80000000
@@ -316,6 +343,13 @@
316 >; 343 >;
317 }; 344 };
318 345
346 pinctrl_i2c1: i2c1grp {
347 fsl,pins = <
348 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
349 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
350 >;
351 };
352
319 pinctrl_i2c2: i2c2grp { 353 pinctrl_i2c2: i2c2grp {
320 fsl,pins = < 354 fsl,pins = <
321 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1 355 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
@@ -323,6 +357,19 @@
323 >; 357 >;
324 }; 358 };
325 359
360 pinctrl_i2c3: i2c3grp {
361 fsl,pins = <
362 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
363 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
364 >;
365 };
366
367 pinctrl_pcie: pciegrp {
368 fsl,pins = <
369 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x100b1
370 >;
371 };
372
326 pinctrl_pfuze: pfuze100grp1 { 373 pinctrl_pfuze: pfuze100grp1 {
327 fsl,pins = < 374 fsl,pins = <
328 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000 375 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x80000000
@@ -385,6 +432,13 @@
385 }; 432 };
386}; 433};
387 434
435&pcie {
436 pinctrl-names = "default";
437 pinctrl-0 = <&pinctrl_pcie>;
438 reset-gpio = <&gpio4 8 0>;
439 status = "okay";
440};
441
388&sata { 442&sata {
389 status = "okay"; 443 status = "okay";
390}; 444};
diff --git a/arch/arm/boot/dts/imx6q-gw51xx.dts b/arch/arm/boot/dts/imx6q-gw51xx.dts
index 0e1406e58eff..8e8bcd8fe0fb 100644
--- a/arch/arm/boot/dts/imx6q-gw51xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw51xx.dts
@@ -14,6 +14,6 @@
14#include "imx6qdl-gw51xx.dtsi" 14#include "imx6qdl-gw51xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW51XX"; 17 model = "Gateworks Ventana i.MX6 Dual/Quad GW51XX";
18 compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; 18 compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q";
19}; 19};
diff --git a/arch/arm/boot/dts/imx6q-gw52xx.dts b/arch/arm/boot/dts/imx6q-gw52xx.dts
index 5f71ddbc7f05..a12c47e5ee05 100644
--- a/arch/arm/boot/dts/imx6q-gw52xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw52xx.dts
@@ -14,7 +14,7 @@
14#include "imx6qdl-gw52xx.dtsi" 14#include "imx6qdl-gw52xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW52XX"; 17 model = "Gateworks Ventana i.MX6 Dual/Quad GW52XX";
18 compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; 18 compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q";
19}; 19};
20 20
diff --git a/arch/arm/boot/dts/imx6q-gw53xx.dts b/arch/arm/boot/dts/imx6q-gw53xx.dts
index 360c316b4740..d76aaa83dad0 100644
--- a/arch/arm/boot/dts/imx6q-gw53xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw53xx.dts
@@ -14,7 +14,7 @@
14#include "imx6qdl-gw53xx.dtsi" 14#include "imx6qdl-gw53xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW53XX"; 17 model = "Gateworks Ventana i.MX6 Dual/Quad GW53XX";
18 compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; 18 compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q";
19}; 19};
20 20
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 3689eaa58826..22e6f8e657d2 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -115,9 +115,9 @@
115 }; 115 };
116 116
117 sound { 117 sound {
118 compatible = "fsl,imx6q-sabrelite-sgtl5000", 118 compatible = "fsl,imx6q-ventana-sgtl5000",
119 "fsl,imx-audio-sgtl5000"; 119 "fsl,imx-audio-sgtl5000";
120 model = "imx6q-sabrelite-sgtl5000"; 120 model = "sgtl5000-audio";
121 ssi-controller = <&ssi1>; 121 ssi-controller = <&ssi1>;
122 audio-codec = <&codec>; 122 audio-codec = <&codec>;
123 audio-routing = 123 audio-routing =
@@ -504,7 +504,6 @@
504}; 504};
505 505
506&ssi1 { 506&ssi1 {
507 fsl,mode = "i2s-slave";
508 status = "okay"; 507 status = "okay";
509}; 508};
510 509
diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts
index ab518d66a75e..6e8f53e92a2d 100644
--- a/arch/arm/boot/dts/imx6q-gw54xx.dts
+++ b/arch/arm/boot/dts/imx6q-gw54xx.dts
@@ -14,7 +14,7 @@
14#include "imx6qdl-gw54xx.dtsi" 14#include "imx6qdl-gw54xx.dtsi"
15 15
16/ { 16/ {
17 model = "Gateworks Ventana i.MX6 Quad GW54XX"; 17 model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
18 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; 18 compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
19}; 19};
20 20
diff --git a/arch/arm/boot/dts/imx6q-rex-pro.dts b/arch/arm/boot/dts/imx6q-rex-pro.dts
new file mode 100644
index 000000000000..3c2852b16f78
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-rex-pro.dts
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2014 FEDEVEL, Inc.
3 *
4 * Author: Robert Nelson <robertcnelson@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6q.dtsi"
13#include "imx6qdl-rex.dtsi"
14
15/ {
16 model = "Rex Pro i.MX6 Quad Board";
17 compatible = "rex,imx6q-rex-pro", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&ecspi3 {
25 flash: m25p80@0 {
26 compatible = "sst,sst25vf032b";
27 spi-max-frequency = <20000000>;
28 reg = <0>;
29 };
30};
31
32&sata {
33 status = "okay";
34};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
new file mode 100644
index 000000000000..b18fae10b2e3
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010-comtft.dts
@@ -0,0 +1,103 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6Q-1010 Module on CoMpact TFT";
18 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 0>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 native-mode = <&ET070001DM6>;
61
62 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
63 clock-frequency = <33264000>;
64 hactive = <800>;
65 vactive = <480>;
66 hback-porch = <88>;
67 hsync-len = <128>;
68 hfront-porch = <40>;
69 vback-porch = <33>;
70 vsync-len = <2>;
71 vfront-porch = <10>;
72 hsync-active = <0>;
73 vsync-active = <0>;
74 de-active = <1>;
75 pixelclk-active = <1>;
76 };
77 };
78 };
79};
80
81&can1 {
82 status = "disabled";
83};
84
85&can2 {
86 xceiver-supply = <&reg_3v3>;
87};
88
89&ipu1_di0_disp0 {
90 remote-endpoint = <&display0_in>;
91};
92
93&kpp {
94 status = "disabled";
95};
96
97&reg_can_xcvr {
98 status = "disabled";
99};
100
101&touchscreen {
102 status = "disabled";
103};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1010.dts b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
new file mode 100644
index 000000000000..b58ec9c966c8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1010.dts
@@ -0,0 +1,177 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6Q-1010 Module";
18 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 VGA {
61 clock-frequency = <25200000>;
62 hactive = <640>;
63 vactive = <480>;
64 hback-porch = <48>;
65 hsync-len = <96>;
66 hfront-porch = <16>;
67 vback-porch = <31>;
68 vsync-len = <2>;
69 vfront-porch = <12>;
70 hsync-active = <0>;
71 vsync-active = <0>;
72 de-active = <1>;
73 pixelclk-active = <0>;
74 };
75
76 ETV570 {
77 clock-frequency = <25200000>;
78 hactive = <640>;
79 vactive = <480>;
80 hback-porch = <114>;
81 hsync-len = <30>;
82 hfront-porch = <16>;
83 vback-porch = <32>;
84 vsync-len = <3>;
85 vfront-porch = <10>;
86 hsync-active = <0>;
87 vsync-active = <0>;
88 de-active = <1>;
89 pixelclk-active = <0>;
90 };
91
92 ET0350 {
93 clock-frequency = <6413760>;
94 hactive = <320>;
95 vactive = <240>;
96 hback-porch = <34>;
97 hsync-len = <34>;
98 hfront-porch = <20>;
99 vback-porch = <15>;
100 vsync-len = <3>;
101 vfront-porch = <4>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <0>;
106 };
107
108 ET0430 {
109 clock-frequency = <9009000>;
110 hactive = <480>;
111 vactive = <272>;
112 hback-porch = <2>;
113 hsync-len = <41>;
114 hfront-porch = <2>;
115 vback-porch = <2>;
116 vsync-len = <10>;
117 vfront-porch = <2>;
118 hsync-active = <0>;
119 vsync-active = <0>;
120 de-active = <1>;
121 pixelclk-active = <1>;
122 };
123
124 ET0500 {
125 clock-frequency = <33264000>;
126 hactive = <800>;
127 vactive = <480>;
128 hback-porch = <88>;
129 hsync-len = <128>;
130 hfront-porch = <40>;
131 vback-porch = <33>;
132 vsync-len = <2>;
133 vfront-porch = <10>;
134 hsync-active = <0>;
135 vsync-active = <0>;
136 de-active = <1>;
137 pixelclk-active = <0>;
138 };
139
140 ET0700 { /* same as ET0500 */
141 clock-frequency = <33264000>;
142 hactive = <800>;
143 vactive = <480>;
144 hback-porch = <88>;
145 hsync-len = <128>;
146 hfront-porch = <40>;
147 vback-porch = <33>;
148 vsync-len = <2>;
149 vfront-porch = <10>;
150 hsync-active = <0>;
151 vsync-active = <0>;
152 de-active = <1>;
153 pixelclk-active = <0>;
154 };
155
156 ETQ570 {
157 clock-frequency = <6596040>;
158 hactive = <320>;
159 vactive = <240>;
160 hback-porch = <38>;
161 hsync-len = <30>;
162 hfront-porch = <30>;
163 vback-porch = <16>;
164 vsync-len = <3>;
165 vfront-porch = <4>;
166 hsync-active = <0>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <0>;
170 };
171 };
172 };
173};
174
175&ipu1_di0_disp0 {
176 remote-endpoint = <&display0_in>;
177};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
new file mode 100644
index 000000000000..0bb9a9de62a9
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020-comtft.dts
@@ -0,0 +1,136 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6Q-1020 Module on CoMpact TFT";
18 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 0>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 native-mode = <&ET070001DM6>;
61
62 ET070001DM6: CoMTFT { /* same as ET0700 but with inverted pixel clock */
63 clock-frequency = <33264000>;
64 hactive = <800>;
65 vactive = <480>;
66 hback-porch = <88>;
67 hsync-len = <128>;
68 hfront-porch = <40>;
69 vback-porch = <33>;
70 vsync-len = <2>;
71 vfront-porch = <10>;
72 hsync-active = <0>;
73 vsync-active = <0>;
74 de-active = <1>;
75 pixelclk-active = <1>;
76 };
77 };
78 };
79};
80
81&can1 {
82 status = "disabled";
83};
84
85&can2 {
86 xceiver-supply = <&reg_3v3>;
87};
88
89&ds1339 {
90 status = "disabled";
91};
92
93&gpmi {
94 status = "disabled";
95};
96
97&iomuxc {
98 imx6qdl-tx6 {
99 pinctrl_usdhc4: usdhc4grp {
100 fsl,pins = <
101 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
102 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
103 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
104 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
105 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
106 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
107 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
108 >;
109 };
110 };
111};
112
113&ipu1_di0_disp0 {
114 remote-endpoint = <&display0_in>;
115};
116
117&kpp {
118 status = "disabled";
119};
120
121&reg_can_xcvr {
122 status = "disabled";
123};
124
125&touchscreen {
126 status = "disabled";
127};
128
129&usdhc4 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&pinctrl_usdhc4>;
132 bus-width = <4>;
133 no-1-8-v;
134 fsl,wp-controller;
135 status = "okay";
136};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1020.dts b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
new file mode 100644
index 000000000000..b96d80a35d39
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1020.dts
@@ -0,0 +1,210 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6Q-1020 Module";
18 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
19
20 aliases {
21 display = &display;
22 };
23
24 backlight: backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>;
27 power-supply = <&reg_3v3>;
28 /*
29 * a poor man's way to create a 1:1 relationship between
30 * the PWM value and the actual duty cycle
31 */
32 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
33 10 11 12 13 14 15 16 17 18 19
34 20 21 22 23 24 25 26 27 28 29
35 30 31 32 33 34 35 36 37 38 39
36 40 41 42 43 44 45 46 47 48 49
37 50 51 52 53 54 55 56 57 58 59
38 60 61 62 63 64 65 66 67 68 69
39 70 71 72 73 74 75 76 77 78 79
40 80 81 82 83 84 85 86 87 88 89
41 90 91 92 93 94 95 96 97 98 99
42 100>;
43 default-brightness-level = <50>;
44 };
45
46 display: display@di0 {
47 compatible = "fsl,imx-parallel-display";
48 interface-pix-fmt = "rgb24";
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_disp0_1>;
51 status = "okay";
52
53 port {
54 display0_in: endpoint {
55 remote-endpoint = <&ipu1_di0_disp0>;
56 };
57 };
58
59 display-timings {
60 VGA {
61 clock-frequency = <25200000>;
62 hactive = <640>;
63 vactive = <480>;
64 hback-porch = <48>;
65 hsync-len = <96>;
66 hfront-porch = <16>;
67 vback-porch = <31>;
68 vsync-len = <2>;
69 vfront-porch = <12>;
70 hsync-active = <0>;
71 vsync-active = <0>;
72 de-active = <1>;
73 pixelclk-active = <0>;
74 };
75
76 ETV570 {
77 clock-frequency = <25200000>;
78 hactive = <640>;
79 vactive = <480>;
80 hback-porch = <114>;
81 hsync-len = <30>;
82 hfront-porch = <16>;
83 vback-porch = <32>;
84 vsync-len = <3>;
85 vfront-porch = <10>;
86 hsync-active = <0>;
87 vsync-active = <0>;
88 de-active = <1>;
89 pixelclk-active = <0>;
90 };
91
92 ET0350 {
93 clock-frequency = <6413760>;
94 hactive = <320>;
95 vactive = <240>;
96 hback-porch = <34>;
97 hsync-len = <34>;
98 hfront-porch = <20>;
99 vback-porch = <15>;
100 vsync-len = <3>;
101 vfront-porch = <4>;
102 hsync-active = <0>;
103 vsync-active = <0>;
104 de-active = <1>;
105 pixelclk-active = <0>;
106 };
107
108 ET0430 {
109 clock-frequency = <9009000>;
110 hactive = <480>;
111 vactive = <272>;
112 hback-porch = <2>;
113 hsync-len = <41>;
114 hfront-porch = <2>;
115 vback-porch = <2>;
116 vsync-len = <10>;
117 vfront-porch = <2>;
118 hsync-active = <0>;
119 vsync-active = <0>;
120 de-active = <1>;
121 pixelclk-active = <1>;
122 };
123
124 ET0500 {
125 clock-frequency = <33264000>;
126 hactive = <800>;
127 vactive = <480>;
128 hback-porch = <88>;
129 hsync-len = <128>;
130 hfront-porch = <40>;
131 vback-porch = <33>;
132 vsync-len = <2>;
133 vfront-porch = <10>;
134 hsync-active = <0>;
135 vsync-active = <0>;
136 de-active = <1>;
137 pixelclk-active = <0>;
138 };
139
140 ET0700 { /* same as ET0500 */
141 clock-frequency = <33264000>;
142 hactive = <800>;
143 vactive = <480>;
144 hback-porch = <88>;
145 hsync-len = <128>;
146 hfront-porch = <40>;
147 vback-porch = <33>;
148 vsync-len = <2>;
149 vfront-porch = <10>;
150 hsync-active = <0>;
151 vsync-active = <0>;
152 de-active = <1>;
153 pixelclk-active = <0>;
154 };
155
156 ETQ570 {
157 clock-frequency = <6596040>;
158 hactive = <320>;
159 vactive = <240>;
160 hback-porch = <38>;
161 hsync-len = <30>;
162 hfront-porch = <30>;
163 vback-porch = <16>;
164 vsync-len = <3>;
165 vfront-porch = <4>;
166 hsync-active = <0>;
167 vsync-active = <0>;
168 de-active = <1>;
169 pixelclk-active = <0>;
170 };
171 };
172 };
173};
174
175&ds1339 {
176 status = "disabled";
177};
178
179&gpmi {
180 status = "disabled";
181};
182
183&iomuxc {
184 imx6qdl-tx6 {
185 pinctrl_usdhc4: usdhc4grp {
186 fsl,pins = <
187 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x070b1
188 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x070b1
189 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x070b1
190 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x070b1
191 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x070b1
192 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x070b1
193 MX6QDL_PAD_NANDF_ALE__SD4_RESET 0x0b0b1
194 >;
195 };
196 };
197};
198
199&ipu1_di0_disp0 {
200 remote-endpoint = <&display0_in>;
201};
202
203&usdhc4 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_usdhc4>;
206 bus-width = <4>;
207 no-1-8-v;
208 fsl,wp-controller;
209 status = "okay";
210};
diff --git a/arch/arm/boot/dts/imx6q-tx6q-1110.dts b/arch/arm/boot/dts/imx6q-tx6q-1110.dts
new file mode 100644
index 000000000000..88aa1e4c792d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-tx6q-1110.dts
@@ -0,0 +1,154 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13#include "imx6q.dtsi"
14#include "imx6qdl-tx6.dtsi"
15
16/ {
17 model = "Ka-Ro electronics TX6Q-1110 Module";
18 compatible = "karo,imx6q-tx6q", "fsl,imx6q";
19
20 aliases {
21 display = &lvds0;
22 lvds0 = &lvds0;
23 lvds1 = &lvds1;
24 };
25
26 backlight0: backlight0 {
27 compatible = "pwm-backlight";
28 pwms = <&pwm2 0 500000 0>;
29 power-supply = <&reg_lcd0_pwr>;
30 /*
31 * a poor man's way to create a 1:1 relationship between
32 * the PWM value and the actual duty cycle
33 */
34 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
35 10 11 12 13 14 15 16 17 18 19
36 20 21 22 23 24 25 26 27 28 29
37 30 31 32 33 34 35 36 37 38 39
38 40 41 42 43 44 45 46 47 48 49
39 50 51 52 53 54 55 56 57 58 59
40 60 61 62 63 64 65 66 67 68 69
41 70 71 72 73 74 75 76 77 78 79
42 80 81 82 83 84 85 86 87 88 89
43 90 91 92 93 94 95 96 97 98 99
44 100>;
45 default-brightness-level = <50>;
46 };
47
48 backlight1: backlight1 {
49 compatible = "pwm-backlight";
50 pwms = <&pwm1 0 500000 0>;
51 power-supply = <&reg_lcd1_pwr>;
52 /*
53 * a poor man's way to create a 1:1 relationship between
54 * the PWM value and the actual duty cycle
55 */
56 brightness-levels = < 0 1 2 3 4 5 6 7 8 9
57 10 11 12 13 14 15 16 17 18 19
58 20 21 22 23 24 25 26 27 28 29
59 30 31 32 33 34 35 36 37 38 39
60 40 41 42 43 44 45 46 47 48 49
61 50 51 52 53 54 55 56 57 58 59
62 60 61 62 63 64 65 66 67 68 69
63 70 71 72 73 74 75 76 77 78 79
64 80 81 82 83 84 85 86 87 88 89
65 90 91 92 93 94 95 96 97 98 99
66 100>;
67 default-brightness-level = <50>;
68 };
69};
70
71&i2c3 {
72 polytouch1: eeti@04 {
73 compatible = "eeti,egalax_ts";
74 reg = <0x04>;
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_eeti>;
77 interrupt-parent = <&gpio3>;
78 interrupts = <22 0>;
79 wakeup-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
80 linux,wakeup;
81 };
82};
83
84&iomuxc {
85 imx6q-tx6q-1110 {
86 pinctrl_eeti: eetigrp {
87 fsl,pins = <
88 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b1 /* Interrupt */
89 >;
90 };
91 };
92};
93
94&kpp {
95 status = "disabled"; /* pad conflict with backlight1 PWM */
96};
97
98&ldb {
99 status = "okay";
100
101 lvds0: lvds-channel@0 {
102 fsl,data-mapping = "spwg";
103 fsl,data-width = <18>;
104 status = "okay";
105
106 display-timings {
107 native-mode = <&lvds_timing0>;
108 lvds_timing0: hsd100pxn1 {
109 clock-frequency = <65000000>;
110 hactive = <1024>;
111 vactive = <768>;
112 hback-porch = <220>;
113 hfront-porch = <40>;
114 vback-porch = <21>;
115 vfront-porch = <7>;
116 hsync-len = <60>;
117 vsync-len = <10>;
118 de-active = <1>;
119 pixelclk-active = <1>;
120 };
121 };
122 };
123
124 lvds1: lvds-channel@1 {
125 fsl,data-mapping = "spwg";
126 fsl,data-width = <18>;
127 status = "disabled";
128
129 display-timings {
130 native-mode = <&lvds_timing1>;
131 lvds_timing1: hsd100pxn1 {
132 clock-frequency = <65000000>;
133 hactive = <1024>;
134 vactive = <768>;
135 hback-porch = <220>;
136 hfront-porch = <40>;
137 vback-porch = <21>;
138 vfront-porch = <7>;
139 hsync-len = <60>;
140 vsync-len = <10>;
141 de-active = <1>;
142 pixelclk-active = <1>;
143 };
144 };
145 };
146};
147
148&pwm1 {
149 status = "okay";
150};
151
152&sata {
153 status = "okay";
154};
diff --git a/arch/arm/boot/dts/imx6q-udoo.dts b/arch/arm/boot/dts/imx6q-udoo.dts
index 6c561060bf5c..e3bff2ac00db 100644
--- a/arch/arm/boot/dts/imx6q-udoo.dts
+++ b/arch/arm/boot/dts/imx6q-udoo.dts
@@ -23,6 +23,23 @@
23 memory { 23 memory {
24 reg = <0x10000000 0x40000000>; 24 reg = <0x10000000 0x40000000>;
25 }; 25 };
26
27 regulators {
28 compatible = "simple-bus";
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 reg_usb_h1_vbus: regulator@0 {
33 compatible = "regulator-fixed";
34 reg = <0>;
35 regulator-name = "usb_h1_vbus";
36 regulator-min-microvolt = <5000000>;
37 regulator-max-microvolt = <5000000>;
38 enable-active-high;
39 startup-delay-us = <2>; /* USB2415 requires a POR of 1 us minimum */
40 gpio = <&gpio7 12 0>;
41 };
42 };
26}; 43};
27 44
28&fec { 45&fec {
@@ -81,6 +98,13 @@
81 >; 98 >;
82 }; 99 };
83 100
101 pinctrl_usbh: usbhgrp {
102 fsl,pins = <
103 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000
104 MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x130b0
105 >;
106 };
107
84 pinctrl_usdhc3: usdhc3grp { 108 pinctrl_usdhc3: usdhc3grp {
85 fsl,pins = < 109 fsl,pins = <
86 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 110 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
@@ -104,6 +128,14 @@
104 status = "okay"; 128 status = "okay";
105}; 129};
106 130
131&usbh1 {
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_usbh>;
134 vbus-supply = <&reg_usb_h1_vbus>;
135 clocks = <&clks 201>;
136 status = "okay";
137};
138
107&usdhc3 { 139&usdhc3 {
108 pinctrl-names = "default"; 140 pinctrl-names = "default";
109 pinctrl-0 = <&pinctrl_usdhc3>; 141 pinctrl-0 = <&pinctrl_usdhc3>;
diff --git a/arch/arm/boot/dts/imx6q-wandboard-revb1.dts b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
new file mode 100644
index 000000000000..20bf3c282623
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-wandboard-revb1.dts
@@ -0,0 +1,26 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11/dts-v1/;
12#include "imx6q.dtsi"
13#include "imx6qdl-wandboard-revb1.dtsi"
14
15/ {
16 model = "Wandboard i.MX6 Quad Board";
17 compatible = "wand,imx6q-wandboard", "fsl,imx6q";
18
19 memory {
20 reg = <0x10000000 0x80000000>;
21 };
22};
23
24&sata {
25 status = "okay";
26};
diff --git a/arch/arm/boot/dts/imx6q-wandboard.dts b/arch/arm/boot/dts/imx6q-wandboard.dts
index 36be17f207b1..4a8a6ee13e9f 100644
--- a/arch/arm/boot/dts/imx6q-wandboard.dts
+++ b/arch/arm/boot/dts/imx6q-wandboard.dts
@@ -10,7 +10,7 @@
10 */ 10 */
11/dts-v1/; 11/dts-v1/;
12#include "imx6q.dtsi" 12#include "imx6q.dtsi"
13#include "imx6qdl-wandboard.dtsi" 13#include "imx6qdl-wandboard-revc1.dtsi"
14 14
15/ { 15/ {
16 model = "Wandboard i.MX6 Quad Board"; 16 model = "Wandboard i.MX6 Quad Board";
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index addd3f881ce2..e9f3646d1760 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -43,8 +43,11 @@
43 396000 1175000 43 396000 1175000
44 >; 44 >;
45 clock-latency = <61036>; /* two CLK32 periods */ 45 clock-latency = <61036>; /* two CLK32 periods */
46 clocks = <&clks 104>, <&clks 6>, <&clks 16>, 46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks 17>, <&clks 170>; 47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
48 clock-names = "arm", "pll2_pfd2_396m", "step", 51 clock-names = "arm", "pll2_pfd2_396m", "step",
49 "pll1_sw", "pll1_sys"; 52 "pll1_sw", "pll1_sys";
50 arm-supply = <&reg_arm>; 53 arm-supply = <&reg_arm>;
@@ -78,7 +81,7 @@
78 ocram: sram@00900000 { 81 ocram: sram@00900000 {
79 compatible = "mmio-sram"; 82 compatible = "mmio-sram";
80 reg = <0x00900000 0x40000>; 83 reg = <0x00900000 0x40000>;
81 clocks = <&clks 142>; 84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
82 }; 85 };
83 86
84 aips-bus@02000000 { /* AIPS1 */ 87 aips-bus@02000000 { /* AIPS1 */
@@ -89,7 +92,8 @@
89 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 92 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
90 reg = <0x02018000 0x4000>; 93 reg = <0x02018000 0x4000>;
91 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 94 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&clks 116>, <&clks 116>; 95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
93 clock-names = "ipg", "per"; 97 clock-names = "ipg", "per";
94 status = "disabled"; 98 status = "disabled";
95 }; 99 };
@@ -140,7 +144,9 @@
140 compatible = "fsl,imx6q-ahci"; 144 compatible = "fsl,imx6q-ahci";
141 reg = <0x02200000 0x4000>; 145 reg = <0x02200000 0x4000>;
142 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 146 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&clks 154>, <&clks 187>, <&clks 105>; 147 clocks = <&clks IMX6QDL_CLK_SATA>,
148 <&clks IMX6QDL_CLK_SATA_REF_100M>,
149 <&clks IMX6QDL_CLK_AHB>;
144 clock-names = "sata", "sata_ref", "ahb"; 150 clock-names = "sata", "sata_ref", "ahb";
145 status = "disabled"; 151 status = "disabled";
146 }; 152 };
@@ -152,10 +158,20 @@
152 reg = <0x02800000 0x400000>; 158 reg = <0x02800000 0x400000>;
153 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, 159 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
154 <0 7 IRQ_TYPE_LEVEL_HIGH>; 160 <0 7 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&clks 133>, <&clks 134>, <&clks 137>; 161 clocks = <&clks IMX6QDL_CLK_IPU2>,
162 <&clks IMX6QDL_CLK_IPU2_DI0>,
163 <&clks IMX6QDL_CLK_IPU2_DI1>;
156 clock-names = "bus", "di0", "di1"; 164 clock-names = "bus", "di0", "di1";
157 resets = <&src 4>; 165 resets = <&src 4>;
158 166
167 ipu2_csi0: port@0 {
168 reg = <0>;
169 };
170
171 ipu2_csi1: port@1 {
172 reg = <1>;
173 };
174
159 ipu2_di0: port@2 { 175 ipu2_di0: port@2 {
160 #address-cells = <1>; 176 #address-cells = <1>;
161 #size-cells = <0>; 177 #size-cells = <0>;
@@ -230,9 +246,10 @@
230}; 246};
231 247
232&ldb { 248&ldb {
233 clocks = <&clks 33>, <&clks 34>, 249 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
234 <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>, 250 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
235 <&clks 135>, <&clks 136>; 251 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
252 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
236 clock-names = "di0_pll", "di1_pll", 253 clock-names = "di0_pll", "di1_pll",
237 "di0_sel", "di1_sel", "di2_sel", "di3_sel", 254 "di0_sel", "di1_sel", "di2_sel", "di3_sel",
238 "di0", "di1"; 255 "di0", "di1";
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
new file mode 100644
index 000000000000..e6d9195a1da7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -0,0 +1,418 @@
1/*
2 * support fot the imx6 based aristainetos board
3 *
4 * Copyright (C) 2014 Heiko Schocher <hs@denx.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 regulators {
16 compatible = "simple-bus";
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 reg_2p5v: regulator@0 {
21 compatible = "regulator-fixed";
22 regulator-name = "2P5V";
23 regulator-min-microvolt = <2500000>;
24 regulator-max-microvolt = <2500000>;
25 regulator-always-on;
26 };
27
28 reg_3p3v: regulator@1 {
29 compatible = "regulator-fixed";
30 regulator-name = "3P3V";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
33 regulator-always-on;
34 };
35
36 reg_usbh1_vbus: regulator@2 {
37 compatible = "regulator-fixed";
38 enable-active-high;
39 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
40 pinctrl-names = "default";
41 pinctrl-0 = <&pinctrl_aristainetos_usbh1_vbus>;
42 regulator-name = "usb_h1_vbus";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 };
46
47 reg_usbotg_vbus: regulator@3 {
48 compatible = "regulator-fixed";
49 enable-active-high;
50 gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>;
51 pinctrl-names = "default";
52 pinctrl-0 = <&pinctrl_aristainetos_usbotg_vbus>;
53 regulator-name = "usb_otg_vbus";
54 regulator-min-microvolt = <5000000>;
55 regulator-max-microvolt = <5000000>;
56 };
57 };
58};
59
60&audmux {
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_audmux>;
63 status = "okay";
64};
65
66&can1 {
67 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_flexcan1>;
69 status = "okay";
70};
71
72&can2 {
73 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_flexcan2>;
75 status = "okay";
76};
77
78&i2c1 {
79 clock-frequency = <100000>;
80 pinctrl-names = "default";
81 pinctrl-0 = <&pinctrl_i2c1>;
82 status = "okay";
83
84 tmp103: tmp103@71 {
85 compatible = "ti,tmp103";
86 reg = <0x71>;
87 };
88};
89
90&i2c3 {
91 clock-frequency = <100000>;
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_i2c3>;
94 status = "okay";
95
96 rtc@68 {
97 compatible = "dallas,m41t00";
98 reg = <0x68>;
99 };
100};
101
102&ecspi4 {
103 fsl,spi-num-chipselects = <1>;
104 cs-gpios = <&gpio3 20 0>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_ecspi4>;
107 status = "okay";
108
109 flash: m25p80@0 {
110 #address-cells = <1>;
111 #size-cells = <1>;
112 compatible = "micron,n25q128a11";
113 spi-max-frequency = <20000000>;
114 reg = <0>;
115 };
116};
117
118&fec {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_enet>;
121 phy-mode = "rmii";
122 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
123 status = "okay";
124};
125
126&gpmi {
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_gpmi_nand>;
129 status = "okay";
130};
131
132&pcie {
133 status = "okay";
134};
135
136&uart2 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_uart2>;
139 status = "okay";
140};
141
142
143&uart4 {
144 pinctrl-names = "default";
145 pinctrl-0 = <&pinctrl_uart4>;
146 fsl,uart-has-rtscts;
147 status = "okay";
148};
149
150&uart5 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_uart5>;
153 fsl,uart-has-rtscts;
154 status = "okay";
155};
156
157&usbh1 {
158 vbus-supply = <&reg_usbh1_vbus>;
159 dr_mode = "host";
160 status = "okay";
161};
162
163&usbotg {
164 vbus-supply = <&reg_usbotg_vbus>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_usbotg>;
167 disable-over-current;
168 dr_mode = "host";
169 status = "okay";
170};
171
172&usdhc1 {
173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_usdhc1>;
175 vmmc-supply = <&reg_3p3v>;
176 cd-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
177 status = "okay";
178};
179
180&usdhc2 {
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_usdhc2>;
183 vmmc-supply = <&reg_3p3v>;
184 cd-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
185 status = "okay";
186};
187
188&iomuxc {
189 pinctrl-names = "default";
190 pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
191
192 imx6qdl-aristainetos {
193 pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
194 fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
195 };
196
197 pinctrl_aristainetos_usbotg_vbus: aristainetos-usbotg-vbus {
198 fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x130b0>;
199 };
200
201 pinctrl_audmux: audmuxgrp {
202 fsl,pins = <
203 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0
204 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0
205 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0
206 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0
207 >;
208 };
209
210 pinctrl_backlight: backlightgrp {
211 fsl,pins = <
212 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0
213 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b0
214 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
215 >;
216 };
217
218 pinctrl_ecspi2: ecspi2grp {
219 fsl,pins = <
220 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
221 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
222 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
223 MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x100b1
224 >;
225 };
226
227 pinctrl_ecspi4: ecspi4grp {
228 fsl,pins = <
229 MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
230 MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
231 MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
232 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x100b1
233 MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */
234 >;
235 };
236
237 pinctrl_enet: enetgrp {
238 fsl,pins = <
239 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
240 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
241 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
242 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
243 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
244 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
245 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
246 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
247 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
248 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
249 >;
250 };
251
252 pinctrl_flexcan1: flexcan1grp {
253 fsl,pins = <
254 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
255 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
256 >;
257 };
258
259 pinctrl_flexcan2: flexcan2grp {
260 fsl,pins = <
261 MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
262 MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
263 >;
264 };
265
266 pinctrl_gpio: gpiogrp {
267 fsl,pins = <
268 MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
269 MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0
270 MX6QDL_PAD_SD4_DAT4__GPIO2_IO12 0x1b0b0
271 MX6QDL_PAD_SD4_DAT5__GPIO2_IO13 0x1b0b0
272 MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x1b0b0
273 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
274 MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b0
275 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
276 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0
277 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0
278 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
279 >;
280 };
281
282 pinctrl_gpmi_nand: gpminandgrp {
283 fsl,pins = <
284 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
285 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
286 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
287 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
288 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
289 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
290 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
291 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
292 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
293 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
294 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
295 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
296 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
297 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
298 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
299 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
300 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
301 >;
302 };
303
304 pinctrl_hog: hoggrp {
305 fsl,pins = <
306 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x10
307 >;
308 };
309
310 pinctrl_i2c1: i2c1grp {
311 fsl,pins = <
312 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
313 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
314 >;
315 };
316
317 pinctrl_i2c2: i2c2grp {
318 fsl,pins = <
319 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
320 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
321 >;
322 };
323
324 pinctrl_i2c3: i2c3grp {
325 fsl,pins = <
326 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
327 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
328 >;
329 };
330
331 pinctrl_ipu_disp: ipudisp1grp {
332 fsl,pins = <
333 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
334 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
335 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
336 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
337 MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x20000
338 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
339 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
340 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
341 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
342 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
343 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
344 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
345 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
346 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
347 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
348 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
349 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
350 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
351 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
352 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
353 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
354 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
355 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
356 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
357 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
358 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
359 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
360 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
361 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
362 >;
363 };
364
365 pinctrl_uart2: uart2grp {
366 fsl,pins = <
367 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
368 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
369 >;
370 };
371
372 pinctrl_uart4: uart4grp {
373 fsl,pins = <
374 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
375 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
376 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
377 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
378 >;
379 };
380
381 pinctrl_uart5: uart5grp {
382 fsl,pins = <
383 MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x1b0b1
384 MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x1b0b1
385 >;
386 };
387
388 pinctrl_usbotg: usbotggrp {
389 fsl,pins = <
390 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
391 >;
392 };
393
394 pinctrl_usdhc1: usdhc1grp {
395 fsl,pins = <
396 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
397 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
398 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
399 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
400 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
401 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
402 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
403 >;
404 };
405
406 pinctrl_usdhc2: usdhc2grp {
407 fsl,pins = <
408 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
409 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
410 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
411 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
412 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
413 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
414 MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
415 >;
416 };
417 };
418};
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 744c8a2d81f6..234e7b755232 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -121,9 +121,9 @@
121 }; 121 };
122 122
123 sound { 123 sound {
124 compatible = "fsl,imx6q-sabrelite-sgtl5000", 124 compatible = "fsl,imx6q-ventana-sgtl5000",
125 "fsl,imx-audio-sgtl5000"; 125 "fsl,imx-audio-sgtl5000";
126 model = "imx6q-sabrelite-sgtl5000"; 126 model = "sgtl5000-audio";
127 ssi-controller = <&ssi1>; 127 ssi-controller = <&ssi1>;
128 audio-codec = <&codec>; 128 audio-codec = <&codec>;
129 audio-routing = 129 audio-routing =
@@ -489,7 +489,6 @@
489}; 489};
490 490
491&ssi1 { 491&ssi1 {
492 fsl,mode = "i2s-slave";
493 status = "okay"; 492 status = "okay";
494}; 493};
495 494
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index adf150c1be90..143f84f7812c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -124,9 +124,9 @@
124 }; 124 };
125 125
126 sound { 126 sound {
127 compatible = "fsl,imx6q-sabrelite-sgtl5000", 127 compatible = "fsl,imx6q-ventana-sgtl5000",
128 "fsl,imx-audio-sgtl5000"; 128 "fsl,imx-audio-sgtl5000";
129 model = "imx6q-sabrelite-sgtl5000"; 129 model = "sgtl5000-audio";
130 ssi-controller = <&ssi1>; 130 ssi-controller = <&ssi1>;
131 audio-codec = <&codec>; 131 audio-codec = <&codec>;
132 audio-routing = 132 audio-routing =
@@ -533,7 +533,6 @@
533}; 533};
534 534
535&ssi1 { 535&ssi1 {
536 fsl,mode = "i2s-slave";
537 status = "okay"; 536 status = "okay";
538}; 537};
539 538
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 698d3063b295..16e7ad3d98ad 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -114,9 +114,9 @@
114 }; 114 };
115 115
116 sound { 116 sound {
117 compatible = "fsl,imx6q-sabrelite-sgtl5000", 117 compatible = "fsl,imx6q-ventana-sgtl5000",
118 "fsl,imx-audio-sgtl5000"; 118 "fsl,imx-audio-sgtl5000";
119 model = "imx6q-sabrelite-sgtl5000"; 119 model = "sgtl5000-audio";
120 ssi-controller = <&ssi1>; 120 ssi-controller = <&ssi1>;
121 audio-codec = <&codec>; 121 audio-codec = <&codec>;
122 audio-routing = 122 audio-routing =
@@ -555,12 +555,10 @@
555}; 555};
556 556
557&ssi1 { 557&ssi1 {
558 fsl,mode = "i2s-slave";
559 status = "okay"; 558 status = "okay";
560}; 559};
561 560
562&ssi2 { 561&ssi2 {
563 fsl,mode = "i2s-slave";
564 status = "okay"; 562 status = "okay";
565}; 563};
566 564
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 4c4b17596c8b..42ff525ebe13 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -381,7 +381,6 @@
381}; 381};
382 382
383&ssi1 { 383&ssi1 {
384 fsl,mode = "i2s-slave";
385 status = "okay"; 384 status = "okay";
386}; 385};
387 386
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index faa3494a69d4..2694aa84e187 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -301,6 +301,7 @@
301 pinctrl-0 = <&pinctrl_enet>; 301 pinctrl-0 = <&pinctrl_enet>;
302 phy-mode = "rgmii"; 302 phy-mode = "rgmii";
303 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; 303 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
304 phy-supply = <&vdd_eth_io_reg>;
304 status = "disabled"; 305 status = "disabled";
305}; 306};
306 307
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
new file mode 100644
index 000000000000..df7bcf86c156
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -0,0 +1,357 @@
1/*
2 * Copyright 2014 FEDEVEL, Inc.
3 *
4 * Author: Robert Nelson <robertcnelson@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14
15/ {
16 chosen {
17 stdout-path = &uart1;
18 };
19
20 regulators {
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 reg_3p3v: regulator@0 {
26 compatible = "regulator-fixed";
27 reg = <0>;
28 regulator-name = "3P3V";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
31 regulator-always-on;
32 };
33
34 reg_usbh1_vbus: regulator@1 {
35 compatible = "regulator-fixed";
36 reg = <1>;
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_usbh1>;
39 regulator-name = "usbh1_vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
42 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
43 enable-active-high;
44 };
45
46 reg_usb_otg_vbus: regulator@2 {
47 compatible = "regulator-fixed";
48 reg = <2>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_usbotg>;
51 regulator-name = "usb_otg_vbus";
52 regulator-min-microvolt = <5000000>;
53 regulator-max-microvolt = <5000000>;
54 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
55 enable-active-high;
56 };
57 };
58
59 leds {
60 compatible = "gpio-leds";
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_led>;
63
64 led0: usr {
65 label = "usr";
66 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
67 default-state = "off";
68 linux,default-trigger = "heartbeat";
69 };
70 };
71
72 sound {
73 compatible = "fsl,imx6-rex-sgtl5000",
74 "fsl,imx-audio-sgtl5000";
75 model = "imx6-rex-sgtl5000";
76 ssi-controller = <&ssi1>;
77 audio-codec = <&codec>;
78 audio-routing =
79 "MIC_IN", "Mic Jack",
80 "Mic Jack", "Mic Bias",
81 "Headphone Jack", "HP_OUT";
82 mux-int-port = <1>;
83 mux-ext-port = <3>;
84 };
85};
86
87&audmux {
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_audmux>;
90 status = "okay";
91};
92
93&ecspi2 {
94 fsl,spi-num-chipselects = <1>;
95 cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&pinctrl_ecspi2>;
98 status = "okay";
99};
100
101&ecspi3 {
102 fsl,spi-num-chipselects = <1>;
103 cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_ecspi3>;
106 status = "okay";
107};
108
109&fec {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_enet>;
112 phy-mode = "rgmii";
113 phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
114 status = "okay";
115};
116
117&hdmi {
118 ddc-i2c-bus = <&i2c2>;
119 status = "okay";
120};
121
122&i2c1 {
123 clock-frequency = <100000>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_i2c1>;
126 status = "okay";
127
128 codec: sgtl5000@0a {
129 compatible = "fsl,sgtl5000";
130 reg = <0x0a>;
131 clocks = <&clks 201>;
132 VDDA-supply = <&reg_3p3v>;
133 VDDIO-supply = <&reg_3p3v>;
134 };
135};
136
137&i2c2 {
138 clock-frequency = <100000>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_i2c2>;
141 status = "okay";
142
143 eeprom@57 {
144 compatible = "at,24c02";
145 reg = <0x57>;
146 };
147};
148
149&i2c3 {
150 clock-frequency = <100000>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_i2c3>;
153 status = "okay";
154};
155
156&iomuxc {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_hog>;
159
160 imx6qdl-rex {
161 pinctrl_hog: hoggrp {
162 fsl,pins = <
163 /* SGTL5000 sys_mclk */
164 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
165 >;
166 };
167
168 pinctrl_audmux: audmuxgrp {
169 fsl,pins = <
170 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
171 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
172 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
173 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
174 >;
175 };
176
177 pinctrl_ecspi2: ecspi2grp {
178 fsl,pins = <
179 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
180 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
181 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
182 /* CS */
183 MX6QDL_PAD_DISP0_DAT5__GPIO4_IO26 0x000b1
184 >;
185 };
186
187 pinctrl_ecspi3: ecspi3grp {
188 fsl,pins = <
189 MX6QDL_PAD_DISP0_DAT17__ECSPI2_MISO 0x100b1
190 MX6QDL_PAD_DISP0_DAT16__ECSPI2_MOSI 0x100b1
191 MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x100b1
192 /* CS */
193 MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000b1
194 >;
195 };
196
197 pinctrl_enet: enetgrp {
198 fsl,pins = <
199 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
200 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
201 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
202 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
203 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
204 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
205 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
206 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
207 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
208 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
209 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
210 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
211 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
212 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
213 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
214 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
215 /* Phy reset */
216 MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x000b0
217 >;
218 };
219
220 pinctrl_i2c1: i2c1grp {
221 fsl,pins = <
222 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
223 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
224 >;
225 };
226
227 pinctrl_i2c2: i2c2grp {
228 fsl,pins = <
229 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
230 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
231 >;
232 };
233
234 pinctrl_i2c3: i2c3grp {
235 fsl,pins = <
236 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
237 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
238 >;
239 };
240
241 pinctrl_led: ledgrp {
242 fsl,pins = <
243 /* user led */
244 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
245 >;
246 };
247
248 pinctrl_uart1: uart1grp {
249 fsl,pins = <
250 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
251 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
252 >;
253 };
254
255 pinctrl_uart2: uart2grp {
256 fsl,pins = <
257 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
258 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
259 >;
260 };
261
262 pinctrl_usbh1: usbh1grp {
263 fsl,pins = <
264 /* power enable, high active */
265 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x10b0
266 >;
267 };
268
269 pinctrl_usbotg: usbotggrp {
270 fsl,pins = <
271 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
272 MX6QDL_PAD_EIM_D21__USB_OTG_OC 0x1b0b0
273 /* power enable, high active */
274 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x10b0
275 >;
276 };
277
278 pinctrl_usdhc2: usdhc2grp {
279 fsl,pins = <
280 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
281 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
282 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
283 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
284 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
285 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
286 /* CD */
287 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
288 /* WP */
289 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1f0b0
290 >;
291 };
292
293 pinctrl_usdhc3: usdhc3grp {
294 fsl,pins = <
295 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
296 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
297 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
298 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
299 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
300 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
301 /* CD */
302 MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
303 /* WP */
304 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1f0b0
305 >;
306 };
307 };
308};
309
310&ssi1 {
311 fsl,mode = "i2s-slave";
312 status = "okay";
313};
314
315&uart1 {
316 pinctrl-names = "default";
317 pinctrl-0 = <&pinctrl_uart1>;
318 status = "okay";
319};
320
321&uart2 {
322 pinctrl-names = "default";
323 pinctrl-0 = <&pinctrl_uart2>;
324 status = "okay";
325};
326
327&usbh1 {
328 vbus-supply = <&reg_usbh1_vbus>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_usbh1>;
331 status = "okay";
332};
333
334&usbotg {
335 vbus-supply = <&reg_usb_otg_vbus>;
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_usbotg>;
338 status = "okay";
339};
340
341&usdhc2 {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_usdhc2>;
344 bus-width = <4>;
345 cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
346 wp-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
347 status = "okay";
348};
349
350&usdhc3 {
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_usdhc3>;
353 bus-width = <4>;
354 cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
355 wp-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
356 status = "okay";
357};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 6df6127bf835..0a36129152e0 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -381,7 +381,6 @@
381}; 381};
382 382
383&ssi1 { 383&ssi1 {
384 fsl,mode = "i2s-slave";
385 status = "okay"; 384 status = "okay";
386}; 385};
387 386
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 40ea36534643..ec43dde78525 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -340,6 +340,7 @@
340 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1 340 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
341 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1 341 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
342 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1 342 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
343 MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
343 >; 344 >;
344 }; 345 };
345 346
@@ -512,7 +513,6 @@
512}; 513};
513 514
514&ssi2 { 515&ssi2 {
515 fsl,mode = "i2s-slave";
516 status = "okay"; 516 status = "okay";
517}; 517};
518 518
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
new file mode 100644
index 000000000000..f02b80b41d4f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -0,0 +1,696 @@
1/*
2 * Copyright 2014 Lothar Waßmann <LW@KARO-electronics.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/input/input.h>
14#include <dt-bindings/pwm/pwm.h>
15
16/ {
17 aliases {
18 can0 = &can2;
19 can1 = &can1;
20 ethernet0 = &fec;
21 lcdif_23bit_pins_a = &pinctrl_disp0_1;
22 lcdif_24bit_pins_a = &pinctrl_disp0_2;
23 pwm0 = &pwm1;
24 pwm1 = &pwm2;
25 reg_can_xcvr = &reg_can_xcvr;
26 stk5led = &user_led;
27 usbotg = &usbotg;
28 sdhc0 = &usdhc1;
29 sdhc1 = &usdhc2;
30 };
31
32 memory {
33 reg = <0 0>; /* will be filled by U-Boot */
34 };
35
36 clocks {
37 #address-cells = <1>;
38 #size-cells = <0>;
39 mclk: clock@0 {
40 compatible = "fixed-clock";
41 reg = <0>;
42 #clock-cells = <0>;
43 clock-frequency = <27000000>;
44 };
45 };
46
47 gpio-keys {
48 compatible = "gpio-keys";
49
50 power {
51 label = "Power Button";
52 gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
53 linux,code = <KEY_POWER>;
54 gpio-key,wakeup;
55 };
56 };
57
58 leds {
59 compatible = "gpio-leds";
60
61 user_led: user {
62 label = "Heartbeat";
63 gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
64 linux,default-trigger = "heartbeat";
65 };
66 };
67
68 regulators {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <0>;
72
73 reg_3v3_etn: regulator@0 {
74 compatible = "regulator-fixed";
75 reg = <0>;
76 regulator-name = "3V3_ETN";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_etnphy_power>;
81 gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
82 enable-active-high;
83 };
84
85 reg_2v5: regulator@1 {
86 compatible = "regulator-fixed";
87 reg = <1>;
88 regulator-name = "2V5";
89 regulator-min-microvolt = <2500000>;
90 regulator-max-microvolt = <2500000>;
91 regulator-always-on;
92 };
93
94 reg_3v3: regulator@2 {
95 compatible = "regulator-fixed";
96 reg = <2>;
97 regulator-name = "3V3";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 regulator-always-on;
101 };
102
103 reg_can_xcvr: regulator@3 {
104 compatible = "regulator-fixed";
105 reg = <3>;
106 regulator-name = "CAN XCVR";
107 regulator-min-microvolt = <3300000>;
108 regulator-max-microvolt = <3300000>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_flexcan_xcvr>;
111 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
112 enable-active-low;
113 };
114
115 reg_lcd0_pwr: regulator@4 {
116 compatible = "regulator-fixed";
117 reg = <4>;
118 regulator-name = "LCD0 POWER";
119 regulator-min-microvolt = <3300000>;
120 regulator-max-microvolt = <3300000>;
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_lcd0_pwr>;
123 gpio = <&gpio3 29 GPIO_ACTIVE_HIGH>;
124 enable-active-high;
125 regulator-boot-on;
126 regulator-always-on;
127 };
128
129 reg_lcd1_pwr: regulator@5 {
130 compatible = "regulator-fixed";
131 reg = <5>;
132 regulator-name = "LCD1 POWER";
133 regulator-min-microvolt = <3300000>;
134 regulator-max-microvolt = <3300000>;
135 pinctrl-names = "default";
136 pinctrl-0 = <&pinctrl_lcd1_pwr>;
137 gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>;
138 enable-active-high;
139 regulator-boot-on;
140 regulator-always-on;
141 };
142
143 reg_usbh1_vbus: regulator@6 {
144 compatible = "regulator-fixed";
145 reg = <6>;
146 regulator-name = "usbh1_vbus";
147 regulator-min-microvolt = <5000000>;
148 regulator-max-microvolt = <5000000>;
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_usbh1_vbus>;
151 gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>;
152 enable-active-high;
153 };
154
155 reg_usbotg_vbus: regulator@7 {
156 compatible = "regulator-fixed";
157 reg = <7>;
158 regulator-name = "usbotg_vbus";
159 regulator-min-microvolt = <5000000>;
160 regulator-max-microvolt = <5000000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_usbotg_vbus>;
163 gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
164 enable-active-high;
165 };
166 };
167
168 sound {
169 compatible = "karo,imx6qdl-tx6qdl-sgtl5000",
170 "fsl,imx-audio-sgtl5000";
171 model = "sgtl5000-audio";
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_audmux>;
174 ssi-controller = <&ssi1>;
175 audio-codec = <&sgtl5000>;
176 audio-routing =
177 "MIC_IN", "Mic Jack",
178 "Mic Jack", "Mic Bias",
179 "Headphone Jack", "HP_OUT";
180 mux-int-port = <1>;
181 mux-ext-port = <5>;
182 };
183};
184
185&audmux {
186 status = "okay";
187};
188
189&can1 {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_flexcan1>;
192 xceiver-supply = <&reg_can_xcvr>;
193 status = "okay";
194};
195
196&can2 {
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_flexcan2>;
199 xceiver-supply = <&reg_can_xcvr>;
200 status = "okay";
201};
202
203&ecspi1 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_ecspi1>;
206 fsl,spi-num-chipselects = <2>;
207 cs-gpios = <
208 &gpio2 30 GPIO_ACTIVE_HIGH
209 &gpio3 19 GPIO_ACTIVE_HIGH
210 >;
211 status = "okay";
212
213 spidev0: spi@0 {
214 compatible = "spidev";
215 reg = <0>;
216 spi-max-frequency = <54000000>;
217 };
218
219 spidev1: spi@1 {
220 compatible = "spidev";
221 reg = <1>;
222 spi-max-frequency = <54000000>;
223 };
224};
225
226&fec {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_enet>;
229 phy-mode = "rmii";
230 phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
231 phy-supply = <&reg_3v3_etn>;
232 status = "okay";
233};
234
235&gpmi {
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_gpmi_nand>;
238 nand-on-flash-bbt;
239 fsl,no-blockmark-swap;
240 status = "okay";
241};
242
243&i2c1 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c1>;
246 clock-frequency = <400000>;
247 status = "okay";
248
249 ds1339: rtc@68 {
250 compatible = "dallas,ds1339";
251 reg = <0x68>;
252 };
253};
254
255&i2c3 {
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c3>;
258 clock-frequency = <400000>;
259 status = "okay";
260
261 sgtl5000: sgtl5000@0a {
262 compatible = "fsl,sgtl5000";
263 reg = <0x0a>;
264 VDDA-supply = <&reg_2v5>;
265 VDDIO-supply = <&reg_3v3>;
266 clocks = <&mclk>;
267 };
268
269 polytouch: edt-ft5x06@38 {
270 compatible = "edt,edt-ft5x06";
271 reg = <0x38>;
272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_edt_ft5x06>;
274 interrupt-parent = <&gpio6>;
275 interrupts = <15 0>;
276 reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
277 wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
278 linux,wakeup;
279 };
280
281 touchscreen: tsc2007@48 {
282 compatible = "ti,tsc2007";
283 reg = <0x48>;
284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_tsc2007>;
286 interrupt-parent = <&gpio3>;
287 interrupts = <26 0>;
288 gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
289 ti,x-plate-ohms = <660>;
290 linux,wakeup;
291 };
292};
293
294&iomuxc {
295 pinctrl-names = "default";
296 pinctrl-0 = <&pinctrl_hog>;
297
298 imx6qdl-tx6 {
299 pinctrl_hog: hoggrp {
300 fsl,pins = <
301 MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b1 /* LED */
302 MX6QDL_PAD_SD3_DAT2__GPIO7_IO06 0x1b0b1 /* ETN PHY RESET */
303 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b1 /* ETN PHY INT */
304 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b1 /* PWR BTN */
305 >;
306 };
307
308 pinctrl_audmux: audmuxgrp {
309 fsl,pins = <
310 MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0 /* SSI1_RXD */
311 MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0 /* SSI1_TXD */
312 MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 /* SSI1_CLK */
313 MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0 /* SSI1_FS */
314 >;
315 };
316
317 pinctrl_disp0_1: disp0grp-1 {
318 fsl,pins = <
319 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
320 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
321 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
322 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
323 /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */
324 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
325 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
326 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
327 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
328 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
329 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
330 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
331 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
332 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
333 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
334 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
335 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
336 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
337 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
338 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
339 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
340 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
341 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
342 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
343 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
344 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
345 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
346 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
347 >;
348 };
349
350 pinctrl_disp0_2: disp0grp-2 {
351 fsl,pins = <
352 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
353 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
354 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
355 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
356 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
357 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
358 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
359 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
360 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
361 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
362 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
363 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
364 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
365 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
366 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
367 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
368 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
369 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
370 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
371 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
372 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
373 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
374 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
375 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
376 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
377 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
378 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
379 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
380 >;
381 };
382
383 pinctrl_ecspi1: ecspi1grp {
384 fsl,pins = <
385 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x0b0b0
386 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x0b0b0
387 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x0b0b0
388 MX6QDL_PAD_GPIO_19__ECSPI1_RDY 0x0b0b0
389 MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x0b0b0 /* SPI CS0 */
390 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x0b0b0 /* SPI CS1 */
391 >;
392 };
393
394 pinctrl_edt_ft5x06: edt-ft5x06grp {
395 fsl,pins = <
396 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 /* Interrupt */
397 MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* Reset */
398 MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* Wake */
399 >;
400 };
401
402 pinctrl_enet: enetgrp {
403 fsl,pins = <
404 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
405 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
406 MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
407 MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
408 MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
409 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
410 MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
411 MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
412 MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
413 >;
414 };
415
416 pinctrl_etnphy_power: etnphy-pwrgrp {
417 fsl,pins = <
418 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b1 /* ETN PHY POWER */
419 >;
420 };
421
422 pinctrl_flexcan1: flexcan1grp {
423 fsl,pins = <
424 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
425 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
426 >;
427 };
428
429 pinctrl_flexcan2: flexcan2grp {
430 fsl,pins = <
431 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
432 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
433 >;
434 };
435
436 pinctrl_flexcan_xcvr: flexcan-xcvrgrp {
437 fsl,pins = <
438 MX6QDL_PAD_DISP0_DAT0__GPIO4_IO21 0x1b0b0 /* Flexcan XCVR enable */
439 >;
440 };
441
442 pinctrl_gpmi_nand: gpminandgrp {
443 fsl,pins = <
444 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0x0b0b1
445 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0x0b0b1
446 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0x0b0b1
447 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0x0b000
448 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0x0b0b1
449 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0x0b0b1
450 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0x0b0b1
451 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0x0b0b1
452 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0x0b0b1
453 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0x0b0b1
454 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0x0b0b1
455 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0x0b0b1
456 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0x0b0b1
457 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0x0b0b1
458 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0x0b0b1
459 >;
460 };
461
462 pinctrl_i2c1: i2c1grp {
463 fsl,pins = <
464 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
465 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
466 >;
467 };
468
469 pinctrl_i2c3: i2c3grp {
470 fsl,pins = <
471 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
472 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
473 >;
474 };
475
476 pinctrl_kpp: kppgrp {
477 fsl,pins = <
478 MX6QDL_PAD_GPIO_9__KEY_COL6 0x1b0b1
479 MX6QDL_PAD_GPIO_4__KEY_COL7 0x1b0b1
480 MX6QDL_PAD_KEY_COL2__KEY_COL2 0x1b0b1
481 MX6QDL_PAD_KEY_COL3__KEY_COL3 0x1b0b1
482 MX6QDL_PAD_GPIO_2__KEY_ROW6 0x1b0b1
483 MX6QDL_PAD_GPIO_5__KEY_ROW7 0x1b0b1
484 MX6QDL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b1
485 MX6QDL_PAD_KEY_ROW3__KEY_ROW3 0x1b0b1
486 >;
487 };
488
489 pinctrl_lcd0_pwr: lcd0-pwrgrp {
490 fsl,pins = <
491 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x1b0b1 /* LCD Reset */
492 >;
493 };
494
495 pinctrl_lcd1_pwr: lcd1-pwrgrp {
496 fsl,pins = <
497 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b1 /* LCD Power Enable */
498 >;
499 };
500
501 pinctrl_pwm1: pwm1grp {
502 fsl,pins = <
503 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
504 >;
505 };
506
507 pinctrl_pwm2: pwm2grp {
508 fsl,pins = <
509 MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
510 >;
511 };
512
513 pinctrl_tsc2007: tsc2007grp {
514 fsl,pins = <
515 MX6QDL_PAD_EIM_D26__GPIO3_IO26 0x1b0b0 /* Interrupt */
516 >;
517 };
518
519 pinctrl_uart1: uart1grp {
520 fsl,pins = <
521 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
522 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
523 >;
524 };
525
526 pinctrl_uart1_rtscts: uart1_rtsctsgrp {
527 fsl,pins = <
528 MX6QDL_PAD_SD3_DAT1__UART1_RTS_B 0x1b0b1
529 MX6QDL_PAD_SD3_DAT0__UART1_CTS_B 0x1b0b1
530 >;
531 };
532
533 pinctrl_uart2: uart2grp {
534 fsl,pins = <
535 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
536 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
537 >;
538 };
539
540 pinctrl_uart2_rtscts: uart2_rtsctsgrp {
541 fsl,pins = <
542 MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
543 MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
544 >;
545 };
546
547 pinctrl_uart3: uart3grp {
548 fsl,pins = <
549 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
550 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
551 >;
552 };
553
554 pinctrl_uart3_rtscts: uart3_rtsctsgrp {
555 fsl,pins = <
556 MX6QDL_PAD_SD3_DAT3__UART3_CTS_B 0x1b0b1
557 MX6QDL_PAD_SD3_RST__UART3_RTS_B 0x1b0b1
558 >;
559 };
560
561 pinctrl_usbh1_vbus: usbh1-vbusgrp {
562 fsl,pins = <
563 MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x1b0b0 /* USBH1_VBUSEN */
564 >;
565 };
566
567 pinctrl_usbotg: usbotggrp {
568 fsl,pins = <
569 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x17059
570 >;
571 };
572
573 pinctrl_usbotg_vbus: usbotg-vbusgrp {
574 fsl,pins = <
575 MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* USBOTG_VBUSEN */
576 >;
577 };
578
579 pinctrl_usdhc1: usdhc1grp {
580 fsl,pins = <
581 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x070b1
582 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x070b1
583 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x070b1
584 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x070b1
585 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x070b1
586 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x070b1
587 MX6QDL_PAD_SD3_CMD__GPIO7_IO02 0x170b0 /* SD1 CD */
588 >;
589 };
590
591 pinctrl_usdhc2: usdhc2grp {
592 fsl,pins = <
593 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x070b1
594 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x070b1
595 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x070b1
596 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x070b1
597 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x070b1
598 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x070b1
599 MX6QDL_PAD_SD3_CLK__GPIO7_IO03 0x170b0 /* SD2 CD */
600 >;
601 };
602 };
603};
604
605&kpp {
606 pinctrl-names = "default";
607 pinctrl-0 = <&pinctrl_kpp>;
608 /* sample keymap */
609 /* row/col 0,1 are mapped to KPP row/col 6,7 */
610 linux,keymap = <
611 MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */
612 MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */
613 MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */
614 MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */
615 MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */
616 MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */
617 MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */
618 MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */
619 MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */
620 MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */
621 MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */
622 >;
623 status = "okay";
624};
625
626&pwm1 {
627 pinctrl-names = "default";
628 pinctrl-0 = <&pinctrl_pwm1>;
629 #pwm-cells = <3>;
630 status = "disabled";
631};
632
633&pwm2 {
634 pinctrl-names = "default";
635 pinctrl-0 = <&pinctrl_pwm2>;
636 #pwm-cells = <3>;
637 status = "okay";
638};
639
640&ssi1 {
641 status = "okay";
642};
643
644&uart1 {
645 pinctrl-names = "default";
646 pinctrl-0 = <&pinctrl_uart1>;
647 status = "okay";
648};
649
650&uart2 {
651 pinctrl-names = "default";
652 pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>;
653 status = "okay";
654};
655
656&uart3 {
657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart3 &pinctrl_uart3_rtscts>;
659 status = "okay";
660};
661
662&usbh1 {
663 vbus-supply = <&reg_usbh1_vbus>;
664 dr_mode = "host";
665 disable-over-current;
666 status = "okay";
667};
668
669&usbotg {
670 vbus-supply = <&reg_usbotg_vbus>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_usbotg>;
673 dr_mode = "peripheral";
674 disable-over-current;
675 status = "okay";
676};
677
678&usdhc1 {
679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_usdhc1>;
681 bus-width = <4>;
682 no-1-8-v;
683 cd-gpios = <&gpio7 2 0>;
684 fsl,wp-controller;
685 status = "okay";
686};
687
688&usdhc2 {
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_usdhc2>;
691 bus-width = <4>;
692 no-1-8-v;
693 cd-gpios = <&gpio7 3 0>;
694 fsl,wp-controller;
695 status = "okay";
696};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
new file mode 100644
index 000000000000..ef7fa62b9898
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include "imx6qdl-wandboard.dtsi"
13
14&iomuxc {
15 pinctrl-0 = <&pinctrl_hog>;
16
17 imx6qdl-wandboard {
18 pinctrl_hog: hoggrp {
19 fsl,pins = <
20 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
21 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
22 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
23 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x0f0b0 /* WL_REF_ON */
24 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x0f0b0 /* WL_RST_N */
25 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON */
26 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
27 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
28 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
29 MX6QDL_PAD_EIM_DA13__GPIO3_IO13 0x80000000 /* BT_ON */
30 MX6QDL_PAD_EIM_DA14__GPIO3_IO14 0x80000000 /* BT_WAKE */
31 MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x80000000 /* BT_HOST_WAKE */
32 >;
33 };
34 };
35};
36
37&usdhc2 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_usdhc2>;
40 non-removable;
41 status = "okay";
42};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
new file mode 100644
index 000000000000..8d893a78cdf0
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
@@ -0,0 +1,41 @@
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include "imx6qdl-wandboard.dtsi"
13
14&iomuxc {
15 pinctrl-0 = <&pinctrl_hog>;
16
17 imx6qdl-wandboard {
18 pinctrl_hog: hoggrp {
19 fsl,pins = <
20 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* GPIO_0_CLKO */
21 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* uSDHC1 CD */
22 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000 /* uSDHC3 CD */
23 MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00 0x0f0b0 /* WIFI_ON (reset, active low) */
24 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x000b0 /* WL_REG_ON (unused) */
25 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE, input */
26 MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31 0x0f0b0 /* GPIO5_IO31 (Wifi Power Enable) */
27 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE (unused) */
28 MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0x80000000 /* BT_ON */
29 MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30 0x80000000 /* BT_WAKE */
30 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x80000000 /* BT_HOST_WAKE */
31 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000 /* RGMII_nRST */
32 >;
33 };
34 };
35};
36
37&usdhc2 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_usdhc2>;
40 status = "okay";
41};
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 5c6f10c43f65..5fb091675582 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -91,22 +91,8 @@
91 91
92&iomuxc { 92&iomuxc {
93 pinctrl-names = "default"; 93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_hog>;
95 94
96 imx6qdl-wandboard { 95 imx6qdl-wandboard {
97 pinctrl_hog: hoggrp {
98 fsl,pins = <
99 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
100 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
101 MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
102 MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
103 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
104 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
105 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
106 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
107 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
108 >;
109 };
110 96
111 pinctrl_audmux: audmuxgrp { 97 pinctrl_audmux: audmuxgrp {
112 fsl,pins = < 98 fsl,pins = <
@@ -233,7 +219,6 @@
233}; 219};
234 220
235&ssi1 { 221&ssi1 {
236 fsl,mode = "i2s-slave";
237 status = "okay"; 222 status = "okay";
238}; 223};
239 224
@@ -269,13 +254,6 @@
269 status = "okay"; 254 status = "okay";
270}; 255};
271 256
272&usdhc2 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usdhc2>;
275 non-removable;
276 status = "okay";
277};
278
279&usdhc3 { 257&usdhc3 {
280 pinctrl-names = "default"; 258 pinctrl-names = "default";
281 pinctrl-0 = <&pinctrl_usdhc3>; 259 pinctrl-0 = <&pinctrl_usdhc3>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index ce0599134a69..c701af958006 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -10,6 +10,7 @@
10 * http://www.gnu.org/copyleft/gpl.html 10 * http://www.gnu.org/copyleft/gpl.html
11 */ 11 */
12 12
13#include <dt-bindings/clock/imx6qdl-clock.h>
13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/arm-gic.h>
14 15
15#include "skeleton.dtsi" 16#include "skeleton.dtsi"
@@ -94,7 +95,7 @@
94 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
95 #dma-cells = <1>; 96 #dma-cells = <1>;
96 dma-channels = <4>; 97 dma-channels = <4>;
97 clocks = <&clks 106>; 98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
98 }; 99 };
99 100
100 gpmi: gpmi-nand@00112000 { 101 gpmi: gpmi-nand@00112000 {
@@ -105,8 +106,11 @@
105 reg-names = "gpmi-nand", "bch"; 106 reg-names = "gpmi-nand", "bch";
106 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
107 interrupt-names = "bch"; 108 interrupt-names = "bch";
108 clocks = <&clks 152>, <&clks 153>, <&clks 151>, 109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
109 <&clks 150>, <&clks 149>; 110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
110 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 114 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
111 "gpmi_bch_apb", "per1_bch"; 115 "gpmi_bch_apb", "per1_bch";
112 dmas = <&dma_apbh 0>; 116 dmas = <&dma_apbh 0>;
@@ -118,7 +122,7 @@
118 compatible = "arm,cortex-a9-twd-timer"; 122 compatible = "arm,cortex-a9-twd-timer";
119 reg = <0x00a00600 0x20>; 123 reg = <0x00a00600 0x20>;
120 interrupts = <1 13 0xf01>; 124 interrupts = <1 13 0xf01>;
121 clocks = <&clks 15>; 125 clocks = <&clks IMX6QDL_CLK_TWD>;
122 }; 126 };
123 127
124 L2: l2-cache@00a02000 { 128 L2: l2-cache@00a02000 {
@@ -149,7 +153,9 @@
149 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 153 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 154 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 155 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&clks 144>, <&clks 206>, <&clks 189>; 156 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
157 <&clks IMX6QDL_CLK_LVDS1_GATE>,
158 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
153 clock-names = "pcie", "pcie_bus", "pcie_phy"; 159 clock-names = "pcie", "pcie_bus", "pcie_phy";
154 status = "disabled"; 160 status = "disabled";
155 }; 161 };
@@ -180,11 +186,11 @@
180 dmas = <&sdma 14 18 0>, 186 dmas = <&sdma 14 18 0>,
181 <&sdma 15 18 0>; 187 <&sdma 15 18 0>;
182 dma-names = "rx", "tx"; 188 dma-names = "rx", "tx";
183 clocks = <&clks 197>, <&clks 3>, 189 clocks = <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_OSC>,
184 <&clks 197>, <&clks 107>, 190 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_DUMMY>,
185 <&clks 0>, <&clks 118>, 191 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
186 <&clks 0>, <&clks 139>, 192 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>,
187 <&clks 0>; 193 <&clks IMX6QDL_CLK_DUMMY>;
188 clock-names = "core", "rxtx0", 194 clock-names = "core", "rxtx0",
189 "rxtx1", "rxtx2", 195 "rxtx1", "rxtx2",
190 "rxtx3", "rxtx4", 196 "rxtx3", "rxtx4",
@@ -199,7 +205,8 @@
199 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 205 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
200 reg = <0x02008000 0x4000>; 206 reg = <0x02008000 0x4000>;
201 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 207 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
202 clocks = <&clks 112>, <&clks 112>; 208 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
209 <&clks IMX6QDL_CLK_ECSPI1>;
203 clock-names = "ipg", "per"; 210 clock-names = "ipg", "per";
204 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>; 211 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
205 dma-names = "rx", "tx"; 212 dma-names = "rx", "tx";
@@ -212,7 +219,8 @@
212 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 219 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
213 reg = <0x0200c000 0x4000>; 220 reg = <0x0200c000 0x4000>;
214 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 221 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
215 clocks = <&clks 113>, <&clks 113>; 222 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
223 <&clks IMX6QDL_CLK_ECSPI2>;
216 clock-names = "ipg", "per"; 224 clock-names = "ipg", "per";
217 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>; 225 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
218 dma-names = "rx", "tx"; 226 dma-names = "rx", "tx";
@@ -225,7 +233,8 @@
225 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 233 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
226 reg = <0x02010000 0x4000>; 234 reg = <0x02010000 0x4000>;
227 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 235 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&clks 114>, <&clks 114>; 236 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
237 <&clks IMX6QDL_CLK_ECSPI3>;
229 clock-names = "ipg", "per"; 238 clock-names = "ipg", "per";
230 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>; 239 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
231 dma-names = "rx", "tx"; 240 dma-names = "rx", "tx";
@@ -238,7 +247,8 @@
238 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 247 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
239 reg = <0x02014000 0x4000>; 248 reg = <0x02014000 0x4000>;
240 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 249 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clks 115>, <&clks 115>; 250 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
251 <&clks IMX6QDL_CLK_ECSPI4>;
242 clock-names = "ipg", "per"; 252 clock-names = "ipg", "per";
243 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>; 253 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
244 dma-names = "rx", "tx"; 254 dma-names = "rx", "tx";
@@ -249,7 +259,8 @@
249 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 259 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
250 reg = <0x02020000 0x4000>; 260 reg = <0x02020000 0x4000>;
251 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 261 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
252 clocks = <&clks 160>, <&clks 161>; 262 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
263 <&clks IMX6QDL_CLK_UART_SERIAL>;
253 clock-names = "ipg", "per"; 264 clock-names = "ipg", "per";
254 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 265 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
255 dma-names = "rx", "tx"; 266 dma-names = "rx", "tx";
@@ -263,46 +274,40 @@
263 274
264 ssi1: ssi@02028000 { 275 ssi1: ssi@02028000 {
265 compatible = "fsl,imx6q-ssi", 276 compatible = "fsl,imx6q-ssi",
266 "fsl,imx51-ssi", 277 "fsl,imx51-ssi";
267 "fsl,imx21-ssi";
268 reg = <0x02028000 0x4000>; 278 reg = <0x02028000 0x4000>;
269 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 279 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&clks 178>; 280 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>;
271 dmas = <&sdma 37 1 0>, 281 dmas = <&sdma 37 1 0>,
272 <&sdma 38 1 0>; 282 <&sdma 38 1 0>;
273 dma-names = "rx", "tx"; 283 dma-names = "rx", "tx";
274 fsl,fifo-depth = <15>; 284 fsl,fifo-depth = <15>;
275 fsl,ssi-dma-events = <38 37>;
276 status = "disabled"; 285 status = "disabled";
277 }; 286 };
278 287
279 ssi2: ssi@0202c000 { 288 ssi2: ssi@0202c000 {
280 compatible = "fsl,imx6q-ssi", 289 compatible = "fsl,imx6q-ssi",
281 "fsl,imx51-ssi", 290 "fsl,imx51-ssi";
282 "fsl,imx21-ssi";
283 reg = <0x0202c000 0x4000>; 291 reg = <0x0202c000 0x4000>;
284 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 292 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&clks 179>; 293 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>;
286 dmas = <&sdma 41 1 0>, 294 dmas = <&sdma 41 1 0>,
287 <&sdma 42 1 0>; 295 <&sdma 42 1 0>;
288 dma-names = "rx", "tx"; 296 dma-names = "rx", "tx";
289 fsl,fifo-depth = <15>; 297 fsl,fifo-depth = <15>;
290 fsl,ssi-dma-events = <42 41>;
291 status = "disabled"; 298 status = "disabled";
292 }; 299 };
293 300
294 ssi3: ssi@02030000 { 301 ssi3: ssi@02030000 {
295 compatible = "fsl,imx6q-ssi", 302 compatible = "fsl,imx6q-ssi",
296 "fsl,imx51-ssi", 303 "fsl,imx51-ssi";
297 "fsl,imx21-ssi";
298 reg = <0x02030000 0x4000>; 304 reg = <0x02030000 0x4000>;
299 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 305 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
300 clocks = <&clks 180>; 306 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>;
301 dmas = <&sdma 45 1 0>, 307 dmas = <&sdma 45 1 0>,
302 <&sdma 46 1 0>; 308 <&sdma 46 1 0>;
303 dma-names = "rx", "tx"; 309 dma-names = "rx", "tx";
304 fsl,fifo-depth = <15>; 310 fsl,fifo-depth = <15>;
305 fsl,ssi-dma-events = <46 45>;
306 status = "disabled"; 311 status = "disabled";
307 }; 312 };
308 313
@@ -331,7 +336,8 @@
331 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 336 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
332 reg = <0x02080000 0x4000>; 337 reg = <0x02080000 0x4000>;
333 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 338 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&clks 62>, <&clks 145>; 339 clocks = <&clks IMX6QDL_CLK_IPG>,
340 <&clks IMX6QDL_CLK_PWM1>;
335 clock-names = "ipg", "per"; 341 clock-names = "ipg", "per";
336 }; 342 };
337 343
@@ -340,7 +346,8 @@
340 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 346 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
341 reg = <0x02084000 0x4000>; 347 reg = <0x02084000 0x4000>;
342 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 348 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&clks 62>, <&clks 146>; 349 clocks = <&clks IMX6QDL_CLK_IPG>,
350 <&clks IMX6QDL_CLK_PWM2>;
344 clock-names = "ipg", "per"; 351 clock-names = "ipg", "per";
345 }; 352 };
346 353
@@ -349,7 +356,8 @@
349 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 356 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
350 reg = <0x02088000 0x4000>; 357 reg = <0x02088000 0x4000>;
351 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
352 clocks = <&clks 62>, <&clks 147>; 359 clocks = <&clks IMX6QDL_CLK_IPG>,
360 <&clks IMX6QDL_CLK_PWM3>;
353 clock-names = "ipg", "per"; 361 clock-names = "ipg", "per";
354 }; 362 };
355 363
@@ -358,7 +366,8 @@
358 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 366 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
359 reg = <0x0208c000 0x4000>; 367 reg = <0x0208c000 0x4000>;
360 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 368 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&clks 62>, <&clks 148>; 369 clocks = <&clks IMX6QDL_CLK_IPG>,
370 <&clks IMX6QDL_CLK_PWM4>;
362 clock-names = "ipg", "per"; 371 clock-names = "ipg", "per";
363 }; 372 };
364 373
@@ -366,7 +375,8 @@
366 compatible = "fsl,imx6q-flexcan"; 375 compatible = "fsl,imx6q-flexcan";
367 reg = <0x02090000 0x4000>; 376 reg = <0x02090000 0x4000>;
368 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 377 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&clks 108>, <&clks 109>; 378 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
379 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
370 clock-names = "ipg", "per"; 380 clock-names = "ipg", "per";
371 status = "disabled"; 381 status = "disabled";
372 }; 382 };
@@ -375,7 +385,8 @@
375 compatible = "fsl,imx6q-flexcan"; 385 compatible = "fsl,imx6q-flexcan";
376 reg = <0x02094000 0x4000>; 386 reg = <0x02094000 0x4000>;
377 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 387 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks 110>, <&clks 111>; 388 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
389 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
379 clock-names = "ipg", "per"; 390 clock-names = "ipg", "per";
380 status = "disabled"; 391 status = "disabled";
381 }; 392 };
@@ -384,7 +395,8 @@
384 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 395 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
385 reg = <0x02098000 0x4000>; 396 reg = <0x02098000 0x4000>;
386 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 397 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&clks 119>, <&clks 120>; 398 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
399 <&clks IMX6QDL_CLK_GPT_IPG_PER>;
388 clock-names = "ipg", "per"; 400 clock-names = "ipg", "per";
389 }; 401 };
390 402
@@ -466,22 +478,25 @@
466 }; 478 };
467 479
468 kpp: kpp@020b8000 { 480 kpp: kpp@020b8000 {
481 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
469 reg = <0x020b8000 0x4000>; 482 reg = <0x020b8000 0x4000>;
470 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 483 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks IMX6QDL_CLK_IPG>;
485 status = "disabled";
471 }; 486 };
472 487
473 wdog1: wdog@020bc000 { 488 wdog1: wdog@020bc000 {
474 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 489 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
475 reg = <0x020bc000 0x4000>; 490 reg = <0x020bc000 0x4000>;
476 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 491 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
477 clocks = <&clks 0>; 492 clocks = <&clks IMX6QDL_CLK_DUMMY>;
478 }; 493 };
479 494
480 wdog2: wdog@020c0000 { 495 wdog2: wdog@020c0000 {
481 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 496 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
482 reg = <0x020c0000 0x4000>; 497 reg = <0x020c0000 0x4000>;
483 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 498 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&clks 0>; 499 clocks = <&clks IMX6QDL_CLK_DUMMY>;
485 status = "disabled"; 500 status = "disabled";
486 }; 501 };
487 502
@@ -599,14 +614,14 @@
599 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 614 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
600 fsl,tempmon = <&anatop>; 615 fsl,tempmon = <&anatop>;
601 fsl,tempmon-data = <&ocotp>; 616 fsl,tempmon-data = <&ocotp>;
602 clocks = <&clks 172>; 617 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
603 }; 618 };
604 619
605 usbphy1: usbphy@020c9000 { 620 usbphy1: usbphy@020c9000 {
606 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 621 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
607 reg = <0x020c9000 0x1000>; 622 reg = <0x020c9000 0x1000>;
608 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 623 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&clks 182>; 624 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
610 fsl,anatop = <&anatop>; 625 fsl,anatop = <&anatop>;
611 }; 626 };
612 627
@@ -614,7 +629,7 @@
614 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 629 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
615 reg = <0x020ca000 0x1000>; 630 reg = <0x020ca000 0x1000>;
616 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 631 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&clks 183>; 632 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
618 fsl,anatop = <&anatop>; 633 fsl,anatop = <&anatop>;
619 }; 634 };
620 635
@@ -727,7 +742,8 @@
727 reg = <0x00120000 0x9000>; 742 reg = <0x00120000 0x9000>;
728 interrupts = <0 115 0x04>; 743 interrupts = <0 115 0x04>;
729 gpr = <&gpr>; 744 gpr = <&gpr>;
730 clocks = <&clks 123>, <&clks 124>; 745 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
746 <&clks IMX6QDL_CLK_HDMI_ISFR>;
731 clock-names = "iahb", "isfr"; 747 clock-names = "iahb", "isfr";
732 status = "disabled"; 748 status = "disabled";
733 749
@@ -762,7 +778,8 @@
762 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 778 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
763 reg = <0x020ec000 0x4000>; 779 reg = <0x020ec000 0x4000>;
764 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 780 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
765 clocks = <&clks 155>, <&clks 155>; 781 clocks = <&clks IMX6QDL_CLK_SDMA>,
782 <&clks IMX6QDL_CLK_SDMA>;
766 clock-names = "ipg", "ahb"; 783 clock-names = "ipg", "ahb";
767 #dma-cells = <3>; 784 #dma-cells = <3>;
768 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 785 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
@@ -790,7 +807,7 @@
790 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 807 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
791 reg = <0x02184000 0x200>; 808 reg = <0x02184000 0x200>;
792 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 809 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clks 162>; 810 clocks = <&clks IMX6QDL_CLK_USBOH3>;
794 fsl,usbphy = <&usbphy1>; 811 fsl,usbphy = <&usbphy1>;
795 fsl,usbmisc = <&usbmisc 0>; 812 fsl,usbmisc = <&usbmisc 0>;
796 status = "disabled"; 813 status = "disabled";
@@ -800,7 +817,7 @@
800 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 817 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
801 reg = <0x02184200 0x200>; 818 reg = <0x02184200 0x200>;
802 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 819 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
803 clocks = <&clks 162>; 820 clocks = <&clks IMX6QDL_CLK_USBOH3>;
804 fsl,usbphy = <&usbphy2>; 821 fsl,usbphy = <&usbphy2>;
805 fsl,usbmisc = <&usbmisc 1>; 822 fsl,usbmisc = <&usbmisc 1>;
806 status = "disabled"; 823 status = "disabled";
@@ -810,7 +827,7 @@
810 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 827 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
811 reg = <0x02184400 0x200>; 828 reg = <0x02184400 0x200>;
812 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 829 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
813 clocks = <&clks 162>; 830 clocks = <&clks IMX6QDL_CLK_USBOH3>;
814 fsl,usbmisc = <&usbmisc 2>; 831 fsl,usbmisc = <&usbmisc 2>;
815 status = "disabled"; 832 status = "disabled";
816 }; 833 };
@@ -819,7 +836,7 @@
819 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 836 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
820 reg = <0x02184600 0x200>; 837 reg = <0x02184600 0x200>;
821 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 838 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
822 clocks = <&clks 162>; 839 clocks = <&clks IMX6QDL_CLK_USBOH3>;
823 fsl,usbmisc = <&usbmisc 3>; 840 fsl,usbmisc = <&usbmisc 3>;
824 status = "disabled"; 841 status = "disabled";
825 }; 842 };
@@ -828,7 +845,7 @@
828 #index-cells = <1>; 845 #index-cells = <1>;
829 compatible = "fsl,imx6q-usbmisc"; 846 compatible = "fsl,imx6q-usbmisc";
830 reg = <0x02184800 0x200>; 847 reg = <0x02184800 0x200>;
831 clocks = <&clks 162>; 848 clocks = <&clks IMX6QDL_CLK_USBOH3>;
832 }; 849 };
833 850
834 fec: ethernet@02188000 { 851 fec: ethernet@02188000 {
@@ -837,7 +854,9 @@
837 interrupts-extended = 854 interrupts-extended =
838 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, 855 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
839 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 856 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&clks 117>, <&clks 117>, <&clks 190>; 857 clocks = <&clks IMX6QDL_CLK_ENET>,
858 <&clks IMX6QDL_CLK_ENET>,
859 <&clks IMX6QDL_CLK_ENET_REF>;
841 clock-names = "ipg", "ahb", "ptp"; 860 clock-names = "ipg", "ahb", "ptp";
842 status = "disabled"; 861 status = "disabled";
843 }; 862 };
@@ -853,7 +872,9 @@
853 compatible = "fsl,imx6q-usdhc"; 872 compatible = "fsl,imx6q-usdhc";
854 reg = <0x02190000 0x4000>; 873 reg = <0x02190000 0x4000>;
855 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 874 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&clks 163>, <&clks 163>, <&clks 163>; 875 clocks = <&clks IMX6QDL_CLK_USDHC1>,
876 <&clks IMX6QDL_CLK_USDHC1>,
877 <&clks IMX6QDL_CLK_USDHC1>;
857 clock-names = "ipg", "ahb", "per"; 878 clock-names = "ipg", "ahb", "per";
858 bus-width = <4>; 879 bus-width = <4>;
859 status = "disabled"; 880 status = "disabled";
@@ -863,7 +884,9 @@
863 compatible = "fsl,imx6q-usdhc"; 884 compatible = "fsl,imx6q-usdhc";
864 reg = <0x02194000 0x4000>; 885 reg = <0x02194000 0x4000>;
865 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 886 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&clks 164>, <&clks 164>, <&clks 164>; 887 clocks = <&clks IMX6QDL_CLK_USDHC2>,
888 <&clks IMX6QDL_CLK_USDHC2>,
889 <&clks IMX6QDL_CLK_USDHC2>;
867 clock-names = "ipg", "ahb", "per"; 890 clock-names = "ipg", "ahb", "per";
868 bus-width = <4>; 891 bus-width = <4>;
869 status = "disabled"; 892 status = "disabled";
@@ -873,7 +896,9 @@
873 compatible = "fsl,imx6q-usdhc"; 896 compatible = "fsl,imx6q-usdhc";
874 reg = <0x02198000 0x4000>; 897 reg = <0x02198000 0x4000>;
875 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 898 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&clks 165>, <&clks 165>, <&clks 165>; 899 clocks = <&clks IMX6QDL_CLK_USDHC3>,
900 <&clks IMX6QDL_CLK_USDHC3>,
901 <&clks IMX6QDL_CLK_USDHC3>;
877 clock-names = "ipg", "ahb", "per"; 902 clock-names = "ipg", "ahb", "per";
878 bus-width = <4>; 903 bus-width = <4>;
879 status = "disabled"; 904 status = "disabled";
@@ -883,7 +908,9 @@
883 compatible = "fsl,imx6q-usdhc"; 908 compatible = "fsl,imx6q-usdhc";
884 reg = <0x0219c000 0x4000>; 909 reg = <0x0219c000 0x4000>;
885 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 910 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
886 clocks = <&clks 166>, <&clks 166>, <&clks 166>; 911 clocks = <&clks IMX6QDL_CLK_USDHC4>,
912 <&clks IMX6QDL_CLK_USDHC4>,
913 <&clks IMX6QDL_CLK_USDHC4>;
887 clock-names = "ipg", "ahb", "per"; 914 clock-names = "ipg", "ahb", "per";
888 bus-width = <4>; 915 bus-width = <4>;
889 status = "disabled"; 916 status = "disabled";
@@ -895,7 +922,7 @@
895 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
896 reg = <0x021a0000 0x4000>; 923 reg = <0x021a0000 0x4000>;
897 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 924 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks 125>; 925 clocks = <&clks IMX6QDL_CLK_I2C1>;
899 status = "disabled"; 926 status = "disabled";
900 }; 927 };
901 928
@@ -905,7 +932,7 @@
905 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
906 reg = <0x021a4000 0x4000>; 933 reg = <0x021a4000 0x4000>;
907 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 934 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks 126>; 935 clocks = <&clks IMX6QDL_CLK_I2C2>;
909 status = "disabled"; 936 status = "disabled";
910 }; 937 };
911 938
@@ -915,7 +942,7 @@
915 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
916 reg = <0x021a8000 0x4000>; 943 reg = <0x021a8000 0x4000>;
917 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 944 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks 127>; 945 clocks = <&clks IMX6QDL_CLK_I2C3>;
919 status = "disabled"; 946 status = "disabled";
920 }; 947 };
921 948
@@ -936,7 +963,7 @@
936 compatible = "fsl,imx6q-weim"; 963 compatible = "fsl,imx6q-weim";
937 reg = <0x021b8000 0x4000>; 964 reg = <0x021b8000 0x4000>;
938 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 965 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
939 clocks = <&clks 196>; 966 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
940 }; 967 };
941 968
942 ocotp: ocotp@021bc000 { 969 ocotp: ocotp@021bc000 {
@@ -996,7 +1023,8 @@
996 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1023 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
997 reg = <0x021e8000 0x4000>; 1024 reg = <0x021e8000 0x4000>;
998 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1025 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
999 clocks = <&clks 160>, <&clks 161>; 1026 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1027 <&clks IMX6QDL_CLK_UART_SERIAL>;
1000 clock-names = "ipg", "per"; 1028 clock-names = "ipg", "per";
1001 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1029 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1002 dma-names = "rx", "tx"; 1030 dma-names = "rx", "tx";
@@ -1007,7 +1035,8 @@
1007 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1035 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1008 reg = <0x021ec000 0x4000>; 1036 reg = <0x021ec000 0x4000>;
1009 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1037 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&clks 160>, <&clks 161>; 1038 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1039 <&clks IMX6QDL_CLK_UART_SERIAL>;
1011 clock-names = "ipg", "per"; 1040 clock-names = "ipg", "per";
1012 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1041 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1013 dma-names = "rx", "tx"; 1042 dma-names = "rx", "tx";
@@ -1018,7 +1047,8 @@
1018 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1047 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1019 reg = <0x021f0000 0x4000>; 1048 reg = <0x021f0000 0x4000>;
1020 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1049 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&clks 160>, <&clks 161>; 1050 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1051 <&clks IMX6QDL_CLK_UART_SERIAL>;
1022 clock-names = "ipg", "per"; 1052 clock-names = "ipg", "per";
1023 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1053 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1024 dma-names = "rx", "tx"; 1054 dma-names = "rx", "tx";
@@ -1029,7 +1059,8 @@
1029 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1059 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1030 reg = <0x021f4000 0x4000>; 1060 reg = <0x021f4000 0x4000>;
1031 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1061 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&clks 160>, <&clks 161>; 1062 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1063 <&clks IMX6QDL_CLK_UART_SERIAL>;
1033 clock-names = "ipg", "per"; 1064 clock-names = "ipg", "per";
1034 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1065 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1035 dma-names = "rx", "tx"; 1066 dma-names = "rx", "tx";
@@ -1044,10 +1075,20 @@
1044 reg = <0x02400000 0x400000>; 1075 reg = <0x02400000 0x400000>;
1045 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1076 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1046 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1077 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>; 1078 clocks = <&clks IMX6QDL_CLK_IPU1>,
1079 <&clks IMX6QDL_CLK_IPU1_DI0>,
1080 <&clks IMX6QDL_CLK_IPU1_DI1>;
1048 clock-names = "bus", "di0", "di1"; 1081 clock-names = "bus", "di0", "di1";
1049 resets = <&src 2>; 1082 resets = <&src 2>;
1050 1083
1084 ipu1_csi0: port@0 {
1085 reg = <0>;
1086 };
1087
1088 ipu1_csi1: port@1 {
1089 reg = <1>;
1090 };
1091
1051 ipu1_di0: port@2 { 1092 ipu1_di0: port@2 {
1052 #address-cells = <1>; 1093 #address-cells = <1>;
1053 #size-cells = <0>; 1094 #size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index a8d9a93fab85..3f9e041c0252 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -116,8 +116,9 @@
116}; 116};
117 117
118&fec { 118&fec {
119 pinctrl-names = "default"; 119 pinctrl-names = "default", "sleep";
120 pinctrl-0 = <&pinctrl_fec>; 120 pinctrl-0 = <&pinctrl_fec>;
121 pinctrl-1 = <&pinctrl_fec_sleep>;
121 phy-mode = "rmii"; 122 phy-mode = "rmii";
122 status = "okay"; 123 status = "okay";
123}; 124};
@@ -300,6 +301,19 @@
300 >; 301 >;
301 }; 302 };
302 303
304 pinctrl_fec_sleep: fecgrp-sleep {
305 fsl,pins = <
306 MX6SL_PAD_FEC_MDC__GPIO4_IO23 0x3080
307 MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x3080
308 MX6SL_PAD_FEC_RXD0__GPIO4_IO17 0x3080
309 MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x3080
310 MX6SL_PAD_FEC_TX_EN__GPIO4_IO22 0x3080
311 MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x3080
312 MX6SL_PAD_FEC_TXD1__GPIO4_IO16 0x3080
313 MX6SL_PAD_FEC_REF_CLK__GPIO4_IO26 0x3080
314 >;
315 };
316
303 pinctrl_i2c1: i2c1grp { 317 pinctrl_i2c1: i2c1grp {
304 fsl,pins = < 318 fsl,pins = <
305 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1 319 MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
@@ -475,7 +489,6 @@
475}; 489};
476 490
477&ssi2 { 491&ssi2 {
478 fsl,mode = "i2s-slave";
479 status = "okay"; 492 status = "okay";
480}; 493};
481 494
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 57d4abe03a94..c75800ca8b35 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -227,8 +227,7 @@
227 227
228 ssi1: ssi@02028000 { 228 ssi1: ssi@02028000 {
229 compatible = "fsl,imx6sl-ssi", 229 compatible = "fsl,imx6sl-ssi",
230 "fsl,imx51-ssi", 230 "fsl,imx51-ssi";
231 "fsl,imx21-ssi";
232 reg = <0x02028000 0x4000>; 231 reg = <0x02028000 0x4000>;
233 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 232 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
234 clocks = <&clks IMX6SL_CLK_SSI1>; 233 clocks = <&clks IMX6SL_CLK_SSI1>;
@@ -241,8 +240,7 @@
241 240
242 ssi2: ssi@0202c000 { 241 ssi2: ssi@0202c000 {
243 compatible = "fsl,imx6sl-ssi", 242 compatible = "fsl,imx6sl-ssi",
244 "fsl,imx51-ssi", 243 "fsl,imx51-ssi";
245 "fsl,imx21-ssi";
246 reg = <0x0202c000 0x4000>; 244 reg = <0x0202c000 0x4000>;
247 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 245 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
248 clocks = <&clks IMX6SL_CLK_SSI2>; 246 clocks = <&clks IMX6SL_CLK_SSI2>;
@@ -255,8 +253,7 @@
255 253
256 ssi3: ssi@02030000 { 254 ssi3: ssi@02030000 {
257 compatible = "fsl,imx6sl-ssi", 255 compatible = "fsl,imx6sl-ssi",
258 "fsl,imx51-ssi", 256 "fsl,imx51-ssi";
259 "fsl,imx21-ssi";
260 reg = <0x02030000 0x4000>; 257 reg = <0x02030000 0x4000>;
261 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 258 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&clks IMX6SL_CLK_SSI3>; 259 clocks = <&clks IMX6SL_CLK_SSI3>;
@@ -403,6 +400,7 @@
403 reg = <0x020b8000 0x4000>; 400 reg = <0x020b8000 0x4000>;
404 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 401 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&clks IMX6SL_CLK_DUMMY>; 402 clocks = <&clks IMX6SL_CLK_DUMMY>;
403 status = "disabled";
406 }; 404 };
407 405
408 wdog1: wdog@020bc000 { 406 wdog1: wdog@020bc000 {
@@ -607,7 +605,7 @@
607 }; 605 };
608 606
609 sdma: sdma@020ec000 { 607 sdma: sdma@020ec000 {
610 compatible = "fsl,imx6sl-sdma", "fsl,imx35-sdma"; 608 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma";
611 reg = <0x020ec000 0x4000>; 609 reg = <0x020ec000 0x4000>;
612 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 610 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
613 clocks = <&clks IMX6SL_CLK_SDMA>, 611 clocks = <&clks IMX6SL_CLK_SDMA>,
diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
new file mode 100644
index 000000000000..3e0b816dac08
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
@@ -0,0 +1,1544 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 */
9
10#ifndef __DTS_IMX6SX_PINFUNC_H
11#define __DTS_IMX6SX_PINFUNC_H
12
13/*
14 * The pin function ID is a tuple of
15 * <mux_reg conf_reg input_reg mux_mode input_val>
16 */
17#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
18#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
19#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
20#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
21#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
22#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
23#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
24#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
25#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
26#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
27#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
28#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
29#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
30#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
31#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
32#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
33#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
34#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
35#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
36#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
37#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
38#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
39#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
40#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
41#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
42#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
43#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
44#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
45#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
46#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
47#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
48#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
49#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
50#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
51#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
52#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
53#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
54#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
55#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
56#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
57#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
58#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
59#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
60#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
61#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
62#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
63#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
64#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
65#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
66#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
67#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
68#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
69#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
70#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
71#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
72#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
73#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
74#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
75#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
76#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
77#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
78#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
79#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
80#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
81#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1
82#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
83#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
84#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
85#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
86#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
87#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
88#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
89#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
90#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
91#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
92#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
93#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
94#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
95#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
96#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
97#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
98#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
99#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1
100#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
101#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
102#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
103#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
104#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
105#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
106#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
107#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
108#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
109#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
110#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
111#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
112#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
113#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
114#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
115#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
116#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
117#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
118#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
119#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
120#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
121#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
122#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
123#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
124#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
125#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
126#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
127#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
128#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
129#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
130#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
131#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
132#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
133#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
134#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
135#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
136#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
137#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
138#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
139#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
140#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
141#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
142#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
143#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
144#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
145#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
146#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
147#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
148#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
149#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
150#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
151#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
152#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
153#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
154#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
155#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
156#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
157#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
158#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
159#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
160#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
161#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
162#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
163#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
164#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
165#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
166#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
167#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
168#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
169#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
170#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
171#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
172#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
173#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
174#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
175#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
176#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
177#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
178#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
179#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
180#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
181#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
182#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
183#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
184#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
185#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
186#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
187#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
188#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
189#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
190#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
191#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
192#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
193#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
194#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
195#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
196#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
197#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
198#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
199#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
200#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
201#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
202#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
203#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
204#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
205#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
206#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
207#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
208#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
209#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
210#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
211#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
212#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
213#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
214#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
215#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
216#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1
217#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
218#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
219#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
220#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
221#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
222#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
223#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
224#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
225#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
226#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
227#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
228#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
229#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
230#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
231#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
232#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
233#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
234#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
235#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
236#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
237#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
238#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
239#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
240#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
241#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
242#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
243#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
244#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
245#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
246#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
247#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
248#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
249#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
250#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
251#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
252#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
253#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
254#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
255#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
256#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
257#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3
258#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
259#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
260#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
261#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
262#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
263#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
264#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
265#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
266#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
267#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
268#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
269#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
270#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
271#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
272#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
273#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
274#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
275#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
276#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
277#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
278#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
279#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
280#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
281#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
282#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
283#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
284#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
285#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
286#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
287#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
288#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
289#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
290#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
291#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
292#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
293#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
294#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
295#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
296#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
297#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
298#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
299#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
300#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
301#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
302#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
303#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
304#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
305#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
306#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
307#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
308#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
309#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
310#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
311#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
312#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
313#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
314#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
315#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
316#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
317#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
318#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
319#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
320#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
321#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
322#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
323#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
324#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
325#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
326#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
327#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
328#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
329#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
330#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
331#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
332#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
333#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
334#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
335#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
336#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
337#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
338#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
339#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
340#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
341#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
342#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
343#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
344#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
345#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
346#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
347#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
348#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
349#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
350#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
351#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
352#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
353#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
354#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
355#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
356#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
357#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
358#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
359#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
360#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
361#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
362#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
363#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
364#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
365#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
366#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
367#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
368#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
369#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
370#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
371#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
372#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
373#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
374#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
375#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
376#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
377#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
378#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
379#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
380#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
381#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
382#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
383#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
384#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
385#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
386#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
387#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
388#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
389#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
390#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
391#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
392#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
393#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
394#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
395#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
396#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
397#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
398#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
399#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
400#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
401#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
402#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
403#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
404#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
405#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
406#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
407#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3
408#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
409#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
410#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
411#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
412#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
413#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
414#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
415#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
416#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
417#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
418#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
419#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
420#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
421#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
422#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
423#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
424#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
425#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
426#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3
427#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
428#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
429#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
430#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
431#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
432#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
433#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
434#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
435#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
436#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
437#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
438#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
439#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
440#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
441#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
442#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
443#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
444#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
445#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
446#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
447#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
448#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
449#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
450#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
451#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
452#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
453#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
454#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
455#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
456#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
457#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
458#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
459#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
460#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
461#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
462#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
463#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
464#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
465#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
466#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
467#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
468#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
469#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
470#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
471#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
472#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
473#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
474#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
475#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
476#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
477#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
478#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
479#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
480#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
481#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
482#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
483#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
484#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
485#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
486#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
487#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
488#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
489#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
490#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
491#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
492#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
493#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
494#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
495#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
496#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
497#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
498#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
499#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
500#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
501#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
502#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
503#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
504#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
505#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
506#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
507#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
508#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
509#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
510#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
511#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
512#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
513#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
514#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
515#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
516#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
517#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
518#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
519#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
520#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
521#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
522#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
523#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
524#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
525#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
526#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
527#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
528#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
529#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
530#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
531#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
532#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
533#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
534#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
535#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
536#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
537#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
538#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
539#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
540#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
541#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
542#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
543#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
544#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
545#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
546#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
547#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
548#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
549#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
550#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
551#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
552#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
553#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
554#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
555#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
556#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
557#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
558#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
559#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
560#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
561#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
562#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
563#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
564#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
565#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
566#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
567#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
568#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
569#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
570#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
571#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
572#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
573#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
574#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
575#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
576#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
577#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
578#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
579#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
580#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
581#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
582#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
583#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
584#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
585#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
586#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
587#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
588#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
589#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
590#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
591#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
592#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
593#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
594#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
595#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
596#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
597#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
598#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
599#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
600#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
601#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
602#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
603#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
604#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
605#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
606#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
607#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
608#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
609#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
610#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
611#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
612#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
613#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
614#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
615#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
616#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
617#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
618#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
619#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
620#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
621#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
622#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
623#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
624#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
625#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
626#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
627#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
628#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
629#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
630#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
631#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
632#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
633#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
634#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
635#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
636#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
637#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
638#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
639#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
640#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
641#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
642#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
643#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
644#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
645#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
646#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
647#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
648#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
649#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
650#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
651#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
652#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
653#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
654#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
655#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
656#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
657#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
658#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
659#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
660#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
661#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
662#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
663#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
664#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
665#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
666#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
667#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
668#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
669#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
670#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
671#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
672#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
673#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
674#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
675#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
676#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
677#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
678#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
679#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
680#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
681#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
682#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
683#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
684#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
685#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
686#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
687#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
688#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
689#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
690#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
691#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
692#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
693#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
694#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
695#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
696#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
697#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
698#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
699#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
700#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
701#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
702#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
703#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
704#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
705#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
706#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
707#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
708#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
709#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
710#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
711#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
712#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
713#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
714#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
715#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
716#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
717#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
718#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
719#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
720#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
721#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
722#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
723#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
724#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
725#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
726#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
727#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
728#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
729#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
730#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
731#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
732#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
733#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
734#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
735#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
736#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
737#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
738#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
739#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
740#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
741#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
742#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
743#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
744#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
745#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
746#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
747#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
748#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
749#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
750#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
751#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
752#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
753#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
754#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
755#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
756#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
757#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
758#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
759#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
760#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
761#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
762#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
763#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
764#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
765#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
766#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
767#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
768#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
769#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
770#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
771#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
772#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
773#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
774#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
775#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
776#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
777#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
778#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
779#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
780#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
781#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
782#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
783#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
784#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
785#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
786#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
787#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
788#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
789#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
790#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
791#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
792#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
793#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
794#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
795#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
796#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
797#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
798#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
799#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
800#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
801#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
802#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
803#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
804#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
805#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
806#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
807#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
808#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
809#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
810#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
811#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
812#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
813#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
814#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
815#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
816#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
817#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
818#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1
819#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
820#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
821#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
822#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
823#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
824#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
825#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
826#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
827#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
828#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
829#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
830#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
831#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
832#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
833#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
834#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
835#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
836#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
837#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
838#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
839#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
840#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
841#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
842#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
843#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
844#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
845#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
846#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
847#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
848#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
849#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
850#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
851#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
852#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
853#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
854#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
855#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
856#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
857#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
858#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
859#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
860#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
861#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
862#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
863#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
864#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
865#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
866#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
867#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
868#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
869#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
870#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
871#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
872#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
873#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
874#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
875#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
876#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
877#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
878#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
879#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
880#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
881#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
882#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
883#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
884#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
885#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
886#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
887#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
888#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
889#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
890#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
891#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
892#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
893#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
894#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
895#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
896#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
897#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
898#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
899#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
900#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
901#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
902#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
903#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
904#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
905#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
906#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
907#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
908#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
909#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
910#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
911#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
912#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
913#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
914#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
915#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
916#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
917#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
918#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
919#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
920#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
921#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
922#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
923#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
924#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
925#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
926#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
927#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
928#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
929#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
930#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
931#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
932#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
933#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
934#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
935#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
936#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
937#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
938#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
939#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
940#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
941#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
942#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
943#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
944#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
945#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
946#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
947#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
948#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
949#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
950#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
951#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
952#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
953#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
954#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
955#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
956#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
957#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
958#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
959#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
960#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
961#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
962#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
963#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
964#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
965#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
966#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
967#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
968#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
969#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
970#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
971#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
972#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
973#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
974#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
975#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
976#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
977#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
978#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
979#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
980#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
981#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
982#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
983#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
984#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
985#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
986#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
987#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
988#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
989#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
990#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
991#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
992#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
993#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
994#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
995#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
996#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
997#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
998#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
999#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
1000#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
1001#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
1002#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
1003#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
1004#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
1005#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
1006#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
1007#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
1008#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
1009#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
1010#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
1011#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
1012#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
1013#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
1014#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
1015#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
1016#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
1017#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
1018#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
1019#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
1020#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
1021#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
1022#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
1023#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
1024#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
1025#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
1026#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
1027#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
1028#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
1029#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
1030#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
1031#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
1032#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
1033#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
1034#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
1035#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
1036#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
1037#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
1038#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
1039#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
1040#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
1041#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
1042#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
1043#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
1044#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
1045#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
1046#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
1047#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
1048#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
1049#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
1050#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
1051#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
1052#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
1053#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
1054#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
1055#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
1056#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
1057#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
1058#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
1059#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
1060#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
1061#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
1062#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
1063#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
1064#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
1065#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
1066#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
1067#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
1068#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
1069#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
1070#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
1071#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
1072#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
1073#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
1074#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
1075#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
1076#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
1077#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
1078#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
1079#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
1080#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
1081#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
1082#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
1083#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
1084#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
1085#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
1086#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
1087#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
1088#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
1089#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
1090#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
1091#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
1092#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
1093#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
1094#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
1095#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
1096#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
1097#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
1098#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
1099#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
1100#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
1101#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
1102#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
1103#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
1104#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
1105#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
1106#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
1107#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
1108#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
1109#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
1110#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
1111#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
1112#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
1113#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
1114#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
1115#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
1116#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
1117#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
1118#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
1119#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
1120#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
1121#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
1122#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
1123#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
1124#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
1125#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
1126#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
1127#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
1128#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
1129#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
1130#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
1131#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
1132#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
1133#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
1134#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
1135#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
1136#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
1137#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
1138#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
1139#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
1140#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
1141#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
1142#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
1143#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
1144#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
1145#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
1146#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
1147#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
1148#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
1149#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
1150#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
1151#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
1152#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
1153#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
1154#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
1155#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
1156#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
1157#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
1158#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
1159#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
1160#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
1161#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
1162#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
1163#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
1164#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
1165#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
1166#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
1167#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
1168#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
1169#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
1170#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
1171#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
1172#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
1173#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
1174#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
1175#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
1176#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
1177#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
1178#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
1179#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
1180#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
1181#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
1182#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
1183#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
1184#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
1185#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
1186#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
1187#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
1188#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
1189#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
1190#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
1191#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
1192#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
1193#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
1194#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
1195#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
1196#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
1197#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
1198#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
1199#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
1200#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
1201#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
1202#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
1203#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
1204#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
1205#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
1206#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
1207#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
1208#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
1209#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
1210#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
1211#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
1212#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
1213#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
1214#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
1215#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
1216#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
1217#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
1218#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
1219#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
1220#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
1221#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
1222#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
1223#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
1224#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
1225#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
1226#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
1227#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
1228#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
1229#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
1230#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
1231#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
1232#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
1233#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
1234#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
1235#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
1236#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
1237#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
1238#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
1239#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2
1240#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
1241#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
1242#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
1243#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
1244#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
1245#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
1246#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
1247#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
1248#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
1249#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
1250#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
1251#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
1252#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
1253#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
1254#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
1255#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
1256#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
1257#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
1258#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
1259#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
1260#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
1261#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
1262#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
1263#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
1264#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
1265#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
1266#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
1267#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
1268#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
1269#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
1270#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
1271#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
1272#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
1273#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
1274#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
1275#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
1276#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
1277#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
1278#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
1279#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
1280#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
1281#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
1282#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
1283#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
1284#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
1285#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
1286#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
1287#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
1288#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
1289#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
1290#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
1291#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
1292#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
1293#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
1294#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
1295#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
1296#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
1297#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
1298#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
1299#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
1300#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
1301#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
1302#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
1303#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
1304#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
1305#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
1306#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
1307#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
1308#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
1309#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
1310#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
1311#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
1312#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
1313#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
1314#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
1315#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
1316#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
1317#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
1318#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0
1319#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
1320#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
1321#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
1322#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
1323#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
1324#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
1325#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
1326#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
1327#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
1328#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
1329#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
1330#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
1331#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
1332#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
1333#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
1334#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
1335#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
1336#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
1337#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
1338#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
1339#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
1340#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
1341#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
1342#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
1343#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
1344#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
1345#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
1346#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
1347#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
1348#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
1349#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
1350#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
1351#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
1352#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
1353#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
1354#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
1355#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
1356#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
1357#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
1358#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
1359#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
1360#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
1361#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
1362#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
1363#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
1364#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
1365#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
1366#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
1367#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
1368#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
1369#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
1370#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
1371#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
1372#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
1373#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
1374#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
1375#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
1376#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
1377#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
1378#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
1379#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
1380#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
1381#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
1382#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
1383#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
1384#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
1385#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
1386#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
1387#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
1388#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
1389#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
1390#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
1391#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
1392#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
1393#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
1394#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
1395#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
1396#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
1397#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
1398#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
1399#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
1400#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
1401#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
1402#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
1403#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
1404#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
1405#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
1406#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
1407#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
1408#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
1409#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
1410#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
1411#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
1412#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3
1413#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
1414#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
1415#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
1416#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
1417#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
1418#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
1419#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
1420#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
1421#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
1422#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
1423#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
1424#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
1425#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
1426#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
1427#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
1428#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
1429#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
1430#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
1431#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
1432#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
1433#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
1434#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
1435#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
1436#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
1437#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
1438#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
1439#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
1440#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
1441#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
1442#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
1443#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
1444#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
1445#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
1446#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
1447#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
1448#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
1449#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
1450#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
1451#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
1452#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
1453#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
1454#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
1455#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
1456#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
1457#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
1458#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
1459#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
1460#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
1461#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
1462#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
1463#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
1464#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
1465#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
1466#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
1467#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
1468#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
1469#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
1470#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
1471#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
1472#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
1473#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
1474#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
1475#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
1476#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
1477#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
1478#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
1479#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
1480#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
1481#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
1482#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
1483#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
1484#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
1485#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
1486#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
1487#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
1488#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
1489#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
1490#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
1491#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
1492#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
1493#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
1494#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
1495#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
1496#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
1497#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
1498#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
1499#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
1500#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
1501#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
1502#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
1503#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
1504#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
1505#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
1506#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
1507#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
1508#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
1509#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
1510#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
1511#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
1512#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
1513#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1
1514#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
1515#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
1516#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
1517#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
1518#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
1519#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
1520#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
1521#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
1522#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
1523#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
1524#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
1525#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
1526#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
1527#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
1528#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
1529#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
1530#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
1531#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
1532#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
1533#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
1534#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
1535#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
1536#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
1537#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
1538#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
1539#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
1540#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
1541#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
1542#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
1543
1544#endif /* __DTS_IMX6SX_PINFUNC_H */
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
new file mode 100644
index 000000000000..a3980d970590
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -0,0 +1,479 @@
1/*
2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/dts-v1/;
10
11#include <dt-bindings/gpio/gpio.h>
12#include <dt-bindings/input/input.h>
13#include "imx6sx.dtsi"
14
15/ {
16 model = "Freescale i.MX6 SoloX SDB Board";
17 compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory {
24 reg = <0x80000000 0x40000000>;
25 };
26
27 gpio-keys {
28 compatible = "gpio-keys";
29 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_gpio_keys>;
31
32 volume-up {
33 label = "Volume Up";
34 gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
35 linux,code = <KEY_VOLUMEUP>;
36 };
37
38 volume-down {
39 label = "Volume Down";
40 gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
41 linux,code = <KEY_VOLUMEDOWN>;
42 };
43 };
44
45 regulators {
46 compatible = "simple-bus";
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 vcc_sd3: regulator@0 {
51 compatible = "regulator-fixed";
52 reg = <0>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_vcc_sd3>;
55 regulator-name = "VCC_SD3";
56 regulator-min-microvolt = <3000000>;
57 regulator-max-microvolt = <3000000>;
58 gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
59 enable-active-high;
60 };
61
62 reg_usb_otg1_vbus: regulator@1 {
63 compatible = "regulator-fixed";
64 reg = <1>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_usb_otg1>;
67 regulator-name = "usb_otg1_vbus";
68 regulator-min-microvolt = <5000000>;
69 regulator-max-microvolt = <5000000>;
70 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
71 enable-active-high;
72 };
73
74 reg_usb_otg2_vbus: regulator@2 {
75 compatible = "regulator-fixed";
76 reg = <2>;
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_usb_otg2>;
79 regulator-name = "usb_otg2_vbus";
80 regulator-min-microvolt = <5000000>;
81 regulator-max-microvolt = <5000000>;
82 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
83 enable-active-high;
84 };
85
86 reg_psu_5v: regulator@3 {
87 compatible = "regulator-fixed";
88 reg = <3>;
89 regulator-name = "PSU-5V0";
90 regulator-min-microvolt = <5000000>;
91 regulator-max-microvolt = <5000000>;
92 };
93 };
94
95 sound {
96 compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
97 model = "wm8962-audio";
98 ssi-controller = <&ssi2>;
99 audio-codec = <&codec>;
100 audio-routing =
101 "Headphone Jack", "HPOUTL",
102 "Headphone Jack", "HPOUTR",
103 "Ext Spk", "SPKOUTL",
104 "Ext Spk", "SPKOUTR",
105 "AMIC", "MICBIAS",
106 "IN3R", "AMIC";
107 mux-int-port = <2>;
108 mux-ext-port = <6>;
109 };
110};
111
112&audmux {
113 pinctrl-names = "default";
114 pinctrl-0 = <&pinctrl_audmux>;
115 status = "okay";
116};
117
118&fec1 {
119 pinctrl-names = "default";
120 pinctrl-0 = <&pinctrl_enet1>;
121 phy-mode = "rgmii";
122 status = "okay";
123};
124
125&i2c1 {
126 clock-frequency = <100000>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay";
130
131 pmic: pfuze100@08 {
132 compatible = "fsl,pfuze100";
133 reg = <0x08>;
134
135 regulators {
136 sw1a_reg: sw1ab {
137 regulator-min-microvolt = <300000>;
138 regulator-max-microvolt = <1875000>;
139 regulator-boot-on;
140 regulator-always-on;
141 regulator-ramp-delay = <6250>;
142 };
143
144 sw1c_reg: sw1c {
145 regulator-min-microvolt = <300000>;
146 regulator-max-microvolt = <1875000>;
147 regulator-boot-on;
148 regulator-always-on;
149 regulator-ramp-delay = <6250>;
150 };
151
152 sw2_reg: sw2 {
153 regulator-min-microvolt = <800000>;
154 regulator-max-microvolt = <3300000>;
155 regulator-boot-on;
156 regulator-always-on;
157 };
158
159 sw3a_reg: sw3a {
160 regulator-min-microvolt = <400000>;
161 regulator-max-microvolt = <1975000>;
162 regulator-boot-on;
163 regulator-always-on;
164 };
165
166 sw3b_reg: sw3b {
167 regulator-min-microvolt = <400000>;
168 regulator-max-microvolt = <1975000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 sw4_reg: sw4 {
174 regulator-min-microvolt = <800000>;
175 regulator-max-microvolt = <3300000>;
176 };
177
178 swbst_reg: swbst {
179 regulator-min-microvolt = <5000000>;
180 regulator-max-microvolt = <5150000>;
181 };
182
183 snvs_reg: vsnvs {
184 regulator-min-microvolt = <1000000>;
185 regulator-max-microvolt = <3000000>;
186 regulator-boot-on;
187 regulator-always-on;
188 };
189
190 vref_reg: vrefddr {
191 regulator-boot-on;
192 regulator-always-on;
193 };
194
195 vgen1_reg: vgen1 {
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <1550000>;
198 regulator-always-on;
199 };
200
201 vgen2_reg: vgen2 {
202 regulator-min-microvolt = <800000>;
203 regulator-max-microvolt = <1550000>;
204 };
205
206 vgen3_reg: vgen3 {
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3300000>;
209 regulator-always-on;
210 };
211
212 vgen4_reg: vgen4 {
213 regulator-min-microvolt = <1800000>;
214 regulator-max-microvolt = <3300000>;
215 regulator-always-on;
216 };
217
218 vgen5_reg: vgen5 {
219 regulator-min-microvolt = <1800000>;
220 regulator-max-microvolt = <3300000>;
221 regulator-always-on;
222 };
223
224 vgen6_reg: vgen6 {
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
227 regulator-always-on;
228 };
229 };
230 };
231};
232
233&i2c4 {
234 clock-frequency = <100000>;
235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_i2c4>;
237 status = "okay";
238
239 codec: wm8962@1a {
240 compatible = "wlf,wm8962";
241 reg = <0x1a>;
242 clocks = <&clks IMX6SX_CLK_AUDIO>;
243 DCVDD-supply = <&vgen4_reg>;
244 DBVDD-supply = <&vgen4_reg>;
245 AVDD-supply = <&vgen4_reg>;
246 CPVDD-supply = <&vgen4_reg>;
247 MICVDD-supply = <&vgen3_reg>;
248 PLLVDD-supply = <&vgen4_reg>;
249 SPKVDD1-supply = <&reg_psu_5v>;
250 SPKVDD2-supply = <&reg_psu_5v>;
251 };
252};
253
254&ssi2 {
255 status = "okay";
256};
257
258&uart1 {
259 pinctrl-names = "default";
260 pinctrl-0 = <&pinctrl_uart1>;
261 status = "okay";
262};
263
264&uart5 { /* for bluetooth */
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_uart5>;
267 fsl,uart-has-rtscts;
268 status = "okay";
269};
270
271&usbotg1 {
272 vbus-supply = <&reg_usb_otg1_vbus>;
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_usb_otg1_id>;
275 status = "okay";
276};
277
278&usbotg2 {
279 vbus-supply = <&reg_usb_otg2_vbus>;
280 dr_mode = "host";
281 status = "okay";
282};
283
284&usdhc2 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&pinctrl_usdhc2>;
287 non-removable;
288 no-1-8-v;
289 keep-power-in-suspend;
290 enable-sdio-wakeup;
291 status = "okay";
292};
293
294&usdhc3 {
295 pinctrl-names = "default", "state_100mhz", "state_200mhz";
296 pinctrl-0 = <&pinctrl_usdhc3>;
297 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
298 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
299 bus-width = <8>;
300 cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
301 wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
302 keep-power-in-suspend;
303 enable-sdio-wakeup;
304 vmmc-supply = <&vcc_sd3>;
305 status = "okay";
306};
307
308&usdhc4 {
309 pinctrl-names = "default";
310 pinctrl-0 = <&pinctrl_usdhc4>;
311 cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
312 wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
313 status = "okay";
314};
315
316&iomuxc {
317 imx6x-sdb {
318 pinctrl_audmux: audmuxgrp {
319 fsl,pins = <
320 MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
321 MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
322 MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
323 MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
324 MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
325 >;
326 };
327
328 pinctrl_enet1: enet1grp {
329 fsl,pins = <
330 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
331 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
332 MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
333 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
334 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
335 MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
336 MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
337 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
338 MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
339 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
340 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
341 MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
342 MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
343 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
344 >;
345 };
346
347 pinctrl_gpio_keys: gpio_keysgrp {
348 fsl,pins = <
349 MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
350 MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
351 >;
352 };
353
354 pinctrl_i2c1: i2c1grp {
355 fsl,pins = <
356 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
357 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
358 >;
359 };
360
361 pinctrl_i2c4: i2c4grp {
362 fsl,pins = <
363 MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
364 MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
365 >;
366 };
367
368 pinctrl_vcc_sd3: vccsd3grp {
369 fsl,pins = <
370 MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
371 >;
372 };
373
374 pinctrl_uart1: uart1grp {
375 fsl,pins = <
376 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
377 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
378 >;
379 };
380
381 pinctrl_uart5: uart5grp {
382 fsl,pins = <
383 MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
384 MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
385 MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
386 MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
387 >;
388 };
389
390 pinctrl_usb_otg1: usbotg1grp {
391 fsl,pins = <
392 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
393 >;
394 };
395
396 pinctrl_usb_otg1_id: usbotg1idgrp {
397 fsl,pins = <
398 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
399 >;
400 };
401
402 pinctrl_usb_otg2: usbot2ggrp {
403 fsl,pins = <
404 MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
405 >;
406 };
407
408 pinctrl_usdhc2: usdhc2grp {
409 fsl,pins = <
410 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
411 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
412 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
413 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
414 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
415 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
416 >;
417 };
418
419 pinctrl_usdhc3: usdhc3grp {
420 fsl,pins = <
421 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
422 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
423 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
424 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
425 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
426 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
427 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
428 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
429 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
430 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
431 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
432 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
433 >;
434 };
435
436 pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
437 fsl,pins = <
438 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
439 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
440 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
441 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
442 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
443 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
444 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
445 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
446 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
447 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
448 >;
449 };
450
451 pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
452 fsl,pins = <
453 MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
454 MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
455 MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
456 MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
457 MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
458 MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
459 MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
460 MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
461 MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
462 MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
463 >;
464 };
465
466 pinctrl_usdhc4: usdhc4grp {
467 fsl,pins = <
468 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
469 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
470 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
471 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
472 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
473 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
474 MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
475 MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
476 >;
477 };
478 };
479};
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
new file mode 100644
index 000000000000..f4b9da65bc0f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -0,0 +1,1208 @@
1/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <dt-bindings/clock/imx6sx-clock.h>
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include "imx6sx-pinfunc.h"
13#include "skeleton.dtsi"
14
15/ {
16 aliases {
17 can0 = &flexcan1;
18 can1 = &flexcan2;
19 ethernet0 = &fec1;
20 ethernet1 = &fec2;
21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
25 gpio4 = &gpio5;
26 gpio5 = &gpio6;
27 gpio6 = &gpio7;
28 i2c0 = &i2c1;
29 i2c1 = &i2c2;
30 i2c2 = &i2c3;
31 i2c3 = &i2c4;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 mmc3 = &usdhc4;
36 serial0 = &uart1;
37 serial1 = &uart2;
38 serial2 = &uart3;
39 serial3 = &uart4;
40 serial4 = &uart5;
41 serial5 = &uart6;
42 spi0 = &ecspi1;
43 spi1 = &ecspi2;
44 spi2 = &ecspi3;
45 spi3 = &ecspi4;
46 spi4 = &ecspi5;
47 usbphy0 = &usbphy1;
48 usbphy1 = &usbphy2;
49 };
50
51 cpus {
52 #address-cells = <1>;
53 #size-cells = <0>;
54
55 cpu0: cpu@0 {
56 compatible = "arm,cortex-a9";
57 device_type = "cpu";
58 reg = <0>;
59 next-level-cache = <&L2>;
60 operating-points = <
61 /* kHz uV */
62 996000 1250000
63 792000 1175000
64 396000 1075000
65 >;
66 fsl,soc-operating-points = <
67 /* ARM kHz SOC uV */
68 996000 1175000
69 792000 1175000
70 396000 1175000
71 >;
72 clock-latency = <61036>; /* two CLK32 periods */
73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
78 clock-names = "arm", "pll2_pfd2_396m", "step",
79 "pll1_sw", "pll1_sys";
80 arm-supply = <&reg_arm>;
81 soc-supply = <&reg_soc>;
82 };
83 };
84
85 intc: interrupt-controller@00a01000 {
86 compatible = "arm,cortex-a9-gic";
87 #interrupt-cells = <3>;
88 interrupt-controller;
89 reg = <0x00a01000 0x1000>,
90 <0x00a00100 0x100>;
91 };
92
93 clocks {
94 #address-cells = <1>;
95 #size-cells = <0>;
96
97 ckil: clock@0 {
98 compatible = "fixed-clock";
99 reg = <0>;
100 #clock-cells = <0>;
101 clock-frequency = <32768>;
102 clock-output-names = "ckil";
103 };
104
105 osc: clock@1 {
106 compatible = "fixed-clock";
107 reg = <1>;
108 #clock-cells = <0>;
109 clock-frequency = <24000000>;
110 clock-output-names = "osc";
111 };
112
113 ipp_di0: clock@2 {
114 compatible = "fixed-clock";
115 reg = <2>;
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 clock-output-names = "ipp_di0";
119 };
120
121 ipp_di1: clock@3 {
122 compatible = "fixed-clock";
123 reg = <3>;
124 #clock-cells = <0>;
125 clock-frequency = <0>;
126 clock-output-names = "ipp_di1";
127 };
128 };
129
130 soc {
131 #address-cells = <1>;
132 #size-cells = <1>;
133 compatible = "simple-bus";
134 interrupt-parent = <&intc>;
135 ranges;
136
137 pmu {
138 compatible = "arm,cortex-a9-pmu";
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
140 };
141
142 ocram: sram@00900000 {
143 compatible = "mmio-sram";
144 reg = <0x00900000 0x20000>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
146 };
147
148 L2: l2-cache@00a02000 {
149 compatible = "arm,pl310-cache";
150 reg = <0x00a02000 0x1000>;
151 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
152 cache-unified;
153 cache-level = <2>;
154 arm,tag-latency = <4 2 3>;
155 arm,data-latency = <4 2 3>;
156 };
157
158 dma_apbh: dma-apbh@01804000 {
159 compatible = "fsl,imx6sx-dma-apbh", "fsl,imx28-dma-apbh";
160 reg = <0x01804000 0x2000>;
161 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
163 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
165 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
166 #dma-cells = <1>;
167 dma-channels = <4>;
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
169 };
170
171 gpmi: gpmi-nand@01806000{
172 compatible = "fsl,imx6sx-gpmi-nand";
173 #address-cells = <1>;
174 #size-cells = <1>;
175 reg = <0x01806000 0x2000>, <0x01808000 0x4000>;
176 reg-names = "gpmi-nand", "bch";
177 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-names = "bch";
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
182 <&clks IMX6SX_CLK_GPMI_BCH_APB>,
183 <&clks IMX6SX_CLK_PER1_BCH>;
184 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
185 "gpmi_bch_apb", "per1_bch";
186 dmas = <&dma_apbh 0>;
187 dma-names = "rx-tx";
188 status = "disabled";
189 };
190
191 aips1: aips-bus@02000000 {
192 compatible = "fsl,aips-bus", "simple-bus";
193 #address-cells = <1>;
194 #size-cells = <1>;
195 reg = <0x02000000 0x100000>;
196 ranges;
197
198 spba-bus@02000000 {
199 compatible = "fsl,spba-bus", "simple-bus";
200 #address-cells = <1>;
201 #size-cells = <1>;
202 reg = <0x02000000 0x40000>;
203 ranges;
204
205 spdif: spdif@02004000 {
206 compatible = "fsl,imx6sx-spdif", "fsl,imx35-spdif";
207 reg = <0x02004000 0x4000>;
208 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
209 dmas = <&sdma 14 18 0>,
210 <&sdma 15 18 0>;
211 dma-names = "rx", "tx";
212 clocks = <&clks IMX6SX_CLK_SPDIF>,
213 <&clks IMX6SX_CLK_OSC>,
214 <&clks IMX6SX_CLK_SPDIF>,
215 <&clks 0>, <&clks 0>, <&clks 0>,
216 <&clks IMX6SX_CLK_IPG>,
217 <&clks 0>, <&clks 0>,
218 <&clks IMX6SX_CLK_SPBA>;
219 clock-names = "core", "rxtx0",
220 "rxtx1", "rxtx2",
221 "rxtx3", "rxtx4",
222 "rxtx5", "rxtx6",
223 "rxtx7", "dma";
224 status = "disabled";
225 };
226
227 ecspi1: ecspi@02008000 {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
231 reg = <0x02008000 0x4000>;
232 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&clks IMX6SX_CLK_ECSPI1>,
234 <&clks IMX6SX_CLK_ECSPI1>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238
239 ecspi2: ecspi@0200c000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
243 reg = <0x0200c000 0x4000>;
244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&clks IMX6SX_CLK_ECSPI2>,
246 <&clks IMX6SX_CLK_ECSPI2>;
247 clock-names = "ipg", "per";
248 status = "disabled";
249 };
250
251 ecspi3: ecspi@02010000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
255 reg = <0x02010000 0x4000>;
256 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&clks IMX6SX_CLK_ECSPI3>,
258 <&clks IMX6SX_CLK_ECSPI3>;
259 clock-names = "ipg", "per";
260 status = "disabled";
261 };
262
263 ecspi4: ecspi@02014000 {
264 #address-cells = <1>;
265 #size-cells = <0>;
266 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
267 reg = <0x02014000 0x4000>;
268 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&clks IMX6SX_CLK_ECSPI4>,
270 <&clks IMX6SX_CLK_ECSPI4>;
271 clock-names = "ipg", "per";
272 status = "disabled";
273 };
274
275 uart1: serial@02020000 {
276 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
277 reg = <0x02020000 0x4000>;
278 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&clks IMX6SX_CLK_UART_IPG>,
280 <&clks IMX6SX_CLK_UART_SERIAL>;
281 clock-names = "ipg", "per";
282 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
283 dma-names = "rx", "tx";
284 status = "disabled";
285 };
286
287 esai: esai@02024000 {
288 reg = <0x02024000 0x4000>;
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&clks IMX6SX_CLK_ESAI_IPG>,
291 <&clks IMX6SX_CLK_ESAI_MEM>,
292 <&clks IMX6SX_CLK_ESAI_EXTAL>,
293 <&clks IMX6SX_CLK_ESAI_IPG>,
294 <&clks IMX6SX_CLK_SPBA>;
295 clock-names = "core", "mem", "extal",
296 "fsys", "dma";
297 status = "disabled";
298 };
299
300 ssi1: ssi@02028000 {
301 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
302 reg = <0x02028000 0x4000>;
303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&clks IMX6SX_CLK_SSI1_IPG>,
305 <&clks IMX6SX_CLK_SSI1>;
306 clock-names = "ipg", "baud";
307 dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
308 dma-names = "rx", "tx";
309 fsl,fifo-depth = <15>;
310 status = "disabled";
311 };
312
313 ssi2: ssi@0202c000 {
314 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
315 reg = <0x0202c000 0x4000>;
316 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&clks IMX6SX_CLK_SSI2_IPG>,
318 <&clks IMX6SX_CLK_SSI2>;
319 clock-names = "ipg", "baud";
320 dmas = <&sdma 41 1 0>, <&sdma 42 1 0>;
321 dma-names = "rx", "tx";
322 fsl,fifo-depth = <15>;
323 status = "disabled";
324 };
325
326 ssi3: ssi@02030000 {
327 compatible = "fsl,imx6sx-ssi", "fsl,imx51-ssi";
328 reg = <0x02030000 0x4000>;
329 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&clks IMX6SX_CLK_SSI3_IPG>,
331 <&clks IMX6SX_CLK_SSI3>;
332 clock-names = "ipg", "baud";
333 dmas = <&sdma 45 1 0>, <&sdma 46 1 0>;
334 dma-names = "rx", "tx";
335 fsl,fifo-depth = <15>;
336 status = "disabled";
337 };
338
339 asrc: asrc@02034000 {
340 reg = <0x02034000 0x4000>;
341 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&clks IMX6SX_CLK_ASRC_MEM>,
343 <&clks IMX6SX_CLK_ASRC_IPG>,
344 <&clks IMX6SX_CLK_SPDIF>,
345 <&clks IMX6SX_CLK_SPBA>;
346 clock-names = "mem", "ipg", "asrck", "dma";
347 dmas = <&sdma 17 20 1>, <&sdma 18 20 1>,
348 <&sdma 19 20 1>, <&sdma 20 20 1>,
349 <&sdma 21 20 1>, <&sdma 22 20 1>;
350 dma-names = "rxa", "rxb", "rxc",
351 "txa", "txb", "txc";
352 status = "okay";
353 };
354 };
355
356 pwm1: pwm@02080000 {
357 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
358 reg = <0x02080000 0x4000>;
359 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&clks IMX6SX_CLK_PWM1>,
361 <&clks IMX6SX_CLK_PWM1>;
362 clock-names = "ipg", "per";
363 #pwm-cells = <2>;
364 };
365
366 pwm2: pwm@02084000 {
367 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
368 reg = <0x02084000 0x4000>;
369 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&clks IMX6SX_CLK_PWM2>,
371 <&clks IMX6SX_CLK_PWM2>;
372 clock-names = "ipg", "per";
373 #pwm-cells = <2>;
374 };
375
376 pwm3: pwm@02088000 {
377 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
378 reg = <0x02088000 0x4000>;
379 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&clks IMX6SX_CLK_PWM3>,
381 <&clks IMX6SX_CLK_PWM3>;
382 clock-names = "ipg", "per";
383 #pwm-cells = <2>;
384 };
385
386 pwm4: pwm@0208c000 {
387 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
388 reg = <0x0208c000 0x4000>;
389 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6SX_CLK_PWM4>,
391 <&clks IMX6SX_CLK_PWM4>;
392 clock-names = "ipg", "per";
393 #pwm-cells = <2>;
394 };
395
396 flexcan1: can@02090000 {
397 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
398 reg = <0x02090000 0x4000>;
399 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&clks IMX6SX_CLK_CAN1_IPG>,
401 <&clks IMX6SX_CLK_CAN1_SERIAL>;
402 clock-names = "ipg", "per";
403 status = "disabled";
404 };
405
406 flexcan2: can@02094000 {
407 compatible = "fsl,imx6sx-flexcan", "fsl,imx6q-flexcan";
408 reg = <0x02094000 0x4000>;
409 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&clks IMX6SX_CLK_CAN2_IPG>,
411 <&clks IMX6SX_CLK_CAN2_SERIAL>;
412 clock-names = "ipg", "per";
413 status = "disabled";
414 };
415
416 gpt: gpt@02098000 {
417 compatible = "fsl,imx6sx-gpt", "fsl,imx31-gpt";
418 reg = <0x02098000 0x4000>;
419 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6SX_CLK_GPT_BUS>,
421 <&clks IMX6SX_CLK_GPT_SERIAL>;
422 clock-names = "ipg", "per";
423 };
424
425 gpio1: gpio@0209c000 {
426 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
427 reg = <0x0209c000 0x4000>;
428 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
430 gpio-controller;
431 #gpio-cells = <2>;
432 interrupt-controller;
433 #interrupt-cells = <2>;
434 };
435
436 gpio2: gpio@020a0000 {
437 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
438 reg = <0x020a0000 0x4000>;
439 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
441 gpio-controller;
442 #gpio-cells = <2>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
445 };
446
447 gpio3: gpio@020a4000 {
448 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
449 reg = <0x020a4000 0x4000>;
450 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
452 gpio-controller;
453 #gpio-cells = <2>;
454 interrupt-controller;
455 #interrupt-cells = <2>;
456 };
457
458 gpio4: gpio@020a8000 {
459 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
460 reg = <0x020a8000 0x4000>;
461 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
463 gpio-controller;
464 #gpio-cells = <2>;
465 interrupt-controller;
466 #interrupt-cells = <2>;
467 };
468
469 gpio5: gpio@020ac000 {
470 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
471 reg = <0x020ac000 0x4000>;
472 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
474 gpio-controller;
475 #gpio-cells = <2>;
476 interrupt-controller;
477 #interrupt-cells = <2>;
478 };
479
480 gpio6: gpio@020b0000 {
481 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
482 reg = <0x020b0000 0x4000>;
483 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 };
490
491 gpio7: gpio@020b4000 {
492 compatible = "fsl,imx6sx-gpio", "fsl,imx35-gpio";
493 reg = <0x020b4000 0x4000>;
494 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-controller;
499 #interrupt-cells = <2>;
500 };
501
502 kpp: kpp@020b8000 {
503 compatible = "fsl,imx6sx-kpp", "fsl,imx21-kpp";
504 reg = <0x020b8000 0x4000>;
505 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
506 clocks = <&clks IMX6SX_CLK_DUMMY>;
507 status = "disabled";
508 };
509
510 wdog1: wdog@020bc000 {
511 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
512 reg = <0x020bc000 0x4000>;
513 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&clks IMX6SX_CLK_DUMMY>;
515 };
516
517 wdog2: wdog@020c0000 {
518 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
519 reg = <0x020c0000 0x4000>;
520 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clks IMX6SX_CLK_DUMMY>;
522 status = "disabled";
523 };
524
525 clks: ccm@020c4000 {
526 compatible = "fsl,imx6sx-ccm";
527 reg = <0x020c4000 0x4000>;
528 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
530 #clock-cells = <1>;
531 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
532 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
533 };
534
535 anatop: anatop@020c8000 {
536 compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
537 "syscon", "simple-bus";
538 reg = <0x020c8000 0x1000>;
539 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
542
543 regulator-1p1@110 {
544 compatible = "fsl,anatop-regulator";
545 regulator-name = "vdd1p1";
546 regulator-min-microvolt = <800000>;
547 regulator-max-microvolt = <1375000>;
548 regulator-always-on;
549 anatop-reg-offset = <0x110>;
550 anatop-vol-bit-shift = <8>;
551 anatop-vol-bit-width = <5>;
552 anatop-min-bit-val = <4>;
553 anatop-min-voltage = <800000>;
554 anatop-max-voltage = <1375000>;
555 };
556
557 regulator-3p0@120 {
558 compatible = "fsl,anatop-regulator";
559 regulator-name = "vdd3p0";
560 regulator-min-microvolt = <2800000>;
561 regulator-max-microvolt = <3150000>;
562 regulator-always-on;
563 anatop-reg-offset = <0x120>;
564 anatop-vol-bit-shift = <8>;
565 anatop-vol-bit-width = <5>;
566 anatop-min-bit-val = <0>;
567 anatop-min-voltage = <2625000>;
568 anatop-max-voltage = <3400000>;
569 };
570
571 regulator-2p5@130 {
572 compatible = "fsl,anatop-regulator";
573 regulator-name = "vdd2p5";
574 regulator-min-microvolt = <2100000>;
575 regulator-max-microvolt = <2875000>;
576 regulator-always-on;
577 anatop-reg-offset = <0x130>;
578 anatop-vol-bit-shift = <8>;
579 anatop-vol-bit-width = <5>;
580 anatop-min-bit-val = <0>;
581 anatop-min-voltage = <2100000>;
582 anatop-max-voltage = <2875000>;
583 };
584
585 reg_arm: regulator-vddcore@140 {
586 compatible = "fsl,anatop-regulator";
587 regulator-name = "vddarm";
588 regulator-min-microvolt = <725000>;
589 regulator-max-microvolt = <1450000>;
590 regulator-always-on;
591 anatop-reg-offset = <0x140>;
592 anatop-vol-bit-shift = <0>;
593 anatop-vol-bit-width = <5>;
594 anatop-delay-reg-offset = <0x170>;
595 anatop-delay-bit-shift = <24>;
596 anatop-delay-bit-width = <2>;
597 anatop-min-bit-val = <1>;
598 anatop-min-voltage = <725000>;
599 anatop-max-voltage = <1450000>;
600 };
601
602 reg_pcie: regulator-vddpcie@140 {
603 compatible = "fsl,anatop-regulator";
604 regulator-name = "vddpcie";
605 regulator-min-microvolt = <725000>;
606 regulator-max-microvolt = <1450000>;
607 anatop-reg-offset = <0x140>;
608 anatop-vol-bit-shift = <9>;
609 anatop-vol-bit-width = <5>;
610 anatop-delay-reg-offset = <0x170>;
611 anatop-delay-bit-shift = <26>;
612 anatop-delay-bit-width = <2>;
613 anatop-min-bit-val = <1>;
614 anatop-min-voltage = <725000>;
615 anatop-max-voltage = <1450000>;
616 };
617
618 reg_soc: regulator-vddsoc@140 {
619 compatible = "fsl,anatop-regulator";
620 regulator-name = "vddsoc";
621 regulator-min-microvolt = <725000>;
622 regulator-max-microvolt = <1450000>;
623 regulator-always-on;
624 anatop-reg-offset = <0x140>;
625 anatop-vol-bit-shift = <18>;
626 anatop-vol-bit-width = <5>;
627 anatop-delay-reg-offset = <0x170>;
628 anatop-delay-bit-shift = <28>;
629 anatop-delay-bit-width = <2>;
630 anatop-min-bit-val = <1>;
631 anatop-min-voltage = <725000>;
632 anatop-max-voltage = <1450000>;
633 };
634 };
635
636 tempmon: tempmon {
637 compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon";
638 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
639 fsl,tempmon = <&anatop>;
640 fsl,tempmon-data = <&ocotp>;
641 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
642 };
643
644 usbphy1: usbphy@020c9000 {
645 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
646 reg = <0x020c9000 0x1000>;
647 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
648 clocks = <&clks IMX6SX_CLK_USBPHY1>;
649 fsl,anatop = <&anatop>;
650 };
651
652 usbphy2: usbphy@020ca000 {
653 compatible = "fsl,imx6sx-usbphy", "fsl,imx23-usbphy";
654 reg = <0x020ca000 0x1000>;
655 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&clks IMX6SX_CLK_USBPHY2>;
657 fsl,anatop = <&anatop>;
658 };
659
660 snvs: snvs@020cc000 {
661 compatible = "fsl,sec-v4.0-mon", "simple-bus";
662 #address-cells = <1>;
663 #size-cells = <1>;
664 ranges = <0 0x020cc000 0x4000>;
665
666 snvs-rtc-lp@34 {
667 compatible = "fsl,sec-v4.0-mon-rtc-lp";
668 reg = <0x34 0x58>;
669 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
670 };
671 };
672
673 epit1: epit@020d0000 {
674 reg = <0x020d0000 0x4000>;
675 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
676 };
677
678 epit2: epit@020d4000 {
679 reg = <0x020d4000 0x4000>;
680 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
681 };
682
683 src: src@020d8000 {
684 compatible = "fsl,imx6sx-src", "fsl,imx51-src";
685 reg = <0x020d8000 0x4000>;
686 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
688 #reset-cells = <1>;
689 };
690
691 gpc: gpc@020dc000 {
692 compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
693 reg = <0x020dc000 0x4000>;
694 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
695 };
696
697 iomuxc: iomuxc@020e0000 {
698 compatible = "fsl,imx6sx-iomuxc";
699 reg = <0x020e0000 0x4000>;
700 };
701
702 gpr: iomuxc-gpr@020e4000 {
703 compatible = "fsl,imx6sx-iomuxc-gpr",
704 "fsl,imx6q-iomuxc-gpr", "syscon";
705 reg = <0x020e4000 0x4000>;
706 };
707
708 sdma: sdma@020ec000 {
709 compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma";
710 reg = <0x020ec000 0x4000>;
711 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
712 clocks = <&clks IMX6SX_CLK_SDMA>,
713 <&clks IMX6SX_CLK_SDMA>;
714 clock-names = "ipg", "ahb";
715 #dma-cells = <3>;
716 /* imx6sx reuses imx6q sdma firmware */
717 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
718 };
719 };
720
721 aips2: aips-bus@02100000 {
722 compatible = "fsl,aips-bus", "simple-bus";
723 #address-cells = <1>;
724 #size-cells = <1>;
725 reg = <0x02100000 0x100000>;
726 ranges;
727
728 usbotg1: usb@02184000 {
729 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
730 reg = <0x02184000 0x200>;
731 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&clks IMX6SX_CLK_USBOH3>;
733 fsl,usbphy = <&usbphy1>;
734 fsl,usbmisc = <&usbmisc 0>;
735 fsl,anatop = <&anatop>;
736 status = "disabled";
737 };
738
739 usbotg2: usb@02184200 {
740 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
741 reg = <0x02184200 0x200>;
742 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&clks IMX6SX_CLK_USBOH3>;
744 fsl,usbphy = <&usbphy2>;
745 fsl,usbmisc = <&usbmisc 1>;
746 status = "disabled";
747 };
748
749 usbh: usb@02184400 {
750 compatible = "fsl,imx6sx-usb", "fsl,imx27-usb";
751 reg = <0x02184400 0x200>;
752 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
753 clocks = <&clks IMX6SX_CLK_USBOH3>;
754 fsl,usbmisc = <&usbmisc 2>;
755 phy_type = "hsic";
756 fsl,anatop = <&anatop>;
757 status = "disabled";
758 };
759
760 usbmisc: usbmisc@02184800 {
761 #index-cells = <1>;
762 compatible = "fsl,imx6sx-usbmisc", "fsl,imx6q-usbmisc";
763 reg = <0x02184800 0x200>;
764 clocks = <&clks IMX6SX_CLK_USBOH3>;
765 };
766
767 fec1: ethernet@02188000 {
768 compatible = "fsl,imx6sx-fec", "fsl,imx6q-fec";
769 reg = <0x02188000 0x4000>;
770 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&clks IMX6SX_CLK_ENET>,
773 <&clks IMX6SX_CLK_ENET_AHB>,
774 <&clks IMX6SX_CLK_ENET_PTP>,
775 <&clks IMX6SX_CLK_ENET_REF>,
776 <&clks IMX6SX_CLK_ENET_PTP>;
777 clock-names = "ipg", "ahb", "ptp",
778 "enet_clk_ref", "enet_out";
779 status = "disabled";
780 };
781
782 mlb: mlb@0218c000 {
783 reg = <0x0218c000 0x4000>;
784 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&clks IMX6SX_CLK_MLB>;
788 status = "disabled";
789 };
790
791 usdhc1: usdhc@02190000 {
792 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
793 reg = <0x02190000 0x4000>;
794 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clks IMX6SX_CLK_USDHC1>,
796 <&clks IMX6SX_CLK_USDHC1>,
797 <&clks IMX6SX_CLK_USDHC1>;
798 clock-names = "ipg", "ahb", "per";
799 bus-width = <4>;
800 status = "disabled";
801 };
802
803 usdhc2: usdhc@02194000 {
804 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
805 reg = <0x02194000 0x4000>;
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clks IMX6SX_CLK_USDHC2>,
808 <&clks IMX6SX_CLK_USDHC2>,
809 <&clks IMX6SX_CLK_USDHC2>;
810 clock-names = "ipg", "ahb", "per";
811 bus-width = <4>;
812 status = "disabled";
813 };
814
815 usdhc3: usdhc@02198000 {
816 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
817 reg = <0x02198000 0x4000>;
818 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clks IMX6SX_CLK_USDHC3>,
820 <&clks IMX6SX_CLK_USDHC3>,
821 <&clks IMX6SX_CLK_USDHC3>;
822 clock-names = "ipg", "ahb", "per";
823 bus-width = <4>;
824 status = "disabled";
825 };
826
827 usdhc4: usdhc@0219c000 {
828 compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
829 reg = <0x0219c000 0x4000>;
830 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
831 clocks = <&clks IMX6SX_CLK_USDHC4>,
832 <&clks IMX6SX_CLK_USDHC4>,
833 <&clks IMX6SX_CLK_USDHC4>;
834 clock-names = "ipg", "ahb", "per";
835 bus-width = <4>;
836 status = "disabled";
837 };
838
839 i2c1: i2c@021a0000 {
840 #address-cells = <1>;
841 #size-cells = <0>;
842 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
843 reg = <0x021a0000 0x4000>;
844 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clks IMX6SX_CLK_I2C1>;
846 status = "disabled";
847 };
848
849 i2c2: i2c@021a4000 {
850 #address-cells = <1>;
851 #size-cells = <0>;
852 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
853 reg = <0x021a4000 0x4000>;
854 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
855 clocks = <&clks IMX6SX_CLK_I2C2>;
856 status = "disabled";
857 };
858
859 i2c3: i2c@021a8000 {
860 #address-cells = <1>;
861 #size-cells = <0>;
862 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
863 reg = <0x021a8000 0x4000>;
864 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
865 clocks = <&clks IMX6SX_CLK_I2C3>;
866 status = "disabled";
867 };
868
869 mmdc: mmdc@021b0000 {
870 compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";
871 reg = <0x021b0000 0x4000>;
872 };
873
874 fec2: ethernet@021b4000 {
875 compatible = "fsl,imx6sx-fec";
876 reg = <0x021b4000 0x4000>;
877 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clks IMX6SX_CLK_ENET>,
880 <&clks IMX6SX_CLK_ENET_AHB>,
881 <&clks IMX6SX_CLK_ENET_PTP>,
882 <&clks IMX6SX_CLK_ENET2_REF_125M>,
883 <&clks IMX6SX_CLK_ENET_PTP>;
884 clock-names = "ipg", "ahb", "ptp",
885 "enet_clk_ref", "enet_out";
886 status = "disabled";
887 };
888
889 weim: weim@021b8000 {
890 compatible = "fsl,imx6sx-weim", "fsl,imx6q-weim";
891 reg = <0x021b8000 0x4000>;
892 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clks IMX6SX_CLK_EIM_SLOW>;
894 };
895
896 ocotp: ocotp@021bc000 {
897 compatible = "fsl,imx6sx-ocotp", "syscon";
898 reg = <0x021bc000 0x4000>;
899 clocks = <&clks IMX6SX_CLK_OCOTP>;
900 };
901
902 sai1: sai@021d4000 {
903 compatible = "fsl,imx6sx-sai";
904 reg = <0x021d4000 0x4000>;
905 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&clks IMX6SX_CLK_SAI1_IPG>,
907 <&clks IMX6SX_CLK_SAI1>,
908 <&clks 0>, <&clks 0>;
909 clock-names = "bus", "mclk1", "mclk2", "mclk3";
910 dma-names = "rx", "tx";
911 dmas = <&sdma 31 23 0>, <&sdma 32 23 0>;
912 dma-source = <&gpr 0 15 0 16>;
913 status = "disabled";
914 };
915
916 audmux: audmux@021d8000 {
917 compatible = "fsl,imx6sx-audmux", "fsl,imx31-audmux";
918 reg = <0x021d8000 0x4000>;
919 status = "disabled";
920 };
921
922 sai2: sai@021dc000 {
923 compatible = "fsl,imx6sx-sai";
924 reg = <0x021dc000 0x4000>;
925 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6SX_CLK_SAI2_IPG>,
927 <&clks IMX6SX_CLK_SAI2>,
928 <&clks 0>, <&clks 0>;
929 clock-names = "bus", "mclk1", "mclk2", "mclk3";
930 dma-names = "rx", "tx";
931 dmas = <&sdma 33 23 0>, <&sdma 34 23 0>;
932 dma-source = <&gpr 0 17 0 18>;
933 status = "disabled";
934 };
935
936 qspi1: qspi@021e0000 {
937 #address-cells = <1>;
938 #size-cells = <0>;
939 compatible = "fsl,imx6sx-qspi";
940 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
941 reg-names = "QuadSPI", "QuadSPI-memory";
942 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
943 clocks = <&clks IMX6SX_CLK_QSPI1>,
944 <&clks IMX6SX_CLK_QSPI1>;
945 clock-names = "qspi_en", "qspi";
946 status = "disabled";
947 };
948
949 qspi2: qspi@021e4000 {
950 #address-cells = <1>;
951 #size-cells = <0>;
952 compatible = "fsl,imx6sx-qspi";
953 reg = <0x021e4000 0x4000>, <0x70000000 0x10000000>;
954 reg-names = "QuadSPI", "QuadSPI-memory";
955 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&clks IMX6SX_CLK_QSPI2>,
957 <&clks IMX6SX_CLK_QSPI2>;
958 clock-names = "qspi_en", "qspi";
959 status = "disabled";
960 };
961
962 uart2: serial@021e8000 {
963 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
964 reg = <0x021e8000 0x4000>;
965 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&clks IMX6SX_CLK_UART_IPG>,
967 <&clks IMX6SX_CLK_UART_SERIAL>;
968 clock-names = "ipg", "per";
969 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
970 dma-names = "rx", "tx";
971 status = "disabled";
972 };
973
974 uart3: serial@021ec000 {
975 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
976 reg = <0x021ec000 0x4000>;
977 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
978 clocks = <&clks IMX6SX_CLK_UART_IPG>,
979 <&clks IMX6SX_CLK_UART_SERIAL>;
980 clock-names = "ipg", "per";
981 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
982 dma-names = "rx", "tx";
983 status = "disabled";
984 };
985
986 uart4: serial@021f0000 {
987 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
988 reg = <0x021f0000 0x4000>;
989 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
990 clocks = <&clks IMX6SX_CLK_UART_IPG>,
991 <&clks IMX6SX_CLK_UART_SERIAL>;
992 clock-names = "ipg", "per";
993 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
994 dma-names = "rx", "tx";
995 status = "disabled";
996 };
997
998 uart5: serial@021f4000 {
999 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1000 reg = <0x021f4000 0x4000>;
1001 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1003 <&clks IMX6SX_CLK_UART_SERIAL>;
1004 clock-names = "ipg", "per";
1005 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1006 dma-names = "rx", "tx";
1007 status = "disabled";
1008 };
1009
1010 i2c4: i2c@021f8000 {
1011 #address-cells = <1>;
1012 #size-cells = <0>;
1013 compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
1014 reg = <0x021f8000 0x4000>;
1015 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&clks IMX6SX_CLK_I2C4>;
1017 status = "disabled";
1018 };
1019 };
1020
1021 aips3: aips-bus@02200000 {
1022 compatible = "fsl,aips-bus", "simple-bus";
1023 #address-cells = <1>;
1024 #size-cells = <1>;
1025 reg = <0x02200000 0x100000>;
1026 ranges;
1027
1028 spba-bus@02200000 {
1029 compatible = "fsl,spba-bus", "simple-bus";
1030 #address-cells = <1>;
1031 #size-cells = <1>;
1032 reg = <0x02240000 0x40000>;
1033 ranges;
1034
1035 csi1: csi@02214000 {
1036 reg = <0x02214000 0x4000>;
1037 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1039 <&clks IMX6SX_CLK_CSI>,
1040 <&clks IMX6SX_CLK_DCIC1>;
1041 clock-names = "disp-axi", "csi_mclk", "dcic";
1042 status = "disabled";
1043 };
1044
1045 pxp: pxp@02218000 {
1046 reg = <0x02218000 0x4000>;
1047 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&clks IMX6SX_CLK_PXP_AXI>,
1049 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1050 clock-names = "pxp-axi", "disp-axi";
1051 status = "disabled";
1052 };
1053
1054 csi2: csi@0221c000 {
1055 reg = <0x0221c000 0x4000>;
1056 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&clks IMX6SX_CLK_DISPLAY_AXI>,
1058 <&clks IMX6SX_CLK_CSI>,
1059 <&clks IMX6SX_CLK_DCIC2>;
1060 clock-names = "disp-axi", "csi_mclk", "dcic";
1061 status = "disabled";
1062 };
1063
1064 lcdif1: lcdif@02220000 {
1065 reg = <0x02220000 0x4000>;
1066 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1067 clocks = <&clks IMX6SX_CLK_LCDIF1_PIX>,
1068 <&clks IMX6SX_CLK_LCDIF_APB>,
1069 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1070 clock-names = "pix", "axi", "disp_axi";
1071 status = "disabled";
1072 };
1073
1074 lcdif2: lcdif@02224000 {
1075 reg = <0x02224000 0x4000>;
1076 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1077 clocks = <&clks IMX6SX_CLK_LCDIF2_PIX>,
1078 <&clks IMX6SX_CLK_LCDIF_APB>,
1079 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1080 clock-names = "pix", "axi", "disp_axi";
1081 status = "disabled";
1082 };
1083
1084 vadc: vadc@02228000 {
1085 reg = <0x02228000 0x4000>, <0x0222c000 0x4000>;
1086 reg-names = "vadc-vafe", "vadc-vdec";
1087 clocks = <&clks IMX6SX_CLK_VADC>,
1088 <&clks IMX6SX_CLK_CSI>;
1089 clock-names = "vadc", "csi";
1090 status = "disabled";
1091 };
1092 };
1093
1094 adc1: adc@02280000 {
1095 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1096 reg = <0x02280000 0x4000>;
1097 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1098 clocks = <&clks IMX6SX_CLK_IPG>;
1099 clock-names = "adc";
1100 status = "disabled";
1101 };
1102
1103 adc2: adc@02284000 {
1104 compatible = "fsl,imx6sx-adc", "fsl,vf610-adc";
1105 reg = <0x02284000 0x4000>;
1106 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1107 clocks = <&clks IMX6SX_CLK_IPG>;
1108 clock-names = "adc";
1109 status = "disabled";
1110 };
1111
1112 wdog3: wdog@02288000 {
1113 compatible = "fsl,imx6sx-wdt", "fsl,imx21-wdt";
1114 reg = <0x02288000 0x4000>;
1115 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&clks IMX6SX_CLK_DUMMY>;
1117 status = "disabled";
1118 };
1119
1120 ecspi5: ecspi@0228c000 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 compatible = "fsl,imx6sx-ecspi", "fsl,imx51-ecspi";
1124 reg = <0x0228c000 0x4000>;
1125 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clks IMX6SX_CLK_ECSPI5>,
1127 <&clks IMX6SX_CLK_ECSPI5>;
1128 clock-names = "ipg", "per";
1129 status = "disabled";
1130 };
1131
1132 uart6: serial@022a0000 {
1133 compatible = "fsl,imx6sx-uart", "fsl,imx21-uart";
1134 reg = <0x022a0000 0x4000>;
1135 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&clks IMX6SX_CLK_UART_IPG>,
1137 <&clks IMX6SX_CLK_UART_SERIAL>;
1138 clock-names = "ipg", "per";
1139 dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
1140 dma-names = "rx", "tx";
1141 status = "disabled";
1142 };
1143
1144 pwm5: pwm@022a4000 {
1145 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1146 reg = <0x022a4000 0x4000>;
1147 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&clks IMX6SX_CLK_PWM5>,
1149 <&clks IMX6SX_CLK_PWM5>;
1150 clock-names = "ipg", "per";
1151 #pwm-cells = <2>;
1152 };
1153
1154 pwm6: pwm@022a8000 {
1155 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1156 reg = <0x022a8000 0x4000>;
1157 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1158 clocks = <&clks IMX6SX_CLK_PWM6>,
1159 <&clks IMX6SX_CLK_PWM6>;
1160 clock-names = "ipg", "per";
1161 #pwm-cells = <2>;
1162 };
1163
1164 pwm7: pwm@022ac000 {
1165 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1166 reg = <0x022ac000 0x4000>;
1167 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&clks IMX6SX_CLK_PWM7>,
1169 <&clks IMX6SX_CLK_PWM7>;
1170 clock-names = "ipg", "per";
1171 #pwm-cells = <2>;
1172 };
1173
1174 pwm8: pwm@0022b0000 {
1175 compatible = "fsl,imx6sx-pwm", "fsl,imx27-pwm";
1176 reg = <0x0022b0000 0x4000>;
1177 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&clks IMX6SX_CLK_PWM8>,
1179 <&clks IMX6SX_CLK_PWM8>;
1180 clock-names = "ipg", "per";
1181 #pwm-cells = <2>;
1182 };
1183 };
1184
1185 pcie: pcie@0x08000000 {
1186 compatible = "fsl,imx6sx-pcie", "snps,dw-pcie";
1187 reg = <0x08ffc000 0x4000>; /* DBI */
1188 #address-cells = <3>;
1189 #size-cells = <2>;
1190 device_type = "pci";
1191 /* configuration space */
1192 ranges = <0x00000800 0 0x08f00000 0x08f00000 0 0x00080000
1193 /* downstream I/O */
1194 0x81000000 0 0 0x08f80000 0 0x00010000
1195 /* non-prefetchable memory */
1196 0x82000000 0 0x08000000 0x08000000 0 0x00f00000>;
1197 num-lanes = <1>;
1198 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1199 clocks = <&clks IMX6SX_CLK_PCIE_REF_125M>,
1200 <&clks IMX6SX_CLK_PCIE_AXI>,
1201 <&clks IMX6SX_CLK_LVDS1_OUT>,
1202 <&clks IMX6SX_CLK_DISPLAY_AXI>;
1203 clock-names = "pcie_ref_125m", "pcie_axi",
1204 "lvds_gate", "display_axi";
1205 status = "disabled";
1206 };
1207 };
1208};
diff --git a/arch/arm/boot/dts/k2e-clocks.dtsi b/arch/arm/boot/dts/k2e-clocks.dtsi
index 90774d604bc1..598afe91c676 100644
--- a/arch/arm/boot/dts/k2e-clocks.dtsi
+++ b/arch/arm/boot/dts/k2e-clocks.dtsi
@@ -22,7 +22,7 @@ clocks {
22 #clock-cells = <0>; 22 #clock-cells = <0>;
23 compatible = "ti,keystone,pll-clock"; 23 compatible = "ti,keystone,pll-clock";
24 clocks = <&refclkpass>; 24 clocks = <&refclkpass>;
25 clock-output-names = "pa-pll-clk"; 25 clock-output-names = "papllclk";
26 reg = <0x02620358 4>; 26 reg = <0x02620358 4>;
27 reg-names = "control"; 27 reg-names = "control";
28 }; 28 };
diff --git a/arch/arm/boot/dts/k2hk-clocks.dtsi b/arch/arm/boot/dts/k2hk-clocks.dtsi
index 96e65365afe3..d5adee3c0067 100644
--- a/arch/arm/boot/dts/k2hk-clocks.dtsi
+++ b/arch/arm/boot/dts/k2hk-clocks.dtsi
@@ -31,7 +31,7 @@ clocks {
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock"; 32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclkpass>; 33 clocks = <&refclkpass>;
34 clock-output-names = "pa-pll-clk"; 34 clock-output-names = "papllclk";
35 reg = <0x02620358 4>; 35 reg = <0x02620358 4>;
36 reg-names = "control"; 36 reg-names = "control";
37 }; 37 };
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index 1f90cbf27fd7..3223cc152a85 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -167,3 +167,15 @@
167 }; 167 };
168 }; 168 };
169}; 169};
170
171&mdio {
172 ethphy0: ethernet-phy@0 {
173 compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
174 reg = <0>;
175 };
176
177 ethphy1: ethernet-phy@1 {
178 compatible = "marvell,88E1111", "ethernet-phy-ieee802.3-c22";
179 reg = <1>;
180 };
181};
diff --git a/arch/arm/boot/dts/k2l-clocks.dtsi b/arch/arm/boot/dts/k2l-clocks.dtsi
index f584b80200f8..eb1e3e29f073 100644
--- a/arch/arm/boot/dts/k2l-clocks.dtsi
+++ b/arch/arm/boot/dts/k2l-clocks.dtsi
@@ -31,7 +31,7 @@ clocks {
31 #clock-cells = <0>; 31 #clock-cells = <0>;
32 compatible = "ti,keystone,pll-clock"; 32 compatible = "ti,keystone,pll-clock";
33 clocks = <&refclksys>; 33 clocks = <&refclksys>;
34 clock-output-names = "pa-pll-clk"; 34 clock-output-names = "papllclk";
35 reg = <0x02620358 4>; 35 reg = <0x02620358 4>;
36 reg-names = "control"; 36 reg-names = "control";
37 }; 37 };
diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi b/arch/arm/boot/dts/keystone-clocks.dtsi
index 93f82c7010ab..0c334b25781e 100644
--- a/arch/arm/boot/dts/keystone-clocks.dtsi
+++ b/arch/arm/boot/dts/keystone-clocks.dtsi
@@ -215,7 +215,7 @@ clocks {
215 clkpa: clkpa { 215 clkpa: clkpa {
216 #clock-cells = <0>; 216 #clock-cells = <0>;
217 compatible = "ti,keystone,psc-clock"; 217 compatible = "ti,keystone,psc-clock";
218 clocks = <&chipclk16>; 218 clocks = <&paclk13>;
219 clock-output-names = "pa"; 219 clock-output-names = "pa";
220 reg = <0x0235001c 0xb00>, <0x02350008 0x400>; 220 reg = <0x0235001c 0xb00>, <0x02350008 0x400>;
221 reg-names = "control", "domain"; 221 reg-names = "control", "domain";
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index c1414cb81fd4..9e31fe7d31f8 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -266,5 +266,16 @@
266 ranges = <0 0 0x30000000 0x10000000 266 ranges = <0 0 0x30000000 0x10000000
267 1 0 0x21000A00 0x00000100>; 267 1 0 0x21000A00 0x00000100>;
268 }; 268 };
269
270 mdio: mdio@02090300 {
271 compatible = "ti,keystone_mdio", "ti,davinci_mdio";
272 #address-cells = <1>;
273 #size-cells = <0>;
274 reg = <0x02090300 0x100>;
275 status = "disabled";
276 clocks = <&clkpa>;
277 clock-names = "fck";
278 bus_freq = <2500000>;
279 };
269 }; 280 };
270}; 281};
diff --git a/arch/arm/boot/dts/kirkwood-d2net.dts b/arch/arm/boot/dts/kirkwood-d2net.dts
new file mode 100644
index 000000000000..6b7856025001
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-d2net.dts
@@ -0,0 +1,42 @@
1/*
2 * Device Tree file for d2 Network v2
3 *
4 * Copyright (C) 2014 Simon Guinot <simon.guinot@sequanux.org>
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9*/
10
11/dts-v1/;
12
13#include "kirkwood-netxbig.dtsi"
14
15/ {
16 model = "LaCie d2 Network v2";
17 compatible = "lacie,d2net_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
18
19 memory {
20 device_type = "memory";
21 reg = <0x00000000 0x10000000>;
22 };
23
24 ns2-leds {
25 compatible = "lacie,ns2-leds";
26
27 blue-sata {
28 label = "d2net_v2:blue:sata";
29 slow-gpio = <&gpio0 29 GPIO_ACTIVE_HIGH>;
30 cmd-gpio = <&gpio0 30 GPIO_ACTIVE_HIGH>;
31 };
32 };
33
34 gpio-leds {
35 compatible = "gpio-leds";
36
37 red-fail {
38 label = "d2net_v2:red:fail";
39 gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
40 };
41 };
42};
diff --git a/arch/arm/boot/dts/kirkwood-net2big.dts b/arch/arm/boot/dts/kirkwood-net2big.dts
new file mode 100644
index 000000000000..53dc37a3b687
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-net2big.dts
@@ -0,0 +1,60 @@
1/*
2 * Device Tree file for LaCie 2Big Network v2
3 *
4 * Copyright (C) 2014
5 *
6 * Andrew Lunn <andrew@lunn.ch>
7 *
8 * Based on netxbig_v2-setup.c,
9 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14*/
15
16/dts-v1/;
17
18#include "kirkwood.dtsi"
19#include "kirkwood-6281.dtsi"
20#include "kirkwood-netxbig.dtsi"
21
22/ {
23 model = "LaCie 2Big Network v2";
24 compatible = "lacie,net2big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x10000000>;
29 };
30};
31
32&regulators {
33 regulator@2 {
34 compatible = "regulator-fixed";
35 reg = <2>;
36 regulator-name = "hdd1power";
37 regulator-min-microvolt = <5000000>;
38 regulator-max-microvolt = <5000000>;
39 enable-active-high;
40 regulator-always-on;
41 regulator-boot-on;
42 gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
43 };
44
45 clocks {
46 g762_clk: g762-oscillator {
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <32768>;
50 };
51 };
52};
53
54&i2c0 {
55 g762@3e {
56 compatible = "gmt,g762";
57 reg = <0x3e>;
58 clocks = <&g762_clk>;
59 };
60};
diff --git a/arch/arm/boot/dts/kirkwood-net5big.dts b/arch/arm/boot/dts/kirkwood-net5big.dts
new file mode 100644
index 000000000000..36155b749d9f
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-net5big.dts
@@ -0,0 +1,111 @@
1/*
2 * Device Tree file for LaCie 5Big Network v2
3 *
4 * Copyright (C) 2014
5 *
6 * Andrew Lunn <andrew@lunn.ch>
7 *
8 * Based on netxbig_v2-setup.c,
9 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14*/
15
16/dts-v1/;
17
18#include "kirkwood.dtsi"
19#include "kirkwood-6281.dtsi"
20#include "kirkwood-netxbig.dtsi"
21
22/ {
23 model = "LaCie 5Big Network v2";
24 compatible = "lacie,net5big_v2", "lacie,netxbig", "marvell,kirkwood-88f6281", "marvell,kirkwood";
25
26 memory {
27 device_type = "memory";
28 reg = <0x00000000 0x20000000>;
29 };
30
31};
32
33&regulators {
34 regulator@2 {
35 compatible = "regulator-fixed";
36 reg = <2>;
37 regulator-name = "hdd1power";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 enable-active-high;
41 regulator-always-on;
42 regulator-boot-on;
43 gpio = <&gpio0 17 GPIO_ACTIVE_HIGH>;
44 };
45
46 regulator@3 {
47 compatible = "regulator-fixed";
48 reg = <3>;
49 regulator-name = "hdd2power";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 enable-active-high;
53 regulator-always-on;
54 regulator-boot-on;
55 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
56 };
57
58 regulator@4 {
59 compatible = "regulator-fixed";
60 reg = <4>;
61 regulator-name = "hdd3power";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 enable-active-high;
65 regulator-always-on;
66 regulator-boot-on;
67 gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
68 };
69
70 regulator@5 {
71 compatible = "regulator-fixed";
72 reg = <5>;
73 regulator-name = "hdd4power";
74 regulator-min-microvolt = <5000000>;
75 regulator-max-microvolt = <5000000>;
76 enable-active-high;
77 regulator-always-on;
78 regulator-boot-on;
79 gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
80 };
81
82 clocks {
83 g762_clk: g762-oscillator {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <32768>;
87 };
88 };
89};
90
91&mdio {
92 ethphy1: ethernet-phy@1 {
93 reg = <0>;
94 };
95};
96
97&eth1 {
98 status = "okay";
99 ethernet1-port@0 {
100 phy-handle = <&ethphy1>;
101 };
102};
103
104
105&i2c0 {
106 g762@3e {
107 compatible = "gmt,g762";
108 reg = <0x3e>;
109 clocks = <&g762_clk>;
110 };
111};
diff --git a/arch/arm/boot/dts/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/kirkwood-netxbig.dtsi
new file mode 100644
index 000000000000..b0cfb7cd30b9
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-netxbig.dtsi
@@ -0,0 +1,154 @@
1/*
2 * Device Tree common file for LaCie 2Big and 5Big Network v2
3 *
4 * Copyright (C) 2014
5 *
6 * Andrew Lunn <andrew@lunn.ch>
7 *
8 * Based on netxbig_v2-setup.c,
9 * Copyright (C) 2010 Simon Guinot <sguinot@lacie.com>
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14*/
15
16#include "kirkwood.dtsi"
17#include "kirkwood-6281.dtsi"
18
19/ {
20 chosen {
21 bootargs = "console=ttyS0,115200n8";
22 stdout-path = &uart0;
23 };
24
25 ocp@f1000000 {
26 serial@12000 {
27 status = "okay";
28 };
29
30 spi@10600 {
31 status = "okay";
32
33 flash@0 {
34 #address-cells = <1>;
35 #size-cells = <1>;
36 compatible = "mxicy,mx25l4005a";
37 reg = <0>;
38 spi-max-frequency = <20000000>;
39 mode = <0>;
40
41 partition@0 {
42 reg = <0x0 0x80000>;
43 label = "u-boot";
44 };
45 };
46 };
47
48 sata@80000 {
49 status = "okay";
50 nr-ports = <2>;
51 };
52
53 };
54
55 gpio-keys {
56 compatible = "gpio-keys";
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 /*
61 * button@1 and button@2 represent a three position rocker
62 * switch. Thus the conventional KEY_POWER does not fit
63 */
64 button@1 {
65 label = "Back power switch (on|auto)";
66 linux,code = <KEY_ESC>;
67 linux,input-type = <5>;
68 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
69 };
70 button@2 {
71 label = "Back power switch (auto|off)";
72 linux,code = <KEY_1>;
73 linux,input-type = <5>;
74 gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
75 };
76 button@3 {
77 label = "Function button";
78 linux,code = <KEY_OPTION>;
79 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
80 };
81
82 };
83
84 gpio-poweroff {
85 compatible = "gpio-poweroff";
86 gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
87 };
88
89 regulators: regulators {
90 status = "okay";
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <0>;
94 pinctrl-names = "default";
95
96 regulator@1 {
97 compatible = "regulator-fixed";
98 reg = <1>;
99 regulator-name = "hdd0power";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 enable-active-high;
103 regulator-always-on;
104 regulator-boot-on;
105 gpio = <&gpio0 16 GPIO_ACTIVE_HIGH>;
106 };
107 };
108};
109
110&mdio {
111 status = "okay";
112
113 ethphy0: ethernet-phy@0 {
114 reg = <8>;
115 };
116
117 ethphy1: ethernet-phy@1 {
118 reg = <0>;
119 };
120};
121
122&eth0 {
123 status = "okay";
124 ethernet0-port@0 {
125 phy-handle = <&ethphy0>;
126 };
127};
128
129&pinctrl {
130 pinctrl-names = "default";
131
132 pmx_button_function: pmx-button-function {
133 marvell,pins = "mpp34";
134 marvell,function = "gpio";
135 };
136 pmx_button_power_off: pmx-button-power-off {
137 marvell,pins = "mpp15";
138 marvell,function = "gpio";
139 };
140 pmx_button_power_on: pmx-button-power-on {
141 marvell,pins = "mpp13";
142 marvell,function = "gpio";
143 };
144};
145
146&i2c0 {
147 status = "okay";
148
149 eeprom@50 {
150 compatible = "atmel,24c04";
151 pagesize = <16>;
152 reg = <0x50>;
153 };
154};
diff --git a/arch/arm/boot/dts/kizbox.dts b/arch/arm/boot/dts/kizbox.dts
index 928f6eef2d59..e83e4f9310b8 100644
--- a/arch/arm/boot/dts/kizbox.dts
+++ b/arch/arm/boot/dts/kizbox.dts
@@ -30,6 +30,10 @@
30 compatible = "atmel,osc", "fixed-clock"; 30 compatible = "atmel,osc", "fixed-clock";
31 clock-frequency = <18432000>; 31 clock-frequency = <18432000>;
32 }; 32 };
33
34 main_xtal {
35 clock-frequency = <18432000>;
36 };
33 }; 37 };
34 38
35 ahb { 39 ahb {
diff --git a/arch/arm/boot/dts/mpa1600.dts b/arch/arm/boot/dts/mpa1600.dts
index ccf9ea242f72..f0f5e1098928 100644
--- a/arch/arm/boot/dts/mpa1600.dts
+++ b/arch/arm/boot/dts/mpa1600.dts
@@ -25,6 +25,14 @@
25 compatible = "atmel,osc", "fixed-clock"; 25 compatible = "atmel,osc", "fixed-clock";
26 clock-frequency = <18432000>; 26 clock-frequency = <18432000>;
27 }; 27 };
28
29 slow_xtal {
30 clock-frequency = <32768>;
31 };
32
33 main_xtal {
34 clock-frequency = <18432000>;
35 };
28 }; 36 };
29 37
30 ahb { 38 ahb {
diff --git a/arch/arm/boot/dts/omap2420.dtsi b/arch/arm/boot/dts/omap2420.dtsi
index 6d21994d824b..9be3c1266378 100644
--- a/arch/arm/boot/dts/omap2420.dtsi
+++ b/arch/arm/boot/dts/omap2420.dtsi
@@ -184,3 +184,6 @@
184&i2c2 { 184&i2c2 {
185 compatible = "ti,omap2420-i2c"; 185 compatible = "ti,omap2420-i2c";
186}; 186};
187
188/include/ "omap24xx-clocks.dtsi"
189/include/ "omap2420-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap2430.dtsi b/arch/arm/boot/dts/omap2430.dtsi
index aa6a354e236f..1a00f15d9096 100644
--- a/arch/arm/boot/dts/omap2430.dtsi
+++ b/arch/arm/boot/dts/omap2430.dtsi
@@ -290,3 +290,6 @@
290&i2c2 { 290&i2c2 {
291 compatible = "ti,omap2430-i2c"; 291 compatible = "ti,omap2430-i2c";
292}; 292};
293
294/include/ "omap24xx-clocks.dtsi"
295/include/ "omap2430-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 1e1b05768cec..159720d6c956 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -100,15 +100,33 @@
100 }; 100 };
101 }; 101 };
102 }; 102 };
103
104 sound: sound {
105 compatible = "ti,abe-twl6040";
106 ti,model = "omap5-uevm";
107
108 ti,mclk-freq = <19200000>;
109
110 ti,mcpdm = <&mcpdm>;
111
112 ti,twl6040 = <&twl6040>;
113
114 /* Audio routing */
115 ti,audio-routing =
116 "Headset Stereophone", "HSOL",
117 "Headset Stereophone", "HSOR",
118 "Line Out", "AUXL",
119 "Line Out", "AUXR",
120 "HSMIC", "Headset Mic",
121 "Headset Mic", "Headset Mic Bias",
122 "AFML", "Line In",
123 "AFMR", "Line In";
124 };
103}; 125};
104 126
105&omap5_pmx_core { 127&omap5_pmx_core {
106 pinctrl-names = "default"; 128 pinctrl-names = "default";
107 pinctrl-0 = < 129 pinctrl-0 = <
108 &twl6040_pins
109 &mcpdm_pins
110 &mcbsp1_pins
111 &mcbsp2_pins
112 &usbhost_pins 130 &usbhost_pins
113 &led_gpio_pins 131 &led_gpio_pins
114 >; 132 >;
@@ -306,6 +324,11 @@
306 ti,wakeup; 324 ti,wakeup;
307 }; 325 };
308 326
327 clk32kgaudio: palmas_clk32k@1 {
328 compatible = "ti,palmas-clk32kgaudio";
329 #clock-cells = <0>;
330 };
331
309 palmas_pmic { 332 palmas_pmic {
310 compatible = "ti,palmas-pmic"; 333 compatible = "ti,palmas-pmic";
311 interrupt-parent = <&palmas>; 334 interrupt-parent = <&palmas>;
@@ -489,6 +512,25 @@
489 }; 512 };
490 }; 513 };
491 }; 514 };
515
516 twl6040: twl@4b {
517 compatible = "ti,twl6040";
518 reg = <0x4b>;
519
520 pinctrl-names = "default";
521 pinctrl-0 = <&twl6040_pins>;
522
523 interrupts = <GIC_SPI 119 IRQ_TYPE_NONE>; /* IRQ_SYS_2N cascaded to gic */
524 interrupt-parent = <&gic>;
525 ti,audpwron-gpio = <&gpio5 13 0>; /* gpio line 141 */
526
527 vio-supply = <&smps7_reg>;
528 v2v1-supply = <&smps9_reg>;
529 enable-active-high;
530
531 clocks = <&clk32kgaudio>;
532 clock-names = "clk32k";
533 };
492}; 534};
493 535
494&i2c5 { 536&i2c5 {
@@ -505,8 +547,22 @@
505 }; 547 };
506}; 548};
507 549
508&mcbsp3 { 550&mcpdm {
509 status = "disabled"; 551 pinctrl-names = "default";
552 pinctrl-0 = <&mcpdm_pins>;
553 status = "okay";
554};
555
556&mcbsp1 {
557 pinctrl-names = "default";
558 pinctrl-0 = <&mcbsp1_pins>;
559 status = "okay";
560};
561
562&mcbsp2 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&mcbsp2_pins>;
565 status = "okay";
510}; 566};
511 567
512&usbhshost { 568&usbhshost {
diff --git a/arch/arm/boot/dts/pm9g45.dts b/arch/arm/boot/dts/pm9g45.dts
index 33ffabe9c4c8..66afcff67fde 100644
--- a/arch/arm/boot/dts/pm9g45.dts
+++ b/arch/arm/boot/dts/pm9g45.dts
@@ -29,6 +29,14 @@
29 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>; 30 clock-frequency = <12000000>;
31 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <12000000>;
39 };
32 }; 40 };
33 41
34 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/r7s72100-genmai.dts b/arch/arm/boot/dts/r7s72100-genmai.dts
index 56849b55e1c2..20705467f4c9 100644
--- a/arch/arm/boot/dts/r7s72100-genmai.dts
+++ b/arch/arm/boot/dts/r7s72100-genmai.dts
@@ -57,3 +57,13 @@
57&scif2 { 57&scif2 {
58 status = "okay"; 58 status = "okay";
59}; 59};
60
61&spi4 {
62 status = "okay";
63
64 codec: codec@0 {
65 compatible = "wlf,wm8978";
66 reg = <0>;
67 spi-max-frequency = <5000000>;
68 };
69};
diff --git a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
index 70b1fff8f4a3..a860f32bca27 100644
--- a/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
+++ b/arch/arm/boot/dts/r8a73a4-ape6evm-reference.dts
@@ -16,6 +16,10 @@
16 model = "APE6EVM"; 16 model = "APE6EVM";
17 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4"; 17 compatible = "renesas,ape6evm-reference", "renesas,r8a73a4";
18 18
19 aliases {
20 serial0 = &scifa0;
21 };
22
19 chosen { 23 chosen {
20 bootargs = "console=ttySC0,115200 ignore_loglevel rw"; 24 bootargs = "console=ttySC0,115200 ignore_loglevel rw";
21 }; 25 };
@@ -90,9 +94,6 @@
90}; 94};
91 95
92&pfc { 96&pfc {
93 pinctrl-0 = <&scifa0_pins>;
94 pinctrl-names = "default";
95
96 scifa0_pins: serial0 { 97 scifa0_pins: serial0 {
97 renesas,groups = "scifa0_data"; 98 renesas,groups = "scifa0_data";
98 renesas,function = "scifa0"; 99 renesas,function = "scifa0";
@@ -123,6 +124,13 @@
123 status = "okay"; 124 status = "okay";
124}; 125};
125 126
127&scifa0 {
128 pinctrl-0 = <&scifa0_pins>;
129 pinctrl-names = "default";
130
131 status = "okay";
132};
133
126&sdhi0 { 134&sdhi0 {
127 vmmc-supply = <&vcc_sdhi0>; 135 vmmc-supply = <&vcc_sdhi0>;
128 bus-width = <4>; 136 bus-width = <4>;
diff --git a/arch/arm/boot/dts/r8a73a4.dtsi b/arch/arm/boot/dts/r8a73a4.dtsi
index 82c5ac825386..d8ec5058c351 100644
--- a/arch/arm/boot/dts/r8a73a4.dtsi
+++ b/arch/arm/boot/dts/r8a73a4.dtsi
@@ -252,6 +252,48 @@
252 status = "disabled"; 252 status = "disabled";
253 }; 253 };
254 254
255 scifa0: serial@e6c40000 {
256 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
257 reg = <0 0xe6c40000 0 0x100>;
258 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
259 status = "disabled";
260 };
261
262 scifa1: serial@e6c50000 {
263 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
264 reg = <0 0xe6c50000 0 0x100>;
265 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
266 status = "disabled";
267 };
268
269 scifb2: serial@e6c20000 {
270 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
271 reg = <0 0xe6c20000 0 0x100>;
272 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
273 status = "disabled";
274 };
275
276 scifb3: serial@e6c30000 {
277 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
278 reg = <0 0xe6c30000 0 0x100>;
279 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
280 status = "disabled";
281 };
282
283 scifb4: serial@e6ce0000 {
284 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
285 reg = <0 0xe6ce0000 0 0x100>;
286 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
287 status = "disabled";
288 };
289
290 scifb5: serial@e6cf0000 {
291 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
292 reg = <0 0xe6cf0000 0 0x100>;
293 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
294 status = "disabled";
295 };
296
255 mmcif0: mmc@ee200000 { 297 mmcif0: mmc@ee200000 {
256 compatible = "renesas,sh-mmcif"; 298 compatible = "renesas,sh-mmcif";
257 reg = <0 0xee200000 0 0x80>; 299 reg = <0 0xee200000 0 0x80>;
diff --git a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
index 486007d7ffe4..ee9e7d5c97a9 100644
--- a/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
+++ b/arch/arm/boot/dts/r8a7740-armadillo800eva-reference.dts
@@ -19,8 +19,12 @@
19 model = "armadillo 800 eva reference"; 19 model = "armadillo 800 eva reference";
20 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740"; 20 compatible = "renesas,armadillo800eva-reference", "renesas,r8a7740";
21 21
22 aliases {
23 serial1 = &scifa1;
24 };
25
22 chosen { 26 chosen {
23 bootargs = "console=tty0 console=ttySC1,115200 earlyprintk=sh-sci.1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 27 bootargs = "console=tty0 console=ttySC1,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
24 }; 28 };
25 29
26 memory { 30 memory {
@@ -104,17 +108,21 @@
104 108
105 leds { 109 leds {
106 compatible = "gpio-leds"; 110 compatible = "gpio-leds";
107 led1 { 111 led3 {
108 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>; 112 gpios = <&pfc 102 GPIO_ACTIVE_HIGH>;
113 label = "LED3";
109 }; 114 };
110 led2 { 115 led4 {
111 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>; 116 gpios = <&pfc 111 GPIO_ACTIVE_HIGH>;
117 label = "LED4";
112 }; 118 };
113 led3 { 119 led5 {
114 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>; 120 gpios = <&pfc 110 GPIO_ACTIVE_HIGH>;
121 label = "LED5";
115 }; 122 };
116 led4 { 123 led6 {
117 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>; 124 gpios = <&pfc 177 GPIO_ACTIVE_HIGH>;
125 label = "LED6";
118 }; 126 };
119 }; 127 };
120 128
@@ -198,9 +206,6 @@
198}; 206};
199 207
200&pfc { 208&pfc {
201 pinctrl-0 = <&scifa1_pins>;
202 pinctrl-names = "default";
203
204 ether_pins: ether { 209 ether_pins: ether {
205 renesas,groups = "gether_mii", "gether_int"; 210 renesas,groups = "gether_mii", "gether_int";
206 renesas,function = "gether"; 211 renesas,function = "gether";
@@ -252,6 +257,13 @@
252 status = "okay"; 257 status = "okay";
253}; 258};
254 259
260&scifa1 {
261 pinctrl-0 = <&scifa1_pins>;
262 pinctrl-names = "default";
263
264 status = "okay";
265};
266
255&sdhi0 { 267&sdhi0 {
256 pinctrl-0 = <&sdhi0_pins>; 268 pinctrl-0 = <&sdhi0_pins>;
257 pinctrl-names = "default"; 269 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 55d29f4d2ed6..bda18fb3d9e5 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -156,6 +156,69 @@
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 158
159 scifa0: serial@e6c40000 {
160 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
161 reg = <0xe6c40000 0x100>;
162 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
163 status = "disabled";
164 };
165
166 scifa1: serial@e6c50000 {
167 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
168 reg = <0xe6c50000 0x100>;
169 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
170 status = "disabled";
171 };
172
173 scifa2: serial@e6c60000 {
174 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
175 reg = <0xe6c60000 0x100>;
176 interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
177 status = "disabled";
178 };
179
180 scifa3: serial@e6c70000 {
181 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
182 reg = <0xe6c70000 0x100>;
183 interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>;
184 status = "disabled";
185 };
186
187 scifa4: serial@e6c80000 {
188 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
189 reg = <0xe6c80000 0x100>;
190 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
191 status = "disabled";
192 };
193
194 scifa5: serial@e6cb0000 {
195 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
196 reg = <0xe6cb0000 0x100>;
197 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
198 status = "disabled";
199 };
200
201 scifa6: serial@e6cc0000 {
202 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
203 reg = <0xe6cc0000 0x100>;
204 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
205 status = "disabled";
206 };
207
208 scifa7: serial@e6cd0000 {
209 compatible = "renesas,scifa-r8a7740", "renesas,scifa";
210 reg = <0xe6cd0000 0x100>;
211 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
212 status = "disabled";
213 };
214
215 scifb8: serial@e6c30000 {
216 compatible = "renesas,scifb-r8a7740", "renesas,scifb";
217 reg = <0xe6c30000 0x100>;
218 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
219 status = "disabled";
220 };
221
159 pfc: pfc@e6050000 { 222 pfc: pfc@e6050000 {
160 compatible = "renesas,pfc-r8a7740"; 223 compatible = "renesas,pfc-r8a7740";
161 reg = <0xe6050000 0x8000>, 224 reg = <0xe6050000 0x8000>,
diff --git a/arch/arm/boot/dts/r8a7778-bockw-reference.dts b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
index f76f6ec01e19..3342c74c5de8 100644
--- a/arch/arm/boot/dts/r8a7778-bockw-reference.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw-reference.dts
@@ -23,6 +23,10 @@
23 model = "bockw"; 23 model = "bockw";
24 compatible = "renesas,bockw-reference", "renesas,r8a7778"; 24 compatible = "renesas,bockw-reference", "renesas,r8a7778";
25 25
26 aliases {
27 serial0 = &scif0;
28 };
29
26 chosen { 30 chosen {
27 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw"; 31 bootargs = "console=ttySC0,115200 ignore_loglevel root=/dev/nfs ip=dhcp rw";
28 }; 32 };
@@ -70,9 +74,6 @@
70}; 74};
71 75
72&pfc { 76&pfc {
73 pinctrl-0 = <&scif0_pins>;
74 pinctrl-names = "default";
75
76 scif0_pins: serial0 { 77 scif0_pins: serial0 {
77 renesas,groups = "scif0_data_a", "scif0_ctrl"; 78 renesas,groups = "scif0_data_a", "scif0_ctrl";
78 renesas,function = "scif0"; 79 renesas,function = "scif0";
@@ -124,3 +125,10 @@
124 }; 125 };
125 }; 126 };
126}; 127};
128
129&scif0 {
130 pinctrl-0 = <&scif0_pins>;
131 pinctrl-names = "default";
132
133 status = "okay";
134};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index 3af0a2187493..ecfdf4b01b5a 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -156,6 +156,48 @@
156 status = "disabled"; 156 status = "disabled";
157 }; 157 };
158 158
159 scif0: serial@ffe40000 {
160 compatible = "renesas,scif-r8a7778", "renesas,scif";
161 reg = <0xffe40000 0x100>;
162 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
163 status = "disabled";
164 };
165
166 scif1: serial@ffe41000 {
167 compatible = "renesas,scif-r8a7778", "renesas,scif";
168 reg = <0xffe41000 0x100>;
169 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
170 status = "disabled";
171 };
172
173 scif2: serial@ffe42000 {
174 compatible = "renesas,scif-r8a7778", "renesas,scif";
175 reg = <0xffe42000 0x100>;
176 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
177 status = "disabled";
178 };
179
180 scif3: serial@ffe43000 {
181 compatible = "renesas,scif-r8a7778", "renesas,scif";
182 reg = <0xffe43000 0x100>;
183 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
184 status = "disabled";
185 };
186
187 scif4: serial@ffe44000 {
188 compatible = "renesas,scif-r8a7778", "renesas,scif";
189 reg = <0xffe44000 0x100>;
190 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
191 status = "disabled";
192 };
193
194 scif5: serial@ffe45000 {
195 compatible = "renesas,scif-r8a7778", "renesas,scif";
196 reg = <0xffe45000 0x100>;
197 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
198 status = "disabled";
199 };
200
159 mmcif: mmc@ffe4e000 { 201 mmcif: mmc@ffe4e000 {
160 compatible = "renesas,sh-mmcif"; 202 compatible = "renesas,sh-mmcif";
161 reg = <0xffe4e000 0x100>; 203 reg = <0xffe4e000 0x100>;
diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index 94e2fc836492..58d0d952d60e 100644
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -54,13 +54,13 @@
54 spi2 = &hspi2; 54 spi2 = &hspi2;
55 }; 55 };
56 56
57 gic: interrupt-controller@f0001000 { 57 gic: interrupt-controller@f0001000 {
58 compatible = "arm,cortex-a9-gic"; 58 compatible = "arm,cortex-a9-gic";
59 #interrupt-cells = <3>; 59 #interrupt-cells = <3>;
60 interrupt-controller; 60 interrupt-controller;
61 reg = <0xf0001000 0x1000>, 61 reg = <0xf0001000 0x1000>,
62 <0xf0000100 0x100>; 62 <0xf0000100 0x100>;
63 }; 63 };
64 64
65 gpio0: gpio@ffc40000 { 65 gpio0: gpio@ffc40000 {
66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar"; 66 compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index dd2fe46073f2..856b4236b674 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -29,12 +29,12 @@
29 29
30 memory@40000000 { 30 memory@40000000 {
31 device_type = "memory"; 31 device_type = "memory";
32 reg = <0 0x40000000 0 0x80000000>; 32 reg = <0 0x40000000 0 0x40000000>;
33 }; 33 };
34 34
35 memory@180000000 { 35 memory@180000000 {
36 device_type = "memory"; 36 device_type = "memory";
37 reg = <1 0x80000000 0 0x80000000>; 37 reg = <1 0x40000000 0 0xc0000000>;
38 }; 38 };
39 39
40 lbsc { 40 lbsc {
@@ -204,6 +204,36 @@
204 "msiof1_tx"; 204 "msiof1_tx";
205 renesas,function = "msiof1"; 205 renesas,function = "msiof1";
206 }; 206 };
207
208 iic1_pins: iic1 {
209 renesas,groups = "iic1";
210 renesas,function = "iic1";
211 };
212
213 iic2_pins: iic2 {
214 renesas,groups = "iic2";
215 renesas,function = "iic2";
216 };
217
218 iic3_pins: iic3 {
219 renesas,groups = "iic3";
220 renesas,function = "iic3";
221 };
222
223 usb0_pins: usb0 {
224 renesas,groups = "usb0";
225 renesas,function = "usb0";
226 };
227
228 usb1_pins: usb1 {
229 renesas,groups = "usb1";
230 renesas,function = "usb1";
231 };
232
233 usb2_pins: usb2 {
234 renesas,groups = "usb2";
235 renesas,function = "usb2";
236 };
207}; 237};
208 238
209&ether { 239&ether {
@@ -317,3 +347,57 @@
317 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; 347 cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
318 status = "okay"; 348 status = "okay";
319}; 349};
350
351&cpu0 {
352 cpu0-supply = <&vdd_dvfs>;
353};
354
355&iic0 {
356 status = "ok";
357};
358
359&iic1 {
360 status = "ok";
361 pinctrl-0 = <&iic1_pins>;
362 pinctrl-names = "default";
363};
364
365&iic2 {
366 status = "ok";
367 pinctrl-0 = <&iic2_pins>;
368 pinctrl-names = "default";
369};
370
371&iic3 {
372 pinctrl-names = "default";
373 pinctrl-0 = <&iic3_pins>;
374 status = "okay";
375
376 vdd_dvfs: regulator@68 {
377 compatible = "diasemi,da9210";
378 reg = <0x68>;
379
380 regulator-min-microvolt = <1000000>;
381 regulator-max-microvolt = <1000000>;
382 regulator-boot-on;
383 regulator-always-on;
384 };
385};
386
387&pci0 {
388 status = "okay";
389 pinctrl-0 = <&usb0_pins>;
390 pinctrl-names = "default";
391};
392
393&pci1 {
394 status = "okay";
395 pinctrl-0 = <&usb1_pins>;
396 pinctrl-names = "default";
397};
398
399&pci2 {
400 status = "okay";
401 pinctrl-0 = <&usb2_pins>;
402 pinctrl-names = "default";
403};
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 7ff29601f962..d9ddecbb859c 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -44,6 +44,17 @@
44 compatible = "arm,cortex-a15"; 44 compatible = "arm,cortex-a15";
45 reg = <0>; 45 reg = <0>;
46 clock-frequency = <1300000000>; 46 clock-frequency = <1300000000>;
47 voltage-tolerance = <1>; /* 1% */
48 clocks = <&cpg_clocks R8A7790_CLK_Z>;
49 clock-latency = <300000>; /* 300 us */
50
51 /* kHz - uV - OPPs unknown yet */
52 operating-points = <1400000 1000000>,
53 <1225000 1000000>,
54 <1050000 1000000>,
55 < 875000 1000000>,
56 < 700000 1000000>,
57 < 350000 1000000>;
47 }; 58 };
48 59
49 cpu1: cpu@1 { 60 cpu1: cpu@1 {
@@ -476,6 +487,15 @@
476 clock-output-names = "extal"; 487 clock-output-names = "extal";
477 }; 488 };
478 489
490 /* External PCIe clock - can be overridden by the board */
491 pcie_bus_clk: pcie_bus_clk {
492 compatible = "fixed-clock";
493 #clock-cells = <0>;
494 clock-frequency = <100000000>;
495 clock-output-names = "pcie_bus";
496 status = "disabled";
497 };
498
479 /* 499 /*
480 * The external audio clocks are configured as 0 Hz fixed frequency clocks by 500 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
481 * default. Boards that provide audio clocks should override them. 501 * default. Boards that provide audio clocks should override them.
@@ -754,17 +774,17 @@
754 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 774 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
755 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, 775 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
756 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, 776 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
757 <&hp_clk>, <&hp_clk>, <&rclk_clk>; 777 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
758 #clock-cells = <1>; 778 #clock-cells = <1>;
759 renesas,clock-indices = < 779 renesas,clock-indices = <
760 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 780 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
761 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 781 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
762 R8A7790_CLK_IIC0 R8A7790_CLK_IIC1 R8A7790_CLK_CMT1 782 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
763 >; 783 >;
764 clock-output-names = 784 clock-output-names =
765 "iic2", "tpu0", "mmcif1", "sdhi3", 785 "iic2", "tpu0", "mmcif1", "sdhi3",
766 "sdhi2", "sdhi1", "sdhi0", "mmcif0", 786 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
767 "iic0", "iic1", "cmt1"; 787 "iic0", "pciec", "iic1", "ssusb", "cmt1";
768 }; 788 };
769 mstp5_clks: mstp5_clks@e6150144 { 789 mstp5_clks: mstp5_clks@e6150144 {
770 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 790 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -824,6 +844,39 @@
824 "rcan1", "rcan0", "qspi_mod", "iic3", 844 "rcan1", "rcan0", "qspi_mod", "iic3",
825 "i2c3", "i2c2", "i2c1", "i2c0"; 845 "i2c3", "i2c2", "i2c1", "i2c0";
826 }; 846 };
847 mstp10_clks: mstp10_clks@e6150998 {
848 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
849 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
850 clocks = <&p_clk>,
851 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
852 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
853 <&p_clk>,
854 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
855 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
856 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
857 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
858 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
859 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
860
861 #clock-cells = <1>;
862 clock-indices = <
863 R8A7790_CLK_SSI_ALL
864 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
865 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
866 R8A7790_CLK_SCU_ALL
867 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
868 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
869 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
870 >;
871 clock-output-names =
872 "ssi-all",
873 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
874 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
875 "scu-all",
876 "scu-dvc1", "scu-dvc0",
877 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
878 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
879 };
827 }; 880 };
828 881
829 qspi: spi@e6b10000 { 882 qspi: spi@e6b10000 {
@@ -876,4 +929,152 @@
876 #size-cells = <0>; 929 #size-cells = <0>;
877 status = "disabled"; 930 status = "disabled";
878 }; 931 };
932
933 pci0: pci@ee090000 {
934 compatible = "renesas,pci-r8a7790";
935 device_type = "pci";
936 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
937 reg = <0 0xee090000 0 0xc00>,
938 <0 0xee080000 0 0x1100>;
939 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
940 status = "disabled";
941
942 bus-range = <0 0>;
943 #address-cells = <3>;
944 #size-cells = <2>;
945 #interrupt-cells = <1>;
946 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
947 interrupt-map-mask = <0xff00 0 0 0x7>;
948 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
949 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
950 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
951 };
952
953 pci1: pci@ee0b0000 {
954 compatible = "renesas,pci-r8a7790";
955 device_type = "pci";
956 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
957 reg = <0 0xee0b0000 0 0xc00>,
958 <0 0xee0a0000 0 0x1100>;
959 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
960 status = "disabled";
961
962 bus-range = <1 1>;
963 #address-cells = <3>;
964 #size-cells = <2>;
965 #interrupt-cells = <1>;
966 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
967 interrupt-map-mask = <0xff00 0 0 0x7>;
968 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
969 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
970 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
971 };
972
973 pci2: pci@ee0d0000 {
974 compatible = "renesas,pci-r8a7790";
975 device_type = "pci";
976 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
977 reg = <0 0xee0d0000 0 0xc00>,
978 <0 0xee0c0000 0 0x1100>;
979 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
980 status = "disabled";
981
982 bus-range = <2 2>;
983 #address-cells = <3>;
984 #size-cells = <2>;
985 #interrupt-cells = <1>;
986 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
987 interrupt-map-mask = <0xff00 0 0 0x7>;
988 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
989 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
990 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
991 };
992
993 pciec: pcie@fe000000 {
994 compatible = "renesas,pcie-r8a7790";
995 reg = <0 0xfe000000 0 0x80000>;
996 #address-cells = <3>;
997 #size-cells = <2>;
998 bus-range = <0x00 0xff>;
999 device_type = "pci";
1000 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1001 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1002 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1003 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1004 /* Map all possible DDR as inbound ranges */
1005 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1006 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1007 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1008 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1009 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1010 #interrupt-cells = <1>;
1011 interrupt-map-mask = <0 0 0 0>;
1012 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1014 clock-names = "pcie", "pcie_bus";
1015 status = "disabled";
1016 };
1017
1018 rcar_sound: rcar_sound@0xec500000 {
1019 #sound-dai-cells = <1>;
1020 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1021 interrupt-parent = <&gic>;
1022 reg = <0 0xec500000 0 0x1000>, /* SCU */
1023 <0 0xec5a0000 0 0x100>, /* ADG */
1024 <0 0xec540000 0 0x1000>, /* SSIU */
1025 <0 0xec541000 0 0x1280>; /* SSI */
1026 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1027 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1028 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1029 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1030 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1031 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1032 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1033 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1034 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1035 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1036 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
1037 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
1038 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1039 clock-names = "ssi-all",
1040 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1041 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1042 "src.9", "src.8", "src.7", "src.6", "src.5",
1043 "src.4", "src.3", "src.2", "src.1", "src.0",
1044 "dvc.0", "dvc.1",
1045 "clk_a", "clk_b", "clk_c", "clk_i";
1046
1047 status = "disabled";
1048
1049 rcar_sound,dvc {
1050 dvc0: dvc@0 { };
1051 dvc1: dvc@1 { };
1052 };
1053
1054 rcar_sound,src {
1055 src0: src@0 { };
1056 src1: src@1 { };
1057 src2: src@2 { };
1058 src3: src@3 { };
1059 src4: src@4 { };
1060 src5: src@5 { };
1061 src6: src@6 { };
1062 src7: src@7 { };
1063 src8: src@8 { };
1064 src9: src@9 { };
1065 };
1066
1067 rcar_sound,ssi {
1068 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1069 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1070 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1071 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1072 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1073 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1074 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1075 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1076 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1077 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1078 };
1079 };
879}; 1080};
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index cc6d992e8db2..3a2ef0a2a137 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -110,6 +110,11 @@
110 renesas,function = "sdhi2"; 110 renesas,function = "sdhi2";
111 }; 111 };
112 112
113 i2c2_pins: i2c2 {
114 renesas,groups = "i2c2";
115 renesas,function = "i2c2";
116 };
117
113 qspi_pins: spi0 { 118 qspi_pins: spi0 {
114 renesas,groups = "qspi_ctrl", "qspi_data4"; 119 renesas,groups = "qspi_ctrl", "qspi_data4";
115 renesas,function = "qspi"; 120 renesas,function = "qspi";
@@ -120,6 +125,16 @@
120 "msiof0_tx"; 125 "msiof0_tx";
121 renesas,function = "msiof0"; 126 renesas,function = "msiof0";
122 }; 127 };
128
129 usb0_pins: usb0 {
130 renesas,groups = "usb0";
131 renesas,function = "usb0";
132 };
133
134 usb1_pins: usb1 {
135 renesas,groups = "usb1";
136 renesas,function = "usb1";
137 };
123}; 138};
124 139
125&scif0 { 140&scif0 {
@@ -146,7 +161,7 @@
146}; 161};
147 162
148&sata0 { 163&sata0 {
149 status = "okay"; 164 status = "okay";
150}; 165};
151 166
152&sdhi0 { 167&sdhi0 {
@@ -170,6 +185,14 @@
170 status = "okay"; 185 status = "okay";
171}; 186};
172 187
188&i2c2 {
189 pinctrl-0 = <&i2c2_pins>;
190 pinctrl-names = "default";
191
192 status = "okay";
193 clock-frequency = <400000>;
194};
195
173&qspi { 196&qspi {
174 pinctrl-0 = <&qspi_pins>; 197 pinctrl-0 = <&qspi_pins>;
175 pinctrl-names = "default"; 198 pinctrl-names = "default";
@@ -217,3 +240,23 @@
217 spi-cpha; 240 spi-cpha;
218 }; 241 };
219}; 242};
243
244&pci0 {
245 status = "okay";
246 pinctrl-0 = <&usb0_pins>;
247 pinctrl-names = "default";
248};
249
250&pci1 {
251 status = "okay";
252 pinctrl-0 = <&usb1_pins>;
253 pinctrl-names = "default";
254};
255
256&pcie_bus_clk {
257 status = "okay";
258};
259
260&pciec {
261 status = "okay";
262};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 05d44f9b202f..23486c081a69 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -215,25 +215,6 @@
215 clock-frequency = <20000000>; 215 clock-frequency = <20000000>;
216}; 216};
217 217
218&i2c2 {
219 pinctrl-0 = <&i2c2_pins>;
220 pinctrl-names = "default";
221
222 status = "okay";
223 clock-frequency = <400000>;
224
225 eeprom@50 {
226 compatible = "renesas,24c02";
227 reg = <0x50>;
228 pagesize = <16>;
229 };
230};
231
232&i2c6 {
233 status = "okay";
234 clock-frequency = <100000>;
235};
236
237&pfc { 218&pfc {
238 pinctrl-0 = <&du_pins>; 219 pinctrl-0 = <&du_pins>;
239 pinctrl-names = "default"; 220 pinctrl-names = "default";
@@ -293,6 +274,21 @@
293 "msiof0_tx"; 274 "msiof0_tx";
294 renesas,function = "msiof0"; 275 renesas,function = "msiof0";
295 }; 276 };
277
278 i2c6_pins: i2c6 {
279 renesas,groups = "i2c6";
280 renesas,function = "i2c6";
281 };
282
283 usb0_pins: usb0 {
284 renesas,groups = "usb0";
285 renesas,function = "usb0";
286 };
287
288 usb1_pins: usb1 {
289 renesas,groups = "usb1";
290 renesas,function = "usb1";
291 };
296}; 292};
297 293
298&ether { 294&ether {
@@ -408,3 +404,58 @@
408 spi-cpha; 404 spi-cpha;
409 }; 405 };
410}; 406};
407
408&i2c2 {
409 pinctrl-0 = <&i2c2_pins>;
410 pinctrl-names = "default";
411
412 status = "okay";
413 clock-frequency = <400000>;
414
415 eeprom@50 {
416 compatible = "renesas,24c02";
417 reg = <0x50>;
418 pagesize = <16>;
419 };
420};
421
422&i2c6 {
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c6_pins>;
425 status = "okay";
426 clock-frequency = <100000>;
427
428 vdd_dvfs: regulator@68 {
429 compatible = "diasemi,da9210";
430 reg = <0x68>;
431
432 regulator-min-microvolt = <1000000>;
433 regulator-max-microvolt = <1000000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437};
438
439&pci0 {
440 status = "okay";
441 pinctrl-0 = <&usb0_pins>;
442 pinctrl-names = "default";
443};
444
445&pci1 {
446 status = "okay";
447 pinctrl-0 = <&usb1_pins>;
448 pinctrl-names = "default";
449};
450
451&pcie_bus_clk {
452 status = "okay";
453};
454
455&pciec {
456 status = "okay";
457};
458
459&cpu0 {
460 cpu0-supply = <&vdd_dvfs>;
461};
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 79f68acfd5d4..0d82a4b3c650 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -45,6 +45,17 @@
45 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
46 reg = <0>; 46 reg = <0>;
47 clock-frequency = <1500000000>; 47 clock-frequency = <1500000000>;
48 voltage-tolerance = <1>; /* 1% */
49 clocks = <&cpg_clocks R8A7791_CLK_Z>;
50 clock-latency = <300000>; /* 300 us */
51
52 /* kHz - uV - OPPs unknown yet */
53 operating-points = <1500000 1000000>,
54 <1312500 1000000>,
55 <1125000 1000000>,
56 < 937500 1000000>,
57 < 750000 1000000>,
58 < 375000 1000000>;
48 }; 59 };
49 60
50 cpu1: cpu@1 { 61 cpu1: cpu@1 {
@@ -521,6 +532,38 @@
521 clock-output-names = "extal"; 532 clock-output-names = "extal";
522 }; 533 };
523 534
535 /*
536 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
537 * default. Boards that provide audio clocks should override them.
538 */
539 audio_clk_a: audio_clk_a {
540 compatible = "fixed-clock";
541 #clock-cells = <0>;
542 clock-frequency = <0>;
543 clock-output-names = "audio_clk_a";
544 };
545 audio_clk_b: audio_clk_b {
546 compatible = "fixed-clock";
547 #clock-cells = <0>;
548 clock-frequency = <0>;
549 clock-output-names = "audio_clk_b";
550 };
551 audio_clk_c: audio_clk_c {
552 compatible = "fixed-clock";
553 #clock-cells = <0>;
554 clock-frequency = <0>;
555 clock-output-names = "audio_clk_c";
556 };
557
558 /* External PCIe clock - can be overridden by the board */
559 pcie_bus_clk: pcie_bus_clk {
560 compatible = "fixed-clock";
561 #clock-cells = <0>;
562 clock-frequency = <100000000>;
563 clock-output-names = "pcie_bus";
564 status = "disabled";
565 };
566
524 /* Special CPG clocks */ 567 /* Special CPG clocks */
525 cpg_clocks: cpg_clocks@e6150000 { 568 cpg_clocks: cpg_clocks@e6150000 {
526 compatible = "renesas,r8a7791-cpg-clocks", 569 compatible = "renesas,r8a7791-cpg-clocks",
@@ -743,30 +786,34 @@
743 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 786 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
744 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 787 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
745 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 788 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
746 <&mp_clk>, <&mp_clk>, <&mp_clk>; 789 <&mp_clk>, <&mp_clk>, <&mp_clk>,
790 <&zs_clk>, <&zs_clk>;
747 #clock-cells = <1>; 791 #clock-cells = <1>;
748 renesas,clock-indices = < 792 renesas,clock-indices = <
749 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 793 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
750 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 794 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
751 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 795 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
796 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
752 >; 797 >;
753 clock-output-names = 798 clock-output-names =
754 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", 799 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
755 "scifb1", "msiof1", "scifb2"; 800 "scifb1", "msiof1", "scifb2",
801 "sys-dmac1", "sys-dmac0";
756 }; 802 };
757 mstp3_clks: mstp3_clks@e615013c { 803 mstp3_clks: mstp3_clks@e615013c {
758 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 804 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
759 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 805 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
760 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 806 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
761 <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>; 807 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
762 #clock-cells = <1>; 808 #clock-cells = <1>;
763 renesas,clock-indices = < 809 renesas,clock-indices = <
764 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 810 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
765 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_IIC1 R8A7791_CLK_CMT1 811 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
812 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
766 >; 813 >;
767 clock-output-names = 814 clock-output-names =
768 "tpu0", "sdhi2", "sdhi1", "sdhi0", 815 "tpu0", "sdhi2", "sdhi1", "sdhi0",
769 "mmcif0", "i2c7", "i2c8", "cmt1"; 816 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1";
770 }; 817 };
771 mstp5_clks: mstp5_clks@e6150144 { 818 mstp5_clks: mstp5_clks@e6150144 {
772 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 819 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -828,6 +875,39 @@
828 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", 875 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
829 "i2c1", "i2c0"; 876 "i2c1", "i2c0";
830 }; 877 };
878 mstp10_clks: mstp10_clks@e6150998 {
879 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
880 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
881 clocks = <&p_clk>,
882 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
883 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
884 <&p_clk>,
885 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
886 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
887 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
888 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
889 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
890 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
891
892 #clock-cells = <1>;
893 clock-indices = <
894 R8A7791_CLK_SSI_ALL
895 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
896 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
897 R8A7791_CLK_SCU_ALL
898 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
899 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
900 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
901 >;
902 clock-output-names =
903 "ssi-all",
904 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
905 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
906 "scu-all",
907 "scu-dvc1", "scu-dvc0",
908 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
909 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
910 };
831 mstp11_clks: mstp11_clks@e615099c { 911 mstp11_clks: mstp11_clks@e615099c {
832 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 912 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
833 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; 913 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
@@ -880,4 +960,132 @@
880 #size-cells = <0>; 960 #size-cells = <0>;
881 status = "disabled"; 961 status = "disabled";
882 }; 962 };
963
964 pci0: pci@ee090000 {
965 compatible = "renesas,pci-r8a7791";
966 device_type = "pci";
967 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
968 reg = <0 0xee090000 0 0xc00>,
969 <0 0xee080000 0 0x1100>;
970 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
971 status = "disabled";
972
973 bus-range = <0 0>;
974 #address-cells = <3>;
975 #size-cells = <2>;
976 #interrupt-cells = <1>;
977 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
978 interrupt-map-mask = <0xff00 0 0 0x7>;
979 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
980 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
981 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
982 };
983
984 pci1: pci@ee0d0000 {
985 compatible = "renesas,pci-r8a7791";
986 device_type = "pci";
987 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
988 reg = <0 0xee0d0000 0 0xc00>,
989 <0 0xee0c0000 0 0x1100>;
990 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
991 status = "disabled";
992
993 bus-range = <1 1>;
994 #address-cells = <3>;
995 #size-cells = <2>;
996 #interrupt-cells = <1>;
997 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
998 interrupt-map-mask = <0xff00 0 0 0x7>;
999 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1000 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1001 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
1002 };
1003
1004 pciec: pcie@fe000000 {
1005 compatible = "renesas,pcie-r8a7791";
1006 reg = <0 0xfe000000 0 0x80000>;
1007 #address-cells = <3>;
1008 #size-cells = <2>;
1009 bus-range = <0x00 0xff>;
1010 device_type = "pci";
1011 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1012 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1013 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1014 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1015 /* Map all possible DDR as inbound ranges */
1016 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1017 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1018 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1019 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1020 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1021 #interrupt-cells = <1>;
1022 interrupt-map-mask = <0 0 0 0>;
1023 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1024 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1025 clock-names = "pcie", "pcie_bus";
1026 status = "disabled";
1027 };
1028
1029 rcar_sound: rcar_sound@0xec500000 {
1030 #sound-dai-cells = <1>;
1031 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
1032 interrupt-parent = <&gic>;
1033 reg = <0 0xec500000 0 0x1000>, /* SCU */
1034 <0 0xec5a0000 0 0x100>, /* ADG */
1035 <0 0xec540000 0 0x1000>, /* SSIU */
1036 <0 0xec541000 0 0x1280>; /* SSI */
1037 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1038 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1039 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1040 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1041 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1042 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1043 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1044 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1045 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1046 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1047 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
1048 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
1049 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1050 clock-names = "ssi-all",
1051 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1052 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1053 "src.9", "src.8", "src.7", "src.6", "src.5",
1054 "src.4", "src.3", "src.2", "src.1", "src.0",
1055 "dvc.0", "dvc.1",
1056 "clk_a", "clk_b", "clk_c", "clk_i";
1057
1058 status = "disabled";
1059
1060 rcar_sound,dvc {
1061 dvc0: dvc@0 { };
1062 dvc1: dvc@1 { };
1063 };
1064
1065 rcar_sound,src {
1066 src0: src@0 { };
1067 src1: src@1 { };
1068 src2: src@2 { };
1069 src3: src@3 { };
1070 src4: src@4 { };
1071 src5: src@5 { };
1072 src6: src@6 { };
1073 src7: src@7 { };
1074 src8: src@8 { };
1075 src9: src@9 { };
1076 };
1077
1078 rcar_sound,ssi {
1079 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1080 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1081 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1082 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1083 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1084 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1085 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1086 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1087 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1088 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1089 };
1090 };
883}; 1091};
diff --git a/arch/arm/boot/dts/rk3066a-bqcurie2.dts b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
index afb327322a4a..042f821d9e4d 100644
--- a/arch/arm/boot/dts/rk3066a-bqcurie2.dts
+++ b/arch/arm/boot/dts/rk3066a-bqcurie2.dts
@@ -24,87 +24,171 @@
24 reg = <0x60000000 0x40000000>; 24 reg = <0x60000000 0x40000000>;
25 }; 25 };
26 26
27 soc { 27 vcc_sd0: fixed-regulator {
28 uart0: serial@10124000 { 28 compatible = "regulator-fixed";
29 status = "okay"; 29 regulator-name = "sdmmc-supply";
30 }; 30 regulator-min-microvolt = <3000000>;
31 regulator-max-microvolt = <3000000>;
32 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
33 startup-delay-us = <100000>;
34 vin-supply = <&vcc_io>;
35 };
31 36
32 uart1: serial@10126000 { 37 gpio-keys {
33 status = "okay"; 38 compatible = "gpio-keys";
39 #address-cells = <1>;
40 #size-cells = <0>;
41 autorepeat;
42
43 button@0 {
44 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
45 linux,code = <116>;
46 label = "GPIO Key Power";
47 linux,input-type = <1>;
48 gpio-key,wakeup = <1>;
49 debounce-interval = <100>;
34 }; 50 };
35 51 button@1 {
36 uart2: serial@20064000 { 52 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */
37 pinctrl-names = "default"; 53 linux,code = <104>;
38 pinctrl-0 = <&uart2_xfer>; 54 label = "GPIO Key Vol-";
39 status = "okay"; 55 linux,input-type = <1>;
56 gpio-key,wakeup = <0>;
57 debounce-interval = <100>;
40 }; 58 };
59 /* VOL+ comes somehow thru the ADC */
60 };
61};
41 62
42 uart3: serial@20068000 { 63&i2c1 {
43 status = "okay"; 64 status = "okay";
44 }; 65 clock-frequency = <400000>;
45 66
46 vcc_sd0: fixed-regulator { 67 tps: tps@2d {
47 compatible = "regulator-fixed"; 68 reg = <0x2d>;
48 regulator-name = "sdmmc-supply";
49 regulator-min-microvolt = <3000000>;
50 regulator-max-microvolt = <3000000>;
51 gpio = <&gpio3 7 GPIO_ACTIVE_LOW>;
52 startup-delay-us = <100000>;
53 };
54 69
55 dwmmc@10214000 { /* sdmmc */ 70 interrupt-parent = <&gpio6>;
56 num-slots = <1>; 71 interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
57 status = "okay";
58 72
59 pinctrl-names = "default"; 73 vcc5-supply = <&vcc_io>;
60 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>; 74 vcc6-supply = <&vcc_io>;
61 vmmc-supply = <&vcc_sd0>;
62 75
63 slot@0 { 76 regulators {
64 reg = <0>; 77 vcc_rtc: regulator@0 {
65 bus-width = <4>; 78 regulator-name = "vcc_rtc";
66 disable-wp; 79 regulator-always-on;
67 }; 80 };
68 };
69 81
70 dwmmc@10218000 { /* wifi */ 82 vcc_io: regulator@1 {
71 num-slots = <1>; 83 regulator-name = "vcc_io";
72 status = "okay"; 84 regulator-always-on;
73 non-removable; 85 };
74 86
75 pinctrl-names = "default"; 87 vdd_arm: regulator@2 {
76 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; 88 regulator-name = "vdd_arm";
89 regulator-min-microvolt = <600000>;
90 regulator-max-microvolt = <1500000>;
91 regulator-boot-on;
92 regulator-always-on;
93 };
77 94
78 slot@0 { 95 vcc_ddr: regulator@3 {
79 reg = <0>; 96 regulator-name = "vcc_ddr";
80 bus-width = <4>; 97 regulator-min-microvolt = <600000>;
81 disable-wp; 98 regulator-max-microvolt = <1500000>;
99 regulator-boot-on;
100 regulator-always-on;
101 };
102
103 vcc18_cif: regulator@5 {
104 regulator-name = "vcc18_cif";
105 regulator-always-on;
106 };
107
108 vdd_11: regulator@6 {
109 regulator-name = "vdd_11";
110 regulator-always-on;
111 };
112
113 vcc_25: regulator@7 {
114 regulator-name = "vcc_25";
115 regulator-always-on;
116 };
117
118 vcc_18: regulator@8 {
119 regulator-name = "vcc_18";
120 regulator-always-on;
121 };
122
123 vcc25_hdmi: regulator@9 {
124 regulator-name = "vcc25_hdmi";
125 regulator-always-on;
126 };
127
128 vcca_33: regulator@10 {
129 regulator-name = "vcca_33";
130 regulator-always-on;
82 }; 131 };
83 };
84 132
85 gpio-keys { 133 vcc_tp: regulator@11 {
86 compatible = "gpio-keys"; 134 regulator-name = "vcc_tp";
87 #address-cells = <1>; 135 regulator-always-on;
88 #size-cells = <0>;
89 autorepeat;
90
91 button@0 {
92 gpios = <&gpio6 2 GPIO_ACTIVE_LOW>; /* GPIO6_A2 */
93 linux,code = <116>;
94 label = "GPIO Key Power";
95 linux,input-type = <1>;
96 gpio-key,wakeup = <1>;
97 debounce-interval = <100>;
98 }; 136 };
99 button@1 { 137
100 gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; /* GPIO4_C5 */ 138 vcc28_cif: regulator@12 {
101 linux,code = <104>; 139 regulator-name = "vcc28_cif";
102 label = "GPIO Key Vol-"; 140 regulator-always-on;
103 linux,input-type = <1>;
104 gpio-key,wakeup = <0>;
105 debounce-interval = <100>;
106 }; 141 };
107 /* VOL+ comes somehow thru the ADC */
108 }; 142 };
109 }; 143 };
110}; 144};
145
146/* must be included after &tps gets defined */
147#include "tps65910.dtsi"
148
149&mmc0 { /* sdmmc */
150 num-slots = <1>;
151 status = "okay";
152 vmmc-supply = <&vcc_sd0>;
153
154 slot@0 {
155 reg = <0>;
156 bus-width = <4>;
157 disable-wp;
158 };
159};
160
161&mmc1 { /* wifi */
162 num-slots = <1>;
163 status = "okay";
164 non-removable;
165
166 pinctrl-names = "default";
167 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>;
168
169 slot@0 {
170 reg = <0>;
171 bus-width = <4>;
172 disable-wp;
173 };
174};
175
176&uart0 {
177 status = "okay";
178};
179
180&uart1 {
181 status = "okay";
182};
183
184&uart2 {
185 status = "okay";
186};
187
188&uart3 {
189 status = "okay";
190};
191
192&wdt {
193 status = "okay";
194};
diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi
deleted file mode 100644
index 6e307fc4c451..000000000000
--- a/arch/arm/boot/dts/rk3066a-clocks.dtsi
+++ /dev/null
@@ -1,299 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_i2s0",
69 "gate_i2s0_frac", "gate_i2s1",
70 "gate_i2s1_frac", "gate_i2s2",
71 "gate_i2s2_frac", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer2", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "gate_tsadc";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&dummy>, <&dummy>,
133 <&dummy>, <&dummy>,
134 <&dummy>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&dummy>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_pclkin_cif1", "reserved",
143 "reserved", "gate_cif0_out",
144 "gate_cif1_out", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "gate_gpu_src",
147 "reserved", "gate_xin27m";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&clk_gates0 3>,
161 <&clk_gates0 3>, <&clk_gates2 3>,
162 <&clk_gates0 4>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
171 "gate_aclk_intmem", "gate_pclk_tsadc",
172 "gate_hclk_hdmi";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>,
187 <&clk_gates4 5>, <&dummy>;
188
189 clock-output-names =
190 "gate_aclk_dmac1", "gate_aclk_dmac2",
191 "gate_pclk_efuse", "gate_pclk_tzpc",
192 "gate_pclk_grf", "gate_pclk_pmu",
193 "gate_hclk_rom", "gate_pclk_ddrupctl",
194 "gate_aclk_smc", "gate_hclk_nandc",
195 "gate_hclk_mmc0", "gate_hclk_mmc1",
196 "gate_hclk_emmc", "gate_hclk_otg0",
197 "gate_hclk_otg1", "gate_aclk_gpu";
198
199 #clock-cells = <1>;
200 };
201
202 clk_gates6: gate-clk@200000e8 {
203 compatible = "rockchip,rk2928-gate-clk";
204 reg = <0x200000e8 0x4>;
205 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
206 <&clk_gates0 4>, <&clk_gates1 4>,
207 <&clk_gates0 4>, <&clk_gates3 0>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates3 0>, <&clk_gates0 4>,
210 <&clk_gates0 4>, <&clk_gates1 4>,
211 <&clk_gates0 4>, <&clk_gates3 0>,
212 <&dummy>, <&dummy>;
213
214 clock-output-names =
215 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
216 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
217 "gate_hclk_cif0", "gate_aclk_cif0",
218 "gate_hclk_cif1", "gate_aclk_cif1",
219 "gate_aclk_ipp", "gate_hclk_ipp",
220 "gate_hclk_rga", "gate_aclk_rga",
221 "gate_hclk_vio_bus", "gate_aclk_vio0",
222 "gate_aclk_vcodec", "gate_shclk_vio_h2h";
223
224 #clock-cells = <1>;
225 };
226
227 clk_gates7: gate-clk@200000ec {
228 compatible = "rockchip,rk2928-gate-clk";
229 reg = <0x200000ec 0x4>;
230 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
231 <&clk_gates0 4>, <&clk_gates0 4>,
232 <&clk_gates0 4>, <&clk_gates2 2>,
233 <&clk_gates2 2>, <&clk_gates0 5>,
234 <&clk_gates0 5>, <&clk_gates0 5>,
235 <&clk_gates0 5>, <&clk_gates2 3>,
236 <&clk_gates2 3>, <&clk_gates2 3>,
237 <&clk_gates2 3>, <&clk_gates2 3>;
238
239 clock-output-names =
240 "gate_hclk_emac", "gate_hclk_spdif",
241 "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
242 "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
243 "gate_hclk_pidf", "gate_pclk_timer0",
244 "gate_pclk_timer1", "gate_pclk_timer2",
245 "gate_pclk_pwm01", "gate_pclk_pwm23",
246 "gate_pclk_spi0", "gate_pclk_spi1",
247 "gate_pclk_saradc", "gate_pclk_wdt";
248
249 #clock-cells = <1>;
250 };
251
252 clk_gates8: gate-clk@200000f0 {
253 compatible = "rockchip,rk2928-gate-clk";
254 reg = <0x200000f0 0x4>;
255 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
256 <&clk_gates2 3>, <&clk_gates2 3>,
257 <&clk_gates0 5>, <&clk_gates0 5>,
258 <&clk_gates2 3>, <&clk_gates2 3>,
259 <&clk_gates2 3>, <&clk_gates0 5>,
260 <&clk_gates0 5>, <&clk_gates0 5>,
261 <&clk_gates2 3>, <&clk_gates2 3>,
262 <&dummy>, <&clk_gates0 5>;
263
264 clock-output-names =
265 "gate_pclk_uart0", "gate_pclk_uart1",
266 "gate_pclk_uart2", "gate_pclk_uart3",
267 "gate_pclk_i2c0", "gate_pclk_i2c1",
268 "gate_pclk_i2c2", "gate_pclk_i2c3",
269 "gate_pclk_i2c4", "gate_pclk_gpio0",
270 "gate_pclk_gpio1", "gate_pclk_gpio2",
271 "gate_pclk_gpio3", "gate_pclk_gpio4",
272 "reserved", "gate_pclk_gpio6";
273
274 #clock-cells = <1>;
275 };
276
277 clk_gates9: gate-clk@200000f4 {
278 compatible = "rockchip,rk2928-gate-clk";
279 reg = <0x200000f4 0x4>;
280 clocks = <&dummy>, <&clk_gates0 5>,
281 <&dummy>, <&dummy>,
282 <&dummy>, <&clk_gates1 4>,
283 <&clk_gates0 5>, <&dummy>,
284 <&dummy>, <&dummy>,
285 <&dummy>;
286
287 clock-output-names =
288 "gate_clk_core_dbg", "gate_pclk_dbg",
289 "gate_clk_trace", "gate_atclk",
290 "gate_clk_l2c", "gate_aclk_vio1",
291 "gate_pclk_publ", "gate_aclk_intmem0",
292 "gate_aclk_intmem1", "gate_aclk_intmem2",
293 "gate_aclk_intmem3";
294
295 #clock-cells = <1>;
296 };
297 };
298
299};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index 4387cfd420ba..879a818fba51 100644
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -15,8 +15,8 @@
15 15
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h> 17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3066a-cru.h>
18#include "rk3xxx.dtsi" 19#include "rk3xxx.dtsi"
19#include "rk3066a-clocks.dtsi"
20 20
21/ { 21/ {
22 compatible = "rockchip,rk3066a"; 22 compatible = "rockchip,rk3066a";
@@ -40,247 +40,392 @@
40 }; 40 };
41 }; 41 };
42 42
43 soc { 43 sram: sram@10080000 {
44 timer@20038000 { 44 compatible = "mmio-sram";
45 compatible = "snps,dw-apb-timer-osc"; 45 reg = <0x10080000 0x10000>;
46 reg = <0x20038000 0x100>; 46 #address-cells = <1>;
47 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 47 #size-cells = <1>;
48 clocks = <&clk_gates1 0>, <&clk_gates7 7>; 48 ranges = <0 0x10080000 0x10000>;
49 clock-names = "timer", "pclk"; 49
50 smp-sram@0 {
51 compatible = "rockchip,rk3066-smp-sram";
52 reg = <0x0 0x50>;
50 }; 53 };
54 };
55
56 cru: clock-controller@20000000 {
57 compatible = "rockchip,rk3066a-cru";
58 reg = <0x20000000 0x1000>;
59 rockchip,grf = <&grf>;
51 60
52 timer@2003a000 { 61 #clock-cells = <1>;
53 compatible = "snps,dw-apb-timer-osc"; 62 #reset-cells = <1>;
54 reg = <0x2003a000 0x100>; 63 };
55 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 64
56 clocks = <&clk_gates1 1>, <&clk_gates7 8>; 65 timer@2000e000 {
57 clock-names = "timer", "pclk"; 66 compatible = "snps,dw-apb-timer-osc";
67 reg = <0x2000e000 0x100>;
68 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
69 clocks = <&cru SCLK_TIMER2>, <&cru PCLK_TIMER2>;
70 clock-names = "timer", "pclk";
71 };
72
73 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&cru SCLK_TIMER0>, <&cru PCLK_TIMER0>;
78 clock-names = "timer", "pclk";
79 };
80
81 timer@2003a000 {
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&cru SCLK_TIMER1>, <&cru PCLK_TIMER1>;
86 clock-names = "timer", "pclk";
87 };
88
89 pinctrl: pinctrl {
90 compatible = "rockchip,rk3066a-pinctrl";
91 rockchip,grf = <&grf>;
92 #address-cells = <1>;
93 #size-cells = <1>;
94 ranges;
95
96 gpio0: gpio0@20034000 {
97 compatible = "rockchip,gpio-bank";
98 reg = <0x20034000 0x100>;
99 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru PCLK_GPIO0>;
101
102 gpio-controller;
103 #gpio-cells = <2>;
104
105 interrupt-controller;
106 #interrupt-cells = <2>;
58 }; 107 };
59 108
60 timer@2000e000 { 109 gpio1: gpio1@2003c000 {
61 compatible = "snps,dw-apb-timer-osc"; 110 compatible = "rockchip,gpio-bank";
62 reg = <0x2000e000 0x100>; 111 reg = <0x2003c000 0x100>;
63 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 112 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
64 clocks = <&clk_gates1 2>, <&clk_gates7 9>; 113 clocks = <&cru PCLK_GPIO1>;
65 clock-names = "timer", "pclk"; 114
115 gpio-controller;
116 #gpio-cells = <2>;
117
118 interrupt-controller;
119 #interrupt-cells = <2>;
66 }; 120 };
67 121
68 sram: sram@10080000 { 122 gpio2: gpio2@2003e000 {
69 compatible = "mmio-sram"; 123 compatible = "rockchip,gpio-bank";
70 reg = <0x10080000 0x10000>; 124 reg = <0x2003e000 0x100>;
71 #address-cells = <1>; 125 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
72 #size-cells = <1>; 126 clocks = <&cru PCLK_GPIO2>;
73 ranges = <0 0x10080000 0x10000>;
74 127
75 smp-sram@0 { 128 gpio-controller;
76 compatible = "rockchip,rk3066-smp-sram"; 129 #gpio-cells = <2>;
77 reg = <0x0 0x50>; 130
78 }; 131 interrupt-controller;
132 #interrupt-cells = <2>;
133 };
134
135 gpio3: gpio3@20080000 {
136 compatible = "rockchip,gpio-bank";
137 reg = <0x20080000 0x100>;
138 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru PCLK_GPIO3>;
140
141 gpio-controller;
142 #gpio-cells = <2>;
143
144 interrupt-controller;
145 #interrupt-cells = <2>;
79 }; 146 };
80 147
81 pinctrl@20008000 { 148 gpio4: gpio4@20084000 {
82 compatible = "rockchip,rk3066a-pinctrl"; 149 compatible = "rockchip,gpio-bank";
83 rockchip,grf = <&grf>; 150 reg = <0x20084000 0x100>;
84 #address-cells = <1>; 151 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
85 #size-cells = <1>; 152 clocks = <&cru PCLK_GPIO4>;
86 ranges;
87 153
88 gpio0: gpio0@20034000 { 154 gpio-controller;
89 compatible = "rockchip,gpio-bank"; 155 #gpio-cells = <2>;
90 reg = <0x20034000 0x100>;
91 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
92 clocks = <&clk_gates8 9>;
93 156
94 gpio-controller; 157 interrupt-controller;
95 #gpio-cells = <2>; 158 #interrupt-cells = <2>;
159 };
96 160
97 interrupt-controller; 161 gpio6: gpio6@2000a000 {
98 #interrupt-cells = <2>; 162 compatible = "rockchip,gpio-bank";
163 reg = <0x2000a000 0x100>;
164 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cru PCLK_GPIO6>;
166
167 gpio-controller;
168 #gpio-cells = <2>;
169
170 interrupt-controller;
171 #interrupt-cells = <2>;
172 };
173
174 pcfg_pull_default: pcfg_pull_default {
175 bias-pull-pin-default;
176 };
177
178 pcfg_pull_none: pcfg_pull_none {
179 bias-disable;
180 };
181
182 i2c0 {
183 i2c0_xfer: i2c0-xfer {
184 rockchip,pins = <RK_GPIO2 28 RK_FUNC_1 &pcfg_pull_none>,
185 <RK_GPIO2 29 RK_FUNC_1 &pcfg_pull_none>;
99 }; 186 };
187 };
100 188
101 gpio1: gpio1@2003c000 { 189 i2c1 {
102 compatible = "rockchip,gpio-bank"; 190 i2c1_xfer: i2c1-xfer {
103 reg = <0x2003c000 0x100>; 191 rockchip,pins = <RK_GPIO2 30 RK_FUNC_1 &pcfg_pull_none>,
104 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 192 <RK_GPIO2 31 RK_FUNC_1 &pcfg_pull_none>;
105 clocks = <&clk_gates8 10>; 193 };
194 };
106 195
107 gpio-controller; 196 i2c2 {
108 #gpio-cells = <2>; 197 i2c2_xfer: i2c2-xfer {
198 rockchip,pins = <RK_GPIO3 0 RK_FUNC_1 &pcfg_pull_none>,
199 <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 };
109 202
110 interrupt-controller; 203 i2c3 {
111 #interrupt-cells = <2>; 204 i2c3_xfer: i2c3-xfer {
205 rockchip,pins = <RK_GPIO3 2 RK_FUNC_2 &pcfg_pull_none>,
206 <RK_GPIO3 3 RK_FUNC_2 &pcfg_pull_none>;
112 }; 207 };
208 };
113 209
114 gpio2: gpio2@2003e000 { 210 i2c4 {
115 compatible = "rockchip,gpio-bank"; 211 i2c4_xfer: i2c4-xfer {
116 reg = <0x2003e000 0x100>; 212 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
117 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 213 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>;
118 clocks = <&clk_gates8 11>; 214 };
215 };
119 216
120 gpio-controller; 217 pwm0 {
121 #gpio-cells = <2>; 218 pwm0_out: pwm0-out {
219 rockchip,pins = <RK_GPIO0 3 RK_FUNC_1 &pcfg_pull_none>;
220 };
221 };
122 222
123 interrupt-controller; 223 pwm1 {
124 #interrupt-cells = <2>; 224 pwm1_out: pwm1-out {
225 rockchip,pins = <RK_GPIO0 4 RK_FUNC_1 &pcfg_pull_none>;
125 }; 226 };
227 };
126 228
127 gpio3: gpio3@20080000 { 229 pwm2 {
128 compatible = "rockchip,gpio-bank"; 230 pwm2_out: pwm2-out {
129 reg = <0x20080000 0x100>; 231 rockchip,pins = <RK_GPIO0 30 RK_FUNC_1 &pcfg_pull_none>;
130 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 232 };
131 clocks = <&clk_gates8 12>; 233 };
132 234
133 gpio-controller; 235 pwm3 {
134 #gpio-cells = <2>; 236 pwm3_out: pwm3-out {
237 rockchip,pins = <RK_GPIO0 31 RK_FUNC_1 &pcfg_pull_none>;
238 };
239 };
135 240
136 interrupt-controller; 241 uart0 {
137 #interrupt-cells = <2>; 242 uart0_xfer: uart0-xfer {
243 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
244 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
138 }; 245 };
139 246
140 gpio4: gpio4@20084000 { 247 uart0_cts: uart0-cts {
141 compatible = "rockchip,gpio-bank"; 248 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
142 reg = <0x20084000 0x100>; 249 };
143 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
144 clocks = <&clk_gates8 13>;
145 250
146 gpio-controller; 251 uart0_rts: uart0-rts {
147 #gpio-cells = <2>; 252 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
253 };
254 };
255
256 uart1 {
257 uart1_xfer: uart1-xfer {
258 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
259 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
260 };
148 261
149 interrupt-controller; 262 uart1_cts: uart1-cts {
150 #interrupt-cells = <2>; 263 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
151 }; 264 };
152 265
153 gpio6: gpio6@2000a000 { 266 uart1_rts: uart1-rts {
154 compatible = "rockchip,gpio-bank"; 267 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
155 reg = <0x2000a000 0x100>; 268 };
156 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 269 };
157 clocks = <&clk_gates8 15>;
158 270
159 gpio-controller; 271 uart2 {
160 #gpio-cells = <2>; 272 uart2_xfer: uart2-xfer {
273 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
274 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
275 };
276 /* no rts / cts for uart2 */
277 };
161 278
162 interrupt-controller; 279 uart3 {
163 #interrupt-cells = <2>; 280 uart3_xfer: uart3-xfer {
281 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
282 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
164 }; 283 };
165 284
166 pcfg_pull_default: pcfg_pull_default { 285 uart3_cts: uart3-cts {
167 bias-pull-pin-default; 286 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
168 }; 287 };
169 288
170 pcfg_pull_none: pcfg_pull_none { 289 uart3_rts: uart3-rts {
171 bias-disable; 290 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
172 }; 291 };
292 };
173 293
174 uart0 { 294 sd0 {
175 uart0_xfer: uart0-xfer { 295 sd0_clk: sd0-clk {
176 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>, 296 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
177 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>; 297 };
178 };
179 298
180 uart0_cts: uart0-cts { 299 sd0_cmd: sd0-cmd {
181 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>; 300 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
182 }; 301 };
183 302
184 uart0_rts: uart0-rts { 303 sd0_cd: sd0-cd {
185 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>; 304 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
186 };
187 }; 305 };
188 306
189 uart1 { 307 sd0_wp: sd0-wp {
190 uart1_xfer: uart1-xfer { 308 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
191 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>, 309 };
192 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
193 };
194 310
195 uart1_cts: uart1-cts { 311 sd0_bus1: sd0-bus-width1 {
196 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>; 312 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
197 }; 313 };
198 314
199 uart1_rts: uart1-rts { 315 sd0_bus4: sd0-bus-width4 {
200 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>; 316 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
201 }; 317 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
318 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
319 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
202 }; 320 };
321 };
203 322
204 uart2 { 323 sd1 {
205 uart2_xfer: uart2-xfer { 324 sd1_clk: sd1-clk {
206 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>, 325 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
207 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
208 };
209 /* no rts / cts for uart2 */
210 }; 326 };
211 327
212 uart3 { 328 sd1_cmd: sd1-cmd {
213 uart3_xfer: uart3-xfer { 329 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
214 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>, 330 };
215 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
216 };
217 331
218 uart3_cts: uart3-cts { 332 sd1_cd: sd1-cd {
219 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>; 333 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
220 }; 334 };
221 335
222 uart3_rts: uart3-rts { 336 sd1_wp: sd1-wp {
223 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>; 337 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
224 };
225 }; 338 };
226 339
227 sd0 { 340 sd1_bus1: sd1-bus-width1 {
228 sd0_clk: sd0-clk { 341 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
229 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
230 };
231
232 sd0_cmd: sd0-cmd {
233 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
234 };
235
236 sd0_cd: sd0-cd {
237 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
238 };
239
240 sd0_wp: sd0-wp {
241 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
242 };
243
244 sd0_bus1: sd0-bus-width1 {
245 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
246 };
247
248 sd0_bus4: sd0-bus-width4 {
249 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
250 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
251 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
252 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
253 };
254 }; 342 };
255 343
256 sd1 { 344 sd1_bus4: sd1-bus-width4 {
257 sd1_clk: sd1-clk { 345 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
258 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>; 346 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
259 }; 347 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
260 348 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
261 sd1_cmd: sd1-cmd {
262 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
263 };
264
265 sd1_cd: sd1-cd {
266 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
267 };
268
269 sd1_wp: sd1-wp {
270 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
271 };
272
273 sd1_bus1: sd1-bus-width1 {
274 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
275 };
276
277 sd1_bus4: sd1-bus-width4 {
278 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
279 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
280 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
281 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
282 };
283 }; 349 };
284 }; 350 };
285 }; 351 };
286}; 352};
353
354&i2c0 {
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c0_xfer>;
357};
358
359&i2c1 {
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c1_xfer>;
362};
363
364&i2c2 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&i2c2_xfer>;
367};
368
369&i2c3 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c3_xfer>;
372};
373
374&i2c4 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&i2c4_xfer>;
377};
378
379&mmc0 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_bus4>;
382};
383
384&mmc1 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_bus4>;
387};
388
389&pwm0 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pwm0_out>;
392};
393
394&pwm1 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&pwm1_out>;
397};
398
399&pwm2 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&pwm2_out>;
402};
403
404&pwm3 {
405 pinctrl-names = "default";
406 pinctrl-0 = <&pwm3_out>;
407};
408
409&uart0 {
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart0_xfer>;
412};
413
414&uart1 {
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart1_xfer>;
417};
418
419&uart2 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart2_xfer>;
422};
423
424&uart3 {
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart3_xfer>;
427};
428
429&wdt {
430 compatible = "rockchip,rk3066-wdt", "snps,dw-wdt";
431};
diff --git a/arch/arm/boot/dts/rk3188-clocks.dtsi b/arch/arm/boot/dts/rk3188-clocks.dtsi
deleted file mode 100644
index b1b92dc245ce..000000000000
--- a/arch/arm/boot/dts/rk3188-clocks.dtsi
+++ /dev/null
@@ -1,289 +0,0 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy150m>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_aclk_core",
69 "reserved", "gate_i2s0",
70 "gate_i2s0_frac", "reserved",
71 "reserved", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer3", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "reserved";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&xin24m>, <&xin24m>,
133 <&dummy>, <&dummy>,
134 <&xin24m>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&xin24m>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_timer2", "gate_timer4",
143 "gate_hsicphy", "gate_cif0_out",
144 "gate_timer5", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "reserved",
147 "gate_timer6", "gate_aclk_gpu_src";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&dummy>,
161 <&clk_gates0 3>, <&dummy>,
162 <&dummy>, <&dummy>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "reserved",
171 "gate_aclk_intmem", "reserved",
172 "gate_hclk_imem1", "gate_hclk_imem0";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>;
187
188 clock-output-names =
189 "gate_aclk_dmac1", "gate_aclk_dmac2",
190 "gate_pclk_efuse", "gate_pclk_tzpc",
191 "gate_pclk_grf", "gate_pclk_pmu",
192 "gate_hclk_rom", "gate_pclk_ddrupctl",
193 "gate_aclk_smc", "gate_hclk_nandc",
194 "gate_hclk_mmc0", "gate_hclk_mmc1",
195 "gate_hclk_emmc", "gate_hclk_otg0";
196
197 #clock-cells = <1>;
198 };
199
200 clk_gates6: gate-clk@200000e8 {
201 compatible = "rockchip,rk2928-gate-clk";
202 reg = <0x200000e8 0x4>;
203 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
204 <&clk_gates0 4>, <&clk_gates1 4>,
205 <&clk_gates0 4>, <&clk_gates3 0>,
206 <&dummy>, <&dummy>,
207 <&clk_gates3 0>, <&clk_gates0 4>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates0 4>, <&clk_gates3 0>;
210
211 clock-output-names =
212 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
213 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
214 "gate_hclk_cif0", "gate_aclk_cif0",
215 "reserved", "reserved",
216 "gate_aclk_ipp", "gate_hclk_ipp",
217 "gate_hclk_rga", "gate_aclk_rga",
218 "gate_hclk_vio_bus", "gate_aclk_vio0";
219
220 #clock-cells = <1>;
221 };
222
223 clk_gates7: gate-clk@200000ec {
224 compatible = "rockchip,rk2928-gate-clk";
225 reg = <0x200000ec 0x4>;
226 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
227 <&clk_gates0 4>, <&dummy>,
228 <&dummy>, <&clk_gates2 2>,
229 <&clk_gates2 2>, <&clk_gates0 5>,
230 <&dummy>, <&clk_gates0 5>,
231 <&clk_gates0 5>, <&clk_gates2 3>,
232 <&clk_gates2 3>, <&clk_gates2 3>,
233 <&clk_gates2 3>, <&clk_gates2 3>;
234
235 clock-output-names =
236 "gate_hclk_emac", "gate_hclk_spdif",
237 "gate_hclk_i2s0_2ch", "gate_hclk_otg1",
238 "gate_hclk_hsic", "gate_hclk_hsadc",
239 "gate_hclk_pidf", "gate_pclk_timer0",
240 "reserved", "gate_pclk_timer2",
241 "gate_pclk_pwm01", "gate_pclk_pwm23",
242 "gate_pclk_spi0", "gate_pclk_spi1",
243 "gate_pclk_saradc", "gate_pclk_wdt";
244
245 #clock-cells = <1>;
246 };
247
248 clk_gates8: gate-clk@200000f0 {
249 compatible = "rockchip,rk2928-gate-clk";
250 reg = <0x200000f0 0x4>;
251 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
252 <&clk_gates2 3>, <&clk_gates2 3>,
253 <&clk_gates0 5>, <&clk_gates0 5>,
254 <&clk_gates2 3>, <&clk_gates2 3>,
255 <&clk_gates2 3>, <&clk_gates0 5>,
256 <&clk_gates0 5>, <&clk_gates0 5>,
257 <&clk_gates2 3>, <&dummy>;
258
259 clock-output-names =
260 "gate_pclk_uart0", "gate_pclk_uart1",
261 "gate_pclk_uart2", "gate_pclk_uart3",
262 "gate_pclk_i2c0", "gate_pclk_i2c1",
263 "gate_pclk_i2c2", "gate_pclk_i2c3",
264 "gate_pclk_i2c4", "gate_pclk_gpio0",
265 "gate_pclk_gpio1", "gate_pclk_gpio2",
266 "gate_pclk_gpio3", "gate_aclk_gps";
267
268 #clock-cells = <1>;
269 };
270
271 clk_gates9: gate-clk@200000f4 {
272 compatible = "rockchip,rk2928-gate-clk";
273 reg = <0x200000f4 0x4>;
274 clocks = <&dummy>, <&dummy>,
275 <&dummy>, <&dummy>,
276 <&dummy>, <&dummy>,
277 <&dummy>, <&dummy>;
278
279 clock-output-names =
280 "gate_clk_core_dbg", "gate_pclk_dbg",
281 "gate_clk_trace", "gate_atclk",
282 "gate_clk_l2c", "gate_aclk_vio1",
283 "gate_pclk_publ", "gate_aclk_gpu";
284
285 #clock-cells = <1>;
286 };
287 };
288
289};
diff --git a/arch/arm/boot/dts/rk3188-radxarock.dts b/arch/arm/boot/dts/rk3188-radxarock.dts
index a5eee55079cb..171b610db709 100644
--- a/arch/arm/boot/dts/rk3188-radxarock.dts
+++ b/arch/arm/boot/dts/rk3188-radxarock.dts
@@ -23,59 +23,205 @@
23 reg = <0x60000000 0x80000000>; 23 reg = <0x60000000 0x80000000>;
24 }; 24 };
25 25
26 soc { 26 gpio-keys {
27 uart0: serial@10124000 { 27 compatible = "gpio-keys";
28 status = "okay"; 28 #address-cells = <1>;
29 #size-cells = <0>;
30 autorepeat;
31
32 button@0 {
33 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
34 linux,code = <116>;
35 label = "GPIO Key Power";
36 linux,input-type = <1>;
37 gpio-key,wakeup = <1>;
38 debounce-interval = <100>;
29 }; 39 };
40 };
30 41
31 uart1: serial@10126000 { 42 gpio-leds {
32 status = "okay"; 43 compatible = "gpio-leds";
44
45 green {
46 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
47 default-state = "off";
33 }; 48 };
34 49
35 uart2: serial@20064000 { 50 yellow {
36 pinctrl-names = "default"; 51 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
37 pinctrl-0 = <&uart2_xfer>; 52 default-state = "off";
38 status = "okay";
39 }; 53 };
40 54
41 uart3: serial@20068000 { 55 sleep {
42 status = "okay"; 56 gpios = <&gpio0 15 0>;
57 default-state = "off";
43 }; 58 };
59 };
44 60
45 gpio-keys { 61 ir_recv: gpio-ir-receiver {
46 compatible = "gpio-keys"; 62 compatible = "gpio-ir-receiver";
47 #address-cells = <1>; 63 gpios = <&gpio0 10 1>;
48 #size-cells = <0>; 64 pinctrl-names = "default";
49 autorepeat; 65 pinctrl-0 = <&ir_recv_pin>;
50 66 };
51 button@0 { 67
52 gpios = <&gpio0 4 GPIO_ACTIVE_LOW>; 68 vcc_sd0: sdmmc-regulator {
53 linux,code = <116>; 69 compatible = "regulator-fixed";
54 label = "GPIO Key Power"; 70 regulator-name = "sdmmc-supply";
55 linux,input-type = <1>; 71 regulator-min-microvolt = <3300000>;
56 gpio-key,wakeup = <1>; 72 regulator-max-microvolt = <3300000>;
57 debounce-interval = <100>; 73 gpio = <&gpio3 1 GPIO_ACTIVE_LOW>;
74 startup-delay-us = <100000>;
75 vin-supply = <&vcc_io>;
76 };
77};
78
79&i2c1 {
80 status = "okay";
81 clock-frequency = <400000>;
82
83 act8846: act8846@5a {
84 compatible = "active-semi,act8846";
85 reg = <0x5a>;
86 status = "okay";
87
88 pinctrl-names = "default";
89 pinctrl-0 = <&act8846_dvs0_ctl>;
90
91 regulators {
92 vcc_ddr: REG1 {
93 regulator-name = "VCC_DDR";
94 regulator-min-microvolt = <1200000>;
95 regulator-max-microvolt = <1200000>;
96 regulator-always-on;
97 };
98
99 vdd_log: REG2 {
100 regulator-name = "VDD_LOG";
101 regulator-min-microvolt = <1000000>;
102 regulator-max-microvolt = <1000000>;
103 regulator-always-on;
104 };
105
106 vdd_arm: REG3 {
107 regulator-name = "VDD_ARM";
108 regulator-min-microvolt = <875000>;
109 regulator-max-microvolt = <1300000>;
110 regulator-always-on;
111 };
112
113 vcc_io: REG4 {
114 regulator-name = "VCC_IO";
115 regulator-min-microvolt = <3300000>;
116 regulator-max-microvolt = <3300000>;
117 regulator-always-on;
118 };
119
120 vdd_10: REG5 {
121 regulator-name = "VDD_10";
122 regulator-min-microvolt = <1000000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-always-on;
125 };
126
127 vdd_hdmi: REG6 {
128 regulator-name = "VDD_HDMI";
129 regulator-min-microvolt = <2500000>;
130 regulator-max-microvolt = <2500000>;
131 regulator-always-on;
132 };
133
134 vcc18: REG7 {
135 regulator-name = "VCC_18";
136 regulator-min-microvolt = <1800000>;
137 regulator-max-microvolt = <1800000>;
138 regulator-always-on;
58 }; 139 };
59 };
60 140
61 gpio-leds { 141 vcca_33: REG8 {
62 compatible = "gpio-leds"; 142 regulator-name = "VCCA_33";
143 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <3300000>;
145 regulator-always-on;
146 };
147
148 vcc_rmii: REG9 {
149 regulator-name = "VCC_RMII";
150 regulator-min-microvolt = <3300000>;
151 regulator-max-microvolt = <3300000>;
152 regulator-always-on;
153 };
63 154
64 green { 155 vccio_wl: REG10 {
65 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; 156 regulator-name = "VCCIO_WL";
66 default-state = "off"; 157 regulator-min-microvolt = <3300000>;
158 regulator-max-microvolt = <3300000>;
159 regulator-always-on;
67 }; 160 };
68 161
69 yellow { 162 vcc_18: REG11 {
70 gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; 163 regulator-name = "VCC18_IO";
71 default-state = "off"; 164 regulator-min-microvolt = <1800000>;
165 regulator-max-microvolt = <1800000>;
166 regulator-always-on;
72 }; 167 };
73 168
74 sleep { 169 vcc28: REG12 {
75 gpios = <&gpio0 15 0>; 170 regulator-name = "VCC_28";
76 default-state = "off"; 171 regulator-min-microvolt = <2800000>;
172 regulator-max-microvolt = <2800000>;
173 regulator-always-on;
77 }; 174 };
78 }; 175 };
176 };
177};
178
179&mmc0 {
180 num-slots = <1>;
181 status = "okay";
182 vmmc-supply = <&vcc_sd0>;
79 183
184 slot@0 {
185 reg = <0>;
186 bus-width = <4>;
187 disable-wp;
80 }; 188 };
81}; 189};
190
191&pinctrl {
192 pcfg_output_low: pcfg-output-low {
193 output-low;
194 };
195
196 act8846 {
197 act8846_dvs0_ctl: act8846-dvs0-ctl {
198 rockchip,pins = <RK_GPIO3 27 RK_FUNC_GPIO &pcfg_output_low>;
199 };
200 };
201
202 ir-receiver {
203 ir_recv_pin: ir-recv-pin {
204 rockchip,pins = <RK_GPIO0 10 RK_FUNC_GPIO &pcfg_pull_none>;
205 };
206 };
207};
208
209&uart0 {
210 status = "okay";
211};
212
213&uart1 {
214 status = "okay";
215};
216
217&uart2 {
218 status = "okay";
219};
220
221&uart3 {
222 status = "okay";
223};
224
225&wdt {
226 status = "okay";
227};
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 238c996d4a7f..ee801a9c6b74 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -15,8 +15,8 @@
15 15
16#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/rockchip.h> 17#include <dt-bindings/pinctrl/rockchip.h>
18#include <dt-bindings/clock/rk3188-cru.h>
18#include "rk3xxx.dtsi" 19#include "rk3xxx.dtsi"
19#include "rk3188-clocks.dtsi"
20 20
21/ { 21/ {
22 compatible = "rockchip,rk3188"; 22 compatible = "rockchip,rk3188";
@@ -52,215 +52,355 @@
52 }; 52 };
53 }; 53 };
54 54
55 soc { 55 sram: sram@10080000 {
56 global-timer@1013c200 { 56 compatible = "mmio-sram";
57 interrupts = <GIC_PPI 11 0xf04>; 57 reg = <0x10080000 0x8000>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges = <0 0x10080000 0x8000>;
61
62 smp-sram@0 {
63 compatible = "rockchip,rk3066-smp-sram";
64 reg = <0x0 0x50>;
58 }; 65 };
66 };
67
68 cru: clock-controller@20000000 {
69 compatible = "rockchip,rk3188-cru";
70 reg = <0x20000000 0x1000>;
71 rockchip,grf = <&grf>;
72
73 #clock-cells = <1>;
74 #reset-cells = <1>;
75 };
76
77 pinctrl: pinctrl {
78 compatible = "rockchip,rk3188-pinctrl";
79 rockchip,grf = <&grf>;
80 rockchip,pmu = <&pmu>;
81
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 gpio0: gpio0@0x2000a000 {
87 compatible = "rockchip,rk3188-gpio-bank0";
88 reg = <0x2000a000 0x100>;
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru PCLK_GPIO0>;
91
92 gpio-controller;
93 #gpio-cells = <2>;
59 94
60 local-timer@1013c600 { 95 interrupt-controller;
61 interrupts = <GIC_PPI 13 0xf04>; 96 #interrupt-cells = <2>;
62 }; 97 };
63 98
64 sram: sram@10080000 { 99 gpio1: gpio1@0x2003c000 {
65 compatible = "mmio-sram"; 100 compatible = "rockchip,gpio-bank";
66 reg = <0x10080000 0x8000>; 101 reg = <0x2003c000 0x100>;
67 #address-cells = <1>; 102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
68 #size-cells = <1>; 103 clocks = <&cru PCLK_GPIO1>;
69 ranges = <0 0x10080000 0x8000>;
70 104
71 smp-sram@0 { 105 gpio-controller;
72 compatible = "rockchip,rk3066-smp-sram"; 106 #gpio-cells = <2>;
73 reg = <0x0 0x50>; 107
74 }; 108 interrupt-controller;
109 #interrupt-cells = <2>;
75 }; 110 };
76 111
77 pinctrl@20008000 { 112 gpio2: gpio2@2003e000 {
78 compatible = "rockchip,rk3188-pinctrl"; 113 compatible = "rockchip,gpio-bank";
79 rockchip,grf = <&grf>; 114 reg = <0x2003e000 0x100>;
80 rockchip,pmu = <&pmu>; 115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
116 clocks = <&cru PCLK_GPIO2>;
81 117
82 #address-cells = <1>; 118 gpio-controller;
83 #size-cells = <1>; 119 #gpio-cells = <2>;
84 ranges;
85 120
86 gpio0: gpio0@0x2000a000 { 121 interrupt-controller;
87 compatible = "rockchip,rk3188-gpio-bank0"; 122 #interrupt-cells = <2>;
88 reg = <0x2000a000 0x100>; 123 };
89 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&clk_gates8 9>;
91 124
92 gpio-controller; 125 gpio3: gpio3@20080000 {
93 #gpio-cells = <2>; 126 compatible = "rockchip,gpio-bank";
127 reg = <0x20080000 0x100>;
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
129 clocks = <&cru PCLK_GPIO3>;
94 130
95 interrupt-controller; 131 gpio-controller;
96 #interrupt-cells = <2>; 132 #gpio-cells = <2>;
97 };
98 133
99 gpio1: gpio1@0x2003c000 { 134 interrupt-controller;
100 compatible = "rockchip,gpio-bank"; 135 #interrupt-cells = <2>;
101 reg = <0x2003c000 0x100>; 136 };
102 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&clk_gates8 10>;
104 137
105 gpio-controller; 138 pcfg_pull_up: pcfg_pull_up {
106 #gpio-cells = <2>; 139 bias-pull-up;
140 };
107 141
108 interrupt-controller; 142 pcfg_pull_down: pcfg_pull_down {
109 #interrupt-cells = <2>; 143 bias-pull-down;
110 }; 144 };
111 145
112 gpio2: gpio2@2003e000 { 146 pcfg_pull_none: pcfg_pull_none {
113 compatible = "rockchip,gpio-bank"; 147 bias-disable;
114 reg = <0x2003e000 0x100>; 148 };
115 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 149
116 clocks = <&clk_gates8 11>; 150 i2c0 {
151 i2c0_xfer: i2c0-xfer {
152 rockchip,pins = <RK_GPIO1 24 RK_FUNC_1 &pcfg_pull_none>,
153 <RK_GPIO1 25 RK_FUNC_1 &pcfg_pull_none>;
154 };
155 };
117 156
118 gpio-controller; 157 i2c1 {
119 #gpio-cells = <2>; 158 i2c1_xfer: i2c1-xfer {
159 rockchip,pins = <RK_GPIO1 26 RK_FUNC_1 &pcfg_pull_none>,
160 <RK_GPIO1 27 RK_FUNC_1 &pcfg_pull_none>;
161 };
162 };
120 163
121 interrupt-controller; 164 i2c2 {
122 #interrupt-cells = <2>; 165 i2c2_xfer: i2c2-xfer {
166 rockchip,pins = <RK_GPIO1 28 RK_FUNC_1 &pcfg_pull_none>,
167 <RK_GPIO1 29 RK_FUNC_1 &pcfg_pull_none>;
123 }; 168 };
169 };
124 170
125 gpio3: gpio3@20080000 { 171 i2c3 {
126 compatible = "rockchip,gpio-bank"; 172 i2c3_xfer: i2c3-xfer {
127 reg = <0x20080000 0x100>; 173 rockchip,pins = <RK_GPIO3 14 RK_FUNC_2 &pcfg_pull_none>,
128 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 174 <RK_GPIO3 15 RK_FUNC_2 &pcfg_pull_none>;
129 clocks = <&clk_gates8 12>; 175 };
176 };
130 177
131 gpio-controller; 178 i2c4 {
132 #gpio-cells = <2>; 179 i2c4_xfer: i2c4-xfer {
180 rockchip,pins = <RK_GPIO1 30 RK_FUNC_1 &pcfg_pull_none>,
181 <RK_GPIO1 31 RK_FUNC_1 &pcfg_pull_none>;
182 };
183 };
133 184
134 interrupt-controller; 185 pwm0 {
135 #interrupt-cells = <2>; 186 pwm0_out: pwm0-out {
187 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;
136 }; 188 };
189 };
137 190
138 pcfg_pull_up: pcfg_pull_up { 191 pwm1 {
139 bias-pull-up; 192 pwm1_out: pwm1-out {
193 rockchip,pins = <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_none>;
140 }; 194 };
195 };
141 196
142 pcfg_pull_down: pcfg_pull_down { 197 pwm2 {
143 bias-pull-down; 198 pwm2_out: pwm2-out {
199 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_none>;
144 }; 200 };
201 };
145 202
146 pcfg_pull_none: pcfg_pull_none { 203 pwm3 {
147 bias-disable; 204 pwm3_out: pwm3-out {
205 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_none>;
148 }; 206 };
207 };
149 208
150 uart0 { 209 uart0 {
151 uart0_xfer: uart0-xfer { 210 uart0_xfer: uart0-xfer {
152 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, 211 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>,
153 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; 212 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>;
154 }; 213 };
155 214
156 uart0_cts: uart0-cts { 215 uart0_cts: uart0-cts {
157 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; 216 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>;
158 }; 217 };
159 218
160 uart0_rts: uart0-rts { 219 uart0_rts: uart0-rts {
161 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; 220 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>;
162 };
163 }; 221 };
222 };
164 223
165 uart1 { 224 uart1 {
166 uart1_xfer: uart1-xfer { 225 uart1_xfer: uart1-xfer {
167 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, 226 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>,
168 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; 227 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>;
169 }; 228 };
170 229
171 uart1_cts: uart1-cts { 230 uart1_cts: uart1-cts {
172 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; 231 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>;
173 }; 232 };
174 233
175 uart1_rts: uart1-rts { 234 uart1_rts: uart1-rts {
176 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; 235 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>;
177 };
178 }; 236 };
237 };
179 238
180 uart2 { 239 uart2 {
181 uart2_xfer: uart2-xfer { 240 uart2_xfer: uart2-xfer {
182 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, 241 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>,
183 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; 242 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>;
184 };
185 /* no rts / cts for uart2 */
186 }; 243 };
244 /* no rts / cts for uart2 */
245 };
187 246
188 uart3 { 247 uart3 {
189 uart3_xfer: uart3-xfer { 248 uart3_xfer: uart3-xfer {
190 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, 249 rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>,
191 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; 250 <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>;
192 }; 251 };
193 252
194 uart3_cts: uart3-cts { 253 uart3_cts: uart3-cts {
195 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; 254 rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>;
196 }; 255 };
197 256
198 uart3_rts: uart3-rts { 257 uart3_rts: uart3-rts {
199 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; 258 rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>;
200 };
201 }; 259 };
260 };
202 261
203 sd0 { 262 sd0 {
204 sd0_clk: sd0-clk { 263 sd0_clk: sd0-clk {
205 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; 264 rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>;
206 }; 265 };
207 266
208 sd0_cmd: sd0-cmd { 267 sd0_cmd: sd0-cmd {
209 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; 268 rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>;
210 }; 269 };
211 270
212 sd0_cd: sd0-cd { 271 sd0_cd: sd0-cd {
213 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; 272 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>;
214 }; 273 };
215 274
216 sd0_wp: sd0-wp { 275 sd0_wp: sd0-wp {
217 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; 276 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>;
218 }; 277 };
219 278
220 sd0_pwr: sd0-pwr { 279 sd0_pwr: sd0-pwr {
221 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; 280 rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>;
222 }; 281 };
223 282
224 sd0_bus1: sd0-bus-width1 { 283 sd0_bus1: sd0-bus-width1 {
225 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; 284 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>;
226 }; 285 };
227 286
228 sd0_bus4: sd0-bus-width4 { 287 sd0_bus4: sd0-bus-width4 {
229 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, 288 rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>,
230 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, 289 <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>,
231 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, 290 <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>,
232 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; 291 <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>;
233 };
234 }; 292 };
293 };
235 294
236 sd1 { 295 sd1 {
237 sd1_clk: sd1-clk { 296 sd1_clk: sd1-clk {
238 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; 297 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>;
239 }; 298 };
240 299
241 sd1_cmd: sd1-cmd { 300 sd1_cmd: sd1-cmd {
242 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; 301 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>;
243 }; 302 };
244 303
245 sd1_cd: sd1-cd { 304 sd1_cd: sd1-cd {
246 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; 305 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>;
247 }; 306 };
248 307
249 sd1_wp: sd1-wp { 308 sd1_wp: sd1-wp {
250 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; 309 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>;
251 }; 310 };
252 311
253 sd1_bus1: sd1-bus-width1 { 312 sd1_bus1: sd1-bus-width1 {
254 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; 313 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>;
255 }; 314 };
256 315
257 sd1_bus4: sd1-bus-width4 { 316 sd1_bus4: sd1-bus-width4 {
258 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, 317 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>,
259 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, 318 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>,
260 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, 319 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>,
261 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; 320 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>;
262 };
263 }; 321 };
264 }; 322 };
265 }; 323 };
266}; 324};
325
326&global_timer {
327 interrupts = <GIC_PPI 11 0xf04>;
328};
329
330&local_timer {
331 interrupts = <GIC_PPI 13 0xf04>;
332};
333
334&i2c0 {
335 compatible = "rockchip,rk3188-i2c";
336 pinctrl-names = "default";
337 pinctrl-0 = <&i2c0_xfer>;
338};
339
340&i2c1 {
341 compatible = "rockchip,rk3188-i2c";
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c1_xfer>;
344};
345
346&i2c2 {
347 compatible = "rockchip,rk3188-i2c";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c2_xfer>;
350};
351
352&i2c3 {
353 compatible = "rockchip,rk3188-i2c";
354 pinctrl-names = "default";
355 pinctrl-0 = <&i2c3_xfer>;
356};
357
358&i2c4 {
359 compatible = "rockchip,rk3188-i2c";
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_xfer>;
362};
363
364&pwm0 {
365 pinctrl-names = "default";
366 pinctrl-0 = <&pwm0_out>;
367};
368
369&pwm1 {
370 pinctrl-names = "default";
371 pinctrl-0 = <&pwm1_out>;
372};
373
374&pwm2 {
375 pinctrl-names = "default";
376 pinctrl-0 = <&pwm2_out>;
377};
378
379&pwm3 {
380 pinctrl-names = "default";
381 pinctrl-0 = <&pwm3_out>;
382};
383
384&uart0 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>;
387};
388
389&uart1 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&uart1_xfer>;
392};
393
394&uart2 {
395 pinctrl-names = "default";
396 pinctrl-0 = <&uart2_xfer>;
397};
398
399&uart3 {
400 pinctrl-names = "default";
401 pinctrl-0 = <&uart3_xfer>;
402};
403
404&wdt {
405 compatible = "rockchip,rk3188-wdt", "snps,dw-wdt";
406};
diff --git a/arch/arm/boot/dts/rk3288-evb-act8846.dts b/arch/arm/boot/dts/rk3288-evb-act8846.dts
new file mode 100644
index 000000000000..7d59ff4de408
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb-act8846.dts
@@ -0,0 +1,134 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/dts-v1/;
14#include "rk3288-evb.dtsi"
15
16/ {
17 compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
18};
19
20&i2c0 {
21 hym8563@51 {
22 compatible = "haoyu,hym8563";
23 reg = <0x51>;
24
25 interrupt-parent = <&gpio0>;
26 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
27
28 pinctrl-names = "default";
29 pinctrl-0 = <&hym8563_int>;
30
31 #clock-cells = <0>;
32 clock-output-names = "xin32k";
33 };
34
35 act8846: act8846@5a {
36 compatible = "active-semi,act8846";
37 reg = <0x5a>;
38 status = "okay";
39
40 regulators {
41 vcc_ddr: REG1 {
42 regulator-name = "VCC_DDR";
43 regulator-min-microvolt = <1200000>;
44 regulator-max-microvolt = <1200000>;
45 regulator-always-on;
46 };
47
48 vcc_io: REG2 {
49 regulator-name = "VCC_IO";
50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <3300000>;
52 regulator-always-on;
53 };
54
55 vdd_log: REG3 {
56 regulator-name = "VDD_LOG";
57 regulator-min-microvolt = <1000000>;
58 regulator-max-microvolt = <1000000>;
59 regulator-always-on;
60 };
61
62 vcc_20: REG4 {
63 regulator-name = "VCC_20";
64 regulator-min-microvolt = <2000000>;
65 regulator-max-microvolt = <2000000>;
66 regulator-always-on;
67 };
68
69 vccio_sd: REG5 {
70 regulator-name = "VCCIO_SD";
71 regulator-min-microvolt = <3300000>;
72 regulator-max-microvolt = <3300000>;
73 regulator-always-on;
74 };
75
76 vdd10_lcd: REG6 {
77 regulator-name = "VDD10_LCD";
78 regulator-min-microvolt = <1000000>;
79 regulator-max-microvolt = <1000000>;
80 regulator-always-on;
81 };
82
83 vcca_codec: REG7 {
84 regulator-name = "VCCA_CODEC";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 regulator-always-on;
88 };
89
90 vcca_tp: REG8 {
91 regulator-name = "VCCA_TP";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
95 };
96
97 vccio_pmu: REG9 {
98 regulator-name = "VCCIO_PMU";
99 regulator-min-microvolt = <3300000>;
100 regulator-max-microvolt = <3300000>;
101 regulator-always-on;
102 };
103
104 vdd_10: REG10 {
105 regulator-name = "VDD_10";
106 regulator-min-microvolt = <1000000>;
107 regulator-max-microvolt = <1000000>;
108 regulator-always-on;
109 };
110
111 vcc_18: REG11 {
112 regulator-name = "VCC_18";
113 regulator-min-microvolt = <1800000>;
114 regulator-max-microvolt = <1800000>;
115 regulator-always-on;
116 };
117
118 vcc18_lcd: REG12 {
119 regulator-name = "VCC18_LCD";
120 regulator-min-microvolt = <1800000>;
121 regulator-max-microvolt = <1800000>;
122 regulator-always-on;
123 };
124 };
125 };
126};
127
128&pinctrl {
129 hym8563 {
130 hym8563_int: hym8563-int {
131 rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
132 };
133 };
134};
diff --git a/arch/arm/boot/dts/rk3288-evb-rk808.dts b/arch/arm/boot/dts/rk3288-evb-rk808.dts
new file mode 100644
index 000000000000..9a88b6c66396
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb-rk808.dts
@@ -0,0 +1,18 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13/dts-v1/;
14#include "rk3288-evb.dtsi"
15
16/ {
17 compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
18};
diff --git a/arch/arm/boot/dts/rk3288-evb.dtsi b/arch/arm/boot/dts/rk3288-evb.dtsi
new file mode 100644
index 000000000000..4f572093c8b4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288-evb.dtsi
@@ -0,0 +1,96 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "rk3288.dtsi"
14
15/ {
16 memory {
17 reg = <0x0 0x80000000>;
18 };
19
20 gpio-keys {
21 compatible = "gpio-keys";
22 #address-cells = <1>;
23 #size-cells = <0>;
24 autorepeat;
25
26 pinctrl-names = "default";
27 pinctrl-0 = <&pwrbtn>;
28
29 button@0 {
30 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
31 linux,code = <116>;
32 label = "GPIO Key Power";
33 linux,input-type = <1>;
34 gpio-key,wakeup = <1>;
35 debounce-interval = <100>;
36 };
37 };
38
39 /* This turns on USB vbus for both host0 (ehci) and host1 (dwc2) */
40 vcc_host: vcc-host-regulator {
41 compatible = "regulator-fixed";
42 enable-active-high;
43 gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&host_vbus_drv>;
46 regulator-name = "vcc_host";
47 regulator-always-on;
48 regulator-boot-on;
49 };
50};
51
52&i2c0 {
53 status = "okay";
54};
55
56&wdt {
57 status = "okay";
58};
59
60&uart0 {
61 status = "okay";
62};
63
64&uart1 {
65 status = "okay";
66};
67
68&uart2 {
69 status = "okay";
70};
71
72&uart3 {
73 status = "okay";
74};
75
76&uart4 {
77 status = "okay";
78};
79
80&pinctrl {
81 buttons {
82 pwrbtn: pwrbtn {
83 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;
84 };
85 };
86
87 usb {
88 host_vbus_drv: host-vbus-drv {
89 rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
90 };
91 };
92};
93
94&usb_host0_ehci {
95 status = "okay";
96};
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
new file mode 100644
index 000000000000..e7cb00873dd4
--- /dev/null
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -0,0 +1,595 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16#include <dt-bindings/pinctrl/rockchip.h>
17#include <dt-bindings/clock/rk3288-cru.h>
18#include "skeleton.dtsi"
19
20/ {
21 compatible = "rockchip,rk3288";
22
23 interrupt-parent = <&gic>;
24
25 aliases {
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 };
38
39 cpus {
40 #address-cells = <1>;
41 #size-cells = <0>;
42
43 cpu@500 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a12";
46 reg = <0x500>;
47 };
48 cpu@501 {
49 device_type = "cpu";
50 compatible = "arm,cortex-a12";
51 reg = <0x501>;
52 };
53 cpu@502 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a12";
56 reg = <0x502>;
57 };
58 cpu@503 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a12";
61 reg = <0x503>;
62 };
63 };
64
65 xin24m: oscillator {
66 compatible = "fixed-clock";
67 clock-frequency = <24000000>;
68 clock-output-names = "xin24m";
69 #clock-cells = <0>;
70 };
71
72 timer {
73 compatible = "arm,armv7-timer";
74 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
75 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
77 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
78 clock-frequency = <24000000>;
79 };
80
81 i2c1: i2c@ff140000 {
82 compatible = "rockchip,rk3288-i2c";
83 reg = <0xff140000 0x1000>;
84 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 clock-names = "i2c";
88 clocks = <&cru PCLK_I2C1>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&i2c1_xfer>;
91 status = "disabled";
92 };
93
94 i2c3: i2c@ff150000 {
95 compatible = "rockchip,rk3288-i2c";
96 reg = <0xff150000 0x1000>;
97 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
98 #address-cells = <1>;
99 #size-cells = <0>;
100 clock-names = "i2c";
101 clocks = <&cru PCLK_I2C3>;
102 pinctrl-names = "default";
103 pinctrl-0 = <&i2c3_xfer>;
104 status = "disabled";
105 };
106
107 i2c4: i2c@ff160000 {
108 compatible = "rockchip,rk3288-i2c";
109 reg = <0xff160000 0x1000>;
110 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113 clock-names = "i2c";
114 clocks = <&cru PCLK_I2C4>;
115 pinctrl-names = "default";
116 pinctrl-0 = <&i2c4_xfer>;
117 status = "disabled";
118 };
119
120 i2c5: i2c@ff170000 {
121 compatible = "rockchip,rk3288-i2c";
122 reg = <0xff170000 0x1000>;
123 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
124 #address-cells = <1>;
125 #size-cells = <0>;
126 clock-names = "i2c";
127 clocks = <&cru PCLK_I2C5>;
128 pinctrl-names = "default";
129 pinctrl-0 = <&i2c5_xfer>;
130 status = "disabled";
131 };
132
133 uart0: serial@ff180000 {
134 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
135 reg = <0xff180000 0x100>;
136 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
137 reg-shift = <2>;
138 reg-io-width = <4>;
139 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
140 clock-names = "baudclk", "apb_pclk";
141 pinctrl-names = "default";
142 pinctrl-0 = <&uart0_xfer>;
143 status = "disabled";
144 };
145
146 uart1: serial@ff190000 {
147 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
148 reg = <0xff190000 0x100>;
149 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
150 reg-shift = <2>;
151 reg-io-width = <4>;
152 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
153 clock-names = "baudclk", "apb_pclk";
154 pinctrl-names = "default";
155 pinctrl-0 = <&uart1_xfer>;
156 status = "disabled";
157 };
158
159 uart2: serial@ff690000 {
160 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
161 reg = <0xff690000 0x100>;
162 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
163 reg-shift = <2>;
164 reg-io-width = <4>;
165 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
166 clock-names = "baudclk", "apb_pclk";
167 pinctrl-names = "default";
168 pinctrl-0 = <&uart2_xfer>;
169 status = "disabled";
170 };
171
172 uart3: serial@ff1b0000 {
173 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
174 reg = <0xff1b0000 0x100>;
175 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
176 reg-shift = <2>;
177 reg-io-width = <4>;
178 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
179 clock-names = "baudclk", "apb_pclk";
180 pinctrl-names = "default";
181 pinctrl-0 = <&uart3_xfer>;
182 status = "disabled";
183 };
184
185 uart4: serial@ff1c0000 {
186 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
187 reg = <0xff1c0000 0x100>;
188 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
189 reg-shift = <2>;
190 reg-io-width = <4>;
191 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
192 clock-names = "baudclk", "apb_pclk";
193 pinctrl-names = "default";
194 pinctrl-0 = <&uart4_xfer>;
195 status = "disabled";
196 };
197
198 i2c0: i2c@ff650000 {
199 compatible = "rockchip,rk3288-i2c";
200 reg = <0xff650000 0x1000>;
201 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
202 #address-cells = <1>;
203 #size-cells = <0>;
204 clock-names = "i2c";
205 clocks = <&cru PCLK_I2C0>;
206 pinctrl-names = "default";
207 pinctrl-0 = <&i2c0_xfer>;
208 status = "disabled";
209 };
210
211 i2c2: i2c@ff660000 {
212 compatible = "rockchip,rk3288-i2c";
213 reg = <0xff660000 0x1000>;
214 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
215 #address-cells = <1>;
216 #size-cells = <0>;
217 clock-names = "i2c";
218 clocks = <&cru PCLK_I2C2>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c2_xfer>;
221 status = "disabled";
222 };
223
224 pmu: power-management@ff730000 {
225 compatible = "rockchip,rk3288-pmu", "syscon";
226 reg = <0xff730000 0x100>;
227 };
228
229 sgrf: syscon@ff740000 {
230 compatible = "rockchip,rk3288-sgrf", "syscon";
231 reg = <0xff740000 0x1000>;
232 };
233
234 cru: clock-controller@ff760000 {
235 compatible = "rockchip,rk3288-cru";
236 reg = <0xff760000 0x1000>;
237 rockchip,grf = <&grf>;
238 #clock-cells = <1>;
239 #reset-cells = <1>;
240 };
241
242 grf: syscon@ff770000 {
243 compatible = "rockchip,rk3288-grf", "syscon";
244 reg = <0xff770000 0x1000>;
245 };
246
247 wdt: watchdog@ff800000 {
248 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
249 reg = <0xff800000 0x100>;
250 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 usb_host0_ehci: usb@ff500000 {
255 compatible = "generic-ehci";
256 reg = <0xff500000 0x100>;
257 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
258 clocks = <&cru HCLK_USBHOST0>;
259 clock-names = "usbhost";
260 status = "disabled";
261 };
262
263 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
264
265 usb_hsic: usb@ff5c0000 {
266 compatible = "generic-ehci";
267 reg = <0xff5c0000 0x100>;
268 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&cru HCLK_HSIC>;
270 clock-names = "usbhost";
271 status = "disabled";
272 };
273
274 gic: interrupt-controller@ffc01000 {
275 compatible = "arm,gic-400";
276 interrupt-controller;
277 #interrupt-cells = <3>;
278 #address-cells = <0>;
279
280 reg = <0xffc01000 0x1000>,
281 <0xffc02000 0x1000>,
282 <0xffc04000 0x2000>,
283 <0xffc06000 0x2000>;
284 interrupts = <GIC_PPI 9 0xf04>;
285 };
286
287 pinctrl: pinctrl {
288 compatible = "rockchip,rk3288-pinctrl";
289 rockchip,grf = <&grf>;
290 rockchip,pmu = <&pmu>;
291 #address-cells = <1>;
292 #size-cells = <1>;
293 ranges;
294
295 gpio0: gpio0@ff750000 {
296 compatible = "rockchip,gpio-bank";
297 reg = <0xff750000 0x100>;
298 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cru PCLK_GPIO0>;
300
301 gpio-controller;
302 #gpio-cells = <2>;
303
304 interrupt-controller;
305 #interrupt-cells = <2>;
306 };
307
308 gpio1: gpio1@ff780000 {
309 compatible = "rockchip,gpio-bank";
310 reg = <0xff780000 0x100>;
311 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&cru PCLK_GPIO1>;
313
314 gpio-controller;
315 #gpio-cells = <2>;
316
317 interrupt-controller;
318 #interrupt-cells = <2>;
319 };
320
321 gpio2: gpio2@ff790000 {
322 compatible = "rockchip,gpio-bank";
323 reg = <0xff790000 0x100>;
324 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cru PCLK_GPIO2>;
326
327 gpio-controller;
328 #gpio-cells = <2>;
329
330 interrupt-controller;
331 #interrupt-cells = <2>;
332 };
333
334 gpio3: gpio3@ff7a0000 {
335 compatible = "rockchip,gpio-bank";
336 reg = <0xff7a0000 0x100>;
337 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
338 clocks = <&cru PCLK_GPIO3>;
339
340 gpio-controller;
341 #gpio-cells = <2>;
342
343 interrupt-controller;
344 #interrupt-cells = <2>;
345 };
346
347 gpio4: gpio4@ff7b0000 {
348 compatible = "rockchip,gpio-bank";
349 reg = <0xff7b0000 0x100>;
350 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&cru PCLK_GPIO4>;
352
353 gpio-controller;
354 #gpio-cells = <2>;
355
356 interrupt-controller;
357 #interrupt-cells = <2>;
358 };
359
360 gpio5: gpio5@ff7c0000 {
361 compatible = "rockchip,gpio-bank";
362 reg = <0xff7c0000 0x100>;
363 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&cru PCLK_GPIO5>;
365
366 gpio-controller;
367 #gpio-cells = <2>;
368
369 interrupt-controller;
370 #interrupt-cells = <2>;
371 };
372
373 gpio6: gpio6@ff7d0000 {
374 compatible = "rockchip,gpio-bank";
375 reg = <0xff7d0000 0x100>;
376 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&cru PCLK_GPIO6>;
378
379 gpio-controller;
380 #gpio-cells = <2>;
381
382 interrupt-controller;
383 #interrupt-cells = <2>;
384 };
385
386 gpio7: gpio7@ff7e0000 {
387 compatible = "rockchip,gpio-bank";
388 reg = <0xff7e0000 0x100>;
389 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cru PCLK_GPIO7>;
391
392 gpio-controller;
393 #gpio-cells = <2>;
394
395 interrupt-controller;
396 #interrupt-cells = <2>;
397 };
398
399 gpio8: gpio8@ff7f0000 {
400 compatible = "rockchip,gpio-bank";
401 reg = <0xff7f0000 0x100>;
402 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&cru PCLK_GPIO8>;
404
405 gpio-controller;
406 #gpio-cells = <2>;
407
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 pcfg_pull_up: pcfg-pull-up {
413 bias-pull-up;
414 };
415
416 pcfg_pull_down: pcfg-pull-down {
417 bias-pull-down;
418 };
419
420 pcfg_pull_none: pcfg-pull-none {
421 bias-disable;
422 };
423
424 i2c0 {
425 i2c0_xfer: i2c0-xfer {
426 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
427 <0 16 RK_FUNC_1 &pcfg_pull_none>;
428 };
429 };
430
431 i2c1 {
432 i2c1_xfer: i2c1-xfer {
433 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
434 <8 5 RK_FUNC_1 &pcfg_pull_none>;
435 };
436 };
437
438 i2c2 {
439 i2c2_xfer: i2c2-xfer {
440 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
441 <6 10 RK_FUNC_1 &pcfg_pull_none>;
442 };
443 };
444
445 i2c3 {
446 i2c3_xfer: i2c3-xfer {
447 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
448 <2 17 RK_FUNC_1 &pcfg_pull_none>;
449 };
450 };
451
452 i2c4 {
453 i2c4_xfer: i2c4-xfer {
454 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
455 <7 18 RK_FUNC_1 &pcfg_pull_none>;
456 };
457 };
458
459 i2c5 {
460 i2c5_xfer: i2c5-xfer {
461 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
462 <7 20 RK_FUNC_1 &pcfg_pull_none>;
463 };
464 };
465
466 sdmmc {
467 sdmmc_clk: sdmmc-clk {
468 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
469 };
470
471 sdmmc_cmd: sdmmc-cmd {
472 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
473 };
474
475 sdmmc_cd: sdmcc-cd {
476 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
477 };
478
479 sdmmc_bus1: sdmmc-bus1 {
480 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
481 };
482
483 sdmmc_bus4: sdmmc-bus4 {
484 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
485 <6 17 RK_FUNC_1 &pcfg_pull_up>,
486 <6 18 RK_FUNC_1 &pcfg_pull_up>,
487 <6 19 RK_FUNC_1 &pcfg_pull_up>;
488 };
489 };
490
491 emmc {
492 emmc_clk: emmc-clk {
493 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
494 };
495
496 emmc_cmd: emmc-cmd {
497 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
498 };
499
500 emmc_pwr: emmc-pwr {
501 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
502 };
503
504 emmc_bus1: emmc-bus1 {
505 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
506 };
507
508 emmc_bus4: emmc-bus4 {
509 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
510 <3 1 RK_FUNC_2 &pcfg_pull_up>,
511 <3 2 RK_FUNC_2 &pcfg_pull_up>,
512 <3 3 RK_FUNC_2 &pcfg_pull_up>;
513 };
514
515 emmc_bus8: emmc-bus8 {
516 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
517 <3 1 RK_FUNC_2 &pcfg_pull_up>,
518 <3 2 RK_FUNC_2 &pcfg_pull_up>,
519 <3 3 RK_FUNC_2 &pcfg_pull_up>,
520 <3 4 RK_FUNC_2 &pcfg_pull_up>,
521 <3 5 RK_FUNC_2 &pcfg_pull_up>,
522 <3 6 RK_FUNC_2 &pcfg_pull_up>,
523 <3 7 RK_FUNC_2 &pcfg_pull_up>;
524 };
525 };
526
527 uart0 {
528 uart0_xfer: uart0-xfer {
529 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
530 <4 17 RK_FUNC_1 &pcfg_pull_none>;
531 };
532
533 uart0_cts: uart0-cts {
534 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
535 };
536
537 uart0_rts: uart0-rts {
538 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
539 };
540 };
541
542 uart1 {
543 uart1_xfer: uart1-xfer {
544 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
545 <5 9 RK_FUNC_1 &pcfg_pull_none>;
546 };
547
548 uart1_cts: uart1-cts {
549 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
550 };
551
552 uart1_rts: uart1-rts {
553 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
554 };
555 };
556
557 uart2 {
558 uart2_xfer: uart2-xfer {
559 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
560 <7 23 RK_FUNC_1 &pcfg_pull_none>;
561 };
562 /* no rts / cts for uart2 */
563 };
564
565 uart3 {
566 uart3_xfer: uart3-xfer {
567 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
568 <7 8 RK_FUNC_1 &pcfg_pull_none>;
569 };
570
571 uart3_cts: uart3-cts {
572 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
573 };
574
575 uart3_rts: uart3-rts {
576 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
577 };
578 };
579
580 uart4 {
581 uart4_xfer: uart4-xfer {
582 rockchip,pins = <5 12 3 &pcfg_pull_up>,
583 <5 13 3 &pcfg_pull_none>;
584 };
585
586 uart4_cts: uart4-cts {
587 rockchip,pins = <5 14 3 &pcfg_pull_none>;
588 };
589
590 uart4_rts: uart4-rts {
591 rockchip,pins = <5 15 3 &pcfg_pull_none>;
592 };
593 };
594 };
595};
diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 2adf1cc9e85d..8caf85d83901 100644
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -20,120 +20,248 @@
20/ { 20/ {
21 interrupt-parent = <&gic>; 21 interrupt-parent = <&gic>;
22 22
23 soc { 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 };
30
31 xin24m: oscillator {
32 compatible = "fixed-clock";
33 clock-frequency = <24000000>;
34 #clock-cells = <0>;
35 clock-output-names = "xin24m";
36 };
37
38 L2: l2-cache-controller@10138000 {
39 compatible = "arm,pl310-cache";
40 reg = <0x10138000 0x1000>;
41 cache-unified;
42 cache-level = <2>;
43 };
44
45 scu@1013c000 {
46 compatible = "arm,cortex-a9-scu";
47 reg = <0x1013c000 0x100>;
48 };
49
50 global_timer: global-timer@1013c200 {
51 compatible = "arm,cortex-a9-global-timer";
52 reg = <0x1013c200 0x20>;
53 interrupts = <GIC_PPI 11 0x304>;
54 clocks = <&cru CORE_PERI>;
55 };
56
57 local_timer: local-timer@1013c600 {
58 compatible = "arm,cortex-a9-twd-timer";
59 reg = <0x1013c600 0x20>;
60 interrupts = <GIC_PPI 13 0x304>;
61 clocks = <&cru CORE_PERI>;
62 };
63
64 gic: interrupt-controller@1013d000 {
65 compatible = "arm,cortex-a9-gic";
66 interrupt-controller;
67 #interrupt-cells = <3>;
68 reg = <0x1013d000 0x1000>,
69 <0x1013c100 0x0100>;
70 };
71
72 uart0: serial@10124000 {
73 compatible = "snps,dw-apb-uart";
74 reg = <0x10124000 0x400>;
75 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
76 reg-shift = <2>;
77 reg-io-width = <1>;
78 clock-names = "baudclk", "apb_pclk";
79 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
80 status = "disabled";
81 };
82
83 uart1: serial@10126000 {
84 compatible = "snps,dw-apb-uart";
85 reg = <0x10126000 0x400>;
86 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
87 reg-shift = <2>;
88 reg-io-width = <1>;
89 clock-names = "baudclk", "apb_pclk";
90 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
91 status = "disabled";
92 };
93
94 mmc0: dwmmc@10214000 {
95 compatible = "rockchip,rk2928-dw-mshc";
96 reg = <0x10214000 0x1000>;
97 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
24 #address-cells = <1>; 98 #address-cells = <1>;
25 #size-cells = <1>; 99 #size-cells = <0>;
26 compatible = "simple-bus"; 100
27 ranges; 101 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
28 102 clock-names = "biu", "ciu";
29 scu@1013c000 { 103
30 compatible = "arm,cortex-a9-scu"; 104 status = "disabled";
31 reg = <0x1013c000 0x100>; 105 };
32 }; 106
33 107 mmc1: dwmmc@10218000 {
34 pmu: pmu@20004000 { 108 compatible = "rockchip,rk2928-dw-mshc";
35 compatible = "rockchip,rk3066-pmu", "syscon"; 109 reg = <0x10218000 0x1000>;
36 reg = <0x20004000 0x100>; 110 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
37 }; 111 #address-cells = <1>;
38 112 #size-cells = <0>;
39 grf: grf@20008000 { 113
40 compatible = "syscon"; 114 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
41 reg = <0x20008000 0x200>; 115 clock-names = "biu", "ciu";
42 }; 116
43 117 status = "disabled";
44 gic: interrupt-controller@1013d000 { 118 };
45 compatible = "arm,cortex-a9-gic"; 119
46 interrupt-controller; 120 pmu: pmu@20004000 {
47 #interrupt-cells = <3>; 121 compatible = "rockchip,rk3066-pmu", "syscon";
48 reg = <0x1013d000 0x1000>, 122 reg = <0x20004000 0x100>;
49 <0x1013c100 0x0100>; 123 };
50 }; 124
51 125 grf: grf@20008000 {
52 L2: l2-cache-controller@10138000 { 126 compatible = "syscon";
53 compatible = "arm,pl310-cache"; 127 reg = <0x20008000 0x200>;
54 reg = <0x10138000 0x1000>; 128 };
55 cache-unified; 129
56 cache-level = <2>; 130 i2c0: i2c@2002d000 {
57 }; 131 compatible = "rockchip,rk3066-i2c";
58 132 reg = <0x2002d000 0x1000>;
59 global-timer@1013c200 { 133 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
60 compatible = "arm,cortex-a9-global-timer"; 134 #address-cells = <1>;
61 reg = <0x1013c200 0x20>; 135 #size-cells = <0>;
62 interrupts = <GIC_PPI 11 0x304>; 136
63 clocks = <&dummy150m>; 137 rockchip,grf = <&grf>;
64 }; 138 rockchip,bus-index = <0>;
65 139
66 local-timer@1013c600 { 140 clock-names = "i2c";
67 compatible = "arm,cortex-a9-twd-timer"; 141 clocks = <&cru PCLK_I2C0>;
68 reg = <0x1013c600 0x20>; 142
69 interrupts = <GIC_PPI 13 0x304>; 143 status = "disabled";
70 clocks = <&dummy150m>; 144 };
71 }; 145
72 146 i2c1: i2c@2002f000 {
73 uart0: serial@10124000 { 147 compatible = "rockchip,rk3066-i2c";
74 compatible = "snps,dw-apb-uart"; 148 reg = <0x2002f000 0x1000>;
75 reg = <0x10124000 0x400>; 149 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
76 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <1>;
77 reg-shift = <2>; 151 #size-cells = <0>;
78 reg-io-width = <1>; 152
79 clocks = <&clk_gates1 8>; 153 rockchip,grf = <&grf>;
80 status = "disabled"; 154
81 }; 155 clocks = <&cru PCLK_I2C1>;
82 156 clock-names = "i2c";
83 uart1: serial@10126000 { 157
84 compatible = "snps,dw-apb-uart"; 158 status = "disabled";
85 reg = <0x10126000 0x400>; 159 };
86 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 160
87 reg-shift = <2>; 161 pwm0: pwm@20030000 {
88 reg-io-width = <1>; 162 compatible = "rockchip,rk2928-pwm";
89 clocks = <&clk_gates1 10>; 163 reg = <0x20030000 0x10>;
90 status = "disabled"; 164 #pwm-cells = <2>;
91 }; 165 clocks = <&cru PCLK_PWM01>;
92 166 status = "disabled";
93 uart2: serial@20064000 { 167 };
94 compatible = "snps,dw-apb-uart"; 168
95 reg = <0x20064000 0x400>; 169 pwm1: pwm@20030010 {
96 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 170 compatible = "rockchip,rk2928-pwm";
97 reg-shift = <2>; 171 reg = <0x20030010 0x10>;
98 reg-io-width = <1>; 172 #pwm-cells = <2>;
99 clocks = <&clk_gates1 12>; 173 clocks = <&cru PCLK_PWM01>;
100 status = "disabled"; 174 status = "disabled";
101 }; 175 };
102 176
103 uart3: serial@20068000 { 177 wdt: watchdog@2004c000 {
104 compatible = "snps,dw-apb-uart"; 178 compatible = "snps,dw-wdt";
105 reg = <0x20068000 0x400>; 179 reg = <0x2004c000 0x100>;
106 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 180 clocks = <&cru PCLK_WDT>;
107 reg-shift = <2>; 181 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
108 reg-io-width = <1>; 182 status = "disabled";
109 clocks = <&clk_gates1 14>; 183 };
110 status = "disabled"; 184
111 }; 185 pwm2: pwm@20050020 {
112 186 compatible = "rockchip,rk2928-pwm";
113 dwmmc@10214000 { 187 reg = <0x20050020 0x10>;
114 compatible = "rockchip,rk2928-dw-mshc"; 188 #pwm-cells = <2>;
115 reg = <0x10214000 0x1000>; 189 clocks = <&cru PCLK_PWM23>;
116 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 190 status = "disabled";
117 #address-cells = <1>; 191 };
118 #size-cells = <0>; 192
119 193 pwm3: pwm@20050030 {
120 clocks = <&clk_gates5 10>, <&clk_gates2 11>; 194 compatible = "rockchip,rk2928-pwm";
121 clock-names = "biu", "ciu"; 195 reg = <0x20050030 0x10>;
122 196 #pwm-cells = <2>;
123 status = "disabled"; 197 clocks = <&cru PCLK_PWM23>;
124 }; 198 status = "disabled";
125 199 };
126 dwmmc@10218000 { 200
127 compatible = "rockchip,rk2928-dw-mshc"; 201 i2c2: i2c@20056000 {
128 reg = <0x10218000 0x1000>; 202 compatible = "rockchip,rk3066-i2c";
129 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 203 reg = <0x20056000 0x1000>;
130 #address-cells = <1>; 204 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
131 #size-cells = <0>; 205 #address-cells = <1>;
132 206 #size-cells = <0>;
133 clocks = <&clk_gates5 11>, <&clk_gates2 13>; 207
134 clock-names = "biu", "ciu"; 208 rockchip,grf = <&grf>;
135 209
136 status = "disabled"; 210 clocks = <&cru PCLK_I2C2>;
137 }; 211 clock-names = "i2c";
212
213 status = "disabled";
214 };
215
216 i2c3: i2c@2005a000 {
217 compatible = "rockchip,rk3066-i2c";
218 reg = <0x2005a000 0x1000>;
219 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
221 #size-cells = <0>;
222
223 rockchip,grf = <&grf>;
224
225 clocks = <&cru PCLK_I2C3>;
226 clock-names = "i2c";
227
228 status = "disabled";
229 };
230
231 i2c4: i2c@2005e000 {
232 compatible = "rockchip,rk3066-i2c";
233 reg = <0x2005e000 0x1000>;
234 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
235 #address-cells = <1>;
236 #size-cells = <0>;
237
238 rockchip,grf = <&grf>;
239
240 clocks = <&cru PCLK_I2C4>;
241 clock-names = "i2c";
242
243 status = "disabled";
244 };
245
246 uart2: serial@20064000 {
247 compatible = "snps,dw-apb-uart";
248 reg = <0x20064000 0x400>;
249 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
250 reg-shift = <2>;
251 reg-io-width = <1>;
252 clock-names = "baudclk", "apb_pclk";
253 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
254 status = "disabled";
255 };
256
257 uart3: serial@20068000 {
258 compatible = "snps,dw-apb-uart";
259 reg = <0x20068000 0x400>;
260 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
261 reg-shift = <2>;
262 reg-io-width = <1>;
263 clock-names = "baudclk", "apb_pclk";
264 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
265 status = "disabled";
138 }; 266 };
139}; 267};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index e0b15a6e8897..45013b867c8d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -58,19 +58,19 @@
58 reg = <0x20000000 0x8000000>; 58 reg = <0x20000000 0x8000000>;
59 }; 59 };
60 60
61 slow_xtal: slow_xtal { 61 clocks {
62 compatible = "fixed-clock"; 62 slow_xtal: slow_xtal {
63 #clock-cells = <0>; 63 compatible = "fixed-clock";
64 clock-frequency = <0>; 64 #clock-cells = <0>;
65 }; 65 clock-frequency = <0>;
66 };
66 67
67 main_xtal: main_xtal { 68 main_xtal: main_xtal {
68 compatible = "fixed-clock"; 69 compatible = "fixed-clock";
69 #clock-cells = <0>; 70 #clock-cells = <0>;
70 clock-frequency = <0>; 71 clock-frequency = <0>;
71 }; 72 };
72 73
73 clocks {
74 adc_op_clk: adc_op_clk{ 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock"; 75 compatible = "fixed-clock";
76 #clock-cells = <0>; 76 #clock-cells = <0>;
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index b0b1331c1974..f7d8583eef82 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -18,12 +18,14 @@
18 reg = <0x20000000 0x20000000>; 18 reg = <0x20000000 0x20000000>;
19 }; 19 };
20 20
21 slow_xtal { 21 clocks {
22 clock-frequency = <32768>; 22 slow_xtal {
23 }; 23 clock-frequency = <32768>;
24 };
24 25
25 main_xtal { 26 main_xtal {
26 clock-frequency = <12000000>; 27 clock-frequency = <12000000>;
28 };
27 }; 29 };
28 30
29 ahb { 31 ahb {
diff --git a/arch/arm/boot/dts/sama5d3xmb.dtsi b/arch/arm/boot/dts/sama5d3xmb.dtsi
index 306eef0f97ef..b8c6f20e780c 100644
--- a/arch/arm/boot/dts/sama5d3xmb.dtsi
+++ b/arch/arm/boot/dts/sama5d3xmb.dtsi
@@ -45,6 +45,8 @@
45 wm8904: wm8904@1a { 45 wm8904: wm8904@1a {
46 compatible = "wm8904"; 46 compatible = "wm8904";
47 reg = <0x1a>; 47 reg = <0x1a>;
48 clocks = <&pck0>;
49 clock-names = "mclk";
48 }; 50 };
49 }; 51 };
50 52
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
index a99171c8a782..18662aec2ec4 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
@@ -21,6 +21,10 @@
21 model = "KZM-A9-GT"; 21 model = "KZM-A9-GT";
22 compatible = "renesas,kzm9g-reference", "renesas,sh73a0"; 22 compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
23 23
24 aliases {
25 serial4 = &scifa4;
26 };
27
24 cpus { 28 cpus {
25 cpu@0 { 29 cpu@0 {
26 cpu0-supply = <&vdd_dvfs>; 30 cpu0-supply = <&vdd_dvfs>;
@@ -35,7 +39,7 @@
35 }; 39 };
36 40
37 chosen { 41 chosen {
38 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; 42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
39 }; 43 };
40 44
41 memory { 45 memory {
@@ -276,9 +280,6 @@
276}; 280};
277 281
278&pfc { 282&pfc {
279 pinctrl-0 = <&scifa4_pins>;
280 pinctrl-names = "default";
281
282 i2c3_pins: i2c3 { 283 i2c3_pins: i2c3 {
283 renesas,groups = "i2c3_1"; 284 renesas,groups = "i2c3_1";
284 renesas,function = "i2c3"; 285 renesas,function = "i2c3";
@@ -318,6 +319,13 @@
318 }; 319 };
319}; 320};
320 321
322&scifa4 {
323 pinctrl-0 = <&scifa4_pins>;
324 pinctrl-names = "default";
325
326 status = "okay";
327};
328
321&sdhi0 { 329&sdhi0 {
322 pinctrl-0 = <&sdhi0_pins>; 330 pinctrl-0 = <&sdhi0_pins>;
323 pinctrl-names = "default"; 331 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 5ecf552e1c00..910b79079d5a 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -235,6 +235,78 @@
235 status = "disabled"; 235 status = "disabled";
236 }; 236 };
237 237
238 scifa0: serial@e6c40000 {
239 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
240 reg = <0xe6c40000 0x100>;
241 interrupt-parent = <&gic>;
242 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
243 status = "disabled";
244 };
245
246 scifa1: serial@e6c50000 {
247 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
248 reg = <0xe6c50000 0x100>;
249 interrupt-parent = <&gic>;
250 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
251 status = "disabled";
252 };
253
254 scifa2: serial@e6c60000 {
255 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
256 reg = <0xe6c60000 0x100>;
257 interrupt-parent = <&gic>;
258 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
259 status = "disabled";
260 };
261
262 scifa3: serial@e6c70000 {
263 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
264 reg = <0xe6c70000 0x100>;
265 interrupt-parent = <&gic>;
266 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
267 status = "disabled";
268 };
269
270 scifa4: serial@e6c80000 {
271 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
272 reg = <0xe6c80000 0x100>;
273 interrupt-parent = <&gic>;
274 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
275 status = "disabled";
276 };
277
278 scifa5: serial@e6cb0000 {
279 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
280 reg = <0xe6cb0000 0x100>;
281 interrupt-parent = <&gic>;
282 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
283 status = "disabled";
284 };
285
286 scifa6: serial@e6cc0000 {
287 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
288 reg = <0xe6cc0000 0x100>;
289 interrupt-parent = <&gic>;
290 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
291 status = "disabled";
292 };
293
294 scifa7: serial@e6cd0000 {
295 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
296 reg = <0xe6cd0000 0x100>;
297 interrupt-parent = <&gic>;
298 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
299 status = "disabled";
300 };
301
302 scifb8: serial@e6c30000 {
303 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
304 reg = <0xe6c30000 0x100>;
305 interrupt-parent = <&gic>;
306 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
307 status = "disabled";
308 };
309
238 pfc: pfc@e6050000 { 310 pfc: pfc@e6050000 {
239 compatible = "renesas,pfc-sh73a0"; 311 compatible = "renesas,pfc-sh73a0";
240 reg = <0xe6050000 0x8000>, 312 reg = <0xe6050000 0x8000>,
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 70fdd2064811..4d77ad690ed5 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -687,6 +687,7 @@
687 }; 687 };
688 688
689 rst: rstmgr@ffd05000 { 689 rst: rstmgr@ffd05000 {
690 #reset-cells = <1>;
690 compatible = "altr,rst-mgr"; 691 compatible = "altr,rst-mgr";
691 reg = <0xffd05000 0x1000>; 692 reg = <0xffd05000 0x1000>;
692 }; 693 };
diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi
index e41eedca3ce3..9d2323020d34 100644
--- a/arch/arm/boot/dts/ste-dbx5x0.dtsi
+++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi
@@ -875,6 +875,10 @@
875 reg = <0x80119000 0x1000>; 875 reg = <0x80119000 0x1000>;
876 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>; 876 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
877 877
878 dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
879 <&dma 41 0 0x0>; /* Logical - MemToDev */
880 dma-names = "rx", "tx";
881
878 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>; 882 clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
879 clock-names = "sdi", "apb_pclk"; 883 clock-names = "sdi", "apb_pclk";
880 884
@@ -901,6 +905,10 @@
901 reg = <0x80008000 0x1000>; 905 reg = <0x80008000 0x1000>;
902 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; 906 interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
903 907
908 dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
909 <&dma 43 0 0x0>; /* Logical - MemToDev */
910 dma-names = "rx", "tx";
911
904 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>; 912 clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
905 clock-names = "sdi", "apb_pclk"; 913 clock-names = "sdi", "apb_pclk";
906 914
@@ -929,6 +937,7 @@
929 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 937 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
930 v-ape-supply = <&db8500_vape_reg>; 938 v-ape-supply = <&db8500_vape_reg>;
931 939
940 /* This DMA channel only exist on DB8500 v1 */
932 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */ 941 dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
933 dma-names = "tx"; 942 dma-names = "tx";
934 943
@@ -962,6 +971,7 @@
962 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>; 971 interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
963 v-ape-supply = <&db8500_vape_reg>; 972 v-ape-supply = <&db8500_vape_reg>;
964 973
974 /* This DMA channel only exist on DB8500 v2 */
965 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */ 975 dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
966 dma-names = "rx"; 976 dma-names = "rx";
967 977
diff --git a/arch/arm/boot/dts/ste-href-stuib.dtsi b/arch/arm/boot/dts/ste-href-stuib.dtsi
index 1c3574435ea8..84d7c5d883f2 100644
--- a/arch/arm/boot/dts/ste-href-stuib.dtsi
+++ b/arch/arm/boot/dts/ste-href-stuib.dtsi
@@ -42,6 +42,8 @@
42 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 42 interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
43 interrupt-parent = <&gpio6>; 43 interrupt-parent = <&gpio6>;
44 interrupt-controller; 44 interrupt-controller;
45 vcc-supply = <&db8500_vsmps2_reg>;
46 vio-supply = <&db8500_vsmps2_reg>;
45 47
46 wakeup-source; 48 wakeup-source;
47 st,autosleep-timeout = <1024>; 49 st,autosleep-timeout = <1024>;
diff --git a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
index c40565320978..18b65d1b14f2 100644
--- a/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
+++ b/arch/arm/boot/dts/ste-href-tvk1281618.dtsi
@@ -88,6 +88,43 @@
88 }; 88 };
89 }; 89 };
90 }; 90 };
91 /* Sensors mounted on this board variant */
92 i2c@80128000 {
93 lsm303dlh@18 {
94 /* Accelerometer */
95 compatible = "st,lsm303dlh-accel";
96 st,drdy-int-pin = <1>;
97 reg = <0x18>;
98 vdd-supply = <&ab8500_ldo_aux1_reg>;
99 vddio-supply = <&db8500_vsmps2_reg>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&accel_tvk_mode>;
102 };
103 lsm303dlm@1e {
104 /* Magnetometer */
105 compatible = "st,lsm303dlm-magn";
106 reg = <0x1e>;
107 vdd-supply = <&ab8500_ldo_aux1_reg>;
108 vddio-supply = <&db8500_vsmps2_reg>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&magneto_tvk_mode>;
111 };
112 l3g4200d@68 {
113 /* Gyroscope */
114 compatible = "st,l3g4200d-gyro";
115 st,drdy-int-pin = <2>;
116 reg = <0x68>;
117 vdd-supply = <&ab8500_ldo_aux1_reg>;
118 vddio-supply = <&db8500_vsmps2_reg>;
119 };
120 lsp001wm@5c {
121 /* Barometer/pressure sensor */
122 compatible = "st,lps001wp-press";
123 reg = <0x5c>;
124 vdd-supply = <&ab8500_ldo_aux1_reg>;
125 vddio-supply = <&db8500_vsmps2_reg>;
126 };
127 };
91 pinctrl { 128 pinctrl {
92 /* Pull up this GPIO pin */ 129 /* Pull up this GPIO pin */
93 tc35893 { 130 tc35893 {
@@ -114,6 +151,28 @@
114 }; 151 };
115 }; 152 };
116 }; 153 };
154 accelerometer {
155 accel_tvk_mode: accel_tvk {
156 /* Accelerometer interrupt lines 1 & 2 */
157 tvk_cfg {
158 ste,pins = "GPIO82_C1", "GPIO83_D3";
159 ste,config = <&gpio_in_pu>;
160 };
161 };
162 };
163 magnetometer {
164 magneto_tvk_mode: magneto_tvk {
165 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
166 tvk_cfg1 {
167 ste,pins = "GPIO31_V3";
168 ste,config = <&gpio_in_pu>;
169 };
170 tvk_cfg2 {
171 ste,pins = "GPIO32_V2";
172 ste,config = <&gpio_in_pd>;
173 };
174 };
175 };
117 }; 176 };
118 }; 177 };
119}; 178};
diff --git a/arch/arm/boot/dts/ste-hrefv60plus.dtsi b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
index c2341061b943..bcc1f0c37f49 100644
--- a/arch/arm/boot/dts/ste-hrefv60plus.dtsi
+++ b/arch/arm/boot/dts/ste-hrefv60plus.dtsi
@@ -35,8 +35,6 @@
35 */ 35 */
36 pinctrl-names = "default"; 36 pinctrl-names = "default";
37 pinctrl-0 = <&ipgpio_hrefv60_mode>, 37 pinctrl-0 = <&ipgpio_hrefv60_mode>,
38 <&accel_hrefv60_mode>,
39 <&magneto_hrefv60_mode>,
40 <&etm_hrefv60_mode>, 38 <&etm_hrefv60_mode>,
41 <&nahj_hrefv60_mode>, 39 <&nahj_hrefv60_mode>,
42 <&nfc_hrefv60_mode>, 40 <&nfc_hrefv60_mode>,
@@ -83,28 +81,6 @@
83 }; 81 };
84 }; 82 };
85 }; 83 };
86 accelerometer {
87 accel_hrefv60_mode: accel_hrefv60 {
88 /* Accelerometer interrupt lines 1 & 2 */
89 hrefv60_cfg1 {
90 ste,pins = "GPIO82_C1", "GPIO83_D3";
91 ste,config = <&gpio_in_pu>;
92 };
93 };
94 };
95 magnetometer {
96 magneto_hrefv60_mode: magneto_hrefv60 {
97 /* Magnetometer uses GPIO 31 and 32, pull these up/down respectively */
98 hrefv60_cfg1 {
99 ste,pins = "GPIO31_V3";
100 ste,config = <&gpio_in_pu>;
101 };
102 hrefv60_cfg2 {
103 ste,pins = "GPIO32_V2";
104 ste,config = <&gpio_in_pd>;
105 };
106 };
107 };
108 etm { 84 etm {
109 /* 85 /*
110 * Drive D19-D23 for the ETM PTM trace interface low, 86 * Drive D19-D23 for the ETM PTM trace interface low,
diff --git a/arch/arm/boot/dts/ste-snowball.dts b/arch/arm/boot/dts/ste-snowball.dts
index 474ef83229cd..4a2000c620ad 100644
--- a/arch/arm/boot/dts/ste-snowball.dts
+++ b/arch/arm/boot/dts/ste-snowball.dts
@@ -241,6 +241,40 @@
241 pinctrl-names = "default","sleep"; 241 pinctrl-names = "default","sleep";
242 pinctrl-0 = <&i2c2_default_mode>; 242 pinctrl-0 = <&i2c2_default_mode>;
243 pinctrl-1 = <&i2c2_sleep_mode>; 243 pinctrl-1 = <&i2c2_sleep_mode>;
244 lsm303dlh@18 {
245 /* Accelerometer */
246 compatible = "st,lsm303dlh-accel";
247 st,drdy-int-pin = <1>;
248 reg = <0x18>;
249 vdd-supply = <&ab8500_ldo_aux1_reg>;
250 vddio-supply = <&db8500_vsmps2_reg>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&accel_snowball_mode>;
253 };
254 lsm303dlm@1e {
255 /* Magnetometer */
256 compatible = "st,lsm303dlm-magn";
257 reg = <0x1e>;
258 vdd-supply = <&ab8500_ldo_aux1_reg>;
259 vddio-supply = <&db8500_vsmps2_reg>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&magneto_snowball_mode>;
262 };
263 l3g4200d@68 {
264 /* Gyroscope */
265 compatible = "st,l3g4200d-gyro";
266 st,drdy-int-pin = <2>;
267 reg = <0x68>;
268 vdd-supply = <&ab8500_ldo_aux1_reg>;
269 vddio-supply = <&db8500_vsmps2_reg>;
270 };
271 lsp001wm@5c {
272 /* Barometer/pressure sensor */
273 compatible = "st,lps001wp-press";
274 reg = <0x5c>;
275 vdd-supply = <&ab8500_ldo_aux1_reg>;
276 vddio-supply = <&db8500_vsmps2_reg>;
277 };
244 }; 278 };
245 279
246 i2c@80110000 { 280 i2c@80110000 {
@@ -361,9 +395,7 @@
361 * can be moved over to being controlled by respective device. 395 * can be moved over to being controlled by respective device.
362 */ 396 */
363 pinctrl-names = "default"; 397 pinctrl-names = "default";
364 pinctrl-0 = <&accel_snowball_mode>, 398 pinctrl-0 = <&gbf_snowball_mode>,
365 <&magneto_snowball_mode>,
366 <&gbf_snowball_mode>,
367 <&wlan_snowball_mode>; 399 <&wlan_snowball_mode>;
368 400
369 ethernet { 401 ethernet {
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index 0b97c071dd56..9e99ade35e37 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -88,6 +88,12 @@
88 }; 88 };
89 }; 89 };
90 90
91 ir0: ir@01c21800 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&ir0_pins_a>;
94 status = "okay";
95 };
96
91 uart0: serial@01c28000 { 97 uart0: serial@01c28000 {
92 pinctrl-names = "default"; 98 pinctrl-names = "default";
93 pinctrl-0 = <&uart0_pins_a>; 99 pinctrl-0 = <&uart0_pins_a>;
@@ -98,6 +104,15 @@
98 pinctrl-names = "default"; 104 pinctrl-names = "default";
99 pinctrl-0 = <&i2c0_pins_a>; 105 pinctrl-0 = <&i2c0_pins_a>;
100 status = "okay"; 106 status = "okay";
107
108 axp209: pmic@34 {
109 compatible = "x-powers,axp209";
110 reg = <0x34>;
111 interrupts = <0>;
112
113 interrupt-controller;
114 #interrupt-cells = <1>;
115 };
101 }; 116 };
102 }; 117 };
103 118
diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
new file mode 100644
index 000000000000..1763cc7ec023
--- /dev/null
+++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
@@ -0,0 +1,110 @@
1/*
2 * Copyright 2014 Hans de Goede <hdegoede@redhat.com>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13/include/ "sun4i-a10.dtsi"
14/include/ "sunxi-common-regulators.dtsi"
15
16/ {
17 model = "BA10 tvbox";
18 compatible = "allwinner,ba10-tvbox", "allwinner,sun4i-a10";
19
20 soc@01c00000 {
21 emac: ethernet@01c0b000 {
22 pinctrl-names = "default";
23 pinctrl-0 = <&emac_pins_a>;
24 phy = <&phy1>;
25 status = "okay";
26 };
27
28 mdio@01c0b080 {
29 status = "okay";
30
31 phy1: ethernet-phy@1 {
32 reg = <1>;
33 };
34 };
35
36 mmc0: mmc@01c0f000 {
37 pinctrl-names = "default";
38 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
39 vmmc-supply = <&reg_vcc3v3>;
40 bus-width = <4>;
41 cd-gpios = <&pio 7 1 0>; /* PH1 */
42 cd-inverted;
43 status = "okay";
44 };
45
46 usbphy: phy@01c13400 {
47 usb1_vbus-supply = <&reg_usb1_vbus>;
48 usb2_vbus-supply = <&reg_usb2_vbus>;
49 status = "okay";
50 };
51
52 ehci0: usb@01c14000 {
53 status = "okay";
54 };
55
56 ohci0: usb@01c14400 {
57 status = "okay";
58 };
59
60 ehci1: usb@01c1c000 {
61 status = "okay";
62 };
63
64 ohci1: usb@01c1c400 {
65 status = "okay";
66 };
67
68 pinctrl@01c20800 {
69 usb2_vbus_pin_a: usb2_vbus_pin@0 {
70 allwinner,pins = "PH12";
71 };
72 };
73
74 ir0: ir@01c21800 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&ir0_pins_a>;
77 status = "okay";
78 };
79
80 uart0: serial@01c28000 {
81 pinctrl-names = "default";
82 pinctrl-0 = <&uart0_pins_a>;
83 status = "okay";
84 };
85
86 i2c0: i2c@01c2ac00 {
87 pinctrl-names = "default";
88 pinctrl-0 = <&i2c0_pins_a>;
89 status = "okay";
90
91 axp209: pmic@34 {
92 compatible = "x-powers,axp209";
93 reg = <0x34>;
94 interrupts = <0>;
95
96 interrupt-controller;
97 #interrupt-cells = <1>;
98 };
99 };
100 };
101
102 reg_usb1_vbus: usb1-vbus {
103 status = "okay";
104 };
105
106 reg_usb2_vbus: usb2-vbus {
107 gpio = <&pio 7 12 0>;
108 status = "okay";
109 };
110};
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index c200eacc66e8..3ce56bfbc0b5 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -80,6 +80,12 @@
80 }; 80 };
81 }; 81 };
82 82
83 ir0: ir@01c21800 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&ir0_pins_a>;
86 status = "okay";
87 };
88
83 uart0: serial@01c28000 { 89 uart0: serial@01c28000 {
84 pinctrl-names = "default"; 90 pinctrl-names = "default";
85 pinctrl-0 = <&uart0_pins_a>; 91 pinctrl-0 = <&uart0_pins_a>;
@@ -90,6 +96,15 @@
90 pinctrl-names = "default"; 96 pinctrl-names = "default";
91 pinctrl-0 = <&i2c0_pins_a>; 97 pinctrl-0 = <&i2c0_pins_a>;
92 status = "okay"; 98 status = "okay";
99
100 axp209: pmic@34 {
101 compatible = "x-powers,axp209";
102 reg = <0x34>;
103 interrupts = <0>;
104
105 interrupt-controller;
106 #interrupt-cells = <1>;
107 };
93 }; 108 };
94 109
95 i2c1: i2c@01c2b000 { 110 i2c1: i2c@01c2b000 {
diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
index 547fadcb984b..891ea446abae 100644
--- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
+++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
@@ -87,11 +87,32 @@
87 }; 87 };
88 }; 88 };
89 89
90 ir0: ir@01c21800 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&ir0_pins_a>;
93 status = "okay";
94 };
95
90 uart0: serial@01c28000 { 96 uart0: serial@01c28000 {
91 pinctrl-names = "default"; 97 pinctrl-names = "default";
92 pinctrl-0 = <&uart0_pins_a>; 98 pinctrl-0 = <&uart0_pins_a>;
93 status = "okay"; 99 status = "okay";
94 }; 100 };
101
102 i2c0: i2c@01c2ac00 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&i2c0_pins_a>;
105 status = "okay";
106
107 axp209: pmic@34 {
108 compatible = "x-powers,axp209";
109 reg = <0x34>;
110 interrupts = <0>;
111
112 interrupt-controller;
113 #interrupt-cells = <1>;
114 };
115 };
95 }; 116 };
96 117
97 reg_emac_3v3: emac-3v3 { 118 reg_emac_3v3: emac-3v3 {
diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
index f13723e18b86..6b0c37812ade 100644
--- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
+++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
@@ -40,12 +40,6 @@
40 status = "okay"; 40 status = "okay";
41 }; 41 };
42 42
43 i2c0: i2c@01c2ac00 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&i2c0_pins_a>;
46 status = "okay";
47 };
48
49 usbphy: phy@01c13400 { 43 usbphy: phy@01c13400 {
50 usb1_vbus-supply = <&reg_usb1_vbus>; 44 usb1_vbus-supply = <&reg_usb1_vbus>;
51 usb2_vbus-supply = <&reg_usb2_vbus>; 45 usb2_vbus-supply = <&reg_usb2_vbus>;
@@ -67,6 +61,21 @@
67 ohci1: usb@01c1c400 { 61 ohci1: usb@01c1c400 {
68 status = "okay"; 62 status = "okay";
69 }; 63 };
64
65 i2c0: i2c@01c2ac00 {
66 pinctrl-names = "default";
67 pinctrl-0 = <&i2c0_pins_a>;
68 status = "okay";
69
70 axp209: pmic@34 {
71 compatible = "x-powers,axp209";
72 reg = <0x34>;
73 interrupts = <0>;
74
75 interrupt-controller;
76 #interrupt-cells = <1>;
77 };
78 };
70 }; 79 };
71 80
72 reg_usb1_vbus: usb1-vbus { 81 reg_usb1_vbus: usb1-vbus {
diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
index c01cea50cf0c..b9ecce60f2e7 100644
--- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
+++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
@@ -52,11 +52,39 @@
52 status = "okay"; 52 status = "okay";
53 }; 53 };
54 54
55 pinctrl@01c20800 {
56 ir0_pins_a: ir0@0 {
57 /* The ir receiver is not always populated */
58 allwinner,pull = <1>;
59 };
60 };
61
62 ir0: ir@01c21800 {
63 pinctrl-names = "default";
64 pinctrl-0 = <&ir0_pins_a>;
65 status = "okay";
66 };
67
55 uart0: serial@01c28000 { 68 uart0: serial@01c28000 {
56 pinctrl-names = "default"; 69 pinctrl-names = "default";
57 pinctrl-0 = <&uart0_pins_a>; 70 pinctrl-0 = <&uart0_pins_a>;
58 status = "okay"; 71 status = "okay";
59 }; 72 };
73
74 i2c0: i2c@01c2ac00 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&i2c0_pins_a>;
77 status = "okay";
78
79 axp209: pmic@34 {
80 compatible = "x-powers,axp209";
81 reg = <0x34>;
82 interrupts = <0>;
83
84 interrupt-controller;
85 #interrupt-cells = <1>;
86 };
87 };
60 }; 88 };
61 89
62 reg_usb1_vbus: usb1-vbus { 90 reg_usb1_vbus: usb1-vbus {
diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
index d46a7dbecef5..d046d568f5a1 100644
--- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
+++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
@@ -91,6 +91,21 @@
91 pinctrl-0 = <&uart0_pins_a>; 91 pinctrl-0 = <&uart0_pins_a>;
92 status = "okay"; 92 status = "okay";
93 }; 93 };
94
95 i2c0: i2c@01c2ac00 {
96 pinctrl-names = "default";
97 pinctrl-0 = <&i2c0_pins_a>;
98 status = "okay";
99
100 axp209: pmic@34 {
101 compatible = "x-powers,axp209";
102 reg = <0x34>;
103 interrupts = <0>;
104
105 interrupt-controller;
106 #interrupt-cells = <1>;
107 };
108 };
94 }; 109 };
95 110
96 leds { 111 leds {
diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
index fb03bccb78d2..6675bcd7860e 100644
--- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
+++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
@@ -76,6 +76,15 @@
76 pinctrl-names = "default"; 76 pinctrl-names = "default";
77 pinctrl-0 = <&i2c0_pins_a>; 77 pinctrl-0 = <&i2c0_pins_a>;
78 status = "okay"; 78 status = "okay";
79
80 axp209: pmic@34 {
81 compatible = "x-powers,axp209";
82 reg = <0x34>;
83 interrupts = <0>;
84
85 interrupt-controller;
86 #interrupt-cells = <1>;
87 };
79 }; 88 };
80 }; 89 };
81 90
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index d96e179490ce..459cb6377764 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -509,7 +509,7 @@
509 clocks = <&apb0_gates 5>; 509 clocks = <&apb0_gates 5>;
510 gpio-controller; 510 gpio-controller;
511 interrupt-controller; 511 interrupt-controller;
512 #address-cells = <1>; 512 #interrupt-cells = <2>;
513 #size-cells = <0>; 513 #size-cells = <0>;
514 #gpio-cells = <3>; 514 #gpio-cells = <3>;
515 515
@@ -593,6 +593,20 @@
593 allwinner,drive = <0>; 593 allwinner,drive = <0>;
594 allwinner,pull = <1>; 594 allwinner,pull = <1>;
595 }; 595 };
596
597 ir0_pins_a: ir0@0 {
598 allwinner,pins = "PB3","PB4";
599 allwinner,function = "ir0";
600 allwinner,drive = <0>;
601 allwinner,pull = <0>;
602 };
603
604 ir1_pins_a: ir1@0 {
605 allwinner,pins = "PB22","PB23";
606 allwinner,function = "ir1";
607 allwinner,drive = <0>;
608 allwinner,pull = <0>;
609 };
596 }; 610 };
597 611
598 timer@01c20c00 { 612 timer@01c20c00 {
@@ -621,6 +635,24 @@
621 status = "disabled"; 635 status = "disabled";
622 }; 636 };
623 637
638 ir0: ir@01c21800 {
639 compatible = "allwinner,sun4i-a10-ir";
640 clocks = <&apb0_gates 6>, <&ir0_clk>;
641 clock-names = "apb", "ir";
642 interrupts = <5>;
643 reg = <0x01c21800 0x40>;
644 status = "disabled";
645 };
646
647 ir1: ir@01c21c00 {
648 compatible = "allwinner,sun4i-a10-ir";
649 clocks = <&apb0_gates 7>, <&ir1_clk>;
650 clock-names = "apb", "ir";
651 interrupts = <6>;
652 reg = <0x01c21c00 0x40>;
653 status = "disabled";
654 };
655
624 sid: eeprom@01c23800 { 656 sid: eeprom@01c23800 {
625 compatible = "allwinner,sun4i-a10-sid"; 657 compatible = "allwinner,sun4i-a10-sid";
626 reg = <0x01c23800 0x10>; 658 reg = <0x01c23800 0x10>;
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index b64f705d9008..24b0ad3a7c07 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -422,7 +422,7 @@
422 clocks = <&apb0_gates 5>; 422 clocks = <&apb0_gates 5>;
423 gpio-controller; 423 gpio-controller;
424 interrupt-controller; 424 interrupt-controller;
425 #address-cells = <1>; 425 #interrupt-cells = <2>;
426 #size-cells = <0>; 426 #size-cells = <0>;
427 #gpio-cells = <3>; 427 #gpio-cells = <3>;
428 428
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index 3b2a94c40f6e..bf86e65dd167 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -395,7 +395,7 @@
395 clocks = <&apb0_gates 5>; 395 clocks = <&apb0_gates 5>;
396 gpio-controller; 396 gpio-controller;
397 interrupt-controller; 397 interrupt-controller;
398 #address-cells = <1>; 398 #interrupt-cells = <2>;
399 #size-cells = <0>; 399 #size-cells = <0>;
400 #gpio-cells = <3>; 400 #gpio-cells = <3>;
401 401
diff --git a/arch/arm/boot/dts/sun6i-a31-hummingbird.dts b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
new file mode 100644
index 000000000000..f142065b3c1f
--- /dev/null
+++ b/arch/arm/boot/dts/sun6i-a31-hummingbird.dts
@@ -0,0 +1,119 @@
1/*
2 * Copyright 2014 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun6i-a31.dtsi"
16/include/ "sunxi-common-regulators.dtsi"
17
18/ {
19 model = "Merrii A31 Hummingbird";
20 compatible = "merrii,a31-hummingbird", "allwinner,sun6i-a31";
21
22 chosen {
23 bootargs = "earlyprintk console=ttyS0,115200";
24 };
25
26 soc@01c00000 {
27 mmc0: mmc@01c0f000 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_hummingbird>;
30 vmmc-supply = <&reg_vcc3v0>;
31 bus-width = <4>;
32 cd-gpios = <&pio 0 8 0>; /* PA8 */
33 cd-inverted;
34 status = "okay";
35 };
36
37 usbphy: phy@01c19400 {
38 usb1_vbus-supply = <&reg_usb1_vbus>;
39 status = "okay";
40 };
41
42 ehci0: usb@01c1a000 {
43 status = "okay";
44 };
45
46 ohci0: usb@01c1a400 {
47 status = "okay";
48 };
49
50 pio: pinctrl@01c20800 {
51 mmc0_pins_a: mmc0@0 {
52 /* external pull-ups missing for some pins */
53 allwinner,pull = <1>;
54 };
55
56 mmc0_cd_pin_hummingbird: mmc0_cd_pin@0 {
57 allwinner,pins = "PA8";
58 allwinner,function = "gpio_in";
59 allwinner,drive = <0>;
60 allwinner,pull = <1>;
61 };
62
63 usb1_vbus_pin_a: usb1_vbus_pin@0 {
64 allwinner,pins = "PH24";
65 allwinner,function = "gpio_out";
66 allwinner,drive = <0>;
67 allwinner,pull = <0>;
68 };
69 };
70
71 uart0: serial@01c28000 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&uart0_pins_a>;
74 status = "okay";
75 };
76
77 i2c0: i2c@01c2ac00 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&i2c0_pins_a>;
80 /* pull-ups and devices require AXP221 DLDO3 */
81 status = "failed";
82 };
83
84 i2c1: i2c@01c2b000 {
85 pinctrl-names = "default";
86 pinctrl-0 = <&i2c1_pins_a>;
87 status = "okay";
88 };
89
90 i2c2: i2c@01c2b400 {
91 pinctrl-names = "default";
92 pinctrl-0 = <&i2c2_pins_a>;
93 status = "okay";
94
95 pcf8563: rtc@51 {
96 compatible = "nxp,pcf8563";
97 reg = <0x51>;
98 };
99 };
100
101 gmac: ethernet@01c30000 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&gmac_pins_rgmii_a>;
104 phy = <&phy1>;
105 phy-mode = "rgmii";
106 status = "okay";
107
108 phy1: ethernet-phy@1 {
109 reg = <1>;
110 };
111 };
112 };
113
114 reg_usb1_vbus: usb1-vbus {
115 pinctrl-0 = <&usb1_vbus_pin_a>;
116 gpio = <&pio 7 24 0>; /* PH24 */
117 status = "okay";
118 };
119};
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index a9dfa12eb735..44b07e512c24 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -23,6 +23,7 @@
23 serial3 = &uart3; 23 serial3 = &uart3;
24 serial4 = &uart4; 24 serial4 = &uart4;
25 serial5 = &uart5; 25 serial5 = &uart5;
26 ethernet0 = &gmac;
26 }; 27 };
27 28
28 29
@@ -281,6 +282,34 @@
281 "usb_ohci0", "usb_ohci1", 282 "usb_ohci0", "usb_ohci1",
282 "usb_ohci2"; 283 "usb_ohci2";
283 }; 284 };
285
286 /*
287 * The following two are dummy clocks, placeholders used in the gmac_tx
288 * clock. The gmac driver will choose one parent depending on the PHY
289 * interface mode, using clk_set_rate auto-reparenting.
290 * The actual TX clock rate is not controlled by the gmac_tx clock.
291 */
292 mii_phy_tx_clk: clk@1 {
293 #clock-cells = <0>;
294 compatible = "fixed-clock";
295 clock-frequency = <25000000>;
296 clock-output-names = "mii_phy_tx";
297 };
298
299 gmac_int_tx_clk: clk@2 {
300 #clock-cells = <0>;
301 compatible = "fixed-clock";
302 clock-frequency = <125000000>;
303 clock-output-names = "gmac_int_tx";
304 };
305
306 gmac_tx_clk: clk@01c200d0 {
307 #clock-cells = <0>;
308 compatible = "allwinner,sun7i-a20-gmac-clk";
309 reg = <0x01c200d0 0x4>;
310 clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
311 clock-output-names = "gmac_tx";
312 };
284 }; 313 };
285 314
286 soc@01c00000 { 315 soc@01c00000 {
@@ -429,7 +458,7 @@
429 clocks = <&apb1_gates 5>; 458 clocks = <&apb1_gates 5>;
430 gpio-controller; 459 gpio-controller;
431 interrupt-controller; 460 interrupt-controller;
432 #address-cells = <1>; 461 #interrupt-cells = <2>;
433 #size-cells = <0>; 462 #size-cells = <0>;
434 #gpio-cells = <3>; 463 #gpio-cells = <3>;
435 464
@@ -467,6 +496,48 @@
467 allwinner,drive = <2>; 496 allwinner,drive = <2>;
468 allwinner,pull = <0>; 497 allwinner,pull = <0>;
469 }; 498 };
499
500 gmac_pins_mii_a: gmac_mii@0 {
501 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
502 "PA8", "PA9", "PA11",
503 "PA12", "PA13", "PA14", "PA19",
504 "PA20", "PA21", "PA22", "PA23",
505 "PA24", "PA26", "PA27";
506 allwinner,function = "gmac";
507 allwinner,drive = <0>;
508 allwinner,pull = <0>;
509 };
510
511 gmac_pins_gmii_a: gmac_gmii@0 {
512 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
513 "PA4", "PA5", "PA6", "PA7",
514 "PA8", "PA9", "PA10", "PA11",
515 "PA12", "PA13", "PA14", "PA15",
516 "PA16", "PA17", "PA18", "PA19",
517 "PA20", "PA21", "PA22", "PA23",
518 "PA24", "PA25", "PA26", "PA27";
519 allwinner,function = "gmac";
520 /*
521 * data lines in GMII mode run at 125MHz and
522 * might need a higher signal drive strength
523 */
524 allwinner,drive = <2>;
525 allwinner,pull = <0>;
526 };
527
528 gmac_pins_rgmii_a: gmac_rgmii@0 {
529 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
530 "PA9", "PA10", "PA11",
531 "PA12", "PA13", "PA14", "PA19",
532 "PA20", "PA25", "PA26", "PA27";
533 allwinner,function = "gmac";
534 /*
535 * data lines in RGMII mode use DDR mode
536 * and need a higher signal drive strength
537 */
538 allwinner,drive = <3>;
539 allwinner,pull = <0>;
540 };
470 }; 541 };
471 542
472 ahb1_rst: reset@01c202c0 { 543 ahb1_rst: reset@01c202c0 {
@@ -621,6 +692,23 @@
621 status = "disabled"; 692 status = "disabled";
622 }; 693 };
623 694
695 gmac: ethernet@01c30000 {
696 compatible = "allwinner,sun7i-a20-gmac";
697 reg = <0x01c30000 0x1054>;
698 interrupts = <0 82 4>;
699 interrupt-names = "macirq";
700 clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
701 clock-names = "stmmaceth", "allwinner_gmac_tx";
702 resets = <&ahb1_rst 17>;
703 reset-names = "stmmaceth";
704 snps,pbl = <2>;
705 snps,fixed-burst;
706 snps,force_sf_dma_mode;
707 status = "disabled";
708 #address-cells = <1>;
709 #size-cells = <0>;
710 };
711
624 timer@01c60000 { 712 timer@01c60000 {
625 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer"; 713 compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
626 reg = <0x01c60000 0x1000>; 714 reg = <0x01c60000 0x1000>;
@@ -756,7 +844,7 @@
756 resets = <&apb0_rst 0>; 844 resets = <&apb0_rst 0>;
757 gpio-controller; 845 gpio-controller;
758 interrupt-controller; 846 interrupt-controller;
759 #address-cells = <1>; 847 #interrupt-cells = <2>;
760 #size-cells = <0>; 848 #size-cells = <0>;
761 #gpio-cells = <3>; 849 #gpio-cells = <3>;
762 }; 850 };
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index a5ad945197e8..53680983461a 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -66,6 +66,12 @@
66 }; 66 };
67 }; 67 };
68 68
69 ir0: ir@01c21800 {
70 pinctrl-names = "default";
71 pinctrl-0 = <&ir0_pins_a>;
72 status = "okay";
73 };
74
69 uart0: serial@01c28000 { 75 uart0: serial@01c28000 {
70 pinctrl-names = "default"; 76 pinctrl-names = "default";
71 pinctrl-0 = <&uart0_pins_a>; 77 pinctrl-0 = <&uart0_pins_a>;
@@ -76,6 +82,16 @@
76 pinctrl-names = "default"; 82 pinctrl-names = "default";
77 pinctrl-0 = <&i2c0_pins_a>; 83 pinctrl-0 = <&i2c0_pins_a>;
78 status = "okay"; 84 status = "okay";
85
86 axp209: pmic@34 {
87 compatible = "x-powers,axp209";
88 reg = <0x34>;
89 interrupt-parent = <&nmi_intc>;
90 interrupts = <0 8>;
91
92 interrupt-controller;
93 #interrupt-cells = <1>;
94 };
79 }; 95 };
80 96
81 i2c1: i2c@01c2b000 { 97 i2c1: i2c@01c2b000 {
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index b87fea901489..a6c1a3c717bc 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -100,6 +100,12 @@
100 status = "okay"; 100 status = "okay";
101 }; 101 };
102 102
103 ir0: ir@01c21800 {
104 pinctrl-names = "default";
105 pinctrl-0 = <&ir0_pins_a>;
106 status = "okay";
107 };
108
103 uart0: serial@01c28000 { 109 uart0: serial@01c28000 {
104 pinctrl-names = "default"; 110 pinctrl-names = "default";
105 pinctrl-0 = <&uart0_pins_a>; 111 pinctrl-0 = <&uart0_pins_a>;
@@ -110,6 +116,16 @@
110 pinctrl-names = "default"; 116 pinctrl-names = "default";
111 pinctrl-0 = <&i2c0_pins_a>; 117 pinctrl-0 = <&i2c0_pins_a>;
112 status = "okay"; 118 status = "okay";
119
120 axp209: pmic@34 {
121 compatible = "x-powers,axp209";
122 reg = <0x34>;
123 interrupt-parent = <&nmi_intc>;
124 interrupts = <0 8>;
125
126 interrupt-controller;
127 #interrupt-cells = <1>;
128 };
113 }; 129 };
114 130
115 i2c1: i2c@01c2b000 { 131 i2c1: i2c@01c2b000 {
diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
index b77308e90199..6a67712d417a 100644
--- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
+++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
@@ -94,12 +94,34 @@
94 }; 94 };
95 }; 95 };
96 96
97 ir0: ir@01c21800 {
98 pinctrl-names = "default";
99 pinctrl-0 = <&ir0_pins_a>;
100 status = "okay";
101 };
102
97 uart0: serial@01c28000 { 103 uart0: serial@01c28000 {
98 pinctrl-names = "default"; 104 pinctrl-names = "default";
99 pinctrl-0 = <&uart0_pins_a>; 105 pinctrl-0 = <&uart0_pins_a>;
100 status = "okay"; 106 status = "okay";
101 }; 107 };
102 108
109 i2c0: i2c@01c2ac00 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&i2c0_pins_a>;
112 status = "okay";
113
114 axp209: pmic@34 {
115 compatible = "x-powers,axp209";
116 reg = <0x34>;
117 interrupt-parent = <&nmi_intc>;
118 interrupts = <0 8>;
119
120 interrupt-controller;
121 #interrupt-cells = <1>;
122 };
123 };
124
103 gmac: ethernet@01c50000 { 125 gmac: ethernet@01c50000 {
104 pinctrl-names = "default"; 126 pinctrl-names = "default";
105 pinctrl-0 = <&gmac_pins_mii_a>; 127 pinctrl-0 = <&gmac_pins_mii_a>;
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index b759630bc9a9..9d669cdf031d 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -122,6 +122,16 @@
122 pinctrl-names = "default"; 122 pinctrl-names = "default";
123 pinctrl-0 = <&i2c0_pins_a>; 123 pinctrl-0 = <&i2c0_pins_a>;
124 status = "okay"; 124 status = "okay";
125
126 axp209: pmic@34 {
127 compatible = "x-powers,axp209";
128 reg = <0x34>;
129 interrupt-parent = <&nmi_intc>;
130 interrupts = <0 8>;
131
132 interrupt-controller;
133 #interrupt-cells = <1>;
134 };
125 }; 135 };
126 136
127 i2c1: i2c@01c2b000 { 137 i2c1: i2c@01c2b000 {
diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
new file mode 100644
index 000000000000..046dfc0d45d8
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
@@ -0,0 +1,173 @@
1/*
2 * Copyright 2014 Zoltan HERPAI
3 * Zoltan HERPAI <wigyori@uid0.hu>
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/dts-v1/;
14/include/ "sun7i-a20.dtsi"
15/include/ "sunxi-common-regulators.dtsi"
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18
19/ {
20 model = "LinkSprite pcDuino3";
21 compatible = "linksprite,pcduino3", "allwinner,sun7i-a20";
22
23 soc@01c00000 {
24 mmc0: mmc@01c0f000 {
25 pinctrl-names = "default";
26 pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
27 vmmc-supply = <&reg_vcc3v3>;
28 bus-width = <4>;
29 cd-gpios = <&pio 7 1 0>; /* PH1 */
30 cd-inverted;
31 status = "okay";
32 };
33
34 usbphy: phy@01c13400 {
35 usb1_vbus-supply = <&reg_usb1_vbus>;
36 usb2_vbus-supply = <&reg_usb2_vbus>;
37 status = "okay";
38 };
39
40 ehci0: usb@01c14000 {
41 status = "okay";
42 };
43
44 ohci0: usb@01c14400 {
45 status = "okay";
46 };
47
48 ahci: sata@01c18000 {
49 target-supply = <&reg_ahci_5v>;
50 status = "okay";
51 };
52
53 ehci1: usb@01c1c000 {
54 status = "okay";
55 };
56
57 ohci1: usb@01c1c400 {
58 status = "okay";
59 };
60
61 pinctrl@01c20800 {
62 ahci_pwr_pin_a: ahci_pwr_pin@0 {
63 allwinner,pins = "PH2";
64 };
65
66 led_pins_pcduino3: led_pins@0 {
67 allwinner,pins = "PH15", "PH16";
68 allwinner,function = "gpio_out";
69 allwinner,drive = <0>;
70 allwinner,pull = <0>;
71 };
72
73 key_pins_pcduino3: key_pins@0 {
74 allwinner,pins = "PH17", "PH18", "PH19";
75 allwinner,function = "gpio_in";
76 allwinner,drive = <0>;
77 allwinner,pull = <0>;
78 };
79 };
80
81 ir0: ir@01c21800 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&ir0_pins_a>;
84 status = "okay";
85 };
86
87 uart0: serial@01c28000 {
88 pinctrl-names = "default";
89 pinctrl-0 = <&uart0_pins_a>;
90 status = "okay";
91 };
92
93 i2c0: i2c@01c2ac00 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&i2c0_pins_a>;
96 status = "okay";
97
98 axp209: pmic@34 {
99 compatible = "x-powers,axp209";
100 reg = <0x34>;
101 interrupt-parent = <&nmi_intc>;
102 interrupts = <0 8>;
103
104 interrupt-controller;
105 #interrupt-cells = <1>;
106 };
107 };
108
109 gmac: ethernet@01c50000 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&gmac_pins_mii_a>;
112 phy = <&phy1>;
113 phy-mode = "mii";
114 status = "okay";
115
116 phy1: ethernet-phy@1 {
117 reg = <1>;
118 };
119 };
120 };
121
122 leds {
123 compatible = "gpio-leds";
124 pinctrl-names = "default";
125 pinctrl-0 = <&led_pins_pcduino3>;
126
127 tx {
128 label = "pcduino3:green:tx";
129 gpios = <&pio 7 15 GPIO_ACTIVE_LOW>;
130 };
131
132 rx {
133 label = "pcduino3:green:rx";
134 gpios = <&pio 7 16 GPIO_ACTIVE_LOW>;
135 };
136 };
137
138 gpio_keys {
139 compatible = "gpio-keys";
140 pinctrl-names = "default";
141 pinctrl-0 = <&key_pins_pcduino3>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144 button@0 {
145 label = "Key Back";
146 linux,code = <KEY_BACK>;
147 gpios = <&pio 7 17 GPIO_ACTIVE_LOW>;
148 };
149 button@1 {
150 label = "Key Home";
151 linux,code = <KEY_HOME>;
152 gpios = <&pio 7 18 GPIO_ACTIVE_LOW>;
153 };
154 button@2 {
155 label = "Key Menu";
156 linux,code = <KEY_MENU>;
157 gpios = <&pio 7 19 GPIO_ACTIVE_LOW>;
158 };
159 };
160
161 reg_usb1_vbus: usb1-vbus {
162 status = "okay";
163 };
164
165 reg_usb2_vbus: usb2-vbus {
166 status = "okay";
167 };
168
169 reg_ahci_5v: ahci-5v {
170 gpio = <&pio 7 2 0>;
171 status = "okay";
172 };
173};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 01e94664232a..4011628c7381 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -586,7 +586,7 @@
586 clocks = <&apb0_gates 5>; 586 clocks = <&apb0_gates 5>;
587 gpio-controller; 587 gpio-controller;
588 interrupt-controller; 588 interrupt-controller;
589 #address-cells = <1>; 589 #interrupt-cells = <2>;
590 #size-cells = <0>; 590 #size-cells = <0>;
591 #gpio-cells = <3>; 591 #gpio-cells = <3>;
592 592
@@ -738,6 +738,20 @@
738 allwinner,drive = <2>; 738 allwinner,drive = <2>;
739 allwinner,pull = <0>; 739 allwinner,pull = <0>;
740 }; 740 };
741
742 ir0_pins_a: ir0@0 {
743 allwinner,pins = "PB3","PB4";
744 allwinner,function = "ir0";
745 allwinner,drive = <0>;
746 allwinner,pull = <0>;
747 };
748
749 ir1_pins_a: ir1@0 {
750 allwinner,pins = "PB22","PB23";
751 allwinner,function = "ir1";
752 allwinner,drive = <0>;
753 allwinner,pull = <0>;
754 };
741 }; 755 };
742 756
743 timer@01c20c00 { 757 timer@01c20c00 {
@@ -771,6 +785,24 @@
771 status = "disabled"; 785 status = "disabled";
772 }; 786 };
773 787
788 ir0: ir@01c21800 {
789 compatible = "allwinner,sun4i-a10-ir";
790 clocks = <&apb0_gates 6>, <&ir0_clk>;
791 clock-names = "apb", "ir";
792 interrupts = <0 5 4>;
793 reg = <0x01c21800 0x40>;
794 status = "disabled";
795 };
796
797 ir1: ir@01c21c00 {
798 compatible = "allwinner,sun4i-a10-ir";
799 clocks = <&apb0_gates 7>, <&ir1_clk>;
800 clock-names = "apb", "ir";
801 interrupts = <0 6 4>;
802 reg = <0x01c21c00 0x40>;
803 status = "disabled";
804 };
805
774 sid: eeprom@01c23800 { 806 sid: eeprom@01c23800 {
775 compatible = "allwinner,sun7i-a20-sid"; 807 compatible = "allwinner,sun7i-a20-sid";
776 reg = <0x01c23800 0x200>; 808 reg = <0x01c23800 0x200>;
diff --git a/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
new file mode 100644
index 000000000000..34002e3eba9d
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23-ippo-q8h-v5.dts
@@ -0,0 +1,30 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun8i-a23.dtsi"
16
17/ {
18 model = "Ippo Q8H Dual Core Tablet (v5)";
19 compatible = "ippo,q8h-v5", "allwinner,sun8i-a23";
20
21 chosen {
22 bootargs = "earlyprintk console=ttyS0,115200";
23 };
24
25 soc@01c00000 {
26 r_uart: serial@01f02800 {
27 status = "okay";
28 };
29 };
30};
diff --git a/arch/arm/boot/dts/sun8i-a23.dtsi b/arch/arm/boot/dts/sun8i-a23.dtsi
new file mode 100644
index 000000000000..54ac0787216a
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-a23.dtsi
@@ -0,0 +1,343 @@
1/*
2 * Copyright 2014 Chen-Yu Tsai
3 *
4 * Chen-Yu Tsai <wens@csie.org>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &r_uart;
26 };
27
28 cpus {
29 #address-cells = <1>;
30 #size-cells = <0>;
31
32 cpu@0 {
33 compatible = "arm,cortex-a7";
34 device_type = "cpu";
35 reg = <0>;
36 };
37
38 cpu@1 {
39 compatible = "arm,cortex-a7";
40 device_type = "cpu";
41 reg = <1>;
42 };
43 };
44
45 memory {
46 reg = <0x40000000 0x40000000>;
47 };
48
49 clocks {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 osc24M: osc24M_clk {
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-frequency = <24000000>;
58 clock-output-names = "osc24M";
59 };
60
61 osc32k: osc32k_clk {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 clock-output-names = "osc32k";
66 };
67
68 pll1: clk@01c20000 {
69 #clock-cells = <0>;
70 compatible = "allwinner,sun8i-a23-pll1-clk";
71 reg = <0x01c20000 0x4>;
72 clocks = <&osc24M>;
73 clock-output-names = "pll1";
74 };
75
76 /* dummy clock until actually implemented */
77 pll6: pll6_clk {
78 #clock-cells = <0>;
79 compatible = "fixed-clock";
80 clock-frequency = <600000000>;
81 clock-output-names = "pll6";
82 };
83
84 cpu: cpu_clk@01c20050 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-a10-cpu-clk";
87 reg = <0x01c20050 0x4>;
88
89 /*
90 * PLL1 is listed twice here.
91 * While it looks suspicious, it's actually documented
92 * that way both in the datasheet and in the code from
93 * Allwinner.
94 */
95 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
96 clock-output-names = "cpu";
97 };
98
99 axi: axi_clk@01c20050 {
100 #clock-cells = <0>;
101 compatible = "allwinner,sun8i-a23-axi-clk";
102 reg = <0x01c20050 0x4>;
103 clocks = <&cpu>;
104 clock-output-names = "axi";
105 };
106
107 ahb1_mux: ahb1_mux_clk@01c20054 {
108 #clock-cells = <0>;
109 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
110 reg = <0x01c20054 0x4>;
111 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
112 clock-output-names = "ahb1_mux";
113 };
114
115 ahb1: ahb1_clk@01c20054 {
116 #clock-cells = <0>;
117 compatible = "allwinner,sun4i-a10-ahb-clk";
118 reg = <0x01c20054 0x4>;
119 clocks = <&ahb1_mux>;
120 clock-output-names = "ahb1";
121 };
122
123 apb1: apb1_clk@01c20054 {
124 #clock-cells = <0>;
125 compatible = "allwinner,sun4i-a10-apb0-clk";
126 reg = <0x01c20054 0x4>;
127 clocks = <&ahb1>;
128 clock-output-names = "apb1";
129 };
130
131 ahb1_gates: clk@01c20060 {
132 #clock-cells = <1>;
133 compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
134 reg = <0x01c20060 0x8>;
135 clocks = <&ahb1>;
136 clock-output-names = "ahb1_mipidsi", "ahb1_dma",
137 "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
138 "ahb1_nand", "ahb1_sdram",
139 "ahb1_hstimer", "ahb1_spi0",
140 "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
141 "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
142 "ahb1_csi", "ahb1_be", "ahb1_fe",
143 "ahb1_gpu", "ahb1_spinlock",
144 "ahb1_drc";
145 };
146
147 apb1_gates: clk@01c20068 {
148 #clock-cells = <1>;
149 compatible = "allwinner,sun8i-a23-apb1-gates-clk";
150 reg = <0x01c20068 0x4>;
151 clocks = <&apb1>;
152 clock-output-names = "apb1_codec", "apb1_pio",
153 "apb1_daudio0", "apb1_daudio1";
154 };
155
156 apb2_mux: apb2_mux_clk@01c20058 {
157 #clock-cells = <0>;
158 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
159 reg = <0x01c20058 0x4>;
160 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
161 clock-output-names = "apb2_mux";
162 };
163
164 apb2: apb2_clk@01c20058 {
165 #clock-cells = <0>;
166 compatible = "allwinner,sun6i-a31-apb2-div-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&apb2_mux>;
169 clock-output-names = "apb2";
170 };
171
172 apb2_gates: clk@01c2006c {
173 #clock-cells = <1>;
174 compatible = "allwinner,sun8i-a23-apb2-gates-clk";
175 reg = <0x01c2006c 0x4>;
176 clocks = <&apb2>;
177 clock-output-names = "apb2_i2c0", "apb2_i2c1",
178 "apb2_i2c2", "apb2_uart0",
179 "apb2_uart1", "apb2_uart2",
180 "apb2_uart3", "apb2_uart4";
181 };
182 };
183
184 soc@01c00000 {
185 compatible = "simple-bus";
186 #address-cells = <1>;
187 #size-cells = <1>;
188 ranges;
189
190 ahb1_rst: reset@01c202c0 {
191 #reset-cells = <1>;
192 compatible = "allwinner,sun6i-a31-clock-reset";
193 reg = <0x01c202c0 0xc>;
194 };
195
196 apb1_rst: reset@01c202d0 {
197 #reset-cells = <1>;
198 compatible = "allwinner,sun6i-a31-clock-reset";
199 reg = <0x01c202d0 0x4>;
200 };
201
202 apb2_rst: reset@01c202d8 {
203 #reset-cells = <1>;
204 compatible = "allwinner,sun6i-a31-clock-reset";
205 reg = <0x01c202d8 0x4>;
206 };
207
208 timer@01c20c00 {
209 compatible = "allwinner,sun4i-a10-timer";
210 reg = <0x01c20c00 0xa0>;
211 interrupts = <0 18 4>,
212 <0 19 4>;
213 clocks = <&osc24M>;
214 };
215
216 wdt0: watchdog@01c20ca0 {
217 compatible = "allwinner,sun6i-a31-wdt";
218 reg = <0x01c20ca0 0x20>;
219 interrupts = <0 25 4>;
220 };
221
222 uart0: serial@01c28000 {
223 compatible = "snps,dw-apb-uart";
224 reg = <0x01c28000 0x400>;
225 interrupts = <0 0 4>;
226 reg-shift = <2>;
227 reg-io-width = <4>;
228 clocks = <&apb2_gates 16>;
229 resets = <&apb2_rst 16>;
230 status = "disabled";
231 };
232
233 uart1: serial@01c28400 {
234 compatible = "snps,dw-apb-uart";
235 reg = <0x01c28400 0x400>;
236 interrupts = <0 1 4>;
237 reg-shift = <2>;
238 reg-io-width = <4>;
239 clocks = <&apb2_gates 17>;
240 resets = <&apb2_rst 17>;
241 status = "disabled";
242 };
243
244 uart2: serial@01c28800 {
245 compatible = "snps,dw-apb-uart";
246 reg = <0x01c28800 0x400>;
247 interrupts = <0 2 4>;
248 reg-shift = <2>;
249 reg-io-width = <4>;
250 clocks = <&apb2_gates 18>;
251 resets = <&apb2_rst 18>;
252 status = "disabled";
253 };
254
255 uart3: serial@01c28c00 {
256 compatible = "snps,dw-apb-uart";
257 reg = <0x01c28c00 0x400>;
258 interrupts = <0 3 4>;
259 reg-shift = <2>;
260 reg-io-width = <4>;
261 clocks = <&apb2_gates 19>;
262 resets = <&apb2_rst 19>;
263 status = "disabled";
264 };
265
266 uart4: serial@01c29000 {
267 compatible = "snps,dw-apb-uart";
268 reg = <0x01c29000 0x400>;
269 interrupts = <0 4 4>;
270 reg-shift = <2>;
271 reg-io-width = <4>;
272 clocks = <&apb2_gates 20>;
273 resets = <&apb2_rst 20>;
274 status = "disabled";
275 };
276
277 gic: interrupt-controller@01c81000 {
278 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
279 reg = <0x01c81000 0x1000>,
280 <0x01c82000 0x1000>,
281 <0x01c84000 0x2000>,
282 <0x01c86000 0x2000>;
283 interrupt-controller;
284 #interrupt-cells = <3>;
285 interrupts = <1 9 0xf04>;
286 };
287
288 prcm@01f01400 {
289 compatible = "allwinner,sun8i-a23-prcm";
290 reg = <0x01f01400 0x200>;
291
292 ar100: ar100_clk {
293 compatible = "fixed-factor-clock";
294 #clock-cells = <0>;
295 clock-div = <1>;
296 clock-mult = <1>;
297 clocks = <&osc24M>;
298 clock-output-names = "ar100";
299 };
300
301 ahb0: ahb0_clk {
302 compatible = "fixed-factor-clock";
303 #clock-cells = <0>;
304 clock-div = <1>;
305 clock-mult = <1>;
306 clocks = <&ar100>;
307 clock-output-names = "ahb0";
308 };
309
310 apb0: apb0_clk {
311 compatible = "allwinner,sun8i-a23-apb0-clk";
312 #clock-cells = <0>;
313 clocks = <&ahb0>;
314 clock-output-names = "apb0";
315 };
316
317 apb0_gates: apb0_gates_clk {
318 compatible = "allwinner,sun8i-a23-apb0-gates-clk";
319 #clock-cells = <1>;
320 clocks = <&apb0>;
321 clock-output-names = "apb0_pio", "apb0_timer",
322 "apb0_rsb", "apb0_uart",
323 "apb0_i2c";
324 };
325
326 apb0_rst: apb0_rst {
327 compatible = "allwinner,sun6i-a31-clock-reset";
328 #reset-cells = <1>;
329 };
330 };
331
332 r_uart: serial@01f02800 {
333 compatible = "snps,dw-apb-uart";
334 reg = <0x01f02800 0x400>;
335 interrupts = <0 38 4>;
336 reg-shift = <2>;
337 reg-io-width = <4>;
338 clocks = <&apb0_gates 4>;
339 resets = <&apb0_rst 4>;
340 status = "disabled";
341 };
342 };
343};
diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
index 0b0e8e07d965..c7c6825f11fb 100644
--- a/arch/arm/boot/dts/tegra114-roth.dts
+++ b/arch/arm/boot/dts/tegra114-roth.dts
@@ -28,6 +28,22 @@
28 reg = <0x80000000 0x79600000>; 28 reg = <0x80000000 0x79600000>;
29 }; 29 };
30 30
31 host1x@50000000 {
32 dsi@54300000 {
33 status = "okay";
34
35 vdd-supply = <&vdd_1v2_ap>;
36
37 panel@0 {
38 compatible = "lg,lh500wx1-sd03";
39 reg = <0>;
40
41 power-supply = <&vdd_lcd>;
42 backlight = <&backlight>;
43 };
44 };
45 };
46
31 pinmux@70000868 { 47 pinmux@70000868 {
32 pinctrl-names = "default"; 48 pinctrl-names = "default";
33 pinctrl-0 = <&state_default>; 49 pinctrl-0 = <&state_default>;
@@ -244,7 +260,7 @@
244 nvidia,function = "sdmmc1"; 260 nvidia,function = "sdmmc1";
245 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 261 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
246 nvidia,tristate = <TEGRA_PIN_DISABLE>; 262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 263 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 }; 264 };
249 sdmmc1_cmd_pz1 { 265 sdmmc1_cmd_pz1 {
250 nvidia,pins = "sdmmc1_cmd_pz1", 266 nvidia,pins = "sdmmc1_cmd_pz1",
@@ -262,7 +278,7 @@
262 nvidia,function = "sdmmc3"; 278 nvidia,function = "sdmmc3";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 279 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>; 280 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 281 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
266 }; 282 };
267 sdmmc3_cmd_pa7 { 283 sdmmc3_cmd_pa7 {
268 nvidia,pins = "sdmmc3_cmd_pa7", 284 nvidia,pins = "sdmmc3_cmd_pa7",
@@ -290,7 +306,7 @@
290 nvidia,function = "sdmmc4"; 306 nvidia,function = "sdmmc4";
291 nvidia,pull = <TEGRA_PIN_PULL_NONE>; 307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
292 nvidia,tristate = <TEGRA_PIN_DISABLE>; 308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
293 nvidia,enable-input = <TEGRA_PIN_DISABLE>; 309 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
294 }; 310 };
295 sdmmc4_cmd_pt7 { 311 sdmmc4_cmd_pt7 {
296 nvidia,pins = "sdmmc4_cmd_pt7", 312 nvidia,pins = "sdmmc4_cmd_pt7",
@@ -730,7 +746,6 @@
730 nvidia,pins = "drive_sdio1"; 746 nvidia,pins = "drive_sdio1";
731 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 747 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
732 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 748 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
733 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
734 nvidia,pull-down-strength = <36>; 749 nvidia,pull-down-strength = <36>;
735 nvidia,pull-up-strength = <20>; 750 nvidia,pull-up-strength = <20>;
736 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>; 751 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOW>;
@@ -740,7 +755,6 @@
740 nvidia,pins = "drive_sdio3"; 755 nvidia,pins = "drive_sdio3";
741 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 756 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
742 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 757 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
743 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
744 nvidia,pull-down-strength = <36>; 758 nvidia,pull-down-strength = <36>;
745 nvidia,pull-up-strength = <20>; 759 nvidia,pull-up-strength = <20>;
746 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 760 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
@@ -750,12 +764,10 @@
750 nvidia,pins = "drive_gma"; 764 nvidia,pins = "drive_gma";
751 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; 765 nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
752 nvidia,schmitt = <TEGRA_PIN_DISABLE>; 766 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
753 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
754 nvidia,pull-down-strength = <2>; 767 nvidia,pull-down-strength = <2>;
755 nvidia,pull-up-strength = <2>; 768 nvidia,pull-up-strength = <2>;
756 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; 769 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
757 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; 770 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
758 nvidia,drive-type = <1>;
759 }; 771 };
760 }; 772 };
761 }; 773 };
@@ -815,7 +827,6 @@
815 regulator-name = "vdd-1v8"; 827 regulator-name = "vdd-1v8";
816 regulator-min-microvolt = <1800000>; 828 regulator-min-microvolt = <1800000>;
817 regulator-max-microvolt = <1800000>; 829 regulator-max-microvolt = <1800000>;
818 regulator-always-on;
819 regulator-boot-on; 830 regulator-boot-on;
820 }; 831 };
821 832
@@ -862,10 +873,11 @@
862 regulator-name = "vdd-2v8-display"; 873 regulator-name = "vdd-2v8-display";
863 regulator-min-microvolt = <2800000>; 874 regulator-min-microvolt = <2800000>;
864 regulator-max-microvolt = <2800000>; 875 regulator-max-microvolt = <2800000>;
876 regulator-always-on;
865 regulator-boot-on; 877 regulator-boot-on;
866 }; 878 };
867 879
868 ldo3 { 880 vdd_1v2_ap: ldo3 {
869 regulator-name = "avdd-1v2"; 881 regulator-name = "avdd-1v2";
870 regulator-min-microvolt = <1200000>; 882 regulator-min-microvolt = <1200000>;
871 regulator-max-microvolt = <1200000>; 883 regulator-max-microvolt = <1200000>;
@@ -1052,7 +1064,7 @@
1052 regulator-boot-on; 1064 regulator-boot-on;
1053 }; 1065 };
1054 1066
1055 regulator@1 { 1067 vdd_lcd: regulator@1 {
1056 compatible = "regulator-fixed"; 1068 compatible = "regulator-fixed";
1057 reg = <1>; 1069 reg = <1>;
1058 regulator-name = "vdd_lcd_1v8"; 1070 regulator-name = "vdd_lcd_1v8";
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index e31fb61a81d3..624b0fba2d0a 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1461,7 +1461,7 @@
1461 regulator-max-microamp = <3500000>; 1461 regulator-max-microamp = <3500000>;
1462 regulator-always-on; 1462 regulator-always-on;
1463 regulator-boot-on; 1463 regulator-boot-on;
1464 ams,external-control = <2>; 1464 ams,ext-control = <2>;
1465 }; 1465 };
1466 1466
1467 sd1 { 1467 sd1 {
@@ -1472,7 +1472,7 @@
1472 regulator-max-microamp = <2500000>; 1472 regulator-max-microamp = <2500000>;
1473 regulator-always-on; 1473 regulator-always-on;
1474 regulator-boot-on; 1474 regulator-boot-on;
1475 ams,external-control = <1>; 1475 ams,ext-control = <1>;
1476 }; 1476 };
1477 1477
1478 vdd_1v35_lp0: sd2 { 1478 vdd_1v35_lp0: sd2 {
@@ -1521,7 +1521,7 @@
1521 regulator-max-microvolt = <1050000>; 1521 regulator-max-microvolt = <1050000>;
1522 regulator-boot-on; 1522 regulator-boot-on;
1523 regulator-always-on; 1523 regulator-always-on;
1524 ams,external-control = <1>; 1524 ams,ext-control = <1>;
1525 }; 1525 };
1526 1526
1527 ldo1 { 1527 ldo1 {
@@ -1619,6 +1619,32 @@
1619 nvidia,sys-clock-req-active-high; 1619 nvidia,sys-clock-req-active-high;
1620 }; 1620 };
1621 1621
1622 padctl@0,7009f000 {
1623 pinctrl-0 = <&padctl_default>;
1624 pinctrl-names = "default";
1625
1626 padctl_default: pinmux {
1627 usb3 {
1628 nvidia,lanes = "pcie-0", "pcie-1";
1629 nvidia,function = "usb3";
1630 nvidia,iddq = <0>;
1631 };
1632
1633 pcie {
1634 nvidia,lanes = "pcie-2", "pcie-3",
1635 "pcie-4";
1636 nvidia,function = "pcie";
1637 nvidia,iddq = <0>;
1638 };
1639
1640 sata {
1641 nvidia,lanes = "sata-0";
1642 nvidia,function = "sata";
1643 nvidia,iddq = <0>;
1644 };
1645 };
1646 };
1647
1622 /* SD card */ 1648 /* SD card */
1623 sdhci@0,700b0400 { 1649 sdhci@0,700b0400 {
1624 status = "okay"; 1650 status = "okay";
@@ -1633,6 +1659,7 @@
1633 sdhci@0,700b0600 { 1659 sdhci@0,700b0600 {
1634 status = "okay"; 1660 status = "okay";
1635 bus-width = <8>; 1661 bus-width = <8>;
1662 non-removable;
1636 }; 1663 };
1637 1664
1638 ahub@0,70300000 { 1665 ahub@0,70300000 {
diff --git a/arch/arm/boot/dts/tegra124-venice2.dts b/arch/arm/boot/dts/tegra124-venice2.dts
index f0bb84244025..70ad91d1a20b 100644
--- a/arch/arm/boot/dts/tegra124-venice2.dts
+++ b/arch/arm/boot/dts/tegra124-venice2.dts
@@ -682,7 +682,7 @@
682 regulator-max-microamp = <3500000>; 682 regulator-max-microamp = <3500000>;
683 regulator-always-on; 683 regulator-always-on;
684 regulator-boot-on; 684 regulator-boot-on;
685 ams,external-control = <2>; 685 ams,ext-control = <2>;
686 }; 686 };
687 687
688 sd1 { 688 sd1 {
@@ -693,7 +693,7 @@
693 regulator-max-microamp = <2500000>; 693 regulator-max-microamp = <2500000>;
694 regulator-always-on; 694 regulator-always-on;
695 regulator-boot-on; 695 regulator-boot-on;
696 ams,external-control = <1>; 696 ams,ext-control = <1>;
697 }; 697 };
698 698
699 vdd_1v35_lp0: sd2 { 699 vdd_1v35_lp0: sd2 {
@@ -742,7 +742,7 @@
742 regulator-max-microvolt = <1050000>; 742 regulator-max-microvolt = <1050000>;
743 regulator-boot-on; 743 regulator-boot-on;
744 regulator-always-on; 744 regulator-always-on;
745 ams,external-control = <1>; 745 ams,ext-control = <1>;
746 }; 746 };
747 747
748 ldo1 { 748 ldo1 {
@@ -816,7 +816,7 @@
816 spi@0,7000d400 { 816 spi@0,7000d400 {
817 status = "okay"; 817 status = "okay";
818 818
819 cros-ec@0 { 819 cros_ec: cros-ec@0 {
820 compatible = "google,cros-ec-spi"; 820 compatible = "google,cros-ec-spi";
821 spi-max-frequency = <4000000>; 821 spi-max-frequency = <4000000>;
822 interrupt-parent = <&gpio>; 822 interrupt-parent = <&gpio>;
@@ -825,96 +825,30 @@
825 825
826 google,cros-ec-spi-msg-delay = <2000>; 826 google,cros-ec-spi-msg-delay = <2000>;
827 827
828 cros-ec-keyb { 828 i2c-tunnel {
829 compatible = "google,cros-ec-keyb"; 829 compatible = "google,cros-ec-i2c-tunnel";
830 keypad,num-rows = <8>; 830 #address-cells = <1>;
831 keypad,num-columns = <13>; 831 #size-cells = <0>;
832 google,needs-ghost-filter; 832
833 833 google,remote-bus = <0>;
834 linux,keymap = < 834
835 MATRIX_KEY(0x00, 0x01, KEY_LEFTMETA) 835 charger: bq24735@9 {
836 MATRIX_KEY(0x00, 0x02, KEY_F1) 836 compatible = "ti,bq24735";
837 MATRIX_KEY(0x00, 0x03, KEY_B) 837 reg = <0x9>;
838 MATRIX_KEY(0x00, 0x04, KEY_F10) 838 interrupt-parent = <&gpio>;
839 MATRIX_KEY(0x00, 0x06, KEY_N) 839 interrupts = <TEGRA_GPIO(J, 0)
840 MATRIX_KEY(0x00, 0x08, KEY_EQUAL) 840 GPIO_ACTIVE_HIGH>;
841 MATRIX_KEY(0x00, 0x0a, KEY_RIGHTALT) 841 ti,ac-detect-gpios = <&gpio
842 842 TEGRA_GPIO(J, 0)
843 MATRIX_KEY(0x01, 0x01, KEY_ESC) 843 GPIO_ACTIVE_HIGH>;
844 MATRIX_KEY(0x01, 0x02, KEY_F4) 844 };
845 MATRIX_KEY(0x01, 0x03, KEY_G) 845
846 MATRIX_KEY(0x01, 0x04, KEY_F7) 846 battery: sbs-battery@b {
847 MATRIX_KEY(0x01, 0x06, KEY_H) 847 compatible = "sbs,sbs-battery";
848 MATRIX_KEY(0x01, 0x08, KEY_APOSTROPHE) 848 reg = <0xb>;
849 MATRIX_KEY(0x01, 0x09, KEY_F9) 849 sbs,i2c-retry-count = <2>;
850 MATRIX_KEY(0x01, 0x0b, KEY_BACKSPACE) 850 sbs,poll-retry-count = <1>;
851 851 };
852 MATRIX_KEY(0x02, 0x00, KEY_LEFTCTRL)
853 MATRIX_KEY(0x02, 0x01, KEY_TAB)
854 MATRIX_KEY(0x02, 0x02, KEY_F3)
855 MATRIX_KEY(0x02, 0x03, KEY_T)
856 MATRIX_KEY(0x02, 0x04, KEY_F6)
857 MATRIX_KEY(0x02, 0x05, KEY_RIGHTBRACE)
858 MATRIX_KEY(0x02, 0x06, KEY_Y)
859 MATRIX_KEY(0x02, 0x07, KEY_102ND)
860 MATRIX_KEY(0x02, 0x08, KEY_LEFTBRACE)
861 MATRIX_KEY(0x02, 0x09, KEY_F8)
862
863 MATRIX_KEY(0x03, 0x01, KEY_GRAVE)
864 MATRIX_KEY(0x03, 0x02, KEY_F2)
865 MATRIX_KEY(0x03, 0x03, KEY_5)
866 MATRIX_KEY(0x03, 0x04, KEY_F5)
867 MATRIX_KEY(0x03, 0x06, KEY_6)
868 MATRIX_KEY(0x03, 0x08, KEY_MINUS)
869 MATRIX_KEY(0x03, 0x0b, KEY_BACKSLASH)
870
871 MATRIX_KEY(0x04, 0x00, KEY_RIGHTCTRL)
872 MATRIX_KEY(0x04, 0x01, KEY_A)
873 MATRIX_KEY(0x04, 0x02, KEY_D)
874 MATRIX_KEY(0x04, 0x03, KEY_F)
875 MATRIX_KEY(0x04, 0x04, KEY_S)
876 MATRIX_KEY(0x04, 0x05, KEY_K)
877 MATRIX_KEY(0x04, 0x06, KEY_J)
878 MATRIX_KEY(0x04, 0x08, KEY_SEMICOLON)
879 MATRIX_KEY(0x04, 0x09, KEY_L)
880 MATRIX_KEY(0x04, 0x0a, KEY_BACKSLASH)
881 MATRIX_KEY(0x04, 0x0b, KEY_ENTER)
882
883 MATRIX_KEY(0x05, 0x01, KEY_Z)
884 MATRIX_KEY(0x05, 0x02, KEY_C)
885 MATRIX_KEY(0x05, 0x03, KEY_V)
886 MATRIX_KEY(0x05, 0x04, KEY_X)
887 MATRIX_KEY(0x05, 0x05, KEY_COMMA)
888 MATRIX_KEY(0x05, 0x06, KEY_M)
889 MATRIX_KEY(0x05, 0x07, KEY_LEFTSHIFT)
890 MATRIX_KEY(0x05, 0x08, KEY_SLASH)
891 MATRIX_KEY(0x05, 0x09, KEY_DOT)
892 MATRIX_KEY(0x05, 0x0b, KEY_SPACE)
893
894 MATRIX_KEY(0x06, 0x01, KEY_1)
895 MATRIX_KEY(0x06, 0x02, KEY_3)
896 MATRIX_KEY(0x06, 0x03, KEY_4)
897 MATRIX_KEY(0x06, 0x04, KEY_2)
898 MATRIX_KEY(0x06, 0x05, KEY_8)
899 MATRIX_KEY(0x06, 0x06, KEY_7)
900 MATRIX_KEY(0x06, 0x08, KEY_0)
901 MATRIX_KEY(0x06, 0x09, KEY_9)
902 MATRIX_KEY(0x06, 0x0a, KEY_LEFTALT)
903 MATRIX_KEY(0x06, 0x0b, KEY_DOWN)
904 MATRIX_KEY(0x06, 0x0c, KEY_RIGHT)
905
906 MATRIX_KEY(0x07, 0x01, KEY_Q)
907 MATRIX_KEY(0x07, 0x02, KEY_E)
908 MATRIX_KEY(0x07, 0x03, KEY_R)
909 MATRIX_KEY(0x07, 0x04, KEY_W)
910 MATRIX_KEY(0x07, 0x05, KEY_I)
911 MATRIX_KEY(0x07, 0x06, KEY_U)
912 MATRIX_KEY(0x07, 0x07, KEY_RIGHTSHIFT)
913 MATRIX_KEY(0x07, 0x08, KEY_P)
914 MATRIX_KEY(0x07, 0x09, KEY_O)
915 MATRIX_KEY(0x07, 0x0b, KEY_UP)
916 MATRIX_KEY(0x07, 0x0c, KEY_LEFT)
917 >;
918 }; 852 };
919 }; 853 };
920 }; 854 };
@@ -940,6 +874,10 @@
940 nvidia,sys-clock-req-active-high; 874 nvidia,sys-clock-req-active-high;
941 }; 875 };
942 876
877 hda@0,70030000 {
878 status = "okay";
879 };
880
943 sdhci@0,700b0400 { 881 sdhci@0,700b0400 {
944 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 882 cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
945 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; 883 power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>;
@@ -1205,3 +1143,5 @@
1205 clock-names = "pll_a", "pll_a_out0", "mclk"; 1143 clock-names = "pll_a", "pll_a_out0", "mclk";
1206 }; 1144 };
1207}; 1145};
1146
1147#include "cros-ec-keyboard.dtsi"
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi
index d44e9b91e207..03916efd6fa9 100644
--- a/arch/arm/boot/dts/tegra124.dtsi
+++ b/arch/arm/boot/dts/tegra124.dtsi
@@ -1,6 +1,7 @@
1#include <dt-bindings/clock/tegra124-car.h> 1#include <dt-bindings/clock/tegra124-car.h>
2#include <dt-bindings/gpio/tegra-gpio.h> 2#include <dt-bindings/gpio/tegra-gpio.h>
3#include <dt-bindings/pinctrl/pinctrl-tegra.h> 3#include <dt-bindings/pinctrl/pinctrl-tegra.h>
4#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/interrupt-controller/arm-gic.h>
5 6
6#include "skeleton.dtsi" 7#include "skeleton.dtsi"
@@ -102,6 +103,21 @@
102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
103 }; 104 };
104 105
106 gpu@0,57000000 {
107 compatible = "nvidia,gk20a";
108 reg = <0x0 0x57000000 0x0 0x01000000>,
109 <0x0 0x58000000 0x0 0x01000000>;
110 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
112 interrupt-names = "stall", "nonstall";
113 clocks = <&tegra_car TEGRA124_CLK_GPU>,
114 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
115 clock-names = "gpu", "pwr";
116 resets = <&tegra_car 184>;
117 reset-names = "gpu";
118 status = "disabled";
119 };
120
105 timer@0,60005000 { 121 timer@0,60005000 {
106 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer"; 122 compatible = "nvidia,tegra124-timer", "nvidia,tegra20-timer";
107 reg = <0x0 0x60005000 0x0 0x400>; 123 reg = <0x0 0x60005000 0x0 0x400>;
@@ -464,6 +480,30 @@
464 reset-names = "fuse"; 480 reset-names = "fuse";
465 }; 481 };
466 482
483 hda@0,70030000 {
484 compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
485 reg = <0x0 0x70030000 0x0 0x10000>;
486 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&tegra_car TEGRA124_CLK_HDA>,
488 <&tegra_car TEGRA124_CLK_HDA2HDMI>,
489 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>;
490 clock-names = "hda", "hda2hdmi", "hdacodec_2x";
491 resets = <&tegra_car 125>, /* hda */
492 <&tegra_car 128>, /* hda2hdmi */
493 <&tegra_car 111>; /* hda2codec_2x */
494 reset-names = "hda", "hda2hdmi", "hdacodec_2x";
495 status = "disabled";
496 };
497
498 padctl: padctl@0,7009f000 {
499 compatible = "nvidia,tegra124-xusb-padctl";
500 reg = <0x0 0x7009f000 0x0 0x1000>;
501 resets = <&tegra_car 142>;
502 reset-names = "padctl";
503
504 #phy-cells = <1>;
505 };
506
467 sdhci@0,700b0000 { 507 sdhci@0,700b0000 {
468 compatible = "nvidia,tegra124-sdhci"; 508 compatible = "nvidia,tegra124-sdhci";
469 reg = <0x0 0x700b0000 0x0 0x200>; 509 reg = <0x0 0x700b0000 0x0 0x200>;
diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts
index 6d3a4cbc36cc..1b7c56b33aca 100644
--- a/arch/arm/boot/dts/tegra20-medcom-wide.dts
+++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts
@@ -10,6 +10,15 @@
10 status = "okay"; 10 status = "okay";
11 }; 11 };
12 12
13 host1x@50000000 {
14 dc@54200000 {
15 rgb {
16 status = "okay";
17 nvidia,panel = <&panel>;
18 };
19 };
20 };
21
13 i2c@7000c000 { 22 i2c@7000c000 {
14 wm8903: wm8903@1a { 23 wm8903: wm8903@1a {
15 compatible = "wlf,wm8903"; 24 compatible = "wlf,wm8903";
@@ -30,7 +39,7 @@
30 }; 39 };
31 }; 40 };
32 41
33 backlight { 42 backlight: backlight {
34 compatible = "pwm-backlight"; 43 compatible = "pwm-backlight";
35 pwms = <&pwm 0 5000000>; 44 pwms = <&pwm 0 5000000>;
36 45
@@ -38,6 +47,15 @@
38 default-brightness-level = <6>; 47 default-brightness-level = <6>;
39 }; 48 };
40 49
50 panel: panel {
51 compatible = "innolux,n156bge-l21", "simple-panel";
52
53 power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>;
54 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
55
56 backlight = <&backlight>;
57 };
58
41 sound { 59 sound {
42 compatible = "ad,tegra-audio-wm8903-medcom-wide", 60 compatible = "ad,tegra-audio-wm8903-medcom-wide",
43 "nvidia,tegra-audio-wm8903"; 61 "nvidia,tegra-audio-wm8903";
@@ -64,4 +82,45 @@
64 <&tegra_car TEGRA20_CLK_CDEV1>; 82 <&tegra_car TEGRA20_CLK_CDEV1>;
65 clock-names = "pll_a", "pll_a_out0", "mclk"; 83 clock-names = "pll_a", "pll_a_out0", "mclk";
66 }; 84 };
85
86 regulators {
87 vcc_24v_reg: regulator@100 {
88 compatible = "regulator-fixed";
89 reg = <100>;
90 regulator-name = "vcc_24v";
91 regulator-min-microvolt = <24000000>;
92 regulator-max-microvolt = <24000000>;
93 regulator-always-on;
94 };
95
96 vdd_5v0_reg: regulator@101 {
97 compatible = "regulator-fixed";
98 reg = <101>;
99 regulator-name = "vdd_5v0";
100 vin-supply = <&vcc_24v_reg>;
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 };
105
106 vdd_3v3_reg: regulator@102 {
107 compatible = "regulator-fixed";
108 reg = <102>;
109 regulator-name = "vdd_3v3";
110 vin-supply = <&vcc_24v_reg>;
111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <3300000>;
113 regulator-always-on;
114 };
115
116 vdd_1v8_reg: regulator@103 {
117 compatible = "regulator-fixed";
118 reg = <103>;
119 regulator-name = "vdd_1v8";
120 vin-supply = <&vdd_3v3_reg>;
121 regulator-min-microvolt = <1800000>;
122 regulator-max-microvolt = <1800000>;
123 regulator-always-on;
124 };
125 };
67}; 126};
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9a39a8001f78..d4438e30de45 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -296,7 +296,7 @@
296 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; 296 request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
297 slave-addr = <138>; 297 slave-addr = <138>;
298 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 298 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
299 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 299 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
300 clock-names = "div-clk", "fast-clk"; 300 clock-names = "div-clk", "fast-clk";
301 resets = <&tegra_car 67>; 301 resets = <&tegra_car 67>;
302 reset-names = "i2c"; 302 reset-names = "i2c";
@@ -589,8 +589,8 @@
589 GPIO_ACTIVE_HIGH>; 589 GPIO_ACTIVE_HIGH>;
590 590
591 clocks = <&tegra_car TEGRA20_CLK_PLL_A>, 591 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
592 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, 592 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
593 <&tegra_car TEGRA20_CLK_CDEV1>; 593 <&tegra_car TEGRA20_CLK_CDEV1>;
594 clock-names = "pll_a", "pll_a_out0", "mclk"; 594 clock-names = "pll_a", "pll_a_out0", "mclk";
595 }; 595 };
596}; 596};
diff --git a/arch/arm/boot/dts/tegra20-plutux.dts b/arch/arm/boot/dts/tegra20-plutux.dts
index 29051a2ae0ae..a10b415bbdee 100644
--- a/arch/arm/boot/dts/tegra20-plutux.dts
+++ b/arch/arm/boot/dts/tegra20-plutux.dts
@@ -58,4 +58,45 @@
58 <&tegra_car TEGRA20_CLK_CDEV1>; 58 <&tegra_car TEGRA20_CLK_CDEV1>;
59 clock-names = "pll_a", "pll_a_out0", "mclk"; 59 clock-names = "pll_a", "pll_a_out0", "mclk";
60 }; 60 };
61
62 regulators {
63 vcc_24v_reg: regulator@100 {
64 compatible = "regulator-fixed";
65 reg = <100>;
66 regulator-name = "vcc_24v";
67 regulator-min-microvolt = <24000000>;
68 regulator-max-microvolt = <24000000>;
69 regulator-always-on;
70 };
71
72 vdd_5v0_reg: regulator@101 {
73 compatible = "regulator-fixed";
74 reg = <101>;
75 regulator-name = "vdd_5v0";
76 vin-supply = <&vcc_24v_reg>;
77 regulator-min-microvolt = <5000000>;
78 regulator-max-microvolt = <5000000>;
79 regulator-always-on;
80 };
81
82 vdd_3v3_reg: regulator@102 {
83 compatible = "regulator-fixed";
84 reg = <102>;
85 regulator-name = "vdd_3v3";
86 vin-supply = <&vcc_24v_reg>;
87 regulator-min-microvolt = <3300000>;
88 regulator-max-microvolt = <3300000>;
89 regulator-always-on;
90 };
91
92 vdd_1v8_reg: regulator@103 {
93 compatible = "regulator-fixed";
94 reg = <103>;
95 regulator-name = "vdd_1v8";
96 vin-supply = <&vdd_3v3_reg>;
97 regulator-min-microvolt = <1800000>;
98 regulator-max-microvolt = <1800000>;
99 regulator-always-on;
100 };
101 };
61}; 102};
diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi
index a1b0d965757f..9c8318538a11 100644
--- a/arch/arm/boot/dts/tegra20-tamonten.dtsi
+++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi
@@ -334,6 +334,7 @@
334 #gpio-cells = <2>; 334 #gpio-cells = <2>;
335 gpio-controller; 335 gpio-controller;
336 336
337 /* vdd_5v0_reg must be provided by the base board */
337 sys-supply = <&vdd_5v0_reg>; 338 sys-supply = <&vdd_5v0_reg>;
338 vin-sm0-supply = <&sys_reg>; 339 vin-sm0-supply = <&sys_reg>;
339 vin-sm1-supply = <&sys_reg>; 340 vin-sm1-supply = <&sys_reg>;
@@ -511,15 +512,6 @@
511 #address-cells = <1>; 512 #address-cells = <1>;
512 #size-cells = <0>; 513 #size-cells = <0>;
513 514
514 vdd_5v0_reg: regulator@0 {
515 compatible = "regulator-fixed";
516 reg = <0>;
517 regulator-name = "vdd_5v0";
518 regulator-min-microvolt = <5000000>;
519 regulator-max-microvolt = <5000000>;
520 regulator-always-on;
521 };
522
523 pci_vdd_reg: regulator@1 { 515 pci_vdd_reg: regulator@1 {
524 compatible = "regulator-fixed"; 516 compatible = "regulator-fixed";
525 reg = <1>; 517 reg = <1>;
diff --git a/arch/arm/boot/dts/tegra20-tec.dts b/arch/arm/boot/dts/tegra20-tec.dts
index 890562c667fb..c12d8bead2ee 100644
--- a/arch/arm/boot/dts/tegra20-tec.dts
+++ b/arch/arm/boot/dts/tegra20-tec.dts
@@ -67,4 +67,45 @@
67 <&tegra_car TEGRA20_CLK_CDEV1>; 67 <&tegra_car TEGRA20_CLK_CDEV1>;
68 clock-names = "pll_a", "pll_a_out0", "mclk"; 68 clock-names = "pll_a", "pll_a_out0", "mclk";
69 }; 69 };
70
71 regulators {
72 vcc_24v_reg: regulator@100 {
73 compatible = "regulator-fixed";
74 reg = <100>;
75 regulator-name = "vcc_24v";
76 regulator-min-microvolt = <24000000>;
77 regulator-max-microvolt = <24000000>;
78 regulator-always-on;
79 };
80
81 vdd_5v0_reg: regulator@101 {
82 compatible = "regulator-fixed";
83 reg = <101>;
84 regulator-name = "vdd_5v0";
85 vin-supply = <&vcc_24v_reg>;
86 regulator-min-microvolt = <5000000>;
87 regulator-max-microvolt = <5000000>;
88 regulator-always-on;
89 };
90
91 vdd_3v3_reg: regulator@102 {
92 compatible = "regulator-fixed";
93 reg = <102>;
94 regulator-name = "vdd_3v3";
95 vin-supply = <&vcc_24v_reg>;
96 regulator-min-microvolt = <3300000>;
97 regulator-max-microvolt = <3300000>;
98 regulator-always-on;
99 };
100
101 vdd_1v8_reg: regulator@103 {
102 compatible = "regulator-fixed";
103 reg = <103>;
104 regulator-name = "vdd_1v8";
105 vin-supply = <&vdd_3v3_reg>;
106 regulator-min-microvolt = <1800000>;
107 regulator-max-microvolt = <1800000>;
108 regulator-always-on;
109 };
110 };
70}; 111};
diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts
new file mode 100644
index 000000000000..45d40f024585
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts
@@ -0,0 +1,260 @@
1/dts-v1/;
2
3#include <dt-bindings/input/input.h>
4#include "tegra30-apalis.dtsi"
5
6/ {
7 model = "Toradex Apalis T30 on Apalis Evaluation Board";
8 compatible = "toradex,apalis_t30-eval", "toradex,apalis_t30", "nvidia,tegra30";
9
10 aliases {
11 rtc0 = "/i2c@7000c000/rtc@68";
12 rtc1 = "/i2c@7000d000/tps65911@2d";
13 rtc2 = "/rtc@7000e000";
14 };
15
16 pcie-controller@00003000 {
17 status = "okay";
18
19 pci@1,0 {
20 status = "okay";
21 };
22
23 pci@2,0 {
24 status = "okay";
25 };
26
27 pci@3,0 {
28 status = "okay";
29 };
30 };
31
32 host1x@50000000 {
33 dc@54200000 {
34 rgb {
35 status = "okay";
36 nvidia,panel = <&panel>;
37 };
38 };
39 hdmi@54280000 {
40 status = "okay";
41 };
42 };
43
44 serial@70006000 {
45 status = "okay";
46 };
47
48 serial@70006040 {
49 compatible = "nvidia,tegra30-hsuart";
50 status = "okay";
51 };
52
53 serial@70006200 {
54 compatible = "nvidia,tegra30-hsuart";
55 status = "okay";
56 };
57
58 serial@70006300 {
59 compatible = "nvidia,tegra30-hsuart";
60 status = "okay";
61 };
62
63 pwm@7000a000 {
64 status = "okay";
65 };
66
67 /*
68 * GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier
69 * board)
70 */
71 i2c@7000c000 {
72 status = "okay";
73 clock-frequency = <100000>;
74
75 pcie-switch@58 {
76 compatible = "plx,pex8605";
77 reg = <0x58>;
78 };
79
80 /* M41T0M6 real time clock on carrier board */
81 rtc@68 {
82 compatible = "st,m41t00";
83 reg = <0x68>;
84 };
85 };
86
87 /* GEN2_I2C: unused */
88
89 /*
90 * CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on
91 * carrier board)
92 */
93 cami2c: i2c@7000c500 {
94 status = "okay";
95 clock-frequency = <400000>;
96 };
97
98 /* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */
99 hdmiddc: i2c@7000c700 {
100 status = "okay";
101 };
102
103 /* SPI1: Apalis SPI1 */
104 spi@7000d400 {
105 status = "okay";
106 spi-max-frequency = <25000000>;
107 spidev0: spidev@1 {
108 compatible = "spidev";
109 reg = <1>;
110 spi-max-frequency = <25000000>;
111 };
112 };
113
114 /* SPI5: Apalis SPI2 */
115 spi@7000dc00 {
116 status = "okay";
117 spi-max-frequency = <25000000>;
118 spidev1: spidev@2 {
119 compatible = "spidev";
120 reg = <2>;
121 spi-max-frequency = <25000000>;
122 };
123 };
124
125 sd1: sdhci@78000000 {
126 status = "okay";
127 bus-width = <4>;
128 /* SD1_CD# */
129 cd-gpios = <&gpio TEGRA_GPIO(CC, 5) GPIO_ACTIVE_LOW>;
130 no-1-8-v;
131 };
132
133 mmc1: sdhci@78000400 {
134 status = "okay";
135 bus-width = <8>;
136 /* MMC1_CD# */
137 cd-gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
138 no-1-8-v;
139 };
140
141 /* EHCI instance 0: USB1_DP/N -> USBO1_DP/N */
142 usb@7d000000 {
143 status = "okay";
144 };
145
146 usb-phy@7d000000 {
147 status = "okay";
148 vbus-supply = <&usbo1_vbus_reg>;
149 };
150
151 /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */
152 usb@7d004000 {
153 status = "okay";
154 };
155
156 usb-phy@7d004000 {
157 status = "okay";
158 vbus-supply = <&usbh_vbus_reg>;
159 };
160
161 /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */
162 usb@7d008000 {
163 status = "okay";
164 };
165
166 usb-phy@7d008000 {
167 status = "okay";
168 vbus-supply = <&usbh_vbus_reg>;
169 };
170
171 backlight: backlight {
172 compatible = "pwm-backlight";
173
174 /* PWM0 */
175 pwms = <&pwm 0 5000000>;
176 brightness-levels = <255 231 223 207 191 159 127 0>;
177 default-brightness-level = <6>;
178 /* BKL1_ON */
179 enable-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
180 };
181
182 gpio-keys {
183 compatible = "gpio-keys";
184
185 power {
186 label = "Power";
187 gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
188 linux,code = <KEY_POWER>;
189 debounce-interval = <10>;
190 gpio-key,wakeup;
191 };
192 };
193
194 panel: panel {
195 /*
196 * edt,et057090dhu: EDT 5.7" LCD TFT
197 * edt,et070080dh6: EDT 7.0" LCD TFT
198 */
199 compatible = "edt,et057090dhu", "simple-panel";
200
201 backlight = <&backlight>;
202 };
203
204 pwmleds {
205 compatible = "pwm-leds";
206
207 pwm1 {
208 label = "PWM1";
209 pwms = <&pwm 3 19600>;
210 max-brightness = <255>;
211 };
212
213 pwm2 {
214 label = "PWM2";
215 pwms = <&pwm 2 19600>;
216 max-brightness = <255>;
217 };
218
219 pwm3 {
220 label = "PWM3";
221 pwms = <&pwm 1 19600>;
222 max-brightness = <255>;
223 };
224 };
225
226 regulators {
227 sys_5v0_reg: regulator@1 {
228 compatible = "regulator-fixed";
229 reg = <1>;
230 regulator-name = "5v0";
231 regulator-min-microvolt = <5000000>;
232 regulator-max-microvolt = <5000000>;
233 regulator-always-on;
234 };
235
236 /* USBO1_EN */
237 usbo1_vbus_reg: regulator@2 {
238 compatible = "regulator-fixed";
239 reg = <2>;
240 regulator-name = "usbo1_vbus";
241 regulator-min-microvolt = <5000000>;
242 regulator-max-microvolt = <5000000>;
243 gpio = <&gpio TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
244 enable-active-high;
245 vin-supply = <&sys_5v0_reg>;
246 };
247
248 /* USBH_EN */
249 usbh_vbus_reg: regulator@3 {
250 compatible = "regulator-fixed";
251 reg = <3>;
252 regulator-name = "usbh_vbus";
253 regulator-min-microvolt = <5000000>;
254 regulator-max-microvolt = <5000000>;
255 gpio = <&gpio TEGRA_GPIO(DD, 1) GPIO_ACTIVE_HIGH>;
256 enable-active-high;
257 vin-supply = <&sys_5v0_reg>;
258 };
259 };
260};
diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi
new file mode 100644
index 000000000000..8adaa7871dd3
--- /dev/null
+++ b/arch/arm/boot/dts/tegra30-apalis.dtsi
@@ -0,0 +1,678 @@
1#include "tegra30.dtsi"
2
3/*
4 * Toradex Apalis T30 Device Tree
5 * Compatible for Revisions 1GB: V1.0A; 2GB: V1.0B, V1.0C
6 */
7/ {
8 model = "Toradex Apalis T30";
9 compatible = "toradex,apalis_t30", "nvidia,tegra30";
10
11 pcie-controller@00003000 {
12 avdd-pexa-supply = <&vdd2_reg>;
13 vdd-pexa-supply = <&vdd2_reg>;
14 avdd-pexb-supply = <&vdd2_reg>;
15 vdd-pexb-supply = <&vdd2_reg>;
16 avdd-pex-pll-supply = <&vdd2_reg>;
17 avdd-plle-supply = <&ldo6_reg>;
18 vddio-pex-ctl-supply = <&sys_3v3_reg>;
19 hvdd-pex-supply = <&sys_3v3_reg>;
20
21 pci@1,0 {
22 nvidia,num-lanes = <4>;
23 };
24
25 pci@2,0 {
26 nvidia,num-lanes = <1>;
27 };
28
29 pci@3,0 {
30 nvidia,num-lanes = <1>;
31 };
32 };
33
34 host1x@50000000 {
35 hdmi@54280000 {
36 vdd-supply = <&sys_3v3_reg>;
37 pll-supply = <&vio_reg>;
38
39 nvidia,hpd-gpio =
40 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
41 nvidia,ddc-i2c-bus = <&hdmiddc>;
42 };
43 };
44
45 pinmux@70000868 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&state_default>;
48
49 state_default: pinmux {
50 /* Apalis BKL1_ON */
51 pv2 {
52 nvidia,pins = "pv2";
53 nvidia,function = "rsvd4";
54 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
55 nvidia,tristate = <TEGRA_PIN_DISABLE>;
56 };
57
58 /* Apalis BKL1_PWM */
59 uart3_rts_n_pc0 {
60 nvidia,pins = "uart3_rts_n_pc0";
61 nvidia,function = "pwm0";
62 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
63 nvidia,tristate = <TEGRA_PIN_DISABLE>;
64 };
65 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
66 uart3_cts_n_pa1 {
67 nvidia,pins = "uart3_cts_n_pa1";
68 nvidia,function = "rsvd1";
69 nvidia,pull = <TEGRA_PIN_PULL_UP>;
70 nvidia,tristate = <TEGRA_PIN_DISABLE>;
71 };
72
73 /* Apalis CAN1 on SPI6 */
74 spi2_cs0_n_px3 {
75 nvidia,pins = "spi2_cs0_n_px3",
76 "spi2_miso_px1",
77 "spi2_mosi_px0",
78 "spi2_sck_px2";
79 nvidia,function = "spi6";
80 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
81 nvidia,tristate = <TEGRA_PIN_DISABLE>;
82 };
83 /* CAN_INT1 */
84 spi2_cs1_n_pw2 {
85 nvidia,pins = "spi2_cs1_n_pw2";
86 nvidia,function = "spi3";
87 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
88 nvidia,tristate = <TEGRA_PIN_DISABLE>;
89 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
90 };
91
92 /* Apalis CAN2 on SPI4 */
93 gmi_a16_pj7 {
94 nvidia,pins = "gmi_a16_pj7",
95 "gmi_a17_pb0",
96 "gmi_a18_pb1",
97 "gmi_a19_pk7";
98 nvidia,function = "spi4";
99 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
100 nvidia,tristate = <TEGRA_PIN_DISABLE>;
101 };
102 /* CAN_INT2 */
103 spi2_cs2_n_pw3 {
104 nvidia,pins = "spi2_cs2_n_pw3";
105 nvidia,function = "spi3";
106 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
107 nvidia,tristate = <TEGRA_PIN_DISABLE>;
108 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
109 };
110
111 /* Apalis I2C3 */
112 cam_i2c_scl_pbb1 {
113 nvidia,pins = "cam_i2c_scl_pbb1",
114 "cam_i2c_sda_pbb2";
115 nvidia,function = "i2c3";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
119 nvidia,lock = <TEGRA_PIN_DISABLE>;
120 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
121 };
122
123 /* Apalis MMC1 */
124 sdmmc3_clk_pa6 {
125 nvidia,pins = "sdmmc3_clk_pa6",
126 "sdmmc3_cmd_pa7";
127 nvidia,function = "sdmmc3";
128 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
129 nvidia,tristate = <TEGRA_PIN_DISABLE>;
130 };
131 sdmmc3_dat0_pb7 {
132 nvidia,pins = "sdmmc3_dat0_pb7",
133 "sdmmc3_dat1_pb6",
134 "sdmmc3_dat2_pb5",
135 "sdmmc3_dat3_pb4",
136 "sdmmc3_dat4_pd1",
137 "sdmmc3_dat5_pd0",
138 "sdmmc3_dat6_pd3",
139 "sdmmc3_dat7_pd4";
140 nvidia,function = "sdmmc3";
141 nvidia,pull = <TEGRA_PIN_PULL_UP>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 };
144 /* Apalis MMC1_CD# */
145 pv3 {
146 nvidia,pins = "pv3";
147 nvidia,function = "rsvd2";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
150 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
151 };
152
153 /* Apalis PWM1 */
154 gpio_pu6 {
155 nvidia,pins = "gpio_pu6";
156 nvidia,function = "pwm3";
157 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
158 nvidia,tristate = <TEGRA_PIN_DISABLE>;
159 };
160
161 /* Apalis PWM2 */
162 gpio_pu5 {
163 nvidia,pins = "gpio_pu5";
164 nvidia,function = "pwm2";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 };
168
169 /* Apalis PWM3 */
170 gpio_pu4 {
171 nvidia,pins = "gpio_pu4";
172 nvidia,function = "pwm1";
173 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
174 nvidia,tristate = <TEGRA_PIN_DISABLE>;
175 };
176
177 /* Apalis PWM4 */
178 gpio_pu3 {
179 nvidia,pins = "gpio_pu3";
180 nvidia,function = "pwm0";
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 };
184
185 /* Apalis RESET_MOCI# */
186 gmi_rst_n_pi4 {
187 nvidia,pins = "gmi_rst_n_pi4";
188 nvidia,function = "gmi";
189 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
190 nvidia,tristate = <TEGRA_PIN_DISABLE>;
191 };
192
193 /* Apalis SD1 */
194 sdmmc1_clk_pz0 {
195 nvidia,pins = "sdmmc1_clk_pz0";
196 nvidia,function = "sdmmc1";
197 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
198 nvidia,tristate = <TEGRA_PIN_DISABLE>;
199 };
200 sdmmc1_cmd_pz1 {
201 nvidia,pins = "sdmmc1_cmd_pz1",
202 "sdmmc1_dat0_py7",
203 "sdmmc1_dat1_py6",
204 "sdmmc1_dat2_py5",
205 "sdmmc1_dat3_py4";
206 nvidia,function = "sdmmc1";
207 nvidia,pull = <TEGRA_PIN_PULL_UP>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
209 };
210 /* Apalis SD1_CD# */
211 clk2_req_pcc5 {
212 nvidia,pins = "clk2_req_pcc5";
213 nvidia,function = "rsvd2";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_DISABLE>;
216 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
217 };
218
219 /* Apalis SPI1 */
220 spi1_sck_px5 {
221 nvidia,pins = "spi1_sck_px5",
222 "spi1_mosi_px4",
223 "spi1_miso_px7",
224 "spi1_cs0_n_px6";
225 nvidia,function = "spi1";
226 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
228 };
229
230 /* Apalis SPI2 */
231 lcd_sck_pz4 {
232 nvidia,pins = "lcd_sck_pz4",
233 "lcd_sdout_pn5",
234 "lcd_sdin_pz2",
235 "lcd_cs0_n_pn4";
236 nvidia,function = "spi5";
237 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
238 nvidia,tristate = <TEGRA_PIN_DISABLE>;
239 };
240
241 /* Apalis UART1 */
242 ulpi_data0 {
243 nvidia,pins = "ulpi_data0_po1",
244 "ulpi_data1_po2",
245 "ulpi_data2_po3",
246 "ulpi_data3_po4",
247 "ulpi_data4_po5",
248 "ulpi_data5_po6",
249 "ulpi_data6_po7",
250 "ulpi_data7_po0";
251 nvidia,function = "uarta";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 };
255
256 /* Apalis UART2 */
257 ulpi_clk_py0 {
258 nvidia,pins = "ulpi_clk_py0",
259 "ulpi_dir_py1",
260 "ulpi_nxt_py2",
261 "ulpi_stp_py3";
262 nvidia,function = "uartd";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_DISABLE>;
265 };
266
267 /* Apalis UART3 */
268 uart2_rxd_pc3 {
269 nvidia,pins = "uart2_rxd_pc3",
270 "uart2_txd_pc2";
271 nvidia,function = "uartb";
272 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
273 nvidia,tristate = <TEGRA_PIN_DISABLE>;
274 };
275
276 /* Apalis UART4 */
277 uart3_rxd_pw7 {
278 nvidia,pins = "uart3_rxd_pw7",
279 "uart3_txd_pw6";
280 nvidia,function = "uartc";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
283 };
284
285 /* Apalis USBO1_EN */
286 gen2_i2c_scl_pt5 {
287 nvidia,pins = "gen2_i2c_scl_pt5";
288 nvidia,function = "rsvd4";
289 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
290 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
291 nvidia,tristate = <TEGRA_PIN_DISABLE>;
292 };
293
294 /* Apalis USBO1_OC# */
295 gen2_i2c_sda_pt6 {
296 nvidia,pins = "gen2_i2c_sda_pt6";
297 nvidia,function = "rsvd4";
298 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
299 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
300 nvidia,tristate = <TEGRA_PIN_DISABLE>;
301 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
302 };
303
304 /* Apalis WAKE1_MICO */
305 pv1 {
306 nvidia,pins = "pv1";
307 nvidia,function = "rsvd1";
308 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
309 nvidia,tristate = <TEGRA_PIN_DISABLE>;
310 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
311 };
312
313 /* eMMC (On-module) */
314 sdmmc4_clk_pcc4 {
315 nvidia,pins = "sdmmc4_clk_pcc4",
316 "sdmmc4_rst_n_pcc3";
317 nvidia,function = "sdmmc4";
318 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
319 nvidia,tristate = <TEGRA_PIN_DISABLE>;
320 };
321 sdmmc4_dat0_paa0 {
322 nvidia,pins = "sdmmc4_dat0_paa0",
323 "sdmmc4_dat1_paa1",
324 "sdmmc4_dat2_paa2",
325 "sdmmc4_dat3_paa3",
326 "sdmmc4_dat4_paa4",
327 "sdmmc4_dat5_paa5",
328 "sdmmc4_dat6_paa6",
329 "sdmmc4_dat7_paa7";
330 nvidia,function = "sdmmc4";
331 nvidia,pull = <TEGRA_PIN_PULL_UP>;
332 nvidia,tristate = <TEGRA_PIN_DISABLE>;
333 };
334
335 /* LVDS Transceiver Configuration */
336 pbb0 {
337 nvidia,pins = "pbb0",
338 "pbb7",
339 "pcc1",
340 "pcc2";
341 nvidia,function = "rsvd2";
342 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
343 nvidia,tristate = <TEGRA_PIN_DISABLE>;
344 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
345 nvidia,lock = <TEGRA_PIN_DISABLE>;
346 };
347 pbb3 {
348 nvidia,pins = "pbb3",
349 "pbb4",
350 "pbb5",
351 "pbb6";
352 nvidia,function = "displayb";
353 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
354 nvidia,tristate = <TEGRA_PIN_DISABLE>;
355 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
356 nvidia,lock = <TEGRA_PIN_DISABLE>;
357 };
358
359 /* Power I2C (On-module) */
360 pwr_i2c_scl_pz6 {
361 nvidia,pins = "pwr_i2c_scl_pz6",
362 "pwr_i2c_sda_pz7";
363 nvidia,function = "i2cpwr";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
367 nvidia,lock = <TEGRA_PIN_DISABLE>;
368 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
369 };
370
371 /*
372 * THERMD_ALERT#, unlatched I2C address pin of LM95245
373 * temperature sensor therefore requires disabling for
374 * now
375 */
376 lcd_dc1_pd2 {
377 nvidia,pins = "lcd_dc1_pd2";
378 nvidia,function = "rsvd3";
379 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
380 nvidia,tristate = <TEGRA_PIN_DISABLE>;
381 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
382 };
383
384 /* TOUCH_PEN_INT# */
385 pv0 {
386 nvidia,pins = "pv0";
387 nvidia,function = "rsvd1";
388 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
389 nvidia,tristate = <TEGRA_PIN_DISABLE>;
390 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
391 };
392 };
393 };
394
395 hdmiddc: i2c@7000c700 {
396 clock-frequency = <100000>;
397 };
398
399 /*
400 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
401 * touch screen controller
402 */
403 i2c@7000d000 {
404 status = "okay";
405 clock-frequency = <100000>;
406
407 pmic: tps65911@2d {
408 compatible = "ti,tps65911";
409 reg = <0x2d>;
410
411 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
412 #interrupt-cells = <2>;
413 interrupt-controller;
414
415 ti,system-power-controller;
416
417 #gpio-cells = <2>;
418 gpio-controller;
419
420 vcc1-supply = <&sys_3v3_reg>;
421 vcc2-supply = <&sys_3v3_reg>;
422 vcc3-supply = <&vio_reg>;
423 vcc4-supply = <&sys_3v3_reg>;
424 vcc5-supply = <&sys_3v3_reg>;
425 vcc6-supply = <&vio_reg>;
426 vcc7-supply = <&sys_5v0_reg>;
427 vccio-supply = <&sys_3v3_reg>;
428
429 regulators {
430 /* SW1: +V1.35_VDDIO_DDR */
431 vdd1_reg: vdd1 {
432 regulator-name = "vddio_ddr_1v35";
433 regulator-min-microvolt = <1350000>;
434 regulator-max-microvolt = <1350000>;
435 regulator-always-on;
436 };
437
438 /* SW2: +V1.05 */
439 vdd2_reg: vdd2 {
440 regulator-name =
441 "vdd_pexa,vdd_pexb,vdd_sata";
442 regulator-min-microvolt = <1050000>;
443 regulator-max-microvolt = <1050000>;
444 };
445
446 /* SW CTRL: +V1.0_VDD_CPU */
447 vddctrl_reg: vddctrl {
448 regulator-name = "vdd_cpu,vdd_sys";
449 regulator-min-microvolt = <1150000>;
450 regulator-max-microvolt = <1150000>;
451 regulator-always-on;
452 };
453
454 /* SWIO: +V1.8 */
455 vio_reg: vio {
456 regulator-name = "vdd_1v8_gen";
457 regulator-min-microvolt = <1800000>;
458 regulator-max-microvolt = <1800000>;
459 regulator-always-on;
460 };
461
462 /* LDO1: unused */
463
464 /*
465 * EN_+V3.3 switching via FET:
466 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
467 * see also v3_3 fixed supply
468 */
469 ldo2_reg: ldo2 {
470 regulator-name = "en_3v3";
471 regulator-min-microvolt = <3300000>;
472 regulator-max-microvolt = <3300000>;
473 regulator-always-on;
474 };
475
476 /* +V1.2_CSI */
477 ldo3_reg: ldo3 {
478 regulator-name =
479 "avdd_dsi_csi,pwrdet_mipi";
480 regulator-min-microvolt = <1200000>;
481 regulator-max-microvolt = <1200000>;
482 };
483
484 /* +V1.2_VDD_RTC */
485 ldo4_reg: ldo4 {
486 regulator-name = "vdd_rtc";
487 regulator-min-microvolt = <1200000>;
488 regulator-max-microvolt = <1200000>;
489 regulator-always-on;
490 };
491
492 /*
493 * +V2.8_AVDD_VDAC:
494 * only required for analog RGB
495 */
496 ldo5_reg: ldo5 {
497 regulator-name = "avdd_vdac";
498 regulator-min-microvolt = <2800000>;
499 regulator-max-microvolt = <2800000>;
500 regulator-always-on;
501 };
502
503 /*
504 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
505 * but LDO6 can't set voltage in 50mV
506 * granularity
507 */
508 ldo6_reg: ldo6 {
509 regulator-name = "avdd_plle";
510 regulator-min-microvolt = <1100000>;
511 regulator-max-microvolt = <1100000>;
512 };
513
514 /* +V1.2_AVDD_PLL */
515 ldo7_reg: ldo7 {
516 regulator-name = "avdd_pll";
517 regulator-min-microvolt = <1200000>;
518 regulator-max-microvolt = <1200000>;
519 regulator-always-on;
520 };
521
522 /* +V1.0_VDD_DDR_HS */
523 ldo8_reg: ldo8 {
524 regulator-name = "vdd_ddr_hs";
525 regulator-min-microvolt = <1000000>;
526 regulator-max-microvolt = <1000000>;
527 regulator-always-on;
528 };
529 };
530 };
531
532 /* STMPE811 touch screen controller */
533 stmpe811@41 {
534 compatible = "st,stmpe811";
535 #address-cells = <1>;
536 #size-cells = <0>;
537 reg = <0x41>;
538 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
539 interrupt-parent = <&gpio>;
540 interrupt-controller;
541 id = <0>;
542 blocks = <0x5>;
543 irq-trigger = <0x1>;
544
545 stmpe_touchscreen {
546 compatible = "st,stmpe-ts";
547 reg = <0>;
548 /* 3.25 MHz ADC clock speed */
549 st,adc-freq = <1>;
550 /* 8 sample average control */
551 st,ave-ctrl = <3>;
552 /* 7 length fractional part in z */
553 st,fraction-z = <7>;
554 /*
555 * 50 mA typical 80 mA max touchscreen drivers
556 * current limit value
557 */
558 st,i-drive = <1>;
559 /* 12-bit ADC */
560 st,mod-12b = <1>;
561 /* internal ADC reference */
562 st,ref-sel = <0>;
563 /* ADC converstion time: 80 clocks */
564 st,sample-time = <4>;
565 /* 1 ms panel driver settling time */
566 st,settling = <3>;
567 /* 5 ms touch detect interrupt delay */
568 st,touch-det-delay = <5>;
569 };
570 };
571
572 /*
573 * LM95245 temperature sensor
574 * Note: OVERT_N directly connected to PMIC PWRDN
575 */
576 temp-sensor@4c {
577 compatible = "national,lm95245";
578 reg = <0x4c>;
579 };
580
581 /* SW: +V1.2_VDD_CORE */
582 tps62362@60 {
583 compatible = "ti,tps62362";
584 reg = <0x60>;
585
586 regulator-name = "tps62362-vout";
587 regulator-min-microvolt = <900000>;
588 regulator-max-microvolt = <1400000>;
589 regulator-boot-on;
590 regulator-always-on;
591 ti,vsel0-state-low;
592 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
593 ti,vsel1-state-low;
594 };
595 };
596
597 /* SPI4: CAN2 */
598 spi@7000da00 {
599 status = "okay";
600 spi-max-frequency = <10000000>;
601
602 can@1 {
603 compatible = "microchip,mcp2515";
604 reg = <1>;
605 clocks = <&clk16m>;
606 interrupt-parent = <&gpio>;
607 interrupts = <TEGRA_GPIO(W, 3) GPIO_ACTIVE_LOW>;
608 spi-max-frequency = <10000000>;
609 };
610 };
611
612 /* SPI6: CAN1 */
613 spi@7000de00 {
614 status = "okay";
615 spi-max-frequency = <10000000>;
616
617 can@0 {
618 compatible = "microchip,mcp2515";
619 reg = <0>;
620 clocks = <&clk16m>;
621 interrupt-parent = <&gpio>;
622 interrupts = <TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
623 spi-max-frequency = <10000000>;
624 };
625 };
626
627 pmc@7000e400 {
628 nvidia,invert-interrupt;
629 nvidia,suspend-mode = <1>;
630 nvidia,cpu-pwr-good-time = <5000>;
631 nvidia,cpu-pwr-off-time = <5000>;
632 nvidia,core-pwr-good-time = <3845 3845>;
633 nvidia,core-pwr-off-time = <0>;
634 nvidia,core-power-req-active-high;
635 nvidia,sys-clock-req-active-high;
636 };
637
638 sdhci@78000600 {
639 status = "okay";
640 bus-width = <8>;
641 non-removable;
642 };
643
644 clocks {
645 compatible = "simple-bus";
646 #address-cells = <1>;
647 #size-cells = <0>;
648
649 clk32k_in: clk@0 {
650 compatible = "fixed-clock";
651 reg=<0>;
652 #clock-cells = <0>;
653 clock-frequency = <32768>;
654 };
655 clk16m: clk@1 {
656 compatible = "fixed-clock";
657 reg=<1>;
658 #clock-cells = <0>;
659 clock-frequency = <16000000>;
660 clock-output-names = "clk16m";
661 };
662 };
663
664 regulators {
665 compatible = "simple-bus";
666 #address-cells = <1>;
667 #size-cells = <0>;
668
669 sys_3v3_reg: regulator@100 {
670 compatible = "regulator-fixed";
671 reg = <100>;
672 regulator-name = "3v3";
673 regulator-min-microvolt = <3300000>;
674 regulator-max-microvolt = <3300000>;
675 regulator-always-on;
676 };
677 };
678};
diff --git a/arch/arm/boot/dts/tny_a9260_common.dtsi b/arch/arm/boot/dts/tny_a9260_common.dtsi
index 0e6d3de2e09e..ce7138c3af1b 100644
--- a/arch/arm/boot/dts/tny_a9260_common.dtsi
+++ b/arch/arm/boot/dts/tny_a9260_common.dtsi
@@ -24,6 +24,14 @@
24 compatible = "atmel,osc", "fixed-clock"; 24 compatible = "atmel,osc", "fixed-clock";
25 clock-frequency = <12000000>; 25 clock-frequency = <12000000>;
26 }; 26 };
27
28 slow_xtal {
29 clock-frequency = <32768>;
30 };
31
32 main_xtal {
33 clock-frequency = <12000000>;
34 };
27 }; 35 };
28 36
29 ahb { 37 ahb {
diff --git a/arch/arm/boot/dts/tny_a9263.dts b/arch/arm/boot/dts/tny_a9263.dts
index 0751a6a979a8..3043296345b7 100644
--- a/arch/arm/boot/dts/tny_a9263.dts
+++ b/arch/arm/boot/dts/tny_a9263.dts
@@ -29,6 +29,14 @@
29 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>; 30 clock-frequency = <12000000>;
31 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <12000000>;
39 };
32 }; 40 };
33 41
34 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/usb_a9260_common.dtsi b/arch/arm/boot/dts/usb_a9260_common.dtsi
index 285977682cf3..12edafefd44a 100644
--- a/arch/arm/boot/dts/usb_a9260_common.dtsi
+++ b/arch/arm/boot/dts/usb_a9260_common.dtsi
@@ -16,6 +16,14 @@
16 compatible = "atmel,osc", "fixed-clock"; 16 compatible = "atmel,osc", "fixed-clock";
17 clock-frequency = <12000000>; 17 clock-frequency = <12000000>;
18 }; 18 };
19
20 slow_xtal {
21 clock-frequency = <32768>;
22 };
23
24 main_xtal {
25 clock-frequency = <12000000>;
26 };
19 }; 27 };
20 28
21 ahb { 29 ahb {
diff --git a/arch/arm/boot/dts/usb_a9263.dts b/arch/arm/boot/dts/usb_a9263.dts
index 290e60383baf..68c0de36c339 100644
--- a/arch/arm/boot/dts/usb_a9263.dts
+++ b/arch/arm/boot/dts/usb_a9263.dts
@@ -29,6 +29,14 @@
29 compatible = "atmel,osc", "fixed-clock"; 29 compatible = "atmel,osc", "fixed-clock";
30 clock-frequency = <12000000>; 30 clock-frequency = <12000000>;
31 }; 31 };
32
33 slow_xtal {
34 clock-frequency = <32768>;
35 };
36
37 main_xtal {
38 clock-frequency = <12000000>;
39 };
32 }; 40 };
33 41
34 ahb { 42 ahb {
diff --git a/arch/arm/boot/dts/vf610.dtsi b/arch/arm/boot/dts/vf610.dtsi
index 6cc314e7b8fb..583dd363c9dc 100644
--- a/arch/arm/boot/dts/vf610.dtsi
+++ b/arch/arm/boot/dts/vf610.dtsi
@@ -14,6 +14,8 @@
14 14
15/ { 15/ {
16 aliases { 16 aliases {
17 can0 = &can0;
18 can1 = &can1;
17 serial0 = &uart0; 19 serial0 = &uart0;
18 serial1 = &uart1; 20 serial1 = &uart1;
19 serial2 = &uart2; 21 serial2 = &uart2;
@@ -103,6 +105,16 @@
103 <&clks VF610_CLK_DMAMUX1>; 105 <&clks VF610_CLK_DMAMUX1>;
104 }; 106 };
105 107
108 can0: flexcan@40020000 {
109 compatible = "fsl,vf610-flexcan";
110 reg = <0x40020000 0x4000>;
111 interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>;
112 clocks = <&clks VF610_CLK_FLEXCAN0>,
113 <&clks VF610_CLK_FLEXCAN0>;
114 clock-names = "ipg", "per";
115 status = "disabled";
116 };
117
106 uart0: serial@40027000 { 118 uart0: serial@40027000 {
107 compatible = "fsl,vf610-lpuart"; 119 compatible = "fsl,vf610-lpuart";
108 reg = <0x40027000 0x1000>; 120 reg = <0x40027000 0x1000>;
@@ -362,7 +374,7 @@
362 374
363 esdhc1: esdhc@400b2000 { 375 esdhc1: esdhc@400b2000 {
364 compatible = "fsl,imx53-esdhc"; 376 compatible = "fsl,imx53-esdhc";
365 reg = <0x400b2000 0x4000>; 377 reg = <0x400b2000 0x1000>;
366 interrupts = <0 28 0x04>; 378 interrupts = <0 28 0x04>;
367 clocks = <&clks VF610_CLK_IPG_BUS>, 379 clocks = <&clks VF610_CLK_IPG_BUS>,
368 <&clks VF610_CLK_PLATFORM_BUS>, 380 <&clks VF610_CLK_PLATFORM_BUS>,
@@ -405,6 +417,17 @@
405 clock-names = "ipg", "ahb", "ptp"; 417 clock-names = "ipg", "ahb", "ptp";
406 status = "disabled"; 418 status = "disabled";
407 }; 419 };
420
421 can1: flexcan@400d4000 {
422 compatible = "fsl,vf610-flexcan";
423 reg = <0x400d4000 0x4000>;
424 interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&clks VF610_CLK_FLEXCAN1>,
426 <&clks VF610_CLK_FLEXCAN1>;
427 clock-names = "ipg", "per";
428 status = "disabled";
429 };
430
408 }; 431 };
409 }; 432 };
410}; 433};
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 760bbc463c5b..6cc83d4c6c76 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -65,6 +65,48 @@
65 interrupt-parent = <&intc>; 65 interrupt-parent = <&intc>;
66 ranges; 66 ranges;
67 67
68 adc@f8007100 {
69 compatible = "xlnx,zynq-xadc-1.00.a";
70 reg = <0xf8007100 0x20>;
71 interrupts = <0 7 4>;
72 interrupt-parent = <&intc>;
73 clocks = <&clkc 12>;
74 };
75
76 can0: can@e0008000 {
77 compatible = "xlnx,zynq-can-1.0";
78 status = "disabled";
79 clocks = <&clkc 19>, <&clkc 36>;
80 clock-names = "can_clk", "pclk";
81 reg = <0xe0008000 0x1000>;
82 interrupts = <0 28 4>;
83 interrupt-parent = <&intc>;
84 tx-fifo-depth = <0x40>;
85 rx-fifo-depth = <0x40>;
86 };
87
88 can1: can@e0009000 {
89 compatible = "xlnx,zynq-can-1.0";
90 status = "disabled";
91 clocks = <&clkc 20>, <&clkc 37>;
92 clock-names = "can_clk", "pclk";
93 reg = <0xe0009000 0x1000>;
94 interrupts = <0 51 4>;
95 interrupt-parent = <&intc>;
96 tx-fifo-depth = <0x40>;
97 rx-fifo-depth = <0x40>;
98 };
99
100 gpio0: gpio@e000a000 {
101 compatible = "xlnx,zynq-gpio-1.0";
102 #gpio-cells = <2>;
103 clocks = <&clkc 42>;
104 gpio-controller;
105 interrupt-parent = <&intc>;
106 interrupts = <0 20 4>;
107 reg = <0xe000a000 0x1000>;
108 };
109
68 i2c0: i2c@e0004000 { 110 i2c0: i2c@e0004000 {
69 compatible = "cdns,i2c-r1p10"; 111 compatible = "cdns,i2c-r1p10";
70 status = "disabled"; 112 status = "disabled";
@@ -105,23 +147,47 @@
105 }; 147 };
106 148
107 uart0: serial@e0000000 { 149 uart0: serial@e0000000 {
108 compatible = "xlnx,xuartps"; 150 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
109 status = "disabled"; 151 status = "disabled";
110 clocks = <&clkc 23>, <&clkc 40>; 152 clocks = <&clkc 23>, <&clkc 40>;
111 clock-names = "ref_clk", "aper_clk"; 153 clock-names = "uart_clk", "pclk";
112 reg = <0xE0000000 0x1000>; 154 reg = <0xE0000000 0x1000>;
113 interrupts = <0 27 4>; 155 interrupts = <0 27 4>;
114 }; 156 };
115 157
116 uart1: serial@e0001000 { 158 uart1: serial@e0001000 {
117 compatible = "xlnx,xuartps"; 159 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
118 status = "disabled"; 160 status = "disabled";
119 clocks = <&clkc 24>, <&clkc 41>; 161 clocks = <&clkc 24>, <&clkc 41>;
120 clock-names = "ref_clk", "aper_clk"; 162 clock-names = "uart_clk", "pclk";
121 reg = <0xE0001000 0x1000>; 163 reg = <0xE0001000 0x1000>;
122 interrupts = <0 50 4>; 164 interrupts = <0 50 4>;
123 }; 165 };
124 166
167 spi0: spi@e0006000 {
168 compatible = "xlnx,zynq-spi-r1p6";
169 reg = <0xe0006000 0x1000>;
170 status = "disabled";
171 interrupt-parent = <&intc>;
172 interrupts = <0 26 4>;
173 clocks = <&clkc 25>, <&clkc 34>;
174 clock-names = "ref_clk", "pclk";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 };
178
179 spi1: spi@e0007000 {
180 compatible = "xlnx,zynq-spi-r1p6";
181 reg = <0xe0007000 0x1000>;
182 status = "disabled";
183 interrupt-parent = <&intc>;
184 interrupts = <0 49 4>;
185 clocks = <&clkc 26>, <&clkc 35>;
186 clock-names = "ref_clk", "pclk";
187 #address-cells = <1>;
188 #size-cells = <0>;
189 };
190
125 gem0: ethernet@e000b000 { 191 gem0: ethernet@e000b000 {
126 compatible = "cdns,gem"; 192 compatible = "cdns,gem";
127 reg = <0xe000b000 0x4000>; 193 reg = <0xe000b000 0x4000>;
@@ -186,6 +252,22 @@
186 }; 252 };
187 }; 253 };
188 254
255 dmac_s: dmac@f8003000 {
256 compatible = "arm,pl330", "arm,primecell";
257 reg = <0xf8003000 0x1000>;
258 interrupt-parent = <&intc>;
259 interrupts = <0 13 4>,
260 <0 14 4>, <0 15 4>,
261 <0 16 4>, <0 17 4>,
262 <0 40 4>, <0 41 4>,
263 <0 42 4>, <0 43 4>;
264 #dma-cells = <1>;
265 #dma-channels = <8>;
266 #dma-requests = <4>;
267 clocks = <&clkc 27>;
268 clock-names = "apb_pclk";
269 };
270
189 devcfg: devcfg@f8007000 { 271 devcfg: devcfg@f8007000 {
190 compatible = "xlnx,zynq-devcfg-1.0"; 272 compatible = "xlnx,zynq-devcfg-1.0";
191 reg = <0xf8007000 0x100>; 273 reg = <0xf8007000 0x100>;
diff --git a/arch/arm/boot/dts/zynq-parallella.dts b/arch/arm/boot/dts/zynq-parallella.dts
new file mode 100644
index 000000000000..41afd9da6876
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-parallella.dts
@@ -0,0 +1,64 @@
1/*
2 * Copyright (c) 2014 SUSE LINUX Products GmbH
3 *
4 * Derived from zynq-zed.dts:
5 *
6 * Copyright (C) 2011 Xilinx
7 * Copyright (C) 2012 National Instruments Corp.
8 * Copyright (C) 2013 Xilinx
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 */
19/dts-v1/;
20/include/ "zynq-7000.dtsi"
21
22/ {
23 model = "Adapteva Parallella Board";
24 compatible = "adapteva,parallella", "xlnx,zynq-7000";
25
26 memory {
27 device_type = "memory";
28 reg = <0 0x40000000>;
29 };
30
31 chosen {
32 bootargs = "console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait";
33 linux,stdout-path = "/amba/serial@e0001000";
34 };
35};
36
37&gem0 {
38 status = "okay";
39 phy-mode = "rgmii-id";
40 phy-handle = <&ethernet_phy>;
41 #address-cells = <1>;
42 #size-cells = <0>;
43
44 ethernet_phy: ethernet-phy@0 {
45 /* Marvell 88E1318 */
46 compatible = "ethernet-phy-id0141.0e90",
47 "ethernet-phy-ieee802.3-c22";
48 reg = <0>;
49 marvell,reg-init = <0x3 0x10 0xff00 0x1e>,
50 <0x3 0x11 0xfff0 0xa>;
51 };
52};
53
54&i2c0 {
55 status = "okay";
56};
57
58&sdhci1 {
59 status = "okay";
60};
61
62&uart1 {
63 status = "okay";
64};
diff --git a/arch/arm/boot/dts/zynq-zc702.dts b/arch/arm/boot/dts/zynq-zc702.dts
index 5e09cee33d42..835c3089c61c 100644
--- a/arch/arm/boot/dts/zynq-zc702.dts
+++ b/arch/arm/boot/dts/zynq-zc702.dts
@@ -29,6 +29,10 @@
29 29
30}; 30};
31 31
32&can0 {
33 status = "okay";
34};
35
32&gem0 { 36&gem0 {
33 status = "okay"; 37 status = "okay";
34 phy-mode = "rgmii"; 38 phy-mode = "rgmii";
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 536a137863cb..f650f00e8cee 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -180,6 +180,7 @@ CONFIG_TWL4030_WATCHDOG=y
180CONFIG_MFD_SYSCON=y 180CONFIG_MFD_SYSCON=y
181CONFIG_MFD_PALMAS=y 181CONFIG_MFD_PALMAS=y
182CONFIG_MFD_TPS65217=y 182CONFIG_MFD_TPS65217=y
183CONFIG_MFD_TPS65218=y
183CONFIG_MFD_TPS65910=y 184CONFIG_MFD_TPS65910=y
184CONFIG_TWL6040_CORE=y 185CONFIG_TWL6040_CORE=y
185CONFIG_REGULATOR_FIXED_VOLTAGE=y 186CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -188,6 +189,7 @@ CONFIG_REGULATOR_TI_ABB=y
188CONFIG_REGULATOR_TPS65023=y 189CONFIG_REGULATOR_TPS65023=y
189CONFIG_REGULATOR_TPS6507X=y 190CONFIG_REGULATOR_TPS6507X=y
190CONFIG_REGULATOR_TPS65217=y 191CONFIG_REGULATOR_TPS65217=y
192CONFIG_REGULATOR_TPS65218=y
191CONFIG_REGULATOR_TPS65910=y 193CONFIG_REGULATOR_TPS65910=y
192CONFIG_REGULATOR_TWL4030=y 194CONFIG_REGULATOR_TWL4030=y
193CONFIG_REGULATOR_PBIAS=y 195CONFIG_REGULATOR_PBIAS=y
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 45b55e0f0db6..6cc6f7aebdae 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -113,14 +113,12 @@ config SOC_AT91RM9200
113 select HAVE_AT91_DBGU0 113 select HAVE_AT91_DBGU0
114 select MULTI_IRQ_HANDLER 114 select MULTI_IRQ_HANDLER
115 select SPARSE_IRQ 115 select SPARSE_IRQ
116 select AT91_USE_OLD_CLK
117 select HAVE_AT91_USB_CLK 116 select HAVE_AT91_USB_CLK
118 117
119config SOC_AT91SAM9260 118config SOC_AT91SAM9260
120 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20" 119 bool "AT91SAM9260, AT91SAM9XE or AT91SAM9G20"
121 select HAVE_AT91_DBGU0 120 select HAVE_AT91_DBGU0
122 select SOC_AT91SAM9 121 select SOC_AT91SAM9
123 select AT91_USE_OLD_CLK
124 select HAVE_AT91_USB_CLK 122 select HAVE_AT91_USB_CLK
125 help 123 help
126 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE 124 Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
@@ -140,7 +138,6 @@ config SOC_AT91SAM9263
140 select HAVE_AT91_DBGU1 138 select HAVE_AT91_DBGU1
141 select HAVE_FB_ATMEL 139 select HAVE_FB_ATMEL
142 select SOC_AT91SAM9 140 select SOC_AT91SAM9
143 select AT91_USE_OLD_CLK
144 select HAVE_AT91_USB_CLK 141 select HAVE_AT91_USB_CLK
145 142
146config SOC_AT91SAM9RL 143config SOC_AT91SAM9RL
@@ -155,7 +152,6 @@ config SOC_AT91SAM9G45
155 select HAVE_AT91_DBGU1 152 select HAVE_AT91_DBGU1
156 select HAVE_FB_ATMEL 153 select HAVE_FB_ATMEL
157 select SOC_AT91SAM9 154 select SOC_AT91SAM9
158 select AT91_USE_OLD_CLK
159 select HAVE_AT91_UTMI 155 select HAVE_AT91_UTMI
160 select HAVE_AT91_USB_CLK 156 select HAVE_AT91_USB_CLK
161 help 157 help
diff --git a/arch/arm/mach-at91/at91rm9200.c b/arch/arm/mach-at91/at91rm9200.c
index 787bb50a4dff..038702ee8bc6 100644
--- a/arch/arm/mach-at91/at91rm9200.c
+++ b/arch/arm/mach-at91/at91rm9200.c
@@ -26,10 +26,11 @@
26#include "at91_aic.h" 26#include "at91_aic.h"
27#include "soc.h" 27#include "soc.h"
28#include "generic.h" 28#include "generic.h"
29#include "clock.h"
30#include "sam9_smc.h" 29#include "sam9_smc.h"
31#include "pm.h" 30#include "pm.h"
32 31
32#if defined(CONFIG_OLD_CLK_AT91)
33#include "clock.h"
33/* -------------------------------------------------------------------- 34/* --------------------------------------------------------------------
34 * Clocks 35 * Clocks
35 * -------------------------------------------------------------------- */ 36 * -------------------------------------------------------------------- */
@@ -277,6 +278,9 @@ static void __init at91rm9200_register_clocks(void)
277 clk_register(&pck2); 278 clk_register(&pck2);
278 clk_register(&pck3); 279 clk_register(&pck3);
279} 280}
281#else
282#define at91rm9200_register_clocks NULL
283#endif
280 284
281/* -------------------------------------------------------------------- 285/* --------------------------------------------------------------------
282 * GPIO 286 * GPIO
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index c3d22be73b7c..3477ba94c4c5 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -27,10 +27,11 @@
27#include "at91_rstc.h" 27#include "at91_rstc.h"
28#include "soc.h" 28#include "soc.h"
29#include "generic.h" 29#include "generic.h"
30#include "clock.h"
31#include "sam9_smc.h" 30#include "sam9_smc.h"
32#include "pm.h" 31#include "pm.h"
33 32
33#if defined(CONFIG_OLD_CLK_AT91)
34#include "clock.h"
34/* -------------------------------------------------------------------- 35/* --------------------------------------------------------------------
35 * Clocks 36 * Clocks
36 * -------------------------------------------------------------------- */ 37 * -------------------------------------------------------------------- */
@@ -288,6 +289,9 @@ static void __init at91sam9260_register_clocks(void)
288 clk_register(&pck0); 289 clk_register(&pck0);
289 clk_register(&pck1); 290 clk_register(&pck1);
290} 291}
292#else
293#define at91sam9260_register_clocks NULL
294#endif
291 295
292/* -------------------------------------------------------------------- 296/* --------------------------------------------------------------------
293 * GPIO 297 * GPIO
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index f30290572293..c07465361947 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -25,10 +25,11 @@
25#include "at91_rstc.h" 25#include "at91_rstc.h"
26#include "soc.h" 26#include "soc.h"
27#include "generic.h" 27#include "generic.h"
28#include "clock.h"
29#include "sam9_smc.h" 28#include "sam9_smc.h"
30#include "pm.h" 29#include "pm.h"
31 30
31#if defined(CONFIG_OLD_CLK_AT91)
32#include "clock.h"
32/* -------------------------------------------------------------------- 33/* --------------------------------------------------------------------
33 * Clocks 34 * Clocks
34 * -------------------------------------------------------------------- */ 35 * -------------------------------------------------------------------- */
@@ -280,6 +281,9 @@ static void __init at91sam9263_register_clocks(void)
280 clk_register(&pck2); 281 clk_register(&pck2);
281 clk_register(&pck3); 282 clk_register(&pck3);
282} 283}
284#else
285#define at91sam9263_register_clocks NULL
286#endif
283 287
284/* -------------------------------------------------------------------- 288/* --------------------------------------------------------------------
285 * GPIO 289 * GPIO
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 9d3d544ac19c..0d5d85797cd6 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -25,10 +25,11 @@
25#include "at91_aic.h" 25#include "at91_aic.h"
26#include "soc.h" 26#include "soc.h"
27#include "generic.h" 27#include "generic.h"
28#include "clock.h"
29#include "sam9_smc.h" 28#include "sam9_smc.h"
30#include "pm.h" 29#include "pm.h"
31 30
31#if defined(CONFIG_OLD_CLK_AT91)
32#include "clock.h"
32/* -------------------------------------------------------------------- 33/* --------------------------------------------------------------------
33 * Clocks 34 * Clocks
34 * -------------------------------------------------------------------- */ 35 * -------------------------------------------------------------------- */
@@ -331,6 +332,9 @@ static void __init at91sam9g45_register_clocks(void)
331 clk_register(&pck0); 332 clk_register(&pck0);
332 clk_register(&pck1); 333 clk_register(&pck1);
333} 334}
335#else
336#define at91sam9g45_register_clocks NULL
337#endif
334 338
335/* -------------------------------------------------------------------- 339/* --------------------------------------------------------------------
336 * GPIO 340 * GPIO
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index c426093bdbd9..6a24e111d6e1 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -252,6 +252,8 @@ static const struct of_device_id exynos_dt_pmu_match[] = {
252 { .compatible = "samsung,exynos4212-pmu" }, 252 { .compatible = "samsung,exynos4212-pmu" },
253 { .compatible = "samsung,exynos4412-pmu" }, 253 { .compatible = "samsung,exynos4412-pmu" },
254 { .compatible = "samsung,exynos5250-pmu" }, 254 { .compatible = "samsung,exynos5250-pmu" },
255 { .compatible = "samsung,exynos5260-pmu" },
256 { .compatible = "samsung,exynos5410-pmu" },
255 { .compatible = "samsung,exynos5420-pmu" }, 257 { .compatible = "samsung,exynos5420-pmu" },
256 { /*sentinel*/ }, 258 { /*sentinel*/ },
257}; 259};
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 4481b6867902..69bbcba8842f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -176,13 +176,11 @@ obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
176 176
177# Clock framework 177# Clock framework
178obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 178obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
179obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
180obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o 179obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
181obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o 180obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
182obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o 181obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o
183obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o 182obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
184obj-$(CONFIG_SOC_OMAP2420) += cclock2420_data.o 183obj-$(CONFIG_SOC_OMAP2430) += clock2430.o
185obj-$(CONFIG_SOC_OMAP2430) += clock2430.o cclock2430_data.o
186obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o 184obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
187obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o 185obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
188obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o 186obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
deleted file mode 100644
index 3662f4d4c8ea..000000000000
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ /dev/null
@@ -1,1931 +0,0 @@
1/*
2 * OMAP2420 clock data
3 *
4 * Copyright (C) 2005-2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 * Updated to COMMON clk format by Rajendra Nayak <rnayak@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17#include <linux/kernel.h>
18#include <linux/io.h>
19#include <linux/clk.h>
20#include <linux/clk-private.h>
21#include <linux/list.h>
22
23#include "soc.h"
24#include "iomap.h"
25#include "clock.h"
26#include "clock2xxx.h"
27#include "opp2xxx.h"
28#include "cm2xxx.h"
29#include "prm2xxx.h"
30#include "prm-regbits-24xx.h"
31#include "cm-regbits-24xx.h"
32#include "sdrc.h"
33#include "control.h"
34
35#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
36
37/*
38 * 2420 clock tree.
39 *
40 * NOTE:In many cases here we are assigning a 'default' parent. In
41 * many cases the parent is selectable. The set parent calls will
42 * also switch sources.
43 *
44 * Several sources are given initial rates which may be wrong, this will
45 * be fixed up in the init func.
46 *
47 * Things are broadly separated below by clock domains. It is
48 * noteworthy that most peripherals have dependencies on multiple clock
49 * domains. Many get their interface clocks from the L4 domain, but get
50 * functional clocks from fixed sources or other core domain derived
51 * clocks.
52 */
53
54DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
55
56DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
57
58DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
59
60static struct clk osc_ck;
61
62static const struct clk_ops osc_ck_ops = {
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static struct clk func_96m_ck;
226
227static const char *func_96m_ck_parent_names[] = {
228 "apll96_ck",
229};
230
231DEFINE_STRUCT_CLK_HW_OMAP(func_96m_ck, "wkup_clkdm");
232DEFINE_STRUCT_CLK(func_96m_ck, func_96m_ck_parent_names, core_ck_ops);
233
234static struct clk cam_fck;
235
236static const char *cam_fck_parent_names[] = {
237 "func_96m_ck",
238};
239
240static struct clk_hw_omap cam_fck_hw = {
241 .hw = {
242 .clk = &cam_fck,
243 },
244 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
245 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
246 .clkdm_name = "core_l3_clkdm",
247};
248
249DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
250
251static struct clk cam_ick;
252
253static struct clk_hw_omap cam_ick_hw = {
254 .hw = {
255 .clk = &cam_ick,
256 },
257 .ops = &clkhwops_iclk,
258 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
259 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
260 .clkdm_name = "core_l4_clkdm",
261};
262
263DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
264
265static struct clk des_ick;
266
267static struct clk_hw_omap des_ick_hw = {
268 .hw = {
269 .clk = &des_ick,
270 },
271 .ops = &clkhwops_iclk_wait,
272 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
273 .enable_bit = OMAP24XX_EN_DES_SHIFT,
274 .clkdm_name = "core_l4_clkdm",
275};
276
277DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
278
279static const struct clksel_rate dsp_fck_core_rates[] = {
280 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
281 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
282 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
283 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
284 { .div = 6, .val = 6, .flags = RATE_IN_242X },
285 { .div = 8, .val = 8, .flags = RATE_IN_242X },
286 { .div = 12, .val = 12, .flags = RATE_IN_242X },
287 { .div = 0 }
288};
289
290static const struct clksel dsp_fck_clksel[] = {
291 { .parent = &core_ck, .rates = dsp_fck_core_rates },
292 { .parent = NULL },
293};
294
295static const char *dsp_fck_parent_names[] = {
296 "core_ck",
297};
298
299static const struct clk_ops dsp_fck_ops = {
300 .init = &omap2_init_clk_clkdm,
301 .enable = &omap2_dflt_clk_enable,
302 .disable = &omap2_dflt_clk_disable,
303 .is_enabled = &omap2_dflt_clk_is_enabled,
304 .recalc_rate = &omap2_clksel_recalc,
305 .set_rate = &omap2_clksel_set_rate,
306 .round_rate = &omap2_clksel_round_rate,
307};
308
309DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
311 OMAP24XX_CLKSEL_DSP_MASK,
312 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
313 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
314 dsp_fck_parent_names, dsp_fck_ops);
315
316static const struct clksel dsp_ick_clksel[] = {
317 { .parent = &dsp_fck, .rates = dsp_ick_rates },
318 { .parent = NULL },
319};
320
321static const char *dsp_ick_parent_names[] = {
322 "dsp_fck",
323};
324
325DEFINE_CLK_OMAP_MUX_GATE(dsp_ick, "dsp_clkdm", dsp_ick_clksel,
326 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
327 OMAP24XX_CLKSEL_DSP_IF_MASK,
328 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
329 OMAP2420_EN_DSP_IPI_SHIFT, &clkhwops_iclk_wait,
330 dsp_ick_parent_names, dsp_fck_ops);
331
332static const struct clksel_rate dss1_fck_sys_rates[] = {
333 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
334 { .div = 0 }
335};
336
337static const struct clksel_rate dss1_fck_core_rates[] = {
338 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
339 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
340 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
341 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
342 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
343 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
344 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
345 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
346 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
347 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
348 { .div = 0 }
349};
350
351static const struct clksel dss1_fck_clksel[] = {
352 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
353 { .parent = &core_ck, .rates = dss1_fck_core_rates },
354 { .parent = NULL },
355};
356
357static const char *dss1_fck_parent_names[] = {
358 "sys_ck", "core_ck",
359};
360
361static struct clk dss1_fck;
362
363static const struct clk_ops dss1_fck_ops = {
364 .init = &omap2_init_clk_clkdm,
365 .enable = &omap2_dflt_clk_enable,
366 .disable = &omap2_dflt_clk_disable,
367 .is_enabled = &omap2_dflt_clk_is_enabled,
368 .recalc_rate = &omap2_clksel_recalc,
369 .get_parent = &omap2_clksel_find_parent_index,
370 .set_parent = &omap2_clksel_set_parent,
371};
372
373DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
374 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
375 OMAP24XX_CLKSEL_DSS1_MASK,
376 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
377 OMAP24XX_EN_DSS1_SHIFT, NULL,
378 dss1_fck_parent_names, dss1_fck_ops);
379
380static const struct clksel_rate dss2_fck_sys_rates[] = {
381 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
382 { .div = 0 }
383};
384
385static const struct clksel_rate dss2_fck_48m_rates[] = {
386 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
387 { .div = 0 }
388};
389
390static const struct clksel_rate func_48m_apll96_rates[] = {
391 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
392 { .div = 0 }
393};
394
395static const struct clksel_rate func_48m_alt_rates[] = {
396 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
397 { .div = 0 }
398};
399
400static const struct clksel func_48m_clksel[] = {
401 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
402 { .parent = &alt_ck, .rates = func_48m_alt_rates },
403 { .parent = NULL },
404};
405
406static const char *func_48m_ck_parent_names[] = {
407 "apll96_ck", "alt_ck",
408};
409
410static struct clk func_48m_ck;
411
412static const struct clk_ops func_48m_ck_ops = {
413 .init = &omap2_init_clk_clkdm,
414 .recalc_rate = &omap2_clksel_recalc,
415 .set_rate = &omap2_clksel_set_rate,
416 .round_rate = &omap2_clksel_round_rate,
417 .get_parent = &omap2_clksel_find_parent_index,
418 .set_parent = &omap2_clksel_set_parent,
419};
420
421static struct clk_hw_omap func_48m_ck_hw = {
422 .hw = {
423 .clk = &func_48m_ck,
424 },
425 .clksel = func_48m_clksel,
426 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
427 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
428 .clkdm_name = "wkup_clkdm",
429};
430
431DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
432
433static const struct clksel dss2_fck_clksel[] = {
434 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
435 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
436 { .parent = NULL },
437};
438
439static const char *dss2_fck_parent_names[] = {
440 "sys_ck", "func_48m_ck",
441};
442
443DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
444 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
445 OMAP24XX_CLKSEL_DSS2_MASK,
446 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
447 OMAP24XX_EN_DSS2_SHIFT, NULL,
448 dss2_fck_parent_names, dss1_fck_ops);
449
450static const char *func_54m_ck_parent_names[] = {
451 "apll54_ck", "alt_ck",
452};
453
454DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
455 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
456 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH,
457 0x0, NULL);
458
459static struct clk dss_54m_fck;
460
461static const char *dss_54m_fck_parent_names[] = {
462 "func_54m_ck",
463};
464
465static struct clk_hw_omap dss_54m_fck_hw = {
466 .hw = {
467 .clk = &dss_54m_fck,
468 },
469 .ops = &clkhwops_wait,
470 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
471 .enable_bit = OMAP24XX_EN_TV_SHIFT,
472 .clkdm_name = "dss_clkdm",
473};
474
475DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
476
477static struct clk dss_ick;
478
479static struct clk_hw_omap dss_ick_hw = {
480 .hw = {
481 .clk = &dss_ick,
482 },
483 .ops = &clkhwops_iclk,
484 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
485 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
486 .clkdm_name = "dss_clkdm",
487};
488
489DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
490
491static struct clk eac_fck;
492
493static struct clk_hw_omap eac_fck_hw = {
494 .hw = {
495 .clk = &eac_fck,
496 },
497 .ops = &clkhwops_wait,
498 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
499 .enable_bit = OMAP2420_EN_EAC_SHIFT,
500 .clkdm_name = "core_l4_clkdm",
501};
502
503DEFINE_STRUCT_CLK(eac_fck, cam_fck_parent_names, aes_ick_ops);
504
505static struct clk eac_ick;
506
507static struct clk_hw_omap eac_ick_hw = {
508 .hw = {
509 .clk = &eac_ick,
510 },
511 .ops = &clkhwops_iclk_wait,
512 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
513 .enable_bit = OMAP2420_EN_EAC_SHIFT,
514 .clkdm_name = "core_l4_clkdm",
515};
516
517DEFINE_STRUCT_CLK(eac_ick, aes_ick_parent_names, aes_ick_ops);
518
519static struct clk emul_ck;
520
521static struct clk_hw_omap emul_ck_hw = {
522 .hw = {
523 .clk = &emul_ck,
524 },
525 .enable_reg = OMAP2420_PRCM_CLKEMUL_CTRL,
526 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
527 .clkdm_name = "wkup_clkdm",
528};
529
530DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
531
532DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
533
534static struct clk fac_fck;
535
536static const char *fac_fck_parent_names[] = {
537 "func_12m_ck",
538};
539
540static struct clk_hw_omap fac_fck_hw = {
541 .hw = {
542 .clk = &fac_fck,
543 },
544 .ops = &clkhwops_wait,
545 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
546 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
547 .clkdm_name = "core_l4_clkdm",
548};
549
550DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
551
552static struct clk fac_ick;
553
554static struct clk_hw_omap fac_ick_hw = {
555 .hw = {
556 .clk = &fac_ick,
557 },
558 .ops = &clkhwops_iclk_wait,
559 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
560 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
561 .clkdm_name = "core_l4_clkdm",
562};
563
564DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
565
566static const struct clksel gfx_fck_clksel[] = {
567 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
568 { .parent = NULL },
569};
570
571static const char *gfx_2d_fck_parent_names[] = {
572 "core_l3_ck",
573};
574
575DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
576 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
577 OMAP_CLKSEL_GFX_MASK,
578 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
579 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
580 gfx_2d_fck_parent_names, dsp_fck_ops);
581
582DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
583 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
584 OMAP_CLKSEL_GFX_MASK,
585 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
586 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
587 gfx_2d_fck_parent_names, dsp_fck_ops);
588
589static struct clk gfx_ick;
590
591static const char *gfx_ick_parent_names[] = {
592 "core_l3_ck",
593};
594
595static struct clk_hw_omap gfx_ick_hw = {
596 .hw = {
597 .clk = &gfx_ick,
598 },
599 .ops = &clkhwops_wait,
600 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
601 .enable_bit = OMAP_EN_GFX_SHIFT,
602 .clkdm_name = "gfx_clkdm",
603};
604
605DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
606
607static struct clk gpios_fck;
608
609static const char *gpios_fck_parent_names[] = {
610 "func_32k_ck",
611};
612
613static struct clk_hw_omap gpios_fck_hw = {
614 .hw = {
615 .clk = &gpios_fck,
616 },
617 .ops = &clkhwops_wait,
618 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
619 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
620 .clkdm_name = "wkup_clkdm",
621};
622
623DEFINE_STRUCT_CLK(gpios_fck, gpios_fck_parent_names, aes_ick_ops);
624
625static struct clk gpios_ick;
626
627static const char *gpios_ick_parent_names[] = {
628 "sys_ck",
629};
630
631static struct clk_hw_omap gpios_ick_hw = {
632 .hw = {
633 .clk = &gpios_ick,
634 },
635 .ops = &clkhwops_iclk_wait,
636 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
637 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
638 .clkdm_name = "wkup_clkdm",
639};
640
641DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
642
643static struct clk gpmc_fck;
644
645static struct clk_hw_omap gpmc_fck_hw = {
646 .hw = {
647 .clk = &gpmc_fck,
648 },
649 .ops = &clkhwops_iclk,
650 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
651 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
652 .flags = ENABLE_ON_INIT,
653 .clkdm_name = "core_l3_clkdm",
654};
655
656DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
657
658static const struct clksel_rate gpt_alt_rates[] = {
659 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
660 { .div = 0 }
661};
662
663static const struct clksel omap24xx_gpt_clksel[] = {
664 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
665 { .parent = &sys_ck, .rates = gpt_sys_rates },
666 { .parent = &alt_ck, .rates = gpt_alt_rates },
667 { .parent = NULL },
668};
669
670static const char *gpt10_fck_parent_names[] = {
671 "func_32k_ck", "sys_ck", "alt_ck",
672};
673
674DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
675 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
676 OMAP24XX_CLKSEL_GPT10_MASK,
677 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
678 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
679 gpt10_fck_parent_names, dss1_fck_ops);
680
681static struct clk gpt10_ick;
682
683static struct clk_hw_omap gpt10_ick_hw = {
684 .hw = {
685 .clk = &gpt10_ick,
686 },
687 .ops = &clkhwops_iclk_wait,
688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
689 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
690 .clkdm_name = "core_l4_clkdm",
691};
692
693DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
694
695DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
696 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
697 OMAP24XX_CLKSEL_GPT11_MASK,
698 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
699 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
700 gpt10_fck_parent_names, dss1_fck_ops);
701
702static struct clk gpt11_ick;
703
704static struct clk_hw_omap gpt11_ick_hw = {
705 .hw = {
706 .clk = &gpt11_ick,
707 },
708 .ops = &clkhwops_iclk_wait,
709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
710 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
711 .clkdm_name = "core_l4_clkdm",
712};
713
714DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
715
716DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
717 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
718 OMAP24XX_CLKSEL_GPT12_MASK,
719 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
720 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
721 gpt10_fck_parent_names, dss1_fck_ops);
722
723static struct clk gpt12_ick;
724
725static struct clk_hw_omap gpt12_ick_hw = {
726 .hw = {
727 .clk = &gpt12_ick,
728 },
729 .ops = &clkhwops_iclk_wait,
730 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
731 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
732 .clkdm_name = "core_l4_clkdm",
733};
734
735DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
736
737static const struct clk_ops gpt1_fck_ops = {
738 .init = &omap2_init_clk_clkdm,
739 .enable = &omap2_dflt_clk_enable,
740 .disable = &omap2_dflt_clk_disable,
741 .is_enabled = &omap2_dflt_clk_is_enabled,
742 .recalc_rate = &omap2_clksel_recalc,
743 .set_rate = &omap2_clksel_set_rate,
744 .round_rate = &omap2_clksel_round_rate,
745 .get_parent = &omap2_clksel_find_parent_index,
746 .set_parent = &omap2_clksel_set_parent,
747};
748
749DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
750 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
751 OMAP24XX_CLKSEL_GPT1_MASK,
752 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
753 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
754 gpt10_fck_parent_names, gpt1_fck_ops);
755
756static struct clk gpt1_ick;
757
758static struct clk_hw_omap gpt1_ick_hw = {
759 .hw = {
760 .clk = &gpt1_ick,
761 },
762 .ops = &clkhwops_iclk_wait,
763 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
764 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
765 .clkdm_name = "wkup_clkdm",
766};
767
768DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
769
770DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
771 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
772 OMAP24XX_CLKSEL_GPT2_MASK,
773 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
774 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
775 gpt10_fck_parent_names, dss1_fck_ops);
776
777static struct clk gpt2_ick;
778
779static struct clk_hw_omap gpt2_ick_hw = {
780 .hw = {
781 .clk = &gpt2_ick,
782 },
783 .ops = &clkhwops_iclk_wait,
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
785 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
786 .clkdm_name = "core_l4_clkdm",
787};
788
789DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
790
791DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
792 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
793 OMAP24XX_CLKSEL_GPT3_MASK,
794 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
796 gpt10_fck_parent_names, dss1_fck_ops);
797
798static struct clk gpt3_ick;
799
800static struct clk_hw_omap gpt3_ick_hw = {
801 .hw = {
802 .clk = &gpt3_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
811
812DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
813 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
814 OMAP24XX_CLKSEL_GPT4_MASK,
815 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
816 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
817 gpt10_fck_parent_names, dss1_fck_ops);
818
819static struct clk gpt4_ick;
820
821static struct clk_hw_omap gpt4_ick_hw = {
822 .hw = {
823 .clk = &gpt4_ick,
824 },
825 .ops = &clkhwops_iclk_wait,
826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
827 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
828 .clkdm_name = "core_l4_clkdm",
829};
830
831DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
832
833DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
834 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
835 OMAP24XX_CLKSEL_GPT5_MASK,
836 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
838 gpt10_fck_parent_names, dss1_fck_ops);
839
840static struct clk gpt5_ick;
841
842static struct clk_hw_omap gpt5_ick_hw = {
843 .hw = {
844 .clk = &gpt5_ick,
845 },
846 .ops = &clkhwops_iclk_wait,
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
849 .clkdm_name = "core_l4_clkdm",
850};
851
852DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
853
854DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
855 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
856 OMAP24XX_CLKSEL_GPT6_MASK,
857 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
859 gpt10_fck_parent_names, dss1_fck_ops);
860
861static struct clk gpt6_ick;
862
863static struct clk_hw_omap gpt6_ick_hw = {
864 .hw = {
865 .clk = &gpt6_ick,
866 },
867 .ops = &clkhwops_iclk_wait,
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
870 .clkdm_name = "core_l4_clkdm",
871};
872
873DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
874
875DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
876 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
877 OMAP24XX_CLKSEL_GPT7_MASK,
878 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
879 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
880 gpt10_fck_parent_names, dss1_fck_ops);
881
882static struct clk gpt7_ick;
883
884static struct clk_hw_omap gpt7_ick_hw = {
885 .hw = {
886 .clk = &gpt7_ick,
887 },
888 .ops = &clkhwops_iclk_wait,
889 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
890 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
891 .clkdm_name = "core_l4_clkdm",
892};
893
894DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
895
896DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
897 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
898 OMAP24XX_CLKSEL_GPT8_MASK,
899 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
900 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
901 gpt10_fck_parent_names, dss1_fck_ops);
902
903static struct clk gpt8_ick;
904
905static struct clk_hw_omap gpt8_ick_hw = {
906 .hw = {
907 .clk = &gpt8_ick,
908 },
909 .ops = &clkhwops_iclk_wait,
910 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
911 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
912 .clkdm_name = "core_l4_clkdm",
913};
914
915DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
916
917DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
918 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
919 OMAP24XX_CLKSEL_GPT9_MASK,
920 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
921 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
922 gpt10_fck_parent_names, dss1_fck_ops);
923
924static struct clk gpt9_ick;
925
926static struct clk_hw_omap gpt9_ick_hw = {
927 .hw = {
928 .clk = &gpt9_ick,
929 },
930 .ops = &clkhwops_iclk_wait,
931 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
932 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
933 .clkdm_name = "core_l4_clkdm",
934};
935
936DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
937
938static struct clk hdq_fck;
939
940static struct clk_hw_omap hdq_fck_hw = {
941 .hw = {
942 .clk = &hdq_fck,
943 },
944 .ops = &clkhwops_wait,
945 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
946 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
947 .clkdm_name = "core_l4_clkdm",
948};
949
950DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
951
952static struct clk hdq_ick;
953
954static struct clk_hw_omap hdq_ick_hw = {
955 .hw = {
956 .clk = &hdq_ick,
957 },
958 .ops = &clkhwops_iclk_wait,
959 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
960 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
961 .clkdm_name = "core_l4_clkdm",
962};
963
964DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
965
966static struct clk i2c1_fck;
967
968static struct clk_hw_omap i2c1_fck_hw = {
969 .hw = {
970 .clk = &i2c1_fck,
971 },
972 .ops = &clkhwops_wait,
973 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
974 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
975 .clkdm_name = "core_l4_clkdm",
976};
977
978DEFINE_STRUCT_CLK(i2c1_fck, fac_fck_parent_names, aes_ick_ops);
979
980static struct clk i2c1_ick;
981
982static struct clk_hw_omap i2c1_ick_hw = {
983 .hw = {
984 .clk = &i2c1_ick,
985 },
986 .ops = &clkhwops_iclk_wait,
987 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
988 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
989 .clkdm_name = "core_l4_clkdm",
990};
991
992DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
993
994static struct clk i2c2_fck;
995
996static struct clk_hw_omap i2c2_fck_hw = {
997 .hw = {
998 .clk = &i2c2_fck,
999 },
1000 .ops = &clkhwops_wait,
1001 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1002 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1003 .clkdm_name = "core_l4_clkdm",
1004};
1005
1006DEFINE_STRUCT_CLK(i2c2_fck, fac_fck_parent_names, aes_ick_ops);
1007
1008static struct clk i2c2_ick;
1009
1010static struct clk_hw_omap i2c2_ick_hw = {
1011 .hw = {
1012 .clk = &i2c2_ick,
1013 },
1014 .ops = &clkhwops_iclk_wait,
1015 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1016 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
1017 .clkdm_name = "core_l4_clkdm",
1018};
1019
1020DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
1021
1022DEFINE_CLK_OMAP_MUX_GATE(iva1_ifck, "iva1_clkdm", dsp_fck_clksel,
1023 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1024 OMAP2420_CLKSEL_IVA_MASK,
1025 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1026 OMAP2420_EN_IVA_COP_SHIFT, &clkhwops_wait,
1027 dsp_fck_parent_names, dsp_fck_ops);
1028
1029static struct clk iva1_mpu_int_ifck;
1030
1031static const char *iva1_mpu_int_ifck_parent_names[] = {
1032 "iva1_ifck",
1033};
1034
1035static const struct clk_ops iva1_mpu_int_ifck_ops = {
1036 .init = &omap2_init_clk_clkdm,
1037 .enable = &omap2_dflt_clk_enable,
1038 .disable = &omap2_dflt_clk_disable,
1039 .is_enabled = &omap2_dflt_clk_is_enabled,
1040 .recalc_rate = &omap_fixed_divisor_recalc,
1041};
1042
1043static struct clk_hw_omap iva1_mpu_int_ifck_hw = {
1044 .hw = {
1045 .clk = &iva1_mpu_int_ifck,
1046 },
1047 .ops = &clkhwops_wait,
1048 .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1049 .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT,
1050 .clkdm_name = "iva1_clkdm",
1051 .fixed_div = 2,
1052};
1053
1054DEFINE_STRUCT_CLK(iva1_mpu_int_ifck, iva1_mpu_int_ifck_parent_names,
1055 iva1_mpu_int_ifck_ops);
1056
1057static struct clk mailboxes_ick;
1058
1059static struct clk_hw_omap mailboxes_ick_hw = {
1060 .hw = {
1061 .clk = &mailboxes_ick,
1062 },
1063 .ops = &clkhwops_iclk_wait,
1064 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1065 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1066 .clkdm_name = "core_l4_clkdm",
1067};
1068
1069DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1070
1071static const struct clksel_rate common_mcbsp_96m_rates[] = {
1072 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1073 { .div = 0 }
1074};
1075
1076static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1077 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1078 { .div = 0 }
1079};
1080
1081static const struct clksel mcbsp_fck_clksel[] = {
1082 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1083 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1084 { .parent = NULL },
1085};
1086
1087static const char *mcbsp1_fck_parent_names[] = {
1088 "func_96m_ck", "mcbsp_clks",
1089};
1090
1091DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1092 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1093 OMAP2_MCBSP1_CLKS_MASK,
1094 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1095 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1096 mcbsp1_fck_parent_names, dss1_fck_ops);
1097
1098static struct clk mcbsp1_ick;
1099
1100static struct clk_hw_omap mcbsp1_ick_hw = {
1101 .hw = {
1102 .clk = &mcbsp1_ick,
1103 },
1104 .ops = &clkhwops_iclk_wait,
1105 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1106 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1107 .clkdm_name = "core_l4_clkdm",
1108};
1109
1110DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1111
1112DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1113 OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1114 OMAP2_MCBSP2_CLKS_MASK,
1115 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1116 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1117 mcbsp1_fck_parent_names, dss1_fck_ops);
1118
1119static struct clk mcbsp2_ick;
1120
1121static struct clk_hw_omap mcbsp2_ick_hw = {
1122 .hw = {
1123 .clk = &mcbsp2_ick,
1124 },
1125 .ops = &clkhwops_iclk_wait,
1126 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1127 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1128 .clkdm_name = "core_l4_clkdm",
1129};
1130
1131DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1132
1133static struct clk mcspi1_fck;
1134
1135static const char *mcspi1_fck_parent_names[] = {
1136 "func_48m_ck",
1137};
1138
1139static struct clk_hw_omap mcspi1_fck_hw = {
1140 .hw = {
1141 .clk = &mcspi1_fck,
1142 },
1143 .ops = &clkhwops_wait,
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1145 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1146 .clkdm_name = "core_l4_clkdm",
1147};
1148
1149DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1150
1151static struct clk mcspi1_ick;
1152
1153static struct clk_hw_omap mcspi1_ick_hw = {
1154 .hw = {
1155 .clk = &mcspi1_ick,
1156 },
1157 .ops = &clkhwops_iclk_wait,
1158 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1159 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1160 .clkdm_name = "core_l4_clkdm",
1161};
1162
1163DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1164
1165static struct clk mcspi2_fck;
1166
1167static struct clk_hw_omap mcspi2_fck_hw = {
1168 .hw = {
1169 .clk = &mcspi2_fck,
1170 },
1171 .ops = &clkhwops_wait,
1172 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1173 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1174 .clkdm_name = "core_l4_clkdm",
1175};
1176
1177DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1178
1179static struct clk mcspi2_ick;
1180
1181static struct clk_hw_omap mcspi2_ick_hw = {
1182 .hw = {
1183 .clk = &mcspi2_ick,
1184 },
1185 .ops = &clkhwops_iclk_wait,
1186 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1187 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1188 .clkdm_name = "core_l4_clkdm",
1189};
1190
1191DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1192
1193static struct clk mmc_fck;
1194
1195static struct clk_hw_omap mmc_fck_hw = {
1196 .hw = {
1197 .clk = &mmc_fck,
1198 },
1199 .ops = &clkhwops_wait,
1200 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1201 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1202 .clkdm_name = "core_l4_clkdm",
1203};
1204
1205DEFINE_STRUCT_CLK(mmc_fck, cam_fck_parent_names, aes_ick_ops);
1206
1207static struct clk mmc_ick;
1208
1209static struct clk_hw_omap mmc_ick_hw = {
1210 .hw = {
1211 .clk = &mmc_ick,
1212 },
1213 .ops = &clkhwops_iclk_wait,
1214 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1215 .enable_bit = OMAP2420_EN_MMC_SHIFT,
1216 .clkdm_name = "core_l4_clkdm",
1217};
1218
1219DEFINE_STRUCT_CLK(mmc_ick, aes_ick_parent_names, aes_ick_ops);
1220
1221DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1222 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1223 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1224 CLK_DIVIDER_ONE_BASED, NULL);
1225
1226static struct clk mpu_wdt_fck;
1227
1228static struct clk_hw_omap mpu_wdt_fck_hw = {
1229 .hw = {
1230 .clk = &mpu_wdt_fck,
1231 },
1232 .ops = &clkhwops_wait,
1233 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1234 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1235 .clkdm_name = "wkup_clkdm",
1236};
1237
1238DEFINE_STRUCT_CLK(mpu_wdt_fck, gpios_fck_parent_names, aes_ick_ops);
1239
1240static struct clk mpu_wdt_ick;
1241
1242static struct clk_hw_omap mpu_wdt_ick_hw = {
1243 .hw = {
1244 .clk = &mpu_wdt_ick,
1245 },
1246 .ops = &clkhwops_iclk_wait,
1247 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1248 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1249 .clkdm_name = "wkup_clkdm",
1250};
1251
1252DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1253
1254static struct clk mspro_fck;
1255
1256static struct clk_hw_omap mspro_fck_hw = {
1257 .hw = {
1258 .clk = &mspro_fck,
1259 },
1260 .ops = &clkhwops_wait,
1261 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1262 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1263 .clkdm_name = "core_l4_clkdm",
1264};
1265
1266DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1267
1268static struct clk mspro_ick;
1269
1270static struct clk_hw_omap mspro_ick_hw = {
1271 .hw = {
1272 .clk = &mspro_ick,
1273 },
1274 .ops = &clkhwops_iclk_wait,
1275 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1276 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1277 .clkdm_name = "core_l4_clkdm",
1278};
1279
1280DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1281
1282static struct clk omapctrl_ick;
1283
1284static struct clk_hw_omap omapctrl_ick_hw = {
1285 .hw = {
1286 .clk = &omapctrl_ick,
1287 },
1288 .ops = &clkhwops_iclk_wait,
1289 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1290 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1291 .flags = ENABLE_ON_INIT,
1292 .clkdm_name = "wkup_clkdm",
1293};
1294
1295DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1296
1297static struct clk pka_ick;
1298
1299static struct clk_hw_omap pka_ick_hw = {
1300 .hw = {
1301 .clk = &pka_ick,
1302 },
1303 .ops = &clkhwops_iclk_wait,
1304 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1305 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1306 .clkdm_name = "core_l4_clkdm",
1307};
1308
1309DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1310
1311static struct clk rng_ick;
1312
1313static struct clk_hw_omap rng_ick_hw = {
1314 .hw = {
1315 .clk = &rng_ick,
1316 },
1317 .ops = &clkhwops_iclk_wait,
1318 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1319 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1320 .clkdm_name = "core_l4_clkdm",
1321};
1322
1323DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1324
1325static struct clk sdma_fck;
1326
1327DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1328DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1329
1330static struct clk sdma_ick;
1331
1332static struct clk_hw_omap sdma_ick_hw = {
1333 .hw = {
1334 .clk = &sdma_ick,
1335 },
1336 .ops = &clkhwops_iclk,
1337 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1338 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1339 .clkdm_name = "core_l3_clkdm",
1340};
1341
1342DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1343
1344static struct clk sdrc_ick;
1345
1346static struct clk_hw_omap sdrc_ick_hw = {
1347 .hw = {
1348 .clk = &sdrc_ick,
1349 },
1350 .ops = &clkhwops_iclk,
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1352 .enable_bit = OMAP24XX_AUTO_SDRC_SHIFT,
1353 .flags = ENABLE_ON_INIT,
1354 .clkdm_name = "core_l3_clkdm",
1355};
1356
1357DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1358
1359static struct clk sha_ick;
1360
1361static struct clk_hw_omap sha_ick_hw = {
1362 .hw = {
1363 .clk = &sha_ick,
1364 },
1365 .ops = &clkhwops_iclk_wait,
1366 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1367 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1368 .clkdm_name = "core_l4_clkdm",
1369};
1370
1371DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1372
1373static struct clk ssi_l4_ick;
1374
1375static struct clk_hw_omap ssi_l4_ick_hw = {
1376 .hw = {
1377 .clk = &ssi_l4_ick,
1378 },
1379 .ops = &clkhwops_iclk_wait,
1380 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1381 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1382 .clkdm_name = "core_l4_clkdm",
1383};
1384
1385DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1386
1387static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1388 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1389 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1390 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1391 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1392 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1393 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1394 { .div = 0 }
1395};
1396
1397static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1398 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1399 { .parent = NULL },
1400};
1401
1402static const char *ssi_ssr_sst_fck_parent_names[] = {
1403 "core_ck",
1404};
1405
1406DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1407 ssi_ssr_sst_fck_clksel,
1408 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1409 OMAP24XX_CLKSEL_SSI_MASK,
1410 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1411 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1412 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1413
1414static struct clk sync_32k_ick;
1415
1416static struct clk_hw_omap sync_32k_ick_hw = {
1417 .hw = {
1418 .clk = &sync_32k_ick,
1419 },
1420 .ops = &clkhwops_iclk_wait,
1421 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1422 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1423 .flags = ENABLE_ON_INIT,
1424 .clkdm_name = "wkup_clkdm",
1425};
1426
1427DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1428
1429static const struct clksel_rate common_clkout_src_core_rates[] = {
1430 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1431 { .div = 0 }
1432};
1433
1434static const struct clksel_rate common_clkout_src_sys_rates[] = {
1435 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1436 { .div = 0 }
1437};
1438
1439static const struct clksel_rate common_clkout_src_96m_rates[] = {
1440 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1441 { .div = 0 }
1442};
1443
1444static const struct clksel_rate common_clkout_src_54m_rates[] = {
1445 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1446 { .div = 0 }
1447};
1448
1449static const struct clksel common_clkout_src_clksel[] = {
1450 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1451 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1452 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1453 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1454 { .parent = NULL },
1455};
1456
1457static const char *sys_clkout_src_parent_names[] = {
1458 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1459};
1460
1461DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1462 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1463 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1464 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1465
1466DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1467 OMAP2420_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1468 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1469
1470DEFINE_CLK_OMAP_MUX_GATE(sys_clkout2_src, "wkup_clkdm",
1471 common_clkout_src_clksel, OMAP2420_PRCM_CLKOUT_CTRL,
1472 OMAP2420_CLKOUT2_SOURCE_MASK,
1473 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_EN_SHIFT,
1474 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1475
1476DEFINE_CLK_DIVIDER(sys_clkout2, "sys_clkout2_src", &sys_clkout2_src, 0x0,
1477 OMAP2420_PRCM_CLKOUT_CTRL, OMAP2420_CLKOUT2_DIV_SHIFT,
1478 OMAP2420_CLKOUT2_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1479
1480static struct clk uart1_fck;
1481
1482static struct clk_hw_omap uart1_fck_hw = {
1483 .hw = {
1484 .clk = &uart1_fck,
1485 },
1486 .ops = &clkhwops_wait,
1487 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1488 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1489 .clkdm_name = "core_l4_clkdm",
1490};
1491
1492DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1493
1494static struct clk uart1_ick;
1495
1496static struct clk_hw_omap uart1_ick_hw = {
1497 .hw = {
1498 .clk = &uart1_ick,
1499 },
1500 .ops = &clkhwops_iclk_wait,
1501 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1502 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1503 .clkdm_name = "core_l4_clkdm",
1504};
1505
1506DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1507
1508static struct clk uart2_fck;
1509
1510static struct clk_hw_omap uart2_fck_hw = {
1511 .hw = {
1512 .clk = &uart2_fck,
1513 },
1514 .ops = &clkhwops_wait,
1515 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1516 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1517 .clkdm_name = "core_l4_clkdm",
1518};
1519
1520DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1521
1522static struct clk uart2_ick;
1523
1524static struct clk_hw_omap uart2_ick_hw = {
1525 .hw = {
1526 .clk = &uart2_ick,
1527 },
1528 .ops = &clkhwops_iclk_wait,
1529 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1530 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1531 .clkdm_name = "core_l4_clkdm",
1532};
1533
1534DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1535
1536static struct clk uart3_fck;
1537
1538static struct clk_hw_omap uart3_fck_hw = {
1539 .hw = {
1540 .clk = &uart3_fck,
1541 },
1542 .ops = &clkhwops_wait,
1543 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1544 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1545 .clkdm_name = "core_l4_clkdm",
1546};
1547
1548DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1549
1550static struct clk uart3_ick;
1551
1552static struct clk_hw_omap uart3_ick_hw = {
1553 .hw = {
1554 .clk = &uart3_ick,
1555 },
1556 .ops = &clkhwops_iclk_wait,
1557 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1558 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1559 .clkdm_name = "core_l4_clkdm",
1560};
1561
1562DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1563
1564static struct clk usb_fck;
1565
1566static struct clk_hw_omap usb_fck_hw = {
1567 .hw = {
1568 .clk = &usb_fck,
1569 },
1570 .ops = &clkhwops_wait,
1571 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1572 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1573 .clkdm_name = "core_l3_clkdm",
1574};
1575
1576DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1577
1578static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1579 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1580 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1581 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1582 { .div = 0 }
1583};
1584
1585static const struct clksel usb_l4_ick_clksel[] = {
1586 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1587 { .parent = NULL },
1588};
1589
1590static const char *usb_l4_ick_parent_names[] = {
1591 "core_l3_ck",
1592};
1593
1594DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1595 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1596 OMAP24XX_CLKSEL_USB_MASK,
1597 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1598 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1599 usb_l4_ick_parent_names, dsp_fck_ops);
1600
1601static struct clk virt_prcm_set;
1602
1603static const char *virt_prcm_set_parent_names[] = {
1604 "mpu_ck",
1605};
1606
1607static const struct clk_ops virt_prcm_set_ops = {
1608 .recalc_rate = &omap2_table_mpu_recalc,
1609 .set_rate = &omap2_select_table_rate,
1610 .round_rate = &omap2_round_to_table_rate,
1611};
1612
1613DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1614DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1615
1616static const struct clksel_rate vlynq_fck_96m_rates[] = {
1617 { .div = 1, .val = 0, .flags = RATE_IN_242X },
1618 { .div = 0 }
1619};
1620
1621static const struct clksel_rate vlynq_fck_core_rates[] = {
1622 { .div = 1, .val = 1, .flags = RATE_IN_242X },
1623 { .div = 2, .val = 2, .flags = RATE_IN_242X },
1624 { .div = 3, .val = 3, .flags = RATE_IN_242X },
1625 { .div = 4, .val = 4, .flags = RATE_IN_242X },
1626 { .div = 6, .val = 6, .flags = RATE_IN_242X },
1627 { .div = 8, .val = 8, .flags = RATE_IN_242X },
1628 { .div = 9, .val = 9, .flags = RATE_IN_242X },
1629 { .div = 12, .val = 12, .flags = RATE_IN_242X },
1630 { .div = 16, .val = 16, .flags = RATE_IN_242X },
1631 { .div = 18, .val = 18, .flags = RATE_IN_242X },
1632 { .div = 0 }
1633};
1634
1635static const struct clksel vlynq_fck_clksel[] = {
1636 { .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
1637 { .parent = &core_ck, .rates = vlynq_fck_core_rates },
1638 { .parent = NULL },
1639};
1640
1641static const char *vlynq_fck_parent_names[] = {
1642 "func_96m_ck", "core_ck",
1643};
1644
1645DEFINE_CLK_OMAP_MUX_GATE(vlynq_fck, "core_l3_clkdm", vlynq_fck_clksel,
1646 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1647 OMAP2420_CLKSEL_VLYNQ_MASK,
1648 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1649 OMAP2420_EN_VLYNQ_SHIFT, &clkhwops_wait,
1650 vlynq_fck_parent_names, dss1_fck_ops);
1651
1652static struct clk vlynq_ick;
1653
1654static struct clk_hw_omap vlynq_ick_hw = {
1655 .hw = {
1656 .clk = &vlynq_ick,
1657 },
1658 .ops = &clkhwops_iclk_wait,
1659 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1660 .enable_bit = OMAP2420_EN_VLYNQ_SHIFT,
1661 .clkdm_name = "core_l3_clkdm",
1662};
1663
1664DEFINE_STRUCT_CLK(vlynq_ick, gfx_ick_parent_names, aes_ick_ops);
1665
1666static struct clk wdt1_ick;
1667
1668static struct clk_hw_omap wdt1_ick_hw = {
1669 .hw = {
1670 .clk = &wdt1_ick,
1671 },
1672 .ops = &clkhwops_iclk_wait,
1673 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1674 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1675 .clkdm_name = "wkup_clkdm",
1676};
1677
1678DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1679
1680static struct clk wdt3_fck;
1681
1682static struct clk_hw_omap wdt3_fck_hw = {
1683 .hw = {
1684 .clk = &wdt3_fck,
1685 },
1686 .ops = &clkhwops_wait,
1687 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1688 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1689 .clkdm_name = "core_l4_clkdm",
1690};
1691
1692DEFINE_STRUCT_CLK(wdt3_fck, gpios_fck_parent_names, aes_ick_ops);
1693
1694static struct clk wdt3_ick;
1695
1696static struct clk_hw_omap wdt3_ick_hw = {
1697 .hw = {
1698 .clk = &wdt3_ick,
1699 },
1700 .ops = &clkhwops_iclk_wait,
1701 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1702 .enable_bit = OMAP2420_EN_WDT3_SHIFT,
1703 .clkdm_name = "core_l4_clkdm",
1704};
1705
1706DEFINE_STRUCT_CLK(wdt3_ick, aes_ick_parent_names, aes_ick_ops);
1707
1708static struct clk wdt4_fck;
1709
1710static struct clk_hw_omap wdt4_fck_hw = {
1711 .hw = {
1712 .clk = &wdt4_fck,
1713 },
1714 .ops = &clkhwops_wait,
1715 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1716 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1717 .clkdm_name = "core_l4_clkdm",
1718};
1719
1720DEFINE_STRUCT_CLK(wdt4_fck, gpios_fck_parent_names, aes_ick_ops);
1721
1722static struct clk wdt4_ick;
1723
1724static struct clk_hw_omap wdt4_ick_hw = {
1725 .hw = {
1726 .clk = &wdt4_ick,
1727 },
1728 .ops = &clkhwops_iclk_wait,
1729 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1730 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1731 .clkdm_name = "core_l4_clkdm",
1732};
1733
1734DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1735
1736/*
1737 * clkdev integration
1738 */
1739
1740static struct omap_clk omap2420_clks[] = {
1741 /* external root sources */
1742 CLK(NULL, "func_32k_ck", &func_32k_ck),
1743 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1744 CLK(NULL, "osc_ck", &osc_ck),
1745 CLK(NULL, "sys_ck", &sys_ck),
1746 CLK(NULL, "alt_ck", &alt_ck),
1747 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1748 /* internal analog sources */
1749 CLK(NULL, "dpll_ck", &dpll_ck),
1750 CLK(NULL, "apll96_ck", &apll96_ck),
1751 CLK(NULL, "apll54_ck", &apll54_ck),
1752 /* internal prcm root sources */
1753 CLK(NULL, "func_54m_ck", &func_54m_ck),
1754 CLK(NULL, "core_ck", &core_ck),
1755 CLK(NULL, "func_96m_ck", &func_96m_ck),
1756 CLK(NULL, "func_48m_ck", &func_48m_ck),
1757 CLK(NULL, "func_12m_ck", &func_12m_ck),
1758 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1759 CLK(NULL, "sys_clkout", &sys_clkout),
1760 CLK(NULL, "sys_clkout2_src", &sys_clkout2_src),
1761 CLK(NULL, "sys_clkout2", &sys_clkout2),
1762 CLK(NULL, "emul_ck", &emul_ck),
1763 /* mpu domain clocks */
1764 CLK(NULL, "mpu_ck", &mpu_ck),
1765 /* dsp domain clocks */
1766 CLK(NULL, "dsp_fck", &dsp_fck),
1767 CLK(NULL, "dsp_ick", &dsp_ick),
1768 CLK(NULL, "iva1_ifck", &iva1_ifck),
1769 CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
1770 /* GFX domain clocks */
1771 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1772 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1773 CLK(NULL, "gfx_ick", &gfx_ick),
1774 /* DSS domain clocks */
1775 CLK("omapdss_dss", "ick", &dss_ick),
1776 CLK(NULL, "dss_ick", &dss_ick),
1777 CLK(NULL, "dss1_fck", &dss1_fck),
1778 CLK(NULL, "dss2_fck", &dss2_fck),
1779 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1780 /* L3 domain clocks */
1781 CLK(NULL, "core_l3_ck", &core_l3_ck),
1782 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1783 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1784 /* L4 domain clocks */
1785 CLK(NULL, "l4_ck", &l4_ck),
1786 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1787 /* virtual meta-group clock */
1788 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1789 /* general l4 interface ck, multi-parent functional clk */
1790 CLK(NULL, "gpt1_ick", &gpt1_ick),
1791 CLK(NULL, "gpt1_fck", &gpt1_fck),
1792 CLK(NULL, "gpt2_ick", &gpt2_ick),
1793 CLK(NULL, "gpt2_fck", &gpt2_fck),
1794 CLK(NULL, "gpt3_ick", &gpt3_ick),
1795 CLK(NULL, "gpt3_fck", &gpt3_fck),
1796 CLK(NULL, "gpt4_ick", &gpt4_ick),
1797 CLK(NULL, "gpt4_fck", &gpt4_fck),
1798 CLK(NULL, "gpt5_ick", &gpt5_ick),
1799 CLK(NULL, "gpt5_fck", &gpt5_fck),
1800 CLK(NULL, "gpt6_ick", &gpt6_ick),
1801 CLK(NULL, "gpt6_fck", &gpt6_fck),
1802 CLK(NULL, "gpt7_ick", &gpt7_ick),
1803 CLK(NULL, "gpt7_fck", &gpt7_fck),
1804 CLK(NULL, "gpt8_ick", &gpt8_ick),
1805 CLK(NULL, "gpt8_fck", &gpt8_fck),
1806 CLK(NULL, "gpt9_ick", &gpt9_ick),
1807 CLK(NULL, "gpt9_fck", &gpt9_fck),
1808 CLK(NULL, "gpt10_ick", &gpt10_ick),
1809 CLK(NULL, "gpt10_fck", &gpt10_fck),
1810 CLK(NULL, "gpt11_ick", &gpt11_ick),
1811 CLK(NULL, "gpt11_fck", &gpt11_fck),
1812 CLK(NULL, "gpt12_ick", &gpt12_ick),
1813 CLK(NULL, "gpt12_fck", &gpt12_fck),
1814 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1815 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1816 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1817 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1818 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1819 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1820 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1821 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1822 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1823 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1824 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1825 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1826 CLK(NULL, "uart1_ick", &uart1_ick),
1827 CLK(NULL, "uart1_fck", &uart1_fck),
1828 CLK(NULL, "uart2_ick", &uart2_ick),
1829 CLK(NULL, "uart2_fck", &uart2_fck),
1830 CLK(NULL, "uart3_ick", &uart3_ick),
1831 CLK(NULL, "uart3_fck", &uart3_fck),
1832 CLK(NULL, "gpios_ick", &gpios_ick),
1833 CLK(NULL, "gpios_fck", &gpios_fck),
1834 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1835 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1836 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1837 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1838 CLK(NULL, "wdt1_ick", &wdt1_ick),
1839 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1840 CLK("omap24xxcam", "fck", &cam_fck),
1841 CLK(NULL, "cam_fck", &cam_fck),
1842 CLK("omap24xxcam", "ick", &cam_ick),
1843 CLK(NULL, "cam_ick", &cam_ick),
1844 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1845 CLK(NULL, "wdt4_ick", &wdt4_ick),
1846 CLK(NULL, "wdt4_fck", &wdt4_fck),
1847 CLK(NULL, "wdt3_ick", &wdt3_ick),
1848 CLK(NULL, "wdt3_fck", &wdt3_fck),
1849 CLK(NULL, "mspro_ick", &mspro_ick),
1850 CLK(NULL, "mspro_fck", &mspro_fck),
1851 CLK("mmci-omap.0", "ick", &mmc_ick),
1852 CLK(NULL, "mmc_ick", &mmc_ick),
1853 CLK("mmci-omap.0", "fck", &mmc_fck),
1854 CLK(NULL, "mmc_fck", &mmc_fck),
1855 CLK(NULL, "fac_ick", &fac_ick),
1856 CLK(NULL, "fac_fck", &fac_fck),
1857 CLK(NULL, "eac_ick", &eac_ick),
1858 CLK(NULL, "eac_fck", &eac_fck),
1859 CLK("omap_hdq.0", "ick", &hdq_ick),
1860 CLK(NULL, "hdq_ick", &hdq_ick),
1861 CLK("omap_hdq.0", "fck", &hdq_fck),
1862 CLK(NULL, "hdq_fck", &hdq_fck),
1863 CLK("omap_i2c.1", "ick", &i2c1_ick),
1864 CLK(NULL, "i2c1_ick", &i2c1_ick),
1865 CLK(NULL, "i2c1_fck", &i2c1_fck),
1866 CLK("omap_i2c.2", "ick", &i2c2_ick),
1867 CLK(NULL, "i2c2_ick", &i2c2_ick),
1868 CLK(NULL, "i2c2_fck", &i2c2_fck),
1869 CLK(NULL, "gpmc_fck", &gpmc_fck),
1870 CLK(NULL, "sdma_fck", &sdma_fck),
1871 CLK(NULL, "sdma_ick", &sdma_ick),
1872 CLK(NULL, "sdrc_ick", &sdrc_ick),
1873 CLK(NULL, "vlynq_ick", &vlynq_ick),
1874 CLK(NULL, "vlynq_fck", &vlynq_fck),
1875 CLK(NULL, "des_ick", &des_ick),
1876 CLK("omap-sham", "ick", &sha_ick),
1877 CLK(NULL, "sha_ick", &sha_ick),
1878 CLK("omap_rng", "ick", &rng_ick),
1879 CLK(NULL, "rng_ick", &rng_ick),
1880 CLK("omap-aes", "ick", &aes_ick),
1881 CLK(NULL, "aes_ick", &aes_ick),
1882 CLK(NULL, "pka_ick", &pka_ick),
1883 CLK(NULL, "usb_fck", &usb_fck),
1884 CLK("musb-hdrc", "fck", &osc_ck),
1885 CLK(NULL, "timer_32k_ck", &func_32k_ck),
1886 CLK(NULL, "timer_sys_ck", &sys_ck),
1887 CLK(NULL, "timer_ext_ck", &alt_ck),
1888 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
1889};
1890
1891
1892static const char *enable_init_clks[] = {
1893 "apll96_ck",
1894 "apll54_ck",
1895 "sync_32k_ick",
1896 "omapctrl_ick",
1897 "gpmc_fck",
1898 "sdrc_ick",
1899};
1900
1901/*
1902 * init code
1903 */
1904
1905int __init omap2420_clk_init(void)
1906{
1907 prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
1908 cpu_mask = RATE_IN_242X;
1909 rate_table = omap2420_rate_table;
1910
1911 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
1912
1913 omap2xxx_clkt_vps_check_bootloader_rates();
1914
1915 omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
1916
1917 omap2xxx_clkt_vps_late_init();
1918
1919 omap2_clk_disable_autoidle_all();
1920
1921 omap2_clk_enable_init_clocks(enable_init_clks,
1922 ARRAY_SIZE(enable_init_clks));
1923
1924 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
1925 (clk_get_rate(&sys_ck) / 1000000),
1926 (clk_get_rate(&sys_ck) / 100000) % 10,
1927 (clk_get_rate(&dpll_ck) / 1000000),
1928 (clk_get_rate(&mpu_ck) / 1000000));
1929
1930 return 0;
1931}
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
deleted file mode 100644
index 5e4b037bb24c..000000000000
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ /dev/null
@@ -1,2048 +0,0 @@
1/*
2 * OMAP2430 clock data
3 *
4 * Copyright (C) 2005-2009, 2012 Texas Instruments, Inc.
5 * Copyright (C) 2004-2011 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/kernel.h>
17#include <linux/clk.h>
18#include <linux/clk-private.h>
19#include <linux/list.h>
20
21#include "soc.h"
22#include "iomap.h"
23#include "clock.h"
24#include "clock2xxx.h"
25#include "opp2xxx.h"
26#include "cm2xxx.h"
27#include "prm2xxx.h"
28#include "prm-regbits-24xx.h"
29#include "cm-regbits-24xx.h"
30#include "sdrc.h"
31#include "control.h"
32
33#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
34
35/*
36 * 2430 clock tree.
37 *
38 * NOTE:In many cases here we are assigning a 'default' parent. In
39 * many cases the parent is selectable. The set parent calls will
40 * also switch sources.
41 *
42 * Several sources are given initial rates which may be wrong, this will
43 * be fixed up in the init func.
44 *
45 * Things are broadly separated below by clock domains. It is
46 * noteworthy that most peripherals have dependencies on multiple clock
47 * domains. Many get their interface clocks from the L4 domain, but get
48 * functional clocks from fixed sources or other core domain derived
49 * clocks.
50 */
51
52DEFINE_CLK_FIXED_RATE(alt_ck, CLK_IS_ROOT, 54000000, 0x0);
53
54DEFINE_CLK_FIXED_RATE(func_32k_ck, CLK_IS_ROOT, 32768, 0x0);
55
56DEFINE_CLK_FIXED_RATE(mcbsp_clks, CLK_IS_ROOT, 0x0, 0x0);
57
58static struct clk osc_ck;
59
60static const struct clk_ops osc_ck_ops = {
61 .enable = &omap2_enable_osc_ck,
62 .disable = omap2_disable_osc_ck,
63 .recalc_rate = &omap2_osc_clk_recalc,
64};
65
66static struct clk_hw_omap osc_ck_hw = {
67 .hw = {
68 .clk = &osc_ck,
69 },
70};
71
72static struct clk osc_ck = {
73 .name = "osc_ck",
74 .ops = &osc_ck_ops,
75 .hw = &osc_ck_hw.hw,
76 .flags = CLK_IS_ROOT,
77};
78
79DEFINE_CLK_FIXED_RATE(secure_32k_ck, CLK_IS_ROOT, 32768, 0x0);
80
81static struct clk sys_ck;
82
83static const char *sys_ck_parent_names[] = {
84 "osc_ck",
85};
86
87static const struct clk_ops sys_ck_ops = {
88 .init = &omap2_init_clk_clkdm,
89 .recalc_rate = &omap2xxx_sys_clk_recalc,
90};
91
92DEFINE_STRUCT_CLK_HW_OMAP(sys_ck, "wkup_clkdm");
93DEFINE_STRUCT_CLK(sys_ck, sys_ck_parent_names, sys_ck_ops);
94
95static struct dpll_data dpll_dd = {
96 .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
97 .mult_mask = OMAP24XX_DPLL_MULT_MASK,
98 .div1_mask = OMAP24XX_DPLL_DIV_MASK,
99 .clk_bypass = &sys_ck,
100 .clk_ref = &sys_ck,
101 .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
102 .enable_mask = OMAP24XX_EN_DPLL_MASK,
103 .max_multiplier = 1023,
104 .min_divider = 1,
105 .max_divider = 16,
106};
107
108static struct clk dpll_ck;
109
110static const char *dpll_ck_parent_names[] = {
111 "sys_ck",
112};
113
114static const struct clk_ops dpll_ck_ops = {
115 .init = &omap2_init_clk_clkdm,
116 .get_parent = &omap2_init_dpll_parent,
117 .recalc_rate = &omap2_dpllcore_recalc,
118 .round_rate = &omap2_dpll_round_rate,
119 .set_rate = &omap2_reprogram_dpllcore,
120};
121
122static struct clk_hw_omap dpll_ck_hw = {
123 .hw = {
124 .clk = &dpll_ck,
125 },
126 .ops = &clkhwops_omap2xxx_dpll,
127 .dpll_data = &dpll_dd,
128 .clkdm_name = "wkup_clkdm",
129};
130
131DEFINE_STRUCT_CLK(dpll_ck, dpll_ck_parent_names, dpll_ck_ops);
132
133static struct clk core_ck;
134
135static const char *core_ck_parent_names[] = {
136 "dpll_ck",
137};
138
139static const struct clk_ops core_ck_ops = {
140 .init = &omap2_init_clk_clkdm,
141};
142
143DEFINE_STRUCT_CLK_HW_OMAP(core_ck, "wkup_clkdm");
144DEFINE_STRUCT_CLK(core_ck, core_ck_parent_names, core_ck_ops);
145
146DEFINE_CLK_DIVIDER(core_l3_ck, "core_ck", &core_ck, 0x0,
147 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
148 OMAP24XX_CLKSEL_L3_SHIFT, OMAP24XX_CLKSEL_L3_WIDTH,
149 CLK_DIVIDER_ONE_BASED, NULL);
150
151DEFINE_CLK_DIVIDER(l4_ck, "core_l3_ck", &core_l3_ck, 0x0,
152 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
153 OMAP24XX_CLKSEL_L4_SHIFT, OMAP24XX_CLKSEL_L4_WIDTH,
154 CLK_DIVIDER_ONE_BASED, NULL);
155
156static struct clk aes_ick;
157
158static const char *aes_ick_parent_names[] = {
159 "l4_ck",
160};
161
162static const struct clk_ops aes_ick_ops = {
163 .init = &omap2_init_clk_clkdm,
164 .enable = &omap2_dflt_clk_enable,
165 .disable = &omap2_dflt_clk_disable,
166 .is_enabled = &omap2_dflt_clk_is_enabled,
167};
168
169static struct clk_hw_omap aes_ick_hw = {
170 .hw = {
171 .clk = &aes_ick,
172 },
173 .ops = &clkhwops_iclk_wait,
174 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
175 .enable_bit = OMAP24XX_EN_AES_SHIFT,
176 .clkdm_name = "core_l4_clkdm",
177};
178
179DEFINE_STRUCT_CLK(aes_ick, aes_ick_parent_names, aes_ick_ops);
180
181static struct clk apll54_ck;
182
183static const struct clk_ops apll54_ck_ops = {
184 .init = &omap2_init_clk_clkdm,
185 .enable = &omap2_clk_apll54_enable,
186 .disable = &omap2_clk_apll54_disable,
187 .recalc_rate = &omap2_clk_apll54_recalc,
188};
189
190static struct clk_hw_omap apll54_ck_hw = {
191 .hw = {
192 .clk = &apll54_ck,
193 },
194 .ops = &clkhwops_apll54,
195 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
196 .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT,
197 .flags = ENABLE_ON_INIT,
198 .clkdm_name = "wkup_clkdm",
199};
200
201DEFINE_STRUCT_CLK(apll54_ck, dpll_ck_parent_names, apll54_ck_ops);
202
203static struct clk apll96_ck;
204
205static const struct clk_ops apll96_ck_ops = {
206 .init = &omap2_init_clk_clkdm,
207 .enable = &omap2_clk_apll96_enable,
208 .disable = &omap2_clk_apll96_disable,
209 .recalc_rate = &omap2_clk_apll96_recalc,
210};
211
212static struct clk_hw_omap apll96_ck_hw = {
213 .hw = {
214 .clk = &apll96_ck,
215 },
216 .ops = &clkhwops_apll96,
217 .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
218 .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT,
219 .flags = ENABLE_ON_INIT,
220 .clkdm_name = "wkup_clkdm",
221};
222
223DEFINE_STRUCT_CLK(apll96_ck, dpll_ck_parent_names, apll96_ck_ops);
224
225static const char *func_96m_ck_parent_names[] = {
226 "apll96_ck", "alt_ck",
227};
228
229DEFINE_CLK_MUX(func_96m_ck, func_96m_ck_parent_names, NULL, 0x0,
230 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), OMAP2430_96M_SOURCE_SHIFT,
231 OMAP2430_96M_SOURCE_WIDTH, 0x0, NULL);
232
233static struct clk cam_fck;
234
235static const char *cam_fck_parent_names[] = {
236 "func_96m_ck",
237};
238
239static struct clk_hw_omap cam_fck_hw = {
240 .hw = {
241 .clk = &cam_fck,
242 },
243 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
244 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
245 .clkdm_name = "core_l3_clkdm",
246};
247
248DEFINE_STRUCT_CLK(cam_fck, cam_fck_parent_names, aes_ick_ops);
249
250static struct clk cam_ick;
251
252static struct clk_hw_omap cam_ick_hw = {
253 .hw = {
254 .clk = &cam_ick,
255 },
256 .ops = &clkhwops_iclk,
257 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
258 .enable_bit = OMAP24XX_EN_CAM_SHIFT,
259 .clkdm_name = "core_l4_clkdm",
260};
261
262DEFINE_STRUCT_CLK(cam_ick, aes_ick_parent_names, aes_ick_ops);
263
264static struct clk des_ick;
265
266static struct clk_hw_omap des_ick_hw = {
267 .hw = {
268 .clk = &des_ick,
269 },
270 .ops = &clkhwops_iclk_wait,
271 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
272 .enable_bit = OMAP24XX_EN_DES_SHIFT,
273 .clkdm_name = "core_l4_clkdm",
274};
275
276DEFINE_STRUCT_CLK(des_ick, aes_ick_parent_names, aes_ick_ops);
277
278static const struct clksel_rate dsp_fck_core_rates[] = {
279 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
280 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
281 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
282 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
283 { .div = 0 }
284};
285
286static const struct clksel dsp_fck_clksel[] = {
287 { .parent = &core_ck, .rates = dsp_fck_core_rates },
288 { .parent = NULL },
289};
290
291static const char *dsp_fck_parent_names[] = {
292 "core_ck",
293};
294
295static struct clk dsp_fck;
296
297static const struct clk_ops dsp_fck_ops = {
298 .init = &omap2_init_clk_clkdm,
299 .enable = &omap2_dflt_clk_enable,
300 .disable = &omap2_dflt_clk_disable,
301 .is_enabled = &omap2_dflt_clk_is_enabled,
302 .recalc_rate = &omap2_clksel_recalc,
303 .set_rate = &omap2_clksel_set_rate,
304 .round_rate = &omap2_clksel_round_rate,
305};
306
307DEFINE_CLK_OMAP_MUX_GATE(dsp_fck, "dsp_clkdm", dsp_fck_clksel,
308 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
309 OMAP24XX_CLKSEL_DSP_MASK,
310 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
311 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
312 dsp_fck_parent_names, dsp_fck_ops);
313
314static const struct clksel_rate dss1_fck_sys_rates[] = {
315 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
316 { .div = 0 }
317};
318
319static const struct clksel_rate dss1_fck_core_rates[] = {
320 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
321 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
322 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
323 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
324 { .div = 5, .val = 5, .flags = RATE_IN_24XX },
325 { .div = 6, .val = 6, .flags = RATE_IN_24XX },
326 { .div = 8, .val = 8, .flags = RATE_IN_24XX },
327 { .div = 9, .val = 9, .flags = RATE_IN_24XX },
328 { .div = 12, .val = 12, .flags = RATE_IN_24XX },
329 { .div = 16, .val = 16, .flags = RATE_IN_24XX },
330 { .div = 0 }
331};
332
333static const struct clksel dss1_fck_clksel[] = {
334 { .parent = &sys_ck, .rates = dss1_fck_sys_rates },
335 { .parent = &core_ck, .rates = dss1_fck_core_rates },
336 { .parent = NULL },
337};
338
339static const char *dss1_fck_parent_names[] = {
340 "sys_ck", "core_ck",
341};
342
343static const struct clk_ops dss1_fck_ops = {
344 .init = &omap2_init_clk_clkdm,
345 .enable = &omap2_dflt_clk_enable,
346 .disable = &omap2_dflt_clk_disable,
347 .is_enabled = &omap2_dflt_clk_is_enabled,
348 .recalc_rate = &omap2_clksel_recalc,
349 .get_parent = &omap2_clksel_find_parent_index,
350 .set_parent = &omap2_clksel_set_parent,
351};
352
353DEFINE_CLK_OMAP_MUX_GATE(dss1_fck, "dss_clkdm", dss1_fck_clksel,
354 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
355 OMAP24XX_CLKSEL_DSS1_MASK,
356 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
357 OMAP24XX_EN_DSS1_SHIFT, NULL,
358 dss1_fck_parent_names, dss1_fck_ops);
359
360static const struct clksel_rate dss2_fck_sys_rates[] = {
361 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
362 { .div = 0 }
363};
364
365static const struct clksel_rate dss2_fck_48m_rates[] = {
366 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
367 { .div = 0 }
368};
369
370static const struct clksel_rate func_48m_apll96_rates[] = {
371 { .div = 2, .val = 0, .flags = RATE_IN_24XX },
372 { .div = 0 }
373};
374
375static const struct clksel_rate func_48m_alt_rates[] = {
376 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
377 { .div = 0 }
378};
379
380static const struct clksel func_48m_clksel[] = {
381 { .parent = &apll96_ck, .rates = func_48m_apll96_rates },
382 { .parent = &alt_ck, .rates = func_48m_alt_rates },
383 { .parent = NULL },
384};
385
386static const char *func_48m_ck_parent_names[] = {
387 "apll96_ck", "alt_ck",
388};
389
390static struct clk func_48m_ck;
391
392static const struct clk_ops func_48m_ck_ops = {
393 .init = &omap2_init_clk_clkdm,
394 .recalc_rate = &omap2_clksel_recalc,
395 .set_rate = &omap2_clksel_set_rate,
396 .round_rate = &omap2_clksel_round_rate,
397 .get_parent = &omap2_clksel_find_parent_index,
398 .set_parent = &omap2_clksel_set_parent,
399};
400
401static struct clk_hw_omap func_48m_ck_hw = {
402 .hw = {
403 .clk = &func_48m_ck,
404 },
405 .clksel = func_48m_clksel,
406 .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
407 .clksel_mask = OMAP24XX_48M_SOURCE_MASK,
408 .clkdm_name = "wkup_clkdm",
409};
410
411DEFINE_STRUCT_CLK(func_48m_ck, func_48m_ck_parent_names, func_48m_ck_ops);
412
413static const struct clksel dss2_fck_clksel[] = {
414 { .parent = &sys_ck, .rates = dss2_fck_sys_rates },
415 { .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
416 { .parent = NULL },
417};
418
419static const char *dss2_fck_parent_names[] = {
420 "sys_ck", "func_48m_ck",
421};
422
423DEFINE_CLK_OMAP_MUX_GATE(dss2_fck, "dss_clkdm", dss2_fck_clksel,
424 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
425 OMAP24XX_CLKSEL_DSS2_MASK,
426 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
427 OMAP24XX_EN_DSS2_SHIFT, NULL,
428 dss2_fck_parent_names, dss1_fck_ops);
429
430static const char *func_54m_ck_parent_names[] = {
431 "apll54_ck", "alt_ck",
432};
433
434DEFINE_CLK_MUX(func_54m_ck, func_54m_ck_parent_names, NULL, 0x0,
435 OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
436 OMAP24XX_54M_SOURCE_SHIFT, OMAP24XX_54M_SOURCE_WIDTH, 0x0, NULL);
437
438static struct clk dss_54m_fck;
439
440static const char *dss_54m_fck_parent_names[] = {
441 "func_54m_ck",
442};
443
444static struct clk_hw_omap dss_54m_fck_hw = {
445 .hw = {
446 .clk = &dss_54m_fck,
447 },
448 .ops = &clkhwops_wait,
449 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
450 .enable_bit = OMAP24XX_EN_TV_SHIFT,
451 .clkdm_name = "dss_clkdm",
452};
453
454DEFINE_STRUCT_CLK(dss_54m_fck, dss_54m_fck_parent_names, aes_ick_ops);
455
456static struct clk dss_ick;
457
458static struct clk_hw_omap dss_ick_hw = {
459 .hw = {
460 .clk = &dss_ick,
461 },
462 .ops = &clkhwops_iclk,
463 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
464 .enable_bit = OMAP24XX_EN_DSS1_SHIFT,
465 .clkdm_name = "dss_clkdm",
466};
467
468DEFINE_STRUCT_CLK(dss_ick, aes_ick_parent_names, aes_ick_ops);
469
470static struct clk emul_ck;
471
472static struct clk_hw_omap emul_ck_hw = {
473 .hw = {
474 .clk = &emul_ck,
475 },
476 .enable_reg = OMAP2430_PRCM_CLKEMUL_CTRL,
477 .enable_bit = OMAP24XX_EMULATION_EN_SHIFT,
478 .clkdm_name = "wkup_clkdm",
479};
480
481DEFINE_STRUCT_CLK(emul_ck, dss_54m_fck_parent_names, aes_ick_ops);
482
483DEFINE_CLK_FIXED_FACTOR(func_12m_ck, "func_48m_ck", &func_48m_ck, 0x0, 1, 4);
484
485static struct clk fac_fck;
486
487static const char *fac_fck_parent_names[] = {
488 "func_12m_ck",
489};
490
491static struct clk_hw_omap fac_fck_hw = {
492 .hw = {
493 .clk = &fac_fck,
494 },
495 .ops = &clkhwops_wait,
496 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
497 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
498 .clkdm_name = "core_l4_clkdm",
499};
500
501DEFINE_STRUCT_CLK(fac_fck, fac_fck_parent_names, aes_ick_ops);
502
503static struct clk fac_ick;
504
505static struct clk_hw_omap fac_ick_hw = {
506 .hw = {
507 .clk = &fac_ick,
508 },
509 .ops = &clkhwops_iclk_wait,
510 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
511 .enable_bit = OMAP24XX_EN_FAC_SHIFT,
512 .clkdm_name = "core_l4_clkdm",
513};
514
515DEFINE_STRUCT_CLK(fac_ick, aes_ick_parent_names, aes_ick_ops);
516
517static const struct clksel gfx_fck_clksel[] = {
518 { .parent = &core_l3_ck, .rates = gfx_l3_rates },
519 { .parent = NULL },
520};
521
522static const char *gfx_2d_fck_parent_names[] = {
523 "core_l3_ck",
524};
525
526DEFINE_CLK_OMAP_MUX_GATE(gfx_2d_fck, "gfx_clkdm", gfx_fck_clksel,
527 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
528 OMAP_CLKSEL_GFX_MASK,
529 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
530 OMAP24XX_EN_2D_SHIFT, &clkhwops_wait,
531 gfx_2d_fck_parent_names, dsp_fck_ops);
532
533DEFINE_CLK_OMAP_MUX_GATE(gfx_3d_fck, "gfx_clkdm", gfx_fck_clksel,
534 OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
535 OMAP_CLKSEL_GFX_MASK,
536 OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
537 OMAP24XX_EN_3D_SHIFT, &clkhwops_wait,
538 gfx_2d_fck_parent_names, dsp_fck_ops);
539
540static struct clk gfx_ick;
541
542static const char *gfx_ick_parent_names[] = {
543 "core_l3_ck",
544};
545
546static struct clk_hw_omap gfx_ick_hw = {
547 .hw = {
548 .clk = &gfx_ick,
549 },
550 .ops = &clkhwops_wait,
551 .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
552 .enable_bit = OMAP_EN_GFX_SHIFT,
553 .clkdm_name = "gfx_clkdm",
554};
555
556DEFINE_STRUCT_CLK(gfx_ick, gfx_ick_parent_names, aes_ick_ops);
557
558static struct clk gpio5_fck;
559
560static const char *gpio5_fck_parent_names[] = {
561 "func_32k_ck",
562};
563
564static struct clk_hw_omap gpio5_fck_hw = {
565 .hw = {
566 .clk = &gpio5_fck,
567 },
568 .ops = &clkhwops_wait,
569 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
570 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
571 .clkdm_name = "core_l4_clkdm",
572};
573
574DEFINE_STRUCT_CLK(gpio5_fck, gpio5_fck_parent_names, aes_ick_ops);
575
576static struct clk gpio5_ick;
577
578static struct clk_hw_omap gpio5_ick_hw = {
579 .hw = {
580 .clk = &gpio5_ick,
581 },
582 .ops = &clkhwops_iclk_wait,
583 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
584 .enable_bit = OMAP2430_EN_GPIO5_SHIFT,
585 .clkdm_name = "core_l4_clkdm",
586};
587
588DEFINE_STRUCT_CLK(gpio5_ick, aes_ick_parent_names, aes_ick_ops);
589
590static struct clk gpios_fck;
591
592static struct clk_hw_omap gpios_fck_hw = {
593 .hw = {
594 .clk = &gpios_fck,
595 },
596 .ops = &clkhwops_wait,
597 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
598 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
599 .clkdm_name = "wkup_clkdm",
600};
601
602DEFINE_STRUCT_CLK(gpios_fck, gpio5_fck_parent_names, aes_ick_ops);
603
604static struct clk gpios_ick;
605
606static const char *gpios_ick_parent_names[] = {
607 "sys_ck",
608};
609
610static struct clk_hw_omap gpios_ick_hw = {
611 .hw = {
612 .clk = &gpios_ick,
613 },
614 .ops = &clkhwops_iclk_wait,
615 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
616 .enable_bit = OMAP24XX_EN_GPIOS_SHIFT,
617 .clkdm_name = "wkup_clkdm",
618};
619
620DEFINE_STRUCT_CLK(gpios_ick, gpios_ick_parent_names, aes_ick_ops);
621
622static struct clk gpmc_fck;
623
624static struct clk_hw_omap gpmc_fck_hw = {
625 .hw = {
626 .clk = &gpmc_fck,
627 },
628 .ops = &clkhwops_iclk,
629 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
630 .enable_bit = OMAP24XX_AUTO_GPMC_SHIFT,
631 .flags = ENABLE_ON_INIT,
632 .clkdm_name = "core_l3_clkdm",
633};
634
635DEFINE_STRUCT_CLK(gpmc_fck, gfx_ick_parent_names, core_ck_ops);
636
637static const struct clksel_rate gpt_alt_rates[] = {
638 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
639 { .div = 0 }
640};
641
642static const struct clksel omap24xx_gpt_clksel[] = {
643 { .parent = &func_32k_ck, .rates = gpt_32k_rates },
644 { .parent = &sys_ck, .rates = gpt_sys_rates },
645 { .parent = &alt_ck, .rates = gpt_alt_rates },
646 { .parent = NULL },
647};
648
649static const char *gpt10_fck_parent_names[] = {
650 "func_32k_ck", "sys_ck", "alt_ck",
651};
652
653DEFINE_CLK_OMAP_MUX_GATE(gpt10_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
654 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
655 OMAP24XX_CLKSEL_GPT10_MASK,
656 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
657 OMAP24XX_EN_GPT10_SHIFT, &clkhwops_wait,
658 gpt10_fck_parent_names, dss1_fck_ops);
659
660static struct clk gpt10_ick;
661
662static struct clk_hw_omap gpt10_ick_hw = {
663 .hw = {
664 .clk = &gpt10_ick,
665 },
666 .ops = &clkhwops_iclk_wait,
667 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
668 .enable_bit = OMAP24XX_EN_GPT10_SHIFT,
669 .clkdm_name = "core_l4_clkdm",
670};
671
672DEFINE_STRUCT_CLK(gpt10_ick, aes_ick_parent_names, aes_ick_ops);
673
674DEFINE_CLK_OMAP_MUX_GATE(gpt11_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
675 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
676 OMAP24XX_CLKSEL_GPT11_MASK,
677 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
678 OMAP24XX_EN_GPT11_SHIFT, &clkhwops_wait,
679 gpt10_fck_parent_names, dss1_fck_ops);
680
681static struct clk gpt11_ick;
682
683static struct clk_hw_omap gpt11_ick_hw = {
684 .hw = {
685 .clk = &gpt11_ick,
686 },
687 .ops = &clkhwops_iclk_wait,
688 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
689 .enable_bit = OMAP24XX_EN_GPT11_SHIFT,
690 .clkdm_name = "core_l4_clkdm",
691};
692
693DEFINE_STRUCT_CLK(gpt11_ick, aes_ick_parent_names, aes_ick_ops);
694
695DEFINE_CLK_OMAP_MUX_GATE(gpt12_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
696 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
697 OMAP24XX_CLKSEL_GPT12_MASK,
698 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
699 OMAP24XX_EN_GPT12_SHIFT, &clkhwops_wait,
700 gpt10_fck_parent_names, dss1_fck_ops);
701
702static struct clk gpt12_ick;
703
704static struct clk_hw_omap gpt12_ick_hw = {
705 .hw = {
706 .clk = &gpt12_ick,
707 },
708 .ops = &clkhwops_iclk_wait,
709 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
710 .enable_bit = OMAP24XX_EN_GPT12_SHIFT,
711 .clkdm_name = "core_l4_clkdm",
712};
713
714DEFINE_STRUCT_CLK(gpt12_ick, aes_ick_parent_names, aes_ick_ops);
715
716static const struct clk_ops gpt1_fck_ops = {
717 .init = &omap2_init_clk_clkdm,
718 .enable = &omap2_dflt_clk_enable,
719 .disable = &omap2_dflt_clk_disable,
720 .is_enabled = &omap2_dflt_clk_is_enabled,
721 .recalc_rate = &omap2_clksel_recalc,
722 .set_rate = &omap2_clksel_set_rate,
723 .round_rate = &omap2_clksel_round_rate,
724 .get_parent = &omap2_clksel_find_parent_index,
725 .set_parent = &omap2_clksel_set_parent,
726};
727
728DEFINE_CLK_OMAP_MUX_GATE(gpt1_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
729 OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
730 OMAP24XX_CLKSEL_GPT1_MASK,
731 OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
732 OMAP24XX_EN_GPT1_SHIFT, &clkhwops_wait,
733 gpt10_fck_parent_names, gpt1_fck_ops);
734
735static struct clk gpt1_ick;
736
737static struct clk_hw_omap gpt1_ick_hw = {
738 .hw = {
739 .clk = &gpt1_ick,
740 },
741 .ops = &clkhwops_iclk_wait,
742 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
743 .enable_bit = OMAP24XX_EN_GPT1_SHIFT,
744 .clkdm_name = "wkup_clkdm",
745};
746
747DEFINE_STRUCT_CLK(gpt1_ick, gpios_ick_parent_names, aes_ick_ops);
748
749DEFINE_CLK_OMAP_MUX_GATE(gpt2_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
750 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
751 OMAP24XX_CLKSEL_GPT2_MASK,
752 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
753 OMAP24XX_EN_GPT2_SHIFT, &clkhwops_wait,
754 gpt10_fck_parent_names, dss1_fck_ops);
755
756static struct clk gpt2_ick;
757
758static struct clk_hw_omap gpt2_ick_hw = {
759 .hw = {
760 .clk = &gpt2_ick,
761 },
762 .ops = &clkhwops_iclk_wait,
763 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
764 .enable_bit = OMAP24XX_EN_GPT2_SHIFT,
765 .clkdm_name = "core_l4_clkdm",
766};
767
768DEFINE_STRUCT_CLK(gpt2_ick, aes_ick_parent_names, aes_ick_ops);
769
770DEFINE_CLK_OMAP_MUX_GATE(gpt3_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
771 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
772 OMAP24XX_CLKSEL_GPT3_MASK,
773 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
774 OMAP24XX_EN_GPT3_SHIFT, &clkhwops_wait,
775 gpt10_fck_parent_names, dss1_fck_ops);
776
777static struct clk gpt3_ick;
778
779static struct clk_hw_omap gpt3_ick_hw = {
780 .hw = {
781 .clk = &gpt3_ick,
782 },
783 .ops = &clkhwops_iclk_wait,
784 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
785 .enable_bit = OMAP24XX_EN_GPT3_SHIFT,
786 .clkdm_name = "core_l4_clkdm",
787};
788
789DEFINE_STRUCT_CLK(gpt3_ick, aes_ick_parent_names, aes_ick_ops);
790
791DEFINE_CLK_OMAP_MUX_GATE(gpt4_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
792 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
793 OMAP24XX_CLKSEL_GPT4_MASK,
794 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
795 OMAP24XX_EN_GPT4_SHIFT, &clkhwops_wait,
796 gpt10_fck_parent_names, dss1_fck_ops);
797
798static struct clk gpt4_ick;
799
800static struct clk_hw_omap gpt4_ick_hw = {
801 .hw = {
802 .clk = &gpt4_ick,
803 },
804 .ops = &clkhwops_iclk_wait,
805 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
806 .enable_bit = OMAP24XX_EN_GPT4_SHIFT,
807 .clkdm_name = "core_l4_clkdm",
808};
809
810DEFINE_STRUCT_CLK(gpt4_ick, aes_ick_parent_names, aes_ick_ops);
811
812DEFINE_CLK_OMAP_MUX_GATE(gpt5_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
813 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
814 OMAP24XX_CLKSEL_GPT5_MASK,
815 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
816 OMAP24XX_EN_GPT5_SHIFT, &clkhwops_wait,
817 gpt10_fck_parent_names, dss1_fck_ops);
818
819static struct clk gpt5_ick;
820
821static struct clk_hw_omap gpt5_ick_hw = {
822 .hw = {
823 .clk = &gpt5_ick,
824 },
825 .ops = &clkhwops_iclk_wait,
826 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
827 .enable_bit = OMAP24XX_EN_GPT5_SHIFT,
828 .clkdm_name = "core_l4_clkdm",
829};
830
831DEFINE_STRUCT_CLK(gpt5_ick, aes_ick_parent_names, aes_ick_ops);
832
833DEFINE_CLK_OMAP_MUX_GATE(gpt6_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
834 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
835 OMAP24XX_CLKSEL_GPT6_MASK,
836 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
837 OMAP24XX_EN_GPT6_SHIFT, &clkhwops_wait,
838 gpt10_fck_parent_names, dss1_fck_ops);
839
840static struct clk gpt6_ick;
841
842static struct clk_hw_omap gpt6_ick_hw = {
843 .hw = {
844 .clk = &gpt6_ick,
845 },
846 .ops = &clkhwops_iclk_wait,
847 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
848 .enable_bit = OMAP24XX_EN_GPT6_SHIFT,
849 .clkdm_name = "core_l4_clkdm",
850};
851
852DEFINE_STRUCT_CLK(gpt6_ick, aes_ick_parent_names, aes_ick_ops);
853
854DEFINE_CLK_OMAP_MUX_GATE(gpt7_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
855 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
856 OMAP24XX_CLKSEL_GPT7_MASK,
857 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
858 OMAP24XX_EN_GPT7_SHIFT, &clkhwops_wait,
859 gpt10_fck_parent_names, dss1_fck_ops);
860
861static struct clk gpt7_ick;
862
863static struct clk_hw_omap gpt7_ick_hw = {
864 .hw = {
865 .clk = &gpt7_ick,
866 },
867 .ops = &clkhwops_iclk_wait,
868 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
869 .enable_bit = OMAP24XX_EN_GPT7_SHIFT,
870 .clkdm_name = "core_l4_clkdm",
871};
872
873DEFINE_STRUCT_CLK(gpt7_ick, aes_ick_parent_names, aes_ick_ops);
874
875static struct clk gpt8_fck;
876
877DEFINE_CLK_OMAP_MUX_GATE(gpt8_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
878 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
879 OMAP24XX_CLKSEL_GPT8_MASK,
880 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
881 OMAP24XX_EN_GPT8_SHIFT, &clkhwops_wait,
882 gpt10_fck_parent_names, dss1_fck_ops);
883
884static struct clk gpt8_ick;
885
886static struct clk_hw_omap gpt8_ick_hw = {
887 .hw = {
888 .clk = &gpt8_ick,
889 },
890 .ops = &clkhwops_iclk_wait,
891 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
892 .enable_bit = OMAP24XX_EN_GPT8_SHIFT,
893 .clkdm_name = "core_l4_clkdm",
894};
895
896DEFINE_STRUCT_CLK(gpt8_ick, aes_ick_parent_names, aes_ick_ops);
897
898DEFINE_CLK_OMAP_MUX_GATE(gpt9_fck, "core_l4_clkdm", omap24xx_gpt_clksel,
899 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
900 OMAP24XX_CLKSEL_GPT9_MASK,
901 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
902 OMAP24XX_EN_GPT9_SHIFT, &clkhwops_wait,
903 gpt10_fck_parent_names, dss1_fck_ops);
904
905static struct clk gpt9_ick;
906
907static struct clk_hw_omap gpt9_ick_hw = {
908 .hw = {
909 .clk = &gpt9_ick,
910 },
911 .ops = &clkhwops_iclk_wait,
912 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
913 .enable_bit = OMAP24XX_EN_GPT9_SHIFT,
914 .clkdm_name = "core_l4_clkdm",
915};
916
917DEFINE_STRUCT_CLK(gpt9_ick, aes_ick_parent_names, aes_ick_ops);
918
919static struct clk hdq_fck;
920
921static struct clk_hw_omap hdq_fck_hw = {
922 .hw = {
923 .clk = &hdq_fck,
924 },
925 .ops = &clkhwops_wait,
926 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
927 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
928 .clkdm_name = "core_l4_clkdm",
929};
930
931DEFINE_STRUCT_CLK(hdq_fck, fac_fck_parent_names, aes_ick_ops);
932
933static struct clk hdq_ick;
934
935static struct clk_hw_omap hdq_ick_hw = {
936 .hw = {
937 .clk = &hdq_ick,
938 },
939 .ops = &clkhwops_iclk_wait,
940 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
941 .enable_bit = OMAP24XX_EN_HDQ_SHIFT,
942 .clkdm_name = "core_l4_clkdm",
943};
944
945DEFINE_STRUCT_CLK(hdq_ick, aes_ick_parent_names, aes_ick_ops);
946
947static struct clk i2c1_ick;
948
949static struct clk_hw_omap i2c1_ick_hw = {
950 .hw = {
951 .clk = &i2c1_ick,
952 },
953 .ops = &clkhwops_iclk_wait,
954 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
955 .enable_bit = OMAP2420_EN_I2C1_SHIFT,
956 .clkdm_name = "core_l4_clkdm",
957};
958
959DEFINE_STRUCT_CLK(i2c1_ick, aes_ick_parent_names, aes_ick_ops);
960
961static struct clk i2c2_ick;
962
963static struct clk_hw_omap i2c2_ick_hw = {
964 .hw = {
965 .clk = &i2c2_ick,
966 },
967 .ops = &clkhwops_iclk_wait,
968 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
969 .enable_bit = OMAP2420_EN_I2C2_SHIFT,
970 .clkdm_name = "core_l4_clkdm",
971};
972
973DEFINE_STRUCT_CLK(i2c2_ick, aes_ick_parent_names, aes_ick_ops);
974
975static struct clk i2chs1_fck;
976
977static struct clk_hw_omap i2chs1_fck_hw = {
978 .hw = {
979 .clk = &i2chs1_fck,
980 },
981 .ops = &clkhwops_omap2430_i2chs_wait,
982 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
983 .enable_bit = OMAP2430_EN_I2CHS1_SHIFT,
984 .clkdm_name = "core_l4_clkdm",
985};
986
987DEFINE_STRUCT_CLK(i2chs1_fck, cam_fck_parent_names, aes_ick_ops);
988
989static struct clk i2chs2_fck;
990
991static struct clk_hw_omap i2chs2_fck_hw = {
992 .hw = {
993 .clk = &i2chs2_fck,
994 },
995 .ops = &clkhwops_omap2430_i2chs_wait,
996 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
997 .enable_bit = OMAP2430_EN_I2CHS2_SHIFT,
998 .clkdm_name = "core_l4_clkdm",
999};
1000
1001DEFINE_STRUCT_CLK(i2chs2_fck, cam_fck_parent_names, aes_ick_ops);
1002
1003static struct clk icr_ick;
1004
1005static struct clk_hw_omap icr_ick_hw = {
1006 .hw = {
1007 .clk = &icr_ick,
1008 },
1009 .ops = &clkhwops_iclk_wait,
1010 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1011 .enable_bit = OMAP2430_EN_ICR_SHIFT,
1012 .clkdm_name = "wkup_clkdm",
1013};
1014
1015DEFINE_STRUCT_CLK(icr_ick, gpios_ick_parent_names, aes_ick_ops);
1016
1017static const struct clksel dsp_ick_clksel[] = {
1018 { .parent = &dsp_fck, .rates = dsp_ick_rates },
1019 { .parent = NULL },
1020};
1021
1022static const char *iva2_1_ick_parent_names[] = {
1023 "dsp_fck",
1024};
1025
1026DEFINE_CLK_OMAP_MUX_GATE(iva2_1_ick, "dsp_clkdm", dsp_ick_clksel,
1027 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
1028 OMAP24XX_CLKSEL_DSP_IF_MASK,
1029 OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
1030 OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, &clkhwops_wait,
1031 iva2_1_ick_parent_names, dsp_fck_ops);
1032
1033static struct clk mailboxes_ick;
1034
1035static struct clk_hw_omap mailboxes_ick_hw = {
1036 .hw = {
1037 .clk = &mailboxes_ick,
1038 },
1039 .ops = &clkhwops_iclk_wait,
1040 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1041 .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
1042 .clkdm_name = "core_l4_clkdm",
1043};
1044
1045DEFINE_STRUCT_CLK(mailboxes_ick, aes_ick_parent_names, aes_ick_ops);
1046
1047static const struct clksel_rate common_mcbsp_96m_rates[] = {
1048 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1049 { .div = 0 }
1050};
1051
1052static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
1053 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1054 { .div = 0 }
1055};
1056
1057static const struct clksel mcbsp_fck_clksel[] = {
1058 { .parent = &func_96m_ck, .rates = common_mcbsp_96m_rates },
1059 { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates },
1060 { .parent = NULL },
1061};
1062
1063static const char *mcbsp1_fck_parent_names[] = {
1064 "func_96m_ck", "mcbsp_clks",
1065};
1066
1067DEFINE_CLK_OMAP_MUX_GATE(mcbsp1_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1068 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1069 OMAP2_MCBSP1_CLKS_MASK,
1070 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1071 OMAP24XX_EN_MCBSP1_SHIFT, &clkhwops_wait,
1072 mcbsp1_fck_parent_names, dss1_fck_ops);
1073
1074static struct clk mcbsp1_ick;
1075
1076static struct clk_hw_omap mcbsp1_ick_hw = {
1077 .hw = {
1078 .clk = &mcbsp1_ick,
1079 },
1080 .ops = &clkhwops_iclk_wait,
1081 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1082 .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT,
1083 .clkdm_name = "core_l4_clkdm",
1084};
1085
1086DEFINE_STRUCT_CLK(mcbsp1_ick, aes_ick_parent_names, aes_ick_ops);
1087
1088DEFINE_CLK_OMAP_MUX_GATE(mcbsp2_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1089 OMAP243X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
1090 OMAP2_MCBSP2_CLKS_MASK,
1091 OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1092 OMAP24XX_EN_MCBSP2_SHIFT, &clkhwops_wait,
1093 mcbsp1_fck_parent_names, dss1_fck_ops);
1094
1095static struct clk mcbsp2_ick;
1096
1097static struct clk_hw_omap mcbsp2_ick_hw = {
1098 .hw = {
1099 .clk = &mcbsp2_ick,
1100 },
1101 .ops = &clkhwops_iclk_wait,
1102 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1103 .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT,
1104 .clkdm_name = "core_l4_clkdm",
1105};
1106
1107DEFINE_STRUCT_CLK(mcbsp2_ick, aes_ick_parent_names, aes_ick_ops);
1108
1109DEFINE_CLK_OMAP_MUX_GATE(mcbsp3_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1110 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1111 OMAP2_MCBSP3_CLKS_MASK,
1112 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1113 OMAP2430_EN_MCBSP3_SHIFT, &clkhwops_wait,
1114 mcbsp1_fck_parent_names, dss1_fck_ops);
1115
1116static struct clk mcbsp3_ick;
1117
1118static struct clk_hw_omap mcbsp3_ick_hw = {
1119 .hw = {
1120 .clk = &mcbsp3_ick,
1121 },
1122 .ops = &clkhwops_iclk_wait,
1123 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1124 .enable_bit = OMAP2430_EN_MCBSP3_SHIFT,
1125 .clkdm_name = "core_l4_clkdm",
1126};
1127
1128DEFINE_STRUCT_CLK(mcbsp3_ick, aes_ick_parent_names, aes_ick_ops);
1129
1130DEFINE_CLK_OMAP_MUX_GATE(mcbsp4_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1131 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1132 OMAP2_MCBSP4_CLKS_MASK,
1133 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1134 OMAP2430_EN_MCBSP4_SHIFT, &clkhwops_wait,
1135 mcbsp1_fck_parent_names, dss1_fck_ops);
1136
1137static struct clk mcbsp4_ick;
1138
1139static struct clk_hw_omap mcbsp4_ick_hw = {
1140 .hw = {
1141 .clk = &mcbsp4_ick,
1142 },
1143 .ops = &clkhwops_iclk_wait,
1144 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1145 .enable_bit = OMAP2430_EN_MCBSP4_SHIFT,
1146 .clkdm_name = "core_l4_clkdm",
1147};
1148
1149DEFINE_STRUCT_CLK(mcbsp4_ick, aes_ick_parent_names, aes_ick_ops);
1150
1151DEFINE_CLK_OMAP_MUX_GATE(mcbsp5_fck, "core_l4_clkdm", mcbsp_fck_clksel,
1152 OMAP243X_CTRL_REGADDR(OMAP243X_CONTROL_DEVCONF1),
1153 OMAP2_MCBSP5_CLKS_MASK,
1154 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1155 OMAP2430_EN_MCBSP5_SHIFT, &clkhwops_wait,
1156 mcbsp1_fck_parent_names, dss1_fck_ops);
1157
1158static struct clk mcbsp5_ick;
1159
1160static struct clk_hw_omap mcbsp5_ick_hw = {
1161 .hw = {
1162 .clk = &mcbsp5_ick,
1163 },
1164 .ops = &clkhwops_iclk_wait,
1165 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1166 .enable_bit = OMAP2430_EN_MCBSP5_SHIFT,
1167 .clkdm_name = "core_l4_clkdm",
1168};
1169
1170DEFINE_STRUCT_CLK(mcbsp5_ick, aes_ick_parent_names, aes_ick_ops);
1171
1172static struct clk mcspi1_fck;
1173
1174static const char *mcspi1_fck_parent_names[] = {
1175 "func_48m_ck",
1176};
1177
1178static struct clk_hw_omap mcspi1_fck_hw = {
1179 .hw = {
1180 .clk = &mcspi1_fck,
1181 },
1182 .ops = &clkhwops_wait,
1183 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1184 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1185 .clkdm_name = "core_l4_clkdm",
1186};
1187
1188DEFINE_STRUCT_CLK(mcspi1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1189
1190static struct clk mcspi1_ick;
1191
1192static struct clk_hw_omap mcspi1_ick_hw = {
1193 .hw = {
1194 .clk = &mcspi1_ick,
1195 },
1196 .ops = &clkhwops_iclk_wait,
1197 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1198 .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT,
1199 .clkdm_name = "core_l4_clkdm",
1200};
1201
1202DEFINE_STRUCT_CLK(mcspi1_ick, aes_ick_parent_names, aes_ick_ops);
1203
1204static struct clk mcspi2_fck;
1205
1206static struct clk_hw_omap mcspi2_fck_hw = {
1207 .hw = {
1208 .clk = &mcspi2_fck,
1209 },
1210 .ops = &clkhwops_wait,
1211 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1212 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1213 .clkdm_name = "core_l4_clkdm",
1214};
1215
1216DEFINE_STRUCT_CLK(mcspi2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1217
1218static struct clk mcspi2_ick;
1219
1220static struct clk_hw_omap mcspi2_ick_hw = {
1221 .hw = {
1222 .clk = &mcspi2_ick,
1223 },
1224 .ops = &clkhwops_iclk_wait,
1225 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1226 .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT,
1227 .clkdm_name = "core_l4_clkdm",
1228};
1229
1230DEFINE_STRUCT_CLK(mcspi2_ick, aes_ick_parent_names, aes_ick_ops);
1231
1232static struct clk mcspi3_fck;
1233
1234static struct clk_hw_omap mcspi3_fck_hw = {
1235 .hw = {
1236 .clk = &mcspi3_fck,
1237 },
1238 .ops = &clkhwops_wait,
1239 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1240 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1241 .clkdm_name = "core_l4_clkdm",
1242};
1243
1244DEFINE_STRUCT_CLK(mcspi3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1245
1246static struct clk mcspi3_ick;
1247
1248static struct clk_hw_omap mcspi3_ick_hw = {
1249 .hw = {
1250 .clk = &mcspi3_ick,
1251 },
1252 .ops = &clkhwops_iclk_wait,
1253 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1254 .enable_bit = OMAP2430_EN_MCSPI3_SHIFT,
1255 .clkdm_name = "core_l4_clkdm",
1256};
1257
1258DEFINE_STRUCT_CLK(mcspi3_ick, aes_ick_parent_names, aes_ick_ops);
1259
1260static const struct clksel_rate mdm_ick_core_rates[] = {
1261 { .div = 1, .val = 1, .flags = RATE_IN_243X },
1262 { .div = 4, .val = 4, .flags = RATE_IN_243X },
1263 { .div = 6, .val = 6, .flags = RATE_IN_243X },
1264 { .div = 9, .val = 9, .flags = RATE_IN_243X },
1265 { .div = 0 }
1266};
1267
1268static const struct clksel mdm_ick_clksel[] = {
1269 { .parent = &core_ck, .rates = mdm_ick_core_rates },
1270 { .parent = NULL },
1271};
1272
1273static const char *mdm_ick_parent_names[] = {
1274 "core_ck",
1275};
1276
1277DEFINE_CLK_OMAP_MUX_GATE(mdm_ick, "mdm_clkdm", mdm_ick_clksel,
1278 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL),
1279 OMAP2430_CLKSEL_MDM_MASK,
1280 OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN),
1281 OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT,
1282 &clkhwops_iclk_wait, mdm_ick_parent_names,
1283 dsp_fck_ops);
1284
1285static struct clk mdm_intc_ick;
1286
1287static struct clk_hw_omap mdm_intc_ick_hw = {
1288 .hw = {
1289 .clk = &mdm_intc_ick,
1290 },
1291 .ops = &clkhwops_iclk_wait,
1292 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1293 .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT,
1294 .clkdm_name = "core_l4_clkdm",
1295};
1296
1297DEFINE_STRUCT_CLK(mdm_intc_ick, aes_ick_parent_names, aes_ick_ops);
1298
1299static struct clk mdm_osc_ck;
1300
1301static struct clk_hw_omap mdm_osc_ck_hw = {
1302 .hw = {
1303 .clk = &mdm_osc_ck,
1304 },
1305 .ops = &clkhwops_iclk_wait,
1306 .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN),
1307 .enable_bit = OMAP2430_EN_OSC_SHIFT,
1308 .clkdm_name = "mdm_clkdm",
1309};
1310
1311DEFINE_STRUCT_CLK(mdm_osc_ck, sys_ck_parent_names, aes_ick_ops);
1312
1313static struct clk mmchs1_fck;
1314
1315static struct clk_hw_omap mmchs1_fck_hw = {
1316 .hw = {
1317 .clk = &mmchs1_fck,
1318 },
1319 .ops = &clkhwops_wait,
1320 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1321 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1322 .clkdm_name = "core_l4_clkdm",
1323};
1324
1325DEFINE_STRUCT_CLK(mmchs1_fck, cam_fck_parent_names, aes_ick_ops);
1326
1327static struct clk mmchs1_ick;
1328
1329static struct clk_hw_omap mmchs1_ick_hw = {
1330 .hw = {
1331 .clk = &mmchs1_ick,
1332 },
1333 .ops = &clkhwops_iclk_wait,
1334 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1335 .enable_bit = OMAP2430_EN_MMCHS1_SHIFT,
1336 .clkdm_name = "core_l4_clkdm",
1337};
1338
1339DEFINE_STRUCT_CLK(mmchs1_ick, aes_ick_parent_names, aes_ick_ops);
1340
1341static struct clk mmchs2_fck;
1342
1343static struct clk_hw_omap mmchs2_fck_hw = {
1344 .hw = {
1345 .clk = &mmchs2_fck,
1346 },
1347 .ops = &clkhwops_wait,
1348 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1349 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1350 .clkdm_name = "core_l4_clkdm",
1351};
1352
1353DEFINE_STRUCT_CLK(mmchs2_fck, cam_fck_parent_names, aes_ick_ops);
1354
1355static struct clk mmchs2_ick;
1356
1357static struct clk_hw_omap mmchs2_ick_hw = {
1358 .hw = {
1359 .clk = &mmchs2_ick,
1360 },
1361 .ops = &clkhwops_iclk_wait,
1362 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1363 .enable_bit = OMAP2430_EN_MMCHS2_SHIFT,
1364 .clkdm_name = "core_l4_clkdm",
1365};
1366
1367DEFINE_STRUCT_CLK(mmchs2_ick, aes_ick_parent_names, aes_ick_ops);
1368
1369static struct clk mmchsdb1_fck;
1370
1371static struct clk_hw_omap mmchsdb1_fck_hw = {
1372 .hw = {
1373 .clk = &mmchsdb1_fck,
1374 },
1375 .ops = &clkhwops_wait,
1376 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1377 .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT,
1378 .clkdm_name = "core_l4_clkdm",
1379};
1380
1381DEFINE_STRUCT_CLK(mmchsdb1_fck, gpio5_fck_parent_names, aes_ick_ops);
1382
1383static struct clk mmchsdb2_fck;
1384
1385static struct clk_hw_omap mmchsdb2_fck_hw = {
1386 .hw = {
1387 .clk = &mmchsdb2_fck,
1388 },
1389 .ops = &clkhwops_wait,
1390 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1391 .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT,
1392 .clkdm_name = "core_l4_clkdm",
1393};
1394
1395DEFINE_STRUCT_CLK(mmchsdb2_fck, gpio5_fck_parent_names, aes_ick_ops);
1396
1397DEFINE_CLK_DIVIDER(mpu_ck, "core_ck", &core_ck, 0x0,
1398 OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
1399 OMAP24XX_CLKSEL_MPU_SHIFT, OMAP24XX_CLKSEL_MPU_WIDTH,
1400 CLK_DIVIDER_ONE_BASED, NULL);
1401
1402static struct clk mpu_wdt_fck;
1403
1404static struct clk_hw_omap mpu_wdt_fck_hw = {
1405 .hw = {
1406 .clk = &mpu_wdt_fck,
1407 },
1408 .ops = &clkhwops_wait,
1409 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
1410 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1411 .clkdm_name = "wkup_clkdm",
1412};
1413
1414DEFINE_STRUCT_CLK(mpu_wdt_fck, gpio5_fck_parent_names, aes_ick_ops);
1415
1416static struct clk mpu_wdt_ick;
1417
1418static struct clk_hw_omap mpu_wdt_ick_hw = {
1419 .hw = {
1420 .clk = &mpu_wdt_ick,
1421 },
1422 .ops = &clkhwops_iclk_wait,
1423 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1424 .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
1425 .clkdm_name = "wkup_clkdm",
1426};
1427
1428DEFINE_STRUCT_CLK(mpu_wdt_ick, gpios_ick_parent_names, aes_ick_ops);
1429
1430static struct clk mspro_fck;
1431
1432static struct clk_hw_omap mspro_fck_hw = {
1433 .hw = {
1434 .clk = &mspro_fck,
1435 },
1436 .ops = &clkhwops_wait,
1437 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1438 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1439 .clkdm_name = "core_l4_clkdm",
1440};
1441
1442DEFINE_STRUCT_CLK(mspro_fck, cam_fck_parent_names, aes_ick_ops);
1443
1444static struct clk mspro_ick;
1445
1446static struct clk_hw_omap mspro_ick_hw = {
1447 .hw = {
1448 .clk = &mspro_ick,
1449 },
1450 .ops = &clkhwops_iclk_wait,
1451 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1452 .enable_bit = OMAP24XX_EN_MSPRO_SHIFT,
1453 .clkdm_name = "core_l4_clkdm",
1454};
1455
1456DEFINE_STRUCT_CLK(mspro_ick, aes_ick_parent_names, aes_ick_ops);
1457
1458static struct clk omapctrl_ick;
1459
1460static struct clk_hw_omap omapctrl_ick_hw = {
1461 .hw = {
1462 .clk = &omapctrl_ick,
1463 },
1464 .ops = &clkhwops_iclk_wait,
1465 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1466 .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT,
1467 .flags = ENABLE_ON_INIT,
1468 .clkdm_name = "wkup_clkdm",
1469};
1470
1471DEFINE_STRUCT_CLK(omapctrl_ick, gpios_ick_parent_names, aes_ick_ops);
1472
1473static struct clk pka_ick;
1474
1475static struct clk_hw_omap pka_ick_hw = {
1476 .hw = {
1477 .clk = &pka_ick,
1478 },
1479 .ops = &clkhwops_iclk_wait,
1480 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1481 .enable_bit = OMAP24XX_EN_PKA_SHIFT,
1482 .clkdm_name = "core_l4_clkdm",
1483};
1484
1485DEFINE_STRUCT_CLK(pka_ick, aes_ick_parent_names, aes_ick_ops);
1486
1487static struct clk rng_ick;
1488
1489static struct clk_hw_omap rng_ick_hw = {
1490 .hw = {
1491 .clk = &rng_ick,
1492 },
1493 .ops = &clkhwops_iclk_wait,
1494 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1495 .enable_bit = OMAP24XX_EN_RNG_SHIFT,
1496 .clkdm_name = "core_l4_clkdm",
1497};
1498
1499DEFINE_STRUCT_CLK(rng_ick, aes_ick_parent_names, aes_ick_ops);
1500
1501static struct clk sdma_fck;
1502
1503DEFINE_STRUCT_CLK_HW_OMAP(sdma_fck, "core_l3_clkdm");
1504DEFINE_STRUCT_CLK(sdma_fck, gfx_ick_parent_names, core_ck_ops);
1505
1506static struct clk sdma_ick;
1507
1508static struct clk_hw_omap sdma_ick_hw = {
1509 .hw = {
1510 .clk = &sdma_ick,
1511 },
1512 .ops = &clkhwops_iclk,
1513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1514 .enable_bit = OMAP24XX_AUTO_SDMA_SHIFT,
1515 .clkdm_name = "core_l3_clkdm",
1516};
1517
1518DEFINE_STRUCT_CLK(sdma_ick, gfx_ick_parent_names, core_ck_ops);
1519
1520static struct clk sdrc_ick;
1521
1522static struct clk_hw_omap sdrc_ick_hw = {
1523 .hw = {
1524 .clk = &sdrc_ick,
1525 },
1526 .ops = &clkhwops_iclk,
1527 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1528 .enable_bit = OMAP2430_EN_SDRC_SHIFT,
1529 .flags = ENABLE_ON_INIT,
1530 .clkdm_name = "core_l3_clkdm",
1531};
1532
1533DEFINE_STRUCT_CLK(sdrc_ick, gfx_ick_parent_names, core_ck_ops);
1534
1535static struct clk sha_ick;
1536
1537static struct clk_hw_omap sha_ick_hw = {
1538 .hw = {
1539 .clk = &sha_ick,
1540 },
1541 .ops = &clkhwops_iclk_wait,
1542 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
1543 .enable_bit = OMAP24XX_EN_SHA_SHIFT,
1544 .clkdm_name = "core_l4_clkdm",
1545};
1546
1547DEFINE_STRUCT_CLK(sha_ick, aes_ick_parent_names, aes_ick_ops);
1548
1549static struct clk ssi_l4_ick;
1550
1551static struct clk_hw_omap ssi_l4_ick_hw = {
1552 .hw = {
1553 .clk = &ssi_l4_ick,
1554 },
1555 .ops = &clkhwops_iclk_wait,
1556 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1557 .enable_bit = OMAP24XX_EN_SSI_SHIFT,
1558 .clkdm_name = "core_l4_clkdm",
1559};
1560
1561DEFINE_STRUCT_CLK(ssi_l4_ick, aes_ick_parent_names, aes_ick_ops);
1562
1563static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
1564 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1565 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1566 { .div = 3, .val = 3, .flags = RATE_IN_24XX },
1567 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1568 { .div = 5, .val = 5, .flags = RATE_IN_243X },
1569 { .div = 0 }
1570};
1571
1572static const struct clksel ssi_ssr_sst_fck_clksel[] = {
1573 { .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
1574 { .parent = NULL },
1575};
1576
1577static const char *ssi_ssr_sst_fck_parent_names[] = {
1578 "core_ck",
1579};
1580
1581DEFINE_CLK_OMAP_MUX_GATE(ssi_ssr_sst_fck, "core_l3_clkdm",
1582 ssi_ssr_sst_fck_clksel,
1583 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1584 OMAP24XX_CLKSEL_SSI_MASK,
1585 OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1586 OMAP24XX_EN_SSI_SHIFT, &clkhwops_wait,
1587 ssi_ssr_sst_fck_parent_names, dsp_fck_ops);
1588
1589static struct clk sync_32k_ick;
1590
1591static struct clk_hw_omap sync_32k_ick_hw = {
1592 .hw = {
1593 .clk = &sync_32k_ick,
1594 },
1595 .ops = &clkhwops_iclk_wait,
1596 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1597 .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT,
1598 .flags = ENABLE_ON_INIT,
1599 .clkdm_name = "wkup_clkdm",
1600};
1601
1602DEFINE_STRUCT_CLK(sync_32k_ick, gpios_ick_parent_names, aes_ick_ops);
1603
1604static const struct clksel_rate common_clkout_src_core_rates[] = {
1605 { .div = 1, .val = 0, .flags = RATE_IN_24XX },
1606 { .div = 0 }
1607};
1608
1609static const struct clksel_rate common_clkout_src_sys_rates[] = {
1610 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1611 { .div = 0 }
1612};
1613
1614static const struct clksel_rate common_clkout_src_96m_rates[] = {
1615 { .div = 1, .val = 2, .flags = RATE_IN_24XX },
1616 { .div = 0 }
1617};
1618
1619static const struct clksel_rate common_clkout_src_54m_rates[] = {
1620 { .div = 1, .val = 3, .flags = RATE_IN_24XX },
1621 { .div = 0 }
1622};
1623
1624static const struct clksel common_clkout_src_clksel[] = {
1625 { .parent = &core_ck, .rates = common_clkout_src_core_rates },
1626 { .parent = &sys_ck, .rates = common_clkout_src_sys_rates },
1627 { .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
1628 { .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
1629 { .parent = NULL },
1630};
1631
1632static const char *sys_clkout_src_parent_names[] = {
1633 "core_ck", "sys_ck", "func_96m_ck", "func_54m_ck",
1634};
1635
1636DEFINE_CLK_OMAP_MUX_GATE(sys_clkout_src, "wkup_clkdm", common_clkout_src_clksel,
1637 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_SOURCE_MASK,
1638 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_EN_SHIFT,
1639 NULL, sys_clkout_src_parent_names, gpt1_fck_ops);
1640
1641DEFINE_CLK_DIVIDER(sys_clkout, "sys_clkout_src", &sys_clkout_src, 0x0,
1642 OMAP2430_PRCM_CLKOUT_CTRL, OMAP24XX_CLKOUT_DIV_SHIFT,
1643 OMAP24XX_CLKOUT_DIV_WIDTH, CLK_DIVIDER_POWER_OF_TWO, NULL);
1644
1645static struct clk uart1_fck;
1646
1647static struct clk_hw_omap uart1_fck_hw = {
1648 .hw = {
1649 .clk = &uart1_fck,
1650 },
1651 .ops = &clkhwops_wait,
1652 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1653 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1654 .clkdm_name = "core_l4_clkdm",
1655};
1656
1657DEFINE_STRUCT_CLK(uart1_fck, mcspi1_fck_parent_names, aes_ick_ops);
1658
1659static struct clk uart1_ick;
1660
1661static struct clk_hw_omap uart1_ick_hw = {
1662 .hw = {
1663 .clk = &uart1_ick,
1664 },
1665 .ops = &clkhwops_iclk_wait,
1666 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1667 .enable_bit = OMAP24XX_EN_UART1_SHIFT,
1668 .clkdm_name = "core_l4_clkdm",
1669};
1670
1671DEFINE_STRUCT_CLK(uart1_ick, aes_ick_parent_names, aes_ick_ops);
1672
1673static struct clk uart2_fck;
1674
1675static struct clk_hw_omap uart2_fck_hw = {
1676 .hw = {
1677 .clk = &uart2_fck,
1678 },
1679 .ops = &clkhwops_wait,
1680 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1681 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1682 .clkdm_name = "core_l4_clkdm",
1683};
1684
1685DEFINE_STRUCT_CLK(uart2_fck, mcspi1_fck_parent_names, aes_ick_ops);
1686
1687static struct clk uart2_ick;
1688
1689static struct clk_hw_omap uart2_ick_hw = {
1690 .hw = {
1691 .clk = &uart2_ick,
1692 },
1693 .ops = &clkhwops_iclk_wait,
1694 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1695 .enable_bit = OMAP24XX_EN_UART2_SHIFT,
1696 .clkdm_name = "core_l4_clkdm",
1697};
1698
1699DEFINE_STRUCT_CLK(uart2_ick, aes_ick_parent_names, aes_ick_ops);
1700
1701static struct clk uart3_fck;
1702
1703static struct clk_hw_omap uart3_fck_hw = {
1704 .hw = {
1705 .clk = &uart3_fck,
1706 },
1707 .ops = &clkhwops_wait,
1708 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1709 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1710 .clkdm_name = "core_l4_clkdm",
1711};
1712
1713DEFINE_STRUCT_CLK(uart3_fck, mcspi1_fck_parent_names, aes_ick_ops);
1714
1715static struct clk uart3_ick;
1716
1717static struct clk_hw_omap uart3_ick_hw = {
1718 .hw = {
1719 .clk = &uart3_ick,
1720 },
1721 .ops = &clkhwops_iclk_wait,
1722 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1723 .enable_bit = OMAP24XX_EN_UART3_SHIFT,
1724 .clkdm_name = "core_l4_clkdm",
1725};
1726
1727DEFINE_STRUCT_CLK(uart3_ick, aes_ick_parent_names, aes_ick_ops);
1728
1729static struct clk usb_fck;
1730
1731static struct clk_hw_omap usb_fck_hw = {
1732 .hw = {
1733 .clk = &usb_fck,
1734 },
1735 .ops = &clkhwops_wait,
1736 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
1737 .enable_bit = OMAP24XX_EN_USB_SHIFT,
1738 .clkdm_name = "core_l3_clkdm",
1739};
1740
1741DEFINE_STRUCT_CLK(usb_fck, mcspi1_fck_parent_names, aes_ick_ops);
1742
1743static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
1744 { .div = 1, .val = 1, .flags = RATE_IN_24XX },
1745 { .div = 2, .val = 2, .flags = RATE_IN_24XX },
1746 { .div = 4, .val = 4, .flags = RATE_IN_24XX },
1747 { .div = 0 }
1748};
1749
1750static const struct clksel usb_l4_ick_clksel[] = {
1751 { .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
1752 { .parent = NULL },
1753};
1754
1755static const char *usb_l4_ick_parent_names[] = {
1756 "core_l3_ck",
1757};
1758
1759DEFINE_CLK_OMAP_MUX_GATE(usb_l4_ick, "core_l4_clkdm", usb_l4_ick_clksel,
1760 OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
1761 OMAP24XX_CLKSEL_USB_MASK,
1762 OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1763 OMAP24XX_EN_USB_SHIFT, &clkhwops_iclk_wait,
1764 usb_l4_ick_parent_names, dsp_fck_ops);
1765
1766static struct clk usbhs_ick;
1767
1768static struct clk_hw_omap usbhs_ick_hw = {
1769 .hw = {
1770 .clk = &usbhs_ick,
1771 },
1772 .ops = &clkhwops_iclk_wait,
1773 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
1774 .enable_bit = OMAP2430_EN_USBHS_SHIFT,
1775 .clkdm_name = "core_l3_clkdm",
1776};
1777
1778DEFINE_STRUCT_CLK(usbhs_ick, gfx_ick_parent_names, aes_ick_ops);
1779
1780static struct clk virt_prcm_set;
1781
1782static const char *virt_prcm_set_parent_names[] = {
1783 "mpu_ck",
1784};
1785
1786static const struct clk_ops virt_prcm_set_ops = {
1787 .recalc_rate = &omap2_table_mpu_recalc,
1788 .set_rate = &omap2_select_table_rate,
1789 .round_rate = &omap2_round_to_table_rate,
1790};
1791
1792DEFINE_STRUCT_CLK_HW_OMAP(virt_prcm_set, NULL);
1793DEFINE_STRUCT_CLK(virt_prcm_set, virt_prcm_set_parent_names, virt_prcm_set_ops);
1794
1795static struct clk wdt1_ick;
1796
1797static struct clk_hw_omap wdt1_ick_hw = {
1798 .hw = {
1799 .clk = &wdt1_ick,
1800 },
1801 .ops = &clkhwops_iclk_wait,
1802 .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
1803 .enable_bit = OMAP24XX_EN_WDT1_SHIFT,
1804 .clkdm_name = "wkup_clkdm",
1805};
1806
1807DEFINE_STRUCT_CLK(wdt1_ick, gpios_ick_parent_names, aes_ick_ops);
1808
1809static struct clk wdt4_fck;
1810
1811static struct clk_hw_omap wdt4_fck_hw = {
1812 .hw = {
1813 .clk = &wdt4_fck,
1814 },
1815 .ops = &clkhwops_wait,
1816 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1817 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1818 .clkdm_name = "core_l4_clkdm",
1819};
1820
1821DEFINE_STRUCT_CLK(wdt4_fck, gpio5_fck_parent_names, aes_ick_ops);
1822
1823static struct clk wdt4_ick;
1824
1825static struct clk_hw_omap wdt4_ick_hw = {
1826 .hw = {
1827 .clk = &wdt4_ick,
1828 },
1829 .ops = &clkhwops_iclk_wait,
1830 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1831 .enable_bit = OMAP24XX_EN_WDT4_SHIFT,
1832 .clkdm_name = "core_l4_clkdm",
1833};
1834
1835DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
1836
1837/*
1838 * clkdev integration
1839 */
1840
1841static struct omap_clk omap2430_clks[] = {
1842 /* external root sources */
1843 CLK(NULL, "func_32k_ck", &func_32k_ck),
1844 CLK(NULL, "secure_32k_ck", &secure_32k_ck),
1845 CLK(NULL, "osc_ck", &osc_ck),
1846 CLK("twl", "fck", &osc_ck),
1847 CLK(NULL, "sys_ck", &sys_ck),
1848 CLK(NULL, "alt_ck", &alt_ck),
1849 CLK(NULL, "mcbsp_clks", &mcbsp_clks),
1850 /* internal analog sources */
1851 CLK(NULL, "dpll_ck", &dpll_ck),
1852 CLK(NULL, "apll96_ck", &apll96_ck),
1853 CLK(NULL, "apll54_ck", &apll54_ck),
1854 /* internal prcm root sources */
1855 CLK(NULL, "func_54m_ck", &func_54m_ck),
1856 CLK(NULL, "core_ck", &core_ck),
1857 CLK(NULL, "func_96m_ck", &func_96m_ck),
1858 CLK(NULL, "func_48m_ck", &func_48m_ck),
1859 CLK(NULL, "func_12m_ck", &func_12m_ck),
1860 CLK(NULL, "sys_clkout_src", &sys_clkout_src),
1861 CLK(NULL, "sys_clkout", &sys_clkout),
1862 CLK(NULL, "emul_ck", &emul_ck),
1863 /* mpu domain clocks */
1864 CLK(NULL, "mpu_ck", &mpu_ck),
1865 /* dsp domain clocks */
1866 CLK(NULL, "dsp_fck", &dsp_fck),
1867 CLK(NULL, "iva2_1_ick", &iva2_1_ick),
1868 /* GFX domain clocks */
1869 CLK(NULL, "gfx_3d_fck", &gfx_3d_fck),
1870 CLK(NULL, "gfx_2d_fck", &gfx_2d_fck),
1871 CLK(NULL, "gfx_ick", &gfx_ick),
1872 /* Modem domain clocks */
1873 CLK(NULL, "mdm_ick", &mdm_ick),
1874 CLK(NULL, "mdm_osc_ck", &mdm_osc_ck),
1875 /* DSS domain clocks */
1876 CLK("omapdss_dss", "ick", &dss_ick),
1877 CLK(NULL, "dss_ick", &dss_ick),
1878 CLK(NULL, "dss1_fck", &dss1_fck),
1879 CLK(NULL, "dss2_fck", &dss2_fck),
1880 CLK(NULL, "dss_54m_fck", &dss_54m_fck),
1881 /* L3 domain clocks */
1882 CLK(NULL, "core_l3_ck", &core_l3_ck),
1883 CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck),
1884 CLK(NULL, "usb_l4_ick", &usb_l4_ick),
1885 /* L4 domain clocks */
1886 CLK(NULL, "l4_ck", &l4_ck),
1887 CLK(NULL, "ssi_l4_ick", &ssi_l4_ick),
1888 /* virtual meta-group clock */
1889 CLK(NULL, "virt_prcm_set", &virt_prcm_set),
1890 /* general l4 interface ck, multi-parent functional clk */
1891 CLK(NULL, "gpt1_ick", &gpt1_ick),
1892 CLK(NULL, "gpt1_fck", &gpt1_fck),
1893 CLK(NULL, "gpt2_ick", &gpt2_ick),
1894 CLK(NULL, "gpt2_fck", &gpt2_fck),
1895 CLK(NULL, "gpt3_ick", &gpt3_ick),
1896 CLK(NULL, "gpt3_fck", &gpt3_fck),
1897 CLK(NULL, "gpt4_ick", &gpt4_ick),
1898 CLK(NULL, "gpt4_fck", &gpt4_fck),
1899 CLK(NULL, "gpt5_ick", &gpt5_ick),
1900 CLK(NULL, "gpt5_fck", &gpt5_fck),
1901 CLK(NULL, "gpt6_ick", &gpt6_ick),
1902 CLK(NULL, "gpt6_fck", &gpt6_fck),
1903 CLK(NULL, "gpt7_ick", &gpt7_ick),
1904 CLK(NULL, "gpt7_fck", &gpt7_fck),
1905 CLK(NULL, "gpt8_ick", &gpt8_ick),
1906 CLK(NULL, "gpt8_fck", &gpt8_fck),
1907 CLK(NULL, "gpt9_ick", &gpt9_ick),
1908 CLK(NULL, "gpt9_fck", &gpt9_fck),
1909 CLK(NULL, "gpt10_ick", &gpt10_ick),
1910 CLK(NULL, "gpt10_fck", &gpt10_fck),
1911 CLK(NULL, "gpt11_ick", &gpt11_ick),
1912 CLK(NULL, "gpt11_fck", &gpt11_fck),
1913 CLK(NULL, "gpt12_ick", &gpt12_ick),
1914 CLK(NULL, "gpt12_fck", &gpt12_fck),
1915 CLK("omap-mcbsp.1", "ick", &mcbsp1_ick),
1916 CLK(NULL, "mcbsp1_ick", &mcbsp1_ick),
1917 CLK(NULL, "mcbsp1_fck", &mcbsp1_fck),
1918 CLK("omap-mcbsp.2", "ick", &mcbsp2_ick),
1919 CLK(NULL, "mcbsp2_ick", &mcbsp2_ick),
1920 CLK(NULL, "mcbsp2_fck", &mcbsp2_fck),
1921 CLK("omap-mcbsp.3", "ick", &mcbsp3_ick),
1922 CLK(NULL, "mcbsp3_ick", &mcbsp3_ick),
1923 CLK(NULL, "mcbsp3_fck", &mcbsp3_fck),
1924 CLK("omap-mcbsp.4", "ick", &mcbsp4_ick),
1925 CLK(NULL, "mcbsp4_ick", &mcbsp4_ick),
1926 CLK(NULL, "mcbsp4_fck", &mcbsp4_fck),
1927 CLK("omap-mcbsp.5", "ick", &mcbsp5_ick),
1928 CLK(NULL, "mcbsp5_ick", &mcbsp5_ick),
1929 CLK(NULL, "mcbsp5_fck", &mcbsp5_fck),
1930 CLK("omap2_mcspi.1", "ick", &mcspi1_ick),
1931 CLK(NULL, "mcspi1_ick", &mcspi1_ick),
1932 CLK(NULL, "mcspi1_fck", &mcspi1_fck),
1933 CLK("omap2_mcspi.2", "ick", &mcspi2_ick),
1934 CLK(NULL, "mcspi2_ick", &mcspi2_ick),
1935 CLK(NULL, "mcspi2_fck", &mcspi2_fck),
1936 CLK("omap2_mcspi.3", "ick", &mcspi3_ick),
1937 CLK(NULL, "mcspi3_ick", &mcspi3_ick),
1938 CLK(NULL, "mcspi3_fck", &mcspi3_fck),
1939 CLK(NULL, "uart1_ick", &uart1_ick),
1940 CLK(NULL, "uart1_fck", &uart1_fck),
1941 CLK(NULL, "uart2_ick", &uart2_ick),
1942 CLK(NULL, "uart2_fck", &uart2_fck),
1943 CLK(NULL, "uart3_ick", &uart3_ick),
1944 CLK(NULL, "uart3_fck", &uart3_fck),
1945 CLK(NULL, "gpios_ick", &gpios_ick),
1946 CLK(NULL, "gpios_fck", &gpios_fck),
1947 CLK("omap_wdt", "ick", &mpu_wdt_ick),
1948 CLK(NULL, "mpu_wdt_ick", &mpu_wdt_ick),
1949 CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck),
1950 CLK(NULL, "sync_32k_ick", &sync_32k_ick),
1951 CLK(NULL, "wdt1_ick", &wdt1_ick),
1952 CLK(NULL, "omapctrl_ick", &omapctrl_ick),
1953 CLK(NULL, "icr_ick", &icr_ick),
1954 CLK("omap24xxcam", "fck", &cam_fck),
1955 CLK(NULL, "cam_fck", &cam_fck),
1956 CLK("omap24xxcam", "ick", &cam_ick),
1957 CLK(NULL, "cam_ick", &cam_ick),
1958 CLK(NULL, "mailboxes_ick", &mailboxes_ick),
1959 CLK(NULL, "wdt4_ick", &wdt4_ick),
1960 CLK(NULL, "wdt4_fck", &wdt4_fck),
1961 CLK(NULL, "mspro_ick", &mspro_ick),
1962 CLK(NULL, "mspro_fck", &mspro_fck),
1963 CLK(NULL, "fac_ick", &fac_ick),
1964 CLK(NULL, "fac_fck", &fac_fck),
1965 CLK("omap_hdq.0", "ick", &hdq_ick),
1966 CLK(NULL, "hdq_ick", &hdq_ick),
1967 CLK("omap_hdq.1", "fck", &hdq_fck),
1968 CLK(NULL, "hdq_fck", &hdq_fck),
1969 CLK("omap_i2c.1", "ick", &i2c1_ick),
1970 CLK(NULL, "i2c1_ick", &i2c1_ick),
1971 CLK(NULL, "i2chs1_fck", &i2chs1_fck),
1972 CLK("omap_i2c.2", "ick", &i2c2_ick),
1973 CLK(NULL, "i2c2_ick", &i2c2_ick),
1974 CLK(NULL, "i2chs2_fck", &i2chs2_fck),
1975 CLK(NULL, "gpmc_fck", &gpmc_fck),
1976 CLK(NULL, "sdma_fck", &sdma_fck),
1977 CLK(NULL, "sdma_ick", &sdma_ick),
1978 CLK(NULL, "sdrc_ick", &sdrc_ick),
1979 CLK(NULL, "des_ick", &des_ick),
1980 CLK("omap-sham", "ick", &sha_ick),
1981 CLK(NULL, "sha_ick", &sha_ick),
1982 CLK("omap_rng", "ick", &rng_ick),
1983 CLK(NULL, "rng_ick", &rng_ick),
1984 CLK("omap-aes", "ick", &aes_ick),
1985 CLK(NULL, "aes_ick", &aes_ick),
1986 CLK(NULL, "pka_ick", &pka_ick),
1987 CLK(NULL, "usb_fck", &usb_fck),
1988 CLK("musb-omap2430", "ick", &usbhs_ick),
1989 CLK(NULL, "usbhs_ick", &usbhs_ick),
1990 CLK("omap_hsmmc.0", "ick", &mmchs1_ick),
1991 CLK(NULL, "mmchs1_ick", &mmchs1_ick),
1992 CLK(NULL, "mmchs1_fck", &mmchs1_fck),
1993 CLK("omap_hsmmc.1", "ick", &mmchs2_ick),
1994 CLK(NULL, "mmchs2_ick", &mmchs2_ick),
1995 CLK(NULL, "mmchs2_fck", &mmchs2_fck),
1996 CLK(NULL, "gpio5_ick", &gpio5_ick),
1997 CLK(NULL, "gpio5_fck", &gpio5_fck),
1998 CLK(NULL, "mdm_intc_ick", &mdm_intc_ick),
1999 CLK("omap_hsmmc.0", "mmchsdb_fck", &mmchsdb1_fck),
2000 CLK(NULL, "mmchsdb1_fck", &mmchsdb1_fck),
2001 CLK("omap_hsmmc.1", "mmchsdb_fck", &mmchsdb2_fck),
2002 CLK(NULL, "mmchsdb2_fck", &mmchsdb2_fck),
2003 CLK(NULL, "timer_32k_ck", &func_32k_ck),
2004 CLK(NULL, "timer_sys_ck", &sys_ck),
2005 CLK(NULL, "timer_ext_ck", &alt_ck),
2006 CLK(NULL, "cpufreq_ck", &virt_prcm_set),
2007};
2008
2009static const char *enable_init_clks[] = {
2010 "apll96_ck",
2011 "apll54_ck",
2012 "sync_32k_ick",
2013 "omapctrl_ick",
2014 "gpmc_fck",
2015 "sdrc_ick",
2016};
2017
2018/*
2019 * init code
2020 */
2021
2022int __init omap2430_clk_init(void)
2023{
2024 prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
2025 cpu_mask = RATE_IN_243X;
2026 rate_table = omap2430_rate_table;
2027
2028 omap2xxx_clkt_dpllcore_init(&dpll_ck_hw.hw);
2029
2030 omap2xxx_clkt_vps_check_bootloader_rates();
2031
2032 omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
2033
2034 omap2xxx_clkt_vps_late_init();
2035
2036 omap2_clk_disable_autoidle_all();
2037
2038 omap2_clk_enable_init_clocks(enable_init_clks,
2039 ARRAY_SIZE(enable_init_clks));
2040
2041 pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
2042 (clk_get_rate(&sys_ck) / 1000000),
2043 (clk_get_rate(&sys_ck) / 100000) % 10,
2044 (clk_get_rate(&dpll_ck) / 1000000),
2045 (clk_get_rate(&mpu_ck) / 1000000));
2046
2047 return 0;
2048}
diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c
deleted file mode 100644
index 0717dff1bc04..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_osc.c
+++ /dev/null
@@ -1,69 +0,0 @@
1/*
2 * OMAP2xxx osc_clk-specific clock code
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/module.h>
21#include <linux/kernel.h>
22#include <linux/errno.h>
23#include <linux/clk.h>
24#include <linux/io.h>
25
26#include "clock.h"
27#include "clock2xxx.h"
28#include "prm2xxx_3xxx.h"
29#include "prm-regbits-24xx.h"
30
31/*
32 * XXX This does not actually enable the osc_ck, since the osc_ck must
33 * be running for this function to be called. Instead, this function
34 * is used to disable an autoidle mode on the osc_ck. The existing
35 * clk_enable/clk_disable()-based usecounting for osc_ck should be
36 * replaced with autoidle-based usecounting.
37 */
38int omap2_enable_osc_ck(struct clk_hw *clk)
39{
40 u32 pcc;
41
42 pcc = readl_relaxed(prcm_clksrc_ctrl);
43
44 writel_relaxed(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
45
46 return 0;
47}
48
49/*
50 * XXX This does not actually disable the osc_ck, since doing so would
51 * immediately halt the system. Instead, this function is used to
52 * enable an autoidle mode on the osc_ck. The existing
53 * clk_enable/clk_disable()-based usecounting for osc_ck should be
54 * replaced with autoidle-based usecounting.
55 */
56void omap2_disable_osc_ck(struct clk_hw *clk)
57{
58 u32 pcc;
59
60 pcc = readl_relaxed(prcm_clksrc_ctrl);
61
62 writel_relaxed(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl);
63}
64
65unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
66 unsigned long parent_rate)
67{
68 return omap2xxx_get_apll_clkin() * omap2xxx_get_sysclkdiv();
69}
diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c
deleted file mode 100644
index 58dd3a9b726c..000000000000
--- a/arch/arm/mach-omap2/clkt2xxx_sys.c
+++ /dev/null
@@ -1,47 +0,0 @@
1/*
2 * OMAP2xxx sys_clk-specific clock code
3 *
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
6 *
7 * Contacts:
8 * Richard Woodruff <r-woodruff2@ti.com>
9 * Paul Walmsley
10 *
11 * Based on earlier work by Tuukka Tikkanen, Tony Lindgren,
12 * Gordon McNutt and RidgeRun, Inc.
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 */
18#undef DEBUG
19
20#include <linux/kernel.h>
21#include <linux/errno.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include "clock.h"
26#include "clock2xxx.h"
27#include "prm2xxx_3xxx.h"
28#include "prm-regbits-24xx.h"
29
30void __iomem *prcm_clksrc_ctrl;
31
32u32 omap2xxx_get_sysclkdiv(void)
33{
34 u32 div;
35
36 div = readl_relaxed(prcm_clksrc_ctrl);
37 div &= OMAP_SYSCLKDIV_MASK;
38 div >>= OMAP_SYSCLKDIV_SHIFT;
39
40 return div;
41}
42
43unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
44 unsigned long parent_rate)
45{
46 return parent_rate / omap2xxx_get_sysclkdiv();
47}
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 5a0cac93d9ec..500530d1364a 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -100,27 +100,6 @@ u32 omap2_clk_readl(struct clk_hw_omap *clk, void __iomem *reg)
100} 100}
101 101
102/* 102/*
103 * Used for clocks that have the same value as the parent clock,
104 * divided by some factor
105 */
106unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
107 unsigned long parent_rate)
108{
109 struct clk_hw_omap *oclk;
110
111 if (!hw) {
112 pr_warn("%s: hw is NULL\n", __func__);
113 return -EINVAL;
114 }
115
116 oclk = to_clk_hw_omap(hw);
117
118 WARN_ON(!oclk->fixed_div);
119
120 return parent_rate / oclk->fixed_div;
121}
122
123/*
124 * OMAP2+ specific clock functions 103 * OMAP2+ specific clock functions
125 */ 104 */
126 105
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 0f100dc4e97f..4592a2762592 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -153,9 +153,6 @@ struct clksel {
153 const struct clksel_rate *rates; 153 const struct clksel_rate *rates;
154}; 154};
155 155
156unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
157 unsigned long parent_rate);
158
159/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ 156/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
160#define CORE_CLK_SRC_32K 0x0 157#define CORE_CLK_SRC_32K 0x0
161#define CORE_CLK_SRC_DPLL 0x1 158#define CORE_CLK_SRC_DPLL 0x1
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index 45f41a411603..a090225ceeba 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -45,8 +45,6 @@ int omap2430_clk_init(void);
45#define omap2430_clk_init() do { } while(0) 45#define omap2430_clk_init() do { } while(0)
46#endif 46#endif
47 47
48extern void __iomem *prcm_clksrc_ctrl;
49
50extern struct clk_hw *dclk_hw; 48extern struct clk_hw *dclk_hw;
51int omap2_enable_osc_ck(struct clk_hw *hw); 49int omap2_enable_osc_ck(struct clk_hw *hw);
52void omap2_disable_osc_ck(struct clk_hw *hw); 50void omap2_disable_osc_ck(struct clk_hw *hw);
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
index 8538669cc2ad..d7a5d11cbcbf 100644
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -107,6 +107,7 @@
107#define OMAP24XX_AUTO_DPLL_SHIFT 0 107#define OMAP24XX_AUTO_DPLL_SHIFT 0
108#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0) 108#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
109#define OMAP24XX_APLLS_CLKIN_SHIFT 23 109#define OMAP24XX_APLLS_CLKIN_SHIFT 23
110#define OMAP24XX_APLLS_CLKIN_WIDTH 3
110#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23) 111#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
111#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12) 112#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
112#define OMAP24XX_DPLL_DIV_MASK (0xf << 8) 113#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 1fae5c123f79..5d0667c119f6 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -53,6 +53,7 @@
53#include "prm2xxx.h" 53#include "prm2xxx.h"
54#include "prm3xxx.h" 54#include "prm3xxx.h"
55#include "prm44xx.h" 55#include "prm44xx.h"
56#include "opp2xxx.h"
56 57
57/* 58/*
58 * omap_clk_soc_init: points to a function that does the SoC-specific 59 * omap_clk_soc_init: points to a function that does the SoC-specific
@@ -410,7 +411,8 @@ void __init omap2420_init_early(void)
410 omap242x_clockdomains_init(); 411 omap242x_clockdomains_init();
411 omap2420_hwmod_init(); 412 omap2420_hwmod_init();
412 omap_hwmod_init_postsetup(); 413 omap_hwmod_init_postsetup();
413 omap_clk_soc_init = omap2420_clk_init; 414 omap_clk_soc_init = omap2420_dt_clk_init;
415 rate_table = omap2420_rate_table;
414} 416}
415 417
416void __init omap2420_init_late(void) 418void __init omap2420_init_late(void)
@@ -439,7 +441,8 @@ void __init omap2430_init_early(void)
439 omap243x_clockdomains_init(); 441 omap243x_clockdomains_init();
440 omap2430_hwmod_init(); 442 omap2430_hwmod_init();
441 omap_hwmod_init_postsetup(); 443 omap_hwmod_init_postsetup();
442 omap_clk_soc_init = omap2430_clk_init; 444 omap_clk_soc_init = omap2430_dt_clk_init;
445 rate_table = omap2430_rate_table;
443} 446}
444 447
445void __init omap2430_init_late(void) 448void __init omap2430_init_late(void)
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index d76694b7a591..fe01c5a03aa2 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -244,6 +244,10 @@ static void __init prcm_setup_regs(void)
244 /* Enable wake-up events */ 244 /* Enable wake-up events */
245 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, 245 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK,
246 WKUP_MOD, PM_WKEN); 246 WKUP_MOD, PM_WKEN);
247
248 /* Enable SYS_CLKEN control when all domains idle */
249 omap2_prm_set_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, OMAP24XX_GR_MOD,
250 OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
247} 251}
248 252
249int __init omap2_pm_init(void) 253int __init omap2_pm_init(void)
diff --git a/arch/arm/mach-omap2/prm_common.c b/arch/arm/mach-omap2/prm_common.c
index 25e8b8232115..76ca320f007c 100644
--- a/arch/arm/mach-omap2/prm_common.c
+++ b/arch/arm/mach-omap2/prm_common.c
@@ -472,6 +472,8 @@ static struct of_device_id omap_prcm_dt_match_table[] = {
472 { .compatible = "ti,am3-scrm" }, 472 { .compatible = "ti,am3-scrm" },
473 { .compatible = "ti,am4-prcm" }, 473 { .compatible = "ti,am4-prcm" },
474 { .compatible = "ti,am4-scrm" }, 474 { .compatible = "ti,am4-scrm" },
475 { .compatible = "ti,omap2-prcm" },
476 { .compatible = "ti,omap2-scrm" },
475 { .compatible = "ti,omap3-prm" }, 477 { .compatible = "ti,omap3-prm" },
476 { .compatible = "ti,omap3-cm" }, 478 { .compatible = "ti,omap3-cm" },
477 { .compatible = "ti,omap3-scrm" }, 479 { .compatible = "ti,omap3-scrm" },
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index e4564c259ed1..d1686696ca41 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -6,6 +6,7 @@ config ARCH_ROCKCHIP
6 select ARCH_REQUIRE_GPIOLIB 6 select ARCH_REQUIRE_GPIOLIB
7 select ARM_GIC 7 select ARM_GIC
8 select CACHE_L2X0 8 select CACHE_L2X0
9 select HAVE_ARM_ARCH_TIMER
9 select HAVE_ARM_SCU if SMP 10 select HAVE_ARM_SCU if SMP
10 select HAVE_ARM_TWD if SMP 11 select HAVE_ARM_TWD if SMP
11 select DW_APB_TIMER_OF 12 select DW_APB_TIMER_OF
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index 968cc348e624..8ab9e0e7ff04 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -29,6 +29,7 @@ static const char * const rockchip_board_dt_compat[] = {
29 "rockchip,rk3066a", 29 "rockchip,rk3066a",
30 "rockchip,rk3066b", 30 "rockchip,rk3066b",
31 "rockchip,rk3188", 31 "rockchip,rk3188",
32 "rockchip,rk3288",
32 NULL, 33 NULL,
33}; 34};
34 35
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c
index 49d139748aa6..c2330ea1802c 100644
--- a/arch/arm/mach-shmobile/clock-r8a73a4.c
+++ b/arch/arm/mach-shmobile/clock-r8a73a4.c
@@ -604,6 +604,7 @@ static struct clk_lookup lookups[] = {
604 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]), 604 CLKDEV_DEV_ID("e6500000.i2c", &mstp_clks[MSTP318]),
605 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]), 605 CLKDEV_DEV_ID("e6510000.i2c", &mstp_clks[MSTP323]),
606 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]), 606 CLKDEV_ICK_ID("fck", "sh-cmt-48-gen2.1", &mstp_clks[MSTP329]),
607 CLKDEV_ICK_ID("fck", "e6130000.timer", &mstp_clks[MSTP329]),
607 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]), 608 CLKDEV_DEV_ID("e60b0000.i2c", &mstp_clks[MSTP409]),
608 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]), 609 CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP410]),
609 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]), 610 CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP411]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c
index a60c324df64e..0794f0426e70 100644
--- a/arch/arm/mach-shmobile/clock-r8a7740.c
+++ b/arch/arm/mach-shmobile/clock-r8a7740.c
@@ -599,8 +599,11 @@ static struct clk_lookup lookups[] = {
599 599
600 /* ICK */ 600 /* ICK */
601 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]), 601 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP111]),
602 CLKDEV_ICK_ID("fck", "fff90000.timer", &mstp_clks[MSTP111]),
602 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), 603 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]),
604 CLKDEV_ICK_ID("fck", "fff80000.timer", &mstp_clks[MSTP125]),
603 CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), 605 CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]),
606 CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]),
604 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]), 607 CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
605 CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]), 608 CLKDEV_ICK_ID("func", "renesas_usbhs", &mstp_clks[MSTP407]),
606 CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]), 609 CLKDEV_ICK_ID("phy", "renesas_usbhs", &mstp_clks[MSTP406]),
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c
index 95579073cfce..67980a08a601 100644
--- a/arch/arm/mach-shmobile/clock-r8a7778.c
+++ b/arch/arm/mach-shmobile/clock-r8a7778.c
@@ -244,7 +244,9 @@ static struct clk_lookup lookups[] = {
244 CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]), 244 CLKDEV_ICK_ID("src.7", "rcar_sound", &mstp_clks[MSTP524]),
245 CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]), 245 CLKDEV_ICK_ID("src.8", "rcar_sound", &mstp_clks[MSTP523]),
246 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]), 246 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP016]),
247 CLKDEV_ICK_ID("fck", "ffd80000.timer", &mstp_clks[MSTP016]),
247 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]), 248 CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP015]),
249 CLKDEV_ICK_ID("fck", "ffd81000.timer", &mstp_clks[MSTP015]),
248}; 250};
249 251
250void __init r8a7778_clock_init(void) 252void __init r8a7778_clock_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 9433a4e2c88e..d8c4048b9e33 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -690,6 +690,7 @@ static struct clk_lookup lookups[] = {
690 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk), 690 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.0", &dsi0phy_clk),
691 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk), 691 CLKDEV_ICK_ID("dsiphy_clk", "sh-mipi-dsi.1", &dsi1phy_clk),
692 CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */ 692 CLKDEV_ICK_ID("fck", "sh-cmt-48.1", &mstp_clks[MSTP329]), /* CMT1 */
693 CLKDEV_ICK_ID("fck", "e6138000.timer", &mstp_clks[MSTP329]), /* CMT1 */
693 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */ 694 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
694}; 695};
695 696
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c
index cc9823246847..6683072a9d98 100644
--- a/arch/arm/mach-shmobile/setup-r8a73a4.c
+++ b/arch/arm/mach-shmobile/setup-r8a73a4.c
@@ -189,12 +189,6 @@ static struct resource cmt1_resources[] = {
189 189
190void __init r8a73a4_add_dt_devices(void) 190void __init r8a73a4_add_dt_devices(void)
191{ 191{
192 r8a73a4_register_scif(0);
193 r8a73a4_register_scif(1);
194 r8a73a4_register_scif(2);
195 r8a73a4_register_scif(3);
196 r8a73a4_register_scif(4);
197 r8a73a4_register_scif(5);
198 r8a7790_register_cmt(1); 192 r8a7790_register_cmt(1);
199} 193}
200 194
@@ -289,6 +283,12 @@ static struct resource dma_resources[] = {
289void __init r8a73a4_add_standard_devices(void) 283void __init r8a73a4_add_standard_devices(void)
290{ 284{
291 r8a73a4_add_dt_devices(); 285 r8a73a4_add_dt_devices();
286 r8a73a4_register_scif(0);
287 r8a73a4_register_scif(1);
288 r8a73a4_register_scif(2);
289 r8a73a4_register_scif(3);
290 r8a73a4_register_scif(4);
291 r8a73a4_register_scif(5);
292 r8a73a4_register_irqc(0); 292 r8a73a4_register_irqc(0);
293 r8a73a4_register_irqc(1); 293 r8a73a4_register_irqc(1);
294 r8a73a4_register_thermal(); 294 r8a73a4_register_thermal();
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c
index 348af358a239..3d5eacaba3e6 100644
--- a/arch/arm/mach-shmobile/setup-r8a7740.c
+++ b/arch/arm/mach-shmobile/setup-r8a7740.c
@@ -312,6 +312,10 @@ static struct platform_device ipmmu_device = {
312}; 312};
313 313
314static struct platform_device *r8a7740_devices_dt[] __initdata = { 314static struct platform_device *r8a7740_devices_dt[] __initdata = {
315 &cmt1_device,
316};
317
318static struct platform_device *r8a7740_early_devices[] __initdata = {
315 &scif0_device, 319 &scif0_device,
316 &scif1_device, 320 &scif1_device,
317 &scif2_device, 321 &scif2_device,
@@ -321,10 +325,6 @@ static struct platform_device *r8a7740_devices_dt[] __initdata = {
321 &scif6_device, 325 &scif6_device,
322 &scif7_device, 326 &scif7_device,
323 &scif8_device, 327 &scif8_device,
324 &cmt1_device,
325};
326
327static struct platform_device *r8a7740_early_devices[] __initdata = {
328 &irqpin0_device, 328 &irqpin0_device,
329 &irqpin1_device, 329 &irqpin1_device,
330 &irqpin2_device, 330 &irqpin2_device,
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index 18490af0d0a0..f00a488dcf43 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -293,12 +293,6 @@ void __init r8a7778_add_dt_devices(void)
293 } 293 }
294#endif 294#endif
295 295
296 r8a7778_register_scif(0);
297 r8a7778_register_scif(1);
298 r8a7778_register_scif(2);
299 r8a7778_register_scif(3);
300 r8a7778_register_scif(4);
301 r8a7778_register_scif(5);
302 r8a7778_register_tmu(0); 296 r8a7778_register_tmu(0);
303} 297}
304 298
@@ -507,6 +501,12 @@ static void __init r8a7778_register_hpb_dmae(void)
507void __init r8a7778_add_standard_devices(void) 501void __init r8a7778_add_standard_devices(void)
508{ 502{
509 r8a7778_add_dt_devices(); 503 r8a7778_add_dt_devices();
504 r8a7778_register_scif(0);
505 r8a7778_register_scif(1);
506 r8a7778_register_scif(2);
507 r8a7778_register_scif(3);
508 r8a7778_register_scif(4);
509 r8a7778_register_scif(5);
510 r8a7778_register_i2c(0); 510 r8a7778_register_i2c(0);
511 r8a7778_register_i2c(1); 511 r8a7778_register_i2c(1);
512 r8a7778_register_i2c(2); 512 r8a7778_register_i2c(2);
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 224882151667..2c802ae9b241 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -697,6 +697,10 @@ static struct platform_device irqpin3_device = {
697}; 697};
698 698
699static struct platform_device *sh73a0_devices_dt[] __initdata = { 699static struct platform_device *sh73a0_devices_dt[] __initdata = {
700 &cmt1_device,
701};
702
703static struct platform_device *sh73a0_early_devices[] __initdata = {
700 &scif0_device, 704 &scif0_device,
701 &scif1_device, 705 &scif1_device,
702 &scif2_device, 706 &scif2_device,
@@ -706,10 +710,6 @@ static struct platform_device *sh73a0_devices_dt[] __initdata = {
706 &scif6_device, 710 &scif6_device,
707 &scif7_device, 711 &scif7_device,
708 &scif8_device, 712 &scif8_device,
709 &cmt1_device,
710};
711
712static struct platform_device *sh73a0_early_devices[] __initdata = {
713 &tmu0_device, 713 &tmu0_device,
714 &ipmmu_device, 714 &ipmmu_device,
715}; 715};
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-23 20:51:18 -0500