diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-omap2/clock24xx.h | 238 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/mach/clock.h | 3 |
2 files changed, 190 insertions, 51 deletions
diff --git a/arch/arm/mach-omap2/clock24xx.h b/arch/arm/mach-omap2/clock24xx.h index be4e25554e05..242a19d86ccd 100644 --- a/arch/arm/mach-omap2/clock24xx.h +++ b/arch/arm/mach-omap2/clock24xx.h | |||
@@ -626,6 +626,7 @@ static struct clk func_32k_ck = { | |||
626 | .rate = 32000, | 626 | .rate = 32000, |
627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 627 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
628 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | 628 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
629 | .clkdm_name = "wkup_clkdm", | ||
629 | .recalc = &propagate_rate, | 630 | .recalc = &propagate_rate, |
630 | }; | 631 | }; |
631 | 632 | ||
@@ -634,17 +635,19 @@ static struct clk osc_ck = { /* (*12, *13, 19.2, *26, 38.4)MHz */ | |||
634 | .name = "osc_ck", | 635 | .name = "osc_ck", |
635 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 636 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
636 | RATE_PROPAGATES, | 637 | RATE_PROPAGATES, |
638 | .clkdm_name = "wkup_clkdm", | ||
637 | .enable = &omap2_enable_osc_ck, | 639 | .enable = &omap2_enable_osc_ck, |
638 | .disable = &omap2_disable_osc_ck, | 640 | .disable = &omap2_disable_osc_ck, |
639 | .recalc = &omap2_osc_clk_recalc, | 641 | .recalc = &omap2_osc_clk_recalc, |
640 | }; | 642 | }; |
641 | 643 | ||
642 | /* With out modem likely 12MHz, with modem likely 13MHz */ | 644 | /* Without modem likely 12MHz, with modem likely 13MHz */ |
643 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ | 645 | static struct clk sys_ck = { /* (*12, *13, 19.2, 26, 38.4)MHz */ |
644 | .name = "sys_ck", /* ~ ref_clk also */ | 646 | .name = "sys_ck", /* ~ ref_clk also */ |
645 | .parent = &osc_ck, | 647 | .parent = &osc_ck, |
646 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 648 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
647 | ALWAYS_ENABLED | RATE_PROPAGATES, | 649 | ALWAYS_ENABLED | RATE_PROPAGATES, |
650 | .clkdm_name = "wkup_clkdm", | ||
648 | .recalc = &omap2_sys_clk_recalc, | 651 | .recalc = &omap2_sys_clk_recalc, |
649 | }; | 652 | }; |
650 | 653 | ||
@@ -653,6 +656,7 @@ static struct clk alt_ck = { /* Typical 54M or 48M, may not exist */ | |||
653 | .rate = 54000000, | 656 | .rate = 54000000, |
654 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 657 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
655 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, | 658 | RATE_FIXED | ALWAYS_ENABLED | RATE_PROPAGATES, |
659 | .clkdm_name = "wkup_clkdm", | ||
656 | .recalc = &propagate_rate, | 660 | .recalc = &propagate_rate, |
657 | }; | 661 | }; |
658 | 662 | ||
@@ -684,6 +688,7 @@ static struct clk dpll_ck = { | |||
684 | .dpll_data = &dpll_dd, | 688 | .dpll_data = &dpll_dd, |
685 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 689 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
686 | RATE_PROPAGATES | ALWAYS_ENABLED, | 690 | RATE_PROPAGATES | ALWAYS_ENABLED, |
691 | .clkdm_name = "wkup_clkdm", | ||
687 | .recalc = &omap2_dpllcore_recalc, | 692 | .recalc = &omap2_dpllcore_recalc, |
688 | .set_rate = &omap2_reprogram_dpllcore, | 693 | .set_rate = &omap2_reprogram_dpllcore, |
689 | }; | 694 | }; |
@@ -694,6 +699,7 @@ static struct clk apll96_ck = { | |||
694 | .rate = 96000000, | 699 | .rate = 96000000, |
695 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 700 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
696 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | 701 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
702 | .clkdm_name = "wkup_clkdm", | ||
697 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 703 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
698 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, | 704 | .enable_bit = OMAP24XX_EN_96M_PLL_SHIFT, |
699 | .enable = &omap2_clk_fixed_enable, | 705 | .enable = &omap2_clk_fixed_enable, |
@@ -707,6 +713,7 @@ static struct clk apll54_ck = { | |||
707 | .rate = 54000000, | 713 | .rate = 54000000, |
708 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 714 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
709 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, | 715 | RATE_FIXED | RATE_PROPAGATES | ENABLE_ON_INIT, |
716 | .clkdm_name = "wkup_clkdm", | ||
710 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | 717 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
711 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, | 718 | .enable_bit = OMAP24XX_EN_54M_PLL_SHIFT, |
712 | .enable = &omap2_clk_fixed_enable, | 719 | .enable = &omap2_clk_fixed_enable, |
@@ -741,6 +748,7 @@ static struct clk func_54m_ck = { | |||
741 | .parent = &apll54_ck, /* can also be alt_clk */ | 748 | .parent = &apll54_ck, /* can also be alt_clk */ |
742 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
743 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | 750 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, |
751 | .clkdm_name = "wkup_clkdm", | ||
744 | .init = &omap2_init_clksel_parent, | 752 | .init = &omap2_init_clksel_parent, |
745 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 753 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
746 | .clksel_mask = OMAP24XX_54M_SOURCE, | 754 | .clksel_mask = OMAP24XX_54M_SOURCE, |
@@ -753,6 +761,7 @@ static struct clk core_ck = { | |||
753 | .parent = &dpll_ck, /* can also be 32k */ | 761 | .parent = &dpll_ck, /* can also be 32k */ |
754 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 762 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
755 | ALWAYS_ENABLED | RATE_PROPAGATES, | 763 | ALWAYS_ENABLED | RATE_PROPAGATES, |
764 | .clkdm_name = "wkup_clkdm", | ||
756 | .recalc = &followparent_recalc, | 765 | .recalc = &followparent_recalc, |
757 | }; | 766 | }; |
758 | 767 | ||
@@ -779,6 +788,7 @@ static struct clk func_96m_ck = { | |||
779 | .parent = &apll96_ck, | 788 | .parent = &apll96_ck, |
780 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 789 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
781 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | 790 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, |
791 | .clkdm_name = "wkup_clkdm", | ||
782 | .init = &omap2_init_clksel_parent, | 792 | .init = &omap2_init_clksel_parent, |
783 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 793 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
784 | .clksel_mask = OMAP2430_96M_SOURCE, | 794 | .clksel_mask = OMAP2430_96M_SOURCE, |
@@ -811,6 +821,7 @@ static struct clk func_48m_ck = { | |||
811 | .parent = &apll96_ck, /* 96M or Alt */ | 821 | .parent = &apll96_ck, /* 96M or Alt */ |
812 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 822 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
813 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | 823 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, |
824 | .clkdm_name = "wkup_clkdm", | ||
814 | .init = &omap2_init_clksel_parent, | 825 | .init = &omap2_init_clksel_parent, |
815 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | 826 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
816 | .clksel_mask = OMAP24XX_48M_SOURCE, | 827 | .clksel_mask = OMAP24XX_48M_SOURCE, |
@@ -826,6 +837,7 @@ static struct clk func_12m_ck = { | |||
826 | .fixed_div = 4, | 837 | .fixed_div = 4, |
827 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 838 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
828 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, | 839 | RATE_PROPAGATES | PARENT_CONTROLS_CLOCK, |
840 | .clkdm_name = "wkup_clkdm", | ||
829 | .recalc = &omap2_fixed_divisor_recalc, | 841 | .recalc = &omap2_fixed_divisor_recalc, |
830 | }; | 842 | }; |
831 | 843 | ||
@@ -878,6 +890,7 @@ static struct clk sys_clkout_src = { | |||
878 | .parent = &func_54m_ck, | 890 | .parent = &func_54m_ck, |
879 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 891 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
880 | RATE_PROPAGATES, | 892 | RATE_PROPAGATES, |
893 | .clkdm_name = "wkup_clkdm", | ||
881 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 894 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
882 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, | 895 | .enable_bit = OMAP24XX_CLKOUT_EN_SHIFT, |
883 | .init = &omap2_init_clksel_parent, | 896 | .init = &omap2_init_clksel_parent, |
@@ -908,6 +921,7 @@ static struct clk sys_clkout = { | |||
908 | .parent = &sys_clkout_src, | 921 | .parent = &sys_clkout_src, |
909 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 922 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
910 | PARENT_CONTROLS_CLOCK, | 923 | PARENT_CONTROLS_CLOCK, |
924 | .clkdm_name = "wkup_clkdm", | ||
911 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 925 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
912 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, | 926 | .clksel_mask = OMAP24XX_CLKOUT_DIV_MASK, |
913 | .clksel = sys_clkout_clksel, | 927 | .clksel = sys_clkout_clksel, |
@@ -921,6 +935,7 @@ static struct clk sys_clkout2_src = { | |||
921 | .name = "sys_clkout2_src", | 935 | .name = "sys_clkout2_src", |
922 | .parent = &func_54m_ck, | 936 | .parent = &func_54m_ck, |
923 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, | 937 | .flags = CLOCK_IN_OMAP242X | RATE_PROPAGATES, |
938 | .clkdm_name = "wkup_clkdm", | ||
924 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 939 | .enable_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
925 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, | 940 | .enable_bit = OMAP2420_CLKOUT2_EN_SHIFT, |
926 | .init = &omap2_init_clksel_parent, | 941 | .init = &omap2_init_clksel_parent, |
@@ -942,6 +957,7 @@ static struct clk sys_clkout2 = { | |||
942 | .name = "sys_clkout2", | 957 | .name = "sys_clkout2", |
943 | .parent = &sys_clkout2_src, | 958 | .parent = &sys_clkout2_src, |
944 | .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, | 959 | .flags = CLOCK_IN_OMAP242X | PARENT_CONTROLS_CLOCK, |
960 | .clkdm_name = "wkup_clkdm", | ||
945 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, | 961 | .clksel_reg = OMAP24XX_PRCM_CLKOUT_CTRL, |
946 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, | 962 | .clksel_mask = OMAP2420_CLKOUT2_DIV_MASK, |
947 | .clksel = sys_clkout2_clksel, | 963 | .clksel = sys_clkout2_clksel, |
@@ -954,6 +970,7 @@ static struct clk emul_ck = { | |||
954 | .name = "emul_ck", | 970 | .name = "emul_ck", |
955 | .parent = &func_54m_ck, | 971 | .parent = &func_54m_ck, |
956 | .flags = CLOCK_IN_OMAP242X, | 972 | .flags = CLOCK_IN_OMAP242X, |
973 | .clkdm_name = "wkup_clkdm", | ||
957 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, | 974 | .enable_reg = OMAP24XX_PRCM_CLKEMUL_CTRL, |
958 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, | 975 | .enable_bit = OMAP24XX_EMULATION_EN_SHIFT, |
959 | .recalc = &followparent_recalc, | 976 | .recalc = &followparent_recalc, |
@@ -990,12 +1007,13 @@ static struct clk mpu_ck = { /* Control cpu */ | |||
990 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
991 | ALWAYS_ENABLED | DELAYED_APP | | 1008 | ALWAYS_ENABLED | DELAYED_APP | |
992 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 1009 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
1010 | .clkdm_name = "mpu_clkdm", | ||
993 | .init = &omap2_init_clksel_parent, | 1011 | .init = &omap2_init_clksel_parent, |
994 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), | 1012 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL), |
995 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, | 1013 | .clksel_mask = OMAP24XX_CLKSEL_MPU_MASK, |
996 | .clksel = mpu_clksel, | 1014 | .clksel = mpu_clksel, |
997 | .recalc = &omap2_clksel_recalc, | 1015 | .recalc = &omap2_clksel_recalc, |
998 | .round_rate = &omap2_clksel_round_rate, | 1016 | .round_rate = &omap2_clksel_round_rate, |
999 | .set_rate = &omap2_clksel_set_rate | 1017 | .set_rate = &omap2_clksel_set_rate |
1000 | }; | 1018 | }; |
1001 | 1019 | ||
@@ -1031,6 +1049,7 @@ static struct clk dsp_fck = { | |||
1031 | .parent = &core_ck, | 1049 | .parent = &core_ck, |
1032 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | | 1050 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | DELAYED_APP | |
1033 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 1051 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
1052 | .clkdm_name = "dsp_clkdm", | ||
1034 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1053 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
1035 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1054 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
1036 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 1055 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
@@ -1054,10 +1073,7 @@ static const struct clksel dsp_irate_ick_clksel[] = { | |||
1054 | { .parent = NULL } | 1073 | { .parent = NULL } |
1055 | }; | 1074 | }; |
1056 | 1075 | ||
1057 | /* | 1076 | /* This clock does not exist as such in the TRM. */ |
1058 | * This clock does not exist as such in the TRM, but is added to | ||
1059 | * separate source selection from XXX | ||
1060 | */ | ||
1061 | static struct clk dsp_irate_ick = { | 1077 | static struct clk dsp_irate_ick = { |
1062 | .name = "dsp_irate_ick", | 1078 | .name = "dsp_irate_ick", |
1063 | .parent = &dsp_fck, | 1079 | .parent = &dsp_fck, |
@@ -1089,11 +1105,17 @@ static struct clk iva2_1_ick = { | |||
1089 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, | 1105 | .enable_bit = OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT, |
1090 | }; | 1106 | }; |
1091 | 1107 | ||
1108 | /* | ||
1109 | * The IVA1 is an ARM7 core on the 2420 that has nothing to do with | ||
1110 | * the C54x, but which is contained in the DSP powerdomain. Does not | ||
1111 | * exist on later OMAPs. | ||
1112 | */ | ||
1092 | static struct clk iva1_ifck = { | 1113 | static struct clk iva1_ifck = { |
1093 | .name = "iva1_ifck", | 1114 | .name = "iva1_ifck", |
1094 | .parent = &core_ck, | 1115 | .parent = &core_ck, |
1095 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | | 1116 | .flags = CLOCK_IN_OMAP242X | CONFIG_PARTICIPANT | |
1096 | RATE_PROPAGATES | DELAYED_APP, | 1117 | RATE_PROPAGATES | DELAYED_APP, |
1118 | .clkdm_name = "iva1_clkdm", | ||
1097 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1119 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
1098 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, | 1120 | .enable_bit = OMAP2420_EN_IVA_COP_SHIFT, |
1099 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), | 1121 | .clksel_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL), |
@@ -1109,6 +1131,7 @@ static struct clk iva1_mpu_int_ifck = { | |||
1109 | .name = "iva1_mpu_int_ifck", | 1131 | .name = "iva1_mpu_int_ifck", |
1110 | .parent = &iva1_ifck, | 1132 | .parent = &iva1_ifck, |
1111 | .flags = CLOCK_IN_OMAP242X, | 1133 | .flags = CLOCK_IN_OMAP242X, |
1134 | .clkdm_name = "iva1_clkdm", | ||
1112 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), | 1135 | .enable_reg = OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN), |
1113 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, | 1136 | .enable_bit = OMAP2420_EN_IVA_MPU_SHIFT, |
1114 | .fixed_div = 2, | 1137 | .fixed_div = 2, |
@@ -1156,6 +1179,7 @@ static struct clk core_l3_ck = { /* Used for ick and fck, interconnect */ | |||
1156 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1179 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1157 | ALWAYS_ENABLED | DELAYED_APP | | 1180 | ALWAYS_ENABLED | DELAYED_APP | |
1158 | CONFIG_PARTICIPANT | RATE_PROPAGATES, | 1181 | CONFIG_PARTICIPANT | RATE_PROPAGATES, |
1182 | .clkdm_name = "core_l3_clkdm", | ||
1159 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1183 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
1160 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, | 1184 | .clksel_mask = OMAP24XX_CLKSEL_L3_MASK, |
1161 | .clksel = core_l3_clksel, | 1185 | .clksel = core_l3_clksel, |
@@ -1177,11 +1201,13 @@ static const struct clksel usb_l4_ick_clksel[] = { | |||
1177 | { .parent = NULL }, | 1201 | { .parent = NULL }, |
1178 | }; | 1202 | }; |
1179 | 1203 | ||
1204 | /* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */ | ||
1180 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ | 1205 | static struct clk usb_l4_ick = { /* FS-USB interface clock */ |
1181 | .name = "usb_l4_ick", | 1206 | .name = "usb_l4_ick", |
1182 | .parent = &core_l3_ck, | 1207 | .parent = &core_l3_ck, |
1183 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1208 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1184 | DELAYED_APP | CONFIG_PARTICIPANT, | 1209 | DELAYED_APP | CONFIG_PARTICIPANT, |
1210 | .clkdm_name = "core_l4_clkdm", | ||
1185 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1211 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1186 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 1212 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
1187 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1213 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
@@ -1193,10 +1219,42 @@ static struct clk usb_l4_ick = { /* FS-USB interface clock */ | |||
1193 | }; | 1219 | }; |
1194 | 1220 | ||
1195 | /* | 1221 | /* |
1222 | * L4 clock management domain | ||
1223 | * | ||
1224 | * This domain contains lots of interface clocks from the L4 interface, some | ||
1225 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
1226 | * this domain. | ||
1227 | */ | ||
1228 | static const struct clksel_rate l4_core_l3_rates[] = { | ||
1229 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
1230 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
1231 | { .div = 0 } | ||
1232 | }; | ||
1233 | |||
1234 | static const struct clksel l4_clksel[] = { | ||
1235 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | ||
1236 | { .parent = NULL } | ||
1237 | }; | ||
1238 | |||
1239 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
1240 | .name = "l4_ck", | ||
1241 | .parent = &core_l3_ck, | ||
1242 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
1243 | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, | ||
1244 | .clkdm_name = "core_l4_clkdm", | ||
1245 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
1246 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | ||
1247 | .clksel = l4_clksel, | ||
1248 | .recalc = &omap2_clksel_recalc, | ||
1249 | .round_rate = &omap2_clksel_round_rate, | ||
1250 | .set_rate = &omap2_clksel_set_rate | ||
1251 | }; | ||
1252 | |||
1253 | /* | ||
1196 | * SSI is in L3 management domain, its direct parent is core not l3, | 1254 | * SSI is in L3 management domain, its direct parent is core not l3, |
1197 | * many core power domain entities are grouped into the L3 clock | 1255 | * many core power domain entities are grouped into the L3 clock |
1198 | * domain. | 1256 | * domain. |
1199 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_CLIK | 1257 | * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK |
1200 | * | 1258 | * |
1201 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. | 1259 | * ssr = core/1/2/3/4/5, sst = 1/2 ssr. |
1202 | */ | 1260 | */ |
@@ -1221,6 +1279,7 @@ static struct clk ssi_ssr_sst_fck = { | |||
1221 | .parent = &core_ck, | 1279 | .parent = &core_ck, |
1222 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1280 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1223 | DELAYED_APP, | 1281 | DELAYED_APP, |
1282 | .clkdm_name = "core_l3_clkdm", | ||
1224 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1283 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1225 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | 1284 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, |
1226 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | 1285 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), |
@@ -1231,6 +1290,7 @@ static struct clk ssi_ssr_sst_fck = { | |||
1231 | .set_rate = &omap2_clksel_set_rate | 1290 | .set_rate = &omap2_clksel_set_rate |
1232 | }; | 1291 | }; |
1233 | 1292 | ||
1293 | |||
1234 | /* | 1294 | /* |
1235 | * GFX clock domain | 1295 | * GFX clock domain |
1236 | * Clocks: | 1296 | * Clocks: |
@@ -1254,6 +1314,7 @@ static struct clk gfx_3d_fck = { | |||
1254 | .name = "gfx_3d_fck", | 1314 | .name = "gfx_3d_fck", |
1255 | .parent = &core_l3_ck, | 1315 | .parent = &core_l3_ck, |
1256 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1316 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1317 | .clkdm_name = "gfx_clkdm", | ||
1257 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1318 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1258 | .enable_bit = OMAP24XX_EN_3D_SHIFT, | 1319 | .enable_bit = OMAP24XX_EN_3D_SHIFT, |
1259 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | 1320 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
@@ -1268,6 +1329,7 @@ static struct clk gfx_2d_fck = { | |||
1268 | .name = "gfx_2d_fck", | 1329 | .name = "gfx_2d_fck", |
1269 | .parent = &core_l3_ck, | 1330 | .parent = &core_l3_ck, |
1270 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1331 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1332 | .clkdm_name = "gfx_clkdm", | ||
1271 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | 1333 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1272 | .enable_bit = OMAP24XX_EN_2D_SHIFT, | 1334 | .enable_bit = OMAP24XX_EN_2D_SHIFT, |
1273 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | 1335 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
@@ -1282,6 +1344,7 @@ static struct clk gfx_ick = { | |||
1282 | .name = "gfx_ick", /* From l3 */ | 1344 | .name = "gfx_ick", /* From l3 */ |
1283 | .parent = &core_l3_ck, | 1345 | .parent = &core_l3_ck, |
1284 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1346 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1347 | .clkdm_name = "gfx_clkdm", | ||
1285 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | 1348 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), |
1286 | .enable_bit = OMAP_EN_GFX_SHIFT, | 1349 | .enable_bit = OMAP_EN_GFX_SHIFT, |
1287 | .recalc = &followparent_recalc, | 1350 | .recalc = &followparent_recalc, |
@@ -1311,6 +1374,7 @@ static struct clk mdm_ick = { /* used both as a ick and fck */ | |||
1311 | .name = "mdm_ick", | 1374 | .name = "mdm_ick", |
1312 | .parent = &core_ck, | 1375 | .parent = &core_ck, |
1313 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, | 1376 | .flags = CLOCK_IN_OMAP243X | DELAYED_APP | CONFIG_PARTICIPANT, |
1377 | .clkdm_name = "mdm_clkdm", | ||
1314 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), | 1378 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_ICLKEN), |
1315 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, | 1379 | .enable_bit = OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT, |
1316 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), | 1380 | .clksel_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_CLKSEL), |
@@ -1325,52 +1389,13 @@ static struct clk mdm_osc_ck = { | |||
1325 | .name = "mdm_osc_ck", | 1389 | .name = "mdm_osc_ck", |
1326 | .parent = &osc_ck, | 1390 | .parent = &osc_ck, |
1327 | .flags = CLOCK_IN_OMAP243X, | 1391 | .flags = CLOCK_IN_OMAP243X, |
1392 | .clkdm_name = "mdm_clkdm", | ||
1328 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), | 1393 | .enable_reg = OMAP_CM_REGADDR(OMAP2430_MDM_MOD, CM_FCLKEN), |
1329 | .enable_bit = OMAP2430_EN_OSC_SHIFT, | 1394 | .enable_bit = OMAP2430_EN_OSC_SHIFT, |
1330 | .recalc = &followparent_recalc, | 1395 | .recalc = &followparent_recalc, |
1331 | }; | 1396 | }; |
1332 | 1397 | ||
1333 | /* | 1398 | /* |
1334 | * L4 clock management domain | ||
1335 | * | ||
1336 | * This domain contains lots of interface clocks from the L4 interface, some | ||
1337 | * functional clocks. Fixed APLL functional source clocks are managed in | ||
1338 | * this domain. | ||
1339 | */ | ||
1340 | static const struct clksel_rate l4_core_l3_rates[] = { | ||
1341 | { .div = 1, .val = 1, .flags = RATE_IN_24XX | DEFAULT_RATE }, | ||
1342 | { .div = 2, .val = 2, .flags = RATE_IN_24XX }, | ||
1343 | { .div = 0 } | ||
1344 | }; | ||
1345 | |||
1346 | static const struct clksel l4_clksel[] = { | ||
1347 | { .parent = &core_l3_ck, .rates = l4_core_l3_rates }, | ||
1348 | { .parent = NULL } | ||
1349 | }; | ||
1350 | |||
1351 | static struct clk l4_ck = { /* used both as an ick and fck */ | ||
1352 | .name = "l4_ck", | ||
1353 | .parent = &core_l3_ck, | ||
1354 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | ||
1355 | ALWAYS_ENABLED | DELAYED_APP | RATE_PROPAGATES, | ||
1356 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1), | ||
1357 | .clksel_mask = OMAP24XX_CLKSEL_L4_MASK, | ||
1358 | .clksel = l4_clksel, | ||
1359 | .recalc = &omap2_clksel_recalc, | ||
1360 | .round_rate = &omap2_clksel_round_rate, | ||
1361 | .set_rate = &omap2_clksel_set_rate | ||
1362 | }; | ||
1363 | |||
1364 | static struct clk ssi_l4_ick = { | ||
1365 | .name = "ssi_l4_ick", | ||
1366 | .parent = &l4_ck, | ||
1367 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | ||
1368 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | ||
1369 | .enable_bit = OMAP24XX_EN_SSI_SHIFT, | ||
1370 | .recalc = &followparent_recalc, | ||
1371 | }; | ||
1372 | |||
1373 | /* | ||
1374 | * DSS clock domain | 1399 | * DSS clock domain |
1375 | * CLOCKs: | 1400 | * CLOCKs: |
1376 | * DSS_L4_ICLK, DSS_L3_ICLK, | 1401 | * DSS_L4_ICLK, DSS_L3_ICLK, |
@@ -1409,6 +1434,7 @@ static struct clk dss_ick = { /* Enables both L3,L4 ICLK's */ | |||
1409 | .name = "dss_ick", | 1434 | .name = "dss_ick", |
1410 | .parent = &l4_ck, /* really both l3 and l4 */ | 1435 | .parent = &l4_ck, /* really both l3 and l4 */ |
1411 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1436 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1437 | .clkdm_name = "dss_clkdm", | ||
1412 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1413 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1439 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
1414 | .recalc = &followparent_recalc, | 1440 | .recalc = &followparent_recalc, |
@@ -1419,6 +1445,7 @@ static struct clk dss1_fck = { | |||
1419 | .parent = &core_ck, /* Core or sys */ | 1445 | .parent = &core_ck, /* Core or sys */ |
1420 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1446 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1421 | DELAYED_APP, | 1447 | DELAYED_APP, |
1448 | .clkdm_name = "dss_clkdm", | ||
1422 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1423 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, | 1450 | .enable_bit = OMAP24XX_EN_DSS1_SHIFT, |
1424 | .init = &omap2_init_clksel_parent, | 1451 | .init = &omap2_init_clksel_parent, |
@@ -1451,6 +1478,7 @@ static struct clk dss2_fck = { /* Alt clk used in power management */ | |||
1451 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ | 1478 | .parent = &sys_ck, /* fixed at sys_ck or 48MHz */ |
1452 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | | 1479 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
1453 | DELAYED_APP, | 1480 | DELAYED_APP, |
1481 | .clkdm_name = "dss_clkdm", | ||
1454 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1455 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, | 1483 | .enable_bit = OMAP24XX_EN_DSS2_SHIFT, |
1456 | .init = &omap2_init_clksel_parent, | 1484 | .init = &omap2_init_clksel_parent, |
@@ -1464,6 +1492,7 @@ static struct clk dss_54m_fck = { /* Alt clk used in power management */ | |||
1464 | .name = "dss_54m_fck", /* 54m tv clk */ | 1492 | .name = "dss_54m_fck", /* 54m tv clk */ |
1465 | .parent = &func_54m_ck, | 1493 | .parent = &func_54m_ck, |
1466 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1494 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1495 | .clkdm_name = "dss_clkdm", | ||
1467 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1496 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1468 | .enable_bit = OMAP24XX_EN_TV_SHIFT, | 1497 | .enable_bit = OMAP24XX_EN_TV_SHIFT, |
1469 | .recalc = &followparent_recalc, | 1498 | .recalc = &followparent_recalc, |
@@ -1491,6 +1520,7 @@ static struct clk gpt1_ick = { | |||
1491 | .name = "gpt1_ick", | 1520 | .name = "gpt1_ick", |
1492 | .parent = &l4_ck, | 1521 | .parent = &l4_ck, |
1493 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1522 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1523 | .clkdm_name = "core_l4_clkdm", | ||
1494 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 1524 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1495 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1525 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
1496 | .recalc = &followparent_recalc, | 1526 | .recalc = &followparent_recalc, |
@@ -1500,6 +1530,7 @@ static struct clk gpt1_fck = { | |||
1500 | .name = "gpt1_fck", | 1530 | .name = "gpt1_fck", |
1501 | .parent = &func_32k_ck, | 1531 | .parent = &func_32k_ck, |
1502 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1532 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1533 | .clkdm_name = "core_l4_clkdm", | ||
1503 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 1534 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1504 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, | 1535 | .enable_bit = OMAP24XX_EN_GPT1_SHIFT, |
1505 | .init = &omap2_init_clksel_parent, | 1536 | .init = &omap2_init_clksel_parent, |
@@ -1515,6 +1546,7 @@ static struct clk gpt2_ick = { | |||
1515 | .name = "gpt2_ick", | 1546 | .name = "gpt2_ick", |
1516 | .parent = &l4_ck, | 1547 | .parent = &l4_ck, |
1517 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1548 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1549 | .clkdm_name = "core_l4_clkdm", | ||
1518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1550 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1519 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1551 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
1520 | .recalc = &followparent_recalc, | 1552 | .recalc = &followparent_recalc, |
@@ -1524,6 +1556,7 @@ static struct clk gpt2_fck = { | |||
1524 | .name = "gpt2_fck", | 1556 | .name = "gpt2_fck", |
1525 | .parent = &func_32k_ck, | 1557 | .parent = &func_32k_ck, |
1526 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1558 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1559 | .clkdm_name = "core_l4_clkdm", | ||
1527 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1560 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1528 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, | 1561 | .enable_bit = OMAP24XX_EN_GPT2_SHIFT, |
1529 | .init = &omap2_init_clksel_parent, | 1562 | .init = &omap2_init_clksel_parent, |
@@ -1537,6 +1570,7 @@ static struct clk gpt3_ick = { | |||
1537 | .name = "gpt3_ick", | 1570 | .name = "gpt3_ick", |
1538 | .parent = &l4_ck, | 1571 | .parent = &l4_ck, |
1539 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1572 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1573 | .clkdm_name = "core_l4_clkdm", | ||
1540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1574 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1541 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1575 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
1542 | .recalc = &followparent_recalc, | 1576 | .recalc = &followparent_recalc, |
@@ -1546,6 +1580,7 @@ static struct clk gpt3_fck = { | |||
1546 | .name = "gpt3_fck", | 1580 | .name = "gpt3_fck", |
1547 | .parent = &func_32k_ck, | 1581 | .parent = &func_32k_ck, |
1548 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1582 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1583 | .clkdm_name = "core_l4_clkdm", | ||
1549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1550 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, | 1585 | .enable_bit = OMAP24XX_EN_GPT3_SHIFT, |
1551 | .init = &omap2_init_clksel_parent, | 1586 | .init = &omap2_init_clksel_parent, |
@@ -1559,6 +1594,7 @@ static struct clk gpt4_ick = { | |||
1559 | .name = "gpt4_ick", | 1594 | .name = "gpt4_ick", |
1560 | .parent = &l4_ck, | 1595 | .parent = &l4_ck, |
1561 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1596 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1597 | .clkdm_name = "core_l4_clkdm", | ||
1562 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1598 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1563 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1599 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
1564 | .recalc = &followparent_recalc, | 1600 | .recalc = &followparent_recalc, |
@@ -1568,6 +1604,7 @@ static struct clk gpt4_fck = { | |||
1568 | .name = "gpt4_fck", | 1604 | .name = "gpt4_fck", |
1569 | .parent = &func_32k_ck, | 1605 | .parent = &func_32k_ck, |
1570 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1606 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1607 | .clkdm_name = "core_l4_clkdm", | ||
1571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1608 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1572 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, | 1609 | .enable_bit = OMAP24XX_EN_GPT4_SHIFT, |
1573 | .init = &omap2_init_clksel_parent, | 1610 | .init = &omap2_init_clksel_parent, |
@@ -1581,6 +1618,7 @@ static struct clk gpt5_ick = { | |||
1581 | .name = "gpt5_ick", | 1618 | .name = "gpt5_ick", |
1582 | .parent = &l4_ck, | 1619 | .parent = &l4_ck, |
1583 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1620 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1621 | .clkdm_name = "core_l4_clkdm", | ||
1584 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1585 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1623 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
1586 | .recalc = &followparent_recalc, | 1624 | .recalc = &followparent_recalc, |
@@ -1590,6 +1628,7 @@ static struct clk gpt5_fck = { | |||
1590 | .name = "gpt5_fck", | 1628 | .name = "gpt5_fck", |
1591 | .parent = &func_32k_ck, | 1629 | .parent = &func_32k_ck, |
1592 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1630 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1631 | .clkdm_name = "core_l4_clkdm", | ||
1593 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1632 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1594 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, | 1633 | .enable_bit = OMAP24XX_EN_GPT5_SHIFT, |
1595 | .init = &omap2_init_clksel_parent, | 1634 | .init = &omap2_init_clksel_parent, |
@@ -1603,6 +1642,7 @@ static struct clk gpt6_ick = { | |||
1603 | .name = "gpt6_ick", | 1642 | .name = "gpt6_ick", |
1604 | .parent = &l4_ck, | 1643 | .parent = &l4_ck, |
1605 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1644 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1645 | .clkdm_name = "core_l4_clkdm", | ||
1606 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1646 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1607 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1647 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
1608 | .recalc = &followparent_recalc, | 1648 | .recalc = &followparent_recalc, |
@@ -1612,6 +1652,7 @@ static struct clk gpt6_fck = { | |||
1612 | .name = "gpt6_fck", | 1652 | .name = "gpt6_fck", |
1613 | .parent = &func_32k_ck, | 1653 | .parent = &func_32k_ck, |
1614 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1654 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1655 | .clkdm_name = "core_l4_clkdm", | ||
1615 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1656 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1616 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, | 1657 | .enable_bit = OMAP24XX_EN_GPT6_SHIFT, |
1617 | .init = &omap2_init_clksel_parent, | 1658 | .init = &omap2_init_clksel_parent, |
@@ -1634,6 +1675,7 @@ static struct clk gpt7_fck = { | |||
1634 | .name = "gpt7_fck", | 1675 | .name = "gpt7_fck", |
1635 | .parent = &func_32k_ck, | 1676 | .parent = &func_32k_ck, |
1636 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1677 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1678 | .clkdm_name = "core_l4_clkdm", | ||
1637 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1679 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1638 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, | 1680 | .enable_bit = OMAP24XX_EN_GPT7_SHIFT, |
1639 | .init = &omap2_init_clksel_parent, | 1681 | .init = &omap2_init_clksel_parent, |
@@ -1647,6 +1689,7 @@ static struct clk gpt8_ick = { | |||
1647 | .name = "gpt8_ick", | 1689 | .name = "gpt8_ick", |
1648 | .parent = &l4_ck, | 1690 | .parent = &l4_ck, |
1649 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1691 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1692 | .clkdm_name = "core_l4_clkdm", | ||
1650 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1693 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1651 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1694 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
1652 | .recalc = &followparent_recalc, | 1695 | .recalc = &followparent_recalc, |
@@ -1656,6 +1699,7 @@ static struct clk gpt8_fck = { | |||
1656 | .name = "gpt8_fck", | 1699 | .name = "gpt8_fck", |
1657 | .parent = &func_32k_ck, | 1700 | .parent = &func_32k_ck, |
1658 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1701 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1702 | .clkdm_name = "core_l4_clkdm", | ||
1659 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1660 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, | 1704 | .enable_bit = OMAP24XX_EN_GPT8_SHIFT, |
1661 | .init = &omap2_init_clksel_parent, | 1705 | .init = &omap2_init_clksel_parent, |
@@ -1669,6 +1713,7 @@ static struct clk gpt9_ick = { | |||
1669 | .name = "gpt9_ick", | 1713 | .name = "gpt9_ick", |
1670 | .parent = &l4_ck, | 1714 | .parent = &l4_ck, |
1671 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1715 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1716 | .clkdm_name = "core_l4_clkdm", | ||
1672 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1673 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1718 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
1674 | .recalc = &followparent_recalc, | 1719 | .recalc = &followparent_recalc, |
@@ -1678,6 +1723,7 @@ static struct clk gpt9_fck = { | |||
1678 | .name = "gpt9_fck", | 1723 | .name = "gpt9_fck", |
1679 | .parent = &func_32k_ck, | 1724 | .parent = &func_32k_ck, |
1680 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1725 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1726 | .clkdm_name = "core_l4_clkdm", | ||
1681 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1727 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1682 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, | 1728 | .enable_bit = OMAP24XX_EN_GPT9_SHIFT, |
1683 | .init = &omap2_init_clksel_parent, | 1729 | .init = &omap2_init_clksel_parent, |
@@ -1691,6 +1737,7 @@ static struct clk gpt10_ick = { | |||
1691 | .name = "gpt10_ick", | 1737 | .name = "gpt10_ick", |
1692 | .parent = &l4_ck, | 1738 | .parent = &l4_ck, |
1693 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1739 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1740 | .clkdm_name = "core_l4_clkdm", | ||
1694 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1741 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1695 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1742 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
1696 | .recalc = &followparent_recalc, | 1743 | .recalc = &followparent_recalc, |
@@ -1700,6 +1747,7 @@ static struct clk gpt10_fck = { | |||
1700 | .name = "gpt10_fck", | 1747 | .name = "gpt10_fck", |
1701 | .parent = &func_32k_ck, | 1748 | .parent = &func_32k_ck, |
1702 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1749 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1750 | .clkdm_name = "core_l4_clkdm", | ||
1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1751 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1704 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, | 1752 | .enable_bit = OMAP24XX_EN_GPT10_SHIFT, |
1705 | .init = &omap2_init_clksel_parent, | 1753 | .init = &omap2_init_clksel_parent, |
@@ -1713,6 +1761,7 @@ static struct clk gpt11_ick = { | |||
1713 | .name = "gpt11_ick", | 1761 | .name = "gpt11_ick", |
1714 | .parent = &l4_ck, | 1762 | .parent = &l4_ck, |
1715 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1763 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1764 | .clkdm_name = "core_l4_clkdm", | ||
1716 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1765 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1717 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1766 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
1718 | .recalc = &followparent_recalc, | 1767 | .recalc = &followparent_recalc, |
@@ -1722,6 +1771,7 @@ static struct clk gpt11_fck = { | |||
1722 | .name = "gpt11_fck", | 1771 | .name = "gpt11_fck", |
1723 | .parent = &func_32k_ck, | 1772 | .parent = &func_32k_ck, |
1724 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1773 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1774 | .clkdm_name = "core_l4_clkdm", | ||
1725 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1775 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1726 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, | 1776 | .enable_bit = OMAP24XX_EN_GPT11_SHIFT, |
1727 | .init = &omap2_init_clksel_parent, | 1777 | .init = &omap2_init_clksel_parent, |
@@ -1735,6 +1785,7 @@ static struct clk gpt12_ick = { | |||
1735 | .name = "gpt12_ick", | 1785 | .name = "gpt12_ick", |
1736 | .parent = &l4_ck, | 1786 | .parent = &l4_ck, |
1737 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1787 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1788 | .clkdm_name = "core_l4_clkdm", | ||
1738 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1789 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1739 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1790 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
1740 | .recalc = &followparent_recalc, | 1791 | .recalc = &followparent_recalc, |
@@ -1744,6 +1795,7 @@ static struct clk gpt12_fck = { | |||
1744 | .name = "gpt12_fck", | 1795 | .name = "gpt12_fck", |
1745 | .parent = &func_32k_ck, | 1796 | .parent = &func_32k_ck, |
1746 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1797 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1798 | .clkdm_name = "core_l4_clkdm", | ||
1747 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1799 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1748 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, | 1800 | .enable_bit = OMAP24XX_EN_GPT12_SHIFT, |
1749 | .init = &omap2_init_clksel_parent, | 1801 | .init = &omap2_init_clksel_parent, |
@@ -1758,6 +1810,7 @@ static struct clk mcbsp1_ick = { | |||
1758 | .id = 1, | 1810 | .id = 1, |
1759 | .parent = &l4_ck, | 1811 | .parent = &l4_ck, |
1760 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1812 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1813 | .clkdm_name = "core_l4_clkdm", | ||
1761 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1762 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1815 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
1763 | .recalc = &followparent_recalc, | 1816 | .recalc = &followparent_recalc, |
@@ -1768,6 +1821,7 @@ static struct clk mcbsp1_fck = { | |||
1768 | .id = 1, | 1821 | .id = 1, |
1769 | .parent = &func_96m_ck, | 1822 | .parent = &func_96m_ck, |
1770 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1823 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1824 | .clkdm_name = "core_l4_clkdm", | ||
1771 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1825 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1772 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, | 1826 | .enable_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
1773 | .recalc = &followparent_recalc, | 1827 | .recalc = &followparent_recalc, |
@@ -1778,6 +1832,7 @@ static struct clk mcbsp2_ick = { | |||
1778 | .id = 2, | 1832 | .id = 2, |
1779 | .parent = &l4_ck, | 1833 | .parent = &l4_ck, |
1780 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1834 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1835 | .clkdm_name = "core_l4_clkdm", | ||
1781 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1836 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1782 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1837 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
1783 | .recalc = &followparent_recalc, | 1838 | .recalc = &followparent_recalc, |
@@ -1788,6 +1843,7 @@ static struct clk mcbsp2_fck = { | |||
1788 | .id = 2, | 1843 | .id = 2, |
1789 | .parent = &func_96m_ck, | 1844 | .parent = &func_96m_ck, |
1790 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1845 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1846 | .clkdm_name = "core_l4_clkdm", | ||
1791 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1847 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1792 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, | 1848 | .enable_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
1793 | .recalc = &followparent_recalc, | 1849 | .recalc = &followparent_recalc, |
@@ -1798,6 +1854,7 @@ static struct clk mcbsp3_ick = { | |||
1798 | .id = 3, | 1854 | .id = 3, |
1799 | .parent = &l4_ck, | 1855 | .parent = &l4_ck, |
1800 | .flags = CLOCK_IN_OMAP243X, | 1856 | .flags = CLOCK_IN_OMAP243X, |
1857 | .clkdm_name = "core_l4_clkdm", | ||
1801 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1858 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1802 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1859 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
1803 | .recalc = &followparent_recalc, | 1860 | .recalc = &followparent_recalc, |
@@ -1808,6 +1865,7 @@ static struct clk mcbsp3_fck = { | |||
1808 | .id = 3, | 1865 | .id = 3, |
1809 | .parent = &func_96m_ck, | 1866 | .parent = &func_96m_ck, |
1810 | .flags = CLOCK_IN_OMAP243X, | 1867 | .flags = CLOCK_IN_OMAP243X, |
1868 | .clkdm_name = "core_l4_clkdm", | ||
1811 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1869 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1812 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, | 1870 | .enable_bit = OMAP2430_EN_MCBSP3_SHIFT, |
1813 | .recalc = &followparent_recalc, | 1871 | .recalc = &followparent_recalc, |
@@ -1818,6 +1876,7 @@ static struct clk mcbsp4_ick = { | |||
1818 | .id = 4, | 1876 | .id = 4, |
1819 | .parent = &l4_ck, | 1877 | .parent = &l4_ck, |
1820 | .flags = CLOCK_IN_OMAP243X, | 1878 | .flags = CLOCK_IN_OMAP243X, |
1879 | .clkdm_name = "core_l4_clkdm", | ||
1821 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1880 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1822 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1881 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
1823 | .recalc = &followparent_recalc, | 1882 | .recalc = &followparent_recalc, |
@@ -1828,6 +1887,7 @@ static struct clk mcbsp4_fck = { | |||
1828 | .id = 4, | 1887 | .id = 4, |
1829 | .parent = &func_96m_ck, | 1888 | .parent = &func_96m_ck, |
1830 | .flags = CLOCK_IN_OMAP243X, | 1889 | .flags = CLOCK_IN_OMAP243X, |
1890 | .clkdm_name = "core_l4_clkdm", | ||
1831 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1832 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, | 1892 | .enable_bit = OMAP2430_EN_MCBSP4_SHIFT, |
1833 | .recalc = &followparent_recalc, | 1893 | .recalc = &followparent_recalc, |
@@ -1838,6 +1898,7 @@ static struct clk mcbsp5_ick = { | |||
1838 | .id = 5, | 1898 | .id = 5, |
1839 | .parent = &l4_ck, | 1899 | .parent = &l4_ck, |
1840 | .flags = CLOCK_IN_OMAP243X, | 1900 | .flags = CLOCK_IN_OMAP243X, |
1901 | .clkdm_name = "core_l4_clkdm", | ||
1841 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1902 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1842 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1903 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
1843 | .recalc = &followparent_recalc, | 1904 | .recalc = &followparent_recalc, |
@@ -1848,6 +1909,7 @@ static struct clk mcbsp5_fck = { | |||
1848 | .id = 5, | 1909 | .id = 5, |
1849 | .parent = &func_96m_ck, | 1910 | .parent = &func_96m_ck, |
1850 | .flags = CLOCK_IN_OMAP243X, | 1911 | .flags = CLOCK_IN_OMAP243X, |
1912 | .clkdm_name = "core_l4_clkdm", | ||
1851 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1852 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, | 1914 | .enable_bit = OMAP2430_EN_MCBSP5_SHIFT, |
1853 | .recalc = &followparent_recalc, | 1915 | .recalc = &followparent_recalc, |
@@ -1857,6 +1919,7 @@ static struct clk mcspi1_ick = { | |||
1857 | .name = "mcspi_ick", | 1919 | .name = "mcspi_ick", |
1858 | .id = 1, | 1920 | .id = 1, |
1859 | .parent = &l4_ck, | 1921 | .parent = &l4_ck, |
1922 | .clkdm_name = "core_l4_clkdm", | ||
1860 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1923 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1861 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1862 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1925 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
@@ -1868,6 +1931,7 @@ static struct clk mcspi1_fck = { | |||
1868 | .id = 1, | 1931 | .id = 1, |
1869 | .parent = &func_48m_ck, | 1932 | .parent = &func_48m_ck, |
1870 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1933 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1934 | .clkdm_name = "core_l4_clkdm", | ||
1871 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1935 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1872 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, | 1936 | .enable_bit = OMAP24XX_EN_MCSPI1_SHIFT, |
1873 | .recalc = &followparent_recalc, | 1937 | .recalc = &followparent_recalc, |
@@ -1878,6 +1942,7 @@ static struct clk mcspi2_ick = { | |||
1878 | .id = 2, | 1942 | .id = 2, |
1879 | .parent = &l4_ck, | 1943 | .parent = &l4_ck, |
1880 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1944 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1945 | .clkdm_name = "core_l4_clkdm", | ||
1881 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1946 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1882 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1947 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
1883 | .recalc = &followparent_recalc, | 1948 | .recalc = &followparent_recalc, |
@@ -1888,6 +1953,7 @@ static struct clk mcspi2_fck = { | |||
1888 | .id = 2, | 1953 | .id = 2, |
1889 | .parent = &func_48m_ck, | 1954 | .parent = &func_48m_ck, |
1890 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1955 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1956 | .clkdm_name = "core_l4_clkdm", | ||
1891 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1957 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1892 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, | 1958 | .enable_bit = OMAP24XX_EN_MCSPI2_SHIFT, |
1893 | .recalc = &followparent_recalc, | 1959 | .recalc = &followparent_recalc, |
@@ -1898,6 +1964,7 @@ static struct clk mcspi3_ick = { | |||
1898 | .id = 3, | 1964 | .id = 3, |
1899 | .parent = &l4_ck, | 1965 | .parent = &l4_ck, |
1900 | .flags = CLOCK_IN_OMAP243X, | 1966 | .flags = CLOCK_IN_OMAP243X, |
1967 | .clkdm_name = "core_l4_clkdm", | ||
1901 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 1968 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1902 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1969 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
1903 | .recalc = &followparent_recalc, | 1970 | .recalc = &followparent_recalc, |
@@ -1908,6 +1975,7 @@ static struct clk mcspi3_fck = { | |||
1908 | .id = 3, | 1975 | .id = 3, |
1909 | .parent = &func_48m_ck, | 1976 | .parent = &func_48m_ck, |
1910 | .flags = CLOCK_IN_OMAP243X, | 1977 | .flags = CLOCK_IN_OMAP243X, |
1978 | .clkdm_name = "core_l4_clkdm", | ||
1911 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 1979 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1912 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, | 1980 | .enable_bit = OMAP2430_EN_MCSPI3_SHIFT, |
1913 | .recalc = &followparent_recalc, | 1981 | .recalc = &followparent_recalc, |
@@ -1917,6 +1985,7 @@ static struct clk uart1_ick = { | |||
1917 | .name = "uart1_ick", | 1985 | .name = "uart1_ick", |
1918 | .parent = &l4_ck, | 1986 | .parent = &l4_ck, |
1919 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1987 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1988 | .clkdm_name = "core_l4_clkdm", | ||
1920 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 1989 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1921 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 1990 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
1922 | .recalc = &followparent_recalc, | 1991 | .recalc = &followparent_recalc, |
@@ -1926,6 +1995,7 @@ static struct clk uart1_fck = { | |||
1926 | .name = "uart1_fck", | 1995 | .name = "uart1_fck", |
1927 | .parent = &func_48m_ck, | 1996 | .parent = &func_48m_ck, |
1928 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 1997 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
1998 | .clkdm_name = "core_l4_clkdm", | ||
1929 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 1999 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1930 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, | 2000 | .enable_bit = OMAP24XX_EN_UART1_SHIFT, |
1931 | .recalc = &followparent_recalc, | 2001 | .recalc = &followparent_recalc, |
@@ -1935,6 +2005,7 @@ static struct clk uart2_ick = { | |||
1935 | .name = "uart2_ick", | 2005 | .name = "uart2_ick", |
1936 | .parent = &l4_ck, | 2006 | .parent = &l4_ck, |
1937 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2007 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2008 | .clkdm_name = "core_l4_clkdm", | ||
1938 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2009 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
1939 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2010 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
1940 | .recalc = &followparent_recalc, | 2011 | .recalc = &followparent_recalc, |
@@ -1944,6 +2015,7 @@ static struct clk uart2_fck = { | |||
1944 | .name = "uart2_fck", | 2015 | .name = "uart2_fck", |
1945 | .parent = &func_48m_ck, | 2016 | .parent = &func_48m_ck, |
1946 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2017 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2018 | .clkdm_name = "core_l4_clkdm", | ||
1947 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2019 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1948 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, | 2020 | .enable_bit = OMAP24XX_EN_UART2_SHIFT, |
1949 | .recalc = &followparent_recalc, | 2021 | .recalc = &followparent_recalc, |
@@ -1953,6 +2025,7 @@ static struct clk uart3_ick = { | |||
1953 | .name = "uart3_ick", | 2025 | .name = "uart3_ick", |
1954 | .parent = &l4_ck, | 2026 | .parent = &l4_ck, |
1955 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2027 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2028 | .clkdm_name = "core_l4_clkdm", | ||
1956 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2029 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
1957 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2030 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
1958 | .recalc = &followparent_recalc, | 2031 | .recalc = &followparent_recalc, |
@@ -1962,6 +2035,7 @@ static struct clk uart3_fck = { | |||
1962 | .name = "uart3_fck", | 2035 | .name = "uart3_fck", |
1963 | .parent = &func_48m_ck, | 2036 | .parent = &func_48m_ck, |
1964 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2037 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2038 | .clkdm_name = "core_l4_clkdm", | ||
1965 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2039 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
1966 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, | 2040 | .enable_bit = OMAP24XX_EN_UART3_SHIFT, |
1967 | .recalc = &followparent_recalc, | 2041 | .recalc = &followparent_recalc, |
@@ -1971,6 +2045,7 @@ static struct clk gpios_ick = { | |||
1971 | .name = "gpios_ick", | 2045 | .name = "gpios_ick", |
1972 | .parent = &l4_ck, | 2046 | .parent = &l4_ck, |
1973 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2047 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2048 | .clkdm_name = "core_l4_clkdm", | ||
1974 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2049 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1975 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2050 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
1976 | .recalc = &followparent_recalc, | 2051 | .recalc = &followparent_recalc, |
@@ -1980,6 +2055,7 @@ static struct clk gpios_fck = { | |||
1980 | .name = "gpios_fck", | 2055 | .name = "gpios_fck", |
1981 | .parent = &func_32k_ck, | 2056 | .parent = &func_32k_ck, |
1982 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2057 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2058 | .clkdm_name = "wkup_clkdm", | ||
1983 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2059 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
1984 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, | 2060 | .enable_bit = OMAP24XX_EN_GPIOS_SHIFT, |
1985 | .recalc = &followparent_recalc, | 2061 | .recalc = &followparent_recalc, |
@@ -1989,6 +2065,7 @@ static struct clk mpu_wdt_ick = { | |||
1989 | .name = "mpu_wdt_ick", | 2065 | .name = "mpu_wdt_ick", |
1990 | .parent = &l4_ck, | 2066 | .parent = &l4_ck, |
1991 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2067 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2068 | .clkdm_name = "core_l4_clkdm", | ||
1992 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2069 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
1993 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2070 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
1994 | .recalc = &followparent_recalc, | 2071 | .recalc = &followparent_recalc, |
@@ -1998,6 +2075,7 @@ static struct clk mpu_wdt_fck = { | |||
1998 | .name = "mpu_wdt_fck", | 2075 | .name = "mpu_wdt_fck", |
1999 | .parent = &func_32k_ck, | 2076 | .parent = &func_32k_ck, |
2000 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2077 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2078 | .clkdm_name = "wkup_clkdm", | ||
2001 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | 2079 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), |
2002 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, | 2080 | .enable_bit = OMAP24XX_EN_MPU_WDT_SHIFT, |
2003 | .recalc = &followparent_recalc, | 2081 | .recalc = &followparent_recalc, |
@@ -2006,31 +2084,40 @@ static struct clk mpu_wdt_fck = { | |||
2006 | static struct clk sync_32k_ick = { | 2084 | static struct clk sync_32k_ick = { |
2007 | .name = "sync_32k_ick", | 2085 | .name = "sync_32k_ick", |
2008 | .parent = &l4_ck, | 2086 | .parent = &l4_ck, |
2009 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2087 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
2088 | ENABLE_ON_INIT, | ||
2089 | .clkdm_name = "core_l4_clkdm", | ||
2010 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2090 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2011 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, | 2091 | .enable_bit = OMAP24XX_EN_32KSYNC_SHIFT, |
2012 | .recalc = &followparent_recalc, | 2092 | .recalc = &followparent_recalc, |
2013 | }; | 2093 | }; |
2094 | |||
2014 | static struct clk wdt1_ick = { | 2095 | static struct clk wdt1_ick = { |
2015 | .name = "wdt1_ick", | 2096 | .name = "wdt1_ick", |
2016 | .parent = &l4_ck, | 2097 | .parent = &l4_ck, |
2017 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2098 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2099 | .clkdm_name = "core_l4_clkdm", | ||
2018 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2100 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2019 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, | 2101 | .enable_bit = OMAP24XX_EN_WDT1_SHIFT, |
2020 | .recalc = &followparent_recalc, | 2102 | .recalc = &followparent_recalc, |
2021 | }; | 2103 | }; |
2104 | |||
2022 | static struct clk omapctrl_ick = { | 2105 | static struct clk omapctrl_ick = { |
2023 | .name = "omapctrl_ick", | 2106 | .name = "omapctrl_ick", |
2024 | .parent = &l4_ck, | 2107 | .parent = &l4_ck, |
2025 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2108 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
2109 | ENABLE_ON_INIT, | ||
2110 | .clkdm_name = "core_l4_clkdm", | ||
2026 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2111 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2027 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, | 2112 | .enable_bit = OMAP24XX_EN_OMAPCTRL_SHIFT, |
2028 | .recalc = &followparent_recalc, | 2113 | .recalc = &followparent_recalc, |
2029 | }; | 2114 | }; |
2115 | |||
2030 | static struct clk icr_ick = { | 2116 | static struct clk icr_ick = { |
2031 | .name = "icr_ick", | 2117 | .name = "icr_ick", |
2032 | .parent = &l4_ck, | 2118 | .parent = &l4_ck, |
2033 | .flags = CLOCK_IN_OMAP243X, | 2119 | .flags = CLOCK_IN_OMAP243X, |
2120 | .clkdm_name = "core_l4_clkdm", | ||
2034 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | 2121 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), |
2035 | .enable_bit = OMAP2430_EN_ICR_SHIFT, | 2122 | .enable_bit = OMAP2430_EN_ICR_SHIFT, |
2036 | .recalc = &followparent_recalc, | 2123 | .recalc = &followparent_recalc, |
@@ -2040,15 +2127,22 @@ static struct clk cam_ick = { | |||
2040 | .name = "cam_ick", | 2127 | .name = "cam_ick", |
2041 | .parent = &l4_ck, | 2128 | .parent = &l4_ck, |
2042 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2129 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2130 | .clkdm_name = "core_l4_clkdm", | ||
2043 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2131 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2044 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2132 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
2045 | .recalc = &followparent_recalc, | 2133 | .recalc = &followparent_recalc, |
2046 | }; | 2134 | }; |
2047 | 2135 | ||
2136 | /* | ||
2137 | * cam_fck controls both CAM_MCLK and CAM_FCLK. It should probably be | ||
2138 | * split into two separate clocks, since the parent clocks are different | ||
2139 | * and the clockdomains are also different. | ||
2140 | */ | ||
2048 | static struct clk cam_fck = { | 2141 | static struct clk cam_fck = { |
2049 | .name = "cam_fck", | 2142 | .name = "cam_fck", |
2050 | .parent = &func_96m_ck, | 2143 | .parent = &func_96m_ck, |
2051 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2144 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2145 | .clkdm_name = "core_l3_clkdm", | ||
2052 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2146 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2053 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, | 2147 | .enable_bit = OMAP24XX_EN_CAM_SHIFT, |
2054 | .recalc = &followparent_recalc, | 2148 | .recalc = &followparent_recalc, |
@@ -2058,6 +2152,7 @@ static struct clk mailboxes_ick = { | |||
2058 | .name = "mailboxes_ick", | 2152 | .name = "mailboxes_ick", |
2059 | .parent = &l4_ck, | 2153 | .parent = &l4_ck, |
2060 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2154 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2155 | .clkdm_name = "core_l4_clkdm", | ||
2061 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2156 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2062 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, | 2157 | .enable_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
2063 | .recalc = &followparent_recalc, | 2158 | .recalc = &followparent_recalc, |
@@ -2067,6 +2162,7 @@ static struct clk wdt4_ick = { | |||
2067 | .name = "wdt4_ick", | 2162 | .name = "wdt4_ick", |
2068 | .parent = &l4_ck, | 2163 | .parent = &l4_ck, |
2069 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2164 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2165 | .clkdm_name = "core_l4_clkdm", | ||
2070 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2166 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2071 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2167 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
2072 | .recalc = &followparent_recalc, | 2168 | .recalc = &followparent_recalc, |
@@ -2076,6 +2172,7 @@ static struct clk wdt4_fck = { | |||
2076 | .name = "wdt4_fck", | 2172 | .name = "wdt4_fck", |
2077 | .parent = &func_32k_ck, | 2173 | .parent = &func_32k_ck, |
2078 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2174 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2175 | .clkdm_name = "core_l4_clkdm", | ||
2079 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2176 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2080 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, | 2177 | .enable_bit = OMAP24XX_EN_WDT4_SHIFT, |
2081 | .recalc = &followparent_recalc, | 2178 | .recalc = &followparent_recalc, |
@@ -2085,6 +2182,7 @@ static struct clk wdt3_ick = { | |||
2085 | .name = "wdt3_ick", | 2182 | .name = "wdt3_ick", |
2086 | .parent = &l4_ck, | 2183 | .parent = &l4_ck, |
2087 | .flags = CLOCK_IN_OMAP242X, | 2184 | .flags = CLOCK_IN_OMAP242X, |
2185 | .clkdm_name = "core_l4_clkdm", | ||
2088 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2186 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2089 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2187 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
2090 | .recalc = &followparent_recalc, | 2188 | .recalc = &followparent_recalc, |
@@ -2094,6 +2192,7 @@ static struct clk wdt3_fck = { | |||
2094 | .name = "wdt3_fck", | 2192 | .name = "wdt3_fck", |
2095 | .parent = &func_32k_ck, | 2193 | .parent = &func_32k_ck, |
2096 | .flags = CLOCK_IN_OMAP242X, | 2194 | .flags = CLOCK_IN_OMAP242X, |
2195 | .clkdm_name = "core_l4_clkdm", | ||
2097 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2196 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2098 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, | 2197 | .enable_bit = OMAP2420_EN_WDT3_SHIFT, |
2099 | .recalc = &followparent_recalc, | 2198 | .recalc = &followparent_recalc, |
@@ -2103,6 +2202,7 @@ static struct clk mspro_ick = { | |||
2103 | .name = "mspro_ick", | 2202 | .name = "mspro_ick", |
2104 | .parent = &l4_ck, | 2203 | .parent = &l4_ck, |
2105 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2204 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2205 | .clkdm_name = "core_l4_clkdm", | ||
2106 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2206 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2107 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2207 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
2108 | .recalc = &followparent_recalc, | 2208 | .recalc = &followparent_recalc, |
@@ -2112,6 +2212,7 @@ static struct clk mspro_fck = { | |||
2112 | .name = "mspro_fck", | 2212 | .name = "mspro_fck", |
2113 | .parent = &func_96m_ck, | 2213 | .parent = &func_96m_ck, |
2114 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2214 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2215 | .clkdm_name = "core_l4_clkdm", | ||
2115 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2216 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2116 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, | 2217 | .enable_bit = OMAP24XX_EN_MSPRO_SHIFT, |
2117 | .recalc = &followparent_recalc, | 2218 | .recalc = &followparent_recalc, |
@@ -2121,6 +2222,7 @@ static struct clk mmc_ick = { | |||
2121 | .name = "mmc_ick", | 2222 | .name = "mmc_ick", |
2122 | .parent = &l4_ck, | 2223 | .parent = &l4_ck, |
2123 | .flags = CLOCK_IN_OMAP242X, | 2224 | .flags = CLOCK_IN_OMAP242X, |
2225 | .clkdm_name = "core_l4_clkdm", | ||
2124 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2226 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2125 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2227 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
2126 | .recalc = &followparent_recalc, | 2228 | .recalc = &followparent_recalc, |
@@ -2130,6 +2232,7 @@ static struct clk mmc_fck = { | |||
2130 | .name = "mmc_fck", | 2232 | .name = "mmc_fck", |
2131 | .parent = &func_96m_ck, | 2233 | .parent = &func_96m_ck, |
2132 | .flags = CLOCK_IN_OMAP242X, | 2234 | .flags = CLOCK_IN_OMAP242X, |
2235 | .clkdm_name = "core_l4_clkdm", | ||
2133 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2236 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2134 | .enable_bit = OMAP2420_EN_MMC_SHIFT, | 2237 | .enable_bit = OMAP2420_EN_MMC_SHIFT, |
2135 | .recalc = &followparent_recalc, | 2238 | .recalc = &followparent_recalc, |
@@ -2139,6 +2242,7 @@ static struct clk fac_ick = { | |||
2139 | .name = "fac_ick", | 2242 | .name = "fac_ick", |
2140 | .parent = &l4_ck, | 2243 | .parent = &l4_ck, |
2141 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2244 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2245 | .clkdm_name = "core_l4_clkdm", | ||
2142 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2246 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2143 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2247 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
2144 | .recalc = &followparent_recalc, | 2248 | .recalc = &followparent_recalc, |
@@ -2148,6 +2252,7 @@ static struct clk fac_fck = { | |||
2148 | .name = "fac_fck", | 2252 | .name = "fac_fck", |
2149 | .parent = &func_12m_ck, | 2253 | .parent = &func_12m_ck, |
2150 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2254 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2255 | .clkdm_name = "core_l4_clkdm", | ||
2151 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2256 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2152 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, | 2257 | .enable_bit = OMAP24XX_EN_FAC_SHIFT, |
2153 | .recalc = &followparent_recalc, | 2258 | .recalc = &followparent_recalc, |
@@ -2157,6 +2262,7 @@ static struct clk eac_ick = { | |||
2157 | .name = "eac_ick", | 2262 | .name = "eac_ick", |
2158 | .parent = &l4_ck, | 2263 | .parent = &l4_ck, |
2159 | .flags = CLOCK_IN_OMAP242X, | 2264 | .flags = CLOCK_IN_OMAP242X, |
2265 | .clkdm_name = "core_l4_clkdm", | ||
2160 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2266 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2161 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2267 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
2162 | .recalc = &followparent_recalc, | 2268 | .recalc = &followparent_recalc, |
@@ -2166,6 +2272,7 @@ static struct clk eac_fck = { | |||
2166 | .name = "eac_fck", | 2272 | .name = "eac_fck", |
2167 | .parent = &func_96m_ck, | 2273 | .parent = &func_96m_ck, |
2168 | .flags = CLOCK_IN_OMAP242X, | 2274 | .flags = CLOCK_IN_OMAP242X, |
2275 | .clkdm_name = "core_l4_clkdm", | ||
2169 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2276 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2170 | .enable_bit = OMAP2420_EN_EAC_SHIFT, | 2277 | .enable_bit = OMAP2420_EN_EAC_SHIFT, |
2171 | .recalc = &followparent_recalc, | 2278 | .recalc = &followparent_recalc, |
@@ -2175,6 +2282,7 @@ static struct clk hdq_ick = { | |||
2175 | .name = "hdq_ick", | 2282 | .name = "hdq_ick", |
2176 | .parent = &l4_ck, | 2283 | .parent = &l4_ck, |
2177 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2284 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2285 | .clkdm_name = "core_l4_clkdm", | ||
2178 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2286 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2179 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2287 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
2180 | .recalc = &followparent_recalc, | 2288 | .recalc = &followparent_recalc, |
@@ -2184,6 +2292,7 @@ static struct clk hdq_fck = { | |||
2184 | .name = "hdq_fck", | 2292 | .name = "hdq_fck", |
2185 | .parent = &func_12m_ck, | 2293 | .parent = &func_12m_ck, |
2186 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2294 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2295 | .clkdm_name = "core_l4_clkdm", | ||
2187 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2296 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2188 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, | 2297 | .enable_bit = OMAP24XX_EN_HDQ_SHIFT, |
2189 | .recalc = &followparent_recalc, | 2298 | .recalc = &followparent_recalc, |
@@ -2194,6 +2303,7 @@ static struct clk i2c2_ick = { | |||
2194 | .id = 2, | 2303 | .id = 2, |
2195 | .parent = &l4_ck, | 2304 | .parent = &l4_ck, |
2196 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2305 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2306 | .clkdm_name = "core_l4_clkdm", | ||
2197 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2198 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2308 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
2199 | .recalc = &followparent_recalc, | 2309 | .recalc = &followparent_recalc, |
@@ -2204,6 +2314,7 @@ static struct clk i2c2_fck = { | |||
2204 | .id = 2, | 2314 | .id = 2, |
2205 | .parent = &func_12m_ck, | 2315 | .parent = &func_12m_ck, |
2206 | .flags = CLOCK_IN_OMAP242X, | 2316 | .flags = CLOCK_IN_OMAP242X, |
2317 | .clkdm_name = "core_l4_clkdm", | ||
2207 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2318 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2208 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, | 2319 | .enable_bit = OMAP2420_EN_I2C2_SHIFT, |
2209 | .recalc = &followparent_recalc, | 2320 | .recalc = &followparent_recalc, |
@@ -2214,6 +2325,7 @@ static struct clk i2chs2_fck = { | |||
2214 | .id = 2, | 2325 | .id = 2, |
2215 | .parent = &func_96m_ck, | 2326 | .parent = &func_96m_ck, |
2216 | .flags = CLOCK_IN_OMAP243X, | 2327 | .flags = CLOCK_IN_OMAP243X, |
2328 | .clkdm_name = "core_l4_clkdm", | ||
2217 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2329 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2218 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, | 2330 | .enable_bit = OMAP2430_EN_I2CHS2_SHIFT, |
2219 | .recalc = &followparent_recalc, | 2331 | .recalc = &followparent_recalc, |
@@ -2224,6 +2336,7 @@ static struct clk i2c1_ick = { | |||
2224 | .id = 1, | 2336 | .id = 1, |
2225 | .parent = &l4_ck, | 2337 | .parent = &l4_ck, |
2226 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2338 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2339 | .clkdm_name = "core_l4_clkdm", | ||
2227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2228 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2341 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
2229 | .recalc = &followparent_recalc, | 2342 | .recalc = &followparent_recalc, |
@@ -2234,6 +2347,7 @@ static struct clk i2c1_fck = { | |||
2234 | .id = 1, | 2347 | .id = 1, |
2235 | .parent = &func_12m_ck, | 2348 | .parent = &func_12m_ck, |
2236 | .flags = CLOCK_IN_OMAP242X, | 2349 | .flags = CLOCK_IN_OMAP242X, |
2350 | .clkdm_name = "core_l4_clkdm", | ||
2237 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2238 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, | 2352 | .enable_bit = OMAP2420_EN_I2C1_SHIFT, |
2239 | .recalc = &followparent_recalc, | 2353 | .recalc = &followparent_recalc, |
@@ -2244,6 +2358,7 @@ static struct clk i2chs1_fck = { | |||
2244 | .id = 1, | 2358 | .id = 1, |
2245 | .parent = &func_96m_ck, | 2359 | .parent = &func_96m_ck, |
2246 | .flags = CLOCK_IN_OMAP243X, | 2360 | .flags = CLOCK_IN_OMAP243X, |
2361 | .clkdm_name = "core_l4_clkdm", | ||
2247 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2362 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2248 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, | 2363 | .enable_bit = OMAP2430_EN_I2CHS1_SHIFT, |
2249 | .recalc = &followparent_recalc, | 2364 | .recalc = &followparent_recalc, |
@@ -2252,7 +2367,9 @@ static struct clk i2chs1_fck = { | |||
2252 | static struct clk gpmc_fck = { | 2367 | static struct clk gpmc_fck = { |
2253 | .name = "gpmc_fck", | 2368 | .name = "gpmc_fck", |
2254 | .parent = &core_l3_ck, | 2369 | .parent = &core_l3_ck, |
2255 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2370 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | |
2371 | ENABLE_ON_INIT, | ||
2372 | .clkdm_name = "core_l3_clkdm", | ||
2256 | .recalc = &followparent_recalc, | 2373 | .recalc = &followparent_recalc, |
2257 | }; | 2374 | }; |
2258 | 2375 | ||
@@ -2260,6 +2377,7 @@ static struct clk sdma_fck = { | |||
2260 | .name = "sdma_fck", | 2377 | .name = "sdma_fck", |
2261 | .parent = &core_l3_ck, | 2378 | .parent = &core_l3_ck, |
2262 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2379 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2380 | .clkdm_name = "core_l3_clkdm", | ||
2263 | .recalc = &followparent_recalc, | 2381 | .recalc = &followparent_recalc, |
2264 | }; | 2382 | }; |
2265 | 2383 | ||
@@ -2267,6 +2385,7 @@ static struct clk sdma_ick = { | |||
2267 | .name = "sdma_ick", | 2385 | .name = "sdma_ick", |
2268 | .parent = &l4_ck, | 2386 | .parent = &l4_ck, |
2269 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, | 2387 | .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X, |
2388 | .clkdm_name = "core_l3_clkdm", | ||
2270 | .recalc = &followparent_recalc, | 2389 | .recalc = &followparent_recalc, |
2271 | }; | 2390 | }; |
2272 | 2391 | ||
@@ -2274,6 +2393,7 @@ static struct clk vlynq_ick = { | |||
2274 | .name = "vlynq_ick", | 2393 | .name = "vlynq_ick", |
2275 | .parent = &core_l3_ck, | 2394 | .parent = &core_l3_ck, |
2276 | .flags = CLOCK_IN_OMAP242X, | 2395 | .flags = CLOCK_IN_OMAP242X, |
2396 | .clkdm_name = "core_l3_clkdm", | ||
2277 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | 2397 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), |
2278 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2398 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
2279 | .recalc = &followparent_recalc, | 2399 | .recalc = &followparent_recalc, |
@@ -2308,6 +2428,7 @@ static struct clk vlynq_fck = { | |||
2308 | .name = "vlynq_fck", | 2428 | .name = "vlynq_fck", |
2309 | .parent = &func_96m_ck, | 2429 | .parent = &func_96m_ck, |
2310 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, | 2430 | .flags = CLOCK_IN_OMAP242X | DELAYED_APP, |
2431 | .clkdm_name = "core_l3_clkdm", | ||
2311 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | 2432 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
2312 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, | 2433 | .enable_bit = OMAP2420_EN_VLYNQ_SHIFT, |
2313 | .init = &omap2_init_clksel_parent, | 2434 | .init = &omap2_init_clksel_parent, |
@@ -2323,6 +2444,7 @@ static struct clk sdrc_ick = { | |||
2323 | .name = "sdrc_ick", | 2444 | .name = "sdrc_ick", |
2324 | .parent = &l4_ck, | 2445 | .parent = &l4_ck, |
2325 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, | 2446 | .flags = CLOCK_IN_OMAP243X | ENABLE_ON_INIT, |
2447 | .clkdm_name = "core_l4_clkdm", | ||
2326 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | 2448 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), |
2327 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, | 2449 | .enable_bit = OMAP2430_EN_SDRC_SHIFT, |
2328 | .recalc = &followparent_recalc, | 2450 | .recalc = &followparent_recalc, |
@@ -2332,6 +2454,7 @@ static struct clk des_ick = { | |||
2332 | .name = "des_ick", | 2454 | .name = "des_ick", |
2333 | .parent = &l4_ck, | 2455 | .parent = &l4_ck, |
2334 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2456 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2457 | .clkdm_name = "core_l4_clkdm", | ||
2335 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2458 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
2336 | .enable_bit = OMAP24XX_EN_DES_SHIFT, | 2459 | .enable_bit = OMAP24XX_EN_DES_SHIFT, |
2337 | .recalc = &followparent_recalc, | 2460 | .recalc = &followparent_recalc, |
@@ -2341,6 +2464,7 @@ static struct clk sha_ick = { | |||
2341 | .name = "sha_ick", | 2464 | .name = "sha_ick", |
2342 | .parent = &l4_ck, | 2465 | .parent = &l4_ck, |
2343 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2466 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2467 | .clkdm_name = "core_l4_clkdm", | ||
2344 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2468 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
2345 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, | 2469 | .enable_bit = OMAP24XX_EN_SHA_SHIFT, |
2346 | .recalc = &followparent_recalc, | 2470 | .recalc = &followparent_recalc, |
@@ -2350,6 +2474,7 @@ static struct clk rng_ick = { | |||
2350 | .name = "rng_ick", | 2474 | .name = "rng_ick", |
2351 | .parent = &l4_ck, | 2475 | .parent = &l4_ck, |
2352 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2476 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2477 | .clkdm_name = "core_l4_clkdm", | ||
2353 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2478 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
2354 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, | 2479 | .enable_bit = OMAP24XX_EN_RNG_SHIFT, |
2355 | .recalc = &followparent_recalc, | 2480 | .recalc = &followparent_recalc, |
@@ -2359,6 +2484,7 @@ static struct clk aes_ick = { | |||
2359 | .name = "aes_ick", | 2484 | .name = "aes_ick", |
2360 | .parent = &l4_ck, | 2485 | .parent = &l4_ck, |
2361 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2486 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2487 | .clkdm_name = "core_l4_clkdm", | ||
2362 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2488 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
2363 | .enable_bit = OMAP24XX_EN_AES_SHIFT, | 2489 | .enable_bit = OMAP24XX_EN_AES_SHIFT, |
2364 | .recalc = &followparent_recalc, | 2490 | .recalc = &followparent_recalc, |
@@ -2368,6 +2494,7 @@ static struct clk pka_ick = { | |||
2368 | .name = "pka_ick", | 2494 | .name = "pka_ick", |
2369 | .parent = &l4_ck, | 2495 | .parent = &l4_ck, |
2370 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2496 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2497 | .clkdm_name = "core_l4_clkdm", | ||
2371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), | 2498 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4), |
2372 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, | 2499 | .enable_bit = OMAP24XX_EN_PKA_SHIFT, |
2373 | .recalc = &followparent_recalc, | 2500 | .recalc = &followparent_recalc, |
@@ -2377,6 +2504,7 @@ static struct clk usb_fck = { | |||
2377 | .name = "usb_fck", | 2504 | .name = "usb_fck", |
2378 | .parent = &func_48m_ck, | 2505 | .parent = &func_48m_ck, |
2379 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, | 2506 | .flags = CLOCK_IN_OMAP243X | CLOCK_IN_OMAP242X, |
2507 | .clkdm_name = "core_l3_clkdm", | ||
2380 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2508 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2381 | .enable_bit = OMAP24XX_EN_USB_SHIFT, | 2509 | .enable_bit = OMAP24XX_EN_USB_SHIFT, |
2382 | .recalc = &followparent_recalc, | 2510 | .recalc = &followparent_recalc, |
@@ -2386,6 +2514,7 @@ static struct clk usbhs_ick = { | |||
2386 | .name = "usbhs_ick", | 2514 | .name = "usbhs_ick", |
2387 | .parent = &core_l3_ck, | 2515 | .parent = &core_l3_ck, |
2388 | .flags = CLOCK_IN_OMAP243X, | 2516 | .flags = CLOCK_IN_OMAP243X, |
2517 | .clkdm_name = "core_l3_clkdm", | ||
2389 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2518 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2390 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, | 2519 | .enable_bit = OMAP2430_EN_USBHS_SHIFT, |
2391 | .recalc = &followparent_recalc, | 2520 | .recalc = &followparent_recalc, |
@@ -2396,6 +2525,7 @@ static struct clk mmchs1_ick = { | |||
2396 | .id = 1, | 2525 | .id = 1, |
2397 | .parent = &l4_ck, | 2526 | .parent = &l4_ck, |
2398 | .flags = CLOCK_IN_OMAP243X, | 2527 | .flags = CLOCK_IN_OMAP243X, |
2528 | .clkdm_name = "core_l4_clkdm", | ||
2399 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2529 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2400 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2530 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
2401 | .recalc = &followparent_recalc, | 2531 | .recalc = &followparent_recalc, |
@@ -2406,6 +2536,7 @@ static struct clk mmchs1_fck = { | |||
2406 | .id = 1, | 2536 | .id = 1, |
2407 | .parent = &func_96m_ck, | 2537 | .parent = &func_96m_ck, |
2408 | .flags = CLOCK_IN_OMAP243X, | 2538 | .flags = CLOCK_IN_OMAP243X, |
2539 | .clkdm_name = "core_l3_clkdm", | ||
2409 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2540 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2410 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, | 2541 | .enable_bit = OMAP2430_EN_MMCHS1_SHIFT, |
2411 | .recalc = &followparent_recalc, | 2542 | .recalc = &followparent_recalc, |
@@ -2416,6 +2547,7 @@ static struct clk mmchs2_ick = { | |||
2416 | .id = 2, | 2547 | .id = 2, |
2417 | .parent = &l4_ck, | 2548 | .parent = &l4_ck, |
2418 | .flags = CLOCK_IN_OMAP243X, | 2549 | .flags = CLOCK_IN_OMAP243X, |
2550 | .clkdm_name = "core_l4_clkdm", | ||
2419 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2551 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2420 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, | 2552 | .enable_bit = OMAP2430_EN_MMCHS2_SHIFT, |
2421 | .recalc = &followparent_recalc, | 2553 | .recalc = &followparent_recalc, |
@@ -2435,6 +2567,7 @@ static struct clk gpio5_ick = { | |||
2435 | .name = "gpio5_ick", | 2567 | .name = "gpio5_ick", |
2436 | .parent = &l4_ck, | 2568 | .parent = &l4_ck, |
2437 | .flags = CLOCK_IN_OMAP243X, | 2569 | .flags = CLOCK_IN_OMAP243X, |
2570 | .clkdm_name = "core_l4_clkdm", | ||
2438 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2571 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2439 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2572 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
2440 | .recalc = &followparent_recalc, | 2573 | .recalc = &followparent_recalc, |
@@ -2444,6 +2577,7 @@ static struct clk gpio5_fck = { | |||
2444 | .name = "gpio5_fck", | 2577 | .name = "gpio5_fck", |
2445 | .parent = &func_32k_ck, | 2578 | .parent = &func_32k_ck, |
2446 | .flags = CLOCK_IN_OMAP243X, | 2579 | .flags = CLOCK_IN_OMAP243X, |
2580 | .clkdm_name = "core_l4_clkdm", | ||
2447 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2581 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2448 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, | 2582 | .enable_bit = OMAP2430_EN_GPIO5_SHIFT, |
2449 | .recalc = &followparent_recalc, | 2583 | .recalc = &followparent_recalc, |
@@ -2453,6 +2587,7 @@ static struct clk mdm_intc_ick = { | |||
2453 | .name = "mdm_intc_ick", | 2587 | .name = "mdm_intc_ick", |
2454 | .parent = &l4_ck, | 2588 | .parent = &l4_ck, |
2455 | .flags = CLOCK_IN_OMAP243X, | 2589 | .flags = CLOCK_IN_OMAP243X, |
2590 | .clkdm_name = "core_l4_clkdm", | ||
2456 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | 2591 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), |
2457 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, | 2592 | .enable_bit = OMAP2430_EN_MDM_INTC_SHIFT, |
2458 | .recalc = &followparent_recalc, | 2593 | .recalc = &followparent_recalc, |
@@ -2463,6 +2598,7 @@ static struct clk mmchsdb1_fck = { | |||
2463 | .id = 1, | 2598 | .id = 1, |
2464 | .parent = &func_32k_ck, | 2599 | .parent = &func_32k_ck, |
2465 | .flags = CLOCK_IN_OMAP243X, | 2600 | .flags = CLOCK_IN_OMAP243X, |
2601 | .clkdm_name = "core_l4_clkdm", | ||
2466 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2602 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2467 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, | 2603 | .enable_bit = OMAP2430_EN_MMCHSDB1_SHIFT, |
2468 | .recalc = &followparent_recalc, | 2604 | .recalc = &followparent_recalc, |
@@ -2473,6 +2609,7 @@ static struct clk mmchsdb2_fck = { | |||
2473 | .id = 2, | 2609 | .id = 2, |
2474 | .parent = &func_32k_ck, | 2610 | .parent = &func_32k_ck, |
2475 | .flags = CLOCK_IN_OMAP243X, | 2611 | .flags = CLOCK_IN_OMAP243X, |
2612 | .clkdm_name = "core_l4_clkdm", | ||
2476 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), | 2613 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2), |
2477 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, | 2614 | .enable_bit = OMAP2430_EN_MMCHSDB2_SHIFT, |
2478 | .recalc = &followparent_recalc, | 2615 | .recalc = &followparent_recalc, |
@@ -2551,7 +2688,6 @@ static struct clk *onchip_24xx_clks[] __initdata = { | |||
2551 | &usb_l4_ick, | 2688 | &usb_l4_ick, |
2552 | /* L4 domain clocks */ | 2689 | /* L4 domain clocks */ |
2553 | &l4_ck, /* used as both core_l4 and wu_l4 */ | 2690 | &l4_ck, /* used as both core_l4 and wu_l4 */ |
2554 | &ssi_l4_ick, | ||
2555 | /* virtual meta-group clock */ | 2691 | /* virtual meta-group clock */ |
2556 | &virt_prcm_set, | 2692 | &virt_prcm_set, |
2557 | /* general l4 interface ck, multi-parent functional clk */ | 2693 | /* general l4 interface ck, multi-parent functional clk */ |
diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h index 92f7c7238fcd..719298554ed7 100644 --- a/arch/arm/plat-omap/include/mach/clock.h +++ b/arch/arm/plat-omap/include/mach/clock.h | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | struct module; | 16 | struct module; |
17 | struct clk; | 17 | struct clk; |
18 | struct clockdomain; | ||
18 | 19 | ||
19 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) | 20 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
20 | 21 | ||
@@ -79,6 +80,8 @@ struct clk { | |||
79 | u32 clksel_mask; | 80 | u32 clksel_mask; |
80 | const struct clksel *clksel; | 81 | const struct clksel *clksel; |
81 | struct dpll_data *dpll_data; | 82 | struct dpll_data *dpll_data; |
83 | const char *clkdm_name; | ||
84 | struct clockdomain *clkdm; | ||
82 | #else | 85 | #else |
83 | __u8 rate_offset; | 86 | __u8 rate_offset; |
84 | __u8 src_offset; | 87 | __u8 src_offset; |