diff options
Diffstat (limited to 'arch/arm')
-rw-r--r-- | arch/arm/mach-mmp/time.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c index 99833b9485cf..09e88c25fe8e 100644 --- a/arch/arm/mach-mmp/time.c +++ b/arch/arm/mach-mmp/time.c | |||
@@ -145,23 +145,26 @@ static struct clocksource cksrc = { | |||
145 | static void __init timer_config(void) | 145 | static void __init timer_config(void) |
146 | { | 146 | { |
147 | uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); | 147 | uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR); |
148 | uint32_t cer = __raw_readl(TIMERS_VIRT_BASE + TMR_CER); | ||
149 | uint32_t cmr = __raw_readl(TIMERS_VIRT_BASE + TMR_CMR); | ||
150 | 148 | ||
151 | __raw_writel(cer & ~0x1, TIMERS_VIRT_BASE + TMR_CER); /* disable */ | 149 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */ |
152 | 150 | ||
153 | ccr &= (cpu_is_mmp2()) ? TMR_CCR_CS_0(0) : TMR_CCR_CS_0(3); | 151 | ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) : |
152 | (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3)); | ||
154 | __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); | 153 | __raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR); |
155 | 154 | ||
156 | /* free-running mode */ | 155 | /* free-running mode */ |
157 | __raw_writel(cmr | 0x01, TIMERS_VIRT_BASE + TMR_CMR); | 156 | __raw_writel(0x3, TIMERS_VIRT_BASE + TMR_CMR); |
158 | 157 | ||
159 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */ | 158 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* free-running */ |
160 | __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ | 159 | __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */ |
161 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); | 160 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0)); |
162 | 161 | ||
162 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */ | ||
163 | __raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */ | ||
164 | __raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1)); | ||
165 | |||
163 | /* enable timer counter */ | 166 | /* enable timer counter */ |
164 | __raw_writel(cer | 0x01, TIMERS_VIRT_BASE + TMR_CER); | 167 | __raw_writel(0x3, TIMERS_VIRT_BASE + TMR_CER); |
165 | } | 168 | } |
166 | 169 | ||
167 | static struct irqaction timer_irq = { | 170 | static struct irqaction timer_irq = { |