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-rw-r--r--arch/arm/mach-imx/Makefile5
-rw-r--r--arch/arm/mach-imx/cache-l2x0.c56
-rw-r--r--arch/arm/mach-imx/mm-imx3.c256
-rw-r--r--arch/arm/mach-imx/mm-imx31.c91
-rw-r--r--arch/arm/mach-imx/mm-imx35.c109
-rw-r--r--arch/arm/mach-imx/pm-imx27.c2
-rw-r--r--arch/arm/mach-mx5/mm.c6
-rw-r--r--arch/arm/mach-mx5/pm-imx5.c3
-rw-r--r--arch/arm/mach-mx5/system.c1
-rw-r--r--arch/arm/mach-mxs/Makefile6
-rw-r--r--arch/arm/mach-mxs/mm-mx23.c44
-rw-r--r--arch/arm/mach-mxs/mm.c (renamed from arch/arm/mach-mxs/mm-mx28.c)19
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h11
-rw-r--r--arch/arm/plat-mxc/include/mach/io.h22
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h7
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h35
-rw-r--r--arch/arm/plat-mxc/system.c3
17 files changed, 313 insertions, 363 deletions
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index db6394a77e85..6cc821384ccd 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -8,9 +8,8 @@ obj-$(CONFIG_SOC_IMX25) += clock-imx25.o mm-imx25.o ehci-imx25.o
8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o 8obj-$(CONFIG_SOC_IMX27) += cpu-imx27.o pm-imx27.o
9obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o 9obj-$(CONFIG_SOC_IMX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
10 10
11obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o 11obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
12obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o 12obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clock-imx35.o ehci-imx35.o
13obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
14 13
15# Support for CMOS sensor interface 14# Support for CMOS sensor interface
16obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o 15obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
deleted file mode 100644
index 69d1322add3c..000000000000
--- a/arch/arm/mach-imx/cache-l2x0.c
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Sascha Hauer <s.hauer@pengutronix.de>
4 * Juergen Beisert <j.beisert@pengutronix.de>
5 *
6 * This program is free software; you can redistribute it and/or modify it under
7 * the terms of the GNU General Public License version 2 as published by the
8 * Free Software Foundation.
9 */
10
11#include <linux/init.h>
12#include <linux/err.h>
13#include <linux/kernel.h>
14
15#include <asm/hardware/cache-l2x0.h>
16
17#include <mach/hardware.h>
18
19static int mxc_init_l2x0(void)
20{
21 void __iomem *l2x0_base;
22 void __iomem *clkctl_base;
23
24 if (!cpu_is_mx31() && !cpu_is_mx35())
25 return 0;
26
27/*
28 * First of all, we must repair broken chip settings. There are some
29 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
30 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
31 * Workaraound is to setup the correct register setting prior enabling the
32 * L2 cache. This should not hurt already working CPUs, as they are using the
33 * same value.
34 */
35#define L2_MEM_VAL 0x10
36
37 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
38 if (clkctl_base != NULL) {
39 writel(0x00000515, clkctl_base + L2_MEM_VAL);
40 iounmap(clkctl_base);
41 } else {
42 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
43 }
44
45 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
46 if (IS_ERR(l2x0_base)) {
47 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
48 PTR_ERR(l2x0_base));
49 return 0;
50 }
51
52 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
53
54 return 0;
55}
56arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/mm-imx3.c b/arch/arm/mach-imx/mm-imx3.c
new file mode 100644
index 000000000000..9f0e82ec3398
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx3.c
@@ -0,0 +1,256 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/hardware/cache-l2x0.h>
25#include <asm/mach/map.h>
26
27#include <mach/common.h>
28#include <mach/devices-common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-v3.h>
31#include <mach/irqs.h>
32
33static void imx3_idle(void)
34{
35 unsigned long reg = 0;
36 __asm__ __volatile__(
37 /* disable I and D cache */
38 "mrc p15, 0, %0, c1, c0, 0\n"
39 "bic %0, %0, #0x00001000\n"
40 "bic %0, %0, #0x00000004\n"
41 "mcr p15, 0, %0, c1, c0, 0\n"
42 /* invalidate I cache */
43 "mov %0, #0\n"
44 "mcr p15, 0, %0, c7, c5, 0\n"
45 /* clear and invalidate D cache */
46 "mov %0, #0\n"
47 "mcr p15, 0, %0, c7, c14, 0\n"
48 /* WFI */
49 "mov %0, #0\n"
50 "mcr p15, 0, %0, c7, c0, 4\n"
51 "nop\n" "nop\n" "nop\n" "nop\n"
52 "nop\n" "nop\n" "nop\n"
53 /* enable I and D cache */
54 "mrc p15, 0, %0, c1, c0, 0\n"
55 "orr %0, %0, #0x00001000\n"
56 "orr %0, %0, #0x00000004\n"
57 "mcr p15, 0, %0, c1, c0, 0\n"
58 : "=r" (reg));
59}
60
61static void __iomem *imx3_ioremap(unsigned long phys_addr, size_t size,
62 unsigned int mtype)
63{
64 if (mtype == MT_DEVICE) {
65 /*
66 * Access all peripherals below 0x80000000 as nonshared device
67 * on mx3, but leave l2cc alone. Otherwise cache corruptions
68 * can occur.
69 */
70 if (phys_addr < 0x80000000 &&
71 !addr_in_module(phys_addr, MX3x_L2CC))
72 mtype = MT_DEVICE_NONSHARED;
73 }
74
75 return __arm_ioremap(phys_addr, size, mtype);
76}
77
78void imx3_init_l2x0(void)
79{
80 void __iomem *l2x0_base;
81 void __iomem *clkctl_base;
82
83/*
84 * First of all, we must repair broken chip settings. There are some
85 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
86 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
87 * Workaraound is to setup the correct register setting prior enabling the
88 * L2 cache. This should not hurt already working CPUs, as they are using the
89 * same value.
90 */
91#define L2_MEM_VAL 0x10
92
93 clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
94 if (clkctl_base != NULL) {
95 writel(0x00000515, clkctl_base + L2_MEM_VAL);
96 iounmap(clkctl_base);
97 } else {
98 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
99 }
100
101 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
102 if (IS_ERR(l2x0_base)) {
103 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
104 PTR_ERR(l2x0_base));
105 return;
106 }
107
108 l2x0_init(l2x0_base, 0x00030024, 0x00000000);
109}
110
111static struct map_desc mx31_io_desc[] __initdata = {
112 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
113 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
114 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
115 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
116 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
117};
118
119/*
120 * This function initializes the memory map. It is called during the
121 * system startup to create static physical to virtual memory mappings
122 * for the IO modules.
123 */
124void __init mx31_map_io(void)
125{
126 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
127}
128
129static struct map_desc mx35_io_desc[] __initdata = {
130 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
131 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
132 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
133 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
134 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
135};
136
137void __init mx35_map_io(void)
138{
139 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
140}
141
142void __init imx31_init_early(void)
143{
144 mxc_set_cpu_type(MXC_CPU_MX31);
145 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
146 imx_idle = imx3_idle;
147 imx_ioremap = imx3_ioremap;
148}
149
150void __init imx35_init_early(void)
151{
152 mxc_set_cpu_type(MXC_CPU_MX35);
153 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
154 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
155 imx_idle = imx3_idle;
156 imx_ioremap = imx3_ioremap;
157}
158
159void __init mx31_init_irq(void)
160{
161 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
162}
163
164void __init mx35_init_irq(void)
165{
166 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
167}
168
169static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
170 .per_2_per_addr = 1677,
171};
172
173static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
174 .ap_2_ap_addr = 423,
175 .ap_2_bp_addr = 829,
176 .bp_2_ap_addr = 1029,
177};
178
179static struct sdma_platform_data imx31_sdma_pdata __initdata = {
180 .fw_name = "sdma-imx31-to2.bin",
181 .script_addrs = &imx31_to2_sdma_script,
182};
183
184void __init imx31_soc_init(void)
185{
186 int to_version = mx31_revision() >> 4;
187
188 imx3_init_l2x0();
189
190 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
191 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
192 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
193
194 if (to_version == 1) {
195 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
196 strlen(imx31_sdma_pdata.fw_name));
197 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
198 }
199
200 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
201}
202
203static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
204 .ap_2_ap_addr = 642,
205 .uart_2_mcu_addr = 817,
206 .mcu_2_app_addr = 747,
207 .uartsh_2_mcu_addr = 1183,
208 .per_2_shp_addr = 1033,
209 .mcu_2_shp_addr = 961,
210 .ata_2_mcu_addr = 1333,
211 .mcu_2_ata_addr = 1252,
212 .app_2_mcu_addr = 683,
213 .shp_2_per_addr = 1111,
214 .shp_2_mcu_addr = 892,
215};
216
217static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
218 .ap_2_ap_addr = 729,
219 .uart_2_mcu_addr = 904,
220 .per_2_app_addr = 1597,
221 .mcu_2_app_addr = 834,
222 .uartsh_2_mcu_addr = 1270,
223 .per_2_shp_addr = 1120,
224 .mcu_2_shp_addr = 1048,
225 .ata_2_mcu_addr = 1429,
226 .mcu_2_ata_addr = 1339,
227 .app_2_per_addr = 1531,
228 .app_2_mcu_addr = 770,
229 .shp_2_per_addr = 1198,
230 .shp_2_mcu_addr = 979,
231};
232
233static struct sdma_platform_data imx35_sdma_pdata __initdata = {
234 .fw_name = "sdma-imx35-to2.bin",
235 .script_addrs = &imx35_to2_sdma_script,
236};
237
238void __init imx35_soc_init(void)
239{
240 int to_version = mx35_revision() >> 4;
241
242 imx3_init_l2x0();
243
244 /* i.mx35 has the i.mx31 type gpio */
245 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
246 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
247 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
248
249 if (to_version == 1) {
250 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
251 strlen(imx35_sdma_pdata.fw_name));
252 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
253 }
254
255 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
256}
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
deleted file mode 100644
index b7c55e7db000..000000000000
--- a/arch/arm/mach-imx/mm-imx31.c
+++ /dev/null
@@ -1,91 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25
26#include <mach/common.h>
27#include <mach/devices-common.h>
28#include <mach/hardware.h>
29#include <mach/iomux-v3.h>
30#include <mach/irqs.h>
31
32static struct map_desc mx31_io_desc[] __initdata = {
33 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
34 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
35 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
38};
39
40/*
41 * This function initializes the memory map. It is called during the
42 * system startup to create static physical to virtual memory mappings
43 * for the IO modules.
44 */
45void __init mx31_map_io(void)
46{
47 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
48}
49
50void __init imx31_init_early(void)
51{
52 mxc_set_cpu_type(MXC_CPU_MX31);
53 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
54}
55
56void __init mx31_init_irq(void)
57{
58 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
59}
60
61static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
62 .per_2_per_addr = 1677,
63};
64
65static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
66 .ap_2_ap_addr = 423,
67 .ap_2_bp_addr = 829,
68 .bp_2_ap_addr = 1029,
69};
70
71static struct sdma_platform_data imx31_sdma_pdata __initdata = {
72 .fw_name = "sdma-imx31-to2.bin",
73 .script_addrs = &imx31_to2_sdma_script,
74};
75
76void __init imx31_soc_init(void)
77{
78 int to_version = mx31_revision() >> 4;
79
80 mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
81 mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
82 mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
83
84 if (to_version == 1) {
85 strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
86 strlen(imx31_sdma_pdata.fw_name));
87 imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
88 }
89
90 imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
91}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
deleted file mode 100644
index f49bac7a1ede..000000000000
--- a/arch/arm/mach-imx/mm-imx35.c
+++ /dev/null
@@ -1,109 +0,0 @@
1/*
2 * Copyright (C) 1999,2000 Arm Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
5 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * - add MX31 specific definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/mm.h>
20#include <linux/init.h>
21#include <linux/err.h>
22
23#include <asm/pgtable.h>
24#include <asm/mach/map.h>
25#include <asm/hardware/cache-l2x0.h>
26
27#include <mach/common.h>
28#include <mach/devices-common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-v3.h>
31#include <mach/irqs.h>
32
33static struct map_desc mx35_io_desc[] __initdata = {
34 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
35 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
36 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
37 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
38 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
39};
40
41void __init mx35_map_io(void)
42{
43 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
44}
45
46void __init imx35_init_early(void)
47{
48 mxc_set_cpu_type(MXC_CPU_MX35);
49 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
50 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
51}
52
53void __init mx35_init_irq(void)
54{
55 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
56}
57
58static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
59 .ap_2_ap_addr = 642,
60 .uart_2_mcu_addr = 817,
61 .mcu_2_app_addr = 747,
62 .uartsh_2_mcu_addr = 1183,
63 .per_2_shp_addr = 1033,
64 .mcu_2_shp_addr = 961,
65 .ata_2_mcu_addr = 1333,
66 .mcu_2_ata_addr = 1252,
67 .app_2_mcu_addr = 683,
68 .shp_2_per_addr = 1111,
69 .shp_2_mcu_addr = 892,
70};
71
72static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
73 .ap_2_ap_addr = 729,
74 .uart_2_mcu_addr = 904,
75 .per_2_app_addr = 1597,
76 .mcu_2_app_addr = 834,
77 .uartsh_2_mcu_addr = 1270,
78 .per_2_shp_addr = 1120,
79 .mcu_2_shp_addr = 1048,
80 .ata_2_mcu_addr = 1429,
81 .mcu_2_ata_addr = 1339,
82 .app_2_per_addr = 1531,
83 .app_2_mcu_addr = 770,
84 .shp_2_per_addr = 1198,
85 .shp_2_mcu_addr = 979,
86};
87
88static struct sdma_platform_data imx35_sdma_pdata __initdata = {
89 .fw_name = "sdma-imx35-to2.bin",
90 .script_addrs = &imx35_to2_sdma_script,
91};
92
93void __init imx35_soc_init(void)
94{
95 int to_version = mx35_revision() >> 4;
96
97 /* i.mx35 has the i.mx31 type gpio */
98 mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
99 mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
100 mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
101
102 if (to_version == 1) {
103 strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
104 strlen(imx35_sdma_pdata.fw_name));
105 imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
106 }
107
108 imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
109}
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index acf17691d2cc..e455d2f855bf 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -11,7 +11,7 @@
11#include <linux/suspend.h> 11#include <linux/suspend.h>
12#include <linux/io.h> 12#include <linux/io.h>
13#include <mach/system.h> 13#include <mach/system.h>
14#include <mach/mx27.h> 14#include <mach/hardware.h>
15 15
16static int mx27_suspend_enter(suspend_state_t state) 16static int mx27_suspend_enter(suspend_state_t state)
17{ 17{
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index fb653395624d..26eacc9d0d90 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -21,6 +21,11 @@
21#include <mach/devices-common.h> 21#include <mach/devices-common.h>
22#include <mach/iomux-v3.h> 22#include <mach/iomux-v3.h>
23 23
24static void imx5_idle(void)
25{
26 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
27}
28
24/* 29/*
25 * Define the MX50 memory map. 30 * Define the MX50 memory map.
26 */ 31 */
@@ -84,6 +89,7 @@ void __init imx51_init_early(void)
84 mxc_set_cpu_type(MXC_CPU_MX51); 89 mxc_set_cpu_type(MXC_CPU_MX51);
85 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 90 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
86 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR)); 91 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
92 imx_idle = imx5_idle;
87} 93}
88 94
89void __init imx53_init_early(void) 95void __init imx53_init_early(void)
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
index e4529af0da72..0624fb8edffb 100644
--- a/arch/arm/mach-mx5/pm-imx5.c
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -14,7 +14,8 @@
14#include <linux/err.h> 14#include <linux/err.h>
15#include <asm/cacheflush.h> 15#include <asm/cacheflush.h>
16#include <asm/tlbflush.h> 16#include <asm/tlbflush.h>
17#include <mach/system.h> 17#include <mach/common.h>
18#include <mach/hardware.h>
18#include "crm_regs.h" 19#include "crm_regs.h"
19 20
20static struct clk *gpc_dvfs_clk; 21static struct clk *gpc_dvfs_clk;
diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c
index 76ae8dc33e00..144ebebc4a61 100644
--- a/arch/arm/mach-mx5/system.c
+++ b/arch/arm/mach-mx5/system.c
@@ -13,6 +13,7 @@
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <mach/hardware.h> 15#include <mach/hardware.h>
16#include <mach/common.h>
16#include "crm_regs.h" 17#include "crm_regs.h"
17 18
18/* set cpu low power mode before WFI instruction. This function is called 19/* set cpu low power mode before WFI instruction. This function is called
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 6c38262a3aaa..ea8dcb7742bc 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,11 +1,11 @@
1# Common support 1# Common support
2obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o 2obj-y := clock.o devices.o icoll.o iomux.o system.o timer.o mm.o
3 3
4obj-$(CONFIG_MXS_OCOTP) += ocotp.o 4obj-$(CONFIG_MXS_OCOTP) += ocotp.o
5obj-$(CONFIG_PM) += pm.o 5obj-$(CONFIG_PM) += pm.o
6 6
7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o 7obj-$(CONFIG_SOC_IMX23) += clock-mx23.o
8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o 8obj-$(CONFIG_SOC_IMX28) += clock-mx28.o
9 9
10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o 10obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o 11obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
deleted file mode 100644
index 1b2345ac1a87..000000000000
--- a/arch/arm/mach-mxs/mm-mx23.c
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/mx23.h>
20#include <mach/common.h>
21#include <mach/iomux.h>
22
23/*
24 * Define the MX23 memory map.
25 */
26static struct map_desc mx23_io_desc[] __initdata = {
27 mxs_map_entry(MX23, OCRAM, MT_DEVICE),
28 mxs_map_entry(MX23, IO, MT_DEVICE),
29};
30
31/*
32 * This function initializes the memory map. It is called during the
33 * system startup to create static physical to virtual memory mappings
34 * for the IO modules.
35 */
36void __init mx23_map_io(void)
37{
38 iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
39}
40
41void __init mx23_init_irq(void)
42{
43 icoll_init_irq();
44}
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm.c
index b6e18ddb92c0..50af5ceebf6d 100644
--- a/arch/arm/mach-mxs/mm-mx28.c
+++ b/arch/arm/mach-mxs/mm.c
@@ -16,11 +16,20 @@
16 16
17#include <asm/mach/map.h> 17#include <asm/mach/map.h>
18 18
19#include <mach/mx23.h>
19#include <mach/mx28.h> 20#include <mach/mx28.h>
20#include <mach/common.h> 21#include <mach/common.h>
21#include <mach/iomux.h> 22#include <mach/iomux.h>
22 23
23/* 24/*
25 * Define the MX23 memory map.
26 */
27static struct map_desc mx23_io_desc[] __initdata = {
28 mxs_map_entry(MX23, OCRAM, MT_DEVICE),
29 mxs_map_entry(MX23, IO, MT_DEVICE),
30};
31
32/*
24 * Define the MX28 memory map. 33 * Define the MX28 memory map.
25 */ 34 */
26static struct map_desc mx28_io_desc[] __initdata = { 35static struct map_desc mx28_io_desc[] __initdata = {
@@ -33,6 +42,16 @@ static struct map_desc mx28_io_desc[] __initdata = {
33 * system startup to create static physical to virtual memory mappings 42 * system startup to create static physical to virtual memory mappings
34 * for the IO modules. 43 * for the IO modules.
35 */ 44 */
45void __init mx23_map_io(void)
46{
47 iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
48}
49
50void __init mx23_init_irq(void)
51{
52 icoll_init_irq();
53}
54
36void __init mx28_map_io(void) 55void __init mx28_map_io(void)
37{ 56{
38 iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc)); 57 iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 91d810cef6fa..d7149d1bd32c 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -71,4 +71,15 @@ extern void mxc_arch_reset_init(void __iomem *);
71extern void mx51_efikamx_reset(void); 71extern void mx51_efikamx_reset(void);
72extern int mx53_revision(void); 72extern int mx53_revision(void);
73extern int mx53_display_revision(void); 73extern int mx53_display_revision(void);
74
75enum mxc_cpu_pwr_mode {
76 WAIT_CLOCKED, /* wfi only */
77 WAIT_UNCLOCKED, /* WAIT */
78 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
79 STOP_POWER_ON, /* just STOP */
80 STOP_POWER_OFF, /* STOP + SRPG */
81};
82
83extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
84extern void (*imx_idle)(void);
74#endif 85#endif
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index 4347a87d2bb0..338300b18b00 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,32 +14,22 @@
14/* Allow IO space to be anywhere in the memory */ 14/* Allow IO space to be anywhere in the memory */
15#define IO_SPACE_LIMIT 0xffffffff 15#define IO_SPACE_LIMIT 0xffffffff
16 16
17#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
18#include <mach/hardware.h>
19
20#define __arch_ioremap __imx_ioremap 17#define __arch_ioremap __imx_ioremap
21#define __arch_iounmap __iounmap 18#define __arch_iounmap __iounmap
22 19
23#define addr_in_module(addr, mod) \ 20#define addr_in_module(addr, mod) \
24 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE) 21 ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
25 22
23extern void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int);
24
26static inline void __iomem * 25static inline void __iomem *
27__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype) 26__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
28{ 27{
29 if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) { 28 if (imx_ioremap != NULL)
30 /* 29 return imx_ioremap(phys_addr, size, mtype);
31 * Access all peripherals below 0x80000000 as nonshared device 30 else
32 * on mx3, but leave l2cc alone. Otherwise cache corruptions 31 return __arm_ioremap(phys_addr, size, mtype);
33 * can occur.
34 */
35 if (phys_addr < 0x80000000 &&
36 !addr_in_module(phys_addr, MX3x_L2CC))
37 mtype = MT_DEVICE_NONSHARED;
38 }
39
40 return __arm_ioremap(phys_addr, size, mtype);
41} 32}
42#endif
43 33
44/* io address mapping macro */ 34/* io address mapping macro */
45#define __io(a) __typesafe_io(a) 35#define __io(a) __typesafe_io(a)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 09879235a9f5..00a78193c681 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -183,13 +183,6 @@ struct cpu_op {
183}; 183};
184 184
185int tzic_enable_wake(int is_idle); 185int tzic_enable_wake(int is_idle);
186enum mxc_cpu_pwr_mode {
187 WAIT_CLOCKED, /* wfi only */
188 WAIT_UNCLOCKED, /* WAIT */
189 WAIT_UNCLOCKED_POWER_OFF, /* WAIT + SRPG */
190 STOP_POWER_ON, /* just STOP */
191 STOP_POWER_OFF, /* STOP + SRPG */
192};
193 186
194extern struct cpu_op *(*get_cpu_op)(int *op); 187extern struct cpu_op *(*get_cpu_op)(int *op);
195#endif 188#endif
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 51f02a9d41a3..cf88b3593fba 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -17,41 +17,12 @@
17#ifndef __ASM_ARCH_MXC_SYSTEM_H__ 17#ifndef __ASM_ARCH_MXC_SYSTEM_H__
18#define __ASM_ARCH_MXC_SYSTEM_H__ 18#define __ASM_ARCH_MXC_SYSTEM_H__
19 19
20#include <mach/hardware.h> 20extern void (*imx_idle)(void);
21#include <mach/common.h>
22
23extern void mx5_cpu_lp_set(enum mxc_cpu_pwr_mode mode);
24 21
25static inline void arch_idle(void) 22static inline void arch_idle(void)
26{ 23{
27 /* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */ 24 if (imx_idle != NULL)
28 if (cpu_is_mx31() || cpu_is_mx35()) { 25 (imx_idle)();
29 unsigned long reg = 0;
30 __asm__ __volatile__(
31 /* disable I and D cache */
32 "mrc p15, 0, %0, c1, c0, 0\n"
33 "bic %0, %0, #0x00001000\n"
34 "bic %0, %0, #0x00000004\n"
35 "mcr p15, 0, %0, c1, c0, 0\n"
36 /* invalidate I cache */
37 "mov %0, #0\n"
38 "mcr p15, 0, %0, c7, c5, 0\n"
39 /* clear and invalidate D cache */
40 "mov %0, #0\n"
41 "mcr p15, 0, %0, c7, c14, 0\n"
42 /* WFI */
43 "mov %0, #0\n"
44 "mcr p15, 0, %0, c7, c0, 4\n"
45 "nop\n" "nop\n" "nop\n" "nop\n"
46 "nop\n" "nop\n" "nop\n"
47 /* enable I and D cache */
48 "mrc p15, 0, %0, c1, c0, 0\n"
49 "orr %0, %0, #0x00001000\n"
50 "orr %0, %0, #0x00000004\n"
51 "mcr p15, 0, %0, c1, c0, 0\n"
52 : "=r" (reg));
53 } else if (cpu_is_mx51())
54 mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
55 else 26 else
56 cpu_do_idle(); 27 cpu_do_idle();
57} 28}
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 8024f2ac177c..9dad8dcc2ea9 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -28,6 +28,9 @@
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
30 30
31void (*imx_idle)(void) = NULL;
32void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
33
31static void __iomem *wdog_base; 34static void __iomem *wdog_base;
32 35
33/* 36/*
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-09 02:03:01 -0500