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-rw-r--r--arch/arm/mach-s3c2410/Kconfig2
-rw-r--r--arch/arm/mach-s3c2440/Kconfig2
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig5
-rw-r--r--arch/arm/plat-s3c24xx/Makefile1
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c194
-rw-r--r--arch/arm/plat-s3c24xx/clock.c171
6 files changed, 204 insertions, 171 deletions
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 5453aff60486..63a30d1dd425 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -80,6 +80,7 @@ config ARCH_BAST
80 select PM_SIMTEC if PM 80 select PM_SIMTEC if PM
81 select SIMTEC_NOR 81 select SIMTEC_NOR
82 select MACH_BAST_IDE 82 select MACH_BAST_IDE
83 select S3C24XX_DCLK
83 select ISA 84 select ISA
84 help 85 help
85 Say Y here if you are using the Simtec Electronics EB2410ITX 86 Say Y here if you are using the Simtec Electronics EB2410ITX
@@ -117,6 +118,7 @@ config MACH_TCT_HAMMER
117config MACH_VR1000 118config MACH_VR1000
118 bool "Thorcom VR1000" 119 bool "Thorcom VR1000"
119 select PM_SIMTEC if PM 120 select PM_SIMTEC if PM
121 select S3C24XX_DCLK
120 select SIMTEC_NOR 122 select SIMTEC_NOR
121 select MACH_BAST_IDE 123 select MACH_BAST_IDE
122 select CPU_S3C2410 124 select CPU_S3C2410
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 0429d255b0d8..57b9c57ff2b4 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -29,6 +29,7 @@ menu "S3C2440 Machines"
29config MACH_ANUBIS 29config MACH_ANUBIS
30 bool "Simtec Electronics ANUBIS" 30 bool "Simtec Electronics ANUBIS"
31 select CPU_S3C2440 31 select CPU_S3C2440
32 select S3C24XX_DCLK
32 select PM_SIMTEC if PM 33 select PM_SIMTEC if PM
33 select HAVE_PATA_PLATFORM 34 select HAVE_PATA_PLATFORM
34 help 35 help
@@ -38,6 +39,7 @@ config MACH_ANUBIS
38config MACH_OSIRIS 39config MACH_OSIRIS
39 bool "Simtec IM2440D20 (OSIRIS) module" 40 bool "Simtec IM2440D20 (OSIRIS) module"
40 select CPU_S3C2440 41 select CPU_S3C2440
42 select S3C24XX_DCLK
41 select PM_SIMTEC if PM 43 select PM_SIMTEC if PM
42 help 44 help
43 Say Y here if you are using the Simtec IM2440D20 module, also 45 Say Y here if you are using the Simtec IM2440D20 module, also
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 2bc4b10f5227..d3faf01bbfc2 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -23,6 +23,11 @@ config S3C2410_CLOCK
23 Clock code for the S3C2410, and similar processors which 23 Clock code for the S3C2410, and similar processors which
24 is currently includes the S3C2410, S3C2440, S3C2442. 24 is currently includes the S3C2410, S3C2440, S3C2442.
25 25
26config S3C24XX_DCLK
27 bool
28 help
29 Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
30
26config CPU_S3C244X 31config CPU_S3C244X
27 bool 32 bool
28 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442) 33 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 095a6c2324da..80cf8eb211ff 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -20,6 +20,7 @@ obj-y += gpiolib.o
20obj-y += time.o 20obj-y += time.o
21obj-y += clock.o 21obj-y += clock.o
22obj-y += pwm-clock.o 22obj-y += pwm-clock.o
23obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o
23 24
24# Architecture dependant builds 25# Architecture dependant builds
25 26
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
new file mode 100644
index 000000000000..5b75a797b5ab
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -0,0 +1,194 @@
1/* linux/arch/arm/plat-s3c24xx/clock-dclk.c
2 *
3 * Copyright (c) 2004,2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 * http://armlinux.simtec.co.uk/
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * S3C24XX - definitions for DCLK and CLKOUT registers
12 */
13
14#include <linux/kernel.h>
15#include <linux/errno.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18
19#include <mach/regs-clock.h>
20#include <mach/regs-gpio.h>
21
22#include <plat/clock.h>
23#include <plat/cpu.h>
24
25/* clocks that could be registered by external code */
26
27static int s3c24xx_dclk_enable(struct clk *clk, int enable)
28{
29 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
30
31 if (enable)
32 dclkcon |= clk->ctrlbit;
33 else
34 dclkcon &= ~clk->ctrlbit;
35
36 __raw_writel(dclkcon, S3C24XX_DCLKCON);
37
38 return 0;
39}
40
41static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
42{
43 unsigned long dclkcon;
44 unsigned int uclk;
45
46 if (parent == &clk_upll)
47 uclk = 1;
48 else if (parent == &clk_p)
49 uclk = 0;
50 else
51 return -EINVAL;
52
53 clk->parent = parent;
54
55 dclkcon = __raw_readl(S3C24XX_DCLKCON);
56
57 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
58 if (uclk)
59 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
60 else
61 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
62 } else {
63 if (uclk)
64 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
65 else
66 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
67 }
68
69 __raw_writel(dclkcon, S3C24XX_DCLKCON);
70
71 return 0;
72}
73static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
74{
75 unsigned long div;
76
77 if ((rate == 0) || !clk->parent)
78 return 0;
79
80 div = clk_get_rate(clk->parent) / rate;
81 if (div < 2)
82 div = 2;
83 else if (div > 16)
84 div = 16;
85
86 return div;
87}
88
89static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
90 unsigned long rate)
91{
92 unsigned long div = s3c24xx_calc_div(clk, rate);
93
94 if (div == 0)
95 return 0;
96
97 return clk_get_rate(clk->parent) / div;
98}
99
100static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
101{
102 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
103
104 if (div == 0)
105 return -EINVAL;
106
107 if (clk == &s3c24xx_dclk0) {
108 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
109 S3C2410_DCLKCON_DCLK0_CMP_MASK;
110 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
111 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
112 } else if (clk == &s3c24xx_dclk1) {
113 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
114 S3C2410_DCLKCON_DCLK1_CMP_MASK;
115 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
116 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
117 } else
118 return -EINVAL;
119
120 clk->rate = clk_get_rate(clk->parent) / div;
121 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
122 S3C24XX_DCLKCON);
123 return clk->rate;
124}
125static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
126{
127 unsigned long mask;
128 unsigned long source;
129
130 /* calculate the MISCCR setting for the clock */
131
132 if (parent == &clk_xtal)
133 source = S3C2410_MISCCR_CLK0_MPLL;
134 else if (parent == &clk_upll)
135 source = S3C2410_MISCCR_CLK0_UPLL;
136 else if (parent == &clk_f)
137 source = S3C2410_MISCCR_CLK0_FCLK;
138 else if (parent == &clk_h)
139 source = S3C2410_MISCCR_CLK0_HCLK;
140 else if (parent == &clk_p)
141 source = S3C2410_MISCCR_CLK0_PCLK;
142 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
143 source = S3C2410_MISCCR_CLK0_DCLK0;
144 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
145 source = S3C2410_MISCCR_CLK0_DCLK0;
146 else
147 return -EINVAL;
148
149 clk->parent = parent;
150
151 if (clk == &s3c24xx_clkout0)
152 mask = S3C2410_MISCCR_CLK0_MASK;
153 else {
154 source <<= 4;
155 mask = S3C2410_MISCCR_CLK1_MASK;
156 }
157
158 s3c2410_modify_misccr(mask, source);
159 return 0;
160}
161
162/* external clock definitions */
163
164struct clk s3c24xx_dclk0 = {
165 .name = "dclk0",
166 .id = -1,
167 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
168 .enable = s3c24xx_dclk_enable,
169 .set_parent = s3c24xx_dclk_setparent,
170 .set_rate = s3c24xx_set_dclk_rate,
171 .round_rate = s3c24xx_round_dclk_rate,
172};
173
174struct clk s3c24xx_dclk1 = {
175 .name = "dclk1",
176 .id = -1,
177 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
178 .enable = s3c24xx_dclk_enable,
179 .set_parent = s3c24xx_dclk_setparent,
180 .set_rate = s3c24xx_set_dclk_rate,
181 .round_rate = s3c24xx_round_dclk_rate,
182};
183
184struct clk s3c24xx_clkout0 = {
185 .name = "clkout0",
186 .id = -1,
187 .set_parent = s3c24xx_clkout_setparent,
188};
189
190struct clk s3c24xx_clkout1 = {
191 .name = "clkout1",
192 .id = -1,
193 .set_parent = s3c24xx_clkout_setparent,
194};
diff --git a/arch/arm/plat-s3c24xx/clock.c b/arch/arm/plat-s3c24xx/clock.c
index a005ddbd9ef3..bf2633bd3996 100644
--- a/arch/arm/plat-s3c24xx/clock.c
+++ b/arch/arm/plat-s3c24xx/clock.c
@@ -283,178 +283,7 @@ struct clk clk_usb_bus = {
283 .parent = &clk_upll, 283 .parent = &clk_upll,
284}; 284};
285 285
286/* clocks that could be registered by external code */
287 286
288static int s3c24xx_dclk_enable(struct clk *clk, int enable)
289{
290 unsigned long dclkcon = __raw_readl(S3C24XX_DCLKCON);
291
292 if (enable)
293 dclkcon |= clk->ctrlbit;
294 else
295 dclkcon &= ~clk->ctrlbit;
296
297 __raw_writel(dclkcon, S3C24XX_DCLKCON);
298
299 return 0;
300}
301
302static int s3c24xx_dclk_setparent(struct clk *clk, struct clk *parent)
303{
304 unsigned long dclkcon;
305 unsigned int uclk;
306
307 if (parent == &clk_upll)
308 uclk = 1;
309 else if (parent == &clk_p)
310 uclk = 0;
311 else
312 return -EINVAL;
313
314 clk->parent = parent;
315
316 dclkcon = __raw_readl(S3C24XX_DCLKCON);
317
318 if (clk->ctrlbit == S3C2410_DCLKCON_DCLK0EN) {
319 if (uclk)
320 dclkcon |= S3C2410_DCLKCON_DCLK0_UCLK;
321 else
322 dclkcon &= ~S3C2410_DCLKCON_DCLK0_UCLK;
323 } else {
324 if (uclk)
325 dclkcon |= S3C2410_DCLKCON_DCLK1_UCLK;
326 else
327 dclkcon &= ~S3C2410_DCLKCON_DCLK1_UCLK;
328 }
329
330 __raw_writel(dclkcon, S3C24XX_DCLKCON);
331
332 return 0;
333}
334
335static unsigned long s3c24xx_calc_div(struct clk *clk, unsigned long rate)
336{
337 unsigned long div;
338
339 if ((rate == 0) || !clk->parent)
340 return 0;
341
342 div = clk_get_rate(clk->parent) / rate;
343 if (div < 2)
344 div = 2;
345 else if (div > 16)
346 div = 16;
347
348 return div;
349}
350
351static unsigned long s3c24xx_round_dclk_rate(struct clk *clk,
352 unsigned long rate)
353{
354 unsigned long div = s3c24xx_calc_div(clk, rate);
355
356 if (div == 0)
357 return 0;
358
359 return clk_get_rate(clk->parent) / div;
360}
361
362static int s3c24xx_set_dclk_rate(struct clk *clk, unsigned long rate)
363{
364 unsigned long mask, data, div = s3c24xx_calc_div(clk, rate);
365
366 if (div == 0)
367 return -EINVAL;
368
369 if (clk == &s3c24xx_dclk0) {
370 mask = S3C2410_DCLKCON_DCLK0_DIV_MASK |
371 S3C2410_DCLKCON_DCLK0_CMP_MASK;
372 data = S3C2410_DCLKCON_DCLK0_DIV(div) |
373 S3C2410_DCLKCON_DCLK0_CMP((div + 1) / 2);
374 } else if (clk == &s3c24xx_dclk1) {
375 mask = S3C2410_DCLKCON_DCLK1_DIV_MASK |
376 S3C2410_DCLKCON_DCLK1_CMP_MASK;
377 data = S3C2410_DCLKCON_DCLK1_DIV(div) |
378 S3C2410_DCLKCON_DCLK1_CMP((div + 1) / 2);
379 } else
380 return -EINVAL;
381
382 clk->rate = clk_get_rate(clk->parent) / div;
383 __raw_writel(((__raw_readl(S3C24XX_DCLKCON) & ~mask) | data),
384 S3C24XX_DCLKCON);
385 return clk->rate;
386}
387
388static int s3c24xx_clkout_setparent(struct clk *clk, struct clk *parent)
389{
390 unsigned long mask;
391 unsigned long source;
392
393 /* calculate the MISCCR setting for the clock */
394
395 if (parent == &clk_xtal)
396 source = S3C2410_MISCCR_CLK0_MPLL;
397 else if (parent == &clk_upll)
398 source = S3C2410_MISCCR_CLK0_UPLL;
399 else if (parent == &clk_f)
400 source = S3C2410_MISCCR_CLK0_FCLK;
401 else if (parent == &clk_h)
402 source = S3C2410_MISCCR_CLK0_HCLK;
403 else if (parent == &clk_p)
404 source = S3C2410_MISCCR_CLK0_PCLK;
405 else if (clk == &s3c24xx_clkout0 && parent == &s3c24xx_dclk0)
406 source = S3C2410_MISCCR_CLK0_DCLK0;
407 else if (clk == &s3c24xx_clkout1 && parent == &s3c24xx_dclk1)
408 source = S3C2410_MISCCR_CLK0_DCLK0;
409 else
410 return -EINVAL;
411
412 clk->parent = parent;
413
414 if (clk == &s3c24xx_clkout0)
415 mask = S3C2410_MISCCR_CLK0_MASK;
416 else {
417 source <<= 4;
418 mask = S3C2410_MISCCR_CLK1_MASK;
419 }
420
421 s3c2410_modify_misccr(mask, source);
422 return 0;
423}
424
425/* external clock definitions */
426
427struct clk s3c24xx_dclk0 = {
428 .name = "dclk0",
429 .id = -1,
430 .ctrlbit = S3C2410_DCLKCON_DCLK0EN,
431 .enable = s3c24xx_dclk_enable,
432 .set_parent = s3c24xx_dclk_setparent,
433 .set_rate = s3c24xx_set_dclk_rate,
434 .round_rate = s3c24xx_round_dclk_rate,
435};
436
437struct clk s3c24xx_dclk1 = {
438 .name = "dclk1",
439 .id = -1,
440 .ctrlbit = S3C2410_DCLKCON_DCLK1EN,
441 .enable = s3c24xx_dclk_enable,
442 .set_parent = s3c24xx_dclk_setparent,
443 .set_rate = s3c24xx_set_dclk_rate,
444 .round_rate = s3c24xx_round_dclk_rate,
445};
446
447struct clk s3c24xx_clkout0 = {
448 .name = "clkout0",
449 .id = -1,
450 .set_parent = s3c24xx_clkout_setparent,
451};
452
453struct clk s3c24xx_clkout1 = {
454 .name = "clkout1",
455 .id = -1,
456 .set_parent = s3c24xx_clkout_setparent,
457};
458 287
459struct clk s3c24xx_uclk = { 288struct clk s3c24xx_uclk = {
460 .name = "uclk", 289 .name = "uclk",
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-11 11:22:44 -0500