35 files changed, 195 insertions, 147 deletions

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e60ec54df334..9d02cdb15b23 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -273,6 +273,7 @@ config ARCH_EP93XX
         select HAVE_CLK
         select COMMON_CLKDEV
         select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_HOLES_MEMORYMODEL
         help
           This enables support for the Cirrus EP93xx series of CPUs.
 
@@ -976,10 +977,9 @@ config OABI_COMPAT
           UNPREDICTABLE (in fact it can be predicted that it won't work
           at all). If in doubt say Y.
 
-config ARCH_FLATMEM_HAS_HOLES
+config ARCH_HAS_HOLES_MEMORYMODEL
         bool
-        default y
-        depends on FLATMEM
+        default n
 
 # Discontigmem is deprecated
 config ARCH_DISCONTIGMEM_ENABLE
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index c6884ba1d5ed..3e1714c6523f 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -253,9 +253,9 @@ void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
 }
 
 #ifdef CONFIG_SMP
-void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
+void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 {
-        unsigned long map = *cpus_addr(cpumask);
+        unsigned long map = *cpus_addr(*mask);
 
         /* this always happens on GIC0 */
         writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
diff --git a/arch/arm/include/asm/flat.h b/arch/arm/include/asm/flat.h
index 1d77e51907f6..59426a4595c9 100644
--- a/arch/arm/include/asm/flat.h
+++ b/arch/arm/include/asm/flat.h
@@ -5,9 +5,6 @@
 #ifndef __ARM_FLAT_H__
 #define __ARM_FLAT_H__
 
-/* An odd number of words will be pushed after this alignment, so
-   deliberately misalign the value.  */
-#define flat_stack_align(sp)    sp = (void *)(((unsigned long)(sp) - 4) | 4)
 #define flat_argvp_envp_on_stack()              1
 #define flat_old_ram_flag(flags)                (flags)
 #define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 4924914af188..7f34333bb545 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -36,7 +36,7 @@
 void gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start);
 void gic_cpu_init(unsigned int gic_nr, void __iomem *base);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
-void gic_raise_softirq(cpumask_t cpumask, unsigned int irq);
+void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index fad70da5911d..5995935338e1 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -53,17 +53,12 @@ extern void smp_store_cpu_info(unsigned int cpuid);
 /*
  * Raise an IPI cross call on CPUs in callmap.
  */
-extern void smp_cross_call(cpumask_t callmap);
-
-/*
- * Broadcast a timer interrupt to the other CPUs.
- */
-extern void smp_send_timer(void);
+extern void smp_cross_call(const struct cpumask *mask);
 
 /*
  * Broadcast a clock event to other CPUs.
  */
-extern void smp_timer_broadcast(cpumask_t mask);
+extern void smp_timer_broadcast(const struct cpumask *mask);
 
 /*
  * Boot a secondary CPU, and assign it the specified idle task.
@@ -102,7 +97,8 @@ extern int platform_cpu_kill(unsigned int cpu);
 extern void platform_cpu_enable(unsigned int cpu);
 
 extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
+extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
+#define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask
 
 /*
  * Local timer interrupt handling function (can be IPI'ed).
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 7801aac3c043..6014dfd22af4 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -326,14 +326,14 @@ void __init smp_prepare_boot_cpu(void)
         per_cpu(cpu_data, cpu).idle = current;
 }
 
-static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)
+static void send_ipi_message(const struct cpumask *mask, enum ipi_msg_type msg)
 {
         unsigned long flags;
         unsigned int cpu;
 
         local_irq_save(flags);
 
-        for_each_cpu_mask(cpu, callmap) {
+        for_each_cpu(cpu, mask) {
                 struct ipi_data *ipi = &per_cpu(ipi_data, cpu);
 
                 spin_lock(&ipi->lock);
@@ -344,19 +344,19 @@ static void send_ipi_message(cpumask_t callmap, enum ipi_msg_type msg)
         /*
          * Call the platform specific cross-CPU call function.
          */
-        smp_cross_call(callmap);
+        smp_cross_call(mask);
 
         local_irq_restore(flags);
 }
 
-void arch_send_call_function_ipi(cpumask_t mask)
+void arch_send_call_function_ipi_mask(const struct cpumask *mask)
 {
         send_ipi_message(mask, IPI_CALL_FUNC);
 }
 
 void arch_send_call_function_single_ipi(int cpu)
 {
-        send_ipi_message(cpumask_of_cpu(cpu), IPI_CALL_FUNC_SINGLE);
+        send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC_SINGLE);
 }
 
 void show_ipi_list(struct seq_file *p)
@@ -498,17 +498,10 @@ asmlinkage void __exception do_IPI(struct pt_regs *regs)
 
 void smp_send_reschedule(int cpu)
 {
-        send_ipi_message(cpumask_of_cpu(cpu), IPI_RESCHEDULE);
+        send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
-void smp_send_timer(void)
-{
-        cpumask_t mask = cpu_online_map;
-        cpu_clear(smp_processor_id(), mask);
-        send_ipi_message(mask, IPI_TIMER);
-}
-
-void smp_timer_broadcast(cpumask_t mask)
+void smp_timer_broadcast(const struct cpumask *mask)
 {
         send_ipi_message(mask, IPI_TIMER);
 }
@@ -517,7 +510,7 @@ void smp_send_stop(void)
 {
         cpumask_t mask = cpu_online_map;
         cpu_clear(smp_processor_id(), mask);
-        send_ipi_message(mask, IPI_CPU_STOP);
+        send_ipi_message(&mask, IPI_CPU_STOP);
 }
 
 /*
@@ -528,20 +521,17 @@ int setup_profiling_timer(unsigned int multiplier)
         return -EINVAL;
 }
 
-static int
-on_each_cpu_mask(void (*func)(void *), void *info, int wait, cpumask_t mask)
+static void
+on_each_cpu_mask(void (*func)(void *), void *info, int wait,
+                const struct cpumask *mask)
 {
-        int ret = 0;
-
         preempt_disable();
 
-        ret = smp_call_function_mask(mask, func, info, wait);
-        if (cpu_isset(smp_processor_id(), mask))
+        smp_call_function_many(mask, func, info, wait);
+        if (cpumask_test_cpu(smp_processor_id(), mask))
                 func(info);
 
         preempt_enable();
-
-        return ret;
 }
 
 /**********************************************************************/
@@ -602,20 +592,17 @@ void flush_tlb_all(void)
 
 void flush_tlb_mm(struct mm_struct *mm)
 {
-        cpumask_t mask = mm->cpu_vm_mask;
-
-        on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, mask);
+        on_each_cpu_mask(ipi_flush_tlb_mm, mm, 1, &mm->cpu_vm_mask);
 }
 
 void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 {
-        cpumask_t mask = vma->vm_mm->cpu_vm_mask;
         struct tlb_args ta;
 
         ta.ta_vma = vma;
         ta.ta_start = uaddr;
 
-        on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, mask);
+        on_each_cpu_mask(ipi_flush_tlb_page, &ta, 1, &vma->vm_mm->cpu_vm_mask);
 }
 
 void flush_tlb_kernel_page(unsigned long kaddr)
@@ -630,14 +617,13 @@ void flush_tlb_kernel_page(unsigned long kaddr)
 void flush_tlb_range(struct vm_area_struct *vma,
                      unsigned long start, unsigned long end)
 {
-        cpumask_t mask = vma->vm_mm->cpu_vm_mask;
         struct tlb_args ta;
 
         ta.ta_vma = vma;
         ta.ta_start = start;
         ta.ta_end = end;
 
-        on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, mask);
+        on_each_cpu_mask(ipi_flush_tlb_range, &ta, 1, &vma->vm_mm->cpu_vm_mask);
 }
 
 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
diff --git a/arch/arm/mach-davinci/include/mach/asp.h b/arch/arm/mach-davinci/include/mach/asp.h
new file mode 100644
index 000000000000..e0abc437d796
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/asp.h
@@ -0,0 +1,25 @@
+/*
+ * <mach/asp.h> - DaVinci Audio Serial Port support
+ */
+#ifndef __ASM_ARCH_DAVINCI_ASP_H
+#define __ASM_ARCH_DAVINCI_ASP_H
+
+#include <mach/irqs.h>
+
+/* Bases of register banks */
+#define DAVINCI_ASP0_BASE       0x01E02000
+#define DAVINCI_ASP1_BASE       0x01E04000
+
+/* EDMA channels */
+#define DAVINCI_DMA_ASP0_TX     2
+#define DAVINCI_DMA_ASP0_RX     3
+#define DAVINCI_DMA_ASP1_TX     8
+#define DAVINCI_DMA_ASP1_RX     9
+
+/* Interrupts */
+#define DAVINCI_ASP0_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP0_TX_INT     IRQ_MBXINT
+#define DAVINCI_ASP1_RX_INT     IRQ_MBRINT
+#define DAVINCI_ASP1_TX_INT     IRQ_MBXINT
+
+#endif /* __ASM_ARCH_DAVINCI_ASP_H */
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index e8ebeaea6c48..b2eede5531c8 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -21,15 +21,50 @@
 #include <asm/div64.h>
 #include <mach/hardware.h>
 
+
+/*
+ * The EP93xx has two external crystal oscillators.  To generate the
+ * required high-frequency clocks, the processor uses two phase-locked-
+ * loops (PLLs) to multiply the incoming external clock signal to much
+ * higher frequencies that are then divided down by programmable dividers
+ * to produce the needed clocks.  The PLLs operate independently of one
+ * another.
+ */
+#define EP93XX_EXT_CLK_RATE     14745600
+#define EP93XX_EXT_RTC_RATE     32768
+
+
 struct clk {
         unsigned long   rate;
         int             users;
+        int             sw_locked;
         u32             enable_reg;
         u32             enable_mask;
+
+        unsigned long   (*get_rate)(struct clk *clk);
 };
 
-static struct clk clk_uart = {
-        .rate           = 14745600,
+
+static unsigned long get_uart_rate(struct clk *clk);
+
+
+static struct clk clk_uart1 = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+        .get_rate       = get_uart_rate,
+};
+static struct clk clk_uart2 = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+        .get_rate       = get_uart_rate,
+};
+static struct clk clk_uart3 = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+        .get_rate       = get_uart_rate,
 };
 static struct clk clk_pll1;
 static struct clk clk_f;
@@ -95,9 +130,9 @@ static struct clk clk_m2m1 = {
         { .dev_id = dev, .con_id = con, .clk = ck }
 
 static struct clk_lookup clocks[] = {
-        INIT_CK("apb:uart1", NULL, &clk_uart),
-        INIT_CK("apb:uart2", NULL, &clk_uart),
-        INIT_CK("apb:uart3", NULL, &clk_uart),
+        INIT_CK("apb:uart1", NULL, &clk_uart1),
+        INIT_CK("apb:uart2", NULL, &clk_uart2),
+        INIT_CK("apb:uart3", NULL, &clk_uart3),
         INIT_CK(NULL, "pll1", &clk_pll1),
         INIT_CK(NULL, "fclk", &clk_f),
         INIT_CK(NULL, "hclk", &clk_h),
@@ -125,6 +160,8 @@ int clk_enable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                if (clk->sw_locked)
+                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
                 __raw_writel(value | clk->enable_mask, clk->enable_reg);
         }
 
@@ -138,13 +175,29 @@ void clk_disable(struct clk *clk)
                 u32 value;
 
                 value = __raw_readl(clk->enable_reg);
+                if (clk->sw_locked)
+                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
                 __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
         }
 }
 EXPORT_SYMBOL(clk_disable);
 
+static unsigned long get_uart_rate(struct clk *clk)
+{
+        u32 value;
+
+        value = __raw_readl(EP93XX_SYSCON_CLOCK_CONTROL);
+        if (value & EP93XX_SYSCON_CLOCK_UARTBAUD)
+                return EP93XX_EXT_CLK_RATE;
+        else
+                return EP93XX_EXT_CLK_RATE / 2;
+}
+
 unsigned long clk_get_rate(struct clk *clk)
 {
+        if (clk->get_rate)
+                return clk->get_rate(clk);
+
         return clk->rate;
 }
 EXPORT_SYMBOL(clk_get_rate);
@@ -162,7 +215,7 @@ static unsigned long calc_pll_rate(u32 config_word)
         unsigned long long rate;
         int i;
 
-        rate = 14745600;
+        rate = EP93XX_EXT_CLK_RATE;
         rate *= ((config_word >> 11) & 0x1f) + 1;               /* X1FBD */
         rate *= ((config_word >> 5) & 0x3f) + 1;                /* X2FBD */
         do_div(rate, (config_word & 0x1f) + 1);                 /* X2IPD */
@@ -195,7 +248,7 @@ static int __init ep93xx_clock_init(void)
 
         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET1);
         if (!(value & 0x00800000)) {                    /* PLL1 bypassed?  */
-                clk_pll1.rate = 14745600;
+                clk_pll1.rate = EP93XX_EXT_CLK_RATE;
         } else {
                 clk_pll1.rate = calc_pll_rate(value);
         }
@@ -206,7 +259,7 @@ static int __init ep93xx_clock_init(void)
 
         value = __raw_readl(EP93XX_SYSCON_CLOCK_SET2);
         if (!(value & 0x00080000)) {                    /* PLL2 bypassed?  */
-                clk_pll2.rate = 14745600;
+                clk_pll2.rate = EP93XX_EXT_CLK_RATE;
         } else if (value & 0x00040000) {                /* PLL2 enabled?  */
                 clk_pll2.rate = calc_pll_rate(value);
         } else {
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index f66be12b856e..1732de7629a5 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -159,7 +159,10 @@
 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
 #define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
 #define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       0x00800000
+#define EP93XX_SYSCON_DEVICE_CONFIG_U3EN                (1<<24)
+#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       (1<<23)
+#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN                (1<<20)
+#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN                (1<<18)
 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
 
 #define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c
index 6f8872913073..a0f60e55da6a 100644
--- a/arch/arm/mach-integrator/core.c
+++ b/arch/arm/mach-integrator/core.c
@@ -121,7 +121,7 @@ static struct clk uartclk = {
         .rate   = 14745600,
 };
 
-static struct clk_lookup lookups[] __initdata = {
+static struct clk_lookup lookups[] = {
         {       /* UART0 */
                 .dev_id         = "mb:16",
                 .clk            = &uartclk,
diff --git a/arch/arm/mach-ixp4xx/ixp4xx_npe.c b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
index 252310234903..7bb8e778e4b6 100644
--- a/arch/arm/mach-ixp4xx/ixp4xx_npe.c
+++ b/arch/arm/mach-ixp4xx/ixp4xx_npe.c
@@ -714,7 +714,7 @@ static int __init npe_init_module(void)
         }
 
         if (!found)
-                return -ENOSYS;
+                return -ENODEV;
         return 0;
 }
 
diff --git a/arch/arm/mach-l7200/include/mach/sys-clock.h b/arch/arm/mach-l7200/include/mach/sys-clock.h
index 2d7722be60ea..e9729a35751d 100644
--- a/arch/arm/mach-l7200/include/mach/sys-clock.h
+++ b/arch/arm/mach-l7200/include/mach/sys-clock.h
@@ -18,7 +18,7 @@
 
 /* IO_START and IO_BASE are defined in hardware.h */
 
-#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF)  /* Physical address */
+#define SYS_CLOCK_START (IO_START + SYS_CLOCK_OFF)  /* Physical address */
 #define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
 
 /* Define the interface to the SYS_CLOCK */
diff --git a/arch/arm/mach-omap2/clock24xx.c b/arch/arm/mach-omap2/clock24xx.c
index efc59c49341b..e4cef333e291 100644
--- a/arch/arm/mach-omap2/clock24xx.c
+++ b/arch/arm/mach-omap2/clock24xx.c
@@ -103,10 +103,10 @@ static struct omap_clk omap24xx_clks[] = {
         CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
-        CLK(NULL,       "dss_ick",      &dss_ick,       CK_243X | CK_242X),
-        CLK(NULL,       "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X | CK_242X),
+        CLK("omapfb",   "ick",          &dss_ick,       CK_243X | CK_242X),
+        CLK("omapfb",   "dss1_fck",     &dss1_fck,      CK_243X | CK_242X),
+        CLK("omapfb",   "dss2_fck",     &dss2_fck,      CK_243X | CK_242X),
+        CLK("omapfb",   "tv_fck",       &dss_54m_fck,   CK_243X | CK_242X),
         /* L3 domain clocks */
         CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X | CK_242X),
         CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X | CK_242X),
@@ -206,7 +206,7 @@ static struct omap_clk omap24xx_clks[] = {
         CLK(NULL,       "aes_ick",      &aes_ick,       CK_243X | CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X | CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X | CK_242X),
-        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
+        CLK("musb_hdrc",        "ick",  &usbhs_ick,     CK_243X),
         CLK("mmci-omap-hs.0", "ick",    &mmchs1_ick,    CK_243X),
         CLK("mmci-omap-hs.0", "fck",    &mmchs1_fck,    CK_243X),
         CLK("mmci-omap-hs.1", "ick",    &mmchs2_ick,    CK_243X),
diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c
index 0a14dca31e30..ba05aa42bd8e 100644
--- a/arch/arm/mach-omap2/clock34xx.c
+++ b/arch/arm/mach-omap2/clock34xx.c
@@ -157,7 +157,7 @@ static struct omap_clk omap34xx_clks[] = {
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck,   CK_343X),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck,   CK_343X),
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_343X),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick,  CK_343X),
+        CLK("musb_hdrc",        "ick",  &hsotgusb_ick,  CK_343X),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_343X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_343X),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_343X),
@@ -197,11 +197,11 @@ static struct omap_clk omap34xx_clks[] = {
         CLK("omap_rng", "ick",          &rng_ick,       CK_343X),
         CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_343X),
         CLK(NULL,       "des1_ick",     &des1_ick,      CK_343X),
-        CLK(NULL,       "dss1_alwon_fck", &dss1_alwon_fck, CK_343X),
-        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_343X),
-        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_343X),
-        CLK(NULL,       "dss2_alwon_fck", &dss2_alwon_fck, CK_343X),
-        CLK(NULL,       "dss_ick",      &dss_ick,       CK_343X),
+        CLK("omapfb",   "dss1_fck",     &dss1_alwon_fck, CK_343X),
+        CLK("omapfb",   "tv_fck",       &dss_tv_fck,    CK_343X),
+        CLK("omapfb",   "video_fck",    &dss_96m_fck,   CK_343X),
+        CLK("omapfb",   "dss2_fck",     &dss2_alwon_fck, CK_343X),
+        CLK("omapfb",   "ick",          &dss_ick,       CK_343X),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_343X),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_343X),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_343X),
diff --git a/arch/arm/mach-omap2/clock34xx.h b/arch/arm/mach-omap2/clock34xx.h
index 6763b8f73028..017a30e9aa1d 100644
--- a/arch/arm/mach-omap2/clock34xx.h
+++ b/arch/arm/mach-omap2/clock34xx.h
@@ -2182,7 +2182,7 @@ static struct clk wkup_32k_fck = {
 
 static struct clk gpio1_dbck = {
         .name           = "gpio1_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &wkup_32k_fck,
         .enable_reg     = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO1_SHIFT,
@@ -2427,7 +2427,7 @@ static struct clk per_32k_alwon_fck = {
 
 static struct clk gpio6_dbck = {
         .name           = "gpio6_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO6_SHIFT,
@@ -2437,7 +2437,7 @@ static struct clk gpio6_dbck = {
 
 static struct clk gpio5_dbck = {
         .name           = "gpio5_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO5_SHIFT,
@@ -2447,7 +2447,7 @@ static struct clk gpio5_dbck = {
 
 static struct clk gpio4_dbck = {
         .name           = "gpio4_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO4_SHIFT,
@@ -2457,7 +2457,7 @@ static struct clk gpio4_dbck = {
 
 static struct clk gpio3_dbck = {
         .name           = "gpio3_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO3_SHIFT,
@@ -2467,7 +2467,7 @@ static struct clk gpio3_dbck = {
 
 static struct clk gpio2_dbck = {
         .name           = "gpio2_dbck",
-        .ops            = &clkops_omap2_dflt_wait,
+        .ops            = &clkops_omap2_dflt,
         .parent         = &per_32k_alwon_fck,
         .enable_reg     = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN),
         .enable_bit     = OMAP3430_EN_GPIO2_SHIFT,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 496983ade97e..894cc355818a 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -354,10 +354,12 @@ static void omap_init_mcspi(void)
         platform_device_register(&omap2_mcspi1);
         platform_device_register(&omap2_mcspi2);
 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
-        platform_device_register(&omap2_mcspi3);
+        if (cpu_is_omap2430() || cpu_is_omap343x())
+                platform_device_register(&omap2_mcspi3);
 #endif
 #ifdef CONFIG_ARCH_OMAP3
-        platform_device_register(&omap2_mcspi4);
+        if (cpu_is_omap343x())
+                platform_device_register(&omap2_mcspi4);
 #endif
 }
 
diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h
index c6a7940f4287..9fd03a2ec95c 100644
--- a/arch/arm/mach-omap2/prm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-34xx.h
@@ -409,7 +409,7 @@
 /* PM_PREPWSTST_CAM specific bits */
 
 /* PM_PWSTCTRL_USBHOST specific bits */
-#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                (1 << 4)
+#define OMAP3430ES2_SAVEANDRESTORE_SHIFT                4
 
 /* RM_RSTST_PER specific bits */
 
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c
index 8df55f40f4c0..8622c24cd270 100644
--- a/arch/arm/mach-omap2/usb-tusb6010.c
+++ b/arch/arm/mach-omap2/usb-tusb6010.c
@@ -187,7 +187,7 @@ int tusb6010_platform_retime(unsigned is_refclk)
         unsigned        sysclk_ps;
         int             status;
 
-        if (!refclk_psec || sysclk_ps == 0)
+        if (!refclk_psec || fclk_ps == 0)
                 return -ENODEV;
 
         sysclk_ps = is_refclk ? refclk_psec : TUSB6010_OSCCLK_60;
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 0e65344e9f53..dd031cc41847 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -46,6 +46,7 @@
 #include <mach/audio.h>
 #include <mach/pxafb.h>
 #include <mach/i2c.h>
+#include <mach/regs-uart.h>
 #include <mach/viper.h>
 
 #include <asm/setup.h>
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 942e1a7eb9b2..076acbc50706 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -750,14 +750,6 @@ void __init realview_timer_init(unsigned int timer_irq)
 {
         u32 val;
 
-#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
-        /*
-         * The dummy clock device has to be registered before the main device
-         * so that the latter will broadcast the clock events
-         */
-        local_timer_setup();
-#endif
-
         /* 
          * set clock frequency: 
          *      REALVIEW_REFCLK is 32KHz
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
index 515819efd046..dd53892d44a7 100644
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ b/arch/arm/mach-realview/include/mach/smp.h
@@ -15,16 +15,9 @@
 /*
  * We use IRQ1 as the IPI
  */
-static inline void smp_cross_call(cpumask_t callmap)
-{
-        gic_raise_softirq(callmap, 1);
-}
-
-/*
- * Do nothing on MPcore.
- */
-static inline void smp_cross_call_done(cpumask_t callmap)
+static inline void smp_cross_call(const struct cpumask *mask)
 {
+        gic_raise_softirq(mask, 1);
 }
 
 #endif
diff --git a/arch/arm/mach-realview/localtimer.c b/arch/arm/mach-realview/localtimer.c
index d0d39adf6407..1c01d13460f0 100644
--- a/arch/arm/mach-realview/localtimer.c
+++ b/arch/arm/mach-realview/localtimer.c
@@ -189,8 +189,10 @@ void __cpuinit local_timer_setup(void)
         struct clock_event_device *clk = &per_cpu(local_clockevent, cpu);
 
         clk->name               = "dummy_timer";
-        clk->features           = CLOCK_EVT_FEAT_DUMMY;
-        clk->rating             = 200;
+        clk->features           = CLOCK_EVT_FEAT_ONESHOT |
+                                  CLOCK_EVT_FEAT_PERIODIC |
+                                  CLOCK_EVT_FEAT_DUMMY;
+        clk->rating             = 400;
         clk->mult               = 1;
         clk->set_mode           = dummy_timer_set_mode;
         clk->broadcast          = smp_timer_broadcast;
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index ea3c75595fa9..30a9c68591f6 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -78,13 +78,6 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
         trace_hardirqs_off();
 
         /*
-         * the primary core may have used a "cross call" soft interrupt
-         * to get this processor out of WFI in the BootMonitor - make
-         * sure that we are no longer being sent this soft interrupt
-         */
-        smp_cross_call_done(cpumask_of_cpu(cpu));
-
-        /*
          * if any interrupts are already enabled for the primary
          * core (e.g. timer irq), then they will not have been enabled
          * for us: do so
@@ -136,7 +129,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          * Use smp_cross_call() for this, since there's little
          * point duplicating the code here
          */
-        smp_cross_call(cpumask_of_cpu(cpu));
+        smp_cross_call(cpumask_of(cpu));
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
@@ -224,11 +217,9 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
         if (max_cpus > ncores)
                 max_cpus = ncores;
 
-#ifdef CONFIG_LOCAL_TIMERS
+#if defined(CONFIG_LOCAL_TIMERS) || defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
         /*
-         * Enable the local timer for primary CPU. If the device is
-         * dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
-         * realview_timer_init
+         * Enable the local timer or broadcast device for the boot CPU.
          */
         local_timer_setup();
 #endif
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 4389c160f7d0..8637dea5e150 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -588,8 +588,6 @@ static void __init bast_map_io(void)
 
         s3c_device_nand.dev.platform_data = &bast_nand_info;
 
-        s3c_i2c0_set_platdata(&bast_i2c_info);
-
         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
         s3c24xx_init_clocks(0);
         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
@@ -602,6 +600,7 @@ static void __init bast_init(void)
         sysdev_class_register(&bast_pm_sysclass);
         sysdev_register(&bast_pm_sysdev);
 
+        s3c_i2c0_set_platdata(&bast_i2c_info);
         s3c24xx_fb_set_platdata(&bast_fb_info);
         platform_add_devices(bast_devices, ARRAY_SIZE(bast_devices));
 
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 1f929c391af7..b3bebcc5623b 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -413,7 +413,7 @@ static struct clk ref24_clk = {
         .rate   = 24000000,
 };
 
-static struct clk_lookup lookups[] __initdata = {
+static struct clk_lookup lookups[] = {
         {       /* UART0 */
                 .dev_id         = "dev:f1",
                 .clk            = &ref24_clk,
diff --git a/arch/arm/nwfpe/fpa11.h b/arch/arm/nwfpe/fpa11.h
index 386cbd13eaf4..d3a6f9298e9e 100644
--- a/arch/arm/nwfpe/fpa11.h
+++ b/arch/arm/nwfpe/fpa11.h
@@ -114,4 +114,8 @@ extern unsigned int SingleCPDO(struct roundingData *roundData,
 extern unsigned int DoubleCPDO(struct roundingData *roundData,
                                const unsigned int opcode, FPREG * rFd);
 
+/* extneded_cpdo.c */
+extern unsigned int ExtendedCPDO(struct roundingData *roundData,
+                                 const unsigned int opcode, FPREG * rFd);
+
 #endif
diff --git a/arch/arm/nwfpe/fpa11_cprt.c b/arch/arm/nwfpe/fpa11_cprt.c
index 9843dc533047..31c4eeec18b0 100644
--- a/arch/arm/nwfpe/fpa11_cprt.c
+++ b/arch/arm/nwfpe/fpa11_cprt.c
@@ -27,10 +27,6 @@
 #include "fpmodule.inl"
 #include "softfloat.h"
 
-#ifdef CONFIG_FPE_NWFPE_XP
-extern flag floatx80_is_nan(floatx80);
-#endif
-
 unsigned int PerformFLT(const unsigned int opcode);
 unsigned int PerformFIX(const unsigned int opcode);
 
diff --git a/arch/arm/nwfpe/softfloat.h b/arch/arm/nwfpe/softfloat.h
index 260fe29d73f5..13e479c5da57 100644
--- a/arch/arm/nwfpe/softfloat.h
+++ b/arch/arm/nwfpe/softfloat.h
@@ -226,6 +226,8 @@ char floatx80_le_quiet( floatx80, floatx80 );
 char floatx80_lt_quiet( floatx80, floatx80 );
 char floatx80_is_signaling_nan( floatx80 );
 
+extern flag floatx80_is_nan(floatx80);
+
 #endif
 
 static inline flag extractFloat32Sign(float32 a)
diff --git a/arch/arm/plat-omap/fb.c b/arch/arm/plat-omap/fb.c
index ce6b4baeedec..3746222bed10 100644
--- a/arch/arm/plat-omap/fb.c
+++ b/arch/arm/plat-omap/fb.c
@@ -206,9 +206,10 @@ void __init omapfb_reserve_sdram(void)
                         config_invalid = 1;
                         return;
                 }
-                if (rg.paddr)
+                if (rg.paddr) {
                         reserve_bootmem(rg.paddr, rg.size, BOOTMEM_DEFAULT);
-                reserved += rg.size;
+                        reserved += rg.size;
+                }
                 omapfb_config.mem_desc.region[i] = rg;
                 configured_regions++;
         }
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 17d7afe42b83..ee0b21f5b094 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -307,7 +307,7 @@ static inline int gpio_valid(int gpio)
                 return 0;
         if (cpu_is_omap24xx() && gpio < 128)
                 return 0;
-        if (cpu_is_omap34xx() && gpio < 160)
+        if (cpu_is_omap34xx() && gpio < 192)
                 return 0;
         return -1;
 }
diff --git a/arch/arm/plat-s3c/clock.c b/arch/arm/plat-s3c/clock.c
index b6be76e2fe51..4d01ef1a25dd 100644
--- a/arch/arm/plat-s3c/clock.c
+++ b/arch/arm/plat-s3c/clock.c
@@ -306,8 +306,6 @@ struct clk s3c24xx_uclk = {
 
 int s3c24xx_register_clock(struct clk *clk)
 {
-        clk->owner = THIS_MODULE;
-
         if (clk->enable == NULL)
                 clk->enable = clk_null_enable;
 
diff --git a/arch/arm/plat-s3c/include/plat/nand.h b/arch/arm/plat-s3c/include/plat/nand.h
index f4dcd14af059..18f958801e64 100644
--- a/arch/arm/plat-s3c/include/plat/nand.h
+++ b/arch/arm/plat-s3c/include/plat/nand.h
@@ -10,19 +10,26 @@
  * published by the Free Software Foundation.
 */
 
-/* struct s3c2410_nand_set
+/**
+ * struct s3c2410_nand_set - define a set of one or more nand chips
+ * @disable_ecc:        Entirely disable ECC - Dangerous
+ * @flash_bbt:          Openmoko u-boot can create a Bad Block Table
+ *                      Setting this flag will allow the kernel to
+ *                      look for it at boot time and also skip the NAND
+ *                      scan.
+ * @nr_chips:           Number of chips in this set
+ * @nr_partitions:      Number of partitions pointed to by @partitions
+ * @name:               Name of set (optional)
+ * @nr_map:             Map for low-layer logical to physical chip numbers (option)
+ * @partitions:         The mtd partition list
  *
- * define an set of one or more nand chips registered with an unique mtd
- *
- * nr_chips      = number of chips in this set
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * name          = name of set (optional)
- * nr_map        = map for low-layer logical to physical chip numbers (option)
- * partitions    = mtd partition list
-*/
-
+ * define a set of one or more nand chips registered with an unique mtd. Also
+ * allows to pass flag to the underlying NAND layer. 'disable_ecc' will trigger
+ * a warning at boot time.
+ */
 struct s3c2410_nand_set {
-        unsigned int            disable_ecc : 1;
+        unsigned int            disable_ecc:1;
+        unsigned int            flash_bbt:1;
 
         int                     nr_chips;
         int                     nr_partitions;
@@ -39,7 +46,7 @@ struct s3c2410_platform_nand {
         int     twrph0; /* active time for nWE/nOE */
         int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
 
-        unsigned int    ignore_unset_ecc : 1;
+        unsigned int    ignore_unset_ecc:1;
 
         int                     nr_sets;
         struct s3c2410_nand_set *sets;
diff --git a/arch/arm/plat-s3c24xx/dma.c b/arch/arm/plat-s3c24xx/dma.c
index aee2aeb46c60..07326f632361 100644
--- a/arch/arm/plat-s3c24xx/dma.c
+++ b/arch/arm/plat-s3c24xx/dma.c
@@ -1235,7 +1235,7 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d
 
 EXPORT_SYMBOL(s3c2410_dma_getposition);
 
-static struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
+static inline struct s3c2410_dma_chan *to_dma_chan(struct sys_device *dev)
 {
         return container_of(dev, struct s3c2410_dma_chan, dev);
 }
diff --git a/arch/arm/plat-s3c64xx/gpiolib.c b/arch/arm/plat-s3c64xx/gpiolib.c
index ee9188add8fb..78ee52cffc9e 100644
--- a/arch/arm/plat-s3c64xx/gpiolib.c
+++ b/arch/arm/plat-s3c64xx/gpiolib.c
@@ -57,7 +57,7 @@
 #if 1
 #define gpio_dbg(x...) do { } while(0)
 #else
-#define gpio_dbg(x...) printk(KERN_DEBUG ## x)
+#define gpio_dbg(x...) printk(KERN_DEBUG x)
 #endif
 
 /* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
diff --git a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
index 81549516572f..2ba1767512d7 100644
--- a/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
+++ b/arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
@@ -61,14 +61,14 @@
 #define S3C64XX_GPH7_ADDR_CF1           (0x06 << 28)
 #define S3C64XX_GPH7_EINT_G6_7          (0x07 << 28)
 
-#define S3C64XX_GPH8_MMC1_DATA6         (0x02 << 32)
-#define S3C64XX_GPH8_MMC2_DATA2         (0x03 << 32)
-#define S3C64XX_GPH8_I2S_V40_LRCLK      (0x05 << 32)
-#define S3C64XX_GPH8_ADDR_CF2           (0x06 << 32)
-#define S3C64XX_GPH8_EINT_G6_8          (0x07 << 32)
-
-#define S3C64XX_GPH9_MMC1_DATA7         (0x02 << 36)
-#define S3C64XX_GPH9_MMC2_DATA3         (0x03 << 36)
-#define S3C64XX_GPH9_I2S_V40_DI         (0x05 << 36)
-#define S3C64XX_GPH9_EINT_G6_9          (0x07 << 36)
+#define S3C64XX_GPH8_MMC1_DATA6         (0x02 <<  0)
+#define S3C64XX_GPH8_MMC2_DATA2         (0x03 <<  0)
+#define S3C64XX_GPH8_I2S_V40_LRCLK      (0x05 <<  0)
+#define S3C64XX_GPH8_ADDR_CF2           (0x06 <<  0)
+#define S3C64XX_GPH8_EINT_G6_8          (0x07 <<  0)
 
+#define S3C64XX_GPH9_OUTPUT             (0x01 <<  4)
+#define S3C64XX_GPH9_MMC1_DATA7         (0x02 <<  4)
+#define S3C64XX_GPH9_MMC2_DATA3         (0x03 <<  4)
+#define S3C64XX_GPH9_I2S_V40_DI         (0x05 <<  4)
+#define S3C64XX_GPH9_EINT_G6_9          (0x07 <<  4)