4 files changed, 10 insertions, 8 deletions

diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 98356f810007..02e188d98e7d 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -95,7 +95,10 @@ static void __init mainstone_init_irq(void)
         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
                 set_irq_chip(irq, &mainstone_irq_chip);
                 set_irq_handler(irq, do_level_IRQ);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
+                else
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
         set_irq_flags(MAINSTONE_IRQ(8), 0);
         set_irq_flags(MAINSTONE_IRQ(12), 0);
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 832fb86a03b4..73de2eaca22a 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -59,8 +59,7 @@ ENTRY(s3c2410_cpu_suspend)
         mrc     p15, 0, r5, c13, c0, 0  @ PID
         mrc     p15, 0, r6, c3, c0, 0   @ Domain ID
         mrc     p15, 0, r7, c2, c0, 0   @ translation table base address
-        mrc     p15, 0, r8, c2, c0, 0   @ auxiliary control register
-        mrc     p15, 0, r9, c1, c0, 0   @ control register
+        mrc     p15, 0, r8, c1, c0, 0   @ control register
 
         stmia   r0, { r4 - r13 }
 
@@ -165,7 +164,6 @@ ENTRY(s3c2410_cpu_resume)
         mcr     p15, 0, r5, c13, c0, 0          @ PID
         mcr     p15, 0, r6, c3, c0, 0           @ Domain ID
         mcr     p15, 0, r7, c2, c0, 0           @ translation table base
-        mcr     p15, 0, r8, c1, c1, 0           @ auxilliary control
 
 #ifdef CONFIG_DEBUG_RESUME
         mov     r3, #'R'
@@ -173,7 +171,7 @@ ENTRY(s3c2410_cpu_resume)
 #endif
 
         ldr     r2, =resume_with_mmu
-        mcr     p15, 0, r9, c1, c0, 0           @ turn on MMU, etc
+        mcr     p15, 0, r8, c1, c0, 0           @ turn on MMU, etc
         nop                                     @ second-to-last before mmu
         mov     pc, r2                          @ go back to virtual address
 
diff --git a/arch/arm/mm/mm-armv.c b/arch/arm/mm/mm-armv.c
index f14b2d0f3690..95273de4f772 100644
--- a/arch/arm/mm/mm-armv.c
+++ b/arch/arm/mm/mm-armv.c
@@ -376,7 +376,7 @@ void __init build_mem_type_table(void)
                 ecc_mask = 0;
         }
 
-        if (cpu_arch <= CPU_ARCH_ARMv5TEJ) {
+        if (cpu_arch <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) {
                 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
                         if (mem_types[i].prot_l1)
                                 mem_types[i].prot_l1 |= PMD_BIT4;
@@ -631,7 +631,7 @@ void setup_mm_for_reboot(char mode)
                 pgd = init_mm.pgd;
 
         base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT;
-        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ)
+        if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale())
                 base_pmdval |= PMD_BIT4;
 
         for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) {
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 80873b36c3f7..8d32e21fe151 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -427,12 +427,13 @@ __xsc3_setup:
 #endif
         mcr     p15, 0, r0, c1, c0, 1           @ set auxiliary control reg
         mrc     p15, 0, r0, c1, c0, 0           @ get control register
-        bic     r0, r0, #0x0200                 @ .... ..R. .... ....
         bic     r0, r0, #0x0002                 @ .... .... .... ..A.
         orr     r0, r0, #0x0005                 @ .... .... .... .C.M
 #if BTB_ENABLE
+        bic     r0, r0, #0x0200                 @ .... ..R. .... ....
         orr     r0, r0, #0x3900                 @ ..VI Z..S .... ....
 #else
+        bic     r0, r0, #0x0a00                 @ .... Z.R. .... ....
         orr     r0, r0, #0x3100                 @ ..VI ...S .... ....
 #endif
 #if L2_CACHE_ENABLE